2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats
[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats
[] = {
62 DRM_FORMAT_XRGB2101010
,
63 DRM_FORMAT_XBGR2101010
,
66 static const uint32_t skl_primary_formats
[] = {
73 DRM_FORMAT_XRGB2101010
,
74 DRM_FORMAT_XBGR2101010
,
82 static const uint32_t intel_cursor_formats
[] = {
86 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
88 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
89 struct intel_crtc_state
*pipe_config
);
90 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
91 struct intel_crtc_state
*pipe_config
);
93 static int intel_framebuffer_init(struct drm_device
*dev
,
94 struct intel_framebuffer
*ifb
,
95 struct drm_mode_fb_cmd2
*mode_cmd
,
96 struct drm_i915_gem_object
*obj
);
97 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
98 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
100 struct intel_link_m_n
*m_n
,
101 struct intel_link_m_n
*m2_n2
);
102 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
103 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
104 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
105 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
106 const struct intel_crtc_state
*pipe_config
);
107 static void chv_prepare_pll(struct intel_crtc
*crtc
,
108 const struct intel_crtc_state
*pipe_config
);
109 static void intel_begin_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
110 static void intel_finish_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
111 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
112 struct intel_crtc_state
*crtc_state
);
113 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
115 static void skylake_pfit_enable(struct intel_crtc
*crtc
);
116 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
);
117 static void ironlake_pfit_enable(struct intel_crtc
*crtc
);
118 static void intel_modeset_setup_hw_state(struct drm_device
*dev
);
126 int p2_slow
, p2_fast
;
129 typedef struct intel_limit intel_limit_t
;
131 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
136 intel_pch_rawclk(struct drm_device
*dev
)
138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
140 WARN_ON(!HAS_PCH_SPLIT(dev
));
142 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
145 /* hrawclock is 1/4 the FSB frequency */
146 int intel_hrawclk(struct drm_device
*dev
)
148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
152 if (IS_VALLEYVIEW(dev
))
155 clkcfg
= I915_READ(CLKCFG
);
156 switch (clkcfg
& CLKCFG_FSB_MASK
) {
165 case CLKCFG_FSB_1067
:
167 case CLKCFG_FSB_1333
:
169 /* these two are just a guess; one of them might be right */
170 case CLKCFG_FSB_1600
:
171 case CLKCFG_FSB_1600_ALT
:
178 static inline u32
/* units of 100MHz */
179 intel_fdi_link_freq(struct drm_device
*dev
)
182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
183 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
188 static const intel_limit_t intel_limits_i8xx_dac
= {
189 .dot
= { .min
= 25000, .max
= 350000 },
190 .vco
= { .min
= 908000, .max
= 1512000 },
191 .n
= { .min
= 2, .max
= 16 },
192 .m
= { .min
= 96, .max
= 140 },
193 .m1
= { .min
= 18, .max
= 26 },
194 .m2
= { .min
= 6, .max
= 16 },
195 .p
= { .min
= 4, .max
= 128 },
196 .p1
= { .min
= 2, .max
= 33 },
197 .p2
= { .dot_limit
= 165000,
198 .p2_slow
= 4, .p2_fast
= 2 },
201 static const intel_limit_t intel_limits_i8xx_dvo
= {
202 .dot
= { .min
= 25000, .max
= 350000 },
203 .vco
= { .min
= 908000, .max
= 1512000 },
204 .n
= { .min
= 2, .max
= 16 },
205 .m
= { .min
= 96, .max
= 140 },
206 .m1
= { .min
= 18, .max
= 26 },
207 .m2
= { .min
= 6, .max
= 16 },
208 .p
= { .min
= 4, .max
= 128 },
209 .p1
= { .min
= 2, .max
= 33 },
210 .p2
= { .dot_limit
= 165000,
211 .p2_slow
= 4, .p2_fast
= 4 },
214 static const intel_limit_t intel_limits_i8xx_lvds
= {
215 .dot
= { .min
= 25000, .max
= 350000 },
216 .vco
= { .min
= 908000, .max
= 1512000 },
217 .n
= { .min
= 2, .max
= 16 },
218 .m
= { .min
= 96, .max
= 140 },
219 .m1
= { .min
= 18, .max
= 26 },
220 .m2
= { .min
= 6, .max
= 16 },
221 .p
= { .min
= 4, .max
= 128 },
222 .p1
= { .min
= 1, .max
= 6 },
223 .p2
= { .dot_limit
= 165000,
224 .p2_slow
= 14, .p2_fast
= 7 },
227 static const intel_limit_t intel_limits_i9xx_sdvo
= {
228 .dot
= { .min
= 20000, .max
= 400000 },
229 .vco
= { .min
= 1400000, .max
= 2800000 },
230 .n
= { .min
= 1, .max
= 6 },
231 .m
= { .min
= 70, .max
= 120 },
232 .m1
= { .min
= 8, .max
= 18 },
233 .m2
= { .min
= 3, .max
= 7 },
234 .p
= { .min
= 5, .max
= 80 },
235 .p1
= { .min
= 1, .max
= 8 },
236 .p2
= { .dot_limit
= 200000,
237 .p2_slow
= 10, .p2_fast
= 5 },
240 static const intel_limit_t intel_limits_i9xx_lvds
= {
241 .dot
= { .min
= 20000, .max
= 400000 },
242 .vco
= { .min
= 1400000, .max
= 2800000 },
243 .n
= { .min
= 1, .max
= 6 },
244 .m
= { .min
= 70, .max
= 120 },
245 .m1
= { .min
= 8, .max
= 18 },
246 .m2
= { .min
= 3, .max
= 7 },
247 .p
= { .min
= 7, .max
= 98 },
248 .p1
= { .min
= 1, .max
= 8 },
249 .p2
= { .dot_limit
= 112000,
250 .p2_slow
= 14, .p2_fast
= 7 },
254 static const intel_limit_t intel_limits_g4x_sdvo
= {
255 .dot
= { .min
= 25000, .max
= 270000 },
256 .vco
= { .min
= 1750000, .max
= 3500000},
257 .n
= { .min
= 1, .max
= 4 },
258 .m
= { .min
= 104, .max
= 138 },
259 .m1
= { .min
= 17, .max
= 23 },
260 .m2
= { .min
= 5, .max
= 11 },
261 .p
= { .min
= 10, .max
= 30 },
262 .p1
= { .min
= 1, .max
= 3},
263 .p2
= { .dot_limit
= 270000,
269 static const intel_limit_t intel_limits_g4x_hdmi
= {
270 .dot
= { .min
= 22000, .max
= 400000 },
271 .vco
= { .min
= 1750000, .max
= 3500000},
272 .n
= { .min
= 1, .max
= 4 },
273 .m
= { .min
= 104, .max
= 138 },
274 .m1
= { .min
= 16, .max
= 23 },
275 .m2
= { .min
= 5, .max
= 11 },
276 .p
= { .min
= 5, .max
= 80 },
277 .p1
= { .min
= 1, .max
= 8},
278 .p2
= { .dot_limit
= 165000,
279 .p2_slow
= 10, .p2_fast
= 5 },
282 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
283 .dot
= { .min
= 20000, .max
= 115000 },
284 .vco
= { .min
= 1750000, .max
= 3500000 },
285 .n
= { .min
= 1, .max
= 3 },
286 .m
= { .min
= 104, .max
= 138 },
287 .m1
= { .min
= 17, .max
= 23 },
288 .m2
= { .min
= 5, .max
= 11 },
289 .p
= { .min
= 28, .max
= 112 },
290 .p1
= { .min
= 2, .max
= 8 },
291 .p2
= { .dot_limit
= 0,
292 .p2_slow
= 14, .p2_fast
= 14
296 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
297 .dot
= { .min
= 80000, .max
= 224000 },
298 .vco
= { .min
= 1750000, .max
= 3500000 },
299 .n
= { .min
= 1, .max
= 3 },
300 .m
= { .min
= 104, .max
= 138 },
301 .m1
= { .min
= 17, .max
= 23 },
302 .m2
= { .min
= 5, .max
= 11 },
303 .p
= { .min
= 14, .max
= 42 },
304 .p1
= { .min
= 2, .max
= 6 },
305 .p2
= { .dot_limit
= 0,
306 .p2_slow
= 7, .p2_fast
= 7
310 static const intel_limit_t intel_limits_pineview_sdvo
= {
311 .dot
= { .min
= 20000, .max
= 400000},
312 .vco
= { .min
= 1700000, .max
= 3500000 },
313 /* Pineview's Ncounter is a ring counter */
314 .n
= { .min
= 3, .max
= 6 },
315 .m
= { .min
= 2, .max
= 256 },
316 /* Pineview only has one combined m divider, which we treat as m2. */
317 .m1
= { .min
= 0, .max
= 0 },
318 .m2
= { .min
= 0, .max
= 254 },
319 .p
= { .min
= 5, .max
= 80 },
320 .p1
= { .min
= 1, .max
= 8 },
321 .p2
= { .dot_limit
= 200000,
322 .p2_slow
= 10, .p2_fast
= 5 },
325 static const intel_limit_t intel_limits_pineview_lvds
= {
326 .dot
= { .min
= 20000, .max
= 400000 },
327 .vco
= { .min
= 1700000, .max
= 3500000 },
328 .n
= { .min
= 3, .max
= 6 },
329 .m
= { .min
= 2, .max
= 256 },
330 .m1
= { .min
= 0, .max
= 0 },
331 .m2
= { .min
= 0, .max
= 254 },
332 .p
= { .min
= 7, .max
= 112 },
333 .p1
= { .min
= 1, .max
= 8 },
334 .p2
= { .dot_limit
= 112000,
335 .p2_slow
= 14, .p2_fast
= 14 },
338 /* Ironlake / Sandybridge
340 * We calculate clock using (register_value + 2) for N/M1/M2, so here
341 * the range value for them is (actual_value - 2).
343 static const intel_limit_t intel_limits_ironlake_dac
= {
344 .dot
= { .min
= 25000, .max
= 350000 },
345 .vco
= { .min
= 1760000, .max
= 3510000 },
346 .n
= { .min
= 1, .max
= 5 },
347 .m
= { .min
= 79, .max
= 127 },
348 .m1
= { .min
= 12, .max
= 22 },
349 .m2
= { .min
= 5, .max
= 9 },
350 .p
= { .min
= 5, .max
= 80 },
351 .p1
= { .min
= 1, .max
= 8 },
352 .p2
= { .dot_limit
= 225000,
353 .p2_slow
= 10, .p2_fast
= 5 },
356 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
357 .dot
= { .min
= 25000, .max
= 350000 },
358 .vco
= { .min
= 1760000, .max
= 3510000 },
359 .n
= { .min
= 1, .max
= 3 },
360 .m
= { .min
= 79, .max
= 118 },
361 .m1
= { .min
= 12, .max
= 22 },
362 .m2
= { .min
= 5, .max
= 9 },
363 .p
= { .min
= 28, .max
= 112 },
364 .p1
= { .min
= 2, .max
= 8 },
365 .p2
= { .dot_limit
= 225000,
366 .p2_slow
= 14, .p2_fast
= 14 },
369 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
370 .dot
= { .min
= 25000, .max
= 350000 },
371 .vco
= { .min
= 1760000, .max
= 3510000 },
372 .n
= { .min
= 1, .max
= 3 },
373 .m
= { .min
= 79, .max
= 127 },
374 .m1
= { .min
= 12, .max
= 22 },
375 .m2
= { .min
= 5, .max
= 9 },
376 .p
= { .min
= 14, .max
= 56 },
377 .p1
= { .min
= 2, .max
= 8 },
378 .p2
= { .dot_limit
= 225000,
379 .p2_slow
= 7, .p2_fast
= 7 },
382 /* LVDS 100mhz refclk limits. */
383 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
384 .dot
= { .min
= 25000, .max
= 350000 },
385 .vco
= { .min
= 1760000, .max
= 3510000 },
386 .n
= { .min
= 1, .max
= 2 },
387 .m
= { .min
= 79, .max
= 126 },
388 .m1
= { .min
= 12, .max
= 22 },
389 .m2
= { .min
= 5, .max
= 9 },
390 .p
= { .min
= 28, .max
= 112 },
391 .p1
= { .min
= 2, .max
= 8 },
392 .p2
= { .dot_limit
= 225000,
393 .p2_slow
= 14, .p2_fast
= 14 },
396 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
397 .dot
= { .min
= 25000, .max
= 350000 },
398 .vco
= { .min
= 1760000, .max
= 3510000 },
399 .n
= { .min
= 1, .max
= 3 },
400 .m
= { .min
= 79, .max
= 126 },
401 .m1
= { .min
= 12, .max
= 22 },
402 .m2
= { .min
= 5, .max
= 9 },
403 .p
= { .min
= 14, .max
= 42 },
404 .p1
= { .min
= 2, .max
= 6 },
405 .p2
= { .dot_limit
= 225000,
406 .p2_slow
= 7, .p2_fast
= 7 },
409 static const intel_limit_t intel_limits_vlv
= {
411 * These are the data rate limits (measured in fast clocks)
412 * since those are the strictest limits we have. The fast
413 * clock and actual rate limits are more relaxed, so checking
414 * them would make no difference.
416 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
417 .vco
= { .min
= 4000000, .max
= 6000000 },
418 .n
= { .min
= 1, .max
= 7 },
419 .m1
= { .min
= 2, .max
= 3 },
420 .m2
= { .min
= 11, .max
= 156 },
421 .p1
= { .min
= 2, .max
= 3 },
422 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
425 static const intel_limit_t intel_limits_chv
= {
427 * These are the data rate limits (measured in fast clocks)
428 * since those are the strictest limits we have. The fast
429 * clock and actual rate limits are more relaxed, so checking
430 * them would make no difference.
432 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
433 .vco
= { .min
= 4800000, .max
= 6480000 },
434 .n
= { .min
= 1, .max
= 1 },
435 .m1
= { .min
= 2, .max
= 2 },
436 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
437 .p1
= { .min
= 2, .max
= 4 },
438 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
441 static const intel_limit_t intel_limits_bxt
= {
442 /* FIXME: find real dot limits */
443 .dot
= { .min
= 0, .max
= INT_MAX
},
444 .vco
= { .min
= 4800000, .max
= 6700000 },
445 .n
= { .min
= 1, .max
= 1 },
446 .m1
= { .min
= 2, .max
= 2 },
447 /* FIXME: find real m2 limits */
448 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
449 .p1
= { .min
= 2, .max
= 4 },
450 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
454 needs_modeset(struct drm_crtc_state
*state
)
456 return drm_atomic_crtc_needs_modeset(state
);
460 * Returns whether any output on the specified pipe is of the specified type
462 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
464 struct drm_device
*dev
= crtc
->base
.dev
;
465 struct intel_encoder
*encoder
;
467 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
468 if (encoder
->type
== type
)
475 * Returns whether any output on the specified pipe will have the specified
476 * type after a staged modeset is complete, i.e., the same as
477 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
480 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
483 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
484 struct drm_connector
*connector
;
485 struct drm_connector_state
*connector_state
;
486 struct intel_encoder
*encoder
;
487 int i
, num_connectors
= 0;
489 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
490 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
495 encoder
= to_intel_encoder(connector_state
->best_encoder
);
496 if (encoder
->type
== type
)
500 WARN_ON(num_connectors
== 0);
505 static const intel_limit_t
*
506 intel_ironlake_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
508 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
509 const intel_limit_t
*limit
;
511 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
512 if (intel_is_dual_link_lvds(dev
)) {
513 if (refclk
== 100000)
514 limit
= &intel_limits_ironlake_dual_lvds_100m
;
516 limit
= &intel_limits_ironlake_dual_lvds
;
518 if (refclk
== 100000)
519 limit
= &intel_limits_ironlake_single_lvds_100m
;
521 limit
= &intel_limits_ironlake_single_lvds
;
524 limit
= &intel_limits_ironlake_dac
;
529 static const intel_limit_t
*
530 intel_g4x_limit(struct intel_crtc_state
*crtc_state
)
532 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
533 const intel_limit_t
*limit
;
535 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
536 if (intel_is_dual_link_lvds(dev
))
537 limit
= &intel_limits_g4x_dual_channel_lvds
;
539 limit
= &intel_limits_g4x_single_channel_lvds
;
540 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
541 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
542 limit
= &intel_limits_g4x_hdmi
;
543 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
544 limit
= &intel_limits_g4x_sdvo
;
545 } else /* The option is for other outputs */
546 limit
= &intel_limits_i9xx_sdvo
;
551 static const intel_limit_t
*
552 intel_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
554 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
555 const intel_limit_t
*limit
;
558 limit
= &intel_limits_bxt
;
559 else if (HAS_PCH_SPLIT(dev
))
560 limit
= intel_ironlake_limit(crtc_state
, refclk
);
561 else if (IS_G4X(dev
)) {
562 limit
= intel_g4x_limit(crtc_state
);
563 } else if (IS_PINEVIEW(dev
)) {
564 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
565 limit
= &intel_limits_pineview_lvds
;
567 limit
= &intel_limits_pineview_sdvo
;
568 } else if (IS_CHERRYVIEW(dev
)) {
569 limit
= &intel_limits_chv
;
570 } else if (IS_VALLEYVIEW(dev
)) {
571 limit
= &intel_limits_vlv
;
572 } else if (!IS_GEN2(dev
)) {
573 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
574 limit
= &intel_limits_i9xx_lvds
;
576 limit
= &intel_limits_i9xx_sdvo
;
578 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
579 limit
= &intel_limits_i8xx_lvds
;
580 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
581 limit
= &intel_limits_i8xx_dvo
;
583 limit
= &intel_limits_i8xx_dac
;
589 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
590 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
591 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
592 * The helpers' return value is the rate of the clock that is fed to the
593 * display engine's pipe which can be the above fast dot clock rate or a
594 * divided-down version of it.
596 /* m1 is reserved as 0 in Pineview, n is a ring counter */
597 static int pnv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
599 clock
->m
= clock
->m2
+ 2;
600 clock
->p
= clock
->p1
* clock
->p2
;
601 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
603 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
604 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
609 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
611 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
614 static int i9xx_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
616 clock
->m
= i9xx_dpll_compute_m(clock
);
617 clock
->p
= clock
->p1
* clock
->p2
;
618 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
620 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
621 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
626 static int vlv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
628 clock
->m
= clock
->m1
* clock
->m2
;
629 clock
->p
= clock
->p1
* clock
->p2
;
630 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
632 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
633 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
635 return clock
->dot
/ 5;
638 int chv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
640 clock
->m
= clock
->m1
* clock
->m2
;
641 clock
->p
= clock
->p1
* clock
->p2
;
642 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
644 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
646 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
648 return clock
->dot
/ 5;
651 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
653 * Returns whether the given set of divisors are valid for a given refclk with
654 * the given connectors.
657 static bool intel_PLL_is_valid(struct drm_device
*dev
,
658 const intel_limit_t
*limit
,
659 const intel_clock_t
*clock
)
661 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
662 INTELPllInvalid("n out of range\n");
663 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
664 INTELPllInvalid("p1 out of range\n");
665 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
666 INTELPllInvalid("m2 out of range\n");
667 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
668 INTELPllInvalid("m1 out of range\n");
670 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
))
671 if (clock
->m1
<= clock
->m2
)
672 INTELPllInvalid("m1 <= m2\n");
674 if (!IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
)) {
675 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
676 INTELPllInvalid("p out of range\n");
677 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
678 INTELPllInvalid("m out of range\n");
681 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
682 INTELPllInvalid("vco out of range\n");
683 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
684 * connector, etc., rather than just a single range.
686 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
687 INTELPllInvalid("dot out of range\n");
693 i9xx_select_p2_div(const intel_limit_t
*limit
,
694 const struct intel_crtc_state
*crtc_state
,
697 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
699 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
701 * For LVDS just rely on its current settings for dual-channel.
702 * We haven't figured out how to reliably set up different
703 * single/dual channel state, if we even can.
705 if (intel_is_dual_link_lvds(dev
))
706 return limit
->p2
.p2_fast
;
708 return limit
->p2
.p2_slow
;
710 if (target
< limit
->p2
.dot_limit
)
711 return limit
->p2
.p2_slow
;
713 return limit
->p2
.p2_fast
;
718 i9xx_find_best_dpll(const intel_limit_t
*limit
,
719 struct intel_crtc_state
*crtc_state
,
720 int target
, int refclk
, intel_clock_t
*match_clock
,
721 intel_clock_t
*best_clock
)
723 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
727 memset(best_clock
, 0, sizeof(*best_clock
));
729 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
731 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
733 for (clock
.m2
= limit
->m2
.min
;
734 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
735 if (clock
.m2
>= clock
.m1
)
737 for (clock
.n
= limit
->n
.min
;
738 clock
.n
<= limit
->n
.max
; clock
.n
++) {
739 for (clock
.p1
= limit
->p1
.min
;
740 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
743 i9xx_calc_dpll_params(refclk
, &clock
);
744 if (!intel_PLL_is_valid(dev
, limit
,
748 clock
.p
!= match_clock
->p
)
751 this_err
= abs(clock
.dot
- target
);
752 if (this_err
< err
) {
761 return (err
!= target
);
765 pnv_find_best_dpll(const intel_limit_t
*limit
,
766 struct intel_crtc_state
*crtc_state
,
767 int target
, int refclk
, intel_clock_t
*match_clock
,
768 intel_clock_t
*best_clock
)
770 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
774 memset(best_clock
, 0, sizeof(*best_clock
));
776 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
778 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
780 for (clock
.m2
= limit
->m2
.min
;
781 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
782 for (clock
.n
= limit
->n
.min
;
783 clock
.n
<= limit
->n
.max
; clock
.n
++) {
784 for (clock
.p1
= limit
->p1
.min
;
785 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
788 pnv_calc_dpll_params(refclk
, &clock
);
789 if (!intel_PLL_is_valid(dev
, limit
,
793 clock
.p
!= match_clock
->p
)
796 this_err
= abs(clock
.dot
- target
);
797 if (this_err
< err
) {
806 return (err
!= target
);
810 g4x_find_best_dpll(const intel_limit_t
*limit
,
811 struct intel_crtc_state
*crtc_state
,
812 int target
, int refclk
, intel_clock_t
*match_clock
,
813 intel_clock_t
*best_clock
)
815 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
819 /* approximately equals target * 0.00585 */
820 int err_most
= (target
>> 8) + (target
>> 9);
822 memset(best_clock
, 0, sizeof(*best_clock
));
824 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
826 max_n
= limit
->n
.max
;
827 /* based on hardware requirement, prefer smaller n to precision */
828 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
829 /* based on hardware requirement, prefere larger m1,m2 */
830 for (clock
.m1
= limit
->m1
.max
;
831 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
832 for (clock
.m2
= limit
->m2
.max
;
833 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
834 for (clock
.p1
= limit
->p1
.max
;
835 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
838 i9xx_calc_dpll_params(refclk
, &clock
);
839 if (!intel_PLL_is_valid(dev
, limit
,
843 this_err
= abs(clock
.dot
- target
);
844 if (this_err
< err_most
) {
858 * Check if the calculated PLL configuration is more optimal compared to the
859 * best configuration and error found so far. Return the calculated error.
861 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
862 const intel_clock_t
*calculated_clock
,
863 const intel_clock_t
*best_clock
,
864 unsigned int best_error_ppm
,
865 unsigned int *error_ppm
)
868 * For CHV ignore the error and consider only the P value.
869 * Prefer a bigger P value based on HW requirements.
871 if (IS_CHERRYVIEW(dev
)) {
874 return calculated_clock
->p
> best_clock
->p
;
877 if (WARN_ON_ONCE(!target_freq
))
880 *error_ppm
= div_u64(1000000ULL *
881 abs(target_freq
- calculated_clock
->dot
),
884 * Prefer a better P value over a better (smaller) error if the error
885 * is small. Ensure this preference for future configurations too by
886 * setting the error to 0.
888 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
894 return *error_ppm
+ 10 < best_error_ppm
;
898 vlv_find_best_dpll(const intel_limit_t
*limit
,
899 struct intel_crtc_state
*crtc_state
,
900 int target
, int refclk
, intel_clock_t
*match_clock
,
901 intel_clock_t
*best_clock
)
903 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
904 struct drm_device
*dev
= crtc
->base
.dev
;
906 unsigned int bestppm
= 1000000;
907 /* min update 19.2 MHz */
908 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
911 target
*= 5; /* fast clock */
913 memset(best_clock
, 0, sizeof(*best_clock
));
915 /* based on hardware requirement, prefer smaller n to precision */
916 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
917 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
918 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
919 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
920 clock
.p
= clock
.p1
* clock
.p2
;
921 /* based on hardware requirement, prefer bigger m1,m2 values */
922 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
925 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
928 vlv_calc_dpll_params(refclk
, &clock
);
930 if (!intel_PLL_is_valid(dev
, limit
,
934 if (!vlv_PLL_is_optimal(dev
, target
,
952 chv_find_best_dpll(const intel_limit_t
*limit
,
953 struct intel_crtc_state
*crtc_state
,
954 int target
, int refclk
, intel_clock_t
*match_clock
,
955 intel_clock_t
*best_clock
)
957 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
958 struct drm_device
*dev
= crtc
->base
.dev
;
959 unsigned int best_error_ppm
;
964 memset(best_clock
, 0, sizeof(*best_clock
));
965 best_error_ppm
= 1000000;
968 * Based on hardware doc, the n always set to 1, and m1 always
969 * set to 2. If requires to support 200Mhz refclk, we need to
970 * revisit this because n may not 1 anymore.
972 clock
.n
= 1, clock
.m1
= 2;
973 target
*= 5; /* fast clock */
975 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
976 for (clock
.p2
= limit
->p2
.p2_fast
;
977 clock
.p2
>= limit
->p2
.p2_slow
;
978 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
979 unsigned int error_ppm
;
981 clock
.p
= clock
.p1
* clock
.p2
;
983 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
984 clock
.n
) << 22, refclk
* clock
.m1
);
986 if (m2
> INT_MAX
/clock
.m1
)
991 chv_calc_dpll_params(refclk
, &clock
);
993 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
996 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
997 best_error_ppm
, &error_ppm
))
1000 *best_clock
= clock
;
1001 best_error_ppm
= error_ppm
;
1009 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1010 intel_clock_t
*best_clock
)
1012 int refclk
= i9xx_get_refclk(crtc_state
, 0);
1014 return chv_find_best_dpll(intel_limit(crtc_state
, refclk
), crtc_state
,
1015 target_clock
, refclk
, NULL
, best_clock
);
1018 bool intel_crtc_active(struct drm_crtc
*crtc
)
1020 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1022 /* Be paranoid as we can arrive here with only partial
1023 * state retrieved from the hardware during setup.
1025 * We can ditch the adjusted_mode.crtc_clock check as soon
1026 * as Haswell has gained clock readout/fastboot support.
1028 * We can ditch the crtc->primary->fb check as soon as we can
1029 * properly reconstruct framebuffers.
1031 * FIXME: The intel_crtc->active here should be switched to
1032 * crtc->state->active once we have proper CRTC states wired up
1035 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
1036 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1039 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1042 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1043 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1045 return intel_crtc
->config
->cpu_transcoder
;
1048 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1051 u32 reg
= PIPEDSL(pipe
);
1056 line_mask
= DSL_LINEMASK_GEN2
;
1058 line_mask
= DSL_LINEMASK_GEN3
;
1060 line1
= I915_READ(reg
) & line_mask
;
1062 line2
= I915_READ(reg
) & line_mask
;
1064 return line1
== line2
;
1068 * intel_wait_for_pipe_off - wait for pipe to turn off
1069 * @crtc: crtc whose pipe to wait for
1071 * After disabling a pipe, we can't wait for vblank in the usual way,
1072 * spinning on the vblank interrupt status bit, since we won't actually
1073 * see an interrupt when the pipe is disabled.
1075 * On Gen4 and above:
1076 * wait for the pipe register state bit to turn off
1079 * wait for the display line value to settle (it usually
1080 * ends up stopping at the start of the next frame).
1083 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1085 struct drm_device
*dev
= crtc
->base
.dev
;
1086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1087 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1088 enum pipe pipe
= crtc
->pipe
;
1090 if (INTEL_INFO(dev
)->gen
>= 4) {
1091 int reg
= PIPECONF(cpu_transcoder
);
1093 /* Wait for the Pipe State to go off */
1094 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1096 WARN(1, "pipe_off wait timed out\n");
1098 /* Wait for the display line to settle */
1099 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1100 WARN(1, "pipe_off wait timed out\n");
1104 static const char *state_string(bool enabled
)
1106 return enabled
? "on" : "off";
1109 /* Only for pre-ILK configs */
1110 void assert_pll(struct drm_i915_private
*dev_priv
,
1111 enum pipe pipe
, bool state
)
1118 val
= I915_READ(reg
);
1119 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1120 I915_STATE_WARN(cur_state
!= state
,
1121 "PLL state assertion failure (expected %s, current %s)\n",
1122 state_string(state
), state_string(cur_state
));
1125 /* XXX: the dsi pll is shared between MIPI DSI ports */
1126 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1131 mutex_lock(&dev_priv
->sb_lock
);
1132 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1133 mutex_unlock(&dev_priv
->sb_lock
);
1135 cur_state
= val
& DSI_PLL_VCO_EN
;
1136 I915_STATE_WARN(cur_state
!= state
,
1137 "DSI PLL state assertion failure (expected %s, current %s)\n",
1138 state_string(state
), state_string(cur_state
));
1140 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1141 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1143 struct intel_shared_dpll
*
1144 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1146 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1148 if (crtc
->config
->shared_dpll
< 0)
1151 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1155 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1156 struct intel_shared_dpll
*pll
,
1160 struct intel_dpll_hw_state hw_state
;
1163 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1166 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1167 I915_STATE_WARN(cur_state
!= state
,
1168 "%s assertion failure (expected %s, current %s)\n",
1169 pll
->name
, state_string(state
), state_string(cur_state
));
1172 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1173 enum pipe pipe
, bool state
)
1178 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1181 if (HAS_DDI(dev_priv
->dev
)) {
1182 /* DDI does not have a specific FDI_TX register */
1183 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1184 val
= I915_READ(reg
);
1185 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1187 reg
= FDI_TX_CTL(pipe
);
1188 val
= I915_READ(reg
);
1189 cur_state
= !!(val
& FDI_TX_ENABLE
);
1191 I915_STATE_WARN(cur_state
!= state
,
1192 "FDI TX state assertion failure (expected %s, current %s)\n",
1193 state_string(state
), state_string(cur_state
));
1195 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1196 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1198 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1199 enum pipe pipe
, bool state
)
1205 reg
= FDI_RX_CTL(pipe
);
1206 val
= I915_READ(reg
);
1207 cur_state
= !!(val
& FDI_RX_ENABLE
);
1208 I915_STATE_WARN(cur_state
!= state
,
1209 "FDI RX state assertion failure (expected %s, current %s)\n",
1210 state_string(state
), state_string(cur_state
));
1212 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1213 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1215 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1221 /* ILK FDI PLL is always enabled */
1222 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1225 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1226 if (HAS_DDI(dev_priv
->dev
))
1229 reg
= FDI_TX_CTL(pipe
);
1230 val
= I915_READ(reg
);
1231 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1234 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1235 enum pipe pipe
, bool state
)
1241 reg
= FDI_RX_CTL(pipe
);
1242 val
= I915_READ(reg
);
1243 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1244 I915_STATE_WARN(cur_state
!= state
,
1245 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1246 state_string(state
), state_string(cur_state
));
1249 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1252 struct drm_device
*dev
= dev_priv
->dev
;
1255 enum pipe panel_pipe
= PIPE_A
;
1258 if (WARN_ON(HAS_DDI(dev
)))
1261 if (HAS_PCH_SPLIT(dev
)) {
1264 pp_reg
= PCH_PP_CONTROL
;
1265 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1267 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1268 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1269 panel_pipe
= PIPE_B
;
1270 /* XXX: else fix for eDP */
1271 } else if (IS_VALLEYVIEW(dev
)) {
1272 /* presumably write lock depends on pipe, not port select */
1273 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1276 pp_reg
= PP_CONTROL
;
1277 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1278 panel_pipe
= PIPE_B
;
1281 val
= I915_READ(pp_reg
);
1282 if (!(val
& PANEL_POWER_ON
) ||
1283 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1286 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1287 "panel assertion failure, pipe %c regs locked\n",
1291 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1292 enum pipe pipe
, bool state
)
1294 struct drm_device
*dev
= dev_priv
->dev
;
1297 if (IS_845G(dev
) || IS_I865G(dev
))
1298 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1300 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1302 I915_STATE_WARN(cur_state
!= state
,
1303 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1304 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1306 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1307 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1309 void assert_pipe(struct drm_i915_private
*dev_priv
,
1310 enum pipe pipe
, bool state
)
1315 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1318 /* if we need the pipe quirk it must be always on */
1319 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1320 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1323 if (!intel_display_power_is_enabled(dev_priv
,
1324 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1327 reg
= PIPECONF(cpu_transcoder
);
1328 val
= I915_READ(reg
);
1329 cur_state
= !!(val
& PIPECONF_ENABLE
);
1332 I915_STATE_WARN(cur_state
!= state
,
1333 "pipe %c assertion failure (expected %s, current %s)\n",
1334 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1337 static void assert_plane(struct drm_i915_private
*dev_priv
,
1338 enum plane plane
, bool state
)
1344 reg
= DSPCNTR(plane
);
1345 val
= I915_READ(reg
);
1346 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1347 I915_STATE_WARN(cur_state
!= state
,
1348 "plane %c assertion failure (expected %s, current %s)\n",
1349 plane_name(plane
), state_string(state
), state_string(cur_state
));
1352 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1353 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1355 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1358 struct drm_device
*dev
= dev_priv
->dev
;
1363 /* Primary planes are fixed to pipes on gen4+ */
1364 if (INTEL_INFO(dev
)->gen
>= 4) {
1365 reg
= DSPCNTR(pipe
);
1366 val
= I915_READ(reg
);
1367 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1368 "plane %c assertion failure, should be disabled but not\n",
1373 /* Need to check both planes against the pipe */
1374 for_each_pipe(dev_priv
, i
) {
1376 val
= I915_READ(reg
);
1377 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1378 DISPPLANE_SEL_PIPE_SHIFT
;
1379 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1380 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1381 plane_name(i
), pipe_name(pipe
));
1385 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1388 struct drm_device
*dev
= dev_priv
->dev
;
1392 if (INTEL_INFO(dev
)->gen
>= 9) {
1393 for_each_sprite(dev_priv
, pipe
, sprite
) {
1394 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1395 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1396 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1397 sprite
, pipe_name(pipe
));
1399 } else if (IS_VALLEYVIEW(dev
)) {
1400 for_each_sprite(dev_priv
, pipe
, sprite
) {
1401 reg
= SPCNTR(pipe
, sprite
);
1402 val
= I915_READ(reg
);
1403 I915_STATE_WARN(val
& SP_ENABLE
,
1404 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1405 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1407 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1409 val
= I915_READ(reg
);
1410 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1411 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1412 plane_name(pipe
), pipe_name(pipe
));
1413 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1414 reg
= DVSCNTR(pipe
);
1415 val
= I915_READ(reg
);
1416 I915_STATE_WARN(val
& DVS_ENABLE
,
1417 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1418 plane_name(pipe
), pipe_name(pipe
));
1422 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1424 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1425 drm_crtc_vblank_put(crtc
);
1428 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1433 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1435 val
= I915_READ(PCH_DREF_CONTROL
);
1436 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1437 DREF_SUPERSPREAD_SOURCE_MASK
));
1438 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1441 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1448 reg
= PCH_TRANSCONF(pipe
);
1449 val
= I915_READ(reg
);
1450 enabled
= !!(val
& TRANS_ENABLE
);
1451 I915_STATE_WARN(enabled
,
1452 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1456 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1457 enum pipe pipe
, u32 port_sel
, u32 val
)
1459 if ((val
& DP_PORT_EN
) == 0)
1462 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1463 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1464 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1465 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1467 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1468 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1471 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1477 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1478 enum pipe pipe
, u32 val
)
1480 if ((val
& SDVO_ENABLE
) == 0)
1483 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1484 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1486 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1487 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1490 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1496 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1497 enum pipe pipe
, u32 val
)
1499 if ((val
& LVDS_PORT_EN
) == 0)
1502 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1503 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1506 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1512 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1513 enum pipe pipe
, u32 val
)
1515 if ((val
& ADPA_DAC_ENABLE
) == 0)
1517 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1518 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1521 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1527 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1528 enum pipe pipe
, int reg
, u32 port_sel
)
1530 u32 val
= I915_READ(reg
);
1531 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1532 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1533 reg
, pipe_name(pipe
));
1535 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1536 && (val
& DP_PIPEB_SELECT
),
1537 "IBX PCH dp port still using transcoder B\n");
1540 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1541 enum pipe pipe
, int reg
)
1543 u32 val
= I915_READ(reg
);
1544 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1545 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1546 reg
, pipe_name(pipe
));
1548 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1549 && (val
& SDVO_PIPE_B_SELECT
),
1550 "IBX PCH hdmi port still using transcoder B\n");
1553 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1559 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1560 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1561 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1564 val
= I915_READ(reg
);
1565 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1566 "PCH VGA enabled on transcoder %c, should be disabled\n",
1570 val
= I915_READ(reg
);
1571 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1572 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1575 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1576 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1577 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1580 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1581 const struct intel_crtc_state
*pipe_config
)
1583 struct drm_device
*dev
= crtc
->base
.dev
;
1584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1585 int reg
= DPLL(crtc
->pipe
);
1586 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1588 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1590 /* No really, not for ILK+ */
1591 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1593 /* PLL is protected by panel, make sure we can write it */
1594 if (IS_MOBILE(dev_priv
->dev
))
1595 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1597 I915_WRITE(reg
, dpll
);
1601 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1602 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1604 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1605 POSTING_READ(DPLL_MD(crtc
->pipe
));
1607 /* We do this three times for luck */
1608 I915_WRITE(reg
, dpll
);
1610 udelay(150); /* wait for warmup */
1611 I915_WRITE(reg
, dpll
);
1613 udelay(150); /* wait for warmup */
1614 I915_WRITE(reg
, dpll
);
1616 udelay(150); /* wait for warmup */
1619 static void chv_enable_pll(struct intel_crtc
*crtc
,
1620 const struct intel_crtc_state
*pipe_config
)
1622 struct drm_device
*dev
= crtc
->base
.dev
;
1623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1624 int pipe
= crtc
->pipe
;
1625 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1628 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1630 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1632 mutex_lock(&dev_priv
->sb_lock
);
1634 /* Enable back the 10bit clock to display controller */
1635 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1636 tmp
|= DPIO_DCLKP_EN
;
1637 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1639 mutex_unlock(&dev_priv
->sb_lock
);
1642 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1647 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1649 /* Check PLL is locked */
1650 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1651 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1653 /* not sure when this should be written */
1654 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1655 POSTING_READ(DPLL_MD(pipe
));
1658 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1660 struct intel_crtc
*crtc
;
1663 for_each_intel_crtc(dev
, crtc
)
1664 count
+= crtc
->base
.state
->active
&&
1665 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1670 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1672 struct drm_device
*dev
= crtc
->base
.dev
;
1673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1674 int reg
= DPLL(crtc
->pipe
);
1675 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1677 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1679 /* No really, not for ILK+ */
1680 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1682 /* PLL is protected by panel, make sure we can write it */
1683 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1684 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1686 /* Enable DVO 2x clock on both PLLs if necessary */
1687 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1689 * It appears to be important that we don't enable this
1690 * for the current pipe before otherwise configuring the
1691 * PLL. No idea how this should be handled if multiple
1692 * DVO outputs are enabled simultaneosly.
1694 dpll
|= DPLL_DVO_2X_MODE
;
1695 I915_WRITE(DPLL(!crtc
->pipe
),
1696 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1699 /* Wait for the clocks to stabilize. */
1703 if (INTEL_INFO(dev
)->gen
>= 4) {
1704 I915_WRITE(DPLL_MD(crtc
->pipe
),
1705 crtc
->config
->dpll_hw_state
.dpll_md
);
1707 /* The pixel multiplier can only be updated once the
1708 * DPLL is enabled and the clocks are stable.
1710 * So write it again.
1712 I915_WRITE(reg
, dpll
);
1715 /* We do this three times for luck */
1716 I915_WRITE(reg
, dpll
);
1718 udelay(150); /* wait for warmup */
1719 I915_WRITE(reg
, dpll
);
1721 udelay(150); /* wait for warmup */
1722 I915_WRITE(reg
, dpll
);
1724 udelay(150); /* wait for warmup */
1728 * i9xx_disable_pll - disable a PLL
1729 * @dev_priv: i915 private structure
1730 * @pipe: pipe PLL to disable
1732 * Disable the PLL for @pipe, making sure the pipe is off first.
1734 * Note! This is for pre-ILK only.
1736 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1738 struct drm_device
*dev
= crtc
->base
.dev
;
1739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1740 enum pipe pipe
= crtc
->pipe
;
1742 /* Disable DVO 2x clock on both PLLs if necessary */
1744 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1745 !intel_num_dvo_pipes(dev
)) {
1746 I915_WRITE(DPLL(PIPE_B
),
1747 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1748 I915_WRITE(DPLL(PIPE_A
),
1749 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1752 /* Don't disable pipe or pipe PLLs if needed */
1753 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1754 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1757 /* Make sure the pipe isn't still relying on us */
1758 assert_pipe_disabled(dev_priv
, pipe
);
1760 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1761 POSTING_READ(DPLL(pipe
));
1764 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1768 /* Make sure the pipe isn't still relying on us */
1769 assert_pipe_disabled(dev_priv
, pipe
);
1772 * Leave integrated clock source and reference clock enabled for pipe B.
1773 * The latter is needed for VGA hotplug / manual detection.
1775 val
= DPLL_VGA_MODE_DIS
;
1777 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REF_CLK_ENABLE_VLV
;
1778 I915_WRITE(DPLL(pipe
), val
);
1779 POSTING_READ(DPLL(pipe
));
1783 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1785 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1788 /* Make sure the pipe isn't still relying on us */
1789 assert_pipe_disabled(dev_priv
, pipe
);
1791 /* Set PLL en = 0 */
1792 val
= DPLL_SSC_REF_CLK_CHV
|
1793 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1795 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1796 I915_WRITE(DPLL(pipe
), val
);
1797 POSTING_READ(DPLL(pipe
));
1799 mutex_lock(&dev_priv
->sb_lock
);
1801 /* Disable 10bit clock to display controller */
1802 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1803 val
&= ~DPIO_DCLKP_EN
;
1804 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1806 mutex_unlock(&dev_priv
->sb_lock
);
1809 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1810 struct intel_digital_port
*dport
,
1811 unsigned int expected_mask
)
1816 switch (dport
->port
) {
1818 port_mask
= DPLL_PORTB_READY_MASK
;
1822 port_mask
= DPLL_PORTC_READY_MASK
;
1824 expected_mask
<<= 4;
1827 port_mask
= DPLL_PORTD_READY_MASK
;
1828 dpll_reg
= DPIO_PHY_STATUS
;
1834 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == expected_mask
, 1000))
1835 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1836 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1839 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1841 struct drm_device
*dev
= crtc
->base
.dev
;
1842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1843 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1845 if (WARN_ON(pll
== NULL
))
1848 WARN_ON(!pll
->config
.crtc_mask
);
1849 if (pll
->active
== 0) {
1850 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1852 assert_shared_dpll_disabled(dev_priv
, pll
);
1854 pll
->mode_set(dev_priv
, pll
);
1859 * intel_enable_shared_dpll - enable PCH PLL
1860 * @dev_priv: i915 private structure
1861 * @pipe: pipe PLL to enable
1863 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1864 * drives the transcoder clock.
1866 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1868 struct drm_device
*dev
= crtc
->base
.dev
;
1869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1870 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1872 if (WARN_ON(pll
== NULL
))
1875 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1878 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1879 pll
->name
, pll
->active
, pll
->on
,
1880 crtc
->base
.base
.id
);
1882 if (pll
->active
++) {
1884 assert_shared_dpll_enabled(dev_priv
, pll
);
1889 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1891 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1892 pll
->enable(dev_priv
, pll
);
1896 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1898 struct drm_device
*dev
= crtc
->base
.dev
;
1899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1900 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1902 /* PCH only available on ILK+ */
1903 if (INTEL_INFO(dev
)->gen
< 5)
1909 if (WARN_ON(!(pll
->config
.crtc_mask
& (1 << drm_crtc_index(&crtc
->base
)))))
1912 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1913 pll
->name
, pll
->active
, pll
->on
,
1914 crtc
->base
.base
.id
);
1916 if (WARN_ON(pll
->active
== 0)) {
1917 assert_shared_dpll_disabled(dev_priv
, pll
);
1921 assert_shared_dpll_enabled(dev_priv
, pll
);
1926 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1927 pll
->disable(dev_priv
, pll
);
1930 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1933 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1936 struct drm_device
*dev
= dev_priv
->dev
;
1937 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1938 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1939 uint32_t reg
, val
, pipeconf_val
;
1941 /* PCH only available on ILK+ */
1942 BUG_ON(!HAS_PCH_SPLIT(dev
));
1944 /* Make sure PCH DPLL is enabled */
1945 assert_shared_dpll_enabled(dev_priv
,
1946 intel_crtc_to_shared_dpll(intel_crtc
));
1948 /* FDI must be feeding us bits for PCH ports */
1949 assert_fdi_tx_enabled(dev_priv
, pipe
);
1950 assert_fdi_rx_enabled(dev_priv
, pipe
);
1952 if (HAS_PCH_CPT(dev
)) {
1953 /* Workaround: Set the timing override bit before enabling the
1954 * pch transcoder. */
1955 reg
= TRANS_CHICKEN2(pipe
);
1956 val
= I915_READ(reg
);
1957 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1958 I915_WRITE(reg
, val
);
1961 reg
= PCH_TRANSCONF(pipe
);
1962 val
= I915_READ(reg
);
1963 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1965 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1967 * Make the BPC in transcoder be consistent with
1968 * that in pipeconf reg. For HDMI we must use 8bpc
1969 * here for both 8bpc and 12bpc.
1971 val
&= ~PIPECONF_BPC_MASK
;
1972 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_HDMI
))
1973 val
|= PIPECONF_8BPC
;
1975 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1978 val
&= ~TRANS_INTERLACE_MASK
;
1979 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1980 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1981 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1982 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1984 val
|= TRANS_INTERLACED
;
1986 val
|= TRANS_PROGRESSIVE
;
1988 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1989 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1990 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1993 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1994 enum transcoder cpu_transcoder
)
1996 u32 val
, pipeconf_val
;
1998 /* PCH only available on ILK+ */
1999 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
2001 /* FDI must be feeding us bits for PCH ports */
2002 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
2003 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
2005 /* Workaround: set timing override bit. */
2006 val
= I915_READ(_TRANSA_CHICKEN2
);
2007 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
2008 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2011 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
2013 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
2014 PIPECONF_INTERLACED_ILK
)
2015 val
|= TRANS_INTERLACED
;
2017 val
|= TRANS_PROGRESSIVE
;
2019 I915_WRITE(LPT_TRANSCONF
, val
);
2020 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
2021 DRM_ERROR("Failed to enable PCH transcoder\n");
2024 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2027 struct drm_device
*dev
= dev_priv
->dev
;
2030 /* FDI relies on the transcoder */
2031 assert_fdi_tx_disabled(dev_priv
, pipe
);
2032 assert_fdi_rx_disabled(dev_priv
, pipe
);
2034 /* Ports must be off as well */
2035 assert_pch_ports_disabled(dev_priv
, pipe
);
2037 reg
= PCH_TRANSCONF(pipe
);
2038 val
= I915_READ(reg
);
2039 val
&= ~TRANS_ENABLE
;
2040 I915_WRITE(reg
, val
);
2041 /* wait for PCH transcoder off, transcoder state */
2042 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2043 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
2045 if (!HAS_PCH_IBX(dev
)) {
2046 /* Workaround: Clear the timing override chicken bit again. */
2047 reg
= TRANS_CHICKEN2(pipe
);
2048 val
= I915_READ(reg
);
2049 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2050 I915_WRITE(reg
, val
);
2054 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
2058 val
= I915_READ(LPT_TRANSCONF
);
2059 val
&= ~TRANS_ENABLE
;
2060 I915_WRITE(LPT_TRANSCONF
, val
);
2061 /* wait for PCH transcoder off, transcoder state */
2062 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
2063 DRM_ERROR("Failed to disable PCH transcoder\n");
2065 /* Workaround: clear timing override bit. */
2066 val
= I915_READ(_TRANSA_CHICKEN2
);
2067 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2068 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2072 * intel_enable_pipe - enable a pipe, asserting requirements
2073 * @crtc: crtc responsible for the pipe
2075 * Enable @crtc's pipe, making sure that various hardware specific requirements
2076 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2078 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2080 struct drm_device
*dev
= crtc
->base
.dev
;
2081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2082 enum pipe pipe
= crtc
->pipe
;
2083 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2085 enum pipe pch_transcoder
;
2089 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
2091 assert_planes_disabled(dev_priv
, pipe
);
2092 assert_cursor_disabled(dev_priv
, pipe
);
2093 assert_sprites_disabled(dev_priv
, pipe
);
2095 if (HAS_PCH_LPT(dev_priv
->dev
))
2096 pch_transcoder
= TRANSCODER_A
;
2098 pch_transcoder
= pipe
;
2101 * A pipe without a PLL won't actually be able to drive bits from
2102 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2105 if (HAS_GMCH_DISPLAY(dev_priv
->dev
))
2106 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2107 assert_dsi_pll_enabled(dev_priv
);
2109 assert_pll_enabled(dev_priv
, pipe
);
2111 if (crtc
->config
->has_pch_encoder
) {
2112 /* if driving the PCH, we need FDI enabled */
2113 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2114 assert_fdi_tx_pll_enabled(dev_priv
,
2115 (enum pipe
) cpu_transcoder
);
2117 /* FIXME: assert CPU port conditions for SNB+ */
2120 reg
= PIPECONF(cpu_transcoder
);
2121 val
= I915_READ(reg
);
2122 if (val
& PIPECONF_ENABLE
) {
2123 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2124 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2128 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2133 * intel_disable_pipe - disable a pipe, asserting requirements
2134 * @crtc: crtc whose pipes is to be disabled
2136 * Disable the pipe of @crtc, making sure that various hardware
2137 * specific requirements are met, if applicable, e.g. plane
2138 * disabled, panel fitter off, etc.
2140 * Will wait until the pipe has shut down before returning.
2142 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2144 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2145 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2146 enum pipe pipe
= crtc
->pipe
;
2150 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
2153 * Make sure planes won't keep trying to pump pixels to us,
2154 * or we might hang the display.
2156 assert_planes_disabled(dev_priv
, pipe
);
2157 assert_cursor_disabled(dev_priv
, pipe
);
2158 assert_sprites_disabled(dev_priv
, pipe
);
2160 reg
= PIPECONF(cpu_transcoder
);
2161 val
= I915_READ(reg
);
2162 if ((val
& PIPECONF_ENABLE
) == 0)
2166 * Double wide has implications for planes
2167 * so best keep it disabled when not needed.
2169 if (crtc
->config
->double_wide
)
2170 val
&= ~PIPECONF_DOUBLE_WIDE
;
2172 /* Don't disable pipe or pipe PLLs if needed */
2173 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2174 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2175 val
&= ~PIPECONF_ENABLE
;
2177 I915_WRITE(reg
, val
);
2178 if ((val
& PIPECONF_ENABLE
) == 0)
2179 intel_wait_for_pipe_off(crtc
);
2182 static bool need_vtd_wa(struct drm_device
*dev
)
2184 #ifdef CONFIG_INTEL_IOMMU
2185 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2192 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
2193 uint64_t fb_format_modifier
, unsigned int plane
)
2195 unsigned int tile_height
;
2196 uint32_t pixel_bytes
;
2198 switch (fb_format_modifier
) {
2199 case DRM_FORMAT_MOD_NONE
:
2202 case I915_FORMAT_MOD_X_TILED
:
2203 tile_height
= IS_GEN2(dev
) ? 16 : 8;
2205 case I915_FORMAT_MOD_Y_TILED
:
2208 case I915_FORMAT_MOD_Yf_TILED
:
2209 pixel_bytes
= drm_format_plane_cpp(pixel_format
, plane
);
2210 switch (pixel_bytes
) {
2224 "128-bit pixels are not supported for display!");
2230 MISSING_CASE(fb_format_modifier
);
2239 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2240 uint32_t pixel_format
, uint64_t fb_format_modifier
)
2242 return ALIGN(height
, intel_tile_height(dev
, pixel_format
,
2243 fb_format_modifier
, 0));
2247 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
, struct drm_framebuffer
*fb
,
2248 const struct drm_plane_state
*plane_state
)
2250 struct intel_rotation_info
*info
= &view
->rotation_info
;
2251 unsigned int tile_height
, tile_pitch
;
2253 *view
= i915_ggtt_view_normal
;
2258 if (!intel_rotation_90_or_270(plane_state
->rotation
))
2261 *view
= i915_ggtt_view_rotated
;
2263 info
->height
= fb
->height
;
2264 info
->pixel_format
= fb
->pixel_format
;
2265 info
->pitch
= fb
->pitches
[0];
2266 info
->uv_offset
= fb
->offsets
[1];
2267 info
->fb_modifier
= fb
->modifier
[0];
2269 tile_height
= intel_tile_height(fb
->dev
, fb
->pixel_format
,
2270 fb
->modifier
[0], 0);
2271 tile_pitch
= PAGE_SIZE
/ tile_height
;
2272 info
->width_pages
= DIV_ROUND_UP(fb
->pitches
[0], tile_pitch
);
2273 info
->height_pages
= DIV_ROUND_UP(fb
->height
, tile_height
);
2274 info
->size
= info
->width_pages
* info
->height_pages
* PAGE_SIZE
;
2276 if (info
->pixel_format
== DRM_FORMAT_NV12
) {
2277 tile_height
= intel_tile_height(fb
->dev
, fb
->pixel_format
,
2278 fb
->modifier
[0], 1);
2279 tile_pitch
= PAGE_SIZE
/ tile_height
;
2280 info
->width_pages_uv
= DIV_ROUND_UP(fb
->pitches
[0], tile_pitch
);
2281 info
->height_pages_uv
= DIV_ROUND_UP(fb
->height
/ 2,
2283 info
->size_uv
= info
->width_pages_uv
* info
->height_pages_uv
*
2290 static unsigned int intel_linear_alignment(struct drm_i915_private
*dev_priv
)
2292 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2294 else if (IS_BROADWATER(dev_priv
) || IS_CRESTLINE(dev_priv
) ||
2295 IS_VALLEYVIEW(dev_priv
))
2297 else if (INTEL_INFO(dev_priv
)->gen
>= 4)
2304 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2305 struct drm_framebuffer
*fb
,
2306 const struct drm_plane_state
*plane_state
,
2307 struct intel_engine_cs
*pipelined
,
2308 struct drm_i915_gem_request
**pipelined_request
)
2310 struct drm_device
*dev
= fb
->dev
;
2311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2312 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2313 struct i915_ggtt_view view
;
2317 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2319 switch (fb
->modifier
[0]) {
2320 case DRM_FORMAT_MOD_NONE
:
2321 alignment
= intel_linear_alignment(dev_priv
);
2323 case I915_FORMAT_MOD_X_TILED
:
2324 if (INTEL_INFO(dev
)->gen
>= 9)
2325 alignment
= 256 * 1024;
2327 /* pin() will align the object as required by fence */
2331 case I915_FORMAT_MOD_Y_TILED
:
2332 case I915_FORMAT_MOD_Yf_TILED
:
2333 if (WARN_ONCE(INTEL_INFO(dev
)->gen
< 9,
2334 "Y tiling bo slipped through, driver bug!\n"))
2336 alignment
= 1 * 1024 * 1024;
2339 MISSING_CASE(fb
->modifier
[0]);
2343 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2347 /* Note that the w/a also requires 64 PTE of padding following the
2348 * bo. We currently fill all unused PTE with the shadow page and so
2349 * we should always have valid PTE following the scanout preventing
2352 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2353 alignment
= 256 * 1024;
2356 * Global gtt pte registers are special registers which actually forward
2357 * writes to a chunk of system memory. Which means that there is no risk
2358 * that the register values disappear as soon as we call
2359 * intel_runtime_pm_put(), so it is correct to wrap only the
2360 * pin/unpin/fence and not more.
2362 intel_runtime_pm_get(dev_priv
);
2364 dev_priv
->mm
.interruptible
= false;
2365 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
,
2366 pipelined_request
, &view
);
2368 goto err_interruptible
;
2370 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2371 * fence, whereas 965+ only requires a fence if using
2372 * framebuffer compression. For simplicity, we always install
2373 * a fence as the cost is not that onerous.
2375 ret
= i915_gem_object_get_fence(obj
);
2376 if (ret
== -EDEADLK
) {
2378 * -EDEADLK means there are no free fences
2381 * This is propagated to atomic, but it uses
2382 * -EDEADLK to force a locking recovery, so
2383 * change the returned error to -EBUSY.
2390 i915_gem_object_pin_fence(obj
);
2392 dev_priv
->mm
.interruptible
= true;
2393 intel_runtime_pm_put(dev_priv
);
2397 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2399 dev_priv
->mm
.interruptible
= true;
2400 intel_runtime_pm_put(dev_priv
);
2404 static void intel_unpin_fb_obj(struct drm_framebuffer
*fb
,
2405 const struct drm_plane_state
*plane_state
)
2407 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2408 struct i915_ggtt_view view
;
2411 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2413 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2414 WARN_ONCE(ret
, "Couldn't get view from plane state!");
2416 i915_gem_object_unpin_fence(obj
);
2417 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2420 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2421 * is assumed to be a power-of-two. */
2422 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private
*dev_priv
,
2424 unsigned int tiling_mode
,
2428 if (tiling_mode
!= I915_TILING_NONE
) {
2429 unsigned int tile_rows
, tiles
;
2434 tiles
= *x
/ (512/cpp
);
2437 return tile_rows
* pitch
* 8 + tiles
* 4096;
2439 unsigned int alignment
= intel_linear_alignment(dev_priv
) - 1;
2440 unsigned int offset
;
2442 offset
= *y
* pitch
+ *x
* cpp
;
2443 *y
= (offset
& alignment
) / pitch
;
2444 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2445 return offset
& ~alignment
;
2449 static int i9xx_format_to_fourcc(int format
)
2452 case DISPPLANE_8BPP
:
2453 return DRM_FORMAT_C8
;
2454 case DISPPLANE_BGRX555
:
2455 return DRM_FORMAT_XRGB1555
;
2456 case DISPPLANE_BGRX565
:
2457 return DRM_FORMAT_RGB565
;
2459 case DISPPLANE_BGRX888
:
2460 return DRM_FORMAT_XRGB8888
;
2461 case DISPPLANE_RGBX888
:
2462 return DRM_FORMAT_XBGR8888
;
2463 case DISPPLANE_BGRX101010
:
2464 return DRM_FORMAT_XRGB2101010
;
2465 case DISPPLANE_RGBX101010
:
2466 return DRM_FORMAT_XBGR2101010
;
2470 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2473 case PLANE_CTL_FORMAT_RGB_565
:
2474 return DRM_FORMAT_RGB565
;
2476 case PLANE_CTL_FORMAT_XRGB_8888
:
2479 return DRM_FORMAT_ABGR8888
;
2481 return DRM_FORMAT_XBGR8888
;
2484 return DRM_FORMAT_ARGB8888
;
2486 return DRM_FORMAT_XRGB8888
;
2488 case PLANE_CTL_FORMAT_XRGB_2101010
:
2490 return DRM_FORMAT_XBGR2101010
;
2492 return DRM_FORMAT_XRGB2101010
;
2497 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2498 struct intel_initial_plane_config
*plane_config
)
2500 struct drm_device
*dev
= crtc
->base
.dev
;
2501 struct drm_i915_gem_object
*obj
= NULL
;
2502 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2503 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2504 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2505 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2508 size_aligned
-= base_aligned
;
2510 if (plane_config
->size
== 0)
2513 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2520 obj
->tiling_mode
= plane_config
->tiling
;
2521 if (obj
->tiling_mode
== I915_TILING_X
)
2522 obj
->stride
= fb
->pitches
[0];
2524 mode_cmd
.pixel_format
= fb
->pixel_format
;
2525 mode_cmd
.width
= fb
->width
;
2526 mode_cmd
.height
= fb
->height
;
2527 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2528 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2529 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2531 mutex_lock(&dev
->struct_mutex
);
2532 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2534 DRM_DEBUG_KMS("intel fb init failed\n");
2537 mutex_unlock(&dev
->struct_mutex
);
2539 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2543 drm_gem_object_unreference(&obj
->base
);
2544 mutex_unlock(&dev
->struct_mutex
);
2548 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2550 update_state_fb(struct drm_plane
*plane
)
2552 if (plane
->fb
== plane
->state
->fb
)
2555 if (plane
->state
->fb
)
2556 drm_framebuffer_unreference(plane
->state
->fb
);
2557 plane
->state
->fb
= plane
->fb
;
2558 if (plane
->state
->fb
)
2559 drm_framebuffer_reference(plane
->state
->fb
);
2563 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2564 struct intel_initial_plane_config
*plane_config
)
2566 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2569 struct intel_crtc
*i
;
2570 struct drm_i915_gem_object
*obj
;
2571 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2572 struct drm_plane_state
*plane_state
= primary
->state
;
2573 struct drm_framebuffer
*fb
;
2575 if (!plane_config
->fb
)
2578 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2579 fb
= &plane_config
->fb
->base
;
2583 kfree(plane_config
->fb
);
2586 * Failed to alloc the obj, check to see if we should share
2587 * an fb with another CRTC instead
2589 for_each_crtc(dev
, c
) {
2590 i
= to_intel_crtc(c
);
2592 if (c
== &intel_crtc
->base
)
2598 fb
= c
->primary
->fb
;
2602 obj
= intel_fb_obj(fb
);
2603 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2604 drm_framebuffer_reference(fb
);
2612 plane_state
->src_x
= plane_state
->src_y
= 0;
2613 plane_state
->src_w
= fb
->width
<< 16;
2614 plane_state
->src_h
= fb
->height
<< 16;
2616 plane_state
->crtc_x
= plane_state
->src_y
= 0;
2617 plane_state
->crtc_w
= fb
->width
;
2618 plane_state
->crtc_h
= fb
->height
;
2620 obj
= intel_fb_obj(fb
);
2621 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2622 dev_priv
->preserve_bios_swizzle
= true;
2624 drm_framebuffer_reference(fb
);
2625 primary
->fb
= primary
->state
->fb
= fb
;
2626 primary
->crtc
= primary
->state
->crtc
= &intel_crtc
->base
;
2627 intel_crtc
->base
.state
->plane_mask
|= (1 << drm_plane_index(primary
));
2628 obj
->frontbuffer_bits
|= to_intel_plane(primary
)->frontbuffer_bit
;
2631 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2632 struct drm_framebuffer
*fb
,
2635 struct drm_device
*dev
= crtc
->dev
;
2636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2637 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2638 struct drm_plane
*primary
= crtc
->primary
;
2639 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2640 struct drm_i915_gem_object
*obj
;
2641 int plane
= intel_crtc
->plane
;
2642 unsigned long linear_offset
;
2644 u32 reg
= DSPCNTR(plane
);
2647 if (!visible
|| !fb
) {
2649 if (INTEL_INFO(dev
)->gen
>= 4)
2650 I915_WRITE(DSPSURF(plane
), 0);
2652 I915_WRITE(DSPADDR(plane
), 0);
2657 obj
= intel_fb_obj(fb
);
2658 if (WARN_ON(obj
== NULL
))
2661 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2663 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2665 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2667 if (INTEL_INFO(dev
)->gen
< 4) {
2668 if (intel_crtc
->pipe
== PIPE_B
)
2669 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2671 /* pipesrc and dspsize control the size that is scaled from,
2672 * which should always be the user's requested size.
2674 I915_WRITE(DSPSIZE(plane
),
2675 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2676 (intel_crtc
->config
->pipe_src_w
- 1));
2677 I915_WRITE(DSPPOS(plane
), 0);
2678 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2679 I915_WRITE(PRIMSIZE(plane
),
2680 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2681 (intel_crtc
->config
->pipe_src_w
- 1));
2682 I915_WRITE(PRIMPOS(plane
), 0);
2683 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2686 switch (fb
->pixel_format
) {
2688 dspcntr
|= DISPPLANE_8BPP
;
2690 case DRM_FORMAT_XRGB1555
:
2691 dspcntr
|= DISPPLANE_BGRX555
;
2693 case DRM_FORMAT_RGB565
:
2694 dspcntr
|= DISPPLANE_BGRX565
;
2696 case DRM_FORMAT_XRGB8888
:
2697 dspcntr
|= DISPPLANE_BGRX888
;
2699 case DRM_FORMAT_XBGR8888
:
2700 dspcntr
|= DISPPLANE_RGBX888
;
2702 case DRM_FORMAT_XRGB2101010
:
2703 dspcntr
|= DISPPLANE_BGRX101010
;
2705 case DRM_FORMAT_XBGR2101010
:
2706 dspcntr
|= DISPPLANE_RGBX101010
;
2712 if (INTEL_INFO(dev
)->gen
>= 4 &&
2713 obj
->tiling_mode
!= I915_TILING_NONE
)
2714 dspcntr
|= DISPPLANE_TILED
;
2717 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2719 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2721 if (INTEL_INFO(dev
)->gen
>= 4) {
2722 intel_crtc
->dspaddr_offset
=
2723 intel_gen4_compute_page_offset(dev_priv
,
2724 &x
, &y
, obj
->tiling_mode
,
2727 linear_offset
-= intel_crtc
->dspaddr_offset
;
2729 intel_crtc
->dspaddr_offset
= linear_offset
;
2732 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2733 dspcntr
|= DISPPLANE_ROTATE_180
;
2735 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2736 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2738 /* Finding the last pixel of the last line of the display
2739 data and adding to linear_offset*/
2741 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2742 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2745 intel_crtc
->adjusted_x
= x
;
2746 intel_crtc
->adjusted_y
= y
;
2748 I915_WRITE(reg
, dspcntr
);
2750 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2751 if (INTEL_INFO(dev
)->gen
>= 4) {
2752 I915_WRITE(DSPSURF(plane
),
2753 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2754 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2755 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2757 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2761 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2762 struct drm_framebuffer
*fb
,
2765 struct drm_device
*dev
= crtc
->dev
;
2766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2767 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2768 struct drm_plane
*primary
= crtc
->primary
;
2769 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2770 struct drm_i915_gem_object
*obj
;
2771 int plane
= intel_crtc
->plane
;
2772 unsigned long linear_offset
;
2774 u32 reg
= DSPCNTR(plane
);
2777 if (!visible
|| !fb
) {
2779 I915_WRITE(DSPSURF(plane
), 0);
2784 obj
= intel_fb_obj(fb
);
2785 if (WARN_ON(obj
== NULL
))
2788 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2790 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2792 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2794 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2795 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2797 switch (fb
->pixel_format
) {
2799 dspcntr
|= DISPPLANE_8BPP
;
2801 case DRM_FORMAT_RGB565
:
2802 dspcntr
|= DISPPLANE_BGRX565
;
2804 case DRM_FORMAT_XRGB8888
:
2805 dspcntr
|= DISPPLANE_BGRX888
;
2807 case DRM_FORMAT_XBGR8888
:
2808 dspcntr
|= DISPPLANE_RGBX888
;
2810 case DRM_FORMAT_XRGB2101010
:
2811 dspcntr
|= DISPPLANE_BGRX101010
;
2813 case DRM_FORMAT_XBGR2101010
:
2814 dspcntr
|= DISPPLANE_RGBX101010
;
2820 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2821 dspcntr
|= DISPPLANE_TILED
;
2823 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2824 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2826 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2827 intel_crtc
->dspaddr_offset
=
2828 intel_gen4_compute_page_offset(dev_priv
,
2829 &x
, &y
, obj
->tiling_mode
,
2832 linear_offset
-= intel_crtc
->dspaddr_offset
;
2833 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2834 dspcntr
|= DISPPLANE_ROTATE_180
;
2836 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2837 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2838 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2840 /* Finding the last pixel of the last line of the display
2841 data and adding to linear_offset*/
2843 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2844 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2848 intel_crtc
->adjusted_x
= x
;
2849 intel_crtc
->adjusted_y
= y
;
2851 I915_WRITE(reg
, dspcntr
);
2853 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2854 I915_WRITE(DSPSURF(plane
),
2855 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2856 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2857 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2859 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2860 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2865 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
2866 uint32_t pixel_format
)
2868 u32 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2871 * The stride is either expressed as a multiple of 64 bytes
2872 * chunks for linear buffers or in number of tiles for tiled
2875 switch (fb_modifier
) {
2876 case DRM_FORMAT_MOD_NONE
:
2878 case I915_FORMAT_MOD_X_TILED
:
2879 if (INTEL_INFO(dev
)->gen
== 2)
2882 case I915_FORMAT_MOD_Y_TILED
:
2883 /* No need to check for old gens and Y tiling since this is
2884 * about the display engine and those will be blocked before
2888 case I915_FORMAT_MOD_Yf_TILED
:
2889 if (bits_per_pixel
== 8)
2894 MISSING_CASE(fb_modifier
);
2899 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2900 struct drm_i915_gem_object
*obj
,
2903 const struct i915_ggtt_view
*view
= &i915_ggtt_view_normal
;
2904 struct i915_vma
*vma
;
2905 unsigned char *offset
;
2907 if (intel_rotation_90_or_270(intel_plane
->base
.state
->rotation
))
2908 view
= &i915_ggtt_view_rotated
;
2910 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
2911 if (WARN(!vma
, "ggtt vma for display object not found! (view=%u)\n",
2915 offset
= (unsigned char *)vma
->node
.start
;
2918 offset
+= vma
->ggtt_view
.rotation_info
.uv_start_page
*
2922 return (unsigned long)offset
;
2925 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
2927 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2930 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
2931 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
2932 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
2936 * This function detaches (aka. unbinds) unused scalers in hardware
2938 static void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2940 struct intel_crtc_scaler_state
*scaler_state
;
2943 scaler_state
= &intel_crtc
->config
->scaler_state
;
2945 /* loop through and disable scalers that aren't in use */
2946 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2947 if (!scaler_state
->scalers
[i
].in_use
)
2948 skl_detach_scaler(intel_crtc
, i
);
2952 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2954 switch (pixel_format
) {
2956 return PLANE_CTL_FORMAT_INDEXED
;
2957 case DRM_FORMAT_RGB565
:
2958 return PLANE_CTL_FORMAT_RGB_565
;
2959 case DRM_FORMAT_XBGR8888
:
2960 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2961 case DRM_FORMAT_XRGB8888
:
2962 return PLANE_CTL_FORMAT_XRGB_8888
;
2964 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2965 * to be already pre-multiplied. We need to add a knob (or a different
2966 * DRM_FORMAT) for user-space to configure that.
2968 case DRM_FORMAT_ABGR8888
:
2969 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
2970 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2971 case DRM_FORMAT_ARGB8888
:
2972 return PLANE_CTL_FORMAT_XRGB_8888
|
2973 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2974 case DRM_FORMAT_XRGB2101010
:
2975 return PLANE_CTL_FORMAT_XRGB_2101010
;
2976 case DRM_FORMAT_XBGR2101010
:
2977 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
2978 case DRM_FORMAT_YUYV
:
2979 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
2980 case DRM_FORMAT_YVYU
:
2981 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
2982 case DRM_FORMAT_UYVY
:
2983 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
2984 case DRM_FORMAT_VYUY
:
2985 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
2987 MISSING_CASE(pixel_format
);
2993 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
2995 switch (fb_modifier
) {
2996 case DRM_FORMAT_MOD_NONE
:
2998 case I915_FORMAT_MOD_X_TILED
:
2999 return PLANE_CTL_TILED_X
;
3000 case I915_FORMAT_MOD_Y_TILED
:
3001 return PLANE_CTL_TILED_Y
;
3002 case I915_FORMAT_MOD_Yf_TILED
:
3003 return PLANE_CTL_TILED_YF
;
3005 MISSING_CASE(fb_modifier
);
3011 u32
skl_plane_ctl_rotation(unsigned int rotation
)
3014 case BIT(DRM_ROTATE_0
):
3017 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3018 * while i915 HW rotation is clockwise, thats why this swapping.
3020 case BIT(DRM_ROTATE_90
):
3021 return PLANE_CTL_ROTATE_270
;
3022 case BIT(DRM_ROTATE_180
):
3023 return PLANE_CTL_ROTATE_180
;
3024 case BIT(DRM_ROTATE_270
):
3025 return PLANE_CTL_ROTATE_90
;
3027 MISSING_CASE(rotation
);
3033 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
3034 struct drm_framebuffer
*fb
,
3037 struct drm_device
*dev
= crtc
->dev
;
3038 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3039 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3040 struct drm_plane
*plane
= crtc
->primary
;
3041 bool visible
= to_intel_plane_state(plane
->state
)->visible
;
3042 struct drm_i915_gem_object
*obj
;
3043 int pipe
= intel_crtc
->pipe
;
3044 u32 plane_ctl
, stride_div
, stride
;
3045 u32 tile_height
, plane_offset
, plane_size
;
3046 unsigned int rotation
;
3047 int x_offset
, y_offset
;
3048 unsigned long surf_addr
;
3049 struct intel_crtc_state
*crtc_state
= intel_crtc
->config
;
3050 struct intel_plane_state
*plane_state
;
3051 int src_x
= 0, src_y
= 0, src_w
= 0, src_h
= 0;
3052 int dst_x
= 0, dst_y
= 0, dst_w
= 0, dst_h
= 0;
3055 plane_state
= to_intel_plane_state(plane
->state
);
3057 if (!visible
|| !fb
) {
3058 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3059 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3060 POSTING_READ(PLANE_CTL(pipe
, 0));
3064 plane_ctl
= PLANE_CTL_ENABLE
|
3065 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3066 PLANE_CTL_PIPE_CSC_ENABLE
;
3068 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3069 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3070 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3072 rotation
= plane
->state
->rotation
;
3073 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3075 obj
= intel_fb_obj(fb
);
3076 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
3078 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
, 0);
3081 * FIXME: intel_plane_state->src, dst aren't set when transitional
3082 * update_plane helpers are called from legacy paths.
3083 * Once full atomic crtc is available, below check can be avoided.
3085 if (drm_rect_width(&plane_state
->src
)) {
3086 scaler_id
= plane_state
->scaler_id
;
3087 src_x
= plane_state
->src
.x1
>> 16;
3088 src_y
= plane_state
->src
.y1
>> 16;
3089 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3090 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3091 dst_x
= plane_state
->dst
.x1
;
3092 dst_y
= plane_state
->dst
.y1
;
3093 dst_w
= drm_rect_width(&plane_state
->dst
);
3094 dst_h
= drm_rect_height(&plane_state
->dst
);
3096 WARN_ON(x
!= src_x
|| y
!= src_y
);
3098 src_w
= intel_crtc
->config
->pipe_src_w
;
3099 src_h
= intel_crtc
->config
->pipe_src_h
;
3102 if (intel_rotation_90_or_270(rotation
)) {
3103 /* stride = Surface height in tiles */
3104 tile_height
= intel_tile_height(dev
, fb
->pixel_format
,
3105 fb
->modifier
[0], 0);
3106 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3107 x_offset
= stride
* tile_height
- y
- src_h
;
3109 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3111 stride
= fb
->pitches
[0] / stride_div
;
3114 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3116 plane_offset
= y_offset
<< 16 | x_offset
;
3118 intel_crtc
->adjusted_x
= x_offset
;
3119 intel_crtc
->adjusted_y
= y_offset
;
3121 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3122 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3123 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3124 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3126 if (scaler_id
>= 0) {
3127 uint32_t ps_ctrl
= 0;
3129 WARN_ON(!dst_w
|| !dst_h
);
3130 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3131 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3132 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3133 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3134 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3135 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3136 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3138 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3141 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3143 POSTING_READ(PLANE_SURF(pipe
, 0));
3146 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3148 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3149 int x
, int y
, enum mode_set_atomic state
)
3151 struct drm_device
*dev
= crtc
->dev
;
3152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3154 if (dev_priv
->fbc
.disable_fbc
)
3155 dev_priv
->fbc
.disable_fbc(dev_priv
);
3157 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
3162 static void intel_complete_page_flips(struct drm_device
*dev
)
3164 struct drm_crtc
*crtc
;
3166 for_each_crtc(dev
, crtc
) {
3167 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3168 enum plane plane
= intel_crtc
->plane
;
3170 intel_prepare_page_flip(dev
, plane
);
3171 intel_finish_page_flip_plane(dev
, plane
);
3175 static void intel_update_primary_planes(struct drm_device
*dev
)
3177 struct drm_crtc
*crtc
;
3179 for_each_crtc(dev
, crtc
) {
3180 struct intel_plane
*plane
= to_intel_plane(crtc
->primary
);
3181 struct intel_plane_state
*plane_state
;
3183 drm_modeset_lock_crtc(crtc
, &plane
->base
);
3185 plane_state
= to_intel_plane_state(plane
->base
.state
);
3187 if (plane_state
->base
.fb
)
3188 plane
->commit_plane(&plane
->base
, plane_state
);
3190 drm_modeset_unlock_crtc(crtc
);
3194 void intel_prepare_reset(struct drm_device
*dev
)
3196 /* no reset support for gen2 */
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
3204 drm_modeset_lock_all(dev
);
3206 * Disabling the crtcs gracefully seems nicer. Also the
3207 * g33 docs say we should at least disable all the planes.
3209 intel_display_suspend(dev
);
3212 void intel_finish_reset(struct drm_device
*dev
)
3214 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3217 * Flips in the rings will be nuked by the reset,
3218 * so complete all pending flips so that user space
3219 * will get its events and not get stuck.
3221 intel_complete_page_flips(dev
);
3223 /* no reset support for gen2 */
3227 /* reset doesn't touch the display */
3228 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3230 * Flips in the rings have been nuked by the reset,
3231 * so update the base address of all primary
3232 * planes to the the last fb to make sure we're
3233 * showing the correct fb after a reset.
3235 * FIXME: Atomic will make this obsolete since we won't schedule
3236 * CS-based flips (which might get lost in gpu resets) any more.
3238 intel_update_primary_planes(dev
);
3243 * The display has been reset as well,
3244 * so need a full re-initialization.
3246 intel_runtime_pm_disable_interrupts(dev_priv
);
3247 intel_runtime_pm_enable_interrupts(dev_priv
);
3249 intel_modeset_init_hw(dev
);
3251 spin_lock_irq(&dev_priv
->irq_lock
);
3252 if (dev_priv
->display
.hpd_irq_setup
)
3253 dev_priv
->display
.hpd_irq_setup(dev
);
3254 spin_unlock_irq(&dev_priv
->irq_lock
);
3256 intel_display_resume(dev
);
3258 intel_hpd_init(dev_priv
);
3260 drm_modeset_unlock_all(dev
);
3264 intel_finish_fb(struct drm_framebuffer
*old_fb
)
3266 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
3267 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3268 bool was_interruptible
= dev_priv
->mm
.interruptible
;
3271 /* Big Hammer, we also need to ensure that any pending
3272 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3273 * current scanout is retired before unpinning the old
3274 * framebuffer. Note that we rely on userspace rendering
3275 * into the buffer attached to the pipe they are waiting
3276 * on. If not, userspace generates a GPU hang with IPEHR
3277 * point to the MI_WAIT_FOR_EVENT.
3279 * This should only fail upon a hung GPU, in which case we
3280 * can safely continue.
3282 dev_priv
->mm
.interruptible
= false;
3283 ret
= i915_gem_object_wait_rendering(obj
, true);
3284 dev_priv
->mm
.interruptible
= was_interruptible
;
3289 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3291 struct drm_device
*dev
= crtc
->dev
;
3292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3293 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3296 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3297 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3300 spin_lock_irq(&dev
->event_lock
);
3301 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3302 spin_unlock_irq(&dev
->event_lock
);
3307 static void intel_update_pipe_config(struct intel_crtc
*crtc
,
3308 struct intel_crtc_state
*old_crtc_state
)
3310 struct drm_device
*dev
= crtc
->base
.dev
;
3311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3312 struct intel_crtc_state
*pipe_config
=
3313 to_intel_crtc_state(crtc
->base
.state
);
3315 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3316 crtc
->base
.mode
= crtc
->base
.state
->mode
;
3318 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3319 old_crtc_state
->pipe_src_w
, old_crtc_state
->pipe_src_h
,
3320 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
3323 intel_set_pipe_csc(&crtc
->base
);
3326 * Update pipe size and adjust fitter if needed: the reason for this is
3327 * that in compute_mode_changes we check the native mode (not the pfit
3328 * mode) to see if we can flip rather than do a full mode set. In the
3329 * fastboot case, we'll flip, but if we don't update the pipesrc and
3330 * pfit state, we'll end up with a big fb scanned out into the wrong
3334 I915_WRITE(PIPESRC(crtc
->pipe
),
3335 ((pipe_config
->pipe_src_w
- 1) << 16) |
3336 (pipe_config
->pipe_src_h
- 1));
3338 /* on skylake this is done by detaching scalers */
3339 if (INTEL_INFO(dev
)->gen
>= 9) {
3340 skl_detach_scalers(crtc
);
3342 if (pipe_config
->pch_pfit
.enabled
)
3343 skylake_pfit_enable(crtc
);
3344 } else if (HAS_PCH_SPLIT(dev
)) {
3345 if (pipe_config
->pch_pfit
.enabled
)
3346 ironlake_pfit_enable(crtc
);
3347 else if (old_crtc_state
->pch_pfit
.enabled
)
3348 ironlake_pfit_disable(crtc
, true);
3352 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3354 struct drm_device
*dev
= crtc
->dev
;
3355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3356 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3357 int pipe
= intel_crtc
->pipe
;
3360 /* enable normal train */
3361 reg
= FDI_TX_CTL(pipe
);
3362 temp
= I915_READ(reg
);
3363 if (IS_IVYBRIDGE(dev
)) {
3364 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3365 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3367 temp
&= ~FDI_LINK_TRAIN_NONE
;
3368 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3370 I915_WRITE(reg
, temp
);
3372 reg
= FDI_RX_CTL(pipe
);
3373 temp
= I915_READ(reg
);
3374 if (HAS_PCH_CPT(dev
)) {
3375 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3376 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3378 temp
&= ~FDI_LINK_TRAIN_NONE
;
3379 temp
|= FDI_LINK_TRAIN_NONE
;
3381 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3383 /* wait one idle pattern time */
3387 /* IVB wants error correction enabled */
3388 if (IS_IVYBRIDGE(dev
))
3389 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3390 FDI_FE_ERRC_ENABLE
);
3393 /* The FDI link training functions for ILK/Ibexpeak. */
3394 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3396 struct drm_device
*dev
= crtc
->dev
;
3397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3398 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3399 int pipe
= intel_crtc
->pipe
;
3400 u32 reg
, temp
, tries
;
3402 /* FDI needs bits from pipe first */
3403 assert_pipe_enabled(dev_priv
, pipe
);
3405 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3407 reg
= FDI_RX_IMR(pipe
);
3408 temp
= I915_READ(reg
);
3409 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3410 temp
&= ~FDI_RX_BIT_LOCK
;
3411 I915_WRITE(reg
, temp
);
3415 /* enable CPU FDI TX and PCH FDI RX */
3416 reg
= FDI_TX_CTL(pipe
);
3417 temp
= I915_READ(reg
);
3418 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3419 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3420 temp
&= ~FDI_LINK_TRAIN_NONE
;
3421 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3422 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3424 reg
= FDI_RX_CTL(pipe
);
3425 temp
= I915_READ(reg
);
3426 temp
&= ~FDI_LINK_TRAIN_NONE
;
3427 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3428 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3433 /* Ironlake workaround, enable clock pointer after FDI enable*/
3434 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3435 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3436 FDI_RX_PHASE_SYNC_POINTER_EN
);
3438 reg
= FDI_RX_IIR(pipe
);
3439 for (tries
= 0; tries
< 5; tries
++) {
3440 temp
= I915_READ(reg
);
3441 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3443 if ((temp
& FDI_RX_BIT_LOCK
)) {
3444 DRM_DEBUG_KMS("FDI train 1 done.\n");
3445 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3450 DRM_ERROR("FDI train 1 fail!\n");
3453 reg
= FDI_TX_CTL(pipe
);
3454 temp
= I915_READ(reg
);
3455 temp
&= ~FDI_LINK_TRAIN_NONE
;
3456 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3457 I915_WRITE(reg
, temp
);
3459 reg
= FDI_RX_CTL(pipe
);
3460 temp
= I915_READ(reg
);
3461 temp
&= ~FDI_LINK_TRAIN_NONE
;
3462 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3463 I915_WRITE(reg
, temp
);
3468 reg
= FDI_RX_IIR(pipe
);
3469 for (tries
= 0; tries
< 5; tries
++) {
3470 temp
= I915_READ(reg
);
3471 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3473 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3474 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3475 DRM_DEBUG_KMS("FDI train 2 done.\n");
3480 DRM_ERROR("FDI train 2 fail!\n");
3482 DRM_DEBUG_KMS("FDI train done\n");
3486 static const int snb_b_fdi_train_param
[] = {
3487 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3488 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3489 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3490 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3493 /* The FDI link training functions for SNB/Cougarpoint. */
3494 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3496 struct drm_device
*dev
= crtc
->dev
;
3497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3498 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3499 int pipe
= intel_crtc
->pipe
;
3500 u32 reg
, temp
, i
, retry
;
3502 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3504 reg
= FDI_RX_IMR(pipe
);
3505 temp
= I915_READ(reg
);
3506 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3507 temp
&= ~FDI_RX_BIT_LOCK
;
3508 I915_WRITE(reg
, temp
);
3513 /* enable CPU FDI TX and PCH FDI RX */
3514 reg
= FDI_TX_CTL(pipe
);
3515 temp
= I915_READ(reg
);
3516 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3517 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3518 temp
&= ~FDI_LINK_TRAIN_NONE
;
3519 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3520 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3522 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3523 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3525 I915_WRITE(FDI_RX_MISC(pipe
),
3526 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3528 reg
= FDI_RX_CTL(pipe
);
3529 temp
= I915_READ(reg
);
3530 if (HAS_PCH_CPT(dev
)) {
3531 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3532 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3534 temp
&= ~FDI_LINK_TRAIN_NONE
;
3535 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3537 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3542 for (i
= 0; i
< 4; i
++) {
3543 reg
= FDI_TX_CTL(pipe
);
3544 temp
= I915_READ(reg
);
3545 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3546 temp
|= snb_b_fdi_train_param
[i
];
3547 I915_WRITE(reg
, temp
);
3552 for (retry
= 0; retry
< 5; retry
++) {
3553 reg
= FDI_RX_IIR(pipe
);
3554 temp
= I915_READ(reg
);
3555 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3556 if (temp
& FDI_RX_BIT_LOCK
) {
3557 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3558 DRM_DEBUG_KMS("FDI train 1 done.\n");
3567 DRM_ERROR("FDI train 1 fail!\n");
3570 reg
= FDI_TX_CTL(pipe
);
3571 temp
= I915_READ(reg
);
3572 temp
&= ~FDI_LINK_TRAIN_NONE
;
3573 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3575 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3577 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3579 I915_WRITE(reg
, temp
);
3581 reg
= FDI_RX_CTL(pipe
);
3582 temp
= I915_READ(reg
);
3583 if (HAS_PCH_CPT(dev
)) {
3584 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3585 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3587 temp
&= ~FDI_LINK_TRAIN_NONE
;
3588 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3590 I915_WRITE(reg
, temp
);
3595 for (i
= 0; i
< 4; i
++) {
3596 reg
= FDI_TX_CTL(pipe
);
3597 temp
= I915_READ(reg
);
3598 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3599 temp
|= snb_b_fdi_train_param
[i
];
3600 I915_WRITE(reg
, temp
);
3605 for (retry
= 0; retry
< 5; retry
++) {
3606 reg
= FDI_RX_IIR(pipe
);
3607 temp
= I915_READ(reg
);
3608 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3609 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3610 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3611 DRM_DEBUG_KMS("FDI train 2 done.\n");
3620 DRM_ERROR("FDI train 2 fail!\n");
3622 DRM_DEBUG_KMS("FDI train done.\n");
3625 /* Manual link training for Ivy Bridge A0 parts */
3626 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3628 struct drm_device
*dev
= crtc
->dev
;
3629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3630 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3631 int pipe
= intel_crtc
->pipe
;
3632 u32 reg
, temp
, i
, j
;
3634 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3636 reg
= FDI_RX_IMR(pipe
);
3637 temp
= I915_READ(reg
);
3638 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3639 temp
&= ~FDI_RX_BIT_LOCK
;
3640 I915_WRITE(reg
, temp
);
3645 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3646 I915_READ(FDI_RX_IIR(pipe
)));
3648 /* Try each vswing and preemphasis setting twice before moving on */
3649 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3650 /* disable first in case we need to retry */
3651 reg
= FDI_TX_CTL(pipe
);
3652 temp
= I915_READ(reg
);
3653 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3654 temp
&= ~FDI_TX_ENABLE
;
3655 I915_WRITE(reg
, temp
);
3657 reg
= FDI_RX_CTL(pipe
);
3658 temp
= I915_READ(reg
);
3659 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3660 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3661 temp
&= ~FDI_RX_ENABLE
;
3662 I915_WRITE(reg
, temp
);
3664 /* enable CPU FDI TX and PCH FDI RX */
3665 reg
= FDI_TX_CTL(pipe
);
3666 temp
= I915_READ(reg
);
3667 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3668 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3669 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3670 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3671 temp
|= snb_b_fdi_train_param
[j
/2];
3672 temp
|= FDI_COMPOSITE_SYNC
;
3673 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3675 I915_WRITE(FDI_RX_MISC(pipe
),
3676 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3678 reg
= FDI_RX_CTL(pipe
);
3679 temp
= I915_READ(reg
);
3680 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3681 temp
|= FDI_COMPOSITE_SYNC
;
3682 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3685 udelay(1); /* should be 0.5us */
3687 for (i
= 0; i
< 4; i
++) {
3688 reg
= FDI_RX_IIR(pipe
);
3689 temp
= I915_READ(reg
);
3690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3692 if (temp
& FDI_RX_BIT_LOCK
||
3693 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3694 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3699 udelay(1); /* should be 0.5us */
3702 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3707 reg
= FDI_TX_CTL(pipe
);
3708 temp
= I915_READ(reg
);
3709 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3710 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3711 I915_WRITE(reg
, temp
);
3713 reg
= FDI_RX_CTL(pipe
);
3714 temp
= I915_READ(reg
);
3715 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3716 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3717 I915_WRITE(reg
, temp
);
3720 udelay(2); /* should be 1.5us */
3722 for (i
= 0; i
< 4; i
++) {
3723 reg
= FDI_RX_IIR(pipe
);
3724 temp
= I915_READ(reg
);
3725 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3727 if (temp
& FDI_RX_SYMBOL_LOCK
||
3728 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3729 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3730 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3734 udelay(2); /* should be 1.5us */
3737 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3741 DRM_DEBUG_KMS("FDI train done.\n");
3744 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3746 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3748 int pipe
= intel_crtc
->pipe
;
3752 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3753 reg
= FDI_RX_CTL(pipe
);
3754 temp
= I915_READ(reg
);
3755 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3756 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3757 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3758 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3763 /* Switch from Rawclk to PCDclk */
3764 temp
= I915_READ(reg
);
3765 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3770 /* Enable CPU FDI TX PLL, always on for Ironlake */
3771 reg
= FDI_TX_CTL(pipe
);
3772 temp
= I915_READ(reg
);
3773 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3774 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3781 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3783 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3785 int pipe
= intel_crtc
->pipe
;
3788 /* Switch from PCDclk to Rawclk */
3789 reg
= FDI_RX_CTL(pipe
);
3790 temp
= I915_READ(reg
);
3791 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3793 /* Disable CPU FDI TX PLL */
3794 reg
= FDI_TX_CTL(pipe
);
3795 temp
= I915_READ(reg
);
3796 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3801 reg
= FDI_RX_CTL(pipe
);
3802 temp
= I915_READ(reg
);
3803 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3805 /* Wait for the clocks to turn off. */
3810 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3812 struct drm_device
*dev
= crtc
->dev
;
3813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3814 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3815 int pipe
= intel_crtc
->pipe
;
3818 /* disable CPU FDI tx and PCH FDI rx */
3819 reg
= FDI_TX_CTL(pipe
);
3820 temp
= I915_READ(reg
);
3821 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3824 reg
= FDI_RX_CTL(pipe
);
3825 temp
= I915_READ(reg
);
3826 temp
&= ~(0x7 << 16);
3827 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3828 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3833 /* Ironlake workaround, disable clock pointer after downing FDI */
3834 if (HAS_PCH_IBX(dev
))
3835 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3837 /* still set train pattern 1 */
3838 reg
= FDI_TX_CTL(pipe
);
3839 temp
= I915_READ(reg
);
3840 temp
&= ~FDI_LINK_TRAIN_NONE
;
3841 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3842 I915_WRITE(reg
, temp
);
3844 reg
= FDI_RX_CTL(pipe
);
3845 temp
= I915_READ(reg
);
3846 if (HAS_PCH_CPT(dev
)) {
3847 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3848 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3850 temp
&= ~FDI_LINK_TRAIN_NONE
;
3851 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3853 /* BPC in FDI rx is consistent with that in PIPECONF */
3854 temp
&= ~(0x07 << 16);
3855 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3856 I915_WRITE(reg
, temp
);
3862 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3864 struct intel_crtc
*crtc
;
3866 /* Note that we don't need to be called with mode_config.lock here
3867 * as our list of CRTC objects is static for the lifetime of the
3868 * device and so cannot disappear as we iterate. Similarly, we can
3869 * happily treat the predicates as racy, atomic checks as userspace
3870 * cannot claim and pin a new fb without at least acquring the
3871 * struct_mutex and so serialising with us.
3873 for_each_intel_crtc(dev
, crtc
) {
3874 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3877 if (crtc
->unpin_work
)
3878 intel_wait_for_vblank(dev
, crtc
->pipe
);
3886 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3888 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3889 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3891 /* ensure that the unpin work is consistent wrt ->pending. */
3893 intel_crtc
->unpin_work
= NULL
;
3896 drm_send_vblank_event(intel_crtc
->base
.dev
,
3900 drm_crtc_vblank_put(&intel_crtc
->base
);
3902 wake_up_all(&dev_priv
->pending_flip_queue
);
3903 queue_work(dev_priv
->wq
, &work
->work
);
3905 trace_i915_flip_complete(intel_crtc
->plane
,
3906 work
->pending_flip_obj
);
3909 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3911 struct drm_device
*dev
= crtc
->dev
;
3912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3914 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3915 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3916 !intel_crtc_has_pending_flip(crtc
),
3918 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3920 spin_lock_irq(&dev
->event_lock
);
3921 if (intel_crtc
->unpin_work
) {
3922 WARN_ONCE(1, "Removing stuck page flip\n");
3923 page_flip_completed(intel_crtc
);
3925 spin_unlock_irq(&dev
->event_lock
);
3928 if (crtc
->primary
->fb
) {
3929 mutex_lock(&dev
->struct_mutex
);
3930 intel_finish_fb(crtc
->primary
->fb
);
3931 mutex_unlock(&dev
->struct_mutex
);
3935 /* Program iCLKIP clock to the desired frequency */
3936 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3938 struct drm_device
*dev
= crtc
->dev
;
3939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3940 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3941 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3944 mutex_lock(&dev_priv
->sb_lock
);
3946 /* It is necessary to ungate the pixclk gate prior to programming
3947 * the divisors, and gate it back when it is done.
3949 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3951 /* Disable SSCCTL */
3952 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3953 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3957 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3958 if (clock
== 20000) {
3963 /* The iCLK virtual clock root frequency is in MHz,
3964 * but the adjusted_mode->crtc_clock in in KHz. To get the
3965 * divisors, it is necessary to divide one by another, so we
3966 * convert the virtual clock precision to KHz here for higher
3969 u32 iclk_virtual_root_freq
= 172800 * 1000;
3970 u32 iclk_pi_range
= 64;
3971 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3973 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3974 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3975 pi_value
= desired_divisor
% iclk_pi_range
;
3978 divsel
= msb_divisor_value
- 2;
3979 phaseinc
= pi_value
;
3982 /* This should not happen with any sane values */
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3984 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3985 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3986 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3988 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3995 /* Program SSCDIVINTPHASE6 */
3996 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3997 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3998 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3999 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
4000 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
4001 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4002 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4003 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4005 /* Program SSCAUXDIV */
4006 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4007 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4008 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4009 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4011 /* Enable modulator and associated divider */
4012 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4013 temp
&= ~SBI_SSCCTL_DISABLE
;
4014 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4016 /* Wait for initialization time */
4019 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4021 mutex_unlock(&dev_priv
->sb_lock
);
4024 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
4025 enum pipe pch_transcoder
)
4027 struct drm_device
*dev
= crtc
->base
.dev
;
4028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4029 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4031 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4032 I915_READ(HTOTAL(cpu_transcoder
)));
4033 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4034 I915_READ(HBLANK(cpu_transcoder
)));
4035 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4036 I915_READ(HSYNC(cpu_transcoder
)));
4038 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4039 I915_READ(VTOTAL(cpu_transcoder
)));
4040 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4041 I915_READ(VBLANK(cpu_transcoder
)));
4042 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4043 I915_READ(VSYNC(cpu_transcoder
)));
4044 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4045 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4048 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4053 temp
= I915_READ(SOUTH_CHICKEN1
);
4054 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4057 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4058 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4060 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4062 temp
|= FDI_BC_BIFURCATION_SELECT
;
4064 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4065 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4066 POSTING_READ(SOUTH_CHICKEN1
);
4069 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4071 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4073 switch (intel_crtc
->pipe
) {
4077 if (intel_crtc
->config
->fdi_lanes
> 2)
4078 cpt_set_fdi_bc_bifurcation(dev
, false);
4080 cpt_set_fdi_bc_bifurcation(dev
, true);
4084 cpt_set_fdi_bc_bifurcation(dev
, true);
4093 * Enable PCH resources required for PCH ports:
4095 * - FDI training & RX/TX
4096 * - update transcoder timings
4097 * - DP transcoding bits
4100 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4102 struct drm_device
*dev
= crtc
->dev
;
4103 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4104 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4105 int pipe
= intel_crtc
->pipe
;
4108 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4110 if (IS_IVYBRIDGE(dev
))
4111 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4113 /* Write the TU size bits before fdi link training, so that error
4114 * detection works. */
4115 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4116 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4118 /* For PCH output, training FDI link */
4119 dev_priv
->display
.fdi_link_train(crtc
);
4121 /* We need to program the right clock selection before writing the pixel
4122 * mutliplier into the DPLL. */
4123 if (HAS_PCH_CPT(dev
)) {
4126 temp
= I915_READ(PCH_DPLL_SEL
);
4127 temp
|= TRANS_DPLL_ENABLE(pipe
);
4128 sel
= TRANS_DPLLB_SEL(pipe
);
4129 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
4133 I915_WRITE(PCH_DPLL_SEL
, temp
);
4136 /* XXX: pch pll's can be enabled any time before we enable the PCH
4137 * transcoder, and we actually should do this to not upset any PCH
4138 * transcoder that already use the clock when we share it.
4140 * Note that enable_shared_dpll tries to do the right thing, but
4141 * get_shared_dpll unconditionally resets the pll - we need that to have
4142 * the right LVDS enable sequence. */
4143 intel_enable_shared_dpll(intel_crtc
);
4145 /* set transcoder timing, panel must allow it */
4146 assert_panel_unlocked(dev_priv
, pipe
);
4147 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4149 intel_fdi_normal_train(crtc
);
4151 /* For PCH DP, enable TRANS_DP_CTL */
4152 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4153 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4154 reg
= TRANS_DP_CTL(pipe
);
4155 temp
= I915_READ(reg
);
4156 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4157 TRANS_DP_SYNC_MASK
|
4159 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4160 temp
|= bpc
<< 9; /* same format but at 11:9 */
4162 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
4163 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4164 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
4165 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4167 switch (intel_trans_dp_port_sel(crtc
)) {
4169 temp
|= TRANS_DP_PORT_SEL_B
;
4172 temp
|= TRANS_DP_PORT_SEL_C
;
4175 temp
|= TRANS_DP_PORT_SEL_D
;
4181 I915_WRITE(reg
, temp
);
4184 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4187 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4189 struct drm_device
*dev
= crtc
->dev
;
4190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4191 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4192 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4194 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4196 lpt_program_iclkip(crtc
);
4198 /* Set transcoder timing. */
4199 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4201 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4204 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
4205 struct intel_crtc_state
*crtc_state
)
4207 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
4208 struct intel_shared_dpll
*pll
;
4209 struct intel_shared_dpll_config
*shared_dpll
;
4210 enum intel_dpll_id i
;
4212 shared_dpll
= intel_atomic_get_shared_dpll_state(crtc_state
->base
.state
);
4214 if (HAS_PCH_IBX(dev_priv
->dev
)) {
4215 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4216 i
= (enum intel_dpll_id
) crtc
->pipe
;
4217 pll
= &dev_priv
->shared_dplls
[i
];
4219 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4220 crtc
->base
.base
.id
, pll
->name
);
4222 WARN_ON(shared_dpll
[i
].crtc_mask
);
4227 if (IS_BROXTON(dev_priv
->dev
)) {
4228 /* PLL is attached to port in bxt */
4229 struct intel_encoder
*encoder
;
4230 struct intel_digital_port
*intel_dig_port
;
4232 encoder
= intel_ddi_get_crtc_new_encoder(crtc_state
);
4233 if (WARN_ON(!encoder
))
4236 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
4237 /* 1:1 mapping between ports and PLLs */
4238 i
= (enum intel_dpll_id
)intel_dig_port
->port
;
4239 pll
= &dev_priv
->shared_dplls
[i
];
4240 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4241 crtc
->base
.base
.id
, pll
->name
);
4242 WARN_ON(shared_dpll
[i
].crtc_mask
);
4247 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4248 pll
= &dev_priv
->shared_dplls
[i
];
4250 /* Only want to check enabled timings first */
4251 if (shared_dpll
[i
].crtc_mask
== 0)
4254 if (memcmp(&crtc_state
->dpll_hw_state
,
4255 &shared_dpll
[i
].hw_state
,
4256 sizeof(crtc_state
->dpll_hw_state
)) == 0) {
4257 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4258 crtc
->base
.base
.id
, pll
->name
,
4259 shared_dpll
[i
].crtc_mask
,
4265 /* Ok no matching timings, maybe there's a free one? */
4266 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4267 pll
= &dev_priv
->shared_dplls
[i
];
4268 if (shared_dpll
[i
].crtc_mask
== 0) {
4269 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4270 crtc
->base
.base
.id
, pll
->name
);
4278 if (shared_dpll
[i
].crtc_mask
== 0)
4279 shared_dpll
[i
].hw_state
=
4280 crtc_state
->dpll_hw_state
;
4282 crtc_state
->shared_dpll
= i
;
4283 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
4284 pipe_name(crtc
->pipe
));
4286 shared_dpll
[i
].crtc_mask
|= 1 << crtc
->pipe
;
4291 static void intel_shared_dpll_commit(struct drm_atomic_state
*state
)
4293 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
4294 struct intel_shared_dpll_config
*shared_dpll
;
4295 struct intel_shared_dpll
*pll
;
4296 enum intel_dpll_id i
;
4298 if (!to_intel_atomic_state(state
)->dpll_set
)
4301 shared_dpll
= to_intel_atomic_state(state
)->shared_dpll
;
4302 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4303 pll
= &dev_priv
->shared_dplls
[i
];
4304 pll
->config
= shared_dpll
[i
];
4308 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4311 int dslreg
= PIPEDSL(pipe
);
4314 temp
= I915_READ(dslreg
);
4316 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4317 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4318 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4323 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
4324 unsigned scaler_user
, int *scaler_id
, unsigned int rotation
,
4325 int src_w
, int src_h
, int dst_w
, int dst_h
)
4327 struct intel_crtc_scaler_state
*scaler_state
=
4328 &crtc_state
->scaler_state
;
4329 struct intel_crtc
*intel_crtc
=
4330 to_intel_crtc(crtc_state
->base
.crtc
);
4333 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4334 (src_h
!= dst_w
|| src_w
!= dst_h
):
4335 (src_w
!= dst_w
|| src_h
!= dst_h
);
4338 * if plane is being disabled or scaler is no more required or force detach
4339 * - free scaler binded to this plane/crtc
4340 * - in order to do this, update crtc->scaler_usage
4342 * Here scaler state in crtc_state is set free so that
4343 * scaler can be assigned to other user. Actual register
4344 * update to free the scaler is done in plane/panel-fit programming.
4345 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4347 if (force_detach
|| !need_scaling
) {
4348 if (*scaler_id
>= 0) {
4349 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
4350 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4352 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4353 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4354 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
4355 scaler_state
->scaler_users
);
4362 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4363 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4365 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4366 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4367 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4368 "size is out of scaler range\n",
4369 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
4373 /* mark this plane as a scaler user in crtc_state */
4374 scaler_state
->scaler_users
|= (1 << scaler_user
);
4375 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4376 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4377 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
4378 scaler_state
->scaler_users
);
4384 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4386 * @state: crtc's scaler state
4389 * 0 - scaler_usage updated successfully
4390 * error - requested scaling cannot be supported or other error condition
4392 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
4394 struct intel_crtc
*intel_crtc
= to_intel_crtc(state
->base
.crtc
);
4395 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
4397 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4398 intel_crtc
->base
.base
.id
, intel_crtc
->pipe
, SKL_CRTC_INDEX
);
4400 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
4401 &state
->scaler_state
.scaler_id
, DRM_ROTATE_0
,
4402 state
->pipe_src_w
, state
->pipe_src_h
,
4403 adjusted_mode
->crtc_hdisplay
, adjusted_mode
->crtc_vdisplay
);
4407 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4409 * @state: crtc's scaler state
4410 * @plane_state: atomic plane state to update
4413 * 0 - scaler_usage updated successfully
4414 * error - requested scaling cannot be supported or other error condition
4416 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
4417 struct intel_plane_state
*plane_state
)
4420 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4421 struct intel_plane
*intel_plane
=
4422 to_intel_plane(plane_state
->base
.plane
);
4423 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4426 bool force_detach
= !fb
|| !plane_state
->visible
;
4428 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4429 intel_plane
->base
.base
.id
, intel_crtc
->pipe
,
4430 drm_plane_index(&intel_plane
->base
));
4432 ret
= skl_update_scaler(crtc_state
, force_detach
,
4433 drm_plane_index(&intel_plane
->base
),
4434 &plane_state
->scaler_id
,
4435 plane_state
->base
.rotation
,
4436 drm_rect_width(&plane_state
->src
) >> 16,
4437 drm_rect_height(&plane_state
->src
) >> 16,
4438 drm_rect_width(&plane_state
->dst
),
4439 drm_rect_height(&plane_state
->dst
));
4441 if (ret
|| plane_state
->scaler_id
< 0)
4444 /* check colorkey */
4445 if (plane_state
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4446 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4447 intel_plane
->base
.base
.id
);
4451 /* Check src format */
4452 switch (fb
->pixel_format
) {
4453 case DRM_FORMAT_RGB565
:
4454 case DRM_FORMAT_XBGR8888
:
4455 case DRM_FORMAT_XRGB8888
:
4456 case DRM_FORMAT_ABGR8888
:
4457 case DRM_FORMAT_ARGB8888
:
4458 case DRM_FORMAT_XRGB2101010
:
4459 case DRM_FORMAT_XBGR2101010
:
4460 case DRM_FORMAT_YUYV
:
4461 case DRM_FORMAT_YVYU
:
4462 case DRM_FORMAT_UYVY
:
4463 case DRM_FORMAT_VYUY
:
4466 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4467 intel_plane
->base
.base
.id
, fb
->base
.id
, fb
->pixel_format
);
4474 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
4478 for (i
= 0; i
< crtc
->num_scalers
; i
++)
4479 skl_detach_scaler(crtc
, i
);
4482 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4484 struct drm_device
*dev
= crtc
->base
.dev
;
4485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4486 int pipe
= crtc
->pipe
;
4487 struct intel_crtc_scaler_state
*scaler_state
=
4488 &crtc
->config
->scaler_state
;
4490 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4492 if (crtc
->config
->pch_pfit
.enabled
) {
4495 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4496 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4500 id
= scaler_state
->scaler_id
;
4501 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4502 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4503 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4504 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4506 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4510 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4512 struct drm_device
*dev
= crtc
->base
.dev
;
4513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4514 int pipe
= crtc
->pipe
;
4516 if (crtc
->config
->pch_pfit
.enabled
) {
4517 /* Force use of hard-coded filter coefficients
4518 * as some pre-programmed values are broken,
4521 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4522 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4523 PF_PIPE_SEL_IVB(pipe
));
4525 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4526 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4527 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4531 void hsw_enable_ips(struct intel_crtc
*crtc
)
4533 struct drm_device
*dev
= crtc
->base
.dev
;
4534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4536 if (!crtc
->config
->ips_enabled
)
4539 /* We can only enable IPS after we enable a plane and wait for a vblank */
4540 intel_wait_for_vblank(dev
, crtc
->pipe
);
4542 assert_plane_enabled(dev_priv
, crtc
->plane
);
4543 if (IS_BROADWELL(dev
)) {
4544 mutex_lock(&dev_priv
->rps
.hw_lock
);
4545 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4546 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4547 /* Quoting Art Runyan: "its not safe to expect any particular
4548 * value in IPS_CTL bit 31 after enabling IPS through the
4549 * mailbox." Moreover, the mailbox may return a bogus state,
4550 * so we need to just enable it and continue on.
4553 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4554 /* The bit only becomes 1 in the next vblank, so this wait here
4555 * is essentially intel_wait_for_vblank. If we don't have this
4556 * and don't wait for vblanks until the end of crtc_enable, then
4557 * the HW state readout code will complain that the expected
4558 * IPS_CTL value is not the one we read. */
4559 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4560 DRM_ERROR("Timed out waiting for IPS enable\n");
4564 void hsw_disable_ips(struct intel_crtc
*crtc
)
4566 struct drm_device
*dev
= crtc
->base
.dev
;
4567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4569 if (!crtc
->config
->ips_enabled
)
4572 assert_plane_enabled(dev_priv
, crtc
->plane
);
4573 if (IS_BROADWELL(dev
)) {
4574 mutex_lock(&dev_priv
->rps
.hw_lock
);
4575 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4576 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4577 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4578 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4579 DRM_ERROR("Timed out waiting for IPS disable\n");
4581 I915_WRITE(IPS_CTL
, 0);
4582 POSTING_READ(IPS_CTL
);
4585 /* We need to wait for a vblank before we can disable the plane. */
4586 intel_wait_for_vblank(dev
, crtc
->pipe
);
4589 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4590 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4592 struct drm_device
*dev
= crtc
->dev
;
4593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4594 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4595 enum pipe pipe
= intel_crtc
->pipe
;
4596 int palreg
= PALETTE(pipe
);
4598 bool reenable_ips
= false;
4600 /* The clocks have to be on to load the palette. */
4601 if (!crtc
->state
->active
)
4604 if (HAS_GMCH_DISPLAY(dev_priv
->dev
)) {
4605 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4606 assert_dsi_pll_enabled(dev_priv
);
4608 assert_pll_enabled(dev_priv
, pipe
);
4611 /* use legacy palette for Ironlake */
4612 if (!HAS_GMCH_DISPLAY(dev
))
4613 palreg
= LGC_PALETTE(pipe
);
4615 /* Workaround : Do not read or write the pipe palette/gamma data while
4616 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4618 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4619 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4620 GAMMA_MODE_MODE_SPLIT
)) {
4621 hsw_disable_ips(intel_crtc
);
4622 reenable_ips
= true;
4625 for (i
= 0; i
< 256; i
++) {
4626 I915_WRITE(palreg
+ 4 * i
,
4627 (intel_crtc
->lut_r
[i
] << 16) |
4628 (intel_crtc
->lut_g
[i
] << 8) |
4629 intel_crtc
->lut_b
[i
]);
4633 hsw_enable_ips(intel_crtc
);
4636 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4638 if (intel_crtc
->overlay
) {
4639 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4642 mutex_lock(&dev
->struct_mutex
);
4643 dev_priv
->mm
.interruptible
= false;
4644 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4645 dev_priv
->mm
.interruptible
= true;
4646 mutex_unlock(&dev
->struct_mutex
);
4649 /* Let userspace switch the overlay on again. In most cases userspace
4650 * has to recompute where to put it anyway.
4655 * intel_post_enable_primary - Perform operations after enabling primary plane
4656 * @crtc: the CRTC whose primary plane was just enabled
4658 * Performs potentially sleeping operations that must be done after the primary
4659 * plane is enabled, such as updating FBC and IPS. Note that this may be
4660 * called due to an explicit primary plane update, or due to an implicit
4661 * re-enable that is caused when a sprite plane is updated to no longer
4662 * completely hide the primary plane.
4665 intel_post_enable_primary(struct drm_crtc
*crtc
)
4667 struct drm_device
*dev
= crtc
->dev
;
4668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4669 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4670 int pipe
= intel_crtc
->pipe
;
4673 * BDW signals flip done immediately if the plane
4674 * is disabled, even if the plane enable is already
4675 * armed to occur at the next vblank :(
4677 if (IS_BROADWELL(dev
))
4678 intel_wait_for_vblank(dev
, pipe
);
4681 * FIXME IPS should be fine as long as one plane is
4682 * enabled, but in practice it seems to have problems
4683 * when going from primary only to sprite only and vice
4686 hsw_enable_ips(intel_crtc
);
4689 * Gen2 reports pipe underruns whenever all planes are disabled.
4690 * So don't enable underrun reporting before at least some planes
4692 * FIXME: Need to fix the logic to work when we turn off all planes
4693 * but leave the pipe running.
4696 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4698 /* Underruns don't raise interrupts, so check manually. */
4699 if (HAS_GMCH_DISPLAY(dev
))
4700 i9xx_check_fifo_underruns(dev_priv
);
4704 * intel_pre_disable_primary - Perform operations before disabling primary plane
4705 * @crtc: the CRTC whose primary plane is to be disabled
4707 * Performs potentially sleeping operations that must be done before the
4708 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4709 * be called due to an explicit primary plane update, or due to an implicit
4710 * disable that is caused when a sprite plane completely hides the primary
4714 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4716 struct drm_device
*dev
= crtc
->dev
;
4717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4718 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4719 int pipe
= intel_crtc
->pipe
;
4722 * Gen2 reports pipe underruns whenever all planes are disabled.
4723 * So diasble underrun reporting before all the planes get disabled.
4724 * FIXME: Need to fix the logic to work when we turn off all planes
4725 * but leave the pipe running.
4728 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4731 * Vblank time updates from the shadow to live plane control register
4732 * are blocked if the memory self-refresh mode is active at that
4733 * moment. So to make sure the plane gets truly disabled, disable
4734 * first the self-refresh mode. The self-refresh enable bit in turn
4735 * will be checked/applied by the HW only at the next frame start
4736 * event which is after the vblank start event, so we need to have a
4737 * wait-for-vblank between disabling the plane and the pipe.
4739 if (HAS_GMCH_DISPLAY(dev
)) {
4740 intel_set_memory_cxsr(dev_priv
, false);
4741 dev_priv
->wm
.vlv
.cxsr
= false;
4742 intel_wait_for_vblank(dev
, pipe
);
4746 * FIXME IPS should be fine as long as one plane is
4747 * enabled, but in practice it seems to have problems
4748 * when going from primary only to sprite only and vice
4751 hsw_disable_ips(intel_crtc
);
4754 static void intel_post_plane_update(struct intel_crtc
*crtc
)
4756 struct intel_crtc_atomic_commit
*atomic
= &crtc
->atomic
;
4757 struct drm_device
*dev
= crtc
->base
.dev
;
4758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4759 struct drm_plane
*plane
;
4761 if (atomic
->wait_vblank
)
4762 intel_wait_for_vblank(dev
, crtc
->pipe
);
4764 intel_frontbuffer_flip(dev
, atomic
->fb_bits
);
4766 if (atomic
->disable_cxsr
)
4767 crtc
->wm
.cxsr_allowed
= true;
4769 if (crtc
->atomic
.update_wm_post
)
4770 intel_update_watermarks(&crtc
->base
);
4772 if (atomic
->update_fbc
)
4773 intel_fbc_update(dev_priv
);
4775 if (atomic
->post_enable_primary
)
4776 intel_post_enable_primary(&crtc
->base
);
4778 drm_for_each_plane_mask(plane
, dev
, atomic
->update_sprite_watermarks
)
4779 intel_update_sprite_watermarks(plane
, &crtc
->base
,
4780 0, 0, 0, false, false);
4782 memset(atomic
, 0, sizeof(*atomic
));
4785 static void intel_pre_plane_update(struct intel_crtc
*crtc
)
4787 struct drm_device
*dev
= crtc
->base
.dev
;
4788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4789 struct intel_crtc_atomic_commit
*atomic
= &crtc
->atomic
;
4790 struct drm_plane
*p
;
4792 /* Track fb's for any planes being disabled */
4793 drm_for_each_plane_mask(p
, dev
, atomic
->disabled_planes
) {
4794 struct intel_plane
*plane
= to_intel_plane(p
);
4796 mutex_lock(&dev
->struct_mutex
);
4797 i915_gem_track_fb(intel_fb_obj(plane
->base
.fb
), NULL
,
4798 plane
->frontbuffer_bit
);
4799 mutex_unlock(&dev
->struct_mutex
);
4802 if (atomic
->wait_for_flips
)
4803 intel_crtc_wait_for_pending_flips(&crtc
->base
);
4805 if (atomic
->disable_fbc
)
4806 intel_fbc_disable_crtc(crtc
);
4808 if (crtc
->atomic
.disable_ips
)
4809 hsw_disable_ips(crtc
);
4811 if (atomic
->pre_disable_primary
)
4812 intel_pre_disable_primary(&crtc
->base
);
4814 if (atomic
->disable_cxsr
) {
4815 crtc
->wm
.cxsr_allowed
= false;
4816 intel_set_memory_cxsr(dev_priv
, false);
4820 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
, unsigned plane_mask
)
4822 struct drm_device
*dev
= crtc
->dev
;
4823 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4824 struct drm_plane
*p
;
4825 int pipe
= intel_crtc
->pipe
;
4827 intel_crtc_dpms_overlay_disable(intel_crtc
);
4829 drm_for_each_plane_mask(p
, dev
, plane_mask
)
4830 to_intel_plane(p
)->disable_plane(p
, crtc
);
4833 * FIXME: Once we grow proper nuclear flip support out of this we need
4834 * to compute the mask of flip planes precisely. For the time being
4835 * consider this a flip to a NULL plane.
4837 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4840 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4842 struct drm_device
*dev
= crtc
->dev
;
4843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4844 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4845 struct intel_encoder
*encoder
;
4846 int pipe
= intel_crtc
->pipe
;
4848 if (WARN_ON(intel_crtc
->active
))
4851 if (intel_crtc
->config
->has_pch_encoder
)
4852 intel_prepare_shared_dpll(intel_crtc
);
4854 if (intel_crtc
->config
->has_dp_encoder
)
4855 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4857 intel_set_pipe_timings(intel_crtc
);
4859 if (intel_crtc
->config
->has_pch_encoder
) {
4860 intel_cpu_transcoder_set_m_n(intel_crtc
,
4861 &intel_crtc
->config
->fdi_m_n
, NULL
);
4864 ironlake_set_pipeconf(crtc
);
4866 intel_crtc
->active
= true;
4868 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4869 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4871 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4872 if (encoder
->pre_enable
)
4873 encoder
->pre_enable(encoder
);
4875 if (intel_crtc
->config
->has_pch_encoder
) {
4876 /* Note: FDI PLL enabling _must_ be done before we enable the
4877 * cpu pipes, hence this is separate from all the other fdi/pch
4879 ironlake_fdi_pll_enable(intel_crtc
);
4881 assert_fdi_tx_disabled(dev_priv
, pipe
);
4882 assert_fdi_rx_disabled(dev_priv
, pipe
);
4885 ironlake_pfit_enable(intel_crtc
);
4888 * On ILK+ LUT must be loaded before the pipe is running but with
4891 intel_crtc_load_lut(crtc
);
4893 intel_update_watermarks(crtc
);
4894 intel_enable_pipe(intel_crtc
);
4896 if (intel_crtc
->config
->has_pch_encoder
)
4897 ironlake_pch_enable(crtc
);
4899 assert_vblank_disabled(crtc
);
4900 drm_crtc_vblank_on(crtc
);
4902 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4903 encoder
->enable(encoder
);
4905 if (HAS_PCH_CPT(dev
))
4906 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4909 /* IPS only exists on ULT machines and is tied to pipe A. */
4910 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4912 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4915 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4917 struct drm_device
*dev
= crtc
->dev
;
4918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4919 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4920 struct intel_encoder
*encoder
;
4921 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
4922 struct intel_crtc_state
*pipe_config
=
4923 to_intel_crtc_state(crtc
->state
);
4925 if (WARN_ON(intel_crtc
->active
))
4928 if (intel_crtc_to_shared_dpll(intel_crtc
))
4929 intel_enable_shared_dpll(intel_crtc
);
4931 if (intel_crtc
->config
->has_dp_encoder
)
4932 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4934 intel_set_pipe_timings(intel_crtc
);
4936 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
4937 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
4938 intel_crtc
->config
->pixel_multiplier
- 1);
4941 if (intel_crtc
->config
->has_pch_encoder
) {
4942 intel_cpu_transcoder_set_m_n(intel_crtc
,
4943 &intel_crtc
->config
->fdi_m_n
, NULL
);
4946 haswell_set_pipeconf(crtc
);
4948 intel_set_pipe_csc(crtc
);
4950 intel_crtc
->active
= true;
4952 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4953 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4954 if (encoder
->pre_enable
)
4955 encoder
->pre_enable(encoder
);
4957 if (intel_crtc
->config
->has_pch_encoder
) {
4958 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4960 dev_priv
->display
.fdi_link_train(crtc
);
4963 intel_ddi_enable_pipe_clock(intel_crtc
);
4965 if (INTEL_INFO(dev
)->gen
>= 9)
4966 skylake_pfit_enable(intel_crtc
);
4968 ironlake_pfit_enable(intel_crtc
);
4971 * On ILK+ LUT must be loaded before the pipe is running but with
4974 intel_crtc_load_lut(crtc
);
4976 intel_ddi_set_pipe_settings(crtc
);
4977 intel_ddi_enable_transcoder_func(crtc
);
4979 intel_update_watermarks(crtc
);
4980 intel_enable_pipe(intel_crtc
);
4982 if (intel_crtc
->config
->has_pch_encoder
)
4983 lpt_pch_enable(crtc
);
4985 if (intel_crtc
->config
->dp_encoder_is_mst
)
4986 intel_ddi_set_vc_payload_alloc(crtc
, true);
4988 assert_vblank_disabled(crtc
);
4989 drm_crtc_vblank_on(crtc
);
4991 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4992 encoder
->enable(encoder
);
4993 intel_opregion_notify_encoder(encoder
, true);
4996 /* If we change the relative order between pipe/planes enabling, we need
4997 * to change the workaround. */
4998 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
4999 if (IS_HASWELL(dev
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
5000 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
5001 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
5005 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
)
5007 struct drm_device
*dev
= crtc
->base
.dev
;
5008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5009 int pipe
= crtc
->pipe
;
5011 /* To avoid upsetting the power well on haswell only disable the pfit if
5012 * it's in use. The hw state code will make sure we get this right. */
5013 if (force
|| crtc
->config
->pch_pfit
.enabled
) {
5014 I915_WRITE(PF_CTL(pipe
), 0);
5015 I915_WRITE(PF_WIN_POS(pipe
), 0);
5016 I915_WRITE(PF_WIN_SZ(pipe
), 0);
5020 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
5022 struct drm_device
*dev
= crtc
->dev
;
5023 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5024 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5025 struct intel_encoder
*encoder
;
5026 int pipe
= intel_crtc
->pipe
;
5029 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5030 encoder
->disable(encoder
);
5032 drm_crtc_vblank_off(crtc
);
5033 assert_vblank_disabled(crtc
);
5035 if (intel_crtc
->config
->has_pch_encoder
)
5036 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5038 intel_disable_pipe(intel_crtc
);
5040 ironlake_pfit_disable(intel_crtc
, false);
5042 if (intel_crtc
->config
->has_pch_encoder
)
5043 ironlake_fdi_disable(crtc
);
5045 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5046 if (encoder
->post_disable
)
5047 encoder
->post_disable(encoder
);
5049 if (intel_crtc
->config
->has_pch_encoder
) {
5050 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5052 if (HAS_PCH_CPT(dev
)) {
5053 /* disable TRANS_DP_CTL */
5054 reg
= TRANS_DP_CTL(pipe
);
5055 temp
= I915_READ(reg
);
5056 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5057 TRANS_DP_PORT_SEL_MASK
);
5058 temp
|= TRANS_DP_PORT_SEL_NONE
;
5059 I915_WRITE(reg
, temp
);
5061 /* disable DPLL_SEL */
5062 temp
= I915_READ(PCH_DPLL_SEL
);
5063 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5064 I915_WRITE(PCH_DPLL_SEL
, temp
);
5067 ironlake_fdi_pll_disable(intel_crtc
);
5070 intel_crtc
->active
= false;
5071 intel_update_watermarks(crtc
);
5074 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5076 struct drm_device
*dev
= crtc
->dev
;
5077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5078 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5079 struct intel_encoder
*encoder
;
5080 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5082 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5083 intel_opregion_notify_encoder(encoder
, false);
5084 encoder
->disable(encoder
);
5087 drm_crtc_vblank_off(crtc
);
5088 assert_vblank_disabled(crtc
);
5090 if (intel_crtc
->config
->has_pch_encoder
)
5091 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5093 intel_disable_pipe(intel_crtc
);
5095 if (intel_crtc
->config
->dp_encoder_is_mst
)
5096 intel_ddi_set_vc_payload_alloc(crtc
, false);
5098 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5100 if (INTEL_INFO(dev
)->gen
>= 9)
5101 skylake_scaler_disable(intel_crtc
);
5103 ironlake_pfit_disable(intel_crtc
, false);
5105 intel_ddi_disable_pipe_clock(intel_crtc
);
5107 if (intel_crtc
->config
->has_pch_encoder
) {
5108 lpt_disable_pch_transcoder(dev_priv
);
5109 intel_ddi_fdi_disable(crtc
);
5112 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5113 if (encoder
->post_disable
)
5114 encoder
->post_disable(encoder
);
5116 intel_crtc
->active
= false;
5117 intel_update_watermarks(crtc
);
5120 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5122 struct drm_device
*dev
= crtc
->base
.dev
;
5123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5124 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5126 if (!pipe_config
->gmch_pfit
.control
)
5130 * The panel fitter should only be adjusted whilst the pipe is disabled,
5131 * according to register description and PRM.
5133 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5134 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5136 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5137 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5139 /* Border color in case we don't scale up to the full screen. Black by
5140 * default, change to something else for debugging. */
5141 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5144 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5148 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
5150 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
5152 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
5154 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
5156 return POWER_DOMAIN_PORT_DDI_E_2_LANES
;
5159 return POWER_DOMAIN_PORT_OTHER
;
5163 #define for_each_power_domain(domain, mask) \
5164 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5165 if ((1 << (domain)) & (mask))
5167 enum intel_display_power_domain
5168 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5170 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5171 struct intel_digital_port
*intel_dig_port
;
5173 switch (intel_encoder
->type
) {
5174 case INTEL_OUTPUT_UNKNOWN
:
5175 /* Only DDI platforms should ever use this output type */
5176 WARN_ON_ONCE(!HAS_DDI(dev
));
5177 case INTEL_OUTPUT_DISPLAYPORT
:
5178 case INTEL_OUTPUT_HDMI
:
5179 case INTEL_OUTPUT_EDP
:
5180 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5181 return port_to_power_domain(intel_dig_port
->port
);
5182 case INTEL_OUTPUT_DP_MST
:
5183 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5184 return port_to_power_domain(intel_dig_port
->port
);
5185 case INTEL_OUTPUT_ANALOG
:
5186 return POWER_DOMAIN_PORT_CRT
;
5187 case INTEL_OUTPUT_DSI
:
5188 return POWER_DOMAIN_PORT_DSI
;
5190 return POWER_DOMAIN_PORT_OTHER
;
5194 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
5196 struct drm_device
*dev
= crtc
->dev
;
5197 struct intel_encoder
*intel_encoder
;
5198 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5199 enum pipe pipe
= intel_crtc
->pipe
;
5201 enum transcoder transcoder
;
5203 if (!crtc
->state
->active
)
5206 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
5208 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5209 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5210 if (intel_crtc
->config
->pch_pfit
.enabled
||
5211 intel_crtc
->config
->pch_pfit
.force_thru
)
5212 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5214 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5215 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5220 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc
*crtc
)
5222 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5223 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5224 enum intel_display_power_domain domain
;
5225 unsigned long domains
, new_domains
, old_domains
;
5227 old_domains
= intel_crtc
->enabled_power_domains
;
5228 intel_crtc
->enabled_power_domains
= new_domains
= get_crtc_power_domains(crtc
);
5230 domains
= new_domains
& ~old_domains
;
5232 for_each_power_domain(domain
, domains
)
5233 intel_display_power_get(dev_priv
, domain
);
5235 return old_domains
& ~new_domains
;
5238 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
5239 unsigned long domains
)
5241 enum intel_display_power_domain domain
;
5243 for_each_power_domain(domain
, domains
)
5244 intel_display_power_put(dev_priv
, domain
);
5247 static void modeset_update_crtc_power_domains(struct drm_atomic_state
*state
)
5249 struct drm_device
*dev
= state
->dev
;
5250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5251 unsigned long put_domains
[I915_MAX_PIPES
] = {};
5252 struct drm_crtc_state
*crtc_state
;
5253 struct drm_crtc
*crtc
;
5256 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5257 if (needs_modeset(crtc
->state
))
5258 put_domains
[to_intel_crtc(crtc
)->pipe
] =
5259 modeset_get_crtc_power_domains(crtc
);
5262 if (dev_priv
->display
.modeset_commit_cdclk
) {
5263 unsigned int cdclk
= to_intel_atomic_state(state
)->cdclk
;
5265 if (cdclk
!= dev_priv
->cdclk_freq
&&
5266 !WARN_ON(!state
->allow_modeset
))
5267 dev_priv
->display
.modeset_commit_cdclk(state
);
5270 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
5272 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
5275 static int intel_compute_max_dotclk(struct drm_i915_private
*dev_priv
)
5277 int max_cdclk_freq
= dev_priv
->max_cdclk_freq
;
5279 if (INTEL_INFO(dev_priv
)->gen
>= 9 ||
5280 IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5281 return max_cdclk_freq
;
5282 else if (IS_CHERRYVIEW(dev_priv
))
5283 return max_cdclk_freq
*95/100;
5284 else if (INTEL_INFO(dev_priv
)->gen
< 4)
5285 return 2*max_cdclk_freq
*90/100;
5287 return max_cdclk_freq
*90/100;
5290 static void intel_update_max_cdclk(struct drm_device
*dev
)
5292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5294 if (IS_SKYLAKE(dev
)) {
5295 u32 limit
= I915_READ(SKL_DFSM
) & SKL_DFSM_CDCLK_LIMIT_MASK
;
5297 if (limit
== SKL_DFSM_CDCLK_LIMIT_675
)
5298 dev_priv
->max_cdclk_freq
= 675000;
5299 else if (limit
== SKL_DFSM_CDCLK_LIMIT_540
)
5300 dev_priv
->max_cdclk_freq
= 540000;
5301 else if (limit
== SKL_DFSM_CDCLK_LIMIT_450
)
5302 dev_priv
->max_cdclk_freq
= 450000;
5304 dev_priv
->max_cdclk_freq
= 337500;
5305 } else if (IS_BROADWELL(dev
)) {
5307 * FIXME with extra cooling we can allow
5308 * 540 MHz for ULX and 675 Mhz for ULT.
5309 * How can we know if extra cooling is
5310 * available? PCI ID, VTB, something else?
5312 if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5313 dev_priv
->max_cdclk_freq
= 450000;
5314 else if (IS_BDW_ULX(dev
))
5315 dev_priv
->max_cdclk_freq
= 450000;
5316 else if (IS_BDW_ULT(dev
))
5317 dev_priv
->max_cdclk_freq
= 540000;
5319 dev_priv
->max_cdclk_freq
= 675000;
5320 } else if (IS_CHERRYVIEW(dev
)) {
5321 dev_priv
->max_cdclk_freq
= 320000;
5322 } else if (IS_VALLEYVIEW(dev
)) {
5323 dev_priv
->max_cdclk_freq
= 400000;
5325 /* otherwise assume cdclk is fixed */
5326 dev_priv
->max_cdclk_freq
= dev_priv
->cdclk_freq
;
5329 dev_priv
->max_dotclk_freq
= intel_compute_max_dotclk(dev_priv
);
5331 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5332 dev_priv
->max_cdclk_freq
);
5334 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5335 dev_priv
->max_dotclk_freq
);
5338 static void intel_update_cdclk(struct drm_device
*dev
)
5340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5342 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5343 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5344 dev_priv
->cdclk_freq
);
5347 * Program the gmbus_freq based on the cdclk frequency.
5348 * BSpec erroneously claims we should aim for 4MHz, but
5349 * in fact 1MHz is the correct frequency.
5351 if (IS_VALLEYVIEW(dev
)) {
5353 * Program the gmbus_freq based on the cdclk frequency.
5354 * BSpec erroneously claims we should aim for 4MHz, but
5355 * in fact 1MHz is the correct frequency.
5357 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5360 if (dev_priv
->max_cdclk_freq
== 0)
5361 intel_update_max_cdclk(dev
);
5364 static void broxton_set_cdclk(struct drm_device
*dev
, int frequency
)
5366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5369 uint32_t current_freq
;
5372 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5373 switch (frequency
) {
5375 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5376 ratio
= BXT_DE_PLL_RATIO(60);
5379 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5380 ratio
= BXT_DE_PLL_RATIO(60);
5383 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5384 ratio
= BXT_DE_PLL_RATIO(60);
5387 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5388 ratio
= BXT_DE_PLL_RATIO(60);
5391 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5392 ratio
= BXT_DE_PLL_RATIO(65);
5396 * Bypass frequency with DE PLL disabled. Init ratio, divider
5397 * to suppress GCC warning.
5403 DRM_ERROR("unsupported CDCLK freq %d", frequency
);
5408 mutex_lock(&dev_priv
->rps
.hw_lock
);
5409 /* Inform power controller of upcoming frequency change */
5410 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5412 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5415 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5420 current_freq
= I915_READ(CDCLK_CTL
) & CDCLK_FREQ_DECIMAL_MASK
;
5421 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5422 current_freq
= current_freq
* 500 + 1000;
5425 * DE PLL has to be disabled when
5426 * - setting to 19.2MHz (bypass, PLL isn't used)
5427 * - before setting to 624MHz (PLL needs toggling)
5428 * - before setting to any frequency from 624MHz (PLL needs toggling)
5430 if (frequency
== 19200 || frequency
== 624000 ||
5431 current_freq
== 624000) {
5432 I915_WRITE(BXT_DE_PLL_ENABLE
, ~BXT_DE_PLL_PLL_ENABLE
);
5434 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
),
5436 DRM_ERROR("timout waiting for DE PLL unlock\n");
5439 if (frequency
!= 19200) {
5442 val
= I915_READ(BXT_DE_PLL_CTL
);
5443 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5445 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5447 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5449 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
, 1))
5450 DRM_ERROR("timeout waiting for DE PLL lock\n");
5452 val
= I915_READ(CDCLK_CTL
);
5453 val
&= ~BXT_CDCLK_CD2X_DIV_SEL_MASK
;
5456 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5459 val
&= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5460 if (frequency
>= 500000)
5461 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5463 val
&= ~CDCLK_FREQ_DECIMAL_MASK
;
5464 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5465 val
|= (frequency
- 1000) / 500;
5466 I915_WRITE(CDCLK_CTL
, val
);
5469 mutex_lock(&dev_priv
->rps
.hw_lock
);
5470 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5471 DIV_ROUND_UP(frequency
, 25000));
5472 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5475 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5480 intel_update_cdclk(dev
);
5483 void broxton_init_cdclk(struct drm_device
*dev
)
5485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5489 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5490 * or else the reset will hang because there is no PCH to respond.
5491 * Move the handshake programming to initialization sequence.
5492 * Previously was left up to BIOS.
5494 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5495 val
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5496 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
);
5498 /* Enable PG1 for cdclk */
5499 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5501 /* check if cd clock is enabled */
5502 if (I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_PLL_ENABLE
) {
5503 DRM_DEBUG_KMS("Display already initialized\n");
5509 * - The initial CDCLK needs to be read from VBT.
5510 * Need to make this change after VBT has changes for BXT.
5511 * - check if setting the max (or any) cdclk freq is really necessary
5512 * here, it belongs to modeset time
5514 broxton_set_cdclk(dev
, 624000);
5516 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5517 POSTING_READ(DBUF_CTL
);
5521 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5522 DRM_ERROR("DBuf power enable timeout!\n");
5525 void broxton_uninit_cdclk(struct drm_device
*dev
)
5527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5529 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5530 POSTING_READ(DBUF_CTL
);
5534 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5535 DRM_ERROR("DBuf power disable timeout!\n");
5537 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5538 broxton_set_cdclk(dev
, 19200);
5540 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5543 static const struct skl_cdclk_entry
{
5546 } skl_cdclk_frequencies
[] = {
5547 { .freq
= 308570, .vco
= 8640 },
5548 { .freq
= 337500, .vco
= 8100 },
5549 { .freq
= 432000, .vco
= 8640 },
5550 { .freq
= 450000, .vco
= 8100 },
5551 { .freq
= 540000, .vco
= 8100 },
5552 { .freq
= 617140, .vco
= 8640 },
5553 { .freq
= 675000, .vco
= 8100 },
5556 static unsigned int skl_cdclk_decimal(unsigned int freq
)
5558 return (freq
- 1000) / 500;
5561 static unsigned int skl_cdclk_get_vco(unsigned int freq
)
5565 for (i
= 0; i
< ARRAY_SIZE(skl_cdclk_frequencies
); i
++) {
5566 const struct skl_cdclk_entry
*e
= &skl_cdclk_frequencies
[i
];
5568 if (e
->freq
== freq
)
5576 skl_dpll0_enable(struct drm_i915_private
*dev_priv
, unsigned int required_vco
)
5578 unsigned int min_freq
;
5581 /* select the minimum CDCLK before enabling DPLL 0 */
5582 val
= I915_READ(CDCLK_CTL
);
5583 val
&= ~CDCLK_FREQ_SEL_MASK
| ~CDCLK_FREQ_DECIMAL_MASK
;
5584 val
|= CDCLK_FREQ_337_308
;
5586 if (required_vco
== 8640)
5591 val
= CDCLK_FREQ_337_308
| skl_cdclk_decimal(min_freq
);
5593 I915_WRITE(CDCLK_CTL
, val
);
5594 POSTING_READ(CDCLK_CTL
);
5597 * We always enable DPLL0 with the lowest link rate possible, but still
5598 * taking into account the VCO required to operate the eDP panel at the
5599 * desired frequency. The usual DP link rates operate with a VCO of
5600 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5601 * The modeset code is responsible for the selection of the exact link
5602 * rate later on, with the constraint of choosing a frequency that
5603 * works with required_vco.
5605 val
= I915_READ(DPLL_CTRL1
);
5607 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
5608 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5609 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
5610 if (required_vco
== 8640)
5611 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
5614 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
5617 I915_WRITE(DPLL_CTRL1
, val
);
5618 POSTING_READ(DPLL_CTRL1
);
5620 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
5622 if (wait_for(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
, 5))
5623 DRM_ERROR("DPLL0 not locked\n");
5626 static bool skl_cdclk_pcu_ready(struct drm_i915_private
*dev_priv
)
5631 /* inform PCU we want to change CDCLK */
5632 val
= SKL_CDCLK_PREPARE_FOR_CHANGE
;
5633 mutex_lock(&dev_priv
->rps
.hw_lock
);
5634 ret
= sandybridge_pcode_read(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, &val
);
5635 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5637 return ret
== 0 && (val
& SKL_CDCLK_READY_FOR_CHANGE
);
5640 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private
*dev_priv
)
5644 for (i
= 0; i
< 15; i
++) {
5645 if (skl_cdclk_pcu_ready(dev_priv
))
5653 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
, unsigned int freq
)
5655 struct drm_device
*dev
= dev_priv
->dev
;
5656 u32 freq_select
, pcu_ack
;
5658 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq
);
5660 if (!skl_cdclk_wait_for_pcu_ready(dev_priv
)) {
5661 DRM_ERROR("failed to inform PCU about cdclk change\n");
5669 freq_select
= CDCLK_FREQ_450_432
;
5673 freq_select
= CDCLK_FREQ_540
;
5679 freq_select
= CDCLK_FREQ_337_308
;
5684 freq_select
= CDCLK_FREQ_675_617
;
5689 I915_WRITE(CDCLK_CTL
, freq_select
| skl_cdclk_decimal(freq
));
5690 POSTING_READ(CDCLK_CTL
);
5692 /* inform PCU of the change */
5693 mutex_lock(&dev_priv
->rps
.hw_lock
);
5694 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
5695 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5697 intel_update_cdclk(dev
);
5700 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5702 /* disable DBUF power */
5703 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5704 POSTING_READ(DBUF_CTL
);
5708 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5709 DRM_ERROR("DBuf power disable timeout\n");
5712 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5714 if (dev_priv
->csr
.dmc_payload
) {
5716 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) &
5718 if (wait_for(!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
), 1))
5719 DRM_ERROR("Couldn't disable DPLL0\n");
5722 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5725 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
5728 unsigned int required_vco
;
5730 /* enable PCH reset handshake */
5731 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5732 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
| RESET_PCH_HANDSHAKE_ENABLE
);
5734 /* enable PG1 and Misc I/O */
5735 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5737 /* DPLL0 not enabled (happens on early BIOS versions) */
5738 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
)) {
5740 required_vco
= skl_cdclk_get_vco(dev_priv
->skl_boot_cdclk
);
5741 skl_dpll0_enable(dev_priv
, required_vco
);
5744 /* set CDCLK to the frequency the BIOS chose */
5745 skl_set_cdclk(dev_priv
, dev_priv
->skl_boot_cdclk
);
5747 /* enable DBUF power */
5748 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5749 POSTING_READ(DBUF_CTL
);
5753 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5754 DRM_ERROR("DBuf power enable timeout\n");
5757 /* returns HPLL frequency in kHz */
5758 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
5760 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
5762 /* Obtain SKU information */
5763 mutex_lock(&dev_priv
->sb_lock
);
5764 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
5765 CCK_FUSE_HPLL_FREQ_MASK
;
5766 mutex_unlock(&dev_priv
->sb_lock
);
5768 return vco_freq
[hpll_freq
] * 1000;
5771 /* Adjust CDclk dividers to allow high res or save power if possible */
5772 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5777 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5778 != dev_priv
->cdclk_freq
);
5780 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5782 else if (cdclk
== 266667)
5787 mutex_lock(&dev_priv
->rps
.hw_lock
);
5788 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5789 val
&= ~DSPFREQGUAR_MASK
;
5790 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5791 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5792 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5793 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5795 DRM_ERROR("timed out waiting for CDclk change\n");
5797 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5799 mutex_lock(&dev_priv
->sb_lock
);
5801 if (cdclk
== 400000) {
5804 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5806 /* adjust cdclk divider */
5807 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5808 val
&= ~DISPLAY_FREQUENCY_VALUES
;
5810 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5812 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5813 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5815 DRM_ERROR("timed out waiting for CDclk change\n");
5818 /* adjust self-refresh exit latency value */
5819 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5823 * For high bandwidth configs, we set a higher latency in the bunit
5824 * so that the core display fetch happens in time to avoid underruns.
5826 if (cdclk
== 400000)
5827 val
|= 4500 / 250; /* 4.5 usec */
5829 val
|= 3000 / 250; /* 3.0 usec */
5830 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5832 mutex_unlock(&dev_priv
->sb_lock
);
5834 intel_update_cdclk(dev
);
5837 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5842 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5843 != dev_priv
->cdclk_freq
);
5852 MISSING_CASE(cdclk
);
5857 * Specs are full of misinformation, but testing on actual
5858 * hardware has shown that we just need to write the desired
5859 * CCK divider into the Punit register.
5861 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5863 mutex_lock(&dev_priv
->rps
.hw_lock
);
5864 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5865 val
&= ~DSPFREQGUAR_MASK_CHV
;
5866 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5867 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5868 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5869 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5871 DRM_ERROR("timed out waiting for CDclk change\n");
5873 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5875 intel_update_cdclk(dev
);
5878 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5881 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5882 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5885 * Really only a few cases to deal with, as only 4 CDclks are supported:
5888 * 320/333MHz (depends on HPLL freq)
5890 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5891 * of the lower bin and adjust if needed.
5893 * We seem to get an unstable or solid color picture at 200MHz.
5894 * Not sure what's wrong. For now use 200MHz only when all pipes
5897 if (!IS_CHERRYVIEW(dev_priv
) &&
5898 max_pixclk
> freq_320
*limit
/100)
5900 else if (max_pixclk
> 266667*limit
/100)
5902 else if (max_pixclk
> 0)
5908 static int broxton_calc_cdclk(struct drm_i915_private
*dev_priv
,
5913 * - remove the guardband, it's not needed on BXT
5914 * - set 19.2MHz bypass frequency if there are no active pipes
5916 if (max_pixclk
> 576000*9/10)
5918 else if (max_pixclk
> 384000*9/10)
5920 else if (max_pixclk
> 288000*9/10)
5922 else if (max_pixclk
> 144000*9/10)
5928 /* Compute the max pixel clock for new configuration. Uses atomic state if
5929 * that's non-NULL, look at current state otherwise. */
5930 static int intel_mode_max_pixclk(struct drm_device
*dev
,
5931 struct drm_atomic_state
*state
)
5933 struct intel_crtc
*intel_crtc
;
5934 struct intel_crtc_state
*crtc_state
;
5937 for_each_intel_crtc(dev
, intel_crtc
) {
5938 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
5939 if (IS_ERR(crtc_state
))
5940 return PTR_ERR(crtc_state
);
5942 if (!crtc_state
->base
.enable
)
5945 max_pixclk
= max(max_pixclk
,
5946 crtc_state
->base
.adjusted_mode
.crtc_clock
);
5952 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state
*state
)
5954 struct drm_device
*dev
= state
->dev
;
5955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5956 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
5961 to_intel_atomic_state(state
)->cdclk
=
5962 valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5967 static int broxton_modeset_calc_cdclk(struct drm_atomic_state
*state
)
5969 struct drm_device
*dev
= state
->dev
;
5970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5971 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
5976 to_intel_atomic_state(state
)->cdclk
=
5977 broxton_calc_cdclk(dev_priv
, max_pixclk
);
5982 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
5984 unsigned int credits
, default_credits
;
5986 if (IS_CHERRYVIEW(dev_priv
))
5987 default_credits
= PFI_CREDIT(12);
5989 default_credits
= PFI_CREDIT(8);
5991 if (DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 1000) >= dev_priv
->rps
.cz_freq
) {
5992 /* CHV suggested value is 31 or 63 */
5993 if (IS_CHERRYVIEW(dev_priv
))
5994 credits
= PFI_CREDIT_63
;
5996 credits
= PFI_CREDIT(15);
5998 credits
= default_credits
;
6002 * WA - write default credits before re-programming
6003 * FIXME: should we also set the resend bit here?
6005 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6008 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6009 credits
| PFI_CREDIT_RESEND
);
6012 * FIXME is this guaranteed to clear
6013 * immediately or should we poll for it?
6015 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
6018 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
6020 struct drm_device
*dev
= old_state
->dev
;
6021 unsigned int req_cdclk
= to_intel_atomic_state(old_state
)->cdclk
;
6022 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6025 * FIXME: We can end up here with all power domains off, yet
6026 * with a CDCLK frequency other than the minimum. To account
6027 * for this take the PIPE-A power domain, which covers the HW
6028 * blocks needed for the following programming. This can be
6029 * removed once it's guaranteed that we get here either with
6030 * the minimum CDCLK set, or the required power domains
6033 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
6035 if (IS_CHERRYVIEW(dev
))
6036 cherryview_set_cdclk(dev
, req_cdclk
);
6038 valleyview_set_cdclk(dev
, req_cdclk
);
6040 vlv_program_pfi_credits(dev_priv
);
6042 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
6045 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
6047 struct drm_device
*dev
= crtc
->dev
;
6048 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6049 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6050 struct intel_encoder
*encoder
;
6051 int pipe
= intel_crtc
->pipe
;
6054 if (WARN_ON(intel_crtc
->active
))
6057 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
6059 if (intel_crtc
->config
->has_dp_encoder
)
6060 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6062 intel_set_pipe_timings(intel_crtc
);
6064 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
6065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6067 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6068 I915_WRITE(CHV_CANVAS(pipe
), 0);
6071 i9xx_set_pipeconf(intel_crtc
);
6073 intel_crtc
->active
= true;
6075 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6077 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6078 if (encoder
->pre_pll_enable
)
6079 encoder
->pre_pll_enable(encoder
);
6082 if (IS_CHERRYVIEW(dev
)) {
6083 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6084 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
6086 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6087 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
6091 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6092 if (encoder
->pre_enable
)
6093 encoder
->pre_enable(encoder
);
6095 i9xx_pfit_enable(intel_crtc
);
6097 intel_crtc_load_lut(crtc
);
6099 intel_enable_pipe(intel_crtc
);
6101 assert_vblank_disabled(crtc
);
6102 drm_crtc_vblank_on(crtc
);
6104 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6105 encoder
->enable(encoder
);
6108 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
6110 struct drm_device
*dev
= crtc
->base
.dev
;
6111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6113 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
6114 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
6117 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
6119 struct drm_device
*dev
= crtc
->dev
;
6120 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6121 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6122 struct intel_encoder
*encoder
;
6123 int pipe
= intel_crtc
->pipe
;
6125 if (WARN_ON(intel_crtc
->active
))
6128 i9xx_set_pll_dividers(intel_crtc
);
6130 if (intel_crtc
->config
->has_dp_encoder
)
6131 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6133 intel_set_pipe_timings(intel_crtc
);
6135 i9xx_set_pipeconf(intel_crtc
);
6137 intel_crtc
->active
= true;
6140 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6142 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6143 if (encoder
->pre_enable
)
6144 encoder
->pre_enable(encoder
);
6146 i9xx_enable_pll(intel_crtc
);
6148 i9xx_pfit_enable(intel_crtc
);
6150 intel_crtc_load_lut(crtc
);
6152 intel_update_watermarks(crtc
);
6153 intel_enable_pipe(intel_crtc
);
6155 assert_vblank_disabled(crtc
);
6156 drm_crtc_vblank_on(crtc
);
6158 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6159 encoder
->enable(encoder
);
6162 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6164 struct drm_device
*dev
= crtc
->base
.dev
;
6165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6167 if (!crtc
->config
->gmch_pfit
.control
)
6170 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6172 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6173 I915_READ(PFIT_CONTROL
));
6174 I915_WRITE(PFIT_CONTROL
, 0);
6177 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6179 struct drm_device
*dev
= crtc
->dev
;
6180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6181 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6182 struct intel_encoder
*encoder
;
6183 int pipe
= intel_crtc
->pipe
;
6186 * On gen2 planes are double buffered but the pipe isn't, so we must
6187 * wait for planes to fully turn off before disabling the pipe.
6188 * We also need to wait on all gmch platforms because of the
6189 * self-refresh mode constraint explained above.
6191 intel_wait_for_vblank(dev
, pipe
);
6193 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6194 encoder
->disable(encoder
);
6196 drm_crtc_vblank_off(crtc
);
6197 assert_vblank_disabled(crtc
);
6199 intel_disable_pipe(intel_crtc
);
6201 i9xx_pfit_disable(intel_crtc
);
6203 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6204 if (encoder
->post_disable
)
6205 encoder
->post_disable(encoder
);
6207 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
6208 if (IS_CHERRYVIEW(dev
))
6209 chv_disable_pll(dev_priv
, pipe
);
6210 else if (IS_VALLEYVIEW(dev
))
6211 vlv_disable_pll(dev_priv
, pipe
);
6213 i9xx_disable_pll(intel_crtc
);
6216 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6217 if (encoder
->post_pll_disable
)
6218 encoder
->post_pll_disable(encoder
);
6221 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6223 intel_crtc
->active
= false;
6224 intel_update_watermarks(crtc
);
6227 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
)
6229 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6230 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6231 enum intel_display_power_domain domain
;
6232 unsigned long domains
;
6234 if (!intel_crtc
->active
)
6237 if (to_intel_plane_state(crtc
->primary
->state
)->visible
) {
6238 intel_crtc_wait_for_pending_flips(crtc
);
6239 intel_pre_disable_primary(crtc
);
6242 intel_crtc_disable_planes(crtc
, crtc
->state
->plane_mask
);
6243 dev_priv
->display
.crtc_disable(crtc
);
6244 intel_disable_shared_dpll(intel_crtc
);
6246 domains
= intel_crtc
->enabled_power_domains
;
6247 for_each_power_domain(domain
, domains
)
6248 intel_display_power_put(dev_priv
, domain
);
6249 intel_crtc
->enabled_power_domains
= 0;
6253 * turn all crtc's off, but do not adjust state
6254 * This has to be paired with a call to intel_modeset_setup_hw_state.
6256 int intel_display_suspend(struct drm_device
*dev
)
6258 struct drm_mode_config
*config
= &dev
->mode_config
;
6259 struct drm_modeset_acquire_ctx
*ctx
= config
->acquire_ctx
;
6260 struct drm_atomic_state
*state
;
6261 struct drm_crtc
*crtc
;
6262 unsigned crtc_mask
= 0;
6268 lockdep_assert_held(&ctx
->ww_ctx
);
6269 state
= drm_atomic_state_alloc(dev
);
6270 if (WARN_ON(!state
))
6273 state
->acquire_ctx
= ctx
;
6274 state
->allow_modeset
= true;
6276 for_each_crtc(dev
, crtc
) {
6277 struct drm_crtc_state
*crtc_state
=
6278 drm_atomic_get_crtc_state(state
, crtc
);
6280 ret
= PTR_ERR_OR_ZERO(crtc_state
);
6284 if (!crtc_state
->active
)
6287 crtc_state
->active
= false;
6288 crtc_mask
|= 1 << drm_crtc_index(crtc
);
6292 ret
= drm_atomic_commit(state
);
6295 for_each_crtc(dev
, crtc
)
6296 if (crtc_mask
& (1 << drm_crtc_index(crtc
)))
6297 crtc
->state
->active
= true;
6305 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6306 drm_atomic_state_free(state
);
6310 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6312 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6314 drm_encoder_cleanup(encoder
);
6315 kfree(intel_encoder
);
6318 /* Cross check the actual hw state with our own modeset state tracking (and it's
6319 * internal consistency). */
6320 static void intel_connector_check_state(struct intel_connector
*connector
)
6322 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
6324 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6325 connector
->base
.base
.id
,
6326 connector
->base
.name
);
6328 if (connector
->get_hw_state(connector
)) {
6329 struct intel_encoder
*encoder
= connector
->encoder
;
6330 struct drm_connector_state
*conn_state
= connector
->base
.state
;
6332 I915_STATE_WARN(!crtc
,
6333 "connector enabled without attached crtc\n");
6338 I915_STATE_WARN(!crtc
->state
->active
,
6339 "connector is active, but attached crtc isn't\n");
6341 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
6344 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
6345 "atomic encoder doesn't match attached encoder\n");
6347 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
6348 "attached encoder crtc differs from connector crtc\n");
6350 I915_STATE_WARN(crtc
&& crtc
->state
->active
,
6351 "attached crtc is active, but connector isn't\n");
6352 I915_STATE_WARN(!crtc
&& connector
->base
.state
->best_encoder
,
6353 "best encoder set without crtc!\n");
6357 int intel_connector_init(struct intel_connector
*connector
)
6359 struct drm_connector_state
*connector_state
;
6361 connector_state
= kzalloc(sizeof *connector_state
, GFP_KERNEL
);
6362 if (!connector_state
)
6365 connector
->base
.state
= connector_state
;
6369 struct intel_connector
*intel_connector_alloc(void)
6371 struct intel_connector
*connector
;
6373 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6377 if (intel_connector_init(connector
) < 0) {
6385 /* Simple connector->get_hw_state implementation for encoders that support only
6386 * one connector and no cloning and hence the encoder state determines the state
6387 * of the connector. */
6388 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6391 struct intel_encoder
*encoder
= connector
->encoder
;
6393 return encoder
->get_hw_state(encoder
, &pipe
);
6396 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6398 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6399 return crtc_state
->fdi_lanes
;
6404 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6405 struct intel_crtc_state
*pipe_config
)
6407 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6408 struct intel_crtc
*other_crtc
;
6409 struct intel_crtc_state
*other_crtc_state
;
6411 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6412 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6413 if (pipe_config
->fdi_lanes
> 4) {
6414 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6415 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6419 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6420 if (pipe_config
->fdi_lanes
> 2) {
6421 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6422 pipe_config
->fdi_lanes
);
6429 if (INTEL_INFO(dev
)->num_pipes
== 2)
6432 /* Ivybridge 3 pipe is really complicated */
6437 if (pipe_config
->fdi_lanes
<= 2)
6440 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6442 intel_atomic_get_crtc_state(state
, other_crtc
);
6443 if (IS_ERR(other_crtc_state
))
6444 return PTR_ERR(other_crtc_state
);
6446 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6447 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6448 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6453 if (pipe_config
->fdi_lanes
> 2) {
6454 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6455 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6459 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6461 intel_atomic_get_crtc_state(state
, other_crtc
);
6462 if (IS_ERR(other_crtc_state
))
6463 return PTR_ERR(other_crtc_state
);
6465 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6466 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6476 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6477 struct intel_crtc_state
*pipe_config
)
6479 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6480 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6481 int lane
, link_bw
, fdi_dotclock
, ret
;
6482 bool needs_recompute
= false;
6485 /* FDI is a binary signal running at ~2.7GHz, encoding
6486 * each output octet as 10 bits. The actual frequency
6487 * is stored as a divider into a 100MHz clock, and the
6488 * mode pixel clock is stored in units of 1KHz.
6489 * Hence the bw of each lane in terms of the mode signal
6492 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
6494 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6496 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6497 pipe_config
->pipe_bpp
);
6499 pipe_config
->fdi_lanes
= lane
;
6501 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6502 link_bw
, &pipe_config
->fdi_m_n
);
6504 ret
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
6505 intel_crtc
->pipe
, pipe_config
);
6506 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6507 pipe_config
->pipe_bpp
-= 2*3;
6508 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6509 pipe_config
->pipe_bpp
);
6510 needs_recompute
= true;
6511 pipe_config
->bw_constrained
= true;
6516 if (needs_recompute
)
6522 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
6523 struct intel_crtc_state
*pipe_config
)
6525 if (pipe_config
->pipe_bpp
> 24)
6528 /* HSW can handle pixel rate up to cdclk? */
6529 if (IS_HASWELL(dev_priv
->dev
))
6533 * We compare against max which means we must take
6534 * the increased cdclk requirement into account when
6535 * calculating the new cdclk.
6537 * Should measure whether using a lower cdclk w/o IPS
6539 return ilk_pipe_pixel_rate(pipe_config
) <=
6540 dev_priv
->max_cdclk_freq
* 95 / 100;
6543 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6544 struct intel_crtc_state
*pipe_config
)
6546 struct drm_device
*dev
= crtc
->base
.dev
;
6547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6549 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6550 hsw_crtc_supports_ips(crtc
) &&
6551 pipe_config_supports_ips(dev_priv
, pipe_config
);
6554 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6555 struct intel_crtc_state
*pipe_config
)
6557 struct drm_device
*dev
= crtc
->base
.dev
;
6558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6559 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6561 /* FIXME should check pixel clock limits on all platforms */
6562 if (INTEL_INFO(dev
)->gen
< 4) {
6563 int clock_limit
= dev_priv
->max_cdclk_freq
;
6566 * Enable pixel doubling when the dot clock
6567 * is > 90% of the (display) core speed.
6569 * GDG double wide on either pipe,
6570 * otherwise pipe A only.
6572 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
6573 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
6575 pipe_config
->double_wide
= true;
6578 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
6583 * Pipe horizontal size must be even in:
6585 * - LVDS dual channel mode
6586 * - Double wide pipe
6588 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6589 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6590 pipe_config
->pipe_src_w
&= ~1;
6592 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6593 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6595 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6596 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
6600 hsw_compute_ips_config(crtc
, pipe_config
);
6602 if (pipe_config
->has_pch_encoder
)
6603 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6608 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6610 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6611 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
6612 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6615 if (!(lcpll1
& LCPLL_PLL_ENABLE
))
6616 return 24000; /* 24MHz is the cd freq with NSSC ref */
6618 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
6621 linkrate
= (I915_READ(DPLL_CTRL1
) &
6622 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
6624 if (linkrate
== DPLL_CTRL1_LINK_RATE_2160
||
6625 linkrate
== DPLL_CTRL1_LINK_RATE_1080
) {
6627 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6628 case CDCLK_FREQ_450_432
:
6630 case CDCLK_FREQ_337_308
:
6632 case CDCLK_FREQ_675_617
:
6635 WARN(1, "Unknown cd freq selection\n");
6639 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6640 case CDCLK_FREQ_450_432
:
6642 case CDCLK_FREQ_337_308
:
6644 case CDCLK_FREQ_675_617
:
6647 WARN(1, "Unknown cd freq selection\n");
6651 /* error case, do as if DPLL0 isn't enabled */
6655 static int broxton_get_display_clock_speed(struct drm_device
*dev
)
6657 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6658 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6659 uint32_t pll_ratio
= I915_READ(BXT_DE_PLL_CTL
) & BXT_DE_PLL_RATIO_MASK
;
6660 uint32_t pll_enab
= I915_READ(BXT_DE_PLL_ENABLE
);
6663 if (!(pll_enab
& BXT_DE_PLL_PLL_ENABLE
))
6666 cdclk
= 19200 * pll_ratio
/ 2;
6668 switch (cdctl
& BXT_CDCLK_CD2X_DIV_SEL_MASK
) {
6669 case BXT_CDCLK_CD2X_DIV_SEL_1
:
6670 return cdclk
; /* 576MHz or 624MHz */
6671 case BXT_CDCLK_CD2X_DIV_SEL_1_5
:
6672 return cdclk
* 2 / 3; /* 384MHz */
6673 case BXT_CDCLK_CD2X_DIV_SEL_2
:
6674 return cdclk
/ 2; /* 288MHz */
6675 case BXT_CDCLK_CD2X_DIV_SEL_4
:
6676 return cdclk
/ 4; /* 144MHz */
6679 /* error case, do as if DE PLL isn't enabled */
6683 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6686 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6687 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6689 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6691 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6693 else if (freq
== LCPLL_CLK_FREQ_450
)
6695 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6697 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6703 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6706 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6707 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6709 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6711 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6713 else if (freq
== LCPLL_CLK_FREQ_450
)
6715 else if (IS_HSW_ULT(dev
))
6721 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6727 if (dev_priv
->hpll_freq
== 0)
6728 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
6730 mutex_lock(&dev_priv
->sb_lock
);
6731 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
6732 mutex_unlock(&dev_priv
->sb_lock
);
6734 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
6736 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
6737 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
6738 "cdclk change in progress\n");
6740 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
6743 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6748 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6753 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6758 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6763 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6767 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6769 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6770 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6772 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6774 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6776 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6779 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6780 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6782 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6787 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6791 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6793 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6796 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6797 case GC_DISPLAY_CLOCK_333_MHZ
:
6800 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6806 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6811 static int i85x_get_display_clock_speed(struct drm_device
*dev
)
6816 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6817 * encoding is different :(
6818 * FIXME is this the right way to detect 852GM/852GMV?
6820 if (dev
->pdev
->revision
== 0x1)
6823 pci_bus_read_config_word(dev
->pdev
->bus
,
6824 PCI_DEVFN(0, 3), HPLLCC
, &hpllcc
);
6826 /* Assume that the hardware is in the high speed state. This
6827 * should be the default.
6829 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6830 case GC_CLOCK_133_200
:
6831 case GC_CLOCK_133_200_2
:
6832 case GC_CLOCK_100_200
:
6834 case GC_CLOCK_166_250
:
6836 case GC_CLOCK_100_133
:
6838 case GC_CLOCK_133_266
:
6839 case GC_CLOCK_133_266_2
:
6840 case GC_CLOCK_166_266
:
6844 /* Shouldn't happen */
6848 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6853 static unsigned int intel_hpll_vco(struct drm_device
*dev
)
6855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6856 static const unsigned int blb_vco
[8] = {
6863 static const unsigned int pnv_vco
[8] = {
6870 static const unsigned int cl_vco
[8] = {
6879 static const unsigned int elk_vco
[8] = {
6885 static const unsigned int ctg_vco
[8] = {
6893 const unsigned int *vco_table
;
6897 /* FIXME other chipsets? */
6899 vco_table
= ctg_vco
;
6900 else if (IS_G4X(dev
))
6901 vco_table
= elk_vco
;
6902 else if (IS_CRESTLINE(dev
))
6904 else if (IS_PINEVIEW(dev
))
6905 vco_table
= pnv_vco
;
6906 else if (IS_G33(dev
))
6907 vco_table
= blb_vco
;
6911 tmp
= I915_READ(IS_MOBILE(dev
) ? HPLLVCO_MOBILE
: HPLLVCO
);
6913 vco
= vco_table
[tmp
& 0x7];
6915 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp
);
6917 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco
);
6922 static int gm45_get_display_clock_speed(struct drm_device
*dev
)
6924 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6927 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6929 cdclk_sel
= (tmp
>> 12) & 0x1;
6935 return cdclk_sel
? 333333 : 222222;
6937 return cdclk_sel
? 320000 : 228571;
6939 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco
, tmp
);
6944 static int i965gm_get_display_clock_speed(struct drm_device
*dev
)
6946 static const uint8_t div_3200
[] = { 16, 10, 8 };
6947 static const uint8_t div_4000
[] = { 20, 12, 10 };
6948 static const uint8_t div_5333
[] = { 24, 16, 14 };
6949 const uint8_t *div_table
;
6950 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6953 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6955 cdclk_sel
= ((tmp
>> 8) & 0x1f) - 1;
6957 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
6962 div_table
= div_3200
;
6965 div_table
= div_4000
;
6968 div_table
= div_5333
;
6974 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
6977 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco
, tmp
);
6981 static int g33_get_display_clock_speed(struct drm_device
*dev
)
6983 static const uint8_t div_3200
[] = { 12, 10, 8, 7, 5, 16 };
6984 static const uint8_t div_4000
[] = { 14, 12, 10, 8, 6, 20 };
6985 static const uint8_t div_4800
[] = { 20, 14, 12, 10, 8, 24 };
6986 static const uint8_t div_5333
[] = { 20, 16, 12, 12, 8, 28 };
6987 const uint8_t *div_table
;
6988 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6991 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6993 cdclk_sel
= (tmp
>> 4) & 0x7;
6995 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7000 div_table
= div_3200
;
7003 div_table
= div_4000
;
7006 div_table
= div_4800
;
7009 div_table
= div_5333
;
7015 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7018 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco
, tmp
);
7023 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
7025 while (*num
> DATA_LINK_M_N_MASK
||
7026 *den
> DATA_LINK_M_N_MASK
) {
7032 static void compute_m_n(unsigned int m
, unsigned int n
,
7033 uint32_t *ret_m
, uint32_t *ret_n
)
7035 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7036 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
7037 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7041 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
7042 int pixel_clock
, int link_clock
,
7043 struct intel_link_m_n
*m_n
)
7047 compute_m_n(bits_per_pixel
* pixel_clock
,
7048 link_clock
* nlanes
* 8,
7049 &m_n
->gmch_m
, &m_n
->gmch_n
);
7051 compute_m_n(pixel_clock
, link_clock
,
7052 &m_n
->link_m
, &m_n
->link_n
);
7055 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7057 if (i915
.panel_use_ssc
>= 0)
7058 return i915
.panel_use_ssc
!= 0;
7059 return dev_priv
->vbt
.lvds_use_ssc
7060 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7063 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
7066 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
7067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7070 WARN_ON(!crtc_state
->base
.state
);
7072 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
7074 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7075 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7076 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7077 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7078 } else if (!IS_GEN2(dev
)) {
7087 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
7089 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7092 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
7094 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7097 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7098 struct intel_crtc_state
*crtc_state
,
7099 intel_clock_t
*reduced_clock
)
7101 struct drm_device
*dev
= crtc
->base
.dev
;
7104 if (IS_PINEVIEW(dev
)) {
7105 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7107 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7109 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7111 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7114 crtc_state
->dpll_hw_state
.fp0
= fp
;
7116 crtc
->lowfreq_avail
= false;
7117 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7119 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7120 crtc
->lowfreq_avail
= true;
7122 crtc_state
->dpll_hw_state
.fp1
= fp
;
7126 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7132 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7133 * and set it to a reasonable value instead.
7135 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7136 reg_val
&= 0xffffff00;
7137 reg_val
|= 0x00000030;
7138 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7140 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7141 reg_val
&= 0x8cffffff;
7142 reg_val
= 0x8c000000;
7143 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7145 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7146 reg_val
&= 0xffffff00;
7147 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7149 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7150 reg_val
&= 0x00ffffff;
7151 reg_val
|= 0xb0000000;
7152 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7155 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
7156 struct intel_link_m_n
*m_n
)
7158 struct drm_device
*dev
= crtc
->base
.dev
;
7159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7160 int pipe
= crtc
->pipe
;
7162 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7163 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7164 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7165 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7168 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
7169 struct intel_link_m_n
*m_n
,
7170 struct intel_link_m_n
*m2_n2
)
7172 struct drm_device
*dev
= crtc
->base
.dev
;
7173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7174 int pipe
= crtc
->pipe
;
7175 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
7177 if (INTEL_INFO(dev
)->gen
>= 5) {
7178 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7179 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7180 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7181 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7182 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7183 * for gen < 8) and if DRRS is supported (to make sure the
7184 * registers are not unnecessarily accessed).
7186 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
7187 crtc
->config
->has_drrs
) {
7188 I915_WRITE(PIPE_DATA_M2(transcoder
),
7189 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7190 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7191 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7192 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7195 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7196 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7197 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7198 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7202 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
7204 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7207 dp_m_n
= &crtc
->config
->dp_m_n
;
7208 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
7209 } else if (m_n
== M2_N2
) {
7212 * M2_N2 registers are not supported. Hence m2_n2 divider value
7213 * needs to be programmed into M1_N1.
7215 dp_m_n
= &crtc
->config
->dp_m2_n2
;
7217 DRM_ERROR("Unsupported divider value\n");
7221 if (crtc
->config
->has_pch_encoder
)
7222 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
7224 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
7227 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7228 struct intel_crtc_state
*pipe_config
)
7233 * Enable DPIO clock input. We should never disable the reference
7234 * clock for pipe B, since VGA hotplug / manual detection depends
7237 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REF_CLK_ENABLE_VLV
|
7238 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_REF_CLK_VLV
;
7239 /* We should never disable this, set it here for state tracking */
7240 if (crtc
->pipe
== PIPE_B
)
7241 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7242 dpll
|= DPLL_VCO_ENABLE
;
7243 pipe_config
->dpll_hw_state
.dpll
= dpll
;
7245 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
7246 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7247 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
7250 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7251 const struct intel_crtc_state
*pipe_config
)
7253 struct drm_device
*dev
= crtc
->base
.dev
;
7254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7255 int pipe
= crtc
->pipe
;
7257 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7258 u32 coreclk
, reg_val
;
7260 mutex_lock(&dev_priv
->sb_lock
);
7262 bestn
= pipe_config
->dpll
.n
;
7263 bestm1
= pipe_config
->dpll
.m1
;
7264 bestm2
= pipe_config
->dpll
.m2
;
7265 bestp1
= pipe_config
->dpll
.p1
;
7266 bestp2
= pipe_config
->dpll
.p2
;
7268 /* See eDP HDMI DPIO driver vbios notes doc */
7270 /* PLL B needs special handling */
7272 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7274 /* Set up Tx target for periodic Rcomp update */
7275 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7277 /* Disable target IRef on PLL */
7278 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7279 reg_val
&= 0x00ffffff;
7280 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7282 /* Disable fast lock */
7283 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7285 /* Set idtafcrecal before PLL is enabled */
7286 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7287 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7288 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7289 mdiv
|= (1 << DPIO_K_SHIFT
);
7292 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7293 * but we don't support that).
7294 * Note: don't use the DAC post divider as it seems unstable.
7296 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7297 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7299 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7300 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7302 /* Set HBR and RBR LPF coefficients */
7303 if (pipe_config
->port_clock
== 162000 ||
7304 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
7305 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
7306 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7309 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7312 if (pipe_config
->has_dp_encoder
) {
7313 /* Use SSC source */
7315 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7318 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7320 } else { /* HDMI or VGA */
7321 /* Use bend source */
7323 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7326 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7330 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7331 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7332 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
7333 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
7334 coreclk
|= 0x01000000;
7335 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7337 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7338 mutex_unlock(&dev_priv
->sb_lock
);
7341 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7342 struct intel_crtc_state
*pipe_config
)
7344 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7345 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
7347 if (crtc
->pipe
!= PIPE_A
)
7348 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7350 pipe_config
->dpll_hw_state
.dpll_md
=
7351 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7354 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7355 const struct intel_crtc_state
*pipe_config
)
7357 struct drm_device
*dev
= crtc
->base
.dev
;
7358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7359 int pipe
= crtc
->pipe
;
7360 int dpll_reg
= DPLL(crtc
->pipe
);
7361 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7362 u32 loopfilter
, tribuf_calcntr
;
7363 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7367 bestn
= pipe_config
->dpll
.n
;
7368 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7369 bestm1
= pipe_config
->dpll
.m1
;
7370 bestm2
= pipe_config
->dpll
.m2
>> 22;
7371 bestp1
= pipe_config
->dpll
.p1
;
7372 bestp2
= pipe_config
->dpll
.p2
;
7373 vco
= pipe_config
->dpll
.vco
;
7378 * Enable Refclk and SSC
7380 I915_WRITE(dpll_reg
,
7381 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7383 mutex_lock(&dev_priv
->sb_lock
);
7385 /* p1 and p2 divider */
7386 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7387 5 << DPIO_CHV_S1_DIV_SHIFT
|
7388 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7389 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7390 1 << DPIO_CHV_K_DIV_SHIFT
);
7392 /* Feedback post-divider - m2 */
7393 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7395 /* Feedback refclk divider - n and m1 */
7396 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7397 DPIO_CHV_M1_DIV_BY_2
|
7398 1 << DPIO_CHV_N_DIV_SHIFT
);
7400 /* M2 fraction division */
7401 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7403 /* M2 fraction division enable */
7404 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7405 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7406 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7408 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7409 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7411 /* Program digital lock detect threshold */
7412 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7413 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7414 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7415 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7417 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7418 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7421 if (vco
== 5400000) {
7422 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7423 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7424 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7425 tribuf_calcntr
= 0x9;
7426 } else if (vco
<= 6200000) {
7427 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7428 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7429 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7430 tribuf_calcntr
= 0x9;
7431 } else if (vco
<= 6480000) {
7432 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7433 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7434 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7435 tribuf_calcntr
= 0x8;
7437 /* Not supported. Apply the same limits as in the max case */
7438 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7439 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7440 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7443 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7445 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7446 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7447 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7448 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7451 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7452 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7455 mutex_unlock(&dev_priv
->sb_lock
);
7459 * vlv_force_pll_on - forcibly enable just the PLL
7460 * @dev_priv: i915 private structure
7461 * @pipe: pipe PLL to enable
7462 * @dpll: PLL configuration
7464 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7465 * in cases where we need the PLL enabled even when @pipe is not going to
7468 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7469 const struct dpll
*dpll
)
7471 struct intel_crtc
*crtc
=
7472 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7473 struct intel_crtc_state pipe_config
= {
7474 .base
.crtc
= &crtc
->base
,
7475 .pixel_multiplier
= 1,
7479 if (IS_CHERRYVIEW(dev
)) {
7480 chv_compute_dpll(crtc
, &pipe_config
);
7481 chv_prepare_pll(crtc
, &pipe_config
);
7482 chv_enable_pll(crtc
, &pipe_config
);
7484 vlv_compute_dpll(crtc
, &pipe_config
);
7485 vlv_prepare_pll(crtc
, &pipe_config
);
7486 vlv_enable_pll(crtc
, &pipe_config
);
7491 * vlv_force_pll_off - forcibly disable just the PLL
7492 * @dev_priv: i915 private structure
7493 * @pipe: pipe PLL to disable
7495 * Disable the PLL for @pipe. To be used in cases where we need
7496 * the PLL enabled even when @pipe is not going to be enabled.
7498 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7500 if (IS_CHERRYVIEW(dev
))
7501 chv_disable_pll(to_i915(dev
), pipe
);
7503 vlv_disable_pll(to_i915(dev
), pipe
);
7506 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
7507 struct intel_crtc_state
*crtc_state
,
7508 intel_clock_t
*reduced_clock
,
7511 struct drm_device
*dev
= crtc
->base
.dev
;
7512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7515 struct dpll
*clock
= &crtc_state
->dpll
;
7517 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7519 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7520 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
7522 dpll
= DPLL_VGA_MODE_DIS
;
7524 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7525 dpll
|= DPLLB_MODE_LVDS
;
7527 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7529 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7530 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7531 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7535 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7537 if (crtc_state
->has_dp_encoder
)
7538 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7540 /* compute bitmask from p1 value */
7541 if (IS_PINEVIEW(dev
))
7542 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7544 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7545 if (IS_G4X(dev
) && reduced_clock
)
7546 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7548 switch (clock
->p2
) {
7550 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7553 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7556 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7559 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7562 if (INTEL_INFO(dev
)->gen
>= 4)
7563 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7565 if (crtc_state
->sdvo_tv_clock
)
7566 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7567 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7568 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7569 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7571 dpll
|= PLL_REF_INPUT_DREFCLK
;
7573 dpll
|= DPLL_VCO_ENABLE
;
7574 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7576 if (INTEL_INFO(dev
)->gen
>= 4) {
7577 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7578 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7579 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7583 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
7584 struct intel_crtc_state
*crtc_state
,
7585 intel_clock_t
*reduced_clock
,
7588 struct drm_device
*dev
= crtc
->base
.dev
;
7589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7591 struct dpll
*clock
= &crtc_state
->dpll
;
7593 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7595 dpll
= DPLL_VGA_MODE_DIS
;
7597 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7598 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7601 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7603 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7605 dpll
|= PLL_P2_DIVIDE_BY_4
;
7608 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
7609 dpll
|= DPLL_DVO_2X_MODE
;
7611 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7612 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7613 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7615 dpll
|= PLL_REF_INPUT_DREFCLK
;
7617 dpll
|= DPLL_VCO_ENABLE
;
7618 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7621 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7623 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7625 enum pipe pipe
= intel_crtc
->pipe
;
7626 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7627 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
7628 uint32_t crtc_vtotal
, crtc_vblank_end
;
7631 /* We need to be careful not to changed the adjusted mode, for otherwise
7632 * the hw state checker will get angry at the mismatch. */
7633 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7634 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7636 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7637 /* the chip adds 2 halflines automatically */
7639 crtc_vblank_end
-= 1;
7641 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7642 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7644 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7645 adjusted_mode
->crtc_htotal
/ 2;
7647 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7650 if (INTEL_INFO(dev
)->gen
> 3)
7651 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7653 I915_WRITE(HTOTAL(cpu_transcoder
),
7654 (adjusted_mode
->crtc_hdisplay
- 1) |
7655 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7656 I915_WRITE(HBLANK(cpu_transcoder
),
7657 (adjusted_mode
->crtc_hblank_start
- 1) |
7658 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7659 I915_WRITE(HSYNC(cpu_transcoder
),
7660 (adjusted_mode
->crtc_hsync_start
- 1) |
7661 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7663 I915_WRITE(VTOTAL(cpu_transcoder
),
7664 (adjusted_mode
->crtc_vdisplay
- 1) |
7665 ((crtc_vtotal
- 1) << 16));
7666 I915_WRITE(VBLANK(cpu_transcoder
),
7667 (adjusted_mode
->crtc_vblank_start
- 1) |
7668 ((crtc_vblank_end
- 1) << 16));
7669 I915_WRITE(VSYNC(cpu_transcoder
),
7670 (adjusted_mode
->crtc_vsync_start
- 1) |
7671 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7673 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7674 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7675 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7677 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7678 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7679 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7681 /* pipesrc controls the size that is scaled from, which should
7682 * always be the user's requested size.
7684 I915_WRITE(PIPESRC(pipe
),
7685 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7686 (intel_crtc
->config
->pipe_src_h
- 1));
7689 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7690 struct intel_crtc_state
*pipe_config
)
7692 struct drm_device
*dev
= crtc
->base
.dev
;
7693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7694 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7697 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7698 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7699 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7700 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7701 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7702 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7703 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7704 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7705 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7707 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7708 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7709 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7710 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7711 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7712 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7713 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7714 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7715 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7717 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7718 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7719 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7720 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7723 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7724 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7725 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7727 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7728 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7731 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7732 struct intel_crtc_state
*pipe_config
)
7734 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7735 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7736 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7737 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7739 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7740 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7741 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7742 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7744 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7745 mode
->type
= DRM_MODE_TYPE_DRIVER
;
7747 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7748 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7750 mode
->hsync
= drm_mode_hsync(mode
);
7751 mode
->vrefresh
= drm_mode_vrefresh(mode
);
7752 drm_mode_set_name(mode
);
7755 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7757 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7763 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7764 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7765 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7767 if (intel_crtc
->config
->double_wide
)
7768 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7770 /* only g4x and later have fancy bpc/dither controls */
7771 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7772 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7773 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7774 pipeconf
|= PIPECONF_DITHER_EN
|
7775 PIPECONF_DITHER_TYPE_SP
;
7777 switch (intel_crtc
->config
->pipe_bpp
) {
7779 pipeconf
|= PIPECONF_6BPC
;
7782 pipeconf
|= PIPECONF_8BPC
;
7785 pipeconf
|= PIPECONF_10BPC
;
7788 /* Case prevented by intel_choose_pipe_bpp_dither. */
7793 if (HAS_PIPE_CXSR(dev
)) {
7794 if (intel_crtc
->lowfreq_avail
) {
7795 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7796 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7798 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7802 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7803 if (INTEL_INFO(dev
)->gen
< 4 ||
7804 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7805 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7807 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7809 pipeconf
|= PIPECONF_PROGRESSIVE
;
7811 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
7812 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7814 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7815 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7818 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7819 struct intel_crtc_state
*crtc_state
)
7821 struct drm_device
*dev
= crtc
->base
.dev
;
7822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7823 int refclk
, num_connectors
= 0;
7824 intel_clock_t clock
;
7826 bool is_dsi
= false;
7827 struct intel_encoder
*encoder
;
7828 const intel_limit_t
*limit
;
7829 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7830 struct drm_connector
*connector
;
7831 struct drm_connector_state
*connector_state
;
7834 memset(&crtc_state
->dpll_hw_state
, 0,
7835 sizeof(crtc_state
->dpll_hw_state
));
7837 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
7838 if (connector_state
->crtc
!= &crtc
->base
)
7841 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7843 switch (encoder
->type
) {
7844 case INTEL_OUTPUT_DSI
:
7857 if (!crtc_state
->clock_set
) {
7858 refclk
= i9xx_get_refclk(crtc_state
, num_connectors
);
7861 * Returns a set of divisors for the desired target clock with
7862 * the given refclk, or FALSE. The returned values represent
7863 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7866 limit
= intel_limit(crtc_state
, refclk
);
7867 ok
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
7868 crtc_state
->port_clock
,
7869 refclk
, NULL
, &clock
);
7871 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7875 /* Compat-code for transition, will disappear. */
7876 crtc_state
->dpll
.n
= clock
.n
;
7877 crtc_state
->dpll
.m1
= clock
.m1
;
7878 crtc_state
->dpll
.m2
= clock
.m2
;
7879 crtc_state
->dpll
.p1
= clock
.p1
;
7880 crtc_state
->dpll
.p2
= clock
.p2
;
7884 i8xx_compute_dpll(crtc
, crtc_state
, NULL
,
7886 } else if (IS_CHERRYVIEW(dev
)) {
7887 chv_compute_dpll(crtc
, crtc_state
);
7888 } else if (IS_VALLEYVIEW(dev
)) {
7889 vlv_compute_dpll(crtc
, crtc_state
);
7891 i9xx_compute_dpll(crtc
, crtc_state
, NULL
,
7898 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7899 struct intel_crtc_state
*pipe_config
)
7901 struct drm_device
*dev
= crtc
->base
.dev
;
7902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7905 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
7908 tmp
= I915_READ(PFIT_CONTROL
);
7909 if (!(tmp
& PFIT_ENABLE
))
7912 /* Check whether the pfit is attached to our pipe. */
7913 if (INTEL_INFO(dev
)->gen
< 4) {
7914 if (crtc
->pipe
!= PIPE_B
)
7917 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
7921 pipe_config
->gmch_pfit
.control
= tmp
;
7922 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
7923 if (INTEL_INFO(dev
)->gen
< 5)
7924 pipe_config
->gmch_pfit
.lvds_border_bits
=
7925 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
7928 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
7929 struct intel_crtc_state
*pipe_config
)
7931 struct drm_device
*dev
= crtc
->base
.dev
;
7932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7933 int pipe
= pipe_config
->cpu_transcoder
;
7934 intel_clock_t clock
;
7936 int refclk
= 100000;
7938 /* In case of MIPI DPLL will not even be used */
7939 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
7942 mutex_lock(&dev_priv
->sb_lock
);
7943 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
7944 mutex_unlock(&dev_priv
->sb_lock
);
7946 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
7947 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
7948 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
7949 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
7950 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
7952 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
7956 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
7957 struct intel_initial_plane_config
*plane_config
)
7959 struct drm_device
*dev
= crtc
->base
.dev
;
7960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7961 u32 val
, base
, offset
;
7962 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7963 int fourcc
, pixel_format
;
7964 unsigned int aligned_height
;
7965 struct drm_framebuffer
*fb
;
7966 struct intel_framebuffer
*intel_fb
;
7968 val
= I915_READ(DSPCNTR(plane
));
7969 if (!(val
& DISPLAY_PLANE_ENABLE
))
7972 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7974 DRM_DEBUG_KMS("failed to alloc fb\n");
7978 fb
= &intel_fb
->base
;
7980 if (INTEL_INFO(dev
)->gen
>= 4) {
7981 if (val
& DISPPLANE_TILED
) {
7982 plane_config
->tiling
= I915_TILING_X
;
7983 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
7987 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7988 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7989 fb
->pixel_format
= fourcc
;
7990 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7992 if (INTEL_INFO(dev
)->gen
>= 4) {
7993 if (plane_config
->tiling
)
7994 offset
= I915_READ(DSPTILEOFF(plane
));
7996 offset
= I915_READ(DSPLINOFF(plane
));
7997 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7999 base
= I915_READ(DSPADDR(plane
));
8001 plane_config
->base
= base
;
8003 val
= I915_READ(PIPESRC(pipe
));
8004 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8005 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8007 val
= I915_READ(DSPSTRIDE(pipe
));
8008 fb
->pitches
[0] = val
& 0xffffffc0;
8010 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8014 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8016 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8017 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
8018 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8019 plane_config
->size
);
8021 plane_config
->fb
= intel_fb
;
8024 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8025 struct intel_crtc_state
*pipe_config
)
8027 struct drm_device
*dev
= crtc
->base
.dev
;
8028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8029 int pipe
= pipe_config
->cpu_transcoder
;
8030 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8031 intel_clock_t clock
;
8032 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
8033 int refclk
= 100000;
8035 mutex_lock(&dev_priv
->sb_lock
);
8036 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8037 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8038 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8039 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8040 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8041 mutex_unlock(&dev_priv
->sb_lock
);
8043 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8044 clock
.m2
= (pll_dw0
& 0xff) << 22;
8045 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
8046 clock
.m2
|= pll_dw2
& 0x3fffff;
8047 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8048 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8049 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8051 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8054 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8055 struct intel_crtc_state
*pipe_config
)
8057 struct drm_device
*dev
= crtc
->base
.dev
;
8058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8061 if (!intel_display_power_is_enabled(dev_priv
,
8062 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8065 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8066 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8068 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8069 if (!(tmp
& PIPECONF_ENABLE
))
8072 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
8073 switch (tmp
& PIPECONF_BPC_MASK
) {
8075 pipe_config
->pipe_bpp
= 18;
8078 pipe_config
->pipe_bpp
= 24;
8080 case PIPECONF_10BPC
:
8081 pipe_config
->pipe_bpp
= 30;
8088 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8089 pipe_config
->limited_color_range
= true;
8091 if (INTEL_INFO(dev
)->gen
< 4)
8092 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8094 intel_get_pipe_timings(crtc
, pipe_config
);
8096 i9xx_get_pfit_config(crtc
, pipe_config
);
8098 if (INTEL_INFO(dev
)->gen
>= 4) {
8099 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8100 pipe_config
->pixel_multiplier
=
8101 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8102 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8103 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8104 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
8105 tmp
= I915_READ(DPLL(crtc
->pipe
));
8106 pipe_config
->pixel_multiplier
=
8107 ((tmp
& SDVO_MULTIPLIER_MASK
)
8108 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8110 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8111 * port and will be fixed up in the encoder->get_config
8113 pipe_config
->pixel_multiplier
= 1;
8115 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8116 if (!IS_VALLEYVIEW(dev
)) {
8118 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8119 * on 830. Filter it out here so that we don't
8120 * report errors due to that.
8123 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
8125 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8126 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8128 /* Mask out read-only status bits. */
8129 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8130 DPLL_PORTC_READY_MASK
|
8131 DPLL_PORTB_READY_MASK
);
8134 if (IS_CHERRYVIEW(dev
))
8135 chv_crtc_clock_get(crtc
, pipe_config
);
8136 else if (IS_VALLEYVIEW(dev
))
8137 vlv_crtc_clock_get(crtc
, pipe_config
);
8139 i9xx_crtc_clock_get(crtc
, pipe_config
);
8142 * Normally the dotclock is filled in by the encoder .get_config()
8143 * but in case the pipe is enabled w/o any ports we need a sane
8146 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8147 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8152 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
8154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8155 struct intel_encoder
*encoder
;
8157 bool has_lvds
= false;
8158 bool has_cpu_edp
= false;
8159 bool has_panel
= false;
8160 bool has_ck505
= false;
8161 bool can_ssc
= false;
8163 /* We need to take the global config into account */
8164 for_each_intel_encoder(dev
, encoder
) {
8165 switch (encoder
->type
) {
8166 case INTEL_OUTPUT_LVDS
:
8170 case INTEL_OUTPUT_EDP
:
8172 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
8180 if (HAS_PCH_IBX(dev
)) {
8181 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8182 can_ssc
= has_ck505
;
8188 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8189 has_panel
, has_lvds
, has_ck505
);
8191 /* Ironlake: try to setup display ref clock before DPLL
8192 * enabling. This is only under driver's control after
8193 * PCH B stepping, previous chipset stepping should be
8194 * ignoring this setting.
8196 val
= I915_READ(PCH_DREF_CONTROL
);
8198 /* As we must carefully and slowly disable/enable each source in turn,
8199 * compute the final state we want first and check if we need to
8200 * make any changes at all.
8203 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8205 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8207 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8209 final
&= ~DREF_SSC_SOURCE_MASK
;
8210 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8211 final
&= ~DREF_SSC1_ENABLE
;
8214 final
|= DREF_SSC_SOURCE_ENABLE
;
8216 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8217 final
|= DREF_SSC1_ENABLE
;
8220 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8221 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8223 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8225 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8227 final
|= DREF_SSC_SOURCE_DISABLE
;
8228 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8234 /* Always enable nonspread source */
8235 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8238 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8240 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8243 val
&= ~DREF_SSC_SOURCE_MASK
;
8244 val
|= DREF_SSC_SOURCE_ENABLE
;
8246 /* SSC must be turned on before enabling the CPU output */
8247 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8248 DRM_DEBUG_KMS("Using SSC on panel\n");
8249 val
|= DREF_SSC1_ENABLE
;
8251 val
&= ~DREF_SSC1_ENABLE
;
8253 /* Get SSC going before enabling the outputs */
8254 I915_WRITE(PCH_DREF_CONTROL
, val
);
8255 POSTING_READ(PCH_DREF_CONTROL
);
8258 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8260 /* Enable CPU source on CPU attached eDP */
8262 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8263 DRM_DEBUG_KMS("Using SSC on eDP\n");
8264 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8266 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8268 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8270 I915_WRITE(PCH_DREF_CONTROL
, val
);
8271 POSTING_READ(PCH_DREF_CONTROL
);
8274 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8276 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8278 /* Turn off CPU output */
8279 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8281 I915_WRITE(PCH_DREF_CONTROL
, val
);
8282 POSTING_READ(PCH_DREF_CONTROL
);
8285 /* Turn off the SSC source */
8286 val
&= ~DREF_SSC_SOURCE_MASK
;
8287 val
|= DREF_SSC_SOURCE_DISABLE
;
8290 val
&= ~DREF_SSC1_ENABLE
;
8292 I915_WRITE(PCH_DREF_CONTROL
, val
);
8293 POSTING_READ(PCH_DREF_CONTROL
);
8297 BUG_ON(val
!= final
);
8300 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8304 tmp
= I915_READ(SOUTH_CHICKEN2
);
8305 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8306 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8308 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
8309 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8310 DRM_ERROR("FDI mPHY reset assert timeout\n");
8312 tmp
= I915_READ(SOUTH_CHICKEN2
);
8313 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8314 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8316 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
8317 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8318 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8321 /* WaMPhyProgramming:hsw */
8322 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8326 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8327 tmp
&= ~(0xFF << 24);
8328 tmp
|= (0x12 << 24);
8329 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8331 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8333 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8335 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8337 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8339 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8340 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8341 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8343 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8344 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8345 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8347 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8350 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8352 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8355 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8357 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8360 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8362 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8365 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8367 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8368 tmp
&= ~(0xFF << 16);
8369 tmp
|= (0x1C << 16);
8370 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8372 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8373 tmp
&= ~(0xFF << 16);
8374 tmp
|= (0x1C << 16);
8375 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8377 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8379 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8381 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8383 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8385 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8386 tmp
&= ~(0xF << 28);
8388 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8390 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8391 tmp
&= ~(0xF << 28);
8393 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8396 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8397 * Programming" based on the parameters passed:
8398 * - Sequence to enable CLKOUT_DP
8399 * - Sequence to enable CLKOUT_DP without spread
8400 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8402 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8408 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8410 if (WARN(HAS_PCH_LPT_LP(dev
) && with_fdi
, "LP PCH doesn't have FDI\n"))
8413 mutex_lock(&dev_priv
->sb_lock
);
8415 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8416 tmp
&= ~SBI_SSCCTL_DISABLE
;
8417 tmp
|= SBI_SSCCTL_PATHALT
;
8418 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8423 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8424 tmp
&= ~SBI_SSCCTL_PATHALT
;
8425 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8428 lpt_reset_fdi_mphy(dev_priv
);
8429 lpt_program_fdi_mphy(dev_priv
);
8433 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8434 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8435 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8436 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8438 mutex_unlock(&dev_priv
->sb_lock
);
8441 /* Sequence to disable CLKOUT_DP */
8442 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8447 mutex_lock(&dev_priv
->sb_lock
);
8449 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8450 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8451 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8452 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8454 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8455 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8456 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8457 tmp
|= SBI_SSCCTL_PATHALT
;
8458 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8461 tmp
|= SBI_SSCCTL_DISABLE
;
8462 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8465 mutex_unlock(&dev_priv
->sb_lock
);
8468 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8470 struct intel_encoder
*encoder
;
8471 bool has_vga
= false;
8473 for_each_intel_encoder(dev
, encoder
) {
8474 switch (encoder
->type
) {
8475 case INTEL_OUTPUT_ANALOG
:
8484 lpt_enable_clkout_dp(dev
, true, true);
8486 lpt_disable_clkout_dp(dev
);
8490 * Initialize reference clocks when the driver loads
8492 void intel_init_pch_refclk(struct drm_device
*dev
)
8494 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8495 ironlake_init_pch_refclk(dev
);
8496 else if (HAS_PCH_LPT(dev
))
8497 lpt_init_pch_refclk(dev
);
8500 static int ironlake_get_refclk(struct intel_crtc_state
*crtc_state
)
8502 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
8503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8504 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8505 struct drm_connector
*connector
;
8506 struct drm_connector_state
*connector_state
;
8507 struct intel_encoder
*encoder
;
8508 int num_connectors
= 0, i
;
8509 bool is_lvds
= false;
8511 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8512 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8515 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8517 switch (encoder
->type
) {
8518 case INTEL_OUTPUT_LVDS
:
8527 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
8528 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8529 dev_priv
->vbt
.lvds_ssc_freq
);
8530 return dev_priv
->vbt
.lvds_ssc_freq
;
8536 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8538 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8539 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8540 int pipe
= intel_crtc
->pipe
;
8545 switch (intel_crtc
->config
->pipe_bpp
) {
8547 val
|= PIPECONF_6BPC
;
8550 val
|= PIPECONF_8BPC
;
8553 val
|= PIPECONF_10BPC
;
8556 val
|= PIPECONF_12BPC
;
8559 /* Case prevented by intel_choose_pipe_bpp_dither. */
8563 if (intel_crtc
->config
->dither
)
8564 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8566 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8567 val
|= PIPECONF_INTERLACED_ILK
;
8569 val
|= PIPECONF_PROGRESSIVE
;
8571 if (intel_crtc
->config
->limited_color_range
)
8572 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8574 I915_WRITE(PIPECONF(pipe
), val
);
8575 POSTING_READ(PIPECONF(pipe
));
8579 * Set up the pipe CSC unit.
8581 * Currently only full range RGB to limited range RGB conversion
8582 * is supported, but eventually this should handle various
8583 * RGB<->YCbCr scenarios as well.
8585 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
8587 struct drm_device
*dev
= crtc
->dev
;
8588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8589 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8590 int pipe
= intel_crtc
->pipe
;
8591 uint16_t coeff
= 0x7800; /* 1.0 */
8594 * TODO: Check what kind of values actually come out of the pipe
8595 * with these coeff/postoff values and adjust to get the best
8596 * accuracy. Perhaps we even need to take the bpc value into
8600 if (intel_crtc
->config
->limited_color_range
)
8601 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8604 * GY/GU and RY/RU should be the other way around according
8605 * to BSpec, but reality doesn't agree. Just set them up in
8606 * a way that results in the correct picture.
8608 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
8609 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
8611 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
8612 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
8614 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
8615 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
8617 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
8618 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
8619 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
8621 if (INTEL_INFO(dev
)->gen
> 6) {
8622 uint16_t postoff
= 0;
8624 if (intel_crtc
->config
->limited_color_range
)
8625 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
8627 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
8628 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
8629 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
8631 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
8633 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
8635 if (intel_crtc
->config
->limited_color_range
)
8636 mode
|= CSC_BLACK_SCREEN_OFFSET
;
8638 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
8642 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8644 struct drm_device
*dev
= crtc
->dev
;
8645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8646 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8647 enum pipe pipe
= intel_crtc
->pipe
;
8648 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8653 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
8654 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8656 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8657 val
|= PIPECONF_INTERLACED_ILK
;
8659 val
|= PIPECONF_PROGRESSIVE
;
8661 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8662 POSTING_READ(PIPECONF(cpu_transcoder
));
8664 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
8665 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
8667 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
8670 switch (intel_crtc
->config
->pipe_bpp
) {
8672 val
|= PIPEMISC_DITHER_6_BPC
;
8675 val
|= PIPEMISC_DITHER_8_BPC
;
8678 val
|= PIPEMISC_DITHER_10_BPC
;
8681 val
|= PIPEMISC_DITHER_12_BPC
;
8684 /* Case prevented by pipe_config_set_bpp. */
8688 if (intel_crtc
->config
->dither
)
8689 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8691 I915_WRITE(PIPEMISC(pipe
), val
);
8695 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
8696 struct intel_crtc_state
*crtc_state
,
8697 intel_clock_t
*clock
,
8698 bool *has_reduced_clock
,
8699 intel_clock_t
*reduced_clock
)
8701 struct drm_device
*dev
= crtc
->dev
;
8702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8704 const intel_limit_t
*limit
;
8707 refclk
= ironlake_get_refclk(crtc_state
);
8710 * Returns a set of divisors for the desired target clock with the given
8711 * refclk, or FALSE. The returned values represent the clock equation:
8712 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8714 limit
= intel_limit(crtc_state
, refclk
);
8715 ret
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
8716 crtc_state
->port_clock
,
8717 refclk
, NULL
, clock
);
8724 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8727 * Account for spread spectrum to avoid
8728 * oversubscribing the link. Max center spread
8729 * is 2.5%; use 5% for safety's sake.
8731 u32 bps
= target_clock
* bpp
* 21 / 20;
8732 return DIV_ROUND_UP(bps
, link_bw
* 8);
8735 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8737 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8740 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8741 struct intel_crtc_state
*crtc_state
,
8743 intel_clock_t
*reduced_clock
, u32
*fp2
)
8745 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8746 struct drm_device
*dev
= crtc
->dev
;
8747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8748 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8749 struct drm_connector
*connector
;
8750 struct drm_connector_state
*connector_state
;
8751 struct intel_encoder
*encoder
;
8753 int factor
, num_connectors
= 0, i
;
8754 bool is_lvds
= false, is_sdvo
= false;
8756 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8757 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8760 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8762 switch (encoder
->type
) {
8763 case INTEL_OUTPUT_LVDS
:
8766 case INTEL_OUTPUT_SDVO
:
8767 case INTEL_OUTPUT_HDMI
:
8777 /* Enable autotuning of the PLL clock (if permissible) */
8780 if ((intel_panel_use_ssc(dev_priv
) &&
8781 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8782 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8784 } else if (crtc_state
->sdvo_tv_clock
)
8787 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8790 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
8796 dpll
|= DPLLB_MODE_LVDS
;
8798 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8800 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8801 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8804 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8805 if (crtc_state
->has_dp_encoder
)
8806 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8808 /* compute bitmask from p1 value */
8809 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8811 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8813 switch (crtc_state
->dpll
.p2
) {
8815 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8818 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8821 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8824 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8828 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
8829 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8831 dpll
|= PLL_REF_INPUT_DREFCLK
;
8833 return dpll
| DPLL_VCO_ENABLE
;
8836 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8837 struct intel_crtc_state
*crtc_state
)
8839 struct drm_device
*dev
= crtc
->base
.dev
;
8840 intel_clock_t clock
, reduced_clock
;
8841 u32 dpll
= 0, fp
= 0, fp2
= 0;
8842 bool ok
, has_reduced_clock
= false;
8843 bool is_lvds
= false;
8844 struct intel_shared_dpll
*pll
;
8846 memset(&crtc_state
->dpll_hw_state
, 0,
8847 sizeof(crtc_state
->dpll_hw_state
));
8849 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
8851 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
8852 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
8854 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
8855 &has_reduced_clock
, &reduced_clock
);
8856 if (!ok
&& !crtc_state
->clock_set
) {
8857 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8860 /* Compat-code for transition, will disappear. */
8861 if (!crtc_state
->clock_set
) {
8862 crtc_state
->dpll
.n
= clock
.n
;
8863 crtc_state
->dpll
.m1
= clock
.m1
;
8864 crtc_state
->dpll
.m2
= clock
.m2
;
8865 crtc_state
->dpll
.p1
= clock
.p1
;
8866 crtc_state
->dpll
.p2
= clock
.p2
;
8869 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8870 if (crtc_state
->has_pch_encoder
) {
8871 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8872 if (has_reduced_clock
)
8873 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
8875 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
8876 &fp
, &reduced_clock
,
8877 has_reduced_clock
? &fp2
: NULL
);
8879 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8880 crtc_state
->dpll_hw_state
.fp0
= fp
;
8881 if (has_reduced_clock
)
8882 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8884 crtc_state
->dpll_hw_state
.fp1
= fp
;
8886 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
8888 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8889 pipe_name(crtc
->pipe
));
8894 if (is_lvds
&& has_reduced_clock
)
8895 crtc
->lowfreq_avail
= true;
8897 crtc
->lowfreq_avail
= false;
8902 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
8903 struct intel_link_m_n
*m_n
)
8905 struct drm_device
*dev
= crtc
->base
.dev
;
8906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8907 enum pipe pipe
= crtc
->pipe
;
8909 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
8910 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
8911 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
8913 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
8914 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
8915 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8918 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
8919 enum transcoder transcoder
,
8920 struct intel_link_m_n
*m_n
,
8921 struct intel_link_m_n
*m2_n2
)
8923 struct drm_device
*dev
= crtc
->base
.dev
;
8924 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8925 enum pipe pipe
= crtc
->pipe
;
8927 if (INTEL_INFO(dev
)->gen
>= 5) {
8928 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8929 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8930 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8932 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8933 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8934 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8935 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8936 * gen < 8) and if DRRS is supported (to make sure the
8937 * registers are not unnecessarily read).
8939 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
8940 crtc
->config
->has_drrs
) {
8941 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
8942 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
8943 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
8945 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
8946 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
8947 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8950 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
8951 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
8952 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
8954 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
8955 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
8956 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8960 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
8961 struct intel_crtc_state
*pipe_config
)
8963 if (pipe_config
->has_pch_encoder
)
8964 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
8966 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8967 &pipe_config
->dp_m_n
,
8968 &pipe_config
->dp_m2_n2
);
8971 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
8972 struct intel_crtc_state
*pipe_config
)
8974 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8975 &pipe_config
->fdi_m_n
, NULL
);
8978 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
8979 struct intel_crtc_state
*pipe_config
)
8981 struct drm_device
*dev
= crtc
->base
.dev
;
8982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8983 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
8984 uint32_t ps_ctrl
= 0;
8988 /* find scaler attached to this pipe */
8989 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
8990 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
8991 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
8993 pipe_config
->pch_pfit
.enabled
= true;
8994 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
8995 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9000 scaler_state
->scaler_id
= id
;
9002 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9004 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9009 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9010 struct intel_initial_plane_config
*plane_config
)
9012 struct drm_device
*dev
= crtc
->base
.dev
;
9013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9014 u32 val
, base
, offset
, stride_mult
, tiling
;
9015 int pipe
= crtc
->pipe
;
9016 int fourcc
, pixel_format
;
9017 unsigned int aligned_height
;
9018 struct drm_framebuffer
*fb
;
9019 struct intel_framebuffer
*intel_fb
;
9021 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9023 DRM_DEBUG_KMS("failed to alloc fb\n");
9027 fb
= &intel_fb
->base
;
9029 val
= I915_READ(PLANE_CTL(pipe
, 0));
9030 if (!(val
& PLANE_CTL_ENABLE
))
9033 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9034 fourcc
= skl_format_to_fourcc(pixel_format
,
9035 val
& PLANE_CTL_ORDER_RGBX
,
9036 val
& PLANE_CTL_ALPHA_MASK
);
9037 fb
->pixel_format
= fourcc
;
9038 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9040 tiling
= val
& PLANE_CTL_TILED_MASK
;
9042 case PLANE_CTL_TILED_LINEAR
:
9043 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
9045 case PLANE_CTL_TILED_X
:
9046 plane_config
->tiling
= I915_TILING_X
;
9047 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9049 case PLANE_CTL_TILED_Y
:
9050 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
9052 case PLANE_CTL_TILED_YF
:
9053 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
9056 MISSING_CASE(tiling
);
9060 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
9061 plane_config
->base
= base
;
9063 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
9065 val
= I915_READ(PLANE_SIZE(pipe
, 0));
9066 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9067 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9069 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
9070 stride_mult
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
9072 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9074 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9078 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9080 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9081 pipe_name(pipe
), fb
->width
, fb
->height
,
9082 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9083 plane_config
->size
);
9085 plane_config
->fb
= intel_fb
;
9092 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9093 struct intel_crtc_state
*pipe_config
)
9095 struct drm_device
*dev
= crtc
->base
.dev
;
9096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9099 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9101 if (tmp
& PF_ENABLE
) {
9102 pipe_config
->pch_pfit
.enabled
= true;
9103 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9104 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9106 /* We currently do not free assignements of panel fitters on
9107 * ivb/hsw (since we don't use the higher upscaling modes which
9108 * differentiates them) so just WARN about this case for now. */
9110 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9111 PF_PIPE_SEL_IVB(crtc
->pipe
));
9117 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
9118 struct intel_initial_plane_config
*plane_config
)
9120 struct drm_device
*dev
= crtc
->base
.dev
;
9121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9122 u32 val
, base
, offset
;
9123 int pipe
= crtc
->pipe
;
9124 int fourcc
, pixel_format
;
9125 unsigned int aligned_height
;
9126 struct drm_framebuffer
*fb
;
9127 struct intel_framebuffer
*intel_fb
;
9129 val
= I915_READ(DSPCNTR(pipe
));
9130 if (!(val
& DISPLAY_PLANE_ENABLE
))
9133 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9135 DRM_DEBUG_KMS("failed to alloc fb\n");
9139 fb
= &intel_fb
->base
;
9141 if (INTEL_INFO(dev
)->gen
>= 4) {
9142 if (val
& DISPPLANE_TILED
) {
9143 plane_config
->tiling
= I915_TILING_X
;
9144 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9148 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
9149 fourcc
= i9xx_format_to_fourcc(pixel_format
);
9150 fb
->pixel_format
= fourcc
;
9151 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9153 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
9154 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
9155 offset
= I915_READ(DSPOFFSET(pipe
));
9157 if (plane_config
->tiling
)
9158 offset
= I915_READ(DSPTILEOFF(pipe
));
9160 offset
= I915_READ(DSPLINOFF(pipe
));
9162 plane_config
->base
= base
;
9164 val
= I915_READ(PIPESRC(pipe
));
9165 fb
->width
= ((val
>> 16) & 0xfff) + 1;
9166 fb
->height
= ((val
>> 0) & 0xfff) + 1;
9168 val
= I915_READ(DSPSTRIDE(pipe
));
9169 fb
->pitches
[0] = val
& 0xffffffc0;
9171 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9175 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9177 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9178 pipe_name(pipe
), fb
->width
, fb
->height
,
9179 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9180 plane_config
->size
);
9182 plane_config
->fb
= intel_fb
;
9185 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9186 struct intel_crtc_state
*pipe_config
)
9188 struct drm_device
*dev
= crtc
->base
.dev
;
9189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9192 if (!intel_display_power_is_enabled(dev_priv
,
9193 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9196 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9197 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9199 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9200 if (!(tmp
& PIPECONF_ENABLE
))
9203 switch (tmp
& PIPECONF_BPC_MASK
) {
9205 pipe_config
->pipe_bpp
= 18;
9208 pipe_config
->pipe_bpp
= 24;
9210 case PIPECONF_10BPC
:
9211 pipe_config
->pipe_bpp
= 30;
9213 case PIPECONF_12BPC
:
9214 pipe_config
->pipe_bpp
= 36;
9220 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9221 pipe_config
->limited_color_range
= true;
9223 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9224 struct intel_shared_dpll
*pll
;
9226 pipe_config
->has_pch_encoder
= true;
9228 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9229 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9230 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9232 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9234 if (HAS_PCH_IBX(dev_priv
->dev
)) {
9235 pipe_config
->shared_dpll
=
9236 (enum intel_dpll_id
) crtc
->pipe
;
9238 tmp
= I915_READ(PCH_DPLL_SEL
);
9239 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9240 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
9242 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
9245 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9247 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9248 &pipe_config
->dpll_hw_state
));
9250 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9251 pipe_config
->pixel_multiplier
=
9252 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9253 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9255 ironlake_pch_clock_get(crtc
, pipe_config
);
9257 pipe_config
->pixel_multiplier
= 1;
9260 intel_get_pipe_timings(crtc
, pipe_config
);
9262 ironlake_get_pfit_config(crtc
, pipe_config
);
9267 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
9269 struct drm_device
*dev
= dev_priv
->dev
;
9270 struct intel_crtc
*crtc
;
9272 for_each_intel_crtc(dev
, crtc
)
9273 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
9274 pipe_name(crtc
->pipe
));
9276 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
9277 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
9278 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
9279 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
9280 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
9281 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
9282 "CPU PWM1 enabled\n");
9283 if (IS_HASWELL(dev
))
9284 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
9285 "CPU PWM2 enabled\n");
9286 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
9287 "PCH PWM1 enabled\n");
9288 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
9289 "Utility pin enabled\n");
9290 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
9293 * In theory we can still leave IRQs enabled, as long as only the HPD
9294 * interrupts remain enabled. We used to check for that, but since it's
9295 * gen-specific and since we only disable LCPLL after we fully disable
9296 * the interrupts, the check below should be enough.
9298 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
9301 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
9303 struct drm_device
*dev
= dev_priv
->dev
;
9305 if (IS_HASWELL(dev
))
9306 return I915_READ(D_COMP_HSW
);
9308 return I915_READ(D_COMP_BDW
);
9311 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
9313 struct drm_device
*dev
= dev_priv
->dev
;
9315 if (IS_HASWELL(dev
)) {
9316 mutex_lock(&dev_priv
->rps
.hw_lock
);
9317 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
9319 DRM_ERROR("Failed to write to D_COMP\n");
9320 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9322 I915_WRITE(D_COMP_BDW
, val
);
9323 POSTING_READ(D_COMP_BDW
);
9328 * This function implements pieces of two sequences from BSpec:
9329 * - Sequence for display software to disable LCPLL
9330 * - Sequence for display software to allow package C8+
9331 * The steps implemented here are just the steps that actually touch the LCPLL
9332 * register. Callers should take care of disabling all the display engine
9333 * functions, doing the mode unset, fixing interrupts, etc.
9335 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9336 bool switch_to_fclk
, bool allow_power_down
)
9340 assert_can_disable_lcpll(dev_priv
);
9342 val
= I915_READ(LCPLL_CTL
);
9344 if (switch_to_fclk
) {
9345 val
|= LCPLL_CD_SOURCE_FCLK
;
9346 I915_WRITE(LCPLL_CTL
, val
);
9348 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9349 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9350 DRM_ERROR("Switching to FCLK failed\n");
9352 val
= I915_READ(LCPLL_CTL
);
9355 val
|= LCPLL_PLL_DISABLE
;
9356 I915_WRITE(LCPLL_CTL
, val
);
9357 POSTING_READ(LCPLL_CTL
);
9359 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
9360 DRM_ERROR("LCPLL still locked\n");
9362 val
= hsw_read_dcomp(dev_priv
);
9363 val
|= D_COMP_COMP_DISABLE
;
9364 hsw_write_dcomp(dev_priv
, val
);
9367 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9369 DRM_ERROR("D_COMP RCOMP still in progress\n");
9371 if (allow_power_down
) {
9372 val
= I915_READ(LCPLL_CTL
);
9373 val
|= LCPLL_POWER_DOWN_ALLOW
;
9374 I915_WRITE(LCPLL_CTL
, val
);
9375 POSTING_READ(LCPLL_CTL
);
9380 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9383 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9387 val
= I915_READ(LCPLL_CTL
);
9389 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9390 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9394 * Make sure we're not on PC8 state before disabling PC8, otherwise
9395 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9397 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9399 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9400 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9401 I915_WRITE(LCPLL_CTL
, val
);
9402 POSTING_READ(LCPLL_CTL
);
9405 val
= hsw_read_dcomp(dev_priv
);
9406 val
|= D_COMP_COMP_FORCE
;
9407 val
&= ~D_COMP_COMP_DISABLE
;
9408 hsw_write_dcomp(dev_priv
, val
);
9410 val
= I915_READ(LCPLL_CTL
);
9411 val
&= ~LCPLL_PLL_DISABLE
;
9412 I915_WRITE(LCPLL_CTL
, val
);
9414 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
9415 DRM_ERROR("LCPLL not locked yet\n");
9417 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9418 val
= I915_READ(LCPLL_CTL
);
9419 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9420 I915_WRITE(LCPLL_CTL
, val
);
9422 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9423 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9424 DRM_ERROR("Switching back to LCPLL failed\n");
9427 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9428 intel_update_cdclk(dev_priv
->dev
);
9432 * Package states C8 and deeper are really deep PC states that can only be
9433 * reached when all the devices on the system allow it, so even if the graphics
9434 * device allows PC8+, it doesn't mean the system will actually get to these
9435 * states. Our driver only allows PC8+ when going into runtime PM.
9437 * The requirements for PC8+ are that all the outputs are disabled, the power
9438 * well is disabled and most interrupts are disabled, and these are also
9439 * requirements for runtime PM. When these conditions are met, we manually do
9440 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9441 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9444 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9445 * the state of some registers, so when we come back from PC8+ we need to
9446 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9447 * need to take care of the registers kept by RC6. Notice that this happens even
9448 * if we don't put the device in PCI D3 state (which is what currently happens
9449 * because of the runtime PM support).
9451 * For more, read "Display Sequences for Package C8" on the hardware
9454 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9456 struct drm_device
*dev
= dev_priv
->dev
;
9459 DRM_DEBUG_KMS("Enabling package C8+\n");
9461 if (HAS_PCH_LPT_LP(dev
)) {
9462 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9463 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9464 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9467 lpt_disable_clkout_dp(dev
);
9468 hsw_disable_lcpll(dev_priv
, true, true);
9471 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9473 struct drm_device
*dev
= dev_priv
->dev
;
9476 DRM_DEBUG_KMS("Disabling package C8+\n");
9478 hsw_restore_lcpll(dev_priv
);
9479 lpt_init_pch_refclk(dev
);
9481 if (HAS_PCH_LPT_LP(dev
)) {
9482 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9483 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9484 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9487 intel_prepare_ddi(dev
);
9490 static void broxton_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9492 struct drm_device
*dev
= old_state
->dev
;
9493 unsigned int req_cdclk
= to_intel_atomic_state(old_state
)->cdclk
;
9495 broxton_set_cdclk(dev
, req_cdclk
);
9498 /* compute the max rate for new configuration */
9499 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
)
9501 struct intel_crtc
*intel_crtc
;
9502 struct intel_crtc_state
*crtc_state
;
9503 int max_pixel_rate
= 0;
9505 for_each_intel_crtc(state
->dev
, intel_crtc
) {
9508 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
9509 if (IS_ERR(crtc_state
))
9510 return PTR_ERR(crtc_state
);
9512 if (!crtc_state
->base
.enable
)
9515 pixel_rate
= ilk_pipe_pixel_rate(crtc_state
);
9517 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9518 if (IS_BROADWELL(state
->dev
) && crtc_state
->ips_enabled
)
9519 pixel_rate
= DIV_ROUND_UP(pixel_rate
* 100, 95);
9521 max_pixel_rate
= max(max_pixel_rate
, pixel_rate
);
9524 return max_pixel_rate
;
9527 static void broadwell_set_cdclk(struct drm_device
*dev
, int cdclk
)
9529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9533 if (WARN((I915_READ(LCPLL_CTL
) &
9534 (LCPLL_PLL_DISABLE
| LCPLL_PLL_LOCK
|
9535 LCPLL_CD_CLOCK_DISABLE
| LCPLL_ROOT_CD_CLOCK_DISABLE
|
9536 LCPLL_CD2X_CLOCK_DISABLE
| LCPLL_POWER_DOWN_ALLOW
|
9537 LCPLL_CD_SOURCE_FCLK
)) != LCPLL_PLL_LOCK
,
9538 "trying to change cdclk frequency with cdclk not enabled\n"))
9541 mutex_lock(&dev_priv
->rps
.hw_lock
);
9542 ret
= sandybridge_pcode_write(dev_priv
,
9543 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
, 0x0);
9544 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9546 DRM_ERROR("failed to inform pcode about cdclk change\n");
9550 val
= I915_READ(LCPLL_CTL
);
9551 val
|= LCPLL_CD_SOURCE_FCLK
;
9552 I915_WRITE(LCPLL_CTL
, val
);
9554 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9555 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9556 DRM_ERROR("Switching to FCLK failed\n");
9558 val
= I915_READ(LCPLL_CTL
);
9559 val
&= ~LCPLL_CLK_FREQ_MASK
;
9563 val
|= LCPLL_CLK_FREQ_450
;
9567 val
|= LCPLL_CLK_FREQ_54O_BDW
;
9571 val
|= LCPLL_CLK_FREQ_337_5_BDW
;
9575 val
|= LCPLL_CLK_FREQ_675_BDW
;
9579 WARN(1, "invalid cdclk frequency\n");
9583 I915_WRITE(LCPLL_CTL
, val
);
9585 val
= I915_READ(LCPLL_CTL
);
9586 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9587 I915_WRITE(LCPLL_CTL
, val
);
9589 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9590 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9591 DRM_ERROR("Switching back to LCPLL failed\n");
9593 mutex_lock(&dev_priv
->rps
.hw_lock
);
9594 sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
, data
);
9595 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9597 intel_update_cdclk(dev
);
9599 WARN(cdclk
!= dev_priv
->cdclk_freq
,
9600 "cdclk requested %d kHz but got %d kHz\n",
9601 cdclk
, dev_priv
->cdclk_freq
);
9604 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state
*state
)
9606 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9607 int max_pixclk
= ilk_max_pixel_rate(state
);
9611 * FIXME should also account for plane ratio
9612 * once 64bpp pixel formats are supported.
9614 if (max_pixclk
> 540000)
9616 else if (max_pixclk
> 450000)
9618 else if (max_pixclk
> 337500)
9624 * FIXME move the cdclk caclulation to
9625 * compute_config() so we can fail gracegully.
9627 if (cdclk
> dev_priv
->max_cdclk_freq
) {
9628 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9629 cdclk
, dev_priv
->max_cdclk_freq
);
9630 cdclk
= dev_priv
->max_cdclk_freq
;
9633 to_intel_atomic_state(state
)->cdclk
= cdclk
;
9638 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9640 struct drm_device
*dev
= old_state
->dev
;
9641 unsigned int req_cdclk
= to_intel_atomic_state(old_state
)->cdclk
;
9643 broadwell_set_cdclk(dev
, req_cdclk
);
9646 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9647 struct intel_crtc_state
*crtc_state
)
9649 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9652 crtc
->lowfreq_avail
= false;
9657 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9659 struct intel_crtc_state
*pipe_config
)
9663 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9664 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9667 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9668 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9671 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9672 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9675 DRM_ERROR("Incorrect port type\n");
9679 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9681 struct intel_crtc_state
*pipe_config
)
9683 u32 temp
, dpll_ctl1
;
9685 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9686 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9688 switch (pipe_config
->ddi_pll_sel
) {
9691 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9692 * of the shared DPLL framework and thus needs to be read out
9695 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
9696 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
9699 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9702 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9705 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9710 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9712 struct intel_crtc_state
*pipe_config
)
9714 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9716 switch (pipe_config
->ddi_pll_sel
) {
9717 case PORT_CLK_SEL_WRPLL1
:
9718 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
9720 case PORT_CLK_SEL_WRPLL2
:
9721 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
9726 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9727 struct intel_crtc_state
*pipe_config
)
9729 struct drm_device
*dev
= crtc
->base
.dev
;
9730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9731 struct intel_shared_dpll
*pll
;
9735 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9737 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9739 if (IS_SKYLAKE(dev
))
9740 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9741 else if (IS_BROXTON(dev
))
9742 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9744 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9746 if (pipe_config
->shared_dpll
>= 0) {
9747 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9749 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9750 &pipe_config
->dpll_hw_state
));
9754 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9755 * DDI E. So just check whether this pipe is wired to DDI E and whether
9756 * the PCH transcoder is on.
9758 if (INTEL_INFO(dev
)->gen
< 9 &&
9759 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9760 pipe_config
->has_pch_encoder
= true;
9762 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9763 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9764 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9766 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9770 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9771 struct intel_crtc_state
*pipe_config
)
9773 struct drm_device
*dev
= crtc
->base
.dev
;
9774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9775 enum intel_display_power_domain pfit_domain
;
9778 if (!intel_display_power_is_enabled(dev_priv
,
9779 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9782 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9783 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9785 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9786 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9787 enum pipe trans_edp_pipe
;
9788 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9790 WARN(1, "unknown pipe linked to edp transcoder\n");
9791 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9792 case TRANS_DDI_EDP_INPUT_A_ON
:
9793 trans_edp_pipe
= PIPE_A
;
9795 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9796 trans_edp_pipe
= PIPE_B
;
9798 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9799 trans_edp_pipe
= PIPE_C
;
9803 if (trans_edp_pipe
== crtc
->pipe
)
9804 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9807 if (!intel_display_power_is_enabled(dev_priv
,
9808 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
9811 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9812 if (!(tmp
& PIPECONF_ENABLE
))
9815 haswell_get_ddi_port_state(crtc
, pipe_config
);
9817 intel_get_pipe_timings(crtc
, pipe_config
);
9819 if (INTEL_INFO(dev
)->gen
>= 9) {
9820 skl_init_scalers(dev
, crtc
, pipe_config
);
9823 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
9825 if (INTEL_INFO(dev
)->gen
>= 9) {
9826 pipe_config
->scaler_state
.scaler_id
= -1;
9827 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9830 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
9831 if (INTEL_INFO(dev
)->gen
>= 9)
9832 skylake_get_pfit_config(crtc
, pipe_config
);
9834 ironlake_get_pfit_config(crtc
, pipe_config
);
9837 if (IS_HASWELL(dev
))
9838 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
9839 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
9841 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
9842 pipe_config
->pixel_multiplier
=
9843 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
9845 pipe_config
->pixel_multiplier
= 1;
9851 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9853 struct drm_device
*dev
= crtc
->dev
;
9854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9855 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9856 uint32_t cntl
= 0, size
= 0;
9859 unsigned int width
= intel_crtc
->base
.cursor
->state
->crtc_w
;
9860 unsigned int height
= intel_crtc
->base
.cursor
->state
->crtc_h
;
9861 unsigned int stride
= roundup_pow_of_two(width
) * 4;
9865 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9876 cntl
|= CURSOR_ENABLE
|
9877 CURSOR_GAMMA_ENABLE
|
9878 CURSOR_FORMAT_ARGB
|
9879 CURSOR_STRIDE(stride
);
9881 size
= (height
<< 12) | width
;
9884 if (intel_crtc
->cursor_cntl
!= 0 &&
9885 (intel_crtc
->cursor_base
!= base
||
9886 intel_crtc
->cursor_size
!= size
||
9887 intel_crtc
->cursor_cntl
!= cntl
)) {
9888 /* On these chipsets we can only modify the base/size/stride
9889 * whilst the cursor is disabled.
9891 I915_WRITE(_CURACNTR
, 0);
9892 POSTING_READ(_CURACNTR
);
9893 intel_crtc
->cursor_cntl
= 0;
9896 if (intel_crtc
->cursor_base
!= base
) {
9897 I915_WRITE(_CURABASE
, base
);
9898 intel_crtc
->cursor_base
= base
;
9901 if (intel_crtc
->cursor_size
!= size
) {
9902 I915_WRITE(CURSIZE
, size
);
9903 intel_crtc
->cursor_size
= size
;
9906 if (intel_crtc
->cursor_cntl
!= cntl
) {
9907 I915_WRITE(_CURACNTR
, cntl
);
9908 POSTING_READ(_CURACNTR
);
9909 intel_crtc
->cursor_cntl
= cntl
;
9913 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9915 struct drm_device
*dev
= crtc
->dev
;
9916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9917 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9918 int pipe
= intel_crtc
->pipe
;
9923 cntl
= MCURSOR_GAMMA_ENABLE
;
9924 switch (intel_crtc
->base
.cursor
->state
->crtc_w
) {
9926 cntl
|= CURSOR_MODE_64_ARGB_AX
;
9929 cntl
|= CURSOR_MODE_128_ARGB_AX
;
9932 cntl
|= CURSOR_MODE_256_ARGB_AX
;
9935 MISSING_CASE(intel_crtc
->base
.cursor
->state
->crtc_w
);
9938 cntl
|= pipe
<< 28; /* Connect to correct pipe */
9940 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
9941 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
9944 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
9945 cntl
|= CURSOR_ROTATE_180
;
9947 if (intel_crtc
->cursor_cntl
!= cntl
) {
9948 I915_WRITE(CURCNTR(pipe
), cntl
);
9949 POSTING_READ(CURCNTR(pipe
));
9950 intel_crtc
->cursor_cntl
= cntl
;
9953 /* and commit changes on next vblank */
9954 I915_WRITE(CURBASE(pipe
), base
);
9955 POSTING_READ(CURBASE(pipe
));
9957 intel_crtc
->cursor_base
= base
;
9960 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9961 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
9964 struct drm_device
*dev
= crtc
->dev
;
9965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9966 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9967 int pipe
= intel_crtc
->pipe
;
9968 struct drm_plane_state
*cursor_state
= crtc
->cursor
->state
;
9969 int x
= cursor_state
->crtc_x
;
9970 int y
= cursor_state
->crtc_y
;
9971 u32 base
= 0, pos
= 0;
9974 base
= intel_crtc
->cursor_addr
;
9976 if (x
>= intel_crtc
->config
->pipe_src_w
)
9979 if (y
>= intel_crtc
->config
->pipe_src_h
)
9983 if (x
+ cursor_state
->crtc_w
<= 0)
9986 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
9989 pos
|= x
<< CURSOR_X_SHIFT
;
9992 if (y
+ cursor_state
->crtc_h
<= 0)
9995 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
9998 pos
|= y
<< CURSOR_Y_SHIFT
;
10000 if (base
== 0 && intel_crtc
->cursor_base
== 0)
10003 I915_WRITE(CURPOS(pipe
), pos
);
10005 /* ILK+ do this automagically */
10006 if (HAS_GMCH_DISPLAY(dev
) &&
10007 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
10008 base
+= (cursor_state
->crtc_h
*
10009 cursor_state
->crtc_w
- 1) * 4;
10012 if (IS_845G(dev
) || IS_I865G(dev
))
10013 i845_update_cursor(crtc
, base
);
10015 i9xx_update_cursor(crtc
, base
);
10018 static bool cursor_size_ok(struct drm_device
*dev
,
10019 uint32_t width
, uint32_t height
)
10021 if (width
== 0 || height
== 0)
10025 * 845g/865g are special in that they are only limited by
10026 * the width of their cursors, the height is arbitrary up to
10027 * the precision of the register. Everything else requires
10028 * square cursors, limited to a few power-of-two sizes.
10030 if (IS_845G(dev
) || IS_I865G(dev
)) {
10031 if ((width
& 63) != 0)
10034 if (width
> (IS_845G(dev
) ? 64 : 512))
10040 switch (width
| height
) {
10055 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
10056 u16
*blue
, uint32_t start
, uint32_t size
)
10058 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
10059 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10061 for (i
= start
; i
< end
; i
++) {
10062 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
10063 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
10064 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
10067 intel_crtc_load_lut(crtc
);
10070 /* VESA 640x480x72Hz mode to set on the pipe */
10071 static struct drm_display_mode load_detect_mode
= {
10072 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10073 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10076 struct drm_framebuffer
*
10077 __intel_framebuffer_create(struct drm_device
*dev
,
10078 struct drm_mode_fb_cmd2
*mode_cmd
,
10079 struct drm_i915_gem_object
*obj
)
10081 struct intel_framebuffer
*intel_fb
;
10084 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10086 drm_gem_object_unreference(&obj
->base
);
10087 return ERR_PTR(-ENOMEM
);
10090 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
10094 return &intel_fb
->base
;
10096 drm_gem_object_unreference(&obj
->base
);
10099 return ERR_PTR(ret
);
10102 static struct drm_framebuffer
*
10103 intel_framebuffer_create(struct drm_device
*dev
,
10104 struct drm_mode_fb_cmd2
*mode_cmd
,
10105 struct drm_i915_gem_object
*obj
)
10107 struct drm_framebuffer
*fb
;
10110 ret
= i915_mutex_lock_interruptible(dev
);
10112 return ERR_PTR(ret
);
10113 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
10114 mutex_unlock(&dev
->struct_mutex
);
10120 intel_framebuffer_pitch_for_width(int width
, int bpp
)
10122 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
10123 return ALIGN(pitch
, 64);
10127 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
10129 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
10130 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
10133 static struct drm_framebuffer
*
10134 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
10135 struct drm_display_mode
*mode
,
10136 int depth
, int bpp
)
10138 struct drm_i915_gem_object
*obj
;
10139 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
10141 obj
= i915_gem_alloc_object(dev
,
10142 intel_framebuffer_size_for_mode(mode
, bpp
));
10144 return ERR_PTR(-ENOMEM
);
10146 mode_cmd
.width
= mode
->hdisplay
;
10147 mode_cmd
.height
= mode
->vdisplay
;
10148 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
10150 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
10152 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
10155 static struct drm_framebuffer
*
10156 mode_fits_in_fbdev(struct drm_device
*dev
,
10157 struct drm_display_mode
*mode
)
10159 #ifdef CONFIG_DRM_FBDEV_EMULATION
10160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10161 struct drm_i915_gem_object
*obj
;
10162 struct drm_framebuffer
*fb
;
10164 if (!dev_priv
->fbdev
)
10167 if (!dev_priv
->fbdev
->fb
)
10170 obj
= dev_priv
->fbdev
->fb
->obj
;
10173 fb
= &dev_priv
->fbdev
->fb
->base
;
10174 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
10175 fb
->bits_per_pixel
))
10178 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
10187 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
10188 struct drm_crtc
*crtc
,
10189 struct drm_display_mode
*mode
,
10190 struct drm_framebuffer
*fb
,
10193 struct drm_plane_state
*plane_state
;
10194 int hdisplay
, vdisplay
;
10197 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
10198 if (IS_ERR(plane_state
))
10199 return PTR_ERR(plane_state
);
10202 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
10204 hdisplay
= vdisplay
= 0;
10206 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
10209 drm_atomic_set_fb_for_plane(plane_state
, fb
);
10210 plane_state
->crtc_x
= 0;
10211 plane_state
->crtc_y
= 0;
10212 plane_state
->crtc_w
= hdisplay
;
10213 plane_state
->crtc_h
= vdisplay
;
10214 plane_state
->src_x
= x
<< 16;
10215 plane_state
->src_y
= y
<< 16;
10216 plane_state
->src_w
= hdisplay
<< 16;
10217 plane_state
->src_h
= vdisplay
<< 16;
10222 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
10223 struct drm_display_mode
*mode
,
10224 struct intel_load_detect_pipe
*old
,
10225 struct drm_modeset_acquire_ctx
*ctx
)
10227 struct intel_crtc
*intel_crtc
;
10228 struct intel_encoder
*intel_encoder
=
10229 intel_attached_encoder(connector
);
10230 struct drm_crtc
*possible_crtc
;
10231 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10232 struct drm_crtc
*crtc
= NULL
;
10233 struct drm_device
*dev
= encoder
->dev
;
10234 struct drm_framebuffer
*fb
;
10235 struct drm_mode_config
*config
= &dev
->mode_config
;
10236 struct drm_atomic_state
*state
= NULL
;
10237 struct drm_connector_state
*connector_state
;
10238 struct intel_crtc_state
*crtc_state
;
10241 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10242 connector
->base
.id
, connector
->name
,
10243 encoder
->base
.id
, encoder
->name
);
10246 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
10251 * Algorithm gets a little messy:
10253 * - if the connector already has an assigned crtc, use it (but make
10254 * sure it's on first)
10256 * - try to find the first unused crtc that can drive this connector,
10257 * and use that if we find one
10260 /* See if we already have a CRTC for this connector */
10261 if (encoder
->crtc
) {
10262 crtc
= encoder
->crtc
;
10264 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10267 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10271 old
->dpms_mode
= connector
->dpms
;
10272 old
->load_detect_temp
= false;
10274 /* Make sure the crtc and connector are running */
10275 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
10276 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
10281 /* Find an unused one (if possible) */
10282 for_each_crtc(dev
, possible_crtc
) {
10284 if (!(encoder
->possible_crtcs
& (1 << i
)))
10286 if (possible_crtc
->state
->enable
)
10289 crtc
= possible_crtc
;
10294 * If we didn't find an unused CRTC, don't use any.
10297 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10301 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10304 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10308 intel_crtc
= to_intel_crtc(crtc
);
10309 old
->dpms_mode
= connector
->dpms
;
10310 old
->load_detect_temp
= true;
10311 old
->release_fb
= NULL
;
10313 state
= drm_atomic_state_alloc(dev
);
10317 state
->acquire_ctx
= ctx
;
10319 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10320 if (IS_ERR(connector_state
)) {
10321 ret
= PTR_ERR(connector_state
);
10325 connector_state
->crtc
= crtc
;
10326 connector_state
->best_encoder
= &intel_encoder
->base
;
10328 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10329 if (IS_ERR(crtc_state
)) {
10330 ret
= PTR_ERR(crtc_state
);
10334 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10337 mode
= &load_detect_mode
;
10339 /* We need a framebuffer large enough to accommodate all accesses
10340 * that the plane may generate whilst we perform load detection.
10341 * We can not rely on the fbcon either being present (we get called
10342 * during its initialisation to detect all boot displays, or it may
10343 * not even exist) or that it is large enough to satisfy the
10346 fb
= mode_fits_in_fbdev(dev
, mode
);
10348 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10349 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
10350 old
->release_fb
= fb
;
10352 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10354 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10358 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
10362 drm_mode_copy(&crtc_state
->base
.mode
, mode
);
10364 if (drm_atomic_commit(state
)) {
10365 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10366 if (old
->release_fb
)
10367 old
->release_fb
->funcs
->destroy(old
->release_fb
);
10370 crtc
->primary
->crtc
= crtc
;
10372 /* let the connector get through one full cycle before testing */
10373 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
10377 drm_atomic_state_free(state
);
10380 if (ret
== -EDEADLK
) {
10381 drm_modeset_backoff(ctx
);
10388 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10389 struct intel_load_detect_pipe
*old
,
10390 struct drm_modeset_acquire_ctx
*ctx
)
10392 struct drm_device
*dev
= connector
->dev
;
10393 struct intel_encoder
*intel_encoder
=
10394 intel_attached_encoder(connector
);
10395 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10396 struct drm_crtc
*crtc
= encoder
->crtc
;
10397 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10398 struct drm_atomic_state
*state
;
10399 struct drm_connector_state
*connector_state
;
10400 struct intel_crtc_state
*crtc_state
;
10403 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10404 connector
->base
.id
, connector
->name
,
10405 encoder
->base
.id
, encoder
->name
);
10407 if (old
->load_detect_temp
) {
10408 state
= drm_atomic_state_alloc(dev
);
10412 state
->acquire_ctx
= ctx
;
10414 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10415 if (IS_ERR(connector_state
))
10418 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10419 if (IS_ERR(crtc_state
))
10422 connector_state
->best_encoder
= NULL
;
10423 connector_state
->crtc
= NULL
;
10425 crtc_state
->base
.enable
= crtc_state
->base
.active
= false;
10427 ret
= intel_modeset_setup_plane_state(state
, crtc
, NULL
, NULL
,
10432 ret
= drm_atomic_commit(state
);
10436 if (old
->release_fb
) {
10437 drm_framebuffer_unregister_private(old
->release_fb
);
10438 drm_framebuffer_unreference(old
->release_fb
);
10444 /* Switch crtc and encoder back off if necessary */
10445 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
10446 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
10450 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10451 drm_atomic_state_free(state
);
10454 static int i9xx_pll_refclk(struct drm_device
*dev
,
10455 const struct intel_crtc_state
*pipe_config
)
10457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10458 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10460 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10461 return dev_priv
->vbt
.lvds_ssc_freq
;
10462 else if (HAS_PCH_SPLIT(dev
))
10464 else if (!IS_GEN2(dev
))
10470 /* Returns the clock of the currently programmed mode of the given pipe. */
10471 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10472 struct intel_crtc_state
*pipe_config
)
10474 struct drm_device
*dev
= crtc
->base
.dev
;
10475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10476 int pipe
= pipe_config
->cpu_transcoder
;
10477 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10479 intel_clock_t clock
;
10481 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10483 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10484 fp
= pipe_config
->dpll_hw_state
.fp0
;
10486 fp
= pipe_config
->dpll_hw_state
.fp1
;
10488 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10489 if (IS_PINEVIEW(dev
)) {
10490 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10491 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10493 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10494 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10497 if (!IS_GEN2(dev
)) {
10498 if (IS_PINEVIEW(dev
))
10499 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10500 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10502 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10503 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10505 switch (dpll
& DPLL_MODE_MASK
) {
10506 case DPLLB_MODE_DAC_SERIAL
:
10507 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10510 case DPLLB_MODE_LVDS
:
10511 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10515 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10516 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10520 if (IS_PINEVIEW(dev
))
10521 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
10523 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10525 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10526 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10529 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10530 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10532 if (lvds
& LVDS_CLKB_POWER_UP
)
10537 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10540 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10541 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10543 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10549 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10553 * This value includes pixel_multiplier. We will use
10554 * port_clock to compute adjusted_mode.crtc_clock in the
10555 * encoder's get_config() function.
10557 pipe_config
->port_clock
= port_clock
;
10560 int intel_dotclock_calculate(int link_freq
,
10561 const struct intel_link_m_n
*m_n
)
10564 * The calculation for the data clock is:
10565 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10566 * But we want to avoid losing precison if possible, so:
10567 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10569 * and the link clock is simpler:
10570 * link_clock = (m * link_clock) / n
10576 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10579 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10580 struct intel_crtc_state
*pipe_config
)
10582 struct drm_device
*dev
= crtc
->base
.dev
;
10584 /* read out port_clock from the DPLL */
10585 i9xx_crtc_clock_get(crtc
, pipe_config
);
10588 * This value does not include pixel_multiplier.
10589 * We will check that port_clock and adjusted_mode.crtc_clock
10590 * agree once we know their relationship in the encoder's
10591 * get_config() function.
10593 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10594 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
10595 &pipe_config
->fdi_m_n
);
10598 /** Returns the currently programmed mode of the given pipe. */
10599 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10600 struct drm_crtc
*crtc
)
10602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10603 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10604 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10605 struct drm_display_mode
*mode
;
10606 struct intel_crtc_state pipe_config
;
10607 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10608 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10609 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10610 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10611 enum pipe pipe
= intel_crtc
->pipe
;
10613 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10618 * Construct a pipe_config sufficient for getting the clock info
10619 * back out of crtc_clock_get.
10621 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10622 * to use a real value here instead.
10624 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
10625 pipe_config
.pixel_multiplier
= 1;
10626 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10627 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10628 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10629 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
10631 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
10632 mode
->hdisplay
= (htot
& 0xffff) + 1;
10633 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10634 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10635 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10636 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10637 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10638 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10639 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10641 drm_mode_set_name(mode
);
10646 void intel_mark_busy(struct drm_device
*dev
)
10648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10650 if (dev_priv
->mm
.busy
)
10653 intel_runtime_pm_get(dev_priv
);
10654 i915_update_gfx_val(dev_priv
);
10655 if (INTEL_INFO(dev
)->gen
>= 6)
10656 gen6_rps_busy(dev_priv
);
10657 dev_priv
->mm
.busy
= true;
10660 void intel_mark_idle(struct drm_device
*dev
)
10662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10664 if (!dev_priv
->mm
.busy
)
10667 dev_priv
->mm
.busy
= false;
10669 if (INTEL_INFO(dev
)->gen
>= 6)
10670 gen6_rps_idle(dev
->dev_private
);
10672 intel_runtime_pm_put(dev_priv
);
10675 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10677 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10678 struct drm_device
*dev
= crtc
->dev
;
10679 struct intel_unpin_work
*work
;
10681 spin_lock_irq(&dev
->event_lock
);
10682 work
= intel_crtc
->unpin_work
;
10683 intel_crtc
->unpin_work
= NULL
;
10684 spin_unlock_irq(&dev
->event_lock
);
10687 cancel_work_sync(&work
->work
);
10691 drm_crtc_cleanup(crtc
);
10696 static void intel_unpin_work_fn(struct work_struct
*__work
)
10698 struct intel_unpin_work
*work
=
10699 container_of(__work
, struct intel_unpin_work
, work
);
10700 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
10701 struct drm_device
*dev
= crtc
->base
.dev
;
10702 struct drm_plane
*primary
= crtc
->base
.primary
;
10704 mutex_lock(&dev
->struct_mutex
);
10705 intel_unpin_fb_obj(work
->old_fb
, primary
->state
);
10706 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10708 if (work
->flip_queued_req
)
10709 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10710 mutex_unlock(&dev
->struct_mutex
);
10712 intel_frontbuffer_flip_complete(dev
, to_intel_plane(primary
)->frontbuffer_bit
);
10713 drm_framebuffer_unreference(work
->old_fb
);
10715 BUG_ON(atomic_read(&crtc
->unpin_work_count
) == 0);
10716 atomic_dec(&crtc
->unpin_work_count
);
10721 static void do_intel_finish_page_flip(struct drm_device
*dev
,
10722 struct drm_crtc
*crtc
)
10724 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10725 struct intel_unpin_work
*work
;
10726 unsigned long flags
;
10728 /* Ignore early vblank irqs */
10729 if (intel_crtc
== NULL
)
10733 * This is called both by irq handlers and the reset code (to complete
10734 * lost pageflips) so needs the full irqsave spinlocks.
10736 spin_lock_irqsave(&dev
->event_lock
, flags
);
10737 work
= intel_crtc
->unpin_work
;
10739 /* Ensure we don't miss a work->pending update ... */
10742 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
10743 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10747 page_flip_completed(intel_crtc
);
10749 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10752 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
10754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10755 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10757 do_intel_finish_page_flip(dev
, crtc
);
10760 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
10762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10763 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
10765 do_intel_finish_page_flip(dev
, crtc
);
10768 /* Is 'a' after or equal to 'b'? */
10769 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10771 return !((a
- b
) & 0x80000000);
10774 static bool page_flip_finished(struct intel_crtc
*crtc
)
10776 struct drm_device
*dev
= crtc
->base
.dev
;
10777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10779 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
10780 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
10784 * The relevant registers doen't exist on pre-ctg.
10785 * As the flip done interrupt doesn't trigger for mmio
10786 * flips on gmch platforms, a flip count check isn't
10787 * really needed there. But since ctg has the registers,
10788 * include it in the check anyway.
10790 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
10794 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10795 * used the same base address. In that case the mmio flip might
10796 * have completed, but the CS hasn't even executed the flip yet.
10798 * A flip count check isn't enough as the CS might have updated
10799 * the base address just after start of vblank, but before we
10800 * managed to process the interrupt. This means we'd complete the
10801 * CS flip too soon.
10803 * Combining both checks should get us a good enough result. It may
10804 * still happen that the CS flip has been executed, but has not
10805 * yet actually completed. But in case the base address is the same
10806 * anyway, we don't really care.
10808 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
10809 crtc
->unpin_work
->gtt_offset
&&
10810 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
10811 crtc
->unpin_work
->flip_count
);
10814 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
10816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10817 struct intel_crtc
*intel_crtc
=
10818 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
10819 unsigned long flags
;
10823 * This is called both by irq handlers and the reset code (to complete
10824 * lost pageflips) so needs the full irqsave spinlocks.
10826 * NB: An MMIO update of the plane base pointer will also
10827 * generate a page-flip completion irq, i.e. every modeset
10828 * is also accompanied by a spurious intel_prepare_page_flip().
10830 spin_lock_irqsave(&dev
->event_lock
, flags
);
10831 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
10832 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
10833 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10836 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
10838 /* Ensure that the work item is consistent when activating it ... */
10840 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
10841 /* and that it is marked active as soon as the irq could fire. */
10845 static int intel_gen2_queue_flip(struct drm_device
*dev
,
10846 struct drm_crtc
*crtc
,
10847 struct drm_framebuffer
*fb
,
10848 struct drm_i915_gem_object
*obj
,
10849 struct drm_i915_gem_request
*req
,
10852 struct intel_engine_cs
*ring
= req
->ring
;
10853 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10857 ret
= intel_ring_begin(req
, 6);
10861 /* Can't queue multiple flips, so wait for the previous
10862 * one to finish before executing the next.
10864 if (intel_crtc
->plane
)
10865 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10867 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10868 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10869 intel_ring_emit(ring
, MI_NOOP
);
10870 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10871 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10872 intel_ring_emit(ring
, fb
->pitches
[0]);
10873 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10874 intel_ring_emit(ring
, 0); /* aux display base address, unused */
10876 intel_mark_page_flip_active(intel_crtc
);
10880 static int intel_gen3_queue_flip(struct drm_device
*dev
,
10881 struct drm_crtc
*crtc
,
10882 struct drm_framebuffer
*fb
,
10883 struct drm_i915_gem_object
*obj
,
10884 struct drm_i915_gem_request
*req
,
10887 struct intel_engine_cs
*ring
= req
->ring
;
10888 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10892 ret
= intel_ring_begin(req
, 6);
10896 if (intel_crtc
->plane
)
10897 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10899 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10900 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10901 intel_ring_emit(ring
, MI_NOOP
);
10902 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
10903 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10904 intel_ring_emit(ring
, fb
->pitches
[0]);
10905 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10906 intel_ring_emit(ring
, MI_NOOP
);
10908 intel_mark_page_flip_active(intel_crtc
);
10912 static int intel_gen4_queue_flip(struct drm_device
*dev
,
10913 struct drm_crtc
*crtc
,
10914 struct drm_framebuffer
*fb
,
10915 struct drm_i915_gem_object
*obj
,
10916 struct drm_i915_gem_request
*req
,
10919 struct intel_engine_cs
*ring
= req
->ring
;
10920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10921 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10922 uint32_t pf
, pipesrc
;
10925 ret
= intel_ring_begin(req
, 4);
10929 /* i965+ uses the linear or tiled offsets from the
10930 * Display Registers (which do not change across a page-flip)
10931 * so we need only reprogram the base address.
10933 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10934 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10935 intel_ring_emit(ring
, fb
->pitches
[0]);
10936 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
10939 /* XXX Enabling the panel-fitter across page-flip is so far
10940 * untested on non-native modes, so ignore it for now.
10941 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10944 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10945 intel_ring_emit(ring
, pf
| pipesrc
);
10947 intel_mark_page_flip_active(intel_crtc
);
10951 static int intel_gen6_queue_flip(struct drm_device
*dev
,
10952 struct drm_crtc
*crtc
,
10953 struct drm_framebuffer
*fb
,
10954 struct drm_i915_gem_object
*obj
,
10955 struct drm_i915_gem_request
*req
,
10958 struct intel_engine_cs
*ring
= req
->ring
;
10959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10960 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10961 uint32_t pf
, pipesrc
;
10964 ret
= intel_ring_begin(req
, 4);
10968 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10969 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10970 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
10971 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10973 /* Contrary to the suggestions in the documentation,
10974 * "Enable Panel Fitter" does not seem to be required when page
10975 * flipping with a non-native mode, and worse causes a normal
10977 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10980 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10981 intel_ring_emit(ring
, pf
| pipesrc
);
10983 intel_mark_page_flip_active(intel_crtc
);
10987 static int intel_gen7_queue_flip(struct drm_device
*dev
,
10988 struct drm_crtc
*crtc
,
10989 struct drm_framebuffer
*fb
,
10990 struct drm_i915_gem_object
*obj
,
10991 struct drm_i915_gem_request
*req
,
10994 struct intel_engine_cs
*ring
= req
->ring
;
10995 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10996 uint32_t plane_bit
= 0;
10999 switch (intel_crtc
->plane
) {
11001 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
11004 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
11007 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
11010 WARN_ONCE(1, "unknown plane in flip command\n");
11015 if (ring
->id
== RCS
) {
11018 * On Gen 8, SRM is now taking an extra dword to accommodate
11019 * 48bits addresses, and we need a NOOP for the batch size to
11027 * BSpec MI_DISPLAY_FLIP for IVB:
11028 * "The full packet must be contained within the same cache line."
11030 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11031 * cacheline, if we ever start emitting more commands before
11032 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11033 * then do the cacheline alignment, and finally emit the
11036 ret
= intel_ring_cacheline_align(req
);
11040 ret
= intel_ring_begin(req
, len
);
11044 /* Unmask the flip-done completion message. Note that the bspec says that
11045 * we should do this for both the BCS and RCS, and that we must not unmask
11046 * more than one flip event at any time (or ensure that one flip message
11047 * can be sent by waiting for flip-done prior to queueing new flips).
11048 * Experimentation says that BCS works despite DERRMR masking all
11049 * flip-done completion events and that unmasking all planes at once
11050 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11051 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11053 if (ring
->id
== RCS
) {
11054 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
11055 intel_ring_emit(ring
, DERRMR
);
11056 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
11057 DERRMR_PIPEB_PRI_FLIP_DONE
|
11058 DERRMR_PIPEC_PRI_FLIP_DONE
));
11060 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8
|
11061 MI_SRM_LRM_GLOBAL_GTT
);
11063 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM
|
11064 MI_SRM_LRM_GLOBAL_GTT
);
11065 intel_ring_emit(ring
, DERRMR
);
11066 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
11067 if (IS_GEN8(dev
)) {
11068 intel_ring_emit(ring
, 0);
11069 intel_ring_emit(ring
, MI_NOOP
);
11073 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
11074 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
11075 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
11076 intel_ring_emit(ring
, (MI_NOOP
));
11078 intel_mark_page_flip_active(intel_crtc
);
11082 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
11083 struct drm_i915_gem_object
*obj
)
11086 * This is not being used for older platforms, because
11087 * non-availability of flip done interrupt forces us to use
11088 * CS flips. Older platforms derive flip done using some clever
11089 * tricks involving the flip_pending status bits and vblank irqs.
11090 * So using MMIO flips there would disrupt this mechanism.
11096 if (INTEL_INFO(ring
->dev
)->gen
< 5)
11099 if (i915
.use_mmio_flip
< 0)
11101 else if (i915
.use_mmio_flip
> 0)
11103 else if (i915
.enable_execlists
)
11106 return ring
!= i915_gem_request_get_ring(obj
->last_write_req
);
11109 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
11111 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11113 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
11114 const enum pipe pipe
= intel_crtc
->pipe
;
11117 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
11118 ctl
&= ~PLANE_CTL_TILED_MASK
;
11119 switch (fb
->modifier
[0]) {
11120 case DRM_FORMAT_MOD_NONE
:
11122 case I915_FORMAT_MOD_X_TILED
:
11123 ctl
|= PLANE_CTL_TILED_X
;
11125 case I915_FORMAT_MOD_Y_TILED
:
11126 ctl
|= PLANE_CTL_TILED_Y
;
11128 case I915_FORMAT_MOD_Yf_TILED
:
11129 ctl
|= PLANE_CTL_TILED_YF
;
11132 MISSING_CASE(fb
->modifier
[0]);
11136 * The stride is either expressed as a multiple of 64 bytes chunks for
11137 * linear buffers or in number of tiles for tiled buffers.
11139 stride
= fb
->pitches
[0] /
11140 intel_fb_stride_alignment(dev
, fb
->modifier
[0],
11144 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11145 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11147 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
11148 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
11150 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
11151 POSTING_READ(PLANE_SURF(pipe
, 0));
11154 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
11156 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11158 struct intel_framebuffer
*intel_fb
=
11159 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
11160 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11164 reg
= DSPCNTR(intel_crtc
->plane
);
11165 dspcntr
= I915_READ(reg
);
11167 if (obj
->tiling_mode
!= I915_TILING_NONE
)
11168 dspcntr
|= DISPPLANE_TILED
;
11170 dspcntr
&= ~DISPPLANE_TILED
;
11172 I915_WRITE(reg
, dspcntr
);
11174 I915_WRITE(DSPSURF(intel_crtc
->plane
),
11175 intel_crtc
->unpin_work
->gtt_offset
);
11176 POSTING_READ(DSPSURF(intel_crtc
->plane
));
11181 * XXX: This is the temporary way to update the plane registers until we get
11182 * around to using the usual plane update functions for MMIO flips
11184 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
11186 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11188 intel_mark_page_flip_active(intel_crtc
);
11190 intel_pipe_update_start(intel_crtc
);
11192 if (INTEL_INFO(dev
)->gen
>= 9)
11193 skl_do_mmio_flip(intel_crtc
);
11195 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11196 ilk_do_mmio_flip(intel_crtc
);
11198 intel_pipe_update_end(intel_crtc
);
11201 static void intel_mmio_flip_work_func(struct work_struct
*work
)
11203 struct intel_mmio_flip
*mmio_flip
=
11204 container_of(work
, struct intel_mmio_flip
, work
);
11206 if (mmio_flip
->req
)
11207 WARN_ON(__i915_wait_request(mmio_flip
->req
,
11208 mmio_flip
->crtc
->reset_counter
,
11210 &mmio_flip
->i915
->rps
.mmioflips
));
11212 intel_do_mmio_flip(mmio_flip
->crtc
);
11214 i915_gem_request_unreference__unlocked(mmio_flip
->req
);
11218 static int intel_queue_mmio_flip(struct drm_device
*dev
,
11219 struct drm_crtc
*crtc
,
11220 struct drm_framebuffer
*fb
,
11221 struct drm_i915_gem_object
*obj
,
11222 struct intel_engine_cs
*ring
,
11225 struct intel_mmio_flip
*mmio_flip
;
11227 mmio_flip
= kmalloc(sizeof(*mmio_flip
), GFP_KERNEL
);
11228 if (mmio_flip
== NULL
)
11231 mmio_flip
->i915
= to_i915(dev
);
11232 mmio_flip
->req
= i915_gem_request_reference(obj
->last_write_req
);
11233 mmio_flip
->crtc
= to_intel_crtc(crtc
);
11235 INIT_WORK(&mmio_flip
->work
, intel_mmio_flip_work_func
);
11236 schedule_work(&mmio_flip
->work
);
11241 static int intel_default_queue_flip(struct drm_device
*dev
,
11242 struct drm_crtc
*crtc
,
11243 struct drm_framebuffer
*fb
,
11244 struct drm_i915_gem_object
*obj
,
11245 struct drm_i915_gem_request
*req
,
11251 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
11252 struct drm_crtc
*crtc
)
11254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11255 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11256 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
11259 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
11262 if (atomic_read(&work
->pending
) < INTEL_FLIP_PENDING
)
11265 if (!work
->enable_stall_check
)
11268 if (work
->flip_ready_vblank
== 0) {
11269 if (work
->flip_queued_req
&&
11270 !i915_gem_request_completed(work
->flip_queued_req
, true))
11273 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
11276 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
11279 /* Potential stall - if we see that the flip has happened,
11280 * assume a missed interrupt. */
11281 if (INTEL_INFO(dev
)->gen
>= 4)
11282 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
11284 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
11286 /* There is a potential issue here with a false positive after a flip
11287 * to the same address. We could address this by checking for a
11288 * non-incrementing frame counter.
11290 return addr
== work
->gtt_offset
;
11293 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
11295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11296 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11297 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11298 struct intel_unpin_work
*work
;
11300 WARN_ON(!in_interrupt());
11305 spin_lock(&dev
->event_lock
);
11306 work
= intel_crtc
->unpin_work
;
11307 if (work
!= NULL
&& __intel_pageflip_stall_check(dev
, crtc
)) {
11308 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11309 work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
11310 page_flip_completed(intel_crtc
);
11313 if (work
!= NULL
&&
11314 drm_vblank_count(dev
, pipe
) - work
->flip_queued_vblank
> 1)
11315 intel_queue_rps_boost_for_request(dev
, work
->flip_queued_req
);
11316 spin_unlock(&dev
->event_lock
);
11319 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
11320 struct drm_framebuffer
*fb
,
11321 struct drm_pending_vblank_event
*event
,
11322 uint32_t page_flip_flags
)
11324 struct drm_device
*dev
= crtc
->dev
;
11325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11326 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11327 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11328 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11329 struct drm_plane
*primary
= crtc
->primary
;
11330 enum pipe pipe
= intel_crtc
->pipe
;
11331 struct intel_unpin_work
*work
;
11332 struct intel_engine_cs
*ring
;
11334 struct drm_i915_gem_request
*request
= NULL
;
11338 * drm_mode_page_flip_ioctl() should already catch this, but double
11339 * check to be safe. In the future we may enable pageflipping from
11340 * a disabled primary plane.
11342 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
11345 /* Can't change pixel format via MI display flips. */
11346 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
11350 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11351 * Note that pitch changes could also affect these register.
11353 if (INTEL_INFO(dev
)->gen
> 3 &&
11354 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
11355 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
11358 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
11361 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
11365 work
->event
= event
;
11367 work
->old_fb
= old_fb
;
11368 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
11370 ret
= drm_crtc_vblank_get(crtc
);
11374 /* We borrow the event spin lock for protecting unpin_work */
11375 spin_lock_irq(&dev
->event_lock
);
11376 if (intel_crtc
->unpin_work
) {
11377 /* Before declaring the flip queue wedged, check if
11378 * the hardware completed the operation behind our backs.
11380 if (__intel_pageflip_stall_check(dev
, crtc
)) {
11381 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11382 page_flip_completed(intel_crtc
);
11384 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11385 spin_unlock_irq(&dev
->event_lock
);
11387 drm_crtc_vblank_put(crtc
);
11392 intel_crtc
->unpin_work
= work
;
11393 spin_unlock_irq(&dev
->event_lock
);
11395 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
11396 flush_workqueue(dev_priv
->wq
);
11398 /* Reference the objects for the scheduled work. */
11399 drm_framebuffer_reference(work
->old_fb
);
11400 drm_gem_object_reference(&obj
->base
);
11402 crtc
->primary
->fb
= fb
;
11403 update_state_fb(crtc
->primary
);
11405 work
->pending_flip_obj
= obj
;
11407 ret
= i915_mutex_lock_interruptible(dev
);
11411 atomic_inc(&intel_crtc
->unpin_work_count
);
11412 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
11414 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
11415 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
11417 if (IS_VALLEYVIEW(dev
)) {
11418 ring
= &dev_priv
->ring
[BCS
];
11419 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
11420 /* vlv: DISPLAY_FLIP fails to change tiling */
11422 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
11423 ring
= &dev_priv
->ring
[BCS
];
11424 } else if (INTEL_INFO(dev
)->gen
>= 7) {
11425 ring
= i915_gem_request_get_ring(obj
->last_write_req
);
11426 if (ring
== NULL
|| ring
->id
!= RCS
)
11427 ring
= &dev_priv
->ring
[BCS
];
11429 ring
= &dev_priv
->ring
[RCS
];
11432 mmio_flip
= use_mmio_flip(ring
, obj
);
11434 /* When using CS flips, we want to emit semaphores between rings.
11435 * However, when using mmio flips we will create a task to do the
11436 * synchronisation, so all we want here is to pin the framebuffer
11437 * into the display plane and skip any waits.
11439 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
,
11440 crtc
->primary
->state
,
11441 mmio_flip
? i915_gem_request_get_ring(obj
->last_write_req
) : ring
, &request
);
11443 goto cleanup_pending
;
11445 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
),
11447 work
->gtt_offset
+= intel_crtc
->dspaddr_offset
;
11450 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
11453 goto cleanup_unpin
;
11455 i915_gem_request_assign(&work
->flip_queued_req
,
11456 obj
->last_write_req
);
11459 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &request
);
11461 goto cleanup_unpin
;
11464 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, request
,
11467 goto cleanup_unpin
;
11469 i915_gem_request_assign(&work
->flip_queued_req
, request
);
11473 i915_add_request_no_flush(request
);
11475 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
11476 work
->enable_stall_check
= true;
11478 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
11479 to_intel_plane(primary
)->frontbuffer_bit
);
11480 mutex_unlock(&dev
->struct_mutex
);
11482 intel_fbc_disable_crtc(intel_crtc
);
11483 intel_frontbuffer_flip_prepare(dev
,
11484 to_intel_plane(primary
)->frontbuffer_bit
);
11486 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11491 intel_unpin_fb_obj(fb
, crtc
->primary
->state
);
11494 i915_gem_request_cancel(request
);
11495 atomic_dec(&intel_crtc
->unpin_work_count
);
11496 mutex_unlock(&dev
->struct_mutex
);
11498 crtc
->primary
->fb
= old_fb
;
11499 update_state_fb(crtc
->primary
);
11501 drm_gem_object_unreference_unlocked(&obj
->base
);
11502 drm_framebuffer_unreference(work
->old_fb
);
11504 spin_lock_irq(&dev
->event_lock
);
11505 intel_crtc
->unpin_work
= NULL
;
11506 spin_unlock_irq(&dev
->event_lock
);
11508 drm_crtc_vblank_put(crtc
);
11513 struct drm_atomic_state
*state
;
11514 struct drm_plane_state
*plane_state
;
11517 state
= drm_atomic_state_alloc(dev
);
11520 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
11523 plane_state
= drm_atomic_get_plane_state(state
, primary
);
11524 ret
= PTR_ERR_OR_ZERO(plane_state
);
11526 drm_atomic_set_fb_for_plane(plane_state
, fb
);
11528 ret
= drm_atomic_set_crtc_for_plane(plane_state
, crtc
);
11530 ret
= drm_atomic_commit(state
);
11533 if (ret
== -EDEADLK
) {
11534 drm_modeset_backoff(state
->acquire_ctx
);
11535 drm_atomic_state_clear(state
);
11540 drm_atomic_state_free(state
);
11542 if (ret
== 0 && event
) {
11543 spin_lock_irq(&dev
->event_lock
);
11544 drm_send_vblank_event(dev
, pipe
, event
);
11545 spin_unlock_irq(&dev
->event_lock
);
11553 * intel_wm_need_update - Check whether watermarks need updating
11554 * @plane: drm plane
11555 * @state: new plane state
11557 * Check current plane state versus the new one to determine whether
11558 * watermarks need to be recalculated.
11560 * Returns true or false.
11562 static bool intel_wm_need_update(struct drm_plane
*plane
,
11563 struct drm_plane_state
*state
)
11565 /* Update watermarks on tiling changes. */
11566 if (!plane
->state
->fb
|| !state
->fb
||
11567 plane
->state
->fb
->modifier
[0] != state
->fb
->modifier
[0] ||
11568 plane
->state
->rotation
!= state
->rotation
)
11571 if (plane
->state
->crtc_w
!= state
->crtc_w
)
11577 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
11578 struct drm_plane_state
*plane_state
)
11580 struct drm_crtc
*crtc
= crtc_state
->crtc
;
11581 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11582 struct drm_plane
*plane
= plane_state
->plane
;
11583 struct drm_device
*dev
= crtc
->dev
;
11584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11585 struct intel_plane_state
*old_plane_state
=
11586 to_intel_plane_state(plane
->state
);
11587 int idx
= intel_crtc
->base
.base
.id
, ret
;
11588 int i
= drm_plane_index(plane
);
11589 bool mode_changed
= needs_modeset(crtc_state
);
11590 bool was_crtc_enabled
= crtc
->state
->active
;
11591 bool is_crtc_enabled
= crtc_state
->active
;
11593 bool turn_off
, turn_on
, visible
, was_visible
;
11594 struct drm_framebuffer
*fb
= plane_state
->fb
;
11596 if (crtc_state
&& INTEL_INFO(dev
)->gen
>= 9 &&
11597 plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11598 ret
= skl_update_scaler_plane(
11599 to_intel_crtc_state(crtc_state
),
11600 to_intel_plane_state(plane_state
));
11606 * Disabling a plane is always okay; we just need to update
11607 * fb tracking in a special way since cleanup_fb() won't
11608 * get called by the plane helpers.
11610 if (old_plane_state
->base
.fb
&& !fb
)
11611 intel_crtc
->atomic
.disabled_planes
|= 1 << i
;
11613 was_visible
= old_plane_state
->visible
;
11614 visible
= to_intel_plane_state(plane_state
)->visible
;
11616 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
11617 was_visible
= false;
11619 if (!is_crtc_enabled
&& WARN_ON(visible
))
11622 if (!was_visible
&& !visible
)
11625 turn_off
= was_visible
&& (!visible
|| mode_changed
);
11626 turn_on
= visible
&& (!was_visible
|| mode_changed
);
11628 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx
,
11629 plane
->base
.id
, fb
? fb
->base
.id
: -1);
11631 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11632 plane
->base
.id
, was_visible
, visible
,
11633 turn_off
, turn_on
, mode_changed
);
11636 intel_crtc
->atomic
.update_wm_pre
= true;
11637 /* must disable cxsr around plane enable/disable */
11638 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11639 intel_crtc
->atomic
.disable_cxsr
= true;
11640 /* to potentially re-enable cxsr */
11641 intel_crtc
->atomic
.wait_vblank
= true;
11642 intel_crtc
->atomic
.update_wm_post
= true;
11644 } else if (turn_off
) {
11645 intel_crtc
->atomic
.update_wm_post
= true;
11646 /* must disable cxsr around plane enable/disable */
11647 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11648 if (is_crtc_enabled
)
11649 intel_crtc
->atomic
.wait_vblank
= true;
11650 intel_crtc
->atomic
.disable_cxsr
= true;
11652 } else if (intel_wm_need_update(plane
, plane_state
)) {
11653 intel_crtc
->atomic
.update_wm_pre
= true;
11656 if (visible
|| was_visible
)
11657 intel_crtc
->atomic
.fb_bits
|=
11658 to_intel_plane(plane
)->frontbuffer_bit
;
11660 switch (plane
->type
) {
11661 case DRM_PLANE_TYPE_PRIMARY
:
11662 intel_crtc
->atomic
.wait_for_flips
= true;
11663 intel_crtc
->atomic
.pre_disable_primary
= turn_off
;
11664 intel_crtc
->atomic
.post_enable_primary
= turn_on
;
11668 * FIXME: Actually if we will still have any other
11669 * plane enabled on the pipe we could let IPS enabled
11670 * still, but for now lets consider that when we make
11671 * primary invisible by setting DSPCNTR to 0 on
11672 * update_primary_plane function IPS needs to be
11675 intel_crtc
->atomic
.disable_ips
= true;
11677 intel_crtc
->atomic
.disable_fbc
= true;
11681 * FBC does not work on some platforms for rotated
11682 * planes, so disable it when rotation is not 0 and
11683 * update it when rotation is set back to 0.
11685 * FIXME: This is redundant with the fbc update done in
11686 * the primary plane enable function except that that
11687 * one is done too late. We eventually need to unify
11692 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11693 dev_priv
->fbc
.crtc
== intel_crtc
&&
11694 plane_state
->rotation
!= BIT(DRM_ROTATE_0
))
11695 intel_crtc
->atomic
.disable_fbc
= true;
11698 * BDW signals flip done immediately if the plane
11699 * is disabled, even if the plane enable is already
11700 * armed to occur at the next vblank :(
11702 if (turn_on
&& IS_BROADWELL(dev
))
11703 intel_crtc
->atomic
.wait_vblank
= true;
11705 intel_crtc
->atomic
.update_fbc
|= visible
|| mode_changed
;
11707 case DRM_PLANE_TYPE_CURSOR
:
11709 case DRM_PLANE_TYPE_OVERLAY
:
11710 if (turn_off
&& !mode_changed
) {
11711 intel_crtc
->atomic
.wait_vblank
= true;
11712 intel_crtc
->atomic
.update_sprite_watermarks
|=
11719 static bool encoders_cloneable(const struct intel_encoder
*a
,
11720 const struct intel_encoder
*b
)
11722 /* masks could be asymmetric, so check both ways */
11723 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11724 b
->cloneable
& (1 << a
->type
));
11727 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11728 struct intel_crtc
*crtc
,
11729 struct intel_encoder
*encoder
)
11731 struct intel_encoder
*source_encoder
;
11732 struct drm_connector
*connector
;
11733 struct drm_connector_state
*connector_state
;
11736 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11737 if (connector_state
->crtc
!= &crtc
->base
)
11741 to_intel_encoder(connector_state
->best_encoder
);
11742 if (!encoders_cloneable(encoder
, source_encoder
))
11749 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
11750 struct intel_crtc
*crtc
)
11752 struct intel_encoder
*encoder
;
11753 struct drm_connector
*connector
;
11754 struct drm_connector_state
*connector_state
;
11757 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11758 if (connector_state
->crtc
!= &crtc
->base
)
11761 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11762 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
11769 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
11770 struct drm_crtc_state
*crtc_state
)
11772 struct drm_device
*dev
= crtc
->dev
;
11773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11774 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11775 struct intel_crtc_state
*pipe_config
=
11776 to_intel_crtc_state(crtc_state
);
11777 struct drm_atomic_state
*state
= crtc_state
->state
;
11779 bool mode_changed
= needs_modeset(crtc_state
);
11781 if (mode_changed
&& !check_encoder_cloning(state
, intel_crtc
)) {
11782 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11786 if (mode_changed
&& !crtc_state
->active
)
11787 intel_crtc
->atomic
.update_wm_post
= true;
11789 if (mode_changed
&& crtc_state
->enable
&&
11790 dev_priv
->display
.crtc_compute_clock
&&
11791 !WARN_ON(pipe_config
->shared_dpll
!= DPLL_ID_PRIVATE
)) {
11792 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11799 if (INTEL_INFO(dev
)->gen
>= 9) {
11801 ret
= skl_update_scaler_crtc(pipe_config
);
11804 ret
= intel_atomic_setup_scalers(dev
, intel_crtc
,
11811 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11812 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
11813 .load_lut
= intel_crtc_load_lut
,
11814 .atomic_begin
= intel_begin_crtc_commit
,
11815 .atomic_flush
= intel_finish_crtc_commit
,
11816 .atomic_check
= intel_crtc_atomic_check
,
11819 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11821 struct intel_connector
*connector
;
11823 for_each_intel_connector(dev
, connector
) {
11824 if (connector
->base
.encoder
) {
11825 connector
->base
.state
->best_encoder
=
11826 connector
->base
.encoder
;
11827 connector
->base
.state
->crtc
=
11828 connector
->base
.encoder
->crtc
;
11830 connector
->base
.state
->best_encoder
= NULL
;
11831 connector
->base
.state
->crtc
= NULL
;
11837 connected_sink_compute_bpp(struct intel_connector
*connector
,
11838 struct intel_crtc_state
*pipe_config
)
11840 int bpp
= pipe_config
->pipe_bpp
;
11842 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11843 connector
->base
.base
.id
,
11844 connector
->base
.name
);
11846 /* Don't use an invalid EDID bpc value */
11847 if (connector
->base
.display_info
.bpc
&&
11848 connector
->base
.display_info
.bpc
* 3 < bpp
) {
11849 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11850 bpp
, connector
->base
.display_info
.bpc
*3);
11851 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
11854 /* Clamp bpp to 8 on screens without EDID 1.4 */
11855 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
11856 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11858 pipe_config
->pipe_bpp
= 24;
11863 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
11864 struct intel_crtc_state
*pipe_config
)
11866 struct drm_device
*dev
= crtc
->base
.dev
;
11867 struct drm_atomic_state
*state
;
11868 struct drm_connector
*connector
;
11869 struct drm_connector_state
*connector_state
;
11872 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)))
11874 else if (INTEL_INFO(dev
)->gen
>= 5)
11880 pipe_config
->pipe_bpp
= bpp
;
11882 state
= pipe_config
->base
.state
;
11884 /* Clamp display bpp to EDID value */
11885 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11886 if (connector_state
->crtc
!= &crtc
->base
)
11889 connected_sink_compute_bpp(to_intel_connector(connector
),
11896 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
11898 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11899 "type: 0x%x flags: 0x%x\n",
11901 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
11902 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
11903 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
11904 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
11907 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
11908 struct intel_crtc_state
*pipe_config
,
11909 const char *context
)
11911 struct drm_device
*dev
= crtc
->base
.dev
;
11912 struct drm_plane
*plane
;
11913 struct intel_plane
*intel_plane
;
11914 struct intel_plane_state
*state
;
11915 struct drm_framebuffer
*fb
;
11917 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc
->base
.base
.id
,
11918 context
, pipe_config
, pipe_name(crtc
->pipe
));
11920 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
11921 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11922 pipe_config
->pipe_bpp
, pipe_config
->dither
);
11923 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11924 pipe_config
->has_pch_encoder
,
11925 pipe_config
->fdi_lanes
,
11926 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
11927 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
11928 pipe_config
->fdi_m_n
.tu
);
11929 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11930 pipe_config
->has_dp_encoder
,
11931 pipe_config
->lane_count
,
11932 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
11933 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
11934 pipe_config
->dp_m_n
.tu
);
11936 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11937 pipe_config
->has_dp_encoder
,
11938 pipe_config
->lane_count
,
11939 pipe_config
->dp_m2_n2
.gmch_m
,
11940 pipe_config
->dp_m2_n2
.gmch_n
,
11941 pipe_config
->dp_m2_n2
.link_m
,
11942 pipe_config
->dp_m2_n2
.link_n
,
11943 pipe_config
->dp_m2_n2
.tu
);
11945 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11946 pipe_config
->has_audio
,
11947 pipe_config
->has_infoframe
);
11949 DRM_DEBUG_KMS("requested mode:\n");
11950 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
11951 DRM_DEBUG_KMS("adjusted mode:\n");
11952 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
11953 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
11954 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
11955 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11956 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
11957 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11959 pipe_config
->scaler_state
.scaler_users
,
11960 pipe_config
->scaler_state
.scaler_id
);
11961 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11962 pipe_config
->gmch_pfit
.control
,
11963 pipe_config
->gmch_pfit
.pgm_ratios
,
11964 pipe_config
->gmch_pfit
.lvds_border_bits
);
11965 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11966 pipe_config
->pch_pfit
.pos
,
11967 pipe_config
->pch_pfit
.size
,
11968 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
11969 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
11970 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
11972 if (IS_BROXTON(dev
)) {
11973 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11974 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11975 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11976 pipe_config
->ddi_pll_sel
,
11977 pipe_config
->dpll_hw_state
.ebb0
,
11978 pipe_config
->dpll_hw_state
.ebb4
,
11979 pipe_config
->dpll_hw_state
.pll0
,
11980 pipe_config
->dpll_hw_state
.pll1
,
11981 pipe_config
->dpll_hw_state
.pll2
,
11982 pipe_config
->dpll_hw_state
.pll3
,
11983 pipe_config
->dpll_hw_state
.pll6
,
11984 pipe_config
->dpll_hw_state
.pll8
,
11985 pipe_config
->dpll_hw_state
.pll9
,
11986 pipe_config
->dpll_hw_state
.pll10
,
11987 pipe_config
->dpll_hw_state
.pcsdw12
);
11988 } else if (IS_SKYLAKE(dev
)) {
11989 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11990 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11991 pipe_config
->ddi_pll_sel
,
11992 pipe_config
->dpll_hw_state
.ctrl1
,
11993 pipe_config
->dpll_hw_state
.cfgcr1
,
11994 pipe_config
->dpll_hw_state
.cfgcr2
);
11995 } else if (HAS_DDI(dev
)) {
11996 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11997 pipe_config
->ddi_pll_sel
,
11998 pipe_config
->dpll_hw_state
.wrpll
);
12000 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12001 "fp0: 0x%x, fp1: 0x%x\n",
12002 pipe_config
->dpll_hw_state
.dpll
,
12003 pipe_config
->dpll_hw_state
.dpll_md
,
12004 pipe_config
->dpll_hw_state
.fp0
,
12005 pipe_config
->dpll_hw_state
.fp1
);
12008 DRM_DEBUG_KMS("planes on this crtc\n");
12009 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
12010 intel_plane
= to_intel_plane(plane
);
12011 if (intel_plane
->pipe
!= crtc
->pipe
)
12014 state
= to_intel_plane_state(plane
->state
);
12015 fb
= state
->base
.fb
;
12017 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12018 "disabled, scaler_id = %d\n",
12019 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12020 plane
->base
.id
, intel_plane
->pipe
,
12021 (crtc
->base
.primary
== plane
) ? 0 : intel_plane
->plane
+ 1,
12022 drm_plane_index(plane
), state
->scaler_id
);
12026 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12027 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12028 plane
->base
.id
, intel_plane
->pipe
,
12029 crtc
->base
.primary
== plane
? 0 : intel_plane
->plane
+ 1,
12030 drm_plane_index(plane
));
12031 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12032 fb
->base
.id
, fb
->width
, fb
->height
, fb
->pixel_format
);
12033 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12035 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
12036 drm_rect_width(&state
->src
) >> 16,
12037 drm_rect_height(&state
->src
) >> 16,
12038 state
->dst
.x1
, state
->dst
.y1
,
12039 drm_rect_width(&state
->dst
), drm_rect_height(&state
->dst
));
12043 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
12045 struct drm_device
*dev
= state
->dev
;
12046 struct intel_encoder
*encoder
;
12047 struct drm_connector
*connector
;
12048 struct drm_connector_state
*connector_state
;
12049 unsigned int used_ports
= 0;
12053 * Walk the connector list instead of the encoder
12054 * list to detect the problem on ddi platforms
12055 * where there's just one encoder per digital port.
12057 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12058 if (!connector_state
->best_encoder
)
12061 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12063 WARN_ON(!connector_state
->crtc
);
12065 switch (encoder
->type
) {
12066 unsigned int port_mask
;
12067 case INTEL_OUTPUT_UNKNOWN
:
12068 if (WARN_ON(!HAS_DDI(dev
)))
12070 case INTEL_OUTPUT_DISPLAYPORT
:
12071 case INTEL_OUTPUT_HDMI
:
12072 case INTEL_OUTPUT_EDP
:
12073 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
12075 /* the same port mustn't appear more than once */
12076 if (used_ports
& port_mask
)
12079 used_ports
|= port_mask
;
12089 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
12091 struct drm_crtc_state tmp_state
;
12092 struct intel_crtc_scaler_state scaler_state
;
12093 struct intel_dpll_hw_state dpll_hw_state
;
12094 enum intel_dpll_id shared_dpll
;
12095 uint32_t ddi_pll_sel
;
12098 /* FIXME: before the switch to atomic started, a new pipe_config was
12099 * kzalloc'd. Code that depends on any field being zero should be
12100 * fixed, so that the crtc_state can be safely duplicated. For now,
12101 * only fields that are know to not cause problems are preserved. */
12103 tmp_state
= crtc_state
->base
;
12104 scaler_state
= crtc_state
->scaler_state
;
12105 shared_dpll
= crtc_state
->shared_dpll
;
12106 dpll_hw_state
= crtc_state
->dpll_hw_state
;
12107 ddi_pll_sel
= crtc_state
->ddi_pll_sel
;
12108 force_thru
= crtc_state
->pch_pfit
.force_thru
;
12110 memset(crtc_state
, 0, sizeof *crtc_state
);
12112 crtc_state
->base
= tmp_state
;
12113 crtc_state
->scaler_state
= scaler_state
;
12114 crtc_state
->shared_dpll
= shared_dpll
;
12115 crtc_state
->dpll_hw_state
= dpll_hw_state
;
12116 crtc_state
->ddi_pll_sel
= ddi_pll_sel
;
12117 crtc_state
->pch_pfit
.force_thru
= force_thru
;
12121 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
12122 struct intel_crtc_state
*pipe_config
)
12124 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12125 struct intel_encoder
*encoder
;
12126 struct drm_connector
*connector
;
12127 struct drm_connector_state
*connector_state
;
12128 int base_bpp
, ret
= -EINVAL
;
12132 clear_intel_crtc_state(pipe_config
);
12134 pipe_config
->cpu_transcoder
=
12135 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
12138 * Sanitize sync polarity flags based on requested ones. If neither
12139 * positive or negative polarity is requested, treat this as meaning
12140 * negative polarity.
12142 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12143 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
12144 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
12146 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12147 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
12148 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
12150 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
12156 * Determine the real pipe dimensions. Note that stereo modes can
12157 * increase the actual pipe size due to the frame doubling and
12158 * insertion of additional space for blanks between the frame. This
12159 * is stored in the crtc timings. We use the requested mode to do this
12160 * computation to clearly distinguish it from the adjusted mode, which
12161 * can be changed by the connectors in the below retry loop.
12163 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
12164 &pipe_config
->pipe_src_w
,
12165 &pipe_config
->pipe_src_h
);
12168 /* Ensure the port clock defaults are reset when retrying. */
12169 pipe_config
->port_clock
= 0;
12170 pipe_config
->pixel_multiplier
= 1;
12172 /* Fill in default crtc timings, allow encoders to overwrite them. */
12173 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
12174 CRTC_STEREO_DOUBLE
);
12176 /* Pass our mode to the connectors and the CRTC to give them a chance to
12177 * adjust it according to limitations or connector properties, and also
12178 * a chance to reject the mode entirely.
12180 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12181 if (connector_state
->crtc
!= crtc
)
12184 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12186 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
12187 DRM_DEBUG_KMS("Encoder config failure\n");
12192 /* Set default port clock if not overwritten by the encoder. Needs to be
12193 * done afterwards in case the encoder adjusts the mode. */
12194 if (!pipe_config
->port_clock
)
12195 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
12196 * pipe_config
->pixel_multiplier
;
12198 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
12200 DRM_DEBUG_KMS("CRTC fixup failed\n");
12204 if (ret
== RETRY
) {
12205 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
12210 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12212 goto encoder_retry
;
12215 /* Dithering seems to not pass-through bits correctly when it should, so
12216 * only enable it on 6bpc panels. */
12217 pipe_config
->dither
= pipe_config
->pipe_bpp
== 6*3;
12218 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12219 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
12226 intel_modeset_update_crtc_state(struct drm_atomic_state
*state
)
12228 struct drm_crtc
*crtc
;
12229 struct drm_crtc_state
*crtc_state
;
12232 /* Double check state. */
12233 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12234 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(crtc
->state
);
12236 /* Update hwmode for vblank functions */
12237 if (crtc
->state
->active
)
12238 crtc
->hwmode
= crtc
->state
->adjusted_mode
;
12240 crtc
->hwmode
.crtc_clock
= 0;
12244 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
12248 if (clock1
== clock2
)
12251 if (!clock1
|| !clock2
)
12254 diff
= abs(clock1
- clock2
);
12256 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
12262 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12263 list_for_each_entry((intel_crtc), \
12264 &(dev)->mode_config.crtc_list, \
12266 if (mask & (1 <<(intel_crtc)->pipe))
12269 intel_compare_m_n(unsigned int m
, unsigned int n
,
12270 unsigned int m2
, unsigned int n2
,
12273 if (m
== m2
&& n
== n2
)
12276 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
12279 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
12286 } else if (m
< m2
) {
12293 return m
== m2
&& n
== n2
;
12297 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
12298 struct intel_link_m_n
*m2_n2
,
12301 if (m_n
->tu
== m2_n2
->tu
&&
12302 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
12303 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
12304 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
12305 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
12316 intel_pipe_config_compare(struct drm_device
*dev
,
12317 struct intel_crtc_state
*current_config
,
12318 struct intel_crtc_state
*pipe_config
,
12323 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12326 DRM_ERROR(fmt, ##__VA_ARGS__); \
12328 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12331 #define PIPE_CONF_CHECK_X(name) \
12332 if (current_config->name != pipe_config->name) { \
12333 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12334 "(expected 0x%08x, found 0x%08x)\n", \
12335 current_config->name, \
12336 pipe_config->name); \
12340 #define PIPE_CONF_CHECK_I(name) \
12341 if (current_config->name != pipe_config->name) { \
12342 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12343 "(expected %i, found %i)\n", \
12344 current_config->name, \
12345 pipe_config->name); \
12349 #define PIPE_CONF_CHECK_M_N(name) \
12350 if (!intel_compare_link_m_n(¤t_config->name, \
12351 &pipe_config->name,\
12353 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12354 "(expected tu %i gmch %i/%i link %i/%i, " \
12355 "found tu %i, gmch %i/%i link %i/%i)\n", \
12356 current_config->name.tu, \
12357 current_config->name.gmch_m, \
12358 current_config->name.gmch_n, \
12359 current_config->name.link_m, \
12360 current_config->name.link_n, \
12361 pipe_config->name.tu, \
12362 pipe_config->name.gmch_m, \
12363 pipe_config->name.gmch_n, \
12364 pipe_config->name.link_m, \
12365 pipe_config->name.link_n); \
12369 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12370 if (!intel_compare_link_m_n(¤t_config->name, \
12371 &pipe_config->name, adjust) && \
12372 !intel_compare_link_m_n(¤t_config->alt_name, \
12373 &pipe_config->name, adjust)) { \
12374 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12375 "(expected tu %i gmch %i/%i link %i/%i, " \
12376 "or tu %i gmch %i/%i link %i/%i, " \
12377 "found tu %i, gmch %i/%i link %i/%i)\n", \
12378 current_config->name.tu, \
12379 current_config->name.gmch_m, \
12380 current_config->name.gmch_n, \
12381 current_config->name.link_m, \
12382 current_config->name.link_n, \
12383 current_config->alt_name.tu, \
12384 current_config->alt_name.gmch_m, \
12385 current_config->alt_name.gmch_n, \
12386 current_config->alt_name.link_m, \
12387 current_config->alt_name.link_n, \
12388 pipe_config->name.tu, \
12389 pipe_config->name.gmch_m, \
12390 pipe_config->name.gmch_n, \
12391 pipe_config->name.link_m, \
12392 pipe_config->name.link_n); \
12396 /* This is required for BDW+ where there is only one set of registers for
12397 * switching between high and low RR.
12398 * This macro can be used whenever a comparison has to be made between one
12399 * hw state and multiple sw state variables.
12401 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12402 if ((current_config->name != pipe_config->name) && \
12403 (current_config->alt_name != pipe_config->name)) { \
12404 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12405 "(expected %i or %i, found %i)\n", \
12406 current_config->name, \
12407 current_config->alt_name, \
12408 pipe_config->name); \
12412 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12413 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12414 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12415 "(expected %i, found %i)\n", \
12416 current_config->name & (mask), \
12417 pipe_config->name & (mask)); \
12421 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12422 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12423 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12424 "(expected %i, found %i)\n", \
12425 current_config->name, \
12426 pipe_config->name); \
12430 #define PIPE_CONF_QUIRK(quirk) \
12431 ((current_config->quirks | pipe_config->quirks) & (quirk))
12433 PIPE_CONF_CHECK_I(cpu_transcoder
);
12435 PIPE_CONF_CHECK_I(has_pch_encoder
);
12436 PIPE_CONF_CHECK_I(fdi_lanes
);
12437 PIPE_CONF_CHECK_M_N(fdi_m_n
);
12439 PIPE_CONF_CHECK_I(has_dp_encoder
);
12440 PIPE_CONF_CHECK_I(lane_count
);
12442 if (INTEL_INFO(dev
)->gen
< 8) {
12443 PIPE_CONF_CHECK_M_N(dp_m_n
);
12445 PIPE_CONF_CHECK_I(has_drrs
);
12446 if (current_config
->has_drrs
)
12447 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
12449 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
12451 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12452 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12453 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12454 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12455 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12456 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12458 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12459 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12460 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12461 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12462 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12463 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12465 PIPE_CONF_CHECK_I(pixel_multiplier
);
12466 PIPE_CONF_CHECK_I(has_hdmi_sink
);
12467 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
12468 IS_VALLEYVIEW(dev
))
12469 PIPE_CONF_CHECK_I(limited_color_range
);
12470 PIPE_CONF_CHECK_I(has_infoframe
);
12472 PIPE_CONF_CHECK_I(has_audio
);
12474 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12475 DRM_MODE_FLAG_INTERLACE
);
12477 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12478 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12479 DRM_MODE_FLAG_PHSYNC
);
12480 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12481 DRM_MODE_FLAG_NHSYNC
);
12482 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12483 DRM_MODE_FLAG_PVSYNC
);
12484 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12485 DRM_MODE_FLAG_NVSYNC
);
12488 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
12489 /* pfit ratios are autocomputed by the hw on gen4+ */
12490 if (INTEL_INFO(dev
)->gen
< 4)
12491 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
12492 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
12495 PIPE_CONF_CHECK_I(pipe_src_w
);
12496 PIPE_CONF_CHECK_I(pipe_src_h
);
12498 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
12499 if (current_config
->pch_pfit
.enabled
) {
12500 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
12501 PIPE_CONF_CHECK_X(pch_pfit
.size
);
12504 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12507 /* BDW+ don't expose a synchronous way to read the state */
12508 if (IS_HASWELL(dev
))
12509 PIPE_CONF_CHECK_I(ips_enabled
);
12511 PIPE_CONF_CHECK_I(double_wide
);
12513 PIPE_CONF_CHECK_X(ddi_pll_sel
);
12515 PIPE_CONF_CHECK_I(shared_dpll
);
12516 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12517 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12518 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12519 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12520 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12521 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12522 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12523 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12525 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
12526 PIPE_CONF_CHECK_I(pipe_bpp
);
12528 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12529 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12531 #undef PIPE_CONF_CHECK_X
12532 #undef PIPE_CONF_CHECK_I
12533 #undef PIPE_CONF_CHECK_I_ALT
12534 #undef PIPE_CONF_CHECK_FLAGS
12535 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12536 #undef PIPE_CONF_QUIRK
12537 #undef INTEL_ERR_OR_DBG_KMS
12542 static void check_wm_state(struct drm_device
*dev
)
12544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12545 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
12546 struct intel_crtc
*intel_crtc
;
12549 if (INTEL_INFO(dev
)->gen
< 9)
12552 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
12553 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12555 for_each_intel_crtc(dev
, intel_crtc
) {
12556 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
12557 const enum pipe pipe
= intel_crtc
->pipe
;
12559 if (!intel_crtc
->active
)
12563 for_each_plane(dev_priv
, pipe
, plane
) {
12564 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
12565 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
12567 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12570 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12571 "(expected (%u,%u), found (%u,%u))\n",
12572 pipe_name(pipe
), plane
+ 1,
12573 sw_entry
->start
, sw_entry
->end
,
12574 hw_entry
->start
, hw_entry
->end
);
12578 hw_entry
= &hw_ddb
.cursor
[pipe
];
12579 sw_entry
= &sw_ddb
->cursor
[pipe
];
12581 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12584 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12585 "(expected (%u,%u), found (%u,%u))\n",
12587 sw_entry
->start
, sw_entry
->end
,
12588 hw_entry
->start
, hw_entry
->end
);
12593 check_connector_state(struct drm_device
*dev
,
12594 struct drm_atomic_state
*old_state
)
12596 struct drm_connector_state
*old_conn_state
;
12597 struct drm_connector
*connector
;
12600 for_each_connector_in_state(old_state
, connector
, old_conn_state
, i
) {
12601 struct drm_encoder
*encoder
= connector
->encoder
;
12602 struct drm_connector_state
*state
= connector
->state
;
12604 /* This also checks the encoder/connector hw state with the
12605 * ->get_hw_state callbacks. */
12606 intel_connector_check_state(to_intel_connector(connector
));
12608 I915_STATE_WARN(state
->best_encoder
!= encoder
,
12609 "connector's atomic encoder doesn't match legacy encoder\n");
12614 check_encoder_state(struct drm_device
*dev
)
12616 struct intel_encoder
*encoder
;
12617 struct intel_connector
*connector
;
12619 for_each_intel_encoder(dev
, encoder
) {
12620 bool enabled
= false;
12623 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12624 encoder
->base
.base
.id
,
12625 encoder
->base
.name
);
12627 for_each_intel_connector(dev
, connector
) {
12628 if (connector
->base
.state
->best_encoder
!= &encoder
->base
)
12632 I915_STATE_WARN(connector
->base
.state
->crtc
!=
12633 encoder
->base
.crtc
,
12634 "connector's crtc doesn't match encoder crtc\n");
12637 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12638 "encoder's enabled state mismatch "
12639 "(expected %i, found %i)\n",
12640 !!encoder
->base
.crtc
, enabled
);
12642 if (!encoder
->base
.crtc
) {
12645 active
= encoder
->get_hw_state(encoder
, &pipe
);
12646 I915_STATE_WARN(active
,
12647 "encoder detached but still enabled on pipe %c.\n",
12654 check_crtc_state(struct drm_device
*dev
, struct drm_atomic_state
*old_state
)
12656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12657 struct intel_encoder
*encoder
;
12658 struct drm_crtc_state
*old_crtc_state
;
12659 struct drm_crtc
*crtc
;
12662 for_each_crtc_in_state(old_state
, crtc
, old_crtc_state
, i
) {
12663 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12664 struct intel_crtc_state
*pipe_config
, *sw_config
;
12667 if (!needs_modeset(crtc
->state
) &&
12668 !to_intel_crtc_state(crtc
->state
)->update_pipe
)
12671 __drm_atomic_helper_crtc_destroy_state(crtc
, old_crtc_state
);
12672 pipe_config
= to_intel_crtc_state(old_crtc_state
);
12673 memset(pipe_config
, 0, sizeof(*pipe_config
));
12674 pipe_config
->base
.crtc
= crtc
;
12675 pipe_config
->base
.state
= old_state
;
12677 DRM_DEBUG_KMS("[CRTC:%d]\n",
12680 active
= dev_priv
->display
.get_pipe_config(intel_crtc
,
12683 /* hw state is inconsistent with the pipe quirk */
12684 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
12685 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
12686 active
= crtc
->state
->active
;
12688 I915_STATE_WARN(crtc
->state
->active
!= active
,
12689 "crtc active state doesn't match with hw state "
12690 "(expected %i, found %i)\n", crtc
->state
->active
, active
);
12692 I915_STATE_WARN(intel_crtc
->active
!= crtc
->state
->active
,
12693 "transitional active state does not match atomic hw state "
12694 "(expected %i, found %i)\n", crtc
->state
->active
, intel_crtc
->active
);
12696 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
12699 active
= encoder
->get_hw_state(encoder
, &pipe
);
12700 I915_STATE_WARN(active
!= crtc
->state
->active
,
12701 "[ENCODER:%i] active %i with crtc active %i\n",
12702 encoder
->base
.base
.id
, active
, crtc
->state
->active
);
12704 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
12705 "Encoder connected to wrong pipe %c\n",
12709 encoder
->get_config(encoder
, pipe_config
);
12712 if (!crtc
->state
->active
)
12715 sw_config
= to_intel_crtc_state(crtc
->state
);
12716 if (!intel_pipe_config_compare(dev
, sw_config
,
12717 pipe_config
, false)) {
12718 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12719 intel_dump_pipe_config(intel_crtc
, pipe_config
,
12721 intel_dump_pipe_config(intel_crtc
, sw_config
,
12728 check_shared_dpll_state(struct drm_device
*dev
)
12730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12731 struct intel_crtc
*crtc
;
12732 struct intel_dpll_hw_state dpll_hw_state
;
12735 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12736 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12737 int enabled_crtcs
= 0, active_crtcs
= 0;
12740 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12742 DRM_DEBUG_KMS("%s\n", pll
->name
);
12744 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12746 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
12747 "more active pll users than references: %i vs %i\n",
12748 pll
->active
, hweight32(pll
->config
.crtc_mask
));
12749 I915_STATE_WARN(pll
->active
&& !pll
->on
,
12750 "pll in active use but not on in sw tracking\n");
12751 I915_STATE_WARN(pll
->on
&& !pll
->active
,
12752 "pll in on but not on in use in sw tracking\n");
12753 I915_STATE_WARN(pll
->on
!= active
,
12754 "pll on state mismatch (expected %i, found %i)\n",
12757 for_each_intel_crtc(dev
, crtc
) {
12758 if (crtc
->base
.state
->enable
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12760 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12763 I915_STATE_WARN(pll
->active
!= active_crtcs
,
12764 "pll active crtcs mismatch (expected %i, found %i)\n",
12765 pll
->active
, active_crtcs
);
12766 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
12767 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12768 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
12770 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
12771 sizeof(dpll_hw_state
)),
12772 "pll hw state mismatch\n");
12777 intel_modeset_check_state(struct drm_device
*dev
,
12778 struct drm_atomic_state
*old_state
)
12780 check_wm_state(dev
);
12781 check_connector_state(dev
, old_state
);
12782 check_encoder_state(dev
);
12783 check_crtc_state(dev
, old_state
);
12784 check_shared_dpll_state(dev
);
12787 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
12791 * FDI already provided one idea for the dotclock.
12792 * Yell if the encoder disagrees.
12794 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
12795 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12796 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
12799 static void update_scanline_offset(struct intel_crtc
*crtc
)
12801 struct drm_device
*dev
= crtc
->base
.dev
;
12804 * The scanline counter increments at the leading edge of hsync.
12806 * On most platforms it starts counting from vtotal-1 on the
12807 * first active line. That means the scanline counter value is
12808 * always one less than what we would expect. Ie. just after
12809 * start of vblank, which also occurs at start of hsync (on the
12810 * last active line), the scanline counter will read vblank_start-1.
12812 * On gen2 the scanline counter starts counting from 1 instead
12813 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12814 * to keep the value positive), instead of adding one.
12816 * On HSW+ the behaviour of the scanline counter depends on the output
12817 * type. For DP ports it behaves like most other platforms, but on HDMI
12818 * there's an extra 1 line difference. So we need to add two instead of
12819 * one to the value.
12821 if (IS_GEN2(dev
)) {
12822 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
12825 vtotal
= adjusted_mode
->crtc_vtotal
;
12826 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
12829 crtc
->scanline_offset
= vtotal
- 1;
12830 } else if (HAS_DDI(dev
) &&
12831 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
12832 crtc
->scanline_offset
= 2;
12834 crtc
->scanline_offset
= 1;
12837 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
12839 struct drm_device
*dev
= state
->dev
;
12840 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12841 struct intel_shared_dpll_config
*shared_dpll
= NULL
;
12842 struct intel_crtc
*intel_crtc
;
12843 struct intel_crtc_state
*intel_crtc_state
;
12844 struct drm_crtc
*crtc
;
12845 struct drm_crtc_state
*crtc_state
;
12848 if (!dev_priv
->display
.crtc_compute_clock
)
12851 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12854 intel_crtc
= to_intel_crtc(crtc
);
12855 intel_crtc_state
= to_intel_crtc_state(crtc_state
);
12856 dpll
= intel_crtc_state
->shared_dpll
;
12858 if (!needs_modeset(crtc_state
) || dpll
== DPLL_ID_PRIVATE
)
12861 intel_crtc_state
->shared_dpll
= DPLL_ID_PRIVATE
;
12864 shared_dpll
= intel_atomic_get_shared_dpll_state(state
);
12866 shared_dpll
[dpll
].crtc_mask
&= ~(1 << intel_crtc
->pipe
);
12871 * This implements the workaround described in the "notes" section of the mode
12872 * set sequence documentation. When going from no pipes or single pipe to
12873 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12874 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12876 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
12878 struct drm_crtc_state
*crtc_state
;
12879 struct intel_crtc
*intel_crtc
;
12880 struct drm_crtc
*crtc
;
12881 struct intel_crtc_state
*first_crtc_state
= NULL
;
12882 struct intel_crtc_state
*other_crtc_state
= NULL
;
12883 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
12886 /* look at all crtc's that are going to be enabled in during modeset */
12887 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12888 intel_crtc
= to_intel_crtc(crtc
);
12890 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
12893 if (first_crtc_state
) {
12894 other_crtc_state
= to_intel_crtc_state(crtc_state
);
12897 first_crtc_state
= to_intel_crtc_state(crtc_state
);
12898 first_pipe
= intel_crtc
->pipe
;
12902 /* No workaround needed? */
12903 if (!first_crtc_state
)
12906 /* w/a possibly needed, check how many crtc's are already enabled. */
12907 for_each_intel_crtc(state
->dev
, intel_crtc
) {
12908 struct intel_crtc_state
*pipe_config
;
12910 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
12911 if (IS_ERR(pipe_config
))
12912 return PTR_ERR(pipe_config
);
12914 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
12916 if (!pipe_config
->base
.active
||
12917 needs_modeset(&pipe_config
->base
))
12920 /* 2 or more enabled crtcs means no need for w/a */
12921 if (enabled_pipe
!= INVALID_PIPE
)
12924 enabled_pipe
= intel_crtc
->pipe
;
12927 if (enabled_pipe
!= INVALID_PIPE
)
12928 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
12929 else if (other_crtc_state
)
12930 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
12935 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
12937 struct drm_crtc
*crtc
;
12938 struct drm_crtc_state
*crtc_state
;
12941 /* add all active pipes to the state */
12942 for_each_crtc(state
->dev
, crtc
) {
12943 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
12944 if (IS_ERR(crtc_state
))
12945 return PTR_ERR(crtc_state
);
12947 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
12950 crtc_state
->mode_changed
= true;
12952 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12956 ret
= drm_atomic_add_affected_planes(state
, crtc
);
12964 static int intel_modeset_checks(struct drm_atomic_state
*state
)
12966 struct drm_device
*dev
= state
->dev
;
12967 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12970 if (!check_digital_port_conflicts(state
)) {
12971 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12976 * See if the config requires any additional preparation, e.g.
12977 * to adjust global state with pipes off. We need to do this
12978 * here so we can get the modeset_pipe updated config for the new
12979 * mode set on this crtc. For other crtcs we need to use the
12980 * adjusted_mode bits in the crtc directly.
12982 if (dev_priv
->display
.modeset_calc_cdclk
) {
12983 unsigned int cdclk
;
12985 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
12987 cdclk
= to_intel_atomic_state(state
)->cdclk
;
12988 if (!ret
&& cdclk
!= dev_priv
->cdclk_freq
)
12989 ret
= intel_modeset_all_pipes(state
);
12994 to_intel_atomic_state(state
)->cdclk
= dev_priv
->cdclk_freq
;
12996 intel_modeset_clear_plls(state
);
12998 if (IS_HASWELL(dev
))
12999 return haswell_mode_set_planes_workaround(state
);
13005 * intel_atomic_check - validate state object
13007 * @state: state to validate
13009 static int intel_atomic_check(struct drm_device
*dev
,
13010 struct drm_atomic_state
*state
)
13012 struct drm_crtc
*crtc
;
13013 struct drm_crtc_state
*crtc_state
;
13015 bool any_ms
= false;
13017 ret
= drm_atomic_helper_check_modeset(dev
, state
);
13021 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13022 struct intel_crtc_state
*pipe_config
=
13023 to_intel_crtc_state(crtc_state
);
13025 /* Catch I915_MODE_FLAG_INHERITED */
13026 if (crtc_state
->mode
.private_flags
!= crtc
->state
->mode
.private_flags
)
13027 crtc_state
->mode_changed
= true;
13029 if (!crtc_state
->enable
) {
13030 if (needs_modeset(crtc_state
))
13035 if (!needs_modeset(crtc_state
))
13038 /* FIXME: For only active_changed we shouldn't need to do any
13039 * state recomputation at all. */
13041 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13045 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
13049 if (intel_pipe_config_compare(state
->dev
,
13050 to_intel_crtc_state(crtc
->state
),
13051 pipe_config
, true)) {
13052 crtc_state
->mode_changed
= false;
13053 to_intel_crtc_state(crtc_state
)->update_pipe
= true;
13056 if (needs_modeset(crtc_state
)) {
13059 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13064 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
13065 needs_modeset(crtc_state
) ?
13066 "[modeset]" : "[fastset]");
13070 ret
= intel_modeset_checks(state
);
13075 to_intel_atomic_state(state
)->cdclk
=
13076 to_i915(state
->dev
)->cdclk_freq
;
13078 return drm_atomic_helper_check_planes(state
->dev
, state
);
13082 * intel_atomic_commit - commit validated state object
13084 * @state: the top-level driver state object
13085 * @async: asynchronous commit
13087 * This function commits a top-level state object that has been validated
13088 * with drm_atomic_helper_check().
13090 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13091 * we can only handle plane-related operations and do not yet support
13092 * asynchronous commit.
13095 * Zero for success or -errno.
13097 static int intel_atomic_commit(struct drm_device
*dev
,
13098 struct drm_atomic_state
*state
,
13101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13102 struct drm_crtc
*crtc
;
13103 struct drm_crtc_state
*crtc_state
;
13106 bool any_ms
= false;
13109 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13113 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
13117 drm_atomic_helper_swap_state(dev
, state
);
13119 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13120 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13122 if (!needs_modeset(crtc
->state
))
13126 intel_pre_plane_update(intel_crtc
);
13128 if (crtc_state
->active
) {
13129 intel_crtc_disable_planes(crtc
, crtc_state
->plane_mask
);
13130 dev_priv
->display
.crtc_disable(crtc
);
13131 intel_crtc
->active
= false;
13132 intel_disable_shared_dpll(intel_crtc
);
13136 /* Only after disabling all output pipelines that will be changed can we
13137 * update the the output configuration. */
13138 intel_modeset_update_crtc_state(state
);
13141 intel_shared_dpll_commit(state
);
13143 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
13144 modeset_update_crtc_power_domains(state
);
13147 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13148 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13149 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13150 bool modeset
= needs_modeset(crtc
->state
);
13151 bool update_pipe
= !modeset
&&
13152 to_intel_crtc_state(crtc
->state
)->update_pipe
;
13153 unsigned long put_domains
= 0;
13155 if (modeset
&& crtc
->state
->active
) {
13156 update_scanline_offset(to_intel_crtc(crtc
));
13157 dev_priv
->display
.crtc_enable(crtc
);
13161 put_domains
= modeset_get_crtc_power_domains(crtc
);
13163 /* make sure intel_modeset_check_state runs */
13168 intel_pre_plane_update(intel_crtc
);
13170 drm_atomic_helper_commit_planes_on_crtc(crtc_state
);
13173 modeset_put_power_domains(dev_priv
, put_domains
);
13175 intel_post_plane_update(intel_crtc
);
13178 /* FIXME: add subpixel order */
13180 drm_atomic_helper_wait_for_vblanks(dev
, state
);
13181 drm_atomic_helper_cleanup_planes(dev
, state
);
13184 intel_modeset_check_state(dev
, state
);
13186 drm_atomic_state_free(state
);
13191 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
13193 struct drm_device
*dev
= crtc
->dev
;
13194 struct drm_atomic_state
*state
;
13195 struct drm_crtc_state
*crtc_state
;
13198 state
= drm_atomic_state_alloc(dev
);
13200 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13205 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
13208 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13209 ret
= PTR_ERR_OR_ZERO(crtc_state
);
13211 if (!crtc_state
->active
)
13214 crtc_state
->mode_changed
= true;
13215 ret
= drm_atomic_commit(state
);
13218 if (ret
== -EDEADLK
) {
13219 drm_atomic_state_clear(state
);
13220 drm_modeset_backoff(state
->acquire_ctx
);
13226 drm_atomic_state_free(state
);
13229 #undef for_each_intel_crtc_masked
13231 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13232 .gamma_set
= intel_crtc_gamma_set
,
13233 .set_config
= drm_atomic_helper_set_config
,
13234 .destroy
= intel_crtc_destroy
,
13235 .page_flip
= intel_crtc_page_flip
,
13236 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13237 .atomic_destroy_state
= intel_crtc_destroy_state
,
13240 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
13241 struct intel_shared_dpll
*pll
,
13242 struct intel_dpll_hw_state
*hw_state
)
13246 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
13249 val
= I915_READ(PCH_DPLL(pll
->id
));
13250 hw_state
->dpll
= val
;
13251 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
13252 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
13254 return val
& DPLL_VCO_ENABLE
;
13257 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
13258 struct intel_shared_dpll
*pll
)
13260 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
13261 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
13264 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
13265 struct intel_shared_dpll
*pll
)
13267 /* PCH refclock must be enabled first */
13268 ibx_assert_pch_refclk_enabled(dev_priv
);
13270 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13272 /* Wait for the clocks to stabilize. */
13273 POSTING_READ(PCH_DPLL(pll
->id
));
13276 /* The pixel multiplier can only be updated once the
13277 * DPLL is enabled and the clocks are stable.
13279 * So write it again.
13281 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13282 POSTING_READ(PCH_DPLL(pll
->id
));
13286 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
13287 struct intel_shared_dpll
*pll
)
13289 struct drm_device
*dev
= dev_priv
->dev
;
13290 struct intel_crtc
*crtc
;
13292 /* Make sure no transcoder isn't still depending on us. */
13293 for_each_intel_crtc(dev
, crtc
) {
13294 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
13295 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
13298 I915_WRITE(PCH_DPLL(pll
->id
), 0);
13299 POSTING_READ(PCH_DPLL(pll
->id
));
13303 static char *ibx_pch_dpll_names
[] = {
13308 static void ibx_pch_dpll_init(struct drm_device
*dev
)
13310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13313 dev_priv
->num_shared_dpll
= 2;
13315 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13316 dev_priv
->shared_dplls
[i
].id
= i
;
13317 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
13318 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
13319 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
13320 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
13321 dev_priv
->shared_dplls
[i
].get_hw_state
=
13322 ibx_pch_dpll_get_hw_state
;
13326 static void intel_shared_dpll_init(struct drm_device
*dev
)
13328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13330 intel_update_cdclk(dev
);
13333 intel_ddi_pll_init(dev
);
13334 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
13335 ibx_pch_dpll_init(dev
);
13337 dev_priv
->num_shared_dpll
= 0;
13339 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
13343 * intel_prepare_plane_fb - Prepare fb for usage on plane
13344 * @plane: drm plane to prepare for
13345 * @fb: framebuffer to prepare for presentation
13347 * Prepares a framebuffer for usage on a display plane. Generally this
13348 * involves pinning the underlying object and updating the frontbuffer tracking
13349 * bits. Some older platforms need special physical address handling for
13352 * Returns 0 on success, negative error code on failure.
13355 intel_prepare_plane_fb(struct drm_plane
*plane
,
13356 const struct drm_plane_state
*new_state
)
13358 struct drm_device
*dev
= plane
->dev
;
13359 struct drm_framebuffer
*fb
= new_state
->fb
;
13360 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13361 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13362 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
13368 mutex_lock(&dev
->struct_mutex
);
13370 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
13371 INTEL_INFO(dev
)->cursor_needs_physical
) {
13372 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
13373 ret
= i915_gem_object_attach_phys(obj
, align
);
13375 DRM_DEBUG_KMS("failed to attach phys object\n");
13377 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, new_state
, NULL
, NULL
);
13381 i915_gem_track_fb(old_obj
, obj
, intel_plane
->frontbuffer_bit
);
13383 mutex_unlock(&dev
->struct_mutex
);
13389 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13390 * @plane: drm plane to clean up for
13391 * @fb: old framebuffer that was on plane
13393 * Cleans up a framebuffer that has just been removed from a plane.
13396 intel_cleanup_plane_fb(struct drm_plane
*plane
,
13397 const struct drm_plane_state
*old_state
)
13399 struct drm_device
*dev
= plane
->dev
;
13400 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_state
->fb
);
13405 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
13406 !INTEL_INFO(dev
)->cursor_needs_physical
) {
13407 mutex_lock(&dev
->struct_mutex
);
13408 intel_unpin_fb_obj(old_state
->fb
, old_state
);
13409 mutex_unlock(&dev
->struct_mutex
);
13414 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
13417 struct drm_device
*dev
;
13418 struct drm_i915_private
*dev_priv
;
13419 int crtc_clock
, cdclk
;
13421 if (!intel_crtc
|| !crtc_state
)
13422 return DRM_PLANE_HELPER_NO_SCALING
;
13424 dev
= intel_crtc
->base
.dev
;
13425 dev_priv
= dev
->dev_private
;
13426 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
13427 cdclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
;
13429 if (!crtc_clock
|| !cdclk
)
13430 return DRM_PLANE_HELPER_NO_SCALING
;
13433 * skl max scale is lower of:
13434 * close to 3 but not 3, -1 is for that purpose
13438 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
13444 intel_check_primary_plane(struct drm_plane
*plane
,
13445 struct intel_crtc_state
*crtc_state
,
13446 struct intel_plane_state
*state
)
13448 struct drm_crtc
*crtc
= state
->base
.crtc
;
13449 struct drm_framebuffer
*fb
= state
->base
.fb
;
13450 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13451 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13452 bool can_position
= false;
13454 /* use scaler when colorkey is not required */
13455 if (INTEL_INFO(plane
->dev
)->gen
>= 9 &&
13456 state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
13458 max_scale
= skl_max_scale(to_intel_crtc(crtc
), crtc_state
);
13459 can_position
= true;
13462 return drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
13463 &state
->dst
, &state
->clip
,
13464 min_scale
, max_scale
,
13465 can_position
, true,
13470 intel_commit_primary_plane(struct drm_plane
*plane
,
13471 struct intel_plane_state
*state
)
13473 struct drm_crtc
*crtc
= state
->base
.crtc
;
13474 struct drm_framebuffer
*fb
= state
->base
.fb
;
13475 struct drm_device
*dev
= plane
->dev
;
13476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13477 struct intel_crtc
*intel_crtc
;
13478 struct drm_rect
*src
= &state
->src
;
13480 crtc
= crtc
? crtc
: plane
->crtc
;
13481 intel_crtc
= to_intel_crtc(crtc
);
13484 crtc
->x
= src
->x1
>> 16;
13485 crtc
->y
= src
->y1
>> 16;
13487 if (!crtc
->state
->active
)
13490 dev_priv
->display
.update_primary_plane(crtc
, fb
,
13491 state
->src
.x1
>> 16,
13492 state
->src
.y1
>> 16);
13496 intel_disable_primary_plane(struct drm_plane
*plane
,
13497 struct drm_crtc
*crtc
)
13499 struct drm_device
*dev
= plane
->dev
;
13500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13502 dev_priv
->display
.update_primary_plane(crtc
, NULL
, 0, 0);
13505 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
,
13506 struct drm_crtc_state
*old_crtc_state
)
13508 struct drm_device
*dev
= crtc
->dev
;
13509 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13510 struct intel_crtc_state
*old_intel_state
=
13511 to_intel_crtc_state(old_crtc_state
);
13512 bool modeset
= needs_modeset(crtc
->state
);
13514 if (intel_crtc
->atomic
.update_wm_pre
)
13515 intel_update_watermarks(crtc
);
13517 /* Perform vblank evasion around commit operation */
13518 if (crtc
->state
->active
)
13519 intel_pipe_update_start(intel_crtc
);
13524 if (to_intel_crtc_state(crtc
->state
)->update_pipe
)
13525 intel_update_pipe_config(intel_crtc
, old_intel_state
);
13526 else if (INTEL_INFO(dev
)->gen
>= 9)
13527 skl_detach_scalers(intel_crtc
);
13530 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
,
13531 struct drm_crtc_state
*old_crtc_state
)
13533 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13535 if (crtc
->state
->active
)
13536 intel_pipe_update_end(intel_crtc
);
13540 * intel_plane_destroy - destroy a plane
13541 * @plane: plane to destroy
13543 * Common destruction function for all types of planes (primary, cursor,
13546 void intel_plane_destroy(struct drm_plane
*plane
)
13548 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13549 drm_plane_cleanup(plane
);
13550 kfree(intel_plane
);
13553 const struct drm_plane_funcs intel_plane_funcs
= {
13554 .update_plane
= drm_atomic_helper_update_plane
,
13555 .disable_plane
= drm_atomic_helper_disable_plane
,
13556 .destroy
= intel_plane_destroy
,
13557 .set_property
= drm_atomic_helper_plane_set_property
,
13558 .atomic_get_property
= intel_plane_atomic_get_property
,
13559 .atomic_set_property
= intel_plane_atomic_set_property
,
13560 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13561 .atomic_destroy_state
= intel_plane_destroy_state
,
13565 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
13568 struct intel_plane
*primary
;
13569 struct intel_plane_state
*state
;
13570 const uint32_t *intel_primary_formats
;
13571 unsigned int num_formats
;
13573 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
13574 if (primary
== NULL
)
13577 state
= intel_create_plane_state(&primary
->base
);
13582 primary
->base
.state
= &state
->base
;
13584 primary
->can_scale
= false;
13585 primary
->max_downscale
= 1;
13586 if (INTEL_INFO(dev
)->gen
>= 9) {
13587 primary
->can_scale
= true;
13588 state
->scaler_id
= -1;
13590 primary
->pipe
= pipe
;
13591 primary
->plane
= pipe
;
13592 primary
->frontbuffer_bit
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
13593 primary
->check_plane
= intel_check_primary_plane
;
13594 primary
->commit_plane
= intel_commit_primary_plane
;
13595 primary
->disable_plane
= intel_disable_primary_plane
;
13596 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
13597 primary
->plane
= !pipe
;
13599 if (INTEL_INFO(dev
)->gen
>= 9) {
13600 intel_primary_formats
= skl_primary_formats
;
13601 num_formats
= ARRAY_SIZE(skl_primary_formats
);
13602 } else if (INTEL_INFO(dev
)->gen
>= 4) {
13603 intel_primary_formats
= i965_primary_formats
;
13604 num_formats
= ARRAY_SIZE(i965_primary_formats
);
13606 intel_primary_formats
= i8xx_primary_formats
;
13607 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
13610 drm_universal_plane_init(dev
, &primary
->base
, 0,
13611 &intel_plane_funcs
,
13612 intel_primary_formats
, num_formats
,
13613 DRM_PLANE_TYPE_PRIMARY
);
13615 if (INTEL_INFO(dev
)->gen
>= 4)
13616 intel_create_rotation_property(dev
, primary
);
13618 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
13620 return &primary
->base
;
13623 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
13625 if (!dev
->mode_config
.rotation_property
) {
13626 unsigned long flags
= BIT(DRM_ROTATE_0
) |
13627 BIT(DRM_ROTATE_180
);
13629 if (INTEL_INFO(dev
)->gen
>= 9)
13630 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
13632 dev
->mode_config
.rotation_property
=
13633 drm_mode_create_rotation_property(dev
, flags
);
13635 if (dev
->mode_config
.rotation_property
)
13636 drm_object_attach_property(&plane
->base
.base
,
13637 dev
->mode_config
.rotation_property
,
13638 plane
->base
.state
->rotation
);
13642 intel_check_cursor_plane(struct drm_plane
*plane
,
13643 struct intel_crtc_state
*crtc_state
,
13644 struct intel_plane_state
*state
)
13646 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
13647 struct drm_framebuffer
*fb
= state
->base
.fb
;
13648 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13652 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
13653 &state
->dst
, &state
->clip
,
13654 DRM_PLANE_HELPER_NO_SCALING
,
13655 DRM_PLANE_HELPER_NO_SCALING
,
13656 true, true, &state
->visible
);
13660 /* if we want to turn off the cursor ignore width and height */
13664 /* Check for which cursor types we support */
13665 if (!cursor_size_ok(plane
->dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
13666 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13667 state
->base
.crtc_w
, state
->base
.crtc_h
);
13671 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
13672 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
13673 DRM_DEBUG_KMS("buffer is too small\n");
13677 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
13678 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13686 intel_disable_cursor_plane(struct drm_plane
*plane
,
13687 struct drm_crtc
*crtc
)
13689 intel_crtc_update_cursor(crtc
, false);
13693 intel_commit_cursor_plane(struct drm_plane
*plane
,
13694 struct intel_plane_state
*state
)
13696 struct drm_crtc
*crtc
= state
->base
.crtc
;
13697 struct drm_device
*dev
= plane
->dev
;
13698 struct intel_crtc
*intel_crtc
;
13699 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
13702 crtc
= crtc
? crtc
: plane
->crtc
;
13703 intel_crtc
= to_intel_crtc(crtc
);
13705 if (intel_crtc
->cursor_bo
== obj
)
13710 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
13711 addr
= i915_gem_obj_ggtt_offset(obj
);
13713 addr
= obj
->phys_handle
->busaddr
;
13715 intel_crtc
->cursor_addr
= addr
;
13716 intel_crtc
->cursor_bo
= obj
;
13719 if (crtc
->state
->active
)
13720 intel_crtc_update_cursor(crtc
, state
->visible
);
13723 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
13726 struct intel_plane
*cursor
;
13727 struct intel_plane_state
*state
;
13729 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
13730 if (cursor
== NULL
)
13733 state
= intel_create_plane_state(&cursor
->base
);
13738 cursor
->base
.state
= &state
->base
;
13740 cursor
->can_scale
= false;
13741 cursor
->max_downscale
= 1;
13742 cursor
->pipe
= pipe
;
13743 cursor
->plane
= pipe
;
13744 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER_CURSOR(pipe
);
13745 cursor
->check_plane
= intel_check_cursor_plane
;
13746 cursor
->commit_plane
= intel_commit_cursor_plane
;
13747 cursor
->disable_plane
= intel_disable_cursor_plane
;
13749 drm_universal_plane_init(dev
, &cursor
->base
, 0,
13750 &intel_plane_funcs
,
13751 intel_cursor_formats
,
13752 ARRAY_SIZE(intel_cursor_formats
),
13753 DRM_PLANE_TYPE_CURSOR
);
13755 if (INTEL_INFO(dev
)->gen
>= 4) {
13756 if (!dev
->mode_config
.rotation_property
)
13757 dev
->mode_config
.rotation_property
=
13758 drm_mode_create_rotation_property(dev
,
13759 BIT(DRM_ROTATE_0
) |
13760 BIT(DRM_ROTATE_180
));
13761 if (dev
->mode_config
.rotation_property
)
13762 drm_object_attach_property(&cursor
->base
.base
,
13763 dev
->mode_config
.rotation_property
,
13764 state
->base
.rotation
);
13767 if (INTEL_INFO(dev
)->gen
>=9)
13768 state
->scaler_id
= -1;
13770 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
13772 return &cursor
->base
;
13775 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
13776 struct intel_crtc_state
*crtc_state
)
13779 struct intel_scaler
*intel_scaler
;
13780 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
13782 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
13783 intel_scaler
= &scaler_state
->scalers
[i
];
13784 intel_scaler
->in_use
= 0;
13785 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
13788 scaler_state
->scaler_id
= -1;
13791 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
13793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13794 struct intel_crtc
*intel_crtc
;
13795 struct intel_crtc_state
*crtc_state
= NULL
;
13796 struct drm_plane
*primary
= NULL
;
13797 struct drm_plane
*cursor
= NULL
;
13800 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
13801 if (intel_crtc
== NULL
)
13804 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
13807 intel_crtc
->config
= crtc_state
;
13808 intel_crtc
->base
.state
= &crtc_state
->base
;
13809 crtc_state
->base
.crtc
= &intel_crtc
->base
;
13811 /* initialize shared scalers */
13812 if (INTEL_INFO(dev
)->gen
>= 9) {
13813 if (pipe
== PIPE_C
)
13814 intel_crtc
->num_scalers
= 1;
13816 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
13818 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
13821 primary
= intel_primary_plane_create(dev
, pipe
);
13825 cursor
= intel_cursor_plane_create(dev
, pipe
);
13829 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
13830 cursor
, &intel_crtc_funcs
);
13834 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
13835 for (i
= 0; i
< 256; i
++) {
13836 intel_crtc
->lut_r
[i
] = i
;
13837 intel_crtc
->lut_g
[i
] = i
;
13838 intel_crtc
->lut_b
[i
] = i
;
13842 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13843 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13845 intel_crtc
->pipe
= pipe
;
13846 intel_crtc
->plane
= pipe
;
13847 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
13848 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13849 intel_crtc
->plane
= !pipe
;
13852 intel_crtc
->cursor_base
= ~0;
13853 intel_crtc
->cursor_cntl
= ~0;
13854 intel_crtc
->cursor_size
= ~0;
13856 intel_crtc
->wm
.cxsr_allowed
= true;
13858 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
13859 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
13860 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
13861 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
13863 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
13865 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
13870 drm_plane_cleanup(primary
);
13872 drm_plane_cleanup(cursor
);
13877 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
13879 struct drm_encoder
*encoder
= connector
->base
.encoder
;
13880 struct drm_device
*dev
= connector
->base
.dev
;
13882 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
13884 if (!encoder
|| WARN_ON(!encoder
->crtc
))
13885 return INVALID_PIPE
;
13887 return to_intel_crtc(encoder
->crtc
)->pipe
;
13890 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
13891 struct drm_file
*file
)
13893 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
13894 struct drm_crtc
*drmmode_crtc
;
13895 struct intel_crtc
*crtc
;
13897 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
13899 if (!drmmode_crtc
) {
13900 DRM_ERROR("no such CRTC id\n");
13904 crtc
= to_intel_crtc(drmmode_crtc
);
13905 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
13910 static int intel_encoder_clones(struct intel_encoder
*encoder
)
13912 struct drm_device
*dev
= encoder
->base
.dev
;
13913 struct intel_encoder
*source_encoder
;
13914 int index_mask
= 0;
13917 for_each_intel_encoder(dev
, source_encoder
) {
13918 if (encoders_cloneable(encoder
, source_encoder
))
13919 index_mask
|= (1 << entry
);
13927 static bool has_edp_a(struct drm_device
*dev
)
13929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13931 if (!IS_MOBILE(dev
))
13934 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
13937 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
13943 static bool intel_crt_present(struct drm_device
*dev
)
13945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13947 if (INTEL_INFO(dev
)->gen
>= 9)
13950 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
13953 if (IS_CHERRYVIEW(dev
))
13956 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
13962 static void intel_setup_outputs(struct drm_device
*dev
)
13964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13965 struct intel_encoder
*encoder
;
13966 bool dpd_is_edp
= false;
13968 intel_lvds_init(dev
);
13970 if (intel_crt_present(dev
))
13971 intel_crt_init(dev
);
13973 if (IS_BROXTON(dev
)) {
13975 * FIXME: Broxton doesn't support port detection via the
13976 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13977 * detect the ports.
13979 intel_ddi_init(dev
, PORT_A
);
13980 intel_ddi_init(dev
, PORT_B
);
13981 intel_ddi_init(dev
, PORT_C
);
13982 } else if (HAS_DDI(dev
)) {
13986 * Haswell uses DDI functions to detect digital outputs.
13987 * On SKL pre-D0 the strap isn't connected, so we assume
13990 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
13991 /* WaIgnoreDDIAStrap: skl */
13992 if (found
|| IS_SKYLAKE(dev
))
13993 intel_ddi_init(dev
, PORT_A
);
13995 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13997 found
= I915_READ(SFUSE_STRAP
);
13999 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
14000 intel_ddi_init(dev
, PORT_B
);
14001 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
14002 intel_ddi_init(dev
, PORT_C
);
14003 if (found
& SFUSE_STRAP_DDID_DETECTED
)
14004 intel_ddi_init(dev
, PORT_D
);
14006 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14008 if (IS_SKYLAKE(dev
) &&
14009 (dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dp
||
14010 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dvi
||
14011 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_hdmi
))
14012 intel_ddi_init(dev
, PORT_E
);
14014 } else if (HAS_PCH_SPLIT(dev
)) {
14016 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
14018 if (has_edp_a(dev
))
14019 intel_dp_init(dev
, DP_A
, PORT_A
);
14021 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
14022 /* PCH SDVOB multiplex with HDMIB */
14023 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
14025 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
14026 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
14027 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
14030 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
14031 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
14033 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
14034 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
14036 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
14037 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
14039 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
14040 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
14041 } else if (IS_VALLEYVIEW(dev
)) {
14043 * The DP_DETECTED bit is the latched state of the DDC
14044 * SDA pin at boot. However since eDP doesn't require DDC
14045 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14046 * eDP ports may have been muxed to an alternate function.
14047 * Thus we can't rely on the DP_DETECTED bit alone to detect
14048 * eDP ports. Consult the VBT as well as DP_DETECTED to
14049 * detect eDP ports.
14051 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
14052 !intel_dp_is_edp(dev
, PORT_B
))
14053 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
14055 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
14056 intel_dp_is_edp(dev
, PORT_B
))
14057 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
14059 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
14060 !intel_dp_is_edp(dev
, PORT_C
))
14061 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
14063 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
14064 intel_dp_is_edp(dev
, PORT_C
))
14065 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
14067 if (IS_CHERRYVIEW(dev
)) {
14068 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
14069 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
14071 /* eDP not supported on port D, so don't check VBT */
14072 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
14073 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
14076 intel_dsi_init(dev
);
14077 } else if (!IS_GEN2(dev
) && !IS_PINEVIEW(dev
)) {
14078 bool found
= false;
14080 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14081 DRM_DEBUG_KMS("probing SDVOB\n");
14082 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
14083 if (!found
&& IS_G4X(dev
)) {
14084 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14085 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
14088 if (!found
&& IS_G4X(dev
))
14089 intel_dp_init(dev
, DP_B
, PORT_B
);
14092 /* Before G4X SDVOC doesn't have its own detect register */
14094 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14095 DRM_DEBUG_KMS("probing SDVOC\n");
14096 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
14099 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14102 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14103 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
14106 intel_dp_init(dev
, DP_C
, PORT_C
);
14110 (I915_READ(DP_D
) & DP_DETECTED
))
14111 intel_dp_init(dev
, DP_D
, PORT_D
);
14112 } else if (IS_GEN2(dev
))
14113 intel_dvo_init(dev
);
14115 if (SUPPORTS_TV(dev
))
14116 intel_tv_init(dev
);
14118 intel_psr_init(dev
);
14120 for_each_intel_encoder(dev
, encoder
) {
14121 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
14122 encoder
->base
.possible_clones
=
14123 intel_encoder_clones(encoder
);
14126 intel_init_pch_refclk(dev
);
14128 drm_helper_move_panel_connectors_to_head(dev
);
14131 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
14133 struct drm_device
*dev
= fb
->dev
;
14134 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14136 drm_framebuffer_cleanup(fb
);
14137 mutex_lock(&dev
->struct_mutex
);
14138 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
14139 drm_gem_object_unreference(&intel_fb
->obj
->base
);
14140 mutex_unlock(&dev
->struct_mutex
);
14144 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
14145 struct drm_file
*file
,
14146 unsigned int *handle
)
14148 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14149 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14151 return drm_gem_handle_create(file
, &obj
->base
, handle
);
14154 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
14155 struct drm_file
*file
,
14156 unsigned flags
, unsigned color
,
14157 struct drm_clip_rect
*clips
,
14158 unsigned num_clips
)
14160 struct drm_device
*dev
= fb
->dev
;
14161 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14162 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14164 mutex_lock(&dev
->struct_mutex
);
14165 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
14166 mutex_unlock(&dev
->struct_mutex
);
14171 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
14172 .destroy
= intel_user_framebuffer_destroy
,
14173 .create_handle
= intel_user_framebuffer_create_handle
,
14174 .dirty
= intel_user_framebuffer_dirty
,
14178 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
14179 uint32_t pixel_format
)
14181 u32 gen
= INTEL_INFO(dev
)->gen
;
14184 /* "The stride in bytes must not exceed the of the size of 8K
14185 * pixels and 32K bytes."
14187 return min(8192*drm_format_plane_cpp(pixel_format
, 0), 32768);
14188 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
14190 } else if (gen
>= 4) {
14191 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14195 } else if (gen
>= 3) {
14196 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14201 /* XXX DSPC is limited to 4k tiled */
14206 static int intel_framebuffer_init(struct drm_device
*dev
,
14207 struct intel_framebuffer
*intel_fb
,
14208 struct drm_mode_fb_cmd2
*mode_cmd
,
14209 struct drm_i915_gem_object
*obj
)
14211 unsigned int aligned_height
;
14213 u32 pitch_limit
, stride_alignment
;
14215 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
14217 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
14218 /* Enforce that fb modifier and tiling mode match, but only for
14219 * X-tiled. This is needed for FBC. */
14220 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
14221 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
14222 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14226 if (obj
->tiling_mode
== I915_TILING_X
)
14227 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
14228 else if (obj
->tiling_mode
== I915_TILING_Y
) {
14229 DRM_DEBUG("No Y tiling for legacy addfb\n");
14234 /* Passed in modifier sanity checking. */
14235 switch (mode_cmd
->modifier
[0]) {
14236 case I915_FORMAT_MOD_Y_TILED
:
14237 case I915_FORMAT_MOD_Yf_TILED
:
14238 if (INTEL_INFO(dev
)->gen
< 9) {
14239 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14240 mode_cmd
->modifier
[0]);
14243 case DRM_FORMAT_MOD_NONE
:
14244 case I915_FORMAT_MOD_X_TILED
:
14247 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14248 mode_cmd
->modifier
[0]);
14252 stride_alignment
= intel_fb_stride_alignment(dev
, mode_cmd
->modifier
[0],
14253 mode_cmd
->pixel_format
);
14254 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
14255 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14256 mode_cmd
->pitches
[0], stride_alignment
);
14260 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
14261 mode_cmd
->pixel_format
);
14262 if (mode_cmd
->pitches
[0] > pitch_limit
) {
14263 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14264 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
14265 "tiled" : "linear",
14266 mode_cmd
->pitches
[0], pitch_limit
);
14270 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
14271 mode_cmd
->pitches
[0] != obj
->stride
) {
14272 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14273 mode_cmd
->pitches
[0], obj
->stride
);
14277 /* Reject formats not supported by any plane early. */
14278 switch (mode_cmd
->pixel_format
) {
14279 case DRM_FORMAT_C8
:
14280 case DRM_FORMAT_RGB565
:
14281 case DRM_FORMAT_XRGB8888
:
14282 case DRM_FORMAT_ARGB8888
:
14284 case DRM_FORMAT_XRGB1555
:
14285 if (INTEL_INFO(dev
)->gen
> 3) {
14286 DRM_DEBUG("unsupported pixel format: %s\n",
14287 drm_get_format_name(mode_cmd
->pixel_format
));
14291 case DRM_FORMAT_ABGR8888
:
14292 if (!IS_VALLEYVIEW(dev
) && INTEL_INFO(dev
)->gen
< 9) {
14293 DRM_DEBUG("unsupported pixel format: %s\n",
14294 drm_get_format_name(mode_cmd
->pixel_format
));
14298 case DRM_FORMAT_XBGR8888
:
14299 case DRM_FORMAT_XRGB2101010
:
14300 case DRM_FORMAT_XBGR2101010
:
14301 if (INTEL_INFO(dev
)->gen
< 4) {
14302 DRM_DEBUG("unsupported pixel format: %s\n",
14303 drm_get_format_name(mode_cmd
->pixel_format
));
14307 case DRM_FORMAT_ABGR2101010
:
14308 if (!IS_VALLEYVIEW(dev
)) {
14309 DRM_DEBUG("unsupported pixel format: %s\n",
14310 drm_get_format_name(mode_cmd
->pixel_format
));
14314 case DRM_FORMAT_YUYV
:
14315 case DRM_FORMAT_UYVY
:
14316 case DRM_FORMAT_YVYU
:
14317 case DRM_FORMAT_VYUY
:
14318 if (INTEL_INFO(dev
)->gen
< 5) {
14319 DRM_DEBUG("unsupported pixel format: %s\n",
14320 drm_get_format_name(mode_cmd
->pixel_format
));
14325 DRM_DEBUG("unsupported pixel format: %s\n",
14326 drm_get_format_name(mode_cmd
->pixel_format
));
14330 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14331 if (mode_cmd
->offsets
[0] != 0)
14334 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
14335 mode_cmd
->pixel_format
,
14336 mode_cmd
->modifier
[0]);
14337 /* FIXME drm helper for size checks (especially planar formats)? */
14338 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
14341 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
14342 intel_fb
->obj
= obj
;
14343 intel_fb
->obj
->framebuffer_references
++;
14345 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
14347 DRM_ERROR("framebuffer init failed %d\n", ret
);
14354 static struct drm_framebuffer
*
14355 intel_user_framebuffer_create(struct drm_device
*dev
,
14356 struct drm_file
*filp
,
14357 struct drm_mode_fb_cmd2
*mode_cmd
)
14359 struct drm_i915_gem_object
*obj
;
14361 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
14362 mode_cmd
->handles
[0]));
14363 if (&obj
->base
== NULL
)
14364 return ERR_PTR(-ENOENT
);
14366 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
14369 #ifndef CONFIG_DRM_FBDEV_EMULATION
14370 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
14375 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14376 .fb_create
= intel_user_framebuffer_create
,
14377 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14378 .atomic_check
= intel_atomic_check
,
14379 .atomic_commit
= intel_atomic_commit
,
14380 .atomic_state_alloc
= intel_atomic_state_alloc
,
14381 .atomic_state_clear
= intel_atomic_state_clear
,
14384 /* Set up chip specific display functions */
14385 static void intel_init_display(struct drm_device
*dev
)
14387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14389 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
14390 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
14391 else if (IS_CHERRYVIEW(dev
))
14392 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
14393 else if (IS_VALLEYVIEW(dev
))
14394 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
14395 else if (IS_PINEVIEW(dev
))
14396 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
14398 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
14400 if (INTEL_INFO(dev
)->gen
>= 9) {
14401 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14402 dev_priv
->display
.get_initial_plane_config
=
14403 skylake_get_initial_plane_config
;
14404 dev_priv
->display
.crtc_compute_clock
=
14405 haswell_crtc_compute_clock
;
14406 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14407 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14408 dev_priv
->display
.update_primary_plane
=
14409 skylake_update_primary_plane
;
14410 } else if (HAS_DDI(dev
)) {
14411 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14412 dev_priv
->display
.get_initial_plane_config
=
14413 ironlake_get_initial_plane_config
;
14414 dev_priv
->display
.crtc_compute_clock
=
14415 haswell_crtc_compute_clock
;
14416 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14417 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14418 dev_priv
->display
.update_primary_plane
=
14419 ironlake_update_primary_plane
;
14420 } else if (HAS_PCH_SPLIT(dev
)) {
14421 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14422 dev_priv
->display
.get_initial_plane_config
=
14423 ironlake_get_initial_plane_config
;
14424 dev_priv
->display
.crtc_compute_clock
=
14425 ironlake_crtc_compute_clock
;
14426 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14427 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14428 dev_priv
->display
.update_primary_plane
=
14429 ironlake_update_primary_plane
;
14430 } else if (IS_VALLEYVIEW(dev
)) {
14431 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14432 dev_priv
->display
.get_initial_plane_config
=
14433 i9xx_get_initial_plane_config
;
14434 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14435 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14436 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14437 dev_priv
->display
.update_primary_plane
=
14438 i9xx_update_primary_plane
;
14440 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14441 dev_priv
->display
.get_initial_plane_config
=
14442 i9xx_get_initial_plane_config
;
14443 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14444 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14445 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14446 dev_priv
->display
.update_primary_plane
=
14447 i9xx_update_primary_plane
;
14450 /* Returns the core display clock speed */
14451 if (IS_SKYLAKE(dev
))
14452 dev_priv
->display
.get_display_clock_speed
=
14453 skylake_get_display_clock_speed
;
14454 else if (IS_BROXTON(dev
))
14455 dev_priv
->display
.get_display_clock_speed
=
14456 broxton_get_display_clock_speed
;
14457 else if (IS_BROADWELL(dev
))
14458 dev_priv
->display
.get_display_clock_speed
=
14459 broadwell_get_display_clock_speed
;
14460 else if (IS_HASWELL(dev
))
14461 dev_priv
->display
.get_display_clock_speed
=
14462 haswell_get_display_clock_speed
;
14463 else if (IS_VALLEYVIEW(dev
))
14464 dev_priv
->display
.get_display_clock_speed
=
14465 valleyview_get_display_clock_speed
;
14466 else if (IS_GEN5(dev
))
14467 dev_priv
->display
.get_display_clock_speed
=
14468 ilk_get_display_clock_speed
;
14469 else if (IS_I945G(dev
) || IS_BROADWATER(dev
) ||
14470 IS_GEN6(dev
) || IS_IVYBRIDGE(dev
))
14471 dev_priv
->display
.get_display_clock_speed
=
14472 i945_get_display_clock_speed
;
14473 else if (IS_GM45(dev
))
14474 dev_priv
->display
.get_display_clock_speed
=
14475 gm45_get_display_clock_speed
;
14476 else if (IS_CRESTLINE(dev
))
14477 dev_priv
->display
.get_display_clock_speed
=
14478 i965gm_get_display_clock_speed
;
14479 else if (IS_PINEVIEW(dev
))
14480 dev_priv
->display
.get_display_clock_speed
=
14481 pnv_get_display_clock_speed
;
14482 else if (IS_G33(dev
) || IS_G4X(dev
))
14483 dev_priv
->display
.get_display_clock_speed
=
14484 g33_get_display_clock_speed
;
14485 else if (IS_I915G(dev
))
14486 dev_priv
->display
.get_display_clock_speed
=
14487 i915_get_display_clock_speed
;
14488 else if (IS_I945GM(dev
) || IS_845G(dev
))
14489 dev_priv
->display
.get_display_clock_speed
=
14490 i9xx_misc_get_display_clock_speed
;
14491 else if (IS_PINEVIEW(dev
))
14492 dev_priv
->display
.get_display_clock_speed
=
14493 pnv_get_display_clock_speed
;
14494 else if (IS_I915GM(dev
))
14495 dev_priv
->display
.get_display_clock_speed
=
14496 i915gm_get_display_clock_speed
;
14497 else if (IS_I865G(dev
))
14498 dev_priv
->display
.get_display_clock_speed
=
14499 i865_get_display_clock_speed
;
14500 else if (IS_I85X(dev
))
14501 dev_priv
->display
.get_display_clock_speed
=
14502 i85x_get_display_clock_speed
;
14504 WARN(!IS_I830(dev
), "Unknown platform. Assuming 133 MHz CDCLK\n");
14505 dev_priv
->display
.get_display_clock_speed
=
14506 i830_get_display_clock_speed
;
14509 if (IS_GEN5(dev
)) {
14510 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
14511 } else if (IS_GEN6(dev
)) {
14512 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
14513 } else if (IS_IVYBRIDGE(dev
)) {
14514 /* FIXME: detect B0+ stepping and use auto training */
14515 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
14516 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
14517 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
14518 if (IS_BROADWELL(dev
)) {
14519 dev_priv
->display
.modeset_commit_cdclk
=
14520 broadwell_modeset_commit_cdclk
;
14521 dev_priv
->display
.modeset_calc_cdclk
=
14522 broadwell_modeset_calc_cdclk
;
14524 } else if (IS_VALLEYVIEW(dev
)) {
14525 dev_priv
->display
.modeset_commit_cdclk
=
14526 valleyview_modeset_commit_cdclk
;
14527 dev_priv
->display
.modeset_calc_cdclk
=
14528 valleyview_modeset_calc_cdclk
;
14529 } else if (IS_BROXTON(dev
)) {
14530 dev_priv
->display
.modeset_commit_cdclk
=
14531 broxton_modeset_commit_cdclk
;
14532 dev_priv
->display
.modeset_calc_cdclk
=
14533 broxton_modeset_calc_cdclk
;
14536 switch (INTEL_INFO(dev
)->gen
) {
14538 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
14542 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
14547 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
14551 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
14554 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14555 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
14558 /* Drop through - unsupported since execlist only. */
14560 /* Default just returns -ENODEV to indicate unsupported */
14561 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
14564 intel_panel_init_backlight_funcs(dev
);
14566 mutex_init(&dev_priv
->pps_mutex
);
14570 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14571 * resume, or other times. This quirk makes sure that's the case for
14572 * affected systems.
14574 static void quirk_pipea_force(struct drm_device
*dev
)
14576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14578 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
14579 DRM_INFO("applying pipe a force quirk\n");
14582 static void quirk_pipeb_force(struct drm_device
*dev
)
14584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14586 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
14587 DRM_INFO("applying pipe b force quirk\n");
14591 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14593 static void quirk_ssc_force_disable(struct drm_device
*dev
)
14595 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14596 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
14597 DRM_INFO("applying lvds SSC disable quirk\n");
14601 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14604 static void quirk_invert_brightness(struct drm_device
*dev
)
14606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14607 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
14608 DRM_INFO("applying inverted panel brightness quirk\n");
14611 /* Some VBT's incorrectly indicate no backlight is present */
14612 static void quirk_backlight_present(struct drm_device
*dev
)
14614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14615 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
14616 DRM_INFO("applying backlight present quirk\n");
14619 struct intel_quirk
{
14621 int subsystem_vendor
;
14622 int subsystem_device
;
14623 void (*hook
)(struct drm_device
*dev
);
14626 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14627 struct intel_dmi_quirk
{
14628 void (*hook
)(struct drm_device
*dev
);
14629 const struct dmi_system_id (*dmi_id_list
)[];
14632 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
14634 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
14638 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
14640 .dmi_id_list
= &(const struct dmi_system_id
[]) {
14642 .callback
= intel_dmi_reverse_brightness
,
14643 .ident
= "NCR Corporation",
14644 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
14645 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
14648 { } /* terminating entry */
14650 .hook
= quirk_invert_brightness
,
14654 static struct intel_quirk intel_quirks
[] = {
14655 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14656 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
14658 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14659 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
14661 /* 830 needs to leave pipe A & dpll A up */
14662 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
14664 /* 830 needs to leave pipe B & dpll B up */
14665 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
14667 /* Lenovo U160 cannot use SSC on LVDS */
14668 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
14670 /* Sony Vaio Y cannot use SSC on LVDS */
14671 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
14673 /* Acer Aspire 5734Z must invert backlight brightness */
14674 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
14676 /* Acer/eMachines G725 */
14677 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
14679 /* Acer/eMachines e725 */
14680 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
14682 /* Acer/Packard Bell NCL20 */
14683 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
14685 /* Acer Aspire 4736Z */
14686 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
14688 /* Acer Aspire 5336 */
14689 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
14691 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14692 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
14694 /* Acer C720 Chromebook (Core i3 4005U) */
14695 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
14697 /* Apple Macbook 2,1 (Core 2 T7400) */
14698 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
14700 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14701 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
14703 /* HP Chromebook 14 (Celeron 2955U) */
14704 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
14706 /* Dell Chromebook 11 */
14707 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
14710 static void intel_init_quirks(struct drm_device
*dev
)
14712 struct pci_dev
*d
= dev
->pdev
;
14715 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
14716 struct intel_quirk
*q
= &intel_quirks
[i
];
14718 if (d
->device
== q
->device
&&
14719 (d
->subsystem_vendor
== q
->subsystem_vendor
||
14720 q
->subsystem_vendor
== PCI_ANY_ID
) &&
14721 (d
->subsystem_device
== q
->subsystem_device
||
14722 q
->subsystem_device
== PCI_ANY_ID
))
14725 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
14726 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
14727 intel_dmi_quirks
[i
].hook(dev
);
14731 /* Disable the VGA plane that we never use */
14732 static void i915_disable_vga(struct drm_device
*dev
)
14734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14736 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14738 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14739 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14740 outb(SR01
, VGA_SR_INDEX
);
14741 sr1
= inb(VGA_SR_DATA
);
14742 outb(sr1
| 1<<5, VGA_SR_DATA
);
14743 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14746 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
14747 POSTING_READ(vga_reg
);
14750 void intel_modeset_init_hw(struct drm_device
*dev
)
14752 intel_update_cdclk(dev
);
14753 intel_prepare_ddi(dev
);
14754 intel_init_clock_gating(dev
);
14755 intel_enable_gt_powersave(dev
);
14758 void intel_modeset_init(struct drm_device
*dev
)
14760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14763 struct intel_crtc
*crtc
;
14765 drm_mode_config_init(dev
);
14767 dev
->mode_config
.min_width
= 0;
14768 dev
->mode_config
.min_height
= 0;
14770 dev
->mode_config
.preferred_depth
= 24;
14771 dev
->mode_config
.prefer_shadow
= 1;
14773 dev
->mode_config
.allow_fb_modifiers
= true;
14775 dev
->mode_config
.funcs
= &intel_mode_funcs
;
14777 intel_init_quirks(dev
);
14779 intel_init_pm(dev
);
14781 if (INTEL_INFO(dev
)->num_pipes
== 0)
14785 * There may be no VBT; and if the BIOS enabled SSC we can
14786 * just keep using it to avoid unnecessary flicker. Whereas if the
14787 * BIOS isn't using it, don't assume it will work even if the VBT
14788 * indicates as much.
14790 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
14791 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
14794 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
14795 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14796 bios_lvds_use_ssc
? "en" : "dis",
14797 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
14798 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
14802 intel_init_display(dev
);
14803 intel_init_audio(dev
);
14805 if (IS_GEN2(dev
)) {
14806 dev
->mode_config
.max_width
= 2048;
14807 dev
->mode_config
.max_height
= 2048;
14808 } else if (IS_GEN3(dev
)) {
14809 dev
->mode_config
.max_width
= 4096;
14810 dev
->mode_config
.max_height
= 4096;
14812 dev
->mode_config
.max_width
= 8192;
14813 dev
->mode_config
.max_height
= 8192;
14816 if (IS_845G(dev
) || IS_I865G(dev
)) {
14817 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
14818 dev
->mode_config
.cursor_height
= 1023;
14819 } else if (IS_GEN2(dev
)) {
14820 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
14821 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
14823 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
14824 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
14827 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
14829 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14830 INTEL_INFO(dev
)->num_pipes
,
14831 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
14833 for_each_pipe(dev_priv
, pipe
) {
14834 intel_crtc_init(dev
, pipe
);
14835 for_each_sprite(dev_priv
, pipe
, sprite
) {
14836 ret
= intel_plane_init(dev
, pipe
, sprite
);
14838 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14839 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
14843 intel_shared_dpll_init(dev
);
14845 /* Just disable it once at startup */
14846 i915_disable_vga(dev
);
14847 intel_setup_outputs(dev
);
14849 /* Just in case the BIOS is doing something questionable. */
14850 intel_fbc_disable(dev_priv
);
14852 drm_modeset_lock_all(dev
);
14853 intel_modeset_setup_hw_state(dev
);
14854 drm_modeset_unlock_all(dev
);
14856 for_each_intel_crtc(dev
, crtc
) {
14857 struct intel_initial_plane_config plane_config
= {};
14863 * Note that reserving the BIOS fb up front prevents us
14864 * from stuffing other stolen allocations like the ring
14865 * on top. This prevents some ugliness at boot time, and
14866 * can even allow for smooth boot transitions if the BIOS
14867 * fb is large enough for the active pipe configuration.
14869 dev_priv
->display
.get_initial_plane_config(crtc
,
14873 * If the fb is shared between multiple heads, we'll
14874 * just get the first one.
14876 intel_find_initial_plane_obj(crtc
, &plane_config
);
14880 static void intel_enable_pipe_a(struct drm_device
*dev
)
14882 struct intel_connector
*connector
;
14883 struct drm_connector
*crt
= NULL
;
14884 struct intel_load_detect_pipe load_detect_temp
;
14885 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
14887 /* We can't just switch on the pipe A, we need to set things up with a
14888 * proper mode and output configuration. As a gross hack, enable pipe A
14889 * by enabling the load detect pipe once. */
14890 for_each_intel_connector(dev
, connector
) {
14891 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
14892 crt
= &connector
->base
;
14900 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
14901 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
14905 intel_check_plane_mapping(struct intel_crtc
*crtc
)
14907 struct drm_device
*dev
= crtc
->base
.dev
;
14908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14911 if (INTEL_INFO(dev
)->num_pipes
== 1)
14914 reg
= DSPCNTR(!crtc
->plane
);
14915 val
= I915_READ(reg
);
14917 if ((val
& DISPLAY_PLANE_ENABLE
) &&
14918 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
14924 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
14926 struct drm_device
*dev
= crtc
->base
.dev
;
14927 struct intel_encoder
*encoder
;
14929 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
14935 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
14937 struct drm_device
*dev
= crtc
->base
.dev
;
14938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14941 /* Clear any frame start delays used for debugging left by the BIOS */
14942 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
14943 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
14945 /* restore vblank interrupts to correct state */
14946 drm_crtc_vblank_reset(&crtc
->base
);
14947 if (crtc
->active
) {
14948 struct intel_plane
*plane
;
14950 drm_crtc_vblank_on(&crtc
->base
);
14952 /* Disable everything but the primary plane */
14953 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
14954 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
14957 plane
->disable_plane(&plane
->base
, &crtc
->base
);
14961 /* We need to sanitize the plane -> pipe mapping first because this will
14962 * disable the crtc (and hence change the state) if it is wrong. Note
14963 * that gen4+ has a fixed plane -> pipe mapping. */
14964 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
14967 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14968 crtc
->base
.base
.id
);
14970 /* Pipe has the wrong plane attached and the plane is active.
14971 * Temporarily change the plane mapping and disable everything
14973 plane
= crtc
->plane
;
14974 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
14975 crtc
->plane
= !plane
;
14976 intel_crtc_disable_noatomic(&crtc
->base
);
14977 crtc
->plane
= plane
;
14980 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
14981 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
14982 /* BIOS forgot to enable pipe A, this mostly happens after
14983 * resume. Force-enable the pipe to fix this, the update_dpms
14984 * call below we restore the pipe to the right state, but leave
14985 * the required bits on. */
14986 intel_enable_pipe_a(dev
);
14989 /* Adjust the state of the output pipe according to whether we
14990 * have active connectors/encoders. */
14991 if (!intel_crtc_has_encoders(crtc
))
14992 intel_crtc_disable_noatomic(&crtc
->base
);
14994 if (crtc
->active
!= crtc
->base
.state
->active
) {
14995 struct intel_encoder
*encoder
;
14997 /* This can happen either due to bugs in the get_hw_state
14998 * functions or because of calls to intel_crtc_disable_noatomic,
14999 * or because the pipe is force-enabled due to the
15001 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15002 crtc
->base
.base
.id
,
15003 crtc
->base
.state
->enable
? "enabled" : "disabled",
15004 crtc
->active
? "enabled" : "disabled");
15006 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, NULL
) < 0);
15007 crtc
->base
.state
->active
= crtc
->active
;
15008 crtc
->base
.enabled
= crtc
->active
;
15010 /* Because we only establish the connector -> encoder ->
15011 * crtc links if something is active, this means the
15012 * crtc is now deactivated. Break the links. connector
15013 * -> encoder links are only establish when things are
15014 * actually up, hence no need to break them. */
15015 WARN_ON(crtc
->active
);
15017 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
15018 encoder
->base
.crtc
= NULL
;
15021 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
15023 * We start out with underrun reporting disabled to avoid races.
15024 * For correct bookkeeping mark this on active crtcs.
15026 * Also on gmch platforms we dont have any hardware bits to
15027 * disable the underrun reporting. Which means we need to start
15028 * out with underrun reporting disabled also on inactive pipes,
15029 * since otherwise we'll complain about the garbage we read when
15030 * e.g. coming up after runtime pm.
15032 * No protection against concurrent access is required - at
15033 * worst a fifo underrun happens which also sets this to false.
15035 crtc
->cpu_fifo_underrun_disabled
= true;
15036 crtc
->pch_fifo_underrun_disabled
= true;
15040 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
15042 struct intel_connector
*connector
;
15043 struct drm_device
*dev
= encoder
->base
.dev
;
15044 bool active
= false;
15046 /* We need to check both for a crtc link (meaning that the
15047 * encoder is active and trying to read from a pipe) and the
15048 * pipe itself being active. */
15049 bool has_active_crtc
= encoder
->base
.crtc
&&
15050 to_intel_crtc(encoder
->base
.crtc
)->active
;
15052 for_each_intel_connector(dev
, connector
) {
15053 if (connector
->base
.encoder
!= &encoder
->base
)
15060 if (active
&& !has_active_crtc
) {
15061 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15062 encoder
->base
.base
.id
,
15063 encoder
->base
.name
);
15065 /* Connector is active, but has no active pipe. This is
15066 * fallout from our resume register restoring. Disable
15067 * the encoder manually again. */
15068 if (encoder
->base
.crtc
) {
15069 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15070 encoder
->base
.base
.id
,
15071 encoder
->base
.name
);
15072 encoder
->disable(encoder
);
15073 if (encoder
->post_disable
)
15074 encoder
->post_disable(encoder
);
15076 encoder
->base
.crtc
= NULL
;
15078 /* Inconsistent output/port/pipe state happens presumably due to
15079 * a bug in one of the get_hw_state functions. Or someplace else
15080 * in our code, like the register restore mess on resume. Clamp
15081 * things to off as a safer default. */
15082 for_each_intel_connector(dev
, connector
) {
15083 if (connector
->encoder
!= encoder
)
15085 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15086 connector
->base
.encoder
= NULL
;
15089 /* Enabled encoders without active connectors will be fixed in
15090 * the crtc fixup. */
15093 void i915_redisable_vga_power_on(struct drm_device
*dev
)
15095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15096 u32 vga_reg
= i915_vgacntrl_reg(dev
);
15098 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
15099 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15100 i915_disable_vga(dev
);
15104 void i915_redisable_vga(struct drm_device
*dev
)
15106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15108 /* This function can be called both from intel_modeset_setup_hw_state or
15109 * at a very early point in our resume sequence, where the power well
15110 * structures are not yet restored. Since this function is at a very
15111 * paranoid "someone might have enabled VGA while we were not looking"
15112 * level, just check if the power well is enabled instead of trying to
15113 * follow the "don't touch the power well if we don't need it" policy
15114 * the rest of the driver uses. */
15115 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
15118 i915_redisable_vga_power_on(dev
);
15121 static bool primary_get_hw_state(struct intel_plane
*plane
)
15123 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
15125 return I915_READ(DSPCNTR(plane
->plane
)) & DISPLAY_PLANE_ENABLE
;
15128 /* FIXME read out full plane state for all planes */
15129 static void readout_plane_state(struct intel_crtc
*crtc
)
15131 struct drm_plane
*primary
= crtc
->base
.primary
;
15132 struct intel_plane_state
*plane_state
=
15133 to_intel_plane_state(primary
->state
);
15135 plane_state
->visible
=
15136 primary_get_hw_state(to_intel_plane(primary
));
15138 if (plane_state
->visible
)
15139 crtc
->base
.state
->plane_mask
|= 1 << drm_plane_index(primary
);
15142 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
15144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15146 struct intel_crtc
*crtc
;
15147 struct intel_encoder
*encoder
;
15148 struct intel_connector
*connector
;
15151 for_each_intel_crtc(dev
, crtc
) {
15152 __drm_atomic_helper_crtc_destroy_state(&crtc
->base
, crtc
->base
.state
);
15153 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
15154 crtc
->config
->base
.crtc
= &crtc
->base
;
15156 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
15159 crtc
->base
.state
->active
= crtc
->active
;
15160 crtc
->base
.enabled
= crtc
->active
;
15162 readout_plane_state(crtc
);
15164 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15165 crtc
->base
.base
.id
,
15166 crtc
->active
? "enabled" : "disabled");
15169 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15170 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15172 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
15173 &pll
->config
.hw_state
);
15175 pll
->config
.crtc_mask
= 0;
15176 for_each_intel_crtc(dev
, crtc
) {
15177 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
15179 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
15183 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15184 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
15186 if (pll
->config
.crtc_mask
)
15187 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
15190 for_each_intel_encoder(dev
, encoder
) {
15193 if (encoder
->get_hw_state(encoder
, &pipe
)) {
15194 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15195 encoder
->base
.crtc
= &crtc
->base
;
15196 encoder
->get_config(encoder
, crtc
->config
);
15198 encoder
->base
.crtc
= NULL
;
15201 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15202 encoder
->base
.base
.id
,
15203 encoder
->base
.name
,
15204 encoder
->base
.crtc
? "enabled" : "disabled",
15208 for_each_intel_connector(dev
, connector
) {
15209 if (connector
->get_hw_state(connector
)) {
15210 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
15211 connector
->base
.encoder
= &connector
->encoder
->base
;
15213 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15214 connector
->base
.encoder
= NULL
;
15216 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15217 connector
->base
.base
.id
,
15218 connector
->base
.name
,
15219 connector
->base
.encoder
? "enabled" : "disabled");
15222 for_each_intel_crtc(dev
, crtc
) {
15223 crtc
->base
.hwmode
= crtc
->config
->base
.adjusted_mode
;
15225 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
15226 if (crtc
->base
.state
->active
) {
15227 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc
->config
);
15228 intel_mode_from_pipe_config(&crtc
->base
.state
->adjusted_mode
, crtc
->config
);
15229 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
15232 * The initial mode needs to be set in order to keep
15233 * the atomic core happy. It wants a valid mode if the
15234 * crtc's enabled, so we do the above call.
15236 * At this point some state updated by the connectors
15237 * in their ->detect() callback has not run yet, so
15238 * no recalculation can be done yet.
15240 * Even if we could do a recalculation and modeset
15241 * right now it would cause a double modeset if
15242 * fbdev or userspace chooses a different initial mode.
15244 * If that happens, someone indicated they wanted a
15245 * mode change, which means it's safe to do a full
15248 crtc
->base
.state
->mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
15250 drm_calc_timestamping_constants(&crtc
->base
, &crtc
->base
.hwmode
);
15251 update_scanline_offset(crtc
);
15256 /* Scan out the current hw modeset state,
15257 * and sanitizes it to the current state
15260 intel_modeset_setup_hw_state(struct drm_device
*dev
)
15262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15264 struct intel_crtc
*crtc
;
15265 struct intel_encoder
*encoder
;
15268 intel_modeset_readout_hw_state(dev
);
15270 /* HW state is read out, now we need to sanitize this mess. */
15271 for_each_intel_encoder(dev
, encoder
) {
15272 intel_sanitize_encoder(encoder
);
15275 for_each_pipe(dev_priv
, pipe
) {
15276 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15277 intel_sanitize_crtc(crtc
);
15278 intel_dump_pipe_config(crtc
, crtc
->config
,
15279 "[setup_hw_state]");
15282 intel_modeset_update_connector_atomic_state(dev
);
15284 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15285 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15287 if (!pll
->on
|| pll
->active
)
15290 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
15292 pll
->disable(dev_priv
, pll
);
15296 if (IS_VALLEYVIEW(dev
))
15297 vlv_wm_get_hw_state(dev
);
15298 else if (IS_GEN9(dev
))
15299 skl_wm_get_hw_state(dev
);
15300 else if (HAS_PCH_SPLIT(dev
))
15301 ilk_wm_get_hw_state(dev
);
15303 for_each_intel_crtc(dev
, crtc
) {
15304 unsigned long put_domains
;
15306 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
);
15307 if (WARN_ON(put_domains
))
15308 modeset_put_power_domains(dev_priv
, put_domains
);
15310 intel_display_set_init_power(dev_priv
, false);
15313 void intel_display_resume(struct drm_device
*dev
)
15315 struct drm_atomic_state
*state
= drm_atomic_state_alloc(dev
);
15316 struct intel_connector
*conn
;
15317 struct intel_plane
*plane
;
15318 struct drm_crtc
*crtc
;
15324 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
15326 /* preserve complete old state, including dpll */
15327 intel_atomic_get_shared_dpll_state(state
);
15329 for_each_crtc(dev
, crtc
) {
15330 struct drm_crtc_state
*crtc_state
=
15331 drm_atomic_get_crtc_state(state
, crtc
);
15333 ret
= PTR_ERR_OR_ZERO(crtc_state
);
15337 /* force a restore */
15338 crtc_state
->mode_changed
= true;
15341 for_each_intel_plane(dev
, plane
) {
15342 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state
, &plane
->base
));
15347 for_each_intel_connector(dev
, conn
) {
15348 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state
, &conn
->base
));
15353 intel_modeset_setup_hw_state(dev
);
15355 i915_redisable_vga(dev
);
15356 ret
= drm_atomic_commit(state
);
15361 DRM_ERROR("Restoring old state failed with %i\n", ret
);
15362 drm_atomic_state_free(state
);
15365 void intel_modeset_gem_init(struct drm_device
*dev
)
15367 struct drm_crtc
*c
;
15368 struct drm_i915_gem_object
*obj
;
15371 mutex_lock(&dev
->struct_mutex
);
15372 intel_init_gt_powersave(dev
);
15373 mutex_unlock(&dev
->struct_mutex
);
15375 intel_modeset_init_hw(dev
);
15377 intel_setup_overlay(dev
);
15380 * Make sure any fbs we allocated at startup are properly
15381 * pinned & fenced. When we do the allocation it's too early
15384 for_each_crtc(dev
, c
) {
15385 obj
= intel_fb_obj(c
->primary
->fb
);
15389 mutex_lock(&dev
->struct_mutex
);
15390 ret
= intel_pin_and_fence_fb_obj(c
->primary
,
15394 mutex_unlock(&dev
->struct_mutex
);
15396 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15397 to_intel_crtc(c
)->pipe
);
15398 drm_framebuffer_unreference(c
->primary
->fb
);
15399 c
->primary
->fb
= NULL
;
15400 c
->primary
->crtc
= c
->primary
->state
->crtc
= NULL
;
15401 update_state_fb(c
->primary
);
15402 c
->state
->plane_mask
&= ~(1 << drm_plane_index(c
->primary
));
15406 intel_backlight_register(dev
);
15409 void intel_connector_unregister(struct intel_connector
*intel_connector
)
15411 struct drm_connector
*connector
= &intel_connector
->base
;
15413 intel_panel_destroy_backlight(connector
);
15414 drm_connector_unregister(connector
);
15417 void intel_modeset_cleanup(struct drm_device
*dev
)
15419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15420 struct drm_connector
*connector
;
15422 intel_disable_gt_powersave(dev
);
15424 intel_backlight_unregister(dev
);
15427 * Interrupts and polling as the first thing to avoid creating havoc.
15428 * Too much stuff here (turning of connectors, ...) would
15429 * experience fancy races otherwise.
15431 intel_irq_uninstall(dev_priv
);
15434 * Due to the hpd irq storm handling the hotplug work can re-arm the
15435 * poll handlers. Hence disable polling after hpd handling is shut down.
15437 drm_kms_helper_poll_fini(dev
);
15439 intel_unregister_dsm_handler();
15441 intel_fbc_disable(dev_priv
);
15443 /* flush any delayed tasks or pending work */
15444 flush_scheduled_work();
15446 /* destroy the backlight and sysfs files before encoders/connectors */
15447 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
15448 struct intel_connector
*intel_connector
;
15450 intel_connector
= to_intel_connector(connector
);
15451 intel_connector
->unregister(intel_connector
);
15454 drm_mode_config_cleanup(dev
);
15456 intel_cleanup_overlay(dev
);
15458 mutex_lock(&dev
->struct_mutex
);
15459 intel_cleanup_gt_powersave(dev
);
15460 mutex_unlock(&dev
->struct_mutex
);
15464 * Return which encoder is currently attached for connector.
15466 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
15468 return &intel_attached_encoder(connector
)->base
;
15471 void intel_connector_attach_encoder(struct intel_connector
*connector
,
15472 struct intel_encoder
*encoder
)
15474 connector
->encoder
= encoder
;
15475 drm_mode_connector_attach_encoder(&connector
->base
,
15480 * set vga decode state - true == enable VGA decode
15482 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
15484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15485 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
15488 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
15489 DRM_ERROR("failed to read control word\n");
15493 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
15497 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
15499 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
15501 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
15502 DRM_ERROR("failed to write control word\n");
15509 struct intel_display_error_state
{
15511 u32 power_well_driver
;
15513 int num_transcoders
;
15515 struct intel_cursor_error_state
{
15520 } cursor
[I915_MAX_PIPES
];
15522 struct intel_pipe_error_state
{
15523 bool power_domain_on
;
15526 } pipe
[I915_MAX_PIPES
];
15528 struct intel_plane_error_state
{
15536 } plane
[I915_MAX_PIPES
];
15538 struct intel_transcoder_error_state
{
15539 bool power_domain_on
;
15540 enum transcoder cpu_transcoder
;
15553 struct intel_display_error_state
*
15554 intel_display_capture_error_state(struct drm_device
*dev
)
15556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15557 struct intel_display_error_state
*error
;
15558 int transcoders
[] = {
15566 if (INTEL_INFO(dev
)->num_pipes
== 0)
15569 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
15573 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15574 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
15576 for_each_pipe(dev_priv
, i
) {
15577 error
->pipe
[i
].power_domain_on
=
15578 __intel_display_power_is_enabled(dev_priv
,
15579 POWER_DOMAIN_PIPE(i
));
15580 if (!error
->pipe
[i
].power_domain_on
)
15583 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
15584 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
15585 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
15587 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
15588 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
15589 if (INTEL_INFO(dev
)->gen
<= 3) {
15590 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
15591 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
15593 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15594 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
15595 if (INTEL_INFO(dev
)->gen
>= 4) {
15596 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
15597 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
15600 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
15602 if (HAS_GMCH_DISPLAY(dev
))
15603 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
15606 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
15607 if (HAS_DDI(dev_priv
->dev
))
15608 error
->num_transcoders
++; /* Account for eDP. */
15610 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15611 enum transcoder cpu_transcoder
= transcoders
[i
];
15613 error
->transcoder
[i
].power_domain_on
=
15614 __intel_display_power_is_enabled(dev_priv
,
15615 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
15616 if (!error
->transcoder
[i
].power_domain_on
)
15619 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
15621 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
15622 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
15623 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
15624 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
15625 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
15626 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
15627 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
15633 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15636 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
15637 struct drm_device
*dev
,
15638 struct intel_display_error_state
*error
)
15640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15646 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
15647 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15648 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
15649 error
->power_well_driver
);
15650 for_each_pipe(dev_priv
, i
) {
15651 err_printf(m
, "Pipe [%d]:\n", i
);
15652 err_printf(m
, " Power: %s\n",
15653 error
->pipe
[i
].power_domain_on
? "on" : "off");
15654 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
15655 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
15657 err_printf(m
, "Plane [%d]:\n", i
);
15658 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
15659 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
15660 if (INTEL_INFO(dev
)->gen
<= 3) {
15661 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
15662 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
15664 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15665 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
15666 if (INTEL_INFO(dev
)->gen
>= 4) {
15667 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
15668 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
15671 err_printf(m
, "Cursor [%d]:\n", i
);
15672 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
15673 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
15674 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
15677 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15678 err_printf(m
, "CPU transcoder: %c\n",
15679 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
15680 err_printf(m
, " Power: %s\n",
15681 error
->transcoder
[i
].power_domain_on
? "on" : "off");
15682 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
15683 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
15684 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
15685 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
15686 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
15687 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
15688 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
15692 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
15694 struct intel_crtc
*crtc
;
15696 for_each_intel_crtc(dev
, crtc
) {
15697 struct intel_unpin_work
*work
;
15699 spin_lock_irq(&dev
->event_lock
);
15701 work
= crtc
->unpin_work
;
15703 if (work
&& work
->event
&&
15704 work
->event
->base
.file_priv
== file
) {
15705 kfree(work
->event
);
15706 work
->event
= NULL
;
15709 spin_unlock_irq(&dev
->event_lock
);