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drm/i915: Store frontbuffer_bits in the plane
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_set_mode(struct drm_atomic_state *state);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void chv_prepare_pll(struct intel_crtc *crtc,
105 const struct intel_crtc_state *pipe_config);
106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
112
113 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
114 {
115 if (!connector->mst_port)
116 return connector->encoder;
117 else
118 return &connector->mst_port->mst_encoders[pipe]->base;
119 }
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 int
137 intel_pch_rawclk(struct drm_device *dev)
138 {
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 WARN_ON(!HAS_PCH_SPLIT(dev));
142
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
144 }
145
146 static inline u32 /* units of 100MHz */
147 intel_fdi_link_freq(struct drm_device *dev)
148 {
149 if (IS_GEN5(dev)) {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
152 } else
153 return 27;
154 }
155
156 static const intel_limit_t intel_limits_i8xx_dac = {
157 .dot = { .min = 25000, .max = 350000 },
158 .vco = { .min = 908000, .max = 1512000 },
159 .n = { .min = 2, .max = 16 },
160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
167 };
168
169 static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
171 .vco = { .min = 908000, .max = 1512000 },
172 .n = { .min = 2, .max = 16 },
173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
180 };
181
182 static const intel_limit_t intel_limits_i8xx_lvds = {
183 .dot = { .min = 25000, .max = 350000 },
184 .vco = { .min = 908000, .max = 1512000 },
185 .n = { .min = 2, .max = 16 },
186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
193 };
194
195 static const intel_limit_t intel_limits_i9xx_sdvo = {
196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
206 };
207
208 static const intel_limit_t intel_limits_i9xx_lvds = {
209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
219 };
220
221
222 static const intel_limit_t intel_limits_g4x_sdvo = {
223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
232 .p2_slow = 10,
233 .p2_fast = 10
234 },
235 };
236
237 static const intel_limit_t intel_limits_g4x_hdmi = {
238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
248 };
249
250 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
261 },
262 };
263
264 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
275 },
276 };
277
278 static const intel_limit_t intel_limits_pineview_sdvo = {
279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
281 /* Pineview's Ncounter is a ring counter */
282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
284 /* Pineview only has one combined m divider, which we treat as m2. */
285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
291 };
292
293 static const intel_limit_t intel_limits_pineview_lvds = {
294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
304 };
305
306 /* Ironlake / Sandybridge
307 *
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
310 */
311 static const intel_limit_t intel_limits_ironlake_dac = {
312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
322 };
323
324 static const intel_limit_t intel_limits_ironlake_single_lvds = {
325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
335 };
336
337 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
348 };
349
350 /* LVDS 100mhz refclk limits. */
351 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
359 .p1 = { .min = 2, .max = 8 },
360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
362 };
363
364 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
372 .p1 = { .min = 2, .max = 6 },
373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
375 };
376
377 static const intel_limit_t intel_limits_vlv = {
378 /*
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
383 */
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
385 .vco = { .min = 4000000, .max = 6000000 },
386 .n = { .min = 1, .max = 7 },
387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
391 };
392
393 static const intel_limit_t intel_limits_chv = {
394 /*
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
399 */
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
401 .vco = { .min = 4800000, .max = 6480000 },
402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
407 };
408
409 static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
412 .vco = { .min = 4800000, .max = 6480000 },
413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
419 };
420
421 static void vlv_clock(int refclk, intel_clock_t *clock)
422 {
423 clock->m = clock->m1 * clock->m2;
424 clock->p = clock->p1 * clock->p2;
425 if (WARN_ON(clock->n == 0 || clock->p == 0))
426 return;
427 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
428 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
429 }
430
431 static bool
432 needs_modeset(struct drm_crtc_state *state)
433 {
434 return state->mode_changed || state->active_changed;
435 }
436
437 /**
438 * Returns whether any output on the specified pipe is of the specified type
439 */
440 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
441 {
442 struct drm_device *dev = crtc->base.dev;
443 struct intel_encoder *encoder;
444
445 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
446 if (encoder->type == type)
447 return true;
448
449 return false;
450 }
451
452 /**
453 * Returns whether any output on the specified pipe will have the specified
454 * type after a staged modeset is complete, i.e., the same as
455 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
456 * encoder->crtc.
457 */
458 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
459 int type)
460 {
461 struct drm_atomic_state *state = crtc_state->base.state;
462 struct drm_connector *connector;
463 struct drm_connector_state *connector_state;
464 struct intel_encoder *encoder;
465 int i, num_connectors = 0;
466
467 for_each_connector_in_state(state, connector, connector_state, i) {
468 if (connector_state->crtc != crtc_state->base.crtc)
469 continue;
470
471 num_connectors++;
472
473 encoder = to_intel_encoder(connector_state->best_encoder);
474 if (encoder->type == type)
475 return true;
476 }
477
478 WARN_ON(num_connectors == 0);
479
480 return false;
481 }
482
483 static const intel_limit_t *
484 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
485 {
486 struct drm_device *dev = crtc_state->base.crtc->dev;
487 const intel_limit_t *limit;
488
489 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
490 if (intel_is_dual_link_lvds(dev)) {
491 if (refclk == 100000)
492 limit = &intel_limits_ironlake_dual_lvds_100m;
493 else
494 limit = &intel_limits_ironlake_dual_lvds;
495 } else {
496 if (refclk == 100000)
497 limit = &intel_limits_ironlake_single_lvds_100m;
498 else
499 limit = &intel_limits_ironlake_single_lvds;
500 }
501 } else
502 limit = &intel_limits_ironlake_dac;
503
504 return limit;
505 }
506
507 static const intel_limit_t *
508 intel_g4x_limit(struct intel_crtc_state *crtc_state)
509 {
510 struct drm_device *dev = crtc_state->base.crtc->dev;
511 const intel_limit_t *limit;
512
513 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
514 if (intel_is_dual_link_lvds(dev))
515 limit = &intel_limits_g4x_dual_channel_lvds;
516 else
517 limit = &intel_limits_g4x_single_channel_lvds;
518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
519 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
520 limit = &intel_limits_g4x_hdmi;
521 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
522 limit = &intel_limits_g4x_sdvo;
523 } else /* The option is for other outputs */
524 limit = &intel_limits_i9xx_sdvo;
525
526 return limit;
527 }
528
529 static const intel_limit_t *
530 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
531 {
532 struct drm_device *dev = crtc_state->base.crtc->dev;
533 const intel_limit_t *limit;
534
535 if (IS_BROXTON(dev))
536 limit = &intel_limits_bxt;
537 else if (HAS_PCH_SPLIT(dev))
538 limit = intel_ironlake_limit(crtc_state, refclk);
539 else if (IS_G4X(dev)) {
540 limit = intel_g4x_limit(crtc_state);
541 } else if (IS_PINEVIEW(dev)) {
542 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
543 limit = &intel_limits_pineview_lvds;
544 else
545 limit = &intel_limits_pineview_sdvo;
546 } else if (IS_CHERRYVIEW(dev)) {
547 limit = &intel_limits_chv;
548 } else if (IS_VALLEYVIEW(dev)) {
549 limit = &intel_limits_vlv;
550 } else if (!IS_GEN2(dev)) {
551 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
552 limit = &intel_limits_i9xx_lvds;
553 else
554 limit = &intel_limits_i9xx_sdvo;
555 } else {
556 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
557 limit = &intel_limits_i8xx_lvds;
558 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
559 limit = &intel_limits_i8xx_dvo;
560 else
561 limit = &intel_limits_i8xx_dac;
562 }
563 return limit;
564 }
565
566 /* m1 is reserved as 0 in Pineview, n is a ring counter */
567 static void pineview_clock(int refclk, intel_clock_t *clock)
568 {
569 clock->m = clock->m2 + 2;
570 clock->p = clock->p1 * clock->p2;
571 if (WARN_ON(clock->n == 0 || clock->p == 0))
572 return;
573 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
574 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
575 }
576
577 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
578 {
579 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
580 }
581
582 static void i9xx_clock(int refclk, intel_clock_t *clock)
583 {
584 clock->m = i9xx_dpll_compute_m(clock);
585 clock->p = clock->p1 * clock->p2;
586 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
587 return;
588 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
589 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
590 }
591
592 static void chv_clock(int refclk, intel_clock_t *clock)
593 {
594 clock->m = clock->m1 * clock->m2;
595 clock->p = clock->p1 * clock->p2;
596 if (WARN_ON(clock->n == 0 || clock->p == 0))
597 return;
598 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
599 clock->n << 22);
600 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
601 }
602
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
604 /**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
609 static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
612 {
613 if (clock->n < limit->n.min || limit->n.max < clock->n)
614 INTELPllInvalid("n out of range\n");
615 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
616 INTELPllInvalid("p1 out of range\n");
617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
620 INTELPllInvalid("m1 out of range\n");
621
622 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
623 if (clock->m1 <= clock->m2)
624 INTELPllInvalid("m1 <= m2\n");
625
626 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
627 if (clock->p < limit->p.min || limit->p.max < clock->p)
628 INTELPllInvalid("p out of range\n");
629 if (clock->m < limit->m.min || limit->m.max < clock->m)
630 INTELPllInvalid("m out of range\n");
631 }
632
633 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
634 INTELPllInvalid("vco out of range\n");
635 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
636 * connector, etc., rather than just a single range.
637 */
638 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
639 INTELPllInvalid("dot out of range\n");
640
641 return true;
642 }
643
644 static int
645 i9xx_select_p2_div(const intel_limit_t *limit,
646 const struct intel_crtc_state *crtc_state,
647 int target)
648 {
649 struct drm_device *dev = crtc_state->base.crtc->dev;
650
651 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
652 /*
653 * For LVDS just rely on its current settings for dual-channel.
654 * We haven't figured out how to reliably set up different
655 * single/dual channel state, if we even can.
656 */
657 if (intel_is_dual_link_lvds(dev))
658 return limit->p2.p2_fast;
659 else
660 return limit->p2.p2_slow;
661 } else {
662 if (target < limit->p2.dot_limit)
663 return limit->p2.p2_slow;
664 else
665 return limit->p2.p2_fast;
666 }
667 }
668
669 static bool
670 i9xx_find_best_dpll(const intel_limit_t *limit,
671 struct intel_crtc_state *crtc_state,
672 int target, int refclk, intel_clock_t *match_clock,
673 intel_clock_t *best_clock)
674 {
675 struct drm_device *dev = crtc_state->base.crtc->dev;
676 intel_clock_t clock;
677 int err = target;
678
679 memset(best_clock, 0, sizeof(*best_clock));
680
681 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
682
683 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
684 clock.m1++) {
685 for (clock.m2 = limit->m2.min;
686 clock.m2 <= limit->m2.max; clock.m2++) {
687 if (clock.m2 >= clock.m1)
688 break;
689 for (clock.n = limit->n.min;
690 clock.n <= limit->n.max; clock.n++) {
691 for (clock.p1 = limit->p1.min;
692 clock.p1 <= limit->p1.max; clock.p1++) {
693 int this_err;
694
695 i9xx_clock(refclk, &clock);
696 if (!intel_PLL_is_valid(dev, limit,
697 &clock))
698 continue;
699 if (match_clock &&
700 clock.p != match_clock->p)
701 continue;
702
703 this_err = abs(clock.dot - target);
704 if (this_err < err) {
705 *best_clock = clock;
706 err = this_err;
707 }
708 }
709 }
710 }
711 }
712
713 return (err != target);
714 }
715
716 static bool
717 pnv_find_best_dpll(const intel_limit_t *limit,
718 struct intel_crtc_state *crtc_state,
719 int target, int refclk, intel_clock_t *match_clock,
720 intel_clock_t *best_clock)
721 {
722 struct drm_device *dev = crtc_state->base.crtc->dev;
723 intel_clock_t clock;
724 int err = target;
725
726 memset(best_clock, 0, sizeof(*best_clock));
727
728 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
729
730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
731 clock.m1++) {
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
738 int this_err;
739
740 pineview_clock(refclk, &clock);
741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759 }
760
761 static bool
762 g4x_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
766 {
767 struct drm_device *dev = crtc_state->base.crtc->dev;
768 intel_clock_t clock;
769 int max_n;
770 bool found = false;
771 /* approximately equals target * 0.00585 */
772 int err_most = (target >> 8) + (target >> 9);
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
778 max_n = limit->n.max;
779 /* based on hardware requirement, prefer smaller n to precision */
780 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
781 /* based on hardware requirement, prefere larger m1,m2 */
782 for (clock.m1 = limit->m1.max;
783 clock.m1 >= limit->m1.min; clock.m1--) {
784 for (clock.m2 = limit->m2.max;
785 clock.m2 >= limit->m2.min; clock.m2--) {
786 for (clock.p1 = limit->p1.max;
787 clock.p1 >= limit->p1.min; clock.p1--) {
788 int this_err;
789
790 i9xx_clock(refclk, &clock);
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 this_err = abs(clock.dot - target);
796 if (this_err < err_most) {
797 *best_clock = clock;
798 err_most = this_err;
799 max_n = clock.n;
800 found = true;
801 }
802 }
803 }
804 }
805 }
806 return found;
807 }
808
809 /*
810 * Check if the calculated PLL configuration is more optimal compared to the
811 * best configuration and error found so far. Return the calculated error.
812 */
813 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
814 const intel_clock_t *calculated_clock,
815 const intel_clock_t *best_clock,
816 unsigned int best_error_ppm,
817 unsigned int *error_ppm)
818 {
819 /*
820 * For CHV ignore the error and consider only the P value.
821 * Prefer a bigger P value based on HW requirements.
822 */
823 if (IS_CHERRYVIEW(dev)) {
824 *error_ppm = 0;
825
826 return calculated_clock->p > best_clock->p;
827 }
828
829 if (WARN_ON_ONCE(!target_freq))
830 return false;
831
832 *error_ppm = div_u64(1000000ULL *
833 abs(target_freq - calculated_clock->dot),
834 target_freq);
835 /*
836 * Prefer a better P value over a better (smaller) error if the error
837 * is small. Ensure this preference for future configurations too by
838 * setting the error to 0.
839 */
840 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
841 *error_ppm = 0;
842
843 return true;
844 }
845
846 return *error_ppm + 10 < best_error_ppm;
847 }
848
849 static bool
850 vlv_find_best_dpll(const intel_limit_t *limit,
851 struct intel_crtc_state *crtc_state,
852 int target, int refclk, intel_clock_t *match_clock,
853 intel_clock_t *best_clock)
854 {
855 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
856 struct drm_device *dev = crtc->base.dev;
857 intel_clock_t clock;
858 unsigned int bestppm = 1000000;
859 /* min update 19.2 MHz */
860 int max_n = min(limit->n.max, refclk / 19200);
861 bool found = false;
862
863 target *= 5; /* fast clock */
864
865 memset(best_clock, 0, sizeof(*best_clock));
866
867 /* based on hardware requirement, prefer smaller n to precision */
868 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
869 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
870 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
871 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
872 clock.p = clock.p1 * clock.p2;
873 /* based on hardware requirement, prefer bigger m1,m2 values */
874 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
875 unsigned int ppm;
876
877 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
878 refclk * clock.m1);
879
880 vlv_clock(refclk, &clock);
881
882 if (!intel_PLL_is_valid(dev, limit,
883 &clock))
884 continue;
885
886 if (!vlv_PLL_is_optimal(dev, target,
887 &clock,
888 best_clock,
889 bestppm, &ppm))
890 continue;
891
892 *best_clock = clock;
893 bestppm = ppm;
894 found = true;
895 }
896 }
897 }
898 }
899
900 return found;
901 }
902
903 static bool
904 chv_find_best_dpll(const intel_limit_t *limit,
905 struct intel_crtc_state *crtc_state,
906 int target, int refclk, intel_clock_t *match_clock,
907 intel_clock_t *best_clock)
908 {
909 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
910 struct drm_device *dev = crtc->base.dev;
911 unsigned int best_error_ppm;
912 intel_clock_t clock;
913 uint64_t m2;
914 int found = false;
915
916 memset(best_clock, 0, sizeof(*best_clock));
917 best_error_ppm = 1000000;
918
919 /*
920 * Based on hardware doc, the n always set to 1, and m1 always
921 * set to 2. If requires to support 200Mhz refclk, we need to
922 * revisit this because n may not 1 anymore.
923 */
924 clock.n = 1, clock.m1 = 2;
925 target *= 5; /* fast clock */
926
927 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
928 for (clock.p2 = limit->p2.p2_fast;
929 clock.p2 >= limit->p2.p2_slow;
930 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
931 unsigned int error_ppm;
932
933 clock.p = clock.p1 * clock.p2;
934
935 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
936 clock.n) << 22, refclk * clock.m1);
937
938 if (m2 > INT_MAX/clock.m1)
939 continue;
940
941 clock.m2 = m2;
942
943 chv_clock(refclk, &clock);
944
945 if (!intel_PLL_is_valid(dev, limit, &clock))
946 continue;
947
948 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
949 best_error_ppm, &error_ppm))
950 continue;
951
952 *best_clock = clock;
953 best_error_ppm = error_ppm;
954 found = true;
955 }
956 }
957
958 return found;
959 }
960
961 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
962 intel_clock_t *best_clock)
963 {
964 int refclk = i9xx_get_refclk(crtc_state, 0);
965
966 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
967 target_clock, refclk, NULL, best_clock);
968 }
969
970 bool intel_crtc_active(struct drm_crtc *crtc)
971 {
972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
973
974 /* Be paranoid as we can arrive here with only partial
975 * state retrieved from the hardware during setup.
976 *
977 * We can ditch the adjusted_mode.crtc_clock check as soon
978 * as Haswell has gained clock readout/fastboot support.
979 *
980 * We can ditch the crtc->primary->fb check as soon as we can
981 * properly reconstruct framebuffers.
982 *
983 * FIXME: The intel_crtc->active here should be switched to
984 * crtc->state->active once we have proper CRTC states wired up
985 * for atomic.
986 */
987 return intel_crtc->active && crtc->primary->state->fb &&
988 intel_crtc->config->base.adjusted_mode.crtc_clock;
989 }
990
991 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
992 enum pipe pipe)
993 {
994 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
996
997 return intel_crtc->config->cpu_transcoder;
998 }
999
1000 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1001 {
1002 struct drm_i915_private *dev_priv = dev->dev_private;
1003 u32 reg = PIPEDSL(pipe);
1004 u32 line1, line2;
1005 u32 line_mask;
1006
1007 if (IS_GEN2(dev))
1008 line_mask = DSL_LINEMASK_GEN2;
1009 else
1010 line_mask = DSL_LINEMASK_GEN3;
1011
1012 line1 = I915_READ(reg) & line_mask;
1013 mdelay(5);
1014 line2 = I915_READ(reg) & line_mask;
1015
1016 return line1 == line2;
1017 }
1018
1019 /*
1020 * intel_wait_for_pipe_off - wait for pipe to turn off
1021 * @crtc: crtc whose pipe to wait for
1022 *
1023 * After disabling a pipe, we can't wait for vblank in the usual way,
1024 * spinning on the vblank interrupt status bit, since we won't actually
1025 * see an interrupt when the pipe is disabled.
1026 *
1027 * On Gen4 and above:
1028 * wait for the pipe register state bit to turn off
1029 *
1030 * Otherwise:
1031 * wait for the display line value to settle (it usually
1032 * ends up stopping at the start of the next frame).
1033 *
1034 */
1035 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1036 {
1037 struct drm_device *dev = crtc->base.dev;
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1040 enum pipe pipe = crtc->pipe;
1041
1042 if (INTEL_INFO(dev)->gen >= 4) {
1043 int reg = PIPECONF(cpu_transcoder);
1044
1045 /* Wait for the Pipe State to go off */
1046 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1047 100))
1048 WARN(1, "pipe_off wait timed out\n");
1049 } else {
1050 /* Wait for the display line to settle */
1051 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1052 WARN(1, "pipe_off wait timed out\n");
1053 }
1054 }
1055
1056 /*
1057 * ibx_digital_port_connected - is the specified port connected?
1058 * @dev_priv: i915 private structure
1059 * @port: the port to test
1060 *
1061 * Returns true if @port is connected, false otherwise.
1062 */
1063 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1064 struct intel_digital_port *port)
1065 {
1066 u32 bit;
1067
1068 if (HAS_PCH_IBX(dev_priv->dev)) {
1069 switch (port->port) {
1070 case PORT_B:
1071 bit = SDE_PORTB_HOTPLUG;
1072 break;
1073 case PORT_C:
1074 bit = SDE_PORTC_HOTPLUG;
1075 break;
1076 case PORT_D:
1077 bit = SDE_PORTD_HOTPLUG;
1078 break;
1079 default:
1080 return true;
1081 }
1082 } else {
1083 switch (port->port) {
1084 case PORT_B:
1085 bit = SDE_PORTB_HOTPLUG_CPT;
1086 break;
1087 case PORT_C:
1088 bit = SDE_PORTC_HOTPLUG_CPT;
1089 break;
1090 case PORT_D:
1091 bit = SDE_PORTD_HOTPLUG_CPT;
1092 break;
1093 default:
1094 return true;
1095 }
1096 }
1097
1098 return I915_READ(SDEISR) & bit;
1099 }
1100
1101 static const char *state_string(bool enabled)
1102 {
1103 return enabled ? "on" : "off";
1104 }
1105
1106 /* Only for pre-ILK configs */
1107 void assert_pll(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1109 {
1110 int reg;
1111 u32 val;
1112 bool cur_state;
1113
1114 reg = DPLL(pipe);
1115 val = I915_READ(reg);
1116 cur_state = !!(val & DPLL_VCO_ENABLE);
1117 I915_STATE_WARN(cur_state != state,
1118 "PLL state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120 }
1121
1122 /* XXX: the dsi pll is shared between MIPI DSI ports */
1123 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1124 {
1125 u32 val;
1126 bool cur_state;
1127
1128 mutex_lock(&dev_priv->sb_lock);
1129 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1130 mutex_unlock(&dev_priv->sb_lock);
1131
1132 cur_state = val & DSI_PLL_VCO_EN;
1133 I915_STATE_WARN(cur_state != state,
1134 "DSI PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1136 }
1137 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1138 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1139
1140 struct intel_shared_dpll *
1141 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1142 {
1143 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1144
1145 if (crtc->config->shared_dpll < 0)
1146 return NULL;
1147
1148 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1149 }
1150
1151 /* For ILK+ */
1152 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1153 struct intel_shared_dpll *pll,
1154 bool state)
1155 {
1156 bool cur_state;
1157 struct intel_dpll_hw_state hw_state;
1158
1159 if (WARN (!pll,
1160 "asserting DPLL %s with no DPLL\n", state_string(state)))
1161 return;
1162
1163 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1164 I915_STATE_WARN(cur_state != state,
1165 "%s assertion failure (expected %s, current %s)\n",
1166 pll->name, state_string(state), state_string(cur_state));
1167 }
1168
1169 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1170 enum pipe pipe, bool state)
1171 {
1172 int reg;
1173 u32 val;
1174 bool cur_state;
1175 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1176 pipe);
1177
1178 if (HAS_DDI(dev_priv->dev)) {
1179 /* DDI does not have a specific FDI_TX register */
1180 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1181 val = I915_READ(reg);
1182 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1183 } else {
1184 reg = FDI_TX_CTL(pipe);
1185 val = I915_READ(reg);
1186 cur_state = !!(val & FDI_TX_ENABLE);
1187 }
1188 I915_STATE_WARN(cur_state != state,
1189 "FDI TX state assertion failure (expected %s, current %s)\n",
1190 state_string(state), state_string(cur_state));
1191 }
1192 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1193 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1194
1195 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1197 {
1198 int reg;
1199 u32 val;
1200 bool cur_state;
1201
1202 reg = FDI_RX_CTL(pipe);
1203 val = I915_READ(reg);
1204 cur_state = !!(val & FDI_RX_ENABLE);
1205 I915_STATE_WARN(cur_state != state,
1206 "FDI RX state assertion failure (expected %s, current %s)\n",
1207 state_string(state), state_string(cur_state));
1208 }
1209 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1210 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1211
1212 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1213 enum pipe pipe)
1214 {
1215 int reg;
1216 u32 val;
1217
1218 /* ILK FDI PLL is always enabled */
1219 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1220 return;
1221
1222 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1223 if (HAS_DDI(dev_priv->dev))
1224 return;
1225
1226 reg = FDI_TX_CTL(pipe);
1227 val = I915_READ(reg);
1228 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1229 }
1230
1231 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1232 enum pipe pipe, bool state)
1233 {
1234 int reg;
1235 u32 val;
1236 bool cur_state;
1237
1238 reg = FDI_RX_CTL(pipe);
1239 val = I915_READ(reg);
1240 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1241 I915_STATE_WARN(cur_state != state,
1242 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1243 state_string(state), state_string(cur_state));
1244 }
1245
1246 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248 {
1249 struct drm_device *dev = dev_priv->dev;
1250 int pp_reg;
1251 u32 val;
1252 enum pipe panel_pipe = PIPE_A;
1253 bool locked = true;
1254
1255 if (WARN_ON(HAS_DDI(dev)))
1256 return;
1257
1258 if (HAS_PCH_SPLIT(dev)) {
1259 u32 port_sel;
1260
1261 pp_reg = PCH_PP_CONTROL;
1262 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1263
1264 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1265 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1266 panel_pipe = PIPE_B;
1267 /* XXX: else fix for eDP */
1268 } else if (IS_VALLEYVIEW(dev)) {
1269 /* presumably write lock depends on pipe, not port select */
1270 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1271 panel_pipe = pipe;
1272 } else {
1273 pp_reg = PP_CONTROL;
1274 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1275 panel_pipe = PIPE_B;
1276 }
1277
1278 val = I915_READ(pp_reg);
1279 if (!(val & PANEL_POWER_ON) ||
1280 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1281 locked = false;
1282
1283 I915_STATE_WARN(panel_pipe == pipe && locked,
1284 "panel assertion failure, pipe %c regs locked\n",
1285 pipe_name(pipe));
1286 }
1287
1288 static void assert_cursor(struct drm_i915_private *dev_priv,
1289 enum pipe pipe, bool state)
1290 {
1291 struct drm_device *dev = dev_priv->dev;
1292 bool cur_state;
1293
1294 if (IS_845G(dev) || IS_I865G(dev))
1295 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1296 else
1297 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1298
1299 I915_STATE_WARN(cur_state != state,
1300 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1301 pipe_name(pipe), state_string(state), state_string(cur_state));
1302 }
1303 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1304 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1305
1306 void assert_pipe(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, bool state)
1308 {
1309 int reg;
1310 u32 val;
1311 bool cur_state;
1312 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1313 pipe);
1314
1315 /* if we need the pipe quirk it must be always on */
1316 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1317 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1318 state = true;
1319
1320 if (!intel_display_power_is_enabled(dev_priv,
1321 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1322 cur_state = false;
1323 } else {
1324 reg = PIPECONF(cpu_transcoder);
1325 val = I915_READ(reg);
1326 cur_state = !!(val & PIPECONF_ENABLE);
1327 }
1328
1329 I915_STATE_WARN(cur_state != state,
1330 "pipe %c assertion failure (expected %s, current %s)\n",
1331 pipe_name(pipe), state_string(state), state_string(cur_state));
1332 }
1333
1334 static void assert_plane(struct drm_i915_private *dev_priv,
1335 enum plane plane, bool state)
1336 {
1337 int reg;
1338 u32 val;
1339 bool cur_state;
1340
1341 reg = DSPCNTR(plane);
1342 val = I915_READ(reg);
1343 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1344 I915_STATE_WARN(cur_state != state,
1345 "plane %c assertion failure (expected %s, current %s)\n",
1346 plane_name(plane), state_string(state), state_string(cur_state));
1347 }
1348
1349 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1350 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1351
1352 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1353 enum pipe pipe)
1354 {
1355 struct drm_device *dev = dev_priv->dev;
1356 int reg, i;
1357 u32 val;
1358 int cur_pipe;
1359
1360 /* Primary planes are fixed to pipes on gen4+ */
1361 if (INTEL_INFO(dev)->gen >= 4) {
1362 reg = DSPCNTR(pipe);
1363 val = I915_READ(reg);
1364 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1365 "plane %c assertion failure, should be disabled but not\n",
1366 plane_name(pipe));
1367 return;
1368 }
1369
1370 /* Need to check both planes against the pipe */
1371 for_each_pipe(dev_priv, i) {
1372 reg = DSPCNTR(i);
1373 val = I915_READ(reg);
1374 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1375 DISPPLANE_SEL_PIPE_SHIFT;
1376 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1377 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1378 plane_name(i), pipe_name(pipe));
1379 }
1380 }
1381
1382 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1383 enum pipe pipe)
1384 {
1385 struct drm_device *dev = dev_priv->dev;
1386 int reg, sprite;
1387 u32 val;
1388
1389 if (INTEL_INFO(dev)->gen >= 9) {
1390 for_each_sprite(dev_priv, pipe, sprite) {
1391 val = I915_READ(PLANE_CTL(pipe, sprite));
1392 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1393 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1394 sprite, pipe_name(pipe));
1395 }
1396 } else if (IS_VALLEYVIEW(dev)) {
1397 for_each_sprite(dev_priv, pipe, sprite) {
1398 reg = SPCNTR(pipe, sprite);
1399 val = I915_READ(reg);
1400 I915_STATE_WARN(val & SP_ENABLE,
1401 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1402 sprite_name(pipe, sprite), pipe_name(pipe));
1403 }
1404 } else if (INTEL_INFO(dev)->gen >= 7) {
1405 reg = SPRCTL(pipe);
1406 val = I915_READ(reg);
1407 I915_STATE_WARN(val & SPRITE_ENABLE,
1408 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1409 plane_name(pipe), pipe_name(pipe));
1410 } else if (INTEL_INFO(dev)->gen >= 5) {
1411 reg = DVSCNTR(pipe);
1412 val = I915_READ(reg);
1413 I915_STATE_WARN(val & DVS_ENABLE,
1414 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1415 plane_name(pipe), pipe_name(pipe));
1416 }
1417 }
1418
1419 static void assert_vblank_disabled(struct drm_crtc *crtc)
1420 {
1421 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1422 drm_crtc_vblank_put(crtc);
1423 }
1424
1425 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1426 {
1427 u32 val;
1428 bool enabled;
1429
1430 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1431
1432 val = I915_READ(PCH_DREF_CONTROL);
1433 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1434 DREF_SUPERSPREAD_SOURCE_MASK));
1435 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1436 }
1437
1438 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1439 enum pipe pipe)
1440 {
1441 int reg;
1442 u32 val;
1443 bool enabled;
1444
1445 reg = PCH_TRANSCONF(pipe);
1446 val = I915_READ(reg);
1447 enabled = !!(val & TRANS_ENABLE);
1448 I915_STATE_WARN(enabled,
1449 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1450 pipe_name(pipe));
1451 }
1452
1453 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe, u32 port_sel, u32 val)
1455 {
1456 if ((val & DP_PORT_EN) == 0)
1457 return false;
1458
1459 if (HAS_PCH_CPT(dev_priv->dev)) {
1460 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1461 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1462 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1463 return false;
1464 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1465 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1466 return false;
1467 } else {
1468 if ((val & DP_PIPE_MASK) != (pipe << 30))
1469 return false;
1470 }
1471 return true;
1472 }
1473
1474 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1475 enum pipe pipe, u32 val)
1476 {
1477 if ((val & SDVO_ENABLE) == 0)
1478 return false;
1479
1480 if (HAS_PCH_CPT(dev_priv->dev)) {
1481 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1482 return false;
1483 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1484 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1485 return false;
1486 } else {
1487 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1488 return false;
1489 }
1490 return true;
1491 }
1492
1493 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1494 enum pipe pipe, u32 val)
1495 {
1496 if ((val & LVDS_PORT_EN) == 0)
1497 return false;
1498
1499 if (HAS_PCH_CPT(dev_priv->dev)) {
1500 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1501 return false;
1502 } else {
1503 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1504 return false;
1505 }
1506 return true;
1507 }
1508
1509 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1511 {
1512 if ((val & ADPA_DAC_ENABLE) == 0)
1513 return false;
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1519 return false;
1520 }
1521 return true;
1522 }
1523
1524 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, int reg, u32 port_sel)
1526 {
1527 u32 val = I915_READ(reg);
1528 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1529 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1530 reg, pipe_name(pipe));
1531
1532 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1533 && (val & DP_PIPEB_SELECT),
1534 "IBX PCH dp port still using transcoder B\n");
1535 }
1536
1537 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1538 enum pipe pipe, int reg)
1539 {
1540 u32 val = I915_READ(reg);
1541 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1542 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1543 reg, pipe_name(pipe));
1544
1545 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1546 && (val & SDVO_PIPE_B_SELECT),
1547 "IBX PCH hdmi port still using transcoder B\n");
1548 }
1549
1550 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1551 enum pipe pipe)
1552 {
1553 int reg;
1554 u32 val;
1555
1556 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1557 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1558 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1559
1560 reg = PCH_ADPA;
1561 val = I915_READ(reg);
1562 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1563 "PCH VGA enabled on transcoder %c, should be disabled\n",
1564 pipe_name(pipe));
1565
1566 reg = PCH_LVDS;
1567 val = I915_READ(reg);
1568 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1569 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1570 pipe_name(pipe));
1571
1572 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1573 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1574 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1575 }
1576
1577 static void intel_init_dpio(struct drm_device *dev)
1578 {
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580
1581 if (!IS_VALLEYVIEW(dev))
1582 return;
1583
1584 /*
1585 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1586 * CHV x1 PHY (DP/HDMI D)
1587 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1588 */
1589 if (IS_CHERRYVIEW(dev)) {
1590 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1591 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1592 } else {
1593 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1594 }
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598 const struct intel_crtc_state *pipe_config)
1599 {
1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605 assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
1611 if (IS_MOBILE(dev_priv->dev))
1612 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622 POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624 /* We do this three times for luck */
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
1628 I915_WRITE(reg, dpll);
1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
1631 I915_WRITE(reg, dpll);
1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637 const struct intel_crtc_state *pipe_config)
1638 {
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649 mutex_lock(&dev_priv->sb_lock);
1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656 mutex_unlock(&dev_priv->sb_lock);
1657
1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666 /* Check PLL is locked */
1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670 /* not sure when this should be written */
1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672 POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
1681 count += crtc->base.state->active &&
1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684 return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694 assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696 /* No really, not for ILK+ */
1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699 /* PLL is protected by panel, make sure we can write it */
1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
1722 crtc->config->dpll_hw_state.dpll_md);
1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
1731
1732 /* We do this three times for luck */
1733 I915_WRITE(reg, dpll);
1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
1736 I915_WRITE(reg, dpll);
1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
1739 I915_WRITE(reg, dpll);
1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742 }
1743
1744 /**
1745 * i9xx_disable_pll - disable a PLL
1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1753 static void i9xx_disable_pll(struct intel_crtc *crtc)
1754 {
1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1762 !intel_num_dvo_pipes(dev)) {
1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
1777 I915_WRITE(DPLL(pipe), 0);
1778 POSTING_READ(DPLL(pipe));
1779 }
1780
1781 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782 {
1783 u32 val = 0;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
1792 if (pipe == PIPE_B)
1793 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1794 I915_WRITE(DPLL(pipe), val);
1795 POSTING_READ(DPLL(pipe));
1796
1797 }
1798
1799 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1800 {
1801 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1802 u32 val;
1803
1804 /* Make sure the pipe isn't still relying on us */
1805 assert_pipe_disabled(dev_priv, pipe);
1806
1807 /* Set PLL en = 0 */
1808 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1809 if (pipe != PIPE_A)
1810 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1811 I915_WRITE(DPLL(pipe), val);
1812 POSTING_READ(DPLL(pipe));
1813
1814 mutex_lock(&dev_priv->sb_lock);
1815
1816 /* Disable 10bit clock to display controller */
1817 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1818 val &= ~DPIO_DCLKP_EN;
1819 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1820
1821 /* disable left/right clock distribution */
1822 if (pipe != PIPE_B) {
1823 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1824 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1825 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1826 } else {
1827 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1828 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1829 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1830 }
1831
1832 mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836 struct intel_digital_port *dport,
1837 unsigned int expected_mask)
1838 {
1839 u32 port_mask;
1840 int dpll_reg;
1841
1842 switch (dport->port) {
1843 case PORT_B:
1844 port_mask = DPLL_PORTB_READY_MASK;
1845 dpll_reg = DPLL(0);
1846 break;
1847 case PORT_C:
1848 port_mask = DPLL_PORTC_READY_MASK;
1849 dpll_reg = DPLL(0);
1850 expected_mask <<= 4;
1851 break;
1852 case PORT_D:
1853 port_mask = DPLL_PORTD_READY_MASK;
1854 dpll_reg = DPIO_PHY_STATUS;
1855 break;
1856 default:
1857 BUG();
1858 }
1859
1860 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867 struct drm_device *dev = crtc->base.dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871 if (WARN_ON(pll == NULL))
1872 return;
1873
1874 WARN_ON(!pll->config.crtc_mask);
1875 if (pll->active == 0) {
1876 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877 WARN_ON(pll->on);
1878 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880 pll->mode_set(dev_priv, pll);
1881 }
1882 }
1883
1884 /**
1885 * intel_enable_shared_dpll - enable PCH PLL
1886 * @dev_priv: i915 private structure
1887 * @pipe: pipe PLL to enable
1888 *
1889 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890 * drives the transcoder clock.
1891 */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894 struct drm_device *dev = crtc->base.dev;
1895 struct drm_i915_private *dev_priv = dev->dev_private;
1896 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898 if (WARN_ON(pll == NULL))
1899 return;
1900
1901 if (WARN_ON(pll->config.crtc_mask == 0))
1902 return;
1903
1904 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905 pll->name, pll->active, pll->on,
1906 crtc->base.base.id);
1907
1908 if (pll->active++) {
1909 WARN_ON(!pll->on);
1910 assert_shared_dpll_enabled(dev_priv, pll);
1911 return;
1912 }
1913 WARN_ON(pll->on);
1914
1915 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918 pll->enable(dev_priv, pll);
1919 pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924 struct drm_device *dev = crtc->base.dev;
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928 /* PCH only available on ILK+ */
1929 BUG_ON(INTEL_INFO(dev)->gen < 5);
1930 if (pll == NULL)
1931 return;
1932
1933 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1934 return;
1935
1936 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1937 pll->name, pll->active, pll->on,
1938 crtc->base.base.id);
1939
1940 if (WARN_ON(pll->active == 0)) {
1941 assert_shared_dpll_disabled(dev_priv, pll);
1942 return;
1943 }
1944
1945 assert_shared_dpll_enabled(dev_priv, pll);
1946 WARN_ON(!pll->on);
1947 if (--pll->active)
1948 return;
1949
1950 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1951 pll->disable(dev_priv, pll);
1952 pll->on = false;
1953
1954 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1955 }
1956
1957 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1958 enum pipe pipe)
1959 {
1960 struct drm_device *dev = dev_priv->dev;
1961 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1963 uint32_t reg, val, pipeconf_val;
1964
1965 /* PCH only available on ILK+ */
1966 BUG_ON(!HAS_PCH_SPLIT(dev));
1967
1968 /* Make sure PCH DPLL is enabled */
1969 assert_shared_dpll_enabled(dev_priv,
1970 intel_crtc_to_shared_dpll(intel_crtc));
1971
1972 /* FDI must be feeding us bits for PCH ports */
1973 assert_fdi_tx_enabled(dev_priv, pipe);
1974 assert_fdi_rx_enabled(dev_priv, pipe);
1975
1976 if (HAS_PCH_CPT(dev)) {
1977 /* Workaround: Set the timing override bit before enabling the
1978 * pch transcoder. */
1979 reg = TRANS_CHICKEN2(pipe);
1980 val = I915_READ(reg);
1981 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1982 I915_WRITE(reg, val);
1983 }
1984
1985 reg = PCH_TRANSCONF(pipe);
1986 val = I915_READ(reg);
1987 pipeconf_val = I915_READ(PIPECONF(pipe));
1988
1989 if (HAS_PCH_IBX(dev_priv->dev)) {
1990 /*
1991 * Make the BPC in transcoder be consistent with
1992 * that in pipeconf reg. For HDMI we must use 8bpc
1993 * here for both 8bpc and 12bpc.
1994 */
1995 val &= ~PIPECONF_BPC_MASK;
1996 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1997 val |= PIPECONF_8BPC;
1998 else
1999 val |= pipeconf_val & PIPECONF_BPC_MASK;
2000 }
2001
2002 val &= ~TRANS_INTERLACE_MASK;
2003 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2004 if (HAS_PCH_IBX(dev_priv->dev) &&
2005 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2006 val |= TRANS_LEGACY_INTERLACED_ILK;
2007 else
2008 val |= TRANS_INTERLACED;
2009 else
2010 val |= TRANS_PROGRESSIVE;
2011
2012 I915_WRITE(reg, val | TRANS_ENABLE);
2013 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2014 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2015 }
2016
2017 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2018 enum transcoder cpu_transcoder)
2019 {
2020 u32 val, pipeconf_val;
2021
2022 /* PCH only available on ILK+ */
2023 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2024
2025 /* FDI must be feeding us bits for PCH ports */
2026 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2027 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2028
2029 /* Workaround: set timing override bit. */
2030 val = I915_READ(_TRANSA_CHICKEN2);
2031 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2032 I915_WRITE(_TRANSA_CHICKEN2, val);
2033
2034 val = TRANS_ENABLE;
2035 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2036
2037 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2038 PIPECONF_INTERLACED_ILK)
2039 val |= TRANS_INTERLACED;
2040 else
2041 val |= TRANS_PROGRESSIVE;
2042
2043 I915_WRITE(LPT_TRANSCONF, val);
2044 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2045 DRM_ERROR("Failed to enable PCH transcoder\n");
2046 }
2047
2048 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2049 enum pipe pipe)
2050 {
2051 struct drm_device *dev = dev_priv->dev;
2052 uint32_t reg, val;
2053
2054 /* FDI relies on the transcoder */
2055 assert_fdi_tx_disabled(dev_priv, pipe);
2056 assert_fdi_rx_disabled(dev_priv, pipe);
2057
2058 /* Ports must be off as well */
2059 assert_pch_ports_disabled(dev_priv, pipe);
2060
2061 reg = PCH_TRANSCONF(pipe);
2062 val = I915_READ(reg);
2063 val &= ~TRANS_ENABLE;
2064 I915_WRITE(reg, val);
2065 /* wait for PCH transcoder off, transcoder state */
2066 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2067 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2068
2069 if (!HAS_PCH_IBX(dev)) {
2070 /* Workaround: Clear the timing override chicken bit again. */
2071 reg = TRANS_CHICKEN2(pipe);
2072 val = I915_READ(reg);
2073 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2074 I915_WRITE(reg, val);
2075 }
2076 }
2077
2078 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2079 {
2080 u32 val;
2081
2082 val = I915_READ(LPT_TRANSCONF);
2083 val &= ~TRANS_ENABLE;
2084 I915_WRITE(LPT_TRANSCONF, val);
2085 /* wait for PCH transcoder off, transcoder state */
2086 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2087 DRM_ERROR("Failed to disable PCH transcoder\n");
2088
2089 /* Workaround: clear timing override bit. */
2090 val = I915_READ(_TRANSA_CHICKEN2);
2091 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2092 I915_WRITE(_TRANSA_CHICKEN2, val);
2093 }
2094
2095 /**
2096 * intel_enable_pipe - enable a pipe, asserting requirements
2097 * @crtc: crtc responsible for the pipe
2098 *
2099 * Enable @crtc's pipe, making sure that various hardware specific requirements
2100 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2101 */
2102 static void intel_enable_pipe(struct intel_crtc *crtc)
2103 {
2104 struct drm_device *dev = crtc->base.dev;
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2106 enum pipe pipe = crtc->pipe;
2107 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2108 pipe);
2109 enum pipe pch_transcoder;
2110 int reg;
2111 u32 val;
2112
2113 assert_planes_disabled(dev_priv, pipe);
2114 assert_cursor_disabled(dev_priv, pipe);
2115 assert_sprites_disabled(dev_priv, pipe);
2116
2117 if (HAS_PCH_LPT(dev_priv->dev))
2118 pch_transcoder = TRANSCODER_A;
2119 else
2120 pch_transcoder = pipe;
2121
2122 /*
2123 * A pipe without a PLL won't actually be able to drive bits from
2124 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2125 * need the check.
2126 */
2127 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2128 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2129 assert_dsi_pll_enabled(dev_priv);
2130 else
2131 assert_pll_enabled(dev_priv, pipe);
2132 else {
2133 if (crtc->config->has_pch_encoder) {
2134 /* if driving the PCH, we need FDI enabled */
2135 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2136 assert_fdi_tx_pll_enabled(dev_priv,
2137 (enum pipe) cpu_transcoder);
2138 }
2139 /* FIXME: assert CPU port conditions for SNB+ */
2140 }
2141
2142 reg = PIPECONF(cpu_transcoder);
2143 val = I915_READ(reg);
2144 if (val & PIPECONF_ENABLE) {
2145 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2146 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2147 return;
2148 }
2149
2150 I915_WRITE(reg, val | PIPECONF_ENABLE);
2151 POSTING_READ(reg);
2152 }
2153
2154 /**
2155 * intel_disable_pipe - disable a pipe, asserting requirements
2156 * @crtc: crtc whose pipes is to be disabled
2157 *
2158 * Disable the pipe of @crtc, making sure that various hardware
2159 * specific requirements are met, if applicable, e.g. plane
2160 * disabled, panel fitter off, etc.
2161 *
2162 * Will wait until the pipe has shut down before returning.
2163 */
2164 static void intel_disable_pipe(struct intel_crtc *crtc)
2165 {
2166 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2167 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2168 enum pipe pipe = crtc->pipe;
2169 int reg;
2170 u32 val;
2171
2172 /*
2173 * Make sure planes won't keep trying to pump pixels to us,
2174 * or we might hang the display.
2175 */
2176 assert_planes_disabled(dev_priv, pipe);
2177 assert_cursor_disabled(dev_priv, pipe);
2178 assert_sprites_disabled(dev_priv, pipe);
2179
2180 reg = PIPECONF(cpu_transcoder);
2181 val = I915_READ(reg);
2182 if ((val & PIPECONF_ENABLE) == 0)
2183 return;
2184
2185 /*
2186 * Double wide has implications for planes
2187 * so best keep it disabled when not needed.
2188 */
2189 if (crtc->config->double_wide)
2190 val &= ~PIPECONF_DOUBLE_WIDE;
2191
2192 /* Don't disable pipe or pipe PLLs if needed */
2193 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2194 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2195 val &= ~PIPECONF_ENABLE;
2196
2197 I915_WRITE(reg, val);
2198 if ((val & PIPECONF_ENABLE) == 0)
2199 intel_wait_for_pipe_off(crtc);
2200 }
2201
2202 static bool need_vtd_wa(struct drm_device *dev)
2203 {
2204 #ifdef CONFIG_INTEL_IOMMU
2205 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2206 return true;
2207 #endif
2208 return false;
2209 }
2210
2211 unsigned int
2212 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2213 uint64_t fb_format_modifier)
2214 {
2215 unsigned int tile_height;
2216 uint32_t pixel_bytes;
2217
2218 switch (fb_format_modifier) {
2219 case DRM_FORMAT_MOD_NONE:
2220 tile_height = 1;
2221 break;
2222 case I915_FORMAT_MOD_X_TILED:
2223 tile_height = IS_GEN2(dev) ? 16 : 8;
2224 break;
2225 case I915_FORMAT_MOD_Y_TILED:
2226 tile_height = 32;
2227 break;
2228 case I915_FORMAT_MOD_Yf_TILED:
2229 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2230 switch (pixel_bytes) {
2231 default:
2232 case 1:
2233 tile_height = 64;
2234 break;
2235 case 2:
2236 case 4:
2237 tile_height = 32;
2238 break;
2239 case 8:
2240 tile_height = 16;
2241 break;
2242 case 16:
2243 WARN_ONCE(1,
2244 "128-bit pixels are not supported for display!");
2245 tile_height = 16;
2246 break;
2247 }
2248 break;
2249 default:
2250 MISSING_CASE(fb_format_modifier);
2251 tile_height = 1;
2252 break;
2253 }
2254
2255 return tile_height;
2256 }
2257
2258 unsigned int
2259 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2260 uint32_t pixel_format, uint64_t fb_format_modifier)
2261 {
2262 return ALIGN(height, intel_tile_height(dev, pixel_format,
2263 fb_format_modifier));
2264 }
2265
2266 static int
2267 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2268 const struct drm_plane_state *plane_state)
2269 {
2270 struct intel_rotation_info *info = &view->rotation_info;
2271 unsigned int tile_height, tile_pitch;
2272
2273 *view = i915_ggtt_view_normal;
2274
2275 if (!plane_state)
2276 return 0;
2277
2278 if (!intel_rotation_90_or_270(plane_state->rotation))
2279 return 0;
2280
2281 *view = i915_ggtt_view_rotated;
2282
2283 info->height = fb->height;
2284 info->pixel_format = fb->pixel_format;
2285 info->pitch = fb->pitches[0];
2286 info->fb_modifier = fb->modifier[0];
2287
2288 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2289 fb->modifier[0]);
2290 tile_pitch = PAGE_SIZE / tile_height;
2291 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2292 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2293 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2294
2295 return 0;
2296 }
2297
2298 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2299 {
2300 if (INTEL_INFO(dev_priv)->gen >= 9)
2301 return 256 * 1024;
2302 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2303 IS_VALLEYVIEW(dev_priv))
2304 return 128 * 1024;
2305 else if (INTEL_INFO(dev_priv)->gen >= 4)
2306 return 4 * 1024;
2307 else
2308 return 0;
2309 }
2310
2311 int
2312 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2313 struct drm_framebuffer *fb,
2314 const struct drm_plane_state *plane_state,
2315 struct intel_engine_cs *pipelined,
2316 struct drm_i915_gem_request **pipelined_request)
2317 {
2318 struct drm_device *dev = fb->dev;
2319 struct drm_i915_private *dev_priv = dev->dev_private;
2320 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2321 struct i915_ggtt_view view;
2322 u32 alignment;
2323 int ret;
2324
2325 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2326
2327 switch (fb->modifier[0]) {
2328 case DRM_FORMAT_MOD_NONE:
2329 alignment = intel_linear_alignment(dev_priv);
2330 break;
2331 case I915_FORMAT_MOD_X_TILED:
2332 if (INTEL_INFO(dev)->gen >= 9)
2333 alignment = 256 * 1024;
2334 else {
2335 /* pin() will align the object as required by fence */
2336 alignment = 0;
2337 }
2338 break;
2339 case I915_FORMAT_MOD_Y_TILED:
2340 case I915_FORMAT_MOD_Yf_TILED:
2341 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2342 "Y tiling bo slipped through, driver bug!\n"))
2343 return -EINVAL;
2344 alignment = 1 * 1024 * 1024;
2345 break;
2346 default:
2347 MISSING_CASE(fb->modifier[0]);
2348 return -EINVAL;
2349 }
2350
2351 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2352 if (ret)
2353 return ret;
2354
2355 /* Note that the w/a also requires 64 PTE of padding following the
2356 * bo. We currently fill all unused PTE with the shadow page and so
2357 * we should always have valid PTE following the scanout preventing
2358 * the VT-d warning.
2359 */
2360 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2361 alignment = 256 * 1024;
2362
2363 /*
2364 * Global gtt pte registers are special registers which actually forward
2365 * writes to a chunk of system memory. Which means that there is no risk
2366 * that the register values disappear as soon as we call
2367 * intel_runtime_pm_put(), so it is correct to wrap only the
2368 * pin/unpin/fence and not more.
2369 */
2370 intel_runtime_pm_get(dev_priv);
2371
2372 dev_priv->mm.interruptible = false;
2373 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2374 pipelined_request, &view);
2375 if (ret)
2376 goto err_interruptible;
2377
2378 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2379 * fence, whereas 965+ only requires a fence if using
2380 * framebuffer compression. For simplicity, we always install
2381 * a fence as the cost is not that onerous.
2382 */
2383 ret = i915_gem_object_get_fence(obj);
2384 if (ret)
2385 goto err_unpin;
2386
2387 i915_gem_object_pin_fence(obj);
2388
2389 dev_priv->mm.interruptible = true;
2390 intel_runtime_pm_put(dev_priv);
2391 return 0;
2392
2393 err_unpin:
2394 i915_gem_object_unpin_from_display_plane(obj, &view);
2395 err_interruptible:
2396 dev_priv->mm.interruptible = true;
2397 intel_runtime_pm_put(dev_priv);
2398 return ret;
2399 }
2400
2401 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2402 const struct drm_plane_state *plane_state)
2403 {
2404 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2405 struct i915_ggtt_view view;
2406 int ret;
2407
2408 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2409
2410 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2411 WARN_ONCE(ret, "Couldn't get view from plane state!");
2412
2413 i915_gem_object_unpin_fence(obj);
2414 i915_gem_object_unpin_from_display_plane(obj, &view);
2415 }
2416
2417 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2418 * is assumed to be a power-of-two. */
2419 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2420 int *x, int *y,
2421 unsigned int tiling_mode,
2422 unsigned int cpp,
2423 unsigned int pitch)
2424 {
2425 if (tiling_mode != I915_TILING_NONE) {
2426 unsigned int tile_rows, tiles;
2427
2428 tile_rows = *y / 8;
2429 *y %= 8;
2430
2431 tiles = *x / (512/cpp);
2432 *x %= 512/cpp;
2433
2434 return tile_rows * pitch * 8 + tiles * 4096;
2435 } else {
2436 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2437 unsigned int offset;
2438
2439 offset = *y * pitch + *x * cpp;
2440 *y = (offset & alignment) / pitch;
2441 *x = ((offset & alignment) - *y * pitch) / cpp;
2442 return offset & ~alignment;
2443 }
2444 }
2445
2446 static int i9xx_format_to_fourcc(int format)
2447 {
2448 switch (format) {
2449 case DISPPLANE_8BPP:
2450 return DRM_FORMAT_C8;
2451 case DISPPLANE_BGRX555:
2452 return DRM_FORMAT_XRGB1555;
2453 case DISPPLANE_BGRX565:
2454 return DRM_FORMAT_RGB565;
2455 default:
2456 case DISPPLANE_BGRX888:
2457 return DRM_FORMAT_XRGB8888;
2458 case DISPPLANE_RGBX888:
2459 return DRM_FORMAT_XBGR8888;
2460 case DISPPLANE_BGRX101010:
2461 return DRM_FORMAT_XRGB2101010;
2462 case DISPPLANE_RGBX101010:
2463 return DRM_FORMAT_XBGR2101010;
2464 }
2465 }
2466
2467 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2468 {
2469 switch (format) {
2470 case PLANE_CTL_FORMAT_RGB_565:
2471 return DRM_FORMAT_RGB565;
2472 default:
2473 case PLANE_CTL_FORMAT_XRGB_8888:
2474 if (rgb_order) {
2475 if (alpha)
2476 return DRM_FORMAT_ABGR8888;
2477 else
2478 return DRM_FORMAT_XBGR8888;
2479 } else {
2480 if (alpha)
2481 return DRM_FORMAT_ARGB8888;
2482 else
2483 return DRM_FORMAT_XRGB8888;
2484 }
2485 case PLANE_CTL_FORMAT_XRGB_2101010:
2486 if (rgb_order)
2487 return DRM_FORMAT_XBGR2101010;
2488 else
2489 return DRM_FORMAT_XRGB2101010;
2490 }
2491 }
2492
2493 static bool
2494 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2495 struct intel_initial_plane_config *plane_config)
2496 {
2497 struct drm_device *dev = crtc->base.dev;
2498 struct drm_i915_gem_object *obj = NULL;
2499 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2500 struct drm_framebuffer *fb = &plane_config->fb->base;
2501 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2502 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2503 PAGE_SIZE);
2504
2505 size_aligned -= base_aligned;
2506
2507 if (plane_config->size == 0)
2508 return false;
2509
2510 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2511 base_aligned,
2512 base_aligned,
2513 size_aligned);
2514 if (!obj)
2515 return false;
2516
2517 obj->tiling_mode = plane_config->tiling;
2518 if (obj->tiling_mode == I915_TILING_X)
2519 obj->stride = fb->pitches[0];
2520
2521 mode_cmd.pixel_format = fb->pixel_format;
2522 mode_cmd.width = fb->width;
2523 mode_cmd.height = fb->height;
2524 mode_cmd.pitches[0] = fb->pitches[0];
2525 mode_cmd.modifier[0] = fb->modifier[0];
2526 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2527
2528 mutex_lock(&dev->struct_mutex);
2529 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2530 &mode_cmd, obj)) {
2531 DRM_DEBUG_KMS("intel fb init failed\n");
2532 goto out_unref_obj;
2533 }
2534 mutex_unlock(&dev->struct_mutex);
2535
2536 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2537 return true;
2538
2539 out_unref_obj:
2540 drm_gem_object_unreference(&obj->base);
2541 mutex_unlock(&dev->struct_mutex);
2542 return false;
2543 }
2544
2545 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2546 static void
2547 update_state_fb(struct drm_plane *plane)
2548 {
2549 if (plane->fb == plane->state->fb)
2550 return;
2551
2552 if (plane->state->fb)
2553 drm_framebuffer_unreference(plane->state->fb);
2554 plane->state->fb = plane->fb;
2555 if (plane->state->fb)
2556 drm_framebuffer_reference(plane->state->fb);
2557 }
2558
2559 static void
2560 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2561 struct intel_initial_plane_config *plane_config)
2562 {
2563 struct drm_device *dev = intel_crtc->base.dev;
2564 struct drm_i915_private *dev_priv = dev->dev_private;
2565 struct drm_crtc *c;
2566 struct intel_crtc *i;
2567 struct drm_i915_gem_object *obj;
2568 struct drm_plane *primary = intel_crtc->base.primary;
2569 struct drm_framebuffer *fb;
2570
2571 if (!plane_config->fb)
2572 return;
2573
2574 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2575 fb = &plane_config->fb->base;
2576 goto valid_fb;
2577 }
2578
2579 kfree(plane_config->fb);
2580
2581 /*
2582 * Failed to alloc the obj, check to see if we should share
2583 * an fb with another CRTC instead
2584 */
2585 for_each_crtc(dev, c) {
2586 i = to_intel_crtc(c);
2587
2588 if (c == &intel_crtc->base)
2589 continue;
2590
2591 if (!i->active)
2592 continue;
2593
2594 fb = c->primary->fb;
2595 if (!fb)
2596 continue;
2597
2598 obj = intel_fb_obj(fb);
2599 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2600 drm_framebuffer_reference(fb);
2601 goto valid_fb;
2602 }
2603 }
2604
2605 return;
2606
2607 valid_fb:
2608 obj = intel_fb_obj(fb);
2609 if (obj->tiling_mode != I915_TILING_NONE)
2610 dev_priv->preserve_bios_swizzle = true;
2611
2612 primary->fb = fb;
2613 primary->crtc = primary->state->crtc = &intel_crtc->base;
2614 update_state_fb(primary);
2615 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2616 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2617 }
2618
2619 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2620 struct drm_framebuffer *fb,
2621 int x, int y)
2622 {
2623 struct drm_device *dev = crtc->dev;
2624 struct drm_i915_private *dev_priv = dev->dev_private;
2625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2626 struct drm_plane *primary = crtc->primary;
2627 bool visible = to_intel_plane_state(primary->state)->visible;
2628 struct drm_i915_gem_object *obj;
2629 int plane = intel_crtc->plane;
2630 unsigned long linear_offset;
2631 u32 dspcntr;
2632 u32 reg = DSPCNTR(plane);
2633 int pixel_size;
2634
2635 if (!visible || !fb) {
2636 I915_WRITE(reg, 0);
2637 if (INTEL_INFO(dev)->gen >= 4)
2638 I915_WRITE(DSPSURF(plane), 0);
2639 else
2640 I915_WRITE(DSPADDR(plane), 0);
2641 POSTING_READ(reg);
2642 return;
2643 }
2644
2645 obj = intel_fb_obj(fb);
2646 if (WARN_ON(obj == NULL))
2647 return;
2648
2649 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2650
2651 dspcntr = DISPPLANE_GAMMA_ENABLE;
2652
2653 dspcntr |= DISPLAY_PLANE_ENABLE;
2654
2655 if (INTEL_INFO(dev)->gen < 4) {
2656 if (intel_crtc->pipe == PIPE_B)
2657 dspcntr |= DISPPLANE_SEL_PIPE_B;
2658
2659 /* pipesrc and dspsize control the size that is scaled from,
2660 * which should always be the user's requested size.
2661 */
2662 I915_WRITE(DSPSIZE(plane),
2663 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2664 (intel_crtc->config->pipe_src_w - 1));
2665 I915_WRITE(DSPPOS(plane), 0);
2666 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2667 I915_WRITE(PRIMSIZE(plane),
2668 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2669 (intel_crtc->config->pipe_src_w - 1));
2670 I915_WRITE(PRIMPOS(plane), 0);
2671 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2672 }
2673
2674 switch (fb->pixel_format) {
2675 case DRM_FORMAT_C8:
2676 dspcntr |= DISPPLANE_8BPP;
2677 break;
2678 case DRM_FORMAT_XRGB1555:
2679 dspcntr |= DISPPLANE_BGRX555;
2680 break;
2681 case DRM_FORMAT_RGB565:
2682 dspcntr |= DISPPLANE_BGRX565;
2683 break;
2684 case DRM_FORMAT_XRGB8888:
2685 dspcntr |= DISPPLANE_BGRX888;
2686 break;
2687 case DRM_FORMAT_XBGR8888:
2688 dspcntr |= DISPPLANE_RGBX888;
2689 break;
2690 case DRM_FORMAT_XRGB2101010:
2691 dspcntr |= DISPPLANE_BGRX101010;
2692 break;
2693 case DRM_FORMAT_XBGR2101010:
2694 dspcntr |= DISPPLANE_RGBX101010;
2695 break;
2696 default:
2697 BUG();
2698 }
2699
2700 if (INTEL_INFO(dev)->gen >= 4 &&
2701 obj->tiling_mode != I915_TILING_NONE)
2702 dspcntr |= DISPPLANE_TILED;
2703
2704 if (IS_G4X(dev))
2705 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2706
2707 linear_offset = y * fb->pitches[0] + x * pixel_size;
2708
2709 if (INTEL_INFO(dev)->gen >= 4) {
2710 intel_crtc->dspaddr_offset =
2711 intel_gen4_compute_page_offset(dev_priv,
2712 &x, &y, obj->tiling_mode,
2713 pixel_size,
2714 fb->pitches[0]);
2715 linear_offset -= intel_crtc->dspaddr_offset;
2716 } else {
2717 intel_crtc->dspaddr_offset = linear_offset;
2718 }
2719
2720 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2721 dspcntr |= DISPPLANE_ROTATE_180;
2722
2723 x += (intel_crtc->config->pipe_src_w - 1);
2724 y += (intel_crtc->config->pipe_src_h - 1);
2725
2726 /* Finding the last pixel of the last line of the display
2727 data and adding to linear_offset*/
2728 linear_offset +=
2729 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2730 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2731 }
2732
2733 I915_WRITE(reg, dspcntr);
2734
2735 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2736 if (INTEL_INFO(dev)->gen >= 4) {
2737 I915_WRITE(DSPSURF(plane),
2738 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2739 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2740 I915_WRITE(DSPLINOFF(plane), linear_offset);
2741 } else
2742 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2743 POSTING_READ(reg);
2744 }
2745
2746 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2747 struct drm_framebuffer *fb,
2748 int x, int y)
2749 {
2750 struct drm_device *dev = crtc->dev;
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2753 struct drm_plane *primary = crtc->primary;
2754 bool visible = to_intel_plane_state(primary->state)->visible;
2755 struct drm_i915_gem_object *obj;
2756 int plane = intel_crtc->plane;
2757 unsigned long linear_offset;
2758 u32 dspcntr;
2759 u32 reg = DSPCNTR(plane);
2760 int pixel_size;
2761
2762 if (!visible || !fb) {
2763 I915_WRITE(reg, 0);
2764 I915_WRITE(DSPSURF(plane), 0);
2765 POSTING_READ(reg);
2766 return;
2767 }
2768
2769 obj = intel_fb_obj(fb);
2770 if (WARN_ON(obj == NULL))
2771 return;
2772
2773 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2774
2775 dspcntr = DISPPLANE_GAMMA_ENABLE;
2776
2777 dspcntr |= DISPLAY_PLANE_ENABLE;
2778
2779 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2780 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2781
2782 switch (fb->pixel_format) {
2783 case DRM_FORMAT_C8:
2784 dspcntr |= DISPPLANE_8BPP;
2785 break;
2786 case DRM_FORMAT_RGB565:
2787 dspcntr |= DISPPLANE_BGRX565;
2788 break;
2789 case DRM_FORMAT_XRGB8888:
2790 dspcntr |= DISPPLANE_BGRX888;
2791 break;
2792 case DRM_FORMAT_XBGR8888:
2793 dspcntr |= DISPPLANE_RGBX888;
2794 break;
2795 case DRM_FORMAT_XRGB2101010:
2796 dspcntr |= DISPPLANE_BGRX101010;
2797 break;
2798 case DRM_FORMAT_XBGR2101010:
2799 dspcntr |= DISPPLANE_RGBX101010;
2800 break;
2801 default:
2802 BUG();
2803 }
2804
2805 if (obj->tiling_mode != I915_TILING_NONE)
2806 dspcntr |= DISPPLANE_TILED;
2807
2808 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2809 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2810
2811 linear_offset = y * fb->pitches[0] + x * pixel_size;
2812 intel_crtc->dspaddr_offset =
2813 intel_gen4_compute_page_offset(dev_priv,
2814 &x, &y, obj->tiling_mode,
2815 pixel_size,
2816 fb->pitches[0]);
2817 linear_offset -= intel_crtc->dspaddr_offset;
2818 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2819 dspcntr |= DISPPLANE_ROTATE_180;
2820
2821 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2822 x += (intel_crtc->config->pipe_src_w - 1);
2823 y += (intel_crtc->config->pipe_src_h - 1);
2824
2825 /* Finding the last pixel of the last line of the display
2826 data and adding to linear_offset*/
2827 linear_offset +=
2828 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2829 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2830 }
2831 }
2832
2833 I915_WRITE(reg, dspcntr);
2834
2835 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2836 I915_WRITE(DSPSURF(plane),
2837 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2838 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2839 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2840 } else {
2841 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2842 I915_WRITE(DSPLINOFF(plane), linear_offset);
2843 }
2844 POSTING_READ(reg);
2845 }
2846
2847 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2848 uint32_t pixel_format)
2849 {
2850 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2851
2852 /*
2853 * The stride is either expressed as a multiple of 64 bytes
2854 * chunks for linear buffers or in number of tiles for tiled
2855 * buffers.
2856 */
2857 switch (fb_modifier) {
2858 case DRM_FORMAT_MOD_NONE:
2859 return 64;
2860 case I915_FORMAT_MOD_X_TILED:
2861 if (INTEL_INFO(dev)->gen == 2)
2862 return 128;
2863 return 512;
2864 case I915_FORMAT_MOD_Y_TILED:
2865 /* No need to check for old gens and Y tiling since this is
2866 * about the display engine and those will be blocked before
2867 * we get here.
2868 */
2869 return 128;
2870 case I915_FORMAT_MOD_Yf_TILED:
2871 if (bits_per_pixel == 8)
2872 return 64;
2873 else
2874 return 128;
2875 default:
2876 MISSING_CASE(fb_modifier);
2877 return 64;
2878 }
2879 }
2880
2881 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2882 struct drm_i915_gem_object *obj)
2883 {
2884 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2885
2886 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2887 view = &i915_ggtt_view_rotated;
2888
2889 return i915_gem_obj_ggtt_offset_view(obj, view);
2890 }
2891
2892 /*
2893 * This function detaches (aka. unbinds) unused scalers in hardware
2894 */
2895 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2896 {
2897 struct drm_device *dev;
2898 struct drm_i915_private *dev_priv;
2899 struct intel_crtc_scaler_state *scaler_state;
2900 int i;
2901
2902 dev = intel_crtc->base.dev;
2903 dev_priv = dev->dev_private;
2904 scaler_state = &intel_crtc->config->scaler_state;
2905
2906 /* loop through and disable scalers that aren't in use */
2907 for (i = 0; i < intel_crtc->num_scalers; i++) {
2908 if (!scaler_state->scalers[i].in_use) {
2909 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2910 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2911 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2912 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2913 intel_crtc->base.base.id, intel_crtc->pipe, i);
2914 }
2915 }
2916 }
2917
2918 u32 skl_plane_ctl_format(uint32_t pixel_format)
2919 {
2920 switch (pixel_format) {
2921 case DRM_FORMAT_C8:
2922 return PLANE_CTL_FORMAT_INDEXED;
2923 case DRM_FORMAT_RGB565:
2924 return PLANE_CTL_FORMAT_RGB_565;
2925 case DRM_FORMAT_XBGR8888:
2926 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2927 case DRM_FORMAT_XRGB8888:
2928 return PLANE_CTL_FORMAT_XRGB_8888;
2929 /*
2930 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2931 * to be already pre-multiplied. We need to add a knob (or a different
2932 * DRM_FORMAT) for user-space to configure that.
2933 */
2934 case DRM_FORMAT_ABGR8888:
2935 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2936 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2937 case DRM_FORMAT_ARGB8888:
2938 return PLANE_CTL_FORMAT_XRGB_8888 |
2939 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2940 case DRM_FORMAT_XRGB2101010:
2941 return PLANE_CTL_FORMAT_XRGB_2101010;
2942 case DRM_FORMAT_XBGR2101010:
2943 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2944 case DRM_FORMAT_YUYV:
2945 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2946 case DRM_FORMAT_YVYU:
2947 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2948 case DRM_FORMAT_UYVY:
2949 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2950 case DRM_FORMAT_VYUY:
2951 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2952 default:
2953 MISSING_CASE(pixel_format);
2954 }
2955
2956 return 0;
2957 }
2958
2959 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2960 {
2961 switch (fb_modifier) {
2962 case DRM_FORMAT_MOD_NONE:
2963 break;
2964 case I915_FORMAT_MOD_X_TILED:
2965 return PLANE_CTL_TILED_X;
2966 case I915_FORMAT_MOD_Y_TILED:
2967 return PLANE_CTL_TILED_Y;
2968 case I915_FORMAT_MOD_Yf_TILED:
2969 return PLANE_CTL_TILED_YF;
2970 default:
2971 MISSING_CASE(fb_modifier);
2972 }
2973
2974 return 0;
2975 }
2976
2977 u32 skl_plane_ctl_rotation(unsigned int rotation)
2978 {
2979 switch (rotation) {
2980 case BIT(DRM_ROTATE_0):
2981 break;
2982 /*
2983 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2984 * while i915 HW rotation is clockwise, thats why this swapping.
2985 */
2986 case BIT(DRM_ROTATE_90):
2987 return PLANE_CTL_ROTATE_270;
2988 case BIT(DRM_ROTATE_180):
2989 return PLANE_CTL_ROTATE_180;
2990 case BIT(DRM_ROTATE_270):
2991 return PLANE_CTL_ROTATE_90;
2992 default:
2993 MISSING_CASE(rotation);
2994 }
2995
2996 return 0;
2997 }
2998
2999 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3000 struct drm_framebuffer *fb,
3001 int x, int y)
3002 {
3003 struct drm_device *dev = crtc->dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3006 struct drm_plane *plane = crtc->primary;
3007 bool visible = to_intel_plane_state(plane->state)->visible;
3008 struct drm_i915_gem_object *obj;
3009 int pipe = intel_crtc->pipe;
3010 u32 plane_ctl, stride_div, stride;
3011 u32 tile_height, plane_offset, plane_size;
3012 unsigned int rotation;
3013 int x_offset, y_offset;
3014 unsigned long surf_addr;
3015 struct intel_crtc_state *crtc_state = intel_crtc->config;
3016 struct intel_plane_state *plane_state;
3017 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3018 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3019 int scaler_id = -1;
3020
3021 plane_state = to_intel_plane_state(plane->state);
3022
3023 if (!visible || !fb) {
3024 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3025 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3026 POSTING_READ(PLANE_CTL(pipe, 0));
3027 return;
3028 }
3029
3030 plane_ctl = PLANE_CTL_ENABLE |
3031 PLANE_CTL_PIPE_GAMMA_ENABLE |
3032 PLANE_CTL_PIPE_CSC_ENABLE;
3033
3034 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3035 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3036 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3037
3038 rotation = plane->state->rotation;
3039 plane_ctl |= skl_plane_ctl_rotation(rotation);
3040
3041 obj = intel_fb_obj(fb);
3042 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3043 fb->pixel_format);
3044 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3045
3046 /*
3047 * FIXME: intel_plane_state->src, dst aren't set when transitional
3048 * update_plane helpers are called from legacy paths.
3049 * Once full atomic crtc is available, below check can be avoided.
3050 */
3051 if (drm_rect_width(&plane_state->src)) {
3052 scaler_id = plane_state->scaler_id;
3053 src_x = plane_state->src.x1 >> 16;
3054 src_y = plane_state->src.y1 >> 16;
3055 src_w = drm_rect_width(&plane_state->src) >> 16;
3056 src_h = drm_rect_height(&plane_state->src) >> 16;
3057 dst_x = plane_state->dst.x1;
3058 dst_y = plane_state->dst.y1;
3059 dst_w = drm_rect_width(&plane_state->dst);
3060 dst_h = drm_rect_height(&plane_state->dst);
3061
3062 WARN_ON(x != src_x || y != src_y);
3063 } else {
3064 src_w = intel_crtc->config->pipe_src_w;
3065 src_h = intel_crtc->config->pipe_src_h;
3066 }
3067
3068 if (intel_rotation_90_or_270(rotation)) {
3069 /* stride = Surface height in tiles */
3070 tile_height = intel_tile_height(dev, fb->pixel_format,
3071 fb->modifier[0]);
3072 stride = DIV_ROUND_UP(fb->height, tile_height);
3073 x_offset = stride * tile_height - y - src_h;
3074 y_offset = x;
3075 plane_size = (src_w - 1) << 16 | (src_h - 1);
3076 } else {
3077 stride = fb->pitches[0] / stride_div;
3078 x_offset = x;
3079 y_offset = y;
3080 plane_size = (src_h - 1) << 16 | (src_w - 1);
3081 }
3082 plane_offset = y_offset << 16 | x_offset;
3083
3084 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3085 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3086 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3087 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3088
3089 if (scaler_id >= 0) {
3090 uint32_t ps_ctrl = 0;
3091
3092 WARN_ON(!dst_w || !dst_h);
3093 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3094 crtc_state->scaler_state.scalers[scaler_id].mode;
3095 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3096 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3097 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3098 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3099 I915_WRITE(PLANE_POS(pipe, 0), 0);
3100 } else {
3101 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3102 }
3103
3104 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3105
3106 POSTING_READ(PLANE_SURF(pipe, 0));
3107 }
3108
3109 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3110 static int
3111 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3112 int x, int y, enum mode_set_atomic state)
3113 {
3114 struct drm_device *dev = crtc->dev;
3115 struct drm_i915_private *dev_priv = dev->dev_private;
3116
3117 if (dev_priv->display.disable_fbc)
3118 dev_priv->display.disable_fbc(dev);
3119
3120 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3121
3122 return 0;
3123 }
3124
3125 static void intel_complete_page_flips(struct drm_device *dev)
3126 {
3127 struct drm_crtc *crtc;
3128
3129 for_each_crtc(dev, crtc) {
3130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3131 enum plane plane = intel_crtc->plane;
3132
3133 intel_prepare_page_flip(dev, plane);
3134 intel_finish_page_flip_plane(dev, plane);
3135 }
3136 }
3137
3138 static void intel_update_primary_planes(struct drm_device *dev)
3139 {
3140 struct drm_i915_private *dev_priv = dev->dev_private;
3141 struct drm_crtc *crtc;
3142
3143 for_each_crtc(dev, crtc) {
3144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3145
3146 drm_modeset_lock(&crtc->mutex, NULL);
3147 /*
3148 * FIXME: Once we have proper support for primary planes (and
3149 * disabling them without disabling the entire crtc) allow again
3150 * a NULL crtc->primary->fb.
3151 */
3152 if (intel_crtc->active && crtc->primary->fb)
3153 dev_priv->display.update_primary_plane(crtc,
3154 crtc->primary->fb,
3155 crtc->x,
3156 crtc->y);
3157 drm_modeset_unlock(&crtc->mutex);
3158 }
3159 }
3160
3161 void intel_prepare_reset(struct drm_device *dev)
3162 {
3163 /* no reset support for gen2 */
3164 if (IS_GEN2(dev))
3165 return;
3166
3167 /* reset doesn't touch the display */
3168 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3169 return;
3170
3171 drm_modeset_lock_all(dev);
3172 /*
3173 * Disabling the crtcs gracefully seems nicer. Also the
3174 * g33 docs say we should at least disable all the planes.
3175 */
3176 intel_display_suspend(dev);
3177 }
3178
3179 void intel_finish_reset(struct drm_device *dev)
3180 {
3181 struct drm_i915_private *dev_priv = to_i915(dev);
3182
3183 /*
3184 * Flips in the rings will be nuked by the reset,
3185 * so complete all pending flips so that user space
3186 * will get its events and not get stuck.
3187 */
3188 intel_complete_page_flips(dev);
3189
3190 /* no reset support for gen2 */
3191 if (IS_GEN2(dev))
3192 return;
3193
3194 /* reset doesn't touch the display */
3195 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3196 /*
3197 * Flips in the rings have been nuked by the reset,
3198 * so update the base address of all primary
3199 * planes to the the last fb to make sure we're
3200 * showing the correct fb after a reset.
3201 */
3202 intel_update_primary_planes(dev);
3203 return;
3204 }
3205
3206 /*
3207 * The display has been reset as well,
3208 * so need a full re-initialization.
3209 */
3210 intel_runtime_pm_disable_interrupts(dev_priv);
3211 intel_runtime_pm_enable_interrupts(dev_priv);
3212
3213 intel_modeset_init_hw(dev);
3214
3215 spin_lock_irq(&dev_priv->irq_lock);
3216 if (dev_priv->display.hpd_irq_setup)
3217 dev_priv->display.hpd_irq_setup(dev);
3218 spin_unlock_irq(&dev_priv->irq_lock);
3219
3220 intel_modeset_setup_hw_state(dev, true);
3221
3222 intel_hpd_init(dev_priv);
3223
3224 drm_modeset_unlock_all(dev);
3225 }
3226
3227 static void
3228 intel_finish_fb(struct drm_framebuffer *old_fb)
3229 {
3230 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3231 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3232 bool was_interruptible = dev_priv->mm.interruptible;
3233 int ret;
3234
3235 /* Big Hammer, we also need to ensure that any pending
3236 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3237 * current scanout is retired before unpinning the old
3238 * framebuffer. Note that we rely on userspace rendering
3239 * into the buffer attached to the pipe they are waiting
3240 * on. If not, userspace generates a GPU hang with IPEHR
3241 * point to the MI_WAIT_FOR_EVENT.
3242 *
3243 * This should only fail upon a hung GPU, in which case we
3244 * can safely continue.
3245 */
3246 dev_priv->mm.interruptible = false;
3247 ret = i915_gem_object_wait_rendering(obj, true);
3248 dev_priv->mm.interruptible = was_interruptible;
3249
3250 WARN_ON(ret);
3251 }
3252
3253 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3254 {
3255 struct drm_device *dev = crtc->dev;
3256 struct drm_i915_private *dev_priv = dev->dev_private;
3257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3258 bool pending;
3259
3260 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3261 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3262 return false;
3263
3264 spin_lock_irq(&dev->event_lock);
3265 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3266 spin_unlock_irq(&dev->event_lock);
3267
3268 return pending;
3269 }
3270
3271 static void intel_update_pipe_size(struct intel_crtc *crtc)
3272 {
3273 struct drm_device *dev = crtc->base.dev;
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3275 const struct drm_display_mode *adjusted_mode;
3276
3277 if (!i915.fastboot)
3278 return;
3279
3280 /*
3281 * Update pipe size and adjust fitter if needed: the reason for this is
3282 * that in compute_mode_changes we check the native mode (not the pfit
3283 * mode) to see if we can flip rather than do a full mode set. In the
3284 * fastboot case, we'll flip, but if we don't update the pipesrc and
3285 * pfit state, we'll end up with a big fb scanned out into the wrong
3286 * sized surface.
3287 *
3288 * To fix this properly, we need to hoist the checks up into
3289 * compute_mode_changes (or above), check the actual pfit state and
3290 * whether the platform allows pfit disable with pipe active, and only
3291 * then update the pipesrc and pfit state, even on the flip path.
3292 */
3293
3294 adjusted_mode = &crtc->config->base.adjusted_mode;
3295
3296 I915_WRITE(PIPESRC(crtc->pipe),
3297 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3298 (adjusted_mode->crtc_vdisplay - 1));
3299 if (!crtc->config->pch_pfit.enabled &&
3300 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3301 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3302 I915_WRITE(PF_CTL(crtc->pipe), 0);
3303 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3304 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3305 }
3306 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3307 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3308 }
3309
3310 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3311 {
3312 struct drm_device *dev = crtc->dev;
3313 struct drm_i915_private *dev_priv = dev->dev_private;
3314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3315 int pipe = intel_crtc->pipe;
3316 u32 reg, temp;
3317
3318 /* enable normal train */
3319 reg = FDI_TX_CTL(pipe);
3320 temp = I915_READ(reg);
3321 if (IS_IVYBRIDGE(dev)) {
3322 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3323 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3324 } else {
3325 temp &= ~FDI_LINK_TRAIN_NONE;
3326 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3327 }
3328 I915_WRITE(reg, temp);
3329
3330 reg = FDI_RX_CTL(pipe);
3331 temp = I915_READ(reg);
3332 if (HAS_PCH_CPT(dev)) {
3333 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3334 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3335 } else {
3336 temp &= ~FDI_LINK_TRAIN_NONE;
3337 temp |= FDI_LINK_TRAIN_NONE;
3338 }
3339 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3340
3341 /* wait one idle pattern time */
3342 POSTING_READ(reg);
3343 udelay(1000);
3344
3345 /* IVB wants error correction enabled */
3346 if (IS_IVYBRIDGE(dev))
3347 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3348 FDI_FE_ERRC_ENABLE);
3349 }
3350
3351 /* The FDI link training functions for ILK/Ibexpeak. */
3352 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3353 {
3354 struct drm_device *dev = crtc->dev;
3355 struct drm_i915_private *dev_priv = dev->dev_private;
3356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357 int pipe = intel_crtc->pipe;
3358 u32 reg, temp, tries;
3359
3360 /* FDI needs bits from pipe first */
3361 assert_pipe_enabled(dev_priv, pipe);
3362
3363 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3364 for train result */
3365 reg = FDI_RX_IMR(pipe);
3366 temp = I915_READ(reg);
3367 temp &= ~FDI_RX_SYMBOL_LOCK;
3368 temp &= ~FDI_RX_BIT_LOCK;
3369 I915_WRITE(reg, temp);
3370 I915_READ(reg);
3371 udelay(150);
3372
3373 /* enable CPU FDI TX and PCH FDI RX */
3374 reg = FDI_TX_CTL(pipe);
3375 temp = I915_READ(reg);
3376 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3377 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3378 temp &= ~FDI_LINK_TRAIN_NONE;
3379 temp |= FDI_LINK_TRAIN_PATTERN_1;
3380 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3381
3382 reg = FDI_RX_CTL(pipe);
3383 temp = I915_READ(reg);
3384 temp &= ~FDI_LINK_TRAIN_NONE;
3385 temp |= FDI_LINK_TRAIN_PATTERN_1;
3386 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3387
3388 POSTING_READ(reg);
3389 udelay(150);
3390
3391 /* Ironlake workaround, enable clock pointer after FDI enable*/
3392 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3393 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3394 FDI_RX_PHASE_SYNC_POINTER_EN);
3395
3396 reg = FDI_RX_IIR(pipe);
3397 for (tries = 0; tries < 5; tries++) {
3398 temp = I915_READ(reg);
3399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3400
3401 if ((temp & FDI_RX_BIT_LOCK)) {
3402 DRM_DEBUG_KMS("FDI train 1 done.\n");
3403 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3404 break;
3405 }
3406 }
3407 if (tries == 5)
3408 DRM_ERROR("FDI train 1 fail!\n");
3409
3410 /* Train 2 */
3411 reg = FDI_TX_CTL(pipe);
3412 temp = I915_READ(reg);
3413 temp &= ~FDI_LINK_TRAIN_NONE;
3414 temp |= FDI_LINK_TRAIN_PATTERN_2;
3415 I915_WRITE(reg, temp);
3416
3417 reg = FDI_RX_CTL(pipe);
3418 temp = I915_READ(reg);
3419 temp &= ~FDI_LINK_TRAIN_NONE;
3420 temp |= FDI_LINK_TRAIN_PATTERN_2;
3421 I915_WRITE(reg, temp);
3422
3423 POSTING_READ(reg);
3424 udelay(150);
3425
3426 reg = FDI_RX_IIR(pipe);
3427 for (tries = 0; tries < 5; tries++) {
3428 temp = I915_READ(reg);
3429 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3430
3431 if (temp & FDI_RX_SYMBOL_LOCK) {
3432 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3433 DRM_DEBUG_KMS("FDI train 2 done.\n");
3434 break;
3435 }
3436 }
3437 if (tries == 5)
3438 DRM_ERROR("FDI train 2 fail!\n");
3439
3440 DRM_DEBUG_KMS("FDI train done\n");
3441
3442 }
3443
3444 static const int snb_b_fdi_train_param[] = {
3445 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3446 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3447 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3448 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3449 };
3450
3451 /* The FDI link training functions for SNB/Cougarpoint. */
3452 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3453 {
3454 struct drm_device *dev = crtc->dev;
3455 struct drm_i915_private *dev_priv = dev->dev_private;
3456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3457 int pipe = intel_crtc->pipe;
3458 u32 reg, temp, i, retry;
3459
3460 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3461 for train result */
3462 reg = FDI_RX_IMR(pipe);
3463 temp = I915_READ(reg);
3464 temp &= ~FDI_RX_SYMBOL_LOCK;
3465 temp &= ~FDI_RX_BIT_LOCK;
3466 I915_WRITE(reg, temp);
3467
3468 POSTING_READ(reg);
3469 udelay(150);
3470
3471 /* enable CPU FDI TX and PCH FDI RX */
3472 reg = FDI_TX_CTL(pipe);
3473 temp = I915_READ(reg);
3474 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3475 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3476 temp &= ~FDI_LINK_TRAIN_NONE;
3477 temp |= FDI_LINK_TRAIN_PATTERN_1;
3478 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3479 /* SNB-B */
3480 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3481 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3482
3483 I915_WRITE(FDI_RX_MISC(pipe),
3484 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3485
3486 reg = FDI_RX_CTL(pipe);
3487 temp = I915_READ(reg);
3488 if (HAS_PCH_CPT(dev)) {
3489 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3490 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3491 } else {
3492 temp &= ~FDI_LINK_TRAIN_NONE;
3493 temp |= FDI_LINK_TRAIN_PATTERN_1;
3494 }
3495 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3496
3497 POSTING_READ(reg);
3498 udelay(150);
3499
3500 for (i = 0; i < 4; i++) {
3501 reg = FDI_TX_CTL(pipe);
3502 temp = I915_READ(reg);
3503 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3504 temp |= snb_b_fdi_train_param[i];
3505 I915_WRITE(reg, temp);
3506
3507 POSTING_READ(reg);
3508 udelay(500);
3509
3510 for (retry = 0; retry < 5; retry++) {
3511 reg = FDI_RX_IIR(pipe);
3512 temp = I915_READ(reg);
3513 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3514 if (temp & FDI_RX_BIT_LOCK) {
3515 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3516 DRM_DEBUG_KMS("FDI train 1 done.\n");
3517 break;
3518 }
3519 udelay(50);
3520 }
3521 if (retry < 5)
3522 break;
3523 }
3524 if (i == 4)
3525 DRM_ERROR("FDI train 1 fail!\n");
3526
3527 /* Train 2 */
3528 reg = FDI_TX_CTL(pipe);
3529 temp = I915_READ(reg);
3530 temp &= ~FDI_LINK_TRAIN_NONE;
3531 temp |= FDI_LINK_TRAIN_PATTERN_2;
3532 if (IS_GEN6(dev)) {
3533 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3534 /* SNB-B */
3535 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3536 }
3537 I915_WRITE(reg, temp);
3538
3539 reg = FDI_RX_CTL(pipe);
3540 temp = I915_READ(reg);
3541 if (HAS_PCH_CPT(dev)) {
3542 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3543 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3544 } else {
3545 temp &= ~FDI_LINK_TRAIN_NONE;
3546 temp |= FDI_LINK_TRAIN_PATTERN_2;
3547 }
3548 I915_WRITE(reg, temp);
3549
3550 POSTING_READ(reg);
3551 udelay(150);
3552
3553 for (i = 0; i < 4; i++) {
3554 reg = FDI_TX_CTL(pipe);
3555 temp = I915_READ(reg);
3556 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3557 temp |= snb_b_fdi_train_param[i];
3558 I915_WRITE(reg, temp);
3559
3560 POSTING_READ(reg);
3561 udelay(500);
3562
3563 for (retry = 0; retry < 5; retry++) {
3564 reg = FDI_RX_IIR(pipe);
3565 temp = I915_READ(reg);
3566 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3567 if (temp & FDI_RX_SYMBOL_LOCK) {
3568 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3569 DRM_DEBUG_KMS("FDI train 2 done.\n");
3570 break;
3571 }
3572 udelay(50);
3573 }
3574 if (retry < 5)
3575 break;
3576 }
3577 if (i == 4)
3578 DRM_ERROR("FDI train 2 fail!\n");
3579
3580 DRM_DEBUG_KMS("FDI train done.\n");
3581 }
3582
3583 /* Manual link training for Ivy Bridge A0 parts */
3584 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3585 {
3586 struct drm_device *dev = crtc->dev;
3587 struct drm_i915_private *dev_priv = dev->dev_private;
3588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3589 int pipe = intel_crtc->pipe;
3590 u32 reg, temp, i, j;
3591
3592 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3593 for train result */
3594 reg = FDI_RX_IMR(pipe);
3595 temp = I915_READ(reg);
3596 temp &= ~FDI_RX_SYMBOL_LOCK;
3597 temp &= ~FDI_RX_BIT_LOCK;
3598 I915_WRITE(reg, temp);
3599
3600 POSTING_READ(reg);
3601 udelay(150);
3602
3603 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3604 I915_READ(FDI_RX_IIR(pipe)));
3605
3606 /* Try each vswing and preemphasis setting twice before moving on */
3607 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3608 /* disable first in case we need to retry */
3609 reg = FDI_TX_CTL(pipe);
3610 temp = I915_READ(reg);
3611 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3612 temp &= ~FDI_TX_ENABLE;
3613 I915_WRITE(reg, temp);
3614
3615 reg = FDI_RX_CTL(pipe);
3616 temp = I915_READ(reg);
3617 temp &= ~FDI_LINK_TRAIN_AUTO;
3618 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3619 temp &= ~FDI_RX_ENABLE;
3620 I915_WRITE(reg, temp);
3621
3622 /* enable CPU FDI TX and PCH FDI RX */
3623 reg = FDI_TX_CTL(pipe);
3624 temp = I915_READ(reg);
3625 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3626 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3627 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3628 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3629 temp |= snb_b_fdi_train_param[j/2];
3630 temp |= FDI_COMPOSITE_SYNC;
3631 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3632
3633 I915_WRITE(FDI_RX_MISC(pipe),
3634 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3635
3636 reg = FDI_RX_CTL(pipe);
3637 temp = I915_READ(reg);
3638 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3639 temp |= FDI_COMPOSITE_SYNC;
3640 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3641
3642 POSTING_READ(reg);
3643 udelay(1); /* should be 0.5us */
3644
3645 for (i = 0; i < 4; i++) {
3646 reg = FDI_RX_IIR(pipe);
3647 temp = I915_READ(reg);
3648 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3649
3650 if (temp & FDI_RX_BIT_LOCK ||
3651 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3652 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3653 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3654 i);
3655 break;
3656 }
3657 udelay(1); /* should be 0.5us */
3658 }
3659 if (i == 4) {
3660 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3661 continue;
3662 }
3663
3664 /* Train 2 */
3665 reg = FDI_TX_CTL(pipe);
3666 temp = I915_READ(reg);
3667 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3668 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3669 I915_WRITE(reg, temp);
3670
3671 reg = FDI_RX_CTL(pipe);
3672 temp = I915_READ(reg);
3673 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3674 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3675 I915_WRITE(reg, temp);
3676
3677 POSTING_READ(reg);
3678 udelay(2); /* should be 1.5us */
3679
3680 for (i = 0; i < 4; i++) {
3681 reg = FDI_RX_IIR(pipe);
3682 temp = I915_READ(reg);
3683 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3684
3685 if (temp & FDI_RX_SYMBOL_LOCK ||
3686 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3687 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3688 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3689 i);
3690 goto train_done;
3691 }
3692 udelay(2); /* should be 1.5us */
3693 }
3694 if (i == 4)
3695 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3696 }
3697
3698 train_done:
3699 DRM_DEBUG_KMS("FDI train done.\n");
3700 }
3701
3702 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3703 {
3704 struct drm_device *dev = intel_crtc->base.dev;
3705 struct drm_i915_private *dev_priv = dev->dev_private;
3706 int pipe = intel_crtc->pipe;
3707 u32 reg, temp;
3708
3709
3710 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3711 reg = FDI_RX_CTL(pipe);
3712 temp = I915_READ(reg);
3713 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3714 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3715 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3716 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3717
3718 POSTING_READ(reg);
3719 udelay(200);
3720
3721 /* Switch from Rawclk to PCDclk */
3722 temp = I915_READ(reg);
3723 I915_WRITE(reg, temp | FDI_PCDCLK);
3724
3725 POSTING_READ(reg);
3726 udelay(200);
3727
3728 /* Enable CPU FDI TX PLL, always on for Ironlake */
3729 reg = FDI_TX_CTL(pipe);
3730 temp = I915_READ(reg);
3731 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3732 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3733
3734 POSTING_READ(reg);
3735 udelay(100);
3736 }
3737 }
3738
3739 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3740 {
3741 struct drm_device *dev = intel_crtc->base.dev;
3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743 int pipe = intel_crtc->pipe;
3744 u32 reg, temp;
3745
3746 /* Switch from PCDclk to Rawclk */
3747 reg = FDI_RX_CTL(pipe);
3748 temp = I915_READ(reg);
3749 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3750
3751 /* Disable CPU FDI TX PLL */
3752 reg = FDI_TX_CTL(pipe);
3753 temp = I915_READ(reg);
3754 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3755
3756 POSTING_READ(reg);
3757 udelay(100);
3758
3759 reg = FDI_RX_CTL(pipe);
3760 temp = I915_READ(reg);
3761 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3762
3763 /* Wait for the clocks to turn off. */
3764 POSTING_READ(reg);
3765 udelay(100);
3766 }
3767
3768 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3769 {
3770 struct drm_device *dev = crtc->dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3773 int pipe = intel_crtc->pipe;
3774 u32 reg, temp;
3775
3776 /* disable CPU FDI tx and PCH FDI rx */
3777 reg = FDI_TX_CTL(pipe);
3778 temp = I915_READ(reg);
3779 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3780 POSTING_READ(reg);
3781
3782 reg = FDI_RX_CTL(pipe);
3783 temp = I915_READ(reg);
3784 temp &= ~(0x7 << 16);
3785 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3786 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3787
3788 POSTING_READ(reg);
3789 udelay(100);
3790
3791 /* Ironlake workaround, disable clock pointer after downing FDI */
3792 if (HAS_PCH_IBX(dev))
3793 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3794
3795 /* still set train pattern 1 */
3796 reg = FDI_TX_CTL(pipe);
3797 temp = I915_READ(reg);
3798 temp &= ~FDI_LINK_TRAIN_NONE;
3799 temp |= FDI_LINK_TRAIN_PATTERN_1;
3800 I915_WRITE(reg, temp);
3801
3802 reg = FDI_RX_CTL(pipe);
3803 temp = I915_READ(reg);
3804 if (HAS_PCH_CPT(dev)) {
3805 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3806 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3807 } else {
3808 temp &= ~FDI_LINK_TRAIN_NONE;
3809 temp |= FDI_LINK_TRAIN_PATTERN_1;
3810 }
3811 /* BPC in FDI rx is consistent with that in PIPECONF */
3812 temp &= ~(0x07 << 16);
3813 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3814 I915_WRITE(reg, temp);
3815
3816 POSTING_READ(reg);
3817 udelay(100);
3818 }
3819
3820 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3821 {
3822 struct intel_crtc *crtc;
3823
3824 /* Note that we don't need to be called with mode_config.lock here
3825 * as our list of CRTC objects is static for the lifetime of the
3826 * device and so cannot disappear as we iterate. Similarly, we can
3827 * happily treat the predicates as racy, atomic checks as userspace
3828 * cannot claim and pin a new fb without at least acquring the
3829 * struct_mutex and so serialising with us.
3830 */
3831 for_each_intel_crtc(dev, crtc) {
3832 if (atomic_read(&crtc->unpin_work_count) == 0)
3833 continue;
3834
3835 if (crtc->unpin_work)
3836 intel_wait_for_vblank(dev, crtc->pipe);
3837
3838 return true;
3839 }
3840
3841 return false;
3842 }
3843
3844 static void page_flip_completed(struct intel_crtc *intel_crtc)
3845 {
3846 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3847 struct intel_unpin_work *work = intel_crtc->unpin_work;
3848
3849 /* ensure that the unpin work is consistent wrt ->pending. */
3850 smp_rmb();
3851 intel_crtc->unpin_work = NULL;
3852
3853 if (work->event)
3854 drm_send_vblank_event(intel_crtc->base.dev,
3855 intel_crtc->pipe,
3856 work->event);
3857
3858 drm_crtc_vblank_put(&intel_crtc->base);
3859
3860 wake_up_all(&dev_priv->pending_flip_queue);
3861 queue_work(dev_priv->wq, &work->work);
3862
3863 trace_i915_flip_complete(intel_crtc->plane,
3864 work->pending_flip_obj);
3865 }
3866
3867 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3868 {
3869 struct drm_device *dev = crtc->dev;
3870 struct drm_i915_private *dev_priv = dev->dev_private;
3871
3872 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3873 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3874 !intel_crtc_has_pending_flip(crtc),
3875 60*HZ) == 0)) {
3876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3877
3878 spin_lock_irq(&dev->event_lock);
3879 if (intel_crtc->unpin_work) {
3880 WARN_ONCE(1, "Removing stuck page flip\n");
3881 page_flip_completed(intel_crtc);
3882 }
3883 spin_unlock_irq(&dev->event_lock);
3884 }
3885
3886 if (crtc->primary->fb) {
3887 mutex_lock(&dev->struct_mutex);
3888 intel_finish_fb(crtc->primary->fb);
3889 mutex_unlock(&dev->struct_mutex);
3890 }
3891 }
3892
3893 /* Program iCLKIP clock to the desired frequency */
3894 static void lpt_program_iclkip(struct drm_crtc *crtc)
3895 {
3896 struct drm_device *dev = crtc->dev;
3897 struct drm_i915_private *dev_priv = dev->dev_private;
3898 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3899 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3900 u32 temp;
3901
3902 mutex_lock(&dev_priv->sb_lock);
3903
3904 /* It is necessary to ungate the pixclk gate prior to programming
3905 * the divisors, and gate it back when it is done.
3906 */
3907 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3908
3909 /* Disable SSCCTL */
3910 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3911 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3912 SBI_SSCCTL_DISABLE,
3913 SBI_ICLK);
3914
3915 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3916 if (clock == 20000) {
3917 auxdiv = 1;
3918 divsel = 0x41;
3919 phaseinc = 0x20;
3920 } else {
3921 /* The iCLK virtual clock root frequency is in MHz,
3922 * but the adjusted_mode->crtc_clock in in KHz. To get the
3923 * divisors, it is necessary to divide one by another, so we
3924 * convert the virtual clock precision to KHz here for higher
3925 * precision.
3926 */
3927 u32 iclk_virtual_root_freq = 172800 * 1000;
3928 u32 iclk_pi_range = 64;
3929 u32 desired_divisor, msb_divisor_value, pi_value;
3930
3931 desired_divisor = (iclk_virtual_root_freq / clock);
3932 msb_divisor_value = desired_divisor / iclk_pi_range;
3933 pi_value = desired_divisor % iclk_pi_range;
3934
3935 auxdiv = 0;
3936 divsel = msb_divisor_value - 2;
3937 phaseinc = pi_value;
3938 }
3939
3940 /* This should not happen with any sane values */
3941 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3942 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3943 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3944 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3945
3946 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3947 clock,
3948 auxdiv,
3949 divsel,
3950 phasedir,
3951 phaseinc);
3952
3953 /* Program SSCDIVINTPHASE6 */
3954 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3955 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3956 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3957 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3958 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3959 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3960 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3961 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3962
3963 /* Program SSCAUXDIV */
3964 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3965 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3966 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3967 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3968
3969 /* Enable modulator and associated divider */
3970 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3971 temp &= ~SBI_SSCCTL_DISABLE;
3972 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3973
3974 /* Wait for initialization time */
3975 udelay(24);
3976
3977 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3978
3979 mutex_unlock(&dev_priv->sb_lock);
3980 }
3981
3982 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3983 enum pipe pch_transcoder)
3984 {
3985 struct drm_device *dev = crtc->base.dev;
3986 struct drm_i915_private *dev_priv = dev->dev_private;
3987 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3988
3989 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3990 I915_READ(HTOTAL(cpu_transcoder)));
3991 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3992 I915_READ(HBLANK(cpu_transcoder)));
3993 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3994 I915_READ(HSYNC(cpu_transcoder)));
3995
3996 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3997 I915_READ(VTOTAL(cpu_transcoder)));
3998 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3999 I915_READ(VBLANK(cpu_transcoder)));
4000 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4001 I915_READ(VSYNC(cpu_transcoder)));
4002 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4003 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4004 }
4005
4006 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4007 {
4008 struct drm_i915_private *dev_priv = dev->dev_private;
4009 uint32_t temp;
4010
4011 temp = I915_READ(SOUTH_CHICKEN1);
4012 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4013 return;
4014
4015 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4016 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4017
4018 temp &= ~FDI_BC_BIFURCATION_SELECT;
4019 if (enable)
4020 temp |= FDI_BC_BIFURCATION_SELECT;
4021
4022 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4023 I915_WRITE(SOUTH_CHICKEN1, temp);
4024 POSTING_READ(SOUTH_CHICKEN1);
4025 }
4026
4027 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4028 {
4029 struct drm_device *dev = intel_crtc->base.dev;
4030
4031 switch (intel_crtc->pipe) {
4032 case PIPE_A:
4033 break;
4034 case PIPE_B:
4035 if (intel_crtc->config->fdi_lanes > 2)
4036 cpt_set_fdi_bc_bifurcation(dev, false);
4037 else
4038 cpt_set_fdi_bc_bifurcation(dev, true);
4039
4040 break;
4041 case PIPE_C:
4042 cpt_set_fdi_bc_bifurcation(dev, true);
4043
4044 break;
4045 default:
4046 BUG();
4047 }
4048 }
4049
4050 /*
4051 * Enable PCH resources required for PCH ports:
4052 * - PCH PLLs
4053 * - FDI training & RX/TX
4054 * - update transcoder timings
4055 * - DP transcoding bits
4056 * - transcoder
4057 */
4058 static void ironlake_pch_enable(struct drm_crtc *crtc)
4059 {
4060 struct drm_device *dev = crtc->dev;
4061 struct drm_i915_private *dev_priv = dev->dev_private;
4062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4063 int pipe = intel_crtc->pipe;
4064 u32 reg, temp;
4065
4066 assert_pch_transcoder_disabled(dev_priv, pipe);
4067
4068 if (IS_IVYBRIDGE(dev))
4069 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4070
4071 /* Write the TU size bits before fdi link training, so that error
4072 * detection works. */
4073 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4074 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4075
4076 /* For PCH output, training FDI link */
4077 dev_priv->display.fdi_link_train(crtc);
4078
4079 /* We need to program the right clock selection before writing the pixel
4080 * mutliplier into the DPLL. */
4081 if (HAS_PCH_CPT(dev)) {
4082 u32 sel;
4083
4084 temp = I915_READ(PCH_DPLL_SEL);
4085 temp |= TRANS_DPLL_ENABLE(pipe);
4086 sel = TRANS_DPLLB_SEL(pipe);
4087 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4088 temp |= sel;
4089 else
4090 temp &= ~sel;
4091 I915_WRITE(PCH_DPLL_SEL, temp);
4092 }
4093
4094 /* XXX: pch pll's can be enabled any time before we enable the PCH
4095 * transcoder, and we actually should do this to not upset any PCH
4096 * transcoder that already use the clock when we share it.
4097 *
4098 * Note that enable_shared_dpll tries to do the right thing, but
4099 * get_shared_dpll unconditionally resets the pll - we need that to have
4100 * the right LVDS enable sequence. */
4101 intel_enable_shared_dpll(intel_crtc);
4102
4103 /* set transcoder timing, panel must allow it */
4104 assert_panel_unlocked(dev_priv, pipe);
4105 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4106
4107 intel_fdi_normal_train(crtc);
4108
4109 /* For PCH DP, enable TRANS_DP_CTL */
4110 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4111 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4112 reg = TRANS_DP_CTL(pipe);
4113 temp = I915_READ(reg);
4114 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4115 TRANS_DP_SYNC_MASK |
4116 TRANS_DP_BPC_MASK);
4117 temp |= TRANS_DP_OUTPUT_ENABLE;
4118 temp |= bpc << 9; /* same format but at 11:9 */
4119
4120 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4121 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4122 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4123 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4124
4125 switch (intel_trans_dp_port_sel(crtc)) {
4126 case PCH_DP_B:
4127 temp |= TRANS_DP_PORT_SEL_B;
4128 break;
4129 case PCH_DP_C:
4130 temp |= TRANS_DP_PORT_SEL_C;
4131 break;
4132 case PCH_DP_D:
4133 temp |= TRANS_DP_PORT_SEL_D;
4134 break;
4135 default:
4136 BUG();
4137 }
4138
4139 I915_WRITE(reg, temp);
4140 }
4141
4142 ironlake_enable_pch_transcoder(dev_priv, pipe);
4143 }
4144
4145 static void lpt_pch_enable(struct drm_crtc *crtc)
4146 {
4147 struct drm_device *dev = crtc->dev;
4148 struct drm_i915_private *dev_priv = dev->dev_private;
4149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4150 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4151
4152 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4153
4154 lpt_program_iclkip(crtc);
4155
4156 /* Set transcoder timing. */
4157 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4158
4159 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4160 }
4161
4162 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4163 struct intel_crtc_state *crtc_state)
4164 {
4165 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4166 struct intel_shared_dpll *pll;
4167 struct intel_shared_dpll_config *shared_dpll;
4168 enum intel_dpll_id i;
4169
4170 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4171
4172 if (HAS_PCH_IBX(dev_priv->dev)) {
4173 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4174 i = (enum intel_dpll_id) crtc->pipe;
4175 pll = &dev_priv->shared_dplls[i];
4176
4177 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4178 crtc->base.base.id, pll->name);
4179
4180 WARN_ON(shared_dpll[i].crtc_mask);
4181
4182 goto found;
4183 }
4184
4185 if (IS_BROXTON(dev_priv->dev)) {
4186 /* PLL is attached to port in bxt */
4187 struct intel_encoder *encoder;
4188 struct intel_digital_port *intel_dig_port;
4189
4190 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4191 if (WARN_ON(!encoder))
4192 return NULL;
4193
4194 intel_dig_port = enc_to_dig_port(&encoder->base);
4195 /* 1:1 mapping between ports and PLLs */
4196 i = (enum intel_dpll_id)intel_dig_port->port;
4197 pll = &dev_priv->shared_dplls[i];
4198 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4199 crtc->base.base.id, pll->name);
4200 WARN_ON(shared_dpll[i].crtc_mask);
4201
4202 goto found;
4203 }
4204
4205 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4206 pll = &dev_priv->shared_dplls[i];
4207
4208 /* Only want to check enabled timings first */
4209 if (shared_dpll[i].crtc_mask == 0)
4210 continue;
4211
4212 if (memcmp(&crtc_state->dpll_hw_state,
4213 &shared_dpll[i].hw_state,
4214 sizeof(crtc_state->dpll_hw_state)) == 0) {
4215 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4216 crtc->base.base.id, pll->name,
4217 shared_dpll[i].crtc_mask,
4218 pll->active);
4219 goto found;
4220 }
4221 }
4222
4223 /* Ok no matching timings, maybe there's a free one? */
4224 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4225 pll = &dev_priv->shared_dplls[i];
4226 if (shared_dpll[i].crtc_mask == 0) {
4227 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4228 crtc->base.base.id, pll->name);
4229 goto found;
4230 }
4231 }
4232
4233 return NULL;
4234
4235 found:
4236 if (shared_dpll[i].crtc_mask == 0)
4237 shared_dpll[i].hw_state =
4238 crtc_state->dpll_hw_state;
4239
4240 crtc_state->shared_dpll = i;
4241 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4242 pipe_name(crtc->pipe));
4243
4244 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4245
4246 return pll;
4247 }
4248
4249 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4250 {
4251 struct drm_i915_private *dev_priv = to_i915(state->dev);
4252 struct intel_shared_dpll_config *shared_dpll;
4253 struct intel_shared_dpll *pll;
4254 enum intel_dpll_id i;
4255
4256 if (!to_intel_atomic_state(state)->dpll_set)
4257 return;
4258
4259 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4260 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4261 pll = &dev_priv->shared_dplls[i];
4262 pll->config = shared_dpll[i];
4263 }
4264 }
4265
4266 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4267 {
4268 struct drm_i915_private *dev_priv = dev->dev_private;
4269 int dslreg = PIPEDSL(pipe);
4270 u32 temp;
4271
4272 temp = I915_READ(dslreg);
4273 udelay(500);
4274 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4275 if (wait_for(I915_READ(dslreg) != temp, 5))
4276 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4277 }
4278 }
4279
4280 static int
4281 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4282 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4283 int src_w, int src_h, int dst_w, int dst_h)
4284 {
4285 struct intel_crtc_scaler_state *scaler_state =
4286 &crtc_state->scaler_state;
4287 struct intel_crtc *intel_crtc =
4288 to_intel_crtc(crtc_state->base.crtc);
4289 int need_scaling;
4290
4291 need_scaling = intel_rotation_90_or_270(rotation) ?
4292 (src_h != dst_w || src_w != dst_h):
4293 (src_w != dst_w || src_h != dst_h);
4294
4295 /*
4296 * if plane is being disabled or scaler is no more required or force detach
4297 * - free scaler binded to this plane/crtc
4298 * - in order to do this, update crtc->scaler_usage
4299 *
4300 * Here scaler state in crtc_state is set free so that
4301 * scaler can be assigned to other user. Actual register
4302 * update to free the scaler is done in plane/panel-fit programming.
4303 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4304 */
4305 if (force_detach || !need_scaling) {
4306 if (*scaler_id >= 0) {
4307 scaler_state->scaler_users &= ~(1 << scaler_user);
4308 scaler_state->scalers[*scaler_id].in_use = 0;
4309
4310 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4311 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4312 intel_crtc->pipe, scaler_user, *scaler_id,
4313 scaler_state->scaler_users);
4314 *scaler_id = -1;
4315 }
4316 return 0;
4317 }
4318
4319 /* range checks */
4320 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4321 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4322
4323 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4324 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4325 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4326 "size is out of scaler range\n",
4327 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4328 return -EINVAL;
4329 }
4330
4331 /* mark this plane as a scaler user in crtc_state */
4332 scaler_state->scaler_users |= (1 << scaler_user);
4333 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4334 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4335 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4336 scaler_state->scaler_users);
4337
4338 return 0;
4339 }
4340
4341 /**
4342 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4343 *
4344 * @state: crtc's scaler state
4345 * @force_detach: whether to forcibly disable scaler
4346 *
4347 * Return
4348 * 0 - scaler_usage updated successfully
4349 * error - requested scaling cannot be supported or other error condition
4350 */
4351 int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4352 {
4353 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4354 struct drm_display_mode *adjusted_mode =
4355 &state->base.adjusted_mode;
4356
4357 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4358 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4359
4360 return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4361 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4362 state->pipe_src_w, state->pipe_src_h,
4363 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4364 }
4365
4366 /**
4367 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4368 *
4369 * @state: crtc's scaler state
4370 * @plane_state: atomic plane state to update
4371 *
4372 * Return
4373 * 0 - scaler_usage updated successfully
4374 * error - requested scaling cannot be supported or other error condition
4375 */
4376 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4377 struct intel_plane_state *plane_state)
4378 {
4379
4380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4381 struct intel_plane *intel_plane =
4382 to_intel_plane(plane_state->base.plane);
4383 struct drm_framebuffer *fb = plane_state->base.fb;
4384 int ret;
4385
4386 bool force_detach = !fb || !plane_state->visible;
4387
4388 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4389 intel_plane->base.base.id, intel_crtc->pipe,
4390 drm_plane_index(&intel_plane->base));
4391
4392 ret = skl_update_scaler(crtc_state, force_detach,
4393 drm_plane_index(&intel_plane->base),
4394 &plane_state->scaler_id,
4395 plane_state->base.rotation,
4396 drm_rect_width(&plane_state->src) >> 16,
4397 drm_rect_height(&plane_state->src) >> 16,
4398 drm_rect_width(&plane_state->dst),
4399 drm_rect_height(&plane_state->dst));
4400
4401 if (ret || plane_state->scaler_id < 0)
4402 return ret;
4403
4404 /* check colorkey */
4405 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4406 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4407 intel_plane->base.base.id);
4408 return -EINVAL;
4409 }
4410
4411 /* Check src format */
4412 switch (fb->pixel_format) {
4413 case DRM_FORMAT_RGB565:
4414 case DRM_FORMAT_XBGR8888:
4415 case DRM_FORMAT_XRGB8888:
4416 case DRM_FORMAT_ABGR8888:
4417 case DRM_FORMAT_ARGB8888:
4418 case DRM_FORMAT_XRGB2101010:
4419 case DRM_FORMAT_XBGR2101010:
4420 case DRM_FORMAT_YUYV:
4421 case DRM_FORMAT_YVYU:
4422 case DRM_FORMAT_UYVY:
4423 case DRM_FORMAT_VYUY:
4424 break;
4425 default:
4426 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4427 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4428 return -EINVAL;
4429 }
4430
4431 return 0;
4432 }
4433
4434 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4435 {
4436 struct drm_device *dev = crtc->base.dev;
4437 struct drm_i915_private *dev_priv = dev->dev_private;
4438 int pipe = crtc->pipe;
4439 struct intel_crtc_scaler_state *scaler_state =
4440 &crtc->config->scaler_state;
4441
4442 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4443
4444 /* To update pfit, first update scaler state */
4445 skl_update_scaler_crtc(crtc->config, !enable);
4446 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4447 skl_detach_scalers(crtc);
4448 if (!enable)
4449 return;
4450
4451 if (crtc->config->pch_pfit.enabled) {
4452 int id;
4453
4454 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4455 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4456 return;
4457 }
4458
4459 id = scaler_state->scaler_id;
4460 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4461 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4462 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4463 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4464
4465 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4466 }
4467 }
4468
4469 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4470 {
4471 struct drm_device *dev = crtc->base.dev;
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 int pipe = crtc->pipe;
4474
4475 if (crtc->config->pch_pfit.enabled) {
4476 /* Force use of hard-coded filter coefficients
4477 * as some pre-programmed values are broken,
4478 * e.g. x201.
4479 */
4480 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4481 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4482 PF_PIPE_SEL_IVB(pipe));
4483 else
4484 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4485 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4486 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4487 }
4488 }
4489
4490 void hsw_enable_ips(struct intel_crtc *crtc)
4491 {
4492 struct drm_device *dev = crtc->base.dev;
4493 struct drm_i915_private *dev_priv = dev->dev_private;
4494
4495 if (!crtc->config->ips_enabled)
4496 return;
4497
4498 /* We can only enable IPS after we enable a plane and wait for a vblank */
4499 intel_wait_for_vblank(dev, crtc->pipe);
4500
4501 assert_plane_enabled(dev_priv, crtc->plane);
4502 if (IS_BROADWELL(dev)) {
4503 mutex_lock(&dev_priv->rps.hw_lock);
4504 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4505 mutex_unlock(&dev_priv->rps.hw_lock);
4506 /* Quoting Art Runyan: "its not safe to expect any particular
4507 * value in IPS_CTL bit 31 after enabling IPS through the
4508 * mailbox." Moreover, the mailbox may return a bogus state,
4509 * so we need to just enable it and continue on.
4510 */
4511 } else {
4512 I915_WRITE(IPS_CTL, IPS_ENABLE);
4513 /* The bit only becomes 1 in the next vblank, so this wait here
4514 * is essentially intel_wait_for_vblank. If we don't have this
4515 * and don't wait for vblanks until the end of crtc_enable, then
4516 * the HW state readout code will complain that the expected
4517 * IPS_CTL value is not the one we read. */
4518 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4519 DRM_ERROR("Timed out waiting for IPS enable\n");
4520 }
4521 }
4522
4523 void hsw_disable_ips(struct intel_crtc *crtc)
4524 {
4525 struct drm_device *dev = crtc->base.dev;
4526 struct drm_i915_private *dev_priv = dev->dev_private;
4527
4528 if (!crtc->config->ips_enabled)
4529 return;
4530
4531 assert_plane_enabled(dev_priv, crtc->plane);
4532 if (IS_BROADWELL(dev)) {
4533 mutex_lock(&dev_priv->rps.hw_lock);
4534 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4535 mutex_unlock(&dev_priv->rps.hw_lock);
4536 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4537 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4538 DRM_ERROR("Timed out waiting for IPS disable\n");
4539 } else {
4540 I915_WRITE(IPS_CTL, 0);
4541 POSTING_READ(IPS_CTL);
4542 }
4543
4544 /* We need to wait for a vblank before we can disable the plane. */
4545 intel_wait_for_vblank(dev, crtc->pipe);
4546 }
4547
4548 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4549 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4550 {
4551 struct drm_device *dev = crtc->dev;
4552 struct drm_i915_private *dev_priv = dev->dev_private;
4553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4554 enum pipe pipe = intel_crtc->pipe;
4555 int palreg = PALETTE(pipe);
4556 int i;
4557 bool reenable_ips = false;
4558
4559 /* The clocks have to be on to load the palette. */
4560 if (!crtc->state->active)
4561 return;
4562
4563 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4564 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4565 assert_dsi_pll_enabled(dev_priv);
4566 else
4567 assert_pll_enabled(dev_priv, pipe);
4568 }
4569
4570 /* use legacy palette for Ironlake */
4571 if (!HAS_GMCH_DISPLAY(dev))
4572 palreg = LGC_PALETTE(pipe);
4573
4574 /* Workaround : Do not read or write the pipe palette/gamma data while
4575 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4576 */
4577 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4578 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4579 GAMMA_MODE_MODE_SPLIT)) {
4580 hsw_disable_ips(intel_crtc);
4581 reenable_ips = true;
4582 }
4583
4584 for (i = 0; i < 256; i++) {
4585 I915_WRITE(palreg + 4 * i,
4586 (intel_crtc->lut_r[i] << 16) |
4587 (intel_crtc->lut_g[i] << 8) |
4588 intel_crtc->lut_b[i]);
4589 }
4590
4591 if (reenable_ips)
4592 hsw_enable_ips(intel_crtc);
4593 }
4594
4595 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4596 {
4597 if (intel_crtc->overlay) {
4598 struct drm_device *dev = intel_crtc->base.dev;
4599 struct drm_i915_private *dev_priv = dev->dev_private;
4600
4601 mutex_lock(&dev->struct_mutex);
4602 dev_priv->mm.interruptible = false;
4603 (void) intel_overlay_switch_off(intel_crtc->overlay);
4604 dev_priv->mm.interruptible = true;
4605 mutex_unlock(&dev->struct_mutex);
4606 }
4607
4608 /* Let userspace switch the overlay on again. In most cases userspace
4609 * has to recompute where to put it anyway.
4610 */
4611 }
4612
4613 /**
4614 * intel_post_enable_primary - Perform operations after enabling primary plane
4615 * @crtc: the CRTC whose primary plane was just enabled
4616 *
4617 * Performs potentially sleeping operations that must be done after the primary
4618 * plane is enabled, such as updating FBC and IPS. Note that this may be
4619 * called due to an explicit primary plane update, or due to an implicit
4620 * re-enable that is caused when a sprite plane is updated to no longer
4621 * completely hide the primary plane.
4622 */
4623 static void
4624 intel_post_enable_primary(struct drm_crtc *crtc)
4625 {
4626 struct drm_device *dev = crtc->dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4629 int pipe = intel_crtc->pipe;
4630
4631 /*
4632 * BDW signals flip done immediately if the plane
4633 * is disabled, even if the plane enable is already
4634 * armed to occur at the next vblank :(
4635 */
4636 if (IS_BROADWELL(dev))
4637 intel_wait_for_vblank(dev, pipe);
4638
4639 /*
4640 * FIXME IPS should be fine as long as one plane is
4641 * enabled, but in practice it seems to have problems
4642 * when going from primary only to sprite only and vice
4643 * versa.
4644 */
4645 hsw_enable_ips(intel_crtc);
4646
4647 /*
4648 * Gen2 reports pipe underruns whenever all planes are disabled.
4649 * So don't enable underrun reporting before at least some planes
4650 * are enabled.
4651 * FIXME: Need to fix the logic to work when we turn off all planes
4652 * but leave the pipe running.
4653 */
4654 if (IS_GEN2(dev))
4655 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4656
4657 /* Underruns don't raise interrupts, so check manually. */
4658 if (HAS_GMCH_DISPLAY(dev))
4659 i9xx_check_fifo_underruns(dev_priv);
4660 }
4661
4662 /**
4663 * intel_pre_disable_primary - Perform operations before disabling primary plane
4664 * @crtc: the CRTC whose primary plane is to be disabled
4665 *
4666 * Performs potentially sleeping operations that must be done before the
4667 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4668 * be called due to an explicit primary plane update, or due to an implicit
4669 * disable that is caused when a sprite plane completely hides the primary
4670 * plane.
4671 */
4672 static void
4673 intel_pre_disable_primary(struct drm_crtc *crtc)
4674 {
4675 struct drm_device *dev = crtc->dev;
4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4678 int pipe = intel_crtc->pipe;
4679
4680 /*
4681 * Gen2 reports pipe underruns whenever all planes are disabled.
4682 * So diasble underrun reporting before all the planes get disabled.
4683 * FIXME: Need to fix the logic to work when we turn off all planes
4684 * but leave the pipe running.
4685 */
4686 if (IS_GEN2(dev))
4687 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4688
4689 /*
4690 * Vblank time updates from the shadow to live plane control register
4691 * are blocked if the memory self-refresh mode is active at that
4692 * moment. So to make sure the plane gets truly disabled, disable
4693 * first the self-refresh mode. The self-refresh enable bit in turn
4694 * will be checked/applied by the HW only at the next frame start
4695 * event which is after the vblank start event, so we need to have a
4696 * wait-for-vblank between disabling the plane and the pipe.
4697 */
4698 if (HAS_GMCH_DISPLAY(dev))
4699 intel_set_memory_cxsr(dev_priv, false);
4700
4701 /*
4702 * FIXME IPS should be fine as long as one plane is
4703 * enabled, but in practice it seems to have problems
4704 * when going from primary only to sprite only and vice
4705 * versa.
4706 */
4707 hsw_disable_ips(intel_crtc);
4708 }
4709
4710 static void intel_post_plane_update(struct intel_crtc *crtc)
4711 {
4712 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4713 struct drm_device *dev = crtc->base.dev;
4714 struct drm_plane *plane;
4715
4716 if (atomic->wait_vblank)
4717 intel_wait_for_vblank(dev, crtc->pipe);
4718
4719 intel_frontbuffer_flip(dev, atomic->fb_bits);
4720
4721 if (atomic->update_fbc) {
4722 mutex_lock(&dev->struct_mutex);
4723 intel_fbc_update(dev);
4724 mutex_unlock(&dev->struct_mutex);
4725 }
4726
4727 if (atomic->post_enable_primary)
4728 intel_post_enable_primary(&crtc->base);
4729
4730 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4731 intel_update_sprite_watermarks(plane, &crtc->base,
4732 0, 0, 0, false, false);
4733
4734 memset(atomic, 0, sizeof(*atomic));
4735 }
4736
4737 static void intel_pre_plane_update(struct intel_crtc *crtc)
4738 {
4739 struct drm_device *dev = crtc->base.dev;
4740 struct drm_i915_private *dev_priv = dev->dev_private;
4741 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4742 struct drm_plane *p;
4743
4744 /* Track fb's for any planes being disabled */
4745 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4746 struct intel_plane *plane = to_intel_plane(p);
4747
4748 mutex_lock(&dev->struct_mutex);
4749 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4750 plane->frontbuffer_bit);
4751 mutex_unlock(&dev->struct_mutex);
4752 }
4753
4754 if (atomic->wait_for_flips)
4755 intel_crtc_wait_for_pending_flips(&crtc->base);
4756
4757 if (atomic->disable_fbc &&
4758 dev_priv->fbc.crtc == crtc) {
4759 mutex_lock(&dev->struct_mutex);
4760 if (dev_priv->fbc.crtc == crtc)
4761 intel_fbc_disable(dev);
4762 mutex_unlock(&dev->struct_mutex);
4763 }
4764
4765 if (atomic->pre_disable_primary)
4766 intel_pre_disable_primary(&crtc->base);
4767 }
4768
4769 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4770 {
4771 struct drm_device *dev = crtc->dev;
4772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4773 struct drm_plane *p;
4774 int pipe = intel_crtc->pipe;
4775
4776 intel_crtc_dpms_overlay_disable(intel_crtc);
4777
4778 drm_for_each_plane_mask(p, dev, plane_mask)
4779 to_intel_plane(p)->disable_plane(p, crtc);
4780
4781 /*
4782 * FIXME: Once we grow proper nuclear flip support out of this we need
4783 * to compute the mask of flip planes precisely. For the time being
4784 * consider this a flip to a NULL plane.
4785 */
4786 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4787 }
4788
4789 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4790 {
4791 struct drm_device *dev = crtc->dev;
4792 struct drm_i915_private *dev_priv = dev->dev_private;
4793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4794 struct intel_encoder *encoder;
4795 int pipe = intel_crtc->pipe;
4796
4797 if (WARN_ON(intel_crtc->active))
4798 return;
4799
4800 if (intel_crtc->config->has_pch_encoder)
4801 intel_prepare_shared_dpll(intel_crtc);
4802
4803 if (intel_crtc->config->has_dp_encoder)
4804 intel_dp_set_m_n(intel_crtc, M1_N1);
4805
4806 intel_set_pipe_timings(intel_crtc);
4807
4808 if (intel_crtc->config->has_pch_encoder) {
4809 intel_cpu_transcoder_set_m_n(intel_crtc,
4810 &intel_crtc->config->fdi_m_n, NULL);
4811 }
4812
4813 ironlake_set_pipeconf(crtc);
4814
4815 intel_crtc->active = true;
4816
4817 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4818 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4819
4820 for_each_encoder_on_crtc(dev, crtc, encoder)
4821 if (encoder->pre_enable)
4822 encoder->pre_enable(encoder);
4823
4824 if (intel_crtc->config->has_pch_encoder) {
4825 /* Note: FDI PLL enabling _must_ be done before we enable the
4826 * cpu pipes, hence this is separate from all the other fdi/pch
4827 * enabling. */
4828 ironlake_fdi_pll_enable(intel_crtc);
4829 } else {
4830 assert_fdi_tx_disabled(dev_priv, pipe);
4831 assert_fdi_rx_disabled(dev_priv, pipe);
4832 }
4833
4834 ironlake_pfit_enable(intel_crtc);
4835
4836 /*
4837 * On ILK+ LUT must be loaded before the pipe is running but with
4838 * clocks enabled
4839 */
4840 intel_crtc_load_lut(crtc);
4841
4842 intel_update_watermarks(crtc);
4843 intel_enable_pipe(intel_crtc);
4844
4845 if (intel_crtc->config->has_pch_encoder)
4846 ironlake_pch_enable(crtc);
4847
4848 assert_vblank_disabled(crtc);
4849 drm_crtc_vblank_on(crtc);
4850
4851 for_each_encoder_on_crtc(dev, crtc, encoder)
4852 encoder->enable(encoder);
4853
4854 if (HAS_PCH_CPT(dev))
4855 cpt_verify_modeset(dev, intel_crtc->pipe);
4856 }
4857
4858 /* IPS only exists on ULT machines and is tied to pipe A. */
4859 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4860 {
4861 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4862 }
4863
4864 static void haswell_crtc_enable(struct drm_crtc *crtc)
4865 {
4866 struct drm_device *dev = crtc->dev;
4867 struct drm_i915_private *dev_priv = dev->dev_private;
4868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4869 struct intel_encoder *encoder;
4870 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4871 struct intel_crtc_state *pipe_config =
4872 to_intel_crtc_state(crtc->state);
4873
4874 if (WARN_ON(intel_crtc->active))
4875 return;
4876
4877 if (intel_crtc_to_shared_dpll(intel_crtc))
4878 intel_enable_shared_dpll(intel_crtc);
4879
4880 if (intel_crtc->config->has_dp_encoder)
4881 intel_dp_set_m_n(intel_crtc, M1_N1);
4882
4883 intel_set_pipe_timings(intel_crtc);
4884
4885 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4886 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4887 intel_crtc->config->pixel_multiplier - 1);
4888 }
4889
4890 if (intel_crtc->config->has_pch_encoder) {
4891 intel_cpu_transcoder_set_m_n(intel_crtc,
4892 &intel_crtc->config->fdi_m_n, NULL);
4893 }
4894
4895 haswell_set_pipeconf(crtc);
4896
4897 intel_set_pipe_csc(crtc);
4898
4899 intel_crtc->active = true;
4900
4901 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4902 for_each_encoder_on_crtc(dev, crtc, encoder)
4903 if (encoder->pre_enable)
4904 encoder->pre_enable(encoder);
4905
4906 if (intel_crtc->config->has_pch_encoder) {
4907 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4908 true);
4909 dev_priv->display.fdi_link_train(crtc);
4910 }
4911
4912 intel_ddi_enable_pipe_clock(intel_crtc);
4913
4914 if (INTEL_INFO(dev)->gen == 9)
4915 skylake_pfit_update(intel_crtc, 1);
4916 else if (INTEL_INFO(dev)->gen < 9)
4917 ironlake_pfit_enable(intel_crtc);
4918 else
4919 MISSING_CASE(INTEL_INFO(dev)->gen);
4920
4921 /*
4922 * On ILK+ LUT must be loaded before the pipe is running but with
4923 * clocks enabled
4924 */
4925 intel_crtc_load_lut(crtc);
4926
4927 intel_ddi_set_pipe_settings(crtc);
4928 intel_ddi_enable_transcoder_func(crtc);
4929
4930 intel_update_watermarks(crtc);
4931 intel_enable_pipe(intel_crtc);
4932
4933 if (intel_crtc->config->has_pch_encoder)
4934 lpt_pch_enable(crtc);
4935
4936 if (intel_crtc->config->dp_encoder_is_mst)
4937 intel_ddi_set_vc_payload_alloc(crtc, true);
4938
4939 assert_vblank_disabled(crtc);
4940 drm_crtc_vblank_on(crtc);
4941
4942 for_each_encoder_on_crtc(dev, crtc, encoder) {
4943 encoder->enable(encoder);
4944 intel_opregion_notify_encoder(encoder, true);
4945 }
4946
4947 /* If we change the relative order between pipe/planes enabling, we need
4948 * to change the workaround. */
4949 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4950 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4951 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4952 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4953 }
4954 }
4955
4956 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4957 {
4958 struct drm_device *dev = crtc->base.dev;
4959 struct drm_i915_private *dev_priv = dev->dev_private;
4960 int pipe = crtc->pipe;
4961
4962 /* To avoid upsetting the power well on haswell only disable the pfit if
4963 * it's in use. The hw state code will make sure we get this right. */
4964 if (crtc->config->pch_pfit.enabled) {
4965 I915_WRITE(PF_CTL(pipe), 0);
4966 I915_WRITE(PF_WIN_POS(pipe), 0);
4967 I915_WRITE(PF_WIN_SZ(pipe), 0);
4968 }
4969 }
4970
4971 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4972 {
4973 struct drm_device *dev = crtc->dev;
4974 struct drm_i915_private *dev_priv = dev->dev_private;
4975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4976 struct intel_encoder *encoder;
4977 int pipe = intel_crtc->pipe;
4978 u32 reg, temp;
4979
4980 for_each_encoder_on_crtc(dev, crtc, encoder)
4981 encoder->disable(encoder);
4982
4983 drm_crtc_vblank_off(crtc);
4984 assert_vblank_disabled(crtc);
4985
4986 if (intel_crtc->config->has_pch_encoder)
4987 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4988
4989 intel_disable_pipe(intel_crtc);
4990
4991 ironlake_pfit_disable(intel_crtc);
4992
4993 if (intel_crtc->config->has_pch_encoder)
4994 ironlake_fdi_disable(crtc);
4995
4996 for_each_encoder_on_crtc(dev, crtc, encoder)
4997 if (encoder->post_disable)
4998 encoder->post_disable(encoder);
4999
5000 if (intel_crtc->config->has_pch_encoder) {
5001 ironlake_disable_pch_transcoder(dev_priv, pipe);
5002
5003 if (HAS_PCH_CPT(dev)) {
5004 /* disable TRANS_DP_CTL */
5005 reg = TRANS_DP_CTL(pipe);
5006 temp = I915_READ(reg);
5007 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5008 TRANS_DP_PORT_SEL_MASK);
5009 temp |= TRANS_DP_PORT_SEL_NONE;
5010 I915_WRITE(reg, temp);
5011
5012 /* disable DPLL_SEL */
5013 temp = I915_READ(PCH_DPLL_SEL);
5014 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5015 I915_WRITE(PCH_DPLL_SEL, temp);
5016 }
5017
5018 ironlake_fdi_pll_disable(intel_crtc);
5019 }
5020 }
5021
5022 static void haswell_crtc_disable(struct drm_crtc *crtc)
5023 {
5024 struct drm_device *dev = crtc->dev;
5025 struct drm_i915_private *dev_priv = dev->dev_private;
5026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5027 struct intel_encoder *encoder;
5028 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5029
5030 for_each_encoder_on_crtc(dev, crtc, encoder) {
5031 intel_opregion_notify_encoder(encoder, false);
5032 encoder->disable(encoder);
5033 }
5034
5035 drm_crtc_vblank_off(crtc);
5036 assert_vblank_disabled(crtc);
5037
5038 if (intel_crtc->config->has_pch_encoder)
5039 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5040 false);
5041 intel_disable_pipe(intel_crtc);
5042
5043 if (intel_crtc->config->dp_encoder_is_mst)
5044 intel_ddi_set_vc_payload_alloc(crtc, false);
5045
5046 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5047
5048 if (INTEL_INFO(dev)->gen == 9)
5049 skylake_pfit_update(intel_crtc, 0);
5050 else if (INTEL_INFO(dev)->gen < 9)
5051 ironlake_pfit_disable(intel_crtc);
5052 else
5053 MISSING_CASE(INTEL_INFO(dev)->gen);
5054
5055 intel_ddi_disable_pipe_clock(intel_crtc);
5056
5057 if (intel_crtc->config->has_pch_encoder) {
5058 lpt_disable_pch_transcoder(dev_priv);
5059 intel_ddi_fdi_disable(crtc);
5060 }
5061
5062 for_each_encoder_on_crtc(dev, crtc, encoder)
5063 if (encoder->post_disable)
5064 encoder->post_disable(encoder);
5065 }
5066
5067 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5068 {
5069 struct drm_device *dev = crtc->base.dev;
5070 struct drm_i915_private *dev_priv = dev->dev_private;
5071 struct intel_crtc_state *pipe_config = crtc->config;
5072
5073 if (!pipe_config->gmch_pfit.control)
5074 return;
5075
5076 /*
5077 * The panel fitter should only be adjusted whilst the pipe is disabled,
5078 * according to register description and PRM.
5079 */
5080 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5081 assert_pipe_disabled(dev_priv, crtc->pipe);
5082
5083 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5084 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5085
5086 /* Border color in case we don't scale up to the full screen. Black by
5087 * default, change to something else for debugging. */
5088 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5089 }
5090
5091 static enum intel_display_power_domain port_to_power_domain(enum port port)
5092 {
5093 switch (port) {
5094 case PORT_A:
5095 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5096 case PORT_B:
5097 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5098 case PORT_C:
5099 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5100 case PORT_D:
5101 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5102 default:
5103 WARN_ON_ONCE(1);
5104 return POWER_DOMAIN_PORT_OTHER;
5105 }
5106 }
5107
5108 #define for_each_power_domain(domain, mask) \
5109 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5110 if ((1 << (domain)) & (mask))
5111
5112 enum intel_display_power_domain
5113 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5114 {
5115 struct drm_device *dev = intel_encoder->base.dev;
5116 struct intel_digital_port *intel_dig_port;
5117
5118 switch (intel_encoder->type) {
5119 case INTEL_OUTPUT_UNKNOWN:
5120 /* Only DDI platforms should ever use this output type */
5121 WARN_ON_ONCE(!HAS_DDI(dev));
5122 case INTEL_OUTPUT_DISPLAYPORT:
5123 case INTEL_OUTPUT_HDMI:
5124 case INTEL_OUTPUT_EDP:
5125 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5126 return port_to_power_domain(intel_dig_port->port);
5127 case INTEL_OUTPUT_DP_MST:
5128 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5129 return port_to_power_domain(intel_dig_port->port);
5130 case INTEL_OUTPUT_ANALOG:
5131 return POWER_DOMAIN_PORT_CRT;
5132 case INTEL_OUTPUT_DSI:
5133 return POWER_DOMAIN_PORT_DSI;
5134 default:
5135 return POWER_DOMAIN_PORT_OTHER;
5136 }
5137 }
5138
5139 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5140 {
5141 struct drm_device *dev = crtc->dev;
5142 struct intel_encoder *intel_encoder;
5143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5144 enum pipe pipe = intel_crtc->pipe;
5145 unsigned long mask;
5146 enum transcoder transcoder;
5147
5148 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5149
5150 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5151 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5152 if (intel_crtc->config->pch_pfit.enabled ||
5153 intel_crtc->config->pch_pfit.force_thru)
5154 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5155
5156 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5157 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5158
5159 return mask;
5160 }
5161
5162 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5163 {
5164 struct drm_device *dev = state->dev;
5165 struct drm_i915_private *dev_priv = dev->dev_private;
5166 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5167 struct intel_crtc *crtc;
5168
5169 /*
5170 * First get all needed power domains, then put all unneeded, to avoid
5171 * any unnecessary toggling of the power wells.
5172 */
5173 for_each_intel_crtc(dev, crtc) {
5174 enum intel_display_power_domain domain;
5175
5176 if (!crtc->base.state->enable)
5177 continue;
5178
5179 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5180
5181 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5182 intel_display_power_get(dev_priv, domain);
5183 }
5184
5185 if (dev_priv->display.modeset_commit_cdclk) {
5186 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5187
5188 if (cdclk != dev_priv->cdclk_freq &&
5189 !WARN_ON(!state->allow_modeset))
5190 dev_priv->display.modeset_commit_cdclk(state);
5191 }
5192
5193 for_each_intel_crtc(dev, crtc) {
5194 enum intel_display_power_domain domain;
5195
5196 for_each_power_domain(domain, crtc->enabled_power_domains)
5197 intel_display_power_put(dev_priv, domain);
5198
5199 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5200 }
5201
5202 intel_display_set_init_power(dev_priv, false);
5203 }
5204
5205 static void intel_update_max_cdclk(struct drm_device *dev)
5206 {
5207 struct drm_i915_private *dev_priv = dev->dev_private;
5208
5209 if (IS_SKYLAKE(dev)) {
5210 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5211
5212 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5213 dev_priv->max_cdclk_freq = 675000;
5214 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5215 dev_priv->max_cdclk_freq = 540000;
5216 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5217 dev_priv->max_cdclk_freq = 450000;
5218 else
5219 dev_priv->max_cdclk_freq = 337500;
5220 } else if (IS_BROADWELL(dev)) {
5221 /*
5222 * FIXME with extra cooling we can allow
5223 * 540 MHz for ULX and 675 Mhz for ULT.
5224 * How can we know if extra cooling is
5225 * available? PCI ID, VTB, something else?
5226 */
5227 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5228 dev_priv->max_cdclk_freq = 450000;
5229 else if (IS_BDW_ULX(dev))
5230 dev_priv->max_cdclk_freq = 450000;
5231 else if (IS_BDW_ULT(dev))
5232 dev_priv->max_cdclk_freq = 540000;
5233 else
5234 dev_priv->max_cdclk_freq = 675000;
5235 } else if (IS_CHERRYVIEW(dev)) {
5236 dev_priv->max_cdclk_freq = 320000;
5237 } else if (IS_VALLEYVIEW(dev)) {
5238 dev_priv->max_cdclk_freq = 400000;
5239 } else {
5240 /* otherwise assume cdclk is fixed */
5241 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5242 }
5243
5244 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5245 dev_priv->max_cdclk_freq);
5246 }
5247
5248 static void intel_update_cdclk(struct drm_device *dev)
5249 {
5250 struct drm_i915_private *dev_priv = dev->dev_private;
5251
5252 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5253 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5254 dev_priv->cdclk_freq);
5255
5256 /*
5257 * Program the gmbus_freq based on the cdclk frequency.
5258 * BSpec erroneously claims we should aim for 4MHz, but
5259 * in fact 1MHz is the correct frequency.
5260 */
5261 if (IS_VALLEYVIEW(dev)) {
5262 /*
5263 * Program the gmbus_freq based on the cdclk frequency.
5264 * BSpec erroneously claims we should aim for 4MHz, but
5265 * in fact 1MHz is the correct frequency.
5266 */
5267 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5268 }
5269
5270 if (dev_priv->max_cdclk_freq == 0)
5271 intel_update_max_cdclk(dev);
5272 }
5273
5274 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5275 {
5276 struct drm_i915_private *dev_priv = dev->dev_private;
5277 uint32_t divider;
5278 uint32_t ratio;
5279 uint32_t current_freq;
5280 int ret;
5281
5282 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5283 switch (frequency) {
5284 case 144000:
5285 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5286 ratio = BXT_DE_PLL_RATIO(60);
5287 break;
5288 case 288000:
5289 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5290 ratio = BXT_DE_PLL_RATIO(60);
5291 break;
5292 case 384000:
5293 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5294 ratio = BXT_DE_PLL_RATIO(60);
5295 break;
5296 case 576000:
5297 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5298 ratio = BXT_DE_PLL_RATIO(60);
5299 break;
5300 case 624000:
5301 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5302 ratio = BXT_DE_PLL_RATIO(65);
5303 break;
5304 case 19200:
5305 /*
5306 * Bypass frequency with DE PLL disabled. Init ratio, divider
5307 * to suppress GCC warning.
5308 */
5309 ratio = 0;
5310 divider = 0;
5311 break;
5312 default:
5313 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5314
5315 return;
5316 }
5317
5318 mutex_lock(&dev_priv->rps.hw_lock);
5319 /* Inform power controller of upcoming frequency change */
5320 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5321 0x80000000);
5322 mutex_unlock(&dev_priv->rps.hw_lock);
5323
5324 if (ret) {
5325 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5326 ret, frequency);
5327 return;
5328 }
5329
5330 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5331 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5332 current_freq = current_freq * 500 + 1000;
5333
5334 /*
5335 * DE PLL has to be disabled when
5336 * - setting to 19.2MHz (bypass, PLL isn't used)
5337 * - before setting to 624MHz (PLL needs toggling)
5338 * - before setting to any frequency from 624MHz (PLL needs toggling)
5339 */
5340 if (frequency == 19200 || frequency == 624000 ||
5341 current_freq == 624000) {
5342 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5343 /* Timeout 200us */
5344 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5345 1))
5346 DRM_ERROR("timout waiting for DE PLL unlock\n");
5347 }
5348
5349 if (frequency != 19200) {
5350 uint32_t val;
5351
5352 val = I915_READ(BXT_DE_PLL_CTL);
5353 val &= ~BXT_DE_PLL_RATIO_MASK;
5354 val |= ratio;
5355 I915_WRITE(BXT_DE_PLL_CTL, val);
5356
5357 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5358 /* Timeout 200us */
5359 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5360 DRM_ERROR("timeout waiting for DE PLL lock\n");
5361
5362 val = I915_READ(CDCLK_CTL);
5363 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5364 val |= divider;
5365 /*
5366 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5367 * enable otherwise.
5368 */
5369 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5370 if (frequency >= 500000)
5371 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5372
5373 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5374 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5375 val |= (frequency - 1000) / 500;
5376 I915_WRITE(CDCLK_CTL, val);
5377 }
5378
5379 mutex_lock(&dev_priv->rps.hw_lock);
5380 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5381 DIV_ROUND_UP(frequency, 25000));
5382 mutex_unlock(&dev_priv->rps.hw_lock);
5383
5384 if (ret) {
5385 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5386 ret, frequency);
5387 return;
5388 }
5389
5390 intel_update_cdclk(dev);
5391 }
5392
5393 void broxton_init_cdclk(struct drm_device *dev)
5394 {
5395 struct drm_i915_private *dev_priv = dev->dev_private;
5396 uint32_t val;
5397
5398 /*
5399 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5400 * or else the reset will hang because there is no PCH to respond.
5401 * Move the handshake programming to initialization sequence.
5402 * Previously was left up to BIOS.
5403 */
5404 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5405 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5406 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5407
5408 /* Enable PG1 for cdclk */
5409 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5410
5411 /* check if cd clock is enabled */
5412 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5413 DRM_DEBUG_KMS("Display already initialized\n");
5414 return;
5415 }
5416
5417 /*
5418 * FIXME:
5419 * - The initial CDCLK needs to be read from VBT.
5420 * Need to make this change after VBT has changes for BXT.
5421 * - check if setting the max (or any) cdclk freq is really necessary
5422 * here, it belongs to modeset time
5423 */
5424 broxton_set_cdclk(dev, 624000);
5425
5426 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5427 POSTING_READ(DBUF_CTL);
5428
5429 udelay(10);
5430
5431 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5432 DRM_ERROR("DBuf power enable timeout!\n");
5433 }
5434
5435 void broxton_uninit_cdclk(struct drm_device *dev)
5436 {
5437 struct drm_i915_private *dev_priv = dev->dev_private;
5438
5439 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5440 POSTING_READ(DBUF_CTL);
5441
5442 udelay(10);
5443
5444 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5445 DRM_ERROR("DBuf power disable timeout!\n");
5446
5447 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5448 broxton_set_cdclk(dev, 19200);
5449
5450 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5451 }
5452
5453 static const struct skl_cdclk_entry {
5454 unsigned int freq;
5455 unsigned int vco;
5456 } skl_cdclk_frequencies[] = {
5457 { .freq = 308570, .vco = 8640 },
5458 { .freq = 337500, .vco = 8100 },
5459 { .freq = 432000, .vco = 8640 },
5460 { .freq = 450000, .vco = 8100 },
5461 { .freq = 540000, .vco = 8100 },
5462 { .freq = 617140, .vco = 8640 },
5463 { .freq = 675000, .vco = 8100 },
5464 };
5465
5466 static unsigned int skl_cdclk_decimal(unsigned int freq)
5467 {
5468 return (freq - 1000) / 500;
5469 }
5470
5471 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5472 {
5473 unsigned int i;
5474
5475 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5476 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5477
5478 if (e->freq == freq)
5479 return e->vco;
5480 }
5481
5482 return 8100;
5483 }
5484
5485 static void
5486 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5487 {
5488 unsigned int min_freq;
5489 u32 val;
5490
5491 /* select the minimum CDCLK before enabling DPLL 0 */
5492 val = I915_READ(CDCLK_CTL);
5493 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5494 val |= CDCLK_FREQ_337_308;
5495
5496 if (required_vco == 8640)
5497 min_freq = 308570;
5498 else
5499 min_freq = 337500;
5500
5501 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5502
5503 I915_WRITE(CDCLK_CTL, val);
5504 POSTING_READ(CDCLK_CTL);
5505
5506 /*
5507 * We always enable DPLL0 with the lowest link rate possible, but still
5508 * taking into account the VCO required to operate the eDP panel at the
5509 * desired frequency. The usual DP link rates operate with a VCO of
5510 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5511 * The modeset code is responsible for the selection of the exact link
5512 * rate later on, with the constraint of choosing a frequency that
5513 * works with required_vco.
5514 */
5515 val = I915_READ(DPLL_CTRL1);
5516
5517 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5518 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5519 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5520 if (required_vco == 8640)
5521 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5522 SKL_DPLL0);
5523 else
5524 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5525 SKL_DPLL0);
5526
5527 I915_WRITE(DPLL_CTRL1, val);
5528 POSTING_READ(DPLL_CTRL1);
5529
5530 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5531
5532 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5533 DRM_ERROR("DPLL0 not locked\n");
5534 }
5535
5536 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5537 {
5538 int ret;
5539 u32 val;
5540
5541 /* inform PCU we want to change CDCLK */
5542 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5543 mutex_lock(&dev_priv->rps.hw_lock);
5544 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5545 mutex_unlock(&dev_priv->rps.hw_lock);
5546
5547 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5548 }
5549
5550 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5551 {
5552 unsigned int i;
5553
5554 for (i = 0; i < 15; i++) {
5555 if (skl_cdclk_pcu_ready(dev_priv))
5556 return true;
5557 udelay(10);
5558 }
5559
5560 return false;
5561 }
5562
5563 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5564 {
5565 struct drm_device *dev = dev_priv->dev;
5566 u32 freq_select, pcu_ack;
5567
5568 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5569
5570 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5571 DRM_ERROR("failed to inform PCU about cdclk change\n");
5572 return;
5573 }
5574
5575 /* set CDCLK_CTL */
5576 switch(freq) {
5577 case 450000:
5578 case 432000:
5579 freq_select = CDCLK_FREQ_450_432;
5580 pcu_ack = 1;
5581 break;
5582 case 540000:
5583 freq_select = CDCLK_FREQ_540;
5584 pcu_ack = 2;
5585 break;
5586 case 308570:
5587 case 337500:
5588 default:
5589 freq_select = CDCLK_FREQ_337_308;
5590 pcu_ack = 0;
5591 break;
5592 case 617140:
5593 case 675000:
5594 freq_select = CDCLK_FREQ_675_617;
5595 pcu_ack = 3;
5596 break;
5597 }
5598
5599 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5600 POSTING_READ(CDCLK_CTL);
5601
5602 /* inform PCU of the change */
5603 mutex_lock(&dev_priv->rps.hw_lock);
5604 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5605 mutex_unlock(&dev_priv->rps.hw_lock);
5606
5607 intel_update_cdclk(dev);
5608 }
5609
5610 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5611 {
5612 /* disable DBUF power */
5613 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5614 POSTING_READ(DBUF_CTL);
5615
5616 udelay(10);
5617
5618 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5619 DRM_ERROR("DBuf power disable timeout\n");
5620
5621 /* disable DPLL0 */
5622 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5623 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5624 DRM_ERROR("Couldn't disable DPLL0\n");
5625
5626 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5627 }
5628
5629 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5630 {
5631 u32 val;
5632 unsigned int required_vco;
5633
5634 /* enable PCH reset handshake */
5635 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5636 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5637
5638 /* enable PG1 and Misc I/O */
5639 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5640
5641 /* DPLL0 already enabed !? */
5642 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5643 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5644 return;
5645 }
5646
5647 /* enable DPLL0 */
5648 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5649 skl_dpll0_enable(dev_priv, required_vco);
5650
5651 /* set CDCLK to the frequency the BIOS chose */
5652 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5653
5654 /* enable DBUF power */
5655 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5656 POSTING_READ(DBUF_CTL);
5657
5658 udelay(10);
5659
5660 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5661 DRM_ERROR("DBuf power enable timeout\n");
5662 }
5663
5664 /* returns HPLL frequency in kHz */
5665 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5666 {
5667 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5668
5669 /* Obtain SKU information */
5670 mutex_lock(&dev_priv->sb_lock);
5671 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5672 CCK_FUSE_HPLL_FREQ_MASK;
5673 mutex_unlock(&dev_priv->sb_lock);
5674
5675 return vco_freq[hpll_freq] * 1000;
5676 }
5677
5678 /* Adjust CDclk dividers to allow high res or save power if possible */
5679 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5680 {
5681 struct drm_i915_private *dev_priv = dev->dev_private;
5682 u32 val, cmd;
5683
5684 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5685 != dev_priv->cdclk_freq);
5686
5687 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5688 cmd = 2;
5689 else if (cdclk == 266667)
5690 cmd = 1;
5691 else
5692 cmd = 0;
5693
5694 mutex_lock(&dev_priv->rps.hw_lock);
5695 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5696 val &= ~DSPFREQGUAR_MASK;
5697 val |= (cmd << DSPFREQGUAR_SHIFT);
5698 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5699 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5700 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5701 50)) {
5702 DRM_ERROR("timed out waiting for CDclk change\n");
5703 }
5704 mutex_unlock(&dev_priv->rps.hw_lock);
5705
5706 mutex_lock(&dev_priv->sb_lock);
5707
5708 if (cdclk == 400000) {
5709 u32 divider;
5710
5711 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5712
5713 /* adjust cdclk divider */
5714 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5715 val &= ~DISPLAY_FREQUENCY_VALUES;
5716 val |= divider;
5717 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5718
5719 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5720 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5721 50))
5722 DRM_ERROR("timed out waiting for CDclk change\n");
5723 }
5724
5725 /* adjust self-refresh exit latency value */
5726 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5727 val &= ~0x7f;
5728
5729 /*
5730 * For high bandwidth configs, we set a higher latency in the bunit
5731 * so that the core display fetch happens in time to avoid underruns.
5732 */
5733 if (cdclk == 400000)
5734 val |= 4500 / 250; /* 4.5 usec */
5735 else
5736 val |= 3000 / 250; /* 3.0 usec */
5737 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5738
5739 mutex_unlock(&dev_priv->sb_lock);
5740
5741 intel_update_cdclk(dev);
5742 }
5743
5744 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5745 {
5746 struct drm_i915_private *dev_priv = dev->dev_private;
5747 u32 val, cmd;
5748
5749 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5750 != dev_priv->cdclk_freq);
5751
5752 switch (cdclk) {
5753 case 333333:
5754 case 320000:
5755 case 266667:
5756 case 200000:
5757 break;
5758 default:
5759 MISSING_CASE(cdclk);
5760 return;
5761 }
5762
5763 /*
5764 * Specs are full of misinformation, but testing on actual
5765 * hardware has shown that we just need to write the desired
5766 * CCK divider into the Punit register.
5767 */
5768 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5769
5770 mutex_lock(&dev_priv->rps.hw_lock);
5771 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5772 val &= ~DSPFREQGUAR_MASK_CHV;
5773 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5774 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5775 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5776 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5777 50)) {
5778 DRM_ERROR("timed out waiting for CDclk change\n");
5779 }
5780 mutex_unlock(&dev_priv->rps.hw_lock);
5781
5782 intel_update_cdclk(dev);
5783 }
5784
5785 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5786 int max_pixclk)
5787 {
5788 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5789 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5790
5791 /*
5792 * Really only a few cases to deal with, as only 4 CDclks are supported:
5793 * 200MHz
5794 * 267MHz
5795 * 320/333MHz (depends on HPLL freq)
5796 * 400MHz (VLV only)
5797 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5798 * of the lower bin and adjust if needed.
5799 *
5800 * We seem to get an unstable or solid color picture at 200MHz.
5801 * Not sure what's wrong. For now use 200MHz only when all pipes
5802 * are off.
5803 */
5804 if (!IS_CHERRYVIEW(dev_priv) &&
5805 max_pixclk > freq_320*limit/100)
5806 return 400000;
5807 else if (max_pixclk > 266667*limit/100)
5808 return freq_320;
5809 else if (max_pixclk > 0)
5810 return 266667;
5811 else
5812 return 200000;
5813 }
5814
5815 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5816 int max_pixclk)
5817 {
5818 /*
5819 * FIXME:
5820 * - remove the guardband, it's not needed on BXT
5821 * - set 19.2MHz bypass frequency if there are no active pipes
5822 */
5823 if (max_pixclk > 576000*9/10)
5824 return 624000;
5825 else if (max_pixclk > 384000*9/10)
5826 return 576000;
5827 else if (max_pixclk > 288000*9/10)
5828 return 384000;
5829 else if (max_pixclk > 144000*9/10)
5830 return 288000;
5831 else
5832 return 144000;
5833 }
5834
5835 /* Compute the max pixel clock for new configuration. Uses atomic state if
5836 * that's non-NULL, look at current state otherwise. */
5837 static int intel_mode_max_pixclk(struct drm_device *dev,
5838 struct drm_atomic_state *state)
5839 {
5840 struct intel_crtc *intel_crtc;
5841 struct intel_crtc_state *crtc_state;
5842 int max_pixclk = 0;
5843
5844 for_each_intel_crtc(dev, intel_crtc) {
5845 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5846 if (IS_ERR(crtc_state))
5847 return PTR_ERR(crtc_state);
5848
5849 if (!crtc_state->base.enable)
5850 continue;
5851
5852 max_pixclk = max(max_pixclk,
5853 crtc_state->base.adjusted_mode.crtc_clock);
5854 }
5855
5856 return max_pixclk;
5857 }
5858
5859 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5860 {
5861 struct drm_device *dev = state->dev;
5862 struct drm_i915_private *dev_priv = dev->dev_private;
5863 int max_pixclk = intel_mode_max_pixclk(dev, state);
5864
5865 if (max_pixclk < 0)
5866 return max_pixclk;
5867
5868 to_intel_atomic_state(state)->cdclk =
5869 valleyview_calc_cdclk(dev_priv, max_pixclk);
5870
5871 return 0;
5872 }
5873
5874 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5875 {
5876 struct drm_device *dev = state->dev;
5877 struct drm_i915_private *dev_priv = dev->dev_private;
5878 int max_pixclk = intel_mode_max_pixclk(dev, state);
5879
5880 if (max_pixclk < 0)
5881 return max_pixclk;
5882
5883 to_intel_atomic_state(state)->cdclk =
5884 broxton_calc_cdclk(dev_priv, max_pixclk);
5885
5886 return 0;
5887 }
5888
5889 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5890 {
5891 unsigned int credits, default_credits;
5892
5893 if (IS_CHERRYVIEW(dev_priv))
5894 default_credits = PFI_CREDIT(12);
5895 else
5896 default_credits = PFI_CREDIT(8);
5897
5898 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5899 /* CHV suggested value is 31 or 63 */
5900 if (IS_CHERRYVIEW(dev_priv))
5901 credits = PFI_CREDIT_63;
5902 else
5903 credits = PFI_CREDIT(15);
5904 } else {
5905 credits = default_credits;
5906 }
5907
5908 /*
5909 * WA - write default credits before re-programming
5910 * FIXME: should we also set the resend bit here?
5911 */
5912 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5913 default_credits);
5914
5915 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5916 credits | PFI_CREDIT_RESEND);
5917
5918 /*
5919 * FIXME is this guaranteed to clear
5920 * immediately or should we poll for it?
5921 */
5922 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5923 }
5924
5925 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5926 {
5927 struct drm_device *dev = old_state->dev;
5928 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5929 struct drm_i915_private *dev_priv = dev->dev_private;
5930
5931 /*
5932 * FIXME: We can end up here with all power domains off, yet
5933 * with a CDCLK frequency other than the minimum. To account
5934 * for this take the PIPE-A power domain, which covers the HW
5935 * blocks needed for the following programming. This can be
5936 * removed once it's guaranteed that we get here either with
5937 * the minimum CDCLK set, or the required power domains
5938 * enabled.
5939 */
5940 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5941
5942 if (IS_CHERRYVIEW(dev))
5943 cherryview_set_cdclk(dev, req_cdclk);
5944 else
5945 valleyview_set_cdclk(dev, req_cdclk);
5946
5947 vlv_program_pfi_credits(dev_priv);
5948
5949 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5950 }
5951
5952 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5953 {
5954 struct drm_device *dev = crtc->dev;
5955 struct drm_i915_private *dev_priv = to_i915(dev);
5956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5957 struct intel_encoder *encoder;
5958 int pipe = intel_crtc->pipe;
5959 bool is_dsi;
5960
5961 if (WARN_ON(intel_crtc->active))
5962 return;
5963
5964 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5965
5966 if (!is_dsi) {
5967 if (IS_CHERRYVIEW(dev))
5968 chv_prepare_pll(intel_crtc, intel_crtc->config);
5969 else
5970 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5971 }
5972
5973 if (intel_crtc->config->has_dp_encoder)
5974 intel_dp_set_m_n(intel_crtc, M1_N1);
5975
5976 intel_set_pipe_timings(intel_crtc);
5977
5978 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5979 struct drm_i915_private *dev_priv = dev->dev_private;
5980
5981 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5982 I915_WRITE(CHV_CANVAS(pipe), 0);
5983 }
5984
5985 i9xx_set_pipeconf(intel_crtc);
5986
5987 intel_crtc->active = true;
5988
5989 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5990
5991 for_each_encoder_on_crtc(dev, crtc, encoder)
5992 if (encoder->pre_pll_enable)
5993 encoder->pre_pll_enable(encoder);
5994
5995 if (!is_dsi) {
5996 if (IS_CHERRYVIEW(dev))
5997 chv_enable_pll(intel_crtc, intel_crtc->config);
5998 else
5999 vlv_enable_pll(intel_crtc, intel_crtc->config);
6000 }
6001
6002 for_each_encoder_on_crtc(dev, crtc, encoder)
6003 if (encoder->pre_enable)
6004 encoder->pre_enable(encoder);
6005
6006 i9xx_pfit_enable(intel_crtc);
6007
6008 intel_crtc_load_lut(crtc);
6009
6010 intel_update_watermarks(crtc);
6011 intel_enable_pipe(intel_crtc);
6012
6013 assert_vblank_disabled(crtc);
6014 drm_crtc_vblank_on(crtc);
6015
6016 for_each_encoder_on_crtc(dev, crtc, encoder)
6017 encoder->enable(encoder);
6018 }
6019
6020 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6021 {
6022 struct drm_device *dev = crtc->base.dev;
6023 struct drm_i915_private *dev_priv = dev->dev_private;
6024
6025 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6026 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6027 }
6028
6029 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6030 {
6031 struct drm_device *dev = crtc->dev;
6032 struct drm_i915_private *dev_priv = to_i915(dev);
6033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6034 struct intel_encoder *encoder;
6035 int pipe = intel_crtc->pipe;
6036
6037 if (WARN_ON(intel_crtc->active))
6038 return;
6039
6040 i9xx_set_pll_dividers(intel_crtc);
6041
6042 if (intel_crtc->config->has_dp_encoder)
6043 intel_dp_set_m_n(intel_crtc, M1_N1);
6044
6045 intel_set_pipe_timings(intel_crtc);
6046
6047 i9xx_set_pipeconf(intel_crtc);
6048
6049 intel_crtc->active = true;
6050
6051 if (!IS_GEN2(dev))
6052 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6053
6054 for_each_encoder_on_crtc(dev, crtc, encoder)
6055 if (encoder->pre_enable)
6056 encoder->pre_enable(encoder);
6057
6058 i9xx_enable_pll(intel_crtc);
6059
6060 i9xx_pfit_enable(intel_crtc);
6061
6062 intel_crtc_load_lut(crtc);
6063
6064 intel_update_watermarks(crtc);
6065 intel_enable_pipe(intel_crtc);
6066
6067 assert_vblank_disabled(crtc);
6068 drm_crtc_vblank_on(crtc);
6069
6070 for_each_encoder_on_crtc(dev, crtc, encoder)
6071 encoder->enable(encoder);
6072 }
6073
6074 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6075 {
6076 struct drm_device *dev = crtc->base.dev;
6077 struct drm_i915_private *dev_priv = dev->dev_private;
6078
6079 if (!crtc->config->gmch_pfit.control)
6080 return;
6081
6082 assert_pipe_disabled(dev_priv, crtc->pipe);
6083
6084 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6085 I915_READ(PFIT_CONTROL));
6086 I915_WRITE(PFIT_CONTROL, 0);
6087 }
6088
6089 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6090 {
6091 struct drm_device *dev = crtc->dev;
6092 struct drm_i915_private *dev_priv = dev->dev_private;
6093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6094 struct intel_encoder *encoder;
6095 int pipe = intel_crtc->pipe;
6096
6097 /*
6098 * On gen2 planes are double buffered but the pipe isn't, so we must
6099 * wait for planes to fully turn off before disabling the pipe.
6100 * We also need to wait on all gmch platforms because of the
6101 * self-refresh mode constraint explained above.
6102 */
6103 intel_wait_for_vblank(dev, pipe);
6104
6105 for_each_encoder_on_crtc(dev, crtc, encoder)
6106 encoder->disable(encoder);
6107
6108 drm_crtc_vblank_off(crtc);
6109 assert_vblank_disabled(crtc);
6110
6111 intel_disable_pipe(intel_crtc);
6112
6113 i9xx_pfit_disable(intel_crtc);
6114
6115 for_each_encoder_on_crtc(dev, crtc, encoder)
6116 if (encoder->post_disable)
6117 encoder->post_disable(encoder);
6118
6119 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6120 if (IS_CHERRYVIEW(dev))
6121 chv_disable_pll(dev_priv, pipe);
6122 else if (IS_VALLEYVIEW(dev))
6123 vlv_disable_pll(dev_priv, pipe);
6124 else
6125 i9xx_disable_pll(intel_crtc);
6126 }
6127
6128 if (!IS_GEN2(dev))
6129 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6130 }
6131
6132 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6133 {
6134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6135 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6136 enum intel_display_power_domain domain;
6137 unsigned long domains;
6138
6139 if (!intel_crtc->active)
6140 return;
6141
6142 if (to_intel_plane_state(crtc->primary->state)->visible) {
6143 intel_crtc_wait_for_pending_flips(crtc);
6144 intel_pre_disable_primary(crtc);
6145 }
6146
6147 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6148 dev_priv->display.crtc_disable(crtc);
6149
6150 domains = intel_crtc->enabled_power_domains;
6151 for_each_power_domain(domain, domains)
6152 intel_display_power_put(dev_priv, domain);
6153 intel_crtc->enabled_power_domains = 0;
6154 }
6155
6156 /*
6157 * turn all crtc's off, but do not adjust state
6158 * This has to be paired with a call to intel_modeset_setup_hw_state.
6159 */
6160 void intel_display_suspend(struct drm_device *dev)
6161 {
6162 struct drm_crtc *crtc;
6163
6164 for_each_crtc(dev, crtc)
6165 intel_crtc_disable_noatomic(crtc);
6166 }
6167
6168 /* Master function to enable/disable CRTC and corresponding power wells */
6169 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6170 {
6171 struct drm_device *dev = crtc->dev;
6172 struct drm_mode_config *config = &dev->mode_config;
6173 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6175 struct intel_crtc_state *pipe_config;
6176 struct drm_atomic_state *state;
6177 int ret;
6178
6179 if (enable == intel_crtc->active)
6180 return 0;
6181
6182 if (enable && !crtc->state->enable)
6183 return 0;
6184
6185 /* this function should be called with drm_modeset_lock_all for now */
6186 if (WARN_ON(!ctx))
6187 return -EIO;
6188 lockdep_assert_held(&ctx->ww_ctx);
6189
6190 state = drm_atomic_state_alloc(dev);
6191 if (WARN_ON(!state))
6192 return -ENOMEM;
6193
6194 state->acquire_ctx = ctx;
6195 state->allow_modeset = true;
6196
6197 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6198 if (IS_ERR(pipe_config)) {
6199 ret = PTR_ERR(pipe_config);
6200 goto err;
6201 }
6202 pipe_config->base.active = enable;
6203
6204 ret = intel_set_mode(state);
6205 if (!ret)
6206 return ret;
6207
6208 err:
6209 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6210 drm_atomic_state_free(state);
6211 return ret;
6212 }
6213
6214 /**
6215 * Sets the power management mode of the pipe and plane.
6216 */
6217 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6218 {
6219 struct drm_device *dev = crtc->dev;
6220 struct intel_encoder *intel_encoder;
6221 bool enable = false;
6222
6223 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6224 enable |= intel_encoder->connectors_active;
6225
6226 intel_crtc_control(crtc, enable);
6227 }
6228
6229 void intel_encoder_destroy(struct drm_encoder *encoder)
6230 {
6231 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6232
6233 drm_encoder_cleanup(encoder);
6234 kfree(intel_encoder);
6235 }
6236
6237 /* Simple dpms helper for encoders with just one connector, no cloning and only
6238 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6239 * state of the entire output pipe. */
6240 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6241 {
6242 if (mode == DRM_MODE_DPMS_ON) {
6243 encoder->connectors_active = true;
6244
6245 intel_crtc_update_dpms(encoder->base.crtc);
6246 } else {
6247 encoder->connectors_active = false;
6248
6249 intel_crtc_update_dpms(encoder->base.crtc);
6250 }
6251 }
6252
6253 /* Cross check the actual hw state with our own modeset state tracking (and it's
6254 * internal consistency). */
6255 static void intel_connector_check_state(struct intel_connector *connector)
6256 {
6257 if (connector->get_hw_state(connector)) {
6258 struct intel_encoder *encoder = connector->encoder;
6259 struct drm_crtc *crtc;
6260 bool encoder_enabled;
6261 enum pipe pipe;
6262
6263 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6264 connector->base.base.id,
6265 connector->base.name);
6266
6267 /* there is no real hw state for MST connectors */
6268 if (connector->mst_port)
6269 return;
6270
6271 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6272 "wrong connector dpms state\n");
6273 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6274 "active connector not linked to encoder\n");
6275
6276 if (encoder) {
6277 I915_STATE_WARN(!encoder->connectors_active,
6278 "encoder->connectors_active not set\n");
6279
6280 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6281 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6282 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6283 return;
6284
6285 crtc = encoder->base.crtc;
6286
6287 I915_STATE_WARN(!crtc->state->enable,
6288 "crtc not enabled\n");
6289 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6290 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6291 "encoder active on the wrong pipe\n");
6292 }
6293 }
6294 }
6295
6296 int intel_connector_init(struct intel_connector *connector)
6297 {
6298 struct drm_connector_state *connector_state;
6299
6300 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6301 if (!connector_state)
6302 return -ENOMEM;
6303
6304 connector->base.state = connector_state;
6305 return 0;
6306 }
6307
6308 struct intel_connector *intel_connector_alloc(void)
6309 {
6310 struct intel_connector *connector;
6311
6312 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6313 if (!connector)
6314 return NULL;
6315
6316 if (intel_connector_init(connector) < 0) {
6317 kfree(connector);
6318 return NULL;
6319 }
6320
6321 return connector;
6322 }
6323
6324 /* Even simpler default implementation, if there's really no special case to
6325 * consider. */
6326 void intel_connector_dpms(struct drm_connector *connector, int mode)
6327 {
6328 /* All the simple cases only support two dpms states. */
6329 if (mode != DRM_MODE_DPMS_ON)
6330 mode = DRM_MODE_DPMS_OFF;
6331
6332 if (mode == connector->dpms)
6333 return;
6334
6335 connector->dpms = mode;
6336
6337 /* Only need to change hw state when actually enabled */
6338 if (connector->encoder)
6339 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6340
6341 intel_modeset_check_state(connector->dev);
6342 }
6343
6344 /* Simple connector->get_hw_state implementation for encoders that support only
6345 * one connector and no cloning and hence the encoder state determines the state
6346 * of the connector. */
6347 bool intel_connector_get_hw_state(struct intel_connector *connector)
6348 {
6349 enum pipe pipe = 0;
6350 struct intel_encoder *encoder = connector->encoder;
6351
6352 return encoder->get_hw_state(encoder, &pipe);
6353 }
6354
6355 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6356 {
6357 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6358 return crtc_state->fdi_lanes;
6359
6360 return 0;
6361 }
6362
6363 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6364 struct intel_crtc_state *pipe_config)
6365 {
6366 struct drm_atomic_state *state = pipe_config->base.state;
6367 struct intel_crtc *other_crtc;
6368 struct intel_crtc_state *other_crtc_state;
6369
6370 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6371 pipe_name(pipe), pipe_config->fdi_lanes);
6372 if (pipe_config->fdi_lanes > 4) {
6373 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6374 pipe_name(pipe), pipe_config->fdi_lanes);
6375 return -EINVAL;
6376 }
6377
6378 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6379 if (pipe_config->fdi_lanes > 2) {
6380 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6381 pipe_config->fdi_lanes);
6382 return -EINVAL;
6383 } else {
6384 return 0;
6385 }
6386 }
6387
6388 if (INTEL_INFO(dev)->num_pipes == 2)
6389 return 0;
6390
6391 /* Ivybridge 3 pipe is really complicated */
6392 switch (pipe) {
6393 case PIPE_A:
6394 return 0;
6395 case PIPE_B:
6396 if (pipe_config->fdi_lanes <= 2)
6397 return 0;
6398
6399 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6400 other_crtc_state =
6401 intel_atomic_get_crtc_state(state, other_crtc);
6402 if (IS_ERR(other_crtc_state))
6403 return PTR_ERR(other_crtc_state);
6404
6405 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6406 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6407 pipe_name(pipe), pipe_config->fdi_lanes);
6408 return -EINVAL;
6409 }
6410 return 0;
6411 case PIPE_C:
6412 if (pipe_config->fdi_lanes > 2) {
6413 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6414 pipe_name(pipe), pipe_config->fdi_lanes);
6415 return -EINVAL;
6416 }
6417
6418 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6419 other_crtc_state =
6420 intel_atomic_get_crtc_state(state, other_crtc);
6421 if (IS_ERR(other_crtc_state))
6422 return PTR_ERR(other_crtc_state);
6423
6424 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6425 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6426 return -EINVAL;
6427 }
6428 return 0;
6429 default:
6430 BUG();
6431 }
6432 }
6433
6434 #define RETRY 1
6435 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6436 struct intel_crtc_state *pipe_config)
6437 {
6438 struct drm_device *dev = intel_crtc->base.dev;
6439 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6440 int lane, link_bw, fdi_dotclock, ret;
6441 bool needs_recompute = false;
6442
6443 retry:
6444 /* FDI is a binary signal running at ~2.7GHz, encoding
6445 * each output octet as 10 bits. The actual frequency
6446 * is stored as a divider into a 100MHz clock, and the
6447 * mode pixel clock is stored in units of 1KHz.
6448 * Hence the bw of each lane in terms of the mode signal
6449 * is:
6450 */
6451 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6452
6453 fdi_dotclock = adjusted_mode->crtc_clock;
6454
6455 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6456 pipe_config->pipe_bpp);
6457
6458 pipe_config->fdi_lanes = lane;
6459
6460 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6461 link_bw, &pipe_config->fdi_m_n);
6462
6463 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6464 intel_crtc->pipe, pipe_config);
6465 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6466 pipe_config->pipe_bpp -= 2*3;
6467 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6468 pipe_config->pipe_bpp);
6469 needs_recompute = true;
6470 pipe_config->bw_constrained = true;
6471
6472 goto retry;
6473 }
6474
6475 if (needs_recompute)
6476 return RETRY;
6477
6478 return ret;
6479 }
6480
6481 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6482 struct intel_crtc_state *pipe_config)
6483 {
6484 if (pipe_config->pipe_bpp > 24)
6485 return false;
6486
6487 /* HSW can handle pixel rate up to cdclk? */
6488 if (IS_HASWELL(dev_priv->dev))
6489 return true;
6490
6491 /*
6492 * We compare against max which means we must take
6493 * the increased cdclk requirement into account when
6494 * calculating the new cdclk.
6495 *
6496 * Should measure whether using a lower cdclk w/o IPS
6497 */
6498 return ilk_pipe_pixel_rate(pipe_config) <=
6499 dev_priv->max_cdclk_freq * 95 / 100;
6500 }
6501
6502 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6503 struct intel_crtc_state *pipe_config)
6504 {
6505 struct drm_device *dev = crtc->base.dev;
6506 struct drm_i915_private *dev_priv = dev->dev_private;
6507
6508 pipe_config->ips_enabled = i915.enable_ips &&
6509 hsw_crtc_supports_ips(crtc) &&
6510 pipe_config_supports_ips(dev_priv, pipe_config);
6511 }
6512
6513 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6514 struct intel_crtc_state *pipe_config)
6515 {
6516 struct drm_device *dev = crtc->base.dev;
6517 struct drm_i915_private *dev_priv = dev->dev_private;
6518 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6519
6520 /* FIXME should check pixel clock limits on all platforms */
6521 if (INTEL_INFO(dev)->gen < 4) {
6522 int clock_limit = dev_priv->max_cdclk_freq;
6523
6524 /*
6525 * Enable pixel doubling when the dot clock
6526 * is > 90% of the (display) core speed.
6527 *
6528 * GDG double wide on either pipe,
6529 * otherwise pipe A only.
6530 */
6531 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6532 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6533 clock_limit *= 2;
6534 pipe_config->double_wide = true;
6535 }
6536
6537 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6538 return -EINVAL;
6539 }
6540
6541 /*
6542 * Pipe horizontal size must be even in:
6543 * - DVO ganged mode
6544 * - LVDS dual channel mode
6545 * - Double wide pipe
6546 */
6547 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6548 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6549 pipe_config->pipe_src_w &= ~1;
6550
6551 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6552 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6553 */
6554 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6555 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6556 return -EINVAL;
6557
6558 if (HAS_IPS(dev))
6559 hsw_compute_ips_config(crtc, pipe_config);
6560
6561 if (pipe_config->has_pch_encoder)
6562 return ironlake_fdi_compute_config(crtc, pipe_config);
6563
6564 return 0;
6565 }
6566
6567 static int skylake_get_display_clock_speed(struct drm_device *dev)
6568 {
6569 struct drm_i915_private *dev_priv = to_i915(dev);
6570 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6571 uint32_t cdctl = I915_READ(CDCLK_CTL);
6572 uint32_t linkrate;
6573
6574 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6575 return 24000; /* 24MHz is the cd freq with NSSC ref */
6576
6577 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6578 return 540000;
6579
6580 linkrate = (I915_READ(DPLL_CTRL1) &
6581 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6582
6583 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6584 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6585 /* vco 8640 */
6586 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6587 case CDCLK_FREQ_450_432:
6588 return 432000;
6589 case CDCLK_FREQ_337_308:
6590 return 308570;
6591 case CDCLK_FREQ_675_617:
6592 return 617140;
6593 default:
6594 WARN(1, "Unknown cd freq selection\n");
6595 }
6596 } else {
6597 /* vco 8100 */
6598 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6599 case CDCLK_FREQ_450_432:
6600 return 450000;
6601 case CDCLK_FREQ_337_308:
6602 return 337500;
6603 case CDCLK_FREQ_675_617:
6604 return 675000;
6605 default:
6606 WARN(1, "Unknown cd freq selection\n");
6607 }
6608 }
6609
6610 /* error case, do as if DPLL0 isn't enabled */
6611 return 24000;
6612 }
6613
6614 static int broxton_get_display_clock_speed(struct drm_device *dev)
6615 {
6616 struct drm_i915_private *dev_priv = to_i915(dev);
6617 uint32_t cdctl = I915_READ(CDCLK_CTL);
6618 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6619 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6620 int cdclk;
6621
6622 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6623 return 19200;
6624
6625 cdclk = 19200 * pll_ratio / 2;
6626
6627 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6628 case BXT_CDCLK_CD2X_DIV_SEL_1:
6629 return cdclk; /* 576MHz or 624MHz */
6630 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6631 return cdclk * 2 / 3; /* 384MHz */
6632 case BXT_CDCLK_CD2X_DIV_SEL_2:
6633 return cdclk / 2; /* 288MHz */
6634 case BXT_CDCLK_CD2X_DIV_SEL_4:
6635 return cdclk / 4; /* 144MHz */
6636 }
6637
6638 /* error case, do as if DE PLL isn't enabled */
6639 return 19200;
6640 }
6641
6642 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6643 {
6644 struct drm_i915_private *dev_priv = dev->dev_private;
6645 uint32_t lcpll = I915_READ(LCPLL_CTL);
6646 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6647
6648 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6649 return 800000;
6650 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6651 return 450000;
6652 else if (freq == LCPLL_CLK_FREQ_450)
6653 return 450000;
6654 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6655 return 540000;
6656 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6657 return 337500;
6658 else
6659 return 675000;
6660 }
6661
6662 static int haswell_get_display_clock_speed(struct drm_device *dev)
6663 {
6664 struct drm_i915_private *dev_priv = dev->dev_private;
6665 uint32_t lcpll = I915_READ(LCPLL_CTL);
6666 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6667
6668 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6669 return 800000;
6670 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6671 return 450000;
6672 else if (freq == LCPLL_CLK_FREQ_450)
6673 return 450000;
6674 else if (IS_HSW_ULT(dev))
6675 return 337500;
6676 else
6677 return 540000;
6678 }
6679
6680 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6681 {
6682 struct drm_i915_private *dev_priv = dev->dev_private;
6683 u32 val;
6684 int divider;
6685
6686 if (dev_priv->hpll_freq == 0)
6687 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6688
6689 mutex_lock(&dev_priv->sb_lock);
6690 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6691 mutex_unlock(&dev_priv->sb_lock);
6692
6693 divider = val & DISPLAY_FREQUENCY_VALUES;
6694
6695 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6696 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6697 "cdclk change in progress\n");
6698
6699 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6700 }
6701
6702 static int ilk_get_display_clock_speed(struct drm_device *dev)
6703 {
6704 return 450000;
6705 }
6706
6707 static int i945_get_display_clock_speed(struct drm_device *dev)
6708 {
6709 return 400000;
6710 }
6711
6712 static int i915_get_display_clock_speed(struct drm_device *dev)
6713 {
6714 return 333333;
6715 }
6716
6717 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6718 {
6719 return 200000;
6720 }
6721
6722 static int pnv_get_display_clock_speed(struct drm_device *dev)
6723 {
6724 u16 gcfgc = 0;
6725
6726 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6727
6728 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6729 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6730 return 266667;
6731 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6732 return 333333;
6733 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6734 return 444444;
6735 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6736 return 200000;
6737 default:
6738 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6739 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6740 return 133333;
6741 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6742 return 166667;
6743 }
6744 }
6745
6746 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6747 {
6748 u16 gcfgc = 0;
6749
6750 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6751
6752 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6753 return 133333;
6754 else {
6755 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6756 case GC_DISPLAY_CLOCK_333_MHZ:
6757 return 333333;
6758 default:
6759 case GC_DISPLAY_CLOCK_190_200_MHZ:
6760 return 190000;
6761 }
6762 }
6763 }
6764
6765 static int i865_get_display_clock_speed(struct drm_device *dev)
6766 {
6767 return 266667;
6768 }
6769
6770 static int i85x_get_display_clock_speed(struct drm_device *dev)
6771 {
6772 u16 hpllcc = 0;
6773
6774 /*
6775 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6776 * encoding is different :(
6777 * FIXME is this the right way to detect 852GM/852GMV?
6778 */
6779 if (dev->pdev->revision == 0x1)
6780 return 133333;
6781
6782 pci_bus_read_config_word(dev->pdev->bus,
6783 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6784
6785 /* Assume that the hardware is in the high speed state. This
6786 * should be the default.
6787 */
6788 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6789 case GC_CLOCK_133_200:
6790 case GC_CLOCK_133_200_2:
6791 case GC_CLOCK_100_200:
6792 return 200000;
6793 case GC_CLOCK_166_250:
6794 return 250000;
6795 case GC_CLOCK_100_133:
6796 return 133333;
6797 case GC_CLOCK_133_266:
6798 case GC_CLOCK_133_266_2:
6799 case GC_CLOCK_166_266:
6800 return 266667;
6801 }
6802
6803 /* Shouldn't happen */
6804 return 0;
6805 }
6806
6807 static int i830_get_display_clock_speed(struct drm_device *dev)
6808 {
6809 return 133333;
6810 }
6811
6812 static unsigned int intel_hpll_vco(struct drm_device *dev)
6813 {
6814 struct drm_i915_private *dev_priv = dev->dev_private;
6815 static const unsigned int blb_vco[8] = {
6816 [0] = 3200000,
6817 [1] = 4000000,
6818 [2] = 5333333,
6819 [3] = 4800000,
6820 [4] = 6400000,
6821 };
6822 static const unsigned int pnv_vco[8] = {
6823 [0] = 3200000,
6824 [1] = 4000000,
6825 [2] = 5333333,
6826 [3] = 4800000,
6827 [4] = 2666667,
6828 };
6829 static const unsigned int cl_vco[8] = {
6830 [0] = 3200000,
6831 [1] = 4000000,
6832 [2] = 5333333,
6833 [3] = 6400000,
6834 [4] = 3333333,
6835 [5] = 3566667,
6836 [6] = 4266667,
6837 };
6838 static const unsigned int elk_vco[8] = {
6839 [0] = 3200000,
6840 [1] = 4000000,
6841 [2] = 5333333,
6842 [3] = 4800000,
6843 };
6844 static const unsigned int ctg_vco[8] = {
6845 [0] = 3200000,
6846 [1] = 4000000,
6847 [2] = 5333333,
6848 [3] = 6400000,
6849 [4] = 2666667,
6850 [5] = 4266667,
6851 };
6852 const unsigned int *vco_table;
6853 unsigned int vco;
6854 uint8_t tmp = 0;
6855
6856 /* FIXME other chipsets? */
6857 if (IS_GM45(dev))
6858 vco_table = ctg_vco;
6859 else if (IS_G4X(dev))
6860 vco_table = elk_vco;
6861 else if (IS_CRESTLINE(dev))
6862 vco_table = cl_vco;
6863 else if (IS_PINEVIEW(dev))
6864 vco_table = pnv_vco;
6865 else if (IS_G33(dev))
6866 vco_table = blb_vco;
6867 else
6868 return 0;
6869
6870 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6871
6872 vco = vco_table[tmp & 0x7];
6873 if (vco == 0)
6874 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6875 else
6876 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6877
6878 return vco;
6879 }
6880
6881 static int gm45_get_display_clock_speed(struct drm_device *dev)
6882 {
6883 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6884 uint16_t tmp = 0;
6885
6886 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6887
6888 cdclk_sel = (tmp >> 12) & 0x1;
6889
6890 switch (vco) {
6891 case 2666667:
6892 case 4000000:
6893 case 5333333:
6894 return cdclk_sel ? 333333 : 222222;
6895 case 3200000:
6896 return cdclk_sel ? 320000 : 228571;
6897 default:
6898 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6899 return 222222;
6900 }
6901 }
6902
6903 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6904 {
6905 static const uint8_t div_3200[] = { 16, 10, 8 };
6906 static const uint8_t div_4000[] = { 20, 12, 10 };
6907 static const uint8_t div_5333[] = { 24, 16, 14 };
6908 const uint8_t *div_table;
6909 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6910 uint16_t tmp = 0;
6911
6912 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6913
6914 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6915
6916 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6917 goto fail;
6918
6919 switch (vco) {
6920 case 3200000:
6921 div_table = div_3200;
6922 break;
6923 case 4000000:
6924 div_table = div_4000;
6925 break;
6926 case 5333333:
6927 div_table = div_5333;
6928 break;
6929 default:
6930 goto fail;
6931 }
6932
6933 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6934
6935 fail:
6936 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6937 return 200000;
6938 }
6939
6940 static int g33_get_display_clock_speed(struct drm_device *dev)
6941 {
6942 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6943 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6944 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6945 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6946 const uint8_t *div_table;
6947 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6948 uint16_t tmp = 0;
6949
6950 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6951
6952 cdclk_sel = (tmp >> 4) & 0x7;
6953
6954 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6955 goto fail;
6956
6957 switch (vco) {
6958 case 3200000:
6959 div_table = div_3200;
6960 break;
6961 case 4000000:
6962 div_table = div_4000;
6963 break;
6964 case 4800000:
6965 div_table = div_4800;
6966 break;
6967 case 5333333:
6968 div_table = div_5333;
6969 break;
6970 default:
6971 goto fail;
6972 }
6973
6974 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6975
6976 fail:
6977 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6978 return 190476;
6979 }
6980
6981 static void
6982 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6983 {
6984 while (*num > DATA_LINK_M_N_MASK ||
6985 *den > DATA_LINK_M_N_MASK) {
6986 *num >>= 1;
6987 *den >>= 1;
6988 }
6989 }
6990
6991 static void compute_m_n(unsigned int m, unsigned int n,
6992 uint32_t *ret_m, uint32_t *ret_n)
6993 {
6994 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6995 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6996 intel_reduce_m_n_ratio(ret_m, ret_n);
6997 }
6998
6999 void
7000 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7001 int pixel_clock, int link_clock,
7002 struct intel_link_m_n *m_n)
7003 {
7004 m_n->tu = 64;
7005
7006 compute_m_n(bits_per_pixel * pixel_clock,
7007 link_clock * nlanes * 8,
7008 &m_n->gmch_m, &m_n->gmch_n);
7009
7010 compute_m_n(pixel_clock, link_clock,
7011 &m_n->link_m, &m_n->link_n);
7012 }
7013
7014 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7015 {
7016 if (i915.panel_use_ssc >= 0)
7017 return i915.panel_use_ssc != 0;
7018 return dev_priv->vbt.lvds_use_ssc
7019 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7020 }
7021
7022 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7023 int num_connectors)
7024 {
7025 struct drm_device *dev = crtc_state->base.crtc->dev;
7026 struct drm_i915_private *dev_priv = dev->dev_private;
7027 int refclk;
7028
7029 WARN_ON(!crtc_state->base.state);
7030
7031 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7032 refclk = 100000;
7033 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7034 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7035 refclk = dev_priv->vbt.lvds_ssc_freq;
7036 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7037 } else if (!IS_GEN2(dev)) {
7038 refclk = 96000;
7039 } else {
7040 refclk = 48000;
7041 }
7042
7043 return refclk;
7044 }
7045
7046 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7047 {
7048 return (1 << dpll->n) << 16 | dpll->m2;
7049 }
7050
7051 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7052 {
7053 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7054 }
7055
7056 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7057 struct intel_crtc_state *crtc_state,
7058 intel_clock_t *reduced_clock)
7059 {
7060 struct drm_device *dev = crtc->base.dev;
7061 u32 fp, fp2 = 0;
7062
7063 if (IS_PINEVIEW(dev)) {
7064 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7065 if (reduced_clock)
7066 fp2 = pnv_dpll_compute_fp(reduced_clock);
7067 } else {
7068 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7069 if (reduced_clock)
7070 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7071 }
7072
7073 crtc_state->dpll_hw_state.fp0 = fp;
7074
7075 crtc->lowfreq_avail = false;
7076 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7077 reduced_clock) {
7078 crtc_state->dpll_hw_state.fp1 = fp2;
7079 crtc->lowfreq_avail = true;
7080 } else {
7081 crtc_state->dpll_hw_state.fp1 = fp;
7082 }
7083 }
7084
7085 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7086 pipe)
7087 {
7088 u32 reg_val;
7089
7090 /*
7091 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7092 * and set it to a reasonable value instead.
7093 */
7094 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7095 reg_val &= 0xffffff00;
7096 reg_val |= 0x00000030;
7097 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7098
7099 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7100 reg_val &= 0x8cffffff;
7101 reg_val = 0x8c000000;
7102 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7103
7104 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7105 reg_val &= 0xffffff00;
7106 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7107
7108 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7109 reg_val &= 0x00ffffff;
7110 reg_val |= 0xb0000000;
7111 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7112 }
7113
7114 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7115 struct intel_link_m_n *m_n)
7116 {
7117 struct drm_device *dev = crtc->base.dev;
7118 struct drm_i915_private *dev_priv = dev->dev_private;
7119 int pipe = crtc->pipe;
7120
7121 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7122 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7123 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7124 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7125 }
7126
7127 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7128 struct intel_link_m_n *m_n,
7129 struct intel_link_m_n *m2_n2)
7130 {
7131 struct drm_device *dev = crtc->base.dev;
7132 struct drm_i915_private *dev_priv = dev->dev_private;
7133 int pipe = crtc->pipe;
7134 enum transcoder transcoder = crtc->config->cpu_transcoder;
7135
7136 if (INTEL_INFO(dev)->gen >= 5) {
7137 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7138 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7139 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7140 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7141 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7142 * for gen < 8) and if DRRS is supported (to make sure the
7143 * registers are not unnecessarily accessed).
7144 */
7145 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7146 crtc->config->has_drrs) {
7147 I915_WRITE(PIPE_DATA_M2(transcoder),
7148 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7149 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7150 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7151 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7152 }
7153 } else {
7154 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7155 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7156 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7157 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7158 }
7159 }
7160
7161 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7162 {
7163 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7164
7165 if (m_n == M1_N1) {
7166 dp_m_n = &crtc->config->dp_m_n;
7167 dp_m2_n2 = &crtc->config->dp_m2_n2;
7168 } else if (m_n == M2_N2) {
7169
7170 /*
7171 * M2_N2 registers are not supported. Hence m2_n2 divider value
7172 * needs to be programmed into M1_N1.
7173 */
7174 dp_m_n = &crtc->config->dp_m2_n2;
7175 } else {
7176 DRM_ERROR("Unsupported divider value\n");
7177 return;
7178 }
7179
7180 if (crtc->config->has_pch_encoder)
7181 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7182 else
7183 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7184 }
7185
7186 static void vlv_compute_dpll(struct intel_crtc *crtc,
7187 struct intel_crtc_state *pipe_config)
7188 {
7189 u32 dpll, dpll_md;
7190
7191 /*
7192 * Enable DPIO clock input. We should never disable the reference
7193 * clock for pipe B, since VGA hotplug / manual detection depends
7194 * on it.
7195 */
7196 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7197 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7198 /* We should never disable this, set it here for state tracking */
7199 if (crtc->pipe == PIPE_B)
7200 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7201 dpll |= DPLL_VCO_ENABLE;
7202 pipe_config->dpll_hw_state.dpll = dpll;
7203
7204 dpll_md = (pipe_config->pixel_multiplier - 1)
7205 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7206 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7207 }
7208
7209 static void vlv_prepare_pll(struct intel_crtc *crtc,
7210 const struct intel_crtc_state *pipe_config)
7211 {
7212 struct drm_device *dev = crtc->base.dev;
7213 struct drm_i915_private *dev_priv = dev->dev_private;
7214 int pipe = crtc->pipe;
7215 u32 mdiv;
7216 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7217 u32 coreclk, reg_val;
7218
7219 mutex_lock(&dev_priv->sb_lock);
7220
7221 bestn = pipe_config->dpll.n;
7222 bestm1 = pipe_config->dpll.m1;
7223 bestm2 = pipe_config->dpll.m2;
7224 bestp1 = pipe_config->dpll.p1;
7225 bestp2 = pipe_config->dpll.p2;
7226
7227 /* See eDP HDMI DPIO driver vbios notes doc */
7228
7229 /* PLL B needs special handling */
7230 if (pipe == PIPE_B)
7231 vlv_pllb_recal_opamp(dev_priv, pipe);
7232
7233 /* Set up Tx target for periodic Rcomp update */
7234 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7235
7236 /* Disable target IRef on PLL */
7237 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7238 reg_val &= 0x00ffffff;
7239 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7240
7241 /* Disable fast lock */
7242 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7243
7244 /* Set idtafcrecal before PLL is enabled */
7245 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7246 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7247 mdiv |= ((bestn << DPIO_N_SHIFT));
7248 mdiv |= (1 << DPIO_K_SHIFT);
7249
7250 /*
7251 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7252 * but we don't support that).
7253 * Note: don't use the DAC post divider as it seems unstable.
7254 */
7255 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7256 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7257
7258 mdiv |= DPIO_ENABLE_CALIBRATION;
7259 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7260
7261 /* Set HBR and RBR LPF coefficients */
7262 if (pipe_config->port_clock == 162000 ||
7263 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7264 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7265 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7266 0x009f0003);
7267 else
7268 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7269 0x00d0000f);
7270
7271 if (pipe_config->has_dp_encoder) {
7272 /* Use SSC source */
7273 if (pipe == PIPE_A)
7274 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7275 0x0df40000);
7276 else
7277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7278 0x0df70000);
7279 } else { /* HDMI or VGA */
7280 /* Use bend source */
7281 if (pipe == PIPE_A)
7282 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7283 0x0df70000);
7284 else
7285 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7286 0x0df40000);
7287 }
7288
7289 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7290 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7291 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7292 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7293 coreclk |= 0x01000000;
7294 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7295
7296 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7297 mutex_unlock(&dev_priv->sb_lock);
7298 }
7299
7300 static void chv_compute_dpll(struct intel_crtc *crtc,
7301 struct intel_crtc_state *pipe_config)
7302 {
7303 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7304 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7305 DPLL_VCO_ENABLE;
7306 if (crtc->pipe != PIPE_A)
7307 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7308
7309 pipe_config->dpll_hw_state.dpll_md =
7310 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7311 }
7312
7313 static void chv_prepare_pll(struct intel_crtc *crtc,
7314 const struct intel_crtc_state *pipe_config)
7315 {
7316 struct drm_device *dev = crtc->base.dev;
7317 struct drm_i915_private *dev_priv = dev->dev_private;
7318 int pipe = crtc->pipe;
7319 int dpll_reg = DPLL(crtc->pipe);
7320 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7321 u32 loopfilter, tribuf_calcntr;
7322 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7323 u32 dpio_val;
7324 int vco;
7325
7326 bestn = pipe_config->dpll.n;
7327 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7328 bestm1 = pipe_config->dpll.m1;
7329 bestm2 = pipe_config->dpll.m2 >> 22;
7330 bestp1 = pipe_config->dpll.p1;
7331 bestp2 = pipe_config->dpll.p2;
7332 vco = pipe_config->dpll.vco;
7333 dpio_val = 0;
7334 loopfilter = 0;
7335
7336 /*
7337 * Enable Refclk and SSC
7338 */
7339 I915_WRITE(dpll_reg,
7340 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7341
7342 mutex_lock(&dev_priv->sb_lock);
7343
7344 /* p1 and p2 divider */
7345 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7346 5 << DPIO_CHV_S1_DIV_SHIFT |
7347 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7348 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7349 1 << DPIO_CHV_K_DIV_SHIFT);
7350
7351 /* Feedback post-divider - m2 */
7352 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7353
7354 /* Feedback refclk divider - n and m1 */
7355 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7356 DPIO_CHV_M1_DIV_BY_2 |
7357 1 << DPIO_CHV_N_DIV_SHIFT);
7358
7359 /* M2 fraction division */
7360 if (bestm2_frac)
7361 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7362
7363 /* M2 fraction division enable */
7364 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7365 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7366 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7367 if (bestm2_frac)
7368 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7369 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7370
7371 /* Program digital lock detect threshold */
7372 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7373 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7374 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7375 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7376 if (!bestm2_frac)
7377 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7378 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7379
7380 /* Loop filter */
7381 if (vco == 5400000) {
7382 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7383 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7384 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7385 tribuf_calcntr = 0x9;
7386 } else if (vco <= 6200000) {
7387 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7388 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7389 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7390 tribuf_calcntr = 0x9;
7391 } else if (vco <= 6480000) {
7392 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7393 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7394 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7395 tribuf_calcntr = 0x8;
7396 } else {
7397 /* Not supported. Apply the same limits as in the max case */
7398 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7399 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7400 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7401 tribuf_calcntr = 0;
7402 }
7403 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7404
7405 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7406 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7407 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7408 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7409
7410 /* AFC Recal */
7411 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7412 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7413 DPIO_AFC_RECAL);
7414
7415 mutex_unlock(&dev_priv->sb_lock);
7416 }
7417
7418 /**
7419 * vlv_force_pll_on - forcibly enable just the PLL
7420 * @dev_priv: i915 private structure
7421 * @pipe: pipe PLL to enable
7422 * @dpll: PLL configuration
7423 *
7424 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7425 * in cases where we need the PLL enabled even when @pipe is not going to
7426 * be enabled.
7427 */
7428 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7429 const struct dpll *dpll)
7430 {
7431 struct intel_crtc *crtc =
7432 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7433 struct intel_crtc_state pipe_config = {
7434 .base.crtc = &crtc->base,
7435 .pixel_multiplier = 1,
7436 .dpll = *dpll,
7437 };
7438
7439 if (IS_CHERRYVIEW(dev)) {
7440 chv_compute_dpll(crtc, &pipe_config);
7441 chv_prepare_pll(crtc, &pipe_config);
7442 chv_enable_pll(crtc, &pipe_config);
7443 } else {
7444 vlv_compute_dpll(crtc, &pipe_config);
7445 vlv_prepare_pll(crtc, &pipe_config);
7446 vlv_enable_pll(crtc, &pipe_config);
7447 }
7448 }
7449
7450 /**
7451 * vlv_force_pll_off - forcibly disable just the PLL
7452 * @dev_priv: i915 private structure
7453 * @pipe: pipe PLL to disable
7454 *
7455 * Disable the PLL for @pipe. To be used in cases where we need
7456 * the PLL enabled even when @pipe is not going to be enabled.
7457 */
7458 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7459 {
7460 if (IS_CHERRYVIEW(dev))
7461 chv_disable_pll(to_i915(dev), pipe);
7462 else
7463 vlv_disable_pll(to_i915(dev), pipe);
7464 }
7465
7466 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7467 struct intel_crtc_state *crtc_state,
7468 intel_clock_t *reduced_clock,
7469 int num_connectors)
7470 {
7471 struct drm_device *dev = crtc->base.dev;
7472 struct drm_i915_private *dev_priv = dev->dev_private;
7473 u32 dpll;
7474 bool is_sdvo;
7475 struct dpll *clock = &crtc_state->dpll;
7476
7477 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7478
7479 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7480 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7481
7482 dpll = DPLL_VGA_MODE_DIS;
7483
7484 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7485 dpll |= DPLLB_MODE_LVDS;
7486 else
7487 dpll |= DPLLB_MODE_DAC_SERIAL;
7488
7489 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7490 dpll |= (crtc_state->pixel_multiplier - 1)
7491 << SDVO_MULTIPLIER_SHIFT_HIRES;
7492 }
7493
7494 if (is_sdvo)
7495 dpll |= DPLL_SDVO_HIGH_SPEED;
7496
7497 if (crtc_state->has_dp_encoder)
7498 dpll |= DPLL_SDVO_HIGH_SPEED;
7499
7500 /* compute bitmask from p1 value */
7501 if (IS_PINEVIEW(dev))
7502 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7503 else {
7504 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7505 if (IS_G4X(dev) && reduced_clock)
7506 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7507 }
7508 switch (clock->p2) {
7509 case 5:
7510 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7511 break;
7512 case 7:
7513 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7514 break;
7515 case 10:
7516 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7517 break;
7518 case 14:
7519 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7520 break;
7521 }
7522 if (INTEL_INFO(dev)->gen >= 4)
7523 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7524
7525 if (crtc_state->sdvo_tv_clock)
7526 dpll |= PLL_REF_INPUT_TVCLKINBC;
7527 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7528 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7529 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7530 else
7531 dpll |= PLL_REF_INPUT_DREFCLK;
7532
7533 dpll |= DPLL_VCO_ENABLE;
7534 crtc_state->dpll_hw_state.dpll = dpll;
7535
7536 if (INTEL_INFO(dev)->gen >= 4) {
7537 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7538 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7539 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7540 }
7541 }
7542
7543 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7544 struct intel_crtc_state *crtc_state,
7545 intel_clock_t *reduced_clock,
7546 int num_connectors)
7547 {
7548 struct drm_device *dev = crtc->base.dev;
7549 struct drm_i915_private *dev_priv = dev->dev_private;
7550 u32 dpll;
7551 struct dpll *clock = &crtc_state->dpll;
7552
7553 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7554
7555 dpll = DPLL_VGA_MODE_DIS;
7556
7557 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7558 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7559 } else {
7560 if (clock->p1 == 2)
7561 dpll |= PLL_P1_DIVIDE_BY_TWO;
7562 else
7563 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7564 if (clock->p2 == 4)
7565 dpll |= PLL_P2_DIVIDE_BY_4;
7566 }
7567
7568 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7569 dpll |= DPLL_DVO_2X_MODE;
7570
7571 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7572 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7573 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7574 else
7575 dpll |= PLL_REF_INPUT_DREFCLK;
7576
7577 dpll |= DPLL_VCO_ENABLE;
7578 crtc_state->dpll_hw_state.dpll = dpll;
7579 }
7580
7581 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7582 {
7583 struct drm_device *dev = intel_crtc->base.dev;
7584 struct drm_i915_private *dev_priv = dev->dev_private;
7585 enum pipe pipe = intel_crtc->pipe;
7586 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7587 struct drm_display_mode *adjusted_mode =
7588 &intel_crtc->config->base.adjusted_mode;
7589 uint32_t crtc_vtotal, crtc_vblank_end;
7590 int vsyncshift = 0;
7591
7592 /* We need to be careful not to changed the adjusted mode, for otherwise
7593 * the hw state checker will get angry at the mismatch. */
7594 crtc_vtotal = adjusted_mode->crtc_vtotal;
7595 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7596
7597 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7598 /* the chip adds 2 halflines automatically */
7599 crtc_vtotal -= 1;
7600 crtc_vblank_end -= 1;
7601
7602 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7603 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7604 else
7605 vsyncshift = adjusted_mode->crtc_hsync_start -
7606 adjusted_mode->crtc_htotal / 2;
7607 if (vsyncshift < 0)
7608 vsyncshift += adjusted_mode->crtc_htotal;
7609 }
7610
7611 if (INTEL_INFO(dev)->gen > 3)
7612 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7613
7614 I915_WRITE(HTOTAL(cpu_transcoder),
7615 (adjusted_mode->crtc_hdisplay - 1) |
7616 ((adjusted_mode->crtc_htotal - 1) << 16));
7617 I915_WRITE(HBLANK(cpu_transcoder),
7618 (adjusted_mode->crtc_hblank_start - 1) |
7619 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7620 I915_WRITE(HSYNC(cpu_transcoder),
7621 (adjusted_mode->crtc_hsync_start - 1) |
7622 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7623
7624 I915_WRITE(VTOTAL(cpu_transcoder),
7625 (adjusted_mode->crtc_vdisplay - 1) |
7626 ((crtc_vtotal - 1) << 16));
7627 I915_WRITE(VBLANK(cpu_transcoder),
7628 (adjusted_mode->crtc_vblank_start - 1) |
7629 ((crtc_vblank_end - 1) << 16));
7630 I915_WRITE(VSYNC(cpu_transcoder),
7631 (adjusted_mode->crtc_vsync_start - 1) |
7632 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7633
7634 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7635 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7636 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7637 * bits. */
7638 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7639 (pipe == PIPE_B || pipe == PIPE_C))
7640 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7641
7642 /* pipesrc controls the size that is scaled from, which should
7643 * always be the user's requested size.
7644 */
7645 I915_WRITE(PIPESRC(pipe),
7646 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7647 (intel_crtc->config->pipe_src_h - 1));
7648 }
7649
7650 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7651 struct intel_crtc_state *pipe_config)
7652 {
7653 struct drm_device *dev = crtc->base.dev;
7654 struct drm_i915_private *dev_priv = dev->dev_private;
7655 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7656 uint32_t tmp;
7657
7658 tmp = I915_READ(HTOTAL(cpu_transcoder));
7659 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7660 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7661 tmp = I915_READ(HBLANK(cpu_transcoder));
7662 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7663 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7664 tmp = I915_READ(HSYNC(cpu_transcoder));
7665 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7666 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7667
7668 tmp = I915_READ(VTOTAL(cpu_transcoder));
7669 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7670 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7671 tmp = I915_READ(VBLANK(cpu_transcoder));
7672 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7673 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7674 tmp = I915_READ(VSYNC(cpu_transcoder));
7675 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7676 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7677
7678 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7679 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7680 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7681 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7682 }
7683
7684 tmp = I915_READ(PIPESRC(crtc->pipe));
7685 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7686 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7687
7688 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7689 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7690 }
7691
7692 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7693 struct intel_crtc_state *pipe_config)
7694 {
7695 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7696 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7697 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7698 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7699
7700 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7701 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7702 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7703 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7704
7705 mode->flags = pipe_config->base.adjusted_mode.flags;
7706
7707 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7708 mode->flags |= pipe_config->base.adjusted_mode.flags;
7709 }
7710
7711 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7712 {
7713 struct drm_device *dev = intel_crtc->base.dev;
7714 struct drm_i915_private *dev_priv = dev->dev_private;
7715 uint32_t pipeconf;
7716
7717 pipeconf = 0;
7718
7719 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7720 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7721 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7722
7723 if (intel_crtc->config->double_wide)
7724 pipeconf |= PIPECONF_DOUBLE_WIDE;
7725
7726 /* only g4x and later have fancy bpc/dither controls */
7727 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7728 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7729 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7730 pipeconf |= PIPECONF_DITHER_EN |
7731 PIPECONF_DITHER_TYPE_SP;
7732
7733 switch (intel_crtc->config->pipe_bpp) {
7734 case 18:
7735 pipeconf |= PIPECONF_6BPC;
7736 break;
7737 case 24:
7738 pipeconf |= PIPECONF_8BPC;
7739 break;
7740 case 30:
7741 pipeconf |= PIPECONF_10BPC;
7742 break;
7743 default:
7744 /* Case prevented by intel_choose_pipe_bpp_dither. */
7745 BUG();
7746 }
7747 }
7748
7749 if (HAS_PIPE_CXSR(dev)) {
7750 if (intel_crtc->lowfreq_avail) {
7751 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7752 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7753 } else {
7754 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7755 }
7756 }
7757
7758 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7759 if (INTEL_INFO(dev)->gen < 4 ||
7760 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7761 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7762 else
7763 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7764 } else
7765 pipeconf |= PIPECONF_PROGRESSIVE;
7766
7767 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7768 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7769
7770 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7771 POSTING_READ(PIPECONF(intel_crtc->pipe));
7772 }
7773
7774 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7775 struct intel_crtc_state *crtc_state)
7776 {
7777 struct drm_device *dev = crtc->base.dev;
7778 struct drm_i915_private *dev_priv = dev->dev_private;
7779 int refclk, num_connectors = 0;
7780 intel_clock_t clock;
7781 bool ok;
7782 bool is_dsi = false;
7783 struct intel_encoder *encoder;
7784 const intel_limit_t *limit;
7785 struct drm_atomic_state *state = crtc_state->base.state;
7786 struct drm_connector *connector;
7787 struct drm_connector_state *connector_state;
7788 int i;
7789
7790 memset(&crtc_state->dpll_hw_state, 0,
7791 sizeof(crtc_state->dpll_hw_state));
7792
7793 for_each_connector_in_state(state, connector, connector_state, i) {
7794 if (connector_state->crtc != &crtc->base)
7795 continue;
7796
7797 encoder = to_intel_encoder(connector_state->best_encoder);
7798
7799 switch (encoder->type) {
7800 case INTEL_OUTPUT_DSI:
7801 is_dsi = true;
7802 break;
7803 default:
7804 break;
7805 }
7806
7807 num_connectors++;
7808 }
7809
7810 if (is_dsi)
7811 return 0;
7812
7813 if (!crtc_state->clock_set) {
7814 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7815
7816 /*
7817 * Returns a set of divisors for the desired target clock with
7818 * the given refclk, or FALSE. The returned values represent
7819 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7820 * 2) / p1 / p2.
7821 */
7822 limit = intel_limit(crtc_state, refclk);
7823 ok = dev_priv->display.find_dpll(limit, crtc_state,
7824 crtc_state->port_clock,
7825 refclk, NULL, &clock);
7826 if (!ok) {
7827 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7828 return -EINVAL;
7829 }
7830
7831 /* Compat-code for transition, will disappear. */
7832 crtc_state->dpll.n = clock.n;
7833 crtc_state->dpll.m1 = clock.m1;
7834 crtc_state->dpll.m2 = clock.m2;
7835 crtc_state->dpll.p1 = clock.p1;
7836 crtc_state->dpll.p2 = clock.p2;
7837 }
7838
7839 if (IS_GEN2(dev)) {
7840 i8xx_compute_dpll(crtc, crtc_state, NULL,
7841 num_connectors);
7842 } else if (IS_CHERRYVIEW(dev)) {
7843 chv_compute_dpll(crtc, crtc_state);
7844 } else if (IS_VALLEYVIEW(dev)) {
7845 vlv_compute_dpll(crtc, crtc_state);
7846 } else {
7847 i9xx_compute_dpll(crtc, crtc_state, NULL,
7848 num_connectors);
7849 }
7850
7851 return 0;
7852 }
7853
7854 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7855 struct intel_crtc_state *pipe_config)
7856 {
7857 struct drm_device *dev = crtc->base.dev;
7858 struct drm_i915_private *dev_priv = dev->dev_private;
7859 uint32_t tmp;
7860
7861 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7862 return;
7863
7864 tmp = I915_READ(PFIT_CONTROL);
7865 if (!(tmp & PFIT_ENABLE))
7866 return;
7867
7868 /* Check whether the pfit is attached to our pipe. */
7869 if (INTEL_INFO(dev)->gen < 4) {
7870 if (crtc->pipe != PIPE_B)
7871 return;
7872 } else {
7873 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7874 return;
7875 }
7876
7877 pipe_config->gmch_pfit.control = tmp;
7878 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7879 if (INTEL_INFO(dev)->gen < 5)
7880 pipe_config->gmch_pfit.lvds_border_bits =
7881 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7882 }
7883
7884 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7885 struct intel_crtc_state *pipe_config)
7886 {
7887 struct drm_device *dev = crtc->base.dev;
7888 struct drm_i915_private *dev_priv = dev->dev_private;
7889 int pipe = pipe_config->cpu_transcoder;
7890 intel_clock_t clock;
7891 u32 mdiv;
7892 int refclk = 100000;
7893
7894 /* In case of MIPI DPLL will not even be used */
7895 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7896 return;
7897
7898 mutex_lock(&dev_priv->sb_lock);
7899 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7900 mutex_unlock(&dev_priv->sb_lock);
7901
7902 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7903 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7904 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7905 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7906 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7907
7908 vlv_clock(refclk, &clock);
7909
7910 /* clock.dot is the fast clock */
7911 pipe_config->port_clock = clock.dot / 5;
7912 }
7913
7914 static void
7915 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7916 struct intel_initial_plane_config *plane_config)
7917 {
7918 struct drm_device *dev = crtc->base.dev;
7919 struct drm_i915_private *dev_priv = dev->dev_private;
7920 u32 val, base, offset;
7921 int pipe = crtc->pipe, plane = crtc->plane;
7922 int fourcc, pixel_format;
7923 unsigned int aligned_height;
7924 struct drm_framebuffer *fb;
7925 struct intel_framebuffer *intel_fb;
7926
7927 val = I915_READ(DSPCNTR(plane));
7928 if (!(val & DISPLAY_PLANE_ENABLE))
7929 return;
7930
7931 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7932 if (!intel_fb) {
7933 DRM_DEBUG_KMS("failed to alloc fb\n");
7934 return;
7935 }
7936
7937 fb = &intel_fb->base;
7938
7939 if (INTEL_INFO(dev)->gen >= 4) {
7940 if (val & DISPPLANE_TILED) {
7941 plane_config->tiling = I915_TILING_X;
7942 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7943 }
7944 }
7945
7946 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7947 fourcc = i9xx_format_to_fourcc(pixel_format);
7948 fb->pixel_format = fourcc;
7949 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7950
7951 if (INTEL_INFO(dev)->gen >= 4) {
7952 if (plane_config->tiling)
7953 offset = I915_READ(DSPTILEOFF(plane));
7954 else
7955 offset = I915_READ(DSPLINOFF(plane));
7956 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7957 } else {
7958 base = I915_READ(DSPADDR(plane));
7959 }
7960 plane_config->base = base;
7961
7962 val = I915_READ(PIPESRC(pipe));
7963 fb->width = ((val >> 16) & 0xfff) + 1;
7964 fb->height = ((val >> 0) & 0xfff) + 1;
7965
7966 val = I915_READ(DSPSTRIDE(pipe));
7967 fb->pitches[0] = val & 0xffffffc0;
7968
7969 aligned_height = intel_fb_align_height(dev, fb->height,
7970 fb->pixel_format,
7971 fb->modifier[0]);
7972
7973 plane_config->size = fb->pitches[0] * aligned_height;
7974
7975 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7976 pipe_name(pipe), plane, fb->width, fb->height,
7977 fb->bits_per_pixel, base, fb->pitches[0],
7978 plane_config->size);
7979
7980 plane_config->fb = intel_fb;
7981 }
7982
7983 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7984 struct intel_crtc_state *pipe_config)
7985 {
7986 struct drm_device *dev = crtc->base.dev;
7987 struct drm_i915_private *dev_priv = dev->dev_private;
7988 int pipe = pipe_config->cpu_transcoder;
7989 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7990 intel_clock_t clock;
7991 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7992 int refclk = 100000;
7993
7994 mutex_lock(&dev_priv->sb_lock);
7995 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7996 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7997 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7998 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7999 mutex_unlock(&dev_priv->sb_lock);
8000
8001 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8002 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8003 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8004 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8005 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8006
8007 chv_clock(refclk, &clock);
8008
8009 /* clock.dot is the fast clock */
8010 pipe_config->port_clock = clock.dot / 5;
8011 }
8012
8013 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8014 struct intel_crtc_state *pipe_config)
8015 {
8016 struct drm_device *dev = crtc->base.dev;
8017 struct drm_i915_private *dev_priv = dev->dev_private;
8018 uint32_t tmp;
8019
8020 if (!intel_display_power_is_enabled(dev_priv,
8021 POWER_DOMAIN_PIPE(crtc->pipe)))
8022 return false;
8023
8024 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8025 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8026
8027 tmp = I915_READ(PIPECONF(crtc->pipe));
8028 if (!(tmp & PIPECONF_ENABLE))
8029 return false;
8030
8031 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8032 switch (tmp & PIPECONF_BPC_MASK) {
8033 case PIPECONF_6BPC:
8034 pipe_config->pipe_bpp = 18;
8035 break;
8036 case PIPECONF_8BPC:
8037 pipe_config->pipe_bpp = 24;
8038 break;
8039 case PIPECONF_10BPC:
8040 pipe_config->pipe_bpp = 30;
8041 break;
8042 default:
8043 break;
8044 }
8045 }
8046
8047 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8048 pipe_config->limited_color_range = true;
8049
8050 if (INTEL_INFO(dev)->gen < 4)
8051 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8052
8053 intel_get_pipe_timings(crtc, pipe_config);
8054
8055 i9xx_get_pfit_config(crtc, pipe_config);
8056
8057 if (INTEL_INFO(dev)->gen >= 4) {
8058 tmp = I915_READ(DPLL_MD(crtc->pipe));
8059 pipe_config->pixel_multiplier =
8060 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8061 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8062 pipe_config->dpll_hw_state.dpll_md = tmp;
8063 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8064 tmp = I915_READ(DPLL(crtc->pipe));
8065 pipe_config->pixel_multiplier =
8066 ((tmp & SDVO_MULTIPLIER_MASK)
8067 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8068 } else {
8069 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8070 * port and will be fixed up in the encoder->get_config
8071 * function. */
8072 pipe_config->pixel_multiplier = 1;
8073 }
8074 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8075 if (!IS_VALLEYVIEW(dev)) {
8076 /*
8077 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8078 * on 830. Filter it out here so that we don't
8079 * report errors due to that.
8080 */
8081 if (IS_I830(dev))
8082 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8083
8084 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8085 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8086 } else {
8087 /* Mask out read-only status bits. */
8088 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8089 DPLL_PORTC_READY_MASK |
8090 DPLL_PORTB_READY_MASK);
8091 }
8092
8093 if (IS_CHERRYVIEW(dev))
8094 chv_crtc_clock_get(crtc, pipe_config);
8095 else if (IS_VALLEYVIEW(dev))
8096 vlv_crtc_clock_get(crtc, pipe_config);
8097 else
8098 i9xx_crtc_clock_get(crtc, pipe_config);
8099
8100 return true;
8101 }
8102
8103 static void ironlake_init_pch_refclk(struct drm_device *dev)
8104 {
8105 struct drm_i915_private *dev_priv = dev->dev_private;
8106 struct intel_encoder *encoder;
8107 u32 val, final;
8108 bool has_lvds = false;
8109 bool has_cpu_edp = false;
8110 bool has_panel = false;
8111 bool has_ck505 = false;
8112 bool can_ssc = false;
8113
8114 /* We need to take the global config into account */
8115 for_each_intel_encoder(dev, encoder) {
8116 switch (encoder->type) {
8117 case INTEL_OUTPUT_LVDS:
8118 has_panel = true;
8119 has_lvds = true;
8120 break;
8121 case INTEL_OUTPUT_EDP:
8122 has_panel = true;
8123 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8124 has_cpu_edp = true;
8125 break;
8126 default:
8127 break;
8128 }
8129 }
8130
8131 if (HAS_PCH_IBX(dev)) {
8132 has_ck505 = dev_priv->vbt.display_clock_mode;
8133 can_ssc = has_ck505;
8134 } else {
8135 has_ck505 = false;
8136 can_ssc = true;
8137 }
8138
8139 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8140 has_panel, has_lvds, has_ck505);
8141
8142 /* Ironlake: try to setup display ref clock before DPLL
8143 * enabling. This is only under driver's control after
8144 * PCH B stepping, previous chipset stepping should be
8145 * ignoring this setting.
8146 */
8147 val = I915_READ(PCH_DREF_CONTROL);
8148
8149 /* As we must carefully and slowly disable/enable each source in turn,
8150 * compute the final state we want first and check if we need to
8151 * make any changes at all.
8152 */
8153 final = val;
8154 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8155 if (has_ck505)
8156 final |= DREF_NONSPREAD_CK505_ENABLE;
8157 else
8158 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8159
8160 final &= ~DREF_SSC_SOURCE_MASK;
8161 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8162 final &= ~DREF_SSC1_ENABLE;
8163
8164 if (has_panel) {
8165 final |= DREF_SSC_SOURCE_ENABLE;
8166
8167 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8168 final |= DREF_SSC1_ENABLE;
8169
8170 if (has_cpu_edp) {
8171 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8172 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8173 else
8174 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8175 } else
8176 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8177 } else {
8178 final |= DREF_SSC_SOURCE_DISABLE;
8179 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8180 }
8181
8182 if (final == val)
8183 return;
8184
8185 /* Always enable nonspread source */
8186 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8187
8188 if (has_ck505)
8189 val |= DREF_NONSPREAD_CK505_ENABLE;
8190 else
8191 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8192
8193 if (has_panel) {
8194 val &= ~DREF_SSC_SOURCE_MASK;
8195 val |= DREF_SSC_SOURCE_ENABLE;
8196
8197 /* SSC must be turned on before enabling the CPU output */
8198 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8199 DRM_DEBUG_KMS("Using SSC on panel\n");
8200 val |= DREF_SSC1_ENABLE;
8201 } else
8202 val &= ~DREF_SSC1_ENABLE;
8203
8204 /* Get SSC going before enabling the outputs */
8205 I915_WRITE(PCH_DREF_CONTROL, val);
8206 POSTING_READ(PCH_DREF_CONTROL);
8207 udelay(200);
8208
8209 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8210
8211 /* Enable CPU source on CPU attached eDP */
8212 if (has_cpu_edp) {
8213 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8214 DRM_DEBUG_KMS("Using SSC on eDP\n");
8215 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8216 } else
8217 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8218 } else
8219 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8220
8221 I915_WRITE(PCH_DREF_CONTROL, val);
8222 POSTING_READ(PCH_DREF_CONTROL);
8223 udelay(200);
8224 } else {
8225 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8226
8227 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8228
8229 /* Turn off CPU output */
8230 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8231
8232 I915_WRITE(PCH_DREF_CONTROL, val);
8233 POSTING_READ(PCH_DREF_CONTROL);
8234 udelay(200);
8235
8236 /* Turn off the SSC source */
8237 val &= ~DREF_SSC_SOURCE_MASK;
8238 val |= DREF_SSC_SOURCE_DISABLE;
8239
8240 /* Turn off SSC1 */
8241 val &= ~DREF_SSC1_ENABLE;
8242
8243 I915_WRITE(PCH_DREF_CONTROL, val);
8244 POSTING_READ(PCH_DREF_CONTROL);
8245 udelay(200);
8246 }
8247
8248 BUG_ON(val != final);
8249 }
8250
8251 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8252 {
8253 uint32_t tmp;
8254
8255 tmp = I915_READ(SOUTH_CHICKEN2);
8256 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8257 I915_WRITE(SOUTH_CHICKEN2, tmp);
8258
8259 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8260 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8261 DRM_ERROR("FDI mPHY reset assert timeout\n");
8262
8263 tmp = I915_READ(SOUTH_CHICKEN2);
8264 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8265 I915_WRITE(SOUTH_CHICKEN2, tmp);
8266
8267 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8268 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8269 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8270 }
8271
8272 /* WaMPhyProgramming:hsw */
8273 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8274 {
8275 uint32_t tmp;
8276
8277 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8278 tmp &= ~(0xFF << 24);
8279 tmp |= (0x12 << 24);
8280 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8281
8282 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8283 tmp |= (1 << 11);
8284 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8285
8286 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8287 tmp |= (1 << 11);
8288 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8289
8290 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8291 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8292 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8293
8294 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8295 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8296 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8297
8298 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8299 tmp &= ~(7 << 13);
8300 tmp |= (5 << 13);
8301 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8302
8303 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8304 tmp &= ~(7 << 13);
8305 tmp |= (5 << 13);
8306 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8307
8308 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8309 tmp &= ~0xFF;
8310 tmp |= 0x1C;
8311 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8312
8313 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8314 tmp &= ~0xFF;
8315 tmp |= 0x1C;
8316 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8317
8318 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8319 tmp &= ~(0xFF << 16);
8320 tmp |= (0x1C << 16);
8321 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8322
8323 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8324 tmp &= ~(0xFF << 16);
8325 tmp |= (0x1C << 16);
8326 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8327
8328 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8329 tmp |= (1 << 27);
8330 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8331
8332 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8333 tmp |= (1 << 27);
8334 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8335
8336 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8337 tmp &= ~(0xF << 28);
8338 tmp |= (4 << 28);
8339 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8340
8341 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8342 tmp &= ~(0xF << 28);
8343 tmp |= (4 << 28);
8344 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8345 }
8346
8347 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8348 * Programming" based on the parameters passed:
8349 * - Sequence to enable CLKOUT_DP
8350 * - Sequence to enable CLKOUT_DP without spread
8351 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8352 */
8353 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8354 bool with_fdi)
8355 {
8356 struct drm_i915_private *dev_priv = dev->dev_private;
8357 uint32_t reg, tmp;
8358
8359 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8360 with_spread = true;
8361 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8362 with_fdi, "LP PCH doesn't have FDI\n"))
8363 with_fdi = false;
8364
8365 mutex_lock(&dev_priv->sb_lock);
8366
8367 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8368 tmp &= ~SBI_SSCCTL_DISABLE;
8369 tmp |= SBI_SSCCTL_PATHALT;
8370 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8371
8372 udelay(24);
8373
8374 if (with_spread) {
8375 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8376 tmp &= ~SBI_SSCCTL_PATHALT;
8377 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8378
8379 if (with_fdi) {
8380 lpt_reset_fdi_mphy(dev_priv);
8381 lpt_program_fdi_mphy(dev_priv);
8382 }
8383 }
8384
8385 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8386 SBI_GEN0 : SBI_DBUFF0;
8387 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8388 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8389 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8390
8391 mutex_unlock(&dev_priv->sb_lock);
8392 }
8393
8394 /* Sequence to disable CLKOUT_DP */
8395 static void lpt_disable_clkout_dp(struct drm_device *dev)
8396 {
8397 struct drm_i915_private *dev_priv = dev->dev_private;
8398 uint32_t reg, tmp;
8399
8400 mutex_lock(&dev_priv->sb_lock);
8401
8402 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8403 SBI_GEN0 : SBI_DBUFF0;
8404 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8405 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8406 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8407
8408 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8409 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8410 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8411 tmp |= SBI_SSCCTL_PATHALT;
8412 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8413 udelay(32);
8414 }
8415 tmp |= SBI_SSCCTL_DISABLE;
8416 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8417 }
8418
8419 mutex_unlock(&dev_priv->sb_lock);
8420 }
8421
8422 static void lpt_init_pch_refclk(struct drm_device *dev)
8423 {
8424 struct intel_encoder *encoder;
8425 bool has_vga = false;
8426
8427 for_each_intel_encoder(dev, encoder) {
8428 switch (encoder->type) {
8429 case INTEL_OUTPUT_ANALOG:
8430 has_vga = true;
8431 break;
8432 default:
8433 break;
8434 }
8435 }
8436
8437 if (has_vga)
8438 lpt_enable_clkout_dp(dev, true, true);
8439 else
8440 lpt_disable_clkout_dp(dev);
8441 }
8442
8443 /*
8444 * Initialize reference clocks when the driver loads
8445 */
8446 void intel_init_pch_refclk(struct drm_device *dev)
8447 {
8448 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8449 ironlake_init_pch_refclk(dev);
8450 else if (HAS_PCH_LPT(dev))
8451 lpt_init_pch_refclk(dev);
8452 }
8453
8454 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8455 {
8456 struct drm_device *dev = crtc_state->base.crtc->dev;
8457 struct drm_i915_private *dev_priv = dev->dev_private;
8458 struct drm_atomic_state *state = crtc_state->base.state;
8459 struct drm_connector *connector;
8460 struct drm_connector_state *connector_state;
8461 struct intel_encoder *encoder;
8462 int num_connectors = 0, i;
8463 bool is_lvds = false;
8464
8465 for_each_connector_in_state(state, connector, connector_state, i) {
8466 if (connector_state->crtc != crtc_state->base.crtc)
8467 continue;
8468
8469 encoder = to_intel_encoder(connector_state->best_encoder);
8470
8471 switch (encoder->type) {
8472 case INTEL_OUTPUT_LVDS:
8473 is_lvds = true;
8474 break;
8475 default:
8476 break;
8477 }
8478 num_connectors++;
8479 }
8480
8481 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8482 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8483 dev_priv->vbt.lvds_ssc_freq);
8484 return dev_priv->vbt.lvds_ssc_freq;
8485 }
8486
8487 return 120000;
8488 }
8489
8490 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8491 {
8492 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8494 int pipe = intel_crtc->pipe;
8495 uint32_t val;
8496
8497 val = 0;
8498
8499 switch (intel_crtc->config->pipe_bpp) {
8500 case 18:
8501 val |= PIPECONF_6BPC;
8502 break;
8503 case 24:
8504 val |= PIPECONF_8BPC;
8505 break;
8506 case 30:
8507 val |= PIPECONF_10BPC;
8508 break;
8509 case 36:
8510 val |= PIPECONF_12BPC;
8511 break;
8512 default:
8513 /* Case prevented by intel_choose_pipe_bpp_dither. */
8514 BUG();
8515 }
8516
8517 if (intel_crtc->config->dither)
8518 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8519
8520 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8521 val |= PIPECONF_INTERLACED_ILK;
8522 else
8523 val |= PIPECONF_PROGRESSIVE;
8524
8525 if (intel_crtc->config->limited_color_range)
8526 val |= PIPECONF_COLOR_RANGE_SELECT;
8527
8528 I915_WRITE(PIPECONF(pipe), val);
8529 POSTING_READ(PIPECONF(pipe));
8530 }
8531
8532 /*
8533 * Set up the pipe CSC unit.
8534 *
8535 * Currently only full range RGB to limited range RGB conversion
8536 * is supported, but eventually this should handle various
8537 * RGB<->YCbCr scenarios as well.
8538 */
8539 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8540 {
8541 struct drm_device *dev = crtc->dev;
8542 struct drm_i915_private *dev_priv = dev->dev_private;
8543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8544 int pipe = intel_crtc->pipe;
8545 uint16_t coeff = 0x7800; /* 1.0 */
8546
8547 /*
8548 * TODO: Check what kind of values actually come out of the pipe
8549 * with these coeff/postoff values and adjust to get the best
8550 * accuracy. Perhaps we even need to take the bpc value into
8551 * consideration.
8552 */
8553
8554 if (intel_crtc->config->limited_color_range)
8555 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8556
8557 /*
8558 * GY/GU and RY/RU should be the other way around according
8559 * to BSpec, but reality doesn't agree. Just set them up in
8560 * a way that results in the correct picture.
8561 */
8562 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8563 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8564
8565 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8566 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8567
8568 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8569 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8570
8571 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8572 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8573 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8574
8575 if (INTEL_INFO(dev)->gen > 6) {
8576 uint16_t postoff = 0;
8577
8578 if (intel_crtc->config->limited_color_range)
8579 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8580
8581 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8582 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8583 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8584
8585 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8586 } else {
8587 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8588
8589 if (intel_crtc->config->limited_color_range)
8590 mode |= CSC_BLACK_SCREEN_OFFSET;
8591
8592 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8593 }
8594 }
8595
8596 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8597 {
8598 struct drm_device *dev = crtc->dev;
8599 struct drm_i915_private *dev_priv = dev->dev_private;
8600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8601 enum pipe pipe = intel_crtc->pipe;
8602 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8603 uint32_t val;
8604
8605 val = 0;
8606
8607 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8608 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8609
8610 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8611 val |= PIPECONF_INTERLACED_ILK;
8612 else
8613 val |= PIPECONF_PROGRESSIVE;
8614
8615 I915_WRITE(PIPECONF(cpu_transcoder), val);
8616 POSTING_READ(PIPECONF(cpu_transcoder));
8617
8618 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8619 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8620
8621 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8622 val = 0;
8623
8624 switch (intel_crtc->config->pipe_bpp) {
8625 case 18:
8626 val |= PIPEMISC_DITHER_6_BPC;
8627 break;
8628 case 24:
8629 val |= PIPEMISC_DITHER_8_BPC;
8630 break;
8631 case 30:
8632 val |= PIPEMISC_DITHER_10_BPC;
8633 break;
8634 case 36:
8635 val |= PIPEMISC_DITHER_12_BPC;
8636 break;
8637 default:
8638 /* Case prevented by pipe_config_set_bpp. */
8639 BUG();
8640 }
8641
8642 if (intel_crtc->config->dither)
8643 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8644
8645 I915_WRITE(PIPEMISC(pipe), val);
8646 }
8647 }
8648
8649 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8650 struct intel_crtc_state *crtc_state,
8651 intel_clock_t *clock,
8652 bool *has_reduced_clock,
8653 intel_clock_t *reduced_clock)
8654 {
8655 struct drm_device *dev = crtc->dev;
8656 struct drm_i915_private *dev_priv = dev->dev_private;
8657 int refclk;
8658 const intel_limit_t *limit;
8659 bool ret;
8660
8661 refclk = ironlake_get_refclk(crtc_state);
8662
8663 /*
8664 * Returns a set of divisors for the desired target clock with the given
8665 * refclk, or FALSE. The returned values represent the clock equation:
8666 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8667 */
8668 limit = intel_limit(crtc_state, refclk);
8669 ret = dev_priv->display.find_dpll(limit, crtc_state,
8670 crtc_state->port_clock,
8671 refclk, NULL, clock);
8672 if (!ret)
8673 return false;
8674
8675 return true;
8676 }
8677
8678 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8679 {
8680 /*
8681 * Account for spread spectrum to avoid
8682 * oversubscribing the link. Max center spread
8683 * is 2.5%; use 5% for safety's sake.
8684 */
8685 u32 bps = target_clock * bpp * 21 / 20;
8686 return DIV_ROUND_UP(bps, link_bw * 8);
8687 }
8688
8689 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8690 {
8691 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8692 }
8693
8694 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8695 struct intel_crtc_state *crtc_state,
8696 u32 *fp,
8697 intel_clock_t *reduced_clock, u32 *fp2)
8698 {
8699 struct drm_crtc *crtc = &intel_crtc->base;
8700 struct drm_device *dev = crtc->dev;
8701 struct drm_i915_private *dev_priv = dev->dev_private;
8702 struct drm_atomic_state *state = crtc_state->base.state;
8703 struct drm_connector *connector;
8704 struct drm_connector_state *connector_state;
8705 struct intel_encoder *encoder;
8706 uint32_t dpll;
8707 int factor, num_connectors = 0, i;
8708 bool is_lvds = false, is_sdvo = false;
8709
8710 for_each_connector_in_state(state, connector, connector_state, i) {
8711 if (connector_state->crtc != crtc_state->base.crtc)
8712 continue;
8713
8714 encoder = to_intel_encoder(connector_state->best_encoder);
8715
8716 switch (encoder->type) {
8717 case INTEL_OUTPUT_LVDS:
8718 is_lvds = true;
8719 break;
8720 case INTEL_OUTPUT_SDVO:
8721 case INTEL_OUTPUT_HDMI:
8722 is_sdvo = true;
8723 break;
8724 default:
8725 break;
8726 }
8727
8728 num_connectors++;
8729 }
8730
8731 /* Enable autotuning of the PLL clock (if permissible) */
8732 factor = 21;
8733 if (is_lvds) {
8734 if ((intel_panel_use_ssc(dev_priv) &&
8735 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8736 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8737 factor = 25;
8738 } else if (crtc_state->sdvo_tv_clock)
8739 factor = 20;
8740
8741 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8742 *fp |= FP_CB_TUNE;
8743
8744 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8745 *fp2 |= FP_CB_TUNE;
8746
8747 dpll = 0;
8748
8749 if (is_lvds)
8750 dpll |= DPLLB_MODE_LVDS;
8751 else
8752 dpll |= DPLLB_MODE_DAC_SERIAL;
8753
8754 dpll |= (crtc_state->pixel_multiplier - 1)
8755 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8756
8757 if (is_sdvo)
8758 dpll |= DPLL_SDVO_HIGH_SPEED;
8759 if (crtc_state->has_dp_encoder)
8760 dpll |= DPLL_SDVO_HIGH_SPEED;
8761
8762 /* compute bitmask from p1 value */
8763 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8764 /* also FPA1 */
8765 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8766
8767 switch (crtc_state->dpll.p2) {
8768 case 5:
8769 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8770 break;
8771 case 7:
8772 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8773 break;
8774 case 10:
8775 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8776 break;
8777 case 14:
8778 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8779 break;
8780 }
8781
8782 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8783 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8784 else
8785 dpll |= PLL_REF_INPUT_DREFCLK;
8786
8787 return dpll | DPLL_VCO_ENABLE;
8788 }
8789
8790 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8791 struct intel_crtc_state *crtc_state)
8792 {
8793 struct drm_device *dev = crtc->base.dev;
8794 intel_clock_t clock, reduced_clock;
8795 u32 dpll = 0, fp = 0, fp2 = 0;
8796 bool ok, has_reduced_clock = false;
8797 bool is_lvds = false;
8798 struct intel_shared_dpll *pll;
8799
8800 memset(&crtc_state->dpll_hw_state, 0,
8801 sizeof(crtc_state->dpll_hw_state));
8802
8803 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8804
8805 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8806 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8807
8808 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8809 &has_reduced_clock, &reduced_clock);
8810 if (!ok && !crtc_state->clock_set) {
8811 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8812 return -EINVAL;
8813 }
8814 /* Compat-code for transition, will disappear. */
8815 if (!crtc_state->clock_set) {
8816 crtc_state->dpll.n = clock.n;
8817 crtc_state->dpll.m1 = clock.m1;
8818 crtc_state->dpll.m2 = clock.m2;
8819 crtc_state->dpll.p1 = clock.p1;
8820 crtc_state->dpll.p2 = clock.p2;
8821 }
8822
8823 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8824 if (crtc_state->has_pch_encoder) {
8825 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8826 if (has_reduced_clock)
8827 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8828
8829 dpll = ironlake_compute_dpll(crtc, crtc_state,
8830 &fp, &reduced_clock,
8831 has_reduced_clock ? &fp2 : NULL);
8832
8833 crtc_state->dpll_hw_state.dpll = dpll;
8834 crtc_state->dpll_hw_state.fp0 = fp;
8835 if (has_reduced_clock)
8836 crtc_state->dpll_hw_state.fp1 = fp2;
8837 else
8838 crtc_state->dpll_hw_state.fp1 = fp;
8839
8840 pll = intel_get_shared_dpll(crtc, crtc_state);
8841 if (pll == NULL) {
8842 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8843 pipe_name(crtc->pipe));
8844 return -EINVAL;
8845 }
8846 }
8847
8848 if (is_lvds && has_reduced_clock)
8849 crtc->lowfreq_avail = true;
8850 else
8851 crtc->lowfreq_avail = false;
8852
8853 return 0;
8854 }
8855
8856 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8857 struct intel_link_m_n *m_n)
8858 {
8859 struct drm_device *dev = crtc->base.dev;
8860 struct drm_i915_private *dev_priv = dev->dev_private;
8861 enum pipe pipe = crtc->pipe;
8862
8863 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8864 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8865 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8866 & ~TU_SIZE_MASK;
8867 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8868 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8869 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8870 }
8871
8872 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8873 enum transcoder transcoder,
8874 struct intel_link_m_n *m_n,
8875 struct intel_link_m_n *m2_n2)
8876 {
8877 struct drm_device *dev = crtc->base.dev;
8878 struct drm_i915_private *dev_priv = dev->dev_private;
8879 enum pipe pipe = crtc->pipe;
8880
8881 if (INTEL_INFO(dev)->gen >= 5) {
8882 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8883 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8884 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8885 & ~TU_SIZE_MASK;
8886 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8887 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8888 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8889 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8890 * gen < 8) and if DRRS is supported (to make sure the
8891 * registers are not unnecessarily read).
8892 */
8893 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8894 crtc->config->has_drrs) {
8895 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8896 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8897 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8898 & ~TU_SIZE_MASK;
8899 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8900 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8901 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8902 }
8903 } else {
8904 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8905 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8906 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8907 & ~TU_SIZE_MASK;
8908 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8909 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8910 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8911 }
8912 }
8913
8914 void intel_dp_get_m_n(struct intel_crtc *crtc,
8915 struct intel_crtc_state *pipe_config)
8916 {
8917 if (pipe_config->has_pch_encoder)
8918 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8919 else
8920 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8921 &pipe_config->dp_m_n,
8922 &pipe_config->dp_m2_n2);
8923 }
8924
8925 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8926 struct intel_crtc_state *pipe_config)
8927 {
8928 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8929 &pipe_config->fdi_m_n, NULL);
8930 }
8931
8932 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8933 struct intel_crtc_state *pipe_config)
8934 {
8935 struct drm_device *dev = crtc->base.dev;
8936 struct drm_i915_private *dev_priv = dev->dev_private;
8937 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8938 uint32_t ps_ctrl = 0;
8939 int id = -1;
8940 int i;
8941
8942 /* find scaler attached to this pipe */
8943 for (i = 0; i < crtc->num_scalers; i++) {
8944 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8945 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8946 id = i;
8947 pipe_config->pch_pfit.enabled = true;
8948 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8949 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8950 break;
8951 }
8952 }
8953
8954 scaler_state->scaler_id = id;
8955 if (id >= 0) {
8956 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8957 } else {
8958 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8959 }
8960 }
8961
8962 static void
8963 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8964 struct intel_initial_plane_config *plane_config)
8965 {
8966 struct drm_device *dev = crtc->base.dev;
8967 struct drm_i915_private *dev_priv = dev->dev_private;
8968 u32 val, base, offset, stride_mult, tiling;
8969 int pipe = crtc->pipe;
8970 int fourcc, pixel_format;
8971 unsigned int aligned_height;
8972 struct drm_framebuffer *fb;
8973 struct intel_framebuffer *intel_fb;
8974
8975 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8976 if (!intel_fb) {
8977 DRM_DEBUG_KMS("failed to alloc fb\n");
8978 return;
8979 }
8980
8981 fb = &intel_fb->base;
8982
8983 val = I915_READ(PLANE_CTL(pipe, 0));
8984 if (!(val & PLANE_CTL_ENABLE))
8985 goto error;
8986
8987 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8988 fourcc = skl_format_to_fourcc(pixel_format,
8989 val & PLANE_CTL_ORDER_RGBX,
8990 val & PLANE_CTL_ALPHA_MASK);
8991 fb->pixel_format = fourcc;
8992 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8993
8994 tiling = val & PLANE_CTL_TILED_MASK;
8995 switch (tiling) {
8996 case PLANE_CTL_TILED_LINEAR:
8997 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8998 break;
8999 case PLANE_CTL_TILED_X:
9000 plane_config->tiling = I915_TILING_X;
9001 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9002 break;
9003 case PLANE_CTL_TILED_Y:
9004 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9005 break;
9006 case PLANE_CTL_TILED_YF:
9007 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9008 break;
9009 default:
9010 MISSING_CASE(tiling);
9011 goto error;
9012 }
9013
9014 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9015 plane_config->base = base;
9016
9017 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9018
9019 val = I915_READ(PLANE_SIZE(pipe, 0));
9020 fb->height = ((val >> 16) & 0xfff) + 1;
9021 fb->width = ((val >> 0) & 0x1fff) + 1;
9022
9023 val = I915_READ(PLANE_STRIDE(pipe, 0));
9024 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9025 fb->pixel_format);
9026 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9027
9028 aligned_height = intel_fb_align_height(dev, fb->height,
9029 fb->pixel_format,
9030 fb->modifier[0]);
9031
9032 plane_config->size = fb->pitches[0] * aligned_height;
9033
9034 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9035 pipe_name(pipe), fb->width, fb->height,
9036 fb->bits_per_pixel, base, fb->pitches[0],
9037 plane_config->size);
9038
9039 plane_config->fb = intel_fb;
9040 return;
9041
9042 error:
9043 kfree(fb);
9044 }
9045
9046 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9047 struct intel_crtc_state *pipe_config)
9048 {
9049 struct drm_device *dev = crtc->base.dev;
9050 struct drm_i915_private *dev_priv = dev->dev_private;
9051 uint32_t tmp;
9052
9053 tmp = I915_READ(PF_CTL(crtc->pipe));
9054
9055 if (tmp & PF_ENABLE) {
9056 pipe_config->pch_pfit.enabled = true;
9057 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9058 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9059
9060 /* We currently do not free assignements of panel fitters on
9061 * ivb/hsw (since we don't use the higher upscaling modes which
9062 * differentiates them) so just WARN about this case for now. */
9063 if (IS_GEN7(dev)) {
9064 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9065 PF_PIPE_SEL_IVB(crtc->pipe));
9066 }
9067 }
9068 }
9069
9070 static void
9071 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9072 struct intel_initial_plane_config *plane_config)
9073 {
9074 struct drm_device *dev = crtc->base.dev;
9075 struct drm_i915_private *dev_priv = dev->dev_private;
9076 u32 val, base, offset;
9077 int pipe = crtc->pipe;
9078 int fourcc, pixel_format;
9079 unsigned int aligned_height;
9080 struct drm_framebuffer *fb;
9081 struct intel_framebuffer *intel_fb;
9082
9083 val = I915_READ(DSPCNTR(pipe));
9084 if (!(val & DISPLAY_PLANE_ENABLE))
9085 return;
9086
9087 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9088 if (!intel_fb) {
9089 DRM_DEBUG_KMS("failed to alloc fb\n");
9090 return;
9091 }
9092
9093 fb = &intel_fb->base;
9094
9095 if (INTEL_INFO(dev)->gen >= 4) {
9096 if (val & DISPPLANE_TILED) {
9097 plane_config->tiling = I915_TILING_X;
9098 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9099 }
9100 }
9101
9102 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9103 fourcc = i9xx_format_to_fourcc(pixel_format);
9104 fb->pixel_format = fourcc;
9105 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9106
9107 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9108 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9109 offset = I915_READ(DSPOFFSET(pipe));
9110 } else {
9111 if (plane_config->tiling)
9112 offset = I915_READ(DSPTILEOFF(pipe));
9113 else
9114 offset = I915_READ(DSPLINOFF(pipe));
9115 }
9116 plane_config->base = base;
9117
9118 val = I915_READ(PIPESRC(pipe));
9119 fb->width = ((val >> 16) & 0xfff) + 1;
9120 fb->height = ((val >> 0) & 0xfff) + 1;
9121
9122 val = I915_READ(DSPSTRIDE(pipe));
9123 fb->pitches[0] = val & 0xffffffc0;
9124
9125 aligned_height = intel_fb_align_height(dev, fb->height,
9126 fb->pixel_format,
9127 fb->modifier[0]);
9128
9129 plane_config->size = fb->pitches[0] * aligned_height;
9130
9131 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9132 pipe_name(pipe), fb->width, fb->height,
9133 fb->bits_per_pixel, base, fb->pitches[0],
9134 plane_config->size);
9135
9136 plane_config->fb = intel_fb;
9137 }
9138
9139 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9140 struct intel_crtc_state *pipe_config)
9141 {
9142 struct drm_device *dev = crtc->base.dev;
9143 struct drm_i915_private *dev_priv = dev->dev_private;
9144 uint32_t tmp;
9145
9146 if (!intel_display_power_is_enabled(dev_priv,
9147 POWER_DOMAIN_PIPE(crtc->pipe)))
9148 return false;
9149
9150 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9151 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9152
9153 tmp = I915_READ(PIPECONF(crtc->pipe));
9154 if (!(tmp & PIPECONF_ENABLE))
9155 return false;
9156
9157 switch (tmp & PIPECONF_BPC_MASK) {
9158 case PIPECONF_6BPC:
9159 pipe_config->pipe_bpp = 18;
9160 break;
9161 case PIPECONF_8BPC:
9162 pipe_config->pipe_bpp = 24;
9163 break;
9164 case PIPECONF_10BPC:
9165 pipe_config->pipe_bpp = 30;
9166 break;
9167 case PIPECONF_12BPC:
9168 pipe_config->pipe_bpp = 36;
9169 break;
9170 default:
9171 break;
9172 }
9173
9174 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9175 pipe_config->limited_color_range = true;
9176
9177 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9178 struct intel_shared_dpll *pll;
9179
9180 pipe_config->has_pch_encoder = true;
9181
9182 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9183 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9184 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9185
9186 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9187
9188 if (HAS_PCH_IBX(dev_priv->dev)) {
9189 pipe_config->shared_dpll =
9190 (enum intel_dpll_id) crtc->pipe;
9191 } else {
9192 tmp = I915_READ(PCH_DPLL_SEL);
9193 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9194 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9195 else
9196 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9197 }
9198
9199 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9200
9201 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9202 &pipe_config->dpll_hw_state));
9203
9204 tmp = pipe_config->dpll_hw_state.dpll;
9205 pipe_config->pixel_multiplier =
9206 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9207 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9208
9209 ironlake_pch_clock_get(crtc, pipe_config);
9210 } else {
9211 pipe_config->pixel_multiplier = 1;
9212 }
9213
9214 intel_get_pipe_timings(crtc, pipe_config);
9215
9216 ironlake_get_pfit_config(crtc, pipe_config);
9217
9218 return true;
9219 }
9220
9221 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9222 {
9223 struct drm_device *dev = dev_priv->dev;
9224 struct intel_crtc *crtc;
9225
9226 for_each_intel_crtc(dev, crtc)
9227 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9228 pipe_name(crtc->pipe));
9229
9230 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9231 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9232 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9233 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9234 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9235 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9236 "CPU PWM1 enabled\n");
9237 if (IS_HASWELL(dev))
9238 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9239 "CPU PWM2 enabled\n");
9240 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9241 "PCH PWM1 enabled\n");
9242 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9243 "Utility pin enabled\n");
9244 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9245
9246 /*
9247 * In theory we can still leave IRQs enabled, as long as only the HPD
9248 * interrupts remain enabled. We used to check for that, but since it's
9249 * gen-specific and since we only disable LCPLL after we fully disable
9250 * the interrupts, the check below should be enough.
9251 */
9252 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9253 }
9254
9255 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9256 {
9257 struct drm_device *dev = dev_priv->dev;
9258
9259 if (IS_HASWELL(dev))
9260 return I915_READ(D_COMP_HSW);
9261 else
9262 return I915_READ(D_COMP_BDW);
9263 }
9264
9265 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9266 {
9267 struct drm_device *dev = dev_priv->dev;
9268
9269 if (IS_HASWELL(dev)) {
9270 mutex_lock(&dev_priv->rps.hw_lock);
9271 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9272 val))
9273 DRM_ERROR("Failed to write to D_COMP\n");
9274 mutex_unlock(&dev_priv->rps.hw_lock);
9275 } else {
9276 I915_WRITE(D_COMP_BDW, val);
9277 POSTING_READ(D_COMP_BDW);
9278 }
9279 }
9280
9281 /*
9282 * This function implements pieces of two sequences from BSpec:
9283 * - Sequence for display software to disable LCPLL
9284 * - Sequence for display software to allow package C8+
9285 * The steps implemented here are just the steps that actually touch the LCPLL
9286 * register. Callers should take care of disabling all the display engine
9287 * functions, doing the mode unset, fixing interrupts, etc.
9288 */
9289 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9290 bool switch_to_fclk, bool allow_power_down)
9291 {
9292 uint32_t val;
9293
9294 assert_can_disable_lcpll(dev_priv);
9295
9296 val = I915_READ(LCPLL_CTL);
9297
9298 if (switch_to_fclk) {
9299 val |= LCPLL_CD_SOURCE_FCLK;
9300 I915_WRITE(LCPLL_CTL, val);
9301
9302 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9303 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9304 DRM_ERROR("Switching to FCLK failed\n");
9305
9306 val = I915_READ(LCPLL_CTL);
9307 }
9308
9309 val |= LCPLL_PLL_DISABLE;
9310 I915_WRITE(LCPLL_CTL, val);
9311 POSTING_READ(LCPLL_CTL);
9312
9313 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9314 DRM_ERROR("LCPLL still locked\n");
9315
9316 val = hsw_read_dcomp(dev_priv);
9317 val |= D_COMP_COMP_DISABLE;
9318 hsw_write_dcomp(dev_priv, val);
9319 ndelay(100);
9320
9321 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9322 1))
9323 DRM_ERROR("D_COMP RCOMP still in progress\n");
9324
9325 if (allow_power_down) {
9326 val = I915_READ(LCPLL_CTL);
9327 val |= LCPLL_POWER_DOWN_ALLOW;
9328 I915_WRITE(LCPLL_CTL, val);
9329 POSTING_READ(LCPLL_CTL);
9330 }
9331 }
9332
9333 /*
9334 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9335 * source.
9336 */
9337 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9338 {
9339 uint32_t val;
9340
9341 val = I915_READ(LCPLL_CTL);
9342
9343 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9344 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9345 return;
9346
9347 /*
9348 * Make sure we're not on PC8 state before disabling PC8, otherwise
9349 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9350 */
9351 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9352
9353 if (val & LCPLL_POWER_DOWN_ALLOW) {
9354 val &= ~LCPLL_POWER_DOWN_ALLOW;
9355 I915_WRITE(LCPLL_CTL, val);
9356 POSTING_READ(LCPLL_CTL);
9357 }
9358
9359 val = hsw_read_dcomp(dev_priv);
9360 val |= D_COMP_COMP_FORCE;
9361 val &= ~D_COMP_COMP_DISABLE;
9362 hsw_write_dcomp(dev_priv, val);
9363
9364 val = I915_READ(LCPLL_CTL);
9365 val &= ~LCPLL_PLL_DISABLE;
9366 I915_WRITE(LCPLL_CTL, val);
9367
9368 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9369 DRM_ERROR("LCPLL not locked yet\n");
9370
9371 if (val & LCPLL_CD_SOURCE_FCLK) {
9372 val = I915_READ(LCPLL_CTL);
9373 val &= ~LCPLL_CD_SOURCE_FCLK;
9374 I915_WRITE(LCPLL_CTL, val);
9375
9376 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9377 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9378 DRM_ERROR("Switching back to LCPLL failed\n");
9379 }
9380
9381 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9382 intel_update_cdclk(dev_priv->dev);
9383 }
9384
9385 /*
9386 * Package states C8 and deeper are really deep PC states that can only be
9387 * reached when all the devices on the system allow it, so even if the graphics
9388 * device allows PC8+, it doesn't mean the system will actually get to these
9389 * states. Our driver only allows PC8+ when going into runtime PM.
9390 *
9391 * The requirements for PC8+ are that all the outputs are disabled, the power
9392 * well is disabled and most interrupts are disabled, and these are also
9393 * requirements for runtime PM. When these conditions are met, we manually do
9394 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9395 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9396 * hang the machine.
9397 *
9398 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9399 * the state of some registers, so when we come back from PC8+ we need to
9400 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9401 * need to take care of the registers kept by RC6. Notice that this happens even
9402 * if we don't put the device in PCI D3 state (which is what currently happens
9403 * because of the runtime PM support).
9404 *
9405 * For more, read "Display Sequences for Package C8" on the hardware
9406 * documentation.
9407 */
9408 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9409 {
9410 struct drm_device *dev = dev_priv->dev;
9411 uint32_t val;
9412
9413 DRM_DEBUG_KMS("Enabling package C8+\n");
9414
9415 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9416 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9417 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9418 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9419 }
9420
9421 lpt_disable_clkout_dp(dev);
9422 hsw_disable_lcpll(dev_priv, true, true);
9423 }
9424
9425 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9426 {
9427 struct drm_device *dev = dev_priv->dev;
9428 uint32_t val;
9429
9430 DRM_DEBUG_KMS("Disabling package C8+\n");
9431
9432 hsw_restore_lcpll(dev_priv);
9433 lpt_init_pch_refclk(dev);
9434
9435 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9436 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9437 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9438 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9439 }
9440
9441 intel_prepare_ddi(dev);
9442 }
9443
9444 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9445 {
9446 struct drm_device *dev = old_state->dev;
9447 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9448
9449 broxton_set_cdclk(dev, req_cdclk);
9450 }
9451
9452 /* compute the max rate for new configuration */
9453 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9454 {
9455 struct intel_crtc *intel_crtc;
9456 struct intel_crtc_state *crtc_state;
9457 int max_pixel_rate = 0;
9458
9459 for_each_intel_crtc(state->dev, intel_crtc) {
9460 int pixel_rate;
9461
9462 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9463 if (IS_ERR(crtc_state))
9464 return PTR_ERR(crtc_state);
9465
9466 if (!crtc_state->base.enable)
9467 continue;
9468
9469 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9470
9471 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9472 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9473 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9474
9475 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9476 }
9477
9478 return max_pixel_rate;
9479 }
9480
9481 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9482 {
9483 struct drm_i915_private *dev_priv = dev->dev_private;
9484 uint32_t val, data;
9485 int ret;
9486
9487 if (WARN((I915_READ(LCPLL_CTL) &
9488 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9489 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9490 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9491 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9492 "trying to change cdclk frequency with cdclk not enabled\n"))
9493 return;
9494
9495 mutex_lock(&dev_priv->rps.hw_lock);
9496 ret = sandybridge_pcode_write(dev_priv,
9497 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9498 mutex_unlock(&dev_priv->rps.hw_lock);
9499 if (ret) {
9500 DRM_ERROR("failed to inform pcode about cdclk change\n");
9501 return;
9502 }
9503
9504 val = I915_READ(LCPLL_CTL);
9505 val |= LCPLL_CD_SOURCE_FCLK;
9506 I915_WRITE(LCPLL_CTL, val);
9507
9508 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9509 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9510 DRM_ERROR("Switching to FCLK failed\n");
9511
9512 val = I915_READ(LCPLL_CTL);
9513 val &= ~LCPLL_CLK_FREQ_MASK;
9514
9515 switch (cdclk) {
9516 case 450000:
9517 val |= LCPLL_CLK_FREQ_450;
9518 data = 0;
9519 break;
9520 case 540000:
9521 val |= LCPLL_CLK_FREQ_54O_BDW;
9522 data = 1;
9523 break;
9524 case 337500:
9525 val |= LCPLL_CLK_FREQ_337_5_BDW;
9526 data = 2;
9527 break;
9528 case 675000:
9529 val |= LCPLL_CLK_FREQ_675_BDW;
9530 data = 3;
9531 break;
9532 default:
9533 WARN(1, "invalid cdclk frequency\n");
9534 return;
9535 }
9536
9537 I915_WRITE(LCPLL_CTL, val);
9538
9539 val = I915_READ(LCPLL_CTL);
9540 val &= ~LCPLL_CD_SOURCE_FCLK;
9541 I915_WRITE(LCPLL_CTL, val);
9542
9543 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9544 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9545 DRM_ERROR("Switching back to LCPLL failed\n");
9546
9547 mutex_lock(&dev_priv->rps.hw_lock);
9548 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9549 mutex_unlock(&dev_priv->rps.hw_lock);
9550
9551 intel_update_cdclk(dev);
9552
9553 WARN(cdclk != dev_priv->cdclk_freq,
9554 "cdclk requested %d kHz but got %d kHz\n",
9555 cdclk, dev_priv->cdclk_freq);
9556 }
9557
9558 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9559 {
9560 struct drm_i915_private *dev_priv = to_i915(state->dev);
9561 int max_pixclk = ilk_max_pixel_rate(state);
9562 int cdclk;
9563
9564 /*
9565 * FIXME should also account for plane ratio
9566 * once 64bpp pixel formats are supported.
9567 */
9568 if (max_pixclk > 540000)
9569 cdclk = 675000;
9570 else if (max_pixclk > 450000)
9571 cdclk = 540000;
9572 else if (max_pixclk > 337500)
9573 cdclk = 450000;
9574 else
9575 cdclk = 337500;
9576
9577 /*
9578 * FIXME move the cdclk caclulation to
9579 * compute_config() so we can fail gracegully.
9580 */
9581 if (cdclk > dev_priv->max_cdclk_freq) {
9582 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9583 cdclk, dev_priv->max_cdclk_freq);
9584 cdclk = dev_priv->max_cdclk_freq;
9585 }
9586
9587 to_intel_atomic_state(state)->cdclk = cdclk;
9588
9589 return 0;
9590 }
9591
9592 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9593 {
9594 struct drm_device *dev = old_state->dev;
9595 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9596
9597 broadwell_set_cdclk(dev, req_cdclk);
9598 }
9599
9600 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9601 struct intel_crtc_state *crtc_state)
9602 {
9603 if (!intel_ddi_pll_select(crtc, crtc_state))
9604 return -EINVAL;
9605
9606 crtc->lowfreq_avail = false;
9607
9608 return 0;
9609 }
9610
9611 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9612 enum port port,
9613 struct intel_crtc_state *pipe_config)
9614 {
9615 switch (port) {
9616 case PORT_A:
9617 pipe_config->ddi_pll_sel = SKL_DPLL0;
9618 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9619 break;
9620 case PORT_B:
9621 pipe_config->ddi_pll_sel = SKL_DPLL1;
9622 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9623 break;
9624 case PORT_C:
9625 pipe_config->ddi_pll_sel = SKL_DPLL2;
9626 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9627 break;
9628 default:
9629 DRM_ERROR("Incorrect port type\n");
9630 }
9631 }
9632
9633 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9634 enum port port,
9635 struct intel_crtc_state *pipe_config)
9636 {
9637 u32 temp, dpll_ctl1;
9638
9639 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9640 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9641
9642 switch (pipe_config->ddi_pll_sel) {
9643 case SKL_DPLL0:
9644 /*
9645 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9646 * of the shared DPLL framework and thus needs to be read out
9647 * separately
9648 */
9649 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9650 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9651 break;
9652 case SKL_DPLL1:
9653 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9654 break;
9655 case SKL_DPLL2:
9656 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9657 break;
9658 case SKL_DPLL3:
9659 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9660 break;
9661 }
9662 }
9663
9664 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9665 enum port port,
9666 struct intel_crtc_state *pipe_config)
9667 {
9668 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9669
9670 switch (pipe_config->ddi_pll_sel) {
9671 case PORT_CLK_SEL_WRPLL1:
9672 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9673 break;
9674 case PORT_CLK_SEL_WRPLL2:
9675 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9676 break;
9677 }
9678 }
9679
9680 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9681 struct intel_crtc_state *pipe_config)
9682 {
9683 struct drm_device *dev = crtc->base.dev;
9684 struct drm_i915_private *dev_priv = dev->dev_private;
9685 struct intel_shared_dpll *pll;
9686 enum port port;
9687 uint32_t tmp;
9688
9689 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9690
9691 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9692
9693 if (IS_SKYLAKE(dev))
9694 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9695 else if (IS_BROXTON(dev))
9696 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9697 else
9698 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9699
9700 if (pipe_config->shared_dpll >= 0) {
9701 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9702
9703 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9704 &pipe_config->dpll_hw_state));
9705 }
9706
9707 /*
9708 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9709 * DDI E. So just check whether this pipe is wired to DDI E and whether
9710 * the PCH transcoder is on.
9711 */
9712 if (INTEL_INFO(dev)->gen < 9 &&
9713 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9714 pipe_config->has_pch_encoder = true;
9715
9716 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9717 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9718 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9719
9720 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9721 }
9722 }
9723
9724 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9725 struct intel_crtc_state *pipe_config)
9726 {
9727 struct drm_device *dev = crtc->base.dev;
9728 struct drm_i915_private *dev_priv = dev->dev_private;
9729 enum intel_display_power_domain pfit_domain;
9730 uint32_t tmp;
9731
9732 if (!intel_display_power_is_enabled(dev_priv,
9733 POWER_DOMAIN_PIPE(crtc->pipe)))
9734 return false;
9735
9736 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9737 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9738
9739 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9740 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9741 enum pipe trans_edp_pipe;
9742 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9743 default:
9744 WARN(1, "unknown pipe linked to edp transcoder\n");
9745 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9746 case TRANS_DDI_EDP_INPUT_A_ON:
9747 trans_edp_pipe = PIPE_A;
9748 break;
9749 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9750 trans_edp_pipe = PIPE_B;
9751 break;
9752 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9753 trans_edp_pipe = PIPE_C;
9754 break;
9755 }
9756
9757 if (trans_edp_pipe == crtc->pipe)
9758 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9759 }
9760
9761 if (!intel_display_power_is_enabled(dev_priv,
9762 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9763 return false;
9764
9765 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9766 if (!(tmp & PIPECONF_ENABLE))
9767 return false;
9768
9769 haswell_get_ddi_port_state(crtc, pipe_config);
9770
9771 intel_get_pipe_timings(crtc, pipe_config);
9772
9773 if (INTEL_INFO(dev)->gen >= 9) {
9774 skl_init_scalers(dev, crtc, pipe_config);
9775 }
9776
9777 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9778
9779 if (INTEL_INFO(dev)->gen >= 9) {
9780 pipe_config->scaler_state.scaler_id = -1;
9781 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9782 }
9783
9784 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9785 if (INTEL_INFO(dev)->gen == 9)
9786 skylake_get_pfit_config(crtc, pipe_config);
9787 else if (INTEL_INFO(dev)->gen < 9)
9788 ironlake_get_pfit_config(crtc, pipe_config);
9789 else
9790 MISSING_CASE(INTEL_INFO(dev)->gen);
9791 }
9792
9793 if (IS_HASWELL(dev))
9794 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9795 (I915_READ(IPS_CTL) & IPS_ENABLE);
9796
9797 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9798 pipe_config->pixel_multiplier =
9799 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9800 } else {
9801 pipe_config->pixel_multiplier = 1;
9802 }
9803
9804 return true;
9805 }
9806
9807 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9808 {
9809 struct drm_device *dev = crtc->dev;
9810 struct drm_i915_private *dev_priv = dev->dev_private;
9811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9812 uint32_t cntl = 0, size = 0;
9813
9814 if (base) {
9815 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9816 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9817 unsigned int stride = roundup_pow_of_two(width) * 4;
9818
9819 switch (stride) {
9820 default:
9821 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9822 width, stride);
9823 stride = 256;
9824 /* fallthrough */
9825 case 256:
9826 case 512:
9827 case 1024:
9828 case 2048:
9829 break;
9830 }
9831
9832 cntl |= CURSOR_ENABLE |
9833 CURSOR_GAMMA_ENABLE |
9834 CURSOR_FORMAT_ARGB |
9835 CURSOR_STRIDE(stride);
9836
9837 size = (height << 12) | width;
9838 }
9839
9840 if (intel_crtc->cursor_cntl != 0 &&
9841 (intel_crtc->cursor_base != base ||
9842 intel_crtc->cursor_size != size ||
9843 intel_crtc->cursor_cntl != cntl)) {
9844 /* On these chipsets we can only modify the base/size/stride
9845 * whilst the cursor is disabled.
9846 */
9847 I915_WRITE(_CURACNTR, 0);
9848 POSTING_READ(_CURACNTR);
9849 intel_crtc->cursor_cntl = 0;
9850 }
9851
9852 if (intel_crtc->cursor_base != base) {
9853 I915_WRITE(_CURABASE, base);
9854 intel_crtc->cursor_base = base;
9855 }
9856
9857 if (intel_crtc->cursor_size != size) {
9858 I915_WRITE(CURSIZE, size);
9859 intel_crtc->cursor_size = size;
9860 }
9861
9862 if (intel_crtc->cursor_cntl != cntl) {
9863 I915_WRITE(_CURACNTR, cntl);
9864 POSTING_READ(_CURACNTR);
9865 intel_crtc->cursor_cntl = cntl;
9866 }
9867 }
9868
9869 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9870 {
9871 struct drm_device *dev = crtc->dev;
9872 struct drm_i915_private *dev_priv = dev->dev_private;
9873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9874 int pipe = intel_crtc->pipe;
9875 uint32_t cntl;
9876
9877 cntl = 0;
9878 if (base) {
9879 cntl = MCURSOR_GAMMA_ENABLE;
9880 switch (intel_crtc->base.cursor->state->crtc_w) {
9881 case 64:
9882 cntl |= CURSOR_MODE_64_ARGB_AX;
9883 break;
9884 case 128:
9885 cntl |= CURSOR_MODE_128_ARGB_AX;
9886 break;
9887 case 256:
9888 cntl |= CURSOR_MODE_256_ARGB_AX;
9889 break;
9890 default:
9891 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9892 return;
9893 }
9894 cntl |= pipe << 28; /* Connect to correct pipe */
9895
9896 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9897 cntl |= CURSOR_PIPE_CSC_ENABLE;
9898 }
9899
9900 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9901 cntl |= CURSOR_ROTATE_180;
9902
9903 if (intel_crtc->cursor_cntl != cntl) {
9904 I915_WRITE(CURCNTR(pipe), cntl);
9905 POSTING_READ(CURCNTR(pipe));
9906 intel_crtc->cursor_cntl = cntl;
9907 }
9908
9909 /* and commit changes on next vblank */
9910 I915_WRITE(CURBASE(pipe), base);
9911 POSTING_READ(CURBASE(pipe));
9912
9913 intel_crtc->cursor_base = base;
9914 }
9915
9916 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9917 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9918 bool on)
9919 {
9920 struct drm_device *dev = crtc->dev;
9921 struct drm_i915_private *dev_priv = dev->dev_private;
9922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9923 int pipe = intel_crtc->pipe;
9924 int x = crtc->cursor_x;
9925 int y = crtc->cursor_y;
9926 u32 base = 0, pos = 0;
9927
9928 if (on)
9929 base = intel_crtc->cursor_addr;
9930
9931 if (x >= intel_crtc->config->pipe_src_w)
9932 base = 0;
9933
9934 if (y >= intel_crtc->config->pipe_src_h)
9935 base = 0;
9936
9937 if (x < 0) {
9938 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9939 base = 0;
9940
9941 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9942 x = -x;
9943 }
9944 pos |= x << CURSOR_X_SHIFT;
9945
9946 if (y < 0) {
9947 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9948 base = 0;
9949
9950 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9951 y = -y;
9952 }
9953 pos |= y << CURSOR_Y_SHIFT;
9954
9955 if (base == 0 && intel_crtc->cursor_base == 0)
9956 return;
9957
9958 I915_WRITE(CURPOS(pipe), pos);
9959
9960 /* ILK+ do this automagically */
9961 if (HAS_GMCH_DISPLAY(dev) &&
9962 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9963 base += (intel_crtc->base.cursor->state->crtc_h *
9964 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9965 }
9966
9967 if (IS_845G(dev) || IS_I865G(dev))
9968 i845_update_cursor(crtc, base);
9969 else
9970 i9xx_update_cursor(crtc, base);
9971 }
9972
9973 static bool cursor_size_ok(struct drm_device *dev,
9974 uint32_t width, uint32_t height)
9975 {
9976 if (width == 0 || height == 0)
9977 return false;
9978
9979 /*
9980 * 845g/865g are special in that they are only limited by
9981 * the width of their cursors, the height is arbitrary up to
9982 * the precision of the register. Everything else requires
9983 * square cursors, limited to a few power-of-two sizes.
9984 */
9985 if (IS_845G(dev) || IS_I865G(dev)) {
9986 if ((width & 63) != 0)
9987 return false;
9988
9989 if (width > (IS_845G(dev) ? 64 : 512))
9990 return false;
9991
9992 if (height > 1023)
9993 return false;
9994 } else {
9995 switch (width | height) {
9996 case 256:
9997 case 128:
9998 if (IS_GEN2(dev))
9999 return false;
10000 case 64:
10001 break;
10002 default:
10003 return false;
10004 }
10005 }
10006
10007 return true;
10008 }
10009
10010 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10011 u16 *blue, uint32_t start, uint32_t size)
10012 {
10013 int end = (start + size > 256) ? 256 : start + size, i;
10014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10015
10016 for (i = start; i < end; i++) {
10017 intel_crtc->lut_r[i] = red[i] >> 8;
10018 intel_crtc->lut_g[i] = green[i] >> 8;
10019 intel_crtc->lut_b[i] = blue[i] >> 8;
10020 }
10021
10022 intel_crtc_load_lut(crtc);
10023 }
10024
10025 /* VESA 640x480x72Hz mode to set on the pipe */
10026 static struct drm_display_mode load_detect_mode = {
10027 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10028 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10029 };
10030
10031 struct drm_framebuffer *
10032 __intel_framebuffer_create(struct drm_device *dev,
10033 struct drm_mode_fb_cmd2 *mode_cmd,
10034 struct drm_i915_gem_object *obj)
10035 {
10036 struct intel_framebuffer *intel_fb;
10037 int ret;
10038
10039 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10040 if (!intel_fb) {
10041 drm_gem_object_unreference(&obj->base);
10042 return ERR_PTR(-ENOMEM);
10043 }
10044
10045 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10046 if (ret)
10047 goto err;
10048
10049 return &intel_fb->base;
10050 err:
10051 drm_gem_object_unreference(&obj->base);
10052 kfree(intel_fb);
10053
10054 return ERR_PTR(ret);
10055 }
10056
10057 static struct drm_framebuffer *
10058 intel_framebuffer_create(struct drm_device *dev,
10059 struct drm_mode_fb_cmd2 *mode_cmd,
10060 struct drm_i915_gem_object *obj)
10061 {
10062 struct drm_framebuffer *fb;
10063 int ret;
10064
10065 ret = i915_mutex_lock_interruptible(dev);
10066 if (ret)
10067 return ERR_PTR(ret);
10068 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10069 mutex_unlock(&dev->struct_mutex);
10070
10071 return fb;
10072 }
10073
10074 static u32
10075 intel_framebuffer_pitch_for_width(int width, int bpp)
10076 {
10077 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10078 return ALIGN(pitch, 64);
10079 }
10080
10081 static u32
10082 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10083 {
10084 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10085 return PAGE_ALIGN(pitch * mode->vdisplay);
10086 }
10087
10088 static struct drm_framebuffer *
10089 intel_framebuffer_create_for_mode(struct drm_device *dev,
10090 struct drm_display_mode *mode,
10091 int depth, int bpp)
10092 {
10093 struct drm_i915_gem_object *obj;
10094 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10095
10096 obj = i915_gem_alloc_object(dev,
10097 intel_framebuffer_size_for_mode(mode, bpp));
10098 if (obj == NULL)
10099 return ERR_PTR(-ENOMEM);
10100
10101 mode_cmd.width = mode->hdisplay;
10102 mode_cmd.height = mode->vdisplay;
10103 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10104 bpp);
10105 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10106
10107 return intel_framebuffer_create(dev, &mode_cmd, obj);
10108 }
10109
10110 static struct drm_framebuffer *
10111 mode_fits_in_fbdev(struct drm_device *dev,
10112 struct drm_display_mode *mode)
10113 {
10114 #ifdef CONFIG_DRM_I915_FBDEV
10115 struct drm_i915_private *dev_priv = dev->dev_private;
10116 struct drm_i915_gem_object *obj;
10117 struct drm_framebuffer *fb;
10118
10119 if (!dev_priv->fbdev)
10120 return NULL;
10121
10122 if (!dev_priv->fbdev->fb)
10123 return NULL;
10124
10125 obj = dev_priv->fbdev->fb->obj;
10126 BUG_ON(!obj);
10127
10128 fb = &dev_priv->fbdev->fb->base;
10129 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10130 fb->bits_per_pixel))
10131 return NULL;
10132
10133 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10134 return NULL;
10135
10136 return fb;
10137 #else
10138 return NULL;
10139 #endif
10140 }
10141
10142 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10143 struct drm_crtc *crtc,
10144 struct drm_display_mode *mode,
10145 struct drm_framebuffer *fb,
10146 int x, int y)
10147 {
10148 struct drm_plane_state *plane_state;
10149 int hdisplay, vdisplay;
10150 int ret;
10151
10152 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10153 if (IS_ERR(plane_state))
10154 return PTR_ERR(plane_state);
10155
10156 if (mode)
10157 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10158 else
10159 hdisplay = vdisplay = 0;
10160
10161 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10162 if (ret)
10163 return ret;
10164 drm_atomic_set_fb_for_plane(plane_state, fb);
10165 plane_state->crtc_x = 0;
10166 plane_state->crtc_y = 0;
10167 plane_state->crtc_w = hdisplay;
10168 plane_state->crtc_h = vdisplay;
10169 plane_state->src_x = x << 16;
10170 plane_state->src_y = y << 16;
10171 plane_state->src_w = hdisplay << 16;
10172 plane_state->src_h = vdisplay << 16;
10173
10174 return 0;
10175 }
10176
10177 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10178 struct drm_display_mode *mode,
10179 struct intel_load_detect_pipe *old,
10180 struct drm_modeset_acquire_ctx *ctx)
10181 {
10182 struct intel_crtc *intel_crtc;
10183 struct intel_encoder *intel_encoder =
10184 intel_attached_encoder(connector);
10185 struct drm_crtc *possible_crtc;
10186 struct drm_encoder *encoder = &intel_encoder->base;
10187 struct drm_crtc *crtc = NULL;
10188 struct drm_device *dev = encoder->dev;
10189 struct drm_framebuffer *fb;
10190 struct drm_mode_config *config = &dev->mode_config;
10191 struct drm_atomic_state *state = NULL;
10192 struct drm_connector_state *connector_state;
10193 struct intel_crtc_state *crtc_state;
10194 int ret, i = -1;
10195
10196 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10197 connector->base.id, connector->name,
10198 encoder->base.id, encoder->name);
10199
10200 retry:
10201 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10202 if (ret)
10203 goto fail_unlock;
10204
10205 /*
10206 * Algorithm gets a little messy:
10207 *
10208 * - if the connector already has an assigned crtc, use it (but make
10209 * sure it's on first)
10210 *
10211 * - try to find the first unused crtc that can drive this connector,
10212 * and use that if we find one
10213 */
10214
10215 /* See if we already have a CRTC for this connector */
10216 if (encoder->crtc) {
10217 crtc = encoder->crtc;
10218
10219 ret = drm_modeset_lock(&crtc->mutex, ctx);
10220 if (ret)
10221 goto fail_unlock;
10222 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10223 if (ret)
10224 goto fail_unlock;
10225
10226 old->dpms_mode = connector->dpms;
10227 old->load_detect_temp = false;
10228
10229 /* Make sure the crtc and connector are running */
10230 if (connector->dpms != DRM_MODE_DPMS_ON)
10231 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10232
10233 return true;
10234 }
10235
10236 /* Find an unused one (if possible) */
10237 for_each_crtc(dev, possible_crtc) {
10238 i++;
10239 if (!(encoder->possible_crtcs & (1 << i)))
10240 continue;
10241 if (possible_crtc->state->enable)
10242 continue;
10243 /* This can occur when applying the pipe A quirk on resume. */
10244 if (to_intel_crtc(possible_crtc)->new_enabled)
10245 continue;
10246
10247 crtc = possible_crtc;
10248 break;
10249 }
10250
10251 /*
10252 * If we didn't find an unused CRTC, don't use any.
10253 */
10254 if (!crtc) {
10255 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10256 goto fail_unlock;
10257 }
10258
10259 ret = drm_modeset_lock(&crtc->mutex, ctx);
10260 if (ret)
10261 goto fail_unlock;
10262 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10263 if (ret)
10264 goto fail_unlock;
10265 intel_encoder->new_crtc = to_intel_crtc(crtc);
10266 to_intel_connector(connector)->new_encoder = intel_encoder;
10267
10268 intel_crtc = to_intel_crtc(crtc);
10269 intel_crtc->new_enabled = true;
10270 old->dpms_mode = connector->dpms;
10271 old->load_detect_temp = true;
10272 old->release_fb = NULL;
10273
10274 state = drm_atomic_state_alloc(dev);
10275 if (!state)
10276 return false;
10277
10278 state->acquire_ctx = ctx;
10279
10280 connector_state = drm_atomic_get_connector_state(state, connector);
10281 if (IS_ERR(connector_state)) {
10282 ret = PTR_ERR(connector_state);
10283 goto fail;
10284 }
10285
10286 connector_state->crtc = crtc;
10287 connector_state->best_encoder = &intel_encoder->base;
10288
10289 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10290 if (IS_ERR(crtc_state)) {
10291 ret = PTR_ERR(crtc_state);
10292 goto fail;
10293 }
10294
10295 crtc_state->base.active = crtc_state->base.enable = true;
10296
10297 if (!mode)
10298 mode = &load_detect_mode;
10299
10300 /* We need a framebuffer large enough to accommodate all accesses
10301 * that the plane may generate whilst we perform load detection.
10302 * We can not rely on the fbcon either being present (we get called
10303 * during its initialisation to detect all boot displays, or it may
10304 * not even exist) or that it is large enough to satisfy the
10305 * requested mode.
10306 */
10307 fb = mode_fits_in_fbdev(dev, mode);
10308 if (fb == NULL) {
10309 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10310 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10311 old->release_fb = fb;
10312 } else
10313 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10314 if (IS_ERR(fb)) {
10315 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10316 goto fail;
10317 }
10318
10319 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10320 if (ret)
10321 goto fail;
10322
10323 drm_mode_copy(&crtc_state->base.mode, mode);
10324
10325 if (intel_set_mode(state)) {
10326 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10327 if (old->release_fb)
10328 old->release_fb->funcs->destroy(old->release_fb);
10329 goto fail;
10330 }
10331 crtc->primary->crtc = crtc;
10332
10333 /* let the connector get through one full cycle before testing */
10334 intel_wait_for_vblank(dev, intel_crtc->pipe);
10335 return true;
10336
10337 fail:
10338 intel_crtc->new_enabled = crtc->state->enable;
10339 fail_unlock:
10340 drm_atomic_state_free(state);
10341 state = NULL;
10342
10343 if (ret == -EDEADLK) {
10344 drm_modeset_backoff(ctx);
10345 goto retry;
10346 }
10347
10348 return false;
10349 }
10350
10351 void intel_release_load_detect_pipe(struct drm_connector *connector,
10352 struct intel_load_detect_pipe *old,
10353 struct drm_modeset_acquire_ctx *ctx)
10354 {
10355 struct drm_device *dev = connector->dev;
10356 struct intel_encoder *intel_encoder =
10357 intel_attached_encoder(connector);
10358 struct drm_encoder *encoder = &intel_encoder->base;
10359 struct drm_crtc *crtc = encoder->crtc;
10360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10361 struct drm_atomic_state *state;
10362 struct drm_connector_state *connector_state;
10363 struct intel_crtc_state *crtc_state;
10364 int ret;
10365
10366 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10367 connector->base.id, connector->name,
10368 encoder->base.id, encoder->name);
10369
10370 if (old->load_detect_temp) {
10371 state = drm_atomic_state_alloc(dev);
10372 if (!state)
10373 goto fail;
10374
10375 state->acquire_ctx = ctx;
10376
10377 connector_state = drm_atomic_get_connector_state(state, connector);
10378 if (IS_ERR(connector_state))
10379 goto fail;
10380
10381 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10382 if (IS_ERR(crtc_state))
10383 goto fail;
10384
10385 to_intel_connector(connector)->new_encoder = NULL;
10386 intel_encoder->new_crtc = NULL;
10387 intel_crtc->new_enabled = false;
10388
10389 connector_state->best_encoder = NULL;
10390 connector_state->crtc = NULL;
10391
10392 crtc_state->base.enable = crtc_state->base.active = false;
10393
10394 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10395 0, 0);
10396 if (ret)
10397 goto fail;
10398
10399 ret = intel_set_mode(state);
10400 if (ret)
10401 goto fail;
10402
10403 if (old->release_fb) {
10404 drm_framebuffer_unregister_private(old->release_fb);
10405 drm_framebuffer_unreference(old->release_fb);
10406 }
10407
10408 return;
10409 }
10410
10411 /* Switch crtc and encoder back off if necessary */
10412 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10413 connector->funcs->dpms(connector, old->dpms_mode);
10414
10415 return;
10416 fail:
10417 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10418 drm_atomic_state_free(state);
10419 }
10420
10421 static int i9xx_pll_refclk(struct drm_device *dev,
10422 const struct intel_crtc_state *pipe_config)
10423 {
10424 struct drm_i915_private *dev_priv = dev->dev_private;
10425 u32 dpll = pipe_config->dpll_hw_state.dpll;
10426
10427 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10428 return dev_priv->vbt.lvds_ssc_freq;
10429 else if (HAS_PCH_SPLIT(dev))
10430 return 120000;
10431 else if (!IS_GEN2(dev))
10432 return 96000;
10433 else
10434 return 48000;
10435 }
10436
10437 /* Returns the clock of the currently programmed mode of the given pipe. */
10438 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10439 struct intel_crtc_state *pipe_config)
10440 {
10441 struct drm_device *dev = crtc->base.dev;
10442 struct drm_i915_private *dev_priv = dev->dev_private;
10443 int pipe = pipe_config->cpu_transcoder;
10444 u32 dpll = pipe_config->dpll_hw_state.dpll;
10445 u32 fp;
10446 intel_clock_t clock;
10447 int refclk = i9xx_pll_refclk(dev, pipe_config);
10448
10449 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10450 fp = pipe_config->dpll_hw_state.fp0;
10451 else
10452 fp = pipe_config->dpll_hw_state.fp1;
10453
10454 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10455 if (IS_PINEVIEW(dev)) {
10456 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10457 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10458 } else {
10459 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10460 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10461 }
10462
10463 if (!IS_GEN2(dev)) {
10464 if (IS_PINEVIEW(dev))
10465 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10466 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10467 else
10468 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10469 DPLL_FPA01_P1_POST_DIV_SHIFT);
10470
10471 switch (dpll & DPLL_MODE_MASK) {
10472 case DPLLB_MODE_DAC_SERIAL:
10473 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10474 5 : 10;
10475 break;
10476 case DPLLB_MODE_LVDS:
10477 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10478 7 : 14;
10479 break;
10480 default:
10481 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10482 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10483 return;
10484 }
10485
10486 if (IS_PINEVIEW(dev))
10487 pineview_clock(refclk, &clock);
10488 else
10489 i9xx_clock(refclk, &clock);
10490 } else {
10491 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10492 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10493
10494 if (is_lvds) {
10495 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10496 DPLL_FPA01_P1_POST_DIV_SHIFT);
10497
10498 if (lvds & LVDS_CLKB_POWER_UP)
10499 clock.p2 = 7;
10500 else
10501 clock.p2 = 14;
10502 } else {
10503 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10504 clock.p1 = 2;
10505 else {
10506 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10507 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10508 }
10509 if (dpll & PLL_P2_DIVIDE_BY_4)
10510 clock.p2 = 4;
10511 else
10512 clock.p2 = 2;
10513 }
10514
10515 i9xx_clock(refclk, &clock);
10516 }
10517
10518 /*
10519 * This value includes pixel_multiplier. We will use
10520 * port_clock to compute adjusted_mode.crtc_clock in the
10521 * encoder's get_config() function.
10522 */
10523 pipe_config->port_clock = clock.dot;
10524 }
10525
10526 int intel_dotclock_calculate(int link_freq,
10527 const struct intel_link_m_n *m_n)
10528 {
10529 /*
10530 * The calculation for the data clock is:
10531 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10532 * But we want to avoid losing precison if possible, so:
10533 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10534 *
10535 * and the link clock is simpler:
10536 * link_clock = (m * link_clock) / n
10537 */
10538
10539 if (!m_n->link_n)
10540 return 0;
10541
10542 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10543 }
10544
10545 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10546 struct intel_crtc_state *pipe_config)
10547 {
10548 struct drm_device *dev = crtc->base.dev;
10549
10550 /* read out port_clock from the DPLL */
10551 i9xx_crtc_clock_get(crtc, pipe_config);
10552
10553 /*
10554 * This value does not include pixel_multiplier.
10555 * We will check that port_clock and adjusted_mode.crtc_clock
10556 * agree once we know their relationship in the encoder's
10557 * get_config() function.
10558 */
10559 pipe_config->base.adjusted_mode.crtc_clock =
10560 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10561 &pipe_config->fdi_m_n);
10562 }
10563
10564 /** Returns the currently programmed mode of the given pipe. */
10565 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10566 struct drm_crtc *crtc)
10567 {
10568 struct drm_i915_private *dev_priv = dev->dev_private;
10569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10570 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10571 struct drm_display_mode *mode;
10572 struct intel_crtc_state pipe_config;
10573 int htot = I915_READ(HTOTAL(cpu_transcoder));
10574 int hsync = I915_READ(HSYNC(cpu_transcoder));
10575 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10576 int vsync = I915_READ(VSYNC(cpu_transcoder));
10577 enum pipe pipe = intel_crtc->pipe;
10578
10579 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10580 if (!mode)
10581 return NULL;
10582
10583 /*
10584 * Construct a pipe_config sufficient for getting the clock info
10585 * back out of crtc_clock_get.
10586 *
10587 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10588 * to use a real value here instead.
10589 */
10590 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10591 pipe_config.pixel_multiplier = 1;
10592 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10593 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10594 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10595 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10596
10597 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10598 mode->hdisplay = (htot & 0xffff) + 1;
10599 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10600 mode->hsync_start = (hsync & 0xffff) + 1;
10601 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10602 mode->vdisplay = (vtot & 0xffff) + 1;
10603 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10604 mode->vsync_start = (vsync & 0xffff) + 1;
10605 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10606
10607 drm_mode_set_name(mode);
10608
10609 return mode;
10610 }
10611
10612 void intel_mark_busy(struct drm_device *dev)
10613 {
10614 struct drm_i915_private *dev_priv = dev->dev_private;
10615
10616 if (dev_priv->mm.busy)
10617 return;
10618
10619 intel_runtime_pm_get(dev_priv);
10620 i915_update_gfx_val(dev_priv);
10621 if (INTEL_INFO(dev)->gen >= 6)
10622 gen6_rps_busy(dev_priv);
10623 dev_priv->mm.busy = true;
10624 }
10625
10626 void intel_mark_idle(struct drm_device *dev)
10627 {
10628 struct drm_i915_private *dev_priv = dev->dev_private;
10629
10630 if (!dev_priv->mm.busy)
10631 return;
10632
10633 dev_priv->mm.busy = false;
10634
10635 if (INTEL_INFO(dev)->gen >= 6)
10636 gen6_rps_idle(dev->dev_private);
10637
10638 intel_runtime_pm_put(dev_priv);
10639 }
10640
10641 static void intel_crtc_destroy(struct drm_crtc *crtc)
10642 {
10643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10644 struct drm_device *dev = crtc->dev;
10645 struct intel_unpin_work *work;
10646
10647 spin_lock_irq(&dev->event_lock);
10648 work = intel_crtc->unpin_work;
10649 intel_crtc->unpin_work = NULL;
10650 spin_unlock_irq(&dev->event_lock);
10651
10652 if (work) {
10653 cancel_work_sync(&work->work);
10654 kfree(work);
10655 }
10656
10657 drm_crtc_cleanup(crtc);
10658
10659 kfree(intel_crtc);
10660 }
10661
10662 static void intel_unpin_work_fn(struct work_struct *__work)
10663 {
10664 struct intel_unpin_work *work =
10665 container_of(__work, struct intel_unpin_work, work);
10666 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10667 struct drm_device *dev = crtc->base.dev;
10668 struct drm_plane *primary = crtc->base.primary;
10669
10670 mutex_lock(&dev->struct_mutex);
10671 intel_unpin_fb_obj(work->old_fb, primary->state);
10672 drm_gem_object_unreference(&work->pending_flip_obj->base);
10673
10674 intel_fbc_update(dev);
10675
10676 if (work->flip_queued_req)
10677 i915_gem_request_assign(&work->flip_queued_req, NULL);
10678 mutex_unlock(&dev->struct_mutex);
10679
10680 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10681 drm_framebuffer_unreference(work->old_fb);
10682
10683 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10684 atomic_dec(&crtc->unpin_work_count);
10685
10686 kfree(work);
10687 }
10688
10689 static void do_intel_finish_page_flip(struct drm_device *dev,
10690 struct drm_crtc *crtc)
10691 {
10692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10693 struct intel_unpin_work *work;
10694 unsigned long flags;
10695
10696 /* Ignore early vblank irqs */
10697 if (intel_crtc == NULL)
10698 return;
10699
10700 /*
10701 * This is called both by irq handlers and the reset code (to complete
10702 * lost pageflips) so needs the full irqsave spinlocks.
10703 */
10704 spin_lock_irqsave(&dev->event_lock, flags);
10705 work = intel_crtc->unpin_work;
10706
10707 /* Ensure we don't miss a work->pending update ... */
10708 smp_rmb();
10709
10710 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10711 spin_unlock_irqrestore(&dev->event_lock, flags);
10712 return;
10713 }
10714
10715 page_flip_completed(intel_crtc);
10716
10717 spin_unlock_irqrestore(&dev->event_lock, flags);
10718 }
10719
10720 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10721 {
10722 struct drm_i915_private *dev_priv = dev->dev_private;
10723 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10724
10725 do_intel_finish_page_flip(dev, crtc);
10726 }
10727
10728 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10729 {
10730 struct drm_i915_private *dev_priv = dev->dev_private;
10731 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10732
10733 do_intel_finish_page_flip(dev, crtc);
10734 }
10735
10736 /* Is 'a' after or equal to 'b'? */
10737 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10738 {
10739 return !((a - b) & 0x80000000);
10740 }
10741
10742 static bool page_flip_finished(struct intel_crtc *crtc)
10743 {
10744 struct drm_device *dev = crtc->base.dev;
10745 struct drm_i915_private *dev_priv = dev->dev_private;
10746
10747 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10748 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10749 return true;
10750
10751 /*
10752 * The relevant registers doen't exist on pre-ctg.
10753 * As the flip done interrupt doesn't trigger for mmio
10754 * flips on gmch platforms, a flip count check isn't
10755 * really needed there. But since ctg has the registers,
10756 * include it in the check anyway.
10757 */
10758 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10759 return true;
10760
10761 /*
10762 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10763 * used the same base address. In that case the mmio flip might
10764 * have completed, but the CS hasn't even executed the flip yet.
10765 *
10766 * A flip count check isn't enough as the CS might have updated
10767 * the base address just after start of vblank, but before we
10768 * managed to process the interrupt. This means we'd complete the
10769 * CS flip too soon.
10770 *
10771 * Combining both checks should get us a good enough result. It may
10772 * still happen that the CS flip has been executed, but has not
10773 * yet actually completed. But in case the base address is the same
10774 * anyway, we don't really care.
10775 */
10776 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10777 crtc->unpin_work->gtt_offset &&
10778 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10779 crtc->unpin_work->flip_count);
10780 }
10781
10782 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10783 {
10784 struct drm_i915_private *dev_priv = dev->dev_private;
10785 struct intel_crtc *intel_crtc =
10786 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10787 unsigned long flags;
10788
10789
10790 /*
10791 * This is called both by irq handlers and the reset code (to complete
10792 * lost pageflips) so needs the full irqsave spinlocks.
10793 *
10794 * NB: An MMIO update of the plane base pointer will also
10795 * generate a page-flip completion irq, i.e. every modeset
10796 * is also accompanied by a spurious intel_prepare_page_flip().
10797 */
10798 spin_lock_irqsave(&dev->event_lock, flags);
10799 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10800 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10801 spin_unlock_irqrestore(&dev->event_lock, flags);
10802 }
10803
10804 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10805 {
10806 /* Ensure that the work item is consistent when activating it ... */
10807 smp_wmb();
10808 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10809 /* and that it is marked active as soon as the irq could fire. */
10810 smp_wmb();
10811 }
10812
10813 static int intel_gen2_queue_flip(struct drm_device *dev,
10814 struct drm_crtc *crtc,
10815 struct drm_framebuffer *fb,
10816 struct drm_i915_gem_object *obj,
10817 struct drm_i915_gem_request *req,
10818 uint32_t flags)
10819 {
10820 struct intel_engine_cs *ring = req->ring;
10821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10822 u32 flip_mask;
10823 int ret;
10824
10825 ret = intel_ring_begin(req, 6);
10826 if (ret)
10827 return ret;
10828
10829 /* Can't queue multiple flips, so wait for the previous
10830 * one to finish before executing the next.
10831 */
10832 if (intel_crtc->plane)
10833 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10834 else
10835 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10836 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10837 intel_ring_emit(ring, MI_NOOP);
10838 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10839 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10840 intel_ring_emit(ring, fb->pitches[0]);
10841 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10842 intel_ring_emit(ring, 0); /* aux display base address, unused */
10843
10844 intel_mark_page_flip_active(intel_crtc);
10845 return 0;
10846 }
10847
10848 static int intel_gen3_queue_flip(struct drm_device *dev,
10849 struct drm_crtc *crtc,
10850 struct drm_framebuffer *fb,
10851 struct drm_i915_gem_object *obj,
10852 struct drm_i915_gem_request *req,
10853 uint32_t flags)
10854 {
10855 struct intel_engine_cs *ring = req->ring;
10856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10857 u32 flip_mask;
10858 int ret;
10859
10860 ret = intel_ring_begin(req, 6);
10861 if (ret)
10862 return ret;
10863
10864 if (intel_crtc->plane)
10865 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10866 else
10867 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10868 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10869 intel_ring_emit(ring, MI_NOOP);
10870 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10871 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10872 intel_ring_emit(ring, fb->pitches[0]);
10873 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10874 intel_ring_emit(ring, MI_NOOP);
10875
10876 intel_mark_page_flip_active(intel_crtc);
10877 return 0;
10878 }
10879
10880 static int intel_gen4_queue_flip(struct drm_device *dev,
10881 struct drm_crtc *crtc,
10882 struct drm_framebuffer *fb,
10883 struct drm_i915_gem_object *obj,
10884 struct drm_i915_gem_request *req,
10885 uint32_t flags)
10886 {
10887 struct intel_engine_cs *ring = req->ring;
10888 struct drm_i915_private *dev_priv = dev->dev_private;
10889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10890 uint32_t pf, pipesrc;
10891 int ret;
10892
10893 ret = intel_ring_begin(req, 4);
10894 if (ret)
10895 return ret;
10896
10897 /* i965+ uses the linear or tiled offsets from the
10898 * Display Registers (which do not change across a page-flip)
10899 * so we need only reprogram the base address.
10900 */
10901 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10902 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10903 intel_ring_emit(ring, fb->pitches[0]);
10904 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10905 obj->tiling_mode);
10906
10907 /* XXX Enabling the panel-fitter across page-flip is so far
10908 * untested on non-native modes, so ignore it for now.
10909 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10910 */
10911 pf = 0;
10912 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10913 intel_ring_emit(ring, pf | pipesrc);
10914
10915 intel_mark_page_flip_active(intel_crtc);
10916 return 0;
10917 }
10918
10919 static int intel_gen6_queue_flip(struct drm_device *dev,
10920 struct drm_crtc *crtc,
10921 struct drm_framebuffer *fb,
10922 struct drm_i915_gem_object *obj,
10923 struct drm_i915_gem_request *req,
10924 uint32_t flags)
10925 {
10926 struct intel_engine_cs *ring = req->ring;
10927 struct drm_i915_private *dev_priv = dev->dev_private;
10928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10929 uint32_t pf, pipesrc;
10930 int ret;
10931
10932 ret = intel_ring_begin(req, 4);
10933 if (ret)
10934 return ret;
10935
10936 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10937 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10938 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10939 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10940
10941 /* Contrary to the suggestions in the documentation,
10942 * "Enable Panel Fitter" does not seem to be required when page
10943 * flipping with a non-native mode, and worse causes a normal
10944 * modeset to fail.
10945 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10946 */
10947 pf = 0;
10948 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10949 intel_ring_emit(ring, pf | pipesrc);
10950
10951 intel_mark_page_flip_active(intel_crtc);
10952 return 0;
10953 }
10954
10955 static int intel_gen7_queue_flip(struct drm_device *dev,
10956 struct drm_crtc *crtc,
10957 struct drm_framebuffer *fb,
10958 struct drm_i915_gem_object *obj,
10959 struct drm_i915_gem_request *req,
10960 uint32_t flags)
10961 {
10962 struct intel_engine_cs *ring = req->ring;
10963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10964 uint32_t plane_bit = 0;
10965 int len, ret;
10966
10967 switch (intel_crtc->plane) {
10968 case PLANE_A:
10969 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10970 break;
10971 case PLANE_B:
10972 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10973 break;
10974 case PLANE_C:
10975 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10976 break;
10977 default:
10978 WARN_ONCE(1, "unknown plane in flip command\n");
10979 return -ENODEV;
10980 }
10981
10982 len = 4;
10983 if (ring->id == RCS) {
10984 len += 6;
10985 /*
10986 * On Gen 8, SRM is now taking an extra dword to accommodate
10987 * 48bits addresses, and we need a NOOP for the batch size to
10988 * stay even.
10989 */
10990 if (IS_GEN8(dev))
10991 len += 2;
10992 }
10993
10994 /*
10995 * BSpec MI_DISPLAY_FLIP for IVB:
10996 * "The full packet must be contained within the same cache line."
10997 *
10998 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10999 * cacheline, if we ever start emitting more commands before
11000 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11001 * then do the cacheline alignment, and finally emit the
11002 * MI_DISPLAY_FLIP.
11003 */
11004 ret = intel_ring_cacheline_align(req);
11005 if (ret)
11006 return ret;
11007
11008 ret = intel_ring_begin(req, len);
11009 if (ret)
11010 return ret;
11011
11012 /* Unmask the flip-done completion message. Note that the bspec says that
11013 * we should do this for both the BCS and RCS, and that we must not unmask
11014 * more than one flip event at any time (or ensure that one flip message
11015 * can be sent by waiting for flip-done prior to queueing new flips).
11016 * Experimentation says that BCS works despite DERRMR masking all
11017 * flip-done completion events and that unmasking all planes at once
11018 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11019 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11020 */
11021 if (ring->id == RCS) {
11022 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11023 intel_ring_emit(ring, DERRMR);
11024 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11025 DERRMR_PIPEB_PRI_FLIP_DONE |
11026 DERRMR_PIPEC_PRI_FLIP_DONE));
11027 if (IS_GEN8(dev))
11028 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11029 MI_SRM_LRM_GLOBAL_GTT);
11030 else
11031 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11032 MI_SRM_LRM_GLOBAL_GTT);
11033 intel_ring_emit(ring, DERRMR);
11034 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11035 if (IS_GEN8(dev)) {
11036 intel_ring_emit(ring, 0);
11037 intel_ring_emit(ring, MI_NOOP);
11038 }
11039 }
11040
11041 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11042 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11043 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11044 intel_ring_emit(ring, (MI_NOOP));
11045
11046 intel_mark_page_flip_active(intel_crtc);
11047 return 0;
11048 }
11049
11050 static bool use_mmio_flip(struct intel_engine_cs *ring,
11051 struct drm_i915_gem_object *obj)
11052 {
11053 /*
11054 * This is not being used for older platforms, because
11055 * non-availability of flip done interrupt forces us to use
11056 * CS flips. Older platforms derive flip done using some clever
11057 * tricks involving the flip_pending status bits and vblank irqs.
11058 * So using MMIO flips there would disrupt this mechanism.
11059 */
11060
11061 if (ring == NULL)
11062 return true;
11063
11064 if (INTEL_INFO(ring->dev)->gen < 5)
11065 return false;
11066
11067 if (i915.use_mmio_flip < 0)
11068 return false;
11069 else if (i915.use_mmio_flip > 0)
11070 return true;
11071 else if (i915.enable_execlists)
11072 return true;
11073 else
11074 return ring != i915_gem_request_get_ring(obj->last_write_req);
11075 }
11076
11077 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11078 {
11079 struct drm_device *dev = intel_crtc->base.dev;
11080 struct drm_i915_private *dev_priv = dev->dev_private;
11081 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11082 const enum pipe pipe = intel_crtc->pipe;
11083 u32 ctl, stride;
11084
11085 ctl = I915_READ(PLANE_CTL(pipe, 0));
11086 ctl &= ~PLANE_CTL_TILED_MASK;
11087 switch (fb->modifier[0]) {
11088 case DRM_FORMAT_MOD_NONE:
11089 break;
11090 case I915_FORMAT_MOD_X_TILED:
11091 ctl |= PLANE_CTL_TILED_X;
11092 break;
11093 case I915_FORMAT_MOD_Y_TILED:
11094 ctl |= PLANE_CTL_TILED_Y;
11095 break;
11096 case I915_FORMAT_MOD_Yf_TILED:
11097 ctl |= PLANE_CTL_TILED_YF;
11098 break;
11099 default:
11100 MISSING_CASE(fb->modifier[0]);
11101 }
11102
11103 /*
11104 * The stride is either expressed as a multiple of 64 bytes chunks for
11105 * linear buffers or in number of tiles for tiled buffers.
11106 */
11107 stride = fb->pitches[0] /
11108 intel_fb_stride_alignment(dev, fb->modifier[0],
11109 fb->pixel_format);
11110
11111 /*
11112 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11113 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11114 */
11115 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11116 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11117
11118 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11119 POSTING_READ(PLANE_SURF(pipe, 0));
11120 }
11121
11122 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11123 {
11124 struct drm_device *dev = intel_crtc->base.dev;
11125 struct drm_i915_private *dev_priv = dev->dev_private;
11126 struct intel_framebuffer *intel_fb =
11127 to_intel_framebuffer(intel_crtc->base.primary->fb);
11128 struct drm_i915_gem_object *obj = intel_fb->obj;
11129 u32 dspcntr;
11130 u32 reg;
11131
11132 reg = DSPCNTR(intel_crtc->plane);
11133 dspcntr = I915_READ(reg);
11134
11135 if (obj->tiling_mode != I915_TILING_NONE)
11136 dspcntr |= DISPPLANE_TILED;
11137 else
11138 dspcntr &= ~DISPPLANE_TILED;
11139
11140 I915_WRITE(reg, dspcntr);
11141
11142 I915_WRITE(DSPSURF(intel_crtc->plane),
11143 intel_crtc->unpin_work->gtt_offset);
11144 POSTING_READ(DSPSURF(intel_crtc->plane));
11145
11146 }
11147
11148 /*
11149 * XXX: This is the temporary way to update the plane registers until we get
11150 * around to using the usual plane update functions for MMIO flips
11151 */
11152 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11153 {
11154 struct drm_device *dev = intel_crtc->base.dev;
11155 bool atomic_update;
11156 u32 start_vbl_count;
11157
11158 intel_mark_page_flip_active(intel_crtc);
11159
11160 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11161
11162 if (INTEL_INFO(dev)->gen >= 9)
11163 skl_do_mmio_flip(intel_crtc);
11164 else
11165 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11166 ilk_do_mmio_flip(intel_crtc);
11167
11168 if (atomic_update)
11169 intel_pipe_update_end(intel_crtc, start_vbl_count);
11170 }
11171
11172 static void intel_mmio_flip_work_func(struct work_struct *work)
11173 {
11174 struct intel_mmio_flip *mmio_flip =
11175 container_of(work, struct intel_mmio_flip, work);
11176
11177 if (mmio_flip->req)
11178 WARN_ON(__i915_wait_request(mmio_flip->req,
11179 mmio_flip->crtc->reset_counter,
11180 false, NULL,
11181 &mmio_flip->i915->rps.mmioflips));
11182
11183 intel_do_mmio_flip(mmio_flip->crtc);
11184
11185 i915_gem_request_unreference__unlocked(mmio_flip->req);
11186 kfree(mmio_flip);
11187 }
11188
11189 static int intel_queue_mmio_flip(struct drm_device *dev,
11190 struct drm_crtc *crtc,
11191 struct drm_framebuffer *fb,
11192 struct drm_i915_gem_object *obj,
11193 struct intel_engine_cs *ring,
11194 uint32_t flags)
11195 {
11196 struct intel_mmio_flip *mmio_flip;
11197
11198 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11199 if (mmio_flip == NULL)
11200 return -ENOMEM;
11201
11202 mmio_flip->i915 = to_i915(dev);
11203 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11204 mmio_flip->crtc = to_intel_crtc(crtc);
11205
11206 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11207 schedule_work(&mmio_flip->work);
11208
11209 return 0;
11210 }
11211
11212 static int intel_default_queue_flip(struct drm_device *dev,
11213 struct drm_crtc *crtc,
11214 struct drm_framebuffer *fb,
11215 struct drm_i915_gem_object *obj,
11216 struct drm_i915_gem_request *req,
11217 uint32_t flags)
11218 {
11219 return -ENODEV;
11220 }
11221
11222 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11223 struct drm_crtc *crtc)
11224 {
11225 struct drm_i915_private *dev_priv = dev->dev_private;
11226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11227 struct intel_unpin_work *work = intel_crtc->unpin_work;
11228 u32 addr;
11229
11230 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11231 return true;
11232
11233 if (!work->enable_stall_check)
11234 return false;
11235
11236 if (work->flip_ready_vblank == 0) {
11237 if (work->flip_queued_req &&
11238 !i915_gem_request_completed(work->flip_queued_req, true))
11239 return false;
11240
11241 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11242 }
11243
11244 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11245 return false;
11246
11247 /* Potential stall - if we see that the flip has happened,
11248 * assume a missed interrupt. */
11249 if (INTEL_INFO(dev)->gen >= 4)
11250 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11251 else
11252 addr = I915_READ(DSPADDR(intel_crtc->plane));
11253
11254 /* There is a potential issue here with a false positive after a flip
11255 * to the same address. We could address this by checking for a
11256 * non-incrementing frame counter.
11257 */
11258 return addr == work->gtt_offset;
11259 }
11260
11261 void intel_check_page_flip(struct drm_device *dev, int pipe)
11262 {
11263 struct drm_i915_private *dev_priv = dev->dev_private;
11264 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11266 struct intel_unpin_work *work;
11267
11268 WARN_ON(!in_interrupt());
11269
11270 if (crtc == NULL)
11271 return;
11272
11273 spin_lock(&dev->event_lock);
11274 work = intel_crtc->unpin_work;
11275 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11276 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11277 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11278 page_flip_completed(intel_crtc);
11279 work = NULL;
11280 }
11281 if (work != NULL &&
11282 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11283 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11284 spin_unlock(&dev->event_lock);
11285 }
11286
11287 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11288 struct drm_framebuffer *fb,
11289 struct drm_pending_vblank_event *event,
11290 uint32_t page_flip_flags)
11291 {
11292 struct drm_device *dev = crtc->dev;
11293 struct drm_i915_private *dev_priv = dev->dev_private;
11294 struct drm_framebuffer *old_fb = crtc->primary->fb;
11295 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11297 struct drm_plane *primary = crtc->primary;
11298 enum pipe pipe = intel_crtc->pipe;
11299 struct intel_unpin_work *work;
11300 struct intel_engine_cs *ring;
11301 bool mmio_flip;
11302 struct drm_i915_gem_request *request = NULL;
11303 int ret;
11304
11305 /*
11306 * drm_mode_page_flip_ioctl() should already catch this, but double
11307 * check to be safe. In the future we may enable pageflipping from
11308 * a disabled primary plane.
11309 */
11310 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11311 return -EBUSY;
11312
11313 /* Can't change pixel format via MI display flips. */
11314 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11315 return -EINVAL;
11316
11317 /*
11318 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11319 * Note that pitch changes could also affect these register.
11320 */
11321 if (INTEL_INFO(dev)->gen > 3 &&
11322 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11323 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11324 return -EINVAL;
11325
11326 if (i915_terminally_wedged(&dev_priv->gpu_error))
11327 goto out_hang;
11328
11329 work = kzalloc(sizeof(*work), GFP_KERNEL);
11330 if (work == NULL)
11331 return -ENOMEM;
11332
11333 work->event = event;
11334 work->crtc = crtc;
11335 work->old_fb = old_fb;
11336 INIT_WORK(&work->work, intel_unpin_work_fn);
11337
11338 ret = drm_crtc_vblank_get(crtc);
11339 if (ret)
11340 goto free_work;
11341
11342 /* We borrow the event spin lock for protecting unpin_work */
11343 spin_lock_irq(&dev->event_lock);
11344 if (intel_crtc->unpin_work) {
11345 /* Before declaring the flip queue wedged, check if
11346 * the hardware completed the operation behind our backs.
11347 */
11348 if (__intel_pageflip_stall_check(dev, crtc)) {
11349 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11350 page_flip_completed(intel_crtc);
11351 } else {
11352 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11353 spin_unlock_irq(&dev->event_lock);
11354
11355 drm_crtc_vblank_put(crtc);
11356 kfree(work);
11357 return -EBUSY;
11358 }
11359 }
11360 intel_crtc->unpin_work = work;
11361 spin_unlock_irq(&dev->event_lock);
11362
11363 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11364 flush_workqueue(dev_priv->wq);
11365
11366 /* Reference the objects for the scheduled work. */
11367 drm_framebuffer_reference(work->old_fb);
11368 drm_gem_object_reference(&obj->base);
11369
11370 crtc->primary->fb = fb;
11371 update_state_fb(crtc->primary);
11372
11373 work->pending_flip_obj = obj;
11374
11375 ret = i915_mutex_lock_interruptible(dev);
11376 if (ret)
11377 goto cleanup;
11378
11379 atomic_inc(&intel_crtc->unpin_work_count);
11380 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11381
11382 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11383 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11384
11385 if (IS_VALLEYVIEW(dev)) {
11386 ring = &dev_priv->ring[BCS];
11387 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11388 /* vlv: DISPLAY_FLIP fails to change tiling */
11389 ring = NULL;
11390 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11391 ring = &dev_priv->ring[BCS];
11392 } else if (INTEL_INFO(dev)->gen >= 7) {
11393 ring = i915_gem_request_get_ring(obj->last_write_req);
11394 if (ring == NULL || ring->id != RCS)
11395 ring = &dev_priv->ring[BCS];
11396 } else {
11397 ring = &dev_priv->ring[RCS];
11398 }
11399
11400 mmio_flip = use_mmio_flip(ring, obj);
11401
11402 /* When using CS flips, we want to emit semaphores between rings.
11403 * However, when using mmio flips we will create a task to do the
11404 * synchronisation, so all we want here is to pin the framebuffer
11405 * into the display plane and skip any waits.
11406 */
11407 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11408 crtc->primary->state,
11409 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11410 if (ret)
11411 goto cleanup_pending;
11412
11413 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11414 + intel_crtc->dspaddr_offset;
11415
11416 if (mmio_flip) {
11417 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11418 page_flip_flags);
11419 if (ret)
11420 goto cleanup_unpin;
11421
11422 i915_gem_request_assign(&work->flip_queued_req,
11423 obj->last_write_req);
11424 } else {
11425 if (!request) {
11426 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11427 if (ret)
11428 goto cleanup_unpin;
11429 }
11430
11431 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11432 page_flip_flags);
11433 if (ret)
11434 goto cleanup_unpin;
11435
11436 i915_gem_request_assign(&work->flip_queued_req, request);
11437 }
11438
11439 if (request)
11440 i915_add_request_no_flush(request);
11441
11442 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11443 work->enable_stall_check = true;
11444
11445 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11446 to_intel_plane(primary)->frontbuffer_bit);
11447
11448 intel_fbc_disable(dev);
11449 intel_frontbuffer_flip_prepare(dev,
11450 to_intel_plane(primary)->frontbuffer_bit);
11451 mutex_unlock(&dev->struct_mutex);
11452
11453 trace_i915_flip_request(intel_crtc->plane, obj);
11454
11455 return 0;
11456
11457 cleanup_unpin:
11458 intel_unpin_fb_obj(fb, crtc->primary->state);
11459 cleanup_pending:
11460 if (request)
11461 i915_gem_request_cancel(request);
11462 atomic_dec(&intel_crtc->unpin_work_count);
11463 mutex_unlock(&dev->struct_mutex);
11464 cleanup:
11465 crtc->primary->fb = old_fb;
11466 update_state_fb(crtc->primary);
11467
11468 drm_gem_object_unreference_unlocked(&obj->base);
11469 drm_framebuffer_unreference(work->old_fb);
11470
11471 spin_lock_irq(&dev->event_lock);
11472 intel_crtc->unpin_work = NULL;
11473 spin_unlock_irq(&dev->event_lock);
11474
11475 drm_crtc_vblank_put(crtc);
11476 free_work:
11477 kfree(work);
11478
11479 if (ret == -EIO) {
11480 struct drm_atomic_state *state;
11481 struct drm_plane_state *plane_state;
11482
11483 out_hang:
11484 state = drm_atomic_state_alloc(dev);
11485 if (!state)
11486 return -ENOMEM;
11487 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11488
11489 retry:
11490 plane_state = drm_atomic_get_plane_state(state, primary);
11491 ret = PTR_ERR_OR_ZERO(plane_state);
11492 if (!ret) {
11493 drm_atomic_set_fb_for_plane(plane_state, fb);
11494
11495 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11496 if (!ret)
11497 ret = drm_atomic_commit(state);
11498 }
11499
11500 if (ret == -EDEADLK) {
11501 drm_modeset_backoff(state->acquire_ctx);
11502 drm_atomic_state_clear(state);
11503 goto retry;
11504 }
11505
11506 if (ret)
11507 drm_atomic_state_free(state);
11508
11509 if (ret == 0 && event) {
11510 spin_lock_irq(&dev->event_lock);
11511 drm_send_vblank_event(dev, pipe, event);
11512 spin_unlock_irq(&dev->event_lock);
11513 }
11514 }
11515 return ret;
11516 }
11517
11518
11519 /**
11520 * intel_wm_need_update - Check whether watermarks need updating
11521 * @plane: drm plane
11522 * @state: new plane state
11523 *
11524 * Check current plane state versus the new one to determine whether
11525 * watermarks need to be recalculated.
11526 *
11527 * Returns true or false.
11528 */
11529 static bool intel_wm_need_update(struct drm_plane *plane,
11530 struct drm_plane_state *state)
11531 {
11532 /* Update watermarks on tiling changes. */
11533 if (!plane->state->fb || !state->fb ||
11534 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11535 plane->state->rotation != state->rotation)
11536 return true;
11537
11538 if (plane->state->crtc_w != state->crtc_w)
11539 return true;
11540
11541 return false;
11542 }
11543
11544 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11545 struct drm_plane_state *plane_state)
11546 {
11547 struct drm_crtc *crtc = crtc_state->crtc;
11548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11549 struct drm_plane *plane = plane_state->plane;
11550 struct drm_device *dev = crtc->dev;
11551 struct drm_i915_private *dev_priv = dev->dev_private;
11552 struct intel_plane_state *old_plane_state =
11553 to_intel_plane_state(plane->state);
11554 int idx = intel_crtc->base.base.id, ret;
11555 int i = drm_plane_index(plane);
11556 bool mode_changed = needs_modeset(crtc_state);
11557 bool was_crtc_enabled = crtc->state->active;
11558 bool is_crtc_enabled = crtc_state->active;
11559
11560 bool turn_off, turn_on, visible, was_visible;
11561 struct drm_framebuffer *fb = plane_state->fb;
11562
11563 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11564 plane->type != DRM_PLANE_TYPE_CURSOR) {
11565 ret = skl_update_scaler_plane(
11566 to_intel_crtc_state(crtc_state),
11567 to_intel_plane_state(plane_state));
11568 if (ret)
11569 return ret;
11570 }
11571
11572 /*
11573 * Disabling a plane is always okay; we just need to update
11574 * fb tracking in a special way since cleanup_fb() won't
11575 * get called by the plane helpers.
11576 */
11577 if (old_plane_state->base.fb && !fb)
11578 intel_crtc->atomic.disabled_planes |= 1 << i;
11579
11580 was_visible = old_plane_state->visible;
11581 visible = to_intel_plane_state(plane_state)->visible;
11582
11583 if (!was_crtc_enabled && WARN_ON(was_visible))
11584 was_visible = false;
11585
11586 if (!is_crtc_enabled && WARN_ON(visible))
11587 visible = false;
11588
11589 if (!was_visible && !visible)
11590 return 0;
11591
11592 turn_off = was_visible && (!visible || mode_changed);
11593 turn_on = visible && (!was_visible || mode_changed);
11594
11595 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11596 plane->base.id, fb ? fb->base.id : -1);
11597
11598 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11599 plane->base.id, was_visible, visible,
11600 turn_off, turn_on, mode_changed);
11601
11602 if (intel_wm_need_update(plane, plane_state))
11603 intel_crtc->atomic.update_wm = true;
11604
11605 if (visible)
11606 intel_crtc->atomic.fb_bits |=
11607 to_intel_plane(plane)->frontbuffer_bit;
11608
11609 switch (plane->type) {
11610 case DRM_PLANE_TYPE_PRIMARY:
11611 intel_crtc->atomic.wait_for_flips = true;
11612 intel_crtc->atomic.pre_disable_primary = turn_off;
11613 intel_crtc->atomic.post_enable_primary = turn_on;
11614
11615 if (turn_off)
11616 intel_crtc->atomic.disable_fbc = true;
11617
11618 /*
11619 * FBC does not work on some platforms for rotated
11620 * planes, so disable it when rotation is not 0 and
11621 * update it when rotation is set back to 0.
11622 *
11623 * FIXME: This is redundant with the fbc update done in
11624 * the primary plane enable function except that that
11625 * one is done too late. We eventually need to unify
11626 * this.
11627 */
11628
11629 if (visible &&
11630 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11631 dev_priv->fbc.crtc == intel_crtc &&
11632 plane_state->rotation != BIT(DRM_ROTATE_0))
11633 intel_crtc->atomic.disable_fbc = true;
11634
11635 /*
11636 * BDW signals flip done immediately if the plane
11637 * is disabled, even if the plane enable is already
11638 * armed to occur at the next vblank :(
11639 */
11640 if (turn_on && IS_BROADWELL(dev))
11641 intel_crtc->atomic.wait_vblank = true;
11642
11643 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11644 break;
11645 case DRM_PLANE_TYPE_CURSOR:
11646 break;
11647 case DRM_PLANE_TYPE_OVERLAY:
11648 if (turn_off && !mode_changed) {
11649 intel_crtc->atomic.wait_vblank = true;
11650 intel_crtc->atomic.update_sprite_watermarks |=
11651 1 << i;
11652 }
11653 }
11654 return 0;
11655 }
11656
11657 static bool encoders_cloneable(const struct intel_encoder *a,
11658 const struct intel_encoder *b)
11659 {
11660 /* masks could be asymmetric, so check both ways */
11661 return a == b || (a->cloneable & (1 << b->type) &&
11662 b->cloneable & (1 << a->type));
11663 }
11664
11665 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11666 struct intel_crtc *crtc,
11667 struct intel_encoder *encoder)
11668 {
11669 struct intel_encoder *source_encoder;
11670 struct drm_connector *connector;
11671 struct drm_connector_state *connector_state;
11672 int i;
11673
11674 for_each_connector_in_state(state, connector, connector_state, i) {
11675 if (connector_state->crtc != &crtc->base)
11676 continue;
11677
11678 source_encoder =
11679 to_intel_encoder(connector_state->best_encoder);
11680 if (!encoders_cloneable(encoder, source_encoder))
11681 return false;
11682 }
11683
11684 return true;
11685 }
11686
11687 static bool check_encoder_cloning(struct drm_atomic_state *state,
11688 struct intel_crtc *crtc)
11689 {
11690 struct intel_encoder *encoder;
11691 struct drm_connector *connector;
11692 struct drm_connector_state *connector_state;
11693 int i;
11694
11695 for_each_connector_in_state(state, connector, connector_state, i) {
11696 if (connector_state->crtc != &crtc->base)
11697 continue;
11698
11699 encoder = to_intel_encoder(connector_state->best_encoder);
11700 if (!check_single_encoder_cloning(state, crtc, encoder))
11701 return false;
11702 }
11703
11704 return true;
11705 }
11706
11707 static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11708 struct drm_crtc_state *crtc_state)
11709 {
11710 struct intel_crtc_state *pipe_config =
11711 to_intel_crtc_state(crtc_state);
11712 struct drm_plane *p;
11713 unsigned visible_mask = 0;
11714
11715 drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11716 struct drm_plane_state *plane_state =
11717 drm_atomic_get_existing_plane_state(crtc_state->state, p);
11718
11719 if (WARN_ON(!plane_state))
11720 continue;
11721
11722 if (!plane_state->fb)
11723 crtc_state->plane_mask &=
11724 ~(1 << drm_plane_index(p));
11725 else if (to_intel_plane_state(plane_state)->visible)
11726 visible_mask |= 1 << drm_plane_index(p);
11727 }
11728
11729 if (!visible_mask)
11730 return;
11731
11732 pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11733 }
11734
11735 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11736 struct drm_crtc_state *crtc_state)
11737 {
11738 struct drm_device *dev = crtc->dev;
11739 struct drm_i915_private *dev_priv = dev->dev_private;
11740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11741 struct intel_crtc_state *pipe_config =
11742 to_intel_crtc_state(crtc_state);
11743 struct drm_atomic_state *state = crtc_state->state;
11744 int ret, idx = crtc->base.id;
11745 bool mode_changed = needs_modeset(crtc_state);
11746
11747 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11748 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11749 return -EINVAL;
11750 }
11751
11752 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11753 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11754 idx, crtc->state->active, intel_crtc->active);
11755
11756 /* plane mask is fixed up after all initial planes are calculated */
11757 if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11758 intel_crtc_check_initial_planes(crtc, crtc_state);
11759
11760 if (mode_changed)
11761 intel_crtc->atomic.update_wm = !crtc_state->active;
11762
11763 if (mode_changed && crtc_state->enable &&
11764 dev_priv->display.crtc_compute_clock &&
11765 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11766 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11767 pipe_config);
11768 if (ret)
11769 return ret;
11770 }
11771
11772 return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
11773 }
11774
11775 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11776 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11777 .load_lut = intel_crtc_load_lut,
11778 .atomic_begin = intel_begin_crtc_commit,
11779 .atomic_flush = intel_finish_crtc_commit,
11780 .atomic_check = intel_crtc_atomic_check,
11781 };
11782
11783 /**
11784 * intel_modeset_update_staged_output_state
11785 *
11786 * Updates the staged output configuration state, e.g. after we've read out the
11787 * current hw state.
11788 */
11789 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11790 {
11791 struct intel_crtc *crtc;
11792 struct intel_encoder *encoder;
11793 struct intel_connector *connector;
11794
11795 for_each_intel_connector(dev, connector) {
11796 connector->new_encoder =
11797 to_intel_encoder(connector->base.encoder);
11798 }
11799
11800 for_each_intel_encoder(dev, encoder) {
11801 encoder->new_crtc =
11802 to_intel_crtc(encoder->base.crtc);
11803 }
11804
11805 for_each_intel_crtc(dev, crtc) {
11806 crtc->new_enabled = crtc->base.state->enable;
11807 }
11808 }
11809
11810 /* Transitional helper to copy current connector/encoder state to
11811 * connector->state. This is needed so that code that is partially
11812 * converted to atomic does the right thing.
11813 */
11814 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11815 {
11816 struct intel_connector *connector;
11817
11818 for_each_intel_connector(dev, connector) {
11819 if (connector->base.encoder) {
11820 connector->base.state->best_encoder =
11821 connector->base.encoder;
11822 connector->base.state->crtc =
11823 connector->base.encoder->crtc;
11824 } else {
11825 connector->base.state->best_encoder = NULL;
11826 connector->base.state->crtc = NULL;
11827 }
11828 }
11829 }
11830
11831 static void
11832 connected_sink_compute_bpp(struct intel_connector *connector,
11833 struct intel_crtc_state *pipe_config)
11834 {
11835 int bpp = pipe_config->pipe_bpp;
11836
11837 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11838 connector->base.base.id,
11839 connector->base.name);
11840
11841 /* Don't use an invalid EDID bpc value */
11842 if (connector->base.display_info.bpc &&
11843 connector->base.display_info.bpc * 3 < bpp) {
11844 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11845 bpp, connector->base.display_info.bpc*3);
11846 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11847 }
11848
11849 /* Clamp bpp to 8 on screens without EDID 1.4 */
11850 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11851 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11852 bpp);
11853 pipe_config->pipe_bpp = 24;
11854 }
11855 }
11856
11857 static int
11858 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11859 struct intel_crtc_state *pipe_config)
11860 {
11861 struct drm_device *dev = crtc->base.dev;
11862 struct drm_atomic_state *state;
11863 struct drm_connector *connector;
11864 struct drm_connector_state *connector_state;
11865 int bpp, i;
11866
11867 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11868 bpp = 10*3;
11869 else if (INTEL_INFO(dev)->gen >= 5)
11870 bpp = 12*3;
11871 else
11872 bpp = 8*3;
11873
11874
11875 pipe_config->pipe_bpp = bpp;
11876
11877 state = pipe_config->base.state;
11878
11879 /* Clamp display bpp to EDID value */
11880 for_each_connector_in_state(state, connector, connector_state, i) {
11881 if (connector_state->crtc != &crtc->base)
11882 continue;
11883
11884 connected_sink_compute_bpp(to_intel_connector(connector),
11885 pipe_config);
11886 }
11887
11888 return bpp;
11889 }
11890
11891 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11892 {
11893 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11894 "type: 0x%x flags: 0x%x\n",
11895 mode->crtc_clock,
11896 mode->crtc_hdisplay, mode->crtc_hsync_start,
11897 mode->crtc_hsync_end, mode->crtc_htotal,
11898 mode->crtc_vdisplay, mode->crtc_vsync_start,
11899 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11900 }
11901
11902 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11903 struct intel_crtc_state *pipe_config,
11904 const char *context)
11905 {
11906 struct drm_device *dev = crtc->base.dev;
11907 struct drm_plane *plane;
11908 struct intel_plane *intel_plane;
11909 struct intel_plane_state *state;
11910 struct drm_framebuffer *fb;
11911
11912 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11913 context, pipe_config, pipe_name(crtc->pipe));
11914
11915 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11916 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11917 pipe_config->pipe_bpp, pipe_config->dither);
11918 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11919 pipe_config->has_pch_encoder,
11920 pipe_config->fdi_lanes,
11921 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11922 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11923 pipe_config->fdi_m_n.tu);
11924 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11925 pipe_config->has_dp_encoder,
11926 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11927 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11928 pipe_config->dp_m_n.tu);
11929
11930 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11931 pipe_config->has_dp_encoder,
11932 pipe_config->dp_m2_n2.gmch_m,
11933 pipe_config->dp_m2_n2.gmch_n,
11934 pipe_config->dp_m2_n2.link_m,
11935 pipe_config->dp_m2_n2.link_n,
11936 pipe_config->dp_m2_n2.tu);
11937
11938 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11939 pipe_config->has_audio,
11940 pipe_config->has_infoframe);
11941
11942 DRM_DEBUG_KMS("requested mode:\n");
11943 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11944 DRM_DEBUG_KMS("adjusted mode:\n");
11945 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11946 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11947 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11948 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11949 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11950 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11951 crtc->num_scalers,
11952 pipe_config->scaler_state.scaler_users,
11953 pipe_config->scaler_state.scaler_id);
11954 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11955 pipe_config->gmch_pfit.control,
11956 pipe_config->gmch_pfit.pgm_ratios,
11957 pipe_config->gmch_pfit.lvds_border_bits);
11958 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11959 pipe_config->pch_pfit.pos,
11960 pipe_config->pch_pfit.size,
11961 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11962 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11963 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11964
11965 if (IS_BROXTON(dev)) {
11966 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11967 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11968 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11969 pipe_config->ddi_pll_sel,
11970 pipe_config->dpll_hw_state.ebb0,
11971 pipe_config->dpll_hw_state.pll0,
11972 pipe_config->dpll_hw_state.pll1,
11973 pipe_config->dpll_hw_state.pll2,
11974 pipe_config->dpll_hw_state.pll3,
11975 pipe_config->dpll_hw_state.pll6,
11976 pipe_config->dpll_hw_state.pll8,
11977 pipe_config->dpll_hw_state.pcsdw12);
11978 } else if (IS_SKYLAKE(dev)) {
11979 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11980 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11981 pipe_config->ddi_pll_sel,
11982 pipe_config->dpll_hw_state.ctrl1,
11983 pipe_config->dpll_hw_state.cfgcr1,
11984 pipe_config->dpll_hw_state.cfgcr2);
11985 } else if (HAS_DDI(dev)) {
11986 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11987 pipe_config->ddi_pll_sel,
11988 pipe_config->dpll_hw_state.wrpll);
11989 } else {
11990 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11991 "fp0: 0x%x, fp1: 0x%x\n",
11992 pipe_config->dpll_hw_state.dpll,
11993 pipe_config->dpll_hw_state.dpll_md,
11994 pipe_config->dpll_hw_state.fp0,
11995 pipe_config->dpll_hw_state.fp1);
11996 }
11997
11998 DRM_DEBUG_KMS("planes on this crtc\n");
11999 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12000 intel_plane = to_intel_plane(plane);
12001 if (intel_plane->pipe != crtc->pipe)
12002 continue;
12003
12004 state = to_intel_plane_state(plane->state);
12005 fb = state->base.fb;
12006 if (!fb) {
12007 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12008 "disabled, scaler_id = %d\n",
12009 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12010 plane->base.id, intel_plane->pipe,
12011 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12012 drm_plane_index(plane), state->scaler_id);
12013 continue;
12014 }
12015
12016 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12017 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12018 plane->base.id, intel_plane->pipe,
12019 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12020 drm_plane_index(plane));
12021 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12022 fb->base.id, fb->width, fb->height, fb->pixel_format);
12023 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12024 state->scaler_id,
12025 state->src.x1 >> 16, state->src.y1 >> 16,
12026 drm_rect_width(&state->src) >> 16,
12027 drm_rect_height(&state->src) >> 16,
12028 state->dst.x1, state->dst.y1,
12029 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12030 }
12031 }
12032
12033 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12034 {
12035 struct drm_device *dev = state->dev;
12036 struct intel_encoder *encoder;
12037 struct drm_connector *connector;
12038 struct drm_connector_state *connector_state;
12039 unsigned int used_ports = 0;
12040 int i;
12041
12042 /*
12043 * Walk the connector list instead of the encoder
12044 * list to detect the problem on ddi platforms
12045 * where there's just one encoder per digital port.
12046 */
12047 for_each_connector_in_state(state, connector, connector_state, i) {
12048 if (!connector_state->best_encoder)
12049 continue;
12050
12051 encoder = to_intel_encoder(connector_state->best_encoder);
12052
12053 WARN_ON(!connector_state->crtc);
12054
12055 switch (encoder->type) {
12056 unsigned int port_mask;
12057 case INTEL_OUTPUT_UNKNOWN:
12058 if (WARN_ON(!HAS_DDI(dev)))
12059 break;
12060 case INTEL_OUTPUT_DISPLAYPORT:
12061 case INTEL_OUTPUT_HDMI:
12062 case INTEL_OUTPUT_EDP:
12063 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12064
12065 /* the same port mustn't appear more than once */
12066 if (used_ports & port_mask)
12067 return false;
12068
12069 used_ports |= port_mask;
12070 default:
12071 break;
12072 }
12073 }
12074
12075 return true;
12076 }
12077
12078 static void
12079 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12080 {
12081 struct drm_crtc_state tmp_state;
12082 struct intel_crtc_scaler_state scaler_state;
12083 struct intel_dpll_hw_state dpll_hw_state;
12084 enum intel_dpll_id shared_dpll;
12085 uint32_t ddi_pll_sel;
12086
12087 /* FIXME: before the switch to atomic started, a new pipe_config was
12088 * kzalloc'd. Code that depends on any field being zero should be
12089 * fixed, so that the crtc_state can be safely duplicated. For now,
12090 * only fields that are know to not cause problems are preserved. */
12091
12092 tmp_state = crtc_state->base;
12093 scaler_state = crtc_state->scaler_state;
12094 shared_dpll = crtc_state->shared_dpll;
12095 dpll_hw_state = crtc_state->dpll_hw_state;
12096 ddi_pll_sel = crtc_state->ddi_pll_sel;
12097
12098 memset(crtc_state, 0, sizeof *crtc_state);
12099
12100 crtc_state->base = tmp_state;
12101 crtc_state->scaler_state = scaler_state;
12102 crtc_state->shared_dpll = shared_dpll;
12103 crtc_state->dpll_hw_state = dpll_hw_state;
12104 crtc_state->ddi_pll_sel = ddi_pll_sel;
12105 }
12106
12107 static int
12108 intel_modeset_pipe_config(struct drm_crtc *crtc,
12109 struct intel_crtc_state *pipe_config)
12110 {
12111 struct drm_atomic_state *state = pipe_config->base.state;
12112 struct intel_encoder *encoder;
12113 struct drm_connector *connector;
12114 struct drm_connector_state *connector_state;
12115 int base_bpp, ret = -EINVAL;
12116 int i;
12117 bool retry = true;
12118
12119 clear_intel_crtc_state(pipe_config);
12120
12121 pipe_config->cpu_transcoder =
12122 (enum transcoder) to_intel_crtc(crtc)->pipe;
12123
12124 /*
12125 * Sanitize sync polarity flags based on requested ones. If neither
12126 * positive or negative polarity is requested, treat this as meaning
12127 * negative polarity.
12128 */
12129 if (!(pipe_config->base.adjusted_mode.flags &
12130 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12131 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12132
12133 if (!(pipe_config->base.adjusted_mode.flags &
12134 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12135 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12136
12137 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12138 * plane pixel format and any sink constraints into account. Returns the
12139 * source plane bpp so that dithering can be selected on mismatches
12140 * after encoders and crtc also have had their say. */
12141 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12142 pipe_config);
12143 if (base_bpp < 0)
12144 goto fail;
12145
12146 /*
12147 * Determine the real pipe dimensions. Note that stereo modes can
12148 * increase the actual pipe size due to the frame doubling and
12149 * insertion of additional space for blanks between the frame. This
12150 * is stored in the crtc timings. We use the requested mode to do this
12151 * computation to clearly distinguish it from the adjusted mode, which
12152 * can be changed by the connectors in the below retry loop.
12153 */
12154 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12155 &pipe_config->pipe_src_w,
12156 &pipe_config->pipe_src_h);
12157
12158 encoder_retry:
12159 /* Ensure the port clock defaults are reset when retrying. */
12160 pipe_config->port_clock = 0;
12161 pipe_config->pixel_multiplier = 1;
12162
12163 /* Fill in default crtc timings, allow encoders to overwrite them. */
12164 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12165 CRTC_STEREO_DOUBLE);
12166
12167 /* Pass our mode to the connectors and the CRTC to give them a chance to
12168 * adjust it according to limitations or connector properties, and also
12169 * a chance to reject the mode entirely.
12170 */
12171 for_each_connector_in_state(state, connector, connector_state, i) {
12172 if (connector_state->crtc != crtc)
12173 continue;
12174
12175 encoder = to_intel_encoder(connector_state->best_encoder);
12176
12177 if (!(encoder->compute_config(encoder, pipe_config))) {
12178 DRM_DEBUG_KMS("Encoder config failure\n");
12179 goto fail;
12180 }
12181 }
12182
12183 /* Set default port clock if not overwritten by the encoder. Needs to be
12184 * done afterwards in case the encoder adjusts the mode. */
12185 if (!pipe_config->port_clock)
12186 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12187 * pipe_config->pixel_multiplier;
12188
12189 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12190 if (ret < 0) {
12191 DRM_DEBUG_KMS("CRTC fixup failed\n");
12192 goto fail;
12193 }
12194
12195 if (ret == RETRY) {
12196 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12197 ret = -EINVAL;
12198 goto fail;
12199 }
12200
12201 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12202 retry = false;
12203 goto encoder_retry;
12204 }
12205
12206 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12207 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12208 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12209
12210 /* Check if we need to force a modeset */
12211 if (pipe_config->has_audio !=
12212 to_intel_crtc_state(crtc->state)->has_audio) {
12213 pipe_config->base.mode_changed = true;
12214 ret = drm_atomic_add_affected_planes(state, crtc);
12215 }
12216
12217 /*
12218 * Note we have an issue here with infoframes: current code
12219 * only updates them on the full mode set path per hw
12220 * requirements. So here we should be checking for any
12221 * required changes and forcing a mode set.
12222 */
12223 fail:
12224 return ret;
12225 }
12226
12227 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12228 {
12229 struct drm_encoder *encoder;
12230 struct drm_device *dev = crtc->dev;
12231
12232 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12233 if (encoder->crtc == crtc)
12234 return true;
12235
12236 return false;
12237 }
12238
12239 static void
12240 intel_modeset_update_state(struct drm_atomic_state *state)
12241 {
12242 struct drm_device *dev = state->dev;
12243 struct intel_encoder *intel_encoder;
12244 struct drm_crtc *crtc;
12245 struct drm_crtc_state *crtc_state;
12246 struct drm_connector *connector;
12247
12248 intel_shared_dpll_commit(state);
12249
12250 for_each_intel_encoder(dev, intel_encoder) {
12251 if (!intel_encoder->base.crtc)
12252 continue;
12253
12254 crtc = intel_encoder->base.crtc;
12255 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12256 if (!crtc_state || !needs_modeset(crtc->state))
12257 continue;
12258
12259 intel_encoder->connectors_active = false;
12260 }
12261
12262 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12263 intel_modeset_update_staged_output_state(state->dev);
12264
12265 /* Double check state. */
12266 for_each_crtc(dev, crtc) {
12267 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12268
12269 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12270
12271 /* Update hwmode for vblank functions */
12272 if (crtc->state->active)
12273 crtc->hwmode = crtc->state->adjusted_mode;
12274 else
12275 crtc->hwmode.crtc_clock = 0;
12276 }
12277
12278 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12279 if (!connector->encoder || !connector->encoder->crtc)
12280 continue;
12281
12282 crtc = connector->encoder->crtc;
12283 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12284 if (!crtc_state || !needs_modeset(crtc->state))
12285 continue;
12286
12287 if (crtc->state->active) {
12288 struct drm_property *dpms_property =
12289 dev->mode_config.dpms_property;
12290
12291 connector->dpms = DRM_MODE_DPMS_ON;
12292 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12293
12294 intel_encoder = to_intel_encoder(connector->encoder);
12295 intel_encoder->connectors_active = true;
12296 } else
12297 connector->dpms = DRM_MODE_DPMS_OFF;
12298 }
12299 }
12300
12301 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12302 {
12303 int diff;
12304
12305 if (clock1 == clock2)
12306 return true;
12307
12308 if (!clock1 || !clock2)
12309 return false;
12310
12311 diff = abs(clock1 - clock2);
12312
12313 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12314 return true;
12315
12316 return false;
12317 }
12318
12319 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12320 list_for_each_entry((intel_crtc), \
12321 &(dev)->mode_config.crtc_list, \
12322 base.head) \
12323 if (mask & (1 <<(intel_crtc)->pipe))
12324
12325 static bool
12326 intel_pipe_config_compare(struct drm_device *dev,
12327 struct intel_crtc_state *current_config,
12328 struct intel_crtc_state *pipe_config)
12329 {
12330 #define PIPE_CONF_CHECK_X(name) \
12331 if (current_config->name != pipe_config->name) { \
12332 DRM_ERROR("mismatch in " #name " " \
12333 "(expected 0x%08x, found 0x%08x)\n", \
12334 current_config->name, \
12335 pipe_config->name); \
12336 return false; \
12337 }
12338
12339 #define PIPE_CONF_CHECK_I(name) \
12340 if (current_config->name != pipe_config->name) { \
12341 DRM_ERROR("mismatch in " #name " " \
12342 "(expected %i, found %i)\n", \
12343 current_config->name, \
12344 pipe_config->name); \
12345 return false; \
12346 }
12347
12348 /* This is required for BDW+ where there is only one set of registers for
12349 * switching between high and low RR.
12350 * This macro can be used whenever a comparison has to be made between one
12351 * hw state and multiple sw state variables.
12352 */
12353 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12354 if ((current_config->name != pipe_config->name) && \
12355 (current_config->alt_name != pipe_config->name)) { \
12356 DRM_ERROR("mismatch in " #name " " \
12357 "(expected %i or %i, found %i)\n", \
12358 current_config->name, \
12359 current_config->alt_name, \
12360 pipe_config->name); \
12361 return false; \
12362 }
12363
12364 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12365 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12366 DRM_ERROR("mismatch in " #name "(" #mask ") " \
12367 "(expected %i, found %i)\n", \
12368 current_config->name & (mask), \
12369 pipe_config->name & (mask)); \
12370 return false; \
12371 }
12372
12373 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12374 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12375 DRM_ERROR("mismatch in " #name " " \
12376 "(expected %i, found %i)\n", \
12377 current_config->name, \
12378 pipe_config->name); \
12379 return false; \
12380 }
12381
12382 #define PIPE_CONF_QUIRK(quirk) \
12383 ((current_config->quirks | pipe_config->quirks) & (quirk))
12384
12385 PIPE_CONF_CHECK_I(cpu_transcoder);
12386
12387 PIPE_CONF_CHECK_I(has_pch_encoder);
12388 PIPE_CONF_CHECK_I(fdi_lanes);
12389 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12390 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12391 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12392 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12393 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12394
12395 PIPE_CONF_CHECK_I(has_dp_encoder);
12396
12397 if (INTEL_INFO(dev)->gen < 8) {
12398 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12399 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12400 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12401 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12402 PIPE_CONF_CHECK_I(dp_m_n.tu);
12403
12404 if (current_config->has_drrs) {
12405 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12406 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12407 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12408 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12409 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12410 }
12411 } else {
12412 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12413 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12414 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12415 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12416 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12417 }
12418
12419 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12420 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12421 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12422 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12423 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12424 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12425
12426 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12427 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12428 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12429 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12430 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12431 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12432
12433 PIPE_CONF_CHECK_I(pixel_multiplier);
12434 PIPE_CONF_CHECK_I(has_hdmi_sink);
12435 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12436 IS_VALLEYVIEW(dev))
12437 PIPE_CONF_CHECK_I(limited_color_range);
12438 PIPE_CONF_CHECK_I(has_infoframe);
12439
12440 PIPE_CONF_CHECK_I(has_audio);
12441
12442 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12443 DRM_MODE_FLAG_INTERLACE);
12444
12445 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12446 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12447 DRM_MODE_FLAG_PHSYNC);
12448 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12449 DRM_MODE_FLAG_NHSYNC);
12450 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12451 DRM_MODE_FLAG_PVSYNC);
12452 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12453 DRM_MODE_FLAG_NVSYNC);
12454 }
12455
12456 PIPE_CONF_CHECK_I(pipe_src_w);
12457 PIPE_CONF_CHECK_I(pipe_src_h);
12458
12459 /*
12460 * FIXME: BIOS likes to set up a cloned config with lvds+external
12461 * screen. Since we don't yet re-compute the pipe config when moving
12462 * just the lvds port away to another pipe the sw tracking won't match.
12463 *
12464 * Proper atomic modesets with recomputed global state will fix this.
12465 * Until then just don't check gmch state for inherited modes.
12466 */
12467 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12468 PIPE_CONF_CHECK_I(gmch_pfit.control);
12469 /* pfit ratios are autocomputed by the hw on gen4+ */
12470 if (INTEL_INFO(dev)->gen < 4)
12471 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12472 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12473 }
12474
12475 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12476 if (current_config->pch_pfit.enabled) {
12477 PIPE_CONF_CHECK_I(pch_pfit.pos);
12478 PIPE_CONF_CHECK_I(pch_pfit.size);
12479 }
12480
12481 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12482
12483 /* BDW+ don't expose a synchronous way to read the state */
12484 if (IS_HASWELL(dev))
12485 PIPE_CONF_CHECK_I(ips_enabled);
12486
12487 PIPE_CONF_CHECK_I(double_wide);
12488
12489 PIPE_CONF_CHECK_X(ddi_pll_sel);
12490
12491 PIPE_CONF_CHECK_I(shared_dpll);
12492 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12493 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12494 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12495 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12496 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12497 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12498 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12499 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12500
12501 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12502 PIPE_CONF_CHECK_I(pipe_bpp);
12503
12504 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12505 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12506
12507 #undef PIPE_CONF_CHECK_X
12508 #undef PIPE_CONF_CHECK_I
12509 #undef PIPE_CONF_CHECK_I_ALT
12510 #undef PIPE_CONF_CHECK_FLAGS
12511 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12512 #undef PIPE_CONF_QUIRK
12513
12514 return true;
12515 }
12516
12517 static void check_wm_state(struct drm_device *dev)
12518 {
12519 struct drm_i915_private *dev_priv = dev->dev_private;
12520 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12521 struct intel_crtc *intel_crtc;
12522 int plane;
12523
12524 if (INTEL_INFO(dev)->gen < 9)
12525 return;
12526
12527 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12528 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12529
12530 for_each_intel_crtc(dev, intel_crtc) {
12531 struct skl_ddb_entry *hw_entry, *sw_entry;
12532 const enum pipe pipe = intel_crtc->pipe;
12533
12534 if (!intel_crtc->active)
12535 continue;
12536
12537 /* planes */
12538 for_each_plane(dev_priv, pipe, plane) {
12539 hw_entry = &hw_ddb.plane[pipe][plane];
12540 sw_entry = &sw_ddb->plane[pipe][plane];
12541
12542 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12543 continue;
12544
12545 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12546 "(expected (%u,%u), found (%u,%u))\n",
12547 pipe_name(pipe), plane + 1,
12548 sw_entry->start, sw_entry->end,
12549 hw_entry->start, hw_entry->end);
12550 }
12551
12552 /* cursor */
12553 hw_entry = &hw_ddb.cursor[pipe];
12554 sw_entry = &sw_ddb->cursor[pipe];
12555
12556 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12557 continue;
12558
12559 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12560 "(expected (%u,%u), found (%u,%u))\n",
12561 pipe_name(pipe),
12562 sw_entry->start, sw_entry->end,
12563 hw_entry->start, hw_entry->end);
12564 }
12565 }
12566
12567 static void
12568 check_connector_state(struct drm_device *dev)
12569 {
12570 struct intel_connector *connector;
12571
12572 for_each_intel_connector(dev, connector) {
12573 /* This also checks the encoder/connector hw state with the
12574 * ->get_hw_state callbacks. */
12575 intel_connector_check_state(connector);
12576
12577 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12578 "connector's staged encoder doesn't match current encoder\n");
12579 }
12580 }
12581
12582 static void
12583 check_encoder_state(struct drm_device *dev)
12584 {
12585 struct intel_encoder *encoder;
12586 struct intel_connector *connector;
12587
12588 for_each_intel_encoder(dev, encoder) {
12589 bool enabled = false;
12590 bool active = false;
12591 enum pipe pipe, tracked_pipe;
12592
12593 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12594 encoder->base.base.id,
12595 encoder->base.name);
12596
12597 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12598 "encoder's stage crtc doesn't match current crtc\n");
12599 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12600 "encoder's active_connectors set, but no crtc\n");
12601
12602 for_each_intel_connector(dev, connector) {
12603 if (connector->base.encoder != &encoder->base)
12604 continue;
12605 enabled = true;
12606 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12607 active = true;
12608 }
12609 /*
12610 * for MST connectors if we unplug the connector is gone
12611 * away but the encoder is still connected to a crtc
12612 * until a modeset happens in response to the hotplug.
12613 */
12614 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12615 continue;
12616
12617 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12618 "encoder's enabled state mismatch "
12619 "(expected %i, found %i)\n",
12620 !!encoder->base.crtc, enabled);
12621 I915_STATE_WARN(active && !encoder->base.crtc,
12622 "active encoder with no crtc\n");
12623
12624 I915_STATE_WARN(encoder->connectors_active != active,
12625 "encoder's computed active state doesn't match tracked active state "
12626 "(expected %i, found %i)\n", active, encoder->connectors_active);
12627
12628 active = encoder->get_hw_state(encoder, &pipe);
12629 I915_STATE_WARN(active != encoder->connectors_active,
12630 "encoder's hw state doesn't match sw tracking "
12631 "(expected %i, found %i)\n",
12632 encoder->connectors_active, active);
12633
12634 if (!encoder->base.crtc)
12635 continue;
12636
12637 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12638 I915_STATE_WARN(active && pipe != tracked_pipe,
12639 "active encoder's pipe doesn't match"
12640 "(expected %i, found %i)\n",
12641 tracked_pipe, pipe);
12642
12643 }
12644 }
12645
12646 static void
12647 check_crtc_state(struct drm_device *dev)
12648 {
12649 struct drm_i915_private *dev_priv = dev->dev_private;
12650 struct intel_crtc *crtc;
12651 struct intel_encoder *encoder;
12652 struct intel_crtc_state pipe_config;
12653
12654 for_each_intel_crtc(dev, crtc) {
12655 bool enabled = false;
12656 bool active = false;
12657
12658 memset(&pipe_config, 0, sizeof(pipe_config));
12659
12660 DRM_DEBUG_KMS("[CRTC:%d]\n",
12661 crtc->base.base.id);
12662
12663 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12664 "active crtc, but not enabled in sw tracking\n");
12665
12666 for_each_intel_encoder(dev, encoder) {
12667 if (encoder->base.crtc != &crtc->base)
12668 continue;
12669 enabled = true;
12670 if (encoder->connectors_active)
12671 active = true;
12672 }
12673
12674 I915_STATE_WARN(active != crtc->active,
12675 "crtc's computed active state doesn't match tracked active state "
12676 "(expected %i, found %i)\n", active, crtc->active);
12677 I915_STATE_WARN(enabled != crtc->base.state->enable,
12678 "crtc's computed enabled state doesn't match tracked enabled state "
12679 "(expected %i, found %i)\n", enabled,
12680 crtc->base.state->enable);
12681
12682 active = dev_priv->display.get_pipe_config(crtc,
12683 &pipe_config);
12684
12685 /* hw state is inconsistent with the pipe quirk */
12686 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12687 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12688 active = crtc->active;
12689
12690 for_each_intel_encoder(dev, encoder) {
12691 enum pipe pipe;
12692 if (encoder->base.crtc != &crtc->base)
12693 continue;
12694 if (encoder->get_hw_state(encoder, &pipe))
12695 encoder->get_config(encoder, &pipe_config);
12696 }
12697
12698 I915_STATE_WARN(crtc->active != active,
12699 "crtc active state doesn't match with hw state "
12700 "(expected %i, found %i)\n", crtc->active, active);
12701
12702 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12703 "transitional active state does not match atomic hw state "
12704 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12705
12706 if (active &&
12707 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12708 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12709 intel_dump_pipe_config(crtc, &pipe_config,
12710 "[hw state]");
12711 intel_dump_pipe_config(crtc, crtc->config,
12712 "[sw state]");
12713 }
12714 }
12715 }
12716
12717 static void
12718 check_shared_dpll_state(struct drm_device *dev)
12719 {
12720 struct drm_i915_private *dev_priv = dev->dev_private;
12721 struct intel_crtc *crtc;
12722 struct intel_dpll_hw_state dpll_hw_state;
12723 int i;
12724
12725 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12726 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12727 int enabled_crtcs = 0, active_crtcs = 0;
12728 bool active;
12729
12730 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12731
12732 DRM_DEBUG_KMS("%s\n", pll->name);
12733
12734 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12735
12736 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12737 "more active pll users than references: %i vs %i\n",
12738 pll->active, hweight32(pll->config.crtc_mask));
12739 I915_STATE_WARN(pll->active && !pll->on,
12740 "pll in active use but not on in sw tracking\n");
12741 I915_STATE_WARN(pll->on && !pll->active,
12742 "pll in on but not on in use in sw tracking\n");
12743 I915_STATE_WARN(pll->on != active,
12744 "pll on state mismatch (expected %i, found %i)\n",
12745 pll->on, active);
12746
12747 for_each_intel_crtc(dev, crtc) {
12748 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12749 enabled_crtcs++;
12750 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12751 active_crtcs++;
12752 }
12753 I915_STATE_WARN(pll->active != active_crtcs,
12754 "pll active crtcs mismatch (expected %i, found %i)\n",
12755 pll->active, active_crtcs);
12756 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12757 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12758 hweight32(pll->config.crtc_mask), enabled_crtcs);
12759
12760 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12761 sizeof(dpll_hw_state)),
12762 "pll hw state mismatch\n");
12763 }
12764 }
12765
12766 void
12767 intel_modeset_check_state(struct drm_device *dev)
12768 {
12769 check_wm_state(dev);
12770 check_connector_state(dev);
12771 check_encoder_state(dev);
12772 check_crtc_state(dev);
12773 check_shared_dpll_state(dev);
12774 }
12775
12776 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12777 int dotclock)
12778 {
12779 /*
12780 * FDI already provided one idea for the dotclock.
12781 * Yell if the encoder disagrees.
12782 */
12783 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12784 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12785 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12786 }
12787
12788 static void update_scanline_offset(struct intel_crtc *crtc)
12789 {
12790 struct drm_device *dev = crtc->base.dev;
12791
12792 /*
12793 * The scanline counter increments at the leading edge of hsync.
12794 *
12795 * On most platforms it starts counting from vtotal-1 on the
12796 * first active line. That means the scanline counter value is
12797 * always one less than what we would expect. Ie. just after
12798 * start of vblank, which also occurs at start of hsync (on the
12799 * last active line), the scanline counter will read vblank_start-1.
12800 *
12801 * On gen2 the scanline counter starts counting from 1 instead
12802 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12803 * to keep the value positive), instead of adding one.
12804 *
12805 * On HSW+ the behaviour of the scanline counter depends on the output
12806 * type. For DP ports it behaves like most other platforms, but on HDMI
12807 * there's an extra 1 line difference. So we need to add two instead of
12808 * one to the value.
12809 */
12810 if (IS_GEN2(dev)) {
12811 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12812 int vtotal;
12813
12814 vtotal = mode->crtc_vtotal;
12815 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12816 vtotal /= 2;
12817
12818 crtc->scanline_offset = vtotal - 1;
12819 } else if (HAS_DDI(dev) &&
12820 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12821 crtc->scanline_offset = 2;
12822 } else
12823 crtc->scanline_offset = 1;
12824 }
12825
12826 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12827 {
12828 struct drm_device *dev = state->dev;
12829 struct drm_i915_private *dev_priv = to_i915(dev);
12830 struct intel_shared_dpll_config *shared_dpll = NULL;
12831 struct intel_crtc *intel_crtc;
12832 struct intel_crtc_state *intel_crtc_state;
12833 struct drm_crtc *crtc;
12834 struct drm_crtc_state *crtc_state;
12835 int i;
12836
12837 if (!dev_priv->display.crtc_compute_clock)
12838 return;
12839
12840 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12841 int dpll;
12842
12843 intel_crtc = to_intel_crtc(crtc);
12844 intel_crtc_state = to_intel_crtc_state(crtc_state);
12845 dpll = intel_crtc_state->shared_dpll;
12846
12847 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12848 continue;
12849
12850 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12851
12852 if (!shared_dpll)
12853 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12854
12855 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12856 }
12857 }
12858
12859 /*
12860 * This implements the workaround described in the "notes" section of the mode
12861 * set sequence documentation. When going from no pipes or single pipe to
12862 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12863 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12864 */
12865 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12866 {
12867 struct drm_crtc_state *crtc_state;
12868 struct intel_crtc *intel_crtc;
12869 struct drm_crtc *crtc;
12870 struct intel_crtc_state *first_crtc_state = NULL;
12871 struct intel_crtc_state *other_crtc_state = NULL;
12872 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12873 int i;
12874
12875 /* look at all crtc's that are going to be enabled in during modeset */
12876 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12877 intel_crtc = to_intel_crtc(crtc);
12878
12879 if (!crtc_state->active || !needs_modeset(crtc_state))
12880 continue;
12881
12882 if (first_crtc_state) {
12883 other_crtc_state = to_intel_crtc_state(crtc_state);
12884 break;
12885 } else {
12886 first_crtc_state = to_intel_crtc_state(crtc_state);
12887 first_pipe = intel_crtc->pipe;
12888 }
12889 }
12890
12891 /* No workaround needed? */
12892 if (!first_crtc_state)
12893 return 0;
12894
12895 /* w/a possibly needed, check how many crtc's are already enabled. */
12896 for_each_intel_crtc(state->dev, intel_crtc) {
12897 struct intel_crtc_state *pipe_config;
12898
12899 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12900 if (IS_ERR(pipe_config))
12901 return PTR_ERR(pipe_config);
12902
12903 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12904
12905 if (!pipe_config->base.active ||
12906 needs_modeset(&pipe_config->base))
12907 continue;
12908
12909 /* 2 or more enabled crtcs means no need for w/a */
12910 if (enabled_pipe != INVALID_PIPE)
12911 return 0;
12912
12913 enabled_pipe = intel_crtc->pipe;
12914 }
12915
12916 if (enabled_pipe != INVALID_PIPE)
12917 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12918 else if (other_crtc_state)
12919 other_crtc_state->hsw_workaround_pipe = first_pipe;
12920
12921 return 0;
12922 }
12923
12924 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12925 {
12926 struct drm_crtc *crtc;
12927 struct drm_crtc_state *crtc_state;
12928 int ret = 0;
12929
12930 /* add all active pipes to the state */
12931 for_each_crtc(state->dev, crtc) {
12932 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12933 if (IS_ERR(crtc_state))
12934 return PTR_ERR(crtc_state);
12935
12936 if (!crtc_state->active || needs_modeset(crtc_state))
12937 continue;
12938
12939 crtc_state->mode_changed = true;
12940
12941 ret = drm_atomic_add_affected_connectors(state, crtc);
12942 if (ret)
12943 break;
12944
12945 ret = drm_atomic_add_affected_planes(state, crtc);
12946 if (ret)
12947 break;
12948 }
12949
12950 return ret;
12951 }
12952
12953
12954 /* Code that should eventually be part of atomic_check() */
12955 static int intel_modeset_checks(struct drm_atomic_state *state)
12956 {
12957 struct drm_device *dev = state->dev;
12958 struct drm_i915_private *dev_priv = dev->dev_private;
12959 int ret;
12960
12961 if (!check_digital_port_conflicts(state)) {
12962 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12963 return -EINVAL;
12964 }
12965
12966 /*
12967 * See if the config requires any additional preparation, e.g.
12968 * to adjust global state with pipes off. We need to do this
12969 * here so we can get the modeset_pipe updated config for the new
12970 * mode set on this crtc. For other crtcs we need to use the
12971 * adjusted_mode bits in the crtc directly.
12972 */
12973 if (dev_priv->display.modeset_calc_cdclk) {
12974 unsigned int cdclk;
12975
12976 ret = dev_priv->display.modeset_calc_cdclk(state);
12977
12978 cdclk = to_intel_atomic_state(state)->cdclk;
12979 if (!ret && cdclk != dev_priv->cdclk_freq)
12980 ret = intel_modeset_all_pipes(state);
12981
12982 if (ret < 0)
12983 return ret;
12984 } else
12985 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12986
12987 intel_modeset_clear_plls(state);
12988
12989 if (IS_HASWELL(dev))
12990 return haswell_mode_set_planes_workaround(state);
12991
12992 return 0;
12993 }
12994
12995 static int
12996 intel_modeset_compute_config(struct drm_atomic_state *state)
12997 {
12998 struct drm_crtc *crtc;
12999 struct drm_crtc_state *crtc_state;
13000 int ret, i;
13001 bool any_ms = false;
13002
13003 ret = drm_atomic_helper_check_modeset(state->dev, state);
13004 if (ret)
13005 return ret;
13006
13007 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13008 if (!crtc_state->enable) {
13009 if (needs_modeset(crtc_state))
13010 any_ms = true;
13011 continue;
13012 }
13013
13014 if (to_intel_crtc_state(crtc_state)->quirks &
13015 PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13016 ret = drm_atomic_add_affected_planes(state, crtc);
13017 if (ret)
13018 return ret;
13019
13020 /*
13021 * We ought to handle i915.fastboot here.
13022 * If no modeset is required and the primary plane has
13023 * a fb, update the members of crtc_state as needed,
13024 * and run the necessary updates during vblank evasion.
13025 */
13026 }
13027
13028 if (!needs_modeset(crtc_state)) {
13029 ret = drm_atomic_add_affected_connectors(state, crtc);
13030 if (ret)
13031 return ret;
13032 }
13033
13034 ret = intel_modeset_pipe_config(crtc,
13035 to_intel_crtc_state(crtc_state));
13036 if (ret)
13037 return ret;
13038
13039 if (needs_modeset(crtc_state))
13040 any_ms = true;
13041
13042 intel_dump_pipe_config(to_intel_crtc(crtc),
13043 to_intel_crtc_state(crtc_state),
13044 "[modeset]");
13045 }
13046
13047 if (any_ms) {
13048 ret = intel_modeset_checks(state);
13049
13050 if (ret)
13051 return ret;
13052 } else
13053 to_intel_atomic_state(state)->cdclk =
13054 to_i915(state->dev)->cdclk_freq;
13055
13056 return drm_atomic_helper_check_planes(state->dev, state);
13057 }
13058
13059 static int __intel_set_mode(struct drm_atomic_state *state)
13060 {
13061 struct drm_device *dev = state->dev;
13062 struct drm_i915_private *dev_priv = dev->dev_private;
13063 struct drm_crtc *crtc;
13064 struct drm_crtc_state *crtc_state;
13065 int ret = 0;
13066 int i;
13067 bool any_ms = false;
13068
13069 ret = drm_atomic_helper_prepare_planes(dev, state);
13070 if (ret)
13071 return ret;
13072
13073 drm_atomic_helper_swap_state(dev, state);
13074
13075 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13077
13078 if (!needs_modeset(crtc->state))
13079 continue;
13080
13081 any_ms = true;
13082 intel_pre_plane_update(intel_crtc);
13083
13084 if (crtc_state->active) {
13085 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13086 dev_priv->display.crtc_disable(crtc);
13087 intel_crtc->active = false;
13088 intel_disable_shared_dpll(intel_crtc);
13089 }
13090 }
13091
13092 /* Only after disabling all output pipelines that will be changed can we
13093 * update the the output configuration. */
13094 intel_modeset_update_state(state);
13095
13096 /* The state has been swaped above, so state actually contains the
13097 * old state now. */
13098 if (any_ms)
13099 modeset_update_crtc_power_domains(state);
13100
13101 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13102 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13103 if (needs_modeset(crtc->state) && crtc->state->active) {
13104 update_scanline_offset(to_intel_crtc(crtc));
13105 dev_priv->display.crtc_enable(crtc);
13106 }
13107
13108 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13109 }
13110
13111 /* FIXME: add subpixel order */
13112
13113 drm_atomic_helper_cleanup_planes(dev, state);
13114
13115 drm_atomic_state_free(state);
13116
13117 return 0;
13118 }
13119
13120 static int intel_set_mode_checked(struct drm_atomic_state *state)
13121 {
13122 struct drm_device *dev = state->dev;
13123 int ret;
13124
13125 ret = __intel_set_mode(state);
13126 if (ret == 0)
13127 intel_modeset_check_state(dev);
13128
13129 return ret;
13130 }
13131
13132 static int intel_set_mode(struct drm_atomic_state *state)
13133 {
13134 int ret;
13135
13136 ret = intel_modeset_compute_config(state);
13137 if (ret)
13138 return ret;
13139
13140 return intel_set_mode_checked(state);
13141 }
13142
13143 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13144 {
13145 struct drm_device *dev = crtc->dev;
13146 struct drm_atomic_state *state;
13147 struct intel_encoder *encoder;
13148 struct intel_connector *connector;
13149 struct drm_connector_state *connector_state;
13150 struct intel_crtc_state *crtc_state;
13151 int ret;
13152
13153 state = drm_atomic_state_alloc(dev);
13154 if (!state) {
13155 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13156 crtc->base.id);
13157 return;
13158 }
13159
13160 state->acquire_ctx = dev->mode_config.acquire_ctx;
13161
13162 /* The force restore path in the HW readout code relies on the staged
13163 * config still keeping the user requested config while the actual
13164 * state has been overwritten by the configuration read from HW. We
13165 * need to copy the staged config to the atomic state, otherwise the
13166 * mode set will just reapply the state the HW is already in. */
13167 for_each_intel_encoder(dev, encoder) {
13168 if (&encoder->new_crtc->base != crtc)
13169 continue;
13170
13171 for_each_intel_connector(dev, connector) {
13172 if (connector->new_encoder != encoder)
13173 continue;
13174
13175 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13176 if (IS_ERR(connector_state)) {
13177 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13178 connector->base.base.id,
13179 connector->base.name,
13180 PTR_ERR(connector_state));
13181 continue;
13182 }
13183
13184 connector_state->crtc = crtc;
13185 connector_state->best_encoder = &encoder->base;
13186 }
13187 }
13188
13189 crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13190 if (IS_ERR(crtc_state)) {
13191 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13192 crtc->base.id, PTR_ERR(crtc_state));
13193 drm_atomic_state_free(state);
13194 return;
13195 }
13196
13197 crtc_state->base.active = crtc_state->base.enable =
13198 to_intel_crtc(crtc)->new_enabled;
13199
13200 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13201
13202 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13203 crtc->primary->fb, crtc->x, crtc->y);
13204
13205 ret = intel_set_mode(state);
13206 if (ret)
13207 drm_atomic_state_free(state);
13208 }
13209
13210 #undef for_each_intel_crtc_masked
13211
13212 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13213 struct drm_mode_set *set)
13214 {
13215 int ro;
13216
13217 for (ro = 0; ro < set->num_connectors; ro++)
13218 if (set->connectors[ro] == &connector->base)
13219 return true;
13220
13221 return false;
13222 }
13223
13224 static int
13225 intel_modeset_stage_output_state(struct drm_device *dev,
13226 struct drm_mode_set *set,
13227 struct drm_atomic_state *state)
13228 {
13229 struct intel_connector *connector;
13230 struct drm_connector *drm_connector;
13231 struct drm_connector_state *connector_state;
13232 struct drm_crtc *crtc;
13233 struct drm_crtc_state *crtc_state;
13234 int i, ret;
13235
13236 /* The upper layers ensure that we either disable a crtc or have a list
13237 * of connectors. For paranoia, double-check this. */
13238 WARN_ON(!set->fb && (set->num_connectors != 0));
13239 WARN_ON(set->fb && (set->num_connectors == 0));
13240
13241 for_each_intel_connector(dev, connector) {
13242 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13243
13244 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13245 continue;
13246
13247 connector_state =
13248 drm_atomic_get_connector_state(state, &connector->base);
13249 if (IS_ERR(connector_state))
13250 return PTR_ERR(connector_state);
13251
13252 if (in_mode_set) {
13253 int pipe = to_intel_crtc(set->crtc)->pipe;
13254 connector_state->best_encoder =
13255 &intel_find_encoder(connector, pipe)->base;
13256 }
13257
13258 if (connector->base.state->crtc != set->crtc)
13259 continue;
13260
13261 /* If we disable the crtc, disable all its connectors. Also, if
13262 * the connector is on the changing crtc but not on the new
13263 * connector list, disable it. */
13264 if (!set->fb || !in_mode_set) {
13265 connector_state->best_encoder = NULL;
13266
13267 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13268 connector->base.base.id,
13269 connector->base.name);
13270 }
13271 }
13272 /* connector->new_encoder is now updated for all connectors. */
13273
13274 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13275 connector = to_intel_connector(drm_connector);
13276
13277 if (!connector_state->best_encoder) {
13278 ret = drm_atomic_set_crtc_for_connector(connector_state,
13279 NULL);
13280 if (ret)
13281 return ret;
13282
13283 continue;
13284 }
13285
13286 if (intel_connector_in_mode_set(connector, set)) {
13287 struct drm_crtc *crtc = connector->base.state->crtc;
13288
13289 /* If this connector was in a previous crtc, add it
13290 * to the state. We might need to disable it. */
13291 if (crtc) {
13292 crtc_state =
13293 drm_atomic_get_crtc_state(state, crtc);
13294 if (IS_ERR(crtc_state))
13295 return PTR_ERR(crtc_state);
13296 }
13297
13298 ret = drm_atomic_set_crtc_for_connector(connector_state,
13299 set->crtc);
13300 if (ret)
13301 return ret;
13302 }
13303
13304 /* Make sure the new CRTC will work with the encoder */
13305 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13306 connector_state->crtc)) {
13307 return -EINVAL;
13308 }
13309
13310 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13311 connector->base.base.id,
13312 connector->base.name,
13313 connector_state->crtc->base.id);
13314
13315 if (connector_state->best_encoder != &connector->encoder->base)
13316 connector->encoder =
13317 to_intel_encoder(connector_state->best_encoder);
13318 }
13319
13320 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13321 bool has_connectors;
13322
13323 ret = drm_atomic_add_affected_connectors(state, crtc);
13324 if (ret)
13325 return ret;
13326
13327 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13328 if (has_connectors != crtc_state->enable)
13329 crtc_state->enable =
13330 crtc_state->active = has_connectors;
13331 }
13332
13333 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13334 set->fb, set->x, set->y);
13335 if (ret)
13336 return ret;
13337
13338 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13339 if (IS_ERR(crtc_state))
13340 return PTR_ERR(crtc_state);
13341
13342 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13343 if (ret)
13344 return ret;
13345
13346 if (set->num_connectors)
13347 crtc_state->active = true;
13348
13349 return 0;
13350 }
13351
13352 static int intel_crtc_set_config(struct drm_mode_set *set)
13353 {
13354 struct drm_device *dev;
13355 struct drm_atomic_state *state = NULL;
13356 int ret;
13357
13358 BUG_ON(!set);
13359 BUG_ON(!set->crtc);
13360 BUG_ON(!set->crtc->helper_private);
13361
13362 /* Enforce sane interface api - has been abused by the fb helper. */
13363 BUG_ON(!set->mode && set->fb);
13364 BUG_ON(set->fb && set->num_connectors == 0);
13365
13366 if (set->fb) {
13367 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13368 set->crtc->base.id, set->fb->base.id,
13369 (int)set->num_connectors, set->x, set->y);
13370 } else {
13371 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13372 }
13373
13374 dev = set->crtc->dev;
13375
13376 state = drm_atomic_state_alloc(dev);
13377 if (!state)
13378 return -ENOMEM;
13379
13380 state->acquire_ctx = dev->mode_config.acquire_ctx;
13381
13382 ret = intel_modeset_stage_output_state(dev, set, state);
13383 if (ret)
13384 goto out;
13385
13386 ret = intel_modeset_compute_config(state);
13387 if (ret)
13388 goto out;
13389
13390 intel_update_pipe_size(to_intel_crtc(set->crtc));
13391
13392 ret = intel_set_mode_checked(state);
13393 if (ret) {
13394 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13395 set->crtc->base.id, ret);
13396 }
13397
13398 out:
13399 if (ret)
13400 drm_atomic_state_free(state);
13401 return ret;
13402 }
13403
13404 static const struct drm_crtc_funcs intel_crtc_funcs = {
13405 .gamma_set = intel_crtc_gamma_set,
13406 .set_config = intel_crtc_set_config,
13407 .destroy = intel_crtc_destroy,
13408 .page_flip = intel_crtc_page_flip,
13409 .atomic_duplicate_state = intel_crtc_duplicate_state,
13410 .atomic_destroy_state = intel_crtc_destroy_state,
13411 };
13412
13413 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13414 struct intel_shared_dpll *pll,
13415 struct intel_dpll_hw_state *hw_state)
13416 {
13417 uint32_t val;
13418
13419 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13420 return false;
13421
13422 val = I915_READ(PCH_DPLL(pll->id));
13423 hw_state->dpll = val;
13424 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13425 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13426
13427 return val & DPLL_VCO_ENABLE;
13428 }
13429
13430 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13431 struct intel_shared_dpll *pll)
13432 {
13433 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13434 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13435 }
13436
13437 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13438 struct intel_shared_dpll *pll)
13439 {
13440 /* PCH refclock must be enabled first */
13441 ibx_assert_pch_refclk_enabled(dev_priv);
13442
13443 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13444
13445 /* Wait for the clocks to stabilize. */
13446 POSTING_READ(PCH_DPLL(pll->id));
13447 udelay(150);
13448
13449 /* The pixel multiplier can only be updated once the
13450 * DPLL is enabled and the clocks are stable.
13451 *
13452 * So write it again.
13453 */
13454 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13455 POSTING_READ(PCH_DPLL(pll->id));
13456 udelay(200);
13457 }
13458
13459 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13460 struct intel_shared_dpll *pll)
13461 {
13462 struct drm_device *dev = dev_priv->dev;
13463 struct intel_crtc *crtc;
13464
13465 /* Make sure no transcoder isn't still depending on us. */
13466 for_each_intel_crtc(dev, crtc) {
13467 if (intel_crtc_to_shared_dpll(crtc) == pll)
13468 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13469 }
13470
13471 I915_WRITE(PCH_DPLL(pll->id), 0);
13472 POSTING_READ(PCH_DPLL(pll->id));
13473 udelay(200);
13474 }
13475
13476 static char *ibx_pch_dpll_names[] = {
13477 "PCH DPLL A",
13478 "PCH DPLL B",
13479 };
13480
13481 static void ibx_pch_dpll_init(struct drm_device *dev)
13482 {
13483 struct drm_i915_private *dev_priv = dev->dev_private;
13484 int i;
13485
13486 dev_priv->num_shared_dpll = 2;
13487
13488 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13489 dev_priv->shared_dplls[i].id = i;
13490 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13491 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13492 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13493 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13494 dev_priv->shared_dplls[i].get_hw_state =
13495 ibx_pch_dpll_get_hw_state;
13496 }
13497 }
13498
13499 static void intel_shared_dpll_init(struct drm_device *dev)
13500 {
13501 struct drm_i915_private *dev_priv = dev->dev_private;
13502
13503 intel_update_cdclk(dev);
13504
13505 if (HAS_DDI(dev))
13506 intel_ddi_pll_init(dev);
13507 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13508 ibx_pch_dpll_init(dev);
13509 else
13510 dev_priv->num_shared_dpll = 0;
13511
13512 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13513 }
13514
13515 /**
13516 * intel_prepare_plane_fb - Prepare fb for usage on plane
13517 * @plane: drm plane to prepare for
13518 * @fb: framebuffer to prepare for presentation
13519 *
13520 * Prepares a framebuffer for usage on a display plane. Generally this
13521 * involves pinning the underlying object and updating the frontbuffer tracking
13522 * bits. Some older platforms need special physical address handling for
13523 * cursor planes.
13524 *
13525 * Returns 0 on success, negative error code on failure.
13526 */
13527 int
13528 intel_prepare_plane_fb(struct drm_plane *plane,
13529 struct drm_framebuffer *fb,
13530 const struct drm_plane_state *new_state)
13531 {
13532 struct drm_device *dev = plane->dev;
13533 struct intel_plane *intel_plane = to_intel_plane(plane);
13534 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13535 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13536 int ret = 0;
13537
13538 if (!obj)
13539 return 0;
13540
13541 mutex_lock(&dev->struct_mutex);
13542
13543 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13544 INTEL_INFO(dev)->cursor_needs_physical) {
13545 int align = IS_I830(dev) ? 16 * 1024 : 256;
13546 ret = i915_gem_object_attach_phys(obj, align);
13547 if (ret)
13548 DRM_DEBUG_KMS("failed to attach phys object\n");
13549 } else {
13550 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13551 }
13552
13553 if (ret == 0)
13554 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13555
13556 mutex_unlock(&dev->struct_mutex);
13557
13558 return ret;
13559 }
13560
13561 /**
13562 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13563 * @plane: drm plane to clean up for
13564 * @fb: old framebuffer that was on plane
13565 *
13566 * Cleans up a framebuffer that has just been removed from a plane.
13567 */
13568 void
13569 intel_cleanup_plane_fb(struct drm_plane *plane,
13570 struct drm_framebuffer *fb,
13571 const struct drm_plane_state *old_state)
13572 {
13573 struct drm_device *dev = plane->dev;
13574 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13575
13576 if (WARN_ON(!obj))
13577 return;
13578
13579 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13580 !INTEL_INFO(dev)->cursor_needs_physical) {
13581 mutex_lock(&dev->struct_mutex);
13582 intel_unpin_fb_obj(fb, old_state);
13583 mutex_unlock(&dev->struct_mutex);
13584 }
13585 }
13586
13587 int
13588 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13589 {
13590 int max_scale;
13591 struct drm_device *dev;
13592 struct drm_i915_private *dev_priv;
13593 int crtc_clock, cdclk;
13594
13595 if (!intel_crtc || !crtc_state)
13596 return DRM_PLANE_HELPER_NO_SCALING;
13597
13598 dev = intel_crtc->base.dev;
13599 dev_priv = dev->dev_private;
13600 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13601 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13602
13603 if (!crtc_clock || !cdclk)
13604 return DRM_PLANE_HELPER_NO_SCALING;
13605
13606 /*
13607 * skl max scale is lower of:
13608 * close to 3 but not 3, -1 is for that purpose
13609 * or
13610 * cdclk/crtc_clock
13611 */
13612 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13613
13614 return max_scale;
13615 }
13616
13617 static int
13618 intel_check_primary_plane(struct drm_plane *plane,
13619 struct intel_crtc_state *crtc_state,
13620 struct intel_plane_state *state)
13621 {
13622 struct drm_crtc *crtc = state->base.crtc;
13623 struct drm_framebuffer *fb = state->base.fb;
13624 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13625 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13626 bool can_position = false;
13627
13628 /* use scaler when colorkey is not required */
13629 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13630 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13631 min_scale = 1;
13632 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13633 can_position = true;
13634 }
13635
13636 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13637 &state->dst, &state->clip,
13638 min_scale, max_scale,
13639 can_position, true,
13640 &state->visible);
13641 }
13642
13643 static void
13644 intel_commit_primary_plane(struct drm_plane *plane,
13645 struct intel_plane_state *state)
13646 {
13647 struct drm_crtc *crtc = state->base.crtc;
13648 struct drm_framebuffer *fb = state->base.fb;
13649 struct drm_device *dev = plane->dev;
13650 struct drm_i915_private *dev_priv = dev->dev_private;
13651 struct intel_crtc *intel_crtc;
13652 struct drm_rect *src = &state->src;
13653
13654 crtc = crtc ? crtc : plane->crtc;
13655 intel_crtc = to_intel_crtc(crtc);
13656
13657 plane->fb = fb;
13658 crtc->x = src->x1 >> 16;
13659 crtc->y = src->y1 >> 16;
13660
13661 if (!crtc->state->active)
13662 return;
13663
13664 if (state->visible)
13665 /* FIXME: kill this fastboot hack */
13666 intel_update_pipe_size(intel_crtc);
13667
13668 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13669 }
13670
13671 static void
13672 intel_disable_primary_plane(struct drm_plane *plane,
13673 struct drm_crtc *crtc)
13674 {
13675 struct drm_device *dev = plane->dev;
13676 struct drm_i915_private *dev_priv = dev->dev_private;
13677
13678 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13679 }
13680
13681 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13682 {
13683 struct drm_device *dev = crtc->dev;
13684 struct drm_i915_private *dev_priv = dev->dev_private;
13685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13686
13687 if (!needs_modeset(crtc->state))
13688 intel_pre_plane_update(intel_crtc);
13689
13690 if (intel_crtc->atomic.update_wm)
13691 intel_update_watermarks(crtc);
13692
13693 intel_runtime_pm_get(dev_priv);
13694
13695 /* Perform vblank evasion around commit operation */
13696 if (crtc->state->active)
13697 intel_crtc->atomic.evade =
13698 intel_pipe_update_start(intel_crtc,
13699 &intel_crtc->atomic.start_vbl_count);
13700
13701 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13702 skl_detach_scalers(intel_crtc);
13703 }
13704
13705 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13706 {
13707 struct drm_device *dev = crtc->dev;
13708 struct drm_i915_private *dev_priv = dev->dev_private;
13709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13710
13711 if (intel_crtc->atomic.evade)
13712 intel_pipe_update_end(intel_crtc,
13713 intel_crtc->atomic.start_vbl_count);
13714
13715 intel_runtime_pm_put(dev_priv);
13716
13717 intel_post_plane_update(intel_crtc);
13718 }
13719
13720 /**
13721 * intel_plane_destroy - destroy a plane
13722 * @plane: plane to destroy
13723 *
13724 * Common destruction function for all types of planes (primary, cursor,
13725 * sprite).
13726 */
13727 void intel_plane_destroy(struct drm_plane *plane)
13728 {
13729 struct intel_plane *intel_plane = to_intel_plane(plane);
13730 drm_plane_cleanup(plane);
13731 kfree(intel_plane);
13732 }
13733
13734 const struct drm_plane_funcs intel_plane_funcs = {
13735 .update_plane = drm_atomic_helper_update_plane,
13736 .disable_plane = drm_atomic_helper_disable_plane,
13737 .destroy = intel_plane_destroy,
13738 .set_property = drm_atomic_helper_plane_set_property,
13739 .atomic_get_property = intel_plane_atomic_get_property,
13740 .atomic_set_property = intel_plane_atomic_set_property,
13741 .atomic_duplicate_state = intel_plane_duplicate_state,
13742 .atomic_destroy_state = intel_plane_destroy_state,
13743
13744 };
13745
13746 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13747 int pipe)
13748 {
13749 struct intel_plane *primary;
13750 struct intel_plane_state *state;
13751 const uint32_t *intel_primary_formats;
13752 int num_formats;
13753
13754 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13755 if (primary == NULL)
13756 return NULL;
13757
13758 state = intel_create_plane_state(&primary->base);
13759 if (!state) {
13760 kfree(primary);
13761 return NULL;
13762 }
13763 primary->base.state = &state->base;
13764
13765 primary->can_scale = false;
13766 primary->max_downscale = 1;
13767 if (INTEL_INFO(dev)->gen >= 9) {
13768 primary->can_scale = true;
13769 state->scaler_id = -1;
13770 }
13771 primary->pipe = pipe;
13772 primary->plane = pipe;
13773 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13774 primary->check_plane = intel_check_primary_plane;
13775 primary->commit_plane = intel_commit_primary_plane;
13776 primary->disable_plane = intel_disable_primary_plane;
13777 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13778 primary->plane = !pipe;
13779
13780 if (INTEL_INFO(dev)->gen >= 9) {
13781 intel_primary_formats = skl_primary_formats;
13782 num_formats = ARRAY_SIZE(skl_primary_formats);
13783 } else if (INTEL_INFO(dev)->gen >= 4) {
13784 intel_primary_formats = i965_primary_formats;
13785 num_formats = ARRAY_SIZE(i965_primary_formats);
13786 } else {
13787 intel_primary_formats = i8xx_primary_formats;
13788 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13789 }
13790
13791 drm_universal_plane_init(dev, &primary->base, 0,
13792 &intel_plane_funcs,
13793 intel_primary_formats, num_formats,
13794 DRM_PLANE_TYPE_PRIMARY);
13795
13796 if (INTEL_INFO(dev)->gen >= 4)
13797 intel_create_rotation_property(dev, primary);
13798
13799 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13800
13801 return &primary->base;
13802 }
13803
13804 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13805 {
13806 if (!dev->mode_config.rotation_property) {
13807 unsigned long flags = BIT(DRM_ROTATE_0) |
13808 BIT(DRM_ROTATE_180);
13809
13810 if (INTEL_INFO(dev)->gen >= 9)
13811 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13812
13813 dev->mode_config.rotation_property =
13814 drm_mode_create_rotation_property(dev, flags);
13815 }
13816 if (dev->mode_config.rotation_property)
13817 drm_object_attach_property(&plane->base.base,
13818 dev->mode_config.rotation_property,
13819 plane->base.state->rotation);
13820 }
13821
13822 static int
13823 intel_check_cursor_plane(struct drm_plane *plane,
13824 struct intel_crtc_state *crtc_state,
13825 struct intel_plane_state *state)
13826 {
13827 struct drm_crtc *crtc = crtc_state->base.crtc;
13828 struct drm_framebuffer *fb = state->base.fb;
13829 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13830 unsigned stride;
13831 int ret;
13832
13833 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13834 &state->dst, &state->clip,
13835 DRM_PLANE_HELPER_NO_SCALING,
13836 DRM_PLANE_HELPER_NO_SCALING,
13837 true, true, &state->visible);
13838 if (ret)
13839 return ret;
13840
13841 /* if we want to turn off the cursor ignore width and height */
13842 if (!obj)
13843 return 0;
13844
13845 /* Check for which cursor types we support */
13846 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13847 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13848 state->base.crtc_w, state->base.crtc_h);
13849 return -EINVAL;
13850 }
13851
13852 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13853 if (obj->base.size < stride * state->base.crtc_h) {
13854 DRM_DEBUG_KMS("buffer is too small\n");
13855 return -ENOMEM;
13856 }
13857
13858 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13859 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13860 return -EINVAL;
13861 }
13862
13863 return 0;
13864 }
13865
13866 static void
13867 intel_disable_cursor_plane(struct drm_plane *plane,
13868 struct drm_crtc *crtc)
13869 {
13870 intel_crtc_update_cursor(crtc, false);
13871 }
13872
13873 static void
13874 intel_commit_cursor_plane(struct drm_plane *plane,
13875 struct intel_plane_state *state)
13876 {
13877 struct drm_crtc *crtc = state->base.crtc;
13878 struct drm_device *dev = plane->dev;
13879 struct intel_crtc *intel_crtc;
13880 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13881 uint32_t addr;
13882
13883 crtc = crtc ? crtc : plane->crtc;
13884 intel_crtc = to_intel_crtc(crtc);
13885
13886 plane->fb = state->base.fb;
13887 crtc->cursor_x = state->base.crtc_x;
13888 crtc->cursor_y = state->base.crtc_y;
13889
13890 if (intel_crtc->cursor_bo == obj)
13891 goto update;
13892
13893 if (!obj)
13894 addr = 0;
13895 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13896 addr = i915_gem_obj_ggtt_offset(obj);
13897 else
13898 addr = obj->phys_handle->busaddr;
13899
13900 intel_crtc->cursor_addr = addr;
13901 intel_crtc->cursor_bo = obj;
13902
13903 update:
13904 if (crtc->state->active)
13905 intel_crtc_update_cursor(crtc, state->visible);
13906 }
13907
13908 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13909 int pipe)
13910 {
13911 struct intel_plane *cursor;
13912 struct intel_plane_state *state;
13913
13914 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13915 if (cursor == NULL)
13916 return NULL;
13917
13918 state = intel_create_plane_state(&cursor->base);
13919 if (!state) {
13920 kfree(cursor);
13921 return NULL;
13922 }
13923 cursor->base.state = &state->base;
13924
13925 cursor->can_scale = false;
13926 cursor->max_downscale = 1;
13927 cursor->pipe = pipe;
13928 cursor->plane = pipe;
13929 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13930 cursor->check_plane = intel_check_cursor_plane;
13931 cursor->commit_plane = intel_commit_cursor_plane;
13932 cursor->disable_plane = intel_disable_cursor_plane;
13933
13934 drm_universal_plane_init(dev, &cursor->base, 0,
13935 &intel_plane_funcs,
13936 intel_cursor_formats,
13937 ARRAY_SIZE(intel_cursor_formats),
13938 DRM_PLANE_TYPE_CURSOR);
13939
13940 if (INTEL_INFO(dev)->gen >= 4) {
13941 if (!dev->mode_config.rotation_property)
13942 dev->mode_config.rotation_property =
13943 drm_mode_create_rotation_property(dev,
13944 BIT(DRM_ROTATE_0) |
13945 BIT(DRM_ROTATE_180));
13946 if (dev->mode_config.rotation_property)
13947 drm_object_attach_property(&cursor->base.base,
13948 dev->mode_config.rotation_property,
13949 state->base.rotation);
13950 }
13951
13952 if (INTEL_INFO(dev)->gen >=9)
13953 state->scaler_id = -1;
13954
13955 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13956
13957 return &cursor->base;
13958 }
13959
13960 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13961 struct intel_crtc_state *crtc_state)
13962 {
13963 int i;
13964 struct intel_scaler *intel_scaler;
13965 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13966
13967 for (i = 0; i < intel_crtc->num_scalers; i++) {
13968 intel_scaler = &scaler_state->scalers[i];
13969 intel_scaler->in_use = 0;
13970 intel_scaler->mode = PS_SCALER_MODE_DYN;
13971 }
13972
13973 scaler_state->scaler_id = -1;
13974 }
13975
13976 static void intel_crtc_init(struct drm_device *dev, int pipe)
13977 {
13978 struct drm_i915_private *dev_priv = dev->dev_private;
13979 struct intel_crtc *intel_crtc;
13980 struct intel_crtc_state *crtc_state = NULL;
13981 struct drm_plane *primary = NULL;
13982 struct drm_plane *cursor = NULL;
13983 int i, ret;
13984
13985 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13986 if (intel_crtc == NULL)
13987 return;
13988
13989 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13990 if (!crtc_state)
13991 goto fail;
13992 intel_crtc->config = crtc_state;
13993 intel_crtc->base.state = &crtc_state->base;
13994 crtc_state->base.crtc = &intel_crtc->base;
13995
13996 /* initialize shared scalers */
13997 if (INTEL_INFO(dev)->gen >= 9) {
13998 if (pipe == PIPE_C)
13999 intel_crtc->num_scalers = 1;
14000 else
14001 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14002
14003 skl_init_scalers(dev, intel_crtc, crtc_state);
14004 }
14005
14006 primary = intel_primary_plane_create(dev, pipe);
14007 if (!primary)
14008 goto fail;
14009
14010 cursor = intel_cursor_plane_create(dev, pipe);
14011 if (!cursor)
14012 goto fail;
14013
14014 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14015 cursor, &intel_crtc_funcs);
14016 if (ret)
14017 goto fail;
14018
14019 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14020 for (i = 0; i < 256; i++) {
14021 intel_crtc->lut_r[i] = i;
14022 intel_crtc->lut_g[i] = i;
14023 intel_crtc->lut_b[i] = i;
14024 }
14025
14026 /*
14027 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14028 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14029 */
14030 intel_crtc->pipe = pipe;
14031 intel_crtc->plane = pipe;
14032 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14033 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14034 intel_crtc->plane = !pipe;
14035 }
14036
14037 intel_crtc->cursor_base = ~0;
14038 intel_crtc->cursor_cntl = ~0;
14039 intel_crtc->cursor_size = ~0;
14040
14041 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14042 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14043 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14044 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14045
14046 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14047
14048 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14049 return;
14050
14051 fail:
14052 if (primary)
14053 drm_plane_cleanup(primary);
14054 if (cursor)
14055 drm_plane_cleanup(cursor);
14056 kfree(crtc_state);
14057 kfree(intel_crtc);
14058 }
14059
14060 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14061 {
14062 struct drm_encoder *encoder = connector->base.encoder;
14063 struct drm_device *dev = connector->base.dev;
14064
14065 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14066
14067 if (!encoder || WARN_ON(!encoder->crtc))
14068 return INVALID_PIPE;
14069
14070 return to_intel_crtc(encoder->crtc)->pipe;
14071 }
14072
14073 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14074 struct drm_file *file)
14075 {
14076 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14077 struct drm_crtc *drmmode_crtc;
14078 struct intel_crtc *crtc;
14079
14080 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14081
14082 if (!drmmode_crtc) {
14083 DRM_ERROR("no such CRTC id\n");
14084 return -ENOENT;
14085 }
14086
14087 crtc = to_intel_crtc(drmmode_crtc);
14088 pipe_from_crtc_id->pipe = crtc->pipe;
14089
14090 return 0;
14091 }
14092
14093 static int intel_encoder_clones(struct intel_encoder *encoder)
14094 {
14095 struct drm_device *dev = encoder->base.dev;
14096 struct intel_encoder *source_encoder;
14097 int index_mask = 0;
14098 int entry = 0;
14099
14100 for_each_intel_encoder(dev, source_encoder) {
14101 if (encoders_cloneable(encoder, source_encoder))
14102 index_mask |= (1 << entry);
14103
14104 entry++;
14105 }
14106
14107 return index_mask;
14108 }
14109
14110 static bool has_edp_a(struct drm_device *dev)
14111 {
14112 struct drm_i915_private *dev_priv = dev->dev_private;
14113
14114 if (!IS_MOBILE(dev))
14115 return false;
14116
14117 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14118 return false;
14119
14120 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14121 return false;
14122
14123 return true;
14124 }
14125
14126 static bool intel_crt_present(struct drm_device *dev)
14127 {
14128 struct drm_i915_private *dev_priv = dev->dev_private;
14129
14130 if (INTEL_INFO(dev)->gen >= 9)
14131 return false;
14132
14133 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14134 return false;
14135
14136 if (IS_CHERRYVIEW(dev))
14137 return false;
14138
14139 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14140 return false;
14141
14142 return true;
14143 }
14144
14145 static void intel_setup_outputs(struct drm_device *dev)
14146 {
14147 struct drm_i915_private *dev_priv = dev->dev_private;
14148 struct intel_encoder *encoder;
14149 bool dpd_is_edp = false;
14150
14151 intel_lvds_init(dev);
14152
14153 if (intel_crt_present(dev))
14154 intel_crt_init(dev);
14155
14156 if (IS_BROXTON(dev)) {
14157 /*
14158 * FIXME: Broxton doesn't support port detection via the
14159 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14160 * detect the ports.
14161 */
14162 intel_ddi_init(dev, PORT_A);
14163 intel_ddi_init(dev, PORT_B);
14164 intel_ddi_init(dev, PORT_C);
14165 } else if (HAS_DDI(dev)) {
14166 int found;
14167
14168 /*
14169 * Haswell uses DDI functions to detect digital outputs.
14170 * On SKL pre-D0 the strap isn't connected, so we assume
14171 * it's there.
14172 */
14173 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14174 /* WaIgnoreDDIAStrap: skl */
14175 if (found ||
14176 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14177 intel_ddi_init(dev, PORT_A);
14178
14179 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14180 * register */
14181 found = I915_READ(SFUSE_STRAP);
14182
14183 if (found & SFUSE_STRAP_DDIB_DETECTED)
14184 intel_ddi_init(dev, PORT_B);
14185 if (found & SFUSE_STRAP_DDIC_DETECTED)
14186 intel_ddi_init(dev, PORT_C);
14187 if (found & SFUSE_STRAP_DDID_DETECTED)
14188 intel_ddi_init(dev, PORT_D);
14189 } else if (HAS_PCH_SPLIT(dev)) {
14190 int found;
14191 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14192
14193 if (has_edp_a(dev))
14194 intel_dp_init(dev, DP_A, PORT_A);
14195
14196 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14197 /* PCH SDVOB multiplex with HDMIB */
14198 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14199 if (!found)
14200 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14201 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14202 intel_dp_init(dev, PCH_DP_B, PORT_B);
14203 }
14204
14205 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14206 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14207
14208 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14209 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14210
14211 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14212 intel_dp_init(dev, PCH_DP_C, PORT_C);
14213
14214 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14215 intel_dp_init(dev, PCH_DP_D, PORT_D);
14216 } else if (IS_VALLEYVIEW(dev)) {
14217 /*
14218 * The DP_DETECTED bit is the latched state of the DDC
14219 * SDA pin at boot. However since eDP doesn't require DDC
14220 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14221 * eDP ports may have been muxed to an alternate function.
14222 * Thus we can't rely on the DP_DETECTED bit alone to detect
14223 * eDP ports. Consult the VBT as well as DP_DETECTED to
14224 * detect eDP ports.
14225 */
14226 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14227 !intel_dp_is_edp(dev, PORT_B))
14228 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14229 PORT_B);
14230 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14231 intel_dp_is_edp(dev, PORT_B))
14232 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14233
14234 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14235 !intel_dp_is_edp(dev, PORT_C))
14236 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14237 PORT_C);
14238 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14239 intel_dp_is_edp(dev, PORT_C))
14240 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14241
14242 if (IS_CHERRYVIEW(dev)) {
14243 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14244 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14245 PORT_D);
14246 /* eDP not supported on port D, so don't check VBT */
14247 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14248 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14249 }
14250
14251 intel_dsi_init(dev);
14252 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14253 bool found = false;
14254
14255 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14256 DRM_DEBUG_KMS("probing SDVOB\n");
14257 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14258 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14259 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14260 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14261 }
14262
14263 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14264 intel_dp_init(dev, DP_B, PORT_B);
14265 }
14266
14267 /* Before G4X SDVOC doesn't have its own detect register */
14268
14269 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14270 DRM_DEBUG_KMS("probing SDVOC\n");
14271 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14272 }
14273
14274 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14275
14276 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14277 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14278 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14279 }
14280 if (SUPPORTS_INTEGRATED_DP(dev))
14281 intel_dp_init(dev, DP_C, PORT_C);
14282 }
14283
14284 if (SUPPORTS_INTEGRATED_DP(dev) &&
14285 (I915_READ(DP_D) & DP_DETECTED))
14286 intel_dp_init(dev, DP_D, PORT_D);
14287 } else if (IS_GEN2(dev))
14288 intel_dvo_init(dev);
14289
14290 if (SUPPORTS_TV(dev))
14291 intel_tv_init(dev);
14292
14293 intel_psr_init(dev);
14294
14295 for_each_intel_encoder(dev, encoder) {
14296 encoder->base.possible_crtcs = encoder->crtc_mask;
14297 encoder->base.possible_clones =
14298 intel_encoder_clones(encoder);
14299 }
14300
14301 intel_init_pch_refclk(dev);
14302
14303 drm_helper_move_panel_connectors_to_head(dev);
14304 }
14305
14306 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14307 {
14308 struct drm_device *dev = fb->dev;
14309 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14310
14311 drm_framebuffer_cleanup(fb);
14312 mutex_lock(&dev->struct_mutex);
14313 WARN_ON(!intel_fb->obj->framebuffer_references--);
14314 drm_gem_object_unreference(&intel_fb->obj->base);
14315 mutex_unlock(&dev->struct_mutex);
14316 kfree(intel_fb);
14317 }
14318
14319 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14320 struct drm_file *file,
14321 unsigned int *handle)
14322 {
14323 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14324 struct drm_i915_gem_object *obj = intel_fb->obj;
14325
14326 return drm_gem_handle_create(file, &obj->base, handle);
14327 }
14328
14329 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14330 .destroy = intel_user_framebuffer_destroy,
14331 .create_handle = intel_user_framebuffer_create_handle,
14332 };
14333
14334 static
14335 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14336 uint32_t pixel_format)
14337 {
14338 u32 gen = INTEL_INFO(dev)->gen;
14339
14340 if (gen >= 9) {
14341 /* "The stride in bytes must not exceed the of the size of 8K
14342 * pixels and 32K bytes."
14343 */
14344 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14345 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14346 return 32*1024;
14347 } else if (gen >= 4) {
14348 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14349 return 16*1024;
14350 else
14351 return 32*1024;
14352 } else if (gen >= 3) {
14353 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14354 return 8*1024;
14355 else
14356 return 16*1024;
14357 } else {
14358 /* XXX DSPC is limited to 4k tiled */
14359 return 8*1024;
14360 }
14361 }
14362
14363 static int intel_framebuffer_init(struct drm_device *dev,
14364 struct intel_framebuffer *intel_fb,
14365 struct drm_mode_fb_cmd2 *mode_cmd,
14366 struct drm_i915_gem_object *obj)
14367 {
14368 unsigned int aligned_height;
14369 int ret;
14370 u32 pitch_limit, stride_alignment;
14371
14372 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14373
14374 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14375 /* Enforce that fb modifier and tiling mode match, but only for
14376 * X-tiled. This is needed for FBC. */
14377 if (!!(obj->tiling_mode == I915_TILING_X) !=
14378 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14379 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14380 return -EINVAL;
14381 }
14382 } else {
14383 if (obj->tiling_mode == I915_TILING_X)
14384 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14385 else if (obj->tiling_mode == I915_TILING_Y) {
14386 DRM_DEBUG("No Y tiling for legacy addfb\n");
14387 return -EINVAL;
14388 }
14389 }
14390
14391 /* Passed in modifier sanity checking. */
14392 switch (mode_cmd->modifier[0]) {
14393 case I915_FORMAT_MOD_Y_TILED:
14394 case I915_FORMAT_MOD_Yf_TILED:
14395 if (INTEL_INFO(dev)->gen < 9) {
14396 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14397 mode_cmd->modifier[0]);
14398 return -EINVAL;
14399 }
14400 case DRM_FORMAT_MOD_NONE:
14401 case I915_FORMAT_MOD_X_TILED:
14402 break;
14403 default:
14404 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14405 mode_cmd->modifier[0]);
14406 return -EINVAL;
14407 }
14408
14409 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14410 mode_cmd->pixel_format);
14411 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14412 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14413 mode_cmd->pitches[0], stride_alignment);
14414 return -EINVAL;
14415 }
14416
14417 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14418 mode_cmd->pixel_format);
14419 if (mode_cmd->pitches[0] > pitch_limit) {
14420 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14421 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14422 "tiled" : "linear",
14423 mode_cmd->pitches[0], pitch_limit);
14424 return -EINVAL;
14425 }
14426
14427 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14428 mode_cmd->pitches[0] != obj->stride) {
14429 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14430 mode_cmd->pitches[0], obj->stride);
14431 return -EINVAL;
14432 }
14433
14434 /* Reject formats not supported by any plane early. */
14435 switch (mode_cmd->pixel_format) {
14436 case DRM_FORMAT_C8:
14437 case DRM_FORMAT_RGB565:
14438 case DRM_FORMAT_XRGB8888:
14439 case DRM_FORMAT_ARGB8888:
14440 break;
14441 case DRM_FORMAT_XRGB1555:
14442 if (INTEL_INFO(dev)->gen > 3) {
14443 DRM_DEBUG("unsupported pixel format: %s\n",
14444 drm_get_format_name(mode_cmd->pixel_format));
14445 return -EINVAL;
14446 }
14447 break;
14448 case DRM_FORMAT_ABGR8888:
14449 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14450 DRM_DEBUG("unsupported pixel format: %s\n",
14451 drm_get_format_name(mode_cmd->pixel_format));
14452 return -EINVAL;
14453 }
14454 break;
14455 case DRM_FORMAT_XBGR8888:
14456 case DRM_FORMAT_XRGB2101010:
14457 case DRM_FORMAT_XBGR2101010:
14458 if (INTEL_INFO(dev)->gen < 4) {
14459 DRM_DEBUG("unsupported pixel format: %s\n",
14460 drm_get_format_name(mode_cmd->pixel_format));
14461 return -EINVAL;
14462 }
14463 break;
14464 case DRM_FORMAT_ABGR2101010:
14465 if (!IS_VALLEYVIEW(dev)) {
14466 DRM_DEBUG("unsupported pixel format: %s\n",
14467 drm_get_format_name(mode_cmd->pixel_format));
14468 return -EINVAL;
14469 }
14470 break;
14471 case DRM_FORMAT_YUYV:
14472 case DRM_FORMAT_UYVY:
14473 case DRM_FORMAT_YVYU:
14474 case DRM_FORMAT_VYUY:
14475 if (INTEL_INFO(dev)->gen < 5) {
14476 DRM_DEBUG("unsupported pixel format: %s\n",
14477 drm_get_format_name(mode_cmd->pixel_format));
14478 return -EINVAL;
14479 }
14480 break;
14481 default:
14482 DRM_DEBUG("unsupported pixel format: %s\n",
14483 drm_get_format_name(mode_cmd->pixel_format));
14484 return -EINVAL;
14485 }
14486
14487 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14488 if (mode_cmd->offsets[0] != 0)
14489 return -EINVAL;
14490
14491 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14492 mode_cmd->pixel_format,
14493 mode_cmd->modifier[0]);
14494 /* FIXME drm helper for size checks (especially planar formats)? */
14495 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14496 return -EINVAL;
14497
14498 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14499 intel_fb->obj = obj;
14500 intel_fb->obj->framebuffer_references++;
14501
14502 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14503 if (ret) {
14504 DRM_ERROR("framebuffer init failed %d\n", ret);
14505 return ret;
14506 }
14507
14508 return 0;
14509 }
14510
14511 static struct drm_framebuffer *
14512 intel_user_framebuffer_create(struct drm_device *dev,
14513 struct drm_file *filp,
14514 struct drm_mode_fb_cmd2 *mode_cmd)
14515 {
14516 struct drm_i915_gem_object *obj;
14517
14518 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14519 mode_cmd->handles[0]));
14520 if (&obj->base == NULL)
14521 return ERR_PTR(-ENOENT);
14522
14523 return intel_framebuffer_create(dev, mode_cmd, obj);
14524 }
14525
14526 #ifndef CONFIG_DRM_I915_FBDEV
14527 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14528 {
14529 }
14530 #endif
14531
14532 static const struct drm_mode_config_funcs intel_mode_funcs = {
14533 .fb_create = intel_user_framebuffer_create,
14534 .output_poll_changed = intel_fbdev_output_poll_changed,
14535 .atomic_check = intel_atomic_check,
14536 .atomic_commit = intel_atomic_commit,
14537 .atomic_state_alloc = intel_atomic_state_alloc,
14538 .atomic_state_clear = intel_atomic_state_clear,
14539 };
14540
14541 /* Set up chip specific display functions */
14542 static void intel_init_display(struct drm_device *dev)
14543 {
14544 struct drm_i915_private *dev_priv = dev->dev_private;
14545
14546 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14547 dev_priv->display.find_dpll = g4x_find_best_dpll;
14548 else if (IS_CHERRYVIEW(dev))
14549 dev_priv->display.find_dpll = chv_find_best_dpll;
14550 else if (IS_VALLEYVIEW(dev))
14551 dev_priv->display.find_dpll = vlv_find_best_dpll;
14552 else if (IS_PINEVIEW(dev))
14553 dev_priv->display.find_dpll = pnv_find_best_dpll;
14554 else
14555 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14556
14557 if (INTEL_INFO(dev)->gen >= 9) {
14558 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14559 dev_priv->display.get_initial_plane_config =
14560 skylake_get_initial_plane_config;
14561 dev_priv->display.crtc_compute_clock =
14562 haswell_crtc_compute_clock;
14563 dev_priv->display.crtc_enable = haswell_crtc_enable;
14564 dev_priv->display.crtc_disable = haswell_crtc_disable;
14565 dev_priv->display.update_primary_plane =
14566 skylake_update_primary_plane;
14567 } else if (HAS_DDI(dev)) {
14568 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14569 dev_priv->display.get_initial_plane_config =
14570 ironlake_get_initial_plane_config;
14571 dev_priv->display.crtc_compute_clock =
14572 haswell_crtc_compute_clock;
14573 dev_priv->display.crtc_enable = haswell_crtc_enable;
14574 dev_priv->display.crtc_disable = haswell_crtc_disable;
14575 dev_priv->display.update_primary_plane =
14576 ironlake_update_primary_plane;
14577 } else if (HAS_PCH_SPLIT(dev)) {
14578 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14579 dev_priv->display.get_initial_plane_config =
14580 ironlake_get_initial_plane_config;
14581 dev_priv->display.crtc_compute_clock =
14582 ironlake_crtc_compute_clock;
14583 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14584 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14585 dev_priv->display.update_primary_plane =
14586 ironlake_update_primary_plane;
14587 } else if (IS_VALLEYVIEW(dev)) {
14588 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14589 dev_priv->display.get_initial_plane_config =
14590 i9xx_get_initial_plane_config;
14591 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14592 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14593 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14594 dev_priv->display.update_primary_plane =
14595 i9xx_update_primary_plane;
14596 } else {
14597 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14598 dev_priv->display.get_initial_plane_config =
14599 i9xx_get_initial_plane_config;
14600 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14601 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14602 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14603 dev_priv->display.update_primary_plane =
14604 i9xx_update_primary_plane;
14605 }
14606
14607 /* Returns the core display clock speed */
14608 if (IS_SKYLAKE(dev))
14609 dev_priv->display.get_display_clock_speed =
14610 skylake_get_display_clock_speed;
14611 else if (IS_BROXTON(dev))
14612 dev_priv->display.get_display_clock_speed =
14613 broxton_get_display_clock_speed;
14614 else if (IS_BROADWELL(dev))
14615 dev_priv->display.get_display_clock_speed =
14616 broadwell_get_display_clock_speed;
14617 else if (IS_HASWELL(dev))
14618 dev_priv->display.get_display_clock_speed =
14619 haswell_get_display_clock_speed;
14620 else if (IS_VALLEYVIEW(dev))
14621 dev_priv->display.get_display_clock_speed =
14622 valleyview_get_display_clock_speed;
14623 else if (IS_GEN5(dev))
14624 dev_priv->display.get_display_clock_speed =
14625 ilk_get_display_clock_speed;
14626 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14627 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14628 dev_priv->display.get_display_clock_speed =
14629 i945_get_display_clock_speed;
14630 else if (IS_GM45(dev))
14631 dev_priv->display.get_display_clock_speed =
14632 gm45_get_display_clock_speed;
14633 else if (IS_CRESTLINE(dev))
14634 dev_priv->display.get_display_clock_speed =
14635 i965gm_get_display_clock_speed;
14636 else if (IS_PINEVIEW(dev))
14637 dev_priv->display.get_display_clock_speed =
14638 pnv_get_display_clock_speed;
14639 else if (IS_G33(dev) || IS_G4X(dev))
14640 dev_priv->display.get_display_clock_speed =
14641 g33_get_display_clock_speed;
14642 else if (IS_I915G(dev))
14643 dev_priv->display.get_display_clock_speed =
14644 i915_get_display_clock_speed;
14645 else if (IS_I945GM(dev) || IS_845G(dev))
14646 dev_priv->display.get_display_clock_speed =
14647 i9xx_misc_get_display_clock_speed;
14648 else if (IS_PINEVIEW(dev))
14649 dev_priv->display.get_display_clock_speed =
14650 pnv_get_display_clock_speed;
14651 else if (IS_I915GM(dev))
14652 dev_priv->display.get_display_clock_speed =
14653 i915gm_get_display_clock_speed;
14654 else if (IS_I865G(dev))
14655 dev_priv->display.get_display_clock_speed =
14656 i865_get_display_clock_speed;
14657 else if (IS_I85X(dev))
14658 dev_priv->display.get_display_clock_speed =
14659 i85x_get_display_clock_speed;
14660 else { /* 830 */
14661 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14662 dev_priv->display.get_display_clock_speed =
14663 i830_get_display_clock_speed;
14664 }
14665
14666 if (IS_GEN5(dev)) {
14667 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14668 } else if (IS_GEN6(dev)) {
14669 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14670 } else if (IS_IVYBRIDGE(dev)) {
14671 /* FIXME: detect B0+ stepping and use auto training */
14672 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14673 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14674 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14675 if (IS_BROADWELL(dev)) {
14676 dev_priv->display.modeset_commit_cdclk =
14677 broadwell_modeset_commit_cdclk;
14678 dev_priv->display.modeset_calc_cdclk =
14679 broadwell_modeset_calc_cdclk;
14680 }
14681 } else if (IS_VALLEYVIEW(dev)) {
14682 dev_priv->display.modeset_commit_cdclk =
14683 valleyview_modeset_commit_cdclk;
14684 dev_priv->display.modeset_calc_cdclk =
14685 valleyview_modeset_calc_cdclk;
14686 } else if (IS_BROXTON(dev)) {
14687 dev_priv->display.modeset_commit_cdclk =
14688 broxton_modeset_commit_cdclk;
14689 dev_priv->display.modeset_calc_cdclk =
14690 broxton_modeset_calc_cdclk;
14691 }
14692
14693 switch (INTEL_INFO(dev)->gen) {
14694 case 2:
14695 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14696 break;
14697
14698 case 3:
14699 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14700 break;
14701
14702 case 4:
14703 case 5:
14704 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14705 break;
14706
14707 case 6:
14708 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14709 break;
14710 case 7:
14711 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14712 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14713 break;
14714 case 9:
14715 /* Drop through - unsupported since execlist only. */
14716 default:
14717 /* Default just returns -ENODEV to indicate unsupported */
14718 dev_priv->display.queue_flip = intel_default_queue_flip;
14719 }
14720
14721 intel_panel_init_backlight_funcs(dev);
14722
14723 mutex_init(&dev_priv->pps_mutex);
14724 }
14725
14726 /*
14727 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14728 * resume, or other times. This quirk makes sure that's the case for
14729 * affected systems.
14730 */
14731 static void quirk_pipea_force(struct drm_device *dev)
14732 {
14733 struct drm_i915_private *dev_priv = dev->dev_private;
14734
14735 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14736 DRM_INFO("applying pipe a force quirk\n");
14737 }
14738
14739 static void quirk_pipeb_force(struct drm_device *dev)
14740 {
14741 struct drm_i915_private *dev_priv = dev->dev_private;
14742
14743 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14744 DRM_INFO("applying pipe b force quirk\n");
14745 }
14746
14747 /*
14748 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14749 */
14750 static void quirk_ssc_force_disable(struct drm_device *dev)
14751 {
14752 struct drm_i915_private *dev_priv = dev->dev_private;
14753 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14754 DRM_INFO("applying lvds SSC disable quirk\n");
14755 }
14756
14757 /*
14758 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14759 * brightness value
14760 */
14761 static void quirk_invert_brightness(struct drm_device *dev)
14762 {
14763 struct drm_i915_private *dev_priv = dev->dev_private;
14764 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14765 DRM_INFO("applying inverted panel brightness quirk\n");
14766 }
14767
14768 /* Some VBT's incorrectly indicate no backlight is present */
14769 static void quirk_backlight_present(struct drm_device *dev)
14770 {
14771 struct drm_i915_private *dev_priv = dev->dev_private;
14772 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14773 DRM_INFO("applying backlight present quirk\n");
14774 }
14775
14776 struct intel_quirk {
14777 int device;
14778 int subsystem_vendor;
14779 int subsystem_device;
14780 void (*hook)(struct drm_device *dev);
14781 };
14782
14783 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14784 struct intel_dmi_quirk {
14785 void (*hook)(struct drm_device *dev);
14786 const struct dmi_system_id (*dmi_id_list)[];
14787 };
14788
14789 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14790 {
14791 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14792 return 1;
14793 }
14794
14795 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14796 {
14797 .dmi_id_list = &(const struct dmi_system_id[]) {
14798 {
14799 .callback = intel_dmi_reverse_brightness,
14800 .ident = "NCR Corporation",
14801 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14802 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14803 },
14804 },
14805 { } /* terminating entry */
14806 },
14807 .hook = quirk_invert_brightness,
14808 },
14809 };
14810
14811 static struct intel_quirk intel_quirks[] = {
14812 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14813 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14814
14815 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14816 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14817
14818 /* 830 needs to leave pipe A & dpll A up */
14819 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14820
14821 /* 830 needs to leave pipe B & dpll B up */
14822 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14823
14824 /* Lenovo U160 cannot use SSC on LVDS */
14825 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14826
14827 /* Sony Vaio Y cannot use SSC on LVDS */
14828 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14829
14830 /* Acer Aspire 5734Z must invert backlight brightness */
14831 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14832
14833 /* Acer/eMachines G725 */
14834 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14835
14836 /* Acer/eMachines e725 */
14837 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14838
14839 /* Acer/Packard Bell NCL20 */
14840 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14841
14842 /* Acer Aspire 4736Z */
14843 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14844
14845 /* Acer Aspire 5336 */
14846 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14847
14848 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14849 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14850
14851 /* Acer C720 Chromebook (Core i3 4005U) */
14852 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14853
14854 /* Apple Macbook 2,1 (Core 2 T7400) */
14855 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14856
14857 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14858 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14859
14860 /* HP Chromebook 14 (Celeron 2955U) */
14861 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14862
14863 /* Dell Chromebook 11 */
14864 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14865 };
14866
14867 static void intel_init_quirks(struct drm_device *dev)
14868 {
14869 struct pci_dev *d = dev->pdev;
14870 int i;
14871
14872 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14873 struct intel_quirk *q = &intel_quirks[i];
14874
14875 if (d->device == q->device &&
14876 (d->subsystem_vendor == q->subsystem_vendor ||
14877 q->subsystem_vendor == PCI_ANY_ID) &&
14878 (d->subsystem_device == q->subsystem_device ||
14879 q->subsystem_device == PCI_ANY_ID))
14880 q->hook(dev);
14881 }
14882 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14883 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14884 intel_dmi_quirks[i].hook(dev);
14885 }
14886 }
14887
14888 /* Disable the VGA plane that we never use */
14889 static void i915_disable_vga(struct drm_device *dev)
14890 {
14891 struct drm_i915_private *dev_priv = dev->dev_private;
14892 u8 sr1;
14893 u32 vga_reg = i915_vgacntrl_reg(dev);
14894
14895 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14896 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14897 outb(SR01, VGA_SR_INDEX);
14898 sr1 = inb(VGA_SR_DATA);
14899 outb(sr1 | 1<<5, VGA_SR_DATA);
14900 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14901 udelay(300);
14902
14903 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14904 POSTING_READ(vga_reg);
14905 }
14906
14907 void intel_modeset_init_hw(struct drm_device *dev)
14908 {
14909 intel_update_cdclk(dev);
14910 intel_prepare_ddi(dev);
14911 intel_init_clock_gating(dev);
14912 intel_enable_gt_powersave(dev);
14913 }
14914
14915 void intel_modeset_init(struct drm_device *dev)
14916 {
14917 struct drm_i915_private *dev_priv = dev->dev_private;
14918 int sprite, ret;
14919 enum pipe pipe;
14920 struct intel_crtc *crtc;
14921
14922 drm_mode_config_init(dev);
14923
14924 dev->mode_config.min_width = 0;
14925 dev->mode_config.min_height = 0;
14926
14927 dev->mode_config.preferred_depth = 24;
14928 dev->mode_config.prefer_shadow = 1;
14929
14930 dev->mode_config.allow_fb_modifiers = true;
14931
14932 dev->mode_config.funcs = &intel_mode_funcs;
14933
14934 intel_init_quirks(dev);
14935
14936 intel_init_pm(dev);
14937
14938 if (INTEL_INFO(dev)->num_pipes == 0)
14939 return;
14940
14941 intel_init_display(dev);
14942 intel_init_audio(dev);
14943
14944 if (IS_GEN2(dev)) {
14945 dev->mode_config.max_width = 2048;
14946 dev->mode_config.max_height = 2048;
14947 } else if (IS_GEN3(dev)) {
14948 dev->mode_config.max_width = 4096;
14949 dev->mode_config.max_height = 4096;
14950 } else {
14951 dev->mode_config.max_width = 8192;
14952 dev->mode_config.max_height = 8192;
14953 }
14954
14955 if (IS_845G(dev) || IS_I865G(dev)) {
14956 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14957 dev->mode_config.cursor_height = 1023;
14958 } else if (IS_GEN2(dev)) {
14959 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14960 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14961 } else {
14962 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14963 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14964 }
14965
14966 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14967
14968 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14969 INTEL_INFO(dev)->num_pipes,
14970 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14971
14972 for_each_pipe(dev_priv, pipe) {
14973 intel_crtc_init(dev, pipe);
14974 for_each_sprite(dev_priv, pipe, sprite) {
14975 ret = intel_plane_init(dev, pipe, sprite);
14976 if (ret)
14977 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14978 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14979 }
14980 }
14981
14982 intel_init_dpio(dev);
14983
14984 intel_shared_dpll_init(dev);
14985
14986 /* Just disable it once at startup */
14987 i915_disable_vga(dev);
14988 intel_setup_outputs(dev);
14989
14990 /* Just in case the BIOS is doing something questionable. */
14991 intel_fbc_disable(dev);
14992
14993 drm_modeset_lock_all(dev);
14994 intel_modeset_setup_hw_state(dev, false);
14995 drm_modeset_unlock_all(dev);
14996
14997 for_each_intel_crtc(dev, crtc) {
14998 if (!crtc->active)
14999 continue;
15000
15001 /*
15002 * Note that reserving the BIOS fb up front prevents us
15003 * from stuffing other stolen allocations like the ring
15004 * on top. This prevents some ugliness at boot time, and
15005 * can even allow for smooth boot transitions if the BIOS
15006 * fb is large enough for the active pipe configuration.
15007 */
15008 if (dev_priv->display.get_initial_plane_config) {
15009 dev_priv->display.get_initial_plane_config(crtc,
15010 &crtc->plane_config);
15011 /*
15012 * If the fb is shared between multiple heads, we'll
15013 * just get the first one.
15014 */
15015 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15016 }
15017 }
15018 }
15019
15020 static void intel_enable_pipe_a(struct drm_device *dev)
15021 {
15022 struct intel_connector *connector;
15023 struct drm_connector *crt = NULL;
15024 struct intel_load_detect_pipe load_detect_temp;
15025 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15026
15027 /* We can't just switch on the pipe A, we need to set things up with a
15028 * proper mode and output configuration. As a gross hack, enable pipe A
15029 * by enabling the load detect pipe once. */
15030 for_each_intel_connector(dev, connector) {
15031 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15032 crt = &connector->base;
15033 break;
15034 }
15035 }
15036
15037 if (!crt)
15038 return;
15039
15040 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15041 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15042 }
15043
15044 static bool
15045 intel_check_plane_mapping(struct intel_crtc *crtc)
15046 {
15047 struct drm_device *dev = crtc->base.dev;
15048 struct drm_i915_private *dev_priv = dev->dev_private;
15049 u32 reg, val;
15050
15051 if (INTEL_INFO(dev)->num_pipes == 1)
15052 return true;
15053
15054 reg = DSPCNTR(!crtc->plane);
15055 val = I915_READ(reg);
15056
15057 if ((val & DISPLAY_PLANE_ENABLE) &&
15058 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15059 return false;
15060
15061 return true;
15062 }
15063
15064 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15065 {
15066 struct drm_device *dev = crtc->base.dev;
15067 struct drm_i915_private *dev_priv = dev->dev_private;
15068 struct intel_encoder *encoder;
15069 u32 reg;
15070 bool enable;
15071
15072 /* Clear any frame start delays used for debugging left by the BIOS */
15073 reg = PIPECONF(crtc->config->cpu_transcoder);
15074 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15075
15076 /* restore vblank interrupts to correct state */
15077 drm_crtc_vblank_reset(&crtc->base);
15078 if (crtc->active) {
15079 update_scanline_offset(crtc);
15080 drm_crtc_vblank_on(&crtc->base);
15081 }
15082
15083 /* We need to sanitize the plane -> pipe mapping first because this will
15084 * disable the crtc (and hence change the state) if it is wrong. Note
15085 * that gen4+ has a fixed plane -> pipe mapping. */
15086 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15087 bool plane;
15088
15089 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15090 crtc->base.base.id);
15091
15092 /* Pipe has the wrong plane attached and the plane is active.
15093 * Temporarily change the plane mapping and disable everything
15094 * ... */
15095 plane = crtc->plane;
15096 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15097 crtc->plane = !plane;
15098 intel_crtc_disable_noatomic(&crtc->base);
15099 crtc->plane = plane;
15100 }
15101
15102 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15103 crtc->pipe == PIPE_A && !crtc->active) {
15104 /* BIOS forgot to enable pipe A, this mostly happens after
15105 * resume. Force-enable the pipe to fix this, the update_dpms
15106 * call below we restore the pipe to the right state, but leave
15107 * the required bits on. */
15108 intel_enable_pipe_a(dev);
15109 }
15110
15111 /* Adjust the state of the output pipe according to whether we
15112 * have active connectors/encoders. */
15113 enable = false;
15114 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15115 enable |= encoder->connectors_active;
15116
15117 if (!enable)
15118 intel_crtc_disable_noatomic(&crtc->base);
15119
15120 if (crtc->active != crtc->base.state->active) {
15121
15122 /* This can happen either due to bugs in the get_hw_state
15123 * functions or because of calls to intel_crtc_disable_noatomic,
15124 * or because the pipe is force-enabled due to the
15125 * pipe A quirk. */
15126 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15127 crtc->base.base.id,
15128 crtc->base.state->enable ? "enabled" : "disabled",
15129 crtc->active ? "enabled" : "disabled");
15130
15131 crtc->base.state->enable = crtc->active;
15132 crtc->base.state->active = crtc->active;
15133 crtc->base.enabled = crtc->active;
15134
15135 /* Because we only establish the connector -> encoder ->
15136 * crtc links if something is active, this means the
15137 * crtc is now deactivated. Break the links. connector
15138 * -> encoder links are only establish when things are
15139 * actually up, hence no need to break them. */
15140 WARN_ON(crtc->active);
15141
15142 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15143 WARN_ON(encoder->connectors_active);
15144 encoder->base.crtc = NULL;
15145 }
15146 }
15147
15148 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15149 /*
15150 * We start out with underrun reporting disabled to avoid races.
15151 * For correct bookkeeping mark this on active crtcs.
15152 *
15153 * Also on gmch platforms we dont have any hardware bits to
15154 * disable the underrun reporting. Which means we need to start
15155 * out with underrun reporting disabled also on inactive pipes,
15156 * since otherwise we'll complain about the garbage we read when
15157 * e.g. coming up after runtime pm.
15158 *
15159 * No protection against concurrent access is required - at
15160 * worst a fifo underrun happens which also sets this to false.
15161 */
15162 crtc->cpu_fifo_underrun_disabled = true;
15163 crtc->pch_fifo_underrun_disabled = true;
15164 }
15165 }
15166
15167 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15168 {
15169 struct intel_connector *connector;
15170 struct drm_device *dev = encoder->base.dev;
15171
15172 /* We need to check both for a crtc link (meaning that the
15173 * encoder is active and trying to read from a pipe) and the
15174 * pipe itself being active. */
15175 bool has_active_crtc = encoder->base.crtc &&
15176 to_intel_crtc(encoder->base.crtc)->active;
15177
15178 if (encoder->connectors_active && !has_active_crtc) {
15179 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15180 encoder->base.base.id,
15181 encoder->base.name);
15182
15183 /* Connector is active, but has no active pipe. This is
15184 * fallout from our resume register restoring. Disable
15185 * the encoder manually again. */
15186 if (encoder->base.crtc) {
15187 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15188 encoder->base.base.id,
15189 encoder->base.name);
15190 encoder->disable(encoder);
15191 if (encoder->post_disable)
15192 encoder->post_disable(encoder);
15193 }
15194 encoder->base.crtc = NULL;
15195 encoder->connectors_active = false;
15196
15197 /* Inconsistent output/port/pipe state happens presumably due to
15198 * a bug in one of the get_hw_state functions. Or someplace else
15199 * in our code, like the register restore mess on resume. Clamp
15200 * things to off as a safer default. */
15201 for_each_intel_connector(dev, connector) {
15202 if (connector->encoder != encoder)
15203 continue;
15204 connector->base.dpms = DRM_MODE_DPMS_OFF;
15205 connector->base.encoder = NULL;
15206 }
15207 }
15208 /* Enabled encoders without active connectors will be fixed in
15209 * the crtc fixup. */
15210 }
15211
15212 void i915_redisable_vga_power_on(struct drm_device *dev)
15213 {
15214 struct drm_i915_private *dev_priv = dev->dev_private;
15215 u32 vga_reg = i915_vgacntrl_reg(dev);
15216
15217 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15218 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15219 i915_disable_vga(dev);
15220 }
15221 }
15222
15223 void i915_redisable_vga(struct drm_device *dev)
15224 {
15225 struct drm_i915_private *dev_priv = dev->dev_private;
15226
15227 /* This function can be called both from intel_modeset_setup_hw_state or
15228 * at a very early point in our resume sequence, where the power well
15229 * structures are not yet restored. Since this function is at a very
15230 * paranoid "someone might have enabled VGA while we were not looking"
15231 * level, just check if the power well is enabled instead of trying to
15232 * follow the "don't touch the power well if we don't need it" policy
15233 * the rest of the driver uses. */
15234 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15235 return;
15236
15237 i915_redisable_vga_power_on(dev);
15238 }
15239
15240 static bool primary_get_hw_state(struct intel_crtc *crtc)
15241 {
15242 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15243
15244 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15245 }
15246
15247 static void readout_plane_state(struct intel_crtc *crtc,
15248 struct intel_crtc_state *crtc_state)
15249 {
15250 struct intel_plane *p;
15251 struct drm_plane_state *drm_plane_state;
15252 bool active = crtc_state->base.active;
15253
15254 if (active) {
15255 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15256
15257 /* apply to previous sw state too */
15258 to_intel_crtc_state(crtc->base.state)->quirks |=
15259 PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15260 }
15261
15262 for_each_intel_plane(crtc->base.dev, p) {
15263 bool visible = active;
15264
15265 if (crtc->pipe != p->pipe)
15266 continue;
15267
15268 drm_plane_state = p->base.state;
15269 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15270 visible = primary_get_hw_state(crtc);
15271 to_intel_plane_state(drm_plane_state)->visible = visible;
15272 } else {
15273 /*
15274 * unknown state, assume it's off to force a transition
15275 * to on when calculating state changes.
15276 */
15277 to_intel_plane_state(drm_plane_state)->visible = false;
15278 }
15279
15280 if (visible) {
15281 crtc_state->base.plane_mask |=
15282 1 << drm_plane_index(&p->base);
15283 } else if (crtc_state->base.state) {
15284 /* Make this unconditional for atomic hw readout. */
15285 crtc_state->base.plane_mask &=
15286 ~(1 << drm_plane_index(&p->base));
15287 }
15288 }
15289 }
15290
15291 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15292 {
15293 struct drm_i915_private *dev_priv = dev->dev_private;
15294 enum pipe pipe;
15295 struct intel_crtc *crtc;
15296 struct intel_encoder *encoder;
15297 struct intel_connector *connector;
15298 int i;
15299
15300 for_each_intel_crtc(dev, crtc) {
15301 memset(crtc->config, 0, sizeof(*crtc->config));
15302 crtc->config->base.crtc = &crtc->base;
15303
15304 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15305
15306 crtc->active = dev_priv->display.get_pipe_config(crtc,
15307 crtc->config);
15308
15309 crtc->base.state->enable = crtc->active;
15310 crtc->base.state->active = crtc->active;
15311 crtc->base.enabled = crtc->active;
15312 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15313
15314 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15315
15316 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15317 crtc->base.base.id,
15318 crtc->active ? "enabled" : "disabled");
15319 }
15320
15321 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15322 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15323
15324 pll->on = pll->get_hw_state(dev_priv, pll,
15325 &pll->config.hw_state);
15326 pll->active = 0;
15327 pll->config.crtc_mask = 0;
15328 for_each_intel_crtc(dev, crtc) {
15329 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15330 pll->active++;
15331 pll->config.crtc_mask |= 1 << crtc->pipe;
15332 }
15333 }
15334
15335 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15336 pll->name, pll->config.crtc_mask, pll->on);
15337
15338 if (pll->config.crtc_mask)
15339 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15340 }
15341
15342 for_each_intel_encoder(dev, encoder) {
15343 pipe = 0;
15344
15345 if (encoder->get_hw_state(encoder, &pipe)) {
15346 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15347 encoder->base.crtc = &crtc->base;
15348 encoder->get_config(encoder, crtc->config);
15349 } else {
15350 encoder->base.crtc = NULL;
15351 }
15352
15353 encoder->connectors_active = false;
15354 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15355 encoder->base.base.id,
15356 encoder->base.name,
15357 encoder->base.crtc ? "enabled" : "disabled",
15358 pipe_name(pipe));
15359 }
15360
15361 for_each_intel_connector(dev, connector) {
15362 if (connector->get_hw_state(connector)) {
15363 connector->base.dpms = DRM_MODE_DPMS_ON;
15364 connector->encoder->connectors_active = true;
15365 connector->base.encoder = &connector->encoder->base;
15366 } else {
15367 connector->base.dpms = DRM_MODE_DPMS_OFF;
15368 connector->base.encoder = NULL;
15369 }
15370 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15371 connector->base.base.id,
15372 connector->base.name,
15373 connector->base.encoder ? "enabled" : "disabled");
15374 }
15375 }
15376
15377 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15378 * and i915 state tracking structures. */
15379 void intel_modeset_setup_hw_state(struct drm_device *dev,
15380 bool force_restore)
15381 {
15382 struct drm_i915_private *dev_priv = dev->dev_private;
15383 enum pipe pipe;
15384 struct intel_crtc *crtc;
15385 struct intel_encoder *encoder;
15386 int i;
15387
15388 intel_modeset_readout_hw_state(dev);
15389
15390 /*
15391 * Now that we have the config, copy it to each CRTC struct
15392 * Note that this could go away if we move to using crtc_config
15393 * checking everywhere.
15394 */
15395 for_each_intel_crtc(dev, crtc) {
15396 if (crtc->active && i915.fastboot) {
15397 intel_mode_from_pipe_config(&crtc->base.mode,
15398 crtc->config);
15399 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15400 crtc->base.base.id);
15401 drm_mode_debug_printmodeline(&crtc->base.mode);
15402 }
15403 }
15404
15405 /* HW state is read out, now we need to sanitize this mess. */
15406 for_each_intel_encoder(dev, encoder) {
15407 intel_sanitize_encoder(encoder);
15408 }
15409
15410 for_each_pipe(dev_priv, pipe) {
15411 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15412 intel_sanitize_crtc(crtc);
15413 intel_dump_pipe_config(crtc, crtc->config,
15414 "[setup_hw_state]");
15415 }
15416
15417 intel_modeset_update_connector_atomic_state(dev);
15418
15419 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15420 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15421
15422 if (!pll->on || pll->active)
15423 continue;
15424
15425 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15426
15427 pll->disable(dev_priv, pll);
15428 pll->on = false;
15429 }
15430
15431 if (IS_GEN9(dev))
15432 skl_wm_get_hw_state(dev);
15433 else if (HAS_PCH_SPLIT(dev))
15434 ilk_wm_get_hw_state(dev);
15435
15436 if (force_restore) {
15437 i915_redisable_vga(dev);
15438
15439 /*
15440 * We need to use raw interfaces for restoring state to avoid
15441 * checking (bogus) intermediate states.
15442 */
15443 for_each_pipe(dev_priv, pipe) {
15444 struct drm_crtc *crtc =
15445 dev_priv->pipe_to_crtc_mapping[pipe];
15446
15447 intel_crtc_restore_mode(crtc);
15448 }
15449 } else {
15450 intel_modeset_update_staged_output_state(dev);
15451 }
15452
15453 intel_modeset_check_state(dev);
15454 }
15455
15456 void intel_modeset_gem_init(struct drm_device *dev)
15457 {
15458 struct drm_i915_private *dev_priv = dev->dev_private;
15459 struct drm_crtc *c;
15460 struct drm_i915_gem_object *obj;
15461 int ret;
15462
15463 mutex_lock(&dev->struct_mutex);
15464 intel_init_gt_powersave(dev);
15465 mutex_unlock(&dev->struct_mutex);
15466
15467 /*
15468 * There may be no VBT; and if the BIOS enabled SSC we can
15469 * just keep using it to avoid unnecessary flicker. Whereas if the
15470 * BIOS isn't using it, don't assume it will work even if the VBT
15471 * indicates as much.
15472 */
15473 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15474 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15475 DREF_SSC1_ENABLE);
15476
15477 intel_modeset_init_hw(dev);
15478
15479 intel_setup_overlay(dev);
15480
15481 /*
15482 * Make sure any fbs we allocated at startup are properly
15483 * pinned & fenced. When we do the allocation it's too early
15484 * for this.
15485 */
15486 for_each_crtc(dev, c) {
15487 obj = intel_fb_obj(c->primary->fb);
15488 if (obj == NULL)
15489 continue;
15490
15491 mutex_lock(&dev->struct_mutex);
15492 ret = intel_pin_and_fence_fb_obj(c->primary,
15493 c->primary->fb,
15494 c->primary->state,
15495 NULL, NULL);
15496 mutex_unlock(&dev->struct_mutex);
15497 if (ret) {
15498 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15499 to_intel_crtc(c)->pipe);
15500 drm_framebuffer_unreference(c->primary->fb);
15501 c->primary->fb = NULL;
15502 c->primary->crtc = c->primary->state->crtc = NULL;
15503 update_state_fb(c->primary);
15504 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15505 }
15506 }
15507
15508 intel_backlight_register(dev);
15509 }
15510
15511 void intel_connector_unregister(struct intel_connector *intel_connector)
15512 {
15513 struct drm_connector *connector = &intel_connector->base;
15514
15515 intel_panel_destroy_backlight(connector);
15516 drm_connector_unregister(connector);
15517 }
15518
15519 void intel_modeset_cleanup(struct drm_device *dev)
15520 {
15521 struct drm_i915_private *dev_priv = dev->dev_private;
15522 struct drm_connector *connector;
15523
15524 intel_disable_gt_powersave(dev);
15525
15526 intel_backlight_unregister(dev);
15527
15528 /*
15529 * Interrupts and polling as the first thing to avoid creating havoc.
15530 * Too much stuff here (turning of connectors, ...) would
15531 * experience fancy races otherwise.
15532 */
15533 intel_irq_uninstall(dev_priv);
15534
15535 /*
15536 * Due to the hpd irq storm handling the hotplug work can re-arm the
15537 * poll handlers. Hence disable polling after hpd handling is shut down.
15538 */
15539 drm_kms_helper_poll_fini(dev);
15540
15541 mutex_lock(&dev->struct_mutex);
15542
15543 intel_unregister_dsm_handler();
15544
15545 intel_fbc_disable(dev);
15546
15547 mutex_unlock(&dev->struct_mutex);
15548
15549 /* flush any delayed tasks or pending work */
15550 flush_scheduled_work();
15551
15552 /* destroy the backlight and sysfs files before encoders/connectors */
15553 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15554 struct intel_connector *intel_connector;
15555
15556 intel_connector = to_intel_connector(connector);
15557 intel_connector->unregister(intel_connector);
15558 }
15559
15560 drm_mode_config_cleanup(dev);
15561
15562 intel_cleanup_overlay(dev);
15563
15564 mutex_lock(&dev->struct_mutex);
15565 intel_cleanup_gt_powersave(dev);
15566 mutex_unlock(&dev->struct_mutex);
15567 }
15568
15569 /*
15570 * Return which encoder is currently attached for connector.
15571 */
15572 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15573 {
15574 return &intel_attached_encoder(connector)->base;
15575 }
15576
15577 void intel_connector_attach_encoder(struct intel_connector *connector,
15578 struct intel_encoder *encoder)
15579 {
15580 connector->encoder = encoder;
15581 drm_mode_connector_attach_encoder(&connector->base,
15582 &encoder->base);
15583 }
15584
15585 /*
15586 * set vga decode state - true == enable VGA decode
15587 */
15588 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15589 {
15590 struct drm_i915_private *dev_priv = dev->dev_private;
15591 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15592 u16 gmch_ctrl;
15593
15594 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15595 DRM_ERROR("failed to read control word\n");
15596 return -EIO;
15597 }
15598
15599 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15600 return 0;
15601
15602 if (state)
15603 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15604 else
15605 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15606
15607 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15608 DRM_ERROR("failed to write control word\n");
15609 return -EIO;
15610 }
15611
15612 return 0;
15613 }
15614
15615 struct intel_display_error_state {
15616
15617 u32 power_well_driver;
15618
15619 int num_transcoders;
15620
15621 struct intel_cursor_error_state {
15622 u32 control;
15623 u32 position;
15624 u32 base;
15625 u32 size;
15626 } cursor[I915_MAX_PIPES];
15627
15628 struct intel_pipe_error_state {
15629 bool power_domain_on;
15630 u32 source;
15631 u32 stat;
15632 } pipe[I915_MAX_PIPES];
15633
15634 struct intel_plane_error_state {
15635 u32 control;
15636 u32 stride;
15637 u32 size;
15638 u32 pos;
15639 u32 addr;
15640 u32 surface;
15641 u32 tile_offset;
15642 } plane[I915_MAX_PIPES];
15643
15644 struct intel_transcoder_error_state {
15645 bool power_domain_on;
15646 enum transcoder cpu_transcoder;
15647
15648 u32 conf;
15649
15650 u32 htotal;
15651 u32 hblank;
15652 u32 hsync;
15653 u32 vtotal;
15654 u32 vblank;
15655 u32 vsync;
15656 } transcoder[4];
15657 };
15658
15659 struct intel_display_error_state *
15660 intel_display_capture_error_state(struct drm_device *dev)
15661 {
15662 struct drm_i915_private *dev_priv = dev->dev_private;
15663 struct intel_display_error_state *error;
15664 int transcoders[] = {
15665 TRANSCODER_A,
15666 TRANSCODER_B,
15667 TRANSCODER_C,
15668 TRANSCODER_EDP,
15669 };
15670 int i;
15671
15672 if (INTEL_INFO(dev)->num_pipes == 0)
15673 return NULL;
15674
15675 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15676 if (error == NULL)
15677 return NULL;
15678
15679 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15680 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15681
15682 for_each_pipe(dev_priv, i) {
15683 error->pipe[i].power_domain_on =
15684 __intel_display_power_is_enabled(dev_priv,
15685 POWER_DOMAIN_PIPE(i));
15686 if (!error->pipe[i].power_domain_on)
15687 continue;
15688
15689 error->cursor[i].control = I915_READ(CURCNTR(i));
15690 error->cursor[i].position = I915_READ(CURPOS(i));
15691 error->cursor[i].base = I915_READ(CURBASE(i));
15692
15693 error->plane[i].control = I915_READ(DSPCNTR(i));
15694 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15695 if (INTEL_INFO(dev)->gen <= 3) {
15696 error->plane[i].size = I915_READ(DSPSIZE(i));
15697 error->plane[i].pos = I915_READ(DSPPOS(i));
15698 }
15699 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15700 error->plane[i].addr = I915_READ(DSPADDR(i));
15701 if (INTEL_INFO(dev)->gen >= 4) {
15702 error->plane[i].surface = I915_READ(DSPSURF(i));
15703 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15704 }
15705
15706 error->pipe[i].source = I915_READ(PIPESRC(i));
15707
15708 if (HAS_GMCH_DISPLAY(dev))
15709 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15710 }
15711
15712 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15713 if (HAS_DDI(dev_priv->dev))
15714 error->num_transcoders++; /* Account for eDP. */
15715
15716 for (i = 0; i < error->num_transcoders; i++) {
15717 enum transcoder cpu_transcoder = transcoders[i];
15718
15719 error->transcoder[i].power_domain_on =
15720 __intel_display_power_is_enabled(dev_priv,
15721 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15722 if (!error->transcoder[i].power_domain_on)
15723 continue;
15724
15725 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15726
15727 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15728 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15729 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15730 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15731 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15732 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15733 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15734 }
15735
15736 return error;
15737 }
15738
15739 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15740
15741 void
15742 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15743 struct drm_device *dev,
15744 struct intel_display_error_state *error)
15745 {
15746 struct drm_i915_private *dev_priv = dev->dev_private;
15747 int i;
15748
15749 if (!error)
15750 return;
15751
15752 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15753 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15754 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15755 error->power_well_driver);
15756 for_each_pipe(dev_priv, i) {
15757 err_printf(m, "Pipe [%d]:\n", i);
15758 err_printf(m, " Power: %s\n",
15759 error->pipe[i].power_domain_on ? "on" : "off");
15760 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15761 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15762
15763 err_printf(m, "Plane [%d]:\n", i);
15764 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15765 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15766 if (INTEL_INFO(dev)->gen <= 3) {
15767 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15768 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15769 }
15770 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15771 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15772 if (INTEL_INFO(dev)->gen >= 4) {
15773 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15774 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15775 }
15776
15777 err_printf(m, "Cursor [%d]:\n", i);
15778 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15779 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15780 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15781 }
15782
15783 for (i = 0; i < error->num_transcoders; i++) {
15784 err_printf(m, "CPU transcoder: %c\n",
15785 transcoder_name(error->transcoder[i].cpu_transcoder));
15786 err_printf(m, " Power: %s\n",
15787 error->transcoder[i].power_domain_on ? "on" : "off");
15788 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15789 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15790 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15791 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15792 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15793 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15794 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15795 }
15796 }
15797
15798 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15799 {
15800 struct intel_crtc *crtc;
15801
15802 for_each_intel_crtc(dev, crtc) {
15803 struct intel_unpin_work *work;
15804
15805 spin_lock_irq(&dev->event_lock);
15806
15807 work = crtc->unpin_work;
15808
15809 if (work && work->event &&
15810 work->event->base.file_priv == file) {
15811 kfree(work->event);
15812 work->event = NULL;
15813 }
15814
15815 spin_unlock_irq(&dev->event_lock);
15816 }
15817 }
Linux kernel - Deliverables
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