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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 int min, max;
50 } intel_range_t;
51
52 typedef struct {
53 int dot_limit;
54 int p2_slow, p2_fast;
55 } intel_p2_t;
56
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t;
59 struct intel_limit {
60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
62 };
63
64 /* FDI */
65 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
67 int
68 intel_pch_rawclk(struct drm_device *dev)
69 {
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75 }
76
77 static inline u32 /* units of 100MHz */
78 intel_fdi_link_freq(struct drm_device *dev)
79 {
80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
85 }
86
87 static const intel_limit_t intel_limits_i8xx_dvo = {
88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
98 };
99
100 static const intel_limit_t intel_limits_i8xx_lvds = {
101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
111 };
112
113 static const intel_limit_t intel_limits_i9xx_sdvo = {
114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
124 };
125
126 static const intel_limit_t intel_limits_i9xx_lvds = {
127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
137 };
138
139
140 static const intel_limit_t intel_limits_g4x_sdvo = {
141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
152 },
153 };
154
155 static const intel_limit_t intel_limits_g4x_hdmi = {
156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
166 };
167
168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
179 },
180 };
181
182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
193 },
194 };
195
196 static const intel_limit_t intel_limits_pineview_sdvo = {
197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
199 /* Pineview's Ncounter is a ring counter */
200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
202 /* Pineview only has one combined m divider, which we treat as m2. */
203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
209 };
210
211 static const intel_limit_t intel_limits_pineview_lvds = {
212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
222 };
223
224 /* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
229 static const intel_limit_t intel_limits_ironlake_dac = {
230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
253 };
254
255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
266 };
267
268 /* LVDS 100mhz refclk limits. */
269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
277 .p1 = { .min = 2, .max = 8 },
278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
280 };
281
282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
290 .p1 = { .min = 2, .max = 6 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
293 };
294
295 static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
303 .p1 = { .min = 1, .max = 3 },
304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
306 };
307
308 static const intel_limit_t intel_limits_vlv_hdmi = {
309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
319 };
320
321 static const intel_limit_t intel_limits_vlv_dp = {
322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
324 .n = { .min = 1, .max = 7 },
325 .m = { .min = 22, .max = 450 },
326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
329 .p1 = { .min = 1, .max = 3 },
330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
332 };
333
334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
336 {
337 struct drm_device *dev = crtc->dev;
338 const intel_limit_t *limit;
339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
341 if (intel_is_dual_link_lvds(dev)) {
342 if (refclk == 100000)
343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
347 if (refclk == 100000)
348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
352 } else
353 limit = &intel_limits_ironlake_dac;
354
355 return limit;
356 }
357
358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359 {
360 struct drm_device *dev = crtc->dev;
361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
364 if (intel_is_dual_link_lvds(dev))
365 limit = &intel_limits_g4x_dual_channel_lvds;
366 else
367 limit = &intel_limits_g4x_single_channel_lvds;
368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
370 limit = &intel_limits_g4x_hdmi;
371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
372 limit = &intel_limits_g4x_sdvo;
373 } else /* The option is for other outputs */
374 limit = &intel_limits_i9xx_sdvo;
375
376 return limit;
377 }
378
379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
380 {
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
384 if (HAS_PCH_SPLIT(dev))
385 limit = intel_ironlake_limit(crtc, refclk);
386 else if (IS_G4X(dev)) {
387 limit = intel_g4x_limit(crtc);
388 } else if (IS_PINEVIEW(dev)) {
389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
390 limit = &intel_limits_pineview_lvds;
391 else
392 limit = &intel_limits_pineview_sdvo;
393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_i8xx_lvds;
408 else
409 limit = &intel_limits_i8xx_dvo;
410 }
411 return limit;
412 }
413
414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
415 static void pineview_clock(int refclk, intel_clock_t *clock)
416 {
417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421 }
422
423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424 {
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426 }
427
428 static void i9xx_clock(int refclk, intel_clock_t *clock)
429 {
430 clock->m = i9xx_dpll_compute_m(clock);
431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434 }
435
436 /**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
440 {
441 struct drm_device *dev = crtc->dev;
442 struct intel_encoder *encoder;
443
444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
446 return true;
447
448 return false;
449 }
450
451 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
452 /**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
457 static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
460 {
461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
462 INTELPllInvalid("p1 out of range\n");
463 if (clock->p < limit->p.min || limit->p.max < clock->p)
464 INTELPllInvalid("p out of range\n");
465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
466 INTELPllInvalid("m2 out of range\n");
467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
468 INTELPllInvalid("m1 out of range\n");
469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
470 INTELPllInvalid("m1 <= m2\n");
471 if (clock->m < limit->m.min || limit->m.max < clock->m)
472 INTELPllInvalid("m out of range\n");
473 if (clock->n < limit->n.min || limit->n.max < clock->n)
474 INTELPllInvalid("n out of range\n");
475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
476 INTELPllInvalid("vco out of range\n");
477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
481 INTELPllInvalid("dot out of range\n");
482
483 return true;
484 }
485
486 static bool
487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
490 {
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
518 if (clock.m2 >= clock.m1)
519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
525
526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545 }
546
547 static bool
548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
551 {
552 struct drm_device *dev = crtc->dev;
553 intel_clock_t clock;
554 int err = target;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557 /*
558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
561 */
562 if (intel_is_dual_link_lvds(dev))
563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
573 memset(best_clock, 0, sizeof(*best_clock));
574
575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
583 int this_err;
584
585 pineview_clock(refclk, &clock);
586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
588 continue;
589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604 }
605
606 static bool
607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
610 {
611 struct drm_device *dev = crtc->dev;
612 intel_clock_t clock;
613 int max_n;
614 bool found;
615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
620 if (intel_is_dual_link_lvds(dev))
621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
633 /* based on hardware requirement, prefer smaller n to precision */
634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
635 /* based on hardware requirement, prefere larger m1,m2 */
636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
644 i9xx_clock(refclk, &clock);
645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
660 return found;
661 }
662
663 static bool
664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
667 {
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
674 flag = 0;
675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730 }
731
732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734 {
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
738 return intel_crtc->config.cpu_transcoder;
739 }
740
741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742 {
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750 }
751
752 /**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
761 {
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 int pipestat_reg = PIPESTAT(pipe);
764
765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
786 /* Wait for vblank interrupt bit to set */
787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
790 DRM_DEBUG_KMS("vblank wait timed out\n");
791 }
792
793 /*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
808 *
809 */
810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
811 {
812 struct drm_i915_private *dev_priv = dev->dev_private;
813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
815
816 if (INTEL_INFO(dev)->gen >= 4) {
817 int reg = PIPECONF(cpu_transcoder);
818
819 /* Wait for the Pipe State to go off */
820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
822 WARN(1, "pipe_off wait timed out\n");
823 } else {
824 u32 last_line, line_mask;
825 int reg = PIPEDSL(pipe);
826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
833 /* Wait for the display line to settle */
834 do {
835 last_line = I915_READ(reg) & line_mask;
836 mdelay(5);
837 } while (((I915_READ(reg) & line_mask) != last_line) &&
838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
840 WARN(1, "pipe_off wait timed out\n");
841 }
842 }
843
844 /*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853 {
854 u32 bit;
855
856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
884 }
885
886 return I915_READ(SDEISR) & bit;
887 }
888
889 static const char *state_string(bool enabled)
890 {
891 return enabled ? "on" : "off";
892 }
893
894 /* Only for pre-ILK configs */
895 static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897 {
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908 }
909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
912 /* For ILK+ */
913 static void assert_pch_pll(struct drm_i915_private *dev_priv,
914 struct intel_pch_pll *pll,
915 struct intel_crtc *crtc,
916 bool state)
917 {
918 u32 val;
919 bool cur_state;
920
921 if (HAS_PCH_LPT(dev_priv->dev)) {
922 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
923 return;
924 }
925
926 if (WARN (!pll,
927 "asserting PCH PLL %s with no PLL\n", state_string(state)))
928 return;
929
930 val = I915_READ(pll->pll_reg);
931 cur_state = !!(val & DPLL_VCO_ENABLE);
932 WARN(cur_state != state,
933 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
934 pll->pll_reg, state_string(state), state_string(cur_state), val);
935
936 /* Make sure the selected PLL is correctly attached to the transcoder */
937 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
938 u32 pch_dpll;
939
940 pch_dpll = I915_READ(PCH_DPLL_SEL);
941 cur_state = pll->pll_reg == _PCH_DPLL_B;
942 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
943 "PLL[%d] not attached to this transcoder %c: %08x\n",
944 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
945 cur_state = !!(val >> (4*crtc->pipe + 3));
946 WARN(cur_state != state,
947 "PLL[%d] not %s on this transcoder %c: %08x\n",
948 pll->pll_reg == _PCH_DPLL_B,
949 state_string(state),
950 pipe_name(crtc->pipe),
951 val);
952 }
953 }
954 }
955 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
956 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
957
958 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
959 enum pipe pipe, bool state)
960 {
961 int reg;
962 u32 val;
963 bool cur_state;
964 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
965 pipe);
966
967 if (HAS_DDI(dev_priv->dev)) {
968 /* DDI does not have a specific FDI_TX register */
969 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
970 val = I915_READ(reg);
971 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
972 } else {
973 reg = FDI_TX_CTL(pipe);
974 val = I915_READ(reg);
975 cur_state = !!(val & FDI_TX_ENABLE);
976 }
977 WARN(cur_state != state,
978 "FDI TX state assertion failure (expected %s, current %s)\n",
979 state_string(state), state_string(cur_state));
980 }
981 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
982 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
983
984 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
985 enum pipe pipe, bool state)
986 {
987 int reg;
988 u32 val;
989 bool cur_state;
990
991 reg = FDI_RX_CTL(pipe);
992 val = I915_READ(reg);
993 cur_state = !!(val & FDI_RX_ENABLE);
994 WARN(cur_state != state,
995 "FDI RX state assertion failure (expected %s, current %s)\n",
996 state_string(state), state_string(cur_state));
997 }
998 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
999 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003 {
1004 int reg;
1005 u32 val;
1006
1007 /* ILK FDI PLL is always enabled */
1008 if (dev_priv->info->gen == 5)
1009 return;
1010
1011 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1012 if (HAS_DDI(dev_priv->dev))
1013 return;
1014
1015 reg = FDI_TX_CTL(pipe);
1016 val = I915_READ(reg);
1017 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018 }
1019
1020 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022 {
1023 int reg;
1024 u32 val;
1025
1026 reg = FDI_RX_CTL(pipe);
1027 val = I915_READ(reg);
1028 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029 }
1030
1031 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032 enum pipe pipe)
1033 {
1034 int pp_reg, lvds_reg;
1035 u32 val;
1036 enum pipe panel_pipe = PIPE_A;
1037 bool locked = true;
1038
1039 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040 pp_reg = PCH_PP_CONTROL;
1041 lvds_reg = PCH_LVDS;
1042 } else {
1043 pp_reg = PP_CONTROL;
1044 lvds_reg = LVDS;
1045 }
1046
1047 val = I915_READ(pp_reg);
1048 if (!(val & PANEL_POWER_ON) ||
1049 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050 locked = false;
1051
1052 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053 panel_pipe = PIPE_B;
1054
1055 WARN(panel_pipe == pipe && locked,
1056 "panel assertion failure, pipe %c regs locked\n",
1057 pipe_name(pipe));
1058 }
1059
1060 void assert_pipe(struct drm_i915_private *dev_priv,
1061 enum pipe pipe, bool state)
1062 {
1063 int reg;
1064 u32 val;
1065 bool cur_state;
1066 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067 pipe);
1068
1069 /* if we need the pipe A quirk it must be always on */
1070 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071 state = true;
1072
1073 if (!intel_display_power_enabled(dev_priv->dev,
1074 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1075 cur_state = false;
1076 } else {
1077 reg = PIPECONF(cpu_transcoder);
1078 val = I915_READ(reg);
1079 cur_state = !!(val & PIPECONF_ENABLE);
1080 }
1081
1082 WARN(cur_state != state,
1083 "pipe %c assertion failure (expected %s, current %s)\n",
1084 pipe_name(pipe), state_string(state), state_string(cur_state));
1085 }
1086
1087 static void assert_plane(struct drm_i915_private *dev_priv,
1088 enum plane plane, bool state)
1089 {
1090 int reg;
1091 u32 val;
1092 bool cur_state;
1093
1094 reg = DSPCNTR(plane);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097 WARN(cur_state != state,
1098 "plane %c assertion failure (expected %s, current %s)\n",
1099 plane_name(plane), state_string(state), state_string(cur_state));
1100 }
1101
1102 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
1105 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106 enum pipe pipe)
1107 {
1108 int reg, i;
1109 u32 val;
1110 int cur_pipe;
1111
1112 /* Planes are fixed to pipes on ILK+ */
1113 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1114 reg = DSPCNTR(pipe);
1115 val = I915_READ(reg);
1116 WARN((val & DISPLAY_PLANE_ENABLE),
1117 "plane %c assertion failure, should be disabled but not\n",
1118 plane_name(pipe));
1119 return;
1120 }
1121
1122 /* Need to check both planes against the pipe */
1123 for (i = 0; i < 2; i++) {
1124 reg = DSPCNTR(i);
1125 val = I915_READ(reg);
1126 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1127 DISPPLANE_SEL_PIPE_SHIFT;
1128 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1129 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1130 plane_name(i), pipe_name(pipe));
1131 }
1132 }
1133
1134 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1135 enum pipe pipe)
1136 {
1137 int reg, i;
1138 u32 val;
1139
1140 if (!IS_VALLEYVIEW(dev_priv->dev))
1141 return;
1142
1143 /* Need to check both planes against the pipe */
1144 for (i = 0; i < dev_priv->num_plane; i++) {
1145 reg = SPCNTR(pipe, i);
1146 val = I915_READ(reg);
1147 WARN((val & SP_ENABLE),
1148 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1149 sprite_name(pipe, i), pipe_name(pipe));
1150 }
1151 }
1152
1153 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1154 {
1155 u32 val;
1156 bool enabled;
1157
1158 if (HAS_PCH_LPT(dev_priv->dev)) {
1159 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1160 return;
1161 }
1162
1163 val = I915_READ(PCH_DREF_CONTROL);
1164 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1165 DREF_SUPERSPREAD_SOURCE_MASK));
1166 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1167 }
1168
1169 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171 {
1172 int reg;
1173 u32 val;
1174 bool enabled;
1175
1176 reg = PCH_TRANSCONF(pipe);
1177 val = I915_READ(reg);
1178 enabled = !!(val & TRANS_ENABLE);
1179 WARN(enabled,
1180 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1181 pipe_name(pipe));
1182 }
1183
1184 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, u32 port_sel, u32 val)
1186 {
1187 if ((val & DP_PORT_EN) == 0)
1188 return false;
1189
1190 if (HAS_PCH_CPT(dev_priv->dev)) {
1191 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1192 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1193 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1194 return false;
1195 } else {
1196 if ((val & DP_PIPE_MASK) != (pipe << 30))
1197 return false;
1198 }
1199 return true;
1200 }
1201
1202 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1203 enum pipe pipe, u32 val)
1204 {
1205 if ((val & SDVO_ENABLE) == 0)
1206 return false;
1207
1208 if (HAS_PCH_CPT(dev_priv->dev)) {
1209 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1210 return false;
1211 } else {
1212 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1213 return false;
1214 }
1215 return true;
1216 }
1217
1218 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, u32 val)
1220 {
1221 if ((val & LVDS_PORT_EN) == 0)
1222 return false;
1223
1224 if (HAS_PCH_CPT(dev_priv->dev)) {
1225 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1226 return false;
1227 } else {
1228 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1229 return false;
1230 }
1231 return true;
1232 }
1233
1234 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1235 enum pipe pipe, u32 val)
1236 {
1237 if ((val & ADPA_DAC_ENABLE) == 0)
1238 return false;
1239 if (HAS_PCH_CPT(dev_priv->dev)) {
1240 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1241 return false;
1242 } else {
1243 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1244 return false;
1245 }
1246 return true;
1247 }
1248
1249 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1250 enum pipe pipe, int reg, u32 port_sel)
1251 {
1252 u32 val = I915_READ(reg);
1253 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1254 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1255 reg, pipe_name(pipe));
1256
1257 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1258 && (val & DP_PIPEB_SELECT),
1259 "IBX PCH dp port still using transcoder B\n");
1260 }
1261
1262 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe, int reg)
1264 {
1265 u32 val = I915_READ(reg);
1266 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1267 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1268 reg, pipe_name(pipe));
1269
1270 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1271 && (val & SDVO_PIPE_B_SELECT),
1272 "IBX PCH hdmi port still using transcoder B\n");
1273 }
1274
1275 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1276 enum pipe pipe)
1277 {
1278 int reg;
1279 u32 val;
1280
1281 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1282 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1284
1285 reg = PCH_ADPA;
1286 val = I915_READ(reg);
1287 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1288 "PCH VGA enabled on transcoder %c, should be disabled\n",
1289 pipe_name(pipe));
1290
1291 reg = PCH_LVDS;
1292 val = I915_READ(reg);
1293 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1294 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1295 pipe_name(pipe));
1296
1297 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1298 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1300 }
1301
1302 /**
1303 * intel_enable_pll - enable a PLL
1304 * @dev_priv: i915 private structure
1305 * @pipe: pipe PLL to enable
1306 *
1307 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1308 * make sure the PLL reg is writable first though, since the panel write
1309 * protect mechanism may be enabled.
1310 *
1311 * Note! This is for pre-ILK only.
1312 *
1313 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1314 */
1315 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1316 {
1317 int reg;
1318 u32 val;
1319
1320 assert_pipe_disabled(dev_priv, pipe);
1321
1322 /* No really, not for ILK+ */
1323 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1324
1325 /* PLL is protected by panel, make sure we can write it */
1326 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1327 assert_panel_unlocked(dev_priv, pipe);
1328
1329 reg = DPLL(pipe);
1330 val = I915_READ(reg);
1331 val |= DPLL_VCO_ENABLE;
1332
1333 /* We do this three times for luck */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337 I915_WRITE(reg, val);
1338 POSTING_READ(reg);
1339 udelay(150); /* wait for warmup */
1340 I915_WRITE(reg, val);
1341 POSTING_READ(reg);
1342 udelay(150); /* wait for warmup */
1343 }
1344
1345 /**
1346 * intel_disable_pll - disable a PLL
1347 * @dev_priv: i915 private structure
1348 * @pipe: pipe PLL to disable
1349 *
1350 * Disable the PLL for @pipe, making sure the pipe is off first.
1351 *
1352 * Note! This is for pre-ILK only.
1353 */
1354 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1355 {
1356 int reg;
1357 u32 val;
1358
1359 /* Don't disable pipe A or pipe A PLLs if needed */
1360 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1361 return;
1362
1363 /* Make sure the pipe isn't still relying on us */
1364 assert_pipe_disabled(dev_priv, pipe);
1365
1366 reg = DPLL(pipe);
1367 val = I915_READ(reg);
1368 val &= ~DPLL_VCO_ENABLE;
1369 I915_WRITE(reg, val);
1370 POSTING_READ(reg);
1371 }
1372
1373 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1374 {
1375 u32 port_mask;
1376
1377 if (!port)
1378 port_mask = DPLL_PORTB_READY_MASK;
1379 else
1380 port_mask = DPLL_PORTC_READY_MASK;
1381
1382 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1383 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1384 'B' + port, I915_READ(DPLL(0)));
1385 }
1386
1387 /**
1388 * ironlake_enable_pch_pll - enable PCH PLL
1389 * @dev_priv: i915 private structure
1390 * @pipe: pipe PLL to enable
1391 *
1392 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1393 * drives the transcoder clock.
1394 */
1395 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1396 {
1397 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1398 struct intel_pch_pll *pll;
1399 int reg;
1400 u32 val;
1401
1402 /* PCH PLLs only available on ILK, SNB and IVB */
1403 BUG_ON(dev_priv->info->gen < 5);
1404 pll = intel_crtc->pch_pll;
1405 if (pll == NULL)
1406 return;
1407
1408 if (WARN_ON(pll->refcount == 0))
1409 return;
1410
1411 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1412 pll->pll_reg, pll->active, pll->on,
1413 intel_crtc->base.base.id);
1414
1415 /* PCH refclock must be enabled first */
1416 assert_pch_refclk_enabled(dev_priv);
1417
1418 if (pll->active++ && pll->on) {
1419 assert_pch_pll_enabled(dev_priv, pll, NULL);
1420 return;
1421 }
1422
1423 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1424
1425 reg = pll->pll_reg;
1426 val = I915_READ(reg);
1427 val |= DPLL_VCO_ENABLE;
1428 I915_WRITE(reg, val);
1429 POSTING_READ(reg);
1430 udelay(200);
1431
1432 pll->on = true;
1433 }
1434
1435 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1436 {
1437 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1438 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1439 int reg;
1440 u32 val;
1441
1442 /* PCH only available on ILK+ */
1443 BUG_ON(dev_priv->info->gen < 5);
1444 if (pll == NULL)
1445 return;
1446
1447 if (WARN_ON(pll->refcount == 0))
1448 return;
1449
1450 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1451 pll->pll_reg, pll->active, pll->on,
1452 intel_crtc->base.base.id);
1453
1454 if (WARN_ON(pll->active == 0)) {
1455 assert_pch_pll_disabled(dev_priv, pll, NULL);
1456 return;
1457 }
1458
1459 if (--pll->active) {
1460 assert_pch_pll_enabled(dev_priv, pll, NULL);
1461 return;
1462 }
1463
1464 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1465
1466 /* Make sure transcoder isn't still depending on us */
1467 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1468
1469 reg = pll->pll_reg;
1470 val = I915_READ(reg);
1471 val &= ~DPLL_VCO_ENABLE;
1472 I915_WRITE(reg, val);
1473 POSTING_READ(reg);
1474 udelay(200);
1475
1476 pll->on = false;
1477 }
1478
1479 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1480 enum pipe pipe)
1481 {
1482 struct drm_device *dev = dev_priv->dev;
1483 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1484 uint32_t reg, val, pipeconf_val;
1485
1486 /* PCH only available on ILK+ */
1487 BUG_ON(dev_priv->info->gen < 5);
1488
1489 /* Make sure PCH DPLL is enabled */
1490 assert_pch_pll_enabled(dev_priv,
1491 to_intel_crtc(crtc)->pch_pll,
1492 to_intel_crtc(crtc));
1493
1494 /* FDI must be feeding us bits for PCH ports */
1495 assert_fdi_tx_enabled(dev_priv, pipe);
1496 assert_fdi_rx_enabled(dev_priv, pipe);
1497
1498 if (HAS_PCH_CPT(dev)) {
1499 /* Workaround: Set the timing override bit before enabling the
1500 * pch transcoder. */
1501 reg = TRANS_CHICKEN2(pipe);
1502 val = I915_READ(reg);
1503 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1504 I915_WRITE(reg, val);
1505 }
1506
1507 reg = PCH_TRANSCONF(pipe);
1508 val = I915_READ(reg);
1509 pipeconf_val = I915_READ(PIPECONF(pipe));
1510
1511 if (HAS_PCH_IBX(dev_priv->dev)) {
1512 /*
1513 * make the BPC in transcoder be consistent with
1514 * that in pipeconf reg.
1515 */
1516 val &= ~PIPECONF_BPC_MASK;
1517 val |= pipeconf_val & PIPECONF_BPC_MASK;
1518 }
1519
1520 val &= ~TRANS_INTERLACE_MASK;
1521 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1522 if (HAS_PCH_IBX(dev_priv->dev) &&
1523 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1524 val |= TRANS_LEGACY_INTERLACED_ILK;
1525 else
1526 val |= TRANS_INTERLACED;
1527 else
1528 val |= TRANS_PROGRESSIVE;
1529
1530 I915_WRITE(reg, val | TRANS_ENABLE);
1531 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1532 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1533 }
1534
1535 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1536 enum transcoder cpu_transcoder)
1537 {
1538 u32 val, pipeconf_val;
1539
1540 /* PCH only available on ILK+ */
1541 BUG_ON(dev_priv->info->gen < 5);
1542
1543 /* FDI must be feeding us bits for PCH ports */
1544 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1545 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1546
1547 /* Workaround: set timing override bit. */
1548 val = I915_READ(_TRANSA_CHICKEN2);
1549 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1550 I915_WRITE(_TRANSA_CHICKEN2, val);
1551
1552 val = TRANS_ENABLE;
1553 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1554
1555 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1556 PIPECONF_INTERLACED_ILK)
1557 val |= TRANS_INTERLACED;
1558 else
1559 val |= TRANS_PROGRESSIVE;
1560
1561 I915_WRITE(LPT_TRANSCONF, val);
1562 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1563 DRM_ERROR("Failed to enable PCH transcoder\n");
1564 }
1565
1566 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
1568 {
1569 struct drm_device *dev = dev_priv->dev;
1570 uint32_t reg, val;
1571
1572 /* FDI relies on the transcoder */
1573 assert_fdi_tx_disabled(dev_priv, pipe);
1574 assert_fdi_rx_disabled(dev_priv, pipe);
1575
1576 /* Ports must be off as well */
1577 assert_pch_ports_disabled(dev_priv, pipe);
1578
1579 reg = PCH_TRANSCONF(pipe);
1580 val = I915_READ(reg);
1581 val &= ~TRANS_ENABLE;
1582 I915_WRITE(reg, val);
1583 /* wait for PCH transcoder off, transcoder state */
1584 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1585 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1586
1587 if (!HAS_PCH_IBX(dev)) {
1588 /* Workaround: Clear the timing override chicken bit again. */
1589 reg = TRANS_CHICKEN2(pipe);
1590 val = I915_READ(reg);
1591 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1592 I915_WRITE(reg, val);
1593 }
1594 }
1595
1596 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1597 {
1598 u32 val;
1599
1600 val = I915_READ(LPT_TRANSCONF);
1601 val &= ~TRANS_ENABLE;
1602 I915_WRITE(LPT_TRANSCONF, val);
1603 /* wait for PCH transcoder off, transcoder state */
1604 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1605 DRM_ERROR("Failed to disable PCH transcoder\n");
1606
1607 /* Workaround: clear timing override bit. */
1608 val = I915_READ(_TRANSA_CHICKEN2);
1609 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1610 I915_WRITE(_TRANSA_CHICKEN2, val);
1611 }
1612
1613 /**
1614 * intel_enable_pipe - enable a pipe, asserting requirements
1615 * @dev_priv: i915 private structure
1616 * @pipe: pipe to enable
1617 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1618 *
1619 * Enable @pipe, making sure that various hardware specific requirements
1620 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1621 *
1622 * @pipe should be %PIPE_A or %PIPE_B.
1623 *
1624 * Will wait until the pipe is actually running (i.e. first vblank) before
1625 * returning.
1626 */
1627 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1628 bool pch_port)
1629 {
1630 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1631 pipe);
1632 enum pipe pch_transcoder;
1633 int reg;
1634 u32 val;
1635
1636 assert_planes_disabled(dev_priv, pipe);
1637 assert_sprites_disabled(dev_priv, pipe);
1638
1639 if (HAS_PCH_LPT(dev_priv->dev))
1640 pch_transcoder = TRANSCODER_A;
1641 else
1642 pch_transcoder = pipe;
1643
1644 /*
1645 * A pipe without a PLL won't actually be able to drive bits from
1646 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1647 * need the check.
1648 */
1649 if (!HAS_PCH_SPLIT(dev_priv->dev))
1650 assert_pll_enabled(dev_priv, pipe);
1651 else {
1652 if (pch_port) {
1653 /* if driving the PCH, we need FDI enabled */
1654 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1655 assert_fdi_tx_pll_enabled(dev_priv,
1656 (enum pipe) cpu_transcoder);
1657 }
1658 /* FIXME: assert CPU port conditions for SNB+ */
1659 }
1660
1661 reg = PIPECONF(cpu_transcoder);
1662 val = I915_READ(reg);
1663 if (val & PIPECONF_ENABLE)
1664 return;
1665
1666 I915_WRITE(reg, val | PIPECONF_ENABLE);
1667 intel_wait_for_vblank(dev_priv->dev, pipe);
1668 }
1669
1670 /**
1671 * intel_disable_pipe - disable a pipe, asserting requirements
1672 * @dev_priv: i915 private structure
1673 * @pipe: pipe to disable
1674 *
1675 * Disable @pipe, making sure that various hardware specific requirements
1676 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1677 *
1678 * @pipe should be %PIPE_A or %PIPE_B.
1679 *
1680 * Will wait until the pipe has shut down before returning.
1681 */
1682 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1683 enum pipe pipe)
1684 {
1685 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1686 pipe);
1687 int reg;
1688 u32 val;
1689
1690 /*
1691 * Make sure planes won't keep trying to pump pixels to us,
1692 * or we might hang the display.
1693 */
1694 assert_planes_disabled(dev_priv, pipe);
1695 assert_sprites_disabled(dev_priv, pipe);
1696
1697 /* Don't disable pipe A or pipe A PLLs if needed */
1698 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1699 return;
1700
1701 reg = PIPECONF(cpu_transcoder);
1702 val = I915_READ(reg);
1703 if ((val & PIPECONF_ENABLE) == 0)
1704 return;
1705
1706 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1707 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1708 }
1709
1710 /*
1711 * Plane regs are double buffered, going from enabled->disabled needs a
1712 * trigger in order to latch. The display address reg provides this.
1713 */
1714 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1715 enum plane plane)
1716 {
1717 if (dev_priv->info->gen >= 4)
1718 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1719 else
1720 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1721 }
1722
1723 /**
1724 * intel_enable_plane - enable a display plane on a given pipe
1725 * @dev_priv: i915 private structure
1726 * @plane: plane to enable
1727 * @pipe: pipe being fed
1728 *
1729 * Enable @plane on @pipe, making sure that @pipe is running first.
1730 */
1731 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1732 enum plane plane, enum pipe pipe)
1733 {
1734 int reg;
1735 u32 val;
1736
1737 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1738 assert_pipe_enabled(dev_priv, pipe);
1739
1740 reg = DSPCNTR(plane);
1741 val = I915_READ(reg);
1742 if (val & DISPLAY_PLANE_ENABLE)
1743 return;
1744
1745 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1746 intel_flush_display_plane(dev_priv, plane);
1747 intel_wait_for_vblank(dev_priv->dev, pipe);
1748 }
1749
1750 /**
1751 * intel_disable_plane - disable a display plane
1752 * @dev_priv: i915 private structure
1753 * @plane: plane to disable
1754 * @pipe: pipe consuming the data
1755 *
1756 * Disable @plane; should be an independent operation.
1757 */
1758 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1759 enum plane plane, enum pipe pipe)
1760 {
1761 int reg;
1762 u32 val;
1763
1764 reg = DSPCNTR(plane);
1765 val = I915_READ(reg);
1766 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1767 return;
1768
1769 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1770 intel_flush_display_plane(dev_priv, plane);
1771 intel_wait_for_vblank(dev_priv->dev, pipe);
1772 }
1773
1774 static bool need_vtd_wa(struct drm_device *dev)
1775 {
1776 #ifdef CONFIG_INTEL_IOMMU
1777 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1778 return true;
1779 #endif
1780 return false;
1781 }
1782
1783 int
1784 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1785 struct drm_i915_gem_object *obj,
1786 struct intel_ring_buffer *pipelined)
1787 {
1788 struct drm_i915_private *dev_priv = dev->dev_private;
1789 u32 alignment;
1790 int ret;
1791
1792 switch (obj->tiling_mode) {
1793 case I915_TILING_NONE:
1794 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1795 alignment = 128 * 1024;
1796 else if (INTEL_INFO(dev)->gen >= 4)
1797 alignment = 4 * 1024;
1798 else
1799 alignment = 64 * 1024;
1800 break;
1801 case I915_TILING_X:
1802 /* pin() will align the object as required by fence */
1803 alignment = 0;
1804 break;
1805 case I915_TILING_Y:
1806 /* Despite that we check this in framebuffer_init userspace can
1807 * screw us over and change the tiling after the fact. Only
1808 * pinned buffers can't change their tiling. */
1809 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1810 return -EINVAL;
1811 default:
1812 BUG();
1813 }
1814
1815 /* Note that the w/a also requires 64 PTE of padding following the
1816 * bo. We currently fill all unused PTE with the shadow page and so
1817 * we should always have valid PTE following the scanout preventing
1818 * the VT-d warning.
1819 */
1820 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1821 alignment = 256 * 1024;
1822
1823 dev_priv->mm.interruptible = false;
1824 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1825 if (ret)
1826 goto err_interruptible;
1827
1828 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1829 * fence, whereas 965+ only requires a fence if using
1830 * framebuffer compression. For simplicity, we always install
1831 * a fence as the cost is not that onerous.
1832 */
1833 ret = i915_gem_object_get_fence(obj);
1834 if (ret)
1835 goto err_unpin;
1836
1837 i915_gem_object_pin_fence(obj);
1838
1839 dev_priv->mm.interruptible = true;
1840 return 0;
1841
1842 err_unpin:
1843 i915_gem_object_unpin(obj);
1844 err_interruptible:
1845 dev_priv->mm.interruptible = true;
1846 return ret;
1847 }
1848
1849 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1850 {
1851 i915_gem_object_unpin_fence(obj);
1852 i915_gem_object_unpin(obj);
1853 }
1854
1855 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1856 * is assumed to be a power-of-two. */
1857 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1858 unsigned int tiling_mode,
1859 unsigned int cpp,
1860 unsigned int pitch)
1861 {
1862 if (tiling_mode != I915_TILING_NONE) {
1863 unsigned int tile_rows, tiles;
1864
1865 tile_rows = *y / 8;
1866 *y %= 8;
1867
1868 tiles = *x / (512/cpp);
1869 *x %= 512/cpp;
1870
1871 return tile_rows * pitch * 8 + tiles * 4096;
1872 } else {
1873 unsigned int offset;
1874
1875 offset = *y * pitch + *x * cpp;
1876 *y = 0;
1877 *x = (offset & 4095) / cpp;
1878 return offset & -4096;
1879 }
1880 }
1881
1882 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1883 int x, int y)
1884 {
1885 struct drm_device *dev = crtc->dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1888 struct intel_framebuffer *intel_fb;
1889 struct drm_i915_gem_object *obj;
1890 int plane = intel_crtc->plane;
1891 unsigned long linear_offset;
1892 u32 dspcntr;
1893 u32 reg;
1894
1895 switch (plane) {
1896 case 0:
1897 case 1:
1898 break;
1899 default:
1900 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1901 return -EINVAL;
1902 }
1903
1904 intel_fb = to_intel_framebuffer(fb);
1905 obj = intel_fb->obj;
1906
1907 reg = DSPCNTR(plane);
1908 dspcntr = I915_READ(reg);
1909 /* Mask out pixel format bits in case we change it */
1910 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1911 switch (fb->pixel_format) {
1912 case DRM_FORMAT_C8:
1913 dspcntr |= DISPPLANE_8BPP;
1914 break;
1915 case DRM_FORMAT_XRGB1555:
1916 case DRM_FORMAT_ARGB1555:
1917 dspcntr |= DISPPLANE_BGRX555;
1918 break;
1919 case DRM_FORMAT_RGB565:
1920 dspcntr |= DISPPLANE_BGRX565;
1921 break;
1922 case DRM_FORMAT_XRGB8888:
1923 case DRM_FORMAT_ARGB8888:
1924 dspcntr |= DISPPLANE_BGRX888;
1925 break;
1926 case DRM_FORMAT_XBGR8888:
1927 case DRM_FORMAT_ABGR8888:
1928 dspcntr |= DISPPLANE_RGBX888;
1929 break;
1930 case DRM_FORMAT_XRGB2101010:
1931 case DRM_FORMAT_ARGB2101010:
1932 dspcntr |= DISPPLANE_BGRX101010;
1933 break;
1934 case DRM_FORMAT_XBGR2101010:
1935 case DRM_FORMAT_ABGR2101010:
1936 dspcntr |= DISPPLANE_RGBX101010;
1937 break;
1938 default:
1939 BUG();
1940 }
1941
1942 if (INTEL_INFO(dev)->gen >= 4) {
1943 if (obj->tiling_mode != I915_TILING_NONE)
1944 dspcntr |= DISPPLANE_TILED;
1945 else
1946 dspcntr &= ~DISPPLANE_TILED;
1947 }
1948
1949 I915_WRITE(reg, dspcntr);
1950
1951 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1952
1953 if (INTEL_INFO(dev)->gen >= 4) {
1954 intel_crtc->dspaddr_offset =
1955 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1956 fb->bits_per_pixel / 8,
1957 fb->pitches[0]);
1958 linear_offset -= intel_crtc->dspaddr_offset;
1959 } else {
1960 intel_crtc->dspaddr_offset = linear_offset;
1961 }
1962
1963 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1964 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1965 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1966 if (INTEL_INFO(dev)->gen >= 4) {
1967 I915_MODIFY_DISPBASE(DSPSURF(plane),
1968 obj->gtt_offset + intel_crtc->dspaddr_offset);
1969 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1970 I915_WRITE(DSPLINOFF(plane), linear_offset);
1971 } else
1972 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1973 POSTING_READ(reg);
1974
1975 return 0;
1976 }
1977
1978 static int ironlake_update_plane(struct drm_crtc *crtc,
1979 struct drm_framebuffer *fb, int x, int y)
1980 {
1981 struct drm_device *dev = crtc->dev;
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1984 struct intel_framebuffer *intel_fb;
1985 struct drm_i915_gem_object *obj;
1986 int plane = intel_crtc->plane;
1987 unsigned long linear_offset;
1988 u32 dspcntr;
1989 u32 reg;
1990
1991 switch (plane) {
1992 case 0:
1993 case 1:
1994 case 2:
1995 break;
1996 default:
1997 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1998 return -EINVAL;
1999 }
2000
2001 intel_fb = to_intel_framebuffer(fb);
2002 obj = intel_fb->obj;
2003
2004 reg = DSPCNTR(plane);
2005 dspcntr = I915_READ(reg);
2006 /* Mask out pixel format bits in case we change it */
2007 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2008 switch (fb->pixel_format) {
2009 case DRM_FORMAT_C8:
2010 dspcntr |= DISPPLANE_8BPP;
2011 break;
2012 case DRM_FORMAT_RGB565:
2013 dspcntr |= DISPPLANE_BGRX565;
2014 break;
2015 case DRM_FORMAT_XRGB8888:
2016 case DRM_FORMAT_ARGB8888:
2017 dspcntr |= DISPPLANE_BGRX888;
2018 break;
2019 case DRM_FORMAT_XBGR8888:
2020 case DRM_FORMAT_ABGR8888:
2021 dspcntr |= DISPPLANE_RGBX888;
2022 break;
2023 case DRM_FORMAT_XRGB2101010:
2024 case DRM_FORMAT_ARGB2101010:
2025 dspcntr |= DISPPLANE_BGRX101010;
2026 break;
2027 case DRM_FORMAT_XBGR2101010:
2028 case DRM_FORMAT_ABGR2101010:
2029 dspcntr |= DISPPLANE_RGBX101010;
2030 break;
2031 default:
2032 BUG();
2033 }
2034
2035 if (obj->tiling_mode != I915_TILING_NONE)
2036 dspcntr |= DISPPLANE_TILED;
2037 else
2038 dspcntr &= ~DISPPLANE_TILED;
2039
2040 /* must disable */
2041 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2042
2043 I915_WRITE(reg, dspcntr);
2044
2045 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2046 intel_crtc->dspaddr_offset =
2047 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2048 fb->bits_per_pixel / 8,
2049 fb->pitches[0]);
2050 linear_offset -= intel_crtc->dspaddr_offset;
2051
2052 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2053 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2054 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2055 I915_MODIFY_DISPBASE(DSPSURF(plane),
2056 obj->gtt_offset + intel_crtc->dspaddr_offset);
2057 if (IS_HASWELL(dev)) {
2058 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2059 } else {
2060 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2061 I915_WRITE(DSPLINOFF(plane), linear_offset);
2062 }
2063 POSTING_READ(reg);
2064
2065 return 0;
2066 }
2067
2068 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2069 static int
2070 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2071 int x, int y, enum mode_set_atomic state)
2072 {
2073 struct drm_device *dev = crtc->dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075
2076 if (dev_priv->display.disable_fbc)
2077 dev_priv->display.disable_fbc(dev);
2078 intel_increase_pllclock(crtc);
2079
2080 return dev_priv->display.update_plane(crtc, fb, x, y);
2081 }
2082
2083 void intel_display_handle_reset(struct drm_device *dev)
2084 {
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 struct drm_crtc *crtc;
2087
2088 /*
2089 * Flips in the rings have been nuked by the reset,
2090 * so complete all pending flips so that user space
2091 * will get its events and not get stuck.
2092 *
2093 * Also update the base address of all primary
2094 * planes to the the last fb to make sure we're
2095 * showing the correct fb after a reset.
2096 *
2097 * Need to make two loops over the crtcs so that we
2098 * don't try to grab a crtc mutex before the
2099 * pending_flip_queue really got woken up.
2100 */
2101
2102 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2104 enum plane plane = intel_crtc->plane;
2105
2106 intel_prepare_page_flip(dev, plane);
2107 intel_finish_page_flip_plane(dev, plane);
2108 }
2109
2110 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2112
2113 mutex_lock(&crtc->mutex);
2114 if (intel_crtc->active)
2115 dev_priv->display.update_plane(crtc, crtc->fb,
2116 crtc->x, crtc->y);
2117 mutex_unlock(&crtc->mutex);
2118 }
2119 }
2120
2121 static int
2122 intel_finish_fb(struct drm_framebuffer *old_fb)
2123 {
2124 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2125 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2126 bool was_interruptible = dev_priv->mm.interruptible;
2127 int ret;
2128
2129 /* Big Hammer, we also need to ensure that any pending
2130 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2131 * current scanout is retired before unpinning the old
2132 * framebuffer.
2133 *
2134 * This should only fail upon a hung GPU, in which case we
2135 * can safely continue.
2136 */
2137 dev_priv->mm.interruptible = false;
2138 ret = i915_gem_object_finish_gpu(obj);
2139 dev_priv->mm.interruptible = was_interruptible;
2140
2141 return ret;
2142 }
2143
2144 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2145 {
2146 struct drm_device *dev = crtc->dev;
2147 struct drm_i915_master_private *master_priv;
2148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2149
2150 if (!dev->primary->master)
2151 return;
2152
2153 master_priv = dev->primary->master->driver_priv;
2154 if (!master_priv->sarea_priv)
2155 return;
2156
2157 switch (intel_crtc->pipe) {
2158 case 0:
2159 master_priv->sarea_priv->pipeA_x = x;
2160 master_priv->sarea_priv->pipeA_y = y;
2161 break;
2162 case 1:
2163 master_priv->sarea_priv->pipeB_x = x;
2164 master_priv->sarea_priv->pipeB_y = y;
2165 break;
2166 default:
2167 break;
2168 }
2169 }
2170
2171 static int
2172 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2173 struct drm_framebuffer *fb)
2174 {
2175 struct drm_device *dev = crtc->dev;
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2178 struct drm_framebuffer *old_fb;
2179 int ret;
2180
2181 /* no fb bound */
2182 if (!fb) {
2183 DRM_ERROR("No FB bound\n");
2184 return 0;
2185 }
2186
2187 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2188 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2189 plane_name(intel_crtc->plane),
2190 INTEL_INFO(dev)->num_pipes);
2191 return -EINVAL;
2192 }
2193
2194 mutex_lock(&dev->struct_mutex);
2195 ret = intel_pin_and_fence_fb_obj(dev,
2196 to_intel_framebuffer(fb)->obj,
2197 NULL);
2198 if (ret != 0) {
2199 mutex_unlock(&dev->struct_mutex);
2200 DRM_ERROR("pin & fence failed\n");
2201 return ret;
2202 }
2203
2204 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2205 if (ret) {
2206 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2207 mutex_unlock(&dev->struct_mutex);
2208 DRM_ERROR("failed to update base address\n");
2209 return ret;
2210 }
2211
2212 old_fb = crtc->fb;
2213 crtc->fb = fb;
2214 crtc->x = x;
2215 crtc->y = y;
2216
2217 if (old_fb) {
2218 if (intel_crtc->active && old_fb != fb)
2219 intel_wait_for_vblank(dev, intel_crtc->pipe);
2220 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2221 }
2222
2223 intel_update_fbc(dev);
2224 mutex_unlock(&dev->struct_mutex);
2225
2226 intel_crtc_update_sarea_pos(crtc, x, y);
2227
2228 return 0;
2229 }
2230
2231 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2232 {
2233 struct drm_device *dev = crtc->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236 int pipe = intel_crtc->pipe;
2237 u32 reg, temp;
2238
2239 /* enable normal train */
2240 reg = FDI_TX_CTL(pipe);
2241 temp = I915_READ(reg);
2242 if (IS_IVYBRIDGE(dev)) {
2243 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2244 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2245 } else {
2246 temp &= ~FDI_LINK_TRAIN_NONE;
2247 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2248 }
2249 I915_WRITE(reg, temp);
2250
2251 reg = FDI_RX_CTL(pipe);
2252 temp = I915_READ(reg);
2253 if (HAS_PCH_CPT(dev)) {
2254 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2255 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2256 } else {
2257 temp &= ~FDI_LINK_TRAIN_NONE;
2258 temp |= FDI_LINK_TRAIN_NONE;
2259 }
2260 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2261
2262 /* wait one idle pattern time */
2263 POSTING_READ(reg);
2264 udelay(1000);
2265
2266 /* IVB wants error correction enabled */
2267 if (IS_IVYBRIDGE(dev))
2268 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2269 FDI_FE_ERRC_ENABLE);
2270 }
2271
2272 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2273 {
2274 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2275 }
2276
2277 static void ivb_modeset_global_resources(struct drm_device *dev)
2278 {
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2280 struct intel_crtc *pipe_B_crtc =
2281 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2282 struct intel_crtc *pipe_C_crtc =
2283 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2284 uint32_t temp;
2285
2286 /*
2287 * When everything is off disable fdi C so that we could enable fdi B
2288 * with all lanes. Note that we don't care about enabled pipes without
2289 * an enabled pch encoder.
2290 */
2291 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2292 !pipe_has_enabled_pch(pipe_C_crtc)) {
2293 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2294 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2295
2296 temp = I915_READ(SOUTH_CHICKEN1);
2297 temp &= ~FDI_BC_BIFURCATION_SELECT;
2298 DRM_DEBUG_KMS("disabling fdi C rx\n");
2299 I915_WRITE(SOUTH_CHICKEN1, temp);
2300 }
2301 }
2302
2303 /* The FDI link training functions for ILK/Ibexpeak. */
2304 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2305 {
2306 struct drm_device *dev = crtc->dev;
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309 int pipe = intel_crtc->pipe;
2310 int plane = intel_crtc->plane;
2311 u32 reg, temp, tries;
2312
2313 /* FDI needs bits from pipe & plane first */
2314 assert_pipe_enabled(dev_priv, pipe);
2315 assert_plane_enabled(dev_priv, plane);
2316
2317 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2318 for train result */
2319 reg = FDI_RX_IMR(pipe);
2320 temp = I915_READ(reg);
2321 temp &= ~FDI_RX_SYMBOL_LOCK;
2322 temp &= ~FDI_RX_BIT_LOCK;
2323 I915_WRITE(reg, temp);
2324 I915_READ(reg);
2325 udelay(150);
2326
2327 /* enable CPU FDI TX and PCH FDI RX */
2328 reg = FDI_TX_CTL(pipe);
2329 temp = I915_READ(reg);
2330 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2331 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2332 temp &= ~FDI_LINK_TRAIN_NONE;
2333 temp |= FDI_LINK_TRAIN_PATTERN_1;
2334 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2335
2336 reg = FDI_RX_CTL(pipe);
2337 temp = I915_READ(reg);
2338 temp &= ~FDI_LINK_TRAIN_NONE;
2339 temp |= FDI_LINK_TRAIN_PATTERN_1;
2340 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2341
2342 POSTING_READ(reg);
2343 udelay(150);
2344
2345 /* Ironlake workaround, enable clock pointer after FDI enable*/
2346 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2347 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2348 FDI_RX_PHASE_SYNC_POINTER_EN);
2349
2350 reg = FDI_RX_IIR(pipe);
2351 for (tries = 0; tries < 5; tries++) {
2352 temp = I915_READ(reg);
2353 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2354
2355 if ((temp & FDI_RX_BIT_LOCK)) {
2356 DRM_DEBUG_KMS("FDI train 1 done.\n");
2357 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2358 break;
2359 }
2360 }
2361 if (tries == 5)
2362 DRM_ERROR("FDI train 1 fail!\n");
2363
2364 /* Train 2 */
2365 reg = FDI_TX_CTL(pipe);
2366 temp = I915_READ(reg);
2367 temp &= ~FDI_LINK_TRAIN_NONE;
2368 temp |= FDI_LINK_TRAIN_PATTERN_2;
2369 I915_WRITE(reg, temp);
2370
2371 reg = FDI_RX_CTL(pipe);
2372 temp = I915_READ(reg);
2373 temp &= ~FDI_LINK_TRAIN_NONE;
2374 temp |= FDI_LINK_TRAIN_PATTERN_2;
2375 I915_WRITE(reg, temp);
2376
2377 POSTING_READ(reg);
2378 udelay(150);
2379
2380 reg = FDI_RX_IIR(pipe);
2381 for (tries = 0; tries < 5; tries++) {
2382 temp = I915_READ(reg);
2383 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2384
2385 if (temp & FDI_RX_SYMBOL_LOCK) {
2386 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2387 DRM_DEBUG_KMS("FDI train 2 done.\n");
2388 break;
2389 }
2390 }
2391 if (tries == 5)
2392 DRM_ERROR("FDI train 2 fail!\n");
2393
2394 DRM_DEBUG_KMS("FDI train done\n");
2395
2396 }
2397
2398 static const int snb_b_fdi_train_param[] = {
2399 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2400 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2401 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2402 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2403 };
2404
2405 /* The FDI link training functions for SNB/Cougarpoint. */
2406 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2407 {
2408 struct drm_device *dev = crtc->dev;
2409 struct drm_i915_private *dev_priv = dev->dev_private;
2410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411 int pipe = intel_crtc->pipe;
2412 u32 reg, temp, i, retry;
2413
2414 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2415 for train result */
2416 reg = FDI_RX_IMR(pipe);
2417 temp = I915_READ(reg);
2418 temp &= ~FDI_RX_SYMBOL_LOCK;
2419 temp &= ~FDI_RX_BIT_LOCK;
2420 I915_WRITE(reg, temp);
2421
2422 POSTING_READ(reg);
2423 udelay(150);
2424
2425 /* enable CPU FDI TX and PCH FDI RX */
2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
2428 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2429 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_PATTERN_1;
2432 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2433 /* SNB-B */
2434 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2435 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2436
2437 I915_WRITE(FDI_RX_MISC(pipe),
2438 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2439
2440 reg = FDI_RX_CTL(pipe);
2441 temp = I915_READ(reg);
2442 if (HAS_PCH_CPT(dev)) {
2443 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2444 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2445 } else {
2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448 }
2449 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2450
2451 POSTING_READ(reg);
2452 udelay(150);
2453
2454 for (i = 0; i < 4; i++) {
2455 reg = FDI_TX_CTL(pipe);
2456 temp = I915_READ(reg);
2457 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2458 temp |= snb_b_fdi_train_param[i];
2459 I915_WRITE(reg, temp);
2460
2461 POSTING_READ(reg);
2462 udelay(500);
2463
2464 for (retry = 0; retry < 5; retry++) {
2465 reg = FDI_RX_IIR(pipe);
2466 temp = I915_READ(reg);
2467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2468 if (temp & FDI_RX_BIT_LOCK) {
2469 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2470 DRM_DEBUG_KMS("FDI train 1 done.\n");
2471 break;
2472 }
2473 udelay(50);
2474 }
2475 if (retry < 5)
2476 break;
2477 }
2478 if (i == 4)
2479 DRM_ERROR("FDI train 1 fail!\n");
2480
2481 /* Train 2 */
2482 reg = FDI_TX_CTL(pipe);
2483 temp = I915_READ(reg);
2484 temp &= ~FDI_LINK_TRAIN_NONE;
2485 temp |= FDI_LINK_TRAIN_PATTERN_2;
2486 if (IS_GEN6(dev)) {
2487 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2488 /* SNB-B */
2489 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2490 }
2491 I915_WRITE(reg, temp);
2492
2493 reg = FDI_RX_CTL(pipe);
2494 temp = I915_READ(reg);
2495 if (HAS_PCH_CPT(dev)) {
2496 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2497 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2498 } else {
2499 temp &= ~FDI_LINK_TRAIN_NONE;
2500 temp |= FDI_LINK_TRAIN_PATTERN_2;
2501 }
2502 I915_WRITE(reg, temp);
2503
2504 POSTING_READ(reg);
2505 udelay(150);
2506
2507 for (i = 0; i < 4; i++) {
2508 reg = FDI_TX_CTL(pipe);
2509 temp = I915_READ(reg);
2510 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511 temp |= snb_b_fdi_train_param[i];
2512 I915_WRITE(reg, temp);
2513
2514 POSTING_READ(reg);
2515 udelay(500);
2516
2517 for (retry = 0; retry < 5; retry++) {
2518 reg = FDI_RX_IIR(pipe);
2519 temp = I915_READ(reg);
2520 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521 if (temp & FDI_RX_SYMBOL_LOCK) {
2522 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2523 DRM_DEBUG_KMS("FDI train 2 done.\n");
2524 break;
2525 }
2526 udelay(50);
2527 }
2528 if (retry < 5)
2529 break;
2530 }
2531 if (i == 4)
2532 DRM_ERROR("FDI train 2 fail!\n");
2533
2534 DRM_DEBUG_KMS("FDI train done.\n");
2535 }
2536
2537 /* Manual link training for Ivy Bridge A0 parts */
2538 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2539 {
2540 struct drm_device *dev = crtc->dev;
2541 struct drm_i915_private *dev_priv = dev->dev_private;
2542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2543 int pipe = intel_crtc->pipe;
2544 u32 reg, temp, i;
2545
2546 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2547 for train result */
2548 reg = FDI_RX_IMR(pipe);
2549 temp = I915_READ(reg);
2550 temp &= ~FDI_RX_SYMBOL_LOCK;
2551 temp &= ~FDI_RX_BIT_LOCK;
2552 I915_WRITE(reg, temp);
2553
2554 POSTING_READ(reg);
2555 udelay(150);
2556
2557 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2558 I915_READ(FDI_RX_IIR(pipe)));
2559
2560 /* enable CPU FDI TX and PCH FDI RX */
2561 reg = FDI_TX_CTL(pipe);
2562 temp = I915_READ(reg);
2563 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2564 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2565 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2566 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2567 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2568 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2569 temp |= FDI_COMPOSITE_SYNC;
2570 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2571
2572 I915_WRITE(FDI_RX_MISC(pipe),
2573 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2574
2575 reg = FDI_RX_CTL(pipe);
2576 temp = I915_READ(reg);
2577 temp &= ~FDI_LINK_TRAIN_AUTO;
2578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2579 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2580 temp |= FDI_COMPOSITE_SYNC;
2581 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2582
2583 POSTING_READ(reg);
2584 udelay(150);
2585
2586 for (i = 0; i < 4; i++) {
2587 reg = FDI_TX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2590 temp |= snb_b_fdi_train_param[i];
2591 I915_WRITE(reg, temp);
2592
2593 POSTING_READ(reg);
2594 udelay(500);
2595
2596 reg = FDI_RX_IIR(pipe);
2597 temp = I915_READ(reg);
2598 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2599
2600 if (temp & FDI_RX_BIT_LOCK ||
2601 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2602 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2603 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2604 break;
2605 }
2606 }
2607 if (i == 4)
2608 DRM_ERROR("FDI train 1 fail!\n");
2609
2610 /* Train 2 */
2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2614 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2615 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2617 I915_WRITE(reg, temp);
2618
2619 reg = FDI_RX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2622 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2623 I915_WRITE(reg, temp);
2624
2625 POSTING_READ(reg);
2626 udelay(150);
2627
2628 for (i = 0; i < 4; i++) {
2629 reg = FDI_TX_CTL(pipe);
2630 temp = I915_READ(reg);
2631 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2632 temp |= snb_b_fdi_train_param[i];
2633 I915_WRITE(reg, temp);
2634
2635 POSTING_READ(reg);
2636 udelay(500);
2637
2638 reg = FDI_RX_IIR(pipe);
2639 temp = I915_READ(reg);
2640 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2641
2642 if (temp & FDI_RX_SYMBOL_LOCK) {
2643 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2644 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2645 break;
2646 }
2647 }
2648 if (i == 4)
2649 DRM_ERROR("FDI train 2 fail!\n");
2650
2651 DRM_DEBUG_KMS("FDI train done.\n");
2652 }
2653
2654 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2655 {
2656 struct drm_device *dev = intel_crtc->base.dev;
2657 struct drm_i915_private *dev_priv = dev->dev_private;
2658 int pipe = intel_crtc->pipe;
2659 u32 reg, temp;
2660
2661
2662 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2663 reg = FDI_RX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2667 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2668 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2669
2670 POSTING_READ(reg);
2671 udelay(200);
2672
2673 /* Switch from Rawclk to PCDclk */
2674 temp = I915_READ(reg);
2675 I915_WRITE(reg, temp | FDI_PCDCLK);
2676
2677 POSTING_READ(reg);
2678 udelay(200);
2679
2680 /* Enable CPU FDI TX PLL, always on for Ironlake */
2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2684 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2685
2686 POSTING_READ(reg);
2687 udelay(100);
2688 }
2689 }
2690
2691 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2692 {
2693 struct drm_device *dev = intel_crtc->base.dev;
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 int pipe = intel_crtc->pipe;
2696 u32 reg, temp;
2697
2698 /* Switch from PCDclk to Rawclk */
2699 reg = FDI_RX_CTL(pipe);
2700 temp = I915_READ(reg);
2701 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2702
2703 /* Disable CPU FDI TX PLL */
2704 reg = FDI_TX_CTL(pipe);
2705 temp = I915_READ(reg);
2706 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2707
2708 POSTING_READ(reg);
2709 udelay(100);
2710
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2714
2715 /* Wait for the clocks to turn off. */
2716 POSTING_READ(reg);
2717 udelay(100);
2718 }
2719
2720 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2721 {
2722 struct drm_device *dev = crtc->dev;
2723 struct drm_i915_private *dev_priv = dev->dev_private;
2724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2725 int pipe = intel_crtc->pipe;
2726 u32 reg, temp;
2727
2728 /* disable CPU FDI tx and PCH FDI rx */
2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2732 POSTING_READ(reg);
2733
2734 reg = FDI_RX_CTL(pipe);
2735 temp = I915_READ(reg);
2736 temp &= ~(0x7 << 16);
2737 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2738 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2739
2740 POSTING_READ(reg);
2741 udelay(100);
2742
2743 /* Ironlake workaround, disable clock pointer after downing FDI */
2744 if (HAS_PCH_IBX(dev)) {
2745 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2746 }
2747
2748 /* still set train pattern 1 */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~FDI_LINK_TRAIN_NONE;
2752 temp |= FDI_LINK_TRAIN_PATTERN_1;
2753 I915_WRITE(reg, temp);
2754
2755 reg = FDI_RX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 if (HAS_PCH_CPT(dev)) {
2758 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2759 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2760 } else {
2761 temp &= ~FDI_LINK_TRAIN_NONE;
2762 temp |= FDI_LINK_TRAIN_PATTERN_1;
2763 }
2764 /* BPC in FDI rx is consistent with that in PIPECONF */
2765 temp &= ~(0x07 << 16);
2766 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2767 I915_WRITE(reg, temp);
2768
2769 POSTING_READ(reg);
2770 udelay(100);
2771 }
2772
2773 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2774 {
2775 struct drm_device *dev = crtc->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778 unsigned long flags;
2779 bool pending;
2780
2781 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2782 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2783 return false;
2784
2785 spin_lock_irqsave(&dev->event_lock, flags);
2786 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2787 spin_unlock_irqrestore(&dev->event_lock, flags);
2788
2789 return pending;
2790 }
2791
2792 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2793 {
2794 struct drm_device *dev = crtc->dev;
2795 struct drm_i915_private *dev_priv = dev->dev_private;
2796
2797 if (crtc->fb == NULL)
2798 return;
2799
2800 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2801
2802 wait_event(dev_priv->pending_flip_queue,
2803 !intel_crtc_has_pending_flip(crtc));
2804
2805 mutex_lock(&dev->struct_mutex);
2806 intel_finish_fb(crtc->fb);
2807 mutex_unlock(&dev->struct_mutex);
2808 }
2809
2810 /* Program iCLKIP clock to the desired frequency */
2811 static void lpt_program_iclkip(struct drm_crtc *crtc)
2812 {
2813 struct drm_device *dev = crtc->dev;
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2816 u32 temp;
2817
2818 mutex_lock(&dev_priv->dpio_lock);
2819
2820 /* It is necessary to ungate the pixclk gate prior to programming
2821 * the divisors, and gate it back when it is done.
2822 */
2823 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2824
2825 /* Disable SSCCTL */
2826 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2827 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2828 SBI_SSCCTL_DISABLE,
2829 SBI_ICLK);
2830
2831 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2832 if (crtc->mode.clock == 20000) {
2833 auxdiv = 1;
2834 divsel = 0x41;
2835 phaseinc = 0x20;
2836 } else {
2837 /* The iCLK virtual clock root frequency is in MHz,
2838 * but the crtc->mode.clock in in KHz. To get the divisors,
2839 * it is necessary to divide one by another, so we
2840 * convert the virtual clock precision to KHz here for higher
2841 * precision.
2842 */
2843 u32 iclk_virtual_root_freq = 172800 * 1000;
2844 u32 iclk_pi_range = 64;
2845 u32 desired_divisor, msb_divisor_value, pi_value;
2846
2847 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2848 msb_divisor_value = desired_divisor / iclk_pi_range;
2849 pi_value = desired_divisor % iclk_pi_range;
2850
2851 auxdiv = 0;
2852 divsel = msb_divisor_value - 2;
2853 phaseinc = pi_value;
2854 }
2855
2856 /* This should not happen with any sane values */
2857 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2858 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2859 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2860 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2861
2862 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2863 crtc->mode.clock,
2864 auxdiv,
2865 divsel,
2866 phasedir,
2867 phaseinc);
2868
2869 /* Program SSCDIVINTPHASE6 */
2870 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2871 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2872 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2873 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2874 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2875 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2876 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2877 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2878
2879 /* Program SSCAUXDIV */
2880 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2881 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2882 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2883 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2884
2885 /* Enable modulator and associated divider */
2886 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2887 temp &= ~SBI_SSCCTL_DISABLE;
2888 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2889
2890 /* Wait for initialization time */
2891 udelay(24);
2892
2893 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2894
2895 mutex_unlock(&dev_priv->dpio_lock);
2896 }
2897
2898 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2899 enum pipe pch_transcoder)
2900 {
2901 struct drm_device *dev = crtc->base.dev;
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2903 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2904
2905 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2906 I915_READ(HTOTAL(cpu_transcoder)));
2907 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2908 I915_READ(HBLANK(cpu_transcoder)));
2909 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2910 I915_READ(HSYNC(cpu_transcoder)));
2911
2912 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2913 I915_READ(VTOTAL(cpu_transcoder)));
2914 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2915 I915_READ(VBLANK(cpu_transcoder)));
2916 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2917 I915_READ(VSYNC(cpu_transcoder)));
2918 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2919 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2920 }
2921
2922 /*
2923 * Enable PCH resources required for PCH ports:
2924 * - PCH PLLs
2925 * - FDI training & RX/TX
2926 * - update transcoder timings
2927 * - DP transcoding bits
2928 * - transcoder
2929 */
2930 static void ironlake_pch_enable(struct drm_crtc *crtc)
2931 {
2932 struct drm_device *dev = crtc->dev;
2933 struct drm_i915_private *dev_priv = dev->dev_private;
2934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2935 int pipe = intel_crtc->pipe;
2936 u32 reg, temp;
2937
2938 assert_pch_transcoder_disabled(dev_priv, pipe);
2939
2940 /* Write the TU size bits before fdi link training, so that error
2941 * detection works. */
2942 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2943 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2944
2945 /* For PCH output, training FDI link */
2946 dev_priv->display.fdi_link_train(crtc);
2947
2948 /* XXX: pch pll's can be enabled any time before we enable the PCH
2949 * transcoder, and we actually should do this to not upset any PCH
2950 * transcoder that already use the clock when we share it.
2951 *
2952 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2953 * unconditionally resets the pll - we need that to have the right LVDS
2954 * enable sequence. */
2955 ironlake_enable_pch_pll(intel_crtc);
2956
2957 if (HAS_PCH_CPT(dev)) {
2958 u32 sel;
2959
2960 temp = I915_READ(PCH_DPLL_SEL);
2961 switch (pipe) {
2962 default:
2963 case 0:
2964 temp |= TRANSA_DPLL_ENABLE;
2965 sel = TRANSA_DPLLB_SEL;
2966 break;
2967 case 1:
2968 temp |= TRANSB_DPLL_ENABLE;
2969 sel = TRANSB_DPLLB_SEL;
2970 break;
2971 case 2:
2972 temp |= TRANSC_DPLL_ENABLE;
2973 sel = TRANSC_DPLLB_SEL;
2974 break;
2975 }
2976 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2977 temp |= sel;
2978 else
2979 temp &= ~sel;
2980 I915_WRITE(PCH_DPLL_SEL, temp);
2981 }
2982
2983 /* set transcoder timing, panel must allow it */
2984 assert_panel_unlocked(dev_priv, pipe);
2985 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2986
2987 intel_fdi_normal_train(crtc);
2988
2989 /* For PCH DP, enable TRANS_DP_CTL */
2990 if (HAS_PCH_CPT(dev) &&
2991 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2992 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2993 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2994 reg = TRANS_DP_CTL(pipe);
2995 temp = I915_READ(reg);
2996 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2997 TRANS_DP_SYNC_MASK |
2998 TRANS_DP_BPC_MASK);
2999 temp |= (TRANS_DP_OUTPUT_ENABLE |
3000 TRANS_DP_ENH_FRAMING);
3001 temp |= bpc << 9; /* same format but at 11:9 */
3002
3003 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3004 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3005 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3006 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3007
3008 switch (intel_trans_dp_port_sel(crtc)) {
3009 case PCH_DP_B:
3010 temp |= TRANS_DP_PORT_SEL_B;
3011 break;
3012 case PCH_DP_C:
3013 temp |= TRANS_DP_PORT_SEL_C;
3014 break;
3015 case PCH_DP_D:
3016 temp |= TRANS_DP_PORT_SEL_D;
3017 break;
3018 default:
3019 BUG();
3020 }
3021
3022 I915_WRITE(reg, temp);
3023 }
3024
3025 ironlake_enable_pch_transcoder(dev_priv, pipe);
3026 }
3027
3028 static void lpt_pch_enable(struct drm_crtc *crtc)
3029 {
3030 struct drm_device *dev = crtc->dev;
3031 struct drm_i915_private *dev_priv = dev->dev_private;
3032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3033 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3034
3035 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3036
3037 lpt_program_iclkip(crtc);
3038
3039 /* Set transcoder timing. */
3040 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3041
3042 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3043 }
3044
3045 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3046 {
3047 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3048
3049 if (pll == NULL)
3050 return;
3051
3052 if (pll->refcount == 0) {
3053 WARN(1, "bad PCH PLL refcount\n");
3054 return;
3055 }
3056
3057 --pll->refcount;
3058 intel_crtc->pch_pll = NULL;
3059 }
3060
3061 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3062 {
3063 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3064 struct intel_pch_pll *pll;
3065 int i;
3066
3067 pll = intel_crtc->pch_pll;
3068 if (pll) {
3069 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3070 intel_crtc->base.base.id, pll->pll_reg);
3071 goto prepare;
3072 }
3073
3074 if (HAS_PCH_IBX(dev_priv->dev)) {
3075 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3076 i = intel_crtc->pipe;
3077 pll = &dev_priv->pch_plls[i];
3078
3079 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3080 intel_crtc->base.base.id, pll->pll_reg);
3081
3082 goto found;
3083 }
3084
3085 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3086 pll = &dev_priv->pch_plls[i];
3087
3088 /* Only want to check enabled timings first */
3089 if (pll->refcount == 0)
3090 continue;
3091
3092 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3093 fp == I915_READ(pll->fp0_reg)) {
3094 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3095 intel_crtc->base.base.id,
3096 pll->pll_reg, pll->refcount, pll->active);
3097
3098 goto found;
3099 }
3100 }
3101
3102 /* Ok no matching timings, maybe there's a free one? */
3103 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3104 pll = &dev_priv->pch_plls[i];
3105 if (pll->refcount == 0) {
3106 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3107 intel_crtc->base.base.id, pll->pll_reg);
3108 goto found;
3109 }
3110 }
3111
3112 return NULL;
3113
3114 found:
3115 intel_crtc->pch_pll = pll;
3116 pll->refcount++;
3117 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3118 prepare: /* separate function? */
3119 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3120
3121 /* Wait for the clocks to stabilize before rewriting the regs */
3122 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3123 POSTING_READ(pll->pll_reg);
3124 udelay(150);
3125
3126 I915_WRITE(pll->fp0_reg, fp);
3127 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3128 pll->on = false;
3129 return pll;
3130 }
3131
3132 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3133 {
3134 struct drm_i915_private *dev_priv = dev->dev_private;
3135 int dslreg = PIPEDSL(pipe);
3136 u32 temp;
3137
3138 temp = I915_READ(dslreg);
3139 udelay(500);
3140 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3141 if (wait_for(I915_READ(dslreg) != temp, 5))
3142 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3143 }
3144 }
3145
3146 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3147 {
3148 struct drm_device *dev = crtc->base.dev;
3149 struct drm_i915_private *dev_priv = dev->dev_private;
3150 int pipe = crtc->pipe;
3151
3152 if (crtc->config.pch_pfit.size) {
3153 /* Force use of hard-coded filter coefficients
3154 * as some pre-programmed values are broken,
3155 * e.g. x201.
3156 */
3157 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3158 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3159 PF_PIPE_SEL_IVB(pipe));
3160 else
3161 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3162 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3163 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3164 }
3165 }
3166
3167 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3168 {
3169 struct drm_device *dev = crtc->dev;
3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3172 struct intel_encoder *encoder;
3173 int pipe = intel_crtc->pipe;
3174 int plane = intel_crtc->plane;
3175 u32 temp;
3176
3177 WARN_ON(!crtc->enabled);
3178
3179 if (intel_crtc->active)
3180 return;
3181
3182 intel_crtc->active = true;
3183
3184 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3185 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3186
3187 intel_update_watermarks(dev);
3188
3189 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3190 temp = I915_READ(PCH_LVDS);
3191 if ((temp & LVDS_PORT_EN) == 0)
3192 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3193 }
3194
3195
3196 if (intel_crtc->config.has_pch_encoder) {
3197 /* Note: FDI PLL enabling _must_ be done before we enable the
3198 * cpu pipes, hence this is separate from all the other fdi/pch
3199 * enabling. */
3200 ironlake_fdi_pll_enable(intel_crtc);
3201 } else {
3202 assert_fdi_tx_disabled(dev_priv, pipe);
3203 assert_fdi_rx_disabled(dev_priv, pipe);
3204 }
3205
3206 for_each_encoder_on_crtc(dev, crtc, encoder)
3207 if (encoder->pre_enable)
3208 encoder->pre_enable(encoder);
3209
3210 /* Enable panel fitting for LVDS */
3211 ironlake_pfit_enable(intel_crtc);
3212
3213 /*
3214 * On ILK+ LUT must be loaded before the pipe is running but with
3215 * clocks enabled
3216 */
3217 intel_crtc_load_lut(crtc);
3218
3219 intel_enable_pipe(dev_priv, pipe,
3220 intel_crtc->config.has_pch_encoder);
3221 intel_enable_plane(dev_priv, plane, pipe);
3222 intel_crtc_update_cursor(crtc, true);
3223
3224 if (intel_crtc->config.has_pch_encoder)
3225 ironlake_pch_enable(crtc);
3226
3227 mutex_lock(&dev->struct_mutex);
3228 intel_update_fbc(dev);
3229 mutex_unlock(&dev->struct_mutex);
3230
3231 for_each_encoder_on_crtc(dev, crtc, encoder)
3232 encoder->enable(encoder);
3233
3234 if (HAS_PCH_CPT(dev))
3235 cpt_verify_modeset(dev, intel_crtc->pipe);
3236
3237 /*
3238 * There seems to be a race in PCH platform hw (at least on some
3239 * outputs) where an enabled pipe still completes any pageflip right
3240 * away (as if the pipe is off) instead of waiting for vblank. As soon
3241 * as the first vblank happend, everything works as expected. Hence just
3242 * wait for one vblank before returning to avoid strange things
3243 * happening.
3244 */
3245 intel_wait_for_vblank(dev, intel_crtc->pipe);
3246 }
3247
3248 /* IPS only exists on ULT machines and is tied to pipe A. */
3249 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3250 {
3251 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3252 }
3253
3254 static void hsw_enable_ips(struct intel_crtc *crtc)
3255 {
3256 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3257
3258 if (!crtc->config.ips_enabled)
3259 return;
3260
3261 /* We can only enable IPS after we enable a plane and wait for a vblank.
3262 * We guarantee that the plane is enabled by calling intel_enable_ips
3263 * only after intel_enable_plane. And intel_enable_plane already waits
3264 * for a vblank, so all we need to do here is to enable the IPS bit. */
3265 assert_plane_enabled(dev_priv, crtc->plane);
3266 I915_WRITE(IPS_CTL, IPS_ENABLE);
3267 }
3268
3269 static void hsw_disable_ips(struct intel_crtc *crtc)
3270 {
3271 struct drm_device *dev = crtc->base.dev;
3272 struct drm_i915_private *dev_priv = dev->dev_private;
3273
3274 if (!crtc->config.ips_enabled)
3275 return;
3276
3277 assert_plane_enabled(dev_priv, crtc->plane);
3278 I915_WRITE(IPS_CTL, 0);
3279
3280 /* We need to wait for a vblank before we can disable the plane. */
3281 intel_wait_for_vblank(dev, crtc->pipe);
3282 }
3283
3284 static void haswell_crtc_enable(struct drm_crtc *crtc)
3285 {
3286 struct drm_device *dev = crtc->dev;
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3289 struct intel_encoder *encoder;
3290 int pipe = intel_crtc->pipe;
3291 int plane = intel_crtc->plane;
3292
3293 WARN_ON(!crtc->enabled);
3294
3295 if (intel_crtc->active)
3296 return;
3297
3298 intel_crtc->active = true;
3299
3300 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3301 if (intel_crtc->config.has_pch_encoder)
3302 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3303
3304 intel_update_watermarks(dev);
3305
3306 if (intel_crtc->config.has_pch_encoder)
3307 dev_priv->display.fdi_link_train(crtc);
3308
3309 for_each_encoder_on_crtc(dev, crtc, encoder)
3310 if (encoder->pre_enable)
3311 encoder->pre_enable(encoder);
3312
3313 intel_ddi_enable_pipe_clock(intel_crtc);
3314
3315 /* Enable panel fitting for eDP */
3316 ironlake_pfit_enable(intel_crtc);
3317
3318 /*
3319 * On ILK+ LUT must be loaded before the pipe is running but with
3320 * clocks enabled
3321 */
3322 intel_crtc_load_lut(crtc);
3323
3324 intel_ddi_set_pipe_settings(crtc);
3325 intel_ddi_enable_transcoder_func(crtc);
3326
3327 intel_enable_pipe(dev_priv, pipe,
3328 intel_crtc->config.has_pch_encoder);
3329 intel_enable_plane(dev_priv, plane, pipe);
3330 intel_crtc_update_cursor(crtc, true);
3331
3332 hsw_enable_ips(intel_crtc);
3333
3334 if (intel_crtc->config.has_pch_encoder)
3335 lpt_pch_enable(crtc);
3336
3337 mutex_lock(&dev->struct_mutex);
3338 intel_update_fbc(dev);
3339 mutex_unlock(&dev->struct_mutex);
3340
3341 for_each_encoder_on_crtc(dev, crtc, encoder)
3342 encoder->enable(encoder);
3343
3344 /*
3345 * There seems to be a race in PCH platform hw (at least on some
3346 * outputs) where an enabled pipe still completes any pageflip right
3347 * away (as if the pipe is off) instead of waiting for vblank. As soon
3348 * as the first vblank happend, everything works as expected. Hence just
3349 * wait for one vblank before returning to avoid strange things
3350 * happening.
3351 */
3352 intel_wait_for_vblank(dev, intel_crtc->pipe);
3353 }
3354
3355 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3356 {
3357 struct drm_device *dev = crtc->base.dev;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 int pipe = crtc->pipe;
3360
3361 /* To avoid upsetting the power well on haswell only disable the pfit if
3362 * it's in use. The hw state code will make sure we get this right. */
3363 if (crtc->config.pch_pfit.size) {
3364 I915_WRITE(PF_CTL(pipe), 0);
3365 I915_WRITE(PF_WIN_POS(pipe), 0);
3366 I915_WRITE(PF_WIN_SZ(pipe), 0);
3367 }
3368 }
3369
3370 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3371 {
3372 struct drm_device *dev = crtc->dev;
3373 struct drm_i915_private *dev_priv = dev->dev_private;
3374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3375 struct intel_encoder *encoder;
3376 int pipe = intel_crtc->pipe;
3377 int plane = intel_crtc->plane;
3378 u32 reg, temp;
3379
3380
3381 if (!intel_crtc->active)
3382 return;
3383
3384 for_each_encoder_on_crtc(dev, crtc, encoder)
3385 encoder->disable(encoder);
3386
3387 intel_crtc_wait_for_pending_flips(crtc);
3388 drm_vblank_off(dev, pipe);
3389 intel_crtc_update_cursor(crtc, false);
3390
3391 intel_disable_plane(dev_priv, plane, pipe);
3392
3393 if (dev_priv->cfb_plane == plane)
3394 intel_disable_fbc(dev);
3395
3396 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3397 intel_disable_pipe(dev_priv, pipe);
3398
3399 ironlake_pfit_disable(intel_crtc);
3400
3401 for_each_encoder_on_crtc(dev, crtc, encoder)
3402 if (encoder->post_disable)
3403 encoder->post_disable(encoder);
3404
3405 ironlake_fdi_disable(crtc);
3406
3407 ironlake_disable_pch_transcoder(dev_priv, pipe);
3408 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3409
3410 if (HAS_PCH_CPT(dev)) {
3411 /* disable TRANS_DP_CTL */
3412 reg = TRANS_DP_CTL(pipe);
3413 temp = I915_READ(reg);
3414 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3415 temp |= TRANS_DP_PORT_SEL_NONE;
3416 I915_WRITE(reg, temp);
3417
3418 /* disable DPLL_SEL */
3419 temp = I915_READ(PCH_DPLL_SEL);
3420 switch (pipe) {
3421 case 0:
3422 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3423 break;
3424 case 1:
3425 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3426 break;
3427 case 2:
3428 /* C shares PLL A or B */
3429 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3430 break;
3431 default:
3432 BUG(); /* wtf */
3433 }
3434 I915_WRITE(PCH_DPLL_SEL, temp);
3435 }
3436
3437 /* disable PCH DPLL */
3438 intel_disable_pch_pll(intel_crtc);
3439
3440 ironlake_fdi_pll_disable(intel_crtc);
3441
3442 intel_crtc->active = false;
3443 intel_update_watermarks(dev);
3444
3445 mutex_lock(&dev->struct_mutex);
3446 intel_update_fbc(dev);
3447 mutex_unlock(&dev->struct_mutex);
3448 }
3449
3450 static void haswell_crtc_disable(struct drm_crtc *crtc)
3451 {
3452 struct drm_device *dev = crtc->dev;
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3455 struct intel_encoder *encoder;
3456 int pipe = intel_crtc->pipe;
3457 int plane = intel_crtc->plane;
3458 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3459
3460 if (!intel_crtc->active)
3461 return;
3462
3463 for_each_encoder_on_crtc(dev, crtc, encoder)
3464 encoder->disable(encoder);
3465
3466 intel_crtc_wait_for_pending_flips(crtc);
3467 drm_vblank_off(dev, pipe);
3468 intel_crtc_update_cursor(crtc, false);
3469
3470 /* FBC must be disabled before disabling the plane on HSW. */
3471 if (dev_priv->cfb_plane == plane)
3472 intel_disable_fbc(dev);
3473
3474 hsw_disable_ips(intel_crtc);
3475
3476 intel_disable_plane(dev_priv, plane, pipe);
3477
3478 if (intel_crtc->config.has_pch_encoder)
3479 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3480 intel_disable_pipe(dev_priv, pipe);
3481
3482 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3483
3484 ironlake_pfit_disable(intel_crtc);
3485
3486 intel_ddi_disable_pipe_clock(intel_crtc);
3487
3488 for_each_encoder_on_crtc(dev, crtc, encoder)
3489 if (encoder->post_disable)
3490 encoder->post_disable(encoder);
3491
3492 if (intel_crtc->config.has_pch_encoder) {
3493 lpt_disable_pch_transcoder(dev_priv);
3494 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3495 intel_ddi_fdi_disable(crtc);
3496 }
3497
3498 intel_crtc->active = false;
3499 intel_update_watermarks(dev);
3500
3501 mutex_lock(&dev->struct_mutex);
3502 intel_update_fbc(dev);
3503 mutex_unlock(&dev->struct_mutex);
3504 }
3505
3506 static void ironlake_crtc_off(struct drm_crtc *crtc)
3507 {
3508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3509 intel_put_pch_pll(intel_crtc);
3510 }
3511
3512 static void haswell_crtc_off(struct drm_crtc *crtc)
3513 {
3514 intel_ddi_put_crtc_pll(crtc);
3515 }
3516
3517 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3518 {
3519 if (!enable && intel_crtc->overlay) {
3520 struct drm_device *dev = intel_crtc->base.dev;
3521 struct drm_i915_private *dev_priv = dev->dev_private;
3522
3523 mutex_lock(&dev->struct_mutex);
3524 dev_priv->mm.interruptible = false;
3525 (void) intel_overlay_switch_off(intel_crtc->overlay);
3526 dev_priv->mm.interruptible = true;
3527 mutex_unlock(&dev->struct_mutex);
3528 }
3529
3530 /* Let userspace switch the overlay on again. In most cases userspace
3531 * has to recompute where to put it anyway.
3532 */
3533 }
3534
3535 /**
3536 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3537 * cursor plane briefly if not already running after enabling the display
3538 * plane.
3539 * This workaround avoids occasional blank screens when self refresh is
3540 * enabled.
3541 */
3542 static void
3543 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3544 {
3545 u32 cntl = I915_READ(CURCNTR(pipe));
3546
3547 if ((cntl & CURSOR_MODE) == 0) {
3548 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3549
3550 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3551 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3552 intel_wait_for_vblank(dev_priv->dev, pipe);
3553 I915_WRITE(CURCNTR(pipe), cntl);
3554 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3555 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3556 }
3557 }
3558
3559 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3560 {
3561 struct drm_device *dev = crtc->base.dev;
3562 struct drm_i915_private *dev_priv = dev->dev_private;
3563 struct intel_crtc_config *pipe_config = &crtc->config;
3564
3565 if (!crtc->config.gmch_pfit.control)
3566 return;
3567
3568 /*
3569 * The panel fitter should only be adjusted whilst the pipe is disabled,
3570 * according to register description and PRM.
3571 */
3572 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3573 assert_pipe_disabled(dev_priv, crtc->pipe);
3574
3575 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3576 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3577
3578 /* Border color in case we don't scale up to the full screen. Black by
3579 * default, change to something else for debugging. */
3580 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3581 }
3582
3583 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3584 {
3585 struct drm_device *dev = crtc->dev;
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3588 struct intel_encoder *encoder;
3589 int pipe = intel_crtc->pipe;
3590 int plane = intel_crtc->plane;
3591
3592 WARN_ON(!crtc->enabled);
3593
3594 if (intel_crtc->active)
3595 return;
3596
3597 intel_crtc->active = true;
3598 intel_update_watermarks(dev);
3599
3600 mutex_lock(&dev_priv->dpio_lock);
3601
3602 for_each_encoder_on_crtc(dev, crtc, encoder)
3603 if (encoder->pre_pll_enable)
3604 encoder->pre_pll_enable(encoder);
3605
3606 intel_enable_pll(dev_priv, pipe);
3607
3608 for_each_encoder_on_crtc(dev, crtc, encoder)
3609 if (encoder->pre_enable)
3610 encoder->pre_enable(encoder);
3611
3612 /* VLV wants encoder enabling _before_ the pipe is up. */
3613 for_each_encoder_on_crtc(dev, crtc, encoder)
3614 encoder->enable(encoder);
3615
3616 /* Enable panel fitting for eDP */
3617 i9xx_pfit_enable(intel_crtc);
3618
3619 intel_crtc_load_lut(crtc);
3620
3621 intel_enable_pipe(dev_priv, pipe, false);
3622 intel_enable_plane(dev_priv, plane, pipe);
3623 intel_crtc_update_cursor(crtc, true);
3624
3625 intel_update_fbc(dev);
3626
3627 /* Give the overlay scaler a chance to enable if it's on this pipe */
3628 intel_crtc_dpms_overlay(intel_crtc, true);
3629
3630 mutex_unlock(&dev_priv->dpio_lock);
3631 }
3632
3633 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3634 {
3635 struct drm_device *dev = crtc->dev;
3636 struct drm_i915_private *dev_priv = dev->dev_private;
3637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3638 struct intel_encoder *encoder;
3639 int pipe = intel_crtc->pipe;
3640 int plane = intel_crtc->plane;
3641
3642 WARN_ON(!crtc->enabled);
3643
3644 if (intel_crtc->active)
3645 return;
3646
3647 intel_crtc->active = true;
3648 intel_update_watermarks(dev);
3649
3650 intel_enable_pll(dev_priv, pipe);
3651
3652 for_each_encoder_on_crtc(dev, crtc, encoder)
3653 if (encoder->pre_enable)
3654 encoder->pre_enable(encoder);
3655
3656 /* Enable panel fitting for LVDS */
3657 i9xx_pfit_enable(intel_crtc);
3658
3659 intel_crtc_load_lut(crtc);
3660
3661 intel_enable_pipe(dev_priv, pipe, false);
3662 intel_enable_plane(dev_priv, plane, pipe);
3663 intel_crtc_update_cursor(crtc, true);
3664 if (IS_G4X(dev))
3665 g4x_fixup_plane(dev_priv, pipe);
3666
3667 intel_update_fbc(dev);
3668
3669 /* Give the overlay scaler a chance to enable if it's on this pipe */
3670 intel_crtc_dpms_overlay(intel_crtc, true);
3671
3672 for_each_encoder_on_crtc(dev, crtc, encoder)
3673 encoder->enable(encoder);
3674 }
3675
3676 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3677 {
3678 struct drm_device *dev = crtc->base.dev;
3679 struct drm_i915_private *dev_priv = dev->dev_private;
3680
3681 if (!crtc->config.gmch_pfit.control)
3682 return;
3683
3684 assert_pipe_disabled(dev_priv, crtc->pipe);
3685
3686 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3687 I915_READ(PFIT_CONTROL));
3688 I915_WRITE(PFIT_CONTROL, 0);
3689 }
3690
3691 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3692 {
3693 struct drm_device *dev = crtc->dev;
3694 struct drm_i915_private *dev_priv = dev->dev_private;
3695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3696 struct intel_encoder *encoder;
3697 int pipe = intel_crtc->pipe;
3698 int plane = intel_crtc->plane;
3699
3700 if (!intel_crtc->active)
3701 return;
3702
3703 for_each_encoder_on_crtc(dev, crtc, encoder)
3704 encoder->disable(encoder);
3705
3706 /* Give the overlay scaler a chance to disable if it's on this pipe */
3707 intel_crtc_wait_for_pending_flips(crtc);
3708 drm_vblank_off(dev, pipe);
3709 intel_crtc_dpms_overlay(intel_crtc, false);
3710 intel_crtc_update_cursor(crtc, false);
3711
3712 if (dev_priv->cfb_plane == plane)
3713 intel_disable_fbc(dev);
3714
3715 intel_disable_plane(dev_priv, plane, pipe);
3716 intel_disable_pipe(dev_priv, pipe);
3717
3718 i9xx_pfit_disable(intel_crtc);
3719
3720 for_each_encoder_on_crtc(dev, crtc, encoder)
3721 if (encoder->post_disable)
3722 encoder->post_disable(encoder);
3723
3724 intel_disable_pll(dev_priv, pipe);
3725
3726 intel_crtc->active = false;
3727 intel_update_fbc(dev);
3728 intel_update_watermarks(dev);
3729 }
3730
3731 static void i9xx_crtc_off(struct drm_crtc *crtc)
3732 {
3733 }
3734
3735 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3736 bool enabled)
3737 {
3738 struct drm_device *dev = crtc->dev;
3739 struct drm_i915_master_private *master_priv;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741 int pipe = intel_crtc->pipe;
3742
3743 if (!dev->primary->master)
3744 return;
3745
3746 master_priv = dev->primary->master->driver_priv;
3747 if (!master_priv->sarea_priv)
3748 return;
3749
3750 switch (pipe) {
3751 case 0:
3752 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3753 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3754 break;
3755 case 1:
3756 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3757 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3758 break;
3759 default:
3760 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3761 break;
3762 }
3763 }
3764
3765 /**
3766 * Sets the power management mode of the pipe and plane.
3767 */
3768 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3769 {
3770 struct drm_device *dev = crtc->dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772 struct intel_encoder *intel_encoder;
3773 bool enable = false;
3774
3775 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3776 enable |= intel_encoder->connectors_active;
3777
3778 if (enable)
3779 dev_priv->display.crtc_enable(crtc);
3780 else
3781 dev_priv->display.crtc_disable(crtc);
3782
3783 intel_crtc_update_sarea(crtc, enable);
3784 }
3785
3786 static void intel_crtc_disable(struct drm_crtc *crtc)
3787 {
3788 struct drm_device *dev = crtc->dev;
3789 struct drm_connector *connector;
3790 struct drm_i915_private *dev_priv = dev->dev_private;
3791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3792
3793 /* crtc should still be enabled when we disable it. */
3794 WARN_ON(!crtc->enabled);
3795
3796 dev_priv->display.crtc_disable(crtc);
3797 intel_crtc->eld_vld = false;
3798 intel_crtc_update_sarea(crtc, false);
3799 dev_priv->display.off(crtc);
3800
3801 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3802 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3803
3804 if (crtc->fb) {
3805 mutex_lock(&dev->struct_mutex);
3806 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3807 mutex_unlock(&dev->struct_mutex);
3808 crtc->fb = NULL;
3809 }
3810
3811 /* Update computed state. */
3812 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3813 if (!connector->encoder || !connector->encoder->crtc)
3814 continue;
3815
3816 if (connector->encoder->crtc != crtc)
3817 continue;
3818
3819 connector->dpms = DRM_MODE_DPMS_OFF;
3820 to_intel_encoder(connector->encoder)->connectors_active = false;
3821 }
3822 }
3823
3824 void intel_modeset_disable(struct drm_device *dev)
3825 {
3826 struct drm_crtc *crtc;
3827
3828 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3829 if (crtc->enabled)
3830 intel_crtc_disable(crtc);
3831 }
3832 }
3833
3834 void intel_encoder_destroy(struct drm_encoder *encoder)
3835 {
3836 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3837
3838 drm_encoder_cleanup(encoder);
3839 kfree(intel_encoder);
3840 }
3841
3842 /* Simple dpms helper for encodres with just one connector, no cloning and only
3843 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3844 * state of the entire output pipe. */
3845 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3846 {
3847 if (mode == DRM_MODE_DPMS_ON) {
3848 encoder->connectors_active = true;
3849
3850 intel_crtc_update_dpms(encoder->base.crtc);
3851 } else {
3852 encoder->connectors_active = false;
3853
3854 intel_crtc_update_dpms(encoder->base.crtc);
3855 }
3856 }
3857
3858 /* Cross check the actual hw state with our own modeset state tracking (and it's
3859 * internal consistency). */
3860 static void intel_connector_check_state(struct intel_connector *connector)
3861 {
3862 if (connector->get_hw_state(connector)) {
3863 struct intel_encoder *encoder = connector->encoder;
3864 struct drm_crtc *crtc;
3865 bool encoder_enabled;
3866 enum pipe pipe;
3867
3868 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3869 connector->base.base.id,
3870 drm_get_connector_name(&connector->base));
3871
3872 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3873 "wrong connector dpms state\n");
3874 WARN(connector->base.encoder != &encoder->base,
3875 "active connector not linked to encoder\n");
3876 WARN(!encoder->connectors_active,
3877 "encoder->connectors_active not set\n");
3878
3879 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3880 WARN(!encoder_enabled, "encoder not enabled\n");
3881 if (WARN_ON(!encoder->base.crtc))
3882 return;
3883
3884 crtc = encoder->base.crtc;
3885
3886 WARN(!crtc->enabled, "crtc not enabled\n");
3887 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3888 WARN(pipe != to_intel_crtc(crtc)->pipe,
3889 "encoder active on the wrong pipe\n");
3890 }
3891 }
3892
3893 /* Even simpler default implementation, if there's really no special case to
3894 * consider. */
3895 void intel_connector_dpms(struct drm_connector *connector, int mode)
3896 {
3897 struct intel_encoder *encoder = intel_attached_encoder(connector);
3898
3899 /* All the simple cases only support two dpms states. */
3900 if (mode != DRM_MODE_DPMS_ON)
3901 mode = DRM_MODE_DPMS_OFF;
3902
3903 if (mode == connector->dpms)
3904 return;
3905
3906 connector->dpms = mode;
3907
3908 /* Only need to change hw state when actually enabled */
3909 if (encoder->base.crtc)
3910 intel_encoder_dpms(encoder, mode);
3911 else
3912 WARN_ON(encoder->connectors_active != false);
3913
3914 intel_modeset_check_state(connector->dev);
3915 }
3916
3917 /* Simple connector->get_hw_state implementation for encoders that support only
3918 * one connector and no cloning and hence the encoder state determines the state
3919 * of the connector. */
3920 bool intel_connector_get_hw_state(struct intel_connector *connector)
3921 {
3922 enum pipe pipe = 0;
3923 struct intel_encoder *encoder = connector->encoder;
3924
3925 return encoder->get_hw_state(encoder, &pipe);
3926 }
3927
3928 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3929 struct intel_crtc_config *pipe_config)
3930 {
3931 struct drm_i915_private *dev_priv = dev->dev_private;
3932 struct intel_crtc *pipe_B_crtc =
3933 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3934
3935 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3936 pipe_name(pipe), pipe_config->fdi_lanes);
3937 if (pipe_config->fdi_lanes > 4) {
3938 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3939 pipe_name(pipe), pipe_config->fdi_lanes);
3940 return false;
3941 }
3942
3943 if (IS_HASWELL(dev)) {
3944 if (pipe_config->fdi_lanes > 2) {
3945 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3946 pipe_config->fdi_lanes);
3947 return false;
3948 } else {
3949 return true;
3950 }
3951 }
3952
3953 if (INTEL_INFO(dev)->num_pipes == 2)
3954 return true;
3955
3956 /* Ivybridge 3 pipe is really complicated */
3957 switch (pipe) {
3958 case PIPE_A:
3959 return true;
3960 case PIPE_B:
3961 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3962 pipe_config->fdi_lanes > 2) {
3963 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3964 pipe_name(pipe), pipe_config->fdi_lanes);
3965 return false;
3966 }
3967 return true;
3968 case PIPE_C:
3969 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3970 pipe_B_crtc->config.fdi_lanes <= 2) {
3971 if (pipe_config->fdi_lanes > 2) {
3972 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3973 pipe_name(pipe), pipe_config->fdi_lanes);
3974 return false;
3975 }
3976 } else {
3977 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3978 return false;
3979 }
3980 return true;
3981 default:
3982 BUG();
3983 }
3984 }
3985
3986 #define RETRY 1
3987 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3988 struct intel_crtc_config *pipe_config)
3989 {
3990 struct drm_device *dev = intel_crtc->base.dev;
3991 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3992 int lane, link_bw, fdi_dotclock;
3993 bool setup_ok, needs_recompute = false;
3994
3995 retry:
3996 /* FDI is a binary signal running at ~2.7GHz, encoding
3997 * each output octet as 10 bits. The actual frequency
3998 * is stored as a divider into a 100MHz clock, and the
3999 * mode pixel clock is stored in units of 1KHz.
4000 * Hence the bw of each lane in terms of the mode signal
4001 * is:
4002 */
4003 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4004
4005 fdi_dotclock = adjusted_mode->clock;
4006 fdi_dotclock /= pipe_config->pixel_multiplier;
4007
4008 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4009 pipe_config->pipe_bpp);
4010
4011 pipe_config->fdi_lanes = lane;
4012
4013 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4014 link_bw, &pipe_config->fdi_m_n);
4015
4016 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4017 intel_crtc->pipe, pipe_config);
4018 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4019 pipe_config->pipe_bpp -= 2*3;
4020 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4021 pipe_config->pipe_bpp);
4022 needs_recompute = true;
4023 pipe_config->bw_constrained = true;
4024
4025 goto retry;
4026 }
4027
4028 if (needs_recompute)
4029 return RETRY;
4030
4031 return setup_ok ? 0 : -EINVAL;
4032 }
4033
4034 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4035 struct intel_crtc_config *pipe_config)
4036 {
4037 pipe_config->ips_enabled = i915_enable_ips &&
4038 hsw_crtc_supports_ips(crtc) &&
4039 pipe_config->pipe_bpp == 24;
4040 }
4041
4042 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4043 struct intel_crtc_config *pipe_config)
4044 {
4045 struct drm_device *dev = crtc->dev;
4046 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4048
4049 if (HAS_PCH_SPLIT(dev)) {
4050 /* FDI link clock is fixed at 2.7G */
4051 if (pipe_config->requested_mode.clock * 3
4052 > IRONLAKE_FDI_FREQ * 4)
4053 return -EINVAL;
4054 }
4055
4056 /* All interlaced capable intel hw wants timings in frames. Note though
4057 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4058 * timings, so we need to be careful not to clobber these.*/
4059 if (!pipe_config->timings_set)
4060 drm_mode_set_crtcinfo(adjusted_mode, 0);
4061
4062 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4063 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4064 */
4065 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4066 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4067 return -EINVAL;
4068
4069 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4070 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4071 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4072 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4073 * for lvds. */
4074 pipe_config->pipe_bpp = 8*3;
4075 }
4076
4077 if (IS_HASWELL(dev))
4078 hsw_compute_ips_config(intel_crtc, pipe_config);
4079
4080 if (pipe_config->has_pch_encoder)
4081 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
4082
4083 return 0;
4084 }
4085
4086 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4087 {
4088 return 400000; /* FIXME */
4089 }
4090
4091 static int i945_get_display_clock_speed(struct drm_device *dev)
4092 {
4093 return 400000;
4094 }
4095
4096 static int i915_get_display_clock_speed(struct drm_device *dev)
4097 {
4098 return 333000;
4099 }
4100
4101 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4102 {
4103 return 200000;
4104 }
4105
4106 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4107 {
4108 u16 gcfgc = 0;
4109
4110 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4111
4112 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4113 return 133000;
4114 else {
4115 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4116 case GC_DISPLAY_CLOCK_333_MHZ:
4117 return 333000;
4118 default:
4119 case GC_DISPLAY_CLOCK_190_200_MHZ:
4120 return 190000;
4121 }
4122 }
4123 }
4124
4125 static int i865_get_display_clock_speed(struct drm_device *dev)
4126 {
4127 return 266000;
4128 }
4129
4130 static int i855_get_display_clock_speed(struct drm_device *dev)
4131 {
4132 u16 hpllcc = 0;
4133 /* Assume that the hardware is in the high speed state. This
4134 * should be the default.
4135 */
4136 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4137 case GC_CLOCK_133_200:
4138 case GC_CLOCK_100_200:
4139 return 200000;
4140 case GC_CLOCK_166_250:
4141 return 250000;
4142 case GC_CLOCK_100_133:
4143 return 133000;
4144 }
4145
4146 /* Shouldn't happen */
4147 return 0;
4148 }
4149
4150 static int i830_get_display_clock_speed(struct drm_device *dev)
4151 {
4152 return 133000;
4153 }
4154
4155 static void
4156 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4157 {
4158 while (*num > DATA_LINK_M_N_MASK ||
4159 *den > DATA_LINK_M_N_MASK) {
4160 *num >>= 1;
4161 *den >>= 1;
4162 }
4163 }
4164
4165 static void compute_m_n(unsigned int m, unsigned int n,
4166 uint32_t *ret_m, uint32_t *ret_n)
4167 {
4168 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4169 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4170 intel_reduce_m_n_ratio(ret_m, ret_n);
4171 }
4172
4173 void
4174 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4175 int pixel_clock, int link_clock,
4176 struct intel_link_m_n *m_n)
4177 {
4178 m_n->tu = 64;
4179
4180 compute_m_n(bits_per_pixel * pixel_clock,
4181 link_clock * nlanes * 8,
4182 &m_n->gmch_m, &m_n->gmch_n);
4183
4184 compute_m_n(pixel_clock, link_clock,
4185 &m_n->link_m, &m_n->link_n);
4186 }
4187
4188 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4189 {
4190 if (i915_panel_use_ssc >= 0)
4191 return i915_panel_use_ssc != 0;
4192 return dev_priv->vbt.lvds_use_ssc
4193 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4194 }
4195
4196 static int vlv_get_refclk(struct drm_crtc *crtc)
4197 {
4198 struct drm_device *dev = crtc->dev;
4199 struct drm_i915_private *dev_priv = dev->dev_private;
4200 int refclk = 27000; /* for DP & HDMI */
4201
4202 return 100000; /* only one validated so far */
4203
4204 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4205 refclk = 96000;
4206 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4207 if (intel_panel_use_ssc(dev_priv))
4208 refclk = 100000;
4209 else
4210 refclk = 96000;
4211 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4212 refclk = 100000;
4213 }
4214
4215 return refclk;
4216 }
4217
4218 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4219 {
4220 struct drm_device *dev = crtc->dev;
4221 struct drm_i915_private *dev_priv = dev->dev_private;
4222 int refclk;
4223
4224 if (IS_VALLEYVIEW(dev)) {
4225 refclk = vlv_get_refclk(crtc);
4226 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4227 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4228 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4229 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4230 refclk / 1000);
4231 } else if (!IS_GEN2(dev)) {
4232 refclk = 96000;
4233 } else {
4234 refclk = 48000;
4235 }
4236
4237 return refclk;
4238 }
4239
4240 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4241 {
4242 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4243 }
4244
4245 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4246 {
4247 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4248 }
4249
4250 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4251 intel_clock_t *reduced_clock)
4252 {
4253 struct drm_device *dev = crtc->base.dev;
4254 struct drm_i915_private *dev_priv = dev->dev_private;
4255 int pipe = crtc->pipe;
4256 u32 fp, fp2 = 0;
4257
4258 if (IS_PINEVIEW(dev)) {
4259 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4260 if (reduced_clock)
4261 fp2 = pnv_dpll_compute_fp(reduced_clock);
4262 } else {
4263 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4264 if (reduced_clock)
4265 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4266 }
4267
4268 I915_WRITE(FP0(pipe), fp);
4269
4270 crtc->lowfreq_avail = false;
4271 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4272 reduced_clock && i915_powersave) {
4273 I915_WRITE(FP1(pipe), fp2);
4274 crtc->lowfreq_avail = true;
4275 } else {
4276 I915_WRITE(FP1(pipe), fp);
4277 }
4278 }
4279
4280 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4281 {
4282 u32 reg_val;
4283
4284 /*
4285 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4286 * and set it to a reasonable value instead.
4287 */
4288 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4289 reg_val &= 0xffffff00;
4290 reg_val |= 0x00000030;
4291 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4292
4293 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4294 reg_val &= 0x8cffffff;
4295 reg_val = 0x8c000000;
4296 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4297
4298 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4299 reg_val &= 0xffffff00;
4300 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4301
4302 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4303 reg_val &= 0x00ffffff;
4304 reg_val |= 0xb0000000;
4305 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4306 }
4307
4308 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4309 struct intel_link_m_n *m_n)
4310 {
4311 struct drm_device *dev = crtc->base.dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int pipe = crtc->pipe;
4314
4315 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4316 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4317 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4318 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4319 }
4320
4321 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4322 struct intel_link_m_n *m_n)
4323 {
4324 struct drm_device *dev = crtc->base.dev;
4325 struct drm_i915_private *dev_priv = dev->dev_private;
4326 int pipe = crtc->pipe;
4327 enum transcoder transcoder = crtc->config.cpu_transcoder;
4328
4329 if (INTEL_INFO(dev)->gen >= 5) {
4330 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4331 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4332 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4333 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4334 } else {
4335 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4336 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4337 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4338 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4339 }
4340 }
4341
4342 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4343 {
4344 if (crtc->config.has_pch_encoder)
4345 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4346 else
4347 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4348 }
4349
4350 static void vlv_update_pll(struct intel_crtc *crtc)
4351 {
4352 struct drm_device *dev = crtc->base.dev;
4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 struct intel_encoder *encoder;
4355 int pipe = crtc->pipe;
4356 u32 dpll, mdiv;
4357 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4358 bool is_hdmi;
4359 u32 coreclk, reg_val, dpll_md;
4360
4361 mutex_lock(&dev_priv->dpio_lock);
4362
4363 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4364
4365 bestn = crtc->config.dpll.n;
4366 bestm1 = crtc->config.dpll.m1;
4367 bestm2 = crtc->config.dpll.m2;
4368 bestp1 = crtc->config.dpll.p1;
4369 bestp2 = crtc->config.dpll.p2;
4370
4371 /* See eDP HDMI DPIO driver vbios notes doc */
4372
4373 /* PLL B needs special handling */
4374 if (pipe)
4375 vlv_pllb_recal_opamp(dev_priv);
4376
4377 /* Set up Tx target for periodic Rcomp update */
4378 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4379
4380 /* Disable target IRef on PLL */
4381 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4382 reg_val &= 0x00ffffff;
4383 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4384
4385 /* Disable fast lock */
4386 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4387
4388 /* Set idtafcrecal before PLL is enabled */
4389 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4390 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4391 mdiv |= ((bestn << DPIO_N_SHIFT));
4392 mdiv |= (1 << DPIO_K_SHIFT);
4393
4394 /*
4395 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4396 * but we don't support that).
4397 * Note: don't use the DAC post divider as it seems unstable.
4398 */
4399 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4400 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4401
4402 mdiv |= DPIO_ENABLE_CALIBRATION;
4403 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4404
4405 /* Set HBR and RBR LPF coefficients */
4406 if (crtc->config.port_clock == 162000 ||
4407 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4408 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4409 0x005f0021);
4410 else
4411 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4412 0x00d0000f);
4413
4414 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4415 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4416 /* Use SSC source */
4417 if (!pipe)
4418 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4419 0x0df40000);
4420 else
4421 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4422 0x0df70000);
4423 } else { /* HDMI or VGA */
4424 /* Use bend source */
4425 if (!pipe)
4426 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4427 0x0df70000);
4428 else
4429 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4430 0x0df40000);
4431 }
4432
4433 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4434 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4435 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4436 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4437 coreclk |= 0x01000000;
4438 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4439
4440 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4441
4442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4443 if (encoder->pre_pll_enable)
4444 encoder->pre_pll_enable(encoder);
4445
4446 /* Enable DPIO clock input */
4447 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4448 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4449 if (pipe)
4450 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4451
4452 dpll |= DPLL_VCO_ENABLE;
4453 I915_WRITE(DPLL(pipe), dpll);
4454 POSTING_READ(DPLL(pipe));
4455 udelay(150);
4456
4457 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4458 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4459
4460 dpll_md = (crtc->config.pixel_multiplier - 1)
4461 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4462 I915_WRITE(DPLL_MD(pipe), dpll_md);
4463 POSTING_READ(DPLL_MD(pipe));
4464
4465 if (crtc->config.has_dp_encoder)
4466 intel_dp_set_m_n(crtc);
4467
4468 mutex_unlock(&dev_priv->dpio_lock);
4469 }
4470
4471 static void i9xx_update_pll(struct intel_crtc *crtc,
4472 intel_clock_t *reduced_clock,
4473 int num_connectors)
4474 {
4475 struct drm_device *dev = crtc->base.dev;
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477 struct intel_encoder *encoder;
4478 int pipe = crtc->pipe;
4479 u32 dpll;
4480 bool is_sdvo;
4481 struct dpll *clock = &crtc->config.dpll;
4482
4483 i9xx_update_pll_dividers(crtc, reduced_clock);
4484
4485 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4486 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4487
4488 dpll = DPLL_VGA_MODE_DIS;
4489
4490 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4491 dpll |= DPLLB_MODE_LVDS;
4492 else
4493 dpll |= DPLLB_MODE_DAC_SERIAL;
4494
4495 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4496 dpll |= (crtc->config.pixel_multiplier - 1)
4497 << SDVO_MULTIPLIER_SHIFT_HIRES;
4498 }
4499
4500 if (is_sdvo)
4501 dpll |= DPLL_DVO_HIGH_SPEED;
4502
4503 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4504 dpll |= DPLL_DVO_HIGH_SPEED;
4505
4506 /* compute bitmask from p1 value */
4507 if (IS_PINEVIEW(dev))
4508 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4509 else {
4510 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4511 if (IS_G4X(dev) && reduced_clock)
4512 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4513 }
4514 switch (clock->p2) {
4515 case 5:
4516 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4517 break;
4518 case 7:
4519 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4520 break;
4521 case 10:
4522 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4523 break;
4524 case 14:
4525 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4526 break;
4527 }
4528 if (INTEL_INFO(dev)->gen >= 4)
4529 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4530
4531 if (crtc->config.sdvo_tv_clock)
4532 dpll |= PLL_REF_INPUT_TVCLKINBC;
4533 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4534 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4535 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4536 else
4537 dpll |= PLL_REF_INPUT_DREFCLK;
4538
4539 dpll |= DPLL_VCO_ENABLE;
4540 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4541 POSTING_READ(DPLL(pipe));
4542 udelay(150);
4543
4544 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4545 if (encoder->pre_pll_enable)
4546 encoder->pre_pll_enable(encoder);
4547
4548 if (crtc->config.has_dp_encoder)
4549 intel_dp_set_m_n(crtc);
4550
4551 I915_WRITE(DPLL(pipe), dpll);
4552
4553 /* Wait for the clocks to stabilize. */
4554 POSTING_READ(DPLL(pipe));
4555 udelay(150);
4556
4557 if (INTEL_INFO(dev)->gen >= 4) {
4558 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4559 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4560 I915_WRITE(DPLL_MD(pipe), dpll_md);
4561 } else {
4562 /* The pixel multiplier can only be updated once the
4563 * DPLL is enabled and the clocks are stable.
4564 *
4565 * So write it again.
4566 */
4567 I915_WRITE(DPLL(pipe), dpll);
4568 }
4569 }
4570
4571 static void i8xx_update_pll(struct intel_crtc *crtc,
4572 intel_clock_t *reduced_clock,
4573 int num_connectors)
4574 {
4575 struct drm_device *dev = crtc->base.dev;
4576 struct drm_i915_private *dev_priv = dev->dev_private;
4577 struct intel_encoder *encoder;
4578 int pipe = crtc->pipe;
4579 u32 dpll;
4580 struct dpll *clock = &crtc->config.dpll;
4581
4582 i9xx_update_pll_dividers(crtc, reduced_clock);
4583
4584 dpll = DPLL_VGA_MODE_DIS;
4585
4586 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4587 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4588 } else {
4589 if (clock->p1 == 2)
4590 dpll |= PLL_P1_DIVIDE_BY_TWO;
4591 else
4592 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4593 if (clock->p2 == 4)
4594 dpll |= PLL_P2_DIVIDE_BY_4;
4595 }
4596
4597 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4598 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4599 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4600 else
4601 dpll |= PLL_REF_INPUT_DREFCLK;
4602
4603 dpll |= DPLL_VCO_ENABLE;
4604 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4605 POSTING_READ(DPLL(pipe));
4606 udelay(150);
4607
4608 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4609 if (encoder->pre_pll_enable)
4610 encoder->pre_pll_enable(encoder);
4611
4612 I915_WRITE(DPLL(pipe), dpll);
4613
4614 /* Wait for the clocks to stabilize. */
4615 POSTING_READ(DPLL(pipe));
4616 udelay(150);
4617
4618 /* The pixel multiplier can only be updated once the
4619 * DPLL is enabled and the clocks are stable.
4620 *
4621 * So write it again.
4622 */
4623 I915_WRITE(DPLL(pipe), dpll);
4624 }
4625
4626 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4627 {
4628 struct drm_device *dev = intel_crtc->base.dev;
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 enum pipe pipe = intel_crtc->pipe;
4631 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4632 struct drm_display_mode *adjusted_mode =
4633 &intel_crtc->config.adjusted_mode;
4634 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4635 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4636
4637 /* We need to be careful not to changed the adjusted mode, for otherwise
4638 * the hw state checker will get angry at the mismatch. */
4639 crtc_vtotal = adjusted_mode->crtc_vtotal;
4640 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4641
4642 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4643 /* the chip adds 2 halflines automatically */
4644 crtc_vtotal -= 1;
4645 crtc_vblank_end -= 1;
4646 vsyncshift = adjusted_mode->crtc_hsync_start
4647 - adjusted_mode->crtc_htotal / 2;
4648 } else {
4649 vsyncshift = 0;
4650 }
4651
4652 if (INTEL_INFO(dev)->gen > 3)
4653 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4654
4655 I915_WRITE(HTOTAL(cpu_transcoder),
4656 (adjusted_mode->crtc_hdisplay - 1) |
4657 ((adjusted_mode->crtc_htotal - 1) << 16));
4658 I915_WRITE(HBLANK(cpu_transcoder),
4659 (adjusted_mode->crtc_hblank_start - 1) |
4660 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4661 I915_WRITE(HSYNC(cpu_transcoder),
4662 (adjusted_mode->crtc_hsync_start - 1) |
4663 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4664
4665 I915_WRITE(VTOTAL(cpu_transcoder),
4666 (adjusted_mode->crtc_vdisplay - 1) |
4667 ((crtc_vtotal - 1) << 16));
4668 I915_WRITE(VBLANK(cpu_transcoder),
4669 (adjusted_mode->crtc_vblank_start - 1) |
4670 ((crtc_vblank_end - 1) << 16));
4671 I915_WRITE(VSYNC(cpu_transcoder),
4672 (adjusted_mode->crtc_vsync_start - 1) |
4673 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4674
4675 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4676 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4677 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4678 * bits. */
4679 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4680 (pipe == PIPE_B || pipe == PIPE_C))
4681 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4682
4683 /* pipesrc controls the size that is scaled from, which should
4684 * always be the user's requested size.
4685 */
4686 I915_WRITE(PIPESRC(pipe),
4687 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4688 }
4689
4690 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4691 struct intel_crtc_config *pipe_config)
4692 {
4693 struct drm_device *dev = crtc->base.dev;
4694 struct drm_i915_private *dev_priv = dev->dev_private;
4695 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4696 uint32_t tmp;
4697
4698 tmp = I915_READ(HTOTAL(cpu_transcoder));
4699 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4700 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4701 tmp = I915_READ(HBLANK(cpu_transcoder));
4702 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4703 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4704 tmp = I915_READ(HSYNC(cpu_transcoder));
4705 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4706 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4707
4708 tmp = I915_READ(VTOTAL(cpu_transcoder));
4709 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4710 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4711 tmp = I915_READ(VBLANK(cpu_transcoder));
4712 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4713 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4714 tmp = I915_READ(VSYNC(cpu_transcoder));
4715 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4716 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4717
4718 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4719 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4720 pipe_config->adjusted_mode.crtc_vtotal += 1;
4721 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4722 }
4723
4724 tmp = I915_READ(PIPESRC(crtc->pipe));
4725 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4726 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4727 }
4728
4729 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4730 {
4731 struct drm_device *dev = intel_crtc->base.dev;
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4733 uint32_t pipeconf;
4734
4735 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4736
4737 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4738 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4739 * core speed.
4740 *
4741 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4742 * pipe == 0 check?
4743 */
4744 if (intel_crtc->config.requested_mode.clock >
4745 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4746 pipeconf |= PIPECONF_DOUBLE_WIDE;
4747 else
4748 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4749 }
4750
4751 /* only g4x and later have fancy bpc/dither controls */
4752 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4753 pipeconf &= ~(PIPECONF_BPC_MASK |
4754 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4755
4756 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4757 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4758 pipeconf |= PIPECONF_DITHER_EN |
4759 PIPECONF_DITHER_TYPE_SP;
4760
4761 switch (intel_crtc->config.pipe_bpp) {
4762 case 18:
4763 pipeconf |= PIPECONF_6BPC;
4764 break;
4765 case 24:
4766 pipeconf |= PIPECONF_8BPC;
4767 break;
4768 case 30:
4769 pipeconf |= PIPECONF_10BPC;
4770 break;
4771 default:
4772 /* Case prevented by intel_choose_pipe_bpp_dither. */
4773 BUG();
4774 }
4775 }
4776
4777 if (HAS_PIPE_CXSR(dev)) {
4778 if (intel_crtc->lowfreq_avail) {
4779 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4780 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4781 } else {
4782 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4783 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4784 }
4785 }
4786
4787 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4788 if (!IS_GEN2(dev) &&
4789 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4790 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4791 else
4792 pipeconf |= PIPECONF_PROGRESSIVE;
4793
4794 if (IS_VALLEYVIEW(dev)) {
4795 if (intel_crtc->config.limited_color_range)
4796 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4797 else
4798 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4799 }
4800
4801 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4802 POSTING_READ(PIPECONF(intel_crtc->pipe));
4803 }
4804
4805 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4806 int x, int y,
4807 struct drm_framebuffer *fb)
4808 {
4809 struct drm_device *dev = crtc->dev;
4810 struct drm_i915_private *dev_priv = dev->dev_private;
4811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4812 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4813 int pipe = intel_crtc->pipe;
4814 int plane = intel_crtc->plane;
4815 int refclk, num_connectors = 0;
4816 intel_clock_t clock, reduced_clock;
4817 u32 dspcntr;
4818 bool ok, has_reduced_clock = false;
4819 bool is_lvds = false;
4820 struct intel_encoder *encoder;
4821 const intel_limit_t *limit;
4822 int ret;
4823
4824 for_each_encoder_on_crtc(dev, crtc, encoder) {
4825 switch (encoder->type) {
4826 case INTEL_OUTPUT_LVDS:
4827 is_lvds = true;
4828 break;
4829 }
4830
4831 num_connectors++;
4832 }
4833
4834 refclk = i9xx_get_refclk(crtc, num_connectors);
4835
4836 /*
4837 * Returns a set of divisors for the desired target clock with the given
4838 * refclk, or FALSE. The returned values represent the clock equation:
4839 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4840 */
4841 limit = intel_limit(crtc, refclk);
4842 ok = dev_priv->display.find_dpll(limit, crtc,
4843 intel_crtc->config.port_clock,
4844 refclk, NULL, &clock);
4845 if (!ok && !intel_crtc->config.clock_set) {
4846 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4847 return -EINVAL;
4848 }
4849
4850 /* Ensure that the cursor is valid for the new mode before changing... */
4851 intel_crtc_update_cursor(crtc, true);
4852
4853 if (is_lvds && dev_priv->lvds_downclock_avail) {
4854 /*
4855 * Ensure we match the reduced clock's P to the target clock.
4856 * If the clocks don't match, we can't switch the display clock
4857 * by using the FP0/FP1. In such case we will disable the LVDS
4858 * downclock feature.
4859 */
4860 has_reduced_clock =
4861 dev_priv->display.find_dpll(limit, crtc,
4862 dev_priv->lvds_downclock,
4863 refclk, &clock,
4864 &reduced_clock);
4865 }
4866 /* Compat-code for transition, will disappear. */
4867 if (!intel_crtc->config.clock_set) {
4868 intel_crtc->config.dpll.n = clock.n;
4869 intel_crtc->config.dpll.m1 = clock.m1;
4870 intel_crtc->config.dpll.m2 = clock.m2;
4871 intel_crtc->config.dpll.p1 = clock.p1;
4872 intel_crtc->config.dpll.p2 = clock.p2;
4873 }
4874
4875 if (IS_GEN2(dev))
4876 i8xx_update_pll(intel_crtc,
4877 has_reduced_clock ? &reduced_clock : NULL,
4878 num_connectors);
4879 else if (IS_VALLEYVIEW(dev))
4880 vlv_update_pll(intel_crtc);
4881 else
4882 i9xx_update_pll(intel_crtc,
4883 has_reduced_clock ? &reduced_clock : NULL,
4884 num_connectors);
4885
4886 /* Set up the display plane register */
4887 dspcntr = DISPPLANE_GAMMA_ENABLE;
4888
4889 if (!IS_VALLEYVIEW(dev)) {
4890 if (pipe == 0)
4891 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4892 else
4893 dspcntr |= DISPPLANE_SEL_PIPE_B;
4894 }
4895
4896 intel_set_pipe_timings(intel_crtc);
4897
4898 /* pipesrc and dspsize control the size that is scaled from,
4899 * which should always be the user's requested size.
4900 */
4901 I915_WRITE(DSPSIZE(plane),
4902 ((mode->vdisplay - 1) << 16) |
4903 (mode->hdisplay - 1));
4904 I915_WRITE(DSPPOS(plane), 0);
4905
4906 i9xx_set_pipeconf(intel_crtc);
4907
4908 I915_WRITE(DSPCNTR(plane), dspcntr);
4909 POSTING_READ(DSPCNTR(plane));
4910
4911 ret = intel_pipe_set_base(crtc, x, y, fb);
4912
4913 intel_update_watermarks(dev);
4914
4915 return ret;
4916 }
4917
4918 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4919 struct intel_crtc_config *pipe_config)
4920 {
4921 struct drm_device *dev = crtc->base.dev;
4922 struct drm_i915_private *dev_priv = dev->dev_private;
4923 uint32_t tmp;
4924
4925 tmp = I915_READ(PFIT_CONTROL);
4926
4927 if (INTEL_INFO(dev)->gen < 4) {
4928 if (crtc->pipe != PIPE_B)
4929 return;
4930
4931 /* gen2/3 store dither state in pfit control, needs to match */
4932 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4933 } else {
4934 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4935 return;
4936 }
4937
4938 if (!(tmp & PFIT_ENABLE))
4939 return;
4940
4941 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4942 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4943 if (INTEL_INFO(dev)->gen < 5)
4944 pipe_config->gmch_pfit.lvds_border_bits =
4945 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4946 }
4947
4948 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4949 struct intel_crtc_config *pipe_config)
4950 {
4951 struct drm_device *dev = crtc->base.dev;
4952 struct drm_i915_private *dev_priv = dev->dev_private;
4953 uint32_t tmp;
4954
4955 pipe_config->cpu_transcoder = crtc->pipe;
4956
4957 tmp = I915_READ(PIPECONF(crtc->pipe));
4958 if (!(tmp & PIPECONF_ENABLE))
4959 return false;
4960
4961 intel_get_pipe_timings(crtc, pipe_config);
4962
4963 i9xx_get_pfit_config(crtc, pipe_config);
4964
4965 return true;
4966 }
4967
4968 static void ironlake_init_pch_refclk(struct drm_device *dev)
4969 {
4970 struct drm_i915_private *dev_priv = dev->dev_private;
4971 struct drm_mode_config *mode_config = &dev->mode_config;
4972 struct intel_encoder *encoder;
4973 u32 val, final;
4974 bool has_lvds = false;
4975 bool has_cpu_edp = false;
4976 bool has_panel = false;
4977 bool has_ck505 = false;
4978 bool can_ssc = false;
4979
4980 /* We need to take the global config into account */
4981 list_for_each_entry(encoder, &mode_config->encoder_list,
4982 base.head) {
4983 switch (encoder->type) {
4984 case INTEL_OUTPUT_LVDS:
4985 has_panel = true;
4986 has_lvds = true;
4987 break;
4988 case INTEL_OUTPUT_EDP:
4989 has_panel = true;
4990 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
4991 has_cpu_edp = true;
4992 break;
4993 }
4994 }
4995
4996 if (HAS_PCH_IBX(dev)) {
4997 has_ck505 = dev_priv->vbt.display_clock_mode;
4998 can_ssc = has_ck505;
4999 } else {
5000 has_ck505 = false;
5001 can_ssc = true;
5002 }
5003
5004 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5005 has_panel, has_lvds, has_ck505);
5006
5007 /* Ironlake: try to setup display ref clock before DPLL
5008 * enabling. This is only under driver's control after
5009 * PCH B stepping, previous chipset stepping should be
5010 * ignoring this setting.
5011 */
5012 val = I915_READ(PCH_DREF_CONTROL);
5013
5014 /* As we must carefully and slowly disable/enable each source in turn,
5015 * compute the final state we want first and check if we need to
5016 * make any changes at all.
5017 */
5018 final = val;
5019 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5020 if (has_ck505)
5021 final |= DREF_NONSPREAD_CK505_ENABLE;
5022 else
5023 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5024
5025 final &= ~DREF_SSC_SOURCE_MASK;
5026 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5027 final &= ~DREF_SSC1_ENABLE;
5028
5029 if (has_panel) {
5030 final |= DREF_SSC_SOURCE_ENABLE;
5031
5032 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5033 final |= DREF_SSC1_ENABLE;
5034
5035 if (has_cpu_edp) {
5036 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5037 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5038 else
5039 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5040 } else
5041 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5042 } else {
5043 final |= DREF_SSC_SOURCE_DISABLE;
5044 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5045 }
5046
5047 if (final == val)
5048 return;
5049
5050 /* Always enable nonspread source */
5051 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5052
5053 if (has_ck505)
5054 val |= DREF_NONSPREAD_CK505_ENABLE;
5055 else
5056 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5057
5058 if (has_panel) {
5059 val &= ~DREF_SSC_SOURCE_MASK;
5060 val |= DREF_SSC_SOURCE_ENABLE;
5061
5062 /* SSC must be turned on before enabling the CPU output */
5063 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5064 DRM_DEBUG_KMS("Using SSC on panel\n");
5065 val |= DREF_SSC1_ENABLE;
5066 } else
5067 val &= ~DREF_SSC1_ENABLE;
5068
5069 /* Get SSC going before enabling the outputs */
5070 I915_WRITE(PCH_DREF_CONTROL, val);
5071 POSTING_READ(PCH_DREF_CONTROL);
5072 udelay(200);
5073
5074 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5075
5076 /* Enable CPU source on CPU attached eDP */
5077 if (has_cpu_edp) {
5078 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5079 DRM_DEBUG_KMS("Using SSC on eDP\n");
5080 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5081 }
5082 else
5083 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5084 } else
5085 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5086
5087 I915_WRITE(PCH_DREF_CONTROL, val);
5088 POSTING_READ(PCH_DREF_CONTROL);
5089 udelay(200);
5090 } else {
5091 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5092
5093 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5094
5095 /* Turn off CPU output */
5096 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5097
5098 I915_WRITE(PCH_DREF_CONTROL, val);
5099 POSTING_READ(PCH_DREF_CONTROL);
5100 udelay(200);
5101
5102 /* Turn off the SSC source */
5103 val &= ~DREF_SSC_SOURCE_MASK;
5104 val |= DREF_SSC_SOURCE_DISABLE;
5105
5106 /* Turn off SSC1 */
5107 val &= ~DREF_SSC1_ENABLE;
5108
5109 I915_WRITE(PCH_DREF_CONTROL, val);
5110 POSTING_READ(PCH_DREF_CONTROL);
5111 udelay(200);
5112 }
5113
5114 BUG_ON(val != final);
5115 }
5116
5117 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5118 static void lpt_init_pch_refclk(struct drm_device *dev)
5119 {
5120 struct drm_i915_private *dev_priv = dev->dev_private;
5121 struct drm_mode_config *mode_config = &dev->mode_config;
5122 struct intel_encoder *encoder;
5123 bool has_vga = false;
5124 bool is_sdv = false;
5125 u32 tmp;
5126
5127 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5128 switch (encoder->type) {
5129 case INTEL_OUTPUT_ANALOG:
5130 has_vga = true;
5131 break;
5132 }
5133 }
5134
5135 if (!has_vga)
5136 return;
5137
5138 mutex_lock(&dev_priv->dpio_lock);
5139
5140 /* XXX: Rip out SDV support once Haswell ships for real. */
5141 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5142 is_sdv = true;
5143
5144 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5145 tmp &= ~SBI_SSCCTL_DISABLE;
5146 tmp |= SBI_SSCCTL_PATHALT;
5147 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5148
5149 udelay(24);
5150
5151 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5152 tmp &= ~SBI_SSCCTL_PATHALT;
5153 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5154
5155 if (!is_sdv) {
5156 tmp = I915_READ(SOUTH_CHICKEN2);
5157 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5158 I915_WRITE(SOUTH_CHICKEN2, tmp);
5159
5160 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5161 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5162 DRM_ERROR("FDI mPHY reset assert timeout\n");
5163
5164 tmp = I915_READ(SOUTH_CHICKEN2);
5165 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5166 I915_WRITE(SOUTH_CHICKEN2, tmp);
5167
5168 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5169 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5170 100))
5171 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5172 }
5173
5174 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5175 tmp &= ~(0xFF << 24);
5176 tmp |= (0x12 << 24);
5177 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5178
5179 if (is_sdv) {
5180 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5181 tmp |= 0x7FFF;
5182 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5183 }
5184
5185 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5186 tmp |= (1 << 11);
5187 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5188
5189 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5190 tmp |= (1 << 11);
5191 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5192
5193 if (is_sdv) {
5194 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5195 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5196 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5197
5198 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5199 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5200 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5201
5202 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5203 tmp |= (0x3F << 8);
5204 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5205
5206 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5207 tmp |= (0x3F << 8);
5208 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5209 }
5210
5211 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5212 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5213 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5214
5215 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5216 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5217 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5218
5219 if (!is_sdv) {
5220 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5221 tmp &= ~(7 << 13);
5222 tmp |= (5 << 13);
5223 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5224
5225 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5226 tmp &= ~(7 << 13);
5227 tmp |= (5 << 13);
5228 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5229 }
5230
5231 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5232 tmp &= ~0xFF;
5233 tmp |= 0x1C;
5234 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5235
5236 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5237 tmp &= ~0xFF;
5238 tmp |= 0x1C;
5239 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5240
5241 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5242 tmp &= ~(0xFF << 16);
5243 tmp |= (0x1C << 16);
5244 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5245
5246 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5247 tmp &= ~(0xFF << 16);
5248 tmp |= (0x1C << 16);
5249 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5250
5251 if (!is_sdv) {
5252 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5253 tmp |= (1 << 27);
5254 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5255
5256 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5257 tmp |= (1 << 27);
5258 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5259
5260 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5261 tmp &= ~(0xF << 28);
5262 tmp |= (4 << 28);
5263 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5264
5265 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5266 tmp &= ~(0xF << 28);
5267 tmp |= (4 << 28);
5268 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5269 }
5270
5271 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5272 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5273 tmp |= SBI_DBUFF0_ENABLE;
5274 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5275
5276 mutex_unlock(&dev_priv->dpio_lock);
5277 }
5278
5279 /*
5280 * Initialize reference clocks when the driver loads
5281 */
5282 void intel_init_pch_refclk(struct drm_device *dev)
5283 {
5284 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5285 ironlake_init_pch_refclk(dev);
5286 else if (HAS_PCH_LPT(dev))
5287 lpt_init_pch_refclk(dev);
5288 }
5289
5290 static int ironlake_get_refclk(struct drm_crtc *crtc)
5291 {
5292 struct drm_device *dev = crtc->dev;
5293 struct drm_i915_private *dev_priv = dev->dev_private;
5294 struct intel_encoder *encoder;
5295 int num_connectors = 0;
5296 bool is_lvds = false;
5297
5298 for_each_encoder_on_crtc(dev, crtc, encoder) {
5299 switch (encoder->type) {
5300 case INTEL_OUTPUT_LVDS:
5301 is_lvds = true;
5302 break;
5303 }
5304 num_connectors++;
5305 }
5306
5307 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5308 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5309 dev_priv->vbt.lvds_ssc_freq);
5310 return dev_priv->vbt.lvds_ssc_freq * 1000;
5311 }
5312
5313 return 120000;
5314 }
5315
5316 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5317 {
5318 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5320 int pipe = intel_crtc->pipe;
5321 uint32_t val;
5322
5323 val = I915_READ(PIPECONF(pipe));
5324
5325 val &= ~PIPECONF_BPC_MASK;
5326 switch (intel_crtc->config.pipe_bpp) {
5327 case 18:
5328 val |= PIPECONF_6BPC;
5329 break;
5330 case 24:
5331 val |= PIPECONF_8BPC;
5332 break;
5333 case 30:
5334 val |= PIPECONF_10BPC;
5335 break;
5336 case 36:
5337 val |= PIPECONF_12BPC;
5338 break;
5339 default:
5340 /* Case prevented by intel_choose_pipe_bpp_dither. */
5341 BUG();
5342 }
5343
5344 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5345 if (intel_crtc->config.dither)
5346 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5347
5348 val &= ~PIPECONF_INTERLACE_MASK;
5349 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5350 val |= PIPECONF_INTERLACED_ILK;
5351 else
5352 val |= PIPECONF_PROGRESSIVE;
5353
5354 if (intel_crtc->config.limited_color_range)
5355 val |= PIPECONF_COLOR_RANGE_SELECT;
5356 else
5357 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5358
5359 I915_WRITE(PIPECONF(pipe), val);
5360 POSTING_READ(PIPECONF(pipe));
5361 }
5362
5363 /*
5364 * Set up the pipe CSC unit.
5365 *
5366 * Currently only full range RGB to limited range RGB conversion
5367 * is supported, but eventually this should handle various
5368 * RGB<->YCbCr scenarios as well.
5369 */
5370 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5371 {
5372 struct drm_device *dev = crtc->dev;
5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5375 int pipe = intel_crtc->pipe;
5376 uint16_t coeff = 0x7800; /* 1.0 */
5377
5378 /*
5379 * TODO: Check what kind of values actually come out of the pipe
5380 * with these coeff/postoff values and adjust to get the best
5381 * accuracy. Perhaps we even need to take the bpc value into
5382 * consideration.
5383 */
5384
5385 if (intel_crtc->config.limited_color_range)
5386 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5387
5388 /*
5389 * GY/GU and RY/RU should be the other way around according
5390 * to BSpec, but reality doesn't agree. Just set them up in
5391 * a way that results in the correct picture.
5392 */
5393 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5394 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5395
5396 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5397 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5398
5399 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5400 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5401
5402 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5403 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5404 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5405
5406 if (INTEL_INFO(dev)->gen > 6) {
5407 uint16_t postoff = 0;
5408
5409 if (intel_crtc->config.limited_color_range)
5410 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5411
5412 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5413 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5414 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5415
5416 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5417 } else {
5418 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5419
5420 if (intel_crtc->config.limited_color_range)
5421 mode |= CSC_BLACK_SCREEN_OFFSET;
5422
5423 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5424 }
5425 }
5426
5427 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5428 {
5429 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5431 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5432 uint32_t val;
5433
5434 val = I915_READ(PIPECONF(cpu_transcoder));
5435
5436 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5437 if (intel_crtc->config.dither)
5438 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5439
5440 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5441 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5442 val |= PIPECONF_INTERLACED_ILK;
5443 else
5444 val |= PIPECONF_PROGRESSIVE;
5445
5446 I915_WRITE(PIPECONF(cpu_transcoder), val);
5447 POSTING_READ(PIPECONF(cpu_transcoder));
5448 }
5449
5450 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5451 intel_clock_t *clock,
5452 bool *has_reduced_clock,
5453 intel_clock_t *reduced_clock)
5454 {
5455 struct drm_device *dev = crtc->dev;
5456 struct drm_i915_private *dev_priv = dev->dev_private;
5457 struct intel_encoder *intel_encoder;
5458 int refclk;
5459 const intel_limit_t *limit;
5460 bool ret, is_lvds = false;
5461
5462 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5463 switch (intel_encoder->type) {
5464 case INTEL_OUTPUT_LVDS:
5465 is_lvds = true;
5466 break;
5467 }
5468 }
5469
5470 refclk = ironlake_get_refclk(crtc);
5471
5472 /*
5473 * Returns a set of divisors for the desired target clock with the given
5474 * refclk, or FALSE. The returned values represent the clock equation:
5475 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5476 */
5477 limit = intel_limit(crtc, refclk);
5478 ret = dev_priv->display.find_dpll(limit, crtc,
5479 to_intel_crtc(crtc)->config.port_clock,
5480 refclk, NULL, clock);
5481 if (!ret)
5482 return false;
5483
5484 if (is_lvds && dev_priv->lvds_downclock_avail) {
5485 /*
5486 * Ensure we match the reduced clock's P to the target clock.
5487 * If the clocks don't match, we can't switch the display clock
5488 * by using the FP0/FP1. In such case we will disable the LVDS
5489 * downclock feature.
5490 */
5491 *has_reduced_clock =
5492 dev_priv->display.find_dpll(limit, crtc,
5493 dev_priv->lvds_downclock,
5494 refclk, clock,
5495 reduced_clock);
5496 }
5497
5498 return true;
5499 }
5500
5501 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5502 {
5503 struct drm_i915_private *dev_priv = dev->dev_private;
5504 uint32_t temp;
5505
5506 temp = I915_READ(SOUTH_CHICKEN1);
5507 if (temp & FDI_BC_BIFURCATION_SELECT)
5508 return;
5509
5510 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5511 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5512
5513 temp |= FDI_BC_BIFURCATION_SELECT;
5514 DRM_DEBUG_KMS("enabling fdi C rx\n");
5515 I915_WRITE(SOUTH_CHICKEN1, temp);
5516 POSTING_READ(SOUTH_CHICKEN1);
5517 }
5518
5519 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5520 {
5521 struct drm_device *dev = intel_crtc->base.dev;
5522 struct drm_i915_private *dev_priv = dev->dev_private;
5523
5524 switch (intel_crtc->pipe) {
5525 case PIPE_A:
5526 break;
5527 case PIPE_B:
5528 if (intel_crtc->config.fdi_lanes > 2)
5529 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5530 else
5531 cpt_enable_fdi_bc_bifurcation(dev);
5532
5533 break;
5534 case PIPE_C:
5535 cpt_enable_fdi_bc_bifurcation(dev);
5536
5537 break;
5538 default:
5539 BUG();
5540 }
5541 }
5542
5543 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5544 {
5545 /*
5546 * Account for spread spectrum to avoid
5547 * oversubscribing the link. Max center spread
5548 * is 2.5%; use 5% for safety's sake.
5549 */
5550 u32 bps = target_clock * bpp * 21 / 20;
5551 return bps / (link_bw * 8) + 1;
5552 }
5553
5554 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5555 {
5556 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5557 }
5558
5559 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5560 u32 *fp,
5561 intel_clock_t *reduced_clock, u32 *fp2)
5562 {
5563 struct drm_crtc *crtc = &intel_crtc->base;
5564 struct drm_device *dev = crtc->dev;
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566 struct intel_encoder *intel_encoder;
5567 uint32_t dpll;
5568 int factor, num_connectors = 0;
5569 bool is_lvds = false, is_sdvo = false;
5570
5571 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5572 switch (intel_encoder->type) {
5573 case INTEL_OUTPUT_LVDS:
5574 is_lvds = true;
5575 break;
5576 case INTEL_OUTPUT_SDVO:
5577 case INTEL_OUTPUT_HDMI:
5578 is_sdvo = true;
5579 break;
5580 }
5581
5582 num_connectors++;
5583 }
5584
5585 /* Enable autotuning of the PLL clock (if permissible) */
5586 factor = 21;
5587 if (is_lvds) {
5588 if ((intel_panel_use_ssc(dev_priv) &&
5589 dev_priv->vbt.lvds_ssc_freq == 100) ||
5590 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5591 factor = 25;
5592 } else if (intel_crtc->config.sdvo_tv_clock)
5593 factor = 20;
5594
5595 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5596 *fp |= FP_CB_TUNE;
5597
5598 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5599 *fp2 |= FP_CB_TUNE;
5600
5601 dpll = 0;
5602
5603 if (is_lvds)
5604 dpll |= DPLLB_MODE_LVDS;
5605 else
5606 dpll |= DPLLB_MODE_DAC_SERIAL;
5607
5608 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5609 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5610
5611 if (is_sdvo)
5612 dpll |= DPLL_DVO_HIGH_SPEED;
5613 if (intel_crtc->config.has_dp_encoder)
5614 dpll |= DPLL_DVO_HIGH_SPEED;
5615
5616 /* compute bitmask from p1 value */
5617 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5618 /* also FPA1 */
5619 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5620
5621 switch (intel_crtc->config.dpll.p2) {
5622 case 5:
5623 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5624 break;
5625 case 7:
5626 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5627 break;
5628 case 10:
5629 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5630 break;
5631 case 14:
5632 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5633 break;
5634 }
5635
5636 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5637 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5638 else
5639 dpll |= PLL_REF_INPUT_DREFCLK;
5640
5641 return dpll;
5642 }
5643
5644 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5645 int x, int y,
5646 struct drm_framebuffer *fb)
5647 {
5648 struct drm_device *dev = crtc->dev;
5649 struct drm_i915_private *dev_priv = dev->dev_private;
5650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5651 int pipe = intel_crtc->pipe;
5652 int plane = intel_crtc->plane;
5653 int num_connectors = 0;
5654 intel_clock_t clock, reduced_clock;
5655 u32 dpll = 0, fp = 0, fp2 = 0;
5656 bool ok, has_reduced_clock = false;
5657 bool is_lvds = false;
5658 struct intel_encoder *encoder;
5659 int ret;
5660
5661 for_each_encoder_on_crtc(dev, crtc, encoder) {
5662 switch (encoder->type) {
5663 case INTEL_OUTPUT_LVDS:
5664 is_lvds = true;
5665 break;
5666 }
5667
5668 num_connectors++;
5669 }
5670
5671 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5672 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5673
5674 ok = ironlake_compute_clocks(crtc, &clock,
5675 &has_reduced_clock, &reduced_clock);
5676 if (!ok && !intel_crtc->config.clock_set) {
5677 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5678 return -EINVAL;
5679 }
5680 /* Compat-code for transition, will disappear. */
5681 if (!intel_crtc->config.clock_set) {
5682 intel_crtc->config.dpll.n = clock.n;
5683 intel_crtc->config.dpll.m1 = clock.m1;
5684 intel_crtc->config.dpll.m2 = clock.m2;
5685 intel_crtc->config.dpll.p1 = clock.p1;
5686 intel_crtc->config.dpll.p2 = clock.p2;
5687 }
5688
5689 /* Ensure that the cursor is valid for the new mode before changing... */
5690 intel_crtc_update_cursor(crtc, true);
5691
5692 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5693 if (intel_crtc->config.has_pch_encoder) {
5694 struct intel_pch_pll *pll;
5695
5696 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5697 if (has_reduced_clock)
5698 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5699
5700 dpll = ironlake_compute_dpll(intel_crtc,
5701 &fp, &reduced_clock,
5702 has_reduced_clock ? &fp2 : NULL);
5703
5704 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5705 if (pll == NULL) {
5706 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5707 pipe_name(pipe));
5708 return -EINVAL;
5709 }
5710 } else
5711 intel_put_pch_pll(intel_crtc);
5712
5713 if (intel_crtc->config.has_dp_encoder)
5714 intel_dp_set_m_n(intel_crtc);
5715
5716 for_each_encoder_on_crtc(dev, crtc, encoder)
5717 if (encoder->pre_pll_enable)
5718 encoder->pre_pll_enable(encoder);
5719
5720 if (intel_crtc->pch_pll) {
5721 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5722
5723 /* Wait for the clocks to stabilize. */
5724 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5725 udelay(150);
5726
5727 /* The pixel multiplier can only be updated once the
5728 * DPLL is enabled and the clocks are stable.
5729 *
5730 * So write it again.
5731 */
5732 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5733 }
5734
5735 intel_crtc->lowfreq_avail = false;
5736 if (intel_crtc->pch_pll) {
5737 if (is_lvds && has_reduced_clock && i915_powersave) {
5738 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5739 intel_crtc->lowfreq_avail = true;
5740 } else {
5741 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5742 }
5743 }
5744
5745 intel_set_pipe_timings(intel_crtc);
5746
5747 if (intel_crtc->config.has_pch_encoder) {
5748 intel_cpu_transcoder_set_m_n(intel_crtc,
5749 &intel_crtc->config.fdi_m_n);
5750 }
5751
5752 if (IS_IVYBRIDGE(dev))
5753 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5754
5755 ironlake_set_pipeconf(crtc);
5756
5757 /* Set up the display plane register */
5758 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5759 POSTING_READ(DSPCNTR(plane));
5760
5761 ret = intel_pipe_set_base(crtc, x, y, fb);
5762
5763 intel_update_watermarks(dev);
5764
5765 return ret;
5766 }
5767
5768 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5769 struct intel_crtc_config *pipe_config)
5770 {
5771 struct drm_device *dev = crtc->base.dev;
5772 struct drm_i915_private *dev_priv = dev->dev_private;
5773 enum transcoder transcoder = pipe_config->cpu_transcoder;
5774
5775 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5776 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5777 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5778 & ~TU_SIZE_MASK;
5779 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5780 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5781 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5782 }
5783
5784 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5785 struct intel_crtc_config *pipe_config)
5786 {
5787 struct drm_device *dev = crtc->base.dev;
5788 struct drm_i915_private *dev_priv = dev->dev_private;
5789 uint32_t tmp;
5790
5791 tmp = I915_READ(PF_CTL(crtc->pipe));
5792
5793 if (tmp & PF_ENABLE) {
5794 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5795 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5796
5797 /* We currently do not free assignements of panel fitters on
5798 * ivb/hsw (since we don't use the higher upscaling modes which
5799 * differentiates them) so just WARN about this case for now. */
5800 if (IS_GEN7(dev)) {
5801 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5802 PF_PIPE_SEL_IVB(crtc->pipe));
5803 }
5804 }
5805 }
5806
5807 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5808 struct intel_crtc_config *pipe_config)
5809 {
5810 struct drm_device *dev = crtc->base.dev;
5811 struct drm_i915_private *dev_priv = dev->dev_private;
5812 uint32_t tmp;
5813
5814 pipe_config->cpu_transcoder = crtc->pipe;
5815
5816 tmp = I915_READ(PIPECONF(crtc->pipe));
5817 if (!(tmp & PIPECONF_ENABLE))
5818 return false;
5819
5820 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5821 pipe_config->has_pch_encoder = true;
5822
5823 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5824 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5825 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5826
5827 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5828 }
5829
5830 intel_get_pipe_timings(crtc, pipe_config);
5831
5832 ironlake_get_pfit_config(crtc, pipe_config);
5833
5834 return true;
5835 }
5836
5837 static void haswell_modeset_global_resources(struct drm_device *dev)
5838 {
5839 bool enable = false;
5840 struct intel_crtc *crtc;
5841
5842 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5843 if (!crtc->base.enabled)
5844 continue;
5845
5846 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5847 crtc->config.cpu_transcoder != TRANSCODER_EDP)
5848 enable = true;
5849 }
5850
5851 intel_set_power_well(dev, enable);
5852 }
5853
5854 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5855 int x, int y,
5856 struct drm_framebuffer *fb)
5857 {
5858 struct drm_device *dev = crtc->dev;
5859 struct drm_i915_private *dev_priv = dev->dev_private;
5860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5861 int plane = intel_crtc->plane;
5862 int ret;
5863
5864 if (!intel_ddi_pll_mode_set(crtc))
5865 return -EINVAL;
5866
5867 /* Ensure that the cursor is valid for the new mode before changing... */
5868 intel_crtc_update_cursor(crtc, true);
5869
5870 if (intel_crtc->config.has_dp_encoder)
5871 intel_dp_set_m_n(intel_crtc);
5872
5873 intel_crtc->lowfreq_avail = false;
5874
5875 intel_set_pipe_timings(intel_crtc);
5876
5877 if (intel_crtc->config.has_pch_encoder) {
5878 intel_cpu_transcoder_set_m_n(intel_crtc,
5879 &intel_crtc->config.fdi_m_n);
5880 }
5881
5882 haswell_set_pipeconf(crtc);
5883
5884 intel_set_pipe_csc(crtc);
5885
5886 /* Set up the display plane register */
5887 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5888 POSTING_READ(DSPCNTR(plane));
5889
5890 ret = intel_pipe_set_base(crtc, x, y, fb);
5891
5892 intel_update_watermarks(dev);
5893
5894 return ret;
5895 }
5896
5897 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5898 struct intel_crtc_config *pipe_config)
5899 {
5900 struct drm_device *dev = crtc->base.dev;
5901 struct drm_i915_private *dev_priv = dev->dev_private;
5902 enum intel_display_power_domain pfit_domain;
5903 uint32_t tmp;
5904
5905 pipe_config->cpu_transcoder = crtc->pipe;
5906 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5907 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5908 enum pipe trans_edp_pipe;
5909 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5910 default:
5911 WARN(1, "unknown pipe linked to edp transcoder\n");
5912 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5913 case TRANS_DDI_EDP_INPUT_A_ON:
5914 trans_edp_pipe = PIPE_A;
5915 break;
5916 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5917 trans_edp_pipe = PIPE_B;
5918 break;
5919 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5920 trans_edp_pipe = PIPE_C;
5921 break;
5922 }
5923
5924 if (trans_edp_pipe == crtc->pipe)
5925 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5926 }
5927
5928 if (!intel_display_power_enabled(dev,
5929 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5930 return false;
5931
5932 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5933 if (!(tmp & PIPECONF_ENABLE))
5934 return false;
5935
5936 /*
5937 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5938 * DDI E. So just check whether this pipe is wired to DDI E and whether
5939 * the PCH transcoder is on.
5940 */
5941 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5942 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5943 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5944 pipe_config->has_pch_encoder = true;
5945
5946 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5947 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5948 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5949
5950 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5951 }
5952
5953 intel_get_pipe_timings(crtc, pipe_config);
5954
5955 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5956 if (intel_display_power_enabled(dev, pfit_domain))
5957 ironlake_get_pfit_config(crtc, pipe_config);
5958
5959 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5960 (I915_READ(IPS_CTL) & IPS_ENABLE);
5961
5962 return true;
5963 }
5964
5965 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5966 int x, int y,
5967 struct drm_framebuffer *fb)
5968 {
5969 struct drm_device *dev = crtc->dev;
5970 struct drm_i915_private *dev_priv = dev->dev_private;
5971 struct drm_encoder_helper_funcs *encoder_funcs;
5972 struct intel_encoder *encoder;
5973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5974 struct drm_display_mode *adjusted_mode =
5975 &intel_crtc->config.adjusted_mode;
5976 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5977 int pipe = intel_crtc->pipe;
5978 int ret;
5979
5980 drm_vblank_pre_modeset(dev, pipe);
5981
5982 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5983
5984 drm_vblank_post_modeset(dev, pipe);
5985
5986 if (ret != 0)
5987 return ret;
5988
5989 for_each_encoder_on_crtc(dev, crtc, encoder) {
5990 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5991 encoder->base.base.id,
5992 drm_get_encoder_name(&encoder->base),
5993 mode->base.id, mode->name);
5994 if (encoder->mode_set) {
5995 encoder->mode_set(encoder);
5996 } else {
5997 encoder_funcs = encoder->base.helper_private;
5998 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5999 }
6000 }
6001
6002 return 0;
6003 }
6004
6005 static bool intel_eld_uptodate(struct drm_connector *connector,
6006 int reg_eldv, uint32_t bits_eldv,
6007 int reg_elda, uint32_t bits_elda,
6008 int reg_edid)
6009 {
6010 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6011 uint8_t *eld = connector->eld;
6012 uint32_t i;
6013
6014 i = I915_READ(reg_eldv);
6015 i &= bits_eldv;
6016
6017 if (!eld[0])
6018 return !i;
6019
6020 if (!i)
6021 return false;
6022
6023 i = I915_READ(reg_elda);
6024 i &= ~bits_elda;
6025 I915_WRITE(reg_elda, i);
6026
6027 for (i = 0; i < eld[2]; i++)
6028 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6029 return false;
6030
6031 return true;
6032 }
6033
6034 static void g4x_write_eld(struct drm_connector *connector,
6035 struct drm_crtc *crtc)
6036 {
6037 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6038 uint8_t *eld = connector->eld;
6039 uint32_t eldv;
6040 uint32_t len;
6041 uint32_t i;
6042
6043 i = I915_READ(G4X_AUD_VID_DID);
6044
6045 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6046 eldv = G4X_ELDV_DEVCL_DEVBLC;
6047 else
6048 eldv = G4X_ELDV_DEVCTG;
6049
6050 if (intel_eld_uptodate(connector,
6051 G4X_AUD_CNTL_ST, eldv,
6052 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6053 G4X_HDMIW_HDMIEDID))
6054 return;
6055
6056 i = I915_READ(G4X_AUD_CNTL_ST);
6057 i &= ~(eldv | G4X_ELD_ADDR);
6058 len = (i >> 9) & 0x1f; /* ELD buffer size */
6059 I915_WRITE(G4X_AUD_CNTL_ST, i);
6060
6061 if (!eld[0])
6062 return;
6063
6064 len = min_t(uint8_t, eld[2], len);
6065 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6066 for (i = 0; i < len; i++)
6067 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6068
6069 i = I915_READ(G4X_AUD_CNTL_ST);
6070 i |= eldv;
6071 I915_WRITE(G4X_AUD_CNTL_ST, i);
6072 }
6073
6074 static void haswell_write_eld(struct drm_connector *connector,
6075 struct drm_crtc *crtc)
6076 {
6077 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6078 uint8_t *eld = connector->eld;
6079 struct drm_device *dev = crtc->dev;
6080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6081 uint32_t eldv;
6082 uint32_t i;
6083 int len;
6084 int pipe = to_intel_crtc(crtc)->pipe;
6085 int tmp;
6086
6087 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6088 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6089 int aud_config = HSW_AUD_CFG(pipe);
6090 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6091
6092
6093 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6094
6095 /* Audio output enable */
6096 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6097 tmp = I915_READ(aud_cntrl_st2);
6098 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6099 I915_WRITE(aud_cntrl_st2, tmp);
6100
6101 /* Wait for 1 vertical blank */
6102 intel_wait_for_vblank(dev, pipe);
6103
6104 /* Set ELD valid state */
6105 tmp = I915_READ(aud_cntrl_st2);
6106 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6107 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6108 I915_WRITE(aud_cntrl_st2, tmp);
6109 tmp = I915_READ(aud_cntrl_st2);
6110 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6111
6112 /* Enable HDMI mode */
6113 tmp = I915_READ(aud_config);
6114 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6115 /* clear N_programing_enable and N_value_index */
6116 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6117 I915_WRITE(aud_config, tmp);
6118
6119 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6120
6121 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6122 intel_crtc->eld_vld = true;
6123
6124 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6125 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6126 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6127 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6128 } else
6129 I915_WRITE(aud_config, 0);
6130
6131 if (intel_eld_uptodate(connector,
6132 aud_cntrl_st2, eldv,
6133 aud_cntl_st, IBX_ELD_ADDRESS,
6134 hdmiw_hdmiedid))
6135 return;
6136
6137 i = I915_READ(aud_cntrl_st2);
6138 i &= ~eldv;
6139 I915_WRITE(aud_cntrl_st2, i);
6140
6141 if (!eld[0])
6142 return;
6143
6144 i = I915_READ(aud_cntl_st);
6145 i &= ~IBX_ELD_ADDRESS;
6146 I915_WRITE(aud_cntl_st, i);
6147 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6148 DRM_DEBUG_DRIVER("port num:%d\n", i);
6149
6150 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6151 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6152 for (i = 0; i < len; i++)
6153 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6154
6155 i = I915_READ(aud_cntrl_st2);
6156 i |= eldv;
6157 I915_WRITE(aud_cntrl_st2, i);
6158
6159 }
6160
6161 static void ironlake_write_eld(struct drm_connector *connector,
6162 struct drm_crtc *crtc)
6163 {
6164 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6165 uint8_t *eld = connector->eld;
6166 uint32_t eldv;
6167 uint32_t i;
6168 int len;
6169 int hdmiw_hdmiedid;
6170 int aud_config;
6171 int aud_cntl_st;
6172 int aud_cntrl_st2;
6173 int pipe = to_intel_crtc(crtc)->pipe;
6174
6175 if (HAS_PCH_IBX(connector->dev)) {
6176 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6177 aud_config = IBX_AUD_CFG(pipe);
6178 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6179 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6180 } else {
6181 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6182 aud_config = CPT_AUD_CFG(pipe);
6183 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6184 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6185 }
6186
6187 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6188
6189 i = I915_READ(aud_cntl_st);
6190 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6191 if (!i) {
6192 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6193 /* operate blindly on all ports */
6194 eldv = IBX_ELD_VALIDB;
6195 eldv |= IBX_ELD_VALIDB << 4;
6196 eldv |= IBX_ELD_VALIDB << 8;
6197 } else {
6198 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6199 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6200 }
6201
6202 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6203 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6204 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6205 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6206 } else
6207 I915_WRITE(aud_config, 0);
6208
6209 if (intel_eld_uptodate(connector,
6210 aud_cntrl_st2, eldv,
6211 aud_cntl_st, IBX_ELD_ADDRESS,
6212 hdmiw_hdmiedid))
6213 return;
6214
6215 i = I915_READ(aud_cntrl_st2);
6216 i &= ~eldv;
6217 I915_WRITE(aud_cntrl_st2, i);
6218
6219 if (!eld[0])
6220 return;
6221
6222 i = I915_READ(aud_cntl_st);
6223 i &= ~IBX_ELD_ADDRESS;
6224 I915_WRITE(aud_cntl_st, i);
6225
6226 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6227 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6228 for (i = 0; i < len; i++)
6229 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6230
6231 i = I915_READ(aud_cntrl_st2);
6232 i |= eldv;
6233 I915_WRITE(aud_cntrl_st2, i);
6234 }
6235
6236 void intel_write_eld(struct drm_encoder *encoder,
6237 struct drm_display_mode *mode)
6238 {
6239 struct drm_crtc *crtc = encoder->crtc;
6240 struct drm_connector *connector;
6241 struct drm_device *dev = encoder->dev;
6242 struct drm_i915_private *dev_priv = dev->dev_private;
6243
6244 connector = drm_select_eld(encoder, mode);
6245 if (!connector)
6246 return;
6247
6248 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6249 connector->base.id,
6250 drm_get_connector_name(connector),
6251 connector->encoder->base.id,
6252 drm_get_encoder_name(connector->encoder));
6253
6254 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6255
6256 if (dev_priv->display.write_eld)
6257 dev_priv->display.write_eld(connector, crtc);
6258 }
6259
6260 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6261 void intel_crtc_load_lut(struct drm_crtc *crtc)
6262 {
6263 struct drm_device *dev = crtc->dev;
6264 struct drm_i915_private *dev_priv = dev->dev_private;
6265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6266 enum pipe pipe = intel_crtc->pipe;
6267 int palreg = PALETTE(pipe);
6268 int i;
6269 bool reenable_ips = false;
6270
6271 /* The clocks have to be on to load the palette. */
6272 if (!crtc->enabled || !intel_crtc->active)
6273 return;
6274
6275 /* use legacy palette for Ironlake */
6276 if (HAS_PCH_SPLIT(dev))
6277 palreg = LGC_PALETTE(pipe);
6278
6279 /* Workaround : Do not read or write the pipe palette/gamma data while
6280 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6281 */
6282 if (intel_crtc->config.ips_enabled &&
6283 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6284 GAMMA_MODE_MODE_SPLIT)) {
6285 hsw_disable_ips(intel_crtc);
6286 reenable_ips = true;
6287 }
6288
6289 for (i = 0; i < 256; i++) {
6290 I915_WRITE(palreg + 4 * i,
6291 (intel_crtc->lut_r[i] << 16) |
6292 (intel_crtc->lut_g[i] << 8) |
6293 intel_crtc->lut_b[i]);
6294 }
6295
6296 if (reenable_ips)
6297 hsw_enable_ips(intel_crtc);
6298 }
6299
6300 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6301 {
6302 struct drm_device *dev = crtc->dev;
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6305 bool visible = base != 0;
6306 u32 cntl;
6307
6308 if (intel_crtc->cursor_visible == visible)
6309 return;
6310
6311 cntl = I915_READ(_CURACNTR);
6312 if (visible) {
6313 /* On these chipsets we can only modify the base whilst
6314 * the cursor is disabled.
6315 */
6316 I915_WRITE(_CURABASE, base);
6317
6318 cntl &= ~(CURSOR_FORMAT_MASK);
6319 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6320 cntl |= CURSOR_ENABLE |
6321 CURSOR_GAMMA_ENABLE |
6322 CURSOR_FORMAT_ARGB;
6323 } else
6324 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6325 I915_WRITE(_CURACNTR, cntl);
6326
6327 intel_crtc->cursor_visible = visible;
6328 }
6329
6330 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6331 {
6332 struct drm_device *dev = crtc->dev;
6333 struct drm_i915_private *dev_priv = dev->dev_private;
6334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6335 int pipe = intel_crtc->pipe;
6336 bool visible = base != 0;
6337
6338 if (intel_crtc->cursor_visible != visible) {
6339 uint32_t cntl = I915_READ(CURCNTR(pipe));
6340 if (base) {
6341 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6342 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6343 cntl |= pipe << 28; /* Connect to correct pipe */
6344 } else {
6345 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6346 cntl |= CURSOR_MODE_DISABLE;
6347 }
6348 I915_WRITE(CURCNTR(pipe), cntl);
6349
6350 intel_crtc->cursor_visible = visible;
6351 }
6352 /* and commit changes on next vblank */
6353 I915_WRITE(CURBASE(pipe), base);
6354 }
6355
6356 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6357 {
6358 struct drm_device *dev = crtc->dev;
6359 struct drm_i915_private *dev_priv = dev->dev_private;
6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361 int pipe = intel_crtc->pipe;
6362 bool visible = base != 0;
6363
6364 if (intel_crtc->cursor_visible != visible) {
6365 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6366 if (base) {
6367 cntl &= ~CURSOR_MODE;
6368 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6369 } else {
6370 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6371 cntl |= CURSOR_MODE_DISABLE;
6372 }
6373 if (IS_HASWELL(dev))
6374 cntl |= CURSOR_PIPE_CSC_ENABLE;
6375 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6376
6377 intel_crtc->cursor_visible = visible;
6378 }
6379 /* and commit changes on next vblank */
6380 I915_WRITE(CURBASE_IVB(pipe), base);
6381 }
6382
6383 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6384 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6385 bool on)
6386 {
6387 struct drm_device *dev = crtc->dev;
6388 struct drm_i915_private *dev_priv = dev->dev_private;
6389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6390 int pipe = intel_crtc->pipe;
6391 int x = intel_crtc->cursor_x;
6392 int y = intel_crtc->cursor_y;
6393 u32 base, pos;
6394 bool visible;
6395
6396 pos = 0;
6397
6398 if (on && crtc->enabled && crtc->fb) {
6399 base = intel_crtc->cursor_addr;
6400 if (x > (int) crtc->fb->width)
6401 base = 0;
6402
6403 if (y > (int) crtc->fb->height)
6404 base = 0;
6405 } else
6406 base = 0;
6407
6408 if (x < 0) {
6409 if (x + intel_crtc->cursor_width < 0)
6410 base = 0;
6411
6412 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6413 x = -x;
6414 }
6415 pos |= x << CURSOR_X_SHIFT;
6416
6417 if (y < 0) {
6418 if (y + intel_crtc->cursor_height < 0)
6419 base = 0;
6420
6421 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6422 y = -y;
6423 }
6424 pos |= y << CURSOR_Y_SHIFT;
6425
6426 visible = base != 0;
6427 if (!visible && !intel_crtc->cursor_visible)
6428 return;
6429
6430 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6431 I915_WRITE(CURPOS_IVB(pipe), pos);
6432 ivb_update_cursor(crtc, base);
6433 } else {
6434 I915_WRITE(CURPOS(pipe), pos);
6435 if (IS_845G(dev) || IS_I865G(dev))
6436 i845_update_cursor(crtc, base);
6437 else
6438 i9xx_update_cursor(crtc, base);
6439 }
6440 }
6441
6442 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6443 struct drm_file *file,
6444 uint32_t handle,
6445 uint32_t width, uint32_t height)
6446 {
6447 struct drm_device *dev = crtc->dev;
6448 struct drm_i915_private *dev_priv = dev->dev_private;
6449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6450 struct drm_i915_gem_object *obj;
6451 uint32_t addr;
6452 int ret;
6453
6454 /* if we want to turn off the cursor ignore width and height */
6455 if (!handle) {
6456 DRM_DEBUG_KMS("cursor off\n");
6457 addr = 0;
6458 obj = NULL;
6459 mutex_lock(&dev->struct_mutex);
6460 goto finish;
6461 }
6462
6463 /* Currently we only support 64x64 cursors */
6464 if (width != 64 || height != 64) {
6465 DRM_ERROR("we currently only support 64x64 cursors\n");
6466 return -EINVAL;
6467 }
6468
6469 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6470 if (&obj->base == NULL)
6471 return -ENOENT;
6472
6473 if (obj->base.size < width * height * 4) {
6474 DRM_ERROR("buffer is to small\n");
6475 ret = -ENOMEM;
6476 goto fail;
6477 }
6478
6479 /* we only need to pin inside GTT if cursor is non-phy */
6480 mutex_lock(&dev->struct_mutex);
6481 if (!dev_priv->info->cursor_needs_physical) {
6482 unsigned alignment;
6483
6484 if (obj->tiling_mode) {
6485 DRM_ERROR("cursor cannot be tiled\n");
6486 ret = -EINVAL;
6487 goto fail_locked;
6488 }
6489
6490 /* Note that the w/a also requires 2 PTE of padding following
6491 * the bo. We currently fill all unused PTE with the shadow
6492 * page and so we should always have valid PTE following the
6493 * cursor preventing the VT-d warning.
6494 */
6495 alignment = 0;
6496 if (need_vtd_wa(dev))
6497 alignment = 64*1024;
6498
6499 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6500 if (ret) {
6501 DRM_ERROR("failed to move cursor bo into the GTT\n");
6502 goto fail_locked;
6503 }
6504
6505 ret = i915_gem_object_put_fence(obj);
6506 if (ret) {
6507 DRM_ERROR("failed to release fence for cursor");
6508 goto fail_unpin;
6509 }
6510
6511 addr = obj->gtt_offset;
6512 } else {
6513 int align = IS_I830(dev) ? 16 * 1024 : 256;
6514 ret = i915_gem_attach_phys_object(dev, obj,
6515 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6516 align);
6517 if (ret) {
6518 DRM_ERROR("failed to attach phys object\n");
6519 goto fail_locked;
6520 }
6521 addr = obj->phys_obj->handle->busaddr;
6522 }
6523
6524 if (IS_GEN2(dev))
6525 I915_WRITE(CURSIZE, (height << 12) | width);
6526
6527 finish:
6528 if (intel_crtc->cursor_bo) {
6529 if (dev_priv->info->cursor_needs_physical) {
6530 if (intel_crtc->cursor_bo != obj)
6531 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6532 } else
6533 i915_gem_object_unpin(intel_crtc->cursor_bo);
6534 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6535 }
6536
6537 mutex_unlock(&dev->struct_mutex);
6538
6539 intel_crtc->cursor_addr = addr;
6540 intel_crtc->cursor_bo = obj;
6541 intel_crtc->cursor_width = width;
6542 intel_crtc->cursor_height = height;
6543
6544 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6545
6546 return 0;
6547 fail_unpin:
6548 i915_gem_object_unpin(obj);
6549 fail_locked:
6550 mutex_unlock(&dev->struct_mutex);
6551 fail:
6552 drm_gem_object_unreference_unlocked(&obj->base);
6553 return ret;
6554 }
6555
6556 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6557 {
6558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6559
6560 intel_crtc->cursor_x = x;
6561 intel_crtc->cursor_y = y;
6562
6563 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6564
6565 return 0;
6566 }
6567
6568 /** Sets the color ramps on behalf of RandR */
6569 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6570 u16 blue, int regno)
6571 {
6572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6573
6574 intel_crtc->lut_r[regno] = red >> 8;
6575 intel_crtc->lut_g[regno] = green >> 8;
6576 intel_crtc->lut_b[regno] = blue >> 8;
6577 }
6578
6579 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6580 u16 *blue, int regno)
6581 {
6582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6583
6584 *red = intel_crtc->lut_r[regno] << 8;
6585 *green = intel_crtc->lut_g[regno] << 8;
6586 *blue = intel_crtc->lut_b[regno] << 8;
6587 }
6588
6589 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6590 u16 *blue, uint32_t start, uint32_t size)
6591 {
6592 int end = (start + size > 256) ? 256 : start + size, i;
6593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6594
6595 for (i = start; i < end; i++) {
6596 intel_crtc->lut_r[i] = red[i] >> 8;
6597 intel_crtc->lut_g[i] = green[i] >> 8;
6598 intel_crtc->lut_b[i] = blue[i] >> 8;
6599 }
6600
6601 intel_crtc_load_lut(crtc);
6602 }
6603
6604 /* VESA 640x480x72Hz mode to set on the pipe */
6605 static struct drm_display_mode load_detect_mode = {
6606 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6607 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6608 };
6609
6610 static struct drm_framebuffer *
6611 intel_framebuffer_create(struct drm_device *dev,
6612 struct drm_mode_fb_cmd2 *mode_cmd,
6613 struct drm_i915_gem_object *obj)
6614 {
6615 struct intel_framebuffer *intel_fb;
6616 int ret;
6617
6618 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6619 if (!intel_fb) {
6620 drm_gem_object_unreference_unlocked(&obj->base);
6621 return ERR_PTR(-ENOMEM);
6622 }
6623
6624 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6625 if (ret) {
6626 drm_gem_object_unreference_unlocked(&obj->base);
6627 kfree(intel_fb);
6628 return ERR_PTR(ret);
6629 }
6630
6631 return &intel_fb->base;
6632 }
6633
6634 static u32
6635 intel_framebuffer_pitch_for_width(int width, int bpp)
6636 {
6637 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6638 return ALIGN(pitch, 64);
6639 }
6640
6641 static u32
6642 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6643 {
6644 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6645 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6646 }
6647
6648 static struct drm_framebuffer *
6649 intel_framebuffer_create_for_mode(struct drm_device *dev,
6650 struct drm_display_mode *mode,
6651 int depth, int bpp)
6652 {
6653 struct drm_i915_gem_object *obj;
6654 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6655
6656 obj = i915_gem_alloc_object(dev,
6657 intel_framebuffer_size_for_mode(mode, bpp));
6658 if (obj == NULL)
6659 return ERR_PTR(-ENOMEM);
6660
6661 mode_cmd.width = mode->hdisplay;
6662 mode_cmd.height = mode->vdisplay;
6663 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6664 bpp);
6665 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6666
6667 return intel_framebuffer_create(dev, &mode_cmd, obj);
6668 }
6669
6670 static struct drm_framebuffer *
6671 mode_fits_in_fbdev(struct drm_device *dev,
6672 struct drm_display_mode *mode)
6673 {
6674 struct drm_i915_private *dev_priv = dev->dev_private;
6675 struct drm_i915_gem_object *obj;
6676 struct drm_framebuffer *fb;
6677
6678 if (dev_priv->fbdev == NULL)
6679 return NULL;
6680
6681 obj = dev_priv->fbdev->ifb.obj;
6682 if (obj == NULL)
6683 return NULL;
6684
6685 fb = &dev_priv->fbdev->ifb.base;
6686 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6687 fb->bits_per_pixel))
6688 return NULL;
6689
6690 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6691 return NULL;
6692
6693 return fb;
6694 }
6695
6696 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6697 struct drm_display_mode *mode,
6698 struct intel_load_detect_pipe *old)
6699 {
6700 struct intel_crtc *intel_crtc;
6701 struct intel_encoder *intel_encoder =
6702 intel_attached_encoder(connector);
6703 struct drm_crtc *possible_crtc;
6704 struct drm_encoder *encoder = &intel_encoder->base;
6705 struct drm_crtc *crtc = NULL;
6706 struct drm_device *dev = encoder->dev;
6707 struct drm_framebuffer *fb;
6708 int i = -1;
6709
6710 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6711 connector->base.id, drm_get_connector_name(connector),
6712 encoder->base.id, drm_get_encoder_name(encoder));
6713
6714 /*
6715 * Algorithm gets a little messy:
6716 *
6717 * - if the connector already has an assigned crtc, use it (but make
6718 * sure it's on first)
6719 *
6720 * - try to find the first unused crtc that can drive this connector,
6721 * and use that if we find one
6722 */
6723
6724 /* See if we already have a CRTC for this connector */
6725 if (encoder->crtc) {
6726 crtc = encoder->crtc;
6727
6728 mutex_lock(&crtc->mutex);
6729
6730 old->dpms_mode = connector->dpms;
6731 old->load_detect_temp = false;
6732
6733 /* Make sure the crtc and connector are running */
6734 if (connector->dpms != DRM_MODE_DPMS_ON)
6735 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6736
6737 return true;
6738 }
6739
6740 /* Find an unused one (if possible) */
6741 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6742 i++;
6743 if (!(encoder->possible_crtcs & (1 << i)))
6744 continue;
6745 if (!possible_crtc->enabled) {
6746 crtc = possible_crtc;
6747 break;
6748 }
6749 }
6750
6751 /*
6752 * If we didn't find an unused CRTC, don't use any.
6753 */
6754 if (!crtc) {
6755 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6756 return false;
6757 }
6758
6759 mutex_lock(&crtc->mutex);
6760 intel_encoder->new_crtc = to_intel_crtc(crtc);
6761 to_intel_connector(connector)->new_encoder = intel_encoder;
6762
6763 intel_crtc = to_intel_crtc(crtc);
6764 old->dpms_mode = connector->dpms;
6765 old->load_detect_temp = true;
6766 old->release_fb = NULL;
6767
6768 if (!mode)
6769 mode = &load_detect_mode;
6770
6771 /* We need a framebuffer large enough to accommodate all accesses
6772 * that the plane may generate whilst we perform load detection.
6773 * We can not rely on the fbcon either being present (we get called
6774 * during its initialisation to detect all boot displays, or it may
6775 * not even exist) or that it is large enough to satisfy the
6776 * requested mode.
6777 */
6778 fb = mode_fits_in_fbdev(dev, mode);
6779 if (fb == NULL) {
6780 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6781 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6782 old->release_fb = fb;
6783 } else
6784 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6785 if (IS_ERR(fb)) {
6786 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6787 mutex_unlock(&crtc->mutex);
6788 return false;
6789 }
6790
6791 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6792 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6793 if (old->release_fb)
6794 old->release_fb->funcs->destroy(old->release_fb);
6795 mutex_unlock(&crtc->mutex);
6796 return false;
6797 }
6798
6799 /* let the connector get through one full cycle before testing */
6800 intel_wait_for_vblank(dev, intel_crtc->pipe);
6801 return true;
6802 }
6803
6804 void intel_release_load_detect_pipe(struct drm_connector *connector,
6805 struct intel_load_detect_pipe *old)
6806 {
6807 struct intel_encoder *intel_encoder =
6808 intel_attached_encoder(connector);
6809 struct drm_encoder *encoder = &intel_encoder->base;
6810 struct drm_crtc *crtc = encoder->crtc;
6811
6812 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6813 connector->base.id, drm_get_connector_name(connector),
6814 encoder->base.id, drm_get_encoder_name(encoder));
6815
6816 if (old->load_detect_temp) {
6817 to_intel_connector(connector)->new_encoder = NULL;
6818 intel_encoder->new_crtc = NULL;
6819 intel_set_mode(crtc, NULL, 0, 0, NULL);
6820
6821 if (old->release_fb) {
6822 drm_framebuffer_unregister_private(old->release_fb);
6823 drm_framebuffer_unreference(old->release_fb);
6824 }
6825
6826 mutex_unlock(&crtc->mutex);
6827 return;
6828 }
6829
6830 /* Switch crtc and encoder back off if necessary */
6831 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6832 connector->funcs->dpms(connector, old->dpms_mode);
6833
6834 mutex_unlock(&crtc->mutex);
6835 }
6836
6837 /* Returns the clock of the currently programmed mode of the given pipe. */
6838 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6839 {
6840 struct drm_i915_private *dev_priv = dev->dev_private;
6841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6842 int pipe = intel_crtc->pipe;
6843 u32 dpll = I915_READ(DPLL(pipe));
6844 u32 fp;
6845 intel_clock_t clock;
6846
6847 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6848 fp = I915_READ(FP0(pipe));
6849 else
6850 fp = I915_READ(FP1(pipe));
6851
6852 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6853 if (IS_PINEVIEW(dev)) {
6854 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6855 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6856 } else {
6857 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6858 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6859 }
6860
6861 if (!IS_GEN2(dev)) {
6862 if (IS_PINEVIEW(dev))
6863 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6864 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6865 else
6866 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6867 DPLL_FPA01_P1_POST_DIV_SHIFT);
6868
6869 switch (dpll & DPLL_MODE_MASK) {
6870 case DPLLB_MODE_DAC_SERIAL:
6871 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6872 5 : 10;
6873 break;
6874 case DPLLB_MODE_LVDS:
6875 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6876 7 : 14;
6877 break;
6878 default:
6879 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6880 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6881 return 0;
6882 }
6883
6884 if (IS_PINEVIEW(dev))
6885 pineview_clock(96000, &clock);
6886 else
6887 i9xx_clock(96000, &clock);
6888 } else {
6889 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6890
6891 if (is_lvds) {
6892 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6893 DPLL_FPA01_P1_POST_DIV_SHIFT);
6894 clock.p2 = 14;
6895
6896 if ((dpll & PLL_REF_INPUT_MASK) ==
6897 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6898 /* XXX: might not be 66MHz */
6899 i9xx_clock(66000, &clock);
6900 } else
6901 i9xx_clock(48000, &clock);
6902 } else {
6903 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6904 clock.p1 = 2;
6905 else {
6906 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6907 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6908 }
6909 if (dpll & PLL_P2_DIVIDE_BY_4)
6910 clock.p2 = 4;
6911 else
6912 clock.p2 = 2;
6913
6914 i9xx_clock(48000, &clock);
6915 }
6916 }
6917
6918 /* XXX: It would be nice to validate the clocks, but we can't reuse
6919 * i830PllIsValid() because it relies on the xf86_config connector
6920 * configuration being accurate, which it isn't necessarily.
6921 */
6922
6923 return clock.dot;
6924 }
6925
6926 /** Returns the currently programmed mode of the given pipe. */
6927 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6928 struct drm_crtc *crtc)
6929 {
6930 struct drm_i915_private *dev_priv = dev->dev_private;
6931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6932 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6933 struct drm_display_mode *mode;
6934 int htot = I915_READ(HTOTAL(cpu_transcoder));
6935 int hsync = I915_READ(HSYNC(cpu_transcoder));
6936 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6937 int vsync = I915_READ(VSYNC(cpu_transcoder));
6938
6939 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6940 if (!mode)
6941 return NULL;
6942
6943 mode->clock = intel_crtc_clock_get(dev, crtc);
6944 mode->hdisplay = (htot & 0xffff) + 1;
6945 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6946 mode->hsync_start = (hsync & 0xffff) + 1;
6947 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6948 mode->vdisplay = (vtot & 0xffff) + 1;
6949 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6950 mode->vsync_start = (vsync & 0xffff) + 1;
6951 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6952
6953 drm_mode_set_name(mode);
6954
6955 return mode;
6956 }
6957
6958 static void intel_increase_pllclock(struct drm_crtc *crtc)
6959 {
6960 struct drm_device *dev = crtc->dev;
6961 drm_i915_private_t *dev_priv = dev->dev_private;
6962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6963 int pipe = intel_crtc->pipe;
6964 int dpll_reg = DPLL(pipe);
6965 int dpll;
6966
6967 if (HAS_PCH_SPLIT(dev))
6968 return;
6969
6970 if (!dev_priv->lvds_downclock_avail)
6971 return;
6972
6973 dpll = I915_READ(dpll_reg);
6974 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6975 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6976
6977 assert_panel_unlocked(dev_priv, pipe);
6978
6979 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6980 I915_WRITE(dpll_reg, dpll);
6981 intel_wait_for_vblank(dev, pipe);
6982
6983 dpll = I915_READ(dpll_reg);
6984 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6985 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6986 }
6987 }
6988
6989 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6990 {
6991 struct drm_device *dev = crtc->dev;
6992 drm_i915_private_t *dev_priv = dev->dev_private;
6993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6994
6995 if (HAS_PCH_SPLIT(dev))
6996 return;
6997
6998 if (!dev_priv->lvds_downclock_avail)
6999 return;
7000
7001 /*
7002 * Since this is called by a timer, we should never get here in
7003 * the manual case.
7004 */
7005 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7006 int pipe = intel_crtc->pipe;
7007 int dpll_reg = DPLL(pipe);
7008 int dpll;
7009
7010 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7011
7012 assert_panel_unlocked(dev_priv, pipe);
7013
7014 dpll = I915_READ(dpll_reg);
7015 dpll |= DISPLAY_RATE_SELECT_FPA1;
7016 I915_WRITE(dpll_reg, dpll);
7017 intel_wait_for_vblank(dev, pipe);
7018 dpll = I915_READ(dpll_reg);
7019 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7020 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7021 }
7022
7023 }
7024
7025 void intel_mark_busy(struct drm_device *dev)
7026 {
7027 i915_update_gfx_val(dev->dev_private);
7028 }
7029
7030 void intel_mark_idle(struct drm_device *dev)
7031 {
7032 struct drm_crtc *crtc;
7033
7034 if (!i915_powersave)
7035 return;
7036
7037 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7038 if (!crtc->fb)
7039 continue;
7040
7041 intel_decrease_pllclock(crtc);
7042 }
7043 }
7044
7045 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7046 {
7047 struct drm_device *dev = obj->base.dev;
7048 struct drm_crtc *crtc;
7049
7050 if (!i915_powersave)
7051 return;
7052
7053 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7054 if (!crtc->fb)
7055 continue;
7056
7057 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7058 intel_increase_pllclock(crtc);
7059 }
7060 }
7061
7062 static void intel_crtc_destroy(struct drm_crtc *crtc)
7063 {
7064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7065 struct drm_device *dev = crtc->dev;
7066 struct intel_unpin_work *work;
7067 unsigned long flags;
7068
7069 spin_lock_irqsave(&dev->event_lock, flags);
7070 work = intel_crtc->unpin_work;
7071 intel_crtc->unpin_work = NULL;
7072 spin_unlock_irqrestore(&dev->event_lock, flags);
7073
7074 if (work) {
7075 cancel_work_sync(&work->work);
7076 kfree(work);
7077 }
7078
7079 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7080
7081 drm_crtc_cleanup(crtc);
7082
7083 kfree(intel_crtc);
7084 }
7085
7086 static void intel_unpin_work_fn(struct work_struct *__work)
7087 {
7088 struct intel_unpin_work *work =
7089 container_of(__work, struct intel_unpin_work, work);
7090 struct drm_device *dev = work->crtc->dev;
7091
7092 mutex_lock(&dev->struct_mutex);
7093 intel_unpin_fb_obj(work->old_fb_obj);
7094 drm_gem_object_unreference(&work->pending_flip_obj->base);
7095 drm_gem_object_unreference(&work->old_fb_obj->base);
7096
7097 intel_update_fbc(dev);
7098 mutex_unlock(&dev->struct_mutex);
7099
7100 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7101 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7102
7103 kfree(work);
7104 }
7105
7106 static void do_intel_finish_page_flip(struct drm_device *dev,
7107 struct drm_crtc *crtc)
7108 {
7109 drm_i915_private_t *dev_priv = dev->dev_private;
7110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7111 struct intel_unpin_work *work;
7112 unsigned long flags;
7113
7114 /* Ignore early vblank irqs */
7115 if (intel_crtc == NULL)
7116 return;
7117
7118 spin_lock_irqsave(&dev->event_lock, flags);
7119 work = intel_crtc->unpin_work;
7120
7121 /* Ensure we don't miss a work->pending update ... */
7122 smp_rmb();
7123
7124 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7125 spin_unlock_irqrestore(&dev->event_lock, flags);
7126 return;
7127 }
7128
7129 /* and that the unpin work is consistent wrt ->pending. */
7130 smp_rmb();
7131
7132 intel_crtc->unpin_work = NULL;
7133
7134 if (work->event)
7135 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7136
7137 drm_vblank_put(dev, intel_crtc->pipe);
7138
7139 spin_unlock_irqrestore(&dev->event_lock, flags);
7140
7141 wake_up_all(&dev_priv->pending_flip_queue);
7142
7143 queue_work(dev_priv->wq, &work->work);
7144
7145 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7146 }
7147
7148 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7149 {
7150 drm_i915_private_t *dev_priv = dev->dev_private;
7151 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7152
7153 do_intel_finish_page_flip(dev, crtc);
7154 }
7155
7156 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7157 {
7158 drm_i915_private_t *dev_priv = dev->dev_private;
7159 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7160
7161 do_intel_finish_page_flip(dev, crtc);
7162 }
7163
7164 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7165 {
7166 drm_i915_private_t *dev_priv = dev->dev_private;
7167 struct intel_crtc *intel_crtc =
7168 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7169 unsigned long flags;
7170
7171 /* NB: An MMIO update of the plane base pointer will also
7172 * generate a page-flip completion irq, i.e. every modeset
7173 * is also accompanied by a spurious intel_prepare_page_flip().
7174 */
7175 spin_lock_irqsave(&dev->event_lock, flags);
7176 if (intel_crtc->unpin_work)
7177 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7178 spin_unlock_irqrestore(&dev->event_lock, flags);
7179 }
7180
7181 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7182 {
7183 /* Ensure that the work item is consistent when activating it ... */
7184 smp_wmb();
7185 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7186 /* and that it is marked active as soon as the irq could fire. */
7187 smp_wmb();
7188 }
7189
7190 static int intel_gen2_queue_flip(struct drm_device *dev,
7191 struct drm_crtc *crtc,
7192 struct drm_framebuffer *fb,
7193 struct drm_i915_gem_object *obj)
7194 {
7195 struct drm_i915_private *dev_priv = dev->dev_private;
7196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7197 u32 flip_mask;
7198 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7199 int ret;
7200
7201 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7202 if (ret)
7203 goto err;
7204
7205 ret = intel_ring_begin(ring, 6);
7206 if (ret)
7207 goto err_unpin;
7208
7209 /* Can't queue multiple flips, so wait for the previous
7210 * one to finish before executing the next.
7211 */
7212 if (intel_crtc->plane)
7213 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7214 else
7215 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7216 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7217 intel_ring_emit(ring, MI_NOOP);
7218 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7219 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7220 intel_ring_emit(ring, fb->pitches[0]);
7221 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7222 intel_ring_emit(ring, 0); /* aux display base address, unused */
7223
7224 intel_mark_page_flip_active(intel_crtc);
7225 intel_ring_advance(ring);
7226 return 0;
7227
7228 err_unpin:
7229 intel_unpin_fb_obj(obj);
7230 err:
7231 return ret;
7232 }
7233
7234 static int intel_gen3_queue_flip(struct drm_device *dev,
7235 struct drm_crtc *crtc,
7236 struct drm_framebuffer *fb,
7237 struct drm_i915_gem_object *obj)
7238 {
7239 struct drm_i915_private *dev_priv = dev->dev_private;
7240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7241 u32 flip_mask;
7242 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7243 int ret;
7244
7245 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7246 if (ret)
7247 goto err;
7248
7249 ret = intel_ring_begin(ring, 6);
7250 if (ret)
7251 goto err_unpin;
7252
7253 if (intel_crtc->plane)
7254 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7255 else
7256 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7257 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7258 intel_ring_emit(ring, MI_NOOP);
7259 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7260 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7261 intel_ring_emit(ring, fb->pitches[0]);
7262 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7263 intel_ring_emit(ring, MI_NOOP);
7264
7265 intel_mark_page_flip_active(intel_crtc);
7266 intel_ring_advance(ring);
7267 return 0;
7268
7269 err_unpin:
7270 intel_unpin_fb_obj(obj);
7271 err:
7272 return ret;
7273 }
7274
7275 static int intel_gen4_queue_flip(struct drm_device *dev,
7276 struct drm_crtc *crtc,
7277 struct drm_framebuffer *fb,
7278 struct drm_i915_gem_object *obj)
7279 {
7280 struct drm_i915_private *dev_priv = dev->dev_private;
7281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7282 uint32_t pf, pipesrc;
7283 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7284 int ret;
7285
7286 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7287 if (ret)
7288 goto err;
7289
7290 ret = intel_ring_begin(ring, 4);
7291 if (ret)
7292 goto err_unpin;
7293
7294 /* i965+ uses the linear or tiled offsets from the
7295 * Display Registers (which do not change across a page-flip)
7296 * so we need only reprogram the base address.
7297 */
7298 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7299 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7300 intel_ring_emit(ring, fb->pitches[0]);
7301 intel_ring_emit(ring,
7302 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7303 obj->tiling_mode);
7304
7305 /* XXX Enabling the panel-fitter across page-flip is so far
7306 * untested on non-native modes, so ignore it for now.
7307 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7308 */
7309 pf = 0;
7310 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7311 intel_ring_emit(ring, pf | pipesrc);
7312
7313 intel_mark_page_flip_active(intel_crtc);
7314 intel_ring_advance(ring);
7315 return 0;
7316
7317 err_unpin:
7318 intel_unpin_fb_obj(obj);
7319 err:
7320 return ret;
7321 }
7322
7323 static int intel_gen6_queue_flip(struct drm_device *dev,
7324 struct drm_crtc *crtc,
7325 struct drm_framebuffer *fb,
7326 struct drm_i915_gem_object *obj)
7327 {
7328 struct drm_i915_private *dev_priv = dev->dev_private;
7329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7330 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7331 uint32_t pf, pipesrc;
7332 int ret;
7333
7334 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7335 if (ret)
7336 goto err;
7337
7338 ret = intel_ring_begin(ring, 4);
7339 if (ret)
7340 goto err_unpin;
7341
7342 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7343 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7344 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7345 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7346
7347 /* Contrary to the suggestions in the documentation,
7348 * "Enable Panel Fitter" does not seem to be required when page
7349 * flipping with a non-native mode, and worse causes a normal
7350 * modeset to fail.
7351 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7352 */
7353 pf = 0;
7354 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7355 intel_ring_emit(ring, pf | pipesrc);
7356
7357 intel_mark_page_flip_active(intel_crtc);
7358 intel_ring_advance(ring);
7359 return 0;
7360
7361 err_unpin:
7362 intel_unpin_fb_obj(obj);
7363 err:
7364 return ret;
7365 }
7366
7367 /*
7368 * On gen7 we currently use the blit ring because (in early silicon at least)
7369 * the render ring doesn't give us interrpts for page flip completion, which
7370 * means clients will hang after the first flip is queued. Fortunately the
7371 * blit ring generates interrupts properly, so use it instead.
7372 */
7373 static int intel_gen7_queue_flip(struct drm_device *dev,
7374 struct drm_crtc *crtc,
7375 struct drm_framebuffer *fb,
7376 struct drm_i915_gem_object *obj)
7377 {
7378 struct drm_i915_private *dev_priv = dev->dev_private;
7379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7380 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7381 uint32_t plane_bit = 0;
7382 int ret;
7383
7384 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7385 if (ret)
7386 goto err;
7387
7388 switch(intel_crtc->plane) {
7389 case PLANE_A:
7390 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7391 break;
7392 case PLANE_B:
7393 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7394 break;
7395 case PLANE_C:
7396 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7397 break;
7398 default:
7399 WARN_ONCE(1, "unknown plane in flip command\n");
7400 ret = -ENODEV;
7401 goto err_unpin;
7402 }
7403
7404 ret = intel_ring_begin(ring, 4);
7405 if (ret)
7406 goto err_unpin;
7407
7408 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7409 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7410 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7411 intel_ring_emit(ring, (MI_NOOP));
7412
7413 intel_mark_page_flip_active(intel_crtc);
7414 intel_ring_advance(ring);
7415 return 0;
7416
7417 err_unpin:
7418 intel_unpin_fb_obj(obj);
7419 err:
7420 return ret;
7421 }
7422
7423 static int intel_default_queue_flip(struct drm_device *dev,
7424 struct drm_crtc *crtc,
7425 struct drm_framebuffer *fb,
7426 struct drm_i915_gem_object *obj)
7427 {
7428 return -ENODEV;
7429 }
7430
7431 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7432 struct drm_framebuffer *fb,
7433 struct drm_pending_vblank_event *event)
7434 {
7435 struct drm_device *dev = crtc->dev;
7436 struct drm_i915_private *dev_priv = dev->dev_private;
7437 struct drm_framebuffer *old_fb = crtc->fb;
7438 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7440 struct intel_unpin_work *work;
7441 unsigned long flags;
7442 int ret;
7443
7444 /* Can't change pixel format via MI display flips. */
7445 if (fb->pixel_format != crtc->fb->pixel_format)
7446 return -EINVAL;
7447
7448 /*
7449 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7450 * Note that pitch changes could also affect these register.
7451 */
7452 if (INTEL_INFO(dev)->gen > 3 &&
7453 (fb->offsets[0] != crtc->fb->offsets[0] ||
7454 fb->pitches[0] != crtc->fb->pitches[0]))
7455 return -EINVAL;
7456
7457 work = kzalloc(sizeof *work, GFP_KERNEL);
7458 if (work == NULL)
7459 return -ENOMEM;
7460
7461 work->event = event;
7462 work->crtc = crtc;
7463 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7464 INIT_WORK(&work->work, intel_unpin_work_fn);
7465
7466 ret = drm_vblank_get(dev, intel_crtc->pipe);
7467 if (ret)
7468 goto free_work;
7469
7470 /* We borrow the event spin lock for protecting unpin_work */
7471 spin_lock_irqsave(&dev->event_lock, flags);
7472 if (intel_crtc->unpin_work) {
7473 spin_unlock_irqrestore(&dev->event_lock, flags);
7474 kfree(work);
7475 drm_vblank_put(dev, intel_crtc->pipe);
7476
7477 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7478 return -EBUSY;
7479 }
7480 intel_crtc->unpin_work = work;
7481 spin_unlock_irqrestore(&dev->event_lock, flags);
7482
7483 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7484 flush_workqueue(dev_priv->wq);
7485
7486 ret = i915_mutex_lock_interruptible(dev);
7487 if (ret)
7488 goto cleanup;
7489
7490 /* Reference the objects for the scheduled work. */
7491 drm_gem_object_reference(&work->old_fb_obj->base);
7492 drm_gem_object_reference(&obj->base);
7493
7494 crtc->fb = fb;
7495
7496 work->pending_flip_obj = obj;
7497
7498 work->enable_stall_check = true;
7499
7500 atomic_inc(&intel_crtc->unpin_work_count);
7501 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7502
7503 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7504 if (ret)
7505 goto cleanup_pending;
7506
7507 intel_disable_fbc(dev);
7508 intel_mark_fb_busy(obj);
7509 mutex_unlock(&dev->struct_mutex);
7510
7511 trace_i915_flip_request(intel_crtc->plane, obj);
7512
7513 return 0;
7514
7515 cleanup_pending:
7516 atomic_dec(&intel_crtc->unpin_work_count);
7517 crtc->fb = old_fb;
7518 drm_gem_object_unreference(&work->old_fb_obj->base);
7519 drm_gem_object_unreference(&obj->base);
7520 mutex_unlock(&dev->struct_mutex);
7521
7522 cleanup:
7523 spin_lock_irqsave(&dev->event_lock, flags);
7524 intel_crtc->unpin_work = NULL;
7525 spin_unlock_irqrestore(&dev->event_lock, flags);
7526
7527 drm_vblank_put(dev, intel_crtc->pipe);
7528 free_work:
7529 kfree(work);
7530
7531 return ret;
7532 }
7533
7534 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7535 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7536 .load_lut = intel_crtc_load_lut,
7537 };
7538
7539 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7540 struct drm_crtc *crtc)
7541 {
7542 struct drm_device *dev;
7543 struct drm_crtc *tmp;
7544 int crtc_mask = 1;
7545
7546 WARN(!crtc, "checking null crtc?\n");
7547
7548 dev = crtc->dev;
7549
7550 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7551 if (tmp == crtc)
7552 break;
7553 crtc_mask <<= 1;
7554 }
7555
7556 if (encoder->possible_crtcs & crtc_mask)
7557 return true;
7558 return false;
7559 }
7560
7561 /**
7562 * intel_modeset_update_staged_output_state
7563 *
7564 * Updates the staged output configuration state, e.g. after we've read out the
7565 * current hw state.
7566 */
7567 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7568 {
7569 struct intel_encoder *encoder;
7570 struct intel_connector *connector;
7571
7572 list_for_each_entry(connector, &dev->mode_config.connector_list,
7573 base.head) {
7574 connector->new_encoder =
7575 to_intel_encoder(connector->base.encoder);
7576 }
7577
7578 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7579 base.head) {
7580 encoder->new_crtc =
7581 to_intel_crtc(encoder->base.crtc);
7582 }
7583 }
7584
7585 /**
7586 * intel_modeset_commit_output_state
7587 *
7588 * This function copies the stage display pipe configuration to the real one.
7589 */
7590 static void intel_modeset_commit_output_state(struct drm_device *dev)
7591 {
7592 struct intel_encoder *encoder;
7593 struct intel_connector *connector;
7594
7595 list_for_each_entry(connector, &dev->mode_config.connector_list,
7596 base.head) {
7597 connector->base.encoder = &connector->new_encoder->base;
7598 }
7599
7600 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7601 base.head) {
7602 encoder->base.crtc = &encoder->new_crtc->base;
7603 }
7604 }
7605
7606 static void
7607 connected_sink_compute_bpp(struct intel_connector * connector,
7608 struct intel_crtc_config *pipe_config)
7609 {
7610 int bpp = pipe_config->pipe_bpp;
7611
7612 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7613 connector->base.base.id,
7614 drm_get_connector_name(&connector->base));
7615
7616 /* Don't use an invalid EDID bpc value */
7617 if (connector->base.display_info.bpc &&
7618 connector->base.display_info.bpc * 3 < bpp) {
7619 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7620 bpp, connector->base.display_info.bpc*3);
7621 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7622 }
7623
7624 /* Clamp bpp to 8 on screens without EDID 1.4 */
7625 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7626 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7627 bpp);
7628 pipe_config->pipe_bpp = 24;
7629 }
7630 }
7631
7632 static int
7633 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7634 struct drm_framebuffer *fb,
7635 struct intel_crtc_config *pipe_config)
7636 {
7637 struct drm_device *dev = crtc->base.dev;
7638 struct intel_connector *connector;
7639 int bpp;
7640
7641 switch (fb->pixel_format) {
7642 case DRM_FORMAT_C8:
7643 bpp = 8*3; /* since we go through a colormap */
7644 break;
7645 case DRM_FORMAT_XRGB1555:
7646 case DRM_FORMAT_ARGB1555:
7647 /* checked in intel_framebuffer_init already */
7648 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7649 return -EINVAL;
7650 case DRM_FORMAT_RGB565:
7651 bpp = 6*3; /* min is 18bpp */
7652 break;
7653 case DRM_FORMAT_XBGR8888:
7654 case DRM_FORMAT_ABGR8888:
7655 /* checked in intel_framebuffer_init already */
7656 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7657 return -EINVAL;
7658 case DRM_FORMAT_XRGB8888:
7659 case DRM_FORMAT_ARGB8888:
7660 bpp = 8*3;
7661 break;
7662 case DRM_FORMAT_XRGB2101010:
7663 case DRM_FORMAT_ARGB2101010:
7664 case DRM_FORMAT_XBGR2101010:
7665 case DRM_FORMAT_ABGR2101010:
7666 /* checked in intel_framebuffer_init already */
7667 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7668 return -EINVAL;
7669 bpp = 10*3;
7670 break;
7671 /* TODO: gen4+ supports 16 bpc floating point, too. */
7672 default:
7673 DRM_DEBUG_KMS("unsupported depth\n");
7674 return -EINVAL;
7675 }
7676
7677 pipe_config->pipe_bpp = bpp;
7678
7679 /* Clamp display bpp to EDID value */
7680 list_for_each_entry(connector, &dev->mode_config.connector_list,
7681 base.head) {
7682 if (!connector->new_encoder ||
7683 connector->new_encoder->new_crtc != crtc)
7684 continue;
7685
7686 connected_sink_compute_bpp(connector, pipe_config);
7687 }
7688
7689 return bpp;
7690 }
7691
7692 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7693 struct intel_crtc_config *pipe_config,
7694 const char *context)
7695 {
7696 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7697 context, pipe_name(crtc->pipe));
7698
7699 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7700 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7701 pipe_config->pipe_bpp, pipe_config->dither);
7702 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7703 pipe_config->has_pch_encoder,
7704 pipe_config->fdi_lanes,
7705 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7706 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7707 pipe_config->fdi_m_n.tu);
7708 DRM_DEBUG_KMS("requested mode:\n");
7709 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7710 DRM_DEBUG_KMS("adjusted mode:\n");
7711 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7712 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7713 pipe_config->gmch_pfit.control,
7714 pipe_config->gmch_pfit.pgm_ratios,
7715 pipe_config->gmch_pfit.lvds_border_bits);
7716 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7717 pipe_config->pch_pfit.pos,
7718 pipe_config->pch_pfit.size);
7719 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7720 }
7721
7722 static bool check_encoder_cloning(struct drm_crtc *crtc)
7723 {
7724 int num_encoders = 0;
7725 bool uncloneable_encoders = false;
7726 struct intel_encoder *encoder;
7727
7728 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7729 base.head) {
7730 if (&encoder->new_crtc->base != crtc)
7731 continue;
7732
7733 num_encoders++;
7734 if (!encoder->cloneable)
7735 uncloneable_encoders = true;
7736 }
7737
7738 return !(num_encoders > 1 && uncloneable_encoders);
7739 }
7740
7741 static struct intel_crtc_config *
7742 intel_modeset_pipe_config(struct drm_crtc *crtc,
7743 struct drm_framebuffer *fb,
7744 struct drm_display_mode *mode)
7745 {
7746 struct drm_device *dev = crtc->dev;
7747 struct drm_encoder_helper_funcs *encoder_funcs;
7748 struct intel_encoder *encoder;
7749 struct intel_crtc_config *pipe_config;
7750 int plane_bpp, ret = -EINVAL;
7751 bool retry = true;
7752
7753 if (!check_encoder_cloning(crtc)) {
7754 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7755 return ERR_PTR(-EINVAL);
7756 }
7757
7758 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7759 if (!pipe_config)
7760 return ERR_PTR(-ENOMEM);
7761
7762 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7763 drm_mode_copy(&pipe_config->requested_mode, mode);
7764 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7765
7766 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7767 * plane pixel format and any sink constraints into account. Returns the
7768 * source plane bpp so that dithering can be selected on mismatches
7769 * after encoders and crtc also have had their say. */
7770 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7771 fb, pipe_config);
7772 if (plane_bpp < 0)
7773 goto fail;
7774
7775 encoder_retry:
7776 /* Ensure the port clock defaults are reset when retrying. */
7777 pipe_config->port_clock = 0;
7778 pipe_config->pixel_multiplier = 1;
7779
7780 /* Pass our mode to the connectors and the CRTC to give them a chance to
7781 * adjust it according to limitations or connector properties, and also
7782 * a chance to reject the mode entirely.
7783 */
7784 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7785 base.head) {
7786
7787 if (&encoder->new_crtc->base != crtc)
7788 continue;
7789
7790 if (encoder->compute_config) {
7791 if (!(encoder->compute_config(encoder, pipe_config))) {
7792 DRM_DEBUG_KMS("Encoder config failure\n");
7793 goto fail;
7794 }
7795
7796 continue;
7797 }
7798
7799 encoder_funcs = encoder->base.helper_private;
7800 if (!(encoder_funcs->mode_fixup(&encoder->base,
7801 &pipe_config->requested_mode,
7802 &pipe_config->adjusted_mode))) {
7803 DRM_DEBUG_KMS("Encoder fixup failed\n");
7804 goto fail;
7805 }
7806 }
7807
7808 /* Set default port clock if not overwritten by the encoder. Needs to be
7809 * done afterwards in case the encoder adjusts the mode. */
7810 if (!pipe_config->port_clock)
7811 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7812
7813 ret = intel_crtc_compute_config(crtc, pipe_config);
7814 if (ret < 0) {
7815 DRM_DEBUG_KMS("CRTC fixup failed\n");
7816 goto fail;
7817 }
7818
7819 if (ret == RETRY) {
7820 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7821 ret = -EINVAL;
7822 goto fail;
7823 }
7824
7825 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7826 retry = false;
7827 goto encoder_retry;
7828 }
7829
7830 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7831 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7832 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7833
7834 return pipe_config;
7835 fail:
7836 kfree(pipe_config);
7837 return ERR_PTR(ret);
7838 }
7839
7840 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7841 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7842 static void
7843 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7844 unsigned *prepare_pipes, unsigned *disable_pipes)
7845 {
7846 struct intel_crtc *intel_crtc;
7847 struct drm_device *dev = crtc->dev;
7848 struct intel_encoder *encoder;
7849 struct intel_connector *connector;
7850 struct drm_crtc *tmp_crtc;
7851
7852 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7853
7854 /* Check which crtcs have changed outputs connected to them, these need
7855 * to be part of the prepare_pipes mask. We don't (yet) support global
7856 * modeset across multiple crtcs, so modeset_pipes will only have one
7857 * bit set at most. */
7858 list_for_each_entry(connector, &dev->mode_config.connector_list,
7859 base.head) {
7860 if (connector->base.encoder == &connector->new_encoder->base)
7861 continue;
7862
7863 if (connector->base.encoder) {
7864 tmp_crtc = connector->base.encoder->crtc;
7865
7866 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7867 }
7868
7869 if (connector->new_encoder)
7870 *prepare_pipes |=
7871 1 << connector->new_encoder->new_crtc->pipe;
7872 }
7873
7874 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7875 base.head) {
7876 if (encoder->base.crtc == &encoder->new_crtc->base)
7877 continue;
7878
7879 if (encoder->base.crtc) {
7880 tmp_crtc = encoder->base.crtc;
7881
7882 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7883 }
7884
7885 if (encoder->new_crtc)
7886 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7887 }
7888
7889 /* Check for any pipes that will be fully disabled ... */
7890 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7891 base.head) {
7892 bool used = false;
7893
7894 /* Don't try to disable disabled crtcs. */
7895 if (!intel_crtc->base.enabled)
7896 continue;
7897
7898 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7899 base.head) {
7900 if (encoder->new_crtc == intel_crtc)
7901 used = true;
7902 }
7903
7904 if (!used)
7905 *disable_pipes |= 1 << intel_crtc->pipe;
7906 }
7907
7908
7909 /* set_mode is also used to update properties on life display pipes. */
7910 intel_crtc = to_intel_crtc(crtc);
7911 if (crtc->enabled)
7912 *prepare_pipes |= 1 << intel_crtc->pipe;
7913
7914 /*
7915 * For simplicity do a full modeset on any pipe where the output routing
7916 * changed. We could be more clever, but that would require us to be
7917 * more careful with calling the relevant encoder->mode_set functions.
7918 */
7919 if (*prepare_pipes)
7920 *modeset_pipes = *prepare_pipes;
7921
7922 /* ... and mask these out. */
7923 *modeset_pipes &= ~(*disable_pipes);
7924 *prepare_pipes &= ~(*disable_pipes);
7925
7926 /*
7927 * HACK: We don't (yet) fully support global modesets. intel_set_config
7928 * obies this rule, but the modeset restore mode of
7929 * intel_modeset_setup_hw_state does not.
7930 */
7931 *modeset_pipes &= 1 << intel_crtc->pipe;
7932 *prepare_pipes &= 1 << intel_crtc->pipe;
7933
7934 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7935 *modeset_pipes, *prepare_pipes, *disable_pipes);
7936 }
7937
7938 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7939 {
7940 struct drm_encoder *encoder;
7941 struct drm_device *dev = crtc->dev;
7942
7943 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7944 if (encoder->crtc == crtc)
7945 return true;
7946
7947 return false;
7948 }
7949
7950 static void
7951 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7952 {
7953 struct intel_encoder *intel_encoder;
7954 struct intel_crtc *intel_crtc;
7955 struct drm_connector *connector;
7956
7957 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7958 base.head) {
7959 if (!intel_encoder->base.crtc)
7960 continue;
7961
7962 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7963
7964 if (prepare_pipes & (1 << intel_crtc->pipe))
7965 intel_encoder->connectors_active = false;
7966 }
7967
7968 intel_modeset_commit_output_state(dev);
7969
7970 /* Update computed state. */
7971 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7972 base.head) {
7973 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7974 }
7975
7976 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7977 if (!connector->encoder || !connector->encoder->crtc)
7978 continue;
7979
7980 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7981
7982 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7983 struct drm_property *dpms_property =
7984 dev->mode_config.dpms_property;
7985
7986 connector->dpms = DRM_MODE_DPMS_ON;
7987 drm_object_property_set_value(&connector->base,
7988 dpms_property,
7989 DRM_MODE_DPMS_ON);
7990
7991 intel_encoder = to_intel_encoder(connector->encoder);
7992 intel_encoder->connectors_active = true;
7993 }
7994 }
7995
7996 }
7997
7998 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7999 list_for_each_entry((intel_crtc), \
8000 &(dev)->mode_config.crtc_list, \
8001 base.head) \
8002 if (mask & (1 <<(intel_crtc)->pipe))
8003
8004 static bool
8005 intel_pipe_config_compare(struct drm_device *dev,
8006 struct intel_crtc_config *current_config,
8007 struct intel_crtc_config *pipe_config)
8008 {
8009 #define PIPE_CONF_CHECK_I(name) \
8010 if (current_config->name != pipe_config->name) { \
8011 DRM_ERROR("mismatch in " #name " " \
8012 "(expected %i, found %i)\n", \
8013 current_config->name, \
8014 pipe_config->name); \
8015 return false; \
8016 }
8017
8018 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8019 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8020 DRM_ERROR("mismatch in " #name " " \
8021 "(expected %i, found %i)\n", \
8022 current_config->name & (mask), \
8023 pipe_config->name & (mask)); \
8024 return false; \
8025 }
8026
8027 PIPE_CONF_CHECK_I(cpu_transcoder);
8028
8029 PIPE_CONF_CHECK_I(has_pch_encoder);
8030 PIPE_CONF_CHECK_I(fdi_lanes);
8031 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8032 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8033 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8034 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8035 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8036
8037 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8038 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8039 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8040 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8041 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8042 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8043
8044 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8045 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8046 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8047 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8048 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8049 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8050
8051 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8052 DRM_MODE_FLAG_INTERLACE);
8053
8054 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8055 DRM_MODE_FLAG_PHSYNC);
8056 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8057 DRM_MODE_FLAG_NHSYNC);
8058 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8059 DRM_MODE_FLAG_PVSYNC);
8060 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8061 DRM_MODE_FLAG_NVSYNC);
8062
8063 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8064 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8065
8066 PIPE_CONF_CHECK_I(gmch_pfit.control);
8067 /* pfit ratios are autocomputed by the hw on gen4+ */
8068 if (INTEL_INFO(dev)->gen < 4)
8069 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8070 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8071 PIPE_CONF_CHECK_I(pch_pfit.pos);
8072 PIPE_CONF_CHECK_I(pch_pfit.size);
8073
8074 PIPE_CONF_CHECK_I(ips_enabled);
8075
8076 #undef PIPE_CONF_CHECK_I
8077 #undef PIPE_CONF_CHECK_FLAGS
8078
8079 return true;
8080 }
8081
8082 void
8083 intel_modeset_check_state(struct drm_device *dev)
8084 {
8085 drm_i915_private_t *dev_priv = dev->dev_private;
8086 struct intel_crtc *crtc;
8087 struct intel_encoder *encoder;
8088 struct intel_connector *connector;
8089 struct intel_crtc_config pipe_config;
8090
8091 list_for_each_entry(connector, &dev->mode_config.connector_list,
8092 base.head) {
8093 /* This also checks the encoder/connector hw state with the
8094 * ->get_hw_state callbacks. */
8095 intel_connector_check_state(connector);
8096
8097 WARN(&connector->new_encoder->base != connector->base.encoder,
8098 "connector's staged encoder doesn't match current encoder\n");
8099 }
8100
8101 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8102 base.head) {
8103 bool enabled = false;
8104 bool active = false;
8105 enum pipe pipe, tracked_pipe;
8106
8107 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8108 encoder->base.base.id,
8109 drm_get_encoder_name(&encoder->base));
8110
8111 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8112 "encoder's stage crtc doesn't match current crtc\n");
8113 WARN(encoder->connectors_active && !encoder->base.crtc,
8114 "encoder's active_connectors set, but no crtc\n");
8115
8116 list_for_each_entry(connector, &dev->mode_config.connector_list,
8117 base.head) {
8118 if (connector->base.encoder != &encoder->base)
8119 continue;
8120 enabled = true;
8121 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8122 active = true;
8123 }
8124 WARN(!!encoder->base.crtc != enabled,
8125 "encoder's enabled state mismatch "
8126 "(expected %i, found %i)\n",
8127 !!encoder->base.crtc, enabled);
8128 WARN(active && !encoder->base.crtc,
8129 "active encoder with no crtc\n");
8130
8131 WARN(encoder->connectors_active != active,
8132 "encoder's computed active state doesn't match tracked active state "
8133 "(expected %i, found %i)\n", active, encoder->connectors_active);
8134
8135 active = encoder->get_hw_state(encoder, &pipe);
8136 WARN(active != encoder->connectors_active,
8137 "encoder's hw state doesn't match sw tracking "
8138 "(expected %i, found %i)\n",
8139 encoder->connectors_active, active);
8140
8141 if (!encoder->base.crtc)
8142 continue;
8143
8144 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8145 WARN(active && pipe != tracked_pipe,
8146 "active encoder's pipe doesn't match"
8147 "(expected %i, found %i)\n",
8148 tracked_pipe, pipe);
8149
8150 }
8151
8152 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8153 base.head) {
8154 bool enabled = false;
8155 bool active = false;
8156
8157 memset(&pipe_config, 0, sizeof(pipe_config));
8158
8159 DRM_DEBUG_KMS("[CRTC:%d]\n",
8160 crtc->base.base.id);
8161
8162 WARN(crtc->active && !crtc->base.enabled,
8163 "active crtc, but not enabled in sw tracking\n");
8164
8165 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8166 base.head) {
8167 if (encoder->base.crtc != &crtc->base)
8168 continue;
8169 enabled = true;
8170 if (encoder->connectors_active)
8171 active = true;
8172 if (encoder->get_config)
8173 encoder->get_config(encoder, &pipe_config);
8174 }
8175 WARN(active != crtc->active,
8176 "crtc's computed active state doesn't match tracked active state "
8177 "(expected %i, found %i)\n", active, crtc->active);
8178 WARN(enabled != crtc->base.enabled,
8179 "crtc's computed enabled state doesn't match tracked enabled state "
8180 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8181
8182 active = dev_priv->display.get_pipe_config(crtc,
8183 &pipe_config);
8184 WARN(crtc->active != active,
8185 "crtc active state doesn't match with hw state "
8186 "(expected %i, found %i)\n", crtc->active, active);
8187
8188 if (active &&
8189 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8190 WARN(1, "pipe state doesn't match!\n");
8191 intel_dump_pipe_config(crtc, &pipe_config,
8192 "[hw state]");
8193 intel_dump_pipe_config(crtc, &crtc->config,
8194 "[sw state]");
8195 }
8196 }
8197 }
8198
8199 static int __intel_set_mode(struct drm_crtc *crtc,
8200 struct drm_display_mode *mode,
8201 int x, int y, struct drm_framebuffer *fb)
8202 {
8203 struct drm_device *dev = crtc->dev;
8204 drm_i915_private_t *dev_priv = dev->dev_private;
8205 struct drm_display_mode *saved_mode, *saved_hwmode;
8206 struct intel_crtc_config *pipe_config = NULL;
8207 struct intel_crtc *intel_crtc;
8208 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8209 int ret = 0;
8210
8211 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8212 if (!saved_mode)
8213 return -ENOMEM;
8214 saved_hwmode = saved_mode + 1;
8215
8216 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8217 &prepare_pipes, &disable_pipes);
8218
8219 *saved_hwmode = crtc->hwmode;
8220 *saved_mode = crtc->mode;
8221
8222 /* Hack: Because we don't (yet) support global modeset on multiple
8223 * crtcs, we don't keep track of the new mode for more than one crtc.
8224 * Hence simply check whether any bit is set in modeset_pipes in all the
8225 * pieces of code that are not yet converted to deal with mutliple crtcs
8226 * changing their mode at the same time. */
8227 if (modeset_pipes) {
8228 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8229 if (IS_ERR(pipe_config)) {
8230 ret = PTR_ERR(pipe_config);
8231 pipe_config = NULL;
8232
8233 goto out;
8234 }
8235 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8236 "[modeset]");
8237 }
8238
8239 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8240 intel_crtc_disable(&intel_crtc->base);
8241
8242 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8243 if (intel_crtc->base.enabled)
8244 dev_priv->display.crtc_disable(&intel_crtc->base);
8245 }
8246
8247 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8248 * to set it here already despite that we pass it down the callchain.
8249 */
8250 if (modeset_pipes) {
8251 crtc->mode = *mode;
8252 /* mode_set/enable/disable functions rely on a correct pipe
8253 * config. */
8254 to_intel_crtc(crtc)->config = *pipe_config;
8255 }
8256
8257 /* Only after disabling all output pipelines that will be changed can we
8258 * update the the output configuration. */
8259 intel_modeset_update_state(dev, prepare_pipes);
8260
8261 if (dev_priv->display.modeset_global_resources)
8262 dev_priv->display.modeset_global_resources(dev);
8263
8264 /* Set up the DPLL and any encoders state that needs to adjust or depend
8265 * on the DPLL.
8266 */
8267 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8268 ret = intel_crtc_mode_set(&intel_crtc->base,
8269 x, y, fb);
8270 if (ret)
8271 goto done;
8272 }
8273
8274 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8275 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8276 dev_priv->display.crtc_enable(&intel_crtc->base);
8277
8278 if (modeset_pipes) {
8279 /* Store real post-adjustment hardware mode. */
8280 crtc->hwmode = pipe_config->adjusted_mode;
8281
8282 /* Calculate and store various constants which
8283 * are later needed by vblank and swap-completion
8284 * timestamping. They are derived from true hwmode.
8285 */
8286 drm_calc_timestamping_constants(crtc);
8287 }
8288
8289 /* FIXME: add subpixel order */
8290 done:
8291 if (ret && crtc->enabled) {
8292 crtc->hwmode = *saved_hwmode;
8293 crtc->mode = *saved_mode;
8294 }
8295
8296 out:
8297 kfree(pipe_config);
8298 kfree(saved_mode);
8299 return ret;
8300 }
8301
8302 int intel_set_mode(struct drm_crtc *crtc,
8303 struct drm_display_mode *mode,
8304 int x, int y, struct drm_framebuffer *fb)
8305 {
8306 int ret;
8307
8308 ret = __intel_set_mode(crtc, mode, x, y, fb);
8309
8310 if (ret == 0)
8311 intel_modeset_check_state(crtc->dev);
8312
8313 return ret;
8314 }
8315
8316 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8317 {
8318 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8319 }
8320
8321 #undef for_each_intel_crtc_masked
8322
8323 static void intel_set_config_free(struct intel_set_config *config)
8324 {
8325 if (!config)
8326 return;
8327
8328 kfree(config->save_connector_encoders);
8329 kfree(config->save_encoder_crtcs);
8330 kfree(config);
8331 }
8332
8333 static int intel_set_config_save_state(struct drm_device *dev,
8334 struct intel_set_config *config)
8335 {
8336 struct drm_encoder *encoder;
8337 struct drm_connector *connector;
8338 int count;
8339
8340 config->save_encoder_crtcs =
8341 kcalloc(dev->mode_config.num_encoder,
8342 sizeof(struct drm_crtc *), GFP_KERNEL);
8343 if (!config->save_encoder_crtcs)
8344 return -ENOMEM;
8345
8346 config->save_connector_encoders =
8347 kcalloc(dev->mode_config.num_connector,
8348 sizeof(struct drm_encoder *), GFP_KERNEL);
8349 if (!config->save_connector_encoders)
8350 return -ENOMEM;
8351
8352 /* Copy data. Note that driver private data is not affected.
8353 * Should anything bad happen only the expected state is
8354 * restored, not the drivers personal bookkeeping.
8355 */
8356 count = 0;
8357 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8358 config->save_encoder_crtcs[count++] = encoder->crtc;
8359 }
8360
8361 count = 0;
8362 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8363 config->save_connector_encoders[count++] = connector->encoder;
8364 }
8365
8366 return 0;
8367 }
8368
8369 static void intel_set_config_restore_state(struct drm_device *dev,
8370 struct intel_set_config *config)
8371 {
8372 struct intel_encoder *encoder;
8373 struct intel_connector *connector;
8374 int count;
8375
8376 count = 0;
8377 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8378 encoder->new_crtc =
8379 to_intel_crtc(config->save_encoder_crtcs[count++]);
8380 }
8381
8382 count = 0;
8383 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8384 connector->new_encoder =
8385 to_intel_encoder(config->save_connector_encoders[count++]);
8386 }
8387 }
8388
8389 static void
8390 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8391 struct intel_set_config *config)
8392 {
8393
8394 /* We should be able to check here if the fb has the same properties
8395 * and then just flip_or_move it */
8396 if (set->crtc->fb != set->fb) {
8397 /* If we have no fb then treat it as a full mode set */
8398 if (set->crtc->fb == NULL) {
8399 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8400 config->mode_changed = true;
8401 } else if (set->fb == NULL) {
8402 config->mode_changed = true;
8403 } else if (set->fb->pixel_format !=
8404 set->crtc->fb->pixel_format) {
8405 config->mode_changed = true;
8406 } else
8407 config->fb_changed = true;
8408 }
8409
8410 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8411 config->fb_changed = true;
8412
8413 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8414 DRM_DEBUG_KMS("modes are different, full mode set\n");
8415 drm_mode_debug_printmodeline(&set->crtc->mode);
8416 drm_mode_debug_printmodeline(set->mode);
8417 config->mode_changed = true;
8418 }
8419 }
8420
8421 static int
8422 intel_modeset_stage_output_state(struct drm_device *dev,
8423 struct drm_mode_set *set,
8424 struct intel_set_config *config)
8425 {
8426 struct drm_crtc *new_crtc;
8427 struct intel_connector *connector;
8428 struct intel_encoder *encoder;
8429 int count, ro;
8430
8431 /* The upper layers ensure that we either disable a crtc or have a list
8432 * of connectors. For paranoia, double-check this. */
8433 WARN_ON(!set->fb && (set->num_connectors != 0));
8434 WARN_ON(set->fb && (set->num_connectors == 0));
8435
8436 count = 0;
8437 list_for_each_entry(connector, &dev->mode_config.connector_list,
8438 base.head) {
8439 /* Otherwise traverse passed in connector list and get encoders
8440 * for them. */
8441 for (ro = 0; ro < set->num_connectors; ro++) {
8442 if (set->connectors[ro] == &connector->base) {
8443 connector->new_encoder = connector->encoder;
8444 break;
8445 }
8446 }
8447
8448 /* If we disable the crtc, disable all its connectors. Also, if
8449 * the connector is on the changing crtc but not on the new
8450 * connector list, disable it. */
8451 if ((!set->fb || ro == set->num_connectors) &&
8452 connector->base.encoder &&
8453 connector->base.encoder->crtc == set->crtc) {
8454 connector->new_encoder = NULL;
8455
8456 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8457 connector->base.base.id,
8458 drm_get_connector_name(&connector->base));
8459 }
8460
8461
8462 if (&connector->new_encoder->base != connector->base.encoder) {
8463 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8464 config->mode_changed = true;
8465 }
8466 }
8467 /* connector->new_encoder is now updated for all connectors. */
8468
8469 /* Update crtc of enabled connectors. */
8470 count = 0;
8471 list_for_each_entry(connector, &dev->mode_config.connector_list,
8472 base.head) {
8473 if (!connector->new_encoder)
8474 continue;
8475
8476 new_crtc = connector->new_encoder->base.crtc;
8477
8478 for (ro = 0; ro < set->num_connectors; ro++) {
8479 if (set->connectors[ro] == &connector->base)
8480 new_crtc = set->crtc;
8481 }
8482
8483 /* Make sure the new CRTC will work with the encoder */
8484 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8485 new_crtc)) {
8486 return -EINVAL;
8487 }
8488 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8489
8490 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8491 connector->base.base.id,
8492 drm_get_connector_name(&connector->base),
8493 new_crtc->base.id);
8494 }
8495
8496 /* Check for any encoders that needs to be disabled. */
8497 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8498 base.head) {
8499 list_for_each_entry(connector,
8500 &dev->mode_config.connector_list,
8501 base.head) {
8502 if (connector->new_encoder == encoder) {
8503 WARN_ON(!connector->new_encoder->new_crtc);
8504
8505 goto next_encoder;
8506 }
8507 }
8508 encoder->new_crtc = NULL;
8509 next_encoder:
8510 /* Only now check for crtc changes so we don't miss encoders
8511 * that will be disabled. */
8512 if (&encoder->new_crtc->base != encoder->base.crtc) {
8513 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8514 config->mode_changed = true;
8515 }
8516 }
8517 /* Now we've also updated encoder->new_crtc for all encoders. */
8518
8519 return 0;
8520 }
8521
8522 static int intel_crtc_set_config(struct drm_mode_set *set)
8523 {
8524 struct drm_device *dev;
8525 struct drm_mode_set save_set;
8526 struct intel_set_config *config;
8527 int ret;
8528
8529 BUG_ON(!set);
8530 BUG_ON(!set->crtc);
8531 BUG_ON(!set->crtc->helper_private);
8532
8533 /* Enforce sane interface api - has been abused by the fb helper. */
8534 BUG_ON(!set->mode && set->fb);
8535 BUG_ON(set->fb && set->num_connectors == 0);
8536
8537 if (set->fb) {
8538 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8539 set->crtc->base.id, set->fb->base.id,
8540 (int)set->num_connectors, set->x, set->y);
8541 } else {
8542 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8543 }
8544
8545 dev = set->crtc->dev;
8546
8547 ret = -ENOMEM;
8548 config = kzalloc(sizeof(*config), GFP_KERNEL);
8549 if (!config)
8550 goto out_config;
8551
8552 ret = intel_set_config_save_state(dev, config);
8553 if (ret)
8554 goto out_config;
8555
8556 save_set.crtc = set->crtc;
8557 save_set.mode = &set->crtc->mode;
8558 save_set.x = set->crtc->x;
8559 save_set.y = set->crtc->y;
8560 save_set.fb = set->crtc->fb;
8561
8562 /* Compute whether we need a full modeset, only an fb base update or no
8563 * change at all. In the future we might also check whether only the
8564 * mode changed, e.g. for LVDS where we only change the panel fitter in
8565 * such cases. */
8566 intel_set_config_compute_mode_changes(set, config);
8567
8568 ret = intel_modeset_stage_output_state(dev, set, config);
8569 if (ret)
8570 goto fail;
8571
8572 if (config->mode_changed) {
8573 ret = intel_set_mode(set->crtc, set->mode,
8574 set->x, set->y, set->fb);
8575 if (ret) {
8576 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8577 set->crtc->base.id, ret);
8578 goto fail;
8579 }
8580 } else if (config->fb_changed) {
8581 intel_crtc_wait_for_pending_flips(set->crtc);
8582
8583 ret = intel_pipe_set_base(set->crtc,
8584 set->x, set->y, set->fb);
8585 }
8586
8587 intel_set_config_free(config);
8588
8589 return 0;
8590
8591 fail:
8592 intel_set_config_restore_state(dev, config);
8593
8594 /* Try to restore the config */
8595 if (config->mode_changed &&
8596 intel_set_mode(save_set.crtc, save_set.mode,
8597 save_set.x, save_set.y, save_set.fb))
8598 DRM_ERROR("failed to restore config after modeset failure\n");
8599
8600 out_config:
8601 intel_set_config_free(config);
8602 return ret;
8603 }
8604
8605 static const struct drm_crtc_funcs intel_crtc_funcs = {
8606 .cursor_set = intel_crtc_cursor_set,
8607 .cursor_move = intel_crtc_cursor_move,
8608 .gamma_set = intel_crtc_gamma_set,
8609 .set_config = intel_crtc_set_config,
8610 .destroy = intel_crtc_destroy,
8611 .page_flip = intel_crtc_page_flip,
8612 };
8613
8614 static void intel_cpu_pll_init(struct drm_device *dev)
8615 {
8616 if (HAS_DDI(dev))
8617 intel_ddi_pll_init(dev);
8618 }
8619
8620 static void intel_pch_pll_init(struct drm_device *dev)
8621 {
8622 drm_i915_private_t *dev_priv = dev->dev_private;
8623 int i;
8624
8625 if (dev_priv->num_pch_pll == 0) {
8626 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8627 return;
8628 }
8629
8630 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8631 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8632 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8633 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8634 }
8635 }
8636
8637 static void intel_crtc_init(struct drm_device *dev, int pipe)
8638 {
8639 drm_i915_private_t *dev_priv = dev->dev_private;
8640 struct intel_crtc *intel_crtc;
8641 int i;
8642
8643 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8644 if (intel_crtc == NULL)
8645 return;
8646
8647 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8648
8649 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8650 for (i = 0; i < 256; i++) {
8651 intel_crtc->lut_r[i] = i;
8652 intel_crtc->lut_g[i] = i;
8653 intel_crtc->lut_b[i] = i;
8654 }
8655
8656 /* Swap pipes & planes for FBC on pre-965 */
8657 intel_crtc->pipe = pipe;
8658 intel_crtc->plane = pipe;
8659 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8660 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8661 intel_crtc->plane = !pipe;
8662 }
8663
8664 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8665 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8666 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8667 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8668
8669 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8670 }
8671
8672 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8673 struct drm_file *file)
8674 {
8675 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8676 struct drm_mode_object *drmmode_obj;
8677 struct intel_crtc *crtc;
8678
8679 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8680 return -ENODEV;
8681
8682 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8683 DRM_MODE_OBJECT_CRTC);
8684
8685 if (!drmmode_obj) {
8686 DRM_ERROR("no such CRTC id\n");
8687 return -EINVAL;
8688 }
8689
8690 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8691 pipe_from_crtc_id->pipe = crtc->pipe;
8692
8693 return 0;
8694 }
8695
8696 static int intel_encoder_clones(struct intel_encoder *encoder)
8697 {
8698 struct drm_device *dev = encoder->base.dev;
8699 struct intel_encoder *source_encoder;
8700 int index_mask = 0;
8701 int entry = 0;
8702
8703 list_for_each_entry(source_encoder,
8704 &dev->mode_config.encoder_list, base.head) {
8705
8706 if (encoder == source_encoder)
8707 index_mask |= (1 << entry);
8708
8709 /* Intel hw has only one MUX where enocoders could be cloned. */
8710 if (encoder->cloneable && source_encoder->cloneable)
8711 index_mask |= (1 << entry);
8712
8713 entry++;
8714 }
8715
8716 return index_mask;
8717 }
8718
8719 static bool has_edp_a(struct drm_device *dev)
8720 {
8721 struct drm_i915_private *dev_priv = dev->dev_private;
8722
8723 if (!IS_MOBILE(dev))
8724 return false;
8725
8726 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8727 return false;
8728
8729 if (IS_GEN5(dev) &&
8730 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8731 return false;
8732
8733 return true;
8734 }
8735
8736 static void intel_setup_outputs(struct drm_device *dev)
8737 {
8738 struct drm_i915_private *dev_priv = dev->dev_private;
8739 struct intel_encoder *encoder;
8740 bool dpd_is_edp = false;
8741 bool has_lvds;
8742
8743 has_lvds = intel_lvds_init(dev);
8744 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8745 /* disable the panel fitter on everything but LVDS */
8746 I915_WRITE(PFIT_CONTROL, 0);
8747 }
8748
8749 if (!IS_ULT(dev))
8750 intel_crt_init(dev);
8751
8752 if (HAS_DDI(dev)) {
8753 int found;
8754
8755 /* Haswell uses DDI functions to detect digital outputs */
8756 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8757 /* DDI A only supports eDP */
8758 if (found)
8759 intel_ddi_init(dev, PORT_A);
8760
8761 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8762 * register */
8763 found = I915_READ(SFUSE_STRAP);
8764
8765 if (found & SFUSE_STRAP_DDIB_DETECTED)
8766 intel_ddi_init(dev, PORT_B);
8767 if (found & SFUSE_STRAP_DDIC_DETECTED)
8768 intel_ddi_init(dev, PORT_C);
8769 if (found & SFUSE_STRAP_DDID_DETECTED)
8770 intel_ddi_init(dev, PORT_D);
8771 } else if (HAS_PCH_SPLIT(dev)) {
8772 int found;
8773 dpd_is_edp = intel_dpd_is_edp(dev);
8774
8775 if (has_edp_a(dev))
8776 intel_dp_init(dev, DP_A, PORT_A);
8777
8778 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8779 /* PCH SDVOB multiplex with HDMIB */
8780 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8781 if (!found)
8782 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8783 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8784 intel_dp_init(dev, PCH_DP_B, PORT_B);
8785 }
8786
8787 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8788 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8789
8790 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8791 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8792
8793 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8794 intel_dp_init(dev, PCH_DP_C, PORT_C);
8795
8796 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8797 intel_dp_init(dev, PCH_DP_D, PORT_D);
8798 } else if (IS_VALLEYVIEW(dev)) {
8799 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8800 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8801 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8802
8803 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8804 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8805 PORT_B);
8806 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8807 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8808 }
8809 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8810 bool found = false;
8811
8812 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8813 DRM_DEBUG_KMS("probing SDVOB\n");
8814 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8815 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8816 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8817 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8818 }
8819
8820 if (!found && SUPPORTS_INTEGRATED_DP(dev))
8821 intel_dp_init(dev, DP_B, PORT_B);
8822 }
8823
8824 /* Before G4X SDVOC doesn't have its own detect register */
8825
8826 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8827 DRM_DEBUG_KMS("probing SDVOC\n");
8828 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8829 }
8830
8831 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8832
8833 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8834 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8835 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8836 }
8837 if (SUPPORTS_INTEGRATED_DP(dev))
8838 intel_dp_init(dev, DP_C, PORT_C);
8839 }
8840
8841 if (SUPPORTS_INTEGRATED_DP(dev) &&
8842 (I915_READ(DP_D) & DP_DETECTED))
8843 intel_dp_init(dev, DP_D, PORT_D);
8844 } else if (IS_GEN2(dev))
8845 intel_dvo_init(dev);
8846
8847 if (SUPPORTS_TV(dev))
8848 intel_tv_init(dev);
8849
8850 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8851 encoder->base.possible_crtcs = encoder->crtc_mask;
8852 encoder->base.possible_clones =
8853 intel_encoder_clones(encoder);
8854 }
8855
8856 intel_init_pch_refclk(dev);
8857
8858 drm_helper_move_panel_connectors_to_head(dev);
8859 }
8860
8861 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8862 {
8863 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8864
8865 drm_framebuffer_cleanup(fb);
8866 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8867
8868 kfree(intel_fb);
8869 }
8870
8871 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8872 struct drm_file *file,
8873 unsigned int *handle)
8874 {
8875 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8876 struct drm_i915_gem_object *obj = intel_fb->obj;
8877
8878 return drm_gem_handle_create(file, &obj->base, handle);
8879 }
8880
8881 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8882 .destroy = intel_user_framebuffer_destroy,
8883 .create_handle = intel_user_framebuffer_create_handle,
8884 };
8885
8886 int intel_framebuffer_init(struct drm_device *dev,
8887 struct intel_framebuffer *intel_fb,
8888 struct drm_mode_fb_cmd2 *mode_cmd,
8889 struct drm_i915_gem_object *obj)
8890 {
8891 int ret;
8892
8893 if (obj->tiling_mode == I915_TILING_Y) {
8894 DRM_DEBUG("hardware does not support tiling Y\n");
8895 return -EINVAL;
8896 }
8897
8898 if (mode_cmd->pitches[0] & 63) {
8899 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8900 mode_cmd->pitches[0]);
8901 return -EINVAL;
8902 }
8903
8904 /* FIXME <= Gen4 stride limits are bit unclear */
8905 if (mode_cmd->pitches[0] > 32768) {
8906 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8907 mode_cmd->pitches[0]);
8908 return -EINVAL;
8909 }
8910
8911 if (obj->tiling_mode != I915_TILING_NONE &&
8912 mode_cmd->pitches[0] != obj->stride) {
8913 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8914 mode_cmd->pitches[0], obj->stride);
8915 return -EINVAL;
8916 }
8917
8918 /* Reject formats not supported by any plane early. */
8919 switch (mode_cmd->pixel_format) {
8920 case DRM_FORMAT_C8:
8921 case DRM_FORMAT_RGB565:
8922 case DRM_FORMAT_XRGB8888:
8923 case DRM_FORMAT_ARGB8888:
8924 break;
8925 case DRM_FORMAT_XRGB1555:
8926 case DRM_FORMAT_ARGB1555:
8927 if (INTEL_INFO(dev)->gen > 3) {
8928 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8929 return -EINVAL;
8930 }
8931 break;
8932 case DRM_FORMAT_XBGR8888:
8933 case DRM_FORMAT_ABGR8888:
8934 case DRM_FORMAT_XRGB2101010:
8935 case DRM_FORMAT_ARGB2101010:
8936 case DRM_FORMAT_XBGR2101010:
8937 case DRM_FORMAT_ABGR2101010:
8938 if (INTEL_INFO(dev)->gen < 4) {
8939 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8940 return -EINVAL;
8941 }
8942 break;
8943 case DRM_FORMAT_YUYV:
8944 case DRM_FORMAT_UYVY:
8945 case DRM_FORMAT_YVYU:
8946 case DRM_FORMAT_VYUY:
8947 if (INTEL_INFO(dev)->gen < 5) {
8948 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8949 return -EINVAL;
8950 }
8951 break;
8952 default:
8953 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8954 return -EINVAL;
8955 }
8956
8957 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8958 if (mode_cmd->offsets[0] != 0)
8959 return -EINVAL;
8960
8961 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8962 intel_fb->obj = obj;
8963
8964 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8965 if (ret) {
8966 DRM_ERROR("framebuffer init failed %d\n", ret);
8967 return ret;
8968 }
8969
8970 return 0;
8971 }
8972
8973 static struct drm_framebuffer *
8974 intel_user_framebuffer_create(struct drm_device *dev,
8975 struct drm_file *filp,
8976 struct drm_mode_fb_cmd2 *mode_cmd)
8977 {
8978 struct drm_i915_gem_object *obj;
8979
8980 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8981 mode_cmd->handles[0]));
8982 if (&obj->base == NULL)
8983 return ERR_PTR(-ENOENT);
8984
8985 return intel_framebuffer_create(dev, mode_cmd, obj);
8986 }
8987
8988 static const struct drm_mode_config_funcs intel_mode_funcs = {
8989 .fb_create = intel_user_framebuffer_create,
8990 .output_poll_changed = intel_fb_output_poll_changed,
8991 };
8992
8993 /* Set up chip specific display functions */
8994 static void intel_init_display(struct drm_device *dev)
8995 {
8996 struct drm_i915_private *dev_priv = dev->dev_private;
8997
8998 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
8999 dev_priv->display.find_dpll = g4x_find_best_dpll;
9000 else if (IS_VALLEYVIEW(dev))
9001 dev_priv->display.find_dpll = vlv_find_best_dpll;
9002 else if (IS_PINEVIEW(dev))
9003 dev_priv->display.find_dpll = pnv_find_best_dpll;
9004 else
9005 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9006
9007 if (HAS_DDI(dev)) {
9008 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9009 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9010 dev_priv->display.crtc_enable = haswell_crtc_enable;
9011 dev_priv->display.crtc_disable = haswell_crtc_disable;
9012 dev_priv->display.off = haswell_crtc_off;
9013 dev_priv->display.update_plane = ironlake_update_plane;
9014 } else if (HAS_PCH_SPLIT(dev)) {
9015 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9016 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9017 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9018 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9019 dev_priv->display.off = ironlake_crtc_off;
9020 dev_priv->display.update_plane = ironlake_update_plane;
9021 } else if (IS_VALLEYVIEW(dev)) {
9022 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9023 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9024 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9025 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9026 dev_priv->display.off = i9xx_crtc_off;
9027 dev_priv->display.update_plane = i9xx_update_plane;
9028 } else {
9029 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9030 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9031 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9032 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9033 dev_priv->display.off = i9xx_crtc_off;
9034 dev_priv->display.update_plane = i9xx_update_plane;
9035 }
9036
9037 /* Returns the core display clock speed */
9038 if (IS_VALLEYVIEW(dev))
9039 dev_priv->display.get_display_clock_speed =
9040 valleyview_get_display_clock_speed;
9041 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9042 dev_priv->display.get_display_clock_speed =
9043 i945_get_display_clock_speed;
9044 else if (IS_I915G(dev))
9045 dev_priv->display.get_display_clock_speed =
9046 i915_get_display_clock_speed;
9047 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9048 dev_priv->display.get_display_clock_speed =
9049 i9xx_misc_get_display_clock_speed;
9050 else if (IS_I915GM(dev))
9051 dev_priv->display.get_display_clock_speed =
9052 i915gm_get_display_clock_speed;
9053 else if (IS_I865G(dev))
9054 dev_priv->display.get_display_clock_speed =
9055 i865_get_display_clock_speed;
9056 else if (IS_I85X(dev))
9057 dev_priv->display.get_display_clock_speed =
9058 i855_get_display_clock_speed;
9059 else /* 852, 830 */
9060 dev_priv->display.get_display_clock_speed =
9061 i830_get_display_clock_speed;
9062
9063 if (HAS_PCH_SPLIT(dev)) {
9064 if (IS_GEN5(dev)) {
9065 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9066 dev_priv->display.write_eld = ironlake_write_eld;
9067 } else if (IS_GEN6(dev)) {
9068 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9069 dev_priv->display.write_eld = ironlake_write_eld;
9070 } else if (IS_IVYBRIDGE(dev)) {
9071 /* FIXME: detect B0+ stepping and use auto training */
9072 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9073 dev_priv->display.write_eld = ironlake_write_eld;
9074 dev_priv->display.modeset_global_resources =
9075 ivb_modeset_global_resources;
9076 } else if (IS_HASWELL(dev)) {
9077 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9078 dev_priv->display.write_eld = haswell_write_eld;
9079 dev_priv->display.modeset_global_resources =
9080 haswell_modeset_global_resources;
9081 }
9082 } else if (IS_G4X(dev)) {
9083 dev_priv->display.write_eld = g4x_write_eld;
9084 }
9085
9086 /* Default just returns -ENODEV to indicate unsupported */
9087 dev_priv->display.queue_flip = intel_default_queue_flip;
9088
9089 switch (INTEL_INFO(dev)->gen) {
9090 case 2:
9091 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9092 break;
9093
9094 case 3:
9095 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9096 break;
9097
9098 case 4:
9099 case 5:
9100 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9101 break;
9102
9103 case 6:
9104 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9105 break;
9106 case 7:
9107 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9108 break;
9109 }
9110 }
9111
9112 /*
9113 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9114 * resume, or other times. This quirk makes sure that's the case for
9115 * affected systems.
9116 */
9117 static void quirk_pipea_force(struct drm_device *dev)
9118 {
9119 struct drm_i915_private *dev_priv = dev->dev_private;
9120
9121 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9122 DRM_INFO("applying pipe a force quirk\n");
9123 }
9124
9125 /*
9126 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9127 */
9128 static void quirk_ssc_force_disable(struct drm_device *dev)
9129 {
9130 struct drm_i915_private *dev_priv = dev->dev_private;
9131 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9132 DRM_INFO("applying lvds SSC disable quirk\n");
9133 }
9134
9135 /*
9136 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9137 * brightness value
9138 */
9139 static void quirk_invert_brightness(struct drm_device *dev)
9140 {
9141 struct drm_i915_private *dev_priv = dev->dev_private;
9142 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9143 DRM_INFO("applying inverted panel brightness quirk\n");
9144 }
9145
9146 struct intel_quirk {
9147 int device;
9148 int subsystem_vendor;
9149 int subsystem_device;
9150 void (*hook)(struct drm_device *dev);
9151 };
9152
9153 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9154 struct intel_dmi_quirk {
9155 void (*hook)(struct drm_device *dev);
9156 const struct dmi_system_id (*dmi_id_list)[];
9157 };
9158
9159 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9160 {
9161 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9162 return 1;
9163 }
9164
9165 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9166 {
9167 .dmi_id_list = &(const struct dmi_system_id[]) {
9168 {
9169 .callback = intel_dmi_reverse_brightness,
9170 .ident = "NCR Corporation",
9171 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9172 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9173 },
9174 },
9175 { } /* terminating entry */
9176 },
9177 .hook = quirk_invert_brightness,
9178 },
9179 };
9180
9181 static struct intel_quirk intel_quirks[] = {
9182 /* HP Mini needs pipe A force quirk (LP: #322104) */
9183 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9184
9185 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9186 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9187
9188 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9189 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9190
9191 /* 830/845 need to leave pipe A & dpll A up */
9192 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9193 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9194
9195 /* Lenovo U160 cannot use SSC on LVDS */
9196 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9197
9198 /* Sony Vaio Y cannot use SSC on LVDS */
9199 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9200
9201 /* Acer Aspire 5734Z must invert backlight brightness */
9202 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9203
9204 /* Acer/eMachines G725 */
9205 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9206
9207 /* Acer/eMachines e725 */
9208 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9209
9210 /* Acer/Packard Bell NCL20 */
9211 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9212
9213 /* Acer Aspire 4736Z */
9214 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9215 };
9216
9217 static void intel_init_quirks(struct drm_device *dev)
9218 {
9219 struct pci_dev *d = dev->pdev;
9220 int i;
9221
9222 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9223 struct intel_quirk *q = &intel_quirks[i];
9224
9225 if (d->device == q->device &&
9226 (d->subsystem_vendor == q->subsystem_vendor ||
9227 q->subsystem_vendor == PCI_ANY_ID) &&
9228 (d->subsystem_device == q->subsystem_device ||
9229 q->subsystem_device == PCI_ANY_ID))
9230 q->hook(dev);
9231 }
9232 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9233 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9234 intel_dmi_quirks[i].hook(dev);
9235 }
9236 }
9237
9238 /* Disable the VGA plane that we never use */
9239 static void i915_disable_vga(struct drm_device *dev)
9240 {
9241 struct drm_i915_private *dev_priv = dev->dev_private;
9242 u8 sr1;
9243 u32 vga_reg = i915_vgacntrl_reg(dev);
9244
9245 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9246 outb(SR01, VGA_SR_INDEX);
9247 sr1 = inb(VGA_SR_DATA);
9248 outb(sr1 | 1<<5, VGA_SR_DATA);
9249 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9250 udelay(300);
9251
9252 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9253 POSTING_READ(vga_reg);
9254 }
9255
9256 void intel_modeset_init_hw(struct drm_device *dev)
9257 {
9258 intel_init_power_well(dev);
9259
9260 intel_prepare_ddi(dev);
9261
9262 intel_init_clock_gating(dev);
9263
9264 mutex_lock(&dev->struct_mutex);
9265 intel_enable_gt_powersave(dev);
9266 mutex_unlock(&dev->struct_mutex);
9267 }
9268
9269 void intel_modeset_suspend_hw(struct drm_device *dev)
9270 {
9271 intel_suspend_hw(dev);
9272 }
9273
9274 void intel_modeset_init(struct drm_device *dev)
9275 {
9276 struct drm_i915_private *dev_priv = dev->dev_private;
9277 int i, j, ret;
9278
9279 drm_mode_config_init(dev);
9280
9281 dev->mode_config.min_width = 0;
9282 dev->mode_config.min_height = 0;
9283
9284 dev->mode_config.preferred_depth = 24;
9285 dev->mode_config.prefer_shadow = 1;
9286
9287 dev->mode_config.funcs = &intel_mode_funcs;
9288
9289 intel_init_quirks(dev);
9290
9291 intel_init_pm(dev);
9292
9293 if (INTEL_INFO(dev)->num_pipes == 0)
9294 return;
9295
9296 intel_init_display(dev);
9297
9298 if (IS_GEN2(dev)) {
9299 dev->mode_config.max_width = 2048;
9300 dev->mode_config.max_height = 2048;
9301 } else if (IS_GEN3(dev)) {
9302 dev->mode_config.max_width = 4096;
9303 dev->mode_config.max_height = 4096;
9304 } else {
9305 dev->mode_config.max_width = 8192;
9306 dev->mode_config.max_height = 8192;
9307 }
9308 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9309
9310 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9311 INTEL_INFO(dev)->num_pipes,
9312 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9313
9314 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9315 intel_crtc_init(dev, i);
9316 for (j = 0; j < dev_priv->num_plane; j++) {
9317 ret = intel_plane_init(dev, i, j);
9318 if (ret)
9319 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9320 pipe_name(i), sprite_name(i, j), ret);
9321 }
9322 }
9323
9324 intel_cpu_pll_init(dev);
9325 intel_pch_pll_init(dev);
9326
9327 /* Just disable it once at startup */
9328 i915_disable_vga(dev);
9329 intel_setup_outputs(dev);
9330
9331 /* Just in case the BIOS is doing something questionable. */
9332 intel_disable_fbc(dev);
9333 }
9334
9335 static void
9336 intel_connector_break_all_links(struct intel_connector *connector)
9337 {
9338 connector->base.dpms = DRM_MODE_DPMS_OFF;
9339 connector->base.encoder = NULL;
9340 connector->encoder->connectors_active = false;
9341 connector->encoder->base.crtc = NULL;
9342 }
9343
9344 static void intel_enable_pipe_a(struct drm_device *dev)
9345 {
9346 struct intel_connector *connector;
9347 struct drm_connector *crt = NULL;
9348 struct intel_load_detect_pipe load_detect_temp;
9349
9350 /* We can't just switch on the pipe A, we need to set things up with a
9351 * proper mode and output configuration. As a gross hack, enable pipe A
9352 * by enabling the load detect pipe once. */
9353 list_for_each_entry(connector,
9354 &dev->mode_config.connector_list,
9355 base.head) {
9356 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9357 crt = &connector->base;
9358 break;
9359 }
9360 }
9361
9362 if (!crt)
9363 return;
9364
9365 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9366 intel_release_load_detect_pipe(crt, &load_detect_temp);
9367
9368
9369 }
9370
9371 static bool
9372 intel_check_plane_mapping(struct intel_crtc *crtc)
9373 {
9374 struct drm_device *dev = crtc->base.dev;
9375 struct drm_i915_private *dev_priv = dev->dev_private;
9376 u32 reg, val;
9377
9378 if (INTEL_INFO(dev)->num_pipes == 1)
9379 return true;
9380
9381 reg = DSPCNTR(!crtc->plane);
9382 val = I915_READ(reg);
9383
9384 if ((val & DISPLAY_PLANE_ENABLE) &&
9385 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9386 return false;
9387
9388 return true;
9389 }
9390
9391 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9392 {
9393 struct drm_device *dev = crtc->base.dev;
9394 struct drm_i915_private *dev_priv = dev->dev_private;
9395 u32 reg;
9396
9397 /* Clear any frame start delays used for debugging left by the BIOS */
9398 reg = PIPECONF(crtc->config.cpu_transcoder);
9399 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9400
9401 /* We need to sanitize the plane -> pipe mapping first because this will
9402 * disable the crtc (and hence change the state) if it is wrong. Note
9403 * that gen4+ has a fixed plane -> pipe mapping. */
9404 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9405 struct intel_connector *connector;
9406 bool plane;
9407
9408 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9409 crtc->base.base.id);
9410
9411 /* Pipe has the wrong plane attached and the plane is active.
9412 * Temporarily change the plane mapping and disable everything
9413 * ... */
9414 plane = crtc->plane;
9415 crtc->plane = !plane;
9416 dev_priv->display.crtc_disable(&crtc->base);
9417 crtc->plane = plane;
9418
9419 /* ... and break all links. */
9420 list_for_each_entry(connector, &dev->mode_config.connector_list,
9421 base.head) {
9422 if (connector->encoder->base.crtc != &crtc->base)
9423 continue;
9424
9425 intel_connector_break_all_links(connector);
9426 }
9427
9428 WARN_ON(crtc->active);
9429 crtc->base.enabled = false;
9430 }
9431
9432 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9433 crtc->pipe == PIPE_A && !crtc->active) {
9434 /* BIOS forgot to enable pipe A, this mostly happens after
9435 * resume. Force-enable the pipe to fix this, the update_dpms
9436 * call below we restore the pipe to the right state, but leave
9437 * the required bits on. */
9438 intel_enable_pipe_a(dev);
9439 }
9440
9441 /* Adjust the state of the output pipe according to whether we
9442 * have active connectors/encoders. */
9443 intel_crtc_update_dpms(&crtc->base);
9444
9445 if (crtc->active != crtc->base.enabled) {
9446 struct intel_encoder *encoder;
9447
9448 /* This can happen either due to bugs in the get_hw_state
9449 * functions or because the pipe is force-enabled due to the
9450 * pipe A quirk. */
9451 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9452 crtc->base.base.id,
9453 crtc->base.enabled ? "enabled" : "disabled",
9454 crtc->active ? "enabled" : "disabled");
9455
9456 crtc->base.enabled = crtc->active;
9457
9458 /* Because we only establish the connector -> encoder ->
9459 * crtc links if something is active, this means the
9460 * crtc is now deactivated. Break the links. connector
9461 * -> encoder links are only establish when things are
9462 * actually up, hence no need to break them. */
9463 WARN_ON(crtc->active);
9464
9465 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9466 WARN_ON(encoder->connectors_active);
9467 encoder->base.crtc = NULL;
9468 }
9469 }
9470 }
9471
9472 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9473 {
9474 struct intel_connector *connector;
9475 struct drm_device *dev = encoder->base.dev;
9476
9477 /* We need to check both for a crtc link (meaning that the
9478 * encoder is active and trying to read from a pipe) and the
9479 * pipe itself being active. */
9480 bool has_active_crtc = encoder->base.crtc &&
9481 to_intel_crtc(encoder->base.crtc)->active;
9482
9483 if (encoder->connectors_active && !has_active_crtc) {
9484 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9485 encoder->base.base.id,
9486 drm_get_encoder_name(&encoder->base));
9487
9488 /* Connector is active, but has no active pipe. This is
9489 * fallout from our resume register restoring. Disable
9490 * the encoder manually again. */
9491 if (encoder->base.crtc) {
9492 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9493 encoder->base.base.id,
9494 drm_get_encoder_name(&encoder->base));
9495 encoder->disable(encoder);
9496 }
9497
9498 /* Inconsistent output/port/pipe state happens presumably due to
9499 * a bug in one of the get_hw_state functions. Or someplace else
9500 * in our code, like the register restore mess on resume. Clamp
9501 * things to off as a safer default. */
9502 list_for_each_entry(connector,
9503 &dev->mode_config.connector_list,
9504 base.head) {
9505 if (connector->encoder != encoder)
9506 continue;
9507
9508 intel_connector_break_all_links(connector);
9509 }
9510 }
9511 /* Enabled encoders without active connectors will be fixed in
9512 * the crtc fixup. */
9513 }
9514
9515 void i915_redisable_vga(struct drm_device *dev)
9516 {
9517 struct drm_i915_private *dev_priv = dev->dev_private;
9518 u32 vga_reg = i915_vgacntrl_reg(dev);
9519
9520 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9521 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9522 i915_disable_vga(dev);
9523 }
9524 }
9525
9526 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9527 * and i915 state tracking structures. */
9528 void intel_modeset_setup_hw_state(struct drm_device *dev,
9529 bool force_restore)
9530 {
9531 struct drm_i915_private *dev_priv = dev->dev_private;
9532 enum pipe pipe;
9533 struct drm_plane *plane;
9534 struct intel_crtc *crtc;
9535 struct intel_encoder *encoder;
9536 struct intel_connector *connector;
9537
9538 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9539 base.head) {
9540 memset(&crtc->config, 0, sizeof(crtc->config));
9541
9542 crtc->active = dev_priv->display.get_pipe_config(crtc,
9543 &crtc->config);
9544
9545 crtc->base.enabled = crtc->active;
9546
9547 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9548 crtc->base.base.id,
9549 crtc->active ? "enabled" : "disabled");
9550 }
9551
9552 if (HAS_DDI(dev))
9553 intel_ddi_setup_hw_pll_state(dev);
9554
9555 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9556 base.head) {
9557 pipe = 0;
9558
9559 if (encoder->get_hw_state(encoder, &pipe)) {
9560 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9561 encoder->base.crtc = &crtc->base;
9562 if (encoder->get_config)
9563 encoder->get_config(encoder, &crtc->config);
9564 } else {
9565 encoder->base.crtc = NULL;
9566 }
9567
9568 encoder->connectors_active = false;
9569 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9570 encoder->base.base.id,
9571 drm_get_encoder_name(&encoder->base),
9572 encoder->base.crtc ? "enabled" : "disabled",
9573 pipe);
9574 }
9575
9576 list_for_each_entry(connector, &dev->mode_config.connector_list,
9577 base.head) {
9578 if (connector->get_hw_state(connector)) {
9579 connector->base.dpms = DRM_MODE_DPMS_ON;
9580 connector->encoder->connectors_active = true;
9581 connector->base.encoder = &connector->encoder->base;
9582 } else {
9583 connector->base.dpms = DRM_MODE_DPMS_OFF;
9584 connector->base.encoder = NULL;
9585 }
9586 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9587 connector->base.base.id,
9588 drm_get_connector_name(&connector->base),
9589 connector->base.encoder ? "enabled" : "disabled");
9590 }
9591
9592 /* HW state is read out, now we need to sanitize this mess. */
9593 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9594 base.head) {
9595 intel_sanitize_encoder(encoder);
9596 }
9597
9598 for_each_pipe(pipe) {
9599 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9600 intel_sanitize_crtc(crtc);
9601 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9602 }
9603
9604 if (force_restore) {
9605 /*
9606 * We need to use raw interfaces for restoring state to avoid
9607 * checking (bogus) intermediate states.
9608 */
9609 for_each_pipe(pipe) {
9610 struct drm_crtc *crtc =
9611 dev_priv->pipe_to_crtc_mapping[pipe];
9612
9613 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9614 crtc->fb);
9615 }
9616 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9617 intel_plane_restore(plane);
9618
9619 i915_redisable_vga(dev);
9620 } else {
9621 intel_modeset_update_staged_output_state(dev);
9622 }
9623
9624 intel_modeset_check_state(dev);
9625
9626 drm_mode_config_reset(dev);
9627 }
9628
9629 void intel_modeset_gem_init(struct drm_device *dev)
9630 {
9631 intel_modeset_init_hw(dev);
9632
9633 intel_setup_overlay(dev);
9634
9635 intel_modeset_setup_hw_state(dev, false);
9636 }
9637
9638 void intel_modeset_cleanup(struct drm_device *dev)
9639 {
9640 struct drm_i915_private *dev_priv = dev->dev_private;
9641 struct drm_crtc *crtc;
9642 struct intel_crtc *intel_crtc;
9643
9644 /*
9645 * Interrupts and polling as the first thing to avoid creating havoc.
9646 * Too much stuff here (turning of rps, connectors, ...) would
9647 * experience fancy races otherwise.
9648 */
9649 drm_irq_uninstall(dev);
9650 cancel_work_sync(&dev_priv->hotplug_work);
9651 /*
9652 * Due to the hpd irq storm handling the hotplug work can re-arm the
9653 * poll handlers. Hence disable polling after hpd handling is shut down.
9654 */
9655 drm_kms_helper_poll_fini(dev);
9656
9657 mutex_lock(&dev->struct_mutex);
9658
9659 intel_unregister_dsm_handler();
9660
9661 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9662 /* Skip inactive CRTCs */
9663 if (!crtc->fb)
9664 continue;
9665
9666 intel_crtc = to_intel_crtc(crtc);
9667 intel_increase_pllclock(crtc);
9668 }
9669
9670 intel_disable_fbc(dev);
9671
9672 intel_disable_gt_powersave(dev);
9673
9674 ironlake_teardown_rc6(dev);
9675
9676 mutex_unlock(&dev->struct_mutex);
9677
9678 /* flush any delayed tasks or pending work */
9679 flush_scheduled_work();
9680
9681 /* destroy backlight, if any, before the connectors */
9682 intel_panel_destroy_backlight(dev);
9683
9684 drm_mode_config_cleanup(dev);
9685
9686 intel_cleanup_overlay(dev);
9687 }
9688
9689 /*
9690 * Return which encoder is currently attached for connector.
9691 */
9692 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9693 {
9694 return &intel_attached_encoder(connector)->base;
9695 }
9696
9697 void intel_connector_attach_encoder(struct intel_connector *connector,
9698 struct intel_encoder *encoder)
9699 {
9700 connector->encoder = encoder;
9701 drm_mode_connector_attach_encoder(&connector->base,
9702 &encoder->base);
9703 }
9704
9705 /*
9706 * set vga decode state - true == enable VGA decode
9707 */
9708 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9709 {
9710 struct drm_i915_private *dev_priv = dev->dev_private;
9711 u16 gmch_ctrl;
9712
9713 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9714 if (state)
9715 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9716 else
9717 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9718 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9719 return 0;
9720 }
9721
9722 #ifdef CONFIG_DEBUG_FS
9723 #include <linux/seq_file.h>
9724
9725 struct intel_display_error_state {
9726
9727 u32 power_well_driver;
9728
9729 struct intel_cursor_error_state {
9730 u32 control;
9731 u32 position;
9732 u32 base;
9733 u32 size;
9734 } cursor[I915_MAX_PIPES];
9735
9736 struct intel_pipe_error_state {
9737 enum transcoder cpu_transcoder;
9738 u32 conf;
9739 u32 source;
9740
9741 u32 htotal;
9742 u32 hblank;
9743 u32 hsync;
9744 u32 vtotal;
9745 u32 vblank;
9746 u32 vsync;
9747 } pipe[I915_MAX_PIPES];
9748
9749 struct intel_plane_error_state {
9750 u32 control;
9751 u32 stride;
9752 u32 size;
9753 u32 pos;
9754 u32 addr;
9755 u32 surface;
9756 u32 tile_offset;
9757 } plane[I915_MAX_PIPES];
9758 };
9759
9760 struct intel_display_error_state *
9761 intel_display_capture_error_state(struct drm_device *dev)
9762 {
9763 drm_i915_private_t *dev_priv = dev->dev_private;
9764 struct intel_display_error_state *error;
9765 enum transcoder cpu_transcoder;
9766 int i;
9767
9768 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9769 if (error == NULL)
9770 return NULL;
9771
9772 if (HAS_POWER_WELL(dev))
9773 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9774
9775 for_each_pipe(i) {
9776 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9777 error->pipe[i].cpu_transcoder = cpu_transcoder;
9778
9779 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9780 error->cursor[i].control = I915_READ(CURCNTR(i));
9781 error->cursor[i].position = I915_READ(CURPOS(i));
9782 error->cursor[i].base = I915_READ(CURBASE(i));
9783 } else {
9784 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9785 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9786 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9787 }
9788
9789 error->plane[i].control = I915_READ(DSPCNTR(i));
9790 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9791 if (INTEL_INFO(dev)->gen <= 3) {
9792 error->plane[i].size = I915_READ(DSPSIZE(i));
9793 error->plane[i].pos = I915_READ(DSPPOS(i));
9794 }
9795 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9796 error->plane[i].addr = I915_READ(DSPADDR(i));
9797 if (INTEL_INFO(dev)->gen >= 4) {
9798 error->plane[i].surface = I915_READ(DSPSURF(i));
9799 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9800 }
9801
9802 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9803 error->pipe[i].source = I915_READ(PIPESRC(i));
9804 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9805 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9806 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9807 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9808 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9809 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9810 }
9811
9812 /* In the code above we read the registers without checking if the power
9813 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9814 * prevent the next I915_WRITE from detecting it and printing an error
9815 * message. */
9816 if (HAS_POWER_WELL(dev))
9817 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9818
9819 return error;
9820 }
9821
9822 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9823
9824 void
9825 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
9826 struct drm_device *dev,
9827 struct intel_display_error_state *error)
9828 {
9829 int i;
9830
9831 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9832 if (HAS_POWER_WELL(dev))
9833 err_printf(m, "PWR_WELL_CTL2: %08x\n",
9834 error->power_well_driver);
9835 for_each_pipe(i) {
9836 err_printf(m, "Pipe [%d]:\n", i);
9837 err_printf(m, " CPU transcoder: %c\n",
9838 transcoder_name(error->pipe[i].cpu_transcoder));
9839 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9840 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9841 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9842 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9843 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9844 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9845 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9846 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9847
9848 err_printf(m, "Plane [%d]:\n", i);
9849 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9850 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9851 if (INTEL_INFO(dev)->gen <= 3) {
9852 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9853 err_printf(m, " POS: %08x\n", error->plane[i].pos);
9854 }
9855 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9856 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9857 if (INTEL_INFO(dev)->gen >= 4) {
9858 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9859 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9860 }
9861
9862 err_printf(m, "Cursor [%d]:\n", i);
9863 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9864 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9865 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
9866 }
9867 }
9868 #endif
Linux kernel - Deliverables
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