2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/cpufreq.h>
29 #include <linux/module.h>
30 #include <linux/input.h>
31 #include <linux/i2c.h>
32 #include <linux/kernel.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
35 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
40 #include "i915_trace.h"
41 #include "drm_dp_helper.h"
42 #include "drm_crtc_helper.h"
43 #include <linux/dma_remapping.h>
45 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
47 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
48 static void intel_update_watermarks(struct drm_device
*dev
);
49 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
50 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
73 #define INTEL_P2_NUM 2
74 typedef struct intel_limit intel_limit_t
;
76 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
78 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
79 int, int, intel_clock_t
*, intel_clock_t
*);
83 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
86 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
87 int target
, int refclk
, intel_clock_t
*match_clock
,
88 intel_clock_t
*best_clock
);
90 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
91 int target
, int refclk
, intel_clock_t
*match_clock
,
92 intel_clock_t
*best_clock
);
95 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
96 int target
, int refclk
, intel_clock_t
*match_clock
,
97 intel_clock_t
*best_clock
);
99 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
100 int target
, int refclk
, intel_clock_t
*match_clock
,
101 intel_clock_t
*best_clock
);
103 static inline u32
/* units of 100MHz */
104 intel_fdi_link_freq(struct drm_device
*dev
)
107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
108 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
113 static const intel_limit_t intel_limits_i8xx_dvo
= {
114 .dot
= { .min
= 25000, .max
= 350000 },
115 .vco
= { .min
= 930000, .max
= 1400000 },
116 .n
= { .min
= 3, .max
= 16 },
117 .m
= { .min
= 96, .max
= 140 },
118 .m1
= { .min
= 18, .max
= 26 },
119 .m2
= { .min
= 6, .max
= 16 },
120 .p
= { .min
= 4, .max
= 128 },
121 .p1
= { .min
= 2, .max
= 33 },
122 .p2
= { .dot_limit
= 165000,
123 .p2_slow
= 4, .p2_fast
= 2 },
124 .find_pll
= intel_find_best_PLL
,
127 static const intel_limit_t intel_limits_i8xx_lvds
= {
128 .dot
= { .min
= 25000, .max
= 350000 },
129 .vco
= { .min
= 930000, .max
= 1400000 },
130 .n
= { .min
= 3, .max
= 16 },
131 .m
= { .min
= 96, .max
= 140 },
132 .m1
= { .min
= 18, .max
= 26 },
133 .m2
= { .min
= 6, .max
= 16 },
134 .p
= { .min
= 4, .max
= 128 },
135 .p1
= { .min
= 1, .max
= 6 },
136 .p2
= { .dot_limit
= 165000,
137 .p2_slow
= 14, .p2_fast
= 7 },
138 .find_pll
= intel_find_best_PLL
,
141 static const intel_limit_t intel_limits_i9xx_sdvo
= {
142 .dot
= { .min
= 20000, .max
= 400000 },
143 .vco
= { .min
= 1400000, .max
= 2800000 },
144 .n
= { .min
= 1, .max
= 6 },
145 .m
= { .min
= 70, .max
= 120 },
146 .m1
= { .min
= 10, .max
= 22 },
147 .m2
= { .min
= 5, .max
= 9 },
148 .p
= { .min
= 5, .max
= 80 },
149 .p1
= { .min
= 1, .max
= 8 },
150 .p2
= { .dot_limit
= 200000,
151 .p2_slow
= 10, .p2_fast
= 5 },
152 .find_pll
= intel_find_best_PLL
,
155 static const intel_limit_t intel_limits_i9xx_lvds
= {
156 .dot
= { .min
= 20000, .max
= 400000 },
157 .vco
= { .min
= 1400000, .max
= 2800000 },
158 .n
= { .min
= 1, .max
= 6 },
159 .m
= { .min
= 70, .max
= 120 },
160 .m1
= { .min
= 10, .max
= 22 },
161 .m2
= { .min
= 5, .max
= 9 },
162 .p
= { .min
= 7, .max
= 98 },
163 .p1
= { .min
= 1, .max
= 8 },
164 .p2
= { .dot_limit
= 112000,
165 .p2_slow
= 14, .p2_fast
= 7 },
166 .find_pll
= intel_find_best_PLL
,
170 static const intel_limit_t intel_limits_g4x_sdvo
= {
171 .dot
= { .min
= 25000, .max
= 270000 },
172 .vco
= { .min
= 1750000, .max
= 3500000},
173 .n
= { .min
= 1, .max
= 4 },
174 .m
= { .min
= 104, .max
= 138 },
175 .m1
= { .min
= 17, .max
= 23 },
176 .m2
= { .min
= 5, .max
= 11 },
177 .p
= { .min
= 10, .max
= 30 },
178 .p1
= { .min
= 1, .max
= 3},
179 .p2
= { .dot_limit
= 270000,
183 .find_pll
= intel_g4x_find_best_PLL
,
186 static const intel_limit_t intel_limits_g4x_hdmi
= {
187 .dot
= { .min
= 22000, .max
= 400000 },
188 .vco
= { .min
= 1750000, .max
= 3500000},
189 .n
= { .min
= 1, .max
= 4 },
190 .m
= { .min
= 104, .max
= 138 },
191 .m1
= { .min
= 16, .max
= 23 },
192 .m2
= { .min
= 5, .max
= 11 },
193 .p
= { .min
= 5, .max
= 80 },
194 .p1
= { .min
= 1, .max
= 8},
195 .p2
= { .dot_limit
= 165000,
196 .p2_slow
= 10, .p2_fast
= 5 },
197 .find_pll
= intel_g4x_find_best_PLL
,
200 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
201 .dot
= { .min
= 20000, .max
= 115000 },
202 .vco
= { .min
= 1750000, .max
= 3500000 },
203 .n
= { .min
= 1, .max
= 3 },
204 .m
= { .min
= 104, .max
= 138 },
205 .m1
= { .min
= 17, .max
= 23 },
206 .m2
= { .min
= 5, .max
= 11 },
207 .p
= { .min
= 28, .max
= 112 },
208 .p1
= { .min
= 2, .max
= 8 },
209 .p2
= { .dot_limit
= 0,
210 .p2_slow
= 14, .p2_fast
= 14
212 .find_pll
= intel_g4x_find_best_PLL
,
215 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
216 .dot
= { .min
= 80000, .max
= 224000 },
217 .vco
= { .min
= 1750000, .max
= 3500000 },
218 .n
= { .min
= 1, .max
= 3 },
219 .m
= { .min
= 104, .max
= 138 },
220 .m1
= { .min
= 17, .max
= 23 },
221 .m2
= { .min
= 5, .max
= 11 },
222 .p
= { .min
= 14, .max
= 42 },
223 .p1
= { .min
= 2, .max
= 6 },
224 .p2
= { .dot_limit
= 0,
225 .p2_slow
= 7, .p2_fast
= 7
227 .find_pll
= intel_g4x_find_best_PLL
,
230 static const intel_limit_t intel_limits_g4x_display_port
= {
231 .dot
= { .min
= 161670, .max
= 227000 },
232 .vco
= { .min
= 1750000, .max
= 3500000},
233 .n
= { .min
= 1, .max
= 2 },
234 .m
= { .min
= 97, .max
= 108 },
235 .m1
= { .min
= 0x10, .max
= 0x12 },
236 .m2
= { .min
= 0x05, .max
= 0x06 },
237 .p
= { .min
= 10, .max
= 20 },
238 .p1
= { .min
= 1, .max
= 2},
239 .p2
= { .dot_limit
= 0,
240 .p2_slow
= 10, .p2_fast
= 10 },
241 .find_pll
= intel_find_pll_g4x_dp
,
244 static const intel_limit_t intel_limits_pineview_sdvo
= {
245 .dot
= { .min
= 20000, .max
= 400000},
246 .vco
= { .min
= 1700000, .max
= 3500000 },
247 /* Pineview's Ncounter is a ring counter */
248 .n
= { .min
= 3, .max
= 6 },
249 .m
= { .min
= 2, .max
= 256 },
250 /* Pineview only has one combined m divider, which we treat as m2. */
251 .m1
= { .min
= 0, .max
= 0 },
252 .m2
= { .min
= 0, .max
= 254 },
253 .p
= { .min
= 5, .max
= 80 },
254 .p1
= { .min
= 1, .max
= 8 },
255 .p2
= { .dot_limit
= 200000,
256 .p2_slow
= 10, .p2_fast
= 5 },
257 .find_pll
= intel_find_best_PLL
,
260 static const intel_limit_t intel_limits_pineview_lvds
= {
261 .dot
= { .min
= 20000, .max
= 400000 },
262 .vco
= { .min
= 1700000, .max
= 3500000 },
263 .n
= { .min
= 3, .max
= 6 },
264 .m
= { .min
= 2, .max
= 256 },
265 .m1
= { .min
= 0, .max
= 0 },
266 .m2
= { .min
= 0, .max
= 254 },
267 .p
= { .min
= 7, .max
= 112 },
268 .p1
= { .min
= 1, .max
= 8 },
269 .p2
= { .dot_limit
= 112000,
270 .p2_slow
= 14, .p2_fast
= 14 },
271 .find_pll
= intel_find_best_PLL
,
274 /* Ironlake / Sandybridge
276 * We calculate clock using (register_value + 2) for N/M1/M2, so here
277 * the range value for them is (actual_value - 2).
279 static const intel_limit_t intel_limits_ironlake_dac
= {
280 .dot
= { .min
= 25000, .max
= 350000 },
281 .vco
= { .min
= 1760000, .max
= 3510000 },
282 .n
= { .min
= 1, .max
= 5 },
283 .m
= { .min
= 79, .max
= 127 },
284 .m1
= { .min
= 12, .max
= 22 },
285 .m2
= { .min
= 5, .max
= 9 },
286 .p
= { .min
= 5, .max
= 80 },
287 .p1
= { .min
= 1, .max
= 8 },
288 .p2
= { .dot_limit
= 225000,
289 .p2_slow
= 10, .p2_fast
= 5 },
290 .find_pll
= intel_g4x_find_best_PLL
,
293 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
294 .dot
= { .min
= 25000, .max
= 350000 },
295 .vco
= { .min
= 1760000, .max
= 3510000 },
296 .n
= { .min
= 1, .max
= 3 },
297 .m
= { .min
= 79, .max
= 118 },
298 .m1
= { .min
= 12, .max
= 22 },
299 .m2
= { .min
= 5, .max
= 9 },
300 .p
= { .min
= 28, .max
= 112 },
301 .p1
= { .min
= 2, .max
= 8 },
302 .p2
= { .dot_limit
= 225000,
303 .p2_slow
= 14, .p2_fast
= 14 },
304 .find_pll
= intel_g4x_find_best_PLL
,
307 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
308 .dot
= { .min
= 25000, .max
= 350000 },
309 .vco
= { .min
= 1760000, .max
= 3510000 },
310 .n
= { .min
= 1, .max
= 3 },
311 .m
= { .min
= 79, .max
= 127 },
312 .m1
= { .min
= 12, .max
= 22 },
313 .m2
= { .min
= 5, .max
= 9 },
314 .p
= { .min
= 14, .max
= 56 },
315 .p1
= { .min
= 2, .max
= 8 },
316 .p2
= { .dot_limit
= 225000,
317 .p2_slow
= 7, .p2_fast
= 7 },
318 .find_pll
= intel_g4x_find_best_PLL
,
321 /* LVDS 100mhz refclk limits. */
322 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
323 .dot
= { .min
= 25000, .max
= 350000 },
324 .vco
= { .min
= 1760000, .max
= 3510000 },
325 .n
= { .min
= 1, .max
= 2 },
326 .m
= { .min
= 79, .max
= 126 },
327 .m1
= { .min
= 12, .max
= 22 },
328 .m2
= { .min
= 5, .max
= 9 },
329 .p
= { .min
= 28, .max
= 112 },
330 .p1
= { .min
= 2, .max
= 8 },
331 .p2
= { .dot_limit
= 225000,
332 .p2_slow
= 14, .p2_fast
= 14 },
333 .find_pll
= intel_g4x_find_best_PLL
,
336 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
337 .dot
= { .min
= 25000, .max
= 350000 },
338 .vco
= { .min
= 1760000, .max
= 3510000 },
339 .n
= { .min
= 1, .max
= 3 },
340 .m
= { .min
= 79, .max
= 126 },
341 .m1
= { .min
= 12, .max
= 22 },
342 .m2
= { .min
= 5, .max
= 9 },
343 .p
= { .min
= 14, .max
= 42 },
344 .p1
= { .min
= 2, .max
= 6 },
345 .p2
= { .dot_limit
= 225000,
346 .p2_slow
= 7, .p2_fast
= 7 },
347 .find_pll
= intel_g4x_find_best_PLL
,
350 static const intel_limit_t intel_limits_ironlake_display_port
= {
351 .dot
= { .min
= 25000, .max
= 350000 },
352 .vco
= { .min
= 1760000, .max
= 3510000},
353 .n
= { .min
= 1, .max
= 2 },
354 .m
= { .min
= 81, .max
= 90 },
355 .m1
= { .min
= 12, .max
= 22 },
356 .m2
= { .min
= 5, .max
= 9 },
357 .p
= { .min
= 10, .max
= 20 },
358 .p1
= { .min
= 1, .max
= 2},
359 .p2
= { .dot_limit
= 0,
360 .p2_slow
= 10, .p2_fast
= 10 },
361 .find_pll
= intel_find_pll_ironlake_dp
,
364 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
369 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
370 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
371 DRM_ERROR("DPIO idle wait timed out\n");
375 I915_WRITE(DPIO_REG
, reg
);
376 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
378 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
379 DRM_ERROR("DPIO read wait timed out\n");
382 val
= I915_READ(DPIO_DATA
);
385 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
389 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
394 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
395 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
396 DRM_ERROR("DPIO idle wait timed out\n");
400 I915_WRITE(DPIO_DATA
, val
);
401 I915_WRITE(DPIO_REG
, reg
);
402 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
404 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
405 DRM_ERROR("DPIO write wait timed out\n");
408 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
411 static void vlv_init_dpio(struct drm_device
*dev
)
413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
415 /* Reset the DPIO config */
416 I915_WRITE(DPIO_CTL
, 0);
417 POSTING_READ(DPIO_CTL
);
418 I915_WRITE(DPIO_CTL
, 1);
419 POSTING_READ(DPIO_CTL
);
422 static int intel_dual_link_lvds_callback(const struct dmi_system_id
*id
)
424 DRM_INFO("Forcing lvds to dual link mode on %s\n", id
->ident
);
428 static const struct dmi_system_id intel_dual_link_lvds
[] = {
430 .callback
= intel_dual_link_lvds_callback
,
431 .ident
= "Apple MacBook Pro (Core i5/i7 Series)",
433 DMI_MATCH(DMI_SYS_VENDOR
, "Apple Inc."),
434 DMI_MATCH(DMI_PRODUCT_NAME
, "MacBookPro8,2"),
437 { } /* terminating entry */
440 static bool is_dual_link_lvds(struct drm_i915_private
*dev_priv
,
445 /* use the module option value if specified */
446 if (i915_lvds_channel_mode
> 0)
447 return i915_lvds_channel_mode
== 2;
449 if (dmi_check_system(intel_dual_link_lvds
))
452 if (dev_priv
->lvds_val
)
453 val
= dev_priv
->lvds_val
;
455 /* BIOS should set the proper LVDS register value at boot, but
456 * in reality, it doesn't set the value when the lid is closed;
457 * we need to check "the value to be set" in VBT when LVDS
458 * register is uninitialized.
460 val
= I915_READ(reg
);
461 if (!(val
& ~LVDS_DETECTED
))
462 val
= dev_priv
->bios_lvds_val
;
463 dev_priv
->lvds_val
= val
;
465 return (val
& LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
;
468 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
471 struct drm_device
*dev
= crtc
->dev
;
472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
473 const intel_limit_t
*limit
;
475 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
476 if (is_dual_link_lvds(dev_priv
, PCH_LVDS
)) {
477 /* LVDS dual channel */
478 if (refclk
== 100000)
479 limit
= &intel_limits_ironlake_dual_lvds_100m
;
481 limit
= &intel_limits_ironlake_dual_lvds
;
483 if (refclk
== 100000)
484 limit
= &intel_limits_ironlake_single_lvds_100m
;
486 limit
= &intel_limits_ironlake_single_lvds
;
488 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
490 limit
= &intel_limits_ironlake_display_port
;
492 limit
= &intel_limits_ironlake_dac
;
497 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
499 struct drm_device
*dev
= crtc
->dev
;
500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
501 const intel_limit_t
*limit
;
503 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
504 if (is_dual_link_lvds(dev_priv
, LVDS
))
505 /* LVDS with dual channel */
506 limit
= &intel_limits_g4x_dual_channel_lvds
;
508 /* LVDS with dual channel */
509 limit
= &intel_limits_g4x_single_channel_lvds
;
510 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
511 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
512 limit
= &intel_limits_g4x_hdmi
;
513 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
514 limit
= &intel_limits_g4x_sdvo
;
515 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
516 limit
= &intel_limits_g4x_display_port
;
517 } else /* The option is for other outputs */
518 limit
= &intel_limits_i9xx_sdvo
;
523 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
525 struct drm_device
*dev
= crtc
->dev
;
526 const intel_limit_t
*limit
;
528 if (HAS_PCH_SPLIT(dev
))
529 limit
= intel_ironlake_limit(crtc
, refclk
);
530 else if (IS_G4X(dev
)) {
531 limit
= intel_g4x_limit(crtc
);
532 } else if (IS_PINEVIEW(dev
)) {
533 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
534 limit
= &intel_limits_pineview_lvds
;
536 limit
= &intel_limits_pineview_sdvo
;
537 } else if (!IS_GEN2(dev
)) {
538 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
539 limit
= &intel_limits_i9xx_lvds
;
541 limit
= &intel_limits_i9xx_sdvo
;
543 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
544 limit
= &intel_limits_i8xx_lvds
;
546 limit
= &intel_limits_i8xx_dvo
;
551 /* m1 is reserved as 0 in Pineview, n is a ring counter */
552 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
554 clock
->m
= clock
->m2
+ 2;
555 clock
->p
= clock
->p1
* clock
->p2
;
556 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
557 clock
->dot
= clock
->vco
/ clock
->p
;
560 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
562 if (IS_PINEVIEW(dev
)) {
563 pineview_clock(refclk
, clock
);
566 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
567 clock
->p
= clock
->p1
* clock
->p2
;
568 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
569 clock
->dot
= clock
->vco
/ clock
->p
;
573 * Returns whether any output on the specified pipe is of the specified type
575 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
577 struct drm_device
*dev
= crtc
->dev
;
578 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
579 struct intel_encoder
*encoder
;
581 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
582 if (encoder
->base
.crtc
== crtc
&& encoder
->type
== type
)
588 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
590 * Returns whether the given set of divisors are valid for a given refclk with
591 * the given connectors.
594 static bool intel_PLL_is_valid(struct drm_device
*dev
,
595 const intel_limit_t
*limit
,
596 const intel_clock_t
*clock
)
598 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
599 INTELPllInvalid("p1 out of range\n");
600 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
601 INTELPllInvalid("p out of range\n");
602 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
603 INTELPllInvalid("m2 out of range\n");
604 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
605 INTELPllInvalid("m1 out of range\n");
606 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
607 INTELPllInvalid("m1 <= m2\n");
608 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
609 INTELPllInvalid("m out of range\n");
610 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
611 INTELPllInvalid("n out of range\n");
612 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
613 INTELPllInvalid("vco out of range\n");
614 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
615 * connector, etc., rather than just a single range.
617 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
618 INTELPllInvalid("dot out of range\n");
624 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
625 int target
, int refclk
, intel_clock_t
*match_clock
,
626 intel_clock_t
*best_clock
)
629 struct drm_device
*dev
= crtc
->dev
;
630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
634 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
635 (I915_READ(LVDS
)) != 0) {
637 * For LVDS, if the panel is on, just rely on its current
638 * settings for dual-channel. We haven't figured out how to
639 * reliably set up different single/dual channel state, if we
642 if (is_dual_link_lvds(dev_priv
, LVDS
))
643 clock
.p2
= limit
->p2
.p2_fast
;
645 clock
.p2
= limit
->p2
.p2_slow
;
647 if (target
< limit
->p2
.dot_limit
)
648 clock
.p2
= limit
->p2
.p2_slow
;
650 clock
.p2
= limit
->p2
.p2_fast
;
653 memset(best_clock
, 0, sizeof(*best_clock
));
655 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
657 for (clock
.m2
= limit
->m2
.min
;
658 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
659 /* m1 is always 0 in Pineview */
660 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
662 for (clock
.n
= limit
->n
.min
;
663 clock
.n
<= limit
->n
.max
; clock
.n
++) {
664 for (clock
.p1
= limit
->p1
.min
;
665 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
668 intel_clock(dev
, refclk
, &clock
);
669 if (!intel_PLL_is_valid(dev
, limit
,
673 clock
.p
!= match_clock
->p
)
676 this_err
= abs(clock
.dot
- target
);
677 if (this_err
< err
) {
686 return (err
!= target
);
690 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
691 int target
, int refclk
, intel_clock_t
*match_clock
,
692 intel_clock_t
*best_clock
)
694 struct drm_device
*dev
= crtc
->dev
;
695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
699 /* approximately equals target * 0.00585 */
700 int err_most
= (target
>> 8) + (target
>> 9);
703 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
706 if (HAS_PCH_SPLIT(dev
))
710 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
712 clock
.p2
= limit
->p2
.p2_fast
;
714 clock
.p2
= limit
->p2
.p2_slow
;
716 if (target
< limit
->p2
.dot_limit
)
717 clock
.p2
= limit
->p2
.p2_slow
;
719 clock
.p2
= limit
->p2
.p2_fast
;
722 memset(best_clock
, 0, sizeof(*best_clock
));
723 max_n
= limit
->n
.max
;
724 /* based on hardware requirement, prefer smaller n to precision */
725 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
726 /* based on hardware requirement, prefere larger m1,m2 */
727 for (clock
.m1
= limit
->m1
.max
;
728 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
729 for (clock
.m2
= limit
->m2
.max
;
730 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
731 for (clock
.p1
= limit
->p1
.max
;
732 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
735 intel_clock(dev
, refclk
, &clock
);
736 if (!intel_PLL_is_valid(dev
, limit
,
740 clock
.p
!= match_clock
->p
)
743 this_err
= abs(clock
.dot
- target
);
744 if (this_err
< err_most
) {
758 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
759 int target
, int refclk
, intel_clock_t
*match_clock
,
760 intel_clock_t
*best_clock
)
762 struct drm_device
*dev
= crtc
->dev
;
765 if (target
< 200000) {
778 intel_clock(dev
, refclk
, &clock
);
779 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
783 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
785 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
786 int target
, int refclk
, intel_clock_t
*match_clock
,
787 intel_clock_t
*best_clock
)
790 if (target
< 200000) {
803 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
804 clock
.p
= (clock
.p1
* clock
.p2
);
805 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
807 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
812 * intel_wait_for_vblank - wait for vblank on a given pipe
814 * @pipe: pipe to wait for
816 * Wait for vblank to occur on a given pipe. Needed for various bits of
819 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
822 int pipestat_reg
= PIPESTAT(pipe
);
824 /* Clear existing vblank status. Note this will clear any other
825 * sticky status fields as well.
827 * This races with i915_driver_irq_handler() with the result
828 * that either function could miss a vblank event. Here it is not
829 * fatal, as we will either wait upon the next vblank interrupt or
830 * timeout. Generally speaking intel_wait_for_vblank() is only
831 * called during modeset at which time the GPU should be idle and
832 * should *not* be performing page flips and thus not waiting on
834 * Currently, the result of us stealing a vblank from the irq
835 * handler is that a single frame will be skipped during swapbuffers.
837 I915_WRITE(pipestat_reg
,
838 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
840 /* Wait for vblank interrupt bit to set */
841 if (wait_for(I915_READ(pipestat_reg
) &
842 PIPE_VBLANK_INTERRUPT_STATUS
,
844 DRM_DEBUG_KMS("vblank wait timed out\n");
848 * intel_wait_for_pipe_off - wait for pipe to turn off
850 * @pipe: pipe to wait for
852 * After disabling a pipe, we can't wait for vblank in the usual way,
853 * spinning on the vblank interrupt status bit, since we won't actually
854 * see an interrupt when the pipe is disabled.
857 * wait for the pipe register state bit to turn off
860 * wait for the display line value to settle (it usually
861 * ends up stopping at the start of the next frame).
864 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
868 if (INTEL_INFO(dev
)->gen
>= 4) {
869 int reg
= PIPECONF(pipe
);
871 /* Wait for the Pipe State to go off */
872 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
874 DRM_DEBUG_KMS("pipe_off wait timed out\n");
877 int reg
= PIPEDSL(pipe
);
878 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
880 /* Wait for the display line to settle */
882 last_line
= I915_READ(reg
) & DSL_LINEMASK
;
884 } while (((I915_READ(reg
) & DSL_LINEMASK
) != last_line
) &&
885 time_after(timeout
, jiffies
));
886 if (time_after(jiffies
, timeout
))
887 DRM_DEBUG_KMS("pipe_off wait timed out\n");
891 static const char *state_string(bool enabled
)
893 return enabled
? "on" : "off";
896 /* Only for pre-ILK configs */
897 static void assert_pll(struct drm_i915_private
*dev_priv
,
898 enum pipe pipe
, bool state
)
905 val
= I915_READ(reg
);
906 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
907 WARN(cur_state
!= state
,
908 "PLL state assertion failure (expected %s, current %s)\n",
909 state_string(state
), state_string(cur_state
));
911 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
912 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
915 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
916 enum pipe pipe
, bool state
)
922 if (HAS_PCH_CPT(dev_priv
->dev
)) {
925 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
927 /* Make sure the selected PLL is enabled to the transcoder */
928 WARN(!((pch_dpll
>> (4 * pipe
)) & 8),
929 "transcoder %d PLL not enabled\n", pipe
);
931 /* Convert the transcoder pipe number to a pll pipe number */
932 pipe
= (pch_dpll
>> (4 * pipe
)) & 1;
935 reg
= PCH_DPLL(pipe
);
936 val
= I915_READ(reg
);
937 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
938 WARN(cur_state
!= state
,
939 "PCH PLL state assertion failure (expected %s, current %s)\n",
940 state_string(state
), state_string(cur_state
));
942 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
943 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
945 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
946 enum pipe pipe
, bool state
)
952 reg
= FDI_TX_CTL(pipe
);
953 val
= I915_READ(reg
);
954 cur_state
= !!(val
& FDI_TX_ENABLE
);
955 WARN(cur_state
!= state
,
956 "FDI TX state assertion failure (expected %s, current %s)\n",
957 state_string(state
), state_string(cur_state
));
959 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
960 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
962 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
963 enum pipe pipe
, bool state
)
969 reg
= FDI_RX_CTL(pipe
);
970 val
= I915_READ(reg
);
971 cur_state
= !!(val
& FDI_RX_ENABLE
);
972 WARN(cur_state
!= state
,
973 "FDI RX state assertion failure (expected %s, current %s)\n",
974 state_string(state
), state_string(cur_state
));
976 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
977 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
979 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
985 /* ILK FDI PLL is always enabled */
986 if (dev_priv
->info
->gen
== 5)
989 reg
= FDI_TX_CTL(pipe
);
990 val
= I915_READ(reg
);
991 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
994 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1000 reg
= FDI_RX_CTL(pipe
);
1001 val
= I915_READ(reg
);
1002 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1005 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1008 int pp_reg
, lvds_reg
;
1010 enum pipe panel_pipe
= PIPE_A
;
1013 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1014 pp_reg
= PCH_PP_CONTROL
;
1015 lvds_reg
= PCH_LVDS
;
1017 pp_reg
= PP_CONTROL
;
1021 val
= I915_READ(pp_reg
);
1022 if (!(val
& PANEL_POWER_ON
) ||
1023 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1026 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1027 panel_pipe
= PIPE_B
;
1029 WARN(panel_pipe
== pipe
&& locked
,
1030 "panel assertion failure, pipe %c regs locked\n",
1034 void assert_pipe(struct drm_i915_private
*dev_priv
,
1035 enum pipe pipe
, bool state
)
1041 /* if we need the pipe A quirk it must be always on */
1042 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1045 reg
= PIPECONF(pipe
);
1046 val
= I915_READ(reg
);
1047 cur_state
= !!(val
& PIPECONF_ENABLE
);
1048 WARN(cur_state
!= state
,
1049 "pipe %c assertion failure (expected %s, current %s)\n",
1050 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1053 static void assert_plane(struct drm_i915_private
*dev_priv
,
1054 enum plane plane
, bool state
)
1060 reg
= DSPCNTR(plane
);
1061 val
= I915_READ(reg
);
1062 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1063 WARN(cur_state
!= state
,
1064 "plane %c assertion failure (expected %s, current %s)\n",
1065 plane_name(plane
), state_string(state
), state_string(cur_state
));
1068 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1069 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1071 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1078 /* Planes are fixed to pipes on ILK+ */
1079 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1080 reg
= DSPCNTR(pipe
);
1081 val
= I915_READ(reg
);
1082 WARN((val
& DISPLAY_PLANE_ENABLE
),
1083 "plane %c assertion failure, should be disabled but not\n",
1088 /* Need to check both planes against the pipe */
1089 for (i
= 0; i
< 2; i
++) {
1091 val
= I915_READ(reg
);
1092 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1093 DISPPLANE_SEL_PIPE_SHIFT
;
1094 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1095 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1096 plane_name(i
), pipe_name(pipe
));
1100 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1105 val
= I915_READ(PCH_DREF_CONTROL
);
1106 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1107 DREF_SUPERSPREAD_SOURCE_MASK
));
1108 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1111 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1118 reg
= TRANSCONF(pipe
);
1119 val
= I915_READ(reg
);
1120 enabled
= !!(val
& TRANS_ENABLE
);
1122 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1126 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1127 enum pipe pipe
, u32 port_sel
, u32 val
)
1129 if ((val
& DP_PORT_EN
) == 0)
1132 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1133 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1134 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1135 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1138 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1144 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1145 enum pipe pipe
, u32 val
)
1147 if ((val
& PORT_ENABLE
) == 0)
1150 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1151 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1154 if ((val
& TRANSCODER_MASK
) != TRANSCODER(pipe
))
1160 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1161 enum pipe pipe
, u32 val
)
1163 if ((val
& LVDS_PORT_EN
) == 0)
1166 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1167 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1170 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1176 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1177 enum pipe pipe
, u32 val
)
1179 if ((val
& ADPA_DAC_ENABLE
) == 0)
1181 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1182 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1185 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1191 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1192 enum pipe pipe
, int reg
, u32 port_sel
)
1194 u32 val
= I915_READ(reg
);
1195 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1196 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1197 reg
, pipe_name(pipe
));
1200 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1201 enum pipe pipe
, int reg
)
1203 u32 val
= I915_READ(reg
);
1204 WARN(hdmi_pipe_enabled(dev_priv
, val
, pipe
),
1205 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1206 reg
, pipe_name(pipe
));
1209 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1215 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1216 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1217 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1220 val
= I915_READ(reg
);
1221 WARN(adpa_pipe_enabled(dev_priv
, val
, pipe
),
1222 "PCH VGA enabled on transcoder %c, should be disabled\n",
1226 val
= I915_READ(reg
);
1227 WARN(lvds_pipe_enabled(dev_priv
, val
, pipe
),
1228 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1231 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1232 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1233 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1237 * intel_enable_pll - enable a PLL
1238 * @dev_priv: i915 private structure
1239 * @pipe: pipe PLL to enable
1241 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1242 * make sure the PLL reg is writable first though, since the panel write
1243 * protect mechanism may be enabled.
1245 * Note! This is for pre-ILK only.
1247 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1252 /* No really, not for ILK+ */
1253 BUG_ON(dev_priv
->info
->gen
>= 5);
1255 /* PLL is protected by panel, make sure we can write it */
1256 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1257 assert_panel_unlocked(dev_priv
, pipe
);
1260 val
= I915_READ(reg
);
1261 val
|= DPLL_VCO_ENABLE
;
1263 /* We do this three times for luck */
1264 I915_WRITE(reg
, val
);
1266 udelay(150); /* wait for warmup */
1267 I915_WRITE(reg
, val
);
1269 udelay(150); /* wait for warmup */
1270 I915_WRITE(reg
, val
);
1272 udelay(150); /* wait for warmup */
1276 * intel_disable_pll - disable a PLL
1277 * @dev_priv: i915 private structure
1278 * @pipe: pipe PLL to disable
1280 * Disable the PLL for @pipe, making sure the pipe is off first.
1282 * Note! This is for pre-ILK only.
1284 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1289 /* Don't disable pipe A or pipe A PLLs if needed */
1290 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1293 /* Make sure the pipe isn't still relying on us */
1294 assert_pipe_disabled(dev_priv
, pipe
);
1297 val
= I915_READ(reg
);
1298 val
&= ~DPLL_VCO_ENABLE
;
1299 I915_WRITE(reg
, val
);
1304 * intel_enable_pch_pll - enable PCH PLL
1305 * @dev_priv: i915 private structure
1306 * @pipe: pipe PLL to enable
1308 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1309 * drives the transcoder clock.
1311 static void intel_enable_pch_pll(struct drm_i915_private
*dev_priv
,
1320 /* PCH only available on ILK+ */
1321 BUG_ON(dev_priv
->info
->gen
< 5);
1323 /* PCH refclock must be enabled first */
1324 assert_pch_refclk_enabled(dev_priv
);
1326 reg
= PCH_DPLL(pipe
);
1327 val
= I915_READ(reg
);
1328 val
|= DPLL_VCO_ENABLE
;
1329 I915_WRITE(reg
, val
);
1334 static void intel_disable_pch_pll(struct drm_i915_private
*dev_priv
,
1338 u32 val
, pll_mask
= TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
,
1339 pll_sel
= TRANSC_DPLL_ENABLE
;
1344 /* PCH only available on ILK+ */
1345 BUG_ON(dev_priv
->info
->gen
< 5);
1347 /* Make sure transcoder isn't still depending on us */
1348 assert_transcoder_disabled(dev_priv
, pipe
);
1351 pll_sel
|= TRANSC_DPLLA_SEL
;
1353 pll_sel
|= TRANSC_DPLLB_SEL
;
1356 if ((I915_READ(PCH_DPLL_SEL
) & pll_mask
) == pll_sel
)
1359 reg
= PCH_DPLL(pipe
);
1360 val
= I915_READ(reg
);
1361 val
&= ~DPLL_VCO_ENABLE
;
1362 I915_WRITE(reg
, val
);
1367 static void intel_enable_transcoder(struct drm_i915_private
*dev_priv
,
1371 u32 val
, pipeconf_val
;
1372 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1374 /* PCH only available on ILK+ */
1375 BUG_ON(dev_priv
->info
->gen
< 5);
1377 /* Make sure PCH DPLL is enabled */
1378 assert_pch_pll_enabled(dev_priv
, pipe
);
1380 /* FDI must be feeding us bits for PCH ports */
1381 assert_fdi_tx_enabled(dev_priv
, pipe
);
1382 assert_fdi_rx_enabled(dev_priv
, pipe
);
1384 reg
= TRANSCONF(pipe
);
1385 val
= I915_READ(reg
);
1386 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1388 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1390 * make the BPC in transcoder be consistent with
1391 * that in pipeconf reg.
1393 val
&= ~PIPE_BPC_MASK
;
1394 val
|= pipeconf_val
& PIPE_BPC_MASK
;
1397 val
&= ~TRANS_INTERLACE_MASK
;
1398 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1399 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1400 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1401 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1403 val
|= TRANS_INTERLACED
;
1405 val
|= TRANS_PROGRESSIVE
;
1407 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1408 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1409 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1412 static void intel_disable_transcoder(struct drm_i915_private
*dev_priv
,
1418 /* FDI relies on the transcoder */
1419 assert_fdi_tx_disabled(dev_priv
, pipe
);
1420 assert_fdi_rx_disabled(dev_priv
, pipe
);
1422 /* Ports must be off as well */
1423 assert_pch_ports_disabled(dev_priv
, pipe
);
1425 reg
= TRANSCONF(pipe
);
1426 val
= I915_READ(reg
);
1427 val
&= ~TRANS_ENABLE
;
1428 I915_WRITE(reg
, val
);
1429 /* wait for PCH transcoder off, transcoder state */
1430 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1431 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1435 * intel_enable_pipe - enable a pipe, asserting requirements
1436 * @dev_priv: i915 private structure
1437 * @pipe: pipe to enable
1438 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1440 * Enable @pipe, making sure that various hardware specific requirements
1441 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1443 * @pipe should be %PIPE_A or %PIPE_B.
1445 * Will wait until the pipe is actually running (i.e. first vblank) before
1448 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1455 * A pipe without a PLL won't actually be able to drive bits from
1456 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1459 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1460 assert_pll_enabled(dev_priv
, pipe
);
1463 /* if driving the PCH, we need FDI enabled */
1464 assert_fdi_rx_pll_enabled(dev_priv
, pipe
);
1465 assert_fdi_tx_pll_enabled(dev_priv
, pipe
);
1467 /* FIXME: assert CPU port conditions for SNB+ */
1470 reg
= PIPECONF(pipe
);
1471 val
= I915_READ(reg
);
1472 if (val
& PIPECONF_ENABLE
)
1475 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1476 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1480 * intel_disable_pipe - disable a pipe, asserting requirements
1481 * @dev_priv: i915 private structure
1482 * @pipe: pipe to disable
1484 * Disable @pipe, making sure that various hardware specific requirements
1485 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1487 * @pipe should be %PIPE_A or %PIPE_B.
1489 * Will wait until the pipe has shut down before returning.
1491 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1498 * Make sure planes won't keep trying to pump pixels to us,
1499 * or we might hang the display.
1501 assert_planes_disabled(dev_priv
, pipe
);
1503 /* Don't disable pipe A or pipe A PLLs if needed */
1504 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1507 reg
= PIPECONF(pipe
);
1508 val
= I915_READ(reg
);
1509 if ((val
& PIPECONF_ENABLE
) == 0)
1512 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1513 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1517 * Plane regs are double buffered, going from enabled->disabled needs a
1518 * trigger in order to latch. The display address reg provides this.
1520 static void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1523 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1524 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1528 * intel_enable_plane - enable a display plane on a given pipe
1529 * @dev_priv: i915 private structure
1530 * @plane: plane to enable
1531 * @pipe: pipe being fed
1533 * Enable @plane on @pipe, making sure that @pipe is running first.
1535 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1536 enum plane plane
, enum pipe pipe
)
1541 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1542 assert_pipe_enabled(dev_priv
, pipe
);
1544 reg
= DSPCNTR(plane
);
1545 val
= I915_READ(reg
);
1546 if (val
& DISPLAY_PLANE_ENABLE
)
1549 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1550 intel_flush_display_plane(dev_priv
, plane
);
1551 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1555 * intel_disable_plane - disable a display plane
1556 * @dev_priv: i915 private structure
1557 * @plane: plane to disable
1558 * @pipe: pipe consuming the data
1560 * Disable @plane; should be an independent operation.
1562 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1563 enum plane plane
, enum pipe pipe
)
1568 reg
= DSPCNTR(plane
);
1569 val
= I915_READ(reg
);
1570 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1573 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1574 intel_flush_display_plane(dev_priv
, plane
);
1575 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1578 static void disable_pch_dp(struct drm_i915_private
*dev_priv
,
1579 enum pipe pipe
, int reg
, u32 port_sel
)
1581 u32 val
= I915_READ(reg
);
1582 if (dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
)) {
1583 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg
, pipe
);
1584 I915_WRITE(reg
, val
& ~DP_PORT_EN
);
1588 static void disable_pch_hdmi(struct drm_i915_private
*dev_priv
,
1589 enum pipe pipe
, int reg
)
1591 u32 val
= I915_READ(reg
);
1592 if (hdmi_pipe_enabled(dev_priv
, val
, pipe
)) {
1593 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1595 I915_WRITE(reg
, val
& ~PORT_ENABLE
);
1599 /* Disable any ports connected to this transcoder */
1600 static void intel_disable_pch_ports(struct drm_i915_private
*dev_priv
,
1605 val
= I915_READ(PCH_PP_CONTROL
);
1606 I915_WRITE(PCH_PP_CONTROL
, val
| PANEL_UNLOCK_REGS
);
1608 disable_pch_dp(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1609 disable_pch_dp(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1610 disable_pch_dp(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1613 val
= I915_READ(reg
);
1614 if (adpa_pipe_enabled(dev_priv
, val
, pipe
))
1615 I915_WRITE(reg
, val
& ~ADPA_DAC_ENABLE
);
1618 val
= I915_READ(reg
);
1619 if (lvds_pipe_enabled(dev_priv
, val
, pipe
)) {
1620 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe
, val
);
1621 I915_WRITE(reg
, val
& ~LVDS_PORT_EN
);
1626 disable_pch_hdmi(dev_priv
, pipe
, HDMIB
);
1627 disable_pch_hdmi(dev_priv
, pipe
, HDMIC
);
1628 disable_pch_hdmi(dev_priv
, pipe
, HDMID
);
1631 static void i8xx_disable_fbc(struct drm_device
*dev
)
1633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1636 /* Disable compression */
1637 fbc_ctl
= I915_READ(FBC_CONTROL
);
1638 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
1641 fbc_ctl
&= ~FBC_CTL_EN
;
1642 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1644 /* Wait for compressing bit to clear */
1645 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
1646 DRM_DEBUG_KMS("FBC idle timed out\n");
1650 DRM_DEBUG_KMS("disabled FBC\n");
1653 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1655 struct drm_device
*dev
= crtc
->dev
;
1656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1657 struct drm_framebuffer
*fb
= crtc
->fb
;
1658 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1659 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1660 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1663 u32 fbc_ctl
, fbc_ctl2
;
1665 cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
1666 if (fb
->pitches
[0] < cfb_pitch
)
1667 cfb_pitch
= fb
->pitches
[0];
1669 /* FBC_CTL wants 64B units */
1670 cfb_pitch
= (cfb_pitch
/ 64) - 1;
1671 plane
= intel_crtc
->plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1673 /* Clear old tags */
1674 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1675 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1678 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
1680 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1681 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1684 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1686 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
1687 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1688 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1689 fbc_ctl
|= obj
->fence_reg
;
1690 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1692 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1693 cfb_pitch
, crtc
->y
, intel_crtc
->plane
);
1696 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
1698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1700 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1703 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1705 struct drm_device
*dev
= crtc
->dev
;
1706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1707 struct drm_framebuffer
*fb
= crtc
->fb
;
1708 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1709 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1710 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1711 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1712 unsigned long stall_watermark
= 200;
1715 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1716 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
1717 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1719 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1720 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1721 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1722 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1725 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1727 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1730 static void g4x_disable_fbc(struct drm_device
*dev
)
1732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1735 /* Disable compression */
1736 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1737 if (dpfc_ctl
& DPFC_CTL_EN
) {
1738 dpfc_ctl
&= ~DPFC_CTL_EN
;
1739 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1741 DRM_DEBUG_KMS("disabled FBC\n");
1745 static bool g4x_fbc_enabled(struct drm_device
*dev
)
1747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1749 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1752 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
1754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1757 /* Make sure blitter notifies FBC of writes */
1758 gen6_gt_force_wake_get(dev_priv
);
1759 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
1760 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
1761 GEN6_BLITTER_LOCK_SHIFT
;
1762 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
1763 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
1764 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
1765 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
1766 GEN6_BLITTER_LOCK_SHIFT
);
1767 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
1768 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
1769 gen6_gt_force_wake_put(dev_priv
);
1772 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1774 struct drm_device
*dev
= crtc
->dev
;
1775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1776 struct drm_framebuffer
*fb
= crtc
->fb
;
1777 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1778 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1779 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1780 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1781 unsigned long stall_watermark
= 200;
1784 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1785 dpfc_ctl
&= DPFC_RESERVED
;
1786 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
1787 /* Set persistent mode for front-buffer rendering, ala X. */
1788 dpfc_ctl
|= DPFC_CTL_PERSISTENT_MODE
;
1789 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| obj
->fence_reg
);
1790 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1792 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1793 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1794 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1795 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
1796 I915_WRITE(ILK_FBC_RT_BASE
, obj
->gtt_offset
| ILK_FBC_RT_VALID
);
1798 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
1801 I915_WRITE(SNB_DPFC_CTL_SA
,
1802 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
1803 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
1804 sandybridge_blit_fbc_update(dev
);
1807 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1810 static void ironlake_disable_fbc(struct drm_device
*dev
)
1812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1815 /* Disable compression */
1816 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1817 if (dpfc_ctl
& DPFC_CTL_EN
) {
1818 dpfc_ctl
&= ~DPFC_CTL_EN
;
1819 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
1821 DRM_DEBUG_KMS("disabled FBC\n");
1825 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
1827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1829 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
1832 bool intel_fbc_enabled(struct drm_device
*dev
)
1834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1836 if (!dev_priv
->display
.fbc_enabled
)
1839 return dev_priv
->display
.fbc_enabled(dev
);
1842 static void intel_fbc_work_fn(struct work_struct
*__work
)
1844 struct intel_fbc_work
*work
=
1845 container_of(to_delayed_work(__work
),
1846 struct intel_fbc_work
, work
);
1847 struct drm_device
*dev
= work
->crtc
->dev
;
1848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1850 mutex_lock(&dev
->struct_mutex
);
1851 if (work
== dev_priv
->fbc_work
) {
1852 /* Double check that we haven't switched fb without cancelling
1855 if (work
->crtc
->fb
== work
->fb
) {
1856 dev_priv
->display
.enable_fbc(work
->crtc
,
1859 dev_priv
->cfb_plane
= to_intel_crtc(work
->crtc
)->plane
;
1860 dev_priv
->cfb_fb
= work
->crtc
->fb
->base
.id
;
1861 dev_priv
->cfb_y
= work
->crtc
->y
;
1864 dev_priv
->fbc_work
= NULL
;
1866 mutex_unlock(&dev
->struct_mutex
);
1871 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
1873 if (dev_priv
->fbc_work
== NULL
)
1876 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1878 /* Synchronisation is provided by struct_mutex and checking of
1879 * dev_priv->fbc_work, so we can perform the cancellation
1880 * entirely asynchronously.
1882 if (cancel_delayed_work(&dev_priv
->fbc_work
->work
))
1883 /* tasklet was killed before being run, clean up */
1884 kfree(dev_priv
->fbc_work
);
1886 /* Mark the work as no longer wanted so that if it does
1887 * wake-up (because the work was already running and waiting
1888 * for our mutex), it will discover that is no longer
1891 dev_priv
->fbc_work
= NULL
;
1894 static void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1896 struct intel_fbc_work
*work
;
1897 struct drm_device
*dev
= crtc
->dev
;
1898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1900 if (!dev_priv
->display
.enable_fbc
)
1903 intel_cancel_fbc_work(dev_priv
);
1905 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
1907 dev_priv
->display
.enable_fbc(crtc
, interval
);
1912 work
->fb
= crtc
->fb
;
1913 work
->interval
= interval
;
1914 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
1916 dev_priv
->fbc_work
= work
;
1918 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1920 /* Delay the actual enabling to let pageflipping cease and the
1921 * display to settle before starting the compression. Note that
1922 * this delay also serves a second purpose: it allows for a
1923 * vblank to pass after disabling the FBC before we attempt
1924 * to modify the control registers.
1926 * A more complicated solution would involve tracking vblanks
1927 * following the termination of the page-flipping sequence
1928 * and indeed performing the enable as a co-routine and not
1929 * waiting synchronously upon the vblank.
1931 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
1934 void intel_disable_fbc(struct drm_device
*dev
)
1936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1938 intel_cancel_fbc_work(dev_priv
);
1940 if (!dev_priv
->display
.disable_fbc
)
1943 dev_priv
->display
.disable_fbc(dev
);
1944 dev_priv
->cfb_plane
= -1;
1948 * intel_update_fbc - enable/disable FBC as needed
1949 * @dev: the drm_device
1951 * Set up the framebuffer compression hardware at mode set time. We
1952 * enable it if possible:
1953 * - plane A only (on pre-965)
1954 * - no pixel mulitply/line duplication
1955 * - no alpha buffer discard
1957 * - framebuffer <= 2048 in width, 1536 in height
1959 * We can't assume that any compression will take place (worst case),
1960 * so the compressed buffer has to be the same size as the uncompressed
1961 * one. It also must reside (along with the line length buffer) in
1964 * We need to enable/disable FBC on a global basis.
1966 static void intel_update_fbc(struct drm_device
*dev
)
1968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1969 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
1970 struct intel_crtc
*intel_crtc
;
1971 struct drm_framebuffer
*fb
;
1972 struct intel_framebuffer
*intel_fb
;
1973 struct drm_i915_gem_object
*obj
;
1976 DRM_DEBUG_KMS("\n");
1978 if (!i915_powersave
)
1981 if (!I915_HAS_FBC(dev
))
1985 * If FBC is already on, we just have to verify that we can
1986 * keep it that way...
1987 * Need to disable if:
1988 * - more than one pipe is active
1989 * - changing FBC params (stride, fence, mode)
1990 * - new fb is too large to fit in compressed buffer
1991 * - going to an unsupported config (interlace, pixel multiply, etc.)
1993 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1994 if (tmp_crtc
->enabled
&& tmp_crtc
->fb
) {
1996 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1997 dev_priv
->no_fbc_reason
= FBC_MULTIPLE_PIPES
;
2004 if (!crtc
|| crtc
->fb
== NULL
) {
2005 DRM_DEBUG_KMS("no output, disabling\n");
2006 dev_priv
->no_fbc_reason
= FBC_NO_OUTPUT
;
2010 intel_crtc
= to_intel_crtc(crtc
);
2012 intel_fb
= to_intel_framebuffer(fb
);
2013 obj
= intel_fb
->obj
;
2015 enable_fbc
= i915_enable_fbc
;
2016 if (enable_fbc
< 0) {
2017 DRM_DEBUG_KMS("fbc set to per-chip default\n");
2019 if (INTEL_INFO(dev
)->gen
<= 6)
2023 DRM_DEBUG_KMS("fbc disabled per module param\n");
2024 dev_priv
->no_fbc_reason
= FBC_MODULE_PARAM
;
2027 if (intel_fb
->obj
->base
.size
> dev_priv
->cfb_size
) {
2028 DRM_DEBUG_KMS("framebuffer too large, disabling "
2030 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
2033 if ((crtc
->mode
.flags
& DRM_MODE_FLAG_INTERLACE
) ||
2034 (crtc
->mode
.flags
& DRM_MODE_FLAG_DBLSCAN
)) {
2035 DRM_DEBUG_KMS("mode incompatible with compression, "
2037 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
2040 if ((crtc
->mode
.hdisplay
> 2048) ||
2041 (crtc
->mode
.vdisplay
> 1536)) {
2042 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
2043 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
2046 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && intel_crtc
->plane
!= 0) {
2047 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
2048 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
2052 /* The use of a CPU fence is mandatory in order to detect writes
2053 * by the CPU to the scanout and trigger updates to the FBC.
2055 if (obj
->tiling_mode
!= I915_TILING_X
||
2056 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
2057 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
2058 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
2062 /* If the kernel debugger is active, always disable compression */
2063 if (in_dbg_master())
2066 /* If the scanout has not changed, don't modify the FBC settings.
2067 * Note that we make the fundamental assumption that the fb->obj
2068 * cannot be unpinned (and have its GTT offset and fence revoked)
2069 * without first being decoupled from the scanout and FBC disabled.
2071 if (dev_priv
->cfb_plane
== intel_crtc
->plane
&&
2072 dev_priv
->cfb_fb
== fb
->base
.id
&&
2073 dev_priv
->cfb_y
== crtc
->y
)
2076 if (intel_fbc_enabled(dev
)) {
2077 /* We update FBC along two paths, after changing fb/crtc
2078 * configuration (modeswitching) and after page-flipping
2079 * finishes. For the latter, we know that not only did
2080 * we disable the FBC at the start of the page-flip
2081 * sequence, but also more than one vblank has passed.
2083 * For the former case of modeswitching, it is possible
2084 * to switch between two FBC valid configurations
2085 * instantaneously so we do need to disable the FBC
2086 * before we can modify its control registers. We also
2087 * have to wait for the next vblank for that to take
2088 * effect. However, since we delay enabling FBC we can
2089 * assume that a vblank has passed since disabling and
2090 * that we can safely alter the registers in the deferred
2093 * In the scenario that we go from a valid to invalid
2094 * and then back to valid FBC configuration we have
2095 * no strict enforcement that a vblank occurred since
2096 * disabling the FBC. However, along all current pipe
2097 * disabling paths we do need to wait for a vblank at
2098 * some point. And we wait before enabling FBC anyway.
2100 DRM_DEBUG_KMS("disabling active FBC for update\n");
2101 intel_disable_fbc(dev
);
2104 intel_enable_fbc(crtc
, 500);
2108 /* Multiple disables should be harmless */
2109 if (intel_fbc_enabled(dev
)) {
2110 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2111 intel_disable_fbc(dev
);
2116 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
2117 struct drm_i915_gem_object
*obj
,
2118 struct intel_ring_buffer
*pipelined
)
2120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2124 switch (obj
->tiling_mode
) {
2125 case I915_TILING_NONE
:
2126 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2127 alignment
= 128 * 1024;
2128 else if (INTEL_INFO(dev
)->gen
>= 4)
2129 alignment
= 4 * 1024;
2131 alignment
= 64 * 1024;
2134 /* pin() will align the object as required by fence */
2138 /* FIXME: Is this true? */
2139 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2145 dev_priv
->mm
.interruptible
= false;
2146 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2148 goto err_interruptible
;
2150 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2151 * fence, whereas 965+ only requires a fence if using
2152 * framebuffer compression. For simplicity, we always install
2153 * a fence as the cost is not that onerous.
2155 ret
= i915_gem_object_get_fence(obj
, pipelined
);
2159 i915_gem_object_pin_fence(obj
);
2161 dev_priv
->mm
.interruptible
= true;
2165 i915_gem_object_unpin(obj
);
2167 dev_priv
->mm
.interruptible
= true;
2171 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2173 i915_gem_object_unpin_fence(obj
);
2174 i915_gem_object_unpin(obj
);
2177 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2180 struct drm_device
*dev
= crtc
->dev
;
2181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2182 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2183 struct intel_framebuffer
*intel_fb
;
2184 struct drm_i915_gem_object
*obj
;
2185 int plane
= intel_crtc
->plane
;
2186 unsigned long Start
, Offset
;
2195 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2199 intel_fb
= to_intel_framebuffer(fb
);
2200 obj
= intel_fb
->obj
;
2202 reg
= DSPCNTR(plane
);
2203 dspcntr
= I915_READ(reg
);
2204 /* Mask out pixel format bits in case we change it */
2205 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2206 switch (fb
->bits_per_pixel
) {
2208 dspcntr
|= DISPPLANE_8BPP
;
2211 if (fb
->depth
== 15)
2212 dspcntr
|= DISPPLANE_15_16BPP
;
2214 dspcntr
|= DISPPLANE_16BPP
;
2218 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2221 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2224 if (INTEL_INFO(dev
)->gen
>= 4) {
2225 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2226 dspcntr
|= DISPPLANE_TILED
;
2228 dspcntr
&= ~DISPPLANE_TILED
;
2231 I915_WRITE(reg
, dspcntr
);
2233 Start
= obj
->gtt_offset
;
2234 Offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2236 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2237 Start
, Offset
, x
, y
, fb
->pitches
[0]);
2238 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2239 if (INTEL_INFO(dev
)->gen
>= 4) {
2240 I915_WRITE(DSPSURF(plane
), Start
);
2241 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2242 I915_WRITE(DSPADDR(plane
), Offset
);
2244 I915_WRITE(DSPADDR(plane
), Start
+ Offset
);
2250 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2251 struct drm_framebuffer
*fb
, int x
, int y
)
2253 struct drm_device
*dev
= crtc
->dev
;
2254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2255 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2256 struct intel_framebuffer
*intel_fb
;
2257 struct drm_i915_gem_object
*obj
;
2258 int plane
= intel_crtc
->plane
;
2259 unsigned long Start
, Offset
;
2269 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2273 intel_fb
= to_intel_framebuffer(fb
);
2274 obj
= intel_fb
->obj
;
2276 reg
= DSPCNTR(plane
);
2277 dspcntr
= I915_READ(reg
);
2278 /* Mask out pixel format bits in case we change it */
2279 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2280 switch (fb
->bits_per_pixel
) {
2282 dspcntr
|= DISPPLANE_8BPP
;
2285 if (fb
->depth
!= 16)
2288 dspcntr
|= DISPPLANE_16BPP
;
2292 if (fb
->depth
== 24)
2293 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2294 else if (fb
->depth
== 30)
2295 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
2300 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2304 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2305 dspcntr
|= DISPPLANE_TILED
;
2307 dspcntr
&= ~DISPPLANE_TILED
;
2310 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2312 I915_WRITE(reg
, dspcntr
);
2314 Start
= obj
->gtt_offset
;
2315 Offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2317 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2318 Start
, Offset
, x
, y
, fb
->pitches
[0]);
2319 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2320 I915_WRITE(DSPSURF(plane
), Start
);
2321 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2322 I915_WRITE(DSPADDR(plane
), Offset
);
2328 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2330 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2331 int x
, int y
, enum mode_set_atomic state
)
2333 struct drm_device
*dev
= crtc
->dev
;
2334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2337 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2341 intel_update_fbc(dev
);
2342 intel_increase_pllclock(crtc
);
2348 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2349 struct drm_framebuffer
*old_fb
)
2351 struct drm_device
*dev
= crtc
->dev
;
2352 struct drm_i915_master_private
*master_priv
;
2353 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2358 DRM_ERROR("No FB bound\n");
2362 switch (intel_crtc
->plane
) {
2367 if (IS_IVYBRIDGE(dev
))
2369 /* fall through otherwise */
2371 DRM_ERROR("no plane for crtc\n");
2375 mutex_lock(&dev
->struct_mutex
);
2376 ret
= intel_pin_and_fence_fb_obj(dev
,
2377 to_intel_framebuffer(crtc
->fb
)->obj
,
2380 mutex_unlock(&dev
->struct_mutex
);
2381 DRM_ERROR("pin & fence failed\n");
2386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2387 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2389 wait_event(dev_priv
->pending_flip_queue
,
2390 atomic_read(&dev_priv
->mm
.wedged
) ||
2391 atomic_read(&obj
->pending_flip
) == 0);
2393 /* Big Hammer, we also need to ensure that any pending
2394 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2395 * current scanout is retired before unpinning the old
2398 * This should only fail upon a hung GPU, in which case we
2399 * can safely continue.
2401 ret
= i915_gem_object_finish_gpu(obj
);
2405 ret
= intel_pipe_set_base_atomic(crtc
, crtc
->fb
, x
, y
,
2406 LEAVE_ATOMIC_MODE_SET
);
2408 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
2409 mutex_unlock(&dev
->struct_mutex
);
2410 DRM_ERROR("failed to update base address\n");
2415 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2416 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2419 mutex_unlock(&dev
->struct_mutex
);
2421 if (!dev
->primary
->master
)
2424 master_priv
= dev
->primary
->master
->driver_priv
;
2425 if (!master_priv
->sarea_priv
)
2428 if (intel_crtc
->pipe
) {
2429 master_priv
->sarea_priv
->pipeB_x
= x
;
2430 master_priv
->sarea_priv
->pipeB_y
= y
;
2432 master_priv
->sarea_priv
->pipeA_x
= x
;
2433 master_priv
->sarea_priv
->pipeA_y
= y
;
2439 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2441 struct drm_device
*dev
= crtc
->dev
;
2442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2445 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2446 dpa_ctl
= I915_READ(DP_A
);
2447 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2449 if (clock
< 200000) {
2451 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2452 /* workaround for 160Mhz:
2453 1) program 0x4600c bits 15:0 = 0x8124
2454 2) program 0x46010 bit 0 = 1
2455 3) program 0x46034 bit 24 = 1
2456 4) program 0x64000 bit 14 = 1
2458 temp
= I915_READ(0x4600c);
2460 I915_WRITE(0x4600c, temp
| 0x8124);
2462 temp
= I915_READ(0x46010);
2463 I915_WRITE(0x46010, temp
| 1);
2465 temp
= I915_READ(0x46034);
2466 I915_WRITE(0x46034, temp
| (1 << 24));
2468 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2470 I915_WRITE(DP_A
, dpa_ctl
);
2476 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2478 struct drm_device
*dev
= crtc
->dev
;
2479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2480 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2481 int pipe
= intel_crtc
->pipe
;
2484 /* enable normal train */
2485 reg
= FDI_TX_CTL(pipe
);
2486 temp
= I915_READ(reg
);
2487 if (IS_IVYBRIDGE(dev
)) {
2488 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2489 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2491 temp
&= ~FDI_LINK_TRAIN_NONE
;
2492 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2494 I915_WRITE(reg
, temp
);
2496 reg
= FDI_RX_CTL(pipe
);
2497 temp
= I915_READ(reg
);
2498 if (HAS_PCH_CPT(dev
)) {
2499 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2500 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2502 temp
&= ~FDI_LINK_TRAIN_NONE
;
2503 temp
|= FDI_LINK_TRAIN_NONE
;
2505 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2507 /* wait one idle pattern time */
2511 /* IVB wants error correction enabled */
2512 if (IS_IVYBRIDGE(dev
))
2513 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2514 FDI_FE_ERRC_ENABLE
);
2517 static void cpt_phase_pointer_enable(struct drm_device
*dev
, int pipe
)
2519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2520 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2522 flags
|= FDI_PHASE_SYNC_OVR(pipe
);
2523 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to unlock... */
2524 flags
|= FDI_PHASE_SYNC_EN(pipe
);
2525 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to enable */
2526 POSTING_READ(SOUTH_CHICKEN1
);
2529 /* The FDI link training functions for ILK/Ibexpeak. */
2530 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2532 struct drm_device
*dev
= crtc
->dev
;
2533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2534 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2535 int pipe
= intel_crtc
->pipe
;
2536 int plane
= intel_crtc
->plane
;
2537 u32 reg
, temp
, tries
;
2539 /* FDI needs bits from pipe & plane first */
2540 assert_pipe_enabled(dev_priv
, pipe
);
2541 assert_plane_enabled(dev_priv
, plane
);
2543 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2545 reg
= FDI_RX_IMR(pipe
);
2546 temp
= I915_READ(reg
);
2547 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2548 temp
&= ~FDI_RX_BIT_LOCK
;
2549 I915_WRITE(reg
, temp
);
2553 /* enable CPU FDI TX and PCH FDI RX */
2554 reg
= FDI_TX_CTL(pipe
);
2555 temp
= I915_READ(reg
);
2557 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2558 temp
&= ~FDI_LINK_TRAIN_NONE
;
2559 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2560 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2562 reg
= FDI_RX_CTL(pipe
);
2563 temp
= I915_READ(reg
);
2564 temp
&= ~FDI_LINK_TRAIN_NONE
;
2565 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2566 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2571 /* Ironlake workaround, enable clock pointer after FDI enable*/
2572 if (HAS_PCH_IBX(dev
)) {
2573 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2574 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2575 FDI_RX_PHASE_SYNC_POINTER_EN
);
2578 reg
= FDI_RX_IIR(pipe
);
2579 for (tries
= 0; tries
< 5; tries
++) {
2580 temp
= I915_READ(reg
);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2583 if ((temp
& FDI_RX_BIT_LOCK
)) {
2584 DRM_DEBUG_KMS("FDI train 1 done.\n");
2585 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2590 DRM_ERROR("FDI train 1 fail!\n");
2593 reg
= FDI_TX_CTL(pipe
);
2594 temp
= I915_READ(reg
);
2595 temp
&= ~FDI_LINK_TRAIN_NONE
;
2596 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2597 I915_WRITE(reg
, temp
);
2599 reg
= FDI_RX_CTL(pipe
);
2600 temp
= I915_READ(reg
);
2601 temp
&= ~FDI_LINK_TRAIN_NONE
;
2602 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2603 I915_WRITE(reg
, temp
);
2608 reg
= FDI_RX_IIR(pipe
);
2609 for (tries
= 0; tries
< 5; tries
++) {
2610 temp
= I915_READ(reg
);
2611 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2613 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2614 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2615 DRM_DEBUG_KMS("FDI train 2 done.\n");
2620 DRM_ERROR("FDI train 2 fail!\n");
2622 DRM_DEBUG_KMS("FDI train done\n");
2626 static const int snb_b_fdi_train_param
[] = {
2627 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2628 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2629 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2630 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2633 /* The FDI link training functions for SNB/Cougarpoint. */
2634 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2636 struct drm_device
*dev
= crtc
->dev
;
2637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2638 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2639 int pipe
= intel_crtc
->pipe
;
2640 u32 reg
, temp
, i
, retry
;
2642 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2644 reg
= FDI_RX_IMR(pipe
);
2645 temp
= I915_READ(reg
);
2646 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2647 temp
&= ~FDI_RX_BIT_LOCK
;
2648 I915_WRITE(reg
, temp
);
2653 /* enable CPU FDI TX and PCH FDI RX */
2654 reg
= FDI_TX_CTL(pipe
);
2655 temp
= I915_READ(reg
);
2657 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2658 temp
&= ~FDI_LINK_TRAIN_NONE
;
2659 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2660 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2662 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2663 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2665 reg
= FDI_RX_CTL(pipe
);
2666 temp
= I915_READ(reg
);
2667 if (HAS_PCH_CPT(dev
)) {
2668 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2669 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2671 temp
&= ~FDI_LINK_TRAIN_NONE
;
2672 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2674 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2679 if (HAS_PCH_CPT(dev
))
2680 cpt_phase_pointer_enable(dev
, pipe
);
2682 for (i
= 0; i
< 4; i
++) {
2683 reg
= FDI_TX_CTL(pipe
);
2684 temp
= I915_READ(reg
);
2685 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2686 temp
|= snb_b_fdi_train_param
[i
];
2687 I915_WRITE(reg
, temp
);
2692 for (retry
= 0; retry
< 5; retry
++) {
2693 reg
= FDI_RX_IIR(pipe
);
2694 temp
= I915_READ(reg
);
2695 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2696 if (temp
& FDI_RX_BIT_LOCK
) {
2697 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2698 DRM_DEBUG_KMS("FDI train 1 done.\n");
2707 DRM_ERROR("FDI train 1 fail!\n");
2710 reg
= FDI_TX_CTL(pipe
);
2711 temp
= I915_READ(reg
);
2712 temp
&= ~FDI_LINK_TRAIN_NONE
;
2713 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2715 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2717 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2719 I915_WRITE(reg
, temp
);
2721 reg
= FDI_RX_CTL(pipe
);
2722 temp
= I915_READ(reg
);
2723 if (HAS_PCH_CPT(dev
)) {
2724 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2725 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2727 temp
&= ~FDI_LINK_TRAIN_NONE
;
2728 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2730 I915_WRITE(reg
, temp
);
2735 for (i
= 0; i
< 4; i
++) {
2736 reg
= FDI_TX_CTL(pipe
);
2737 temp
= I915_READ(reg
);
2738 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2739 temp
|= snb_b_fdi_train_param
[i
];
2740 I915_WRITE(reg
, temp
);
2745 for (retry
= 0; retry
< 5; retry
++) {
2746 reg
= FDI_RX_IIR(pipe
);
2747 temp
= I915_READ(reg
);
2748 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2749 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2750 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2751 DRM_DEBUG_KMS("FDI train 2 done.\n");
2760 DRM_ERROR("FDI train 2 fail!\n");
2762 DRM_DEBUG_KMS("FDI train done.\n");
2765 /* Manual link training for Ivy Bridge A0 parts */
2766 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2768 struct drm_device
*dev
= crtc
->dev
;
2769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2770 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2771 int pipe
= intel_crtc
->pipe
;
2774 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2776 reg
= FDI_RX_IMR(pipe
);
2777 temp
= I915_READ(reg
);
2778 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2779 temp
&= ~FDI_RX_BIT_LOCK
;
2780 I915_WRITE(reg
, temp
);
2785 /* enable CPU FDI TX and PCH FDI RX */
2786 reg
= FDI_TX_CTL(pipe
);
2787 temp
= I915_READ(reg
);
2789 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2790 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2791 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2792 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2793 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2794 temp
|= FDI_COMPOSITE_SYNC
;
2795 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2797 reg
= FDI_RX_CTL(pipe
);
2798 temp
= I915_READ(reg
);
2799 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2800 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2801 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2802 temp
|= FDI_COMPOSITE_SYNC
;
2803 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2808 if (HAS_PCH_CPT(dev
))
2809 cpt_phase_pointer_enable(dev
, pipe
);
2811 for (i
= 0; i
< 4; i
++) {
2812 reg
= FDI_TX_CTL(pipe
);
2813 temp
= I915_READ(reg
);
2814 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2815 temp
|= snb_b_fdi_train_param
[i
];
2816 I915_WRITE(reg
, temp
);
2821 reg
= FDI_RX_IIR(pipe
);
2822 temp
= I915_READ(reg
);
2823 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2825 if (temp
& FDI_RX_BIT_LOCK
||
2826 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2827 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2828 DRM_DEBUG_KMS("FDI train 1 done.\n");
2833 DRM_ERROR("FDI train 1 fail!\n");
2836 reg
= FDI_TX_CTL(pipe
);
2837 temp
= I915_READ(reg
);
2838 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2839 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2840 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2841 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2842 I915_WRITE(reg
, temp
);
2844 reg
= FDI_RX_CTL(pipe
);
2845 temp
= I915_READ(reg
);
2846 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2847 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2848 I915_WRITE(reg
, temp
);
2853 for (i
= 0; i
< 4; i
++) {
2854 reg
= FDI_TX_CTL(pipe
);
2855 temp
= I915_READ(reg
);
2856 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2857 temp
|= snb_b_fdi_train_param
[i
];
2858 I915_WRITE(reg
, temp
);
2863 reg
= FDI_RX_IIR(pipe
);
2864 temp
= I915_READ(reg
);
2865 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2867 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2868 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2869 DRM_DEBUG_KMS("FDI train 2 done.\n");
2874 DRM_ERROR("FDI train 2 fail!\n");
2876 DRM_DEBUG_KMS("FDI train done.\n");
2879 static void ironlake_fdi_pll_enable(struct drm_crtc
*crtc
)
2881 struct drm_device
*dev
= crtc
->dev
;
2882 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2883 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2884 int pipe
= intel_crtc
->pipe
;
2887 /* Write the TU size bits so error detection works */
2888 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2889 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2891 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2892 reg
= FDI_RX_CTL(pipe
);
2893 temp
= I915_READ(reg
);
2894 temp
&= ~((0x7 << 19) | (0x7 << 16));
2895 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2896 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2897 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2902 /* Switch from Rawclk to PCDclk */
2903 temp
= I915_READ(reg
);
2904 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2909 /* Enable CPU FDI TX PLL, always on for Ironlake */
2910 reg
= FDI_TX_CTL(pipe
);
2911 temp
= I915_READ(reg
);
2912 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2913 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2920 static void cpt_phase_pointer_disable(struct drm_device
*dev
, int pipe
)
2922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2923 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2925 flags
&= ~(FDI_PHASE_SYNC_EN(pipe
));
2926 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to disable... */
2927 flags
&= ~(FDI_PHASE_SYNC_OVR(pipe
));
2928 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to lock */
2929 POSTING_READ(SOUTH_CHICKEN1
);
2931 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2933 struct drm_device
*dev
= crtc
->dev
;
2934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2935 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2936 int pipe
= intel_crtc
->pipe
;
2939 /* disable CPU FDI tx and PCH FDI rx */
2940 reg
= FDI_TX_CTL(pipe
);
2941 temp
= I915_READ(reg
);
2942 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2945 reg
= FDI_RX_CTL(pipe
);
2946 temp
= I915_READ(reg
);
2947 temp
&= ~(0x7 << 16);
2948 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2949 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2954 /* Ironlake workaround, disable clock pointer after downing FDI */
2955 if (HAS_PCH_IBX(dev
)) {
2956 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2957 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2958 I915_READ(FDI_RX_CHICKEN(pipe
) &
2959 ~FDI_RX_PHASE_SYNC_POINTER_EN
));
2960 } else if (HAS_PCH_CPT(dev
)) {
2961 cpt_phase_pointer_disable(dev
, pipe
);
2964 /* still set train pattern 1 */
2965 reg
= FDI_TX_CTL(pipe
);
2966 temp
= I915_READ(reg
);
2967 temp
&= ~FDI_LINK_TRAIN_NONE
;
2968 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2969 I915_WRITE(reg
, temp
);
2971 reg
= FDI_RX_CTL(pipe
);
2972 temp
= I915_READ(reg
);
2973 if (HAS_PCH_CPT(dev
)) {
2974 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2975 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2977 temp
&= ~FDI_LINK_TRAIN_NONE
;
2978 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2980 /* BPC in FDI rx is consistent with that in PIPECONF */
2981 temp
&= ~(0x07 << 16);
2982 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2983 I915_WRITE(reg
, temp
);
2990 * When we disable a pipe, we need to clear any pending scanline wait events
2991 * to avoid hanging the ring, which we assume we are waiting on.
2993 static void intel_clear_scanline_wait(struct drm_device
*dev
)
2995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2996 struct intel_ring_buffer
*ring
;
3000 /* Can't break the hang on i8xx */
3003 ring
= LP_RING(dev_priv
);
3004 tmp
= I915_READ_CTL(ring
);
3005 if (tmp
& RING_WAIT
)
3006 I915_WRITE_CTL(ring
, tmp
);
3009 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3011 struct drm_i915_gem_object
*obj
;
3012 struct drm_i915_private
*dev_priv
;
3014 if (crtc
->fb
== NULL
)
3017 obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
3018 dev_priv
= crtc
->dev
->dev_private
;
3019 wait_event(dev_priv
->pending_flip_queue
,
3020 atomic_read(&obj
->pending_flip
) == 0);
3023 static bool intel_crtc_driving_pch(struct drm_crtc
*crtc
)
3025 struct drm_device
*dev
= crtc
->dev
;
3026 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3027 struct intel_encoder
*encoder
;
3030 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
3031 * must be driven by its own crtc; no sharing is possible.
3033 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
3034 if (encoder
->base
.crtc
!= crtc
)
3037 switch (encoder
->type
) {
3038 case INTEL_OUTPUT_EDP
:
3039 if (!intel_encoder_is_pch_edp(&encoder
->base
))
3049 * Enable PCH resources required for PCH ports:
3051 * - FDI training & RX/TX
3052 * - update transcoder timings
3053 * - DP transcoding bits
3056 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3058 struct drm_device
*dev
= crtc
->dev
;
3059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3060 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3061 int pipe
= intel_crtc
->pipe
;
3062 u32 reg
, temp
, transc_sel
;
3064 /* For PCH output, training FDI link */
3065 dev_priv
->display
.fdi_link_train(crtc
);
3067 intel_enable_pch_pll(dev_priv
, pipe
);
3069 if (HAS_PCH_CPT(dev
)) {
3070 transc_sel
= intel_crtc
->use_pll_a
? TRANSC_DPLLA_SEL
:
3073 /* Be sure PCH DPLL SEL is set */
3074 temp
= I915_READ(PCH_DPLL_SEL
);
3076 temp
&= ~(TRANSA_DPLLB_SEL
);
3077 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
3078 } else if (pipe
== 1) {
3079 temp
&= ~(TRANSB_DPLLB_SEL
);
3080 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3081 } else if (pipe
== 2) {
3082 temp
&= ~(TRANSC_DPLLB_SEL
);
3083 temp
|= (TRANSC_DPLL_ENABLE
| transc_sel
);
3085 I915_WRITE(PCH_DPLL_SEL
, temp
);
3088 /* set transcoder timing, panel must allow it */
3089 assert_panel_unlocked(dev_priv
, pipe
);
3090 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3091 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3092 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3094 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3095 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3096 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3097 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3099 intel_fdi_normal_train(crtc
);
3101 /* For PCH DP, enable TRANS_DP_CTL */
3102 if (HAS_PCH_CPT(dev
) &&
3103 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3104 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3105 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) >> 5;
3106 reg
= TRANS_DP_CTL(pipe
);
3107 temp
= I915_READ(reg
);
3108 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3109 TRANS_DP_SYNC_MASK
|
3111 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3112 TRANS_DP_ENH_FRAMING
);
3113 temp
|= bpc
<< 9; /* same format but at 11:9 */
3115 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3116 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3117 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3118 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3120 switch (intel_trans_dp_port_sel(crtc
)) {
3122 temp
|= TRANS_DP_PORT_SEL_B
;
3125 temp
|= TRANS_DP_PORT_SEL_C
;
3128 temp
|= TRANS_DP_PORT_SEL_D
;
3131 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3132 temp
|= TRANS_DP_PORT_SEL_B
;
3136 I915_WRITE(reg
, temp
);
3139 intel_enable_transcoder(dev_priv
, pipe
);
3142 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3145 int dslreg
= PIPEDSL(pipe
), tc2reg
= TRANS_CHICKEN2(pipe
);
3148 temp
= I915_READ(dslreg
);
3150 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3151 /* Without this, mode sets may fail silently on FDI */
3152 I915_WRITE(tc2reg
, TRANS_AUTOTRAIN_GEN_STALL_DIS
);
3154 I915_WRITE(tc2reg
, 0);
3155 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3156 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3160 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3162 struct drm_device
*dev
= crtc
->dev
;
3163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3164 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3165 int pipe
= intel_crtc
->pipe
;
3166 int plane
= intel_crtc
->plane
;
3170 if (intel_crtc
->active
)
3173 intel_crtc
->active
= true;
3174 intel_update_watermarks(dev
);
3176 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3177 temp
= I915_READ(PCH_LVDS
);
3178 if ((temp
& LVDS_PORT_EN
) == 0)
3179 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3182 is_pch_port
= intel_crtc_driving_pch(crtc
);
3185 ironlake_fdi_pll_enable(crtc
);
3187 ironlake_fdi_disable(crtc
);
3189 /* Enable panel fitting for LVDS */
3190 if (dev_priv
->pch_pf_size
&&
3191 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
3192 /* Force use of hard-coded filter coefficients
3193 * as some pre-programmed values are broken,
3196 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3197 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3198 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3202 * On ILK+ LUT must be loaded before the pipe is running but with
3205 intel_crtc_load_lut(crtc
);
3207 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3208 intel_enable_plane(dev_priv
, plane
, pipe
);
3211 ironlake_pch_enable(crtc
);
3213 mutex_lock(&dev
->struct_mutex
);
3214 intel_update_fbc(dev
);
3215 mutex_unlock(&dev
->struct_mutex
);
3217 intel_crtc_update_cursor(crtc
, true);
3220 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3222 struct drm_device
*dev
= crtc
->dev
;
3223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3224 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3225 int pipe
= intel_crtc
->pipe
;
3226 int plane
= intel_crtc
->plane
;
3229 if (!intel_crtc
->active
)
3232 intel_crtc_wait_for_pending_flips(crtc
);
3233 drm_vblank_off(dev
, pipe
);
3234 intel_crtc_update_cursor(crtc
, false);
3236 intel_disable_plane(dev_priv
, plane
, pipe
);
3238 if (dev_priv
->cfb_plane
== plane
)
3239 intel_disable_fbc(dev
);
3241 intel_disable_pipe(dev_priv
, pipe
);
3244 I915_WRITE(PF_CTL(pipe
), 0);
3245 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3247 ironlake_fdi_disable(crtc
);
3249 /* This is a horrible layering violation; we should be doing this in
3250 * the connector/encoder ->prepare instead, but we don't always have
3251 * enough information there about the config to know whether it will
3252 * actually be necessary or just cause undesired flicker.
3254 intel_disable_pch_ports(dev_priv
, pipe
);
3256 intel_disable_transcoder(dev_priv
, pipe
);
3258 if (HAS_PCH_CPT(dev
)) {
3259 /* disable TRANS_DP_CTL */
3260 reg
= TRANS_DP_CTL(pipe
);
3261 temp
= I915_READ(reg
);
3262 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3263 temp
|= TRANS_DP_PORT_SEL_NONE
;
3264 I915_WRITE(reg
, temp
);
3266 /* disable DPLL_SEL */
3267 temp
= I915_READ(PCH_DPLL_SEL
);
3270 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3273 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3276 /* C shares PLL A or B */
3277 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3282 I915_WRITE(PCH_DPLL_SEL
, temp
);
3285 /* disable PCH DPLL */
3286 if (!intel_crtc
->no_pll
)
3287 intel_disable_pch_pll(dev_priv
, pipe
);
3289 /* Switch from PCDclk to Rawclk */
3290 reg
= FDI_RX_CTL(pipe
);
3291 temp
= I915_READ(reg
);
3292 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3294 /* Disable CPU FDI TX PLL */
3295 reg
= FDI_TX_CTL(pipe
);
3296 temp
= I915_READ(reg
);
3297 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3302 reg
= FDI_RX_CTL(pipe
);
3303 temp
= I915_READ(reg
);
3304 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3306 /* Wait for the clocks to turn off. */
3310 intel_crtc
->active
= false;
3311 intel_update_watermarks(dev
);
3313 mutex_lock(&dev
->struct_mutex
);
3314 intel_update_fbc(dev
);
3315 intel_clear_scanline_wait(dev
);
3316 mutex_unlock(&dev
->struct_mutex
);
3319 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3321 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3322 int pipe
= intel_crtc
->pipe
;
3323 int plane
= intel_crtc
->plane
;
3325 /* XXX: When our outputs are all unaware of DPMS modes other than off
3326 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3329 case DRM_MODE_DPMS_ON
:
3330 case DRM_MODE_DPMS_STANDBY
:
3331 case DRM_MODE_DPMS_SUSPEND
:
3332 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe
, plane
);
3333 ironlake_crtc_enable(crtc
);
3336 case DRM_MODE_DPMS_OFF
:
3337 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe
, plane
);
3338 ironlake_crtc_disable(crtc
);
3343 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3345 if (!enable
&& intel_crtc
->overlay
) {
3346 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3349 mutex_lock(&dev
->struct_mutex
);
3350 dev_priv
->mm
.interruptible
= false;
3351 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3352 dev_priv
->mm
.interruptible
= true;
3353 mutex_unlock(&dev
->struct_mutex
);
3356 /* Let userspace switch the overlay on again. In most cases userspace
3357 * has to recompute where to put it anyway.
3361 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3363 struct drm_device
*dev
= crtc
->dev
;
3364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3365 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3366 int pipe
= intel_crtc
->pipe
;
3367 int plane
= intel_crtc
->plane
;
3369 if (intel_crtc
->active
)
3372 intel_crtc
->active
= true;
3373 intel_update_watermarks(dev
);
3375 intel_enable_pll(dev_priv
, pipe
);
3376 intel_enable_pipe(dev_priv
, pipe
, false);
3377 intel_enable_plane(dev_priv
, plane
, pipe
);
3379 intel_crtc_load_lut(crtc
);
3380 intel_update_fbc(dev
);
3382 /* Give the overlay scaler a chance to enable if it's on this pipe */
3383 intel_crtc_dpms_overlay(intel_crtc
, true);
3384 intel_crtc_update_cursor(crtc
, true);
3387 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3389 struct drm_device
*dev
= crtc
->dev
;
3390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3391 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3392 int pipe
= intel_crtc
->pipe
;
3393 int plane
= intel_crtc
->plane
;
3395 if (!intel_crtc
->active
)
3398 /* Give the overlay scaler a chance to disable if it's on this pipe */
3399 intel_crtc_wait_for_pending_flips(crtc
);
3400 drm_vblank_off(dev
, pipe
);
3401 intel_crtc_dpms_overlay(intel_crtc
, false);
3402 intel_crtc_update_cursor(crtc
, false);
3404 if (dev_priv
->cfb_plane
== plane
)
3405 intel_disable_fbc(dev
);
3407 intel_disable_plane(dev_priv
, plane
, pipe
);
3408 intel_disable_pipe(dev_priv
, pipe
);
3409 intel_disable_pll(dev_priv
, pipe
);
3411 intel_crtc
->active
= false;
3412 intel_update_fbc(dev
);
3413 intel_update_watermarks(dev
);
3414 intel_clear_scanline_wait(dev
);
3417 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3419 /* XXX: When our outputs are all unaware of DPMS modes other than off
3420 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3423 case DRM_MODE_DPMS_ON
:
3424 case DRM_MODE_DPMS_STANDBY
:
3425 case DRM_MODE_DPMS_SUSPEND
:
3426 i9xx_crtc_enable(crtc
);
3428 case DRM_MODE_DPMS_OFF
:
3429 i9xx_crtc_disable(crtc
);
3435 * Sets the power management mode of the pipe and plane.
3437 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3439 struct drm_device
*dev
= crtc
->dev
;
3440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3441 struct drm_i915_master_private
*master_priv
;
3442 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3443 int pipe
= intel_crtc
->pipe
;
3446 if (intel_crtc
->dpms_mode
== mode
)
3449 intel_crtc
->dpms_mode
= mode
;
3451 dev_priv
->display
.dpms(crtc
, mode
);
3453 if (!dev
->primary
->master
)
3456 master_priv
= dev
->primary
->master
->driver_priv
;
3457 if (!master_priv
->sarea_priv
)
3460 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
3464 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3465 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3468 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3469 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3472 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3477 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3479 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
3480 struct drm_device
*dev
= crtc
->dev
;
3482 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
3483 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3484 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3487 mutex_lock(&dev
->struct_mutex
);
3488 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3489 mutex_unlock(&dev
->struct_mutex
);
3493 /* Prepare for a mode set.
3495 * Note we could be a lot smarter here. We need to figure out which outputs
3496 * will be enabled, which disabled (in short, how the config will changes)
3497 * and perform the minimum necessary steps to accomplish that, e.g. updating
3498 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3499 * panel fitting is in the proper state, etc.
3501 static void i9xx_crtc_prepare(struct drm_crtc
*crtc
)
3503 i9xx_crtc_disable(crtc
);
3506 static void i9xx_crtc_commit(struct drm_crtc
*crtc
)
3508 i9xx_crtc_enable(crtc
);
3511 static void ironlake_crtc_prepare(struct drm_crtc
*crtc
)
3513 ironlake_crtc_disable(crtc
);
3516 static void ironlake_crtc_commit(struct drm_crtc
*crtc
)
3518 ironlake_crtc_enable(crtc
);
3521 void intel_encoder_prepare(struct drm_encoder
*encoder
)
3523 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3524 /* lvds has its own version of prepare see intel_lvds_prepare */
3525 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
3528 void intel_encoder_commit(struct drm_encoder
*encoder
)
3530 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3531 struct drm_device
*dev
= encoder
->dev
;
3532 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3533 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
3535 /* lvds has its own version of commit see intel_lvds_commit */
3536 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
3538 if (HAS_PCH_CPT(dev
))
3539 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3542 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3544 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3546 drm_encoder_cleanup(encoder
);
3547 kfree(intel_encoder
);
3550 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3551 struct drm_display_mode
*mode
,
3552 struct drm_display_mode
*adjusted_mode
)
3554 struct drm_device
*dev
= crtc
->dev
;
3556 if (HAS_PCH_SPLIT(dev
)) {
3557 /* FDI link clock is fixed at 2.7G */
3558 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3562 /* All interlaced capable intel hw wants timings in frames. */
3563 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3568 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3570 return 400000; /* FIXME */
3573 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3578 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3583 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3588 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3592 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3594 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3597 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3598 case GC_DISPLAY_CLOCK_333_MHZ
:
3601 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3607 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3612 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3615 /* Assume that the hardware is in the high speed state. This
3616 * should be the default.
3618 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3619 case GC_CLOCK_133_200
:
3620 case GC_CLOCK_100_200
:
3622 case GC_CLOCK_166_250
:
3624 case GC_CLOCK_100_133
:
3628 /* Shouldn't happen */
3632 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3646 fdi_reduce_ratio(u32
*num
, u32
*den
)
3648 while (*num
> 0xffffff || *den
> 0xffffff) {
3655 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
3656 int link_clock
, struct fdi_m_n
*m_n
)
3658 m_n
->tu
= 64; /* default size */
3660 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3661 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3662 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3663 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3665 m_n
->link_m
= pixel_clock
;
3666 m_n
->link_n
= link_clock
;
3667 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3671 struct intel_watermark_params
{
3672 unsigned long fifo_size
;
3673 unsigned long max_wm
;
3674 unsigned long default_wm
;
3675 unsigned long guard_size
;
3676 unsigned long cacheline_size
;
3679 /* Pineview has different values for various configs */
3680 static const struct intel_watermark_params pineview_display_wm
= {
3681 PINEVIEW_DISPLAY_FIFO
,
3685 PINEVIEW_FIFO_LINE_SIZE
3687 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
3688 PINEVIEW_DISPLAY_FIFO
,
3690 PINEVIEW_DFT_HPLLOFF_WM
,
3692 PINEVIEW_FIFO_LINE_SIZE
3694 static const struct intel_watermark_params pineview_cursor_wm
= {
3695 PINEVIEW_CURSOR_FIFO
,
3696 PINEVIEW_CURSOR_MAX_WM
,
3697 PINEVIEW_CURSOR_DFT_WM
,
3698 PINEVIEW_CURSOR_GUARD_WM
,
3699 PINEVIEW_FIFO_LINE_SIZE
,
3701 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
3702 PINEVIEW_CURSOR_FIFO
,
3703 PINEVIEW_CURSOR_MAX_WM
,
3704 PINEVIEW_CURSOR_DFT_WM
,
3705 PINEVIEW_CURSOR_GUARD_WM
,
3706 PINEVIEW_FIFO_LINE_SIZE
3708 static const struct intel_watermark_params g4x_wm_info
= {
3715 static const struct intel_watermark_params g4x_cursor_wm_info
= {
3722 static const struct intel_watermark_params valleyview_wm_info
= {
3723 VALLEYVIEW_FIFO_SIZE
,
3729 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
3731 VALLEYVIEW_CURSOR_MAX_WM
,
3736 static const struct intel_watermark_params i965_cursor_wm_info
= {
3741 I915_FIFO_LINE_SIZE
,
3743 static const struct intel_watermark_params i945_wm_info
= {
3750 static const struct intel_watermark_params i915_wm_info
= {
3757 static const struct intel_watermark_params i855_wm_info
= {
3764 static const struct intel_watermark_params i830_wm_info
= {
3772 static const struct intel_watermark_params ironlake_display_wm_info
= {
3779 static const struct intel_watermark_params ironlake_cursor_wm_info
= {
3786 static const struct intel_watermark_params ironlake_display_srwm_info
= {
3787 ILK_DISPLAY_SR_FIFO
,
3788 ILK_DISPLAY_MAX_SRWM
,
3789 ILK_DISPLAY_DFT_SRWM
,
3793 static const struct intel_watermark_params ironlake_cursor_srwm_info
= {
3795 ILK_CURSOR_MAX_SRWM
,
3796 ILK_CURSOR_DFT_SRWM
,
3801 static const struct intel_watermark_params sandybridge_display_wm_info
= {
3808 static const struct intel_watermark_params sandybridge_cursor_wm_info
= {
3815 static const struct intel_watermark_params sandybridge_display_srwm_info
= {
3816 SNB_DISPLAY_SR_FIFO
,
3817 SNB_DISPLAY_MAX_SRWM
,
3818 SNB_DISPLAY_DFT_SRWM
,
3822 static const struct intel_watermark_params sandybridge_cursor_srwm_info
= {
3824 SNB_CURSOR_MAX_SRWM
,
3825 SNB_CURSOR_DFT_SRWM
,
3832 * intel_calculate_wm - calculate watermark level
3833 * @clock_in_khz: pixel clock
3834 * @wm: chip FIFO params
3835 * @pixel_size: display pixel size
3836 * @latency_ns: memory latency for the platform
3838 * Calculate the watermark level (the level at which the display plane will
3839 * start fetching from memory again). Each chip has a different display
3840 * FIFO size and allocation, so the caller needs to figure that out and pass
3841 * in the correct intel_watermark_params structure.
3843 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3844 * on the pixel size. When it reaches the watermark level, it'll start
3845 * fetching FIFO line sized based chunks from memory until the FIFO fills
3846 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3847 * will occur, and a display engine hang could result.
3849 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
3850 const struct intel_watermark_params
*wm
,
3853 unsigned long latency_ns
)
3855 long entries_required
, wm_size
;
3858 * Note: we need to make sure we don't overflow for various clock &
3860 * clocks go from a few thousand to several hundred thousand.
3861 * latency is usually a few thousand
3863 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
3865 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
3867 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
3869 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
3871 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
3873 /* Don't promote wm_size to unsigned... */
3874 if (wm_size
> (long)wm
->max_wm
)
3875 wm_size
= wm
->max_wm
;
3877 wm_size
= wm
->default_wm
;
3881 struct cxsr_latency
{
3884 unsigned long fsb_freq
;
3885 unsigned long mem_freq
;
3886 unsigned long display_sr
;
3887 unsigned long display_hpll_disable
;
3888 unsigned long cursor_sr
;
3889 unsigned long cursor_hpll_disable
;
3892 static const struct cxsr_latency cxsr_latency_table
[] = {
3893 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3894 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3895 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3896 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3897 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3899 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3900 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3901 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3902 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3903 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3905 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3906 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3907 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3908 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3909 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3911 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3912 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3913 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3914 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3915 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3917 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3918 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3919 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3920 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3921 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3923 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3924 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3925 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3926 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3927 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3930 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
3935 const struct cxsr_latency
*latency
;
3938 if (fsb
== 0 || mem
== 0)
3941 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
3942 latency
= &cxsr_latency_table
[i
];
3943 if (is_desktop
== latency
->is_desktop
&&
3944 is_ddr3
== latency
->is_ddr3
&&
3945 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
3949 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3954 static void pineview_disable_cxsr(struct drm_device
*dev
)
3956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3958 /* deactivate cxsr */
3959 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
3963 * Latency for FIFO fetches is dependent on several factors:
3964 * - memory configuration (speed, channels)
3966 * - current MCH state
3967 * It can be fairly high in some situations, so here we assume a fairly
3968 * pessimal value. It's a tradeoff between extra memory fetches (if we
3969 * set this value too high, the FIFO will fetch frequently to stay full)
3970 * and power consumption (set it too low to save power and we might see
3971 * FIFO underruns and display "flicker").
3973 * A value of 5us seems to be a good balance; safe for very low end
3974 * platforms but not overly aggressive on lower latency configs.
3976 static const int latency_ns
= 5000;
3978 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
3980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3981 uint32_t dsparb
= I915_READ(DSPARB
);
3984 size
= dsparb
& 0x7f;
3986 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
3988 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3989 plane
? "B" : "A", size
);
3994 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
3996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3997 uint32_t dsparb
= I915_READ(DSPARB
);
4000 size
= dsparb
& 0x1ff;
4002 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
4003 size
>>= 1; /* Convert to cachelines */
4005 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
4006 plane
? "B" : "A", size
);
4011 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
4013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4014 uint32_t dsparb
= I915_READ(DSPARB
);
4017 size
= dsparb
& 0x7f;
4018 size
>>= 2; /* Convert to cachelines */
4020 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
4027 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
4029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4030 uint32_t dsparb
= I915_READ(DSPARB
);
4033 size
= dsparb
& 0x7f;
4034 size
>>= 1; /* Convert to cachelines */
4036 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
4037 plane
? "B" : "A", size
);
4042 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
4044 struct drm_crtc
*crtc
, *enabled
= NULL
;
4046 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4047 if (crtc
->enabled
&& crtc
->fb
) {
4057 static void pineview_update_wm(struct drm_device
*dev
)
4059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4060 struct drm_crtc
*crtc
;
4061 const struct cxsr_latency
*latency
;
4065 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
4066 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
4068 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
4069 pineview_disable_cxsr(dev
);
4073 crtc
= single_enabled_crtc(dev
);
4075 int clock
= crtc
->mode
.clock
;
4076 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4079 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
4080 pineview_display_wm
.fifo_size
,
4081 pixel_size
, latency
->display_sr
);
4082 reg
= I915_READ(DSPFW1
);
4083 reg
&= ~DSPFW_SR_MASK
;
4084 reg
|= wm
<< DSPFW_SR_SHIFT
;
4085 I915_WRITE(DSPFW1
, reg
);
4086 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
4089 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
4090 pineview_display_wm
.fifo_size
,
4091 pixel_size
, latency
->cursor_sr
);
4092 reg
= I915_READ(DSPFW3
);
4093 reg
&= ~DSPFW_CURSOR_SR_MASK
;
4094 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
4095 I915_WRITE(DSPFW3
, reg
);
4097 /* Display HPLL off SR */
4098 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
4099 pineview_display_hplloff_wm
.fifo_size
,
4100 pixel_size
, latency
->display_hpll_disable
);
4101 reg
= I915_READ(DSPFW3
);
4102 reg
&= ~DSPFW_HPLL_SR_MASK
;
4103 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
4104 I915_WRITE(DSPFW3
, reg
);
4106 /* cursor HPLL off SR */
4107 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
4108 pineview_display_hplloff_wm
.fifo_size
,
4109 pixel_size
, latency
->cursor_hpll_disable
);
4110 reg
= I915_READ(DSPFW3
);
4111 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
4112 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
4113 I915_WRITE(DSPFW3
, reg
);
4114 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
4118 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
4119 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4121 pineview_disable_cxsr(dev
);
4122 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4126 static bool g4x_compute_wm0(struct drm_device
*dev
,
4128 const struct intel_watermark_params
*display
,
4129 int display_latency_ns
,
4130 const struct intel_watermark_params
*cursor
,
4131 int cursor_latency_ns
,
4135 struct drm_crtc
*crtc
;
4136 int htotal
, hdisplay
, clock
, pixel_size
;
4137 int line_time_us
, line_count
;
4138 int entries
, tlb_miss
;
4140 crtc
= intel_get_crtc_for_plane(dev
, plane
);
4141 if (crtc
->fb
== NULL
|| !crtc
->enabled
) {
4142 *cursor_wm
= cursor
->guard_size
;
4143 *plane_wm
= display
->guard_size
;
4147 htotal
= crtc
->mode
.htotal
;
4148 hdisplay
= crtc
->mode
.hdisplay
;
4149 clock
= crtc
->mode
.clock
;
4150 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4152 /* Use the small buffer method to calculate plane watermark */
4153 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
4154 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
4156 entries
+= tlb_miss
;
4157 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
4158 *plane_wm
= entries
+ display
->guard_size
;
4159 if (*plane_wm
> (int)display
->max_wm
)
4160 *plane_wm
= display
->max_wm
;
4162 /* Use the large buffer method to calculate cursor watermark */
4163 line_time_us
= ((htotal
* 1000) / clock
);
4164 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
4165 entries
= line_count
* 64 * pixel_size
;
4166 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
4168 entries
+= tlb_miss
;
4169 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
4170 *cursor_wm
= entries
+ cursor
->guard_size
;
4171 if (*cursor_wm
> (int)cursor
->max_wm
)
4172 *cursor_wm
= (int)cursor
->max_wm
;
4178 * Check the wm result.
4180 * If any calculated watermark values is larger than the maximum value that
4181 * can be programmed into the associated watermark register, that watermark
4184 static bool g4x_check_srwm(struct drm_device
*dev
,
4185 int display_wm
, int cursor_wm
,
4186 const struct intel_watermark_params
*display
,
4187 const struct intel_watermark_params
*cursor
)
4189 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4190 display_wm
, cursor_wm
);
4192 if (display_wm
> display
->max_wm
) {
4193 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4194 display_wm
, display
->max_wm
);
4198 if (cursor_wm
> cursor
->max_wm
) {
4199 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4200 cursor_wm
, cursor
->max_wm
);
4204 if (!(display_wm
|| cursor_wm
)) {
4205 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4212 static bool g4x_compute_srwm(struct drm_device
*dev
,
4215 const struct intel_watermark_params
*display
,
4216 const struct intel_watermark_params
*cursor
,
4217 int *display_wm
, int *cursor_wm
)
4219 struct drm_crtc
*crtc
;
4220 int hdisplay
, htotal
, pixel_size
, clock
;
4221 unsigned long line_time_us
;
4222 int line_count
, line_size
;
4227 *display_wm
= *cursor_wm
= 0;
4231 crtc
= intel_get_crtc_for_plane(dev
, plane
);
4232 hdisplay
= crtc
->mode
.hdisplay
;
4233 htotal
= crtc
->mode
.htotal
;
4234 clock
= crtc
->mode
.clock
;
4235 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4237 line_time_us
= (htotal
* 1000) / clock
;
4238 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
4239 line_size
= hdisplay
* pixel_size
;
4241 /* Use the minimum of the small and large buffer method for primary */
4242 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
4243 large
= line_count
* line_size
;
4245 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
4246 *display_wm
= entries
+ display
->guard_size
;
4248 /* calculate the self-refresh watermark for display cursor */
4249 entries
= line_count
* pixel_size
* 64;
4250 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
4251 *cursor_wm
= entries
+ cursor
->guard_size
;
4253 return g4x_check_srwm(dev
,
4254 *display_wm
, *cursor_wm
,
4258 static bool vlv_compute_drain_latency(struct drm_device
*dev
,
4260 int *plane_prec_mult
,
4262 int *cursor_prec_mult
,
4265 struct drm_crtc
*crtc
;
4266 int clock
, pixel_size
;
4269 crtc
= intel_get_crtc_for_plane(dev
, plane
);
4270 if (crtc
->fb
== NULL
|| !crtc
->enabled
)
4273 clock
= crtc
->mode
.clock
; /* VESA DOT Clock */
4274 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8; /* BPP */
4276 entries
= (clock
/ 1000) * pixel_size
;
4277 *plane_prec_mult
= (entries
> 256) ?
4278 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
4279 *plane_dl
= (64 * (*plane_prec_mult
) * 4) / ((clock
/ 1000) *
4282 entries
= (clock
/ 1000) * 4; /* BPP is always 4 for cursor */
4283 *cursor_prec_mult
= (entries
> 256) ?
4284 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
4285 *cursor_dl
= (64 * (*cursor_prec_mult
) * 4) / ((clock
/ 1000) * 4);
4291 * Update drain latency registers of memory arbiter
4293 * Valleyview SoC has a new memory arbiter and needs drain latency registers
4294 * to be programmed. Each plane has a drain latency multiplier and a drain
4298 static void vlv_update_drain_latency(struct drm_device
*dev
)
4300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4301 int planea_prec
, planea_dl
, planeb_prec
, planeb_dl
;
4302 int cursora_prec
, cursora_dl
, cursorb_prec
, cursorb_dl
;
4303 int plane_prec_mult
, cursor_prec_mult
; /* Precision multiplier is
4306 /* For plane A, Cursor A */
4307 if (vlv_compute_drain_latency(dev
, 0, &plane_prec_mult
, &planea_dl
,
4308 &cursor_prec_mult
, &cursora_dl
)) {
4309 cursora_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
4310 DDL_CURSORA_PRECISION_32
: DDL_CURSORA_PRECISION_16
;
4311 planea_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
4312 DDL_PLANEA_PRECISION_32
: DDL_PLANEA_PRECISION_16
;
4314 I915_WRITE(VLV_DDL1
, cursora_prec
|
4315 (cursora_dl
<< DDL_CURSORA_SHIFT
) |
4316 planea_prec
| planea_dl
);
4319 /* For plane B, Cursor B */
4320 if (vlv_compute_drain_latency(dev
, 1, &plane_prec_mult
, &planeb_dl
,
4321 &cursor_prec_mult
, &cursorb_dl
)) {
4322 cursorb_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
4323 DDL_CURSORB_PRECISION_32
: DDL_CURSORB_PRECISION_16
;
4324 planeb_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
4325 DDL_PLANEB_PRECISION_32
: DDL_PLANEB_PRECISION_16
;
4327 I915_WRITE(VLV_DDL2
, cursorb_prec
|
4328 (cursorb_dl
<< DDL_CURSORB_SHIFT
) |
4329 planeb_prec
| planeb_dl
);
4333 #define single_plane_enabled(mask) is_power_of_2(mask)
4335 static void valleyview_update_wm(struct drm_device
*dev
)
4337 static const int sr_latency_ns
= 12000;
4338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4339 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
4340 int plane_sr
, cursor_sr
;
4341 unsigned int enabled
= 0;
4343 vlv_update_drain_latency(dev
);
4345 if (g4x_compute_wm0(dev
, 0,
4346 &valleyview_wm_info
, latency_ns
,
4347 &valleyview_cursor_wm_info
, latency_ns
,
4348 &planea_wm
, &cursora_wm
))
4351 if (g4x_compute_wm0(dev
, 1,
4352 &valleyview_wm_info
, latency_ns
,
4353 &valleyview_cursor_wm_info
, latency_ns
,
4354 &planeb_wm
, &cursorb_wm
))
4357 plane_sr
= cursor_sr
= 0;
4358 if (single_plane_enabled(enabled
) &&
4359 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
4361 &valleyview_wm_info
,
4362 &valleyview_cursor_wm_info
,
4363 &plane_sr
, &cursor_sr
))
4364 I915_WRITE(FW_BLC_SELF_VLV
, FW_CSPWRDWNEN
);
4366 I915_WRITE(FW_BLC_SELF_VLV
,
4367 I915_READ(FW_BLC_SELF_VLV
) & ~FW_CSPWRDWNEN
);
4369 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4370 planea_wm
, cursora_wm
,
4371 planeb_wm
, cursorb_wm
,
4372 plane_sr
, cursor_sr
);
4375 (plane_sr
<< DSPFW_SR_SHIFT
) |
4376 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
4377 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
4380 (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
4381 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
4383 (I915_READ(DSPFW3
) | (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
)));
4386 static void g4x_update_wm(struct drm_device
*dev
)
4388 static const int sr_latency_ns
= 12000;
4389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4390 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
4391 int plane_sr
, cursor_sr
;
4392 unsigned int enabled
= 0;
4394 if (g4x_compute_wm0(dev
, 0,
4395 &g4x_wm_info
, latency_ns
,
4396 &g4x_cursor_wm_info
, latency_ns
,
4397 &planea_wm
, &cursora_wm
))
4400 if (g4x_compute_wm0(dev
, 1,
4401 &g4x_wm_info
, latency_ns
,
4402 &g4x_cursor_wm_info
, latency_ns
,
4403 &planeb_wm
, &cursorb_wm
))
4406 plane_sr
= cursor_sr
= 0;
4407 if (single_plane_enabled(enabled
) &&
4408 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
4411 &g4x_cursor_wm_info
,
4412 &plane_sr
, &cursor_sr
))
4413 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
4415 I915_WRITE(FW_BLC_SELF
,
4416 I915_READ(FW_BLC_SELF
) & ~FW_BLC_SELF_EN
);
4418 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4419 planea_wm
, cursora_wm
,
4420 planeb_wm
, cursorb_wm
,
4421 plane_sr
, cursor_sr
);
4424 (plane_sr
<< DSPFW_SR_SHIFT
) |
4425 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
4426 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
4429 (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
4430 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
4431 /* HPLL off in SR has some issues on G4x... disable it */
4433 (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
4434 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
4437 static void i965_update_wm(struct drm_device
*dev
)
4439 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4440 struct drm_crtc
*crtc
;
4444 /* Calc sr entries for one plane configs */
4445 crtc
= single_enabled_crtc(dev
);
4447 /* self-refresh has much higher latency */
4448 static const int sr_latency_ns
= 12000;
4449 int clock
= crtc
->mode
.clock
;
4450 int htotal
= crtc
->mode
.htotal
;
4451 int hdisplay
= crtc
->mode
.hdisplay
;
4452 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4453 unsigned long line_time_us
;
4456 line_time_us
= ((htotal
* 1000) / clock
);
4458 /* Use ns/us then divide to preserve precision */
4459 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
4460 pixel_size
* hdisplay
;
4461 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
4462 srwm
= I965_FIFO_SIZE
- entries
;
4466 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4469 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
4471 entries
= DIV_ROUND_UP(entries
,
4472 i965_cursor_wm_info
.cacheline_size
);
4473 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
4474 (entries
+ i965_cursor_wm_info
.guard_size
);
4476 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
4477 cursor_sr
= i965_cursor_wm_info
.max_wm
;
4479 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4480 "cursor %d\n", srwm
, cursor_sr
);
4482 if (IS_CRESTLINE(dev
))
4483 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
4485 /* Turn off self refresh if both pipes are enabled */
4486 if (IS_CRESTLINE(dev
))
4487 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
4491 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4494 /* 965 has limitations... */
4495 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
4496 (8 << 16) | (8 << 8) | (8 << 0));
4497 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
4498 /* update cursor SR watermark */
4499 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
4502 static void i9xx_update_wm(struct drm_device
*dev
)
4504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4505 const struct intel_watermark_params
*wm_info
;
4510 int planea_wm
, planeb_wm
;
4511 struct drm_crtc
*crtc
, *enabled
= NULL
;
4514 wm_info
= &i945_wm_info
;
4515 else if (!IS_GEN2(dev
))
4516 wm_info
= &i915_wm_info
;
4518 wm_info
= &i855_wm_info
;
4520 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
4521 crtc
= intel_get_crtc_for_plane(dev
, 0);
4522 if (crtc
->enabled
&& crtc
->fb
) {
4523 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
,
4525 crtc
->fb
->bits_per_pixel
/ 8,
4529 planea_wm
= fifo_size
- wm_info
->guard_size
;
4531 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
4532 crtc
= intel_get_crtc_for_plane(dev
, 1);
4533 if (crtc
->enabled
&& crtc
->fb
) {
4534 planeb_wm
= intel_calculate_wm(crtc
->mode
.clock
,
4536 crtc
->fb
->bits_per_pixel
/ 8,
4538 if (enabled
== NULL
)
4543 planeb_wm
= fifo_size
- wm_info
->guard_size
;
4545 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
4548 * Overlay gets an aggressive default since video jitter is bad.
4552 /* Play safe and disable self-refresh before adjusting watermarks. */
4553 if (IS_I945G(dev
) || IS_I945GM(dev
))
4554 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| 0);
4555 else if (IS_I915GM(dev
))
4556 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
4558 /* Calc sr entries for one plane configs */
4559 if (HAS_FW_BLC(dev
) && enabled
) {
4560 /* self-refresh has much higher latency */
4561 static const int sr_latency_ns
= 6000;
4562 int clock
= enabled
->mode
.clock
;
4563 int htotal
= enabled
->mode
.htotal
;
4564 int hdisplay
= enabled
->mode
.hdisplay
;
4565 int pixel_size
= enabled
->fb
->bits_per_pixel
/ 8;
4566 unsigned long line_time_us
;
4569 line_time_us
= (htotal
* 1000) / clock
;
4571 /* Use ns/us then divide to preserve precision */
4572 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
4573 pixel_size
* hdisplay
;
4574 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
4575 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
4576 srwm
= wm_info
->fifo_size
- entries
;
4580 if (IS_I945G(dev
) || IS_I945GM(dev
))
4581 I915_WRITE(FW_BLC_SELF
,
4582 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
4583 else if (IS_I915GM(dev
))
4584 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
4587 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4588 planea_wm
, planeb_wm
, cwm
, srwm
);
4590 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
4591 fwater_hi
= (cwm
& 0x1f);
4593 /* Set request length to 8 cachelines per fetch */
4594 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
4595 fwater_hi
= fwater_hi
| (1 << 8);
4597 I915_WRITE(FW_BLC
, fwater_lo
);
4598 I915_WRITE(FW_BLC2
, fwater_hi
);
4600 if (HAS_FW_BLC(dev
)) {
4602 if (IS_I945G(dev
) || IS_I945GM(dev
))
4603 I915_WRITE(FW_BLC_SELF
,
4604 FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
4605 else if (IS_I915GM(dev
))
4606 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
4607 DRM_DEBUG_KMS("memory self refresh enabled\n");
4609 DRM_DEBUG_KMS("memory self refresh disabled\n");
4613 static void i830_update_wm(struct drm_device
*dev
)
4615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4616 struct drm_crtc
*crtc
;
4620 crtc
= single_enabled_crtc(dev
);
4624 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
, &i830_wm_info
,
4625 dev_priv
->display
.get_fifo_size(dev
, 0),
4626 crtc
->fb
->bits_per_pixel
/ 8,
4628 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
4629 fwater_lo
|= (3<<8) | planea_wm
;
4631 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
4633 I915_WRITE(FW_BLC
, fwater_lo
);
4636 #define ILK_LP0_PLANE_LATENCY 700
4637 #define ILK_LP0_CURSOR_LATENCY 1300
4640 * Check the wm result.
4642 * If any calculated watermark values is larger than the maximum value that
4643 * can be programmed into the associated watermark register, that watermark
4646 static bool ironlake_check_srwm(struct drm_device
*dev
, int level
,
4647 int fbc_wm
, int display_wm
, int cursor_wm
,
4648 const struct intel_watermark_params
*display
,
4649 const struct intel_watermark_params
*cursor
)
4651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4653 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4654 " cursor %d\n", level
, display_wm
, fbc_wm
, cursor_wm
);
4656 if (fbc_wm
> SNB_FBC_MAX_SRWM
) {
4657 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4658 fbc_wm
, SNB_FBC_MAX_SRWM
, level
);
4660 /* fbc has it's own way to disable FBC WM */
4661 I915_WRITE(DISP_ARB_CTL
,
4662 I915_READ(DISP_ARB_CTL
) | DISP_FBC_WM_DIS
);
4666 if (display_wm
> display
->max_wm
) {
4667 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4668 display_wm
, SNB_DISPLAY_MAX_SRWM
, level
);
4672 if (cursor_wm
> cursor
->max_wm
) {
4673 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4674 cursor_wm
, SNB_CURSOR_MAX_SRWM
, level
);
4678 if (!(fbc_wm
|| display_wm
|| cursor_wm
)) {
4679 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level
, level
);
4687 * Compute watermark values of WM[1-3],
4689 static bool ironlake_compute_srwm(struct drm_device
*dev
, int level
, int plane
,
4691 const struct intel_watermark_params
*display
,
4692 const struct intel_watermark_params
*cursor
,
4693 int *fbc_wm
, int *display_wm
, int *cursor_wm
)
4695 struct drm_crtc
*crtc
;
4696 unsigned long line_time_us
;
4697 int hdisplay
, htotal
, pixel_size
, clock
;
4698 int line_count
, line_size
;
4703 *fbc_wm
= *display_wm
= *cursor_wm
= 0;
4707 crtc
= intel_get_crtc_for_plane(dev
, plane
);
4708 hdisplay
= crtc
->mode
.hdisplay
;
4709 htotal
= crtc
->mode
.htotal
;
4710 clock
= crtc
->mode
.clock
;
4711 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4713 line_time_us
= (htotal
* 1000) / clock
;
4714 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
4715 line_size
= hdisplay
* pixel_size
;
4717 /* Use the minimum of the small and large buffer method for primary */
4718 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
4719 large
= line_count
* line_size
;
4721 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
4722 *display_wm
= entries
+ display
->guard_size
;
4726 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4728 *fbc_wm
= DIV_ROUND_UP(*display_wm
* 64, line_size
) + 2;
4730 /* calculate the self-refresh watermark for display cursor */
4731 entries
= line_count
* pixel_size
* 64;
4732 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
4733 *cursor_wm
= entries
+ cursor
->guard_size
;
4735 return ironlake_check_srwm(dev
, level
,
4736 *fbc_wm
, *display_wm
, *cursor_wm
,
4740 static void ironlake_update_wm(struct drm_device
*dev
)
4742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4743 int fbc_wm
, plane_wm
, cursor_wm
;
4744 unsigned int enabled
;
4747 if (g4x_compute_wm0(dev
, 0,
4748 &ironlake_display_wm_info
,
4749 ILK_LP0_PLANE_LATENCY
,
4750 &ironlake_cursor_wm_info
,
4751 ILK_LP0_CURSOR_LATENCY
,
4752 &plane_wm
, &cursor_wm
)) {
4753 I915_WRITE(WM0_PIPEA_ILK
,
4754 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4755 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4756 " plane %d, " "cursor: %d\n",
4757 plane_wm
, cursor_wm
);
4761 if (g4x_compute_wm0(dev
, 1,
4762 &ironlake_display_wm_info
,
4763 ILK_LP0_PLANE_LATENCY
,
4764 &ironlake_cursor_wm_info
,
4765 ILK_LP0_CURSOR_LATENCY
,
4766 &plane_wm
, &cursor_wm
)) {
4767 I915_WRITE(WM0_PIPEB_ILK
,
4768 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4769 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4770 " plane %d, cursor: %d\n",
4771 plane_wm
, cursor_wm
);
4776 * Calculate and update the self-refresh watermark only when one
4777 * display plane is used.
4779 I915_WRITE(WM3_LP_ILK
, 0);
4780 I915_WRITE(WM2_LP_ILK
, 0);
4781 I915_WRITE(WM1_LP_ILK
, 0);
4783 if (!single_plane_enabled(enabled
))
4785 enabled
= ffs(enabled
) - 1;
4788 if (!ironlake_compute_srwm(dev
, 1, enabled
,
4789 ILK_READ_WM1_LATENCY() * 500,
4790 &ironlake_display_srwm_info
,
4791 &ironlake_cursor_srwm_info
,
4792 &fbc_wm
, &plane_wm
, &cursor_wm
))
4795 I915_WRITE(WM1_LP_ILK
,
4797 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4798 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4799 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4803 if (!ironlake_compute_srwm(dev
, 2, enabled
,
4804 ILK_READ_WM2_LATENCY() * 500,
4805 &ironlake_display_srwm_info
,
4806 &ironlake_cursor_srwm_info
,
4807 &fbc_wm
, &plane_wm
, &cursor_wm
))
4810 I915_WRITE(WM2_LP_ILK
,
4812 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4813 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4814 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4818 * WM3 is unsupported on ILK, probably because we don't have latency
4819 * data for that power state
4823 void sandybridge_update_wm(struct drm_device
*dev
)
4825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4826 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4828 int fbc_wm
, plane_wm
, cursor_wm
;
4829 unsigned int enabled
;
4832 if (g4x_compute_wm0(dev
, 0,
4833 &sandybridge_display_wm_info
, latency
,
4834 &sandybridge_cursor_wm_info
, latency
,
4835 &plane_wm
, &cursor_wm
)) {
4836 val
= I915_READ(WM0_PIPEA_ILK
);
4837 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
4838 I915_WRITE(WM0_PIPEA_ILK
, val
|
4839 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
4840 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4841 " plane %d, " "cursor: %d\n",
4842 plane_wm
, cursor_wm
);
4846 if (g4x_compute_wm0(dev
, 1,
4847 &sandybridge_display_wm_info
, latency
,
4848 &sandybridge_cursor_wm_info
, latency
,
4849 &plane_wm
, &cursor_wm
)) {
4850 val
= I915_READ(WM0_PIPEB_ILK
);
4851 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
4852 I915_WRITE(WM0_PIPEB_ILK
, val
|
4853 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
4854 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4855 " plane %d, cursor: %d\n",
4856 plane_wm
, cursor_wm
);
4860 /* IVB has 3 pipes */
4861 if (IS_IVYBRIDGE(dev
) &&
4862 g4x_compute_wm0(dev
, 2,
4863 &sandybridge_display_wm_info
, latency
,
4864 &sandybridge_cursor_wm_info
, latency
,
4865 &plane_wm
, &cursor_wm
)) {
4866 val
= I915_READ(WM0_PIPEC_IVB
);
4867 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
4868 I915_WRITE(WM0_PIPEC_IVB
, val
|
4869 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
4870 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4871 " plane %d, cursor: %d\n",
4872 plane_wm
, cursor_wm
);
4877 * Calculate and update the self-refresh watermark only when one
4878 * display plane is used.
4880 * SNB support 3 levels of watermark.
4882 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4883 * and disabled in the descending order
4886 I915_WRITE(WM3_LP_ILK
, 0);
4887 I915_WRITE(WM2_LP_ILK
, 0);
4888 I915_WRITE(WM1_LP_ILK
, 0);
4890 if (!single_plane_enabled(enabled
) ||
4891 dev_priv
->sprite_scaling_enabled
)
4893 enabled
= ffs(enabled
) - 1;
4896 if (!ironlake_compute_srwm(dev
, 1, enabled
,
4897 SNB_READ_WM1_LATENCY() * 500,
4898 &sandybridge_display_srwm_info
,
4899 &sandybridge_cursor_srwm_info
,
4900 &fbc_wm
, &plane_wm
, &cursor_wm
))
4903 I915_WRITE(WM1_LP_ILK
,
4905 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4906 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4907 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4911 if (!ironlake_compute_srwm(dev
, 2, enabled
,
4912 SNB_READ_WM2_LATENCY() * 500,
4913 &sandybridge_display_srwm_info
,
4914 &sandybridge_cursor_srwm_info
,
4915 &fbc_wm
, &plane_wm
, &cursor_wm
))
4918 I915_WRITE(WM2_LP_ILK
,
4920 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4921 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4922 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4926 if (!ironlake_compute_srwm(dev
, 3, enabled
,
4927 SNB_READ_WM3_LATENCY() * 500,
4928 &sandybridge_display_srwm_info
,
4929 &sandybridge_cursor_srwm_info
,
4930 &fbc_wm
, &plane_wm
, &cursor_wm
))
4933 I915_WRITE(WM3_LP_ILK
,
4935 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4936 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4937 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4942 sandybridge_compute_sprite_wm(struct drm_device
*dev
, int plane
,
4943 uint32_t sprite_width
, int pixel_size
,
4944 const struct intel_watermark_params
*display
,
4945 int display_latency_ns
, int *sprite_wm
)
4947 struct drm_crtc
*crtc
;
4949 int entries
, tlb_miss
;
4951 crtc
= intel_get_crtc_for_plane(dev
, plane
);
4952 if (crtc
->fb
== NULL
|| !crtc
->enabled
) {
4953 *sprite_wm
= display
->guard_size
;
4957 clock
= crtc
->mode
.clock
;
4959 /* Use the small buffer method to calculate the sprite watermark */
4960 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
4961 tlb_miss
= display
->fifo_size
*display
->cacheline_size
-
4964 entries
+= tlb_miss
;
4965 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
4966 *sprite_wm
= entries
+ display
->guard_size
;
4967 if (*sprite_wm
> (int)display
->max_wm
)
4968 *sprite_wm
= display
->max_wm
;
4974 sandybridge_compute_sprite_srwm(struct drm_device
*dev
, int plane
,
4975 uint32_t sprite_width
, int pixel_size
,
4976 const struct intel_watermark_params
*display
,
4977 int latency_ns
, int *sprite_wm
)
4979 struct drm_crtc
*crtc
;
4980 unsigned long line_time_us
;
4982 int line_count
, line_size
;
4991 crtc
= intel_get_crtc_for_plane(dev
, plane
);
4992 clock
= crtc
->mode
.clock
;
4998 line_time_us
= (sprite_width
* 1000) / clock
;
4999 if (!line_time_us
) {
5004 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
5005 line_size
= sprite_width
* pixel_size
;
5007 /* Use the minimum of the small and large buffer method for primary */
5008 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
5009 large
= line_count
* line_size
;
5011 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
5012 *sprite_wm
= entries
+ display
->guard_size
;
5014 return *sprite_wm
> 0x3ff ? false : true;
5017 static void sandybridge_update_sprite_wm(struct drm_device
*dev
, int pipe
,
5018 uint32_t sprite_width
, int pixel_size
)
5020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5021 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
5028 reg
= WM0_PIPEA_ILK
;
5031 reg
= WM0_PIPEB_ILK
;
5034 reg
= WM0_PIPEC_IVB
;
5037 return; /* bad pipe */
5040 ret
= sandybridge_compute_sprite_wm(dev
, pipe
, sprite_width
, pixel_size
,
5041 &sandybridge_display_wm_info
,
5042 latency
, &sprite_wm
);
5044 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
5049 val
= I915_READ(reg
);
5050 val
&= ~WM0_PIPE_SPRITE_MASK
;
5051 I915_WRITE(reg
, val
| (sprite_wm
<< WM0_PIPE_SPRITE_SHIFT
));
5052 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe
, sprite_wm
);
5055 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
5057 &sandybridge_display_srwm_info
,
5058 SNB_READ_WM1_LATENCY() * 500,
5061 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
5065 I915_WRITE(WM1S_LP_ILK
, sprite_wm
);
5067 /* Only IVB has two more LP watermarks for sprite */
5068 if (!IS_IVYBRIDGE(dev
))
5071 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
5073 &sandybridge_display_srwm_info
,
5074 SNB_READ_WM2_LATENCY() * 500,
5077 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
5081 I915_WRITE(WM2S_LP_IVB
, sprite_wm
);
5083 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
5085 &sandybridge_display_srwm_info
,
5086 SNB_READ_WM3_LATENCY() * 500,
5089 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
5093 I915_WRITE(WM3S_LP_IVB
, sprite_wm
);
5097 * intel_update_watermarks - update FIFO watermark values based on current modes
5099 * Calculate watermark values for the various WM regs based on current mode
5100 * and plane configuration.
5102 * There are several cases to deal with here:
5103 * - normal (i.e. non-self-refresh)
5104 * - self-refresh (SR) mode
5105 * - lines are large relative to FIFO size (buffer can hold up to 2)
5106 * - lines are small relative to FIFO size (buffer can hold more than 2
5107 * lines), so need to account for TLB latency
5109 * The normal calculation is:
5110 * watermark = dotclock * bytes per pixel * latency
5111 * where latency is platform & configuration dependent (we assume pessimal
5114 * The SR calculation is:
5115 * watermark = (trunc(latency/line time)+1) * surface width *
5118 * line time = htotal / dotclock
5119 * surface width = hdisplay for normal plane and 64 for cursor
5120 * and latency is assumed to be high, as above.
5122 * The final value programmed to the register should always be rounded up,
5123 * and include an extra 2 entries to account for clock crossings.
5125 * We don't use the sprite, so we can ignore that. And on Crestline we have
5126 * to set the non-SR watermarks to 8.
5128 static void intel_update_watermarks(struct drm_device
*dev
)
5130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5132 if (dev_priv
->display
.update_wm
)
5133 dev_priv
->display
.update_wm(dev
);
5136 void intel_update_sprite_watermarks(struct drm_device
*dev
, int pipe
,
5137 uint32_t sprite_width
, int pixel_size
)
5139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5141 if (dev_priv
->display
.update_sprite_wm
)
5142 dev_priv
->display
.update_sprite_wm(dev
, pipe
, sprite_width
,
5146 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5148 if (i915_panel_use_ssc
>= 0)
5149 return i915_panel_use_ssc
!= 0;
5150 return dev_priv
->lvds_use_ssc
5151 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5155 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
5156 * @crtc: CRTC structure
5157 * @mode: requested mode
5159 * A pipe may be connected to one or more outputs. Based on the depth of the
5160 * attached framebuffer, choose a good color depth to use on the pipe.
5162 * If possible, match the pipe depth to the fb depth. In some cases, this
5163 * isn't ideal, because the connected output supports a lesser or restricted
5164 * set of depths. Resolve that here:
5165 * LVDS typically supports only 6bpc, so clamp down in that case
5166 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
5167 * Displays may support a restricted set as well, check EDID and clamp as
5169 * DP may want to dither down to 6bpc to fit larger modes
5172 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
5173 * true if they don't match).
5175 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
5176 unsigned int *pipe_bpp
,
5177 struct drm_display_mode
*mode
)
5179 struct drm_device
*dev
= crtc
->dev
;
5180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5181 struct drm_encoder
*encoder
;
5182 struct drm_connector
*connector
;
5183 unsigned int display_bpc
= UINT_MAX
, bpc
;
5185 /* Walk the encoders & connectors on this crtc, get min bpc */
5186 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
5187 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5189 if (encoder
->crtc
!= crtc
)
5192 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
5193 unsigned int lvds_bpc
;
5195 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
5201 if (lvds_bpc
< display_bpc
) {
5202 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
5203 display_bpc
= lvds_bpc
;
5208 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
) {
5209 /* Use VBT settings if we have an eDP panel */
5210 unsigned int edp_bpc
= dev_priv
->edp
.bpp
/ 3;
5212 if (edp_bpc
< display_bpc
) {
5213 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc
, edp_bpc
);
5214 display_bpc
= edp_bpc
;
5219 /* Not one of the known troublemakers, check the EDID */
5220 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
5222 if (connector
->encoder
!= encoder
)
5225 /* Don't use an invalid EDID bpc value */
5226 if (connector
->display_info
.bpc
&&
5227 connector
->display_info
.bpc
< display_bpc
) {
5228 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
5229 display_bpc
= connector
->display_info
.bpc
;
5234 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5235 * through, clamp it down. (Note: >12bpc will be caught below.)
5237 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
5238 if (display_bpc
> 8 && display_bpc
< 12) {
5239 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5242 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5248 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
5249 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5254 * We could just drive the pipe at the highest bpc all the time and
5255 * enable dithering as needed, but that costs bandwidth. So choose
5256 * the minimum value that expresses the full color range of the fb but
5257 * also stays within the max display bpc discovered above.
5260 switch (crtc
->fb
->depth
) {
5262 bpc
= 8; /* since we go through a colormap */
5266 bpc
= 6; /* min is 18bpp */
5278 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5279 bpc
= min((unsigned int)8, display_bpc
);
5283 display_bpc
= min(display_bpc
, bpc
);
5285 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5288 *pipe_bpp
= display_bpc
* 3;
5290 return display_bpc
!= bpc
;
5293 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
5295 struct drm_device
*dev
= crtc
->dev
;
5296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5299 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5300 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5301 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
5302 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5304 } else if (!IS_GEN2(dev
)) {
5313 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
5314 intel_clock_t
*clock
)
5316 /* SDVO TV has fixed PLL values depend on its clock range,
5317 this mirrors vbios setting. */
5318 if (adjusted_mode
->clock
>= 100000
5319 && adjusted_mode
->clock
< 140500) {
5325 } else if (adjusted_mode
->clock
>= 140500
5326 && adjusted_mode
->clock
<= 200000) {
5335 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
5336 intel_clock_t
*clock
,
5337 intel_clock_t
*reduced_clock
)
5339 struct drm_device
*dev
= crtc
->dev
;
5340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5341 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5342 int pipe
= intel_crtc
->pipe
;
5345 if (IS_PINEVIEW(dev
)) {
5346 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
5348 fp2
= (1 << reduced_clock
->n
) << 16 |
5349 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
5351 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
5353 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
5357 I915_WRITE(FP0(pipe
), fp
);
5359 intel_crtc
->lowfreq_avail
= false;
5360 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5361 reduced_clock
&& i915_powersave
) {
5362 I915_WRITE(FP1(pipe
), fp2
);
5363 intel_crtc
->lowfreq_avail
= true;
5365 I915_WRITE(FP1(pipe
), fp
);
5369 static void intel_update_lvds(struct drm_crtc
*crtc
, intel_clock_t
*clock
,
5370 struct drm_display_mode
*adjusted_mode
)
5372 struct drm_device
*dev
= crtc
->dev
;
5373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5374 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5375 int pipe
= intel_crtc
->pipe
;
5376 u32 temp
, lvds_sync
= 0;
5378 temp
= I915_READ(LVDS
);
5379 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
5381 temp
|= LVDS_PIPEB_SELECT
;
5383 temp
&= ~LVDS_PIPEB_SELECT
;
5385 /* set the corresponsding LVDS_BORDER bit */
5386 temp
|= dev_priv
->lvds_border_bits
;
5387 /* Set the B0-B3 data pairs corresponding to whether we're going to
5388 * set the DPLLs for dual-channel mode or not.
5391 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
5393 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
5395 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5396 * appropriately here, but we need to look more thoroughly into how
5397 * panels behave in the two modes.
5399 /* set the dithering flag on LVDS as needed */
5400 if (INTEL_INFO(dev
)->gen
>= 4) {
5401 if (dev_priv
->lvds_dither
)
5402 temp
|= LVDS_ENABLE_DITHER
;
5404 temp
&= ~LVDS_ENABLE_DITHER
;
5406 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
5407 lvds_sync
|= LVDS_HSYNC_POLARITY
;
5408 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
5409 lvds_sync
|= LVDS_VSYNC_POLARITY
;
5410 if ((temp
& (LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
))
5412 char flags
[2] = "-+";
5413 DRM_INFO("Changing LVDS panel from "
5414 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5415 flags
[!(temp
& LVDS_HSYNC_POLARITY
)],
5416 flags
[!(temp
& LVDS_VSYNC_POLARITY
)],
5417 flags
[!(lvds_sync
& LVDS_HSYNC_POLARITY
)],
5418 flags
[!(lvds_sync
& LVDS_VSYNC_POLARITY
)]);
5419 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
5422 I915_WRITE(LVDS
, temp
);
5425 static void i9xx_update_pll(struct drm_crtc
*crtc
,
5426 struct drm_display_mode
*mode
,
5427 struct drm_display_mode
*adjusted_mode
,
5428 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
5431 struct drm_device
*dev
= crtc
->dev
;
5432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5433 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5434 int pipe
= intel_crtc
->pipe
;
5438 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
5439 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
5441 dpll
= DPLL_VGA_MODE_DIS
;
5443 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
5444 dpll
|= DPLLB_MODE_LVDS
;
5446 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5448 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5449 if (pixel_multiplier
> 1) {
5450 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5451 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
5453 dpll
|= DPLL_DVO_HIGH_SPEED
;
5455 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
5456 dpll
|= DPLL_DVO_HIGH_SPEED
;
5458 /* compute bitmask from p1 value */
5459 if (IS_PINEVIEW(dev
))
5460 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5462 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5463 if (IS_G4X(dev
) && reduced_clock
)
5464 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5466 switch (clock
->p2
) {
5468 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5471 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5474 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5477 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5480 if (INTEL_INFO(dev
)->gen
>= 4)
5481 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5483 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
5484 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5485 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
5486 /* XXX: just matching BIOS for now */
5487 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5489 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5490 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5491 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5493 dpll
|= PLL_REF_INPUT_DREFCLK
;
5495 dpll
|= DPLL_VCO_ENABLE
;
5496 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
5497 POSTING_READ(DPLL(pipe
));
5500 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5501 * This is an exception to the general rule that mode_set doesn't turn
5504 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
5505 intel_update_lvds(crtc
, clock
, adjusted_mode
);
5507 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
5508 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5510 I915_WRITE(DPLL(pipe
), dpll
);
5512 /* Wait for the clocks to stabilize. */
5513 POSTING_READ(DPLL(pipe
));
5516 if (INTEL_INFO(dev
)->gen
>= 4) {
5519 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5521 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5525 I915_WRITE(DPLL_MD(pipe
), temp
);
5527 /* The pixel multiplier can only be updated once the
5528 * DPLL is enabled and the clocks are stable.
5530 * So write it again.
5532 I915_WRITE(DPLL(pipe
), dpll
);
5536 static void i8xx_update_pll(struct drm_crtc
*crtc
,
5537 struct drm_display_mode
*adjusted_mode
,
5538 intel_clock_t
*clock
,
5541 struct drm_device
*dev
= crtc
->dev
;
5542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5543 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5544 int pipe
= intel_crtc
->pipe
;
5547 dpll
= DPLL_VGA_MODE_DIS
;
5549 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
5550 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5553 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5555 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5557 dpll
|= PLL_P2_DIVIDE_BY_4
;
5560 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
5561 /* XXX: just matching BIOS for now */
5562 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5564 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5565 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5566 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5568 dpll
|= PLL_REF_INPUT_DREFCLK
;
5570 dpll
|= DPLL_VCO_ENABLE
;
5571 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
5572 POSTING_READ(DPLL(pipe
));
5575 I915_WRITE(DPLL(pipe
), dpll
);
5577 /* Wait for the clocks to stabilize. */
5578 POSTING_READ(DPLL(pipe
));
5581 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5582 * This is an exception to the general rule that mode_set doesn't turn
5585 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
5586 intel_update_lvds(crtc
, clock
, adjusted_mode
);
5588 /* The pixel multiplier can only be updated once the
5589 * DPLL is enabled and the clocks are stable.
5591 * So write it again.
5593 I915_WRITE(DPLL(pipe
), dpll
);
5596 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
5597 struct drm_display_mode
*mode
,
5598 struct drm_display_mode
*adjusted_mode
,
5600 struct drm_framebuffer
*old_fb
)
5602 struct drm_device
*dev
= crtc
->dev
;
5603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5604 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5605 int pipe
= intel_crtc
->pipe
;
5606 int plane
= intel_crtc
->plane
;
5607 int refclk
, num_connectors
= 0;
5608 intel_clock_t clock
, reduced_clock
;
5609 u32 dspcntr
, pipeconf
, vsyncshift
;
5610 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
5611 bool is_lvds
= false, is_tv
= false, is_dp
= false;
5612 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5613 struct intel_encoder
*encoder
;
5614 const intel_limit_t
*limit
;
5617 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5618 if (encoder
->base
.crtc
!= crtc
)
5621 switch (encoder
->type
) {
5622 case INTEL_OUTPUT_LVDS
:
5625 case INTEL_OUTPUT_SDVO
:
5626 case INTEL_OUTPUT_HDMI
:
5628 if (encoder
->needs_tv_clock
)
5631 case INTEL_OUTPUT_TVOUT
:
5634 case INTEL_OUTPUT_DISPLAYPORT
:
5642 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
5645 * Returns a set of divisors for the desired target clock with the given
5646 * refclk, or FALSE. The returned values represent the clock equation:
5647 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5649 limit
= intel_limit(crtc
, refclk
);
5650 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
5653 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5657 /* Ensure that the cursor is valid for the new mode before changing... */
5658 intel_crtc_update_cursor(crtc
, true);
5660 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5662 * Ensure we match the reduced clock's P to the target clock.
5663 * If the clocks don't match, we can't switch the display clock
5664 * by using the FP0/FP1. In such case we will disable the LVDS
5665 * downclock feature.
5667 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
5668 dev_priv
->lvds_downclock
,
5674 if (is_sdvo
&& is_tv
)
5675 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
5677 i9xx_update_pll_dividers(crtc
, &clock
, has_reduced_clock
?
5678 &reduced_clock
: NULL
);
5681 i8xx_update_pll(crtc
, adjusted_mode
, &clock
, num_connectors
);
5683 i9xx_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
5684 has_reduced_clock
? &reduced_clock
: NULL
,
5687 /* setup pipeconf */
5688 pipeconf
= I915_READ(PIPECONF(pipe
));
5690 /* Set up the display plane register */
5691 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
5694 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
5696 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
5698 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
5699 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5702 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5706 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
5707 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
5709 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
5712 /* default to 8bpc */
5713 pipeconf
&= ~(PIPECONF_BPP_MASK
| PIPECONF_DITHER_EN
);
5715 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
5716 pipeconf
|= PIPECONF_BPP_6
|
5717 PIPECONF_DITHER_EN
|
5718 PIPECONF_DITHER_TYPE_SP
;
5722 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
5723 drm_mode_debug_printmodeline(mode
);
5725 if (HAS_PIPE_CXSR(dev
)) {
5726 if (intel_crtc
->lowfreq_avail
) {
5727 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5728 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
5730 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5731 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
5735 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
5736 if (!IS_GEN2(dev
) &&
5737 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5738 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
5739 /* the chip adds 2 halflines automatically */
5740 adjusted_mode
->crtc_vtotal
-= 1;
5741 adjusted_mode
->crtc_vblank_end
-= 1;
5742 vsyncshift
= adjusted_mode
->crtc_hsync_start
5743 - adjusted_mode
->crtc_htotal
/2;
5745 pipeconf
|= PIPECONF_PROGRESSIVE
;
5750 I915_WRITE(VSYNCSHIFT(pipe
), vsyncshift
);
5752 I915_WRITE(HTOTAL(pipe
),
5753 (adjusted_mode
->crtc_hdisplay
- 1) |
5754 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5755 I915_WRITE(HBLANK(pipe
),
5756 (adjusted_mode
->crtc_hblank_start
- 1) |
5757 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5758 I915_WRITE(HSYNC(pipe
),
5759 (adjusted_mode
->crtc_hsync_start
- 1) |
5760 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5762 I915_WRITE(VTOTAL(pipe
),
5763 (adjusted_mode
->crtc_vdisplay
- 1) |
5764 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
5765 I915_WRITE(VBLANK(pipe
),
5766 (adjusted_mode
->crtc_vblank_start
- 1) |
5767 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
5768 I915_WRITE(VSYNC(pipe
),
5769 (adjusted_mode
->crtc_vsync_start
- 1) |
5770 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5772 /* pipesrc and dspsize control the size that is scaled from,
5773 * which should always be the user's requested size.
5775 I915_WRITE(DSPSIZE(plane
),
5776 ((mode
->vdisplay
- 1) << 16) |
5777 (mode
->hdisplay
- 1));
5778 I915_WRITE(DSPPOS(plane
), 0);
5779 I915_WRITE(PIPESRC(pipe
),
5780 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
5782 I915_WRITE(PIPECONF(pipe
), pipeconf
);
5783 POSTING_READ(PIPECONF(pipe
));
5784 intel_enable_pipe(dev_priv
, pipe
, false);
5786 intel_wait_for_vblank(dev
, pipe
);
5788 I915_WRITE(DSPCNTR(plane
), dspcntr
);
5789 POSTING_READ(DSPCNTR(plane
));
5790 intel_enable_plane(dev_priv
, plane
, pipe
);
5792 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
5794 intel_update_watermarks(dev
);
5800 * Initialize reference clocks when the driver loads
5802 void ironlake_init_pch_refclk(struct drm_device
*dev
)
5804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5805 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5806 struct intel_encoder
*encoder
;
5808 bool has_lvds
= false;
5809 bool has_cpu_edp
= false;
5810 bool has_pch_edp
= false;
5811 bool has_panel
= false;
5812 bool has_ck505
= false;
5813 bool can_ssc
= false;
5815 /* We need to take the global config into account */
5816 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5818 switch (encoder
->type
) {
5819 case INTEL_OUTPUT_LVDS
:
5823 case INTEL_OUTPUT_EDP
:
5825 if (intel_encoder_is_pch_edp(&encoder
->base
))
5833 if (HAS_PCH_IBX(dev
)) {
5834 has_ck505
= dev_priv
->display_clock_mode
;
5835 can_ssc
= has_ck505
;
5841 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5842 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
5845 /* Ironlake: try to setup display ref clock before DPLL
5846 * enabling. This is only under driver's control after
5847 * PCH B stepping, previous chipset stepping should be
5848 * ignoring this setting.
5850 temp
= I915_READ(PCH_DREF_CONTROL
);
5851 /* Always enable nonspread source */
5852 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5855 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
5857 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5860 temp
&= ~DREF_SSC_SOURCE_MASK
;
5861 temp
|= DREF_SSC_SOURCE_ENABLE
;
5863 /* SSC must be turned on before enabling the CPU output */
5864 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5865 DRM_DEBUG_KMS("Using SSC on panel\n");
5866 temp
|= DREF_SSC1_ENABLE
;
5868 temp
&= ~DREF_SSC1_ENABLE
;
5870 /* Get SSC going before enabling the outputs */
5871 I915_WRITE(PCH_DREF_CONTROL
, temp
);
5872 POSTING_READ(PCH_DREF_CONTROL
);
5875 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5877 /* Enable CPU source on CPU attached eDP */
5879 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5880 DRM_DEBUG_KMS("Using SSC on eDP\n");
5881 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5884 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5886 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5888 I915_WRITE(PCH_DREF_CONTROL
, temp
);
5889 POSTING_READ(PCH_DREF_CONTROL
);
5892 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5894 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5896 /* Turn off CPU output */
5897 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5899 I915_WRITE(PCH_DREF_CONTROL
, temp
);
5900 POSTING_READ(PCH_DREF_CONTROL
);
5903 /* Turn off the SSC source */
5904 temp
&= ~DREF_SSC_SOURCE_MASK
;
5905 temp
|= DREF_SSC_SOURCE_DISABLE
;
5908 temp
&= ~ DREF_SSC1_ENABLE
;
5910 I915_WRITE(PCH_DREF_CONTROL
, temp
);
5911 POSTING_READ(PCH_DREF_CONTROL
);
5916 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5918 struct drm_device
*dev
= crtc
->dev
;
5919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5920 struct intel_encoder
*encoder
;
5921 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5922 struct intel_encoder
*edp_encoder
= NULL
;
5923 int num_connectors
= 0;
5924 bool is_lvds
= false;
5926 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5927 if (encoder
->base
.crtc
!= crtc
)
5930 switch (encoder
->type
) {
5931 case INTEL_OUTPUT_LVDS
:
5934 case INTEL_OUTPUT_EDP
:
5935 edp_encoder
= encoder
;
5941 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5942 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5943 dev_priv
->lvds_ssc_freq
);
5944 return dev_priv
->lvds_ssc_freq
* 1000;
5950 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5951 struct drm_display_mode
*mode
,
5952 struct drm_display_mode
*adjusted_mode
,
5954 struct drm_framebuffer
*old_fb
)
5956 struct drm_device
*dev
= crtc
->dev
;
5957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5958 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5959 int pipe
= intel_crtc
->pipe
;
5960 int plane
= intel_crtc
->plane
;
5961 int refclk
, num_connectors
= 0;
5962 intel_clock_t clock
, reduced_clock
;
5963 u32 dpll
, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
5964 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
5965 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
5966 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5967 struct intel_encoder
*encoder
, *edp_encoder
= NULL
;
5968 const intel_limit_t
*limit
;
5970 struct fdi_m_n m_n
= {0};
5973 int target_clock
, pixel_multiplier
, lane
, link_bw
, factor
;
5974 unsigned int pipe_bpp
;
5976 bool is_cpu_edp
= false, is_pch_edp
= false;
5978 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5979 if (encoder
->base
.crtc
!= crtc
)
5982 switch (encoder
->type
) {
5983 case INTEL_OUTPUT_LVDS
:
5986 case INTEL_OUTPUT_SDVO
:
5987 case INTEL_OUTPUT_HDMI
:
5989 if (encoder
->needs_tv_clock
)
5992 case INTEL_OUTPUT_TVOUT
:
5995 case INTEL_OUTPUT_ANALOG
:
5998 case INTEL_OUTPUT_DISPLAYPORT
:
6001 case INTEL_OUTPUT_EDP
:
6003 if (intel_encoder_is_pch_edp(&encoder
->base
))
6007 edp_encoder
= encoder
;
6014 refclk
= ironlake_get_refclk(crtc
);
6017 * Returns a set of divisors for the desired target clock with the given
6018 * refclk, or FALSE. The returned values represent the clock equation:
6019 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6021 limit
= intel_limit(crtc
, refclk
);
6022 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
6025 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6029 /* Ensure that the cursor is valid for the new mode before changing... */
6030 intel_crtc_update_cursor(crtc
, true);
6032 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6034 * Ensure we match the reduced clock's P to the target clock.
6035 * If the clocks don't match, we can't switch the display clock
6036 * by using the FP0/FP1. In such case we will disable the LVDS
6037 * downclock feature.
6039 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
6040 dev_priv
->lvds_downclock
,
6045 /* SDVO TV has fixed PLL values depend on its clock range,
6046 this mirrors vbios setting. */
6047 if (is_sdvo
&& is_tv
) {
6048 if (adjusted_mode
->clock
>= 100000
6049 && adjusted_mode
->clock
< 140500) {
6055 } else if (adjusted_mode
->clock
>= 140500
6056 && adjusted_mode
->clock
<= 200000) {
6066 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
6068 /* CPU eDP doesn't require FDI link, so just set DP M/N
6069 according to current link config */
6071 target_clock
= mode
->clock
;
6072 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
6074 /* [e]DP over FDI requires target mode clock
6075 instead of link clock */
6077 target_clock
= mode
->clock
;
6079 target_clock
= adjusted_mode
->clock
;
6081 /* FDI is a binary signal running at ~2.7GHz, encoding
6082 * each output octet as 10 bits. The actual frequency
6083 * is stored as a divider into a 100MHz clock, and the
6084 * mode pixel clock is stored in units of 1KHz.
6085 * Hence the bw of each lane in terms of the mode signal
6088 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
6091 /* determine panel color depth */
6092 temp
= I915_READ(PIPECONF(pipe
));
6093 temp
&= ~PIPE_BPC_MASK
;
6094 dither
= intel_choose_pipe_bpp_dither(crtc
, &pipe_bpp
, mode
);
6109 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
6116 intel_crtc
->bpp
= pipe_bpp
;
6117 I915_WRITE(PIPECONF(pipe
), temp
);
6121 * Account for spread spectrum to avoid
6122 * oversubscribing the link. Max center spread
6123 * is 2.5%; use 5% for safety's sake.
6125 u32 bps
= target_clock
* intel_crtc
->bpp
* 21 / 20;
6126 lane
= bps
/ (link_bw
* 8) + 1;
6129 intel_crtc
->fdi_lanes
= lane
;
6131 if (pixel_multiplier
> 1)
6132 link_bw
*= pixel_multiplier
;
6133 ironlake_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
,
6136 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
6137 if (has_reduced_clock
)
6138 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
6141 /* Enable autotuning of the PLL clock (if permissible) */
6144 if ((intel_panel_use_ssc(dev_priv
) &&
6145 dev_priv
->lvds_ssc_freq
== 100) ||
6146 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
6148 } else if (is_sdvo
&& is_tv
)
6151 if (clock
.m
< factor
* clock
.n
)
6157 dpll
|= DPLLB_MODE_LVDS
;
6159 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6161 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
6162 if (pixel_multiplier
> 1) {
6163 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
6165 dpll
|= DPLL_DVO_HIGH_SPEED
;
6167 if (is_dp
&& !is_cpu_edp
)
6168 dpll
|= DPLL_DVO_HIGH_SPEED
;
6170 /* compute bitmask from p1 value */
6171 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6173 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6177 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6180 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6183 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6186 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6190 if (is_sdvo
&& is_tv
)
6191 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
6193 /* XXX: just matching BIOS for now */
6194 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
6196 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6197 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6199 dpll
|= PLL_REF_INPUT_DREFCLK
;
6201 /* setup pipeconf */
6202 pipeconf
= I915_READ(PIPECONF(pipe
));
6204 /* Set up the display plane register */
6205 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
6207 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
6208 drm_mode_debug_printmodeline(mode
);
6210 /* PCH eDP needs FDI, but CPU eDP does not */
6211 if (!intel_crtc
->no_pll
) {
6213 I915_WRITE(PCH_FP0(pipe
), fp
);
6214 I915_WRITE(PCH_DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
6216 POSTING_READ(PCH_DPLL(pipe
));
6220 if (dpll
== (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
6221 fp
== I915_READ(PCH_FP0(0))) {
6222 intel_crtc
->use_pll_a
= true;
6223 DRM_DEBUG_KMS("using pipe a dpll\n");
6224 } else if (dpll
== (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
6225 fp
== I915_READ(PCH_FP0(1))) {
6226 intel_crtc
->use_pll_a
= false;
6227 DRM_DEBUG_KMS("using pipe b dpll\n");
6229 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
6234 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
6235 * This is an exception to the general rule that mode_set doesn't turn
6239 temp
= I915_READ(PCH_LVDS
);
6240 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
6241 if (HAS_PCH_CPT(dev
)) {
6242 temp
&= ~PORT_TRANS_SEL_MASK
;
6243 temp
|= PORT_TRANS_SEL_CPT(pipe
);
6246 temp
|= LVDS_PIPEB_SELECT
;
6248 temp
&= ~LVDS_PIPEB_SELECT
;
6251 /* set the corresponsding LVDS_BORDER bit */
6252 temp
|= dev_priv
->lvds_border_bits
;
6253 /* Set the B0-B3 data pairs corresponding to whether we're going to
6254 * set the DPLLs for dual-channel mode or not.
6257 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
6259 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
6261 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
6262 * appropriately here, but we need to look more thoroughly into how
6263 * panels behave in the two modes.
6265 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
6266 lvds_sync
|= LVDS_HSYNC_POLARITY
;
6267 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
6268 lvds_sync
|= LVDS_VSYNC_POLARITY
;
6269 if ((temp
& (LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
))
6271 char flags
[2] = "-+";
6272 DRM_INFO("Changing LVDS panel from "
6273 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
6274 flags
[!(temp
& LVDS_HSYNC_POLARITY
)],
6275 flags
[!(temp
& LVDS_VSYNC_POLARITY
)],
6276 flags
[!(lvds_sync
& LVDS_HSYNC_POLARITY
)],
6277 flags
[!(lvds_sync
& LVDS_VSYNC_POLARITY
)]);
6278 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
6281 I915_WRITE(PCH_LVDS
, temp
);
6284 pipeconf
&= ~PIPECONF_DITHER_EN
;
6285 pipeconf
&= ~PIPECONF_DITHER_TYPE_MASK
;
6286 if ((is_lvds
&& dev_priv
->lvds_dither
) || dither
) {
6287 pipeconf
|= PIPECONF_DITHER_EN
;
6288 pipeconf
|= PIPECONF_DITHER_TYPE_SP
;
6290 if (is_dp
&& !is_cpu_edp
) {
6291 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
6293 /* For non-DP output, clear any trans DP clock recovery setting.*/
6294 I915_WRITE(TRANSDATA_M1(pipe
), 0);
6295 I915_WRITE(TRANSDATA_N1(pipe
), 0);
6296 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
6297 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
6300 if (!intel_crtc
->no_pll
&& (!edp_encoder
|| is_pch_edp
)) {
6301 I915_WRITE(PCH_DPLL(pipe
), dpll
);
6303 /* Wait for the clocks to stabilize. */
6304 POSTING_READ(PCH_DPLL(pipe
));
6307 /* The pixel multiplier can only be updated once the
6308 * DPLL is enabled and the clocks are stable.
6310 * So write it again.
6312 I915_WRITE(PCH_DPLL(pipe
), dpll
);
6315 intel_crtc
->lowfreq_avail
= false;
6316 if (!intel_crtc
->no_pll
) {
6317 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
6318 I915_WRITE(PCH_FP1(pipe
), fp2
);
6319 intel_crtc
->lowfreq_avail
= true;
6320 if (HAS_PIPE_CXSR(dev
)) {
6321 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6322 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6325 I915_WRITE(PCH_FP1(pipe
), fp
);
6326 if (HAS_PIPE_CXSR(dev
)) {
6327 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6328 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
6333 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
6334 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6335 pipeconf
|= PIPECONF_INTERLACED_ILK
;
6336 /* the chip adds 2 halflines automatically */
6337 adjusted_mode
->crtc_vtotal
-= 1;
6338 adjusted_mode
->crtc_vblank_end
-= 1;
6339 I915_WRITE(VSYNCSHIFT(pipe
),
6340 adjusted_mode
->crtc_hsync_start
6341 - adjusted_mode
->crtc_htotal
/2);
6343 pipeconf
|= PIPECONF_PROGRESSIVE
;
6344 I915_WRITE(VSYNCSHIFT(pipe
), 0);
6347 I915_WRITE(HTOTAL(pipe
),
6348 (adjusted_mode
->crtc_hdisplay
- 1) |
6349 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6350 I915_WRITE(HBLANK(pipe
),
6351 (adjusted_mode
->crtc_hblank_start
- 1) |
6352 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6353 I915_WRITE(HSYNC(pipe
),
6354 (adjusted_mode
->crtc_hsync_start
- 1) |
6355 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6357 I915_WRITE(VTOTAL(pipe
),
6358 (adjusted_mode
->crtc_vdisplay
- 1) |
6359 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
6360 I915_WRITE(VBLANK(pipe
),
6361 (adjusted_mode
->crtc_vblank_start
- 1) |
6362 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
6363 I915_WRITE(VSYNC(pipe
),
6364 (adjusted_mode
->crtc_vsync_start
- 1) |
6365 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6367 /* pipesrc controls the size that is scaled from, which should
6368 * always be the user's requested size.
6370 I915_WRITE(PIPESRC(pipe
),
6371 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
6373 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
6374 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
6375 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
6376 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
6379 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
6381 I915_WRITE(PIPECONF(pipe
), pipeconf
);
6382 POSTING_READ(PIPECONF(pipe
));
6384 intel_wait_for_vblank(dev
, pipe
);
6386 I915_WRITE(DSPCNTR(plane
), dspcntr
);
6387 POSTING_READ(DSPCNTR(plane
));
6389 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
6391 intel_update_watermarks(dev
);
6396 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6397 struct drm_display_mode
*mode
,
6398 struct drm_display_mode
*adjusted_mode
,
6400 struct drm_framebuffer
*old_fb
)
6402 struct drm_device
*dev
= crtc
->dev
;
6403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6404 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6405 int pipe
= intel_crtc
->pipe
;
6408 drm_vblank_pre_modeset(dev
, pipe
);
6410 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
6412 drm_vblank_post_modeset(dev
, pipe
);
6415 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
6417 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_ON
;
6422 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6423 int reg_eldv
, uint32_t bits_eldv
,
6424 int reg_elda
, uint32_t bits_elda
,
6427 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6428 uint8_t *eld
= connector
->eld
;
6431 i
= I915_READ(reg_eldv
);
6440 i
= I915_READ(reg_elda
);
6442 I915_WRITE(reg_elda
, i
);
6444 for (i
= 0; i
< eld
[2]; i
++)
6445 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6451 static void g4x_write_eld(struct drm_connector
*connector
,
6452 struct drm_crtc
*crtc
)
6454 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6455 uint8_t *eld
= connector
->eld
;
6460 i
= I915_READ(G4X_AUD_VID_DID
);
6462 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6463 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6465 eldv
= G4X_ELDV_DEVCTG
;
6467 if (intel_eld_uptodate(connector
,
6468 G4X_AUD_CNTL_ST
, eldv
,
6469 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6470 G4X_HDMIW_HDMIEDID
))
6473 i
= I915_READ(G4X_AUD_CNTL_ST
);
6474 i
&= ~(eldv
| G4X_ELD_ADDR
);
6475 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6476 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6481 len
= min_t(uint8_t, eld
[2], len
);
6482 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6483 for (i
= 0; i
< len
; i
++)
6484 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6486 i
= I915_READ(G4X_AUD_CNTL_ST
);
6488 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6491 static void ironlake_write_eld(struct drm_connector
*connector
,
6492 struct drm_crtc
*crtc
)
6494 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6495 uint8_t *eld
= connector
->eld
;
6504 if (HAS_PCH_IBX(connector
->dev
)) {
6505 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID_A
;
6506 aud_config
= IBX_AUD_CONFIG_A
;
6507 aud_cntl_st
= IBX_AUD_CNTL_ST_A
;
6508 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6510 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID_A
;
6511 aud_config
= CPT_AUD_CONFIG_A
;
6512 aud_cntl_st
= CPT_AUD_CNTL_ST_A
;
6513 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6516 i
= to_intel_crtc(crtc
)->pipe
;
6517 hdmiw_hdmiedid
+= i
* 0x100;
6518 aud_cntl_st
+= i
* 0x100;
6519 aud_config
+= i
* 0x100;
6521 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i
));
6523 i
= I915_READ(aud_cntl_st
);
6524 i
= (i
>> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6526 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6527 /* operate blindly on all ports */
6528 eldv
= IBX_ELD_VALIDB
;
6529 eldv
|= IBX_ELD_VALIDB
<< 4;
6530 eldv
|= IBX_ELD_VALIDB
<< 8;
6532 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
6533 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6536 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6537 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6538 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6539 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6541 I915_WRITE(aud_config
, 0);
6543 if (intel_eld_uptodate(connector
,
6544 aud_cntrl_st2
, eldv
,
6545 aud_cntl_st
, IBX_ELD_ADDRESS
,
6549 i
= I915_READ(aud_cntrl_st2
);
6551 I915_WRITE(aud_cntrl_st2
, i
);
6556 i
= I915_READ(aud_cntl_st
);
6557 i
&= ~IBX_ELD_ADDRESS
;
6558 I915_WRITE(aud_cntl_st
, i
);
6560 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6561 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6562 for (i
= 0; i
< len
; i
++)
6563 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6565 i
= I915_READ(aud_cntrl_st2
);
6567 I915_WRITE(aud_cntrl_st2
, i
);
6570 void intel_write_eld(struct drm_encoder
*encoder
,
6571 struct drm_display_mode
*mode
)
6573 struct drm_crtc
*crtc
= encoder
->crtc
;
6574 struct drm_connector
*connector
;
6575 struct drm_device
*dev
= encoder
->dev
;
6576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6578 connector
= drm_select_eld(encoder
, mode
);
6582 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6584 drm_get_connector_name(connector
),
6585 connector
->encoder
->base
.id
,
6586 drm_get_encoder_name(connector
->encoder
));
6588 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6590 if (dev_priv
->display
.write_eld
)
6591 dev_priv
->display
.write_eld(connector
, crtc
);
6594 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6595 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6597 struct drm_device
*dev
= crtc
->dev
;
6598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6599 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6600 int palreg
= PALETTE(intel_crtc
->pipe
);
6603 /* The clocks have to be on to load the palette. */
6604 if (!crtc
->enabled
|| !intel_crtc
->active
)
6607 /* use legacy palette for Ironlake */
6608 if (HAS_PCH_SPLIT(dev
))
6609 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
6611 for (i
= 0; i
< 256; i
++) {
6612 I915_WRITE(palreg
+ 4 * i
,
6613 (intel_crtc
->lut_r
[i
] << 16) |
6614 (intel_crtc
->lut_g
[i
] << 8) |
6615 intel_crtc
->lut_b
[i
]);
6619 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6621 struct drm_device
*dev
= crtc
->dev
;
6622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6623 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6624 bool visible
= base
!= 0;
6627 if (intel_crtc
->cursor_visible
== visible
)
6630 cntl
= I915_READ(_CURACNTR
);
6632 /* On these chipsets we can only modify the base whilst
6633 * the cursor is disabled.
6635 I915_WRITE(_CURABASE
, base
);
6637 cntl
&= ~(CURSOR_FORMAT_MASK
);
6638 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6639 cntl
|= CURSOR_ENABLE
|
6640 CURSOR_GAMMA_ENABLE
|
6643 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6644 I915_WRITE(_CURACNTR
, cntl
);
6646 intel_crtc
->cursor_visible
= visible
;
6649 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6651 struct drm_device
*dev
= crtc
->dev
;
6652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6653 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6654 int pipe
= intel_crtc
->pipe
;
6655 bool visible
= base
!= 0;
6657 if (intel_crtc
->cursor_visible
!= visible
) {
6658 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6660 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6661 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6662 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6664 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6665 cntl
|= CURSOR_MODE_DISABLE
;
6667 I915_WRITE(CURCNTR(pipe
), cntl
);
6669 intel_crtc
->cursor_visible
= visible
;
6671 /* and commit changes on next vblank */
6672 I915_WRITE(CURBASE(pipe
), base
);
6675 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6677 struct drm_device
*dev
= crtc
->dev
;
6678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6679 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6680 int pipe
= intel_crtc
->pipe
;
6681 bool visible
= base
!= 0;
6683 if (intel_crtc
->cursor_visible
!= visible
) {
6684 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6686 cntl
&= ~CURSOR_MODE
;
6687 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6689 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6690 cntl
|= CURSOR_MODE_DISABLE
;
6692 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6694 intel_crtc
->cursor_visible
= visible
;
6696 /* and commit changes on next vblank */
6697 I915_WRITE(CURBASE_IVB(pipe
), base
);
6700 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6701 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6704 struct drm_device
*dev
= crtc
->dev
;
6705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6706 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6707 int pipe
= intel_crtc
->pipe
;
6708 int x
= intel_crtc
->cursor_x
;
6709 int y
= intel_crtc
->cursor_y
;
6715 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6716 base
= intel_crtc
->cursor_addr
;
6717 if (x
> (int) crtc
->fb
->width
)
6720 if (y
> (int) crtc
->fb
->height
)
6726 if (x
+ intel_crtc
->cursor_width
< 0)
6729 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6732 pos
|= x
<< CURSOR_X_SHIFT
;
6735 if (y
+ intel_crtc
->cursor_height
< 0)
6738 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6741 pos
|= y
<< CURSOR_Y_SHIFT
;
6743 visible
= base
!= 0;
6744 if (!visible
&& !intel_crtc
->cursor_visible
)
6747 if (IS_IVYBRIDGE(dev
)) {
6748 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6749 ivb_update_cursor(crtc
, base
);
6751 I915_WRITE(CURPOS(pipe
), pos
);
6752 if (IS_845G(dev
) || IS_I865G(dev
))
6753 i845_update_cursor(crtc
, base
);
6755 i9xx_update_cursor(crtc
, base
);
6759 intel_mark_busy(dev
, to_intel_framebuffer(crtc
->fb
)->obj
);
6762 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6763 struct drm_file
*file
,
6765 uint32_t width
, uint32_t height
)
6767 struct drm_device
*dev
= crtc
->dev
;
6768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6769 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6770 struct drm_i915_gem_object
*obj
;
6774 DRM_DEBUG_KMS("\n");
6776 /* if we want to turn off the cursor ignore width and height */
6778 DRM_DEBUG_KMS("cursor off\n");
6781 mutex_lock(&dev
->struct_mutex
);
6785 /* Currently we only support 64x64 cursors */
6786 if (width
!= 64 || height
!= 64) {
6787 DRM_ERROR("we currently only support 64x64 cursors\n");
6791 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6792 if (&obj
->base
== NULL
)
6795 if (obj
->base
.size
< width
* height
* 4) {
6796 DRM_ERROR("buffer is to small\n");
6801 /* we only need to pin inside GTT if cursor is non-phy */
6802 mutex_lock(&dev
->struct_mutex
);
6803 if (!dev_priv
->info
->cursor_needs_physical
) {
6804 if (obj
->tiling_mode
) {
6805 DRM_ERROR("cursor cannot be tiled\n");
6810 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
6812 DRM_ERROR("failed to move cursor bo into the GTT\n");
6816 ret
= i915_gem_object_put_fence(obj
);
6818 DRM_ERROR("failed to release fence for cursor");
6822 addr
= obj
->gtt_offset
;
6824 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6825 ret
= i915_gem_attach_phys_object(dev
, obj
,
6826 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6829 DRM_ERROR("failed to attach phys object\n");
6832 addr
= obj
->phys_obj
->handle
->busaddr
;
6836 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6839 if (intel_crtc
->cursor_bo
) {
6840 if (dev_priv
->info
->cursor_needs_physical
) {
6841 if (intel_crtc
->cursor_bo
!= obj
)
6842 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6844 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6845 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6848 mutex_unlock(&dev
->struct_mutex
);
6850 intel_crtc
->cursor_addr
= addr
;
6851 intel_crtc
->cursor_bo
= obj
;
6852 intel_crtc
->cursor_width
= width
;
6853 intel_crtc
->cursor_height
= height
;
6855 intel_crtc_update_cursor(crtc
, true);
6859 i915_gem_object_unpin(obj
);
6861 mutex_unlock(&dev
->struct_mutex
);
6863 drm_gem_object_unreference_unlocked(&obj
->base
);
6867 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6869 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6871 intel_crtc
->cursor_x
= x
;
6872 intel_crtc
->cursor_y
= y
;
6874 intel_crtc_update_cursor(crtc
, true);
6879 /** Sets the color ramps on behalf of RandR */
6880 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6881 u16 blue
, int regno
)
6883 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6885 intel_crtc
->lut_r
[regno
] = red
>> 8;
6886 intel_crtc
->lut_g
[regno
] = green
>> 8;
6887 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6890 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6891 u16
*blue
, int regno
)
6893 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6895 *red
= intel_crtc
->lut_r
[regno
] << 8;
6896 *green
= intel_crtc
->lut_g
[regno
] << 8;
6897 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6900 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6901 u16
*blue
, uint32_t start
, uint32_t size
)
6903 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6904 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6906 for (i
= start
; i
< end
; i
++) {
6907 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6908 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6909 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6912 intel_crtc_load_lut(crtc
);
6916 * Get a pipe with a simple mode set on it for doing load-based monitor
6919 * It will be up to the load-detect code to adjust the pipe as appropriate for
6920 * its requirements. The pipe will be connected to no other encoders.
6922 * Currently this code will only succeed if there is a pipe with no encoders
6923 * configured for it. In the future, it could choose to temporarily disable
6924 * some outputs to free up a pipe for its use.
6926 * \return crtc, or NULL if no pipes are available.
6929 /* VESA 640x480x72Hz mode to set on the pipe */
6930 static struct drm_display_mode load_detect_mode
= {
6931 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6932 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6935 static struct drm_framebuffer
*
6936 intel_framebuffer_create(struct drm_device
*dev
,
6937 struct drm_mode_fb_cmd2
*mode_cmd
,
6938 struct drm_i915_gem_object
*obj
)
6940 struct intel_framebuffer
*intel_fb
;
6943 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6945 drm_gem_object_unreference_unlocked(&obj
->base
);
6946 return ERR_PTR(-ENOMEM
);
6949 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6951 drm_gem_object_unreference_unlocked(&obj
->base
);
6953 return ERR_PTR(ret
);
6956 return &intel_fb
->base
;
6960 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6962 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6963 return ALIGN(pitch
, 64);
6967 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6969 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6970 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6973 static struct drm_framebuffer
*
6974 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6975 struct drm_display_mode
*mode
,
6978 struct drm_i915_gem_object
*obj
;
6979 struct drm_mode_fb_cmd2 mode_cmd
;
6981 obj
= i915_gem_alloc_object(dev
,
6982 intel_framebuffer_size_for_mode(mode
, bpp
));
6984 return ERR_PTR(-ENOMEM
);
6986 mode_cmd
.width
= mode
->hdisplay
;
6987 mode_cmd
.height
= mode
->vdisplay
;
6988 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6990 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6992 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6995 static struct drm_framebuffer
*
6996 mode_fits_in_fbdev(struct drm_device
*dev
,
6997 struct drm_display_mode
*mode
)
6999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7000 struct drm_i915_gem_object
*obj
;
7001 struct drm_framebuffer
*fb
;
7003 if (dev_priv
->fbdev
== NULL
)
7006 obj
= dev_priv
->fbdev
->ifb
.obj
;
7010 fb
= &dev_priv
->fbdev
->ifb
.base
;
7011 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
7012 fb
->bits_per_pixel
))
7015 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
7021 bool intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
7022 struct drm_connector
*connector
,
7023 struct drm_display_mode
*mode
,
7024 struct intel_load_detect_pipe
*old
)
7026 struct intel_crtc
*intel_crtc
;
7027 struct drm_crtc
*possible_crtc
;
7028 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7029 struct drm_crtc
*crtc
= NULL
;
7030 struct drm_device
*dev
= encoder
->dev
;
7031 struct drm_framebuffer
*old_fb
;
7034 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7035 connector
->base
.id
, drm_get_connector_name(connector
),
7036 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7039 * Algorithm gets a little messy:
7041 * - if the connector already has an assigned crtc, use it (but make
7042 * sure it's on first)
7044 * - try to find the first unused crtc that can drive this connector,
7045 * and use that if we find one
7048 /* See if we already have a CRTC for this connector */
7049 if (encoder
->crtc
) {
7050 crtc
= encoder
->crtc
;
7052 intel_crtc
= to_intel_crtc(crtc
);
7053 old
->dpms_mode
= intel_crtc
->dpms_mode
;
7054 old
->load_detect_temp
= false;
7056 /* Make sure the crtc and connector are running */
7057 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
7058 struct drm_encoder_helper_funcs
*encoder_funcs
;
7059 struct drm_crtc_helper_funcs
*crtc_funcs
;
7061 crtc_funcs
= crtc
->helper_private
;
7062 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
7064 encoder_funcs
= encoder
->helper_private
;
7065 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
7071 /* Find an unused one (if possible) */
7072 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
7074 if (!(encoder
->possible_crtcs
& (1 << i
)))
7076 if (!possible_crtc
->enabled
) {
7077 crtc
= possible_crtc
;
7083 * If we didn't find an unused CRTC, don't use any.
7086 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7090 encoder
->crtc
= crtc
;
7091 connector
->encoder
= encoder
;
7093 intel_crtc
= to_intel_crtc(crtc
);
7094 old
->dpms_mode
= intel_crtc
->dpms_mode
;
7095 old
->load_detect_temp
= true;
7096 old
->release_fb
= NULL
;
7099 mode
= &load_detect_mode
;
7103 /* We need a framebuffer large enough to accommodate all accesses
7104 * that the plane may generate whilst we perform load detection.
7105 * We can not rely on the fbcon either being present (we get called
7106 * during its initialisation to detect all boot displays, or it may
7107 * not even exist) or that it is large enough to satisfy the
7110 crtc
->fb
= mode_fits_in_fbdev(dev
, mode
);
7111 if (crtc
->fb
== NULL
) {
7112 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7113 crtc
->fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
7114 old
->release_fb
= crtc
->fb
;
7116 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7117 if (IS_ERR(crtc
->fb
)) {
7118 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7123 if (!drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, old_fb
)) {
7124 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7125 if (old
->release_fb
)
7126 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7131 /* let the connector get through one full cycle before testing */
7132 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
7137 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
7138 struct drm_connector
*connector
,
7139 struct intel_load_detect_pipe
*old
)
7141 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7142 struct drm_device
*dev
= encoder
->dev
;
7143 struct drm_crtc
*crtc
= encoder
->crtc
;
7144 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
7145 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
7147 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7148 connector
->base
.id
, drm_get_connector_name(connector
),
7149 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7151 if (old
->load_detect_temp
) {
7152 connector
->encoder
= NULL
;
7153 drm_helper_disable_unused_functions(dev
);
7155 if (old
->release_fb
)
7156 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7161 /* Switch crtc and encoder back off if necessary */
7162 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
7163 encoder_funcs
->dpms(encoder
, old
->dpms_mode
);
7164 crtc_funcs
->dpms(crtc
, old
->dpms_mode
);
7168 /* Returns the clock of the currently programmed mode of the given pipe. */
7169 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
7171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7172 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7173 int pipe
= intel_crtc
->pipe
;
7174 u32 dpll
= I915_READ(DPLL(pipe
));
7176 intel_clock_t clock
;
7178 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
7179 fp
= I915_READ(FP0(pipe
));
7181 fp
= I915_READ(FP1(pipe
));
7183 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
7184 if (IS_PINEVIEW(dev
)) {
7185 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
7186 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7188 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
7189 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7192 if (!IS_GEN2(dev
)) {
7193 if (IS_PINEVIEW(dev
))
7194 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
7195 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
7197 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
7198 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7200 switch (dpll
& DPLL_MODE_MASK
) {
7201 case DPLLB_MODE_DAC_SERIAL
:
7202 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
7205 case DPLLB_MODE_LVDS
:
7206 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
7210 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7211 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
7215 /* XXX: Handle the 100Mhz refclk */
7216 intel_clock(dev
, 96000, &clock
);
7218 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
7221 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
7222 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7225 if ((dpll
& PLL_REF_INPUT_MASK
) ==
7226 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
7227 /* XXX: might not be 66MHz */
7228 intel_clock(dev
, 66000, &clock
);
7230 intel_clock(dev
, 48000, &clock
);
7232 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
7235 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
7236 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
7238 if (dpll
& PLL_P2_DIVIDE_BY_4
)
7243 intel_clock(dev
, 48000, &clock
);
7247 /* XXX: It would be nice to validate the clocks, but we can't reuse
7248 * i830PllIsValid() because it relies on the xf86_config connector
7249 * configuration being accurate, which it isn't necessarily.
7255 /** Returns the currently programmed mode of the given pipe. */
7256 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
7257 struct drm_crtc
*crtc
)
7259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7260 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7261 int pipe
= intel_crtc
->pipe
;
7262 struct drm_display_mode
*mode
;
7263 int htot
= I915_READ(HTOTAL(pipe
));
7264 int hsync
= I915_READ(HSYNC(pipe
));
7265 int vtot
= I915_READ(VTOTAL(pipe
));
7266 int vsync
= I915_READ(VSYNC(pipe
));
7268 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
7272 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
7273 mode
->hdisplay
= (htot
& 0xffff) + 1;
7274 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
7275 mode
->hsync_start
= (hsync
& 0xffff) + 1;
7276 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
7277 mode
->vdisplay
= (vtot
& 0xffff) + 1;
7278 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
7279 mode
->vsync_start
= (vsync
& 0xffff) + 1;
7280 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
7282 drm_mode_set_name(mode
);
7283 drm_mode_set_crtcinfo(mode
, 0);
7288 #define GPU_IDLE_TIMEOUT 500 /* ms */
7290 /* When this timer fires, we've been idle for awhile */
7291 static void intel_gpu_idle_timer(unsigned long arg
)
7293 struct drm_device
*dev
= (struct drm_device
*)arg
;
7294 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7296 if (!list_empty(&dev_priv
->mm
.active_list
)) {
7297 /* Still processing requests, so just re-arm the timer. */
7298 mod_timer(&dev_priv
->idle_timer
, jiffies
+
7299 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
7303 dev_priv
->busy
= false;
7304 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
7307 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
7309 static void intel_crtc_idle_timer(unsigned long arg
)
7311 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
7312 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7313 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
7314 struct intel_framebuffer
*intel_fb
;
7316 intel_fb
= to_intel_framebuffer(crtc
->fb
);
7317 if (intel_fb
&& intel_fb
->obj
->active
) {
7318 /* The framebuffer is still being accessed by the GPU. */
7319 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
7320 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
7324 intel_crtc
->busy
= false;
7325 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
7328 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
7330 struct drm_device
*dev
= crtc
->dev
;
7331 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7332 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7333 int pipe
= intel_crtc
->pipe
;
7334 int dpll_reg
= DPLL(pipe
);
7337 if (HAS_PCH_SPLIT(dev
))
7340 if (!dev_priv
->lvds_downclock_avail
)
7343 dpll
= I915_READ(dpll_reg
);
7344 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
7345 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7347 assert_panel_unlocked(dev_priv
, pipe
);
7349 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
7350 I915_WRITE(dpll_reg
, dpll
);
7351 intel_wait_for_vblank(dev
, pipe
);
7353 dpll
= I915_READ(dpll_reg
);
7354 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7355 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7358 /* Schedule downclock */
7359 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
7360 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
7363 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7365 struct drm_device
*dev
= crtc
->dev
;
7366 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7368 int pipe
= intel_crtc
->pipe
;
7369 int dpll_reg
= DPLL(pipe
);
7370 int dpll
= I915_READ(dpll_reg
);
7372 if (HAS_PCH_SPLIT(dev
))
7375 if (!dev_priv
->lvds_downclock_avail
)
7379 * Since this is called by a timer, we should never get here in
7382 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7383 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7385 assert_panel_unlocked(dev_priv
, pipe
);
7387 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7388 I915_WRITE(dpll_reg
, dpll
);
7389 intel_wait_for_vblank(dev
, pipe
);
7390 dpll
= I915_READ(dpll_reg
);
7391 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7392 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7398 * intel_idle_update - adjust clocks for idleness
7399 * @work: work struct
7401 * Either the GPU or display (or both) went idle. Check the busy status
7402 * here and adjust the CRTC and GPU clocks as necessary.
7404 static void intel_idle_update(struct work_struct
*work
)
7406 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
7408 struct drm_device
*dev
= dev_priv
->dev
;
7409 struct drm_crtc
*crtc
;
7410 struct intel_crtc
*intel_crtc
;
7412 if (!i915_powersave
)
7415 mutex_lock(&dev
->struct_mutex
);
7417 i915_update_gfx_val(dev_priv
);
7419 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7420 /* Skip inactive CRTCs */
7424 intel_crtc
= to_intel_crtc(crtc
);
7425 if (!intel_crtc
->busy
)
7426 intel_decrease_pllclock(crtc
);
7430 mutex_unlock(&dev
->struct_mutex
);
7434 * intel_mark_busy - mark the GPU and possibly the display busy
7436 * @obj: object we're operating on
7438 * Callers can use this function to indicate that the GPU is busy processing
7439 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7440 * buffer), we'll also mark the display as busy, so we know to increase its
7443 void intel_mark_busy(struct drm_device
*dev
, struct drm_i915_gem_object
*obj
)
7445 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7446 struct drm_crtc
*crtc
= NULL
;
7447 struct intel_framebuffer
*intel_fb
;
7448 struct intel_crtc
*intel_crtc
;
7450 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
7453 if (!dev_priv
->busy
)
7454 dev_priv
->busy
= true;
7456 mod_timer(&dev_priv
->idle_timer
, jiffies
+
7457 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
7459 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7463 intel_crtc
= to_intel_crtc(crtc
);
7464 intel_fb
= to_intel_framebuffer(crtc
->fb
);
7465 if (intel_fb
->obj
== obj
) {
7466 if (!intel_crtc
->busy
) {
7467 /* Non-busy -> busy, upclock */
7468 intel_increase_pllclock(crtc
);
7469 intel_crtc
->busy
= true;
7471 /* Busy -> busy, put off timer */
7472 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
7473 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
7479 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7481 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7482 struct drm_device
*dev
= crtc
->dev
;
7483 struct intel_unpin_work
*work
;
7484 unsigned long flags
;
7486 spin_lock_irqsave(&dev
->event_lock
, flags
);
7487 work
= intel_crtc
->unpin_work
;
7488 intel_crtc
->unpin_work
= NULL
;
7489 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7492 cancel_work_sync(&work
->work
);
7496 drm_crtc_cleanup(crtc
);
7501 static void intel_unpin_work_fn(struct work_struct
*__work
)
7503 struct intel_unpin_work
*work
=
7504 container_of(__work
, struct intel_unpin_work
, work
);
7506 mutex_lock(&work
->dev
->struct_mutex
);
7507 intel_unpin_fb_obj(work
->old_fb_obj
);
7508 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7509 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7511 intel_update_fbc(work
->dev
);
7512 mutex_unlock(&work
->dev
->struct_mutex
);
7516 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7517 struct drm_crtc
*crtc
)
7519 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7520 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7521 struct intel_unpin_work
*work
;
7522 struct drm_i915_gem_object
*obj
;
7523 struct drm_pending_vblank_event
*e
;
7524 struct timeval tnow
, tvbl
;
7525 unsigned long flags
;
7527 /* Ignore early vblank irqs */
7528 if (intel_crtc
== NULL
)
7531 do_gettimeofday(&tnow
);
7533 spin_lock_irqsave(&dev
->event_lock
, flags
);
7534 work
= intel_crtc
->unpin_work
;
7535 if (work
== NULL
|| !work
->pending
) {
7536 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7540 intel_crtc
->unpin_work
= NULL
;
7544 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
7546 /* Called before vblank count and timestamps have
7547 * been updated for the vblank interval of flip
7548 * completion? Need to increment vblank count and
7549 * add one videorefresh duration to returned timestamp
7550 * to account for this. We assume this happened if we
7551 * get called over 0.9 frame durations after the last
7552 * timestamped vblank.
7554 * This calculation can not be used with vrefresh rates
7555 * below 5Hz (10Hz to be on the safe side) without
7556 * promoting to 64 integers.
7558 if (10 * (timeval_to_ns(&tnow
) - timeval_to_ns(&tvbl
)) >
7559 9 * crtc
->framedur_ns
) {
7560 e
->event
.sequence
++;
7561 tvbl
= ns_to_timeval(timeval_to_ns(&tvbl
) +
7565 e
->event
.tv_sec
= tvbl
.tv_sec
;
7566 e
->event
.tv_usec
= tvbl
.tv_usec
;
7568 list_add_tail(&e
->base
.link
,
7569 &e
->base
.file_priv
->event_list
);
7570 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
7573 drm_vblank_put(dev
, intel_crtc
->pipe
);
7575 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7577 obj
= work
->old_fb_obj
;
7579 atomic_clear_mask(1 << intel_crtc
->plane
,
7580 &obj
->pending_flip
.counter
);
7581 if (atomic_read(&obj
->pending_flip
) == 0)
7582 wake_up(&dev_priv
->pending_flip_queue
);
7584 schedule_work(&work
->work
);
7586 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7589 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7591 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7592 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7594 do_intel_finish_page_flip(dev
, crtc
);
7597 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7599 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7600 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7602 do_intel_finish_page_flip(dev
, crtc
);
7605 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7607 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7608 struct intel_crtc
*intel_crtc
=
7609 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7610 unsigned long flags
;
7612 spin_lock_irqsave(&dev
->event_lock
, flags
);
7613 if (intel_crtc
->unpin_work
) {
7614 if ((++intel_crtc
->unpin_work
->pending
) > 1)
7615 DRM_ERROR("Prepared flip multiple times\n");
7617 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7619 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7622 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7623 struct drm_crtc
*crtc
,
7624 struct drm_framebuffer
*fb
,
7625 struct drm_i915_gem_object
*obj
)
7627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7628 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7629 unsigned long offset
;
7633 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, LP_RING(dev_priv
));
7637 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7638 offset
= crtc
->y
* fb
->pitches
[0] + crtc
->x
* fb
->bits_per_pixel
/8;
7640 ret
= BEGIN_LP_RING(6);
7644 /* Can't queue multiple flips, so wait for the previous
7645 * one to finish before executing the next.
7647 if (intel_crtc
->plane
)
7648 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7650 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7651 OUT_RING(MI_WAIT_FOR_EVENT
| flip_mask
);
7653 OUT_RING(MI_DISPLAY_FLIP
|
7654 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7655 OUT_RING(fb
->pitches
[0]);
7656 OUT_RING(obj
->gtt_offset
+ offset
);
7657 OUT_RING(0); /* aux display base address, unused */
7663 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7664 struct drm_crtc
*crtc
,
7665 struct drm_framebuffer
*fb
,
7666 struct drm_i915_gem_object
*obj
)
7668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7669 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7670 unsigned long offset
;
7674 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, LP_RING(dev_priv
));
7678 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7679 offset
= crtc
->y
* fb
->pitches
[0] + crtc
->x
* fb
->bits_per_pixel
/8;
7681 ret
= BEGIN_LP_RING(6);
7685 if (intel_crtc
->plane
)
7686 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7688 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7689 OUT_RING(MI_WAIT_FOR_EVENT
| flip_mask
);
7691 OUT_RING(MI_DISPLAY_FLIP_I915
|
7692 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7693 OUT_RING(fb
->pitches
[0]);
7694 OUT_RING(obj
->gtt_offset
+ offset
);
7702 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7703 struct drm_crtc
*crtc
,
7704 struct drm_framebuffer
*fb
,
7705 struct drm_i915_gem_object
*obj
)
7707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7708 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7709 uint32_t pf
, pipesrc
;
7712 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, LP_RING(dev_priv
));
7716 ret
= BEGIN_LP_RING(4);
7720 /* i965+ uses the linear or tiled offsets from the
7721 * Display Registers (which do not change across a page-flip)
7722 * so we need only reprogram the base address.
7724 OUT_RING(MI_DISPLAY_FLIP
|
7725 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7726 OUT_RING(fb
->pitches
[0]);
7727 OUT_RING(obj
->gtt_offset
| obj
->tiling_mode
);
7729 /* XXX Enabling the panel-fitter across page-flip is so far
7730 * untested on non-native modes, so ignore it for now.
7731 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7734 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7735 OUT_RING(pf
| pipesrc
);
7741 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7742 struct drm_crtc
*crtc
,
7743 struct drm_framebuffer
*fb
,
7744 struct drm_i915_gem_object
*obj
)
7746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7747 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7748 uint32_t pf
, pipesrc
;
7751 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, LP_RING(dev_priv
));
7755 ret
= BEGIN_LP_RING(4);
7759 OUT_RING(MI_DISPLAY_FLIP
|
7760 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7761 OUT_RING(fb
->pitches
[0] | obj
->tiling_mode
);
7762 OUT_RING(obj
->gtt_offset
);
7764 pf
= I915_READ(PF_CTL(intel_crtc
->pipe
)) & PF_ENABLE
;
7765 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7766 OUT_RING(pf
| pipesrc
);
7773 * On gen7 we currently use the blit ring because (in early silicon at least)
7774 * the render ring doesn't give us interrpts for page flip completion, which
7775 * means clients will hang after the first flip is queued. Fortunately the
7776 * blit ring generates interrupts properly, so use it instead.
7778 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7779 struct drm_crtc
*crtc
,
7780 struct drm_framebuffer
*fb
,
7781 struct drm_i915_gem_object
*obj
)
7783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7784 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7785 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7788 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7792 ret
= intel_ring_begin(ring
, 4);
7796 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| (intel_crtc
->plane
<< 19));
7797 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7798 intel_ring_emit(ring
, (obj
->gtt_offset
));
7799 intel_ring_emit(ring
, (MI_NOOP
));
7800 intel_ring_advance(ring
);
7805 static int intel_default_queue_flip(struct drm_device
*dev
,
7806 struct drm_crtc
*crtc
,
7807 struct drm_framebuffer
*fb
,
7808 struct drm_i915_gem_object
*obj
)
7813 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7814 struct drm_framebuffer
*fb
,
7815 struct drm_pending_vblank_event
*event
)
7817 struct drm_device
*dev
= crtc
->dev
;
7818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7819 struct intel_framebuffer
*intel_fb
;
7820 struct drm_i915_gem_object
*obj
;
7821 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7822 struct intel_unpin_work
*work
;
7823 unsigned long flags
;
7826 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7830 work
->event
= event
;
7831 work
->dev
= crtc
->dev
;
7832 intel_fb
= to_intel_framebuffer(crtc
->fb
);
7833 work
->old_fb_obj
= intel_fb
->obj
;
7834 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7836 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7840 /* We borrow the event spin lock for protecting unpin_work */
7841 spin_lock_irqsave(&dev
->event_lock
, flags
);
7842 if (intel_crtc
->unpin_work
) {
7843 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7845 drm_vblank_put(dev
, intel_crtc
->pipe
);
7847 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7850 intel_crtc
->unpin_work
= work
;
7851 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7853 intel_fb
= to_intel_framebuffer(fb
);
7854 obj
= intel_fb
->obj
;
7856 mutex_lock(&dev
->struct_mutex
);
7858 /* Reference the objects for the scheduled work. */
7859 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7860 drm_gem_object_reference(&obj
->base
);
7864 work
->pending_flip_obj
= obj
;
7866 work
->enable_stall_check
= true;
7868 /* Block clients from rendering to the new back buffer until
7869 * the flip occurs and the object is no longer visible.
7871 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
7873 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7875 goto cleanup_pending
;
7877 intel_disable_fbc(dev
);
7878 mutex_unlock(&dev
->struct_mutex
);
7880 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7885 atomic_sub(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
7886 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7887 drm_gem_object_unreference(&obj
->base
);
7888 mutex_unlock(&dev
->struct_mutex
);
7890 spin_lock_irqsave(&dev
->event_lock
, flags
);
7891 intel_crtc
->unpin_work
= NULL
;
7892 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7894 drm_vblank_put(dev
, intel_crtc
->pipe
);
7901 static void intel_sanitize_modesetting(struct drm_device
*dev
,
7902 int pipe
, int plane
)
7904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7907 /* Clear any frame start delays used for debugging left by the BIOS */
7908 for_each_pipe(pipe
) {
7909 reg
= PIPECONF(pipe
);
7910 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
7913 if (HAS_PCH_SPLIT(dev
))
7916 /* Who knows what state these registers were left in by the BIOS or
7919 * If we leave the registers in a conflicting state (e.g. with the
7920 * display plane reading from the other pipe than the one we intend
7921 * to use) then when we attempt to teardown the active mode, we will
7922 * not disable the pipes and planes in the correct order -- leaving
7923 * a plane reading from a disabled pipe and possibly leading to
7924 * undefined behaviour.
7927 reg
= DSPCNTR(plane
);
7928 val
= I915_READ(reg
);
7930 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
7932 if (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == pipe
)
7935 /* This display plane is active and attached to the other CPU pipe. */
7938 /* Disable the plane and wait for it to stop reading from the pipe. */
7939 intel_disable_plane(dev_priv
, plane
, pipe
);
7940 intel_disable_pipe(dev_priv
, pipe
);
7943 static void intel_crtc_reset(struct drm_crtc
*crtc
)
7945 struct drm_device
*dev
= crtc
->dev
;
7946 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7948 /* Reset flags back to the 'unknown' status so that they
7949 * will be correctly set on the initial modeset.
7951 intel_crtc
->dpms_mode
= -1;
7953 /* We need to fix up any BIOS configuration that conflicts with
7956 intel_sanitize_modesetting(dev
, intel_crtc
->pipe
, intel_crtc
->plane
);
7959 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7960 .dpms
= intel_crtc_dpms
,
7961 .mode_fixup
= intel_crtc_mode_fixup
,
7962 .mode_set
= intel_crtc_mode_set
,
7963 .mode_set_base
= intel_pipe_set_base
,
7964 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7965 .load_lut
= intel_crtc_load_lut
,
7966 .disable
= intel_crtc_disable
,
7969 static const struct drm_crtc_funcs intel_crtc_funcs
= {
7970 .reset
= intel_crtc_reset
,
7971 .cursor_set
= intel_crtc_cursor_set
,
7972 .cursor_move
= intel_crtc_cursor_move
,
7973 .gamma_set
= intel_crtc_gamma_set
,
7974 .set_config
= drm_crtc_helper_set_config
,
7975 .destroy
= intel_crtc_destroy
,
7976 .page_flip
= intel_crtc_page_flip
,
7979 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
7981 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7982 struct intel_crtc
*intel_crtc
;
7985 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
7986 if (intel_crtc
== NULL
)
7989 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
7991 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
7992 for (i
= 0; i
< 256; i
++) {
7993 intel_crtc
->lut_r
[i
] = i
;
7994 intel_crtc
->lut_g
[i
] = i
;
7995 intel_crtc
->lut_b
[i
] = i
;
7998 /* Swap pipes & planes for FBC on pre-965 */
7999 intel_crtc
->pipe
= pipe
;
8000 intel_crtc
->plane
= pipe
;
8001 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
8002 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8003 intel_crtc
->plane
= !pipe
;
8006 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
8007 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
8008 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
8009 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
8011 intel_crtc_reset(&intel_crtc
->base
);
8012 intel_crtc
->active
= true; /* force the pipe off on setup_init_config */
8013 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
8015 if (HAS_PCH_SPLIT(dev
)) {
8016 if (pipe
== 2 && IS_IVYBRIDGE(dev
))
8017 intel_crtc
->no_pll
= true;
8018 intel_helper_funcs
.prepare
= ironlake_crtc_prepare
;
8019 intel_helper_funcs
.commit
= ironlake_crtc_commit
;
8021 intel_helper_funcs
.prepare
= i9xx_crtc_prepare
;
8022 intel_helper_funcs
.commit
= i9xx_crtc_commit
;
8025 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
8027 intel_crtc
->busy
= false;
8029 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
8030 (unsigned long)intel_crtc
);
8033 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
8034 struct drm_file
*file
)
8036 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8037 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
8038 struct drm_mode_object
*drmmode_obj
;
8039 struct intel_crtc
*crtc
;
8042 DRM_ERROR("called with no initialization\n");
8046 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
8047 DRM_MODE_OBJECT_CRTC
);
8050 DRM_ERROR("no such CRTC id\n");
8054 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
8055 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
8060 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
8062 struct intel_encoder
*encoder
;
8066 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8067 if (type_mask
& encoder
->clone_mask
)
8068 index_mask
|= (1 << entry
);
8075 static bool has_edp_a(struct drm_device
*dev
)
8077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8079 if (!IS_MOBILE(dev
))
8082 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8086 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8092 static void intel_setup_outputs(struct drm_device
*dev
)
8094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8095 struct intel_encoder
*encoder
;
8096 bool dpd_is_edp
= false;
8099 has_lvds
= intel_lvds_init(dev
);
8100 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
8101 /* disable the panel fitter on everything but LVDS */
8102 I915_WRITE(PFIT_CONTROL
, 0);
8105 if (HAS_PCH_SPLIT(dev
)) {
8106 dpd_is_edp
= intel_dpd_is_edp(dev
);
8109 intel_dp_init(dev
, DP_A
);
8111 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
8112 intel_dp_init(dev
, PCH_DP_D
);
8115 intel_crt_init(dev
);
8117 if (HAS_PCH_SPLIT(dev
)) {
8120 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
8121 /* PCH SDVOB multiplex with HDMIB */
8122 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
8124 intel_hdmi_init(dev
, HDMIB
);
8125 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
8126 intel_dp_init(dev
, PCH_DP_B
);
8129 if (I915_READ(HDMIC
) & PORT_DETECTED
)
8130 intel_hdmi_init(dev
, HDMIC
);
8132 if (I915_READ(HDMID
) & PORT_DETECTED
)
8133 intel_hdmi_init(dev
, HDMID
);
8135 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
8136 intel_dp_init(dev
, PCH_DP_C
);
8138 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
8139 intel_dp_init(dev
, PCH_DP_D
);
8141 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
8144 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
8145 DRM_DEBUG_KMS("probing SDVOB\n");
8146 found
= intel_sdvo_init(dev
, SDVOB
, true);
8147 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
8148 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8149 intel_hdmi_init(dev
, SDVOB
);
8152 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
8153 DRM_DEBUG_KMS("probing DP_B\n");
8154 intel_dp_init(dev
, DP_B
);
8158 /* Before G4X SDVOC doesn't have its own detect register */
8160 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
8161 DRM_DEBUG_KMS("probing SDVOC\n");
8162 found
= intel_sdvo_init(dev
, SDVOC
, false);
8165 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
8167 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
8168 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8169 intel_hdmi_init(dev
, SDVOC
);
8171 if (SUPPORTS_INTEGRATED_DP(dev
)) {
8172 DRM_DEBUG_KMS("probing DP_C\n");
8173 intel_dp_init(dev
, DP_C
);
8177 if (SUPPORTS_INTEGRATED_DP(dev
) &&
8178 (I915_READ(DP_D
) & DP_DETECTED
)) {
8179 DRM_DEBUG_KMS("probing DP_D\n");
8180 intel_dp_init(dev
, DP_D
);
8182 } else if (IS_GEN2(dev
))
8183 intel_dvo_init(dev
);
8185 if (SUPPORTS_TV(dev
))
8188 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8189 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
8190 encoder
->base
.possible_clones
=
8191 intel_encoder_clones(dev
, encoder
->clone_mask
);
8194 /* disable all the possible outputs/crtcs before entering KMS mode */
8195 drm_helper_disable_unused_functions(dev
);
8197 if (HAS_PCH_SPLIT(dev
))
8198 ironlake_init_pch_refclk(dev
);
8201 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
8203 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8205 drm_framebuffer_cleanup(fb
);
8206 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
8211 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
8212 struct drm_file
*file
,
8213 unsigned int *handle
)
8215 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8216 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
8218 return drm_gem_handle_create(file
, &obj
->base
, handle
);
8221 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
8222 .destroy
= intel_user_framebuffer_destroy
,
8223 .create_handle
= intel_user_framebuffer_create_handle
,
8226 int intel_framebuffer_init(struct drm_device
*dev
,
8227 struct intel_framebuffer
*intel_fb
,
8228 struct drm_mode_fb_cmd2
*mode_cmd
,
8229 struct drm_i915_gem_object
*obj
)
8233 if (obj
->tiling_mode
== I915_TILING_Y
)
8236 if (mode_cmd
->pitches
[0] & 63)
8239 switch (mode_cmd
->pixel_format
) {
8240 case DRM_FORMAT_RGB332
:
8241 case DRM_FORMAT_RGB565
:
8242 case DRM_FORMAT_XRGB8888
:
8243 case DRM_FORMAT_XBGR8888
:
8244 case DRM_FORMAT_ARGB8888
:
8245 case DRM_FORMAT_XRGB2101010
:
8246 case DRM_FORMAT_ARGB2101010
:
8247 /* RGB formats are common across chipsets */
8249 case DRM_FORMAT_YUYV
:
8250 case DRM_FORMAT_UYVY
:
8251 case DRM_FORMAT_YVYU
:
8252 case DRM_FORMAT_VYUY
:
8255 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8256 mode_cmd
->pixel_format
);
8260 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
8262 DRM_ERROR("framebuffer init failed %d\n", ret
);
8266 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
8267 intel_fb
->obj
= obj
;
8271 static struct drm_framebuffer
*
8272 intel_user_framebuffer_create(struct drm_device
*dev
,
8273 struct drm_file
*filp
,
8274 struct drm_mode_fb_cmd2
*mode_cmd
)
8276 struct drm_i915_gem_object
*obj
;
8278 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
8279 mode_cmd
->handles
[0]));
8280 if (&obj
->base
== NULL
)
8281 return ERR_PTR(-ENOENT
);
8283 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
8286 static const struct drm_mode_config_funcs intel_mode_funcs
= {
8287 .fb_create
= intel_user_framebuffer_create
,
8288 .output_poll_changed
= intel_fb_output_poll_changed
,
8291 static struct drm_i915_gem_object
*
8292 intel_alloc_context_page(struct drm_device
*dev
)
8294 struct drm_i915_gem_object
*ctx
;
8297 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
8299 ctx
= i915_gem_alloc_object(dev
, 4096);
8301 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8305 ret
= i915_gem_object_pin(ctx
, 4096, true);
8307 DRM_ERROR("failed to pin power context: %d\n", ret
);
8311 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
8313 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
8320 i915_gem_object_unpin(ctx
);
8322 drm_gem_object_unreference(&ctx
->base
);
8323 mutex_unlock(&dev
->struct_mutex
);
8327 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
8329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8332 rgvswctl
= I915_READ16(MEMSWCTL
);
8333 if (rgvswctl
& MEMCTL_CMD_STS
) {
8334 DRM_DEBUG("gpu busy, RCS change rejected\n");
8335 return false; /* still busy with another command */
8338 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
8339 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
8340 I915_WRITE16(MEMSWCTL
, rgvswctl
);
8341 POSTING_READ16(MEMSWCTL
);
8343 rgvswctl
|= MEMCTL_CMD_STS
;
8344 I915_WRITE16(MEMSWCTL
, rgvswctl
);
8349 void ironlake_enable_drps(struct drm_device
*dev
)
8351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8352 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
8353 u8 fmax
, fmin
, fstart
, vstart
;
8355 /* Enable temp reporting */
8356 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
8357 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
8359 /* 100ms RC evaluation intervals */
8360 I915_WRITE(RCUPEI
, 100000);
8361 I915_WRITE(RCDNEI
, 100000);
8363 /* Set max/min thresholds to 90ms and 80ms respectively */
8364 I915_WRITE(RCBMAXAVG
, 90000);
8365 I915_WRITE(RCBMINAVG
, 80000);
8367 I915_WRITE(MEMIHYST
, 1);
8369 /* Set up min, max, and cur for interrupt handling */
8370 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
8371 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
8372 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
8373 MEMMODE_FSTART_SHIFT
;
8375 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
8378 dev_priv
->fmax
= fmax
; /* IPS callback will increase this */
8379 dev_priv
->fstart
= fstart
;
8381 dev_priv
->max_delay
= fstart
;
8382 dev_priv
->min_delay
= fmin
;
8383 dev_priv
->cur_delay
= fstart
;
8385 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8386 fmax
, fmin
, fstart
);
8388 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
8391 * Interrupts will be enabled in ironlake_irq_postinstall
8394 I915_WRITE(VIDSTART
, vstart
);
8395 POSTING_READ(VIDSTART
);
8397 rgvmodectl
|= MEMMODE_SWMODE_EN
;
8398 I915_WRITE(MEMMODECTL
, rgvmodectl
);
8400 if (wait_for((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
8401 DRM_ERROR("stuck trying to change perf mode\n");
8404 ironlake_set_drps(dev
, fstart
);
8406 dev_priv
->last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
8408 dev_priv
->last_time1
= jiffies_to_msecs(jiffies
);
8409 dev_priv
->last_count2
= I915_READ(0x112f4);
8410 getrawmonotonic(&dev_priv
->last_time2
);
8413 void ironlake_disable_drps(struct drm_device
*dev
)
8415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8416 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
8418 /* Ack interrupts, disable EFC interrupt */
8419 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
8420 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
8421 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
8422 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
8423 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
8425 /* Go back to the starting frequency */
8426 ironlake_set_drps(dev
, dev_priv
->fstart
);
8428 rgvswctl
|= MEMCTL_CMD_STS
;
8429 I915_WRITE(MEMSWCTL
, rgvswctl
);
8434 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
8436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8439 swreq
= (val
& 0x3ff) << 25;
8440 I915_WRITE(GEN6_RPNSWREQ
, swreq
);
8443 void gen6_disable_rps(struct drm_device
*dev
)
8445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8447 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
8448 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
8449 I915_WRITE(GEN6_PMIER
, 0);
8450 /* Complete PM interrupt masking here doesn't race with the rps work
8451 * item again unmasking PM interrupts because that is using a different
8452 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8453 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8455 spin_lock_irq(&dev_priv
->rps_lock
);
8456 dev_priv
->pm_iir
= 0;
8457 spin_unlock_irq(&dev_priv
->rps_lock
);
8459 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
8462 static unsigned long intel_pxfreq(u32 vidfreq
)
8465 int div
= (vidfreq
& 0x3f0000) >> 16;
8466 int post
= (vidfreq
& 0x3000) >> 12;
8467 int pre
= (vidfreq
& 0x7);
8472 freq
= ((div
* 133333) / ((1<<post
) * pre
));
8477 void intel_init_emon(struct drm_device
*dev
)
8479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8484 /* Disable to program */
8488 /* Program energy weights for various events */
8489 I915_WRITE(SDEW
, 0x15040d00);
8490 I915_WRITE(CSIEW0
, 0x007f0000);
8491 I915_WRITE(CSIEW1
, 0x1e220004);
8492 I915_WRITE(CSIEW2
, 0x04000004);
8494 for (i
= 0; i
< 5; i
++)
8495 I915_WRITE(PEW
+ (i
* 4), 0);
8496 for (i
= 0; i
< 3; i
++)
8497 I915_WRITE(DEW
+ (i
* 4), 0);
8499 /* Program P-state weights to account for frequency power adjustment */
8500 for (i
= 0; i
< 16; i
++) {
8501 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
8502 unsigned long freq
= intel_pxfreq(pxvidfreq
);
8503 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
8508 val
*= (freq
/ 1000);
8510 val
/= (127*127*900);
8512 DRM_ERROR("bad pxval: %ld\n", val
);
8515 /* Render standby states get 0 weight */
8519 for (i
= 0; i
< 4; i
++) {
8520 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
8521 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
8522 I915_WRITE(PXW
+ (i
* 4), val
);
8525 /* Adjust magic regs to magic values (more experimental results) */
8526 I915_WRITE(OGW0
, 0);
8527 I915_WRITE(OGW1
, 0);
8528 I915_WRITE(EG0
, 0x00007f00);
8529 I915_WRITE(EG1
, 0x0000000e);
8530 I915_WRITE(EG2
, 0x000e0000);
8531 I915_WRITE(EG3
, 0x68000300);
8532 I915_WRITE(EG4
, 0x42000000);
8533 I915_WRITE(EG5
, 0x00140031);
8537 for (i
= 0; i
< 8; i
++)
8538 I915_WRITE(PXWL
+ (i
* 4), 0);
8540 /* Enable PMON + select events */
8541 I915_WRITE(ECR
, 0x80000019);
8543 lcfuse
= I915_READ(LCFUSE02
);
8545 dev_priv
->corr
= (lcfuse
& LCFUSE_HIV_MASK
);
8548 int intel_enable_rc6(const struct drm_device
*dev
)
8551 * Respect the kernel parameter if it is set
8553 if (i915_enable_rc6
>= 0)
8554 return i915_enable_rc6
;
8557 * Disable RC6 on Ironlake
8559 if (INTEL_INFO(dev
)->gen
== 5)
8563 * Disable rc6 on Sandybridge
8565 if (INTEL_INFO(dev
)->gen
== 6) {
8566 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
8567 return INTEL_RC6_ENABLE
;
8569 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
8570 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
8573 void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
8575 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
8576 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
8577 u32 pcu_mbox
, rc6_mask
= 0;
8579 int cur_freq
, min_freq
, max_freq
;
8583 /* Here begins a magic sequence of register writes to enable
8584 * auto-downclocking.
8586 * Perhaps there might be some value in exposing these to
8589 I915_WRITE(GEN6_RC_STATE
, 0);
8590 mutex_lock(&dev_priv
->dev
->struct_mutex
);
8592 /* Clear the DBG now so we don't confuse earlier errors */
8593 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
8594 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
8595 I915_WRITE(GTFIFODBG
, gtfifodbg
);
8598 gen6_gt_force_wake_get(dev_priv
);
8600 /* disable the counters and set deterministic thresholds */
8601 I915_WRITE(GEN6_RC_CONTROL
, 0);
8603 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
8604 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
8605 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
8606 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
8607 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
8609 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
8610 I915_WRITE(RING_MAX_IDLE(dev_priv
->ring
[i
].mmio_base
), 10);
8612 I915_WRITE(GEN6_RC_SLEEP
, 0);
8613 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
8614 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
8615 I915_WRITE(GEN6_RC6p_THRESHOLD
, 100000);
8616 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
8618 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
8619 if (rc6_mode
& INTEL_RC6_ENABLE
)
8620 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
8622 if (rc6_mode
& INTEL_RC6p_ENABLE
)
8623 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
8625 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
8626 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
8628 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
8629 (rc6_mode
& INTEL_RC6_ENABLE
) ? "on" : "off",
8630 (rc6_mode
& INTEL_RC6p_ENABLE
) ? "on" : "off",
8631 (rc6_mode
& INTEL_RC6pp_ENABLE
) ? "on" : "off");
8633 I915_WRITE(GEN6_RC_CONTROL
,
8635 GEN6_RC_CTL_EI_MODE(1) |
8636 GEN6_RC_CTL_HW_ENABLE
);
8638 I915_WRITE(GEN6_RPNSWREQ
,
8639 GEN6_FREQUENCY(10) |
8641 GEN6_AGGRESSIVE_TURBO
);
8642 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
8643 GEN6_FREQUENCY(12));
8645 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
8646 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
8649 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 10000);
8650 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 1000000);
8651 I915_WRITE(GEN6_RP_UP_EI
, 100000);
8652 I915_WRITE(GEN6_RP_DOWN_EI
, 5000000);
8653 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
8654 I915_WRITE(GEN6_RP_CONTROL
,
8655 GEN6_RP_MEDIA_TURBO
|
8656 GEN6_RP_MEDIA_HW_MODE
|
8657 GEN6_RP_MEDIA_IS_GFX
|
8659 GEN6_RP_UP_BUSY_AVG
|
8660 GEN6_RP_DOWN_IDLE_CONT
);
8662 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
8664 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8666 I915_WRITE(GEN6_PCODE_DATA
, 0);
8667 I915_WRITE(GEN6_PCODE_MAILBOX
,
8669 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
);
8670 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
8672 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8674 min_freq
= (rp_state_cap
& 0xff0000) >> 16;
8675 max_freq
= rp_state_cap
& 0xff;
8676 cur_freq
= (gt_perf_status
& 0xff00) >> 8;
8678 /* Check for overclock support */
8679 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
8681 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8682 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_READ_OC_PARAMS
);
8683 pcu_mbox
= I915_READ(GEN6_PCODE_DATA
);
8684 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
8686 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8687 if (pcu_mbox
& (1<<31)) { /* OC supported */
8688 max_freq
= pcu_mbox
& 0xff;
8689 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox
* 50);
8692 /* In units of 100MHz */
8693 dev_priv
->max_delay
= max_freq
;
8694 dev_priv
->min_delay
= min_freq
;
8695 dev_priv
->cur_delay
= cur_freq
;
8697 /* requires MSI enabled */
8698 I915_WRITE(GEN6_PMIER
,
8699 GEN6_PM_MBOX_EVENT
|
8700 GEN6_PM_THERMAL_EVENT
|
8701 GEN6_PM_RP_DOWN_TIMEOUT
|
8702 GEN6_PM_RP_UP_THRESHOLD
|
8703 GEN6_PM_RP_DOWN_THRESHOLD
|
8704 GEN6_PM_RP_UP_EI_EXPIRED
|
8705 GEN6_PM_RP_DOWN_EI_EXPIRED
);
8706 spin_lock_irq(&dev_priv
->rps_lock
);
8707 WARN_ON(dev_priv
->pm_iir
!= 0);
8708 I915_WRITE(GEN6_PMIMR
, 0);
8709 spin_unlock_irq(&dev_priv
->rps_lock
);
8710 /* enable all PM interrupts */
8711 I915_WRITE(GEN6_PMINTRMSK
, 0);
8713 gen6_gt_force_wake_put(dev_priv
);
8714 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
8717 void gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
8720 int gpu_freq
, ia_freq
, max_ia_freq
;
8721 int scaling_factor
= 180;
8723 max_ia_freq
= cpufreq_quick_get_max(0);
8725 * Default to measured freq if none found, PCU will ensure we don't go
8729 max_ia_freq
= tsc_khz
;
8731 /* Convert from kHz to MHz */
8732 max_ia_freq
/= 1000;
8734 mutex_lock(&dev_priv
->dev
->struct_mutex
);
8737 * For each potential GPU frequency, load a ring frequency we'd like
8738 * to use for memory access. We do this by specifying the IA frequency
8739 * the PCU should use as a reference to determine the ring frequency.
8741 for (gpu_freq
= dev_priv
->max_delay
; gpu_freq
>= dev_priv
->min_delay
;
8743 int diff
= dev_priv
->max_delay
- gpu_freq
;
8746 * For GPU frequencies less than 750MHz, just use the lowest
8749 if (gpu_freq
< min_freq
)
8752 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
8753 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
8755 I915_WRITE(GEN6_PCODE_DATA
,
8756 (ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
) |
8758 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
|
8759 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
);
8760 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) &
8761 GEN6_PCODE_READY
) == 0, 10)) {
8762 DRM_ERROR("pcode write of freq table timed out\n");
8767 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
8770 static void ironlake_init_clock_gating(struct drm_device
*dev
)
8772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8773 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
8775 /* Required for FBC */
8776 dspclk_gate
|= DPFCUNIT_CLOCK_GATE_DISABLE
|
8777 DPFCRUNIT_CLOCK_GATE_DISABLE
|
8778 DPFDUNIT_CLOCK_GATE_DISABLE
;
8779 /* Required for CxSR */
8780 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
8782 I915_WRITE(PCH_3DCGDIS0
,
8783 MARIUNIT_CLOCK_GATE_DISABLE
|
8784 SVSMUNIT_CLOCK_GATE_DISABLE
);
8785 I915_WRITE(PCH_3DCGDIS1
,
8786 VFMUNIT_CLOCK_GATE_DISABLE
);
8788 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
8791 * According to the spec the following bits should be set in
8792 * order to enable memory self-refresh
8793 * The bit 22/21 of 0x42004
8794 * The bit 5 of 0x42020
8795 * The bit 15 of 0x45000
8797 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8798 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
8799 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
8800 I915_WRITE(ILK_DSPCLK_GATE
,
8801 (I915_READ(ILK_DSPCLK_GATE
) |
8802 ILK_DPARB_CLK_GATE
));
8803 I915_WRITE(DISP_ARB_CTL
,
8804 (I915_READ(DISP_ARB_CTL
) |
8806 I915_WRITE(WM3_LP_ILK
, 0);
8807 I915_WRITE(WM2_LP_ILK
, 0);
8808 I915_WRITE(WM1_LP_ILK
, 0);
8811 * Based on the document from hardware guys the following bits
8812 * should be set unconditionally in order to enable FBC.
8813 * The bit 22 of 0x42000
8814 * The bit 22 of 0x42004
8815 * The bit 7,8,9 of 0x42020.
8817 if (IS_IRONLAKE_M(dev
)) {
8818 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
8819 I915_READ(ILK_DISPLAY_CHICKEN1
) |
8821 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8822 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8824 I915_WRITE(ILK_DSPCLK_GATE
,
8825 I915_READ(ILK_DSPCLK_GATE
) |
8831 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8832 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8833 ILK_ELPIN_409_SELECT
);
8834 I915_WRITE(_3D_CHICKEN2
,
8835 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
8836 _3D_CHICKEN2_WM_READ_PIPELINED
);
8839 static void gen6_init_clock_gating(struct drm_device
*dev
)
8841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8843 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
8845 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
8847 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8848 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8849 ILK_ELPIN_409_SELECT
);
8851 I915_WRITE(WM3_LP_ILK
, 0);
8852 I915_WRITE(WM2_LP_ILK
, 0);
8853 I915_WRITE(WM1_LP_ILK
, 0);
8855 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8856 * gating disable must be set. Failure to set it results in
8857 * flickering pixels due to Z write ordering failures after
8858 * some amount of runtime in the Mesa "fire" demo, and Unigine
8859 * Sanctuary and Tropics, and apparently anything else with
8860 * alpha test or pixel discard.
8862 * According to the spec, bit 11 (RCCUNIT) must also be set,
8863 * but we didn't debug actual testcases to find it out.
8865 I915_WRITE(GEN6_UCGCTL2
,
8866 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
8867 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
8870 * According to the spec the following bits should be
8871 * set in order to enable memory self-refresh and fbc:
8872 * The bit21 and bit22 of 0x42000
8873 * The bit21 and bit22 of 0x42004
8874 * The bit5 and bit7 of 0x42020
8875 * The bit14 of 0x70180
8876 * The bit14 of 0x71180
8878 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
8879 I915_READ(ILK_DISPLAY_CHICKEN1
) |
8880 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
8881 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8882 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8883 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
8884 I915_WRITE(ILK_DSPCLK_GATE
,
8885 I915_READ(ILK_DSPCLK_GATE
) |
8886 ILK_DPARB_CLK_GATE
|
8889 for_each_pipe(pipe
) {
8890 I915_WRITE(DSPCNTR(pipe
),
8891 I915_READ(DSPCNTR(pipe
)) |
8892 DISPPLANE_TRICKLE_FEED_DISABLE
);
8893 intel_flush_display_plane(dev_priv
, pipe
);
8897 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
8899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8901 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
8903 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
8905 I915_WRITE(WM3_LP_ILK
, 0);
8906 I915_WRITE(WM2_LP_ILK
, 0);
8907 I915_WRITE(WM1_LP_ILK
, 0);
8909 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8910 * This implements the WaDisableRCZUnitClockGating workaround.
8912 I915_WRITE(GEN6_UCGCTL2
, GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
8914 I915_WRITE(ILK_DSPCLK_GATE
, IVB_VRHUNIT_CLK_GATE
);
8916 I915_WRITE(IVB_CHICKEN3
,
8917 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
8918 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
8920 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8921 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
8922 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
8924 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8925 I915_WRITE(GEN7_L3CNTLREG1
,
8926 GEN7_WA_FOR_GEN7_L3_CONTROL
);
8927 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
8928 GEN7_WA_L3_CHICKEN_MODE
);
8930 /* This is required by WaCatErrorRejectionIssue */
8931 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
8932 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
8933 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
8935 for_each_pipe(pipe
) {
8936 I915_WRITE(DSPCNTR(pipe
),
8937 I915_READ(DSPCNTR(pipe
)) |
8938 DISPPLANE_TRICKLE_FEED_DISABLE
);
8939 intel_flush_display_plane(dev_priv
, pipe
);
8943 static void valleyview_init_clock_gating(struct drm_device
*dev
)
8945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8947 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
8949 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
8951 I915_WRITE(WM3_LP_ILK
, 0);
8952 I915_WRITE(WM2_LP_ILK
, 0);
8953 I915_WRITE(WM1_LP_ILK
, 0);
8955 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8956 * This implements the WaDisableRCZUnitClockGating workaround.
8958 I915_WRITE(GEN6_UCGCTL2
, GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
8960 I915_WRITE(ILK_DSPCLK_GATE
, IVB_VRHUNIT_CLK_GATE
);
8962 I915_WRITE(IVB_CHICKEN3
,
8963 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
8964 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
8966 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8967 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
8968 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
8970 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8971 I915_WRITE(GEN7_L3CNTLREG1
, GEN7_WA_FOR_GEN7_L3_CONTROL
);
8972 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
, GEN7_WA_L3_CHICKEN_MODE
);
8974 /* This is required by WaCatErrorRejectionIssue */
8975 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
8976 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
8977 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
8979 for_each_pipe(pipe
) {
8980 I915_WRITE(DSPCNTR(pipe
),
8981 I915_READ(DSPCNTR(pipe
)) |
8982 DISPPLANE_TRICKLE_FEED_DISABLE
);
8983 intel_flush_display_plane(dev_priv
, pipe
);
8986 I915_WRITE(CACHE_MODE_1
, I915_READ(CACHE_MODE_1
) |
8987 (PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
<< 16) |
8988 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
);
8991 static void g4x_init_clock_gating(struct drm_device
*dev
)
8993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8994 uint32_t dspclk_gate
;
8996 I915_WRITE(RENCLK_GATE_D1
, 0);
8997 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
8998 GS_UNIT_CLOCK_GATE_DISABLE
|
8999 CL_UNIT_CLOCK_GATE_DISABLE
);
9000 I915_WRITE(RAMCLK_GATE_D
, 0);
9001 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
9002 OVRUNIT_CLOCK_GATE_DISABLE
|
9003 OVCUNIT_CLOCK_GATE_DISABLE
;
9005 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
9006 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
9009 static void crestline_init_clock_gating(struct drm_device
*dev
)
9011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9013 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
9014 I915_WRITE(RENCLK_GATE_D2
, 0);
9015 I915_WRITE(DSPCLK_GATE_D
, 0);
9016 I915_WRITE(RAMCLK_GATE_D
, 0);
9017 I915_WRITE16(DEUC
, 0);
9020 static void broadwater_init_clock_gating(struct drm_device
*dev
)
9022 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9024 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
9025 I965_RCC_CLOCK_GATE_DISABLE
|
9026 I965_RCPB_CLOCK_GATE_DISABLE
|
9027 I965_ISC_CLOCK_GATE_DISABLE
|
9028 I965_FBC_CLOCK_GATE_DISABLE
);
9029 I915_WRITE(RENCLK_GATE_D2
, 0);
9032 static void gen3_init_clock_gating(struct drm_device
*dev
)
9034 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9035 u32 dstate
= I915_READ(D_STATE
);
9037 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
9038 DSTATE_DOT_CLOCK_GATING
;
9039 I915_WRITE(D_STATE
, dstate
);
9042 static void i85x_init_clock_gating(struct drm_device
*dev
)
9044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9046 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
9049 static void i830_init_clock_gating(struct drm_device
*dev
)
9051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9053 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
9056 static void ibx_init_clock_gating(struct drm_device
*dev
)
9058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9061 * On Ibex Peak and Cougar Point, we need to disable clock
9062 * gating for the panel power sequencer or it will fail to
9063 * start up when no ports are active.
9065 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
9068 static void cpt_init_clock_gating(struct drm_device
*dev
)
9070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9074 * On Ibex Peak and Cougar Point, we need to disable clock
9075 * gating for the panel power sequencer or it will fail to
9076 * start up when no ports are active.
9078 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
9079 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
9080 DPLS_EDP_PPS_FIX_DIS
);
9081 /* Without this, mode sets may fail silently on FDI */
9083 I915_WRITE(TRANS_CHICKEN2(pipe
), TRANS_AUTOTRAIN_GEN_STALL_DIS
);
9086 static void ironlake_teardown_rc6(struct drm_device
*dev
)
9088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9090 if (dev_priv
->renderctx
) {
9091 i915_gem_object_unpin(dev_priv
->renderctx
);
9092 drm_gem_object_unreference(&dev_priv
->renderctx
->base
);
9093 dev_priv
->renderctx
= NULL
;
9096 if (dev_priv
->pwrctx
) {
9097 i915_gem_object_unpin(dev_priv
->pwrctx
);
9098 drm_gem_object_unreference(&dev_priv
->pwrctx
->base
);
9099 dev_priv
->pwrctx
= NULL
;
9103 static void ironlake_disable_rc6(struct drm_device
*dev
)
9105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9107 if (I915_READ(PWRCTXA
)) {
9108 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
9109 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
9110 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
9113 I915_WRITE(PWRCTXA
, 0);
9114 POSTING_READ(PWRCTXA
);
9116 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
9117 POSTING_READ(RSTDBYCTL
);
9120 ironlake_teardown_rc6(dev
);
9123 static int ironlake_setup_rc6(struct drm_device
*dev
)
9125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9127 if (dev_priv
->renderctx
== NULL
)
9128 dev_priv
->renderctx
= intel_alloc_context_page(dev
);
9129 if (!dev_priv
->renderctx
)
9132 if (dev_priv
->pwrctx
== NULL
)
9133 dev_priv
->pwrctx
= intel_alloc_context_page(dev
);
9134 if (!dev_priv
->pwrctx
) {
9135 ironlake_teardown_rc6(dev
);
9142 void ironlake_enable_rc6(struct drm_device
*dev
)
9144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9147 /* rc6 disabled by default due to repeated reports of hanging during
9150 if (!intel_enable_rc6(dev
))
9153 mutex_lock(&dev
->struct_mutex
);
9154 ret
= ironlake_setup_rc6(dev
);
9156 mutex_unlock(&dev
->struct_mutex
);
9161 * GPU can automatically power down the render unit if given a page
9164 ret
= BEGIN_LP_RING(6);
9166 ironlake_teardown_rc6(dev
);
9167 mutex_unlock(&dev
->struct_mutex
);
9171 OUT_RING(MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
9172 OUT_RING(MI_SET_CONTEXT
);
9173 OUT_RING(dev_priv
->renderctx
->gtt_offset
|
9175 MI_SAVE_EXT_STATE_EN
|
9176 MI_RESTORE_EXT_STATE_EN
|
9177 MI_RESTORE_INHIBIT
);
9178 OUT_RING(MI_SUSPEND_FLUSH
);
9184 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
9185 * does an implicit flush, combined with MI_FLUSH above, it should be
9186 * safe to assume that renderctx is valid
9188 ret
= intel_wait_ring_idle(LP_RING(dev_priv
));
9190 DRM_ERROR("failed to enable ironlake power power savings\n");
9191 ironlake_teardown_rc6(dev
);
9192 mutex_unlock(&dev
->struct_mutex
);
9196 I915_WRITE(PWRCTXA
, dev_priv
->pwrctx
->gtt_offset
| PWRCTX_EN
);
9197 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
9198 mutex_unlock(&dev
->struct_mutex
);
9201 void intel_init_clock_gating(struct drm_device
*dev
)
9203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9205 dev_priv
->display
.init_clock_gating(dev
);
9207 if (dev_priv
->display
.init_pch_clock_gating
)
9208 dev_priv
->display
.init_pch_clock_gating(dev
);
9211 /* Set up chip specific display functions */
9212 static void intel_init_display(struct drm_device
*dev
)
9214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9216 /* We always want a DPMS function */
9217 if (HAS_PCH_SPLIT(dev
)) {
9218 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
9219 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
9220 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9222 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
9223 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9224 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9227 if (I915_HAS_FBC(dev
)) {
9228 if (HAS_PCH_SPLIT(dev
)) {
9229 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
9230 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
9231 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
9232 } else if (IS_GM45(dev
)) {
9233 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
9234 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
9235 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
9236 } else if (IS_CRESTLINE(dev
)) {
9237 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
9238 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
9239 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
9241 /* 855GM needs testing */
9244 /* Returns the core display clock speed */
9245 if (IS_VALLEYVIEW(dev
))
9246 dev_priv
->display
.get_display_clock_speed
=
9247 valleyview_get_display_clock_speed
;
9248 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
9249 dev_priv
->display
.get_display_clock_speed
=
9250 i945_get_display_clock_speed
;
9251 else if (IS_I915G(dev
))
9252 dev_priv
->display
.get_display_clock_speed
=
9253 i915_get_display_clock_speed
;
9254 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
9255 dev_priv
->display
.get_display_clock_speed
=
9256 i9xx_misc_get_display_clock_speed
;
9257 else if (IS_I915GM(dev
))
9258 dev_priv
->display
.get_display_clock_speed
=
9259 i915gm_get_display_clock_speed
;
9260 else if (IS_I865G(dev
))
9261 dev_priv
->display
.get_display_clock_speed
=
9262 i865_get_display_clock_speed
;
9263 else if (IS_I85X(dev
))
9264 dev_priv
->display
.get_display_clock_speed
=
9265 i855_get_display_clock_speed
;
9267 dev_priv
->display
.get_display_clock_speed
=
9268 i830_get_display_clock_speed
;
9270 /* For FIFO watermark updates */
9271 if (HAS_PCH_SPLIT(dev
)) {
9272 dev_priv
->display
.force_wake_get
= __gen6_gt_force_wake_get
;
9273 dev_priv
->display
.force_wake_put
= __gen6_gt_force_wake_put
;
9275 /* IVB configs may use multi-threaded forcewake */
9276 if (IS_IVYBRIDGE(dev
)) {
9279 /* A small trick here - if the bios hasn't configured MT forcewake,
9280 * and if the device is in RC6, then force_wake_mt_get will not wake
9281 * the device and the ECOBUS read will return zero. Which will be
9282 * (correctly) interpreted by the test below as MT forcewake being
9285 mutex_lock(&dev
->struct_mutex
);
9286 __gen6_gt_force_wake_mt_get(dev_priv
);
9287 ecobus
= I915_READ_NOTRACE(ECOBUS
);
9288 __gen6_gt_force_wake_mt_put(dev_priv
);
9289 mutex_unlock(&dev
->struct_mutex
);
9291 if (ecobus
& FORCEWAKE_MT_ENABLE
) {
9292 DRM_DEBUG_KMS("Using MT version of forcewake\n");
9293 dev_priv
->display
.force_wake_get
=
9294 __gen6_gt_force_wake_mt_get
;
9295 dev_priv
->display
.force_wake_put
=
9296 __gen6_gt_force_wake_mt_put
;
9300 if (HAS_PCH_IBX(dev
))
9301 dev_priv
->display
.init_pch_clock_gating
= ibx_init_clock_gating
;
9302 else if (HAS_PCH_CPT(dev
))
9303 dev_priv
->display
.init_pch_clock_gating
= cpt_init_clock_gating
;
9306 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
9307 dev_priv
->display
.update_wm
= ironlake_update_wm
;
9309 DRM_DEBUG_KMS("Failed to get proper latency. "
9311 dev_priv
->display
.update_wm
= NULL
;
9313 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
9314 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
9315 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9316 } else if (IS_GEN6(dev
)) {
9317 if (SNB_READ_WM0_LATENCY()) {
9318 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
9319 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
9321 DRM_DEBUG_KMS("Failed to read display plane latency. "
9323 dev_priv
->display
.update_wm
= NULL
;
9325 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
9326 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
9327 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9328 } else if (IS_IVYBRIDGE(dev
)) {
9329 /* FIXME: detect B0+ stepping and use auto training */
9330 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
9331 if (SNB_READ_WM0_LATENCY()) {
9332 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
9333 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
9335 DRM_DEBUG_KMS("Failed to read display plane latency. "
9337 dev_priv
->display
.update_wm
= NULL
;
9339 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
9340 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9342 dev_priv
->display
.update_wm
= NULL
;
9343 } else if (IS_VALLEYVIEW(dev
)) {
9344 dev_priv
->display
.update_wm
= valleyview_update_wm
;
9345 dev_priv
->display
.init_clock_gating
=
9346 valleyview_init_clock_gating
;
9347 dev_priv
->display
.force_wake_get
= vlv_force_wake_get
;
9348 dev_priv
->display
.force_wake_put
= vlv_force_wake_put
;
9349 } else if (IS_PINEVIEW(dev
)) {
9350 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
9353 dev_priv
->mem_freq
)) {
9354 DRM_INFO("failed to find known CxSR latency "
9355 "(found ddr%s fsb freq %d, mem freq %d), "
9357 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
9358 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
9359 /* Disable CxSR and never update its watermark again */
9360 pineview_disable_cxsr(dev
);
9361 dev_priv
->display
.update_wm
= NULL
;
9363 dev_priv
->display
.update_wm
= pineview_update_wm
;
9364 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
9365 } else if (IS_G4X(dev
)) {
9366 dev_priv
->display
.write_eld
= g4x_write_eld
;
9367 dev_priv
->display
.update_wm
= g4x_update_wm
;
9368 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
9369 } else if (IS_GEN4(dev
)) {
9370 dev_priv
->display
.update_wm
= i965_update_wm
;
9371 if (IS_CRESTLINE(dev
))
9372 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
9373 else if (IS_BROADWATER(dev
))
9374 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
9375 } else if (IS_GEN3(dev
)) {
9376 dev_priv
->display
.update_wm
= i9xx_update_wm
;
9377 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
9378 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
9379 } else if (IS_I865G(dev
)) {
9380 dev_priv
->display
.update_wm
= i830_update_wm
;
9381 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
9382 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
9383 } else if (IS_I85X(dev
)) {
9384 dev_priv
->display
.update_wm
= i9xx_update_wm
;
9385 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
9386 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
9388 dev_priv
->display
.update_wm
= i830_update_wm
;
9389 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
9391 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
9393 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
9396 /* Default just returns -ENODEV to indicate unsupported */
9397 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
9399 switch (INTEL_INFO(dev
)->gen
) {
9401 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
9405 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
9410 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
9414 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
9417 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
9423 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9424 * resume, or other times. This quirk makes sure that's the case for
9427 static void quirk_pipea_force(struct drm_device
*dev
)
9429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9431 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
9432 DRM_INFO("applying pipe a force quirk\n");
9436 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9438 static void quirk_ssc_force_disable(struct drm_device
*dev
)
9440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9441 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
9442 DRM_INFO("applying lvds SSC disable quirk\n");
9446 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9449 static void quirk_invert_brightness(struct drm_device
*dev
)
9451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9452 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
9453 DRM_INFO("applying inverted panel brightness quirk\n");
9456 struct intel_quirk
{
9458 int subsystem_vendor
;
9459 int subsystem_device
;
9460 void (*hook
)(struct drm_device
*dev
);
9463 struct intel_quirk intel_quirks
[] = {
9464 /* HP Mini needs pipe A force quirk (LP: #322104) */
9465 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
9467 /* Thinkpad R31 needs pipe A force quirk */
9468 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
9469 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9470 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
9472 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9473 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
9474 /* ThinkPad X40 needs pipe A force quirk */
9476 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9477 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
9479 /* 855 & before need to leave pipe A & dpll A up */
9480 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9481 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9483 /* Lenovo U160 cannot use SSC on LVDS */
9484 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
9486 /* Sony Vaio Y cannot use SSC on LVDS */
9487 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
9489 /* Acer Aspire 5734Z must invert backlight brightness */
9490 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
9493 static void intel_init_quirks(struct drm_device
*dev
)
9495 struct pci_dev
*d
= dev
->pdev
;
9498 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
9499 struct intel_quirk
*q
= &intel_quirks
[i
];
9501 if (d
->device
== q
->device
&&
9502 (d
->subsystem_vendor
== q
->subsystem_vendor
||
9503 q
->subsystem_vendor
== PCI_ANY_ID
) &&
9504 (d
->subsystem_device
== q
->subsystem_device
||
9505 q
->subsystem_device
== PCI_ANY_ID
))
9510 /* Disable the VGA plane that we never use */
9511 static void i915_disable_vga(struct drm_device
*dev
)
9513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9517 if (HAS_PCH_SPLIT(dev
))
9518 vga_reg
= CPU_VGACNTRL
;
9522 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9523 outb(SR01
, VGA_SR_INDEX
);
9524 sr1
= inb(VGA_SR_DATA
);
9525 outb(sr1
| 1<<5, VGA_SR_DATA
);
9526 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9529 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
9530 POSTING_READ(vga_reg
);
9533 void intel_modeset_init(struct drm_device
*dev
)
9535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9538 drm_mode_config_init(dev
);
9540 dev
->mode_config
.min_width
= 0;
9541 dev
->mode_config
.min_height
= 0;
9543 dev
->mode_config
.preferred_depth
= 24;
9544 dev
->mode_config
.prefer_shadow
= 1;
9546 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
9548 intel_init_quirks(dev
);
9550 intel_init_display(dev
);
9553 dev
->mode_config
.max_width
= 2048;
9554 dev
->mode_config
.max_height
= 2048;
9555 } else if (IS_GEN3(dev
)) {
9556 dev
->mode_config
.max_width
= 4096;
9557 dev
->mode_config
.max_height
= 4096;
9559 dev
->mode_config
.max_width
= 8192;
9560 dev
->mode_config
.max_height
= 8192;
9562 dev
->mode_config
.fb_base
= dev
->agp
->base
;
9564 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9565 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
9567 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
9568 intel_crtc_init(dev
, i
);
9569 ret
= intel_plane_init(dev
, i
);
9571 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
9574 /* Just disable it once at startup */
9575 i915_disable_vga(dev
);
9576 intel_setup_outputs(dev
);
9578 intel_init_clock_gating(dev
);
9580 if (IS_IRONLAKE_M(dev
)) {
9581 ironlake_enable_drps(dev
);
9582 intel_init_emon(dev
);
9585 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
9586 gen6_enable_rps(dev_priv
);
9587 gen6_update_ring_freq(dev_priv
);
9590 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
9591 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
9592 (unsigned long)dev
);
9595 void intel_modeset_gem_init(struct drm_device
*dev
)
9597 if (IS_IRONLAKE_M(dev
))
9598 ironlake_enable_rc6(dev
);
9600 intel_setup_overlay(dev
);
9603 void intel_modeset_cleanup(struct drm_device
*dev
)
9605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9606 struct drm_crtc
*crtc
;
9607 struct intel_crtc
*intel_crtc
;
9609 drm_kms_helper_poll_fini(dev
);
9610 mutex_lock(&dev
->struct_mutex
);
9612 intel_unregister_dsm_handler();
9615 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9616 /* Skip inactive CRTCs */
9620 intel_crtc
= to_intel_crtc(crtc
);
9621 intel_increase_pllclock(crtc
);
9624 intel_disable_fbc(dev
);
9626 if (IS_IRONLAKE_M(dev
))
9627 ironlake_disable_drps(dev
);
9628 if (IS_GEN6(dev
) || IS_GEN7(dev
))
9629 gen6_disable_rps(dev
);
9631 if (IS_IRONLAKE_M(dev
))
9632 ironlake_disable_rc6(dev
);
9634 if (IS_VALLEYVIEW(dev
))
9637 mutex_unlock(&dev
->struct_mutex
);
9639 /* Disable the irq before mode object teardown, for the irq might
9640 * enqueue unpin/hotplug work. */
9641 drm_irq_uninstall(dev
);
9642 cancel_work_sync(&dev_priv
->hotplug_work
);
9643 cancel_work_sync(&dev_priv
->rps_work
);
9645 /* flush any delayed tasks or pending work */
9646 flush_scheduled_work();
9648 /* Shut off idle work before the crtcs get freed. */
9649 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9650 intel_crtc
= to_intel_crtc(crtc
);
9651 del_timer_sync(&intel_crtc
->idle_timer
);
9653 del_timer_sync(&dev_priv
->idle_timer
);
9654 cancel_work_sync(&dev_priv
->idle_work
);
9656 drm_mode_config_cleanup(dev
);
9660 * Return which encoder is currently attached for connector.
9662 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9664 return &intel_attached_encoder(connector
)->base
;
9667 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9668 struct intel_encoder
*encoder
)
9670 connector
->encoder
= encoder
;
9671 drm_mode_connector_attach_encoder(&connector
->base
,
9676 * set vga decode state - true == enable VGA decode
9678 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9683 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9685 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9687 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9688 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9692 #ifdef CONFIG_DEBUG_FS
9693 #include <linux/seq_file.h>
9695 struct intel_display_error_state
{
9696 struct intel_cursor_error_state
{
9703 struct intel_pipe_error_state
{
9715 struct intel_plane_error_state
{
9726 struct intel_display_error_state
*
9727 intel_display_capture_error_state(struct drm_device
*dev
)
9729 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9730 struct intel_display_error_state
*error
;
9733 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
9737 for (i
= 0; i
< 2; i
++) {
9738 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
9739 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
9740 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
9742 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
9743 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
9744 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
9745 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
9746 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
9747 if (INTEL_INFO(dev
)->gen
>= 4) {
9748 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
9749 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
9752 error
->pipe
[i
].conf
= I915_READ(PIPECONF(i
));
9753 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
9754 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(i
));
9755 error
->pipe
[i
].hblank
= I915_READ(HBLANK(i
));
9756 error
->pipe
[i
].hsync
= I915_READ(HSYNC(i
));
9757 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(i
));
9758 error
->pipe
[i
].vblank
= I915_READ(VBLANK(i
));
9759 error
->pipe
[i
].vsync
= I915_READ(VSYNC(i
));
9766 intel_display_print_error_state(struct seq_file
*m
,
9767 struct drm_device
*dev
,
9768 struct intel_display_error_state
*error
)
9772 for (i
= 0; i
< 2; i
++) {
9773 seq_printf(m
, "Pipe [%d]:\n", i
);
9774 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
9775 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
9776 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
9777 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
9778 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
9779 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
9780 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
9781 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
9783 seq_printf(m
, "Plane [%d]:\n", i
);
9784 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
9785 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
9786 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
9787 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
9788 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
9789 if (INTEL_INFO(dev
)->gen
>= 4) {
9790 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
9791 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9794 seq_printf(m
, "Cursor [%d]:\n", i
);
9795 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9796 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9797 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);