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drm/i915/skl: Allow scanning out Y and Yf fbs
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_dp_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_rect.h>
45 #include <linux/dma_remapping.h>
46
47 /* Primary plane formats supported by all gen */
48 #define COMMON_PRIMARY_FORMATS \
49 DRM_FORMAT_C8, \
50 DRM_FORMAT_RGB565, \
51 DRM_FORMAT_XRGB8888, \
52 DRM_FORMAT_ARGB8888
53
54 /* Primary plane formats for gen <= 3 */
55 static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
57 DRM_FORMAT_XRGB1555,
58 DRM_FORMAT_ARGB1555,
59 };
60
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_ABGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
70 };
71
72 /* Cursor formats */
73 static const uint32_t intel_cursor_formats[] = {
74 DRM_FORMAT_ARGB8888,
75 };
76
77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78
79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
80 struct intel_crtc_state *pipe_config);
81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
82 struct intel_crtc_state *pipe_config);
83
84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
86 static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
98 static void vlv_prepare_pll(struct intel_crtc *crtc,
99 const struct intel_crtc_state *pipe_config);
100 static void chv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
415 {
416 struct drm_device *dev = crtc->base.dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 /**
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
430 * encoder->crtc.
431 */
432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
433 {
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
436
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
439 return true;
440
441 return false;
442 }
443
444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
445 int refclk)
446 {
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev)) {
452 if (refclk == 100000)
453 limit = &intel_limits_ironlake_dual_lvds_100m;
454 else
455 limit = &intel_limits_ironlake_dual_lvds;
456 } else {
457 if (refclk == 100000)
458 limit = &intel_limits_ironlake_single_lvds_100m;
459 else
460 limit = &intel_limits_ironlake_single_lvds;
461 }
462 } else
463 limit = &intel_limits_ironlake_dac;
464
465 return limit;
466 }
467
468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
469 {
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
472
473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (intel_is_dual_link_lvds(dev))
475 limit = &intel_limits_g4x_dual_channel_lvds;
476 else
477 limit = &intel_limits_g4x_single_channel_lvds;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
480 limit = &intel_limits_g4x_hdmi;
481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
482 limit = &intel_limits_g4x_sdvo;
483 } else /* The option is for other outputs */
484 limit = &intel_limits_i9xx_sdvo;
485
486 return limit;
487 }
488
489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
490 {
491 struct drm_device *dev = crtc->base.dev;
492 const intel_limit_t *limit;
493
494 if (HAS_PCH_SPLIT(dev))
495 limit = intel_ironlake_limit(crtc, refclk);
496 else if (IS_G4X(dev)) {
497 limit = intel_g4x_limit(crtc);
498 } else if (IS_PINEVIEW(dev)) {
499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
500 limit = &intel_limits_pineview_lvds;
501 else
502 limit = &intel_limits_pineview_sdvo;
503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
505 } else if (IS_VALLEYVIEW(dev)) {
506 limit = &intel_limits_vlv;
507 } else if (!IS_GEN2(dev)) {
508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
509 limit = &intel_limits_i9xx_lvds;
510 else
511 limit = &intel_limits_i9xx_sdvo;
512 } else {
513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
514 limit = &intel_limits_i8xx_lvds;
515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
516 limit = &intel_limits_i8xx_dvo;
517 else
518 limit = &intel_limits_i8xx_dac;
519 }
520 return limit;
521 }
522
523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
524 static void pineview_clock(int refclk, intel_clock_t *clock)
525 {
526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return;
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
532 }
533
534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
535 {
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
537 }
538
539 static void i9xx_clock(int refclk, intel_clock_t *clock)
540 {
541 clock->m = i9xx_dpll_compute_m(clock);
542 clock->p = clock->p1 * clock->p2;
543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
544 return;
545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
547 }
548
549 static void chv_clock(int refclk, intel_clock_t *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558 }
559
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561 /**
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
564 */
565
566 static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
569 {
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
578
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
582
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
588 }
589
590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
594 */
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
596 INTELPllInvalid("dot out of range\n");
597
598 return true;
599 }
600
601 static bool
602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
605 {
606 struct drm_device *dev = crtc->base.dev;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
611 /*
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
615 */
616 if (intel_is_dual_link_lvds(dev))
617 clock.p2 = limit->p2.p2_fast;
618 else
619 clock.p2 = limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
623 else
624 clock.p2 = limit->p2.p2_fast;
625 }
626
627 memset(best_clock, 0, sizeof(*best_clock));
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645 if (match_clock &&
646 clock.p != match_clock->p)
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
651 *best_clock = clock;
652 err = this_err;
653 }
654 }
655 }
656 }
657 }
658
659 return (err != target);
660 }
661
662 static bool
663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
666 {
667 struct drm_device *dev = crtc->base.dev;
668 intel_clock_t clock;
669 int err = target;
670
671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
672 /*
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
676 */
677 if (intel_is_dual_link_lvds(dev))
678 clock.p2 = limit->p2.p2_fast;
679 else
680 clock.p2 = limit->p2.p2_slow;
681 } else {
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
684 else
685 clock.p2 = limit->p2.p2_fast;
686 }
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
691 clock.m1++) {
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 pineview_clock(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 static bool
722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
725 {
726 struct drm_device *dev = crtc->base.dev;
727 intel_clock_t clock;
728 int max_n;
729 bool found;
730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
732 found = false;
733
734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
735 if (intel_is_dual_link_lvds(dev))
736 clock.p2 = limit->p2.p2_fast;
737 else
738 clock.p2 = limit->p2.p2_slow;
739 } else {
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
742 else
743 clock.p2 = limit->p2.p2_fast;
744 }
745
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_clock(refclk, &clock);
760 if (!intel_PLL_is_valid(dev, limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776 }
777
778 static bool
779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
782 {
783 struct drm_device *dev = crtc->base.dev;
784 intel_clock_t clock;
785 unsigned int bestppm = 1000000;
786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
788 bool found = false;
789
790 target *= 5; /* fast clock */
791
792 memset(best_clock, 0, sizeof(*best_clock));
793
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799 clock.p = clock.p1 * clock.p2;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
802 unsigned int ppm, diff;
803
804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
805 refclk * clock.m1);
806
807 vlv_clock(refclk, &clock);
808
809 if (!intel_PLL_is_valid(dev, limit,
810 &clock))
811 continue;
812
813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
815
816 if (ppm < 100 && clock.p > best_clock->p) {
817 bestppm = 0;
818 *best_clock = clock;
819 found = true;
820 }
821
822 if (bestppm >= 10 && ppm < bestppm - 10) {
823 bestppm = ppm;
824 *best_clock = clock;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831
832 return found;
833 }
834
835 static bool
836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 struct drm_device *dev = crtc->base.dev;
841 intel_clock_t clock;
842 uint64_t m2;
843 int found = false;
844
845 memset(best_clock, 0, sizeof(*best_clock));
846
847 /*
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
851 */
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
854
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
859
860 clock.p = clock.p1 * clock.p2;
861
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
864
865 if (m2 > INT_MAX/clock.m1)
866 continue;
867
868 clock.m2 = m2;
869
870 chv_clock(refclk, &clock);
871
872 if (!intel_PLL_is_valid(dev, limit, &clock))
873 continue;
874
875 /* based on hardware requirement, prefer bigger p
876 */
877 if (clock.p > best_clock->p) {
878 *best_clock = clock;
879 found = true;
880 }
881 }
882 }
883
884 return found;
885 }
886
887 bool intel_crtc_active(struct drm_crtc *crtc)
888 {
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
893 *
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
896 *
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
899 */
900 return intel_crtc->active && crtc->primary->fb &&
901 intel_crtc->config->base.adjusted_mode.crtc_clock;
902 }
903
904 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
905 enum pipe pipe)
906 {
907 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
909
910 return intel_crtc->config->cpu_transcoder;
911 }
912
913 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
914 {
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 u32 reg = PIPEDSL(pipe);
917 u32 line1, line2;
918 u32 line_mask;
919
920 if (IS_GEN2(dev))
921 line_mask = DSL_LINEMASK_GEN2;
922 else
923 line_mask = DSL_LINEMASK_GEN3;
924
925 line1 = I915_READ(reg) & line_mask;
926 mdelay(5);
927 line2 = I915_READ(reg) & line_mask;
928
929 return line1 == line2;
930 }
931
932 /*
933 * intel_wait_for_pipe_off - wait for pipe to turn off
934 * @crtc: crtc whose pipe to wait for
935 *
936 * After disabling a pipe, we can't wait for vblank in the usual way,
937 * spinning on the vblank interrupt status bit, since we won't actually
938 * see an interrupt when the pipe is disabled.
939 *
940 * On Gen4 and above:
941 * wait for the pipe register state bit to turn off
942 *
943 * Otherwise:
944 * wait for the display line value to settle (it usually
945 * ends up stopping at the start of the next frame).
946 *
947 */
948 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
949 {
950 struct drm_device *dev = crtc->base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
953 enum pipe pipe = crtc->pipe;
954
955 if (INTEL_INFO(dev)->gen >= 4) {
956 int reg = PIPECONF(cpu_transcoder);
957
958 /* Wait for the Pipe State to go off */
959 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
960 100))
961 WARN(1, "pipe_off wait timed out\n");
962 } else {
963 /* Wait for the display line to settle */
964 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
965 WARN(1, "pipe_off wait timed out\n");
966 }
967 }
968
969 /*
970 * ibx_digital_port_connected - is the specified port connected?
971 * @dev_priv: i915 private structure
972 * @port: the port to test
973 *
974 * Returns true if @port is connected, false otherwise.
975 */
976 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
977 struct intel_digital_port *port)
978 {
979 u32 bit;
980
981 if (HAS_PCH_IBX(dev_priv->dev)) {
982 switch (port->port) {
983 case PORT_B:
984 bit = SDE_PORTB_HOTPLUG;
985 break;
986 case PORT_C:
987 bit = SDE_PORTC_HOTPLUG;
988 break;
989 case PORT_D:
990 bit = SDE_PORTD_HOTPLUG;
991 break;
992 default:
993 return true;
994 }
995 } else {
996 switch (port->port) {
997 case PORT_B:
998 bit = SDE_PORTB_HOTPLUG_CPT;
999 break;
1000 case PORT_C:
1001 bit = SDE_PORTC_HOTPLUG_CPT;
1002 break;
1003 case PORT_D:
1004 bit = SDE_PORTD_HOTPLUG_CPT;
1005 break;
1006 default:
1007 return true;
1008 }
1009 }
1010
1011 return I915_READ(SDEISR) & bit;
1012 }
1013
1014 static const char *state_string(bool enabled)
1015 {
1016 return enabled ? "on" : "off";
1017 }
1018
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, bool state)
1022 {
1023 int reg;
1024 u32 val;
1025 bool cur_state;
1026
1027 reg = DPLL(pipe);
1028 val = I915_READ(reg);
1029 cur_state = !!(val & DPLL_VCO_ENABLE);
1030 I915_STATE_WARN(cur_state != state,
1031 "PLL state assertion failure (expected %s, current %s)\n",
1032 state_string(state), state_string(cur_state));
1033 }
1034
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1037 {
1038 u32 val;
1039 bool cur_state;
1040
1041 mutex_lock(&dev_priv->dpio_lock);
1042 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043 mutex_unlock(&dev_priv->dpio_lock);
1044
1045 cur_state = val & DSI_PLL_VCO_EN;
1046 I915_STATE_WARN(cur_state != state,
1047 "DSI PLL state assertion failure (expected %s, current %s)\n",
1048 state_string(state), state_string(cur_state));
1049 }
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052
1053 struct intel_shared_dpll *
1054 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1055 {
1056 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1057
1058 if (crtc->config->shared_dpll < 0)
1059 return NULL;
1060
1061 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1062 }
1063
1064 /* For ILK+ */
1065 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066 struct intel_shared_dpll *pll,
1067 bool state)
1068 {
1069 bool cur_state;
1070 struct intel_dpll_hw_state hw_state;
1071
1072 if (WARN (!pll,
1073 "asserting DPLL %s with no DPLL\n", state_string(state)))
1074 return;
1075
1076 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077 I915_STATE_WARN(cur_state != state,
1078 "%s assertion failure (expected %s, current %s)\n",
1079 pll->name, state_string(state), state_string(cur_state));
1080 }
1081
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083 enum pipe pipe, bool state)
1084 {
1085 int reg;
1086 u32 val;
1087 bool cur_state;
1088 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1089 pipe);
1090
1091 if (HAS_DDI(dev_priv->dev)) {
1092 /* DDI does not have a specific FDI_TX register */
1093 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094 val = I915_READ(reg);
1095 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1096 } else {
1097 reg = FDI_TX_CTL(pipe);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & FDI_TX_ENABLE);
1100 }
1101 I915_STATE_WARN(cur_state != state,
1102 "FDI TX state assertion failure (expected %s, current %s)\n",
1103 state_string(state), state_string(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109 enum pipe pipe, bool state)
1110 {
1111 int reg;
1112 u32 val;
1113 bool cur_state;
1114
1115 reg = FDI_RX_CTL(pipe);
1116 val = I915_READ(reg);
1117 cur_state = !!(val & FDI_RX_ENABLE);
1118 I915_STATE_WARN(cur_state != state,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 state_string(state), state_string(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127 {
1128 int reg;
1129 u32 val;
1130
1131 /* ILK FDI PLL is always enabled */
1132 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1133 return;
1134
1135 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136 if (HAS_DDI(dev_priv->dev))
1137 return;
1138
1139 reg = FDI_TX_CTL(pipe);
1140 val = I915_READ(reg);
1141 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1142 }
1143
1144 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154 I915_STATE_WARN(cur_state != state,
1155 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158
1159 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
1161 {
1162 struct drm_device *dev = dev_priv->dev;
1163 int pp_reg;
1164 u32 val;
1165 enum pipe panel_pipe = PIPE_A;
1166 bool locked = true;
1167
1168 if (WARN_ON(HAS_DDI(dev)))
1169 return;
1170
1171 if (HAS_PCH_SPLIT(dev)) {
1172 u32 port_sel;
1173
1174 pp_reg = PCH_PP_CONTROL;
1175 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1176
1177 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179 panel_pipe = PIPE_B;
1180 /* XXX: else fix for eDP */
1181 } else if (IS_VALLEYVIEW(dev)) {
1182 /* presumably write lock depends on pipe, not port select */
1183 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1184 panel_pipe = pipe;
1185 } else {
1186 pp_reg = PP_CONTROL;
1187 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188 panel_pipe = PIPE_B;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 I915_STATE_WARN(panel_pipe == pipe && locked,
1197 "panel assertion failure, pipe %c regs locked\n",
1198 pipe_name(pipe));
1199 }
1200
1201 static void assert_cursor(struct drm_i915_private *dev_priv,
1202 enum pipe pipe, bool state)
1203 {
1204 struct drm_device *dev = dev_priv->dev;
1205 bool cur_state;
1206
1207 if (IS_845G(dev) || IS_I865G(dev))
1208 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1209 else
1210 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1211
1212 I915_STATE_WARN(cur_state != state,
1213 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214 pipe_name(pipe), state_string(state), state_string(cur_state));
1215 }
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1221 {
1222 int reg;
1223 u32 val;
1224 bool cur_state;
1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 pipe);
1227
1228 /* if we need the pipe quirk it must be always on */
1229 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1231 state = true;
1232
1233 if (!intel_display_power_is_enabled(dev_priv,
1234 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1235 cur_state = false;
1236 } else {
1237 reg = PIPECONF(cpu_transcoder);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & PIPECONF_ENABLE);
1240 }
1241
1242 I915_STATE_WARN(cur_state != state,
1243 "pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248 enum plane plane, bool state)
1249 {
1250 int reg;
1251 u32 val;
1252 bool cur_state;
1253
1254 reg = DSPCNTR(plane);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257 I915_STATE_WARN(cur_state != state,
1258 "plane %c assertion failure (expected %s, current %s)\n",
1259 plane_name(plane), state_string(state), state_string(cur_state));
1260 }
1261
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267 {
1268 struct drm_device *dev = dev_priv->dev;
1269 int reg, i;
1270 u32 val;
1271 int cur_pipe;
1272
1273 /* Primary planes are fixed to pipes on gen4+ */
1274 if (INTEL_INFO(dev)->gen >= 4) {
1275 reg = DSPCNTR(pipe);
1276 val = I915_READ(reg);
1277 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278 "plane %c assertion failure, should be disabled but not\n",
1279 plane_name(pipe));
1280 return;
1281 }
1282
1283 /* Need to check both planes against the pipe */
1284 for_each_pipe(dev_priv, i) {
1285 reg = DSPCNTR(i);
1286 val = I915_READ(reg);
1287 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288 DISPPLANE_SEL_PIPE_SHIFT;
1289 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291 plane_name(i), pipe_name(pipe));
1292 }
1293 }
1294
1295 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe)
1297 {
1298 struct drm_device *dev = dev_priv->dev;
1299 int reg, sprite;
1300 u32 val;
1301
1302 if (INTEL_INFO(dev)->gen >= 9) {
1303 for_each_sprite(pipe, sprite) {
1304 val = I915_READ(PLANE_CTL(pipe, sprite));
1305 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307 sprite, pipe_name(pipe));
1308 }
1309 } else if (IS_VALLEYVIEW(dev)) {
1310 for_each_sprite(pipe, sprite) {
1311 reg = SPCNTR(pipe, sprite);
1312 val = I915_READ(reg);
1313 I915_STATE_WARN(val & SP_ENABLE,
1314 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315 sprite_name(pipe, sprite), pipe_name(pipe));
1316 }
1317 } else if (INTEL_INFO(dev)->gen >= 7) {
1318 reg = SPRCTL(pipe);
1319 val = I915_READ(reg);
1320 I915_STATE_WARN(val & SPRITE_ENABLE,
1321 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322 plane_name(pipe), pipe_name(pipe));
1323 } else if (INTEL_INFO(dev)->gen >= 5) {
1324 reg = DVSCNTR(pipe);
1325 val = I915_READ(reg);
1326 I915_STATE_WARN(val & DVS_ENABLE,
1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328 plane_name(pipe), pipe_name(pipe));
1329 }
1330 }
1331
1332 static void assert_vblank_disabled(struct drm_crtc *crtc)
1333 {
1334 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335 drm_crtc_vblank_put(crtc);
1336 }
1337
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1339 {
1340 u32 val;
1341 bool enabled;
1342
1343 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1344
1345 val = I915_READ(PCH_DREF_CONTROL);
1346 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347 DREF_SUPERSPREAD_SOURCE_MASK));
1348 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1349 }
1350
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe)
1353 {
1354 int reg;
1355 u32 val;
1356 bool enabled;
1357
1358 reg = PCH_TRANSCONF(pipe);
1359 val = I915_READ(reg);
1360 enabled = !!(val & TRANS_ENABLE);
1361 I915_STATE_WARN(enabled,
1362 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363 pipe_name(pipe));
1364 }
1365
1366 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367 enum pipe pipe, u32 port_sel, u32 val)
1368 {
1369 if ((val & DP_PORT_EN) == 0)
1370 return false;
1371
1372 if (HAS_PCH_CPT(dev_priv->dev)) {
1373 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376 return false;
1377 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379 return false;
1380 } else {
1381 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382 return false;
1383 }
1384 return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, u32 val)
1389 {
1390 if ((val & SDVO_ENABLE) == 0)
1391 return false;
1392
1393 if (HAS_PCH_CPT(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395 return false;
1396 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398 return false;
1399 } else {
1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401 return false;
1402 }
1403 return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, u32 val)
1408 {
1409 if ((val & LVDS_PORT_EN) == 0)
1410 return false;
1411
1412 if (HAS_PCH_CPT(dev_priv->dev)) {
1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414 return false;
1415 } else {
1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417 return false;
1418 }
1419 return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe, u32 val)
1424 {
1425 if ((val & ADPA_DAC_ENABLE) == 0)
1426 return false;
1427 if (HAS_PCH_CPT(dev_priv->dev)) {
1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429 return false;
1430 } else {
1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432 return false;
1433 }
1434 return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, int reg, u32 port_sel)
1439 {
1440 u32 val = I915_READ(reg);
1441 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443 reg, pipe_name(pipe));
1444
1445 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446 && (val & DP_PIPEB_SELECT),
1447 "IBX PCH dp port still using transcoder B\n");
1448 }
1449
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, int reg)
1452 {
1453 u32 val = I915_READ(reg);
1454 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456 reg, pipe_name(pipe));
1457
1458 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459 && (val & SDVO_PIPE_B_SELECT),
1460 "IBX PCH hdmi port still using transcoder B\n");
1461 }
1462
1463 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465 {
1466 int reg;
1467 u32 val;
1468
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473 reg = PCH_ADPA;
1474 val = I915_READ(reg);
1475 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476 "PCH VGA enabled on transcoder %c, should be disabled\n",
1477 pipe_name(pipe));
1478
1479 reg = PCH_LVDS;
1480 val = I915_READ(reg);
1481 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1483 pipe_name(pipe));
1484
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1488 }
1489
1490 static void intel_init_dpio(struct drm_device *dev)
1491 {
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493
1494 if (!IS_VALLEYVIEW(dev))
1495 return;
1496
1497 /*
1498 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499 * CHV x1 PHY (DP/HDMI D)
1500 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501 */
1502 if (IS_CHERRYVIEW(dev)) {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1505 } else {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507 }
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511 const struct intel_crtc_state *pipe_config)
1512 {
1513 struct drm_device *dev = crtc->base.dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 int reg = DPLL(crtc->pipe);
1516 u32 dpll = pipe_config->dpll_hw_state.dpll;
1517
1518 assert_pipe_disabled(dev_priv, crtc->pipe);
1519
1520 /* No really, not for ILK+ */
1521 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1522
1523 /* PLL is protected by panel, make sure we can write it */
1524 if (IS_MOBILE(dev_priv->dev))
1525 assert_panel_unlocked(dev_priv, crtc->pipe);
1526
1527 I915_WRITE(reg, dpll);
1528 POSTING_READ(reg);
1529 udelay(150);
1530
1531 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1533
1534 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535 POSTING_READ(DPLL_MD(crtc->pipe));
1536
1537 /* We do this three times for luck */
1538 I915_WRITE(reg, dpll);
1539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544 I915_WRITE(reg, dpll);
1545 POSTING_READ(reg);
1546 udelay(150); /* wait for warmup */
1547 }
1548
1549 static void chv_enable_pll(struct intel_crtc *crtc,
1550 const struct intel_crtc_state *pipe_config)
1551 {
1552 struct drm_device *dev = crtc->base.dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 int pipe = crtc->pipe;
1555 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1556 u32 tmp;
1557
1558 assert_pipe_disabled(dev_priv, crtc->pipe);
1559
1560 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1561
1562 mutex_lock(&dev_priv->dpio_lock);
1563
1564 /* Enable back the 10bit clock to display controller */
1565 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566 tmp |= DPIO_DCLKP_EN;
1567 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1568
1569 /*
1570 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1571 */
1572 udelay(1);
1573
1574 /* Enable PLL */
1575 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1576
1577 /* Check PLL is locked */
1578 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579 DRM_ERROR("PLL %d failed to lock\n", pipe);
1580
1581 /* not sure when this should be written */
1582 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583 POSTING_READ(DPLL_MD(pipe));
1584
1585 mutex_unlock(&dev_priv->dpio_lock);
1586 }
1587
1588 static int intel_num_dvo_pipes(struct drm_device *dev)
1589 {
1590 struct intel_crtc *crtc;
1591 int count = 0;
1592
1593 for_each_intel_crtc(dev, crtc)
1594 count += crtc->active &&
1595 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1596
1597 return count;
1598 }
1599
1600 static void i9xx_enable_pll(struct intel_crtc *crtc)
1601 {
1602 struct drm_device *dev = crtc->base.dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 int reg = DPLL(crtc->pipe);
1605 u32 dpll = crtc->config->dpll_hw_state.dpll;
1606
1607 assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609 /* No really, not for ILK+ */
1610 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1611
1612 /* PLL is protected by panel, make sure we can write it */
1613 if (IS_MOBILE(dev) && !IS_I830(dev))
1614 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616 /* Enable DVO 2x clock on both PLLs if necessary */
1617 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1618 /*
1619 * It appears to be important that we don't enable this
1620 * for the current pipe before otherwise configuring the
1621 * PLL. No idea how this should be handled if multiple
1622 * DVO outputs are enabled simultaneosly.
1623 */
1624 dpll |= DPLL_DVO_2X_MODE;
1625 I915_WRITE(DPLL(!crtc->pipe),
1626 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1627 }
1628
1629 /* Wait for the clocks to stabilize. */
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (INTEL_INFO(dev)->gen >= 4) {
1634 I915_WRITE(DPLL_MD(crtc->pipe),
1635 crtc->config->dpll_hw_state.dpll_md);
1636 } else {
1637 /* The pixel multiplier can only be updated once the
1638 * DPLL is enabled and the clocks are stable.
1639 *
1640 * So write it again.
1641 */
1642 I915_WRITE(reg, dpll);
1643 }
1644
1645 /* We do this three times for luck */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 I915_WRITE(reg, dpll);
1653 POSTING_READ(reg);
1654 udelay(150); /* wait for warmup */
1655 }
1656
1657 /**
1658 * i9xx_disable_pll - disable a PLL
1659 * @dev_priv: i915 private structure
1660 * @pipe: pipe PLL to disable
1661 *
1662 * Disable the PLL for @pipe, making sure the pipe is off first.
1663 *
1664 * Note! This is for pre-ILK only.
1665 */
1666 static void i9xx_disable_pll(struct intel_crtc *crtc)
1667 {
1668 struct drm_device *dev = crtc->base.dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 enum pipe pipe = crtc->pipe;
1671
1672 /* Disable DVO 2x clock on both PLLs if necessary */
1673 if (IS_I830(dev) &&
1674 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675 intel_num_dvo_pipes(dev) == 1) {
1676 I915_WRITE(DPLL(PIPE_B),
1677 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678 I915_WRITE(DPLL(PIPE_A),
1679 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1680 }
1681
1682 /* Don't disable pipe or pipe PLLs if needed */
1683 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1685 return;
1686
1687 /* Make sure the pipe isn't still relying on us */
1688 assert_pipe_disabled(dev_priv, pipe);
1689
1690 I915_WRITE(DPLL(pipe), 0);
1691 POSTING_READ(DPLL(pipe));
1692 }
1693
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696 u32 val = 0;
1697
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1700
1701 /*
1702 * Leave integrated clock source and reference clock enabled for pipe B.
1703 * The latter is needed for VGA hotplug / manual detection.
1704 */
1705 if (pipe == PIPE_B)
1706 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707 I915_WRITE(DPLL(pipe), val);
1708 POSTING_READ(DPLL(pipe));
1709
1710 }
1711
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1715 u32 val;
1716
1717 /* Make sure the pipe isn't still relying on us */
1718 assert_pipe_disabled(dev_priv, pipe);
1719
1720 /* Set PLL en = 0 */
1721 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1722 if (pipe != PIPE_A)
1723 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1726
1727 mutex_lock(&dev_priv->dpio_lock);
1728
1729 /* Disable 10bit clock to display controller */
1730 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731 val &= ~DPIO_DCLKP_EN;
1732 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
1734 /* disable left/right clock distribution */
1735 if (pipe != PIPE_B) {
1736 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739 } else {
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743 }
1744
1745 mutex_unlock(&dev_priv->dpio_lock);
1746 }
1747
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749 struct intel_digital_port *dport)
1750 {
1751 u32 port_mask;
1752 int dpll_reg;
1753
1754 switch (dport->port) {
1755 case PORT_B:
1756 port_mask = DPLL_PORTB_READY_MASK;
1757 dpll_reg = DPLL(0);
1758 break;
1759 case PORT_C:
1760 port_mask = DPLL_PORTC_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 break;
1763 case PORT_D:
1764 port_mask = DPLL_PORTD_READY_MASK;
1765 dpll_reg = DPIO_PHY_STATUS;
1766 break;
1767 default:
1768 BUG();
1769 }
1770
1771 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773 port_name(dport->port), I915_READ(dpll_reg));
1774 }
1775
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777 {
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782 if (WARN_ON(pll == NULL))
1783 return;
1784
1785 WARN_ON(!pll->config.crtc_mask);
1786 if (pll->active == 0) {
1787 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788 WARN_ON(pll->on);
1789 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791 pll->mode_set(dev_priv, pll);
1792 }
1793 }
1794
1795 /**
1796 * intel_enable_shared_dpll - enable PCH PLL
1797 * @dev_priv: i915 private structure
1798 * @pipe: pipe PLL to enable
1799 *
1800 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801 * drives the transcoder clock.
1802 */
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1804 {
1805 struct drm_device *dev = crtc->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809 if (WARN_ON(pll == NULL))
1810 return;
1811
1812 if (WARN_ON(pll->config.crtc_mask == 0))
1813 return;
1814
1815 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816 pll->name, pll->active, pll->on,
1817 crtc->base.base.id);
1818
1819 if (pll->active++) {
1820 WARN_ON(!pll->on);
1821 assert_shared_dpll_enabled(dev_priv, pll);
1822 return;
1823 }
1824 WARN_ON(pll->on);
1825
1826 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
1828 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829 pll->enable(dev_priv, pll);
1830 pll->on = true;
1831 }
1832
1833 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1834 {
1835 struct drm_device *dev = crtc->base.dev;
1836 struct drm_i915_private *dev_priv = dev->dev_private;
1837 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839 /* PCH only available on ILK+ */
1840 BUG_ON(INTEL_INFO(dev)->gen < 5);
1841 if (WARN_ON(pll == NULL))
1842 return;
1843
1844 if (WARN_ON(pll->config.crtc_mask == 0))
1845 return;
1846
1847 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848 pll->name, pll->active, pll->on,
1849 crtc->base.base.id);
1850
1851 if (WARN_ON(pll->active == 0)) {
1852 assert_shared_dpll_disabled(dev_priv, pll);
1853 return;
1854 }
1855
1856 assert_shared_dpll_enabled(dev_priv, pll);
1857 WARN_ON(!pll->on);
1858 if (--pll->active)
1859 return;
1860
1861 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862 pll->disable(dev_priv, pll);
1863 pll->on = false;
1864
1865 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1866 }
1867
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869 enum pipe pipe)
1870 {
1871 struct drm_device *dev = dev_priv->dev;
1872 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874 uint32_t reg, val, pipeconf_val;
1875
1876 /* PCH only available on ILK+ */
1877 BUG_ON(!HAS_PCH_SPLIT(dev));
1878
1879 /* Make sure PCH DPLL is enabled */
1880 assert_shared_dpll_enabled(dev_priv,
1881 intel_crtc_to_shared_dpll(intel_crtc));
1882
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, pipe);
1885 assert_fdi_rx_enabled(dev_priv, pipe);
1886
1887 if (HAS_PCH_CPT(dev)) {
1888 /* Workaround: Set the timing override bit before enabling the
1889 * pch transcoder. */
1890 reg = TRANS_CHICKEN2(pipe);
1891 val = I915_READ(reg);
1892 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893 I915_WRITE(reg, val);
1894 }
1895
1896 reg = PCH_TRANSCONF(pipe);
1897 val = I915_READ(reg);
1898 pipeconf_val = I915_READ(PIPECONF(pipe));
1899
1900 if (HAS_PCH_IBX(dev_priv->dev)) {
1901 /*
1902 * make the BPC in transcoder be consistent with
1903 * that in pipeconf reg.
1904 */
1905 val &= ~PIPECONF_BPC_MASK;
1906 val |= pipeconf_val & PIPECONF_BPC_MASK;
1907 }
1908
1909 val &= ~TRANS_INTERLACE_MASK;
1910 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911 if (HAS_PCH_IBX(dev_priv->dev) &&
1912 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913 val |= TRANS_LEGACY_INTERLACED_ILK;
1914 else
1915 val |= TRANS_INTERLACED;
1916 else
1917 val |= TRANS_PROGRESSIVE;
1918
1919 I915_WRITE(reg, val | TRANS_ENABLE);
1920 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1922 }
1923
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925 enum transcoder cpu_transcoder)
1926 {
1927 u32 val, pipeconf_val;
1928
1929 /* PCH only available on ILK+ */
1930 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1931
1932 /* FDI must be feeding us bits for PCH ports */
1933 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1935
1936 /* Workaround: set timing override bit. */
1937 val = I915_READ(_TRANSA_CHICKEN2);
1938 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939 I915_WRITE(_TRANSA_CHICKEN2, val);
1940
1941 val = TRANS_ENABLE;
1942 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1943
1944 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945 PIPECONF_INTERLACED_ILK)
1946 val |= TRANS_INTERLACED;
1947 else
1948 val |= TRANS_PROGRESSIVE;
1949
1950 I915_WRITE(LPT_TRANSCONF, val);
1951 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952 DRM_ERROR("Failed to enable PCH transcoder\n");
1953 }
1954
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956 enum pipe pipe)
1957 {
1958 struct drm_device *dev = dev_priv->dev;
1959 uint32_t reg, val;
1960
1961 /* FDI relies on the transcoder */
1962 assert_fdi_tx_disabled(dev_priv, pipe);
1963 assert_fdi_rx_disabled(dev_priv, pipe);
1964
1965 /* Ports must be off as well */
1966 assert_pch_ports_disabled(dev_priv, pipe);
1967
1968 reg = PCH_TRANSCONF(pipe);
1969 val = I915_READ(reg);
1970 val &= ~TRANS_ENABLE;
1971 I915_WRITE(reg, val);
1972 /* wait for PCH transcoder off, transcoder state */
1973 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1975
1976 if (!HAS_PCH_IBX(dev)) {
1977 /* Workaround: Clear the timing override chicken bit again. */
1978 reg = TRANS_CHICKEN2(pipe);
1979 val = I915_READ(reg);
1980 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981 I915_WRITE(reg, val);
1982 }
1983 }
1984
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 {
1987 u32 val;
1988
1989 val = I915_READ(LPT_TRANSCONF);
1990 val &= ~TRANS_ENABLE;
1991 I915_WRITE(LPT_TRANSCONF, val);
1992 /* wait for PCH transcoder off, transcoder state */
1993 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994 DRM_ERROR("Failed to disable PCH transcoder\n");
1995
1996 /* Workaround: clear timing override bit. */
1997 val = I915_READ(_TRANSA_CHICKEN2);
1998 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999 I915_WRITE(_TRANSA_CHICKEN2, val);
2000 }
2001
2002 /**
2003 * intel_enable_pipe - enable a pipe, asserting requirements
2004 * @crtc: crtc responsible for the pipe
2005 *
2006 * Enable @crtc's pipe, making sure that various hardware specific requirements
2007 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008 */
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2010 {
2011 struct drm_device *dev = crtc->base.dev;
2012 struct drm_i915_private *dev_priv = dev->dev_private;
2013 enum pipe pipe = crtc->pipe;
2014 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015 pipe);
2016 enum pipe pch_transcoder;
2017 int reg;
2018 u32 val;
2019
2020 assert_planes_disabled(dev_priv, pipe);
2021 assert_cursor_disabled(dev_priv, pipe);
2022 assert_sprites_disabled(dev_priv, pipe);
2023
2024 if (HAS_PCH_LPT(dev_priv->dev))
2025 pch_transcoder = TRANSCODER_A;
2026 else
2027 pch_transcoder = pipe;
2028
2029 /*
2030 * A pipe without a PLL won't actually be able to drive bits from
2031 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2032 * need the check.
2033 */
2034 if (!HAS_PCH_SPLIT(dev_priv->dev))
2035 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036 assert_dsi_pll_enabled(dev_priv);
2037 else
2038 assert_pll_enabled(dev_priv, pipe);
2039 else {
2040 if (crtc->config->has_pch_encoder) {
2041 /* if driving the PCH, we need FDI enabled */
2042 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043 assert_fdi_tx_pll_enabled(dev_priv,
2044 (enum pipe) cpu_transcoder);
2045 }
2046 /* FIXME: assert CPU port conditions for SNB+ */
2047 }
2048
2049 reg = PIPECONF(cpu_transcoder);
2050 val = I915_READ(reg);
2051 if (val & PIPECONF_ENABLE) {
2052 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054 return;
2055 }
2056
2057 I915_WRITE(reg, val | PIPECONF_ENABLE);
2058 POSTING_READ(reg);
2059 }
2060
2061 /**
2062 * intel_disable_pipe - disable a pipe, asserting requirements
2063 * @crtc: crtc whose pipes is to be disabled
2064 *
2065 * Disable the pipe of @crtc, making sure that various hardware
2066 * specific requirements are met, if applicable, e.g. plane
2067 * disabled, panel fitter off, etc.
2068 *
2069 * Will wait until the pipe has shut down before returning.
2070 */
2071 static void intel_disable_pipe(struct intel_crtc *crtc)
2072 {
2073 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075 enum pipe pipe = crtc->pipe;
2076 int reg;
2077 u32 val;
2078
2079 /*
2080 * Make sure planes won't keep trying to pump pixels to us,
2081 * or we might hang the display.
2082 */
2083 assert_planes_disabled(dev_priv, pipe);
2084 assert_cursor_disabled(dev_priv, pipe);
2085 assert_sprites_disabled(dev_priv, pipe);
2086
2087 reg = PIPECONF(cpu_transcoder);
2088 val = I915_READ(reg);
2089 if ((val & PIPECONF_ENABLE) == 0)
2090 return;
2091
2092 /*
2093 * Double wide has implications for planes
2094 * so best keep it disabled when not needed.
2095 */
2096 if (crtc->config->double_wide)
2097 val &= ~PIPECONF_DOUBLE_WIDE;
2098
2099 /* Don't disable pipe or pipe PLLs if needed */
2100 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102 val &= ~PIPECONF_ENABLE;
2103
2104 I915_WRITE(reg, val);
2105 if ((val & PIPECONF_ENABLE) == 0)
2106 intel_wait_for_pipe_off(crtc);
2107 }
2108
2109 /*
2110 * Plane regs are double buffered, going from enabled->disabled needs a
2111 * trigger in order to latch. The display address reg provides this.
2112 */
2113 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2114 enum plane plane)
2115 {
2116 struct drm_device *dev = dev_priv->dev;
2117 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2118
2119 I915_WRITE(reg, I915_READ(reg));
2120 POSTING_READ(reg);
2121 }
2122
2123 /**
2124 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125 * @plane: plane to be enabled
2126 * @crtc: crtc for the plane
2127 *
2128 * Enable @plane on @crtc, making sure that the pipe is running first.
2129 */
2130 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131 struct drm_crtc *crtc)
2132 {
2133 struct drm_device *dev = plane->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2139
2140 if (intel_crtc->primary_enabled)
2141 return;
2142
2143 intel_crtc->primary_enabled = true;
2144
2145 dev_priv->display.update_primary_plane(crtc, plane->fb,
2146 crtc->x, crtc->y);
2147
2148 /*
2149 * BDW signals flip done immediately if the plane
2150 * is disabled, even if the plane enable is already
2151 * armed to occur at the next vblank :(
2152 */
2153 if (IS_BROADWELL(dev))
2154 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 }
2156
2157 /**
2158 * intel_disable_primary_hw_plane - disable the primary hardware plane
2159 * @plane: plane to be disabled
2160 * @crtc: crtc for the plane
2161 *
2162 * Disable @plane on @crtc, making sure that the pipe is running first.
2163 */
2164 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165 struct drm_crtc *crtc)
2166 {
2167 struct drm_device *dev = plane->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170
2171 if (WARN_ON(!intel_crtc->active))
2172 return;
2173
2174 if (!intel_crtc->primary_enabled)
2175 return;
2176
2177 intel_crtc->primary_enabled = false;
2178
2179 dev_priv->display.update_primary_plane(crtc, plane->fb,
2180 crtc->x, crtc->y);
2181 }
2182
2183 static bool need_vtd_wa(struct drm_device *dev)
2184 {
2185 #ifdef CONFIG_INTEL_IOMMU
2186 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2187 return true;
2188 #endif
2189 return false;
2190 }
2191
2192 int
2193 intel_fb_align_height(struct drm_device *dev, int height,
2194 uint32_t pixel_format,
2195 uint64_t fb_format_modifier)
2196 {
2197 int tile_height;
2198
2199 tile_height = fb_format_modifier == I915_FORMAT_MOD_X_TILED ?
2200 (IS_GEN2(dev) ? 16 : 8) : 1;
2201
2202 return ALIGN(height, tile_height);
2203 }
2204
2205 int
2206 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2207 struct drm_framebuffer *fb,
2208 struct intel_engine_cs *pipelined)
2209 {
2210 struct drm_device *dev = fb->dev;
2211 struct drm_i915_private *dev_priv = dev->dev_private;
2212 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2213 u32 alignment;
2214 int ret;
2215
2216 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2217
2218 switch (fb->modifier[0]) {
2219 case DRM_FORMAT_MOD_NONE:
2220 if (INTEL_INFO(dev)->gen >= 9)
2221 alignment = 256 * 1024;
2222 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2223 alignment = 128 * 1024;
2224 else if (INTEL_INFO(dev)->gen >= 4)
2225 alignment = 4 * 1024;
2226 else
2227 alignment = 64 * 1024;
2228 break;
2229 case I915_FORMAT_MOD_X_TILED:
2230 if (INTEL_INFO(dev)->gen >= 9)
2231 alignment = 256 * 1024;
2232 else {
2233 /* pin() will align the object as required by fence */
2234 alignment = 0;
2235 }
2236 break;
2237 case I915_FORMAT_MOD_Y_TILED:
2238 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2239 return -EINVAL;
2240 default:
2241 MISSING_CASE(fb->modifier[0]);
2242 return -EINVAL;
2243 }
2244
2245 /* Note that the w/a also requires 64 PTE of padding following the
2246 * bo. We currently fill all unused PTE with the shadow page and so
2247 * we should always have valid PTE following the scanout preventing
2248 * the VT-d warning.
2249 */
2250 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2251 alignment = 256 * 1024;
2252
2253 /*
2254 * Global gtt pte registers are special registers which actually forward
2255 * writes to a chunk of system memory. Which means that there is no risk
2256 * that the register values disappear as soon as we call
2257 * intel_runtime_pm_put(), so it is correct to wrap only the
2258 * pin/unpin/fence and not more.
2259 */
2260 intel_runtime_pm_get(dev_priv);
2261
2262 dev_priv->mm.interruptible = false;
2263 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2264 if (ret)
2265 goto err_interruptible;
2266
2267 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2268 * fence, whereas 965+ only requires a fence if using
2269 * framebuffer compression. For simplicity, we always install
2270 * a fence as the cost is not that onerous.
2271 */
2272 ret = i915_gem_object_get_fence(obj);
2273 if (ret)
2274 goto err_unpin;
2275
2276 i915_gem_object_pin_fence(obj);
2277
2278 dev_priv->mm.interruptible = true;
2279 intel_runtime_pm_put(dev_priv);
2280 return 0;
2281
2282 err_unpin:
2283 i915_gem_object_unpin_from_display_plane(obj);
2284 err_interruptible:
2285 dev_priv->mm.interruptible = true;
2286 intel_runtime_pm_put(dev_priv);
2287 return ret;
2288 }
2289
2290 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2291 {
2292 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2293
2294 i915_gem_object_unpin_fence(obj);
2295 i915_gem_object_unpin_from_display_plane(obj);
2296 }
2297
2298 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2299 * is assumed to be a power-of-two. */
2300 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2301 unsigned int tiling_mode,
2302 unsigned int cpp,
2303 unsigned int pitch)
2304 {
2305 if (tiling_mode != I915_TILING_NONE) {
2306 unsigned int tile_rows, tiles;
2307
2308 tile_rows = *y / 8;
2309 *y %= 8;
2310
2311 tiles = *x / (512/cpp);
2312 *x %= 512/cpp;
2313
2314 return tile_rows * pitch * 8 + tiles * 4096;
2315 } else {
2316 unsigned int offset;
2317
2318 offset = *y * pitch + *x * cpp;
2319 *y = 0;
2320 *x = (offset & 4095) / cpp;
2321 return offset & -4096;
2322 }
2323 }
2324
2325 static int i9xx_format_to_fourcc(int format)
2326 {
2327 switch (format) {
2328 case DISPPLANE_8BPP:
2329 return DRM_FORMAT_C8;
2330 case DISPPLANE_BGRX555:
2331 return DRM_FORMAT_XRGB1555;
2332 case DISPPLANE_BGRX565:
2333 return DRM_FORMAT_RGB565;
2334 default:
2335 case DISPPLANE_BGRX888:
2336 return DRM_FORMAT_XRGB8888;
2337 case DISPPLANE_RGBX888:
2338 return DRM_FORMAT_XBGR8888;
2339 case DISPPLANE_BGRX101010:
2340 return DRM_FORMAT_XRGB2101010;
2341 case DISPPLANE_RGBX101010:
2342 return DRM_FORMAT_XBGR2101010;
2343 }
2344 }
2345
2346 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2347 {
2348 switch (format) {
2349 case PLANE_CTL_FORMAT_RGB_565:
2350 return DRM_FORMAT_RGB565;
2351 default:
2352 case PLANE_CTL_FORMAT_XRGB_8888:
2353 if (rgb_order) {
2354 if (alpha)
2355 return DRM_FORMAT_ABGR8888;
2356 else
2357 return DRM_FORMAT_XBGR8888;
2358 } else {
2359 if (alpha)
2360 return DRM_FORMAT_ARGB8888;
2361 else
2362 return DRM_FORMAT_XRGB8888;
2363 }
2364 case PLANE_CTL_FORMAT_XRGB_2101010:
2365 if (rgb_order)
2366 return DRM_FORMAT_XBGR2101010;
2367 else
2368 return DRM_FORMAT_XRGB2101010;
2369 }
2370 }
2371
2372 static bool
2373 intel_alloc_plane_obj(struct intel_crtc *crtc,
2374 struct intel_initial_plane_config *plane_config)
2375 {
2376 struct drm_device *dev = crtc->base.dev;
2377 struct drm_i915_gem_object *obj = NULL;
2378 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2379 struct drm_framebuffer *fb = &plane_config->fb->base;
2380 u32 base = plane_config->base;
2381
2382 if (plane_config->size == 0)
2383 return false;
2384
2385 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2386 plane_config->size);
2387 if (!obj)
2388 return false;
2389
2390 obj->tiling_mode = plane_config->tiling;
2391 if (obj->tiling_mode == I915_TILING_X)
2392 obj->stride = fb->pitches[0];
2393
2394 mode_cmd.pixel_format = fb->pixel_format;
2395 mode_cmd.width = fb->width;
2396 mode_cmd.height = fb->height;
2397 mode_cmd.pitches[0] = fb->pitches[0];
2398 mode_cmd.modifier[0] = fb->modifier[0];
2399 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2400
2401 mutex_lock(&dev->struct_mutex);
2402
2403 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2404 &mode_cmd, obj)) {
2405 DRM_DEBUG_KMS("intel fb init failed\n");
2406 goto out_unref_obj;
2407 }
2408
2409 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2410 mutex_unlock(&dev->struct_mutex);
2411
2412 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2413 return true;
2414
2415 out_unref_obj:
2416 drm_gem_object_unreference(&obj->base);
2417 mutex_unlock(&dev->struct_mutex);
2418 return false;
2419 }
2420
2421 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2422 static void
2423 update_state_fb(struct drm_plane *plane)
2424 {
2425 if (plane->fb == plane->state->fb)
2426 return;
2427
2428 if (plane->state->fb)
2429 drm_framebuffer_unreference(plane->state->fb);
2430 plane->state->fb = plane->fb;
2431 if (plane->state->fb)
2432 drm_framebuffer_reference(plane->state->fb);
2433 }
2434
2435 static void
2436 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2437 struct intel_initial_plane_config *plane_config)
2438 {
2439 struct drm_device *dev = intel_crtc->base.dev;
2440 struct drm_i915_private *dev_priv = dev->dev_private;
2441 struct drm_crtc *c;
2442 struct intel_crtc *i;
2443 struct drm_i915_gem_object *obj;
2444
2445 if (!plane_config->fb)
2446 return;
2447
2448 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2449 struct drm_plane *primary = intel_crtc->base.primary;
2450
2451 primary->fb = &plane_config->fb->base;
2452 primary->state->crtc = &intel_crtc->base;
2453 update_state_fb(primary);
2454
2455 return;
2456 }
2457
2458 kfree(plane_config->fb);
2459
2460 /*
2461 * Failed to alloc the obj, check to see if we should share
2462 * an fb with another CRTC instead
2463 */
2464 for_each_crtc(dev, c) {
2465 i = to_intel_crtc(c);
2466
2467 if (c == &intel_crtc->base)
2468 continue;
2469
2470 if (!i->active)
2471 continue;
2472
2473 obj = intel_fb_obj(c->primary->fb);
2474 if (obj == NULL)
2475 continue;
2476
2477 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2478 struct drm_plane *primary = intel_crtc->base.primary;
2479
2480 if (obj->tiling_mode != I915_TILING_NONE)
2481 dev_priv->preserve_bios_swizzle = true;
2482
2483 drm_framebuffer_reference(c->primary->fb);
2484 primary->fb = c->primary->fb;
2485 primary->state->crtc = &intel_crtc->base;
2486 update_state_fb(intel_crtc->base.primary);
2487 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2488 break;
2489 }
2490 }
2491
2492 }
2493
2494 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2495 struct drm_framebuffer *fb,
2496 int x, int y)
2497 {
2498 struct drm_device *dev = crtc->dev;
2499 struct drm_i915_private *dev_priv = dev->dev_private;
2500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2501 struct drm_i915_gem_object *obj;
2502 int plane = intel_crtc->plane;
2503 unsigned long linear_offset;
2504 u32 dspcntr;
2505 u32 reg = DSPCNTR(plane);
2506 int pixel_size;
2507
2508 if (!intel_crtc->primary_enabled) {
2509 I915_WRITE(reg, 0);
2510 if (INTEL_INFO(dev)->gen >= 4)
2511 I915_WRITE(DSPSURF(plane), 0);
2512 else
2513 I915_WRITE(DSPADDR(plane), 0);
2514 POSTING_READ(reg);
2515 return;
2516 }
2517
2518 obj = intel_fb_obj(fb);
2519 if (WARN_ON(obj == NULL))
2520 return;
2521
2522 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2523
2524 dspcntr = DISPPLANE_GAMMA_ENABLE;
2525
2526 dspcntr |= DISPLAY_PLANE_ENABLE;
2527
2528 if (INTEL_INFO(dev)->gen < 4) {
2529 if (intel_crtc->pipe == PIPE_B)
2530 dspcntr |= DISPPLANE_SEL_PIPE_B;
2531
2532 /* pipesrc and dspsize control the size that is scaled from,
2533 * which should always be the user's requested size.
2534 */
2535 I915_WRITE(DSPSIZE(plane),
2536 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2537 (intel_crtc->config->pipe_src_w - 1));
2538 I915_WRITE(DSPPOS(plane), 0);
2539 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2540 I915_WRITE(PRIMSIZE(plane),
2541 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2542 (intel_crtc->config->pipe_src_w - 1));
2543 I915_WRITE(PRIMPOS(plane), 0);
2544 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2545 }
2546
2547 switch (fb->pixel_format) {
2548 case DRM_FORMAT_C8:
2549 dspcntr |= DISPPLANE_8BPP;
2550 break;
2551 case DRM_FORMAT_XRGB1555:
2552 case DRM_FORMAT_ARGB1555:
2553 dspcntr |= DISPPLANE_BGRX555;
2554 break;
2555 case DRM_FORMAT_RGB565:
2556 dspcntr |= DISPPLANE_BGRX565;
2557 break;
2558 case DRM_FORMAT_XRGB8888:
2559 case DRM_FORMAT_ARGB8888:
2560 dspcntr |= DISPPLANE_BGRX888;
2561 break;
2562 case DRM_FORMAT_XBGR8888:
2563 case DRM_FORMAT_ABGR8888:
2564 dspcntr |= DISPPLANE_RGBX888;
2565 break;
2566 case DRM_FORMAT_XRGB2101010:
2567 case DRM_FORMAT_ARGB2101010:
2568 dspcntr |= DISPPLANE_BGRX101010;
2569 break;
2570 case DRM_FORMAT_XBGR2101010:
2571 case DRM_FORMAT_ABGR2101010:
2572 dspcntr |= DISPPLANE_RGBX101010;
2573 break;
2574 default:
2575 BUG();
2576 }
2577
2578 if (INTEL_INFO(dev)->gen >= 4 &&
2579 obj->tiling_mode != I915_TILING_NONE)
2580 dspcntr |= DISPPLANE_TILED;
2581
2582 if (IS_G4X(dev))
2583 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2584
2585 linear_offset = y * fb->pitches[0] + x * pixel_size;
2586
2587 if (INTEL_INFO(dev)->gen >= 4) {
2588 intel_crtc->dspaddr_offset =
2589 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2590 pixel_size,
2591 fb->pitches[0]);
2592 linear_offset -= intel_crtc->dspaddr_offset;
2593 } else {
2594 intel_crtc->dspaddr_offset = linear_offset;
2595 }
2596
2597 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2598 dspcntr |= DISPPLANE_ROTATE_180;
2599
2600 x += (intel_crtc->config->pipe_src_w - 1);
2601 y += (intel_crtc->config->pipe_src_h - 1);
2602
2603 /* Finding the last pixel of the last line of the display
2604 data and adding to linear_offset*/
2605 linear_offset +=
2606 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2607 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2608 }
2609
2610 I915_WRITE(reg, dspcntr);
2611
2612 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2613 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2614 fb->pitches[0]);
2615 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2616 if (INTEL_INFO(dev)->gen >= 4) {
2617 I915_WRITE(DSPSURF(plane),
2618 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2619 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2620 I915_WRITE(DSPLINOFF(plane), linear_offset);
2621 } else
2622 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2623 POSTING_READ(reg);
2624 }
2625
2626 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2627 struct drm_framebuffer *fb,
2628 int x, int y)
2629 {
2630 struct drm_device *dev = crtc->dev;
2631 struct drm_i915_private *dev_priv = dev->dev_private;
2632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2633 struct drm_i915_gem_object *obj;
2634 int plane = intel_crtc->plane;
2635 unsigned long linear_offset;
2636 u32 dspcntr;
2637 u32 reg = DSPCNTR(plane);
2638 int pixel_size;
2639
2640 if (!intel_crtc->primary_enabled) {
2641 I915_WRITE(reg, 0);
2642 I915_WRITE(DSPSURF(plane), 0);
2643 POSTING_READ(reg);
2644 return;
2645 }
2646
2647 obj = intel_fb_obj(fb);
2648 if (WARN_ON(obj == NULL))
2649 return;
2650
2651 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2652
2653 dspcntr = DISPPLANE_GAMMA_ENABLE;
2654
2655 dspcntr |= DISPLAY_PLANE_ENABLE;
2656
2657 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2658 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2659
2660 switch (fb->pixel_format) {
2661 case DRM_FORMAT_C8:
2662 dspcntr |= DISPPLANE_8BPP;
2663 break;
2664 case DRM_FORMAT_RGB565:
2665 dspcntr |= DISPPLANE_BGRX565;
2666 break;
2667 case DRM_FORMAT_XRGB8888:
2668 case DRM_FORMAT_ARGB8888:
2669 dspcntr |= DISPPLANE_BGRX888;
2670 break;
2671 case DRM_FORMAT_XBGR8888:
2672 case DRM_FORMAT_ABGR8888:
2673 dspcntr |= DISPPLANE_RGBX888;
2674 break;
2675 case DRM_FORMAT_XRGB2101010:
2676 case DRM_FORMAT_ARGB2101010:
2677 dspcntr |= DISPPLANE_BGRX101010;
2678 break;
2679 case DRM_FORMAT_XBGR2101010:
2680 case DRM_FORMAT_ABGR2101010:
2681 dspcntr |= DISPPLANE_RGBX101010;
2682 break;
2683 default:
2684 BUG();
2685 }
2686
2687 if (obj->tiling_mode != I915_TILING_NONE)
2688 dspcntr |= DISPPLANE_TILED;
2689
2690 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2691 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2692
2693 linear_offset = y * fb->pitches[0] + x * pixel_size;
2694 intel_crtc->dspaddr_offset =
2695 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2696 pixel_size,
2697 fb->pitches[0]);
2698 linear_offset -= intel_crtc->dspaddr_offset;
2699 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2700 dspcntr |= DISPPLANE_ROTATE_180;
2701
2702 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2703 x += (intel_crtc->config->pipe_src_w - 1);
2704 y += (intel_crtc->config->pipe_src_h - 1);
2705
2706 /* Finding the last pixel of the last line of the display
2707 data and adding to linear_offset*/
2708 linear_offset +=
2709 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2710 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2711 }
2712 }
2713
2714 I915_WRITE(reg, dspcntr);
2715
2716 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2717 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2718 fb->pitches[0]);
2719 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2720 I915_WRITE(DSPSURF(plane),
2721 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2722 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2723 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2724 } else {
2725 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2726 I915_WRITE(DSPLINOFF(plane), linear_offset);
2727 }
2728 POSTING_READ(reg);
2729 }
2730
2731 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2732 uint32_t pixel_format)
2733 {
2734 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2735
2736 /*
2737 * The stride is either expressed as a multiple of 64 bytes
2738 * chunks for linear buffers or in number of tiles for tiled
2739 * buffers.
2740 */
2741 switch (fb_modifier) {
2742 case DRM_FORMAT_MOD_NONE:
2743 return 64;
2744 case I915_FORMAT_MOD_X_TILED:
2745 if (INTEL_INFO(dev)->gen == 2)
2746 return 128;
2747 return 512;
2748 case I915_FORMAT_MOD_Y_TILED:
2749 /* No need to check for old gens and Y tiling since this is
2750 * about the display engine and those will be blocked before
2751 * we get here.
2752 */
2753 return 128;
2754 case I915_FORMAT_MOD_Yf_TILED:
2755 if (bits_per_pixel == 8)
2756 return 64;
2757 else
2758 return 128;
2759 default:
2760 MISSING_CASE(fb_modifier);
2761 return 64;
2762 }
2763 }
2764
2765 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2766 struct drm_framebuffer *fb,
2767 int x, int y)
2768 {
2769 struct drm_device *dev = crtc->dev;
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2772 struct drm_i915_gem_object *obj;
2773 int pipe = intel_crtc->pipe;
2774 u32 plane_ctl, stride_div;
2775
2776 if (!intel_crtc->primary_enabled) {
2777 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2778 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2779 POSTING_READ(PLANE_CTL(pipe, 0));
2780 return;
2781 }
2782
2783 plane_ctl = PLANE_CTL_ENABLE |
2784 PLANE_CTL_PIPE_GAMMA_ENABLE |
2785 PLANE_CTL_PIPE_CSC_ENABLE;
2786
2787 switch (fb->pixel_format) {
2788 case DRM_FORMAT_RGB565:
2789 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2790 break;
2791 case DRM_FORMAT_XRGB8888:
2792 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2793 break;
2794 case DRM_FORMAT_XBGR8888:
2795 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2796 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2797 break;
2798 case DRM_FORMAT_XRGB2101010:
2799 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2800 break;
2801 case DRM_FORMAT_XBGR2101010:
2802 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2803 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2804 break;
2805 default:
2806 BUG();
2807 }
2808
2809 switch (fb->modifier[0]) {
2810 case DRM_FORMAT_MOD_NONE:
2811 break;
2812 case I915_FORMAT_MOD_X_TILED:
2813 plane_ctl |= PLANE_CTL_TILED_X;
2814 break;
2815 case I915_FORMAT_MOD_Y_TILED:
2816 plane_ctl |= PLANE_CTL_TILED_Y;
2817 break;
2818 case I915_FORMAT_MOD_Yf_TILED:
2819 plane_ctl |= PLANE_CTL_TILED_YF;
2820 break;
2821 default:
2822 MISSING_CASE(fb->modifier[0]);
2823 }
2824
2825 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2826 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2827 plane_ctl |= PLANE_CTL_ROTATE_180;
2828
2829 obj = intel_fb_obj(fb);
2830 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2831 fb->pixel_format);
2832
2833 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2834
2835 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2836 i915_gem_obj_ggtt_offset(obj),
2837 x, y, fb->width, fb->height,
2838 fb->pitches[0]);
2839
2840 I915_WRITE(PLANE_POS(pipe, 0), 0);
2841 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2842 I915_WRITE(PLANE_SIZE(pipe, 0),
2843 (intel_crtc->config->pipe_src_h - 1) << 16 |
2844 (intel_crtc->config->pipe_src_w - 1));
2845 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2846 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2847
2848 POSTING_READ(PLANE_SURF(pipe, 0));
2849 }
2850
2851 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2852 static int
2853 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2854 int x, int y, enum mode_set_atomic state)
2855 {
2856 struct drm_device *dev = crtc->dev;
2857 struct drm_i915_private *dev_priv = dev->dev_private;
2858
2859 if (dev_priv->display.disable_fbc)
2860 dev_priv->display.disable_fbc(dev);
2861
2862 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2863
2864 return 0;
2865 }
2866
2867 static void intel_complete_page_flips(struct drm_device *dev)
2868 {
2869 struct drm_crtc *crtc;
2870
2871 for_each_crtc(dev, crtc) {
2872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2873 enum plane plane = intel_crtc->plane;
2874
2875 intel_prepare_page_flip(dev, plane);
2876 intel_finish_page_flip_plane(dev, plane);
2877 }
2878 }
2879
2880 static void intel_update_primary_planes(struct drm_device *dev)
2881 {
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 struct drm_crtc *crtc;
2884
2885 for_each_crtc(dev, crtc) {
2886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2887
2888 drm_modeset_lock(&crtc->mutex, NULL);
2889 /*
2890 * FIXME: Once we have proper support for primary planes (and
2891 * disabling them without disabling the entire crtc) allow again
2892 * a NULL crtc->primary->fb.
2893 */
2894 if (intel_crtc->active && crtc->primary->fb)
2895 dev_priv->display.update_primary_plane(crtc,
2896 crtc->primary->fb,
2897 crtc->x,
2898 crtc->y);
2899 drm_modeset_unlock(&crtc->mutex);
2900 }
2901 }
2902
2903 void intel_prepare_reset(struct drm_device *dev)
2904 {
2905 struct drm_i915_private *dev_priv = to_i915(dev);
2906 struct intel_crtc *crtc;
2907
2908 /* no reset support for gen2 */
2909 if (IS_GEN2(dev))
2910 return;
2911
2912 /* reset doesn't touch the display */
2913 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2914 return;
2915
2916 drm_modeset_lock_all(dev);
2917
2918 /*
2919 * Disabling the crtcs gracefully seems nicer. Also the
2920 * g33 docs say we should at least disable all the planes.
2921 */
2922 for_each_intel_crtc(dev, crtc) {
2923 if (crtc->active)
2924 dev_priv->display.crtc_disable(&crtc->base);
2925 }
2926 }
2927
2928 void intel_finish_reset(struct drm_device *dev)
2929 {
2930 struct drm_i915_private *dev_priv = to_i915(dev);
2931
2932 /*
2933 * Flips in the rings will be nuked by the reset,
2934 * so complete all pending flips so that user space
2935 * will get its events and not get stuck.
2936 */
2937 intel_complete_page_flips(dev);
2938
2939 /* no reset support for gen2 */
2940 if (IS_GEN2(dev))
2941 return;
2942
2943 /* reset doesn't touch the display */
2944 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2945 /*
2946 * Flips in the rings have been nuked by the reset,
2947 * so update the base address of all primary
2948 * planes to the the last fb to make sure we're
2949 * showing the correct fb after a reset.
2950 */
2951 intel_update_primary_planes(dev);
2952 return;
2953 }
2954
2955 /*
2956 * The display has been reset as well,
2957 * so need a full re-initialization.
2958 */
2959 intel_runtime_pm_disable_interrupts(dev_priv);
2960 intel_runtime_pm_enable_interrupts(dev_priv);
2961
2962 intel_modeset_init_hw(dev);
2963
2964 spin_lock_irq(&dev_priv->irq_lock);
2965 if (dev_priv->display.hpd_irq_setup)
2966 dev_priv->display.hpd_irq_setup(dev);
2967 spin_unlock_irq(&dev_priv->irq_lock);
2968
2969 intel_modeset_setup_hw_state(dev, true);
2970
2971 intel_hpd_init(dev_priv);
2972
2973 drm_modeset_unlock_all(dev);
2974 }
2975
2976 static int
2977 intel_finish_fb(struct drm_framebuffer *old_fb)
2978 {
2979 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2980 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2981 bool was_interruptible = dev_priv->mm.interruptible;
2982 int ret;
2983
2984 /* Big Hammer, we also need to ensure that any pending
2985 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2986 * current scanout is retired before unpinning the old
2987 * framebuffer.
2988 *
2989 * This should only fail upon a hung GPU, in which case we
2990 * can safely continue.
2991 */
2992 dev_priv->mm.interruptible = false;
2993 ret = i915_gem_object_finish_gpu(obj);
2994 dev_priv->mm.interruptible = was_interruptible;
2995
2996 return ret;
2997 }
2998
2999 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3000 {
3001 struct drm_device *dev = crtc->dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3004 bool pending;
3005
3006 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3007 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3008 return false;
3009
3010 spin_lock_irq(&dev->event_lock);
3011 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3012 spin_unlock_irq(&dev->event_lock);
3013
3014 return pending;
3015 }
3016
3017 static void intel_update_pipe_size(struct intel_crtc *crtc)
3018 {
3019 struct drm_device *dev = crtc->base.dev;
3020 struct drm_i915_private *dev_priv = dev->dev_private;
3021 const struct drm_display_mode *adjusted_mode;
3022
3023 if (!i915.fastboot)
3024 return;
3025
3026 /*
3027 * Update pipe size and adjust fitter if needed: the reason for this is
3028 * that in compute_mode_changes we check the native mode (not the pfit
3029 * mode) to see if we can flip rather than do a full mode set. In the
3030 * fastboot case, we'll flip, but if we don't update the pipesrc and
3031 * pfit state, we'll end up with a big fb scanned out into the wrong
3032 * sized surface.
3033 *
3034 * To fix this properly, we need to hoist the checks up into
3035 * compute_mode_changes (or above), check the actual pfit state and
3036 * whether the platform allows pfit disable with pipe active, and only
3037 * then update the pipesrc and pfit state, even on the flip path.
3038 */
3039
3040 adjusted_mode = &crtc->config->base.adjusted_mode;
3041
3042 I915_WRITE(PIPESRC(crtc->pipe),
3043 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3044 (adjusted_mode->crtc_vdisplay - 1));
3045 if (!crtc->config->pch_pfit.enabled &&
3046 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3047 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3048 I915_WRITE(PF_CTL(crtc->pipe), 0);
3049 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3050 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3051 }
3052 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3053 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3054 }
3055
3056 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3057 {
3058 struct drm_device *dev = crtc->dev;
3059 struct drm_i915_private *dev_priv = dev->dev_private;
3060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3061 int pipe = intel_crtc->pipe;
3062 u32 reg, temp;
3063
3064 /* enable normal train */
3065 reg = FDI_TX_CTL(pipe);
3066 temp = I915_READ(reg);
3067 if (IS_IVYBRIDGE(dev)) {
3068 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3069 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3070 } else {
3071 temp &= ~FDI_LINK_TRAIN_NONE;
3072 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3073 }
3074 I915_WRITE(reg, temp);
3075
3076 reg = FDI_RX_CTL(pipe);
3077 temp = I915_READ(reg);
3078 if (HAS_PCH_CPT(dev)) {
3079 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3080 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3081 } else {
3082 temp &= ~FDI_LINK_TRAIN_NONE;
3083 temp |= FDI_LINK_TRAIN_NONE;
3084 }
3085 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3086
3087 /* wait one idle pattern time */
3088 POSTING_READ(reg);
3089 udelay(1000);
3090
3091 /* IVB wants error correction enabled */
3092 if (IS_IVYBRIDGE(dev))
3093 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3094 FDI_FE_ERRC_ENABLE);
3095 }
3096
3097 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3098 {
3099 return crtc->base.state->enable && crtc->active &&
3100 crtc->config->has_pch_encoder;
3101 }
3102
3103 static void ivb_modeset_global_resources(struct drm_device *dev)
3104 {
3105 struct drm_i915_private *dev_priv = dev->dev_private;
3106 struct intel_crtc *pipe_B_crtc =
3107 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3108 struct intel_crtc *pipe_C_crtc =
3109 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3110 uint32_t temp;
3111
3112 /*
3113 * When everything is off disable fdi C so that we could enable fdi B
3114 * with all lanes. Note that we don't care about enabled pipes without
3115 * an enabled pch encoder.
3116 */
3117 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3118 !pipe_has_enabled_pch(pipe_C_crtc)) {
3119 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3120 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3121
3122 temp = I915_READ(SOUTH_CHICKEN1);
3123 temp &= ~FDI_BC_BIFURCATION_SELECT;
3124 DRM_DEBUG_KMS("disabling fdi C rx\n");
3125 I915_WRITE(SOUTH_CHICKEN1, temp);
3126 }
3127 }
3128
3129 /* The FDI link training functions for ILK/Ibexpeak. */
3130 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3131 {
3132 struct drm_device *dev = crtc->dev;
3133 struct drm_i915_private *dev_priv = dev->dev_private;
3134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3135 int pipe = intel_crtc->pipe;
3136 u32 reg, temp, tries;
3137
3138 /* FDI needs bits from pipe first */
3139 assert_pipe_enabled(dev_priv, pipe);
3140
3141 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3142 for train result */
3143 reg = FDI_RX_IMR(pipe);
3144 temp = I915_READ(reg);
3145 temp &= ~FDI_RX_SYMBOL_LOCK;
3146 temp &= ~FDI_RX_BIT_LOCK;
3147 I915_WRITE(reg, temp);
3148 I915_READ(reg);
3149 udelay(150);
3150
3151 /* enable CPU FDI TX and PCH FDI RX */
3152 reg = FDI_TX_CTL(pipe);
3153 temp = I915_READ(reg);
3154 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3155 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3156 temp &= ~FDI_LINK_TRAIN_NONE;
3157 temp |= FDI_LINK_TRAIN_PATTERN_1;
3158 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3159
3160 reg = FDI_RX_CTL(pipe);
3161 temp = I915_READ(reg);
3162 temp &= ~FDI_LINK_TRAIN_NONE;
3163 temp |= FDI_LINK_TRAIN_PATTERN_1;
3164 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3165
3166 POSTING_READ(reg);
3167 udelay(150);
3168
3169 /* Ironlake workaround, enable clock pointer after FDI enable*/
3170 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3171 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3172 FDI_RX_PHASE_SYNC_POINTER_EN);
3173
3174 reg = FDI_RX_IIR(pipe);
3175 for (tries = 0; tries < 5; tries++) {
3176 temp = I915_READ(reg);
3177 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3178
3179 if ((temp & FDI_RX_BIT_LOCK)) {
3180 DRM_DEBUG_KMS("FDI train 1 done.\n");
3181 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3182 break;
3183 }
3184 }
3185 if (tries == 5)
3186 DRM_ERROR("FDI train 1 fail!\n");
3187
3188 /* Train 2 */
3189 reg = FDI_TX_CTL(pipe);
3190 temp = I915_READ(reg);
3191 temp &= ~FDI_LINK_TRAIN_NONE;
3192 temp |= FDI_LINK_TRAIN_PATTERN_2;
3193 I915_WRITE(reg, temp);
3194
3195 reg = FDI_RX_CTL(pipe);
3196 temp = I915_READ(reg);
3197 temp &= ~FDI_LINK_TRAIN_NONE;
3198 temp |= FDI_LINK_TRAIN_PATTERN_2;
3199 I915_WRITE(reg, temp);
3200
3201 POSTING_READ(reg);
3202 udelay(150);
3203
3204 reg = FDI_RX_IIR(pipe);
3205 for (tries = 0; tries < 5; tries++) {
3206 temp = I915_READ(reg);
3207 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3208
3209 if (temp & FDI_RX_SYMBOL_LOCK) {
3210 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3211 DRM_DEBUG_KMS("FDI train 2 done.\n");
3212 break;
3213 }
3214 }
3215 if (tries == 5)
3216 DRM_ERROR("FDI train 2 fail!\n");
3217
3218 DRM_DEBUG_KMS("FDI train done\n");
3219
3220 }
3221
3222 static const int snb_b_fdi_train_param[] = {
3223 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3224 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3225 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3226 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3227 };
3228
3229 /* The FDI link training functions for SNB/Cougarpoint. */
3230 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3231 {
3232 struct drm_device *dev = crtc->dev;
3233 struct drm_i915_private *dev_priv = dev->dev_private;
3234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3235 int pipe = intel_crtc->pipe;
3236 u32 reg, temp, i, retry;
3237
3238 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3239 for train result */
3240 reg = FDI_RX_IMR(pipe);
3241 temp = I915_READ(reg);
3242 temp &= ~FDI_RX_SYMBOL_LOCK;
3243 temp &= ~FDI_RX_BIT_LOCK;
3244 I915_WRITE(reg, temp);
3245
3246 POSTING_READ(reg);
3247 udelay(150);
3248
3249 /* enable CPU FDI TX and PCH FDI RX */
3250 reg = FDI_TX_CTL(pipe);
3251 temp = I915_READ(reg);
3252 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3253 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3254 temp &= ~FDI_LINK_TRAIN_NONE;
3255 temp |= FDI_LINK_TRAIN_PATTERN_1;
3256 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3257 /* SNB-B */
3258 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3259 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3260
3261 I915_WRITE(FDI_RX_MISC(pipe),
3262 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3263
3264 reg = FDI_RX_CTL(pipe);
3265 temp = I915_READ(reg);
3266 if (HAS_PCH_CPT(dev)) {
3267 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3268 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3269 } else {
3270 temp &= ~FDI_LINK_TRAIN_NONE;
3271 temp |= FDI_LINK_TRAIN_PATTERN_1;
3272 }
3273 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3274
3275 POSTING_READ(reg);
3276 udelay(150);
3277
3278 for (i = 0; i < 4; i++) {
3279 reg = FDI_TX_CTL(pipe);
3280 temp = I915_READ(reg);
3281 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3282 temp |= snb_b_fdi_train_param[i];
3283 I915_WRITE(reg, temp);
3284
3285 POSTING_READ(reg);
3286 udelay(500);
3287
3288 for (retry = 0; retry < 5; retry++) {
3289 reg = FDI_RX_IIR(pipe);
3290 temp = I915_READ(reg);
3291 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3292 if (temp & FDI_RX_BIT_LOCK) {
3293 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3294 DRM_DEBUG_KMS("FDI train 1 done.\n");
3295 break;
3296 }
3297 udelay(50);
3298 }
3299 if (retry < 5)
3300 break;
3301 }
3302 if (i == 4)
3303 DRM_ERROR("FDI train 1 fail!\n");
3304
3305 /* Train 2 */
3306 reg = FDI_TX_CTL(pipe);
3307 temp = I915_READ(reg);
3308 temp &= ~FDI_LINK_TRAIN_NONE;
3309 temp |= FDI_LINK_TRAIN_PATTERN_2;
3310 if (IS_GEN6(dev)) {
3311 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3312 /* SNB-B */
3313 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3314 }
3315 I915_WRITE(reg, temp);
3316
3317 reg = FDI_RX_CTL(pipe);
3318 temp = I915_READ(reg);
3319 if (HAS_PCH_CPT(dev)) {
3320 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3321 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3322 } else {
3323 temp &= ~FDI_LINK_TRAIN_NONE;
3324 temp |= FDI_LINK_TRAIN_PATTERN_2;
3325 }
3326 I915_WRITE(reg, temp);
3327
3328 POSTING_READ(reg);
3329 udelay(150);
3330
3331 for (i = 0; i < 4; i++) {
3332 reg = FDI_TX_CTL(pipe);
3333 temp = I915_READ(reg);
3334 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3335 temp |= snb_b_fdi_train_param[i];
3336 I915_WRITE(reg, temp);
3337
3338 POSTING_READ(reg);
3339 udelay(500);
3340
3341 for (retry = 0; retry < 5; retry++) {
3342 reg = FDI_RX_IIR(pipe);
3343 temp = I915_READ(reg);
3344 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3345 if (temp & FDI_RX_SYMBOL_LOCK) {
3346 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3347 DRM_DEBUG_KMS("FDI train 2 done.\n");
3348 break;
3349 }
3350 udelay(50);
3351 }
3352 if (retry < 5)
3353 break;
3354 }
3355 if (i == 4)
3356 DRM_ERROR("FDI train 2 fail!\n");
3357
3358 DRM_DEBUG_KMS("FDI train done.\n");
3359 }
3360
3361 /* Manual link training for Ivy Bridge A0 parts */
3362 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3363 {
3364 struct drm_device *dev = crtc->dev;
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3367 int pipe = intel_crtc->pipe;
3368 u32 reg, temp, i, j;
3369
3370 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3371 for train result */
3372 reg = FDI_RX_IMR(pipe);
3373 temp = I915_READ(reg);
3374 temp &= ~FDI_RX_SYMBOL_LOCK;
3375 temp &= ~FDI_RX_BIT_LOCK;
3376 I915_WRITE(reg, temp);
3377
3378 POSTING_READ(reg);
3379 udelay(150);
3380
3381 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3382 I915_READ(FDI_RX_IIR(pipe)));
3383
3384 /* Try each vswing and preemphasis setting twice before moving on */
3385 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3386 /* disable first in case we need to retry */
3387 reg = FDI_TX_CTL(pipe);
3388 temp = I915_READ(reg);
3389 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3390 temp &= ~FDI_TX_ENABLE;
3391 I915_WRITE(reg, temp);
3392
3393 reg = FDI_RX_CTL(pipe);
3394 temp = I915_READ(reg);
3395 temp &= ~FDI_LINK_TRAIN_AUTO;
3396 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3397 temp &= ~FDI_RX_ENABLE;
3398 I915_WRITE(reg, temp);
3399
3400 /* enable CPU FDI TX and PCH FDI RX */
3401 reg = FDI_TX_CTL(pipe);
3402 temp = I915_READ(reg);
3403 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3404 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3405 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3406 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3407 temp |= snb_b_fdi_train_param[j/2];
3408 temp |= FDI_COMPOSITE_SYNC;
3409 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3410
3411 I915_WRITE(FDI_RX_MISC(pipe),
3412 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3413
3414 reg = FDI_RX_CTL(pipe);
3415 temp = I915_READ(reg);
3416 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3417 temp |= FDI_COMPOSITE_SYNC;
3418 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3419
3420 POSTING_READ(reg);
3421 udelay(1); /* should be 0.5us */
3422
3423 for (i = 0; i < 4; i++) {
3424 reg = FDI_RX_IIR(pipe);
3425 temp = I915_READ(reg);
3426 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3427
3428 if (temp & FDI_RX_BIT_LOCK ||
3429 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3430 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3431 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3432 i);
3433 break;
3434 }
3435 udelay(1); /* should be 0.5us */
3436 }
3437 if (i == 4) {
3438 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3439 continue;
3440 }
3441
3442 /* Train 2 */
3443 reg = FDI_TX_CTL(pipe);
3444 temp = I915_READ(reg);
3445 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3446 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3447 I915_WRITE(reg, temp);
3448
3449 reg = FDI_RX_CTL(pipe);
3450 temp = I915_READ(reg);
3451 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3452 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3453 I915_WRITE(reg, temp);
3454
3455 POSTING_READ(reg);
3456 udelay(2); /* should be 1.5us */
3457
3458 for (i = 0; i < 4; i++) {
3459 reg = FDI_RX_IIR(pipe);
3460 temp = I915_READ(reg);
3461 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3462
3463 if (temp & FDI_RX_SYMBOL_LOCK ||
3464 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3465 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3466 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3467 i);
3468 goto train_done;
3469 }
3470 udelay(2); /* should be 1.5us */
3471 }
3472 if (i == 4)
3473 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3474 }
3475
3476 train_done:
3477 DRM_DEBUG_KMS("FDI train done.\n");
3478 }
3479
3480 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3481 {
3482 struct drm_device *dev = intel_crtc->base.dev;
3483 struct drm_i915_private *dev_priv = dev->dev_private;
3484 int pipe = intel_crtc->pipe;
3485 u32 reg, temp;
3486
3487
3488 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3489 reg = FDI_RX_CTL(pipe);
3490 temp = I915_READ(reg);
3491 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3492 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3493 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3494 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3495
3496 POSTING_READ(reg);
3497 udelay(200);
3498
3499 /* Switch from Rawclk to PCDclk */
3500 temp = I915_READ(reg);
3501 I915_WRITE(reg, temp | FDI_PCDCLK);
3502
3503 POSTING_READ(reg);
3504 udelay(200);
3505
3506 /* Enable CPU FDI TX PLL, always on for Ironlake */
3507 reg = FDI_TX_CTL(pipe);
3508 temp = I915_READ(reg);
3509 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3510 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3511
3512 POSTING_READ(reg);
3513 udelay(100);
3514 }
3515 }
3516
3517 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3518 {
3519 struct drm_device *dev = intel_crtc->base.dev;
3520 struct drm_i915_private *dev_priv = dev->dev_private;
3521 int pipe = intel_crtc->pipe;
3522 u32 reg, temp;
3523
3524 /* Switch from PCDclk to Rawclk */
3525 reg = FDI_RX_CTL(pipe);
3526 temp = I915_READ(reg);
3527 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3528
3529 /* Disable CPU FDI TX PLL */
3530 reg = FDI_TX_CTL(pipe);
3531 temp = I915_READ(reg);
3532 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3533
3534 POSTING_READ(reg);
3535 udelay(100);
3536
3537 reg = FDI_RX_CTL(pipe);
3538 temp = I915_READ(reg);
3539 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3540
3541 /* Wait for the clocks to turn off. */
3542 POSTING_READ(reg);
3543 udelay(100);
3544 }
3545
3546 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3547 {
3548 struct drm_device *dev = crtc->dev;
3549 struct drm_i915_private *dev_priv = dev->dev_private;
3550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3551 int pipe = intel_crtc->pipe;
3552 u32 reg, temp;
3553
3554 /* disable CPU FDI tx and PCH FDI rx */
3555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
3557 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3558 POSTING_READ(reg);
3559
3560 reg = FDI_RX_CTL(pipe);
3561 temp = I915_READ(reg);
3562 temp &= ~(0x7 << 16);
3563 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3564 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3565
3566 POSTING_READ(reg);
3567 udelay(100);
3568
3569 /* Ironlake workaround, disable clock pointer after downing FDI */
3570 if (HAS_PCH_IBX(dev))
3571 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3572
3573 /* still set train pattern 1 */
3574 reg = FDI_TX_CTL(pipe);
3575 temp = I915_READ(reg);
3576 temp &= ~FDI_LINK_TRAIN_NONE;
3577 temp |= FDI_LINK_TRAIN_PATTERN_1;
3578 I915_WRITE(reg, temp);
3579
3580 reg = FDI_RX_CTL(pipe);
3581 temp = I915_READ(reg);
3582 if (HAS_PCH_CPT(dev)) {
3583 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3584 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3585 } else {
3586 temp &= ~FDI_LINK_TRAIN_NONE;
3587 temp |= FDI_LINK_TRAIN_PATTERN_1;
3588 }
3589 /* BPC in FDI rx is consistent with that in PIPECONF */
3590 temp &= ~(0x07 << 16);
3591 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3592 I915_WRITE(reg, temp);
3593
3594 POSTING_READ(reg);
3595 udelay(100);
3596 }
3597
3598 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3599 {
3600 struct intel_crtc *crtc;
3601
3602 /* Note that we don't need to be called with mode_config.lock here
3603 * as our list of CRTC objects is static for the lifetime of the
3604 * device and so cannot disappear as we iterate. Similarly, we can
3605 * happily treat the predicates as racy, atomic checks as userspace
3606 * cannot claim and pin a new fb without at least acquring the
3607 * struct_mutex and so serialising with us.
3608 */
3609 for_each_intel_crtc(dev, crtc) {
3610 if (atomic_read(&crtc->unpin_work_count) == 0)
3611 continue;
3612
3613 if (crtc->unpin_work)
3614 intel_wait_for_vblank(dev, crtc->pipe);
3615
3616 return true;
3617 }
3618
3619 return false;
3620 }
3621
3622 static void page_flip_completed(struct intel_crtc *intel_crtc)
3623 {
3624 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3625 struct intel_unpin_work *work = intel_crtc->unpin_work;
3626
3627 /* ensure that the unpin work is consistent wrt ->pending. */
3628 smp_rmb();
3629 intel_crtc->unpin_work = NULL;
3630
3631 if (work->event)
3632 drm_send_vblank_event(intel_crtc->base.dev,
3633 intel_crtc->pipe,
3634 work->event);
3635
3636 drm_crtc_vblank_put(&intel_crtc->base);
3637
3638 wake_up_all(&dev_priv->pending_flip_queue);
3639 queue_work(dev_priv->wq, &work->work);
3640
3641 trace_i915_flip_complete(intel_crtc->plane,
3642 work->pending_flip_obj);
3643 }
3644
3645 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3646 {
3647 struct drm_device *dev = crtc->dev;
3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649
3650 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3651 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3652 !intel_crtc_has_pending_flip(crtc),
3653 60*HZ) == 0)) {
3654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655
3656 spin_lock_irq(&dev->event_lock);
3657 if (intel_crtc->unpin_work) {
3658 WARN_ONCE(1, "Removing stuck page flip\n");
3659 page_flip_completed(intel_crtc);
3660 }
3661 spin_unlock_irq(&dev->event_lock);
3662 }
3663
3664 if (crtc->primary->fb) {
3665 mutex_lock(&dev->struct_mutex);
3666 intel_finish_fb(crtc->primary->fb);
3667 mutex_unlock(&dev->struct_mutex);
3668 }
3669 }
3670
3671 /* Program iCLKIP clock to the desired frequency */
3672 static void lpt_program_iclkip(struct drm_crtc *crtc)
3673 {
3674 struct drm_device *dev = crtc->dev;
3675 struct drm_i915_private *dev_priv = dev->dev_private;
3676 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3677 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3678 u32 temp;
3679
3680 mutex_lock(&dev_priv->dpio_lock);
3681
3682 /* It is necessary to ungate the pixclk gate prior to programming
3683 * the divisors, and gate it back when it is done.
3684 */
3685 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3686
3687 /* Disable SSCCTL */
3688 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3689 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3690 SBI_SSCCTL_DISABLE,
3691 SBI_ICLK);
3692
3693 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3694 if (clock == 20000) {
3695 auxdiv = 1;
3696 divsel = 0x41;
3697 phaseinc = 0x20;
3698 } else {
3699 /* The iCLK virtual clock root frequency is in MHz,
3700 * but the adjusted_mode->crtc_clock in in KHz. To get the
3701 * divisors, it is necessary to divide one by another, so we
3702 * convert the virtual clock precision to KHz here for higher
3703 * precision.
3704 */
3705 u32 iclk_virtual_root_freq = 172800 * 1000;
3706 u32 iclk_pi_range = 64;
3707 u32 desired_divisor, msb_divisor_value, pi_value;
3708
3709 desired_divisor = (iclk_virtual_root_freq / clock);
3710 msb_divisor_value = desired_divisor / iclk_pi_range;
3711 pi_value = desired_divisor % iclk_pi_range;
3712
3713 auxdiv = 0;
3714 divsel = msb_divisor_value - 2;
3715 phaseinc = pi_value;
3716 }
3717
3718 /* This should not happen with any sane values */
3719 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3720 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3721 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3722 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3723
3724 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3725 clock,
3726 auxdiv,
3727 divsel,
3728 phasedir,
3729 phaseinc);
3730
3731 /* Program SSCDIVINTPHASE6 */
3732 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3733 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3734 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3735 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3736 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3737 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3738 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3739 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3740
3741 /* Program SSCAUXDIV */
3742 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3743 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3744 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3745 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3746
3747 /* Enable modulator and associated divider */
3748 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3749 temp &= ~SBI_SSCCTL_DISABLE;
3750 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3751
3752 /* Wait for initialization time */
3753 udelay(24);
3754
3755 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3756
3757 mutex_unlock(&dev_priv->dpio_lock);
3758 }
3759
3760 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3761 enum pipe pch_transcoder)
3762 {
3763 struct drm_device *dev = crtc->base.dev;
3764 struct drm_i915_private *dev_priv = dev->dev_private;
3765 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3766
3767 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3768 I915_READ(HTOTAL(cpu_transcoder)));
3769 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3770 I915_READ(HBLANK(cpu_transcoder)));
3771 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3772 I915_READ(HSYNC(cpu_transcoder)));
3773
3774 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3775 I915_READ(VTOTAL(cpu_transcoder)));
3776 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3777 I915_READ(VBLANK(cpu_transcoder)));
3778 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3779 I915_READ(VSYNC(cpu_transcoder)));
3780 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3781 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3782 }
3783
3784 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3785 {
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787 uint32_t temp;
3788
3789 temp = I915_READ(SOUTH_CHICKEN1);
3790 if (temp & FDI_BC_BIFURCATION_SELECT)
3791 return;
3792
3793 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3794 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3795
3796 temp |= FDI_BC_BIFURCATION_SELECT;
3797 DRM_DEBUG_KMS("enabling fdi C rx\n");
3798 I915_WRITE(SOUTH_CHICKEN1, temp);
3799 POSTING_READ(SOUTH_CHICKEN1);
3800 }
3801
3802 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3803 {
3804 struct drm_device *dev = intel_crtc->base.dev;
3805 struct drm_i915_private *dev_priv = dev->dev_private;
3806
3807 switch (intel_crtc->pipe) {
3808 case PIPE_A:
3809 break;
3810 case PIPE_B:
3811 if (intel_crtc->config->fdi_lanes > 2)
3812 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3813 else
3814 cpt_enable_fdi_bc_bifurcation(dev);
3815
3816 break;
3817 case PIPE_C:
3818 cpt_enable_fdi_bc_bifurcation(dev);
3819
3820 break;
3821 default:
3822 BUG();
3823 }
3824 }
3825
3826 /*
3827 * Enable PCH resources required for PCH ports:
3828 * - PCH PLLs
3829 * - FDI training & RX/TX
3830 * - update transcoder timings
3831 * - DP transcoding bits
3832 * - transcoder
3833 */
3834 static void ironlake_pch_enable(struct drm_crtc *crtc)
3835 {
3836 struct drm_device *dev = crtc->dev;
3837 struct drm_i915_private *dev_priv = dev->dev_private;
3838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3839 int pipe = intel_crtc->pipe;
3840 u32 reg, temp;
3841
3842 assert_pch_transcoder_disabled(dev_priv, pipe);
3843
3844 if (IS_IVYBRIDGE(dev))
3845 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3846
3847 /* Write the TU size bits before fdi link training, so that error
3848 * detection works. */
3849 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3850 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3851
3852 /* For PCH output, training FDI link */
3853 dev_priv->display.fdi_link_train(crtc);
3854
3855 /* We need to program the right clock selection before writing the pixel
3856 * mutliplier into the DPLL. */
3857 if (HAS_PCH_CPT(dev)) {
3858 u32 sel;
3859
3860 temp = I915_READ(PCH_DPLL_SEL);
3861 temp |= TRANS_DPLL_ENABLE(pipe);
3862 sel = TRANS_DPLLB_SEL(pipe);
3863 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3864 temp |= sel;
3865 else
3866 temp &= ~sel;
3867 I915_WRITE(PCH_DPLL_SEL, temp);
3868 }
3869
3870 /* XXX: pch pll's can be enabled any time before we enable the PCH
3871 * transcoder, and we actually should do this to not upset any PCH
3872 * transcoder that already use the clock when we share it.
3873 *
3874 * Note that enable_shared_dpll tries to do the right thing, but
3875 * get_shared_dpll unconditionally resets the pll - we need that to have
3876 * the right LVDS enable sequence. */
3877 intel_enable_shared_dpll(intel_crtc);
3878
3879 /* set transcoder timing, panel must allow it */
3880 assert_panel_unlocked(dev_priv, pipe);
3881 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3882
3883 intel_fdi_normal_train(crtc);
3884
3885 /* For PCH DP, enable TRANS_DP_CTL */
3886 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3887 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3888 reg = TRANS_DP_CTL(pipe);
3889 temp = I915_READ(reg);
3890 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3891 TRANS_DP_SYNC_MASK |
3892 TRANS_DP_BPC_MASK);
3893 temp |= (TRANS_DP_OUTPUT_ENABLE |
3894 TRANS_DP_ENH_FRAMING);
3895 temp |= bpc << 9; /* same format but at 11:9 */
3896
3897 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3898 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3899 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3900 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3901
3902 switch (intel_trans_dp_port_sel(crtc)) {
3903 case PCH_DP_B:
3904 temp |= TRANS_DP_PORT_SEL_B;
3905 break;
3906 case PCH_DP_C:
3907 temp |= TRANS_DP_PORT_SEL_C;
3908 break;
3909 case PCH_DP_D:
3910 temp |= TRANS_DP_PORT_SEL_D;
3911 break;
3912 default:
3913 BUG();
3914 }
3915
3916 I915_WRITE(reg, temp);
3917 }
3918
3919 ironlake_enable_pch_transcoder(dev_priv, pipe);
3920 }
3921
3922 static void lpt_pch_enable(struct drm_crtc *crtc)
3923 {
3924 struct drm_device *dev = crtc->dev;
3925 struct drm_i915_private *dev_priv = dev->dev_private;
3926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3927 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3928
3929 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3930
3931 lpt_program_iclkip(crtc);
3932
3933 /* Set transcoder timing. */
3934 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3935
3936 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3937 }
3938
3939 void intel_put_shared_dpll(struct intel_crtc *crtc)
3940 {
3941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3942
3943 if (pll == NULL)
3944 return;
3945
3946 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3947 WARN(1, "bad %s crtc mask\n", pll->name);
3948 return;
3949 }
3950
3951 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3952 if (pll->config.crtc_mask == 0) {
3953 WARN_ON(pll->on);
3954 WARN_ON(pll->active);
3955 }
3956
3957 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3958 }
3959
3960 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3961 struct intel_crtc_state *crtc_state)
3962 {
3963 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3964 struct intel_shared_dpll *pll;
3965 enum intel_dpll_id i;
3966
3967 if (HAS_PCH_IBX(dev_priv->dev)) {
3968 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3969 i = (enum intel_dpll_id) crtc->pipe;
3970 pll = &dev_priv->shared_dplls[i];
3971
3972 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3973 crtc->base.base.id, pll->name);
3974
3975 WARN_ON(pll->new_config->crtc_mask);
3976
3977 goto found;
3978 }
3979
3980 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3981 pll = &dev_priv->shared_dplls[i];
3982
3983 /* Only want to check enabled timings first */
3984 if (pll->new_config->crtc_mask == 0)
3985 continue;
3986
3987 if (memcmp(&crtc_state->dpll_hw_state,
3988 &pll->new_config->hw_state,
3989 sizeof(pll->new_config->hw_state)) == 0) {
3990 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3991 crtc->base.base.id, pll->name,
3992 pll->new_config->crtc_mask,
3993 pll->active);
3994 goto found;
3995 }
3996 }
3997
3998 /* Ok no matching timings, maybe there's a free one? */
3999 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4000 pll = &dev_priv->shared_dplls[i];
4001 if (pll->new_config->crtc_mask == 0) {
4002 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4003 crtc->base.base.id, pll->name);
4004 goto found;
4005 }
4006 }
4007
4008 return NULL;
4009
4010 found:
4011 if (pll->new_config->crtc_mask == 0)
4012 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4013
4014 crtc_state->shared_dpll = i;
4015 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4016 pipe_name(crtc->pipe));
4017
4018 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4019
4020 return pll;
4021 }
4022
4023 /**
4024 * intel_shared_dpll_start_config - start a new PLL staged config
4025 * @dev_priv: DRM device
4026 * @clear_pipes: mask of pipes that will have their PLLs freed
4027 *
4028 * Starts a new PLL staged config, copying the current config but
4029 * releasing the references of pipes specified in clear_pipes.
4030 */
4031 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4032 unsigned clear_pipes)
4033 {
4034 struct intel_shared_dpll *pll;
4035 enum intel_dpll_id i;
4036
4037 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4038 pll = &dev_priv->shared_dplls[i];
4039
4040 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4041 GFP_KERNEL);
4042 if (!pll->new_config)
4043 goto cleanup;
4044
4045 pll->new_config->crtc_mask &= ~clear_pipes;
4046 }
4047
4048 return 0;
4049
4050 cleanup:
4051 while (--i >= 0) {
4052 pll = &dev_priv->shared_dplls[i];
4053 kfree(pll->new_config);
4054 pll->new_config = NULL;
4055 }
4056
4057 return -ENOMEM;
4058 }
4059
4060 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4061 {
4062 struct intel_shared_dpll *pll;
4063 enum intel_dpll_id i;
4064
4065 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4066 pll = &dev_priv->shared_dplls[i];
4067
4068 WARN_ON(pll->new_config == &pll->config);
4069
4070 pll->config = *pll->new_config;
4071 kfree(pll->new_config);
4072 pll->new_config = NULL;
4073 }
4074 }
4075
4076 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4077 {
4078 struct intel_shared_dpll *pll;
4079 enum intel_dpll_id i;
4080
4081 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4082 pll = &dev_priv->shared_dplls[i];
4083
4084 WARN_ON(pll->new_config == &pll->config);
4085
4086 kfree(pll->new_config);
4087 pll->new_config = NULL;
4088 }
4089 }
4090
4091 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4092 {
4093 struct drm_i915_private *dev_priv = dev->dev_private;
4094 int dslreg = PIPEDSL(pipe);
4095 u32 temp;
4096
4097 temp = I915_READ(dslreg);
4098 udelay(500);
4099 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4100 if (wait_for(I915_READ(dslreg) != temp, 5))
4101 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4102 }
4103 }
4104
4105 static void skylake_pfit_enable(struct intel_crtc *crtc)
4106 {
4107 struct drm_device *dev = crtc->base.dev;
4108 struct drm_i915_private *dev_priv = dev->dev_private;
4109 int pipe = crtc->pipe;
4110
4111 if (crtc->config->pch_pfit.enabled) {
4112 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4113 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4114 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4115 }
4116 }
4117
4118 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4119 {
4120 struct drm_device *dev = crtc->base.dev;
4121 struct drm_i915_private *dev_priv = dev->dev_private;
4122 int pipe = crtc->pipe;
4123
4124 if (crtc->config->pch_pfit.enabled) {
4125 /* Force use of hard-coded filter coefficients
4126 * as some pre-programmed values are broken,
4127 * e.g. x201.
4128 */
4129 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4130 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4131 PF_PIPE_SEL_IVB(pipe));
4132 else
4133 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4134 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4135 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4136 }
4137 }
4138
4139 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4140 {
4141 struct drm_device *dev = crtc->dev;
4142 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4143 struct drm_plane *plane;
4144 struct intel_plane *intel_plane;
4145
4146 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4147 intel_plane = to_intel_plane(plane);
4148 if (intel_plane->pipe == pipe)
4149 intel_plane_restore(&intel_plane->base);
4150 }
4151 }
4152
4153 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4154 {
4155 struct drm_device *dev = crtc->dev;
4156 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4157 struct drm_plane *plane;
4158 struct intel_plane *intel_plane;
4159
4160 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4161 intel_plane = to_intel_plane(plane);
4162 if (intel_plane->pipe == pipe)
4163 plane->funcs->disable_plane(plane);
4164 }
4165 }
4166
4167 void hsw_enable_ips(struct intel_crtc *crtc)
4168 {
4169 struct drm_device *dev = crtc->base.dev;
4170 struct drm_i915_private *dev_priv = dev->dev_private;
4171
4172 if (!crtc->config->ips_enabled)
4173 return;
4174
4175 /* We can only enable IPS after we enable a plane and wait for a vblank */
4176 intel_wait_for_vblank(dev, crtc->pipe);
4177
4178 assert_plane_enabled(dev_priv, crtc->plane);
4179 if (IS_BROADWELL(dev)) {
4180 mutex_lock(&dev_priv->rps.hw_lock);
4181 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4182 mutex_unlock(&dev_priv->rps.hw_lock);
4183 /* Quoting Art Runyan: "its not safe to expect any particular
4184 * value in IPS_CTL bit 31 after enabling IPS through the
4185 * mailbox." Moreover, the mailbox may return a bogus state,
4186 * so we need to just enable it and continue on.
4187 */
4188 } else {
4189 I915_WRITE(IPS_CTL, IPS_ENABLE);
4190 /* The bit only becomes 1 in the next vblank, so this wait here
4191 * is essentially intel_wait_for_vblank. If we don't have this
4192 * and don't wait for vblanks until the end of crtc_enable, then
4193 * the HW state readout code will complain that the expected
4194 * IPS_CTL value is not the one we read. */
4195 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4196 DRM_ERROR("Timed out waiting for IPS enable\n");
4197 }
4198 }
4199
4200 void hsw_disable_ips(struct intel_crtc *crtc)
4201 {
4202 struct drm_device *dev = crtc->base.dev;
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204
4205 if (!crtc->config->ips_enabled)
4206 return;
4207
4208 assert_plane_enabled(dev_priv, crtc->plane);
4209 if (IS_BROADWELL(dev)) {
4210 mutex_lock(&dev_priv->rps.hw_lock);
4211 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4212 mutex_unlock(&dev_priv->rps.hw_lock);
4213 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4214 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4215 DRM_ERROR("Timed out waiting for IPS disable\n");
4216 } else {
4217 I915_WRITE(IPS_CTL, 0);
4218 POSTING_READ(IPS_CTL);
4219 }
4220
4221 /* We need to wait for a vblank before we can disable the plane. */
4222 intel_wait_for_vblank(dev, crtc->pipe);
4223 }
4224
4225 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4226 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4227 {
4228 struct drm_device *dev = crtc->dev;
4229 struct drm_i915_private *dev_priv = dev->dev_private;
4230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4231 enum pipe pipe = intel_crtc->pipe;
4232 int palreg = PALETTE(pipe);
4233 int i;
4234 bool reenable_ips = false;
4235
4236 /* The clocks have to be on to load the palette. */
4237 if (!crtc->state->enable || !intel_crtc->active)
4238 return;
4239
4240 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4241 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4242 assert_dsi_pll_enabled(dev_priv);
4243 else
4244 assert_pll_enabled(dev_priv, pipe);
4245 }
4246
4247 /* use legacy palette for Ironlake */
4248 if (!HAS_GMCH_DISPLAY(dev))
4249 palreg = LGC_PALETTE(pipe);
4250
4251 /* Workaround : Do not read or write the pipe palette/gamma data while
4252 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4253 */
4254 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4255 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4256 GAMMA_MODE_MODE_SPLIT)) {
4257 hsw_disable_ips(intel_crtc);
4258 reenable_ips = true;
4259 }
4260
4261 for (i = 0; i < 256; i++) {
4262 I915_WRITE(palreg + 4 * i,
4263 (intel_crtc->lut_r[i] << 16) |
4264 (intel_crtc->lut_g[i] << 8) |
4265 intel_crtc->lut_b[i]);
4266 }
4267
4268 if (reenable_ips)
4269 hsw_enable_ips(intel_crtc);
4270 }
4271
4272 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4273 {
4274 if (!enable && intel_crtc->overlay) {
4275 struct drm_device *dev = intel_crtc->base.dev;
4276 struct drm_i915_private *dev_priv = dev->dev_private;
4277
4278 mutex_lock(&dev->struct_mutex);
4279 dev_priv->mm.interruptible = false;
4280 (void) intel_overlay_switch_off(intel_crtc->overlay);
4281 dev_priv->mm.interruptible = true;
4282 mutex_unlock(&dev->struct_mutex);
4283 }
4284
4285 /* Let userspace switch the overlay on again. In most cases userspace
4286 * has to recompute where to put it anyway.
4287 */
4288 }
4289
4290 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4291 {
4292 struct drm_device *dev = crtc->dev;
4293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4294 int pipe = intel_crtc->pipe;
4295
4296 intel_enable_primary_hw_plane(crtc->primary, crtc);
4297 intel_enable_sprite_planes(crtc);
4298 intel_crtc_update_cursor(crtc, true);
4299 intel_crtc_dpms_overlay(intel_crtc, true);
4300
4301 hsw_enable_ips(intel_crtc);
4302
4303 mutex_lock(&dev->struct_mutex);
4304 intel_fbc_update(dev);
4305 mutex_unlock(&dev->struct_mutex);
4306
4307 /*
4308 * FIXME: Once we grow proper nuclear flip support out of this we need
4309 * to compute the mask of flip planes precisely. For the time being
4310 * consider this a flip from a NULL plane.
4311 */
4312 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4313 }
4314
4315 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4316 {
4317 struct drm_device *dev = crtc->dev;
4318 struct drm_i915_private *dev_priv = dev->dev_private;
4319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4320 int pipe = intel_crtc->pipe;
4321
4322 intel_crtc_wait_for_pending_flips(crtc);
4323
4324 if (dev_priv->fbc.crtc == intel_crtc)
4325 intel_fbc_disable(dev);
4326
4327 hsw_disable_ips(intel_crtc);
4328
4329 intel_crtc_dpms_overlay(intel_crtc, false);
4330 intel_crtc_update_cursor(crtc, false);
4331 intel_disable_sprite_planes(crtc);
4332 intel_disable_primary_hw_plane(crtc->primary, crtc);
4333
4334 /*
4335 * FIXME: Once we grow proper nuclear flip support out of this we need
4336 * to compute the mask of flip planes precisely. For the time being
4337 * consider this a flip to a NULL plane.
4338 */
4339 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4340 }
4341
4342 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4343 {
4344 struct drm_device *dev = crtc->dev;
4345 struct drm_i915_private *dev_priv = dev->dev_private;
4346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4347 struct intel_encoder *encoder;
4348 int pipe = intel_crtc->pipe;
4349
4350 WARN_ON(!crtc->state->enable);
4351
4352 if (intel_crtc->active)
4353 return;
4354
4355 if (intel_crtc->config->has_pch_encoder)
4356 intel_prepare_shared_dpll(intel_crtc);
4357
4358 if (intel_crtc->config->has_dp_encoder)
4359 intel_dp_set_m_n(intel_crtc, M1_N1);
4360
4361 intel_set_pipe_timings(intel_crtc);
4362
4363 if (intel_crtc->config->has_pch_encoder) {
4364 intel_cpu_transcoder_set_m_n(intel_crtc,
4365 &intel_crtc->config->fdi_m_n, NULL);
4366 }
4367
4368 ironlake_set_pipeconf(crtc);
4369
4370 intel_crtc->active = true;
4371
4372 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4373 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4374
4375 for_each_encoder_on_crtc(dev, crtc, encoder)
4376 if (encoder->pre_enable)
4377 encoder->pre_enable(encoder);
4378
4379 if (intel_crtc->config->has_pch_encoder) {
4380 /* Note: FDI PLL enabling _must_ be done before we enable the
4381 * cpu pipes, hence this is separate from all the other fdi/pch
4382 * enabling. */
4383 ironlake_fdi_pll_enable(intel_crtc);
4384 } else {
4385 assert_fdi_tx_disabled(dev_priv, pipe);
4386 assert_fdi_rx_disabled(dev_priv, pipe);
4387 }
4388
4389 ironlake_pfit_enable(intel_crtc);
4390
4391 /*
4392 * On ILK+ LUT must be loaded before the pipe is running but with
4393 * clocks enabled
4394 */
4395 intel_crtc_load_lut(crtc);
4396
4397 intel_update_watermarks(crtc);
4398 intel_enable_pipe(intel_crtc);
4399
4400 if (intel_crtc->config->has_pch_encoder)
4401 ironlake_pch_enable(crtc);
4402
4403 assert_vblank_disabled(crtc);
4404 drm_crtc_vblank_on(crtc);
4405
4406 for_each_encoder_on_crtc(dev, crtc, encoder)
4407 encoder->enable(encoder);
4408
4409 if (HAS_PCH_CPT(dev))
4410 cpt_verify_modeset(dev, intel_crtc->pipe);
4411
4412 intel_crtc_enable_planes(crtc);
4413 }
4414
4415 /* IPS only exists on ULT machines and is tied to pipe A. */
4416 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4417 {
4418 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4419 }
4420
4421 /*
4422 * This implements the workaround described in the "notes" section of the mode
4423 * set sequence documentation. When going from no pipes or single pipe to
4424 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4425 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4426 */
4427 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4428 {
4429 struct drm_device *dev = crtc->base.dev;
4430 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4431
4432 /* We want to get the other_active_crtc only if there's only 1 other
4433 * active crtc. */
4434 for_each_intel_crtc(dev, crtc_it) {
4435 if (!crtc_it->active || crtc_it == crtc)
4436 continue;
4437
4438 if (other_active_crtc)
4439 return;
4440
4441 other_active_crtc = crtc_it;
4442 }
4443 if (!other_active_crtc)
4444 return;
4445
4446 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4447 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4448 }
4449
4450 static void haswell_crtc_enable(struct drm_crtc *crtc)
4451 {
4452 struct drm_device *dev = crtc->dev;
4453 struct drm_i915_private *dev_priv = dev->dev_private;
4454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4455 struct intel_encoder *encoder;
4456 int pipe = intel_crtc->pipe;
4457
4458 WARN_ON(!crtc->state->enable);
4459
4460 if (intel_crtc->active)
4461 return;
4462
4463 if (intel_crtc_to_shared_dpll(intel_crtc))
4464 intel_enable_shared_dpll(intel_crtc);
4465
4466 if (intel_crtc->config->has_dp_encoder)
4467 intel_dp_set_m_n(intel_crtc, M1_N1);
4468
4469 intel_set_pipe_timings(intel_crtc);
4470
4471 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4472 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4473 intel_crtc->config->pixel_multiplier - 1);
4474 }
4475
4476 if (intel_crtc->config->has_pch_encoder) {
4477 intel_cpu_transcoder_set_m_n(intel_crtc,
4478 &intel_crtc->config->fdi_m_n, NULL);
4479 }
4480
4481 haswell_set_pipeconf(crtc);
4482
4483 intel_set_pipe_csc(crtc);
4484
4485 intel_crtc->active = true;
4486
4487 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4488 for_each_encoder_on_crtc(dev, crtc, encoder)
4489 if (encoder->pre_enable)
4490 encoder->pre_enable(encoder);
4491
4492 if (intel_crtc->config->has_pch_encoder) {
4493 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4494 true);
4495 dev_priv->display.fdi_link_train(crtc);
4496 }
4497
4498 intel_ddi_enable_pipe_clock(intel_crtc);
4499
4500 if (IS_SKYLAKE(dev))
4501 skylake_pfit_enable(intel_crtc);
4502 else
4503 ironlake_pfit_enable(intel_crtc);
4504
4505 /*
4506 * On ILK+ LUT must be loaded before the pipe is running but with
4507 * clocks enabled
4508 */
4509 intel_crtc_load_lut(crtc);
4510
4511 intel_ddi_set_pipe_settings(crtc);
4512 intel_ddi_enable_transcoder_func(crtc);
4513
4514 intel_update_watermarks(crtc);
4515 intel_enable_pipe(intel_crtc);
4516
4517 if (intel_crtc->config->has_pch_encoder)
4518 lpt_pch_enable(crtc);
4519
4520 if (intel_crtc->config->dp_encoder_is_mst)
4521 intel_ddi_set_vc_payload_alloc(crtc, true);
4522
4523 assert_vblank_disabled(crtc);
4524 drm_crtc_vblank_on(crtc);
4525
4526 for_each_encoder_on_crtc(dev, crtc, encoder) {
4527 encoder->enable(encoder);
4528 intel_opregion_notify_encoder(encoder, true);
4529 }
4530
4531 /* If we change the relative order between pipe/planes enabling, we need
4532 * to change the workaround. */
4533 haswell_mode_set_planes_workaround(intel_crtc);
4534 intel_crtc_enable_planes(crtc);
4535 }
4536
4537 static void skylake_pfit_disable(struct intel_crtc *crtc)
4538 {
4539 struct drm_device *dev = crtc->base.dev;
4540 struct drm_i915_private *dev_priv = dev->dev_private;
4541 int pipe = crtc->pipe;
4542
4543 /* To avoid upsetting the power well on haswell only disable the pfit if
4544 * it's in use. The hw state code will make sure we get this right. */
4545 if (crtc->config->pch_pfit.enabled) {
4546 I915_WRITE(PS_CTL(pipe), 0);
4547 I915_WRITE(PS_WIN_POS(pipe), 0);
4548 I915_WRITE(PS_WIN_SZ(pipe), 0);
4549 }
4550 }
4551
4552 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4553 {
4554 struct drm_device *dev = crtc->base.dev;
4555 struct drm_i915_private *dev_priv = dev->dev_private;
4556 int pipe = crtc->pipe;
4557
4558 /* To avoid upsetting the power well on haswell only disable the pfit if
4559 * it's in use. The hw state code will make sure we get this right. */
4560 if (crtc->config->pch_pfit.enabled) {
4561 I915_WRITE(PF_CTL(pipe), 0);
4562 I915_WRITE(PF_WIN_POS(pipe), 0);
4563 I915_WRITE(PF_WIN_SZ(pipe), 0);
4564 }
4565 }
4566
4567 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4568 {
4569 struct drm_device *dev = crtc->dev;
4570 struct drm_i915_private *dev_priv = dev->dev_private;
4571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4572 struct intel_encoder *encoder;
4573 int pipe = intel_crtc->pipe;
4574 u32 reg, temp;
4575
4576 if (!intel_crtc->active)
4577 return;
4578
4579 intel_crtc_disable_planes(crtc);
4580
4581 for_each_encoder_on_crtc(dev, crtc, encoder)
4582 encoder->disable(encoder);
4583
4584 drm_crtc_vblank_off(crtc);
4585 assert_vblank_disabled(crtc);
4586
4587 if (intel_crtc->config->has_pch_encoder)
4588 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4589
4590 intel_disable_pipe(intel_crtc);
4591
4592 ironlake_pfit_disable(intel_crtc);
4593
4594 for_each_encoder_on_crtc(dev, crtc, encoder)
4595 if (encoder->post_disable)
4596 encoder->post_disable(encoder);
4597
4598 if (intel_crtc->config->has_pch_encoder) {
4599 ironlake_fdi_disable(crtc);
4600
4601 ironlake_disable_pch_transcoder(dev_priv, pipe);
4602
4603 if (HAS_PCH_CPT(dev)) {
4604 /* disable TRANS_DP_CTL */
4605 reg = TRANS_DP_CTL(pipe);
4606 temp = I915_READ(reg);
4607 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4608 TRANS_DP_PORT_SEL_MASK);
4609 temp |= TRANS_DP_PORT_SEL_NONE;
4610 I915_WRITE(reg, temp);
4611
4612 /* disable DPLL_SEL */
4613 temp = I915_READ(PCH_DPLL_SEL);
4614 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4615 I915_WRITE(PCH_DPLL_SEL, temp);
4616 }
4617
4618 /* disable PCH DPLL */
4619 intel_disable_shared_dpll(intel_crtc);
4620
4621 ironlake_fdi_pll_disable(intel_crtc);
4622 }
4623
4624 intel_crtc->active = false;
4625 intel_update_watermarks(crtc);
4626
4627 mutex_lock(&dev->struct_mutex);
4628 intel_fbc_update(dev);
4629 mutex_unlock(&dev->struct_mutex);
4630 }
4631
4632 static void haswell_crtc_disable(struct drm_crtc *crtc)
4633 {
4634 struct drm_device *dev = crtc->dev;
4635 struct drm_i915_private *dev_priv = dev->dev_private;
4636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4637 struct intel_encoder *encoder;
4638 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4639
4640 if (!intel_crtc->active)
4641 return;
4642
4643 intel_crtc_disable_planes(crtc);
4644
4645 for_each_encoder_on_crtc(dev, crtc, encoder) {
4646 intel_opregion_notify_encoder(encoder, false);
4647 encoder->disable(encoder);
4648 }
4649
4650 drm_crtc_vblank_off(crtc);
4651 assert_vblank_disabled(crtc);
4652
4653 if (intel_crtc->config->has_pch_encoder)
4654 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4655 false);
4656 intel_disable_pipe(intel_crtc);
4657
4658 if (intel_crtc->config->dp_encoder_is_mst)
4659 intel_ddi_set_vc_payload_alloc(crtc, false);
4660
4661 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4662
4663 if (IS_SKYLAKE(dev))
4664 skylake_pfit_disable(intel_crtc);
4665 else
4666 ironlake_pfit_disable(intel_crtc);
4667
4668 intel_ddi_disable_pipe_clock(intel_crtc);
4669
4670 if (intel_crtc->config->has_pch_encoder) {
4671 lpt_disable_pch_transcoder(dev_priv);
4672 intel_ddi_fdi_disable(crtc);
4673 }
4674
4675 for_each_encoder_on_crtc(dev, crtc, encoder)
4676 if (encoder->post_disable)
4677 encoder->post_disable(encoder);
4678
4679 intel_crtc->active = false;
4680 intel_update_watermarks(crtc);
4681
4682 mutex_lock(&dev->struct_mutex);
4683 intel_fbc_update(dev);
4684 mutex_unlock(&dev->struct_mutex);
4685
4686 if (intel_crtc_to_shared_dpll(intel_crtc))
4687 intel_disable_shared_dpll(intel_crtc);
4688 }
4689
4690 static void ironlake_crtc_off(struct drm_crtc *crtc)
4691 {
4692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4693 intel_put_shared_dpll(intel_crtc);
4694 }
4695
4696
4697 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4698 {
4699 struct drm_device *dev = crtc->base.dev;
4700 struct drm_i915_private *dev_priv = dev->dev_private;
4701 struct intel_crtc_state *pipe_config = crtc->config;
4702
4703 if (!pipe_config->gmch_pfit.control)
4704 return;
4705
4706 /*
4707 * The panel fitter should only be adjusted whilst the pipe is disabled,
4708 * according to register description and PRM.
4709 */
4710 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4711 assert_pipe_disabled(dev_priv, crtc->pipe);
4712
4713 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4714 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4715
4716 /* Border color in case we don't scale up to the full screen. Black by
4717 * default, change to something else for debugging. */
4718 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4719 }
4720
4721 static enum intel_display_power_domain port_to_power_domain(enum port port)
4722 {
4723 switch (port) {
4724 case PORT_A:
4725 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4726 case PORT_B:
4727 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4728 case PORT_C:
4729 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4730 case PORT_D:
4731 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4732 default:
4733 WARN_ON_ONCE(1);
4734 return POWER_DOMAIN_PORT_OTHER;
4735 }
4736 }
4737
4738 #define for_each_power_domain(domain, mask) \
4739 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4740 if ((1 << (domain)) & (mask))
4741
4742 enum intel_display_power_domain
4743 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4744 {
4745 struct drm_device *dev = intel_encoder->base.dev;
4746 struct intel_digital_port *intel_dig_port;
4747
4748 switch (intel_encoder->type) {
4749 case INTEL_OUTPUT_UNKNOWN:
4750 /* Only DDI platforms should ever use this output type */
4751 WARN_ON_ONCE(!HAS_DDI(dev));
4752 case INTEL_OUTPUT_DISPLAYPORT:
4753 case INTEL_OUTPUT_HDMI:
4754 case INTEL_OUTPUT_EDP:
4755 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4756 return port_to_power_domain(intel_dig_port->port);
4757 case INTEL_OUTPUT_DP_MST:
4758 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4759 return port_to_power_domain(intel_dig_port->port);
4760 case INTEL_OUTPUT_ANALOG:
4761 return POWER_DOMAIN_PORT_CRT;
4762 case INTEL_OUTPUT_DSI:
4763 return POWER_DOMAIN_PORT_DSI;
4764 default:
4765 return POWER_DOMAIN_PORT_OTHER;
4766 }
4767 }
4768
4769 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4770 {
4771 struct drm_device *dev = crtc->dev;
4772 struct intel_encoder *intel_encoder;
4773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4774 enum pipe pipe = intel_crtc->pipe;
4775 unsigned long mask;
4776 enum transcoder transcoder;
4777
4778 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4779
4780 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4781 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4782 if (intel_crtc->config->pch_pfit.enabled ||
4783 intel_crtc->config->pch_pfit.force_thru)
4784 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4785
4786 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4787 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4788
4789 return mask;
4790 }
4791
4792 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4793 {
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4795 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4796 struct intel_crtc *crtc;
4797
4798 /*
4799 * First get all needed power domains, then put all unneeded, to avoid
4800 * any unnecessary toggling of the power wells.
4801 */
4802 for_each_intel_crtc(dev, crtc) {
4803 enum intel_display_power_domain domain;
4804
4805 if (!crtc->base.state->enable)
4806 continue;
4807
4808 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4809
4810 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4811 intel_display_power_get(dev_priv, domain);
4812 }
4813
4814 if (dev_priv->display.modeset_global_resources)
4815 dev_priv->display.modeset_global_resources(dev);
4816
4817 for_each_intel_crtc(dev, crtc) {
4818 enum intel_display_power_domain domain;
4819
4820 for_each_power_domain(domain, crtc->enabled_power_domains)
4821 intel_display_power_put(dev_priv, domain);
4822
4823 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4824 }
4825
4826 intel_display_set_init_power(dev_priv, false);
4827 }
4828
4829 /* returns HPLL frequency in kHz */
4830 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4831 {
4832 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4833
4834 /* Obtain SKU information */
4835 mutex_lock(&dev_priv->dpio_lock);
4836 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4837 CCK_FUSE_HPLL_FREQ_MASK;
4838 mutex_unlock(&dev_priv->dpio_lock);
4839
4840 return vco_freq[hpll_freq] * 1000;
4841 }
4842
4843 static void vlv_update_cdclk(struct drm_device *dev)
4844 {
4845 struct drm_i915_private *dev_priv = dev->dev_private;
4846
4847 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4848 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4849 dev_priv->vlv_cdclk_freq);
4850
4851 /*
4852 * Program the gmbus_freq based on the cdclk frequency.
4853 * BSpec erroneously claims we should aim for 4MHz, but
4854 * in fact 1MHz is the correct frequency.
4855 */
4856 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4857 }
4858
4859 /* Adjust CDclk dividers to allow high res or save power if possible */
4860 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4861 {
4862 struct drm_i915_private *dev_priv = dev->dev_private;
4863 u32 val, cmd;
4864
4865 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4866
4867 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4868 cmd = 2;
4869 else if (cdclk == 266667)
4870 cmd = 1;
4871 else
4872 cmd = 0;
4873
4874 mutex_lock(&dev_priv->rps.hw_lock);
4875 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4876 val &= ~DSPFREQGUAR_MASK;
4877 val |= (cmd << DSPFREQGUAR_SHIFT);
4878 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4879 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4880 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4881 50)) {
4882 DRM_ERROR("timed out waiting for CDclk change\n");
4883 }
4884 mutex_unlock(&dev_priv->rps.hw_lock);
4885
4886 if (cdclk == 400000) {
4887 u32 divider;
4888
4889 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4890
4891 mutex_lock(&dev_priv->dpio_lock);
4892 /* adjust cdclk divider */
4893 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4894 val &= ~DISPLAY_FREQUENCY_VALUES;
4895 val |= divider;
4896 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4897
4898 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4899 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4900 50))
4901 DRM_ERROR("timed out waiting for CDclk change\n");
4902 mutex_unlock(&dev_priv->dpio_lock);
4903 }
4904
4905 mutex_lock(&dev_priv->dpio_lock);
4906 /* adjust self-refresh exit latency value */
4907 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4908 val &= ~0x7f;
4909
4910 /*
4911 * For high bandwidth configs, we set a higher latency in the bunit
4912 * so that the core display fetch happens in time to avoid underruns.
4913 */
4914 if (cdclk == 400000)
4915 val |= 4500 / 250; /* 4.5 usec */
4916 else
4917 val |= 3000 / 250; /* 3.0 usec */
4918 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4919 mutex_unlock(&dev_priv->dpio_lock);
4920
4921 vlv_update_cdclk(dev);
4922 }
4923
4924 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4925 {
4926 struct drm_i915_private *dev_priv = dev->dev_private;
4927 u32 val, cmd;
4928
4929 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4930
4931 switch (cdclk) {
4932 case 400000:
4933 cmd = 3;
4934 break;
4935 case 333333:
4936 case 320000:
4937 cmd = 2;
4938 break;
4939 case 266667:
4940 cmd = 1;
4941 break;
4942 case 200000:
4943 cmd = 0;
4944 break;
4945 default:
4946 MISSING_CASE(cdclk);
4947 return;
4948 }
4949
4950 mutex_lock(&dev_priv->rps.hw_lock);
4951 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4952 val &= ~DSPFREQGUAR_MASK_CHV;
4953 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4954 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4955 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4956 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4957 50)) {
4958 DRM_ERROR("timed out waiting for CDclk change\n");
4959 }
4960 mutex_unlock(&dev_priv->rps.hw_lock);
4961
4962 vlv_update_cdclk(dev);
4963 }
4964
4965 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4966 int max_pixclk)
4967 {
4968 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
4969
4970 /* FIXME: Punit isn't quite ready yet */
4971 if (IS_CHERRYVIEW(dev_priv->dev))
4972 return 400000;
4973
4974 /*
4975 * Really only a few cases to deal with, as only 4 CDclks are supported:
4976 * 200MHz
4977 * 267MHz
4978 * 320/333MHz (depends on HPLL freq)
4979 * 400MHz
4980 * So we check to see whether we're above 90% of the lower bin and
4981 * adjust if needed.
4982 *
4983 * We seem to get an unstable or solid color picture at 200MHz.
4984 * Not sure what's wrong. For now use 200MHz only when all pipes
4985 * are off.
4986 */
4987 if (max_pixclk > freq_320*9/10)
4988 return 400000;
4989 else if (max_pixclk > 266667*9/10)
4990 return freq_320;
4991 else if (max_pixclk > 0)
4992 return 266667;
4993 else
4994 return 200000;
4995 }
4996
4997 /* compute the max pixel clock for new configuration */
4998 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4999 {
5000 struct drm_device *dev = dev_priv->dev;
5001 struct intel_crtc *intel_crtc;
5002 int max_pixclk = 0;
5003
5004 for_each_intel_crtc(dev, intel_crtc) {
5005 if (intel_crtc->new_enabled)
5006 max_pixclk = max(max_pixclk,
5007 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5008 }
5009
5010 return max_pixclk;
5011 }
5012
5013 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5014 unsigned *prepare_pipes)
5015 {
5016 struct drm_i915_private *dev_priv = dev->dev_private;
5017 struct intel_crtc *intel_crtc;
5018 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5019
5020 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5021 dev_priv->vlv_cdclk_freq)
5022 return;
5023
5024 /* disable/enable all currently active pipes while we change cdclk */
5025 for_each_intel_crtc(dev, intel_crtc)
5026 if (intel_crtc->base.state->enable)
5027 *prepare_pipes |= (1 << intel_crtc->pipe);
5028 }
5029
5030 static void valleyview_modeset_global_resources(struct drm_device *dev)
5031 {
5032 struct drm_i915_private *dev_priv = dev->dev_private;
5033 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5034 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5035
5036 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5037 /*
5038 * FIXME: We can end up here with all power domains off, yet
5039 * with a CDCLK frequency other than the minimum. To account
5040 * for this take the PIPE-A power domain, which covers the HW
5041 * blocks needed for the following programming. This can be
5042 * removed once it's guaranteed that we get here either with
5043 * the minimum CDCLK set, or the required power domains
5044 * enabled.
5045 */
5046 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5047
5048 if (IS_CHERRYVIEW(dev))
5049 cherryview_set_cdclk(dev, req_cdclk);
5050 else
5051 valleyview_set_cdclk(dev, req_cdclk);
5052
5053 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5054 }
5055 }
5056
5057 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5058 {
5059 struct drm_device *dev = crtc->dev;
5060 struct drm_i915_private *dev_priv = to_i915(dev);
5061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5062 struct intel_encoder *encoder;
5063 int pipe = intel_crtc->pipe;
5064 bool is_dsi;
5065
5066 WARN_ON(!crtc->state->enable);
5067
5068 if (intel_crtc->active)
5069 return;
5070
5071 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5072
5073 if (!is_dsi) {
5074 if (IS_CHERRYVIEW(dev))
5075 chv_prepare_pll(intel_crtc, intel_crtc->config);
5076 else
5077 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5078 }
5079
5080 if (intel_crtc->config->has_dp_encoder)
5081 intel_dp_set_m_n(intel_crtc, M1_N1);
5082
5083 intel_set_pipe_timings(intel_crtc);
5084
5085 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5086 struct drm_i915_private *dev_priv = dev->dev_private;
5087
5088 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5089 I915_WRITE(CHV_CANVAS(pipe), 0);
5090 }
5091
5092 i9xx_set_pipeconf(intel_crtc);
5093
5094 intel_crtc->active = true;
5095
5096 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5097
5098 for_each_encoder_on_crtc(dev, crtc, encoder)
5099 if (encoder->pre_pll_enable)
5100 encoder->pre_pll_enable(encoder);
5101
5102 if (!is_dsi) {
5103 if (IS_CHERRYVIEW(dev))
5104 chv_enable_pll(intel_crtc, intel_crtc->config);
5105 else
5106 vlv_enable_pll(intel_crtc, intel_crtc->config);
5107 }
5108
5109 for_each_encoder_on_crtc(dev, crtc, encoder)
5110 if (encoder->pre_enable)
5111 encoder->pre_enable(encoder);
5112
5113 i9xx_pfit_enable(intel_crtc);
5114
5115 intel_crtc_load_lut(crtc);
5116
5117 intel_update_watermarks(crtc);
5118 intel_enable_pipe(intel_crtc);
5119
5120 assert_vblank_disabled(crtc);
5121 drm_crtc_vblank_on(crtc);
5122
5123 for_each_encoder_on_crtc(dev, crtc, encoder)
5124 encoder->enable(encoder);
5125
5126 intel_crtc_enable_planes(crtc);
5127
5128 /* Underruns don't raise interrupts, so check manually. */
5129 i9xx_check_fifo_underruns(dev_priv);
5130 }
5131
5132 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5133 {
5134 struct drm_device *dev = crtc->base.dev;
5135 struct drm_i915_private *dev_priv = dev->dev_private;
5136
5137 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5138 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5139 }
5140
5141 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5142 {
5143 struct drm_device *dev = crtc->dev;
5144 struct drm_i915_private *dev_priv = to_i915(dev);
5145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5146 struct intel_encoder *encoder;
5147 int pipe = intel_crtc->pipe;
5148
5149 WARN_ON(!crtc->state->enable);
5150
5151 if (intel_crtc->active)
5152 return;
5153
5154 i9xx_set_pll_dividers(intel_crtc);
5155
5156 if (intel_crtc->config->has_dp_encoder)
5157 intel_dp_set_m_n(intel_crtc, M1_N1);
5158
5159 intel_set_pipe_timings(intel_crtc);
5160
5161 i9xx_set_pipeconf(intel_crtc);
5162
5163 intel_crtc->active = true;
5164
5165 if (!IS_GEN2(dev))
5166 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5167
5168 for_each_encoder_on_crtc(dev, crtc, encoder)
5169 if (encoder->pre_enable)
5170 encoder->pre_enable(encoder);
5171
5172 i9xx_enable_pll(intel_crtc);
5173
5174 i9xx_pfit_enable(intel_crtc);
5175
5176 intel_crtc_load_lut(crtc);
5177
5178 intel_update_watermarks(crtc);
5179 intel_enable_pipe(intel_crtc);
5180
5181 assert_vblank_disabled(crtc);
5182 drm_crtc_vblank_on(crtc);
5183
5184 for_each_encoder_on_crtc(dev, crtc, encoder)
5185 encoder->enable(encoder);
5186
5187 intel_crtc_enable_planes(crtc);
5188
5189 /*
5190 * Gen2 reports pipe underruns whenever all planes are disabled.
5191 * So don't enable underrun reporting before at least some planes
5192 * are enabled.
5193 * FIXME: Need to fix the logic to work when we turn off all planes
5194 * but leave the pipe running.
5195 */
5196 if (IS_GEN2(dev))
5197 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5198
5199 /* Underruns don't raise interrupts, so check manually. */
5200 i9xx_check_fifo_underruns(dev_priv);
5201 }
5202
5203 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5204 {
5205 struct drm_device *dev = crtc->base.dev;
5206 struct drm_i915_private *dev_priv = dev->dev_private;
5207
5208 if (!crtc->config->gmch_pfit.control)
5209 return;
5210
5211 assert_pipe_disabled(dev_priv, crtc->pipe);
5212
5213 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5214 I915_READ(PFIT_CONTROL));
5215 I915_WRITE(PFIT_CONTROL, 0);
5216 }
5217
5218 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5219 {
5220 struct drm_device *dev = crtc->dev;
5221 struct drm_i915_private *dev_priv = dev->dev_private;
5222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5223 struct intel_encoder *encoder;
5224 int pipe = intel_crtc->pipe;
5225
5226 if (!intel_crtc->active)
5227 return;
5228
5229 /*
5230 * Gen2 reports pipe underruns whenever all planes are disabled.
5231 * So diasble underrun reporting before all the planes get disabled.
5232 * FIXME: Need to fix the logic to work when we turn off all planes
5233 * but leave the pipe running.
5234 */
5235 if (IS_GEN2(dev))
5236 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5237
5238 /*
5239 * Vblank time updates from the shadow to live plane control register
5240 * are blocked if the memory self-refresh mode is active at that
5241 * moment. So to make sure the plane gets truly disabled, disable
5242 * first the self-refresh mode. The self-refresh enable bit in turn
5243 * will be checked/applied by the HW only at the next frame start
5244 * event which is after the vblank start event, so we need to have a
5245 * wait-for-vblank between disabling the plane and the pipe.
5246 */
5247 intel_set_memory_cxsr(dev_priv, false);
5248 intel_crtc_disable_planes(crtc);
5249
5250 /*
5251 * On gen2 planes are double buffered but the pipe isn't, so we must
5252 * wait for planes to fully turn off before disabling the pipe.
5253 * We also need to wait on all gmch platforms because of the
5254 * self-refresh mode constraint explained above.
5255 */
5256 intel_wait_for_vblank(dev, pipe);
5257
5258 for_each_encoder_on_crtc(dev, crtc, encoder)
5259 encoder->disable(encoder);
5260
5261 drm_crtc_vblank_off(crtc);
5262 assert_vblank_disabled(crtc);
5263
5264 intel_disable_pipe(intel_crtc);
5265
5266 i9xx_pfit_disable(intel_crtc);
5267
5268 for_each_encoder_on_crtc(dev, crtc, encoder)
5269 if (encoder->post_disable)
5270 encoder->post_disable(encoder);
5271
5272 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5273 if (IS_CHERRYVIEW(dev))
5274 chv_disable_pll(dev_priv, pipe);
5275 else if (IS_VALLEYVIEW(dev))
5276 vlv_disable_pll(dev_priv, pipe);
5277 else
5278 i9xx_disable_pll(intel_crtc);
5279 }
5280
5281 if (!IS_GEN2(dev))
5282 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5283
5284 intel_crtc->active = false;
5285 intel_update_watermarks(crtc);
5286
5287 mutex_lock(&dev->struct_mutex);
5288 intel_fbc_update(dev);
5289 mutex_unlock(&dev->struct_mutex);
5290 }
5291
5292 static void i9xx_crtc_off(struct drm_crtc *crtc)
5293 {
5294 }
5295
5296 /* Master function to enable/disable CRTC and corresponding power wells */
5297 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5298 {
5299 struct drm_device *dev = crtc->dev;
5300 struct drm_i915_private *dev_priv = dev->dev_private;
5301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5302 enum intel_display_power_domain domain;
5303 unsigned long domains;
5304
5305 if (enable) {
5306 if (!intel_crtc->active) {
5307 domains = get_crtc_power_domains(crtc);
5308 for_each_power_domain(domain, domains)
5309 intel_display_power_get(dev_priv, domain);
5310 intel_crtc->enabled_power_domains = domains;
5311
5312 dev_priv->display.crtc_enable(crtc);
5313 }
5314 } else {
5315 if (intel_crtc->active) {
5316 dev_priv->display.crtc_disable(crtc);
5317
5318 domains = intel_crtc->enabled_power_domains;
5319 for_each_power_domain(domain, domains)
5320 intel_display_power_put(dev_priv, domain);
5321 intel_crtc->enabled_power_domains = 0;
5322 }
5323 }
5324 }
5325
5326 /**
5327 * Sets the power management mode of the pipe and plane.
5328 */
5329 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5330 {
5331 struct drm_device *dev = crtc->dev;
5332 struct intel_encoder *intel_encoder;
5333 bool enable = false;
5334
5335 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5336 enable |= intel_encoder->connectors_active;
5337
5338 intel_crtc_control(crtc, enable);
5339 }
5340
5341 static void intel_crtc_disable(struct drm_crtc *crtc)
5342 {
5343 struct drm_device *dev = crtc->dev;
5344 struct drm_connector *connector;
5345 struct drm_i915_private *dev_priv = dev->dev_private;
5346
5347 /* crtc should still be enabled when we disable it. */
5348 WARN_ON(!crtc->state->enable);
5349
5350 dev_priv->display.crtc_disable(crtc);
5351 dev_priv->display.off(crtc);
5352
5353 crtc->primary->funcs->disable_plane(crtc->primary);
5354
5355 /* Update computed state. */
5356 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5357 if (!connector->encoder || !connector->encoder->crtc)
5358 continue;
5359
5360 if (connector->encoder->crtc != crtc)
5361 continue;
5362
5363 connector->dpms = DRM_MODE_DPMS_OFF;
5364 to_intel_encoder(connector->encoder)->connectors_active = false;
5365 }
5366 }
5367
5368 void intel_encoder_destroy(struct drm_encoder *encoder)
5369 {
5370 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5371
5372 drm_encoder_cleanup(encoder);
5373 kfree(intel_encoder);
5374 }
5375
5376 /* Simple dpms helper for encoders with just one connector, no cloning and only
5377 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5378 * state of the entire output pipe. */
5379 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5380 {
5381 if (mode == DRM_MODE_DPMS_ON) {
5382 encoder->connectors_active = true;
5383
5384 intel_crtc_update_dpms(encoder->base.crtc);
5385 } else {
5386 encoder->connectors_active = false;
5387
5388 intel_crtc_update_dpms(encoder->base.crtc);
5389 }
5390 }
5391
5392 /* Cross check the actual hw state with our own modeset state tracking (and it's
5393 * internal consistency). */
5394 static void intel_connector_check_state(struct intel_connector *connector)
5395 {
5396 if (connector->get_hw_state(connector)) {
5397 struct intel_encoder *encoder = connector->encoder;
5398 struct drm_crtc *crtc;
5399 bool encoder_enabled;
5400 enum pipe pipe;
5401
5402 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5403 connector->base.base.id,
5404 connector->base.name);
5405
5406 /* there is no real hw state for MST connectors */
5407 if (connector->mst_port)
5408 return;
5409
5410 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5411 "wrong connector dpms state\n");
5412 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5413 "active connector not linked to encoder\n");
5414
5415 if (encoder) {
5416 I915_STATE_WARN(!encoder->connectors_active,
5417 "encoder->connectors_active not set\n");
5418
5419 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5420 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5421 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5422 return;
5423
5424 crtc = encoder->base.crtc;
5425
5426 I915_STATE_WARN(!crtc->state->enable,
5427 "crtc not enabled\n");
5428 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5429 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5430 "encoder active on the wrong pipe\n");
5431 }
5432 }
5433 }
5434
5435 /* Even simpler default implementation, if there's really no special case to
5436 * consider. */
5437 void intel_connector_dpms(struct drm_connector *connector, int mode)
5438 {
5439 /* All the simple cases only support two dpms states. */
5440 if (mode != DRM_MODE_DPMS_ON)
5441 mode = DRM_MODE_DPMS_OFF;
5442
5443 if (mode == connector->dpms)
5444 return;
5445
5446 connector->dpms = mode;
5447
5448 /* Only need to change hw state when actually enabled */
5449 if (connector->encoder)
5450 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5451
5452 intel_modeset_check_state(connector->dev);
5453 }
5454
5455 /* Simple connector->get_hw_state implementation for encoders that support only
5456 * one connector and no cloning and hence the encoder state determines the state
5457 * of the connector. */
5458 bool intel_connector_get_hw_state(struct intel_connector *connector)
5459 {
5460 enum pipe pipe = 0;
5461 struct intel_encoder *encoder = connector->encoder;
5462
5463 return encoder->get_hw_state(encoder, &pipe);
5464 }
5465
5466 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5467 struct intel_crtc_state *pipe_config)
5468 {
5469 struct drm_i915_private *dev_priv = dev->dev_private;
5470 struct intel_crtc *pipe_B_crtc =
5471 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5472
5473 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5474 pipe_name(pipe), pipe_config->fdi_lanes);
5475 if (pipe_config->fdi_lanes > 4) {
5476 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5477 pipe_name(pipe), pipe_config->fdi_lanes);
5478 return false;
5479 }
5480
5481 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5482 if (pipe_config->fdi_lanes > 2) {
5483 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5484 pipe_config->fdi_lanes);
5485 return false;
5486 } else {
5487 return true;
5488 }
5489 }
5490
5491 if (INTEL_INFO(dev)->num_pipes == 2)
5492 return true;
5493
5494 /* Ivybridge 3 pipe is really complicated */
5495 switch (pipe) {
5496 case PIPE_A:
5497 return true;
5498 case PIPE_B:
5499 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5500 pipe_config->fdi_lanes > 2) {
5501 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5502 pipe_name(pipe), pipe_config->fdi_lanes);
5503 return false;
5504 }
5505 return true;
5506 case PIPE_C:
5507 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5508 pipe_B_crtc->config->fdi_lanes <= 2) {
5509 if (pipe_config->fdi_lanes > 2) {
5510 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5511 pipe_name(pipe), pipe_config->fdi_lanes);
5512 return false;
5513 }
5514 } else {
5515 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5516 return false;
5517 }
5518 return true;
5519 default:
5520 BUG();
5521 }
5522 }
5523
5524 #define RETRY 1
5525 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5526 struct intel_crtc_state *pipe_config)
5527 {
5528 struct drm_device *dev = intel_crtc->base.dev;
5529 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5530 int lane, link_bw, fdi_dotclock;
5531 bool setup_ok, needs_recompute = false;
5532
5533 retry:
5534 /* FDI is a binary signal running at ~2.7GHz, encoding
5535 * each output octet as 10 bits. The actual frequency
5536 * is stored as a divider into a 100MHz clock, and the
5537 * mode pixel clock is stored in units of 1KHz.
5538 * Hence the bw of each lane in terms of the mode signal
5539 * is:
5540 */
5541 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5542
5543 fdi_dotclock = adjusted_mode->crtc_clock;
5544
5545 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5546 pipe_config->pipe_bpp);
5547
5548 pipe_config->fdi_lanes = lane;
5549
5550 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5551 link_bw, &pipe_config->fdi_m_n);
5552
5553 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5554 intel_crtc->pipe, pipe_config);
5555 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5556 pipe_config->pipe_bpp -= 2*3;
5557 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5558 pipe_config->pipe_bpp);
5559 needs_recompute = true;
5560 pipe_config->bw_constrained = true;
5561
5562 goto retry;
5563 }
5564
5565 if (needs_recompute)
5566 return RETRY;
5567
5568 return setup_ok ? 0 : -EINVAL;
5569 }
5570
5571 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5572 struct intel_crtc_state *pipe_config)
5573 {
5574 pipe_config->ips_enabled = i915.enable_ips &&
5575 hsw_crtc_supports_ips(crtc) &&
5576 pipe_config->pipe_bpp <= 24;
5577 }
5578
5579 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5580 struct intel_crtc_state *pipe_config)
5581 {
5582 struct drm_device *dev = crtc->base.dev;
5583 struct drm_i915_private *dev_priv = dev->dev_private;
5584 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5585
5586 /* FIXME should check pixel clock limits on all platforms */
5587 if (INTEL_INFO(dev)->gen < 4) {
5588 int clock_limit =
5589 dev_priv->display.get_display_clock_speed(dev);
5590
5591 /*
5592 * Enable pixel doubling when the dot clock
5593 * is > 90% of the (display) core speed.
5594 *
5595 * GDG double wide on either pipe,
5596 * otherwise pipe A only.
5597 */
5598 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5599 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5600 clock_limit *= 2;
5601 pipe_config->double_wide = true;
5602 }
5603
5604 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5605 return -EINVAL;
5606 }
5607
5608 /*
5609 * Pipe horizontal size must be even in:
5610 * - DVO ganged mode
5611 * - LVDS dual channel mode
5612 * - Double wide pipe
5613 */
5614 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5615 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5616 pipe_config->pipe_src_w &= ~1;
5617
5618 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5619 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5620 */
5621 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5622 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5623 return -EINVAL;
5624
5625 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5626 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5627 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5628 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5629 * for lvds. */
5630 pipe_config->pipe_bpp = 8*3;
5631 }
5632
5633 if (HAS_IPS(dev))
5634 hsw_compute_ips_config(crtc, pipe_config);
5635
5636 if (pipe_config->has_pch_encoder)
5637 return ironlake_fdi_compute_config(crtc, pipe_config);
5638
5639 return 0;
5640 }
5641
5642 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5643 {
5644 struct drm_i915_private *dev_priv = dev->dev_private;
5645 u32 val;
5646 int divider;
5647
5648 /* FIXME: Punit isn't quite ready yet */
5649 if (IS_CHERRYVIEW(dev))
5650 return 400000;
5651
5652 if (dev_priv->hpll_freq == 0)
5653 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5654
5655 mutex_lock(&dev_priv->dpio_lock);
5656 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5657 mutex_unlock(&dev_priv->dpio_lock);
5658
5659 divider = val & DISPLAY_FREQUENCY_VALUES;
5660
5661 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5662 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5663 "cdclk change in progress\n");
5664
5665 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5666 }
5667
5668 static int i945_get_display_clock_speed(struct drm_device *dev)
5669 {
5670 return 400000;
5671 }
5672
5673 static int i915_get_display_clock_speed(struct drm_device *dev)
5674 {
5675 return 333000;
5676 }
5677
5678 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5679 {
5680 return 200000;
5681 }
5682
5683 static int pnv_get_display_clock_speed(struct drm_device *dev)
5684 {
5685 u16 gcfgc = 0;
5686
5687 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5688
5689 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5690 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5691 return 267000;
5692 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5693 return 333000;
5694 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5695 return 444000;
5696 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5697 return 200000;
5698 default:
5699 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5700 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5701 return 133000;
5702 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5703 return 167000;
5704 }
5705 }
5706
5707 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5708 {
5709 u16 gcfgc = 0;
5710
5711 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5712
5713 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5714 return 133000;
5715 else {
5716 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5717 case GC_DISPLAY_CLOCK_333_MHZ:
5718 return 333000;
5719 default:
5720 case GC_DISPLAY_CLOCK_190_200_MHZ:
5721 return 190000;
5722 }
5723 }
5724 }
5725
5726 static int i865_get_display_clock_speed(struct drm_device *dev)
5727 {
5728 return 266000;
5729 }
5730
5731 static int i855_get_display_clock_speed(struct drm_device *dev)
5732 {
5733 u16 hpllcc = 0;
5734 /* Assume that the hardware is in the high speed state. This
5735 * should be the default.
5736 */
5737 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5738 case GC_CLOCK_133_200:
5739 case GC_CLOCK_100_200:
5740 return 200000;
5741 case GC_CLOCK_166_250:
5742 return 250000;
5743 case GC_CLOCK_100_133:
5744 return 133000;
5745 }
5746
5747 /* Shouldn't happen */
5748 return 0;
5749 }
5750
5751 static int i830_get_display_clock_speed(struct drm_device *dev)
5752 {
5753 return 133000;
5754 }
5755
5756 static void
5757 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5758 {
5759 while (*num > DATA_LINK_M_N_MASK ||
5760 *den > DATA_LINK_M_N_MASK) {
5761 *num >>= 1;
5762 *den >>= 1;
5763 }
5764 }
5765
5766 static void compute_m_n(unsigned int m, unsigned int n,
5767 uint32_t *ret_m, uint32_t *ret_n)
5768 {
5769 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5770 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5771 intel_reduce_m_n_ratio(ret_m, ret_n);
5772 }
5773
5774 void
5775 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5776 int pixel_clock, int link_clock,
5777 struct intel_link_m_n *m_n)
5778 {
5779 m_n->tu = 64;
5780
5781 compute_m_n(bits_per_pixel * pixel_clock,
5782 link_clock * nlanes * 8,
5783 &m_n->gmch_m, &m_n->gmch_n);
5784
5785 compute_m_n(pixel_clock, link_clock,
5786 &m_n->link_m, &m_n->link_n);
5787 }
5788
5789 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5790 {
5791 if (i915.panel_use_ssc >= 0)
5792 return i915.panel_use_ssc != 0;
5793 return dev_priv->vbt.lvds_use_ssc
5794 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5795 }
5796
5797 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5798 {
5799 struct drm_device *dev = crtc->base.dev;
5800 struct drm_i915_private *dev_priv = dev->dev_private;
5801 int refclk;
5802
5803 if (IS_VALLEYVIEW(dev)) {
5804 refclk = 100000;
5805 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5806 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5807 refclk = dev_priv->vbt.lvds_ssc_freq;
5808 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5809 } else if (!IS_GEN2(dev)) {
5810 refclk = 96000;
5811 } else {
5812 refclk = 48000;
5813 }
5814
5815 return refclk;
5816 }
5817
5818 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5819 {
5820 return (1 << dpll->n) << 16 | dpll->m2;
5821 }
5822
5823 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5824 {
5825 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5826 }
5827
5828 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5829 struct intel_crtc_state *crtc_state,
5830 intel_clock_t *reduced_clock)
5831 {
5832 struct drm_device *dev = crtc->base.dev;
5833 u32 fp, fp2 = 0;
5834
5835 if (IS_PINEVIEW(dev)) {
5836 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5837 if (reduced_clock)
5838 fp2 = pnv_dpll_compute_fp(reduced_clock);
5839 } else {
5840 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5841 if (reduced_clock)
5842 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5843 }
5844
5845 crtc_state->dpll_hw_state.fp0 = fp;
5846
5847 crtc->lowfreq_avail = false;
5848 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5849 reduced_clock && i915.powersave) {
5850 crtc_state->dpll_hw_state.fp1 = fp2;
5851 crtc->lowfreq_avail = true;
5852 } else {
5853 crtc_state->dpll_hw_state.fp1 = fp;
5854 }
5855 }
5856
5857 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5858 pipe)
5859 {
5860 u32 reg_val;
5861
5862 /*
5863 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5864 * and set it to a reasonable value instead.
5865 */
5866 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5867 reg_val &= 0xffffff00;
5868 reg_val |= 0x00000030;
5869 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5870
5871 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5872 reg_val &= 0x8cffffff;
5873 reg_val = 0x8c000000;
5874 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5875
5876 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5877 reg_val &= 0xffffff00;
5878 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5879
5880 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5881 reg_val &= 0x00ffffff;
5882 reg_val |= 0xb0000000;
5883 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5884 }
5885
5886 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5887 struct intel_link_m_n *m_n)
5888 {
5889 struct drm_device *dev = crtc->base.dev;
5890 struct drm_i915_private *dev_priv = dev->dev_private;
5891 int pipe = crtc->pipe;
5892
5893 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5894 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5895 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5896 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5897 }
5898
5899 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5900 struct intel_link_m_n *m_n,
5901 struct intel_link_m_n *m2_n2)
5902 {
5903 struct drm_device *dev = crtc->base.dev;
5904 struct drm_i915_private *dev_priv = dev->dev_private;
5905 int pipe = crtc->pipe;
5906 enum transcoder transcoder = crtc->config->cpu_transcoder;
5907
5908 if (INTEL_INFO(dev)->gen >= 5) {
5909 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5910 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5911 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5912 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5913 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5914 * for gen < 8) and if DRRS is supported (to make sure the
5915 * registers are not unnecessarily accessed).
5916 */
5917 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
5918 crtc->config->has_drrs) {
5919 I915_WRITE(PIPE_DATA_M2(transcoder),
5920 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5921 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5922 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5923 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5924 }
5925 } else {
5926 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5927 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5928 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5929 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5930 }
5931 }
5932
5933 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
5934 {
5935 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
5936
5937 if (m_n == M1_N1) {
5938 dp_m_n = &crtc->config->dp_m_n;
5939 dp_m2_n2 = &crtc->config->dp_m2_n2;
5940 } else if (m_n == M2_N2) {
5941
5942 /*
5943 * M2_N2 registers are not supported. Hence m2_n2 divider value
5944 * needs to be programmed into M1_N1.
5945 */
5946 dp_m_n = &crtc->config->dp_m2_n2;
5947 } else {
5948 DRM_ERROR("Unsupported divider value\n");
5949 return;
5950 }
5951
5952 if (crtc->config->has_pch_encoder)
5953 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5954 else
5955 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
5956 }
5957
5958 static void vlv_update_pll(struct intel_crtc *crtc,
5959 struct intel_crtc_state *pipe_config)
5960 {
5961 u32 dpll, dpll_md;
5962
5963 /*
5964 * Enable DPIO clock input. We should never disable the reference
5965 * clock for pipe B, since VGA hotplug / manual detection depends
5966 * on it.
5967 */
5968 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5969 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5970 /* We should never disable this, set it here for state tracking */
5971 if (crtc->pipe == PIPE_B)
5972 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5973 dpll |= DPLL_VCO_ENABLE;
5974 pipe_config->dpll_hw_state.dpll = dpll;
5975
5976 dpll_md = (pipe_config->pixel_multiplier - 1)
5977 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5978 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5979 }
5980
5981 static void vlv_prepare_pll(struct intel_crtc *crtc,
5982 const struct intel_crtc_state *pipe_config)
5983 {
5984 struct drm_device *dev = crtc->base.dev;
5985 struct drm_i915_private *dev_priv = dev->dev_private;
5986 int pipe = crtc->pipe;
5987 u32 mdiv;
5988 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5989 u32 coreclk, reg_val;
5990
5991 mutex_lock(&dev_priv->dpio_lock);
5992
5993 bestn = pipe_config->dpll.n;
5994 bestm1 = pipe_config->dpll.m1;
5995 bestm2 = pipe_config->dpll.m2;
5996 bestp1 = pipe_config->dpll.p1;
5997 bestp2 = pipe_config->dpll.p2;
5998
5999 /* See eDP HDMI DPIO driver vbios notes doc */
6000
6001 /* PLL B needs special handling */
6002 if (pipe == PIPE_B)
6003 vlv_pllb_recal_opamp(dev_priv, pipe);
6004
6005 /* Set up Tx target for periodic Rcomp update */
6006 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6007
6008 /* Disable target IRef on PLL */
6009 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6010 reg_val &= 0x00ffffff;
6011 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6012
6013 /* Disable fast lock */
6014 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6015
6016 /* Set idtafcrecal before PLL is enabled */
6017 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6018 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6019 mdiv |= ((bestn << DPIO_N_SHIFT));
6020 mdiv |= (1 << DPIO_K_SHIFT);
6021
6022 /*
6023 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6024 * but we don't support that).
6025 * Note: don't use the DAC post divider as it seems unstable.
6026 */
6027 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6028 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6029
6030 mdiv |= DPIO_ENABLE_CALIBRATION;
6031 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6032
6033 /* Set HBR and RBR LPF coefficients */
6034 if (pipe_config->port_clock == 162000 ||
6035 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6036 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6037 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6038 0x009f0003);
6039 else
6040 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6041 0x00d0000f);
6042
6043 if (pipe_config->has_dp_encoder) {
6044 /* Use SSC source */
6045 if (pipe == PIPE_A)
6046 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6047 0x0df40000);
6048 else
6049 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6050 0x0df70000);
6051 } else { /* HDMI or VGA */
6052 /* Use bend source */
6053 if (pipe == PIPE_A)
6054 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6055 0x0df70000);
6056 else
6057 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6058 0x0df40000);
6059 }
6060
6061 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6062 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6063 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6064 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6065 coreclk |= 0x01000000;
6066 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6067
6068 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6069 mutex_unlock(&dev_priv->dpio_lock);
6070 }
6071
6072 static void chv_update_pll(struct intel_crtc *crtc,
6073 struct intel_crtc_state *pipe_config)
6074 {
6075 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6076 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6077 DPLL_VCO_ENABLE;
6078 if (crtc->pipe != PIPE_A)
6079 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6080
6081 pipe_config->dpll_hw_state.dpll_md =
6082 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6083 }
6084
6085 static void chv_prepare_pll(struct intel_crtc *crtc,
6086 const struct intel_crtc_state *pipe_config)
6087 {
6088 struct drm_device *dev = crtc->base.dev;
6089 struct drm_i915_private *dev_priv = dev->dev_private;
6090 int pipe = crtc->pipe;
6091 int dpll_reg = DPLL(crtc->pipe);
6092 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6093 u32 loopfilter, intcoeff;
6094 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6095 int refclk;
6096
6097 bestn = pipe_config->dpll.n;
6098 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6099 bestm1 = pipe_config->dpll.m1;
6100 bestm2 = pipe_config->dpll.m2 >> 22;
6101 bestp1 = pipe_config->dpll.p1;
6102 bestp2 = pipe_config->dpll.p2;
6103
6104 /*
6105 * Enable Refclk and SSC
6106 */
6107 I915_WRITE(dpll_reg,
6108 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6109
6110 mutex_lock(&dev_priv->dpio_lock);
6111
6112 /* p1 and p2 divider */
6113 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6114 5 << DPIO_CHV_S1_DIV_SHIFT |
6115 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6116 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6117 1 << DPIO_CHV_K_DIV_SHIFT);
6118
6119 /* Feedback post-divider - m2 */
6120 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6121
6122 /* Feedback refclk divider - n and m1 */
6123 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6124 DPIO_CHV_M1_DIV_BY_2 |
6125 1 << DPIO_CHV_N_DIV_SHIFT);
6126
6127 /* M2 fraction division */
6128 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6129
6130 /* M2 fraction division enable */
6131 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6132 DPIO_CHV_FRAC_DIV_EN |
6133 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6134
6135 /* Loop filter */
6136 refclk = i9xx_get_refclk(crtc, 0);
6137 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6138 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6139 if (refclk == 100000)
6140 intcoeff = 11;
6141 else if (refclk == 38400)
6142 intcoeff = 10;
6143 else
6144 intcoeff = 9;
6145 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6146 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6147
6148 /* AFC Recal */
6149 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6150 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6151 DPIO_AFC_RECAL);
6152
6153 mutex_unlock(&dev_priv->dpio_lock);
6154 }
6155
6156 /**
6157 * vlv_force_pll_on - forcibly enable just the PLL
6158 * @dev_priv: i915 private structure
6159 * @pipe: pipe PLL to enable
6160 * @dpll: PLL configuration
6161 *
6162 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6163 * in cases where we need the PLL enabled even when @pipe is not going to
6164 * be enabled.
6165 */
6166 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6167 const struct dpll *dpll)
6168 {
6169 struct intel_crtc *crtc =
6170 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6171 struct intel_crtc_state pipe_config = {
6172 .pixel_multiplier = 1,
6173 .dpll = *dpll,
6174 };
6175
6176 if (IS_CHERRYVIEW(dev)) {
6177 chv_update_pll(crtc, &pipe_config);
6178 chv_prepare_pll(crtc, &pipe_config);
6179 chv_enable_pll(crtc, &pipe_config);
6180 } else {
6181 vlv_update_pll(crtc, &pipe_config);
6182 vlv_prepare_pll(crtc, &pipe_config);
6183 vlv_enable_pll(crtc, &pipe_config);
6184 }
6185 }
6186
6187 /**
6188 * vlv_force_pll_off - forcibly disable just the PLL
6189 * @dev_priv: i915 private structure
6190 * @pipe: pipe PLL to disable
6191 *
6192 * Disable the PLL for @pipe. To be used in cases where we need
6193 * the PLL enabled even when @pipe is not going to be enabled.
6194 */
6195 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6196 {
6197 if (IS_CHERRYVIEW(dev))
6198 chv_disable_pll(to_i915(dev), pipe);
6199 else
6200 vlv_disable_pll(to_i915(dev), pipe);
6201 }
6202
6203 static void i9xx_update_pll(struct intel_crtc *crtc,
6204 struct intel_crtc_state *crtc_state,
6205 intel_clock_t *reduced_clock,
6206 int num_connectors)
6207 {
6208 struct drm_device *dev = crtc->base.dev;
6209 struct drm_i915_private *dev_priv = dev->dev_private;
6210 u32 dpll;
6211 bool is_sdvo;
6212 struct dpll *clock = &crtc_state->dpll;
6213
6214 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6215
6216 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6217 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6218
6219 dpll = DPLL_VGA_MODE_DIS;
6220
6221 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6222 dpll |= DPLLB_MODE_LVDS;
6223 else
6224 dpll |= DPLLB_MODE_DAC_SERIAL;
6225
6226 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6227 dpll |= (crtc_state->pixel_multiplier - 1)
6228 << SDVO_MULTIPLIER_SHIFT_HIRES;
6229 }
6230
6231 if (is_sdvo)
6232 dpll |= DPLL_SDVO_HIGH_SPEED;
6233
6234 if (crtc_state->has_dp_encoder)
6235 dpll |= DPLL_SDVO_HIGH_SPEED;
6236
6237 /* compute bitmask from p1 value */
6238 if (IS_PINEVIEW(dev))
6239 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6240 else {
6241 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6242 if (IS_G4X(dev) && reduced_clock)
6243 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6244 }
6245 switch (clock->p2) {
6246 case 5:
6247 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6248 break;
6249 case 7:
6250 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6251 break;
6252 case 10:
6253 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6254 break;
6255 case 14:
6256 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6257 break;
6258 }
6259 if (INTEL_INFO(dev)->gen >= 4)
6260 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6261
6262 if (crtc_state->sdvo_tv_clock)
6263 dpll |= PLL_REF_INPUT_TVCLKINBC;
6264 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6265 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6266 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6267 else
6268 dpll |= PLL_REF_INPUT_DREFCLK;
6269
6270 dpll |= DPLL_VCO_ENABLE;
6271 crtc_state->dpll_hw_state.dpll = dpll;
6272
6273 if (INTEL_INFO(dev)->gen >= 4) {
6274 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6275 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6276 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6277 }
6278 }
6279
6280 static void i8xx_update_pll(struct intel_crtc *crtc,
6281 struct intel_crtc_state *crtc_state,
6282 intel_clock_t *reduced_clock,
6283 int num_connectors)
6284 {
6285 struct drm_device *dev = crtc->base.dev;
6286 struct drm_i915_private *dev_priv = dev->dev_private;
6287 u32 dpll;
6288 struct dpll *clock = &crtc_state->dpll;
6289
6290 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6291
6292 dpll = DPLL_VGA_MODE_DIS;
6293
6294 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6295 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6296 } else {
6297 if (clock->p1 == 2)
6298 dpll |= PLL_P1_DIVIDE_BY_TWO;
6299 else
6300 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6301 if (clock->p2 == 4)
6302 dpll |= PLL_P2_DIVIDE_BY_4;
6303 }
6304
6305 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6306 dpll |= DPLL_DVO_2X_MODE;
6307
6308 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6309 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6310 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6311 else
6312 dpll |= PLL_REF_INPUT_DREFCLK;
6313
6314 dpll |= DPLL_VCO_ENABLE;
6315 crtc_state->dpll_hw_state.dpll = dpll;
6316 }
6317
6318 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6319 {
6320 struct drm_device *dev = intel_crtc->base.dev;
6321 struct drm_i915_private *dev_priv = dev->dev_private;
6322 enum pipe pipe = intel_crtc->pipe;
6323 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6324 struct drm_display_mode *adjusted_mode =
6325 &intel_crtc->config->base.adjusted_mode;
6326 uint32_t crtc_vtotal, crtc_vblank_end;
6327 int vsyncshift = 0;
6328
6329 /* We need to be careful not to changed the adjusted mode, for otherwise
6330 * the hw state checker will get angry at the mismatch. */
6331 crtc_vtotal = adjusted_mode->crtc_vtotal;
6332 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6333
6334 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6335 /* the chip adds 2 halflines automatically */
6336 crtc_vtotal -= 1;
6337 crtc_vblank_end -= 1;
6338
6339 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6340 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6341 else
6342 vsyncshift = adjusted_mode->crtc_hsync_start -
6343 adjusted_mode->crtc_htotal / 2;
6344 if (vsyncshift < 0)
6345 vsyncshift += adjusted_mode->crtc_htotal;
6346 }
6347
6348 if (INTEL_INFO(dev)->gen > 3)
6349 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6350
6351 I915_WRITE(HTOTAL(cpu_transcoder),
6352 (adjusted_mode->crtc_hdisplay - 1) |
6353 ((adjusted_mode->crtc_htotal - 1) << 16));
6354 I915_WRITE(HBLANK(cpu_transcoder),
6355 (adjusted_mode->crtc_hblank_start - 1) |
6356 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6357 I915_WRITE(HSYNC(cpu_transcoder),
6358 (adjusted_mode->crtc_hsync_start - 1) |
6359 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6360
6361 I915_WRITE(VTOTAL(cpu_transcoder),
6362 (adjusted_mode->crtc_vdisplay - 1) |
6363 ((crtc_vtotal - 1) << 16));
6364 I915_WRITE(VBLANK(cpu_transcoder),
6365 (adjusted_mode->crtc_vblank_start - 1) |
6366 ((crtc_vblank_end - 1) << 16));
6367 I915_WRITE(VSYNC(cpu_transcoder),
6368 (adjusted_mode->crtc_vsync_start - 1) |
6369 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6370
6371 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6372 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6373 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6374 * bits. */
6375 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6376 (pipe == PIPE_B || pipe == PIPE_C))
6377 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6378
6379 /* pipesrc controls the size that is scaled from, which should
6380 * always be the user's requested size.
6381 */
6382 I915_WRITE(PIPESRC(pipe),
6383 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6384 (intel_crtc->config->pipe_src_h - 1));
6385 }
6386
6387 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6388 struct intel_crtc_state *pipe_config)
6389 {
6390 struct drm_device *dev = crtc->base.dev;
6391 struct drm_i915_private *dev_priv = dev->dev_private;
6392 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6393 uint32_t tmp;
6394
6395 tmp = I915_READ(HTOTAL(cpu_transcoder));
6396 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6397 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6398 tmp = I915_READ(HBLANK(cpu_transcoder));
6399 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6400 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6401 tmp = I915_READ(HSYNC(cpu_transcoder));
6402 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6403 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6404
6405 tmp = I915_READ(VTOTAL(cpu_transcoder));
6406 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6407 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6408 tmp = I915_READ(VBLANK(cpu_transcoder));
6409 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6410 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6411 tmp = I915_READ(VSYNC(cpu_transcoder));
6412 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6413 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6414
6415 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6416 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6417 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6418 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6419 }
6420
6421 tmp = I915_READ(PIPESRC(crtc->pipe));
6422 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6423 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6424
6425 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6426 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6427 }
6428
6429 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6430 struct intel_crtc_state *pipe_config)
6431 {
6432 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6433 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6434 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6435 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6436
6437 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6438 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6439 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6440 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6441
6442 mode->flags = pipe_config->base.adjusted_mode.flags;
6443
6444 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6445 mode->flags |= pipe_config->base.adjusted_mode.flags;
6446 }
6447
6448 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6449 {
6450 struct drm_device *dev = intel_crtc->base.dev;
6451 struct drm_i915_private *dev_priv = dev->dev_private;
6452 uint32_t pipeconf;
6453
6454 pipeconf = 0;
6455
6456 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6457 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6458 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6459
6460 if (intel_crtc->config->double_wide)
6461 pipeconf |= PIPECONF_DOUBLE_WIDE;
6462
6463 /* only g4x and later have fancy bpc/dither controls */
6464 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6465 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6466 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6467 pipeconf |= PIPECONF_DITHER_EN |
6468 PIPECONF_DITHER_TYPE_SP;
6469
6470 switch (intel_crtc->config->pipe_bpp) {
6471 case 18:
6472 pipeconf |= PIPECONF_6BPC;
6473 break;
6474 case 24:
6475 pipeconf |= PIPECONF_8BPC;
6476 break;
6477 case 30:
6478 pipeconf |= PIPECONF_10BPC;
6479 break;
6480 default:
6481 /* Case prevented by intel_choose_pipe_bpp_dither. */
6482 BUG();
6483 }
6484 }
6485
6486 if (HAS_PIPE_CXSR(dev)) {
6487 if (intel_crtc->lowfreq_avail) {
6488 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6489 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6490 } else {
6491 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6492 }
6493 }
6494
6495 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6496 if (INTEL_INFO(dev)->gen < 4 ||
6497 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6498 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6499 else
6500 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6501 } else
6502 pipeconf |= PIPECONF_PROGRESSIVE;
6503
6504 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6505 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6506
6507 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6508 POSTING_READ(PIPECONF(intel_crtc->pipe));
6509 }
6510
6511 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6512 struct intel_crtc_state *crtc_state)
6513 {
6514 struct drm_device *dev = crtc->base.dev;
6515 struct drm_i915_private *dev_priv = dev->dev_private;
6516 int refclk, num_connectors = 0;
6517 intel_clock_t clock, reduced_clock;
6518 bool ok, has_reduced_clock = false;
6519 bool is_lvds = false, is_dsi = false;
6520 struct intel_encoder *encoder;
6521 const intel_limit_t *limit;
6522
6523 for_each_intel_encoder(dev, encoder) {
6524 if (encoder->new_crtc != crtc)
6525 continue;
6526
6527 switch (encoder->type) {
6528 case INTEL_OUTPUT_LVDS:
6529 is_lvds = true;
6530 break;
6531 case INTEL_OUTPUT_DSI:
6532 is_dsi = true;
6533 break;
6534 default:
6535 break;
6536 }
6537
6538 num_connectors++;
6539 }
6540
6541 if (is_dsi)
6542 return 0;
6543
6544 if (!crtc_state->clock_set) {
6545 refclk = i9xx_get_refclk(crtc, num_connectors);
6546
6547 /*
6548 * Returns a set of divisors for the desired target clock with
6549 * the given refclk, or FALSE. The returned values represent
6550 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6551 * 2) / p1 / p2.
6552 */
6553 limit = intel_limit(crtc, refclk);
6554 ok = dev_priv->display.find_dpll(limit, crtc,
6555 crtc_state->port_clock,
6556 refclk, NULL, &clock);
6557 if (!ok) {
6558 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6559 return -EINVAL;
6560 }
6561
6562 if (is_lvds && dev_priv->lvds_downclock_avail) {
6563 /*
6564 * Ensure we match the reduced clock's P to the target
6565 * clock. If the clocks don't match, we can't switch
6566 * the display clock by using the FP0/FP1. In such case
6567 * we will disable the LVDS downclock feature.
6568 */
6569 has_reduced_clock =
6570 dev_priv->display.find_dpll(limit, crtc,
6571 dev_priv->lvds_downclock,
6572 refclk, &clock,
6573 &reduced_clock);
6574 }
6575 /* Compat-code for transition, will disappear. */
6576 crtc_state->dpll.n = clock.n;
6577 crtc_state->dpll.m1 = clock.m1;
6578 crtc_state->dpll.m2 = clock.m2;
6579 crtc_state->dpll.p1 = clock.p1;
6580 crtc_state->dpll.p2 = clock.p2;
6581 }
6582
6583 if (IS_GEN2(dev)) {
6584 i8xx_update_pll(crtc, crtc_state,
6585 has_reduced_clock ? &reduced_clock : NULL,
6586 num_connectors);
6587 } else if (IS_CHERRYVIEW(dev)) {
6588 chv_update_pll(crtc, crtc_state);
6589 } else if (IS_VALLEYVIEW(dev)) {
6590 vlv_update_pll(crtc, crtc_state);
6591 } else {
6592 i9xx_update_pll(crtc, crtc_state,
6593 has_reduced_clock ? &reduced_clock : NULL,
6594 num_connectors);
6595 }
6596
6597 return 0;
6598 }
6599
6600 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6601 struct intel_crtc_state *pipe_config)
6602 {
6603 struct drm_device *dev = crtc->base.dev;
6604 struct drm_i915_private *dev_priv = dev->dev_private;
6605 uint32_t tmp;
6606
6607 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6608 return;
6609
6610 tmp = I915_READ(PFIT_CONTROL);
6611 if (!(tmp & PFIT_ENABLE))
6612 return;
6613
6614 /* Check whether the pfit is attached to our pipe. */
6615 if (INTEL_INFO(dev)->gen < 4) {
6616 if (crtc->pipe != PIPE_B)
6617 return;
6618 } else {
6619 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6620 return;
6621 }
6622
6623 pipe_config->gmch_pfit.control = tmp;
6624 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6625 if (INTEL_INFO(dev)->gen < 5)
6626 pipe_config->gmch_pfit.lvds_border_bits =
6627 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6628 }
6629
6630 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6631 struct intel_crtc_state *pipe_config)
6632 {
6633 struct drm_device *dev = crtc->base.dev;
6634 struct drm_i915_private *dev_priv = dev->dev_private;
6635 int pipe = pipe_config->cpu_transcoder;
6636 intel_clock_t clock;
6637 u32 mdiv;
6638 int refclk = 100000;
6639
6640 /* In case of MIPI DPLL will not even be used */
6641 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6642 return;
6643
6644 mutex_lock(&dev_priv->dpio_lock);
6645 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6646 mutex_unlock(&dev_priv->dpio_lock);
6647
6648 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6649 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6650 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6651 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6652 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6653
6654 vlv_clock(refclk, &clock);
6655
6656 /* clock.dot is the fast clock */
6657 pipe_config->port_clock = clock.dot / 5;
6658 }
6659
6660 static void
6661 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6662 struct intel_initial_plane_config *plane_config)
6663 {
6664 struct drm_device *dev = crtc->base.dev;
6665 struct drm_i915_private *dev_priv = dev->dev_private;
6666 u32 val, base, offset;
6667 int pipe = crtc->pipe, plane = crtc->plane;
6668 int fourcc, pixel_format;
6669 int aligned_height;
6670 struct drm_framebuffer *fb;
6671 struct intel_framebuffer *intel_fb;
6672
6673 val = I915_READ(DSPCNTR(plane));
6674 if (!(val & DISPLAY_PLANE_ENABLE))
6675 return;
6676
6677 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6678 if (!intel_fb) {
6679 DRM_DEBUG_KMS("failed to alloc fb\n");
6680 return;
6681 }
6682
6683 fb = &intel_fb->base;
6684
6685 if (INTEL_INFO(dev)->gen >= 4) {
6686 if (val & DISPPLANE_TILED) {
6687 plane_config->tiling = I915_TILING_X;
6688 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6689 }
6690 }
6691
6692 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6693 fourcc = i9xx_format_to_fourcc(pixel_format);
6694 fb->pixel_format = fourcc;
6695 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6696
6697 if (INTEL_INFO(dev)->gen >= 4) {
6698 if (plane_config->tiling)
6699 offset = I915_READ(DSPTILEOFF(plane));
6700 else
6701 offset = I915_READ(DSPLINOFF(plane));
6702 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6703 } else {
6704 base = I915_READ(DSPADDR(plane));
6705 }
6706 plane_config->base = base;
6707
6708 val = I915_READ(PIPESRC(pipe));
6709 fb->width = ((val >> 16) & 0xfff) + 1;
6710 fb->height = ((val >> 0) & 0xfff) + 1;
6711
6712 val = I915_READ(DSPSTRIDE(pipe));
6713 fb->pitches[0] = val & 0xffffffc0;
6714
6715 aligned_height = intel_fb_align_height(dev, fb->height,
6716 fb->pixel_format,
6717 fb->modifier[0]);
6718
6719 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
6720
6721 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6722 pipe_name(pipe), plane, fb->width, fb->height,
6723 fb->bits_per_pixel, base, fb->pitches[0],
6724 plane_config->size);
6725
6726 plane_config->fb = intel_fb;
6727 }
6728
6729 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6730 struct intel_crtc_state *pipe_config)
6731 {
6732 struct drm_device *dev = crtc->base.dev;
6733 struct drm_i915_private *dev_priv = dev->dev_private;
6734 int pipe = pipe_config->cpu_transcoder;
6735 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6736 intel_clock_t clock;
6737 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6738 int refclk = 100000;
6739
6740 mutex_lock(&dev_priv->dpio_lock);
6741 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6742 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6743 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6744 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6745 mutex_unlock(&dev_priv->dpio_lock);
6746
6747 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6748 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6749 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6750 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6751 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6752
6753 chv_clock(refclk, &clock);
6754
6755 /* clock.dot is the fast clock */
6756 pipe_config->port_clock = clock.dot / 5;
6757 }
6758
6759 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6760 struct intel_crtc_state *pipe_config)
6761 {
6762 struct drm_device *dev = crtc->base.dev;
6763 struct drm_i915_private *dev_priv = dev->dev_private;
6764 uint32_t tmp;
6765
6766 if (!intel_display_power_is_enabled(dev_priv,
6767 POWER_DOMAIN_PIPE(crtc->pipe)))
6768 return false;
6769
6770 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6771 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6772
6773 tmp = I915_READ(PIPECONF(crtc->pipe));
6774 if (!(tmp & PIPECONF_ENABLE))
6775 return false;
6776
6777 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6778 switch (tmp & PIPECONF_BPC_MASK) {
6779 case PIPECONF_6BPC:
6780 pipe_config->pipe_bpp = 18;
6781 break;
6782 case PIPECONF_8BPC:
6783 pipe_config->pipe_bpp = 24;
6784 break;
6785 case PIPECONF_10BPC:
6786 pipe_config->pipe_bpp = 30;
6787 break;
6788 default:
6789 break;
6790 }
6791 }
6792
6793 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6794 pipe_config->limited_color_range = true;
6795
6796 if (INTEL_INFO(dev)->gen < 4)
6797 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6798
6799 intel_get_pipe_timings(crtc, pipe_config);
6800
6801 i9xx_get_pfit_config(crtc, pipe_config);
6802
6803 if (INTEL_INFO(dev)->gen >= 4) {
6804 tmp = I915_READ(DPLL_MD(crtc->pipe));
6805 pipe_config->pixel_multiplier =
6806 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6807 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6808 pipe_config->dpll_hw_state.dpll_md = tmp;
6809 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6810 tmp = I915_READ(DPLL(crtc->pipe));
6811 pipe_config->pixel_multiplier =
6812 ((tmp & SDVO_MULTIPLIER_MASK)
6813 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6814 } else {
6815 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6816 * port and will be fixed up in the encoder->get_config
6817 * function. */
6818 pipe_config->pixel_multiplier = 1;
6819 }
6820 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6821 if (!IS_VALLEYVIEW(dev)) {
6822 /*
6823 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6824 * on 830. Filter it out here so that we don't
6825 * report errors due to that.
6826 */
6827 if (IS_I830(dev))
6828 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6829
6830 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6831 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6832 } else {
6833 /* Mask out read-only status bits. */
6834 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6835 DPLL_PORTC_READY_MASK |
6836 DPLL_PORTB_READY_MASK);
6837 }
6838
6839 if (IS_CHERRYVIEW(dev))
6840 chv_crtc_clock_get(crtc, pipe_config);
6841 else if (IS_VALLEYVIEW(dev))
6842 vlv_crtc_clock_get(crtc, pipe_config);
6843 else
6844 i9xx_crtc_clock_get(crtc, pipe_config);
6845
6846 return true;
6847 }
6848
6849 static void ironlake_init_pch_refclk(struct drm_device *dev)
6850 {
6851 struct drm_i915_private *dev_priv = dev->dev_private;
6852 struct intel_encoder *encoder;
6853 u32 val, final;
6854 bool has_lvds = false;
6855 bool has_cpu_edp = false;
6856 bool has_panel = false;
6857 bool has_ck505 = false;
6858 bool can_ssc = false;
6859
6860 /* We need to take the global config into account */
6861 for_each_intel_encoder(dev, encoder) {
6862 switch (encoder->type) {
6863 case INTEL_OUTPUT_LVDS:
6864 has_panel = true;
6865 has_lvds = true;
6866 break;
6867 case INTEL_OUTPUT_EDP:
6868 has_panel = true;
6869 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6870 has_cpu_edp = true;
6871 break;
6872 default:
6873 break;
6874 }
6875 }
6876
6877 if (HAS_PCH_IBX(dev)) {
6878 has_ck505 = dev_priv->vbt.display_clock_mode;
6879 can_ssc = has_ck505;
6880 } else {
6881 has_ck505 = false;
6882 can_ssc = true;
6883 }
6884
6885 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6886 has_panel, has_lvds, has_ck505);
6887
6888 /* Ironlake: try to setup display ref clock before DPLL
6889 * enabling. This is only under driver's control after
6890 * PCH B stepping, previous chipset stepping should be
6891 * ignoring this setting.
6892 */
6893 val = I915_READ(PCH_DREF_CONTROL);
6894
6895 /* As we must carefully and slowly disable/enable each source in turn,
6896 * compute the final state we want first and check if we need to
6897 * make any changes at all.
6898 */
6899 final = val;
6900 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6901 if (has_ck505)
6902 final |= DREF_NONSPREAD_CK505_ENABLE;
6903 else
6904 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6905
6906 final &= ~DREF_SSC_SOURCE_MASK;
6907 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6908 final &= ~DREF_SSC1_ENABLE;
6909
6910 if (has_panel) {
6911 final |= DREF_SSC_SOURCE_ENABLE;
6912
6913 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6914 final |= DREF_SSC1_ENABLE;
6915
6916 if (has_cpu_edp) {
6917 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6918 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6919 else
6920 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6921 } else
6922 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6923 } else {
6924 final |= DREF_SSC_SOURCE_DISABLE;
6925 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6926 }
6927
6928 if (final == val)
6929 return;
6930
6931 /* Always enable nonspread source */
6932 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6933
6934 if (has_ck505)
6935 val |= DREF_NONSPREAD_CK505_ENABLE;
6936 else
6937 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6938
6939 if (has_panel) {
6940 val &= ~DREF_SSC_SOURCE_MASK;
6941 val |= DREF_SSC_SOURCE_ENABLE;
6942
6943 /* SSC must be turned on before enabling the CPU output */
6944 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6945 DRM_DEBUG_KMS("Using SSC on panel\n");
6946 val |= DREF_SSC1_ENABLE;
6947 } else
6948 val &= ~DREF_SSC1_ENABLE;
6949
6950 /* Get SSC going before enabling the outputs */
6951 I915_WRITE(PCH_DREF_CONTROL, val);
6952 POSTING_READ(PCH_DREF_CONTROL);
6953 udelay(200);
6954
6955 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6956
6957 /* Enable CPU source on CPU attached eDP */
6958 if (has_cpu_edp) {
6959 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6960 DRM_DEBUG_KMS("Using SSC on eDP\n");
6961 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6962 } else
6963 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6964 } else
6965 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6966
6967 I915_WRITE(PCH_DREF_CONTROL, val);
6968 POSTING_READ(PCH_DREF_CONTROL);
6969 udelay(200);
6970 } else {
6971 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6972
6973 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6974
6975 /* Turn off CPU output */
6976 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6977
6978 I915_WRITE(PCH_DREF_CONTROL, val);
6979 POSTING_READ(PCH_DREF_CONTROL);
6980 udelay(200);
6981
6982 /* Turn off the SSC source */
6983 val &= ~DREF_SSC_SOURCE_MASK;
6984 val |= DREF_SSC_SOURCE_DISABLE;
6985
6986 /* Turn off SSC1 */
6987 val &= ~DREF_SSC1_ENABLE;
6988
6989 I915_WRITE(PCH_DREF_CONTROL, val);
6990 POSTING_READ(PCH_DREF_CONTROL);
6991 udelay(200);
6992 }
6993
6994 BUG_ON(val != final);
6995 }
6996
6997 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6998 {
6999 uint32_t tmp;
7000
7001 tmp = I915_READ(SOUTH_CHICKEN2);
7002 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7003 I915_WRITE(SOUTH_CHICKEN2, tmp);
7004
7005 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7006 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7007 DRM_ERROR("FDI mPHY reset assert timeout\n");
7008
7009 tmp = I915_READ(SOUTH_CHICKEN2);
7010 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7011 I915_WRITE(SOUTH_CHICKEN2, tmp);
7012
7013 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7014 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7015 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7016 }
7017
7018 /* WaMPhyProgramming:hsw */
7019 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7020 {
7021 uint32_t tmp;
7022
7023 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7024 tmp &= ~(0xFF << 24);
7025 tmp |= (0x12 << 24);
7026 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7027
7028 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7029 tmp |= (1 << 11);
7030 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7031
7032 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7033 tmp |= (1 << 11);
7034 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7035
7036 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7037 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7038 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7039
7040 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7041 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7042 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7043
7044 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7045 tmp &= ~(7 << 13);
7046 tmp |= (5 << 13);
7047 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7048
7049 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7050 tmp &= ~(7 << 13);
7051 tmp |= (5 << 13);
7052 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7053
7054 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7055 tmp &= ~0xFF;
7056 tmp |= 0x1C;
7057 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7058
7059 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7060 tmp &= ~0xFF;
7061 tmp |= 0x1C;
7062 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7063
7064 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7065 tmp &= ~(0xFF << 16);
7066 tmp |= (0x1C << 16);
7067 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7068
7069 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7070 tmp &= ~(0xFF << 16);
7071 tmp |= (0x1C << 16);
7072 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7073
7074 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7075 tmp |= (1 << 27);
7076 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7077
7078 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7079 tmp |= (1 << 27);
7080 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7081
7082 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7083 tmp &= ~(0xF << 28);
7084 tmp |= (4 << 28);
7085 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7086
7087 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7088 tmp &= ~(0xF << 28);
7089 tmp |= (4 << 28);
7090 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7091 }
7092
7093 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7094 * Programming" based on the parameters passed:
7095 * - Sequence to enable CLKOUT_DP
7096 * - Sequence to enable CLKOUT_DP without spread
7097 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7098 */
7099 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7100 bool with_fdi)
7101 {
7102 struct drm_i915_private *dev_priv = dev->dev_private;
7103 uint32_t reg, tmp;
7104
7105 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7106 with_spread = true;
7107 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7108 with_fdi, "LP PCH doesn't have FDI\n"))
7109 with_fdi = false;
7110
7111 mutex_lock(&dev_priv->dpio_lock);
7112
7113 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7114 tmp &= ~SBI_SSCCTL_DISABLE;
7115 tmp |= SBI_SSCCTL_PATHALT;
7116 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7117
7118 udelay(24);
7119
7120 if (with_spread) {
7121 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7122 tmp &= ~SBI_SSCCTL_PATHALT;
7123 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7124
7125 if (with_fdi) {
7126 lpt_reset_fdi_mphy(dev_priv);
7127 lpt_program_fdi_mphy(dev_priv);
7128 }
7129 }
7130
7131 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7132 SBI_GEN0 : SBI_DBUFF0;
7133 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7134 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7135 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7136
7137 mutex_unlock(&dev_priv->dpio_lock);
7138 }
7139
7140 /* Sequence to disable CLKOUT_DP */
7141 static void lpt_disable_clkout_dp(struct drm_device *dev)
7142 {
7143 struct drm_i915_private *dev_priv = dev->dev_private;
7144 uint32_t reg, tmp;
7145
7146 mutex_lock(&dev_priv->dpio_lock);
7147
7148 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7149 SBI_GEN0 : SBI_DBUFF0;
7150 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7151 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7152 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7153
7154 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7155 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7156 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7157 tmp |= SBI_SSCCTL_PATHALT;
7158 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7159 udelay(32);
7160 }
7161 tmp |= SBI_SSCCTL_DISABLE;
7162 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7163 }
7164
7165 mutex_unlock(&dev_priv->dpio_lock);
7166 }
7167
7168 static void lpt_init_pch_refclk(struct drm_device *dev)
7169 {
7170 struct intel_encoder *encoder;
7171 bool has_vga = false;
7172
7173 for_each_intel_encoder(dev, encoder) {
7174 switch (encoder->type) {
7175 case INTEL_OUTPUT_ANALOG:
7176 has_vga = true;
7177 break;
7178 default:
7179 break;
7180 }
7181 }
7182
7183 if (has_vga)
7184 lpt_enable_clkout_dp(dev, true, true);
7185 else
7186 lpt_disable_clkout_dp(dev);
7187 }
7188
7189 /*
7190 * Initialize reference clocks when the driver loads
7191 */
7192 void intel_init_pch_refclk(struct drm_device *dev)
7193 {
7194 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7195 ironlake_init_pch_refclk(dev);
7196 else if (HAS_PCH_LPT(dev))
7197 lpt_init_pch_refclk(dev);
7198 }
7199
7200 static int ironlake_get_refclk(struct drm_crtc *crtc)
7201 {
7202 struct drm_device *dev = crtc->dev;
7203 struct drm_i915_private *dev_priv = dev->dev_private;
7204 struct intel_encoder *encoder;
7205 int num_connectors = 0;
7206 bool is_lvds = false;
7207
7208 for_each_intel_encoder(dev, encoder) {
7209 if (encoder->new_crtc != to_intel_crtc(crtc))
7210 continue;
7211
7212 switch (encoder->type) {
7213 case INTEL_OUTPUT_LVDS:
7214 is_lvds = true;
7215 break;
7216 default:
7217 break;
7218 }
7219 num_connectors++;
7220 }
7221
7222 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7223 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7224 dev_priv->vbt.lvds_ssc_freq);
7225 return dev_priv->vbt.lvds_ssc_freq;
7226 }
7227
7228 return 120000;
7229 }
7230
7231 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7232 {
7233 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7235 int pipe = intel_crtc->pipe;
7236 uint32_t val;
7237
7238 val = 0;
7239
7240 switch (intel_crtc->config->pipe_bpp) {
7241 case 18:
7242 val |= PIPECONF_6BPC;
7243 break;
7244 case 24:
7245 val |= PIPECONF_8BPC;
7246 break;
7247 case 30:
7248 val |= PIPECONF_10BPC;
7249 break;
7250 case 36:
7251 val |= PIPECONF_12BPC;
7252 break;
7253 default:
7254 /* Case prevented by intel_choose_pipe_bpp_dither. */
7255 BUG();
7256 }
7257
7258 if (intel_crtc->config->dither)
7259 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7260
7261 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7262 val |= PIPECONF_INTERLACED_ILK;
7263 else
7264 val |= PIPECONF_PROGRESSIVE;
7265
7266 if (intel_crtc->config->limited_color_range)
7267 val |= PIPECONF_COLOR_RANGE_SELECT;
7268
7269 I915_WRITE(PIPECONF(pipe), val);
7270 POSTING_READ(PIPECONF(pipe));
7271 }
7272
7273 /*
7274 * Set up the pipe CSC unit.
7275 *
7276 * Currently only full range RGB to limited range RGB conversion
7277 * is supported, but eventually this should handle various
7278 * RGB<->YCbCr scenarios as well.
7279 */
7280 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7281 {
7282 struct drm_device *dev = crtc->dev;
7283 struct drm_i915_private *dev_priv = dev->dev_private;
7284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7285 int pipe = intel_crtc->pipe;
7286 uint16_t coeff = 0x7800; /* 1.0 */
7287
7288 /*
7289 * TODO: Check what kind of values actually come out of the pipe
7290 * with these coeff/postoff values and adjust to get the best
7291 * accuracy. Perhaps we even need to take the bpc value into
7292 * consideration.
7293 */
7294
7295 if (intel_crtc->config->limited_color_range)
7296 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7297
7298 /*
7299 * GY/GU and RY/RU should be the other way around according
7300 * to BSpec, but reality doesn't agree. Just set them up in
7301 * a way that results in the correct picture.
7302 */
7303 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7304 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7305
7306 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7307 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7308
7309 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7310 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7311
7312 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7313 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7314 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7315
7316 if (INTEL_INFO(dev)->gen > 6) {
7317 uint16_t postoff = 0;
7318
7319 if (intel_crtc->config->limited_color_range)
7320 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7321
7322 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7323 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7324 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7325
7326 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7327 } else {
7328 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7329
7330 if (intel_crtc->config->limited_color_range)
7331 mode |= CSC_BLACK_SCREEN_OFFSET;
7332
7333 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7334 }
7335 }
7336
7337 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7338 {
7339 struct drm_device *dev = crtc->dev;
7340 struct drm_i915_private *dev_priv = dev->dev_private;
7341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7342 enum pipe pipe = intel_crtc->pipe;
7343 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7344 uint32_t val;
7345
7346 val = 0;
7347
7348 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7349 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7350
7351 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7352 val |= PIPECONF_INTERLACED_ILK;
7353 else
7354 val |= PIPECONF_PROGRESSIVE;
7355
7356 I915_WRITE(PIPECONF(cpu_transcoder), val);
7357 POSTING_READ(PIPECONF(cpu_transcoder));
7358
7359 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7360 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7361
7362 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7363 val = 0;
7364
7365 switch (intel_crtc->config->pipe_bpp) {
7366 case 18:
7367 val |= PIPEMISC_DITHER_6_BPC;
7368 break;
7369 case 24:
7370 val |= PIPEMISC_DITHER_8_BPC;
7371 break;
7372 case 30:
7373 val |= PIPEMISC_DITHER_10_BPC;
7374 break;
7375 case 36:
7376 val |= PIPEMISC_DITHER_12_BPC;
7377 break;
7378 default:
7379 /* Case prevented by pipe_config_set_bpp. */
7380 BUG();
7381 }
7382
7383 if (intel_crtc->config->dither)
7384 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7385
7386 I915_WRITE(PIPEMISC(pipe), val);
7387 }
7388 }
7389
7390 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7391 struct intel_crtc_state *crtc_state,
7392 intel_clock_t *clock,
7393 bool *has_reduced_clock,
7394 intel_clock_t *reduced_clock)
7395 {
7396 struct drm_device *dev = crtc->dev;
7397 struct drm_i915_private *dev_priv = dev->dev_private;
7398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7399 int refclk;
7400 const intel_limit_t *limit;
7401 bool ret, is_lvds = false;
7402
7403 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7404
7405 refclk = ironlake_get_refclk(crtc);
7406
7407 /*
7408 * Returns a set of divisors for the desired target clock with the given
7409 * refclk, or FALSE. The returned values represent the clock equation:
7410 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7411 */
7412 limit = intel_limit(intel_crtc, refclk);
7413 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7414 crtc_state->port_clock,
7415 refclk, NULL, clock);
7416 if (!ret)
7417 return false;
7418
7419 if (is_lvds && dev_priv->lvds_downclock_avail) {
7420 /*
7421 * Ensure we match the reduced clock's P to the target clock.
7422 * If the clocks don't match, we can't switch the display clock
7423 * by using the FP0/FP1. In such case we will disable the LVDS
7424 * downclock feature.
7425 */
7426 *has_reduced_clock =
7427 dev_priv->display.find_dpll(limit, intel_crtc,
7428 dev_priv->lvds_downclock,
7429 refclk, clock,
7430 reduced_clock);
7431 }
7432
7433 return true;
7434 }
7435
7436 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7437 {
7438 /*
7439 * Account for spread spectrum to avoid
7440 * oversubscribing the link. Max center spread
7441 * is 2.5%; use 5% for safety's sake.
7442 */
7443 u32 bps = target_clock * bpp * 21 / 20;
7444 return DIV_ROUND_UP(bps, link_bw * 8);
7445 }
7446
7447 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7448 {
7449 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7450 }
7451
7452 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7453 struct intel_crtc_state *crtc_state,
7454 u32 *fp,
7455 intel_clock_t *reduced_clock, u32 *fp2)
7456 {
7457 struct drm_crtc *crtc = &intel_crtc->base;
7458 struct drm_device *dev = crtc->dev;
7459 struct drm_i915_private *dev_priv = dev->dev_private;
7460 struct intel_encoder *intel_encoder;
7461 uint32_t dpll;
7462 int factor, num_connectors = 0;
7463 bool is_lvds = false, is_sdvo = false;
7464
7465 for_each_intel_encoder(dev, intel_encoder) {
7466 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7467 continue;
7468
7469 switch (intel_encoder->type) {
7470 case INTEL_OUTPUT_LVDS:
7471 is_lvds = true;
7472 break;
7473 case INTEL_OUTPUT_SDVO:
7474 case INTEL_OUTPUT_HDMI:
7475 is_sdvo = true;
7476 break;
7477 default:
7478 break;
7479 }
7480
7481 num_connectors++;
7482 }
7483
7484 /* Enable autotuning of the PLL clock (if permissible) */
7485 factor = 21;
7486 if (is_lvds) {
7487 if ((intel_panel_use_ssc(dev_priv) &&
7488 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7489 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7490 factor = 25;
7491 } else if (crtc_state->sdvo_tv_clock)
7492 factor = 20;
7493
7494 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7495 *fp |= FP_CB_TUNE;
7496
7497 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7498 *fp2 |= FP_CB_TUNE;
7499
7500 dpll = 0;
7501
7502 if (is_lvds)
7503 dpll |= DPLLB_MODE_LVDS;
7504 else
7505 dpll |= DPLLB_MODE_DAC_SERIAL;
7506
7507 dpll |= (crtc_state->pixel_multiplier - 1)
7508 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7509
7510 if (is_sdvo)
7511 dpll |= DPLL_SDVO_HIGH_SPEED;
7512 if (crtc_state->has_dp_encoder)
7513 dpll |= DPLL_SDVO_HIGH_SPEED;
7514
7515 /* compute bitmask from p1 value */
7516 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7517 /* also FPA1 */
7518 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7519
7520 switch (crtc_state->dpll.p2) {
7521 case 5:
7522 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7523 break;
7524 case 7:
7525 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7526 break;
7527 case 10:
7528 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7529 break;
7530 case 14:
7531 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7532 break;
7533 }
7534
7535 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7536 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7537 else
7538 dpll |= PLL_REF_INPUT_DREFCLK;
7539
7540 return dpll | DPLL_VCO_ENABLE;
7541 }
7542
7543 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7544 struct intel_crtc_state *crtc_state)
7545 {
7546 struct drm_device *dev = crtc->base.dev;
7547 intel_clock_t clock, reduced_clock;
7548 u32 dpll = 0, fp = 0, fp2 = 0;
7549 bool ok, has_reduced_clock = false;
7550 bool is_lvds = false;
7551 struct intel_shared_dpll *pll;
7552
7553 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7554
7555 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7556 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7557
7558 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7559 &has_reduced_clock, &reduced_clock);
7560 if (!ok && !crtc_state->clock_set) {
7561 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7562 return -EINVAL;
7563 }
7564 /* Compat-code for transition, will disappear. */
7565 if (!crtc_state->clock_set) {
7566 crtc_state->dpll.n = clock.n;
7567 crtc_state->dpll.m1 = clock.m1;
7568 crtc_state->dpll.m2 = clock.m2;
7569 crtc_state->dpll.p1 = clock.p1;
7570 crtc_state->dpll.p2 = clock.p2;
7571 }
7572
7573 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7574 if (crtc_state->has_pch_encoder) {
7575 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7576 if (has_reduced_clock)
7577 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7578
7579 dpll = ironlake_compute_dpll(crtc, crtc_state,
7580 &fp, &reduced_clock,
7581 has_reduced_clock ? &fp2 : NULL);
7582
7583 crtc_state->dpll_hw_state.dpll = dpll;
7584 crtc_state->dpll_hw_state.fp0 = fp;
7585 if (has_reduced_clock)
7586 crtc_state->dpll_hw_state.fp1 = fp2;
7587 else
7588 crtc_state->dpll_hw_state.fp1 = fp;
7589
7590 pll = intel_get_shared_dpll(crtc, crtc_state);
7591 if (pll == NULL) {
7592 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7593 pipe_name(crtc->pipe));
7594 return -EINVAL;
7595 }
7596 }
7597
7598 if (is_lvds && has_reduced_clock && i915.powersave)
7599 crtc->lowfreq_avail = true;
7600 else
7601 crtc->lowfreq_avail = false;
7602
7603 return 0;
7604 }
7605
7606 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7607 struct intel_link_m_n *m_n)
7608 {
7609 struct drm_device *dev = crtc->base.dev;
7610 struct drm_i915_private *dev_priv = dev->dev_private;
7611 enum pipe pipe = crtc->pipe;
7612
7613 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7614 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7615 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7616 & ~TU_SIZE_MASK;
7617 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7618 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7619 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7620 }
7621
7622 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7623 enum transcoder transcoder,
7624 struct intel_link_m_n *m_n,
7625 struct intel_link_m_n *m2_n2)
7626 {
7627 struct drm_device *dev = crtc->base.dev;
7628 struct drm_i915_private *dev_priv = dev->dev_private;
7629 enum pipe pipe = crtc->pipe;
7630
7631 if (INTEL_INFO(dev)->gen >= 5) {
7632 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7633 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7634 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7635 & ~TU_SIZE_MASK;
7636 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7637 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7638 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7639 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7640 * gen < 8) and if DRRS is supported (to make sure the
7641 * registers are not unnecessarily read).
7642 */
7643 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7644 crtc->config->has_drrs) {
7645 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7646 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7647 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7648 & ~TU_SIZE_MASK;
7649 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7650 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7651 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7652 }
7653 } else {
7654 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7655 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7656 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7657 & ~TU_SIZE_MASK;
7658 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7659 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7660 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7661 }
7662 }
7663
7664 void intel_dp_get_m_n(struct intel_crtc *crtc,
7665 struct intel_crtc_state *pipe_config)
7666 {
7667 if (pipe_config->has_pch_encoder)
7668 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7669 else
7670 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7671 &pipe_config->dp_m_n,
7672 &pipe_config->dp_m2_n2);
7673 }
7674
7675 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7676 struct intel_crtc_state *pipe_config)
7677 {
7678 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7679 &pipe_config->fdi_m_n, NULL);
7680 }
7681
7682 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7683 struct intel_crtc_state *pipe_config)
7684 {
7685 struct drm_device *dev = crtc->base.dev;
7686 struct drm_i915_private *dev_priv = dev->dev_private;
7687 uint32_t tmp;
7688
7689 tmp = I915_READ(PS_CTL(crtc->pipe));
7690
7691 if (tmp & PS_ENABLE) {
7692 pipe_config->pch_pfit.enabled = true;
7693 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7694 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7695 }
7696 }
7697
7698 static void
7699 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7700 struct intel_initial_plane_config *plane_config)
7701 {
7702 struct drm_device *dev = crtc->base.dev;
7703 struct drm_i915_private *dev_priv = dev->dev_private;
7704 u32 val, base, offset, stride_mult;
7705 int pipe = crtc->pipe;
7706 int fourcc, pixel_format;
7707 int aligned_height;
7708 struct drm_framebuffer *fb;
7709 struct intel_framebuffer *intel_fb;
7710
7711 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7712 if (!intel_fb) {
7713 DRM_DEBUG_KMS("failed to alloc fb\n");
7714 return;
7715 }
7716
7717 fb = &intel_fb->base;
7718
7719 val = I915_READ(PLANE_CTL(pipe, 0));
7720 if (!(val & PLANE_CTL_ENABLE))
7721 goto error;
7722
7723 if (val & PLANE_CTL_TILED_MASK) {
7724 plane_config->tiling = I915_TILING_X;
7725 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7726 }
7727
7728 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7729 fourcc = skl_format_to_fourcc(pixel_format,
7730 val & PLANE_CTL_ORDER_RGBX,
7731 val & PLANE_CTL_ALPHA_MASK);
7732 fb->pixel_format = fourcc;
7733 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7734
7735 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7736 plane_config->base = base;
7737
7738 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7739
7740 val = I915_READ(PLANE_SIZE(pipe, 0));
7741 fb->height = ((val >> 16) & 0xfff) + 1;
7742 fb->width = ((val >> 0) & 0x1fff) + 1;
7743
7744 val = I915_READ(PLANE_STRIDE(pipe, 0));
7745 switch (plane_config->tiling) {
7746 case I915_TILING_NONE:
7747 stride_mult = 64;
7748 break;
7749 case I915_TILING_X:
7750 stride_mult = 512;
7751 break;
7752 default:
7753 MISSING_CASE(plane_config->tiling);
7754 goto error;
7755 }
7756 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7757
7758 aligned_height = intel_fb_align_height(dev, fb->height,
7759 fb->pixel_format,
7760 fb->modifier[0]);
7761
7762 plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
7763
7764 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7765 pipe_name(pipe), fb->width, fb->height,
7766 fb->bits_per_pixel, base, fb->pitches[0],
7767 plane_config->size);
7768
7769 plane_config->fb = intel_fb;
7770 return;
7771
7772 error:
7773 kfree(fb);
7774 }
7775
7776 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7777 struct intel_crtc_state *pipe_config)
7778 {
7779 struct drm_device *dev = crtc->base.dev;
7780 struct drm_i915_private *dev_priv = dev->dev_private;
7781 uint32_t tmp;
7782
7783 tmp = I915_READ(PF_CTL(crtc->pipe));
7784
7785 if (tmp & PF_ENABLE) {
7786 pipe_config->pch_pfit.enabled = true;
7787 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7788 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7789
7790 /* We currently do not free assignements of panel fitters on
7791 * ivb/hsw (since we don't use the higher upscaling modes which
7792 * differentiates them) so just WARN about this case for now. */
7793 if (IS_GEN7(dev)) {
7794 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7795 PF_PIPE_SEL_IVB(crtc->pipe));
7796 }
7797 }
7798 }
7799
7800 static void
7801 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7802 struct intel_initial_plane_config *plane_config)
7803 {
7804 struct drm_device *dev = crtc->base.dev;
7805 struct drm_i915_private *dev_priv = dev->dev_private;
7806 u32 val, base, offset;
7807 int pipe = crtc->pipe;
7808 int fourcc, pixel_format;
7809 int aligned_height;
7810 struct drm_framebuffer *fb;
7811 struct intel_framebuffer *intel_fb;
7812
7813 val = I915_READ(DSPCNTR(pipe));
7814 if (!(val & DISPLAY_PLANE_ENABLE))
7815 return;
7816
7817 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7818 if (!intel_fb) {
7819 DRM_DEBUG_KMS("failed to alloc fb\n");
7820 return;
7821 }
7822
7823 fb = &intel_fb->base;
7824
7825 if (INTEL_INFO(dev)->gen >= 4) {
7826 if (val & DISPPLANE_TILED) {
7827 plane_config->tiling = I915_TILING_X;
7828 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7829 }
7830 }
7831
7832 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7833 fourcc = i9xx_format_to_fourcc(pixel_format);
7834 fb->pixel_format = fourcc;
7835 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7836
7837 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7838 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7839 offset = I915_READ(DSPOFFSET(pipe));
7840 } else {
7841 if (plane_config->tiling)
7842 offset = I915_READ(DSPTILEOFF(pipe));
7843 else
7844 offset = I915_READ(DSPLINOFF(pipe));
7845 }
7846 plane_config->base = base;
7847
7848 val = I915_READ(PIPESRC(pipe));
7849 fb->width = ((val >> 16) & 0xfff) + 1;
7850 fb->height = ((val >> 0) & 0xfff) + 1;
7851
7852 val = I915_READ(DSPSTRIDE(pipe));
7853 fb->pitches[0] = val & 0xffffffc0;
7854
7855 aligned_height = intel_fb_align_height(dev, fb->height,
7856 fb->pixel_format,
7857 fb->modifier[0]);
7858
7859 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
7860
7861 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7862 pipe_name(pipe), fb->width, fb->height,
7863 fb->bits_per_pixel, base, fb->pitches[0],
7864 plane_config->size);
7865
7866 plane_config->fb = intel_fb;
7867 }
7868
7869 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7870 struct intel_crtc_state *pipe_config)
7871 {
7872 struct drm_device *dev = crtc->base.dev;
7873 struct drm_i915_private *dev_priv = dev->dev_private;
7874 uint32_t tmp;
7875
7876 if (!intel_display_power_is_enabled(dev_priv,
7877 POWER_DOMAIN_PIPE(crtc->pipe)))
7878 return false;
7879
7880 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7881 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7882
7883 tmp = I915_READ(PIPECONF(crtc->pipe));
7884 if (!(tmp & PIPECONF_ENABLE))
7885 return false;
7886
7887 switch (tmp & PIPECONF_BPC_MASK) {
7888 case PIPECONF_6BPC:
7889 pipe_config->pipe_bpp = 18;
7890 break;
7891 case PIPECONF_8BPC:
7892 pipe_config->pipe_bpp = 24;
7893 break;
7894 case PIPECONF_10BPC:
7895 pipe_config->pipe_bpp = 30;
7896 break;
7897 case PIPECONF_12BPC:
7898 pipe_config->pipe_bpp = 36;
7899 break;
7900 default:
7901 break;
7902 }
7903
7904 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7905 pipe_config->limited_color_range = true;
7906
7907 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7908 struct intel_shared_dpll *pll;
7909
7910 pipe_config->has_pch_encoder = true;
7911
7912 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7913 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7914 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7915
7916 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7917
7918 if (HAS_PCH_IBX(dev_priv->dev)) {
7919 pipe_config->shared_dpll =
7920 (enum intel_dpll_id) crtc->pipe;
7921 } else {
7922 tmp = I915_READ(PCH_DPLL_SEL);
7923 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7924 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7925 else
7926 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7927 }
7928
7929 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7930
7931 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7932 &pipe_config->dpll_hw_state));
7933
7934 tmp = pipe_config->dpll_hw_state.dpll;
7935 pipe_config->pixel_multiplier =
7936 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7937 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7938
7939 ironlake_pch_clock_get(crtc, pipe_config);
7940 } else {
7941 pipe_config->pixel_multiplier = 1;
7942 }
7943
7944 intel_get_pipe_timings(crtc, pipe_config);
7945
7946 ironlake_get_pfit_config(crtc, pipe_config);
7947
7948 return true;
7949 }
7950
7951 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7952 {
7953 struct drm_device *dev = dev_priv->dev;
7954 struct intel_crtc *crtc;
7955
7956 for_each_intel_crtc(dev, crtc)
7957 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7958 pipe_name(crtc->pipe));
7959
7960 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7961 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7962 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7963 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7964 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7965 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7966 "CPU PWM1 enabled\n");
7967 if (IS_HASWELL(dev))
7968 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7969 "CPU PWM2 enabled\n");
7970 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7971 "PCH PWM1 enabled\n");
7972 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7973 "Utility pin enabled\n");
7974 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7975
7976 /*
7977 * In theory we can still leave IRQs enabled, as long as only the HPD
7978 * interrupts remain enabled. We used to check for that, but since it's
7979 * gen-specific and since we only disable LCPLL after we fully disable
7980 * the interrupts, the check below should be enough.
7981 */
7982 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7983 }
7984
7985 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7986 {
7987 struct drm_device *dev = dev_priv->dev;
7988
7989 if (IS_HASWELL(dev))
7990 return I915_READ(D_COMP_HSW);
7991 else
7992 return I915_READ(D_COMP_BDW);
7993 }
7994
7995 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7996 {
7997 struct drm_device *dev = dev_priv->dev;
7998
7999 if (IS_HASWELL(dev)) {
8000 mutex_lock(&dev_priv->rps.hw_lock);
8001 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8002 val))
8003 DRM_ERROR("Failed to write to D_COMP\n");
8004 mutex_unlock(&dev_priv->rps.hw_lock);
8005 } else {
8006 I915_WRITE(D_COMP_BDW, val);
8007 POSTING_READ(D_COMP_BDW);
8008 }
8009 }
8010
8011 /*
8012 * This function implements pieces of two sequences from BSpec:
8013 * - Sequence for display software to disable LCPLL
8014 * - Sequence for display software to allow package C8+
8015 * The steps implemented here are just the steps that actually touch the LCPLL
8016 * register. Callers should take care of disabling all the display engine
8017 * functions, doing the mode unset, fixing interrupts, etc.
8018 */
8019 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8020 bool switch_to_fclk, bool allow_power_down)
8021 {
8022 uint32_t val;
8023
8024 assert_can_disable_lcpll(dev_priv);
8025
8026 val = I915_READ(LCPLL_CTL);
8027
8028 if (switch_to_fclk) {
8029 val |= LCPLL_CD_SOURCE_FCLK;
8030 I915_WRITE(LCPLL_CTL, val);
8031
8032 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8033 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8034 DRM_ERROR("Switching to FCLK failed\n");
8035
8036 val = I915_READ(LCPLL_CTL);
8037 }
8038
8039 val |= LCPLL_PLL_DISABLE;
8040 I915_WRITE(LCPLL_CTL, val);
8041 POSTING_READ(LCPLL_CTL);
8042
8043 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8044 DRM_ERROR("LCPLL still locked\n");
8045
8046 val = hsw_read_dcomp(dev_priv);
8047 val |= D_COMP_COMP_DISABLE;
8048 hsw_write_dcomp(dev_priv, val);
8049 ndelay(100);
8050
8051 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8052 1))
8053 DRM_ERROR("D_COMP RCOMP still in progress\n");
8054
8055 if (allow_power_down) {
8056 val = I915_READ(LCPLL_CTL);
8057 val |= LCPLL_POWER_DOWN_ALLOW;
8058 I915_WRITE(LCPLL_CTL, val);
8059 POSTING_READ(LCPLL_CTL);
8060 }
8061 }
8062
8063 /*
8064 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8065 * source.
8066 */
8067 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8068 {
8069 uint32_t val;
8070
8071 val = I915_READ(LCPLL_CTL);
8072
8073 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8074 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8075 return;
8076
8077 /*
8078 * Make sure we're not on PC8 state before disabling PC8, otherwise
8079 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8080 */
8081 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8082
8083 if (val & LCPLL_POWER_DOWN_ALLOW) {
8084 val &= ~LCPLL_POWER_DOWN_ALLOW;
8085 I915_WRITE(LCPLL_CTL, val);
8086 POSTING_READ(LCPLL_CTL);
8087 }
8088
8089 val = hsw_read_dcomp(dev_priv);
8090 val |= D_COMP_COMP_FORCE;
8091 val &= ~D_COMP_COMP_DISABLE;
8092 hsw_write_dcomp(dev_priv, val);
8093
8094 val = I915_READ(LCPLL_CTL);
8095 val &= ~LCPLL_PLL_DISABLE;
8096 I915_WRITE(LCPLL_CTL, val);
8097
8098 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8099 DRM_ERROR("LCPLL not locked yet\n");
8100
8101 if (val & LCPLL_CD_SOURCE_FCLK) {
8102 val = I915_READ(LCPLL_CTL);
8103 val &= ~LCPLL_CD_SOURCE_FCLK;
8104 I915_WRITE(LCPLL_CTL, val);
8105
8106 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8107 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8108 DRM_ERROR("Switching back to LCPLL failed\n");
8109 }
8110
8111 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8112 }
8113
8114 /*
8115 * Package states C8 and deeper are really deep PC states that can only be
8116 * reached when all the devices on the system allow it, so even if the graphics
8117 * device allows PC8+, it doesn't mean the system will actually get to these
8118 * states. Our driver only allows PC8+ when going into runtime PM.
8119 *
8120 * The requirements for PC8+ are that all the outputs are disabled, the power
8121 * well is disabled and most interrupts are disabled, and these are also
8122 * requirements for runtime PM. When these conditions are met, we manually do
8123 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8124 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8125 * hang the machine.
8126 *
8127 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8128 * the state of some registers, so when we come back from PC8+ we need to
8129 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8130 * need to take care of the registers kept by RC6. Notice that this happens even
8131 * if we don't put the device in PCI D3 state (which is what currently happens
8132 * because of the runtime PM support).
8133 *
8134 * For more, read "Display Sequences for Package C8" on the hardware
8135 * documentation.
8136 */
8137 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8138 {
8139 struct drm_device *dev = dev_priv->dev;
8140 uint32_t val;
8141
8142 DRM_DEBUG_KMS("Enabling package C8+\n");
8143
8144 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8145 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8146 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8147 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8148 }
8149
8150 lpt_disable_clkout_dp(dev);
8151 hsw_disable_lcpll(dev_priv, true, true);
8152 }
8153
8154 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8155 {
8156 struct drm_device *dev = dev_priv->dev;
8157 uint32_t val;
8158
8159 DRM_DEBUG_KMS("Disabling package C8+\n");
8160
8161 hsw_restore_lcpll(dev_priv);
8162 lpt_init_pch_refclk(dev);
8163
8164 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8165 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8166 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8167 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8168 }
8169
8170 intel_prepare_ddi(dev);
8171 }
8172
8173 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8174 struct intel_crtc_state *crtc_state)
8175 {
8176 if (!intel_ddi_pll_select(crtc, crtc_state))
8177 return -EINVAL;
8178
8179 crtc->lowfreq_avail = false;
8180
8181 return 0;
8182 }
8183
8184 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8185 enum port port,
8186 struct intel_crtc_state *pipe_config)
8187 {
8188 u32 temp, dpll_ctl1;
8189
8190 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8191 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8192
8193 switch (pipe_config->ddi_pll_sel) {
8194 case SKL_DPLL0:
8195 /*
8196 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8197 * of the shared DPLL framework and thus needs to be read out
8198 * separately
8199 */
8200 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8201 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8202 break;
8203 case SKL_DPLL1:
8204 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8205 break;
8206 case SKL_DPLL2:
8207 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8208 break;
8209 case SKL_DPLL3:
8210 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8211 break;
8212 }
8213 }
8214
8215 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8216 enum port port,
8217 struct intel_crtc_state *pipe_config)
8218 {
8219 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8220
8221 switch (pipe_config->ddi_pll_sel) {
8222 case PORT_CLK_SEL_WRPLL1:
8223 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8224 break;
8225 case PORT_CLK_SEL_WRPLL2:
8226 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8227 break;
8228 }
8229 }
8230
8231 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8232 struct intel_crtc_state *pipe_config)
8233 {
8234 struct drm_device *dev = crtc->base.dev;
8235 struct drm_i915_private *dev_priv = dev->dev_private;
8236 struct intel_shared_dpll *pll;
8237 enum port port;
8238 uint32_t tmp;
8239
8240 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8241
8242 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8243
8244 if (IS_SKYLAKE(dev))
8245 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8246 else
8247 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8248
8249 if (pipe_config->shared_dpll >= 0) {
8250 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8251
8252 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8253 &pipe_config->dpll_hw_state));
8254 }
8255
8256 /*
8257 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8258 * DDI E. So just check whether this pipe is wired to DDI E and whether
8259 * the PCH transcoder is on.
8260 */
8261 if (INTEL_INFO(dev)->gen < 9 &&
8262 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8263 pipe_config->has_pch_encoder = true;
8264
8265 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8266 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8267 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8268
8269 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8270 }
8271 }
8272
8273 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8274 struct intel_crtc_state *pipe_config)
8275 {
8276 struct drm_device *dev = crtc->base.dev;
8277 struct drm_i915_private *dev_priv = dev->dev_private;
8278 enum intel_display_power_domain pfit_domain;
8279 uint32_t tmp;
8280
8281 if (!intel_display_power_is_enabled(dev_priv,
8282 POWER_DOMAIN_PIPE(crtc->pipe)))
8283 return false;
8284
8285 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8286 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8287
8288 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8289 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8290 enum pipe trans_edp_pipe;
8291 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8292 default:
8293 WARN(1, "unknown pipe linked to edp transcoder\n");
8294 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8295 case TRANS_DDI_EDP_INPUT_A_ON:
8296 trans_edp_pipe = PIPE_A;
8297 break;
8298 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8299 trans_edp_pipe = PIPE_B;
8300 break;
8301 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8302 trans_edp_pipe = PIPE_C;
8303 break;
8304 }
8305
8306 if (trans_edp_pipe == crtc->pipe)
8307 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8308 }
8309
8310 if (!intel_display_power_is_enabled(dev_priv,
8311 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8312 return false;
8313
8314 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8315 if (!(tmp & PIPECONF_ENABLE))
8316 return false;
8317
8318 haswell_get_ddi_port_state(crtc, pipe_config);
8319
8320 intel_get_pipe_timings(crtc, pipe_config);
8321
8322 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8323 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8324 if (IS_SKYLAKE(dev))
8325 skylake_get_pfit_config(crtc, pipe_config);
8326 else
8327 ironlake_get_pfit_config(crtc, pipe_config);
8328 }
8329
8330 if (IS_HASWELL(dev))
8331 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8332 (I915_READ(IPS_CTL) & IPS_ENABLE);
8333
8334 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8335 pipe_config->pixel_multiplier =
8336 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8337 } else {
8338 pipe_config->pixel_multiplier = 1;
8339 }
8340
8341 return true;
8342 }
8343
8344 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8345 {
8346 struct drm_device *dev = crtc->dev;
8347 struct drm_i915_private *dev_priv = dev->dev_private;
8348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8349 uint32_t cntl = 0, size = 0;
8350
8351 if (base) {
8352 unsigned int width = intel_crtc->cursor_width;
8353 unsigned int height = intel_crtc->cursor_height;
8354 unsigned int stride = roundup_pow_of_two(width) * 4;
8355
8356 switch (stride) {
8357 default:
8358 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8359 width, stride);
8360 stride = 256;
8361 /* fallthrough */
8362 case 256:
8363 case 512:
8364 case 1024:
8365 case 2048:
8366 break;
8367 }
8368
8369 cntl |= CURSOR_ENABLE |
8370 CURSOR_GAMMA_ENABLE |
8371 CURSOR_FORMAT_ARGB |
8372 CURSOR_STRIDE(stride);
8373
8374 size = (height << 12) | width;
8375 }
8376
8377 if (intel_crtc->cursor_cntl != 0 &&
8378 (intel_crtc->cursor_base != base ||
8379 intel_crtc->cursor_size != size ||
8380 intel_crtc->cursor_cntl != cntl)) {
8381 /* On these chipsets we can only modify the base/size/stride
8382 * whilst the cursor is disabled.
8383 */
8384 I915_WRITE(_CURACNTR, 0);
8385 POSTING_READ(_CURACNTR);
8386 intel_crtc->cursor_cntl = 0;
8387 }
8388
8389 if (intel_crtc->cursor_base != base) {
8390 I915_WRITE(_CURABASE, base);
8391 intel_crtc->cursor_base = base;
8392 }
8393
8394 if (intel_crtc->cursor_size != size) {
8395 I915_WRITE(CURSIZE, size);
8396 intel_crtc->cursor_size = size;
8397 }
8398
8399 if (intel_crtc->cursor_cntl != cntl) {
8400 I915_WRITE(_CURACNTR, cntl);
8401 POSTING_READ(_CURACNTR);
8402 intel_crtc->cursor_cntl = cntl;
8403 }
8404 }
8405
8406 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8407 {
8408 struct drm_device *dev = crtc->dev;
8409 struct drm_i915_private *dev_priv = dev->dev_private;
8410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8411 int pipe = intel_crtc->pipe;
8412 uint32_t cntl;
8413
8414 cntl = 0;
8415 if (base) {
8416 cntl = MCURSOR_GAMMA_ENABLE;
8417 switch (intel_crtc->cursor_width) {
8418 case 64:
8419 cntl |= CURSOR_MODE_64_ARGB_AX;
8420 break;
8421 case 128:
8422 cntl |= CURSOR_MODE_128_ARGB_AX;
8423 break;
8424 case 256:
8425 cntl |= CURSOR_MODE_256_ARGB_AX;
8426 break;
8427 default:
8428 MISSING_CASE(intel_crtc->cursor_width);
8429 return;
8430 }
8431 cntl |= pipe << 28; /* Connect to correct pipe */
8432
8433 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8434 cntl |= CURSOR_PIPE_CSC_ENABLE;
8435 }
8436
8437 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8438 cntl |= CURSOR_ROTATE_180;
8439
8440 if (intel_crtc->cursor_cntl != cntl) {
8441 I915_WRITE(CURCNTR(pipe), cntl);
8442 POSTING_READ(CURCNTR(pipe));
8443 intel_crtc->cursor_cntl = cntl;
8444 }
8445
8446 /* and commit changes on next vblank */
8447 I915_WRITE(CURBASE(pipe), base);
8448 POSTING_READ(CURBASE(pipe));
8449
8450 intel_crtc->cursor_base = base;
8451 }
8452
8453 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8454 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8455 bool on)
8456 {
8457 struct drm_device *dev = crtc->dev;
8458 struct drm_i915_private *dev_priv = dev->dev_private;
8459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8460 int pipe = intel_crtc->pipe;
8461 int x = crtc->cursor_x;
8462 int y = crtc->cursor_y;
8463 u32 base = 0, pos = 0;
8464
8465 if (on)
8466 base = intel_crtc->cursor_addr;
8467
8468 if (x >= intel_crtc->config->pipe_src_w)
8469 base = 0;
8470
8471 if (y >= intel_crtc->config->pipe_src_h)
8472 base = 0;
8473
8474 if (x < 0) {
8475 if (x + intel_crtc->cursor_width <= 0)
8476 base = 0;
8477
8478 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8479 x = -x;
8480 }
8481 pos |= x << CURSOR_X_SHIFT;
8482
8483 if (y < 0) {
8484 if (y + intel_crtc->cursor_height <= 0)
8485 base = 0;
8486
8487 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8488 y = -y;
8489 }
8490 pos |= y << CURSOR_Y_SHIFT;
8491
8492 if (base == 0 && intel_crtc->cursor_base == 0)
8493 return;
8494
8495 I915_WRITE(CURPOS(pipe), pos);
8496
8497 /* ILK+ do this automagically */
8498 if (HAS_GMCH_DISPLAY(dev) &&
8499 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8500 base += (intel_crtc->cursor_height *
8501 intel_crtc->cursor_width - 1) * 4;
8502 }
8503
8504 if (IS_845G(dev) || IS_I865G(dev))
8505 i845_update_cursor(crtc, base);
8506 else
8507 i9xx_update_cursor(crtc, base);
8508 }
8509
8510 static bool cursor_size_ok(struct drm_device *dev,
8511 uint32_t width, uint32_t height)
8512 {
8513 if (width == 0 || height == 0)
8514 return false;
8515
8516 /*
8517 * 845g/865g are special in that they are only limited by
8518 * the width of their cursors, the height is arbitrary up to
8519 * the precision of the register. Everything else requires
8520 * square cursors, limited to a few power-of-two sizes.
8521 */
8522 if (IS_845G(dev) || IS_I865G(dev)) {
8523 if ((width & 63) != 0)
8524 return false;
8525
8526 if (width > (IS_845G(dev) ? 64 : 512))
8527 return false;
8528
8529 if (height > 1023)
8530 return false;
8531 } else {
8532 switch (width | height) {
8533 case 256:
8534 case 128:
8535 if (IS_GEN2(dev))
8536 return false;
8537 case 64:
8538 break;
8539 default:
8540 return false;
8541 }
8542 }
8543
8544 return true;
8545 }
8546
8547 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8548 u16 *blue, uint32_t start, uint32_t size)
8549 {
8550 int end = (start + size > 256) ? 256 : start + size, i;
8551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8552
8553 for (i = start; i < end; i++) {
8554 intel_crtc->lut_r[i] = red[i] >> 8;
8555 intel_crtc->lut_g[i] = green[i] >> 8;
8556 intel_crtc->lut_b[i] = blue[i] >> 8;
8557 }
8558
8559 intel_crtc_load_lut(crtc);
8560 }
8561
8562 /* VESA 640x480x72Hz mode to set on the pipe */
8563 static struct drm_display_mode load_detect_mode = {
8564 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8565 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8566 };
8567
8568 struct drm_framebuffer *
8569 __intel_framebuffer_create(struct drm_device *dev,
8570 struct drm_mode_fb_cmd2 *mode_cmd,
8571 struct drm_i915_gem_object *obj)
8572 {
8573 struct intel_framebuffer *intel_fb;
8574 int ret;
8575
8576 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8577 if (!intel_fb) {
8578 drm_gem_object_unreference(&obj->base);
8579 return ERR_PTR(-ENOMEM);
8580 }
8581
8582 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8583 if (ret)
8584 goto err;
8585
8586 return &intel_fb->base;
8587 err:
8588 drm_gem_object_unreference(&obj->base);
8589 kfree(intel_fb);
8590
8591 return ERR_PTR(ret);
8592 }
8593
8594 static struct drm_framebuffer *
8595 intel_framebuffer_create(struct drm_device *dev,
8596 struct drm_mode_fb_cmd2 *mode_cmd,
8597 struct drm_i915_gem_object *obj)
8598 {
8599 struct drm_framebuffer *fb;
8600 int ret;
8601
8602 ret = i915_mutex_lock_interruptible(dev);
8603 if (ret)
8604 return ERR_PTR(ret);
8605 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8606 mutex_unlock(&dev->struct_mutex);
8607
8608 return fb;
8609 }
8610
8611 static u32
8612 intel_framebuffer_pitch_for_width(int width, int bpp)
8613 {
8614 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8615 return ALIGN(pitch, 64);
8616 }
8617
8618 static u32
8619 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8620 {
8621 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8622 return PAGE_ALIGN(pitch * mode->vdisplay);
8623 }
8624
8625 static struct drm_framebuffer *
8626 intel_framebuffer_create_for_mode(struct drm_device *dev,
8627 struct drm_display_mode *mode,
8628 int depth, int bpp)
8629 {
8630 struct drm_i915_gem_object *obj;
8631 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8632
8633 obj = i915_gem_alloc_object(dev,
8634 intel_framebuffer_size_for_mode(mode, bpp));
8635 if (obj == NULL)
8636 return ERR_PTR(-ENOMEM);
8637
8638 mode_cmd.width = mode->hdisplay;
8639 mode_cmd.height = mode->vdisplay;
8640 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8641 bpp);
8642 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8643
8644 return intel_framebuffer_create(dev, &mode_cmd, obj);
8645 }
8646
8647 static struct drm_framebuffer *
8648 mode_fits_in_fbdev(struct drm_device *dev,
8649 struct drm_display_mode *mode)
8650 {
8651 #ifdef CONFIG_DRM_I915_FBDEV
8652 struct drm_i915_private *dev_priv = dev->dev_private;
8653 struct drm_i915_gem_object *obj;
8654 struct drm_framebuffer *fb;
8655
8656 if (!dev_priv->fbdev)
8657 return NULL;
8658
8659 if (!dev_priv->fbdev->fb)
8660 return NULL;
8661
8662 obj = dev_priv->fbdev->fb->obj;
8663 BUG_ON(!obj);
8664
8665 fb = &dev_priv->fbdev->fb->base;
8666 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8667 fb->bits_per_pixel))
8668 return NULL;
8669
8670 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8671 return NULL;
8672
8673 return fb;
8674 #else
8675 return NULL;
8676 #endif
8677 }
8678
8679 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8680 struct drm_display_mode *mode,
8681 struct intel_load_detect_pipe *old,
8682 struct drm_modeset_acquire_ctx *ctx)
8683 {
8684 struct intel_crtc *intel_crtc;
8685 struct intel_encoder *intel_encoder =
8686 intel_attached_encoder(connector);
8687 struct drm_crtc *possible_crtc;
8688 struct drm_encoder *encoder = &intel_encoder->base;
8689 struct drm_crtc *crtc = NULL;
8690 struct drm_device *dev = encoder->dev;
8691 struct drm_framebuffer *fb;
8692 struct drm_mode_config *config = &dev->mode_config;
8693 int ret, i = -1;
8694
8695 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8696 connector->base.id, connector->name,
8697 encoder->base.id, encoder->name);
8698
8699 retry:
8700 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8701 if (ret)
8702 goto fail_unlock;
8703
8704 /*
8705 * Algorithm gets a little messy:
8706 *
8707 * - if the connector already has an assigned crtc, use it (but make
8708 * sure it's on first)
8709 *
8710 * - try to find the first unused crtc that can drive this connector,
8711 * and use that if we find one
8712 */
8713
8714 /* See if we already have a CRTC for this connector */
8715 if (encoder->crtc) {
8716 crtc = encoder->crtc;
8717
8718 ret = drm_modeset_lock(&crtc->mutex, ctx);
8719 if (ret)
8720 goto fail_unlock;
8721 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8722 if (ret)
8723 goto fail_unlock;
8724
8725 old->dpms_mode = connector->dpms;
8726 old->load_detect_temp = false;
8727
8728 /* Make sure the crtc and connector are running */
8729 if (connector->dpms != DRM_MODE_DPMS_ON)
8730 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8731
8732 return true;
8733 }
8734
8735 /* Find an unused one (if possible) */
8736 for_each_crtc(dev, possible_crtc) {
8737 i++;
8738 if (!(encoder->possible_crtcs & (1 << i)))
8739 continue;
8740 if (possible_crtc->state->enable)
8741 continue;
8742 /* This can occur when applying the pipe A quirk on resume. */
8743 if (to_intel_crtc(possible_crtc)->new_enabled)
8744 continue;
8745
8746 crtc = possible_crtc;
8747 break;
8748 }
8749
8750 /*
8751 * If we didn't find an unused CRTC, don't use any.
8752 */
8753 if (!crtc) {
8754 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8755 goto fail_unlock;
8756 }
8757
8758 ret = drm_modeset_lock(&crtc->mutex, ctx);
8759 if (ret)
8760 goto fail_unlock;
8761 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8762 if (ret)
8763 goto fail_unlock;
8764 intel_encoder->new_crtc = to_intel_crtc(crtc);
8765 to_intel_connector(connector)->new_encoder = intel_encoder;
8766
8767 intel_crtc = to_intel_crtc(crtc);
8768 intel_crtc->new_enabled = true;
8769 intel_crtc->new_config = intel_crtc->config;
8770 old->dpms_mode = connector->dpms;
8771 old->load_detect_temp = true;
8772 old->release_fb = NULL;
8773
8774 if (!mode)
8775 mode = &load_detect_mode;
8776
8777 /* We need a framebuffer large enough to accommodate all accesses
8778 * that the plane may generate whilst we perform load detection.
8779 * We can not rely on the fbcon either being present (we get called
8780 * during its initialisation to detect all boot displays, or it may
8781 * not even exist) or that it is large enough to satisfy the
8782 * requested mode.
8783 */
8784 fb = mode_fits_in_fbdev(dev, mode);
8785 if (fb == NULL) {
8786 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8787 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8788 old->release_fb = fb;
8789 } else
8790 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8791 if (IS_ERR(fb)) {
8792 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8793 goto fail;
8794 }
8795
8796 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8797 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8798 if (old->release_fb)
8799 old->release_fb->funcs->destroy(old->release_fb);
8800 goto fail;
8801 }
8802
8803 /* let the connector get through one full cycle before testing */
8804 intel_wait_for_vblank(dev, intel_crtc->pipe);
8805 return true;
8806
8807 fail:
8808 intel_crtc->new_enabled = crtc->state->enable;
8809 if (intel_crtc->new_enabled)
8810 intel_crtc->new_config = intel_crtc->config;
8811 else
8812 intel_crtc->new_config = NULL;
8813 fail_unlock:
8814 if (ret == -EDEADLK) {
8815 drm_modeset_backoff(ctx);
8816 goto retry;
8817 }
8818
8819 return false;
8820 }
8821
8822 void intel_release_load_detect_pipe(struct drm_connector *connector,
8823 struct intel_load_detect_pipe *old)
8824 {
8825 struct intel_encoder *intel_encoder =
8826 intel_attached_encoder(connector);
8827 struct drm_encoder *encoder = &intel_encoder->base;
8828 struct drm_crtc *crtc = encoder->crtc;
8829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8830
8831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8832 connector->base.id, connector->name,
8833 encoder->base.id, encoder->name);
8834
8835 if (old->load_detect_temp) {
8836 to_intel_connector(connector)->new_encoder = NULL;
8837 intel_encoder->new_crtc = NULL;
8838 intel_crtc->new_enabled = false;
8839 intel_crtc->new_config = NULL;
8840 intel_set_mode(crtc, NULL, 0, 0, NULL);
8841
8842 if (old->release_fb) {
8843 drm_framebuffer_unregister_private(old->release_fb);
8844 drm_framebuffer_unreference(old->release_fb);
8845 }
8846
8847 return;
8848 }
8849
8850 /* Switch crtc and encoder back off if necessary */
8851 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8852 connector->funcs->dpms(connector, old->dpms_mode);
8853 }
8854
8855 static int i9xx_pll_refclk(struct drm_device *dev,
8856 const struct intel_crtc_state *pipe_config)
8857 {
8858 struct drm_i915_private *dev_priv = dev->dev_private;
8859 u32 dpll = pipe_config->dpll_hw_state.dpll;
8860
8861 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8862 return dev_priv->vbt.lvds_ssc_freq;
8863 else if (HAS_PCH_SPLIT(dev))
8864 return 120000;
8865 else if (!IS_GEN2(dev))
8866 return 96000;
8867 else
8868 return 48000;
8869 }
8870
8871 /* Returns the clock of the currently programmed mode of the given pipe. */
8872 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8873 struct intel_crtc_state *pipe_config)
8874 {
8875 struct drm_device *dev = crtc->base.dev;
8876 struct drm_i915_private *dev_priv = dev->dev_private;
8877 int pipe = pipe_config->cpu_transcoder;
8878 u32 dpll = pipe_config->dpll_hw_state.dpll;
8879 u32 fp;
8880 intel_clock_t clock;
8881 int refclk = i9xx_pll_refclk(dev, pipe_config);
8882
8883 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8884 fp = pipe_config->dpll_hw_state.fp0;
8885 else
8886 fp = pipe_config->dpll_hw_state.fp1;
8887
8888 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8889 if (IS_PINEVIEW(dev)) {
8890 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8891 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8892 } else {
8893 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8894 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8895 }
8896
8897 if (!IS_GEN2(dev)) {
8898 if (IS_PINEVIEW(dev))
8899 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8900 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8901 else
8902 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8903 DPLL_FPA01_P1_POST_DIV_SHIFT);
8904
8905 switch (dpll & DPLL_MODE_MASK) {
8906 case DPLLB_MODE_DAC_SERIAL:
8907 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8908 5 : 10;
8909 break;
8910 case DPLLB_MODE_LVDS:
8911 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8912 7 : 14;
8913 break;
8914 default:
8915 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8916 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8917 return;
8918 }
8919
8920 if (IS_PINEVIEW(dev))
8921 pineview_clock(refclk, &clock);
8922 else
8923 i9xx_clock(refclk, &clock);
8924 } else {
8925 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8926 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8927
8928 if (is_lvds) {
8929 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8930 DPLL_FPA01_P1_POST_DIV_SHIFT);
8931
8932 if (lvds & LVDS_CLKB_POWER_UP)
8933 clock.p2 = 7;
8934 else
8935 clock.p2 = 14;
8936 } else {
8937 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8938 clock.p1 = 2;
8939 else {
8940 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8941 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8942 }
8943 if (dpll & PLL_P2_DIVIDE_BY_4)
8944 clock.p2 = 4;
8945 else
8946 clock.p2 = 2;
8947 }
8948
8949 i9xx_clock(refclk, &clock);
8950 }
8951
8952 /*
8953 * This value includes pixel_multiplier. We will use
8954 * port_clock to compute adjusted_mode.crtc_clock in the
8955 * encoder's get_config() function.
8956 */
8957 pipe_config->port_clock = clock.dot;
8958 }
8959
8960 int intel_dotclock_calculate(int link_freq,
8961 const struct intel_link_m_n *m_n)
8962 {
8963 /*
8964 * The calculation for the data clock is:
8965 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8966 * But we want to avoid losing precison if possible, so:
8967 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8968 *
8969 * and the link clock is simpler:
8970 * link_clock = (m * link_clock) / n
8971 */
8972
8973 if (!m_n->link_n)
8974 return 0;
8975
8976 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8977 }
8978
8979 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8980 struct intel_crtc_state *pipe_config)
8981 {
8982 struct drm_device *dev = crtc->base.dev;
8983
8984 /* read out port_clock from the DPLL */
8985 i9xx_crtc_clock_get(crtc, pipe_config);
8986
8987 /*
8988 * This value does not include pixel_multiplier.
8989 * We will check that port_clock and adjusted_mode.crtc_clock
8990 * agree once we know their relationship in the encoder's
8991 * get_config() function.
8992 */
8993 pipe_config->base.adjusted_mode.crtc_clock =
8994 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8995 &pipe_config->fdi_m_n);
8996 }
8997
8998 /** Returns the currently programmed mode of the given pipe. */
8999 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9000 struct drm_crtc *crtc)
9001 {
9002 struct drm_i915_private *dev_priv = dev->dev_private;
9003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9004 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9005 struct drm_display_mode *mode;
9006 struct intel_crtc_state pipe_config;
9007 int htot = I915_READ(HTOTAL(cpu_transcoder));
9008 int hsync = I915_READ(HSYNC(cpu_transcoder));
9009 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9010 int vsync = I915_READ(VSYNC(cpu_transcoder));
9011 enum pipe pipe = intel_crtc->pipe;
9012
9013 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9014 if (!mode)
9015 return NULL;
9016
9017 /*
9018 * Construct a pipe_config sufficient for getting the clock info
9019 * back out of crtc_clock_get.
9020 *
9021 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9022 * to use a real value here instead.
9023 */
9024 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9025 pipe_config.pixel_multiplier = 1;
9026 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9027 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9028 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9029 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9030
9031 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9032 mode->hdisplay = (htot & 0xffff) + 1;
9033 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9034 mode->hsync_start = (hsync & 0xffff) + 1;
9035 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9036 mode->vdisplay = (vtot & 0xffff) + 1;
9037 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9038 mode->vsync_start = (vsync & 0xffff) + 1;
9039 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9040
9041 drm_mode_set_name(mode);
9042
9043 return mode;
9044 }
9045
9046 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9047 {
9048 struct drm_device *dev = crtc->dev;
9049 struct drm_i915_private *dev_priv = dev->dev_private;
9050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9051
9052 if (!HAS_GMCH_DISPLAY(dev))
9053 return;
9054
9055 if (!dev_priv->lvds_downclock_avail)
9056 return;
9057
9058 /*
9059 * Since this is called by a timer, we should never get here in
9060 * the manual case.
9061 */
9062 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9063 int pipe = intel_crtc->pipe;
9064 int dpll_reg = DPLL(pipe);
9065 int dpll;
9066
9067 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9068
9069 assert_panel_unlocked(dev_priv, pipe);
9070
9071 dpll = I915_READ(dpll_reg);
9072 dpll |= DISPLAY_RATE_SELECT_FPA1;
9073 I915_WRITE(dpll_reg, dpll);
9074 intel_wait_for_vblank(dev, pipe);
9075 dpll = I915_READ(dpll_reg);
9076 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9077 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9078 }
9079
9080 }
9081
9082 void intel_mark_busy(struct drm_device *dev)
9083 {
9084 struct drm_i915_private *dev_priv = dev->dev_private;
9085
9086 if (dev_priv->mm.busy)
9087 return;
9088
9089 intel_runtime_pm_get(dev_priv);
9090 i915_update_gfx_val(dev_priv);
9091 dev_priv->mm.busy = true;
9092 }
9093
9094 void intel_mark_idle(struct drm_device *dev)
9095 {
9096 struct drm_i915_private *dev_priv = dev->dev_private;
9097 struct drm_crtc *crtc;
9098
9099 if (!dev_priv->mm.busy)
9100 return;
9101
9102 dev_priv->mm.busy = false;
9103
9104 if (!i915.powersave)
9105 goto out;
9106
9107 for_each_crtc(dev, crtc) {
9108 if (!crtc->primary->fb)
9109 continue;
9110
9111 intel_decrease_pllclock(crtc);
9112 }
9113
9114 if (INTEL_INFO(dev)->gen >= 6)
9115 gen6_rps_idle(dev->dev_private);
9116
9117 out:
9118 intel_runtime_pm_put(dev_priv);
9119 }
9120
9121 static void intel_crtc_set_state(struct intel_crtc *crtc,
9122 struct intel_crtc_state *crtc_state)
9123 {
9124 kfree(crtc->config);
9125 crtc->config = crtc_state;
9126 crtc->base.state = &crtc_state->base;
9127 }
9128
9129 static void intel_crtc_destroy(struct drm_crtc *crtc)
9130 {
9131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9132 struct drm_device *dev = crtc->dev;
9133 struct intel_unpin_work *work;
9134
9135 spin_lock_irq(&dev->event_lock);
9136 work = intel_crtc->unpin_work;
9137 intel_crtc->unpin_work = NULL;
9138 spin_unlock_irq(&dev->event_lock);
9139
9140 if (work) {
9141 cancel_work_sync(&work->work);
9142 kfree(work);
9143 }
9144
9145 intel_crtc_set_state(intel_crtc, NULL);
9146 drm_crtc_cleanup(crtc);
9147
9148 kfree(intel_crtc);
9149 }
9150
9151 static void intel_unpin_work_fn(struct work_struct *__work)
9152 {
9153 struct intel_unpin_work *work =
9154 container_of(__work, struct intel_unpin_work, work);
9155 struct drm_device *dev = work->crtc->dev;
9156 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9157
9158 mutex_lock(&dev->struct_mutex);
9159 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9160 drm_gem_object_unreference(&work->pending_flip_obj->base);
9161 drm_framebuffer_unreference(work->old_fb);
9162
9163 intel_fbc_update(dev);
9164
9165 if (work->flip_queued_req)
9166 i915_gem_request_assign(&work->flip_queued_req, NULL);
9167 mutex_unlock(&dev->struct_mutex);
9168
9169 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9170
9171 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9172 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9173
9174 kfree(work);
9175 }
9176
9177 static void do_intel_finish_page_flip(struct drm_device *dev,
9178 struct drm_crtc *crtc)
9179 {
9180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9181 struct intel_unpin_work *work;
9182 unsigned long flags;
9183
9184 /* Ignore early vblank irqs */
9185 if (intel_crtc == NULL)
9186 return;
9187
9188 /*
9189 * This is called both by irq handlers and the reset code (to complete
9190 * lost pageflips) so needs the full irqsave spinlocks.
9191 */
9192 spin_lock_irqsave(&dev->event_lock, flags);
9193 work = intel_crtc->unpin_work;
9194
9195 /* Ensure we don't miss a work->pending update ... */
9196 smp_rmb();
9197
9198 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9199 spin_unlock_irqrestore(&dev->event_lock, flags);
9200 return;
9201 }
9202
9203 page_flip_completed(intel_crtc);
9204
9205 spin_unlock_irqrestore(&dev->event_lock, flags);
9206 }
9207
9208 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9209 {
9210 struct drm_i915_private *dev_priv = dev->dev_private;
9211 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9212
9213 do_intel_finish_page_flip(dev, crtc);
9214 }
9215
9216 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9217 {
9218 struct drm_i915_private *dev_priv = dev->dev_private;
9219 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9220
9221 do_intel_finish_page_flip(dev, crtc);
9222 }
9223
9224 /* Is 'a' after or equal to 'b'? */
9225 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9226 {
9227 return !((a - b) & 0x80000000);
9228 }
9229
9230 static bool page_flip_finished(struct intel_crtc *crtc)
9231 {
9232 struct drm_device *dev = crtc->base.dev;
9233 struct drm_i915_private *dev_priv = dev->dev_private;
9234
9235 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9236 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9237 return true;
9238
9239 /*
9240 * The relevant registers doen't exist on pre-ctg.
9241 * As the flip done interrupt doesn't trigger for mmio
9242 * flips on gmch platforms, a flip count check isn't
9243 * really needed there. But since ctg has the registers,
9244 * include it in the check anyway.
9245 */
9246 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9247 return true;
9248
9249 /*
9250 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9251 * used the same base address. In that case the mmio flip might
9252 * have completed, but the CS hasn't even executed the flip yet.
9253 *
9254 * A flip count check isn't enough as the CS might have updated
9255 * the base address just after start of vblank, but before we
9256 * managed to process the interrupt. This means we'd complete the
9257 * CS flip too soon.
9258 *
9259 * Combining both checks should get us a good enough result. It may
9260 * still happen that the CS flip has been executed, but has not
9261 * yet actually completed. But in case the base address is the same
9262 * anyway, we don't really care.
9263 */
9264 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9265 crtc->unpin_work->gtt_offset &&
9266 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9267 crtc->unpin_work->flip_count);
9268 }
9269
9270 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9271 {
9272 struct drm_i915_private *dev_priv = dev->dev_private;
9273 struct intel_crtc *intel_crtc =
9274 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9275 unsigned long flags;
9276
9277
9278 /*
9279 * This is called both by irq handlers and the reset code (to complete
9280 * lost pageflips) so needs the full irqsave spinlocks.
9281 *
9282 * NB: An MMIO update of the plane base pointer will also
9283 * generate a page-flip completion irq, i.e. every modeset
9284 * is also accompanied by a spurious intel_prepare_page_flip().
9285 */
9286 spin_lock_irqsave(&dev->event_lock, flags);
9287 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9288 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9289 spin_unlock_irqrestore(&dev->event_lock, flags);
9290 }
9291
9292 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9293 {
9294 /* Ensure that the work item is consistent when activating it ... */
9295 smp_wmb();
9296 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9297 /* and that it is marked active as soon as the irq could fire. */
9298 smp_wmb();
9299 }
9300
9301 static int intel_gen2_queue_flip(struct drm_device *dev,
9302 struct drm_crtc *crtc,
9303 struct drm_framebuffer *fb,
9304 struct drm_i915_gem_object *obj,
9305 struct intel_engine_cs *ring,
9306 uint32_t flags)
9307 {
9308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9309 u32 flip_mask;
9310 int ret;
9311
9312 ret = intel_ring_begin(ring, 6);
9313 if (ret)
9314 return ret;
9315
9316 /* Can't queue multiple flips, so wait for the previous
9317 * one to finish before executing the next.
9318 */
9319 if (intel_crtc->plane)
9320 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9321 else
9322 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9323 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9324 intel_ring_emit(ring, MI_NOOP);
9325 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9326 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9327 intel_ring_emit(ring, fb->pitches[0]);
9328 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9329 intel_ring_emit(ring, 0); /* aux display base address, unused */
9330
9331 intel_mark_page_flip_active(intel_crtc);
9332 __intel_ring_advance(ring);
9333 return 0;
9334 }
9335
9336 static int intel_gen3_queue_flip(struct drm_device *dev,
9337 struct drm_crtc *crtc,
9338 struct drm_framebuffer *fb,
9339 struct drm_i915_gem_object *obj,
9340 struct intel_engine_cs *ring,
9341 uint32_t flags)
9342 {
9343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9344 u32 flip_mask;
9345 int ret;
9346
9347 ret = intel_ring_begin(ring, 6);
9348 if (ret)
9349 return ret;
9350
9351 if (intel_crtc->plane)
9352 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9353 else
9354 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9355 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9356 intel_ring_emit(ring, MI_NOOP);
9357 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9358 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9359 intel_ring_emit(ring, fb->pitches[0]);
9360 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9361 intel_ring_emit(ring, MI_NOOP);
9362
9363 intel_mark_page_flip_active(intel_crtc);
9364 __intel_ring_advance(ring);
9365 return 0;
9366 }
9367
9368 static int intel_gen4_queue_flip(struct drm_device *dev,
9369 struct drm_crtc *crtc,
9370 struct drm_framebuffer *fb,
9371 struct drm_i915_gem_object *obj,
9372 struct intel_engine_cs *ring,
9373 uint32_t flags)
9374 {
9375 struct drm_i915_private *dev_priv = dev->dev_private;
9376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9377 uint32_t pf, pipesrc;
9378 int ret;
9379
9380 ret = intel_ring_begin(ring, 4);
9381 if (ret)
9382 return ret;
9383
9384 /* i965+ uses the linear or tiled offsets from the
9385 * Display Registers (which do not change across a page-flip)
9386 * so we need only reprogram the base address.
9387 */
9388 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9389 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9390 intel_ring_emit(ring, fb->pitches[0]);
9391 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9392 obj->tiling_mode);
9393
9394 /* XXX Enabling the panel-fitter across page-flip is so far
9395 * untested on non-native modes, so ignore it for now.
9396 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9397 */
9398 pf = 0;
9399 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9400 intel_ring_emit(ring, pf | pipesrc);
9401
9402 intel_mark_page_flip_active(intel_crtc);
9403 __intel_ring_advance(ring);
9404 return 0;
9405 }
9406
9407 static int intel_gen6_queue_flip(struct drm_device *dev,
9408 struct drm_crtc *crtc,
9409 struct drm_framebuffer *fb,
9410 struct drm_i915_gem_object *obj,
9411 struct intel_engine_cs *ring,
9412 uint32_t flags)
9413 {
9414 struct drm_i915_private *dev_priv = dev->dev_private;
9415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9416 uint32_t pf, pipesrc;
9417 int ret;
9418
9419 ret = intel_ring_begin(ring, 4);
9420 if (ret)
9421 return ret;
9422
9423 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9424 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9425 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9426 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9427
9428 /* Contrary to the suggestions in the documentation,
9429 * "Enable Panel Fitter" does not seem to be required when page
9430 * flipping with a non-native mode, and worse causes a normal
9431 * modeset to fail.
9432 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9433 */
9434 pf = 0;
9435 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9436 intel_ring_emit(ring, pf | pipesrc);
9437
9438 intel_mark_page_flip_active(intel_crtc);
9439 __intel_ring_advance(ring);
9440 return 0;
9441 }
9442
9443 static int intel_gen7_queue_flip(struct drm_device *dev,
9444 struct drm_crtc *crtc,
9445 struct drm_framebuffer *fb,
9446 struct drm_i915_gem_object *obj,
9447 struct intel_engine_cs *ring,
9448 uint32_t flags)
9449 {
9450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9451 uint32_t plane_bit = 0;
9452 int len, ret;
9453
9454 switch (intel_crtc->plane) {
9455 case PLANE_A:
9456 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9457 break;
9458 case PLANE_B:
9459 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9460 break;
9461 case PLANE_C:
9462 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9463 break;
9464 default:
9465 WARN_ONCE(1, "unknown plane in flip command\n");
9466 return -ENODEV;
9467 }
9468
9469 len = 4;
9470 if (ring->id == RCS) {
9471 len += 6;
9472 /*
9473 * On Gen 8, SRM is now taking an extra dword to accommodate
9474 * 48bits addresses, and we need a NOOP for the batch size to
9475 * stay even.
9476 */
9477 if (IS_GEN8(dev))
9478 len += 2;
9479 }
9480
9481 /*
9482 * BSpec MI_DISPLAY_FLIP for IVB:
9483 * "The full packet must be contained within the same cache line."
9484 *
9485 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9486 * cacheline, if we ever start emitting more commands before
9487 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9488 * then do the cacheline alignment, and finally emit the
9489 * MI_DISPLAY_FLIP.
9490 */
9491 ret = intel_ring_cacheline_align(ring);
9492 if (ret)
9493 return ret;
9494
9495 ret = intel_ring_begin(ring, len);
9496 if (ret)
9497 return ret;
9498
9499 /* Unmask the flip-done completion message. Note that the bspec says that
9500 * we should do this for both the BCS and RCS, and that we must not unmask
9501 * more than one flip event at any time (or ensure that one flip message
9502 * can be sent by waiting for flip-done prior to queueing new flips).
9503 * Experimentation says that BCS works despite DERRMR masking all
9504 * flip-done completion events and that unmasking all planes at once
9505 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9506 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9507 */
9508 if (ring->id == RCS) {
9509 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9510 intel_ring_emit(ring, DERRMR);
9511 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9512 DERRMR_PIPEB_PRI_FLIP_DONE |
9513 DERRMR_PIPEC_PRI_FLIP_DONE));
9514 if (IS_GEN8(dev))
9515 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9516 MI_SRM_LRM_GLOBAL_GTT);
9517 else
9518 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9519 MI_SRM_LRM_GLOBAL_GTT);
9520 intel_ring_emit(ring, DERRMR);
9521 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9522 if (IS_GEN8(dev)) {
9523 intel_ring_emit(ring, 0);
9524 intel_ring_emit(ring, MI_NOOP);
9525 }
9526 }
9527
9528 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9529 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9530 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9531 intel_ring_emit(ring, (MI_NOOP));
9532
9533 intel_mark_page_flip_active(intel_crtc);
9534 __intel_ring_advance(ring);
9535 return 0;
9536 }
9537
9538 static bool use_mmio_flip(struct intel_engine_cs *ring,
9539 struct drm_i915_gem_object *obj)
9540 {
9541 /*
9542 * This is not being used for older platforms, because
9543 * non-availability of flip done interrupt forces us to use
9544 * CS flips. Older platforms derive flip done using some clever
9545 * tricks involving the flip_pending status bits and vblank irqs.
9546 * So using MMIO flips there would disrupt this mechanism.
9547 */
9548
9549 if (ring == NULL)
9550 return true;
9551
9552 if (INTEL_INFO(ring->dev)->gen < 5)
9553 return false;
9554
9555 if (i915.use_mmio_flip < 0)
9556 return false;
9557 else if (i915.use_mmio_flip > 0)
9558 return true;
9559 else if (i915.enable_execlists)
9560 return true;
9561 else
9562 return ring != i915_gem_request_get_ring(obj->last_read_req);
9563 }
9564
9565 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9566 {
9567 struct drm_device *dev = intel_crtc->base.dev;
9568 struct drm_i915_private *dev_priv = dev->dev_private;
9569 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9570 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9571 struct drm_i915_gem_object *obj = intel_fb->obj;
9572 const enum pipe pipe = intel_crtc->pipe;
9573 u32 ctl, stride;
9574
9575 ctl = I915_READ(PLANE_CTL(pipe, 0));
9576 ctl &= ~PLANE_CTL_TILED_MASK;
9577 if (obj->tiling_mode == I915_TILING_X)
9578 ctl |= PLANE_CTL_TILED_X;
9579
9580 /*
9581 * The stride is either expressed as a multiple of 64 bytes chunks for
9582 * linear buffers or in number of tiles for tiled buffers.
9583 */
9584 stride = fb->pitches[0] >> 6;
9585 if (obj->tiling_mode == I915_TILING_X)
9586 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9587
9588 /*
9589 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9590 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9591 */
9592 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9593 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9594
9595 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9596 POSTING_READ(PLANE_SURF(pipe, 0));
9597 }
9598
9599 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9600 {
9601 struct drm_device *dev = intel_crtc->base.dev;
9602 struct drm_i915_private *dev_priv = dev->dev_private;
9603 struct intel_framebuffer *intel_fb =
9604 to_intel_framebuffer(intel_crtc->base.primary->fb);
9605 struct drm_i915_gem_object *obj = intel_fb->obj;
9606 u32 dspcntr;
9607 u32 reg;
9608
9609 reg = DSPCNTR(intel_crtc->plane);
9610 dspcntr = I915_READ(reg);
9611
9612 if (obj->tiling_mode != I915_TILING_NONE)
9613 dspcntr |= DISPPLANE_TILED;
9614 else
9615 dspcntr &= ~DISPPLANE_TILED;
9616
9617 I915_WRITE(reg, dspcntr);
9618
9619 I915_WRITE(DSPSURF(intel_crtc->plane),
9620 intel_crtc->unpin_work->gtt_offset);
9621 POSTING_READ(DSPSURF(intel_crtc->plane));
9622
9623 }
9624
9625 /*
9626 * XXX: This is the temporary way to update the plane registers until we get
9627 * around to using the usual plane update functions for MMIO flips
9628 */
9629 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9630 {
9631 struct drm_device *dev = intel_crtc->base.dev;
9632 bool atomic_update;
9633 u32 start_vbl_count;
9634
9635 intel_mark_page_flip_active(intel_crtc);
9636
9637 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9638
9639 if (INTEL_INFO(dev)->gen >= 9)
9640 skl_do_mmio_flip(intel_crtc);
9641 else
9642 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9643 ilk_do_mmio_flip(intel_crtc);
9644
9645 if (atomic_update)
9646 intel_pipe_update_end(intel_crtc, start_vbl_count);
9647 }
9648
9649 static void intel_mmio_flip_work_func(struct work_struct *work)
9650 {
9651 struct intel_crtc *crtc =
9652 container_of(work, struct intel_crtc, mmio_flip.work);
9653 struct intel_mmio_flip *mmio_flip;
9654
9655 mmio_flip = &crtc->mmio_flip;
9656 if (mmio_flip->req)
9657 WARN_ON(__i915_wait_request(mmio_flip->req,
9658 crtc->reset_counter,
9659 false, NULL, NULL) != 0);
9660
9661 intel_do_mmio_flip(crtc);
9662 if (mmio_flip->req) {
9663 mutex_lock(&crtc->base.dev->struct_mutex);
9664 i915_gem_request_assign(&mmio_flip->req, NULL);
9665 mutex_unlock(&crtc->base.dev->struct_mutex);
9666 }
9667 }
9668
9669 static int intel_queue_mmio_flip(struct drm_device *dev,
9670 struct drm_crtc *crtc,
9671 struct drm_framebuffer *fb,
9672 struct drm_i915_gem_object *obj,
9673 struct intel_engine_cs *ring,
9674 uint32_t flags)
9675 {
9676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9677
9678 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9679 obj->last_write_req);
9680
9681 schedule_work(&intel_crtc->mmio_flip.work);
9682
9683 return 0;
9684 }
9685
9686 static int intel_default_queue_flip(struct drm_device *dev,
9687 struct drm_crtc *crtc,
9688 struct drm_framebuffer *fb,
9689 struct drm_i915_gem_object *obj,
9690 struct intel_engine_cs *ring,
9691 uint32_t flags)
9692 {
9693 return -ENODEV;
9694 }
9695
9696 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9697 struct drm_crtc *crtc)
9698 {
9699 struct drm_i915_private *dev_priv = dev->dev_private;
9700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9701 struct intel_unpin_work *work = intel_crtc->unpin_work;
9702 u32 addr;
9703
9704 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9705 return true;
9706
9707 if (!work->enable_stall_check)
9708 return false;
9709
9710 if (work->flip_ready_vblank == 0) {
9711 if (work->flip_queued_req &&
9712 !i915_gem_request_completed(work->flip_queued_req, true))
9713 return false;
9714
9715 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9716 }
9717
9718 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9719 return false;
9720
9721 /* Potential stall - if we see that the flip has happened,
9722 * assume a missed interrupt. */
9723 if (INTEL_INFO(dev)->gen >= 4)
9724 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9725 else
9726 addr = I915_READ(DSPADDR(intel_crtc->plane));
9727
9728 /* There is a potential issue here with a false positive after a flip
9729 * to the same address. We could address this by checking for a
9730 * non-incrementing frame counter.
9731 */
9732 return addr == work->gtt_offset;
9733 }
9734
9735 void intel_check_page_flip(struct drm_device *dev, int pipe)
9736 {
9737 struct drm_i915_private *dev_priv = dev->dev_private;
9738 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9740
9741 WARN_ON(!in_irq());
9742
9743 if (crtc == NULL)
9744 return;
9745
9746 spin_lock(&dev->event_lock);
9747 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9748 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9749 intel_crtc->unpin_work->flip_queued_vblank,
9750 drm_vblank_count(dev, pipe));
9751 page_flip_completed(intel_crtc);
9752 }
9753 spin_unlock(&dev->event_lock);
9754 }
9755
9756 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9757 struct drm_framebuffer *fb,
9758 struct drm_pending_vblank_event *event,
9759 uint32_t page_flip_flags)
9760 {
9761 struct drm_device *dev = crtc->dev;
9762 struct drm_i915_private *dev_priv = dev->dev_private;
9763 struct drm_framebuffer *old_fb = crtc->primary->fb;
9764 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9766 struct drm_plane *primary = crtc->primary;
9767 enum pipe pipe = intel_crtc->pipe;
9768 struct intel_unpin_work *work;
9769 struct intel_engine_cs *ring;
9770 int ret;
9771
9772 /*
9773 * drm_mode_page_flip_ioctl() should already catch this, but double
9774 * check to be safe. In the future we may enable pageflipping from
9775 * a disabled primary plane.
9776 */
9777 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9778 return -EBUSY;
9779
9780 /* Can't change pixel format via MI display flips. */
9781 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9782 return -EINVAL;
9783
9784 /*
9785 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9786 * Note that pitch changes could also affect these register.
9787 */
9788 if (INTEL_INFO(dev)->gen > 3 &&
9789 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9790 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9791 return -EINVAL;
9792
9793 if (i915_terminally_wedged(&dev_priv->gpu_error))
9794 goto out_hang;
9795
9796 work = kzalloc(sizeof(*work), GFP_KERNEL);
9797 if (work == NULL)
9798 return -ENOMEM;
9799
9800 work->event = event;
9801 work->crtc = crtc;
9802 work->old_fb = old_fb;
9803 INIT_WORK(&work->work, intel_unpin_work_fn);
9804
9805 ret = drm_crtc_vblank_get(crtc);
9806 if (ret)
9807 goto free_work;
9808
9809 /* We borrow the event spin lock for protecting unpin_work */
9810 spin_lock_irq(&dev->event_lock);
9811 if (intel_crtc->unpin_work) {
9812 /* Before declaring the flip queue wedged, check if
9813 * the hardware completed the operation behind our backs.
9814 */
9815 if (__intel_pageflip_stall_check(dev, crtc)) {
9816 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9817 page_flip_completed(intel_crtc);
9818 } else {
9819 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9820 spin_unlock_irq(&dev->event_lock);
9821
9822 drm_crtc_vblank_put(crtc);
9823 kfree(work);
9824 return -EBUSY;
9825 }
9826 }
9827 intel_crtc->unpin_work = work;
9828 spin_unlock_irq(&dev->event_lock);
9829
9830 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9831 flush_workqueue(dev_priv->wq);
9832
9833 ret = i915_mutex_lock_interruptible(dev);
9834 if (ret)
9835 goto cleanup;
9836
9837 /* Reference the objects for the scheduled work. */
9838 drm_framebuffer_reference(work->old_fb);
9839 drm_gem_object_reference(&obj->base);
9840
9841 crtc->primary->fb = fb;
9842 update_state_fb(crtc->primary);
9843
9844 work->pending_flip_obj = obj;
9845
9846 atomic_inc(&intel_crtc->unpin_work_count);
9847 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9848
9849 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9850 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9851
9852 if (IS_VALLEYVIEW(dev)) {
9853 ring = &dev_priv->ring[BCS];
9854 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9855 /* vlv: DISPLAY_FLIP fails to change tiling */
9856 ring = NULL;
9857 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9858 ring = &dev_priv->ring[BCS];
9859 } else if (INTEL_INFO(dev)->gen >= 7) {
9860 ring = i915_gem_request_get_ring(obj->last_read_req);
9861 if (ring == NULL || ring->id != RCS)
9862 ring = &dev_priv->ring[BCS];
9863 } else {
9864 ring = &dev_priv->ring[RCS];
9865 }
9866
9867 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9868 if (ret)
9869 goto cleanup_pending;
9870
9871 work->gtt_offset =
9872 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9873
9874 if (use_mmio_flip(ring, obj)) {
9875 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9876 page_flip_flags);
9877 if (ret)
9878 goto cleanup_unpin;
9879
9880 i915_gem_request_assign(&work->flip_queued_req,
9881 obj->last_write_req);
9882 } else {
9883 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9884 page_flip_flags);
9885 if (ret)
9886 goto cleanup_unpin;
9887
9888 i915_gem_request_assign(&work->flip_queued_req,
9889 intel_ring_get_request(ring));
9890 }
9891
9892 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
9893 work->enable_stall_check = true;
9894
9895 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9896 INTEL_FRONTBUFFER_PRIMARY(pipe));
9897
9898 intel_fbc_disable(dev);
9899 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9900 mutex_unlock(&dev->struct_mutex);
9901
9902 trace_i915_flip_request(intel_crtc->plane, obj);
9903
9904 return 0;
9905
9906 cleanup_unpin:
9907 intel_unpin_fb_obj(obj);
9908 cleanup_pending:
9909 atomic_dec(&intel_crtc->unpin_work_count);
9910 crtc->primary->fb = old_fb;
9911 update_state_fb(crtc->primary);
9912 drm_framebuffer_unreference(work->old_fb);
9913 drm_gem_object_unreference(&obj->base);
9914 mutex_unlock(&dev->struct_mutex);
9915
9916 cleanup:
9917 spin_lock_irq(&dev->event_lock);
9918 intel_crtc->unpin_work = NULL;
9919 spin_unlock_irq(&dev->event_lock);
9920
9921 drm_crtc_vblank_put(crtc);
9922 free_work:
9923 kfree(work);
9924
9925 if (ret == -EIO) {
9926 out_hang:
9927 ret = intel_plane_restore(primary);
9928 if (ret == 0 && event) {
9929 spin_lock_irq(&dev->event_lock);
9930 drm_send_vblank_event(dev, pipe, event);
9931 spin_unlock_irq(&dev->event_lock);
9932 }
9933 }
9934 return ret;
9935 }
9936
9937 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9938 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9939 .load_lut = intel_crtc_load_lut,
9940 .atomic_begin = intel_begin_crtc_commit,
9941 .atomic_flush = intel_finish_crtc_commit,
9942 };
9943
9944 /**
9945 * intel_modeset_update_staged_output_state
9946 *
9947 * Updates the staged output configuration state, e.g. after we've read out the
9948 * current hw state.
9949 */
9950 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9951 {
9952 struct intel_crtc *crtc;
9953 struct intel_encoder *encoder;
9954 struct intel_connector *connector;
9955
9956 list_for_each_entry(connector, &dev->mode_config.connector_list,
9957 base.head) {
9958 connector->new_encoder =
9959 to_intel_encoder(connector->base.encoder);
9960 }
9961
9962 for_each_intel_encoder(dev, encoder) {
9963 encoder->new_crtc =
9964 to_intel_crtc(encoder->base.crtc);
9965 }
9966
9967 for_each_intel_crtc(dev, crtc) {
9968 crtc->new_enabled = crtc->base.state->enable;
9969
9970 if (crtc->new_enabled)
9971 crtc->new_config = crtc->config;
9972 else
9973 crtc->new_config = NULL;
9974 }
9975 }
9976
9977 /**
9978 * intel_modeset_commit_output_state
9979 *
9980 * This function copies the stage display pipe configuration to the real one.
9981 */
9982 static void intel_modeset_commit_output_state(struct drm_device *dev)
9983 {
9984 struct intel_crtc *crtc;
9985 struct intel_encoder *encoder;
9986 struct intel_connector *connector;
9987
9988 list_for_each_entry(connector, &dev->mode_config.connector_list,
9989 base.head) {
9990 connector->base.encoder = &connector->new_encoder->base;
9991 }
9992
9993 for_each_intel_encoder(dev, encoder) {
9994 encoder->base.crtc = &encoder->new_crtc->base;
9995 }
9996
9997 for_each_intel_crtc(dev, crtc) {
9998 crtc->base.state->enable = crtc->new_enabled;
9999 crtc->base.enabled = crtc->new_enabled;
10000 }
10001 }
10002
10003 static void
10004 connected_sink_compute_bpp(struct intel_connector *connector,
10005 struct intel_crtc_state *pipe_config)
10006 {
10007 int bpp = pipe_config->pipe_bpp;
10008
10009 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10010 connector->base.base.id,
10011 connector->base.name);
10012
10013 /* Don't use an invalid EDID bpc value */
10014 if (connector->base.display_info.bpc &&
10015 connector->base.display_info.bpc * 3 < bpp) {
10016 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10017 bpp, connector->base.display_info.bpc*3);
10018 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10019 }
10020
10021 /* Clamp bpp to 8 on screens without EDID 1.4 */
10022 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10023 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10024 bpp);
10025 pipe_config->pipe_bpp = 24;
10026 }
10027 }
10028
10029 static int
10030 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10031 struct drm_framebuffer *fb,
10032 struct intel_crtc_state *pipe_config)
10033 {
10034 struct drm_device *dev = crtc->base.dev;
10035 struct intel_connector *connector;
10036 int bpp;
10037
10038 switch (fb->pixel_format) {
10039 case DRM_FORMAT_C8:
10040 bpp = 8*3; /* since we go through a colormap */
10041 break;
10042 case DRM_FORMAT_XRGB1555:
10043 case DRM_FORMAT_ARGB1555:
10044 /* checked in intel_framebuffer_init already */
10045 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10046 return -EINVAL;
10047 case DRM_FORMAT_RGB565:
10048 bpp = 6*3; /* min is 18bpp */
10049 break;
10050 case DRM_FORMAT_XBGR8888:
10051 case DRM_FORMAT_ABGR8888:
10052 /* checked in intel_framebuffer_init already */
10053 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10054 return -EINVAL;
10055 case DRM_FORMAT_XRGB8888:
10056 case DRM_FORMAT_ARGB8888:
10057 bpp = 8*3;
10058 break;
10059 case DRM_FORMAT_XRGB2101010:
10060 case DRM_FORMAT_ARGB2101010:
10061 case DRM_FORMAT_XBGR2101010:
10062 case DRM_FORMAT_ABGR2101010:
10063 /* checked in intel_framebuffer_init already */
10064 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10065 return -EINVAL;
10066 bpp = 10*3;
10067 break;
10068 /* TODO: gen4+ supports 16 bpc floating point, too. */
10069 default:
10070 DRM_DEBUG_KMS("unsupported depth\n");
10071 return -EINVAL;
10072 }
10073
10074 pipe_config->pipe_bpp = bpp;
10075
10076 /* Clamp display bpp to EDID value */
10077 list_for_each_entry(connector, &dev->mode_config.connector_list,
10078 base.head) {
10079 if (!connector->new_encoder ||
10080 connector->new_encoder->new_crtc != crtc)
10081 continue;
10082
10083 connected_sink_compute_bpp(connector, pipe_config);
10084 }
10085
10086 return bpp;
10087 }
10088
10089 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10090 {
10091 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10092 "type: 0x%x flags: 0x%x\n",
10093 mode->crtc_clock,
10094 mode->crtc_hdisplay, mode->crtc_hsync_start,
10095 mode->crtc_hsync_end, mode->crtc_htotal,
10096 mode->crtc_vdisplay, mode->crtc_vsync_start,
10097 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10098 }
10099
10100 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10101 struct intel_crtc_state *pipe_config,
10102 const char *context)
10103 {
10104 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10105 context, pipe_name(crtc->pipe));
10106
10107 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10108 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10109 pipe_config->pipe_bpp, pipe_config->dither);
10110 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10111 pipe_config->has_pch_encoder,
10112 pipe_config->fdi_lanes,
10113 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10114 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10115 pipe_config->fdi_m_n.tu);
10116 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10117 pipe_config->has_dp_encoder,
10118 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10119 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10120 pipe_config->dp_m_n.tu);
10121
10122 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10123 pipe_config->has_dp_encoder,
10124 pipe_config->dp_m2_n2.gmch_m,
10125 pipe_config->dp_m2_n2.gmch_n,
10126 pipe_config->dp_m2_n2.link_m,
10127 pipe_config->dp_m2_n2.link_n,
10128 pipe_config->dp_m2_n2.tu);
10129
10130 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10131 pipe_config->has_audio,
10132 pipe_config->has_infoframe);
10133
10134 DRM_DEBUG_KMS("requested mode:\n");
10135 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10136 DRM_DEBUG_KMS("adjusted mode:\n");
10137 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10138 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10139 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10140 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10141 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10142 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10143 pipe_config->gmch_pfit.control,
10144 pipe_config->gmch_pfit.pgm_ratios,
10145 pipe_config->gmch_pfit.lvds_border_bits);
10146 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10147 pipe_config->pch_pfit.pos,
10148 pipe_config->pch_pfit.size,
10149 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10150 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10151 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10152 }
10153
10154 static bool encoders_cloneable(const struct intel_encoder *a,
10155 const struct intel_encoder *b)
10156 {
10157 /* masks could be asymmetric, so check both ways */
10158 return a == b || (a->cloneable & (1 << b->type) &&
10159 b->cloneable & (1 << a->type));
10160 }
10161
10162 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10163 struct intel_encoder *encoder)
10164 {
10165 struct drm_device *dev = crtc->base.dev;
10166 struct intel_encoder *source_encoder;
10167
10168 for_each_intel_encoder(dev, source_encoder) {
10169 if (source_encoder->new_crtc != crtc)
10170 continue;
10171
10172 if (!encoders_cloneable(encoder, source_encoder))
10173 return false;
10174 }
10175
10176 return true;
10177 }
10178
10179 static bool check_encoder_cloning(struct intel_crtc *crtc)
10180 {
10181 struct drm_device *dev = crtc->base.dev;
10182 struct intel_encoder *encoder;
10183
10184 for_each_intel_encoder(dev, encoder) {
10185 if (encoder->new_crtc != crtc)
10186 continue;
10187
10188 if (!check_single_encoder_cloning(crtc, encoder))
10189 return false;
10190 }
10191
10192 return true;
10193 }
10194
10195 static bool check_digital_port_conflicts(struct drm_device *dev)
10196 {
10197 struct intel_connector *connector;
10198 unsigned int used_ports = 0;
10199
10200 /*
10201 * Walk the connector list instead of the encoder
10202 * list to detect the problem on ddi platforms
10203 * where there's just one encoder per digital port.
10204 */
10205 list_for_each_entry(connector,
10206 &dev->mode_config.connector_list, base.head) {
10207 struct intel_encoder *encoder = connector->new_encoder;
10208
10209 if (!encoder)
10210 continue;
10211
10212 WARN_ON(!encoder->new_crtc);
10213
10214 switch (encoder->type) {
10215 unsigned int port_mask;
10216 case INTEL_OUTPUT_UNKNOWN:
10217 if (WARN_ON(!HAS_DDI(dev)))
10218 break;
10219 case INTEL_OUTPUT_DISPLAYPORT:
10220 case INTEL_OUTPUT_HDMI:
10221 case INTEL_OUTPUT_EDP:
10222 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10223
10224 /* the same port mustn't appear more than once */
10225 if (used_ports & port_mask)
10226 return false;
10227
10228 used_ports |= port_mask;
10229 default:
10230 break;
10231 }
10232 }
10233
10234 return true;
10235 }
10236
10237 static struct intel_crtc_state *
10238 intel_modeset_pipe_config(struct drm_crtc *crtc,
10239 struct drm_framebuffer *fb,
10240 struct drm_display_mode *mode)
10241 {
10242 struct drm_device *dev = crtc->dev;
10243 struct intel_encoder *encoder;
10244 struct intel_crtc_state *pipe_config;
10245 int plane_bpp, ret = -EINVAL;
10246 bool retry = true;
10247
10248 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10249 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10250 return ERR_PTR(-EINVAL);
10251 }
10252
10253 if (!check_digital_port_conflicts(dev)) {
10254 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10255 return ERR_PTR(-EINVAL);
10256 }
10257
10258 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10259 if (!pipe_config)
10260 return ERR_PTR(-ENOMEM);
10261
10262 pipe_config->base.crtc = crtc;
10263 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10264 drm_mode_copy(&pipe_config->base.mode, mode);
10265
10266 pipe_config->cpu_transcoder =
10267 (enum transcoder) to_intel_crtc(crtc)->pipe;
10268 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10269
10270 /*
10271 * Sanitize sync polarity flags based on requested ones. If neither
10272 * positive or negative polarity is requested, treat this as meaning
10273 * negative polarity.
10274 */
10275 if (!(pipe_config->base.adjusted_mode.flags &
10276 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10277 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10278
10279 if (!(pipe_config->base.adjusted_mode.flags &
10280 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10281 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10282
10283 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10284 * plane pixel format and any sink constraints into account. Returns the
10285 * source plane bpp so that dithering can be selected on mismatches
10286 * after encoders and crtc also have had their say. */
10287 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10288 fb, pipe_config);
10289 if (plane_bpp < 0)
10290 goto fail;
10291
10292 /*
10293 * Determine the real pipe dimensions. Note that stereo modes can
10294 * increase the actual pipe size due to the frame doubling and
10295 * insertion of additional space for blanks between the frame. This
10296 * is stored in the crtc timings. We use the requested mode to do this
10297 * computation to clearly distinguish it from the adjusted mode, which
10298 * can be changed by the connectors in the below retry loop.
10299 */
10300 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10301 &pipe_config->pipe_src_w,
10302 &pipe_config->pipe_src_h);
10303
10304 encoder_retry:
10305 /* Ensure the port clock defaults are reset when retrying. */
10306 pipe_config->port_clock = 0;
10307 pipe_config->pixel_multiplier = 1;
10308
10309 /* Fill in default crtc timings, allow encoders to overwrite them. */
10310 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10311 CRTC_STEREO_DOUBLE);
10312
10313 /* Pass our mode to the connectors and the CRTC to give them a chance to
10314 * adjust it according to limitations or connector properties, and also
10315 * a chance to reject the mode entirely.
10316 */
10317 for_each_intel_encoder(dev, encoder) {
10318
10319 if (&encoder->new_crtc->base != crtc)
10320 continue;
10321
10322 if (!(encoder->compute_config(encoder, pipe_config))) {
10323 DRM_DEBUG_KMS("Encoder config failure\n");
10324 goto fail;
10325 }
10326 }
10327
10328 /* Set default port clock if not overwritten by the encoder. Needs to be
10329 * done afterwards in case the encoder adjusts the mode. */
10330 if (!pipe_config->port_clock)
10331 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10332 * pipe_config->pixel_multiplier;
10333
10334 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10335 if (ret < 0) {
10336 DRM_DEBUG_KMS("CRTC fixup failed\n");
10337 goto fail;
10338 }
10339
10340 if (ret == RETRY) {
10341 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10342 ret = -EINVAL;
10343 goto fail;
10344 }
10345
10346 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10347 retry = false;
10348 goto encoder_retry;
10349 }
10350
10351 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10352 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10353 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10354
10355 return pipe_config;
10356 fail:
10357 kfree(pipe_config);
10358 return ERR_PTR(ret);
10359 }
10360
10361 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10362 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10363 static void
10364 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10365 unsigned *prepare_pipes, unsigned *disable_pipes)
10366 {
10367 struct intel_crtc *intel_crtc;
10368 struct drm_device *dev = crtc->dev;
10369 struct intel_encoder *encoder;
10370 struct intel_connector *connector;
10371 struct drm_crtc *tmp_crtc;
10372
10373 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10374
10375 /* Check which crtcs have changed outputs connected to them, these need
10376 * to be part of the prepare_pipes mask. We don't (yet) support global
10377 * modeset across multiple crtcs, so modeset_pipes will only have one
10378 * bit set at most. */
10379 list_for_each_entry(connector, &dev->mode_config.connector_list,
10380 base.head) {
10381 if (connector->base.encoder == &connector->new_encoder->base)
10382 continue;
10383
10384 if (connector->base.encoder) {
10385 tmp_crtc = connector->base.encoder->crtc;
10386
10387 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10388 }
10389
10390 if (connector->new_encoder)
10391 *prepare_pipes |=
10392 1 << connector->new_encoder->new_crtc->pipe;
10393 }
10394
10395 for_each_intel_encoder(dev, encoder) {
10396 if (encoder->base.crtc == &encoder->new_crtc->base)
10397 continue;
10398
10399 if (encoder->base.crtc) {
10400 tmp_crtc = encoder->base.crtc;
10401
10402 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10403 }
10404
10405 if (encoder->new_crtc)
10406 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10407 }
10408
10409 /* Check for pipes that will be enabled/disabled ... */
10410 for_each_intel_crtc(dev, intel_crtc) {
10411 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10412 continue;
10413
10414 if (!intel_crtc->new_enabled)
10415 *disable_pipes |= 1 << intel_crtc->pipe;
10416 else
10417 *prepare_pipes |= 1 << intel_crtc->pipe;
10418 }
10419
10420
10421 /* set_mode is also used to update properties on life display pipes. */
10422 intel_crtc = to_intel_crtc(crtc);
10423 if (intel_crtc->new_enabled)
10424 *prepare_pipes |= 1 << intel_crtc->pipe;
10425
10426 /*
10427 * For simplicity do a full modeset on any pipe where the output routing
10428 * changed. We could be more clever, but that would require us to be
10429 * more careful with calling the relevant encoder->mode_set functions.
10430 */
10431 if (*prepare_pipes)
10432 *modeset_pipes = *prepare_pipes;
10433
10434 /* ... and mask these out. */
10435 *modeset_pipes &= ~(*disable_pipes);
10436 *prepare_pipes &= ~(*disable_pipes);
10437
10438 /*
10439 * HACK: We don't (yet) fully support global modesets. intel_set_config
10440 * obies this rule, but the modeset restore mode of
10441 * intel_modeset_setup_hw_state does not.
10442 */
10443 *modeset_pipes &= 1 << intel_crtc->pipe;
10444 *prepare_pipes &= 1 << intel_crtc->pipe;
10445
10446 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10447 *modeset_pipes, *prepare_pipes, *disable_pipes);
10448 }
10449
10450 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10451 {
10452 struct drm_encoder *encoder;
10453 struct drm_device *dev = crtc->dev;
10454
10455 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10456 if (encoder->crtc == crtc)
10457 return true;
10458
10459 return false;
10460 }
10461
10462 static void
10463 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10464 {
10465 struct drm_i915_private *dev_priv = dev->dev_private;
10466 struct intel_encoder *intel_encoder;
10467 struct intel_crtc *intel_crtc;
10468 struct drm_connector *connector;
10469
10470 intel_shared_dpll_commit(dev_priv);
10471
10472 for_each_intel_encoder(dev, intel_encoder) {
10473 if (!intel_encoder->base.crtc)
10474 continue;
10475
10476 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10477
10478 if (prepare_pipes & (1 << intel_crtc->pipe))
10479 intel_encoder->connectors_active = false;
10480 }
10481
10482 intel_modeset_commit_output_state(dev);
10483
10484 /* Double check state. */
10485 for_each_intel_crtc(dev, intel_crtc) {
10486 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10487 WARN_ON(intel_crtc->new_config &&
10488 intel_crtc->new_config != intel_crtc->config);
10489 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10490 }
10491
10492 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10493 if (!connector->encoder || !connector->encoder->crtc)
10494 continue;
10495
10496 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10497
10498 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10499 struct drm_property *dpms_property =
10500 dev->mode_config.dpms_property;
10501
10502 connector->dpms = DRM_MODE_DPMS_ON;
10503 drm_object_property_set_value(&connector->base,
10504 dpms_property,
10505 DRM_MODE_DPMS_ON);
10506
10507 intel_encoder = to_intel_encoder(connector->encoder);
10508 intel_encoder->connectors_active = true;
10509 }
10510 }
10511
10512 }
10513
10514 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10515 {
10516 int diff;
10517
10518 if (clock1 == clock2)
10519 return true;
10520
10521 if (!clock1 || !clock2)
10522 return false;
10523
10524 diff = abs(clock1 - clock2);
10525
10526 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10527 return true;
10528
10529 return false;
10530 }
10531
10532 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10533 list_for_each_entry((intel_crtc), \
10534 &(dev)->mode_config.crtc_list, \
10535 base.head) \
10536 if (mask & (1 <<(intel_crtc)->pipe))
10537
10538 static bool
10539 intel_pipe_config_compare(struct drm_device *dev,
10540 struct intel_crtc_state *current_config,
10541 struct intel_crtc_state *pipe_config)
10542 {
10543 #define PIPE_CONF_CHECK_X(name) \
10544 if (current_config->name != pipe_config->name) { \
10545 DRM_ERROR("mismatch in " #name " " \
10546 "(expected 0x%08x, found 0x%08x)\n", \
10547 current_config->name, \
10548 pipe_config->name); \
10549 return false; \
10550 }
10551
10552 #define PIPE_CONF_CHECK_I(name) \
10553 if (current_config->name != pipe_config->name) { \
10554 DRM_ERROR("mismatch in " #name " " \
10555 "(expected %i, found %i)\n", \
10556 current_config->name, \
10557 pipe_config->name); \
10558 return false; \
10559 }
10560
10561 /* This is required for BDW+ where there is only one set of registers for
10562 * switching between high and low RR.
10563 * This macro can be used whenever a comparison has to be made between one
10564 * hw state and multiple sw state variables.
10565 */
10566 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10567 if ((current_config->name != pipe_config->name) && \
10568 (current_config->alt_name != pipe_config->name)) { \
10569 DRM_ERROR("mismatch in " #name " " \
10570 "(expected %i or %i, found %i)\n", \
10571 current_config->name, \
10572 current_config->alt_name, \
10573 pipe_config->name); \
10574 return false; \
10575 }
10576
10577 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10578 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10579 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10580 "(expected %i, found %i)\n", \
10581 current_config->name & (mask), \
10582 pipe_config->name & (mask)); \
10583 return false; \
10584 }
10585
10586 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10587 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10588 DRM_ERROR("mismatch in " #name " " \
10589 "(expected %i, found %i)\n", \
10590 current_config->name, \
10591 pipe_config->name); \
10592 return false; \
10593 }
10594
10595 #define PIPE_CONF_QUIRK(quirk) \
10596 ((current_config->quirks | pipe_config->quirks) & (quirk))
10597
10598 PIPE_CONF_CHECK_I(cpu_transcoder);
10599
10600 PIPE_CONF_CHECK_I(has_pch_encoder);
10601 PIPE_CONF_CHECK_I(fdi_lanes);
10602 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10603 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10604 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10605 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10606 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10607
10608 PIPE_CONF_CHECK_I(has_dp_encoder);
10609
10610 if (INTEL_INFO(dev)->gen < 8) {
10611 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10612 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10613 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10614 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10615 PIPE_CONF_CHECK_I(dp_m_n.tu);
10616
10617 if (current_config->has_drrs) {
10618 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10619 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10620 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10621 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10622 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10623 }
10624 } else {
10625 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10626 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10627 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10628 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10629 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10630 }
10631
10632 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10633 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10634 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10635 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10636 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10637 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10638
10639 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10640 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10641 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10642 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10643 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10644 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10645
10646 PIPE_CONF_CHECK_I(pixel_multiplier);
10647 PIPE_CONF_CHECK_I(has_hdmi_sink);
10648 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10649 IS_VALLEYVIEW(dev))
10650 PIPE_CONF_CHECK_I(limited_color_range);
10651 PIPE_CONF_CHECK_I(has_infoframe);
10652
10653 PIPE_CONF_CHECK_I(has_audio);
10654
10655 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10656 DRM_MODE_FLAG_INTERLACE);
10657
10658 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10659 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10660 DRM_MODE_FLAG_PHSYNC);
10661 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10662 DRM_MODE_FLAG_NHSYNC);
10663 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10664 DRM_MODE_FLAG_PVSYNC);
10665 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10666 DRM_MODE_FLAG_NVSYNC);
10667 }
10668
10669 PIPE_CONF_CHECK_I(pipe_src_w);
10670 PIPE_CONF_CHECK_I(pipe_src_h);
10671
10672 /*
10673 * FIXME: BIOS likes to set up a cloned config with lvds+external
10674 * screen. Since we don't yet re-compute the pipe config when moving
10675 * just the lvds port away to another pipe the sw tracking won't match.
10676 *
10677 * Proper atomic modesets with recomputed global state will fix this.
10678 * Until then just don't check gmch state for inherited modes.
10679 */
10680 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10681 PIPE_CONF_CHECK_I(gmch_pfit.control);
10682 /* pfit ratios are autocomputed by the hw on gen4+ */
10683 if (INTEL_INFO(dev)->gen < 4)
10684 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10685 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10686 }
10687
10688 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10689 if (current_config->pch_pfit.enabled) {
10690 PIPE_CONF_CHECK_I(pch_pfit.pos);
10691 PIPE_CONF_CHECK_I(pch_pfit.size);
10692 }
10693
10694 /* BDW+ don't expose a synchronous way to read the state */
10695 if (IS_HASWELL(dev))
10696 PIPE_CONF_CHECK_I(ips_enabled);
10697
10698 PIPE_CONF_CHECK_I(double_wide);
10699
10700 PIPE_CONF_CHECK_X(ddi_pll_sel);
10701
10702 PIPE_CONF_CHECK_I(shared_dpll);
10703 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10704 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10705 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10706 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10707 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10708 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10709 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10710 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10711
10712 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10713 PIPE_CONF_CHECK_I(pipe_bpp);
10714
10715 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10716 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10717
10718 #undef PIPE_CONF_CHECK_X
10719 #undef PIPE_CONF_CHECK_I
10720 #undef PIPE_CONF_CHECK_I_ALT
10721 #undef PIPE_CONF_CHECK_FLAGS
10722 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10723 #undef PIPE_CONF_QUIRK
10724
10725 return true;
10726 }
10727
10728 static void check_wm_state(struct drm_device *dev)
10729 {
10730 struct drm_i915_private *dev_priv = dev->dev_private;
10731 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10732 struct intel_crtc *intel_crtc;
10733 int plane;
10734
10735 if (INTEL_INFO(dev)->gen < 9)
10736 return;
10737
10738 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10739 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10740
10741 for_each_intel_crtc(dev, intel_crtc) {
10742 struct skl_ddb_entry *hw_entry, *sw_entry;
10743 const enum pipe pipe = intel_crtc->pipe;
10744
10745 if (!intel_crtc->active)
10746 continue;
10747
10748 /* planes */
10749 for_each_plane(pipe, plane) {
10750 hw_entry = &hw_ddb.plane[pipe][plane];
10751 sw_entry = &sw_ddb->plane[pipe][plane];
10752
10753 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10754 continue;
10755
10756 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10757 "(expected (%u,%u), found (%u,%u))\n",
10758 pipe_name(pipe), plane + 1,
10759 sw_entry->start, sw_entry->end,
10760 hw_entry->start, hw_entry->end);
10761 }
10762
10763 /* cursor */
10764 hw_entry = &hw_ddb.cursor[pipe];
10765 sw_entry = &sw_ddb->cursor[pipe];
10766
10767 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10768 continue;
10769
10770 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10771 "(expected (%u,%u), found (%u,%u))\n",
10772 pipe_name(pipe),
10773 sw_entry->start, sw_entry->end,
10774 hw_entry->start, hw_entry->end);
10775 }
10776 }
10777
10778 static void
10779 check_connector_state(struct drm_device *dev)
10780 {
10781 struct intel_connector *connector;
10782
10783 list_for_each_entry(connector, &dev->mode_config.connector_list,
10784 base.head) {
10785 /* This also checks the encoder/connector hw state with the
10786 * ->get_hw_state callbacks. */
10787 intel_connector_check_state(connector);
10788
10789 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10790 "connector's staged encoder doesn't match current encoder\n");
10791 }
10792 }
10793
10794 static void
10795 check_encoder_state(struct drm_device *dev)
10796 {
10797 struct intel_encoder *encoder;
10798 struct intel_connector *connector;
10799
10800 for_each_intel_encoder(dev, encoder) {
10801 bool enabled = false;
10802 bool active = false;
10803 enum pipe pipe, tracked_pipe;
10804
10805 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10806 encoder->base.base.id,
10807 encoder->base.name);
10808
10809 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10810 "encoder's stage crtc doesn't match current crtc\n");
10811 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10812 "encoder's active_connectors set, but no crtc\n");
10813
10814 list_for_each_entry(connector, &dev->mode_config.connector_list,
10815 base.head) {
10816 if (connector->base.encoder != &encoder->base)
10817 continue;
10818 enabled = true;
10819 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10820 active = true;
10821 }
10822 /*
10823 * for MST connectors if we unplug the connector is gone
10824 * away but the encoder is still connected to a crtc
10825 * until a modeset happens in response to the hotplug.
10826 */
10827 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10828 continue;
10829
10830 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10831 "encoder's enabled state mismatch "
10832 "(expected %i, found %i)\n",
10833 !!encoder->base.crtc, enabled);
10834 I915_STATE_WARN(active && !encoder->base.crtc,
10835 "active encoder with no crtc\n");
10836
10837 I915_STATE_WARN(encoder->connectors_active != active,
10838 "encoder's computed active state doesn't match tracked active state "
10839 "(expected %i, found %i)\n", active, encoder->connectors_active);
10840
10841 active = encoder->get_hw_state(encoder, &pipe);
10842 I915_STATE_WARN(active != encoder->connectors_active,
10843 "encoder's hw state doesn't match sw tracking "
10844 "(expected %i, found %i)\n",
10845 encoder->connectors_active, active);
10846
10847 if (!encoder->base.crtc)
10848 continue;
10849
10850 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10851 I915_STATE_WARN(active && pipe != tracked_pipe,
10852 "active encoder's pipe doesn't match"
10853 "(expected %i, found %i)\n",
10854 tracked_pipe, pipe);
10855
10856 }
10857 }
10858
10859 static void
10860 check_crtc_state(struct drm_device *dev)
10861 {
10862 struct drm_i915_private *dev_priv = dev->dev_private;
10863 struct intel_crtc *crtc;
10864 struct intel_encoder *encoder;
10865 struct intel_crtc_state pipe_config;
10866
10867 for_each_intel_crtc(dev, crtc) {
10868 bool enabled = false;
10869 bool active = false;
10870
10871 memset(&pipe_config, 0, sizeof(pipe_config));
10872
10873 DRM_DEBUG_KMS("[CRTC:%d]\n",
10874 crtc->base.base.id);
10875
10876 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
10877 "active crtc, but not enabled in sw tracking\n");
10878
10879 for_each_intel_encoder(dev, encoder) {
10880 if (encoder->base.crtc != &crtc->base)
10881 continue;
10882 enabled = true;
10883 if (encoder->connectors_active)
10884 active = true;
10885 }
10886
10887 I915_STATE_WARN(active != crtc->active,
10888 "crtc's computed active state doesn't match tracked active state "
10889 "(expected %i, found %i)\n", active, crtc->active);
10890 I915_STATE_WARN(enabled != crtc->base.state->enable,
10891 "crtc's computed enabled state doesn't match tracked enabled state "
10892 "(expected %i, found %i)\n", enabled,
10893 crtc->base.state->enable);
10894
10895 active = dev_priv->display.get_pipe_config(crtc,
10896 &pipe_config);
10897
10898 /* hw state is inconsistent with the pipe quirk */
10899 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10900 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10901 active = crtc->active;
10902
10903 for_each_intel_encoder(dev, encoder) {
10904 enum pipe pipe;
10905 if (encoder->base.crtc != &crtc->base)
10906 continue;
10907 if (encoder->get_hw_state(encoder, &pipe))
10908 encoder->get_config(encoder, &pipe_config);
10909 }
10910
10911 I915_STATE_WARN(crtc->active != active,
10912 "crtc active state doesn't match with hw state "
10913 "(expected %i, found %i)\n", crtc->active, active);
10914
10915 if (active &&
10916 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10917 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10918 intel_dump_pipe_config(crtc, &pipe_config,
10919 "[hw state]");
10920 intel_dump_pipe_config(crtc, crtc->config,
10921 "[sw state]");
10922 }
10923 }
10924 }
10925
10926 static void
10927 check_shared_dpll_state(struct drm_device *dev)
10928 {
10929 struct drm_i915_private *dev_priv = dev->dev_private;
10930 struct intel_crtc *crtc;
10931 struct intel_dpll_hw_state dpll_hw_state;
10932 int i;
10933
10934 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10935 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10936 int enabled_crtcs = 0, active_crtcs = 0;
10937 bool active;
10938
10939 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10940
10941 DRM_DEBUG_KMS("%s\n", pll->name);
10942
10943 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10944
10945 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10946 "more active pll users than references: %i vs %i\n",
10947 pll->active, hweight32(pll->config.crtc_mask));
10948 I915_STATE_WARN(pll->active && !pll->on,
10949 "pll in active use but not on in sw tracking\n");
10950 I915_STATE_WARN(pll->on && !pll->active,
10951 "pll in on but not on in use in sw tracking\n");
10952 I915_STATE_WARN(pll->on != active,
10953 "pll on state mismatch (expected %i, found %i)\n",
10954 pll->on, active);
10955
10956 for_each_intel_crtc(dev, crtc) {
10957 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
10958 enabled_crtcs++;
10959 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10960 active_crtcs++;
10961 }
10962 I915_STATE_WARN(pll->active != active_crtcs,
10963 "pll active crtcs mismatch (expected %i, found %i)\n",
10964 pll->active, active_crtcs);
10965 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10966 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10967 hweight32(pll->config.crtc_mask), enabled_crtcs);
10968
10969 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10970 sizeof(dpll_hw_state)),
10971 "pll hw state mismatch\n");
10972 }
10973 }
10974
10975 void
10976 intel_modeset_check_state(struct drm_device *dev)
10977 {
10978 check_wm_state(dev);
10979 check_connector_state(dev);
10980 check_encoder_state(dev);
10981 check_crtc_state(dev);
10982 check_shared_dpll_state(dev);
10983 }
10984
10985 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10986 int dotclock)
10987 {
10988 /*
10989 * FDI already provided one idea for the dotclock.
10990 * Yell if the encoder disagrees.
10991 */
10992 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
10993 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10994 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
10995 }
10996
10997 static void update_scanline_offset(struct intel_crtc *crtc)
10998 {
10999 struct drm_device *dev = crtc->base.dev;
11000
11001 /*
11002 * The scanline counter increments at the leading edge of hsync.
11003 *
11004 * On most platforms it starts counting from vtotal-1 on the
11005 * first active line. That means the scanline counter value is
11006 * always one less than what we would expect. Ie. just after
11007 * start of vblank, which also occurs at start of hsync (on the
11008 * last active line), the scanline counter will read vblank_start-1.
11009 *
11010 * On gen2 the scanline counter starts counting from 1 instead
11011 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11012 * to keep the value positive), instead of adding one.
11013 *
11014 * On HSW+ the behaviour of the scanline counter depends on the output
11015 * type. For DP ports it behaves like most other platforms, but on HDMI
11016 * there's an extra 1 line difference. So we need to add two instead of
11017 * one to the value.
11018 */
11019 if (IS_GEN2(dev)) {
11020 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11021 int vtotal;
11022
11023 vtotal = mode->crtc_vtotal;
11024 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11025 vtotal /= 2;
11026
11027 crtc->scanline_offset = vtotal - 1;
11028 } else if (HAS_DDI(dev) &&
11029 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11030 crtc->scanline_offset = 2;
11031 } else
11032 crtc->scanline_offset = 1;
11033 }
11034
11035 static struct intel_crtc_state *
11036 intel_modeset_compute_config(struct drm_crtc *crtc,
11037 struct drm_display_mode *mode,
11038 struct drm_framebuffer *fb,
11039 unsigned *modeset_pipes,
11040 unsigned *prepare_pipes,
11041 unsigned *disable_pipes)
11042 {
11043 struct intel_crtc_state *pipe_config = NULL;
11044
11045 intel_modeset_affected_pipes(crtc, modeset_pipes,
11046 prepare_pipes, disable_pipes);
11047
11048 if ((*modeset_pipes) == 0)
11049 goto out;
11050
11051 /*
11052 * Note this needs changes when we start tracking multiple modes
11053 * and crtcs. At that point we'll need to compute the whole config
11054 * (i.e. one pipe_config for each crtc) rather than just the one
11055 * for this crtc.
11056 */
11057 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11058 if (IS_ERR(pipe_config)) {
11059 goto out;
11060 }
11061 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11062 "[modeset]");
11063
11064 out:
11065 return pipe_config;
11066 }
11067
11068 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11069 unsigned modeset_pipes,
11070 unsigned disable_pipes)
11071 {
11072 struct drm_i915_private *dev_priv = to_i915(dev);
11073 unsigned clear_pipes = modeset_pipes | disable_pipes;
11074 struct intel_crtc *intel_crtc;
11075 int ret = 0;
11076
11077 if (!dev_priv->display.crtc_compute_clock)
11078 return 0;
11079
11080 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11081 if (ret)
11082 goto done;
11083
11084 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11085 struct intel_crtc_state *state = intel_crtc->new_config;
11086 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11087 state);
11088 if (ret) {
11089 intel_shared_dpll_abort_config(dev_priv);
11090 goto done;
11091 }
11092 }
11093
11094 done:
11095 return ret;
11096 }
11097
11098 static int __intel_set_mode(struct drm_crtc *crtc,
11099 struct drm_display_mode *mode,
11100 int x, int y, struct drm_framebuffer *fb,
11101 struct intel_crtc_state *pipe_config,
11102 unsigned modeset_pipes,
11103 unsigned prepare_pipes,
11104 unsigned disable_pipes)
11105 {
11106 struct drm_device *dev = crtc->dev;
11107 struct drm_i915_private *dev_priv = dev->dev_private;
11108 struct drm_display_mode *saved_mode;
11109 struct intel_crtc *intel_crtc;
11110 int ret = 0;
11111
11112 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11113 if (!saved_mode)
11114 return -ENOMEM;
11115
11116 *saved_mode = crtc->mode;
11117
11118 if (modeset_pipes)
11119 to_intel_crtc(crtc)->new_config = pipe_config;
11120
11121 /*
11122 * See if the config requires any additional preparation, e.g.
11123 * to adjust global state with pipes off. We need to do this
11124 * here so we can get the modeset_pipe updated config for the new
11125 * mode set on this crtc. For other crtcs we need to use the
11126 * adjusted_mode bits in the crtc directly.
11127 */
11128 if (IS_VALLEYVIEW(dev)) {
11129 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11130
11131 /* may have added more to prepare_pipes than we should */
11132 prepare_pipes &= ~disable_pipes;
11133 }
11134
11135 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11136 if (ret)
11137 goto done;
11138
11139 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11140 intel_crtc_disable(&intel_crtc->base);
11141
11142 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11143 if (intel_crtc->base.state->enable)
11144 dev_priv->display.crtc_disable(&intel_crtc->base);
11145 }
11146
11147 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11148 * to set it here already despite that we pass it down the callchain.
11149 *
11150 * Note we'll need to fix this up when we start tracking multiple
11151 * pipes; here we assume a single modeset_pipe and only track the
11152 * single crtc and mode.
11153 */
11154 if (modeset_pipes) {
11155 crtc->mode = *mode;
11156 /* mode_set/enable/disable functions rely on a correct pipe
11157 * config. */
11158 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11159
11160 /*
11161 * Calculate and store various constants which
11162 * are later needed by vblank and swap-completion
11163 * timestamping. They are derived from true hwmode.
11164 */
11165 drm_calc_timestamping_constants(crtc,
11166 &pipe_config->base.adjusted_mode);
11167 }
11168
11169 /* Only after disabling all output pipelines that will be changed can we
11170 * update the the output configuration. */
11171 intel_modeset_update_state(dev, prepare_pipes);
11172
11173 modeset_update_crtc_power_domains(dev);
11174
11175 /* Set up the DPLL and any encoders state that needs to adjust or depend
11176 * on the DPLL.
11177 */
11178 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11179 struct drm_plane *primary = intel_crtc->base.primary;
11180 int vdisplay, hdisplay;
11181
11182 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11183 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11184 fb, 0, 0,
11185 hdisplay, vdisplay,
11186 x << 16, y << 16,
11187 hdisplay << 16, vdisplay << 16);
11188 }
11189
11190 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11191 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11192 update_scanline_offset(intel_crtc);
11193
11194 dev_priv->display.crtc_enable(&intel_crtc->base);
11195 }
11196
11197 /* FIXME: add subpixel order */
11198 done:
11199 if (ret && crtc->state->enable)
11200 crtc->mode = *saved_mode;
11201
11202 kfree(saved_mode);
11203 return ret;
11204 }
11205
11206 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11207 struct drm_display_mode *mode,
11208 int x, int y, struct drm_framebuffer *fb,
11209 struct intel_crtc_state *pipe_config,
11210 unsigned modeset_pipes,
11211 unsigned prepare_pipes,
11212 unsigned disable_pipes)
11213 {
11214 int ret;
11215
11216 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11217 prepare_pipes, disable_pipes);
11218
11219 if (ret == 0)
11220 intel_modeset_check_state(crtc->dev);
11221
11222 return ret;
11223 }
11224
11225 static int intel_set_mode(struct drm_crtc *crtc,
11226 struct drm_display_mode *mode,
11227 int x, int y, struct drm_framebuffer *fb)
11228 {
11229 struct intel_crtc_state *pipe_config;
11230 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11231
11232 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11233 &modeset_pipes,
11234 &prepare_pipes,
11235 &disable_pipes);
11236
11237 if (IS_ERR(pipe_config))
11238 return PTR_ERR(pipe_config);
11239
11240 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11241 modeset_pipes, prepare_pipes,
11242 disable_pipes);
11243 }
11244
11245 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11246 {
11247 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11248 }
11249
11250 #undef for_each_intel_crtc_masked
11251
11252 static void intel_set_config_free(struct intel_set_config *config)
11253 {
11254 if (!config)
11255 return;
11256
11257 kfree(config->save_connector_encoders);
11258 kfree(config->save_encoder_crtcs);
11259 kfree(config->save_crtc_enabled);
11260 kfree(config);
11261 }
11262
11263 static int intel_set_config_save_state(struct drm_device *dev,
11264 struct intel_set_config *config)
11265 {
11266 struct drm_crtc *crtc;
11267 struct drm_encoder *encoder;
11268 struct drm_connector *connector;
11269 int count;
11270
11271 config->save_crtc_enabled =
11272 kcalloc(dev->mode_config.num_crtc,
11273 sizeof(bool), GFP_KERNEL);
11274 if (!config->save_crtc_enabled)
11275 return -ENOMEM;
11276
11277 config->save_encoder_crtcs =
11278 kcalloc(dev->mode_config.num_encoder,
11279 sizeof(struct drm_crtc *), GFP_KERNEL);
11280 if (!config->save_encoder_crtcs)
11281 return -ENOMEM;
11282
11283 config->save_connector_encoders =
11284 kcalloc(dev->mode_config.num_connector,
11285 sizeof(struct drm_encoder *), GFP_KERNEL);
11286 if (!config->save_connector_encoders)
11287 return -ENOMEM;
11288
11289 /* Copy data. Note that driver private data is not affected.
11290 * Should anything bad happen only the expected state is
11291 * restored, not the drivers personal bookkeeping.
11292 */
11293 count = 0;
11294 for_each_crtc(dev, crtc) {
11295 config->save_crtc_enabled[count++] = crtc->state->enable;
11296 }
11297
11298 count = 0;
11299 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11300 config->save_encoder_crtcs[count++] = encoder->crtc;
11301 }
11302
11303 count = 0;
11304 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11305 config->save_connector_encoders[count++] = connector->encoder;
11306 }
11307
11308 return 0;
11309 }
11310
11311 static void intel_set_config_restore_state(struct drm_device *dev,
11312 struct intel_set_config *config)
11313 {
11314 struct intel_crtc *crtc;
11315 struct intel_encoder *encoder;
11316 struct intel_connector *connector;
11317 int count;
11318
11319 count = 0;
11320 for_each_intel_crtc(dev, crtc) {
11321 crtc->new_enabled = config->save_crtc_enabled[count++];
11322
11323 if (crtc->new_enabled)
11324 crtc->new_config = crtc->config;
11325 else
11326 crtc->new_config = NULL;
11327 }
11328
11329 count = 0;
11330 for_each_intel_encoder(dev, encoder) {
11331 encoder->new_crtc =
11332 to_intel_crtc(config->save_encoder_crtcs[count++]);
11333 }
11334
11335 count = 0;
11336 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11337 connector->new_encoder =
11338 to_intel_encoder(config->save_connector_encoders[count++]);
11339 }
11340 }
11341
11342 static bool
11343 is_crtc_connector_off(struct drm_mode_set *set)
11344 {
11345 int i;
11346
11347 if (set->num_connectors == 0)
11348 return false;
11349
11350 if (WARN_ON(set->connectors == NULL))
11351 return false;
11352
11353 for (i = 0; i < set->num_connectors; i++)
11354 if (set->connectors[i]->encoder &&
11355 set->connectors[i]->encoder->crtc == set->crtc &&
11356 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11357 return true;
11358
11359 return false;
11360 }
11361
11362 static void
11363 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11364 struct intel_set_config *config)
11365 {
11366
11367 /* We should be able to check here if the fb has the same properties
11368 * and then just flip_or_move it */
11369 if (is_crtc_connector_off(set)) {
11370 config->mode_changed = true;
11371 } else if (set->crtc->primary->fb != set->fb) {
11372 /*
11373 * If we have no fb, we can only flip as long as the crtc is
11374 * active, otherwise we need a full mode set. The crtc may
11375 * be active if we've only disabled the primary plane, or
11376 * in fastboot situations.
11377 */
11378 if (set->crtc->primary->fb == NULL) {
11379 struct intel_crtc *intel_crtc =
11380 to_intel_crtc(set->crtc);
11381
11382 if (intel_crtc->active) {
11383 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11384 config->fb_changed = true;
11385 } else {
11386 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11387 config->mode_changed = true;
11388 }
11389 } else if (set->fb == NULL) {
11390 config->mode_changed = true;
11391 } else if (set->fb->pixel_format !=
11392 set->crtc->primary->fb->pixel_format) {
11393 config->mode_changed = true;
11394 } else {
11395 config->fb_changed = true;
11396 }
11397 }
11398
11399 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11400 config->fb_changed = true;
11401
11402 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11403 DRM_DEBUG_KMS("modes are different, full mode set\n");
11404 drm_mode_debug_printmodeline(&set->crtc->mode);
11405 drm_mode_debug_printmodeline(set->mode);
11406 config->mode_changed = true;
11407 }
11408
11409 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11410 set->crtc->base.id, config->mode_changed, config->fb_changed);
11411 }
11412
11413 static int
11414 intel_modeset_stage_output_state(struct drm_device *dev,
11415 struct drm_mode_set *set,
11416 struct intel_set_config *config)
11417 {
11418 struct intel_connector *connector;
11419 struct intel_encoder *encoder;
11420 struct intel_crtc *crtc;
11421 int ro;
11422
11423 /* The upper layers ensure that we either disable a crtc or have a list
11424 * of connectors. For paranoia, double-check this. */
11425 WARN_ON(!set->fb && (set->num_connectors != 0));
11426 WARN_ON(set->fb && (set->num_connectors == 0));
11427
11428 list_for_each_entry(connector, &dev->mode_config.connector_list,
11429 base.head) {
11430 /* Otherwise traverse passed in connector list and get encoders
11431 * for them. */
11432 for (ro = 0; ro < set->num_connectors; ro++) {
11433 if (set->connectors[ro] == &connector->base) {
11434 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11435 break;
11436 }
11437 }
11438
11439 /* If we disable the crtc, disable all its connectors. Also, if
11440 * the connector is on the changing crtc but not on the new
11441 * connector list, disable it. */
11442 if ((!set->fb || ro == set->num_connectors) &&
11443 connector->base.encoder &&
11444 connector->base.encoder->crtc == set->crtc) {
11445 connector->new_encoder = NULL;
11446
11447 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11448 connector->base.base.id,
11449 connector->base.name);
11450 }
11451
11452
11453 if (&connector->new_encoder->base != connector->base.encoder) {
11454 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11455 config->mode_changed = true;
11456 }
11457 }
11458 /* connector->new_encoder is now updated for all connectors. */
11459
11460 /* Update crtc of enabled connectors. */
11461 list_for_each_entry(connector, &dev->mode_config.connector_list,
11462 base.head) {
11463 struct drm_crtc *new_crtc;
11464
11465 if (!connector->new_encoder)
11466 continue;
11467
11468 new_crtc = connector->new_encoder->base.crtc;
11469
11470 for (ro = 0; ro < set->num_connectors; ro++) {
11471 if (set->connectors[ro] == &connector->base)
11472 new_crtc = set->crtc;
11473 }
11474
11475 /* Make sure the new CRTC will work with the encoder */
11476 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11477 new_crtc)) {
11478 return -EINVAL;
11479 }
11480 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11481
11482 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11483 connector->base.base.id,
11484 connector->base.name,
11485 new_crtc->base.id);
11486 }
11487
11488 /* Check for any encoders that needs to be disabled. */
11489 for_each_intel_encoder(dev, encoder) {
11490 int num_connectors = 0;
11491 list_for_each_entry(connector,
11492 &dev->mode_config.connector_list,
11493 base.head) {
11494 if (connector->new_encoder == encoder) {
11495 WARN_ON(!connector->new_encoder->new_crtc);
11496 num_connectors++;
11497 }
11498 }
11499
11500 if (num_connectors == 0)
11501 encoder->new_crtc = NULL;
11502 else if (num_connectors > 1)
11503 return -EINVAL;
11504
11505 /* Only now check for crtc changes so we don't miss encoders
11506 * that will be disabled. */
11507 if (&encoder->new_crtc->base != encoder->base.crtc) {
11508 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11509 config->mode_changed = true;
11510 }
11511 }
11512 /* Now we've also updated encoder->new_crtc for all encoders. */
11513 list_for_each_entry(connector, &dev->mode_config.connector_list,
11514 base.head) {
11515 if (connector->new_encoder)
11516 if (connector->new_encoder != connector->encoder)
11517 connector->encoder = connector->new_encoder;
11518 }
11519 for_each_intel_crtc(dev, crtc) {
11520 crtc->new_enabled = false;
11521
11522 for_each_intel_encoder(dev, encoder) {
11523 if (encoder->new_crtc == crtc) {
11524 crtc->new_enabled = true;
11525 break;
11526 }
11527 }
11528
11529 if (crtc->new_enabled != crtc->base.state->enable) {
11530 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11531 crtc->new_enabled ? "en" : "dis");
11532 config->mode_changed = true;
11533 }
11534
11535 if (crtc->new_enabled)
11536 crtc->new_config = crtc->config;
11537 else
11538 crtc->new_config = NULL;
11539 }
11540
11541 return 0;
11542 }
11543
11544 static void disable_crtc_nofb(struct intel_crtc *crtc)
11545 {
11546 struct drm_device *dev = crtc->base.dev;
11547 struct intel_encoder *encoder;
11548 struct intel_connector *connector;
11549
11550 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11551 pipe_name(crtc->pipe));
11552
11553 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11554 if (connector->new_encoder &&
11555 connector->new_encoder->new_crtc == crtc)
11556 connector->new_encoder = NULL;
11557 }
11558
11559 for_each_intel_encoder(dev, encoder) {
11560 if (encoder->new_crtc == crtc)
11561 encoder->new_crtc = NULL;
11562 }
11563
11564 crtc->new_enabled = false;
11565 crtc->new_config = NULL;
11566 }
11567
11568 static int intel_crtc_set_config(struct drm_mode_set *set)
11569 {
11570 struct drm_device *dev;
11571 struct drm_mode_set save_set;
11572 struct intel_set_config *config;
11573 struct intel_crtc_state *pipe_config;
11574 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11575 int ret;
11576
11577 BUG_ON(!set);
11578 BUG_ON(!set->crtc);
11579 BUG_ON(!set->crtc->helper_private);
11580
11581 /* Enforce sane interface api - has been abused by the fb helper. */
11582 BUG_ON(!set->mode && set->fb);
11583 BUG_ON(set->fb && set->num_connectors == 0);
11584
11585 if (set->fb) {
11586 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11587 set->crtc->base.id, set->fb->base.id,
11588 (int)set->num_connectors, set->x, set->y);
11589 } else {
11590 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11591 }
11592
11593 dev = set->crtc->dev;
11594
11595 ret = -ENOMEM;
11596 config = kzalloc(sizeof(*config), GFP_KERNEL);
11597 if (!config)
11598 goto out_config;
11599
11600 ret = intel_set_config_save_state(dev, config);
11601 if (ret)
11602 goto out_config;
11603
11604 save_set.crtc = set->crtc;
11605 save_set.mode = &set->crtc->mode;
11606 save_set.x = set->crtc->x;
11607 save_set.y = set->crtc->y;
11608 save_set.fb = set->crtc->primary->fb;
11609
11610 /* Compute whether we need a full modeset, only an fb base update or no
11611 * change at all. In the future we might also check whether only the
11612 * mode changed, e.g. for LVDS where we only change the panel fitter in
11613 * such cases. */
11614 intel_set_config_compute_mode_changes(set, config);
11615
11616 ret = intel_modeset_stage_output_state(dev, set, config);
11617 if (ret)
11618 goto fail;
11619
11620 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11621 set->fb,
11622 &modeset_pipes,
11623 &prepare_pipes,
11624 &disable_pipes);
11625 if (IS_ERR(pipe_config)) {
11626 ret = PTR_ERR(pipe_config);
11627 goto fail;
11628 } else if (pipe_config) {
11629 if (pipe_config->has_audio !=
11630 to_intel_crtc(set->crtc)->config->has_audio)
11631 config->mode_changed = true;
11632
11633 /*
11634 * Note we have an issue here with infoframes: current code
11635 * only updates them on the full mode set path per hw
11636 * requirements. So here we should be checking for any
11637 * required changes and forcing a mode set.
11638 */
11639 }
11640
11641 /* set_mode will free it in the mode_changed case */
11642 if (!config->mode_changed)
11643 kfree(pipe_config);
11644
11645 intel_update_pipe_size(to_intel_crtc(set->crtc));
11646
11647 if (config->mode_changed) {
11648 ret = intel_set_mode_pipes(set->crtc, set->mode,
11649 set->x, set->y, set->fb, pipe_config,
11650 modeset_pipes, prepare_pipes,
11651 disable_pipes);
11652 } else if (config->fb_changed) {
11653 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11654 struct drm_plane *primary = set->crtc->primary;
11655 int vdisplay, hdisplay;
11656
11657 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11658 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11659 0, 0, hdisplay, vdisplay,
11660 set->x << 16, set->y << 16,
11661 hdisplay << 16, vdisplay << 16);
11662
11663 /*
11664 * We need to make sure the primary plane is re-enabled if it
11665 * has previously been turned off.
11666 */
11667 if (!intel_crtc->primary_enabled && ret == 0) {
11668 WARN_ON(!intel_crtc->active);
11669 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11670 }
11671
11672 /*
11673 * In the fastboot case this may be our only check of the
11674 * state after boot. It would be better to only do it on
11675 * the first update, but we don't have a nice way of doing that
11676 * (and really, set_config isn't used much for high freq page
11677 * flipping, so increasing its cost here shouldn't be a big
11678 * deal).
11679 */
11680 if (i915.fastboot && ret == 0)
11681 intel_modeset_check_state(set->crtc->dev);
11682 }
11683
11684 if (ret) {
11685 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11686 set->crtc->base.id, ret);
11687 fail:
11688 intel_set_config_restore_state(dev, config);
11689
11690 /*
11691 * HACK: if the pipe was on, but we didn't have a framebuffer,
11692 * force the pipe off to avoid oopsing in the modeset code
11693 * due to fb==NULL. This should only happen during boot since
11694 * we don't yet reconstruct the FB from the hardware state.
11695 */
11696 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11697 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11698
11699 /* Try to restore the config */
11700 if (config->mode_changed &&
11701 intel_set_mode(save_set.crtc, save_set.mode,
11702 save_set.x, save_set.y, save_set.fb))
11703 DRM_ERROR("failed to restore config after modeset failure\n");
11704 }
11705
11706 out_config:
11707 intel_set_config_free(config);
11708 return ret;
11709 }
11710
11711 static const struct drm_crtc_funcs intel_crtc_funcs = {
11712 .gamma_set = intel_crtc_gamma_set,
11713 .set_config = intel_crtc_set_config,
11714 .destroy = intel_crtc_destroy,
11715 .page_flip = intel_crtc_page_flip,
11716 .atomic_duplicate_state = intel_crtc_duplicate_state,
11717 .atomic_destroy_state = intel_crtc_destroy_state,
11718 };
11719
11720 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11721 struct intel_shared_dpll *pll,
11722 struct intel_dpll_hw_state *hw_state)
11723 {
11724 uint32_t val;
11725
11726 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11727 return false;
11728
11729 val = I915_READ(PCH_DPLL(pll->id));
11730 hw_state->dpll = val;
11731 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11732 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11733
11734 return val & DPLL_VCO_ENABLE;
11735 }
11736
11737 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11738 struct intel_shared_dpll *pll)
11739 {
11740 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11741 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11742 }
11743
11744 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11745 struct intel_shared_dpll *pll)
11746 {
11747 /* PCH refclock must be enabled first */
11748 ibx_assert_pch_refclk_enabled(dev_priv);
11749
11750 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11751
11752 /* Wait for the clocks to stabilize. */
11753 POSTING_READ(PCH_DPLL(pll->id));
11754 udelay(150);
11755
11756 /* The pixel multiplier can only be updated once the
11757 * DPLL is enabled and the clocks are stable.
11758 *
11759 * So write it again.
11760 */
11761 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11762 POSTING_READ(PCH_DPLL(pll->id));
11763 udelay(200);
11764 }
11765
11766 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11767 struct intel_shared_dpll *pll)
11768 {
11769 struct drm_device *dev = dev_priv->dev;
11770 struct intel_crtc *crtc;
11771
11772 /* Make sure no transcoder isn't still depending on us. */
11773 for_each_intel_crtc(dev, crtc) {
11774 if (intel_crtc_to_shared_dpll(crtc) == pll)
11775 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11776 }
11777
11778 I915_WRITE(PCH_DPLL(pll->id), 0);
11779 POSTING_READ(PCH_DPLL(pll->id));
11780 udelay(200);
11781 }
11782
11783 static char *ibx_pch_dpll_names[] = {
11784 "PCH DPLL A",
11785 "PCH DPLL B",
11786 };
11787
11788 static void ibx_pch_dpll_init(struct drm_device *dev)
11789 {
11790 struct drm_i915_private *dev_priv = dev->dev_private;
11791 int i;
11792
11793 dev_priv->num_shared_dpll = 2;
11794
11795 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11796 dev_priv->shared_dplls[i].id = i;
11797 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11798 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11799 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11800 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11801 dev_priv->shared_dplls[i].get_hw_state =
11802 ibx_pch_dpll_get_hw_state;
11803 }
11804 }
11805
11806 static void intel_shared_dpll_init(struct drm_device *dev)
11807 {
11808 struct drm_i915_private *dev_priv = dev->dev_private;
11809
11810 if (HAS_DDI(dev))
11811 intel_ddi_pll_init(dev);
11812 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11813 ibx_pch_dpll_init(dev);
11814 else
11815 dev_priv->num_shared_dpll = 0;
11816
11817 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11818 }
11819
11820 /**
11821 * intel_prepare_plane_fb - Prepare fb for usage on plane
11822 * @plane: drm plane to prepare for
11823 * @fb: framebuffer to prepare for presentation
11824 *
11825 * Prepares a framebuffer for usage on a display plane. Generally this
11826 * involves pinning the underlying object and updating the frontbuffer tracking
11827 * bits. Some older platforms need special physical address handling for
11828 * cursor planes.
11829 *
11830 * Returns 0 on success, negative error code on failure.
11831 */
11832 int
11833 intel_prepare_plane_fb(struct drm_plane *plane,
11834 struct drm_framebuffer *fb)
11835 {
11836 struct drm_device *dev = plane->dev;
11837 struct intel_plane *intel_plane = to_intel_plane(plane);
11838 enum pipe pipe = intel_plane->pipe;
11839 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11840 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11841 unsigned frontbuffer_bits = 0;
11842 int ret = 0;
11843
11844 if (!obj)
11845 return 0;
11846
11847 switch (plane->type) {
11848 case DRM_PLANE_TYPE_PRIMARY:
11849 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11850 break;
11851 case DRM_PLANE_TYPE_CURSOR:
11852 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11853 break;
11854 case DRM_PLANE_TYPE_OVERLAY:
11855 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11856 break;
11857 }
11858
11859 mutex_lock(&dev->struct_mutex);
11860
11861 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11862 INTEL_INFO(dev)->cursor_needs_physical) {
11863 int align = IS_I830(dev) ? 16 * 1024 : 256;
11864 ret = i915_gem_object_attach_phys(obj, align);
11865 if (ret)
11866 DRM_DEBUG_KMS("failed to attach phys object\n");
11867 } else {
11868 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11869 }
11870
11871 if (ret == 0)
11872 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11873
11874 mutex_unlock(&dev->struct_mutex);
11875
11876 return ret;
11877 }
11878
11879 /**
11880 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11881 * @plane: drm plane to clean up for
11882 * @fb: old framebuffer that was on plane
11883 *
11884 * Cleans up a framebuffer that has just been removed from a plane.
11885 */
11886 void
11887 intel_cleanup_plane_fb(struct drm_plane *plane,
11888 struct drm_framebuffer *fb)
11889 {
11890 struct drm_device *dev = plane->dev;
11891 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11892
11893 if (WARN_ON(!obj))
11894 return;
11895
11896 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11897 !INTEL_INFO(dev)->cursor_needs_physical) {
11898 mutex_lock(&dev->struct_mutex);
11899 intel_unpin_fb_obj(obj);
11900 mutex_unlock(&dev->struct_mutex);
11901 }
11902 }
11903
11904 static int
11905 intel_check_primary_plane(struct drm_plane *plane,
11906 struct intel_plane_state *state)
11907 {
11908 struct drm_device *dev = plane->dev;
11909 struct drm_i915_private *dev_priv = dev->dev_private;
11910 struct drm_crtc *crtc = state->base.crtc;
11911 struct intel_crtc *intel_crtc;
11912 struct drm_framebuffer *fb = state->base.fb;
11913 struct drm_rect *dest = &state->dst;
11914 struct drm_rect *src = &state->src;
11915 const struct drm_rect *clip = &state->clip;
11916 int ret;
11917
11918 crtc = crtc ? crtc : plane->crtc;
11919 intel_crtc = to_intel_crtc(crtc);
11920
11921 ret = drm_plane_helper_check_update(plane, crtc, fb,
11922 src, dest, clip,
11923 DRM_PLANE_HELPER_NO_SCALING,
11924 DRM_PLANE_HELPER_NO_SCALING,
11925 false, true, &state->visible);
11926 if (ret)
11927 return ret;
11928
11929 if (intel_crtc->active) {
11930 intel_crtc->atomic.wait_for_flips = true;
11931
11932 /*
11933 * FBC does not work on some platforms for rotated
11934 * planes, so disable it when rotation is not 0 and
11935 * update it when rotation is set back to 0.
11936 *
11937 * FIXME: This is redundant with the fbc update done in
11938 * the primary plane enable function except that that
11939 * one is done too late. We eventually need to unify
11940 * this.
11941 */
11942 if (intel_crtc->primary_enabled &&
11943 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11944 dev_priv->fbc.crtc == intel_crtc &&
11945 state->base.rotation != BIT(DRM_ROTATE_0)) {
11946 intel_crtc->atomic.disable_fbc = true;
11947 }
11948
11949 if (state->visible) {
11950 /*
11951 * BDW signals flip done immediately if the plane
11952 * is disabled, even if the plane enable is already
11953 * armed to occur at the next vblank :(
11954 */
11955 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
11956 intel_crtc->atomic.wait_vblank = true;
11957 }
11958
11959 intel_crtc->atomic.fb_bits |=
11960 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11961
11962 intel_crtc->atomic.update_fbc = true;
11963 }
11964
11965 return 0;
11966 }
11967
11968 static void
11969 intel_commit_primary_plane(struct drm_plane *plane,
11970 struct intel_plane_state *state)
11971 {
11972 struct drm_crtc *crtc = state->base.crtc;
11973 struct drm_framebuffer *fb = state->base.fb;
11974 struct drm_device *dev = plane->dev;
11975 struct drm_i915_private *dev_priv = dev->dev_private;
11976 struct intel_crtc *intel_crtc;
11977 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11978 struct intel_plane *intel_plane = to_intel_plane(plane);
11979 struct drm_rect *src = &state->src;
11980
11981 crtc = crtc ? crtc : plane->crtc;
11982 intel_crtc = to_intel_crtc(crtc);
11983
11984 plane->fb = fb;
11985 crtc->x = src->x1 >> 16;
11986 crtc->y = src->y1 >> 16;
11987
11988 intel_plane->obj = obj;
11989
11990 if (intel_crtc->active) {
11991 if (state->visible) {
11992 /* FIXME: kill this fastboot hack */
11993 intel_update_pipe_size(intel_crtc);
11994
11995 intel_crtc->primary_enabled = true;
11996
11997 dev_priv->display.update_primary_plane(crtc, plane->fb,
11998 crtc->x, crtc->y);
11999 } else {
12000 /*
12001 * If clipping results in a non-visible primary plane,
12002 * we'll disable the primary plane. Note that this is
12003 * a bit different than what happens if userspace
12004 * explicitly disables the plane by passing fb=0
12005 * because plane->fb still gets set and pinned.
12006 */
12007 intel_disable_primary_hw_plane(plane, crtc);
12008 }
12009 }
12010 }
12011
12012 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12013 {
12014 struct drm_device *dev = crtc->dev;
12015 struct drm_i915_private *dev_priv = dev->dev_private;
12016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12017 struct intel_plane *intel_plane;
12018 struct drm_plane *p;
12019 unsigned fb_bits = 0;
12020
12021 /* Track fb's for any planes being disabled */
12022 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12023 intel_plane = to_intel_plane(p);
12024
12025 if (intel_crtc->atomic.disabled_planes &
12026 (1 << drm_plane_index(p))) {
12027 switch (p->type) {
12028 case DRM_PLANE_TYPE_PRIMARY:
12029 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12030 break;
12031 case DRM_PLANE_TYPE_CURSOR:
12032 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12033 break;
12034 case DRM_PLANE_TYPE_OVERLAY:
12035 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12036 break;
12037 }
12038
12039 mutex_lock(&dev->struct_mutex);
12040 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12041 mutex_unlock(&dev->struct_mutex);
12042 }
12043 }
12044
12045 if (intel_crtc->atomic.wait_for_flips)
12046 intel_crtc_wait_for_pending_flips(crtc);
12047
12048 if (intel_crtc->atomic.disable_fbc)
12049 intel_fbc_disable(dev);
12050
12051 if (intel_crtc->atomic.pre_disable_primary)
12052 intel_pre_disable_primary(crtc);
12053
12054 if (intel_crtc->atomic.update_wm)
12055 intel_update_watermarks(crtc);
12056
12057 intel_runtime_pm_get(dev_priv);
12058
12059 /* Perform vblank evasion around commit operation */
12060 if (intel_crtc->active)
12061 intel_crtc->atomic.evade =
12062 intel_pipe_update_start(intel_crtc,
12063 &intel_crtc->atomic.start_vbl_count);
12064 }
12065
12066 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12067 {
12068 struct drm_device *dev = crtc->dev;
12069 struct drm_i915_private *dev_priv = dev->dev_private;
12070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12071 struct drm_plane *p;
12072
12073 if (intel_crtc->atomic.evade)
12074 intel_pipe_update_end(intel_crtc,
12075 intel_crtc->atomic.start_vbl_count);
12076
12077 intel_runtime_pm_put(dev_priv);
12078
12079 if (intel_crtc->atomic.wait_vblank)
12080 intel_wait_for_vblank(dev, intel_crtc->pipe);
12081
12082 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12083
12084 if (intel_crtc->atomic.update_fbc) {
12085 mutex_lock(&dev->struct_mutex);
12086 intel_fbc_update(dev);
12087 mutex_unlock(&dev->struct_mutex);
12088 }
12089
12090 if (intel_crtc->atomic.post_enable_primary)
12091 intel_post_enable_primary(crtc);
12092
12093 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12094 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12095 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12096 false, false);
12097
12098 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12099 }
12100
12101 /**
12102 * intel_plane_destroy - destroy a plane
12103 * @plane: plane to destroy
12104 *
12105 * Common destruction function for all types of planes (primary, cursor,
12106 * sprite).
12107 */
12108 void intel_plane_destroy(struct drm_plane *plane)
12109 {
12110 struct intel_plane *intel_plane = to_intel_plane(plane);
12111 drm_plane_cleanup(plane);
12112 kfree(intel_plane);
12113 }
12114
12115 const struct drm_plane_funcs intel_plane_funcs = {
12116 .update_plane = drm_atomic_helper_update_plane,
12117 .disable_plane = drm_atomic_helper_disable_plane,
12118 .destroy = intel_plane_destroy,
12119 .set_property = drm_atomic_helper_plane_set_property,
12120 .atomic_get_property = intel_plane_atomic_get_property,
12121 .atomic_set_property = intel_plane_atomic_set_property,
12122 .atomic_duplicate_state = intel_plane_duplicate_state,
12123 .atomic_destroy_state = intel_plane_destroy_state,
12124
12125 };
12126
12127 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12128 int pipe)
12129 {
12130 struct intel_plane *primary;
12131 struct intel_plane_state *state;
12132 const uint32_t *intel_primary_formats;
12133 int num_formats;
12134
12135 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12136 if (primary == NULL)
12137 return NULL;
12138
12139 state = intel_create_plane_state(&primary->base);
12140 if (!state) {
12141 kfree(primary);
12142 return NULL;
12143 }
12144 primary->base.state = &state->base;
12145
12146 primary->can_scale = false;
12147 primary->max_downscale = 1;
12148 primary->pipe = pipe;
12149 primary->plane = pipe;
12150 primary->check_plane = intel_check_primary_plane;
12151 primary->commit_plane = intel_commit_primary_plane;
12152 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12153 primary->plane = !pipe;
12154
12155 if (INTEL_INFO(dev)->gen <= 3) {
12156 intel_primary_formats = intel_primary_formats_gen2;
12157 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12158 } else {
12159 intel_primary_formats = intel_primary_formats_gen4;
12160 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12161 }
12162
12163 drm_universal_plane_init(dev, &primary->base, 0,
12164 &intel_plane_funcs,
12165 intel_primary_formats, num_formats,
12166 DRM_PLANE_TYPE_PRIMARY);
12167
12168 if (INTEL_INFO(dev)->gen >= 4) {
12169 if (!dev->mode_config.rotation_property)
12170 dev->mode_config.rotation_property =
12171 drm_mode_create_rotation_property(dev,
12172 BIT(DRM_ROTATE_0) |
12173 BIT(DRM_ROTATE_180));
12174 if (dev->mode_config.rotation_property)
12175 drm_object_attach_property(&primary->base.base,
12176 dev->mode_config.rotation_property,
12177 state->base.rotation);
12178 }
12179
12180 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12181
12182 return &primary->base;
12183 }
12184
12185 static int
12186 intel_check_cursor_plane(struct drm_plane *plane,
12187 struct intel_plane_state *state)
12188 {
12189 struct drm_crtc *crtc = state->base.crtc;
12190 struct drm_device *dev = plane->dev;
12191 struct drm_framebuffer *fb = state->base.fb;
12192 struct drm_rect *dest = &state->dst;
12193 struct drm_rect *src = &state->src;
12194 const struct drm_rect *clip = &state->clip;
12195 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12196 struct intel_crtc *intel_crtc;
12197 unsigned stride;
12198 int ret;
12199
12200 crtc = crtc ? crtc : plane->crtc;
12201 intel_crtc = to_intel_crtc(crtc);
12202
12203 ret = drm_plane_helper_check_update(plane, crtc, fb,
12204 src, dest, clip,
12205 DRM_PLANE_HELPER_NO_SCALING,
12206 DRM_PLANE_HELPER_NO_SCALING,
12207 true, true, &state->visible);
12208 if (ret)
12209 return ret;
12210
12211
12212 /* if we want to turn off the cursor ignore width and height */
12213 if (!obj)
12214 goto finish;
12215
12216 /* Check for which cursor types we support */
12217 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12218 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12219 state->base.crtc_w, state->base.crtc_h);
12220 return -EINVAL;
12221 }
12222
12223 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12224 if (obj->base.size < stride * state->base.crtc_h) {
12225 DRM_DEBUG_KMS("buffer is too small\n");
12226 return -ENOMEM;
12227 }
12228
12229 if (fb == crtc->cursor->fb)
12230 return 0;
12231
12232 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12233 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12234 ret = -EINVAL;
12235 }
12236
12237 finish:
12238 if (intel_crtc->active) {
12239 if (intel_crtc->cursor_width != state->base.crtc_w)
12240 intel_crtc->atomic.update_wm = true;
12241
12242 intel_crtc->atomic.fb_bits |=
12243 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12244 }
12245
12246 return ret;
12247 }
12248
12249 static void
12250 intel_commit_cursor_plane(struct drm_plane *plane,
12251 struct intel_plane_state *state)
12252 {
12253 struct drm_crtc *crtc = state->base.crtc;
12254 struct drm_device *dev = plane->dev;
12255 struct intel_crtc *intel_crtc;
12256 struct intel_plane *intel_plane = to_intel_plane(plane);
12257 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12258 uint32_t addr;
12259
12260 crtc = crtc ? crtc : plane->crtc;
12261 intel_crtc = to_intel_crtc(crtc);
12262
12263 plane->fb = state->base.fb;
12264 crtc->cursor_x = state->base.crtc_x;
12265 crtc->cursor_y = state->base.crtc_y;
12266
12267 intel_plane->obj = obj;
12268
12269 if (intel_crtc->cursor_bo == obj)
12270 goto update;
12271
12272 if (!obj)
12273 addr = 0;
12274 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12275 addr = i915_gem_obj_ggtt_offset(obj);
12276 else
12277 addr = obj->phys_handle->busaddr;
12278
12279 intel_crtc->cursor_addr = addr;
12280 intel_crtc->cursor_bo = obj;
12281 update:
12282 intel_crtc->cursor_width = state->base.crtc_w;
12283 intel_crtc->cursor_height = state->base.crtc_h;
12284
12285 if (intel_crtc->active)
12286 intel_crtc_update_cursor(crtc, state->visible);
12287 }
12288
12289 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12290 int pipe)
12291 {
12292 struct intel_plane *cursor;
12293 struct intel_plane_state *state;
12294
12295 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12296 if (cursor == NULL)
12297 return NULL;
12298
12299 state = intel_create_plane_state(&cursor->base);
12300 if (!state) {
12301 kfree(cursor);
12302 return NULL;
12303 }
12304 cursor->base.state = &state->base;
12305
12306 cursor->can_scale = false;
12307 cursor->max_downscale = 1;
12308 cursor->pipe = pipe;
12309 cursor->plane = pipe;
12310 cursor->check_plane = intel_check_cursor_plane;
12311 cursor->commit_plane = intel_commit_cursor_plane;
12312
12313 drm_universal_plane_init(dev, &cursor->base, 0,
12314 &intel_plane_funcs,
12315 intel_cursor_formats,
12316 ARRAY_SIZE(intel_cursor_formats),
12317 DRM_PLANE_TYPE_CURSOR);
12318
12319 if (INTEL_INFO(dev)->gen >= 4) {
12320 if (!dev->mode_config.rotation_property)
12321 dev->mode_config.rotation_property =
12322 drm_mode_create_rotation_property(dev,
12323 BIT(DRM_ROTATE_0) |
12324 BIT(DRM_ROTATE_180));
12325 if (dev->mode_config.rotation_property)
12326 drm_object_attach_property(&cursor->base.base,
12327 dev->mode_config.rotation_property,
12328 state->base.rotation);
12329 }
12330
12331 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12332
12333 return &cursor->base;
12334 }
12335
12336 static void intel_crtc_init(struct drm_device *dev, int pipe)
12337 {
12338 struct drm_i915_private *dev_priv = dev->dev_private;
12339 struct intel_crtc *intel_crtc;
12340 struct intel_crtc_state *crtc_state = NULL;
12341 struct drm_plane *primary = NULL;
12342 struct drm_plane *cursor = NULL;
12343 int i, ret;
12344
12345 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12346 if (intel_crtc == NULL)
12347 return;
12348
12349 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12350 if (!crtc_state)
12351 goto fail;
12352 intel_crtc_set_state(intel_crtc, crtc_state);
12353 crtc_state->base.crtc = &intel_crtc->base;
12354
12355 primary = intel_primary_plane_create(dev, pipe);
12356 if (!primary)
12357 goto fail;
12358
12359 cursor = intel_cursor_plane_create(dev, pipe);
12360 if (!cursor)
12361 goto fail;
12362
12363 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12364 cursor, &intel_crtc_funcs);
12365 if (ret)
12366 goto fail;
12367
12368 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12369 for (i = 0; i < 256; i++) {
12370 intel_crtc->lut_r[i] = i;
12371 intel_crtc->lut_g[i] = i;
12372 intel_crtc->lut_b[i] = i;
12373 }
12374
12375 /*
12376 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12377 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12378 */
12379 intel_crtc->pipe = pipe;
12380 intel_crtc->plane = pipe;
12381 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12382 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12383 intel_crtc->plane = !pipe;
12384 }
12385
12386 intel_crtc->cursor_base = ~0;
12387 intel_crtc->cursor_cntl = ~0;
12388 intel_crtc->cursor_size = ~0;
12389
12390 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12391 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12392 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12393 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12394
12395 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12396
12397 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12398
12399 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12400 return;
12401
12402 fail:
12403 if (primary)
12404 drm_plane_cleanup(primary);
12405 if (cursor)
12406 drm_plane_cleanup(cursor);
12407 kfree(crtc_state);
12408 kfree(intel_crtc);
12409 }
12410
12411 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12412 {
12413 struct drm_encoder *encoder = connector->base.encoder;
12414 struct drm_device *dev = connector->base.dev;
12415
12416 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12417
12418 if (!encoder || WARN_ON(!encoder->crtc))
12419 return INVALID_PIPE;
12420
12421 return to_intel_crtc(encoder->crtc)->pipe;
12422 }
12423
12424 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12425 struct drm_file *file)
12426 {
12427 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12428 struct drm_crtc *drmmode_crtc;
12429 struct intel_crtc *crtc;
12430
12431 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12432
12433 if (!drmmode_crtc) {
12434 DRM_ERROR("no such CRTC id\n");
12435 return -ENOENT;
12436 }
12437
12438 crtc = to_intel_crtc(drmmode_crtc);
12439 pipe_from_crtc_id->pipe = crtc->pipe;
12440
12441 return 0;
12442 }
12443
12444 static int intel_encoder_clones(struct intel_encoder *encoder)
12445 {
12446 struct drm_device *dev = encoder->base.dev;
12447 struct intel_encoder *source_encoder;
12448 int index_mask = 0;
12449 int entry = 0;
12450
12451 for_each_intel_encoder(dev, source_encoder) {
12452 if (encoders_cloneable(encoder, source_encoder))
12453 index_mask |= (1 << entry);
12454
12455 entry++;
12456 }
12457
12458 return index_mask;
12459 }
12460
12461 static bool has_edp_a(struct drm_device *dev)
12462 {
12463 struct drm_i915_private *dev_priv = dev->dev_private;
12464
12465 if (!IS_MOBILE(dev))
12466 return false;
12467
12468 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12469 return false;
12470
12471 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12472 return false;
12473
12474 return true;
12475 }
12476
12477 static bool intel_crt_present(struct drm_device *dev)
12478 {
12479 struct drm_i915_private *dev_priv = dev->dev_private;
12480
12481 if (INTEL_INFO(dev)->gen >= 9)
12482 return false;
12483
12484 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12485 return false;
12486
12487 if (IS_CHERRYVIEW(dev))
12488 return false;
12489
12490 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12491 return false;
12492
12493 return true;
12494 }
12495
12496 static void intel_setup_outputs(struct drm_device *dev)
12497 {
12498 struct drm_i915_private *dev_priv = dev->dev_private;
12499 struct intel_encoder *encoder;
12500 struct drm_connector *connector;
12501 bool dpd_is_edp = false;
12502
12503 intel_lvds_init(dev);
12504
12505 if (intel_crt_present(dev))
12506 intel_crt_init(dev);
12507
12508 if (HAS_DDI(dev)) {
12509 int found;
12510
12511 /* Haswell uses DDI functions to detect digital outputs */
12512 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12513 /* DDI A only supports eDP */
12514 if (found)
12515 intel_ddi_init(dev, PORT_A);
12516
12517 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12518 * register */
12519 found = I915_READ(SFUSE_STRAP);
12520
12521 if (found & SFUSE_STRAP_DDIB_DETECTED)
12522 intel_ddi_init(dev, PORT_B);
12523 if (found & SFUSE_STRAP_DDIC_DETECTED)
12524 intel_ddi_init(dev, PORT_C);
12525 if (found & SFUSE_STRAP_DDID_DETECTED)
12526 intel_ddi_init(dev, PORT_D);
12527 } else if (HAS_PCH_SPLIT(dev)) {
12528 int found;
12529 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12530
12531 if (has_edp_a(dev))
12532 intel_dp_init(dev, DP_A, PORT_A);
12533
12534 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12535 /* PCH SDVOB multiplex with HDMIB */
12536 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12537 if (!found)
12538 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12539 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12540 intel_dp_init(dev, PCH_DP_B, PORT_B);
12541 }
12542
12543 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12544 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12545
12546 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12547 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12548
12549 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12550 intel_dp_init(dev, PCH_DP_C, PORT_C);
12551
12552 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12553 intel_dp_init(dev, PCH_DP_D, PORT_D);
12554 } else if (IS_VALLEYVIEW(dev)) {
12555 /*
12556 * The DP_DETECTED bit is the latched state of the DDC
12557 * SDA pin at boot. However since eDP doesn't require DDC
12558 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12559 * eDP ports may have been muxed to an alternate function.
12560 * Thus we can't rely on the DP_DETECTED bit alone to detect
12561 * eDP ports. Consult the VBT as well as DP_DETECTED to
12562 * detect eDP ports.
12563 */
12564 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12565 !intel_dp_is_edp(dev, PORT_B))
12566 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12567 PORT_B);
12568 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12569 intel_dp_is_edp(dev, PORT_B))
12570 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12571
12572 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12573 !intel_dp_is_edp(dev, PORT_C))
12574 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12575 PORT_C);
12576 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12577 intel_dp_is_edp(dev, PORT_C))
12578 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12579
12580 if (IS_CHERRYVIEW(dev)) {
12581 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12582 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12583 PORT_D);
12584 /* eDP not supported on port D, so don't check VBT */
12585 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12586 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12587 }
12588
12589 intel_dsi_init(dev);
12590 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12591 bool found = false;
12592
12593 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12594 DRM_DEBUG_KMS("probing SDVOB\n");
12595 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12596 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12597 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12598 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12599 }
12600
12601 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12602 intel_dp_init(dev, DP_B, PORT_B);
12603 }
12604
12605 /* Before G4X SDVOC doesn't have its own detect register */
12606
12607 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12608 DRM_DEBUG_KMS("probing SDVOC\n");
12609 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12610 }
12611
12612 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12613
12614 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12615 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12616 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12617 }
12618 if (SUPPORTS_INTEGRATED_DP(dev))
12619 intel_dp_init(dev, DP_C, PORT_C);
12620 }
12621
12622 if (SUPPORTS_INTEGRATED_DP(dev) &&
12623 (I915_READ(DP_D) & DP_DETECTED))
12624 intel_dp_init(dev, DP_D, PORT_D);
12625 } else if (IS_GEN2(dev))
12626 intel_dvo_init(dev);
12627
12628 if (SUPPORTS_TV(dev))
12629 intel_tv_init(dev);
12630
12631 /*
12632 * FIXME: We don't have full atomic support yet, but we want to be
12633 * able to enable/test plane updates via the atomic interface in the
12634 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12635 * will take some atomic codepaths to lookup properties during
12636 * drmModeGetConnector() that unconditionally dereference
12637 * connector->state.
12638 *
12639 * We create a dummy connector state here for each connector to ensure
12640 * the DRM core doesn't try to dereference a NULL connector->state.
12641 * The actual connector properties will never be updated or contain
12642 * useful information, but since we're doing this specifically for
12643 * testing/debug of the plane operations (and only when a specific
12644 * kernel module option is given), that shouldn't really matter.
12645 *
12646 * Once atomic support for crtc's + connectors lands, this loop should
12647 * be removed since we'll be setting up real connector state, which
12648 * will contain Intel-specific properties.
12649 */
12650 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12651 list_for_each_entry(connector,
12652 &dev->mode_config.connector_list,
12653 head) {
12654 if (!WARN_ON(connector->state)) {
12655 connector->state =
12656 kzalloc(sizeof(*connector->state),
12657 GFP_KERNEL);
12658 }
12659 }
12660 }
12661
12662 intel_psr_init(dev);
12663
12664 for_each_intel_encoder(dev, encoder) {
12665 encoder->base.possible_crtcs = encoder->crtc_mask;
12666 encoder->base.possible_clones =
12667 intel_encoder_clones(encoder);
12668 }
12669
12670 intel_init_pch_refclk(dev);
12671
12672 drm_helper_move_panel_connectors_to_head(dev);
12673 }
12674
12675 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12676 {
12677 struct drm_device *dev = fb->dev;
12678 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12679
12680 drm_framebuffer_cleanup(fb);
12681 mutex_lock(&dev->struct_mutex);
12682 WARN_ON(!intel_fb->obj->framebuffer_references--);
12683 drm_gem_object_unreference(&intel_fb->obj->base);
12684 mutex_unlock(&dev->struct_mutex);
12685 kfree(intel_fb);
12686 }
12687
12688 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12689 struct drm_file *file,
12690 unsigned int *handle)
12691 {
12692 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12693 struct drm_i915_gem_object *obj = intel_fb->obj;
12694
12695 return drm_gem_handle_create(file, &obj->base, handle);
12696 }
12697
12698 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12699 .destroy = intel_user_framebuffer_destroy,
12700 .create_handle = intel_user_framebuffer_create_handle,
12701 };
12702
12703 static
12704 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12705 uint32_t pixel_format)
12706 {
12707 u32 gen = INTEL_INFO(dev)->gen;
12708
12709 if (gen >= 9) {
12710 /* "The stride in bytes must not exceed the of the size of 8K
12711 * pixels and 32K bytes."
12712 */
12713 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12714 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12715 return 32*1024;
12716 } else if (gen >= 4) {
12717 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12718 return 16*1024;
12719 else
12720 return 32*1024;
12721 } else if (gen >= 3) {
12722 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12723 return 8*1024;
12724 else
12725 return 16*1024;
12726 } else {
12727 /* XXX DSPC is limited to 4k tiled */
12728 return 8*1024;
12729 }
12730 }
12731
12732 static int intel_framebuffer_init(struct drm_device *dev,
12733 struct intel_framebuffer *intel_fb,
12734 struct drm_mode_fb_cmd2 *mode_cmd,
12735 struct drm_i915_gem_object *obj)
12736 {
12737 int aligned_height;
12738 int ret;
12739 u32 pitch_limit, stride_alignment;
12740
12741 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12742
12743 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12744 /* Enforce that fb modifier and tiling mode match, but only for
12745 * X-tiled. This is needed for FBC. */
12746 if (!!(obj->tiling_mode == I915_TILING_X) !=
12747 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12748 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12749 return -EINVAL;
12750 }
12751 } else {
12752 if (obj->tiling_mode == I915_TILING_X)
12753 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12754 else if (obj->tiling_mode == I915_TILING_Y) {
12755 DRM_DEBUG("No Y tiling for legacy addfb\n");
12756 return -EINVAL;
12757 }
12758 }
12759
12760 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED) {
12761 DRM_DEBUG("hardware does not support tiling Y\n");
12762 return -EINVAL;
12763 }
12764
12765 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12766 mode_cmd->pixel_format);
12767 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12768 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12769 mode_cmd->pitches[0], stride_alignment);
12770 return -EINVAL;
12771 }
12772
12773 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12774 mode_cmd->pixel_format);
12775 if (mode_cmd->pitches[0] > pitch_limit) {
12776 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12777 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12778 "tiled" : "linear",
12779 mode_cmd->pitches[0], pitch_limit);
12780 return -EINVAL;
12781 }
12782
12783 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12784 mode_cmd->pitches[0] != obj->stride) {
12785 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12786 mode_cmd->pitches[0], obj->stride);
12787 return -EINVAL;
12788 }
12789
12790 /* Reject formats not supported by any plane early. */
12791 switch (mode_cmd->pixel_format) {
12792 case DRM_FORMAT_C8:
12793 case DRM_FORMAT_RGB565:
12794 case DRM_FORMAT_XRGB8888:
12795 case DRM_FORMAT_ARGB8888:
12796 break;
12797 case DRM_FORMAT_XRGB1555:
12798 case DRM_FORMAT_ARGB1555:
12799 if (INTEL_INFO(dev)->gen > 3) {
12800 DRM_DEBUG("unsupported pixel format: %s\n",
12801 drm_get_format_name(mode_cmd->pixel_format));
12802 return -EINVAL;
12803 }
12804 break;
12805 case DRM_FORMAT_XBGR8888:
12806 case DRM_FORMAT_ABGR8888:
12807 case DRM_FORMAT_XRGB2101010:
12808 case DRM_FORMAT_ARGB2101010:
12809 case DRM_FORMAT_XBGR2101010:
12810 case DRM_FORMAT_ABGR2101010:
12811 if (INTEL_INFO(dev)->gen < 4) {
12812 DRM_DEBUG("unsupported pixel format: %s\n",
12813 drm_get_format_name(mode_cmd->pixel_format));
12814 return -EINVAL;
12815 }
12816 break;
12817 case DRM_FORMAT_YUYV:
12818 case DRM_FORMAT_UYVY:
12819 case DRM_FORMAT_YVYU:
12820 case DRM_FORMAT_VYUY:
12821 if (INTEL_INFO(dev)->gen < 5) {
12822 DRM_DEBUG("unsupported pixel format: %s\n",
12823 drm_get_format_name(mode_cmd->pixel_format));
12824 return -EINVAL;
12825 }
12826 break;
12827 default:
12828 DRM_DEBUG("unsupported pixel format: %s\n",
12829 drm_get_format_name(mode_cmd->pixel_format));
12830 return -EINVAL;
12831 }
12832
12833 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12834 if (mode_cmd->offsets[0] != 0)
12835 return -EINVAL;
12836
12837 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12838 mode_cmd->pixel_format,
12839 mode_cmd->modifier[0]);
12840 /* FIXME drm helper for size checks (especially planar formats)? */
12841 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12842 return -EINVAL;
12843
12844 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12845 intel_fb->obj = obj;
12846 intel_fb->obj->framebuffer_references++;
12847
12848 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12849 if (ret) {
12850 DRM_ERROR("framebuffer init failed %d\n", ret);
12851 return ret;
12852 }
12853
12854 return 0;
12855 }
12856
12857 static struct drm_framebuffer *
12858 intel_user_framebuffer_create(struct drm_device *dev,
12859 struct drm_file *filp,
12860 struct drm_mode_fb_cmd2 *mode_cmd)
12861 {
12862 struct drm_i915_gem_object *obj;
12863
12864 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12865 mode_cmd->handles[0]));
12866 if (&obj->base == NULL)
12867 return ERR_PTR(-ENOENT);
12868
12869 return intel_framebuffer_create(dev, mode_cmd, obj);
12870 }
12871
12872 #ifndef CONFIG_DRM_I915_FBDEV
12873 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12874 {
12875 }
12876 #endif
12877
12878 static const struct drm_mode_config_funcs intel_mode_funcs = {
12879 .fb_create = intel_user_framebuffer_create,
12880 .output_poll_changed = intel_fbdev_output_poll_changed,
12881 .atomic_check = intel_atomic_check,
12882 .atomic_commit = intel_atomic_commit,
12883 };
12884
12885 /* Set up chip specific display functions */
12886 static void intel_init_display(struct drm_device *dev)
12887 {
12888 struct drm_i915_private *dev_priv = dev->dev_private;
12889
12890 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12891 dev_priv->display.find_dpll = g4x_find_best_dpll;
12892 else if (IS_CHERRYVIEW(dev))
12893 dev_priv->display.find_dpll = chv_find_best_dpll;
12894 else if (IS_VALLEYVIEW(dev))
12895 dev_priv->display.find_dpll = vlv_find_best_dpll;
12896 else if (IS_PINEVIEW(dev))
12897 dev_priv->display.find_dpll = pnv_find_best_dpll;
12898 else
12899 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12900
12901 if (INTEL_INFO(dev)->gen >= 9) {
12902 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12903 dev_priv->display.get_initial_plane_config =
12904 skylake_get_initial_plane_config;
12905 dev_priv->display.crtc_compute_clock =
12906 haswell_crtc_compute_clock;
12907 dev_priv->display.crtc_enable = haswell_crtc_enable;
12908 dev_priv->display.crtc_disable = haswell_crtc_disable;
12909 dev_priv->display.off = ironlake_crtc_off;
12910 dev_priv->display.update_primary_plane =
12911 skylake_update_primary_plane;
12912 } else if (HAS_DDI(dev)) {
12913 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12914 dev_priv->display.get_initial_plane_config =
12915 ironlake_get_initial_plane_config;
12916 dev_priv->display.crtc_compute_clock =
12917 haswell_crtc_compute_clock;
12918 dev_priv->display.crtc_enable = haswell_crtc_enable;
12919 dev_priv->display.crtc_disable = haswell_crtc_disable;
12920 dev_priv->display.off = ironlake_crtc_off;
12921 dev_priv->display.update_primary_plane =
12922 ironlake_update_primary_plane;
12923 } else if (HAS_PCH_SPLIT(dev)) {
12924 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12925 dev_priv->display.get_initial_plane_config =
12926 ironlake_get_initial_plane_config;
12927 dev_priv->display.crtc_compute_clock =
12928 ironlake_crtc_compute_clock;
12929 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12930 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12931 dev_priv->display.off = ironlake_crtc_off;
12932 dev_priv->display.update_primary_plane =
12933 ironlake_update_primary_plane;
12934 } else if (IS_VALLEYVIEW(dev)) {
12935 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12936 dev_priv->display.get_initial_plane_config =
12937 i9xx_get_initial_plane_config;
12938 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12939 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12940 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12941 dev_priv->display.off = i9xx_crtc_off;
12942 dev_priv->display.update_primary_plane =
12943 i9xx_update_primary_plane;
12944 } else {
12945 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12946 dev_priv->display.get_initial_plane_config =
12947 i9xx_get_initial_plane_config;
12948 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12949 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12950 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12951 dev_priv->display.off = i9xx_crtc_off;
12952 dev_priv->display.update_primary_plane =
12953 i9xx_update_primary_plane;
12954 }
12955
12956 /* Returns the core display clock speed */
12957 if (IS_VALLEYVIEW(dev))
12958 dev_priv->display.get_display_clock_speed =
12959 valleyview_get_display_clock_speed;
12960 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12961 dev_priv->display.get_display_clock_speed =
12962 i945_get_display_clock_speed;
12963 else if (IS_I915G(dev))
12964 dev_priv->display.get_display_clock_speed =
12965 i915_get_display_clock_speed;
12966 else if (IS_I945GM(dev) || IS_845G(dev))
12967 dev_priv->display.get_display_clock_speed =
12968 i9xx_misc_get_display_clock_speed;
12969 else if (IS_PINEVIEW(dev))
12970 dev_priv->display.get_display_clock_speed =
12971 pnv_get_display_clock_speed;
12972 else if (IS_I915GM(dev))
12973 dev_priv->display.get_display_clock_speed =
12974 i915gm_get_display_clock_speed;
12975 else if (IS_I865G(dev))
12976 dev_priv->display.get_display_clock_speed =
12977 i865_get_display_clock_speed;
12978 else if (IS_I85X(dev))
12979 dev_priv->display.get_display_clock_speed =
12980 i855_get_display_clock_speed;
12981 else /* 852, 830 */
12982 dev_priv->display.get_display_clock_speed =
12983 i830_get_display_clock_speed;
12984
12985 if (IS_GEN5(dev)) {
12986 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12987 } else if (IS_GEN6(dev)) {
12988 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12989 } else if (IS_IVYBRIDGE(dev)) {
12990 /* FIXME: detect B0+ stepping and use auto training */
12991 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12992 dev_priv->display.modeset_global_resources =
12993 ivb_modeset_global_resources;
12994 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12995 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12996 } else if (IS_VALLEYVIEW(dev)) {
12997 dev_priv->display.modeset_global_resources =
12998 valleyview_modeset_global_resources;
12999 }
13000
13001 switch (INTEL_INFO(dev)->gen) {
13002 case 2:
13003 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13004 break;
13005
13006 case 3:
13007 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13008 break;
13009
13010 case 4:
13011 case 5:
13012 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13013 break;
13014
13015 case 6:
13016 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13017 break;
13018 case 7:
13019 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13020 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13021 break;
13022 case 9:
13023 /* Drop through - unsupported since execlist only. */
13024 default:
13025 /* Default just returns -ENODEV to indicate unsupported */
13026 dev_priv->display.queue_flip = intel_default_queue_flip;
13027 }
13028
13029 intel_panel_init_backlight_funcs(dev);
13030
13031 mutex_init(&dev_priv->pps_mutex);
13032 }
13033
13034 /*
13035 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13036 * resume, or other times. This quirk makes sure that's the case for
13037 * affected systems.
13038 */
13039 static void quirk_pipea_force(struct drm_device *dev)
13040 {
13041 struct drm_i915_private *dev_priv = dev->dev_private;
13042
13043 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13044 DRM_INFO("applying pipe a force quirk\n");
13045 }
13046
13047 static void quirk_pipeb_force(struct drm_device *dev)
13048 {
13049 struct drm_i915_private *dev_priv = dev->dev_private;
13050
13051 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13052 DRM_INFO("applying pipe b force quirk\n");
13053 }
13054
13055 /*
13056 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13057 */
13058 static void quirk_ssc_force_disable(struct drm_device *dev)
13059 {
13060 struct drm_i915_private *dev_priv = dev->dev_private;
13061 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13062 DRM_INFO("applying lvds SSC disable quirk\n");
13063 }
13064
13065 /*
13066 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13067 * brightness value
13068 */
13069 static void quirk_invert_brightness(struct drm_device *dev)
13070 {
13071 struct drm_i915_private *dev_priv = dev->dev_private;
13072 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13073 DRM_INFO("applying inverted panel brightness quirk\n");
13074 }
13075
13076 /* Some VBT's incorrectly indicate no backlight is present */
13077 static void quirk_backlight_present(struct drm_device *dev)
13078 {
13079 struct drm_i915_private *dev_priv = dev->dev_private;
13080 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13081 DRM_INFO("applying backlight present quirk\n");
13082 }
13083
13084 struct intel_quirk {
13085 int device;
13086 int subsystem_vendor;
13087 int subsystem_device;
13088 void (*hook)(struct drm_device *dev);
13089 };
13090
13091 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13092 struct intel_dmi_quirk {
13093 void (*hook)(struct drm_device *dev);
13094 const struct dmi_system_id (*dmi_id_list)[];
13095 };
13096
13097 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13098 {
13099 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13100 return 1;
13101 }
13102
13103 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13104 {
13105 .dmi_id_list = &(const struct dmi_system_id[]) {
13106 {
13107 .callback = intel_dmi_reverse_brightness,
13108 .ident = "NCR Corporation",
13109 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13110 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13111 },
13112 },
13113 { } /* terminating entry */
13114 },
13115 .hook = quirk_invert_brightness,
13116 },
13117 };
13118
13119 static struct intel_quirk intel_quirks[] = {
13120 /* HP Mini needs pipe A force quirk (LP: #322104) */
13121 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13122
13123 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13124 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13125
13126 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13127 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13128
13129 /* 830 needs to leave pipe A & dpll A up */
13130 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13131
13132 /* 830 needs to leave pipe B & dpll B up */
13133 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13134
13135 /* Lenovo U160 cannot use SSC on LVDS */
13136 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13137
13138 /* Sony Vaio Y cannot use SSC on LVDS */
13139 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13140
13141 /* Acer Aspire 5734Z must invert backlight brightness */
13142 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13143
13144 /* Acer/eMachines G725 */
13145 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13146
13147 /* Acer/eMachines e725 */
13148 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13149
13150 /* Acer/Packard Bell NCL20 */
13151 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13152
13153 /* Acer Aspire 4736Z */
13154 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13155
13156 /* Acer Aspire 5336 */
13157 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13158
13159 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13160 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13161
13162 /* Acer C720 Chromebook (Core i3 4005U) */
13163 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13164
13165 /* Apple Macbook 2,1 (Core 2 T7400) */
13166 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13167
13168 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13169 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13170
13171 /* HP Chromebook 14 (Celeron 2955U) */
13172 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13173 };
13174
13175 static void intel_init_quirks(struct drm_device *dev)
13176 {
13177 struct pci_dev *d = dev->pdev;
13178 int i;
13179
13180 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13181 struct intel_quirk *q = &intel_quirks[i];
13182
13183 if (d->device == q->device &&
13184 (d->subsystem_vendor == q->subsystem_vendor ||
13185 q->subsystem_vendor == PCI_ANY_ID) &&
13186 (d->subsystem_device == q->subsystem_device ||
13187 q->subsystem_device == PCI_ANY_ID))
13188 q->hook(dev);
13189 }
13190 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13191 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13192 intel_dmi_quirks[i].hook(dev);
13193 }
13194 }
13195
13196 /* Disable the VGA plane that we never use */
13197 static void i915_disable_vga(struct drm_device *dev)
13198 {
13199 struct drm_i915_private *dev_priv = dev->dev_private;
13200 u8 sr1;
13201 u32 vga_reg = i915_vgacntrl_reg(dev);
13202
13203 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13204 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13205 outb(SR01, VGA_SR_INDEX);
13206 sr1 = inb(VGA_SR_DATA);
13207 outb(sr1 | 1<<5, VGA_SR_DATA);
13208 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13209 udelay(300);
13210
13211 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13212 POSTING_READ(vga_reg);
13213 }
13214
13215 void intel_modeset_init_hw(struct drm_device *dev)
13216 {
13217 intel_prepare_ddi(dev);
13218
13219 if (IS_VALLEYVIEW(dev))
13220 vlv_update_cdclk(dev);
13221
13222 intel_init_clock_gating(dev);
13223
13224 intel_enable_gt_powersave(dev);
13225 }
13226
13227 void intel_modeset_init(struct drm_device *dev)
13228 {
13229 struct drm_i915_private *dev_priv = dev->dev_private;
13230 int sprite, ret;
13231 enum pipe pipe;
13232 struct intel_crtc *crtc;
13233
13234 drm_mode_config_init(dev);
13235
13236 dev->mode_config.min_width = 0;
13237 dev->mode_config.min_height = 0;
13238
13239 dev->mode_config.preferred_depth = 24;
13240 dev->mode_config.prefer_shadow = 1;
13241
13242 dev->mode_config.allow_fb_modifiers = true;
13243
13244 dev->mode_config.funcs = &intel_mode_funcs;
13245
13246 intel_init_quirks(dev);
13247
13248 intel_init_pm(dev);
13249
13250 if (INTEL_INFO(dev)->num_pipes == 0)
13251 return;
13252
13253 intel_init_display(dev);
13254 intel_init_audio(dev);
13255
13256 if (IS_GEN2(dev)) {
13257 dev->mode_config.max_width = 2048;
13258 dev->mode_config.max_height = 2048;
13259 } else if (IS_GEN3(dev)) {
13260 dev->mode_config.max_width = 4096;
13261 dev->mode_config.max_height = 4096;
13262 } else {
13263 dev->mode_config.max_width = 8192;
13264 dev->mode_config.max_height = 8192;
13265 }
13266
13267 if (IS_845G(dev) || IS_I865G(dev)) {
13268 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13269 dev->mode_config.cursor_height = 1023;
13270 } else if (IS_GEN2(dev)) {
13271 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13272 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13273 } else {
13274 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13275 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13276 }
13277
13278 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13279
13280 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13281 INTEL_INFO(dev)->num_pipes,
13282 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13283
13284 for_each_pipe(dev_priv, pipe) {
13285 intel_crtc_init(dev, pipe);
13286 for_each_sprite(pipe, sprite) {
13287 ret = intel_plane_init(dev, pipe, sprite);
13288 if (ret)
13289 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13290 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13291 }
13292 }
13293
13294 intel_init_dpio(dev);
13295
13296 intel_shared_dpll_init(dev);
13297
13298 /* Just disable it once at startup */
13299 i915_disable_vga(dev);
13300 intel_setup_outputs(dev);
13301
13302 /* Just in case the BIOS is doing something questionable. */
13303 intel_fbc_disable(dev);
13304
13305 drm_modeset_lock_all(dev);
13306 intel_modeset_setup_hw_state(dev, false);
13307 drm_modeset_unlock_all(dev);
13308
13309 for_each_intel_crtc(dev, crtc) {
13310 if (!crtc->active)
13311 continue;
13312
13313 /*
13314 * Note that reserving the BIOS fb up front prevents us
13315 * from stuffing other stolen allocations like the ring
13316 * on top. This prevents some ugliness at boot time, and
13317 * can even allow for smooth boot transitions if the BIOS
13318 * fb is large enough for the active pipe configuration.
13319 */
13320 if (dev_priv->display.get_initial_plane_config) {
13321 dev_priv->display.get_initial_plane_config(crtc,
13322 &crtc->plane_config);
13323 /*
13324 * If the fb is shared between multiple heads, we'll
13325 * just get the first one.
13326 */
13327 intel_find_plane_obj(crtc, &crtc->plane_config);
13328 }
13329 }
13330 }
13331
13332 static void intel_enable_pipe_a(struct drm_device *dev)
13333 {
13334 struct intel_connector *connector;
13335 struct drm_connector *crt = NULL;
13336 struct intel_load_detect_pipe load_detect_temp;
13337 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13338
13339 /* We can't just switch on the pipe A, we need to set things up with a
13340 * proper mode and output configuration. As a gross hack, enable pipe A
13341 * by enabling the load detect pipe once. */
13342 list_for_each_entry(connector,
13343 &dev->mode_config.connector_list,
13344 base.head) {
13345 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13346 crt = &connector->base;
13347 break;
13348 }
13349 }
13350
13351 if (!crt)
13352 return;
13353
13354 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13355 intel_release_load_detect_pipe(crt, &load_detect_temp);
13356 }
13357
13358 static bool
13359 intel_check_plane_mapping(struct intel_crtc *crtc)
13360 {
13361 struct drm_device *dev = crtc->base.dev;
13362 struct drm_i915_private *dev_priv = dev->dev_private;
13363 u32 reg, val;
13364
13365 if (INTEL_INFO(dev)->num_pipes == 1)
13366 return true;
13367
13368 reg = DSPCNTR(!crtc->plane);
13369 val = I915_READ(reg);
13370
13371 if ((val & DISPLAY_PLANE_ENABLE) &&
13372 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13373 return false;
13374
13375 return true;
13376 }
13377
13378 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13379 {
13380 struct drm_device *dev = crtc->base.dev;
13381 struct drm_i915_private *dev_priv = dev->dev_private;
13382 u32 reg;
13383
13384 /* Clear any frame start delays used for debugging left by the BIOS */
13385 reg = PIPECONF(crtc->config->cpu_transcoder);
13386 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13387
13388 /* restore vblank interrupts to correct state */
13389 drm_crtc_vblank_reset(&crtc->base);
13390 if (crtc->active) {
13391 update_scanline_offset(crtc);
13392 drm_crtc_vblank_on(&crtc->base);
13393 }
13394
13395 /* We need to sanitize the plane -> pipe mapping first because this will
13396 * disable the crtc (and hence change the state) if it is wrong. Note
13397 * that gen4+ has a fixed plane -> pipe mapping. */
13398 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13399 struct intel_connector *connector;
13400 bool plane;
13401
13402 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13403 crtc->base.base.id);
13404
13405 /* Pipe has the wrong plane attached and the plane is active.
13406 * Temporarily change the plane mapping and disable everything
13407 * ... */
13408 plane = crtc->plane;
13409 crtc->plane = !plane;
13410 crtc->primary_enabled = true;
13411 dev_priv->display.crtc_disable(&crtc->base);
13412 crtc->plane = plane;
13413
13414 /* ... and break all links. */
13415 list_for_each_entry(connector, &dev->mode_config.connector_list,
13416 base.head) {
13417 if (connector->encoder->base.crtc != &crtc->base)
13418 continue;
13419
13420 connector->base.dpms = DRM_MODE_DPMS_OFF;
13421 connector->base.encoder = NULL;
13422 }
13423 /* multiple connectors may have the same encoder:
13424 * handle them and break crtc link separately */
13425 list_for_each_entry(connector, &dev->mode_config.connector_list,
13426 base.head)
13427 if (connector->encoder->base.crtc == &crtc->base) {
13428 connector->encoder->base.crtc = NULL;
13429 connector->encoder->connectors_active = false;
13430 }
13431
13432 WARN_ON(crtc->active);
13433 crtc->base.state->enable = false;
13434 crtc->base.enabled = false;
13435 }
13436
13437 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13438 crtc->pipe == PIPE_A && !crtc->active) {
13439 /* BIOS forgot to enable pipe A, this mostly happens after
13440 * resume. Force-enable the pipe to fix this, the update_dpms
13441 * call below we restore the pipe to the right state, but leave
13442 * the required bits on. */
13443 intel_enable_pipe_a(dev);
13444 }
13445
13446 /* Adjust the state of the output pipe according to whether we
13447 * have active connectors/encoders. */
13448 intel_crtc_update_dpms(&crtc->base);
13449
13450 if (crtc->active != crtc->base.state->enable) {
13451 struct intel_encoder *encoder;
13452
13453 /* This can happen either due to bugs in the get_hw_state
13454 * functions or because the pipe is force-enabled due to the
13455 * pipe A quirk. */
13456 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13457 crtc->base.base.id,
13458 crtc->base.state->enable ? "enabled" : "disabled",
13459 crtc->active ? "enabled" : "disabled");
13460
13461 crtc->base.state->enable = crtc->active;
13462 crtc->base.enabled = crtc->active;
13463
13464 /* Because we only establish the connector -> encoder ->
13465 * crtc links if something is active, this means the
13466 * crtc is now deactivated. Break the links. connector
13467 * -> encoder links are only establish when things are
13468 * actually up, hence no need to break them. */
13469 WARN_ON(crtc->active);
13470
13471 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13472 WARN_ON(encoder->connectors_active);
13473 encoder->base.crtc = NULL;
13474 }
13475 }
13476
13477 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13478 /*
13479 * We start out with underrun reporting disabled to avoid races.
13480 * For correct bookkeeping mark this on active crtcs.
13481 *
13482 * Also on gmch platforms we dont have any hardware bits to
13483 * disable the underrun reporting. Which means we need to start
13484 * out with underrun reporting disabled also on inactive pipes,
13485 * since otherwise we'll complain about the garbage we read when
13486 * e.g. coming up after runtime pm.
13487 *
13488 * No protection against concurrent access is required - at
13489 * worst a fifo underrun happens which also sets this to false.
13490 */
13491 crtc->cpu_fifo_underrun_disabled = true;
13492 crtc->pch_fifo_underrun_disabled = true;
13493 }
13494 }
13495
13496 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13497 {
13498 struct intel_connector *connector;
13499 struct drm_device *dev = encoder->base.dev;
13500
13501 /* We need to check both for a crtc link (meaning that the
13502 * encoder is active and trying to read from a pipe) and the
13503 * pipe itself being active. */
13504 bool has_active_crtc = encoder->base.crtc &&
13505 to_intel_crtc(encoder->base.crtc)->active;
13506
13507 if (encoder->connectors_active && !has_active_crtc) {
13508 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13509 encoder->base.base.id,
13510 encoder->base.name);
13511
13512 /* Connector is active, but has no active pipe. This is
13513 * fallout from our resume register restoring. Disable
13514 * the encoder manually again. */
13515 if (encoder->base.crtc) {
13516 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13517 encoder->base.base.id,
13518 encoder->base.name);
13519 encoder->disable(encoder);
13520 if (encoder->post_disable)
13521 encoder->post_disable(encoder);
13522 }
13523 encoder->base.crtc = NULL;
13524 encoder->connectors_active = false;
13525
13526 /* Inconsistent output/port/pipe state happens presumably due to
13527 * a bug in one of the get_hw_state functions. Or someplace else
13528 * in our code, like the register restore mess on resume. Clamp
13529 * things to off as a safer default. */
13530 list_for_each_entry(connector,
13531 &dev->mode_config.connector_list,
13532 base.head) {
13533 if (connector->encoder != encoder)
13534 continue;
13535 connector->base.dpms = DRM_MODE_DPMS_OFF;
13536 connector->base.encoder = NULL;
13537 }
13538 }
13539 /* Enabled encoders without active connectors will be fixed in
13540 * the crtc fixup. */
13541 }
13542
13543 void i915_redisable_vga_power_on(struct drm_device *dev)
13544 {
13545 struct drm_i915_private *dev_priv = dev->dev_private;
13546 u32 vga_reg = i915_vgacntrl_reg(dev);
13547
13548 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13549 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13550 i915_disable_vga(dev);
13551 }
13552 }
13553
13554 void i915_redisable_vga(struct drm_device *dev)
13555 {
13556 struct drm_i915_private *dev_priv = dev->dev_private;
13557
13558 /* This function can be called both from intel_modeset_setup_hw_state or
13559 * at a very early point in our resume sequence, where the power well
13560 * structures are not yet restored. Since this function is at a very
13561 * paranoid "someone might have enabled VGA while we were not looking"
13562 * level, just check if the power well is enabled instead of trying to
13563 * follow the "don't touch the power well if we don't need it" policy
13564 * the rest of the driver uses. */
13565 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13566 return;
13567
13568 i915_redisable_vga_power_on(dev);
13569 }
13570
13571 static bool primary_get_hw_state(struct intel_crtc *crtc)
13572 {
13573 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13574
13575 if (!crtc->active)
13576 return false;
13577
13578 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13579 }
13580
13581 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13582 {
13583 struct drm_i915_private *dev_priv = dev->dev_private;
13584 enum pipe pipe;
13585 struct intel_crtc *crtc;
13586 struct intel_encoder *encoder;
13587 struct intel_connector *connector;
13588 int i;
13589
13590 for_each_intel_crtc(dev, crtc) {
13591 memset(crtc->config, 0, sizeof(*crtc->config));
13592
13593 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13594
13595 crtc->active = dev_priv->display.get_pipe_config(crtc,
13596 crtc->config);
13597
13598 crtc->base.state->enable = crtc->active;
13599 crtc->base.enabled = crtc->active;
13600 crtc->primary_enabled = primary_get_hw_state(crtc);
13601
13602 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13603 crtc->base.base.id,
13604 crtc->active ? "enabled" : "disabled");
13605 }
13606
13607 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13608 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13609
13610 pll->on = pll->get_hw_state(dev_priv, pll,
13611 &pll->config.hw_state);
13612 pll->active = 0;
13613 pll->config.crtc_mask = 0;
13614 for_each_intel_crtc(dev, crtc) {
13615 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13616 pll->active++;
13617 pll->config.crtc_mask |= 1 << crtc->pipe;
13618 }
13619 }
13620
13621 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13622 pll->name, pll->config.crtc_mask, pll->on);
13623
13624 if (pll->config.crtc_mask)
13625 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13626 }
13627
13628 for_each_intel_encoder(dev, encoder) {
13629 pipe = 0;
13630
13631 if (encoder->get_hw_state(encoder, &pipe)) {
13632 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13633 encoder->base.crtc = &crtc->base;
13634 encoder->get_config(encoder, crtc->config);
13635 } else {
13636 encoder->base.crtc = NULL;
13637 }
13638
13639 encoder->connectors_active = false;
13640 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13641 encoder->base.base.id,
13642 encoder->base.name,
13643 encoder->base.crtc ? "enabled" : "disabled",
13644 pipe_name(pipe));
13645 }
13646
13647 list_for_each_entry(connector, &dev->mode_config.connector_list,
13648 base.head) {
13649 if (connector->get_hw_state(connector)) {
13650 connector->base.dpms = DRM_MODE_DPMS_ON;
13651 connector->encoder->connectors_active = true;
13652 connector->base.encoder = &connector->encoder->base;
13653 } else {
13654 connector->base.dpms = DRM_MODE_DPMS_OFF;
13655 connector->base.encoder = NULL;
13656 }
13657 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13658 connector->base.base.id,
13659 connector->base.name,
13660 connector->base.encoder ? "enabled" : "disabled");
13661 }
13662 }
13663
13664 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13665 * and i915 state tracking structures. */
13666 void intel_modeset_setup_hw_state(struct drm_device *dev,
13667 bool force_restore)
13668 {
13669 struct drm_i915_private *dev_priv = dev->dev_private;
13670 enum pipe pipe;
13671 struct intel_crtc *crtc;
13672 struct intel_encoder *encoder;
13673 int i;
13674
13675 intel_modeset_readout_hw_state(dev);
13676
13677 /*
13678 * Now that we have the config, copy it to each CRTC struct
13679 * Note that this could go away if we move to using crtc_config
13680 * checking everywhere.
13681 */
13682 for_each_intel_crtc(dev, crtc) {
13683 if (crtc->active && i915.fastboot) {
13684 intel_mode_from_pipe_config(&crtc->base.mode,
13685 crtc->config);
13686 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13687 crtc->base.base.id);
13688 drm_mode_debug_printmodeline(&crtc->base.mode);
13689 }
13690 }
13691
13692 /* HW state is read out, now we need to sanitize this mess. */
13693 for_each_intel_encoder(dev, encoder) {
13694 intel_sanitize_encoder(encoder);
13695 }
13696
13697 for_each_pipe(dev_priv, pipe) {
13698 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13699 intel_sanitize_crtc(crtc);
13700 intel_dump_pipe_config(crtc, crtc->config,
13701 "[setup_hw_state]");
13702 }
13703
13704 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13705 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13706
13707 if (!pll->on || pll->active)
13708 continue;
13709
13710 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13711
13712 pll->disable(dev_priv, pll);
13713 pll->on = false;
13714 }
13715
13716 if (IS_GEN9(dev))
13717 skl_wm_get_hw_state(dev);
13718 else if (HAS_PCH_SPLIT(dev))
13719 ilk_wm_get_hw_state(dev);
13720
13721 if (force_restore) {
13722 i915_redisable_vga(dev);
13723
13724 /*
13725 * We need to use raw interfaces for restoring state to avoid
13726 * checking (bogus) intermediate states.
13727 */
13728 for_each_pipe(dev_priv, pipe) {
13729 struct drm_crtc *crtc =
13730 dev_priv->pipe_to_crtc_mapping[pipe];
13731
13732 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13733 crtc->primary->fb);
13734 }
13735 } else {
13736 intel_modeset_update_staged_output_state(dev);
13737 }
13738
13739 intel_modeset_check_state(dev);
13740 }
13741
13742 void intel_modeset_gem_init(struct drm_device *dev)
13743 {
13744 struct drm_i915_private *dev_priv = dev->dev_private;
13745 struct drm_crtc *c;
13746 struct drm_i915_gem_object *obj;
13747
13748 mutex_lock(&dev->struct_mutex);
13749 intel_init_gt_powersave(dev);
13750 mutex_unlock(&dev->struct_mutex);
13751
13752 /*
13753 * There may be no VBT; and if the BIOS enabled SSC we can
13754 * just keep using it to avoid unnecessary flicker. Whereas if the
13755 * BIOS isn't using it, don't assume it will work even if the VBT
13756 * indicates as much.
13757 */
13758 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13759 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13760 DREF_SSC1_ENABLE);
13761
13762 intel_modeset_init_hw(dev);
13763
13764 intel_setup_overlay(dev);
13765
13766 /*
13767 * Make sure any fbs we allocated at startup are properly
13768 * pinned & fenced. When we do the allocation it's too early
13769 * for this.
13770 */
13771 mutex_lock(&dev->struct_mutex);
13772 for_each_crtc(dev, c) {
13773 obj = intel_fb_obj(c->primary->fb);
13774 if (obj == NULL)
13775 continue;
13776
13777 if (intel_pin_and_fence_fb_obj(c->primary,
13778 c->primary->fb,
13779 NULL)) {
13780 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13781 to_intel_crtc(c)->pipe);
13782 drm_framebuffer_unreference(c->primary->fb);
13783 c->primary->fb = NULL;
13784 update_state_fb(c->primary);
13785 }
13786 }
13787 mutex_unlock(&dev->struct_mutex);
13788
13789 intel_backlight_register(dev);
13790 }
13791
13792 void intel_connector_unregister(struct intel_connector *intel_connector)
13793 {
13794 struct drm_connector *connector = &intel_connector->base;
13795
13796 intel_panel_destroy_backlight(connector);
13797 drm_connector_unregister(connector);
13798 }
13799
13800 void intel_modeset_cleanup(struct drm_device *dev)
13801 {
13802 struct drm_i915_private *dev_priv = dev->dev_private;
13803 struct drm_connector *connector;
13804
13805 intel_disable_gt_powersave(dev);
13806
13807 intel_backlight_unregister(dev);
13808
13809 /*
13810 * Interrupts and polling as the first thing to avoid creating havoc.
13811 * Too much stuff here (turning of connectors, ...) would
13812 * experience fancy races otherwise.
13813 */
13814 intel_irq_uninstall(dev_priv);
13815
13816 /*
13817 * Due to the hpd irq storm handling the hotplug work can re-arm the
13818 * poll handlers. Hence disable polling after hpd handling is shut down.
13819 */
13820 drm_kms_helper_poll_fini(dev);
13821
13822 mutex_lock(&dev->struct_mutex);
13823
13824 intel_unregister_dsm_handler();
13825
13826 intel_fbc_disable(dev);
13827
13828 ironlake_teardown_rc6(dev);
13829
13830 mutex_unlock(&dev->struct_mutex);
13831
13832 /* flush any delayed tasks or pending work */
13833 flush_scheduled_work();
13834
13835 /* destroy the backlight and sysfs files before encoders/connectors */
13836 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13837 struct intel_connector *intel_connector;
13838
13839 intel_connector = to_intel_connector(connector);
13840 intel_connector->unregister(intel_connector);
13841 }
13842
13843 drm_mode_config_cleanup(dev);
13844
13845 intel_cleanup_overlay(dev);
13846
13847 mutex_lock(&dev->struct_mutex);
13848 intel_cleanup_gt_powersave(dev);
13849 mutex_unlock(&dev->struct_mutex);
13850 }
13851
13852 /*
13853 * Return which encoder is currently attached for connector.
13854 */
13855 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13856 {
13857 return &intel_attached_encoder(connector)->base;
13858 }
13859
13860 void intel_connector_attach_encoder(struct intel_connector *connector,
13861 struct intel_encoder *encoder)
13862 {
13863 connector->encoder = encoder;
13864 drm_mode_connector_attach_encoder(&connector->base,
13865 &encoder->base);
13866 }
13867
13868 /*
13869 * set vga decode state - true == enable VGA decode
13870 */
13871 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13872 {
13873 struct drm_i915_private *dev_priv = dev->dev_private;
13874 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13875 u16 gmch_ctrl;
13876
13877 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13878 DRM_ERROR("failed to read control word\n");
13879 return -EIO;
13880 }
13881
13882 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13883 return 0;
13884
13885 if (state)
13886 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13887 else
13888 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13889
13890 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13891 DRM_ERROR("failed to write control word\n");
13892 return -EIO;
13893 }
13894
13895 return 0;
13896 }
13897
13898 struct intel_display_error_state {
13899
13900 u32 power_well_driver;
13901
13902 int num_transcoders;
13903
13904 struct intel_cursor_error_state {
13905 u32 control;
13906 u32 position;
13907 u32 base;
13908 u32 size;
13909 } cursor[I915_MAX_PIPES];
13910
13911 struct intel_pipe_error_state {
13912 bool power_domain_on;
13913 u32 source;
13914 u32 stat;
13915 } pipe[I915_MAX_PIPES];
13916
13917 struct intel_plane_error_state {
13918 u32 control;
13919 u32 stride;
13920 u32 size;
13921 u32 pos;
13922 u32 addr;
13923 u32 surface;
13924 u32 tile_offset;
13925 } plane[I915_MAX_PIPES];
13926
13927 struct intel_transcoder_error_state {
13928 bool power_domain_on;
13929 enum transcoder cpu_transcoder;
13930
13931 u32 conf;
13932
13933 u32 htotal;
13934 u32 hblank;
13935 u32 hsync;
13936 u32 vtotal;
13937 u32 vblank;
13938 u32 vsync;
13939 } transcoder[4];
13940 };
13941
13942 struct intel_display_error_state *
13943 intel_display_capture_error_state(struct drm_device *dev)
13944 {
13945 struct drm_i915_private *dev_priv = dev->dev_private;
13946 struct intel_display_error_state *error;
13947 int transcoders[] = {
13948 TRANSCODER_A,
13949 TRANSCODER_B,
13950 TRANSCODER_C,
13951 TRANSCODER_EDP,
13952 };
13953 int i;
13954
13955 if (INTEL_INFO(dev)->num_pipes == 0)
13956 return NULL;
13957
13958 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13959 if (error == NULL)
13960 return NULL;
13961
13962 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13963 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13964
13965 for_each_pipe(dev_priv, i) {
13966 error->pipe[i].power_domain_on =
13967 __intel_display_power_is_enabled(dev_priv,
13968 POWER_DOMAIN_PIPE(i));
13969 if (!error->pipe[i].power_domain_on)
13970 continue;
13971
13972 error->cursor[i].control = I915_READ(CURCNTR(i));
13973 error->cursor[i].position = I915_READ(CURPOS(i));
13974 error->cursor[i].base = I915_READ(CURBASE(i));
13975
13976 error->plane[i].control = I915_READ(DSPCNTR(i));
13977 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13978 if (INTEL_INFO(dev)->gen <= 3) {
13979 error->plane[i].size = I915_READ(DSPSIZE(i));
13980 error->plane[i].pos = I915_READ(DSPPOS(i));
13981 }
13982 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13983 error->plane[i].addr = I915_READ(DSPADDR(i));
13984 if (INTEL_INFO(dev)->gen >= 4) {
13985 error->plane[i].surface = I915_READ(DSPSURF(i));
13986 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13987 }
13988
13989 error->pipe[i].source = I915_READ(PIPESRC(i));
13990
13991 if (HAS_GMCH_DISPLAY(dev))
13992 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13993 }
13994
13995 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13996 if (HAS_DDI(dev_priv->dev))
13997 error->num_transcoders++; /* Account for eDP. */
13998
13999 for (i = 0; i < error->num_transcoders; i++) {
14000 enum transcoder cpu_transcoder = transcoders[i];
14001
14002 error->transcoder[i].power_domain_on =
14003 __intel_display_power_is_enabled(dev_priv,
14004 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14005 if (!error->transcoder[i].power_domain_on)
14006 continue;
14007
14008 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14009
14010 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14011 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14012 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14013 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14014 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14015 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14016 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14017 }
14018
14019 return error;
14020 }
14021
14022 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14023
14024 void
14025 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14026 struct drm_device *dev,
14027 struct intel_display_error_state *error)
14028 {
14029 struct drm_i915_private *dev_priv = dev->dev_private;
14030 int i;
14031
14032 if (!error)
14033 return;
14034
14035 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14036 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14037 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14038 error->power_well_driver);
14039 for_each_pipe(dev_priv, i) {
14040 err_printf(m, "Pipe [%d]:\n", i);
14041 err_printf(m, " Power: %s\n",
14042 error->pipe[i].power_domain_on ? "on" : "off");
14043 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14044 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14045
14046 err_printf(m, "Plane [%d]:\n", i);
14047 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14048 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14049 if (INTEL_INFO(dev)->gen <= 3) {
14050 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14051 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14052 }
14053 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14054 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14055 if (INTEL_INFO(dev)->gen >= 4) {
14056 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14057 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14058 }
14059
14060 err_printf(m, "Cursor [%d]:\n", i);
14061 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14062 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14063 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14064 }
14065
14066 for (i = 0; i < error->num_transcoders; i++) {
14067 err_printf(m, "CPU transcoder: %c\n",
14068 transcoder_name(error->transcoder[i].cpu_transcoder));
14069 err_printf(m, " Power: %s\n",
14070 error->transcoder[i].power_domain_on ? "on" : "off");
14071 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14072 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14073 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14074 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14075 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14076 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14077 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14078 }
14079 }
14080
14081 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14082 {
14083 struct intel_crtc *crtc;
14084
14085 for_each_intel_crtc(dev, crtc) {
14086 struct intel_unpin_work *work;
14087
14088 spin_lock_irq(&dev->event_lock);
14089
14090 work = crtc->unpin_work;
14091
14092 if (work && work->event &&
14093 work->event->base.file_priv == file) {
14094 kfree(work->event);
14095 work->event = NULL;
14096 }
14097
14098 spin_unlock_irq(&dev->event_lock);
14099 }
14100 }
Linux kernel - Deliverables
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