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drm/i915: factor out vlv_PLL_is_optimal
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb);
87 static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
99 static void vlv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void chv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105
106 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
107 {
108 if (!connector->mst_port)
109 return connector->encoder;
110 else
111 return &connector->mst_port->mst_encoders[pipe]->base;
112 }
113
114 typedef struct {
115 int min, max;
116 } intel_range_t;
117
118 typedef struct {
119 int dot_limit;
120 int p2_slow, p2_fast;
121 } intel_p2_t;
122
123 typedef struct intel_limit intel_limit_t;
124 struct intel_limit {
125 intel_range_t dot, vco, n, m, m1, m2, p, p1;
126 intel_p2_t p2;
127 };
128
129 int
130 intel_pch_rawclk(struct drm_device *dev)
131 {
132 struct drm_i915_private *dev_priv = dev->dev_private;
133
134 WARN_ON(!HAS_PCH_SPLIT(dev));
135
136 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
137 }
138
139 static inline u32 /* units of 100MHz */
140 intel_fdi_link_freq(struct drm_device *dev)
141 {
142 if (IS_GEN5(dev)) {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
145 } else
146 return 27;
147 }
148
149 static const intel_limit_t intel_limits_i8xx_dac = {
150 .dot = { .min = 25000, .max = 350000 },
151 .vco = { .min = 908000, .max = 1512000 },
152 .n = { .min = 2, .max = 16 },
153 .m = { .min = 96, .max = 140 },
154 .m1 = { .min = 18, .max = 26 },
155 .m2 = { .min = 6, .max = 16 },
156 .p = { .min = 4, .max = 128 },
157 .p1 = { .min = 2, .max = 33 },
158 .p2 = { .dot_limit = 165000,
159 .p2_slow = 4, .p2_fast = 2 },
160 };
161
162 static const intel_limit_t intel_limits_i8xx_dvo = {
163 .dot = { .min = 25000, .max = 350000 },
164 .vco = { .min = 908000, .max = 1512000 },
165 .n = { .min = 2, .max = 16 },
166 .m = { .min = 96, .max = 140 },
167 .m1 = { .min = 18, .max = 26 },
168 .m2 = { .min = 6, .max = 16 },
169 .p = { .min = 4, .max = 128 },
170 .p1 = { .min = 2, .max = 33 },
171 .p2 = { .dot_limit = 165000,
172 .p2_slow = 4, .p2_fast = 4 },
173 };
174
175 static const intel_limit_t intel_limits_i8xx_lvds = {
176 .dot = { .min = 25000, .max = 350000 },
177 .vco = { .min = 908000, .max = 1512000 },
178 .n = { .min = 2, .max = 16 },
179 .m = { .min = 96, .max = 140 },
180 .m1 = { .min = 18, .max = 26 },
181 .m2 = { .min = 6, .max = 16 },
182 .p = { .min = 4, .max = 128 },
183 .p1 = { .min = 1, .max = 6 },
184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 14, .p2_fast = 7 },
186 };
187
188 static const intel_limit_t intel_limits_i9xx_sdvo = {
189 .dot = { .min = 20000, .max = 400000 },
190 .vco = { .min = 1400000, .max = 2800000 },
191 .n = { .min = 1, .max = 6 },
192 .m = { .min = 70, .max = 120 },
193 .m1 = { .min = 8, .max = 18 },
194 .m2 = { .min = 3, .max = 7 },
195 .p = { .min = 5, .max = 80 },
196 .p1 = { .min = 1, .max = 8 },
197 .p2 = { .dot_limit = 200000,
198 .p2_slow = 10, .p2_fast = 5 },
199 };
200
201 static const intel_limit_t intel_limits_i9xx_lvds = {
202 .dot = { .min = 20000, .max = 400000 },
203 .vco = { .min = 1400000, .max = 2800000 },
204 .n = { .min = 1, .max = 6 },
205 .m = { .min = 70, .max = 120 },
206 .m1 = { .min = 8, .max = 18 },
207 .m2 = { .min = 3, .max = 7 },
208 .p = { .min = 7, .max = 98 },
209 .p1 = { .min = 1, .max = 8 },
210 .p2 = { .dot_limit = 112000,
211 .p2_slow = 14, .p2_fast = 7 },
212 };
213
214
215 static const intel_limit_t intel_limits_g4x_sdvo = {
216 .dot = { .min = 25000, .max = 270000 },
217 .vco = { .min = 1750000, .max = 3500000},
218 .n = { .min = 1, .max = 4 },
219 .m = { .min = 104, .max = 138 },
220 .m1 = { .min = 17, .max = 23 },
221 .m2 = { .min = 5, .max = 11 },
222 .p = { .min = 10, .max = 30 },
223 .p1 = { .min = 1, .max = 3},
224 .p2 = { .dot_limit = 270000,
225 .p2_slow = 10,
226 .p2_fast = 10
227 },
228 };
229
230 static const intel_limit_t intel_limits_g4x_hdmi = {
231 .dot = { .min = 22000, .max = 400000 },
232 .vco = { .min = 1750000, .max = 3500000},
233 .n = { .min = 1, .max = 4 },
234 .m = { .min = 104, .max = 138 },
235 .m1 = { .min = 16, .max = 23 },
236 .m2 = { .min = 5, .max = 11 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8},
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 10, .p2_fast = 5 },
241 };
242
243 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
244 .dot = { .min = 20000, .max = 115000 },
245 .vco = { .min = 1750000, .max = 3500000 },
246 .n = { .min = 1, .max = 3 },
247 .m = { .min = 104, .max = 138 },
248 .m1 = { .min = 17, .max = 23 },
249 .m2 = { .min = 5, .max = 11 },
250 .p = { .min = 28, .max = 112 },
251 .p1 = { .min = 2, .max = 8 },
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 14, .p2_fast = 14
254 },
255 };
256
257 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
258 .dot = { .min = 80000, .max = 224000 },
259 .vco = { .min = 1750000, .max = 3500000 },
260 .n = { .min = 1, .max = 3 },
261 .m = { .min = 104, .max = 138 },
262 .m1 = { .min = 17, .max = 23 },
263 .m2 = { .min = 5, .max = 11 },
264 .p = { .min = 14, .max = 42 },
265 .p1 = { .min = 2, .max = 6 },
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 7, .p2_fast = 7
268 },
269 };
270
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 };
285
286 static const intel_limit_t intel_limits_pineview_lvds = {
287 .dot = { .min = 20000, .max = 400000 },
288 .vco = { .min = 1700000, .max = 3500000 },
289 .n = { .min = 3, .max = 6 },
290 .m = { .min = 2, .max = 256 },
291 .m1 = { .min = 0, .max = 0 },
292 .m2 = { .min = 0, .max = 254 },
293 .p = { .min = 7, .max = 112 },
294 .p1 = { .min = 1, .max = 8 },
295 .p2 = { .dot_limit = 112000,
296 .p2_slow = 14, .p2_fast = 14 },
297 };
298
299 /* Ironlake / Sandybridge
300 *
301 * We calculate clock using (register_value + 2) for N/M1/M2, so here
302 * the range value for them is (actual_value - 2).
303 */
304 static const intel_limit_t intel_limits_ironlake_dac = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 5 },
308 .m = { .min = 79, .max = 127 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 5, .max = 80 },
312 .p1 = { .min = 1, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 10, .p2_fast = 5 },
315 };
316
317 static const intel_limit_t intel_limits_ironlake_single_lvds = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 3 },
321 .m = { .min = 79, .max = 118 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328 };
329
330 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 127 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 56 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
341 };
342
343 /* LVDS 100mhz refclk limits. */
344 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000 },
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 79, .max = 126 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 28, .max = 112 },
352 .p1 = { .min = 2, .max = 8 },
353 .p2 = { .dot_limit = 225000,
354 .p2_slow = 14, .p2_fast = 14 },
355 };
356
357 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
358 .dot = { .min = 25000, .max = 350000 },
359 .vco = { .min = 1760000, .max = 3510000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 79, .max = 126 },
362 .m1 = { .min = 12, .max = 22 },
363 .m2 = { .min = 5, .max = 9 },
364 .p = { .min = 14, .max = 42 },
365 .p1 = { .min = 2, .max = 6 },
366 .p2 = { .dot_limit = 225000,
367 .p2_slow = 7, .p2_fast = 7 },
368 };
369
370 static const intel_limit_t intel_limits_vlv = {
371 /*
372 * These are the data rate limits (measured in fast clocks)
373 * since those are the strictest limits we have. The fast
374 * clock and actual rate limits are more relaxed, so checking
375 * them would make no difference.
376 */
377 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
378 .vco = { .min = 4000000, .max = 6000000 },
379 .n = { .min = 1, .max = 7 },
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p1 = { .min = 2, .max = 3 },
383 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
384 };
385
386 static const intel_limit_t intel_limits_chv = {
387 /*
388 * These are the data rate limits (measured in fast clocks)
389 * since those are the strictest limits we have. The fast
390 * clock and actual rate limits are more relaxed, so checking
391 * them would make no difference.
392 */
393 .dot = { .min = 25000 * 5, .max = 540000 * 5},
394 .vco = { .min = 4800000, .max = 6480000 },
395 .n = { .min = 1, .max = 1 },
396 .m1 = { .min = 2, .max = 2 },
397 .m2 = { .min = 24 << 22, .max = 175 << 22 },
398 .p1 = { .min = 2, .max = 4 },
399 .p2 = { .p2_slow = 1, .p2_fast = 14 },
400 };
401
402 static void vlv_clock(int refclk, intel_clock_t *clock)
403 {
404 clock->m = clock->m1 * clock->m2;
405 clock->p = clock->p1 * clock->p2;
406 if (WARN_ON(clock->n == 0 || clock->p == 0))
407 return;
408 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
409 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
410 }
411
412 /**
413 * Returns whether any output on the specified pipe is of the specified type
414 */
415 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
416 {
417 struct drm_device *dev = crtc->base.dev;
418 struct intel_encoder *encoder;
419
420 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
421 if (encoder->type == type)
422 return true;
423
424 return false;
425 }
426
427 /**
428 * Returns whether any output on the specified pipe will have the specified
429 * type after a staged modeset is complete, i.e., the same as
430 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
431 * encoder->crtc.
432 */
433 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
434 {
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_intel_encoder(dev, encoder)
439 if (encoder->new_crtc == crtc && encoder->type == type)
440 return true;
441
442 return false;
443 }
444
445 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
446 int refclk)
447 {
448 struct drm_device *dev = crtc->base.dev;
449 const intel_limit_t *limit;
450
451 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
452 if (intel_is_dual_link_lvds(dev)) {
453 if (refclk == 100000)
454 limit = &intel_limits_ironlake_dual_lvds_100m;
455 else
456 limit = &intel_limits_ironlake_dual_lvds;
457 } else {
458 if (refclk == 100000)
459 limit = &intel_limits_ironlake_single_lvds_100m;
460 else
461 limit = &intel_limits_ironlake_single_lvds;
462 }
463 } else
464 limit = &intel_limits_ironlake_dac;
465
466 return limit;
467 }
468
469 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
470 {
471 struct drm_device *dev = crtc->base.dev;
472 const intel_limit_t *limit;
473
474 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
475 if (intel_is_dual_link_lvds(dev))
476 limit = &intel_limits_g4x_dual_channel_lvds;
477 else
478 limit = &intel_limits_g4x_single_channel_lvds;
479 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
480 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
481 limit = &intel_limits_g4x_hdmi;
482 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
483 limit = &intel_limits_g4x_sdvo;
484 } else /* The option is for other outputs */
485 limit = &intel_limits_i9xx_sdvo;
486
487 return limit;
488 }
489
490 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
491 {
492 struct drm_device *dev = crtc->base.dev;
493 const intel_limit_t *limit;
494
495 if (HAS_PCH_SPLIT(dev))
496 limit = intel_ironlake_limit(crtc, refclk);
497 else if (IS_G4X(dev)) {
498 limit = intel_g4x_limit(crtc);
499 } else if (IS_PINEVIEW(dev)) {
500 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
501 limit = &intel_limits_pineview_lvds;
502 else
503 limit = &intel_limits_pineview_sdvo;
504 } else if (IS_CHERRYVIEW(dev)) {
505 limit = &intel_limits_chv;
506 } else if (IS_VALLEYVIEW(dev)) {
507 limit = &intel_limits_vlv;
508 } else if (!IS_GEN2(dev)) {
509 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
510 limit = &intel_limits_i9xx_lvds;
511 else
512 limit = &intel_limits_i9xx_sdvo;
513 } else {
514 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i8xx_lvds;
516 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
517 limit = &intel_limits_i8xx_dvo;
518 else
519 limit = &intel_limits_i8xx_dac;
520 }
521 return limit;
522 }
523
524 /* m1 is reserved as 0 in Pineview, n is a ring counter */
525 static void pineview_clock(int refclk, intel_clock_t *clock)
526 {
527 clock->m = clock->m2 + 2;
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return;
531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533 }
534
535 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
536 {
537 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
538 }
539
540 static void i9xx_clock(int refclk, intel_clock_t *clock)
541 {
542 clock->m = i9xx_dpll_compute_m(clock);
543 clock->p = clock->p1 * clock->p2;
544 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
545 return;
546 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
547 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
548 }
549
550 static void chv_clock(int refclk, intel_clock_t *clock)
551 {
552 clock->m = clock->m1 * clock->m2;
553 clock->p = clock->p1 * clock->p2;
554 if (WARN_ON(clock->n == 0 || clock->p == 0))
555 return;
556 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
557 clock->n << 22);
558 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
559 }
560
561 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
562 /**
563 * Returns whether the given set of divisors are valid for a given refclk with
564 * the given connectors.
565 */
566
567 static bool intel_PLL_is_valid(struct drm_device *dev,
568 const intel_limit_t *limit,
569 const intel_clock_t *clock)
570 {
571 if (clock->n < limit->n.min || limit->n.max < clock->n)
572 INTELPllInvalid("n out of range\n");
573 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
574 INTELPllInvalid("p1 out of range\n");
575 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
576 INTELPllInvalid("m2 out of range\n");
577 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
578 INTELPllInvalid("m1 out of range\n");
579
580 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
581 if (clock->m1 <= clock->m2)
582 INTELPllInvalid("m1 <= m2\n");
583
584 if (!IS_VALLEYVIEW(dev)) {
585 if (clock->p < limit->p.min || limit->p.max < clock->p)
586 INTELPllInvalid("p out of range\n");
587 if (clock->m < limit->m.min || limit->m.max < clock->m)
588 INTELPllInvalid("m out of range\n");
589 }
590
591 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
592 INTELPllInvalid("vco out of range\n");
593 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
594 * connector, etc., rather than just a single range.
595 */
596 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
597 INTELPllInvalid("dot out of range\n");
598
599 return true;
600 }
601
602 static bool
603 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
606 {
607 struct drm_device *dev = crtc->base.dev;
608 intel_clock_t clock;
609 int err = target;
610
611 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
612 /*
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
616 */
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
640 int this_err;
641
642 i9xx_clock(refclk, &clock);
643 if (!intel_PLL_is_valid(dev, limit,
644 &clock))
645 continue;
646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661 }
662
663 static bool
664 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
667 {
668 struct drm_device *dev = crtc->base.dev;
669 intel_clock_t clock;
670 int err = target;
671
672 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
673 /*
674 * For LVDS just rely on its current settings for dual-channel.
675 * We haven't figured out how to reliably set up different
676 * single/dual channel state, if we even can.
677 */
678 if (intel_is_dual_link_lvds(dev))
679 clock.p2 = limit->p2.p2_fast;
680 else
681 clock.p2 = limit->p2.p2_slow;
682 } else {
683 if (target < limit->p2.dot_limit)
684 clock.p2 = limit->p2.p2_slow;
685 else
686 clock.p2 = limit->p2.p2_fast;
687 }
688
689 memset(best_clock, 0, sizeof(*best_clock));
690
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
699 int this_err;
700
701 pineview_clock(refclk, &clock);
702 if (!intel_PLL_is_valid(dev, limit,
703 &clock))
704 continue;
705 if (match_clock &&
706 clock.p != match_clock->p)
707 continue;
708
709 this_err = abs(clock.dot - target);
710 if (this_err < err) {
711 *best_clock = clock;
712 err = this_err;
713 }
714 }
715 }
716 }
717 }
718
719 return (err != target);
720 }
721
722 static bool
723 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
724 int target, int refclk, intel_clock_t *match_clock,
725 intel_clock_t *best_clock)
726 {
727 struct drm_device *dev = crtc->base.dev;
728 intel_clock_t clock;
729 int max_n;
730 bool found;
731 /* approximately equals target * 0.00585 */
732 int err_most = (target >> 8) + (target >> 9);
733 found = false;
734
735 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
736 if (intel_is_dual_link_lvds(dev))
737 clock.p2 = limit->p2.p2_fast;
738 else
739 clock.p2 = limit->p2.p2_slow;
740 } else {
741 if (target < limit->p2.dot_limit)
742 clock.p2 = limit->p2.p2_slow;
743 else
744 clock.p2 = limit->p2.p2_fast;
745 }
746
747 memset(best_clock, 0, sizeof(*best_clock));
748 max_n = limit->n.max;
749 /* based on hardware requirement, prefer smaller n to precision */
750 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
751 /* based on hardware requirement, prefere larger m1,m2 */
752 for (clock.m1 = limit->m1.max;
753 clock.m1 >= limit->m1.min; clock.m1--) {
754 for (clock.m2 = limit->m2.max;
755 clock.m2 >= limit->m2.min; clock.m2--) {
756 for (clock.p1 = limit->p1.max;
757 clock.p1 >= limit->p1.min; clock.p1--) {
758 int this_err;
759
760 i9xx_clock(refclk, &clock);
761 if (!intel_PLL_is_valid(dev, limit,
762 &clock))
763 continue;
764
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
776 return found;
777 }
778
779 /*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const intel_clock_t *calculated_clock,
785 const intel_clock_t *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788 {
789 *error_ppm = div_u64(1000000ULL *
790 abs(target_freq - calculated_clock->dot),
791 target_freq);
792 /*
793 * Prefer a better P value over a better (smaller) error if the error
794 * is small. Ensure this preference for future configurations too by
795 * setting the error to 0.
796 */
797 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
798 *error_ppm = 0;
799
800 return true;
801 }
802
803 return *error_ppm + 10 < best_error_ppm;
804 }
805
806 static bool
807 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
808 int target, int refclk, intel_clock_t *match_clock,
809 intel_clock_t *best_clock)
810 {
811 struct drm_device *dev = crtc->base.dev;
812 intel_clock_t clock;
813 unsigned int bestppm = 1000000;
814 /* min update 19.2 MHz */
815 int max_n = min(limit->n.max, refclk / 19200);
816 bool found = false;
817
818 target *= 5; /* fast clock */
819
820 memset(best_clock, 0, sizeof(*best_clock));
821
822 /* based on hardware requirement, prefer smaller n to precision */
823 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
824 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
825 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
826 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
827 clock.p = clock.p1 * clock.p2;
828 /* based on hardware requirement, prefer bigger m1,m2 values */
829 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
830 unsigned int ppm;
831
832 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
833 refclk * clock.m1);
834
835 vlv_clock(refclk, &clock);
836
837 if (!intel_PLL_is_valid(dev, limit,
838 &clock))
839 continue;
840
841 if (!vlv_PLL_is_optimal(dev, target,
842 &clock,
843 best_clock,
844 bestppm, &ppm))
845 continue;
846
847 *best_clock = clock;
848 bestppm = ppm;
849 found = true;
850 }
851 }
852 }
853 }
854
855 return found;
856 }
857
858 static bool
859 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
860 int target, int refclk, intel_clock_t *match_clock,
861 intel_clock_t *best_clock)
862 {
863 struct drm_device *dev = crtc->base.dev;
864 intel_clock_t clock;
865 uint64_t m2;
866 int found = false;
867
868 memset(best_clock, 0, sizeof(*best_clock));
869
870 /*
871 * Based on hardware doc, the n always set to 1, and m1 always
872 * set to 2. If requires to support 200Mhz refclk, we need to
873 * revisit this because n may not 1 anymore.
874 */
875 clock.n = 1, clock.m1 = 2;
876 target *= 5; /* fast clock */
877
878 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
879 for (clock.p2 = limit->p2.p2_fast;
880 clock.p2 >= limit->p2.p2_slow;
881 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
882
883 clock.p = clock.p1 * clock.p2;
884
885 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
886 clock.n) << 22, refclk * clock.m1);
887
888 if (m2 > INT_MAX/clock.m1)
889 continue;
890
891 clock.m2 = m2;
892
893 chv_clock(refclk, &clock);
894
895 if (!intel_PLL_is_valid(dev, limit, &clock))
896 continue;
897
898 /* based on hardware requirement, prefer bigger p
899 */
900 if (clock.p > best_clock->p) {
901 *best_clock = clock;
902 found = true;
903 }
904 }
905 }
906
907 return found;
908 }
909
910 bool intel_crtc_active(struct drm_crtc *crtc)
911 {
912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
913
914 /* Be paranoid as we can arrive here with only partial
915 * state retrieved from the hardware during setup.
916 *
917 * We can ditch the adjusted_mode.crtc_clock check as soon
918 * as Haswell has gained clock readout/fastboot support.
919 *
920 * We can ditch the crtc->primary->fb check as soon as we can
921 * properly reconstruct framebuffers.
922 *
923 * FIXME: The intel_crtc->active here should be switched to
924 * crtc->state->active once we have proper CRTC states wired up
925 * for atomic.
926 */
927 return intel_crtc->active && crtc->primary->state->fb &&
928 intel_crtc->config->base.adjusted_mode.crtc_clock;
929 }
930
931 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
932 enum pipe pipe)
933 {
934 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
936
937 return intel_crtc->config->cpu_transcoder;
938 }
939
940 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
941 {
942 struct drm_i915_private *dev_priv = dev->dev_private;
943 u32 reg = PIPEDSL(pipe);
944 u32 line1, line2;
945 u32 line_mask;
946
947 if (IS_GEN2(dev))
948 line_mask = DSL_LINEMASK_GEN2;
949 else
950 line_mask = DSL_LINEMASK_GEN3;
951
952 line1 = I915_READ(reg) & line_mask;
953 mdelay(5);
954 line2 = I915_READ(reg) & line_mask;
955
956 return line1 == line2;
957 }
958
959 /*
960 * intel_wait_for_pipe_off - wait for pipe to turn off
961 * @crtc: crtc whose pipe to wait for
962 *
963 * After disabling a pipe, we can't wait for vblank in the usual way,
964 * spinning on the vblank interrupt status bit, since we won't actually
965 * see an interrupt when the pipe is disabled.
966 *
967 * On Gen4 and above:
968 * wait for the pipe register state bit to turn off
969 *
970 * Otherwise:
971 * wait for the display line value to settle (it usually
972 * ends up stopping at the start of the next frame).
973 *
974 */
975 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
976 {
977 struct drm_device *dev = crtc->base.dev;
978 struct drm_i915_private *dev_priv = dev->dev_private;
979 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
980 enum pipe pipe = crtc->pipe;
981
982 if (INTEL_INFO(dev)->gen >= 4) {
983 int reg = PIPECONF(cpu_transcoder);
984
985 /* Wait for the Pipe State to go off */
986 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
987 100))
988 WARN(1, "pipe_off wait timed out\n");
989 } else {
990 /* Wait for the display line to settle */
991 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
992 WARN(1, "pipe_off wait timed out\n");
993 }
994 }
995
996 /*
997 * ibx_digital_port_connected - is the specified port connected?
998 * @dev_priv: i915 private structure
999 * @port: the port to test
1000 *
1001 * Returns true if @port is connected, false otherwise.
1002 */
1003 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1004 struct intel_digital_port *port)
1005 {
1006 u32 bit;
1007
1008 if (HAS_PCH_IBX(dev_priv->dev)) {
1009 switch (port->port) {
1010 case PORT_B:
1011 bit = SDE_PORTB_HOTPLUG;
1012 break;
1013 case PORT_C:
1014 bit = SDE_PORTC_HOTPLUG;
1015 break;
1016 case PORT_D:
1017 bit = SDE_PORTD_HOTPLUG;
1018 break;
1019 default:
1020 return true;
1021 }
1022 } else {
1023 switch (port->port) {
1024 case PORT_B:
1025 bit = SDE_PORTB_HOTPLUG_CPT;
1026 break;
1027 case PORT_C:
1028 bit = SDE_PORTC_HOTPLUG_CPT;
1029 break;
1030 case PORT_D:
1031 bit = SDE_PORTD_HOTPLUG_CPT;
1032 break;
1033 default:
1034 return true;
1035 }
1036 }
1037
1038 return I915_READ(SDEISR) & bit;
1039 }
1040
1041 static const char *state_string(bool enabled)
1042 {
1043 return enabled ? "on" : "off";
1044 }
1045
1046 /* Only for pre-ILK configs */
1047 void assert_pll(struct drm_i915_private *dev_priv,
1048 enum pipe pipe, bool state)
1049 {
1050 int reg;
1051 u32 val;
1052 bool cur_state;
1053
1054 reg = DPLL(pipe);
1055 val = I915_READ(reg);
1056 cur_state = !!(val & DPLL_VCO_ENABLE);
1057 I915_STATE_WARN(cur_state != state,
1058 "PLL state assertion failure (expected %s, current %s)\n",
1059 state_string(state), state_string(cur_state));
1060 }
1061
1062 /* XXX: the dsi pll is shared between MIPI DSI ports */
1063 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1064 {
1065 u32 val;
1066 bool cur_state;
1067
1068 mutex_lock(&dev_priv->dpio_lock);
1069 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1070 mutex_unlock(&dev_priv->dpio_lock);
1071
1072 cur_state = val & DSI_PLL_VCO_EN;
1073 I915_STATE_WARN(cur_state != state,
1074 "DSI PLL state assertion failure (expected %s, current %s)\n",
1075 state_string(state), state_string(cur_state));
1076 }
1077 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1078 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1079
1080 struct intel_shared_dpll *
1081 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1082 {
1083 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1084
1085 if (crtc->config->shared_dpll < 0)
1086 return NULL;
1087
1088 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1089 }
1090
1091 /* For ILK+ */
1092 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1093 struct intel_shared_dpll *pll,
1094 bool state)
1095 {
1096 bool cur_state;
1097 struct intel_dpll_hw_state hw_state;
1098
1099 if (WARN (!pll,
1100 "asserting DPLL %s with no DPLL\n", state_string(state)))
1101 return;
1102
1103 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1104 I915_STATE_WARN(cur_state != state,
1105 "%s assertion failure (expected %s, current %s)\n",
1106 pll->name, state_string(state), state_string(cur_state));
1107 }
1108
1109 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
1111 {
1112 int reg;
1113 u32 val;
1114 bool cur_state;
1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
1117
1118 if (HAS_DDI(dev_priv->dev)) {
1119 /* DDI does not have a specific FDI_TX register */
1120 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1121 val = I915_READ(reg);
1122 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1123 } else {
1124 reg = FDI_TX_CTL(pipe);
1125 val = I915_READ(reg);
1126 cur_state = !!(val & FDI_TX_ENABLE);
1127 }
1128 I915_STATE_WARN(cur_state != state,
1129 "FDI TX state assertion failure (expected %s, current %s)\n",
1130 state_string(state), state_string(cur_state));
1131 }
1132 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1133 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1134
1135 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1136 enum pipe pipe, bool state)
1137 {
1138 int reg;
1139 u32 val;
1140 bool cur_state;
1141
1142 reg = FDI_RX_CTL(pipe);
1143 val = I915_READ(reg);
1144 cur_state = !!(val & FDI_RX_ENABLE);
1145 I915_STATE_WARN(cur_state != state,
1146 "FDI RX state assertion failure (expected %s, current %s)\n",
1147 state_string(state), state_string(cur_state));
1148 }
1149 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1150 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1151
1152 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1153 enum pipe pipe)
1154 {
1155 int reg;
1156 u32 val;
1157
1158 /* ILK FDI PLL is always enabled */
1159 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1160 return;
1161
1162 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1163 if (HAS_DDI(dev_priv->dev))
1164 return;
1165
1166 reg = FDI_TX_CTL(pipe);
1167 val = I915_READ(reg);
1168 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1169 }
1170
1171 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1172 enum pipe pipe, bool state)
1173 {
1174 int reg;
1175 u32 val;
1176 bool cur_state;
1177
1178 reg = FDI_RX_CTL(pipe);
1179 val = I915_READ(reg);
1180 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1181 I915_STATE_WARN(cur_state != state,
1182 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1183 state_string(state), state_string(cur_state));
1184 }
1185
1186 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1187 enum pipe pipe)
1188 {
1189 struct drm_device *dev = dev_priv->dev;
1190 int pp_reg;
1191 u32 val;
1192 enum pipe panel_pipe = PIPE_A;
1193 bool locked = true;
1194
1195 if (WARN_ON(HAS_DDI(dev)))
1196 return;
1197
1198 if (HAS_PCH_SPLIT(dev)) {
1199 u32 port_sel;
1200
1201 pp_reg = PCH_PP_CONTROL;
1202 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1203
1204 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1205 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1206 panel_pipe = PIPE_B;
1207 /* XXX: else fix for eDP */
1208 } else if (IS_VALLEYVIEW(dev)) {
1209 /* presumably write lock depends on pipe, not port select */
1210 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1211 panel_pipe = pipe;
1212 } else {
1213 pp_reg = PP_CONTROL;
1214 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216 }
1217
1218 val = I915_READ(pp_reg);
1219 if (!(val & PANEL_POWER_ON) ||
1220 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1221 locked = false;
1222
1223 I915_STATE_WARN(panel_pipe == pipe && locked,
1224 "panel assertion failure, pipe %c regs locked\n",
1225 pipe_name(pipe));
1226 }
1227
1228 static void assert_cursor(struct drm_i915_private *dev_priv,
1229 enum pipe pipe, bool state)
1230 {
1231 struct drm_device *dev = dev_priv->dev;
1232 bool cur_state;
1233
1234 if (IS_845G(dev) || IS_I865G(dev))
1235 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1236 else
1237 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1238
1239 I915_STATE_WARN(cur_state != state,
1240 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1244 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1245
1246 void assert_pipe(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
1248 {
1249 int reg;
1250 u32 val;
1251 bool cur_state;
1252 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1253 pipe);
1254
1255 /* if we need the pipe quirk it must be always on */
1256 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1257 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1258 state = true;
1259
1260 if (!intel_display_power_is_enabled(dev_priv,
1261 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1262 cur_state = false;
1263 } else {
1264 reg = PIPECONF(cpu_transcoder);
1265 val = I915_READ(reg);
1266 cur_state = !!(val & PIPECONF_ENABLE);
1267 }
1268
1269 I915_STATE_WARN(cur_state != state,
1270 "pipe %c assertion failure (expected %s, current %s)\n",
1271 pipe_name(pipe), state_string(state), state_string(cur_state));
1272 }
1273
1274 static void assert_plane(struct drm_i915_private *dev_priv,
1275 enum plane plane, bool state)
1276 {
1277 int reg;
1278 u32 val;
1279 bool cur_state;
1280
1281 reg = DSPCNTR(plane);
1282 val = I915_READ(reg);
1283 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1284 I915_STATE_WARN(cur_state != state,
1285 "plane %c assertion failure (expected %s, current %s)\n",
1286 plane_name(plane), state_string(state), state_string(cur_state));
1287 }
1288
1289 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1290 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1291
1292 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1293 enum pipe pipe)
1294 {
1295 struct drm_device *dev = dev_priv->dev;
1296 int reg, i;
1297 u32 val;
1298 int cur_pipe;
1299
1300 /* Primary planes are fixed to pipes on gen4+ */
1301 if (INTEL_INFO(dev)->gen >= 4) {
1302 reg = DSPCNTR(pipe);
1303 val = I915_READ(reg);
1304 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1305 "plane %c assertion failure, should be disabled but not\n",
1306 plane_name(pipe));
1307 return;
1308 }
1309
1310 /* Need to check both planes against the pipe */
1311 for_each_pipe(dev_priv, i) {
1312 reg = DSPCNTR(i);
1313 val = I915_READ(reg);
1314 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1315 DISPPLANE_SEL_PIPE_SHIFT;
1316 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1317 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1318 plane_name(i), pipe_name(pipe));
1319 }
1320 }
1321
1322 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe)
1324 {
1325 struct drm_device *dev = dev_priv->dev;
1326 int reg, sprite;
1327 u32 val;
1328
1329 if (INTEL_INFO(dev)->gen >= 9) {
1330 for_each_sprite(dev_priv, pipe, sprite) {
1331 val = I915_READ(PLANE_CTL(pipe, sprite));
1332 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1333 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1334 sprite, pipe_name(pipe));
1335 }
1336 } else if (IS_VALLEYVIEW(dev)) {
1337 for_each_sprite(dev_priv, pipe, sprite) {
1338 reg = SPCNTR(pipe, sprite);
1339 val = I915_READ(reg);
1340 I915_STATE_WARN(val & SP_ENABLE,
1341 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1342 sprite_name(pipe, sprite), pipe_name(pipe));
1343 }
1344 } else if (INTEL_INFO(dev)->gen >= 7) {
1345 reg = SPRCTL(pipe);
1346 val = I915_READ(reg);
1347 I915_STATE_WARN(val & SPRITE_ENABLE,
1348 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349 plane_name(pipe), pipe_name(pipe));
1350 } else if (INTEL_INFO(dev)->gen >= 5) {
1351 reg = DVSCNTR(pipe);
1352 val = I915_READ(reg);
1353 I915_STATE_WARN(val & DVS_ENABLE,
1354 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1355 plane_name(pipe), pipe_name(pipe));
1356 }
1357 }
1358
1359 static void assert_vblank_disabled(struct drm_crtc *crtc)
1360 {
1361 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1362 drm_crtc_vblank_put(crtc);
1363 }
1364
1365 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1366 {
1367 u32 val;
1368 bool enabled;
1369
1370 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1371
1372 val = I915_READ(PCH_DREF_CONTROL);
1373 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1374 DREF_SUPERSPREAD_SOURCE_MASK));
1375 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1376 }
1377
1378 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1379 enum pipe pipe)
1380 {
1381 int reg;
1382 u32 val;
1383 bool enabled;
1384
1385 reg = PCH_TRANSCONF(pipe);
1386 val = I915_READ(reg);
1387 enabled = !!(val & TRANS_ENABLE);
1388 I915_STATE_WARN(enabled,
1389 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1390 pipe_name(pipe));
1391 }
1392
1393 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe, u32 port_sel, u32 val)
1395 {
1396 if ((val & DP_PORT_EN) == 0)
1397 return false;
1398
1399 if (HAS_PCH_CPT(dev_priv->dev)) {
1400 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1401 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1402 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1403 return false;
1404 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1405 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1406 return false;
1407 } else {
1408 if ((val & DP_PIPE_MASK) != (pipe << 30))
1409 return false;
1410 }
1411 return true;
1412 }
1413
1414 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1415 enum pipe pipe, u32 val)
1416 {
1417 if ((val & SDVO_ENABLE) == 0)
1418 return false;
1419
1420 if (HAS_PCH_CPT(dev_priv->dev)) {
1421 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1422 return false;
1423 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1424 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1425 return false;
1426 } else {
1427 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1428 return false;
1429 }
1430 return true;
1431 }
1432
1433 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1434 enum pipe pipe, u32 val)
1435 {
1436 if ((val & LVDS_PORT_EN) == 0)
1437 return false;
1438
1439 if (HAS_PCH_CPT(dev_priv->dev)) {
1440 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1441 return false;
1442 } else {
1443 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1444 return false;
1445 }
1446 return true;
1447 }
1448
1449 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe, u32 val)
1451 {
1452 if ((val & ADPA_DAC_ENABLE) == 0)
1453 return false;
1454 if (HAS_PCH_CPT(dev_priv->dev)) {
1455 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1456 return false;
1457 } else {
1458 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1459 return false;
1460 }
1461 return true;
1462 }
1463
1464 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe, int reg, u32 port_sel)
1466 {
1467 u32 val = I915_READ(reg);
1468 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1469 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1470 reg, pipe_name(pipe));
1471
1472 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1473 && (val & DP_PIPEB_SELECT),
1474 "IBX PCH dp port still using transcoder B\n");
1475 }
1476
1477 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1478 enum pipe pipe, int reg)
1479 {
1480 u32 val = I915_READ(reg);
1481 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1482 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1483 reg, pipe_name(pipe));
1484
1485 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1486 && (val & SDVO_PIPE_B_SELECT),
1487 "IBX PCH hdmi port still using transcoder B\n");
1488 }
1489
1490 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1491 enum pipe pipe)
1492 {
1493 int reg;
1494 u32 val;
1495
1496 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1497 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1498 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1499
1500 reg = PCH_ADPA;
1501 val = I915_READ(reg);
1502 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1503 "PCH VGA enabled on transcoder %c, should be disabled\n",
1504 pipe_name(pipe));
1505
1506 reg = PCH_LVDS;
1507 val = I915_READ(reg);
1508 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1509 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1510 pipe_name(pipe));
1511
1512 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1513 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1514 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1515 }
1516
1517 static void intel_init_dpio(struct drm_device *dev)
1518 {
1519 struct drm_i915_private *dev_priv = dev->dev_private;
1520
1521 if (!IS_VALLEYVIEW(dev))
1522 return;
1523
1524 /*
1525 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1526 * CHV x1 PHY (DP/HDMI D)
1527 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1528 */
1529 if (IS_CHERRYVIEW(dev)) {
1530 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1531 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1532 } else {
1533 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1534 }
1535 }
1536
1537 static void vlv_enable_pll(struct intel_crtc *crtc,
1538 const struct intel_crtc_state *pipe_config)
1539 {
1540 struct drm_device *dev = crtc->base.dev;
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 int reg = DPLL(crtc->pipe);
1543 u32 dpll = pipe_config->dpll_hw_state.dpll;
1544
1545 assert_pipe_disabled(dev_priv, crtc->pipe);
1546
1547 /* No really, not for ILK+ */
1548 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1549
1550 /* PLL is protected by panel, make sure we can write it */
1551 if (IS_MOBILE(dev_priv->dev))
1552 assert_panel_unlocked(dev_priv, crtc->pipe);
1553
1554 I915_WRITE(reg, dpll);
1555 POSTING_READ(reg);
1556 udelay(150);
1557
1558 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1559 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1560
1561 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1562 POSTING_READ(DPLL_MD(crtc->pipe));
1563
1564 /* We do this three times for luck */
1565 I915_WRITE(reg, dpll);
1566 POSTING_READ(reg);
1567 udelay(150); /* wait for warmup */
1568 I915_WRITE(reg, dpll);
1569 POSTING_READ(reg);
1570 udelay(150); /* wait for warmup */
1571 I915_WRITE(reg, dpll);
1572 POSTING_READ(reg);
1573 udelay(150); /* wait for warmup */
1574 }
1575
1576 static void chv_enable_pll(struct intel_crtc *crtc,
1577 const struct intel_crtc_state *pipe_config)
1578 {
1579 struct drm_device *dev = crtc->base.dev;
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581 int pipe = crtc->pipe;
1582 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1583 u32 tmp;
1584
1585 assert_pipe_disabled(dev_priv, crtc->pipe);
1586
1587 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1588
1589 mutex_lock(&dev_priv->dpio_lock);
1590
1591 /* Enable back the 10bit clock to display controller */
1592 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1593 tmp |= DPIO_DCLKP_EN;
1594 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1595
1596 /*
1597 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1598 */
1599 udelay(1);
1600
1601 /* Enable PLL */
1602 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1603
1604 /* Check PLL is locked */
1605 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1606 DRM_ERROR("PLL %d failed to lock\n", pipe);
1607
1608 /* not sure when this should be written */
1609 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1610 POSTING_READ(DPLL_MD(pipe));
1611
1612 mutex_unlock(&dev_priv->dpio_lock);
1613 }
1614
1615 static int intel_num_dvo_pipes(struct drm_device *dev)
1616 {
1617 struct intel_crtc *crtc;
1618 int count = 0;
1619
1620 for_each_intel_crtc(dev, crtc)
1621 count += crtc->active &&
1622 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1623
1624 return count;
1625 }
1626
1627 static void i9xx_enable_pll(struct intel_crtc *crtc)
1628 {
1629 struct drm_device *dev = crtc->base.dev;
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 int reg = DPLL(crtc->pipe);
1632 u32 dpll = crtc->config->dpll_hw_state.dpll;
1633
1634 assert_pipe_disabled(dev_priv, crtc->pipe);
1635
1636 /* No really, not for ILK+ */
1637 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1638
1639 /* PLL is protected by panel, make sure we can write it */
1640 if (IS_MOBILE(dev) && !IS_I830(dev))
1641 assert_panel_unlocked(dev_priv, crtc->pipe);
1642
1643 /* Enable DVO 2x clock on both PLLs if necessary */
1644 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1645 /*
1646 * It appears to be important that we don't enable this
1647 * for the current pipe before otherwise configuring the
1648 * PLL. No idea how this should be handled if multiple
1649 * DVO outputs are enabled simultaneosly.
1650 */
1651 dpll |= DPLL_DVO_2X_MODE;
1652 I915_WRITE(DPLL(!crtc->pipe),
1653 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1654 }
1655
1656 /* Wait for the clocks to stabilize. */
1657 POSTING_READ(reg);
1658 udelay(150);
1659
1660 if (INTEL_INFO(dev)->gen >= 4) {
1661 I915_WRITE(DPLL_MD(crtc->pipe),
1662 crtc->config->dpll_hw_state.dpll_md);
1663 } else {
1664 /* The pixel multiplier can only be updated once the
1665 * DPLL is enabled and the clocks are stable.
1666 *
1667 * So write it again.
1668 */
1669 I915_WRITE(reg, dpll);
1670 }
1671
1672 /* We do this three times for luck */
1673 I915_WRITE(reg, dpll);
1674 POSTING_READ(reg);
1675 udelay(150); /* wait for warmup */
1676 I915_WRITE(reg, dpll);
1677 POSTING_READ(reg);
1678 udelay(150); /* wait for warmup */
1679 I915_WRITE(reg, dpll);
1680 POSTING_READ(reg);
1681 udelay(150); /* wait for warmup */
1682 }
1683
1684 /**
1685 * i9xx_disable_pll - disable a PLL
1686 * @dev_priv: i915 private structure
1687 * @pipe: pipe PLL to disable
1688 *
1689 * Disable the PLL for @pipe, making sure the pipe is off first.
1690 *
1691 * Note! This is for pre-ILK only.
1692 */
1693 static void i9xx_disable_pll(struct intel_crtc *crtc)
1694 {
1695 struct drm_device *dev = crtc->base.dev;
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697 enum pipe pipe = crtc->pipe;
1698
1699 /* Disable DVO 2x clock on both PLLs if necessary */
1700 if (IS_I830(dev) &&
1701 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1702 intel_num_dvo_pipes(dev) == 1) {
1703 I915_WRITE(DPLL(PIPE_B),
1704 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1705 I915_WRITE(DPLL(PIPE_A),
1706 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1707 }
1708
1709 /* Don't disable pipe or pipe PLLs if needed */
1710 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1711 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1712 return;
1713
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv, pipe);
1716
1717 I915_WRITE(DPLL(pipe), 0);
1718 POSTING_READ(DPLL(pipe));
1719 }
1720
1721 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1722 {
1723 u32 val = 0;
1724
1725 /* Make sure the pipe isn't still relying on us */
1726 assert_pipe_disabled(dev_priv, pipe);
1727
1728 /*
1729 * Leave integrated clock source and reference clock enabled for pipe B.
1730 * The latter is needed for VGA hotplug / manual detection.
1731 */
1732 if (pipe == PIPE_B)
1733 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1734 I915_WRITE(DPLL(pipe), val);
1735 POSTING_READ(DPLL(pipe));
1736
1737 }
1738
1739 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1740 {
1741 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1742 u32 val;
1743
1744 /* Make sure the pipe isn't still relying on us */
1745 assert_pipe_disabled(dev_priv, pipe);
1746
1747 /* Set PLL en = 0 */
1748 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1749 if (pipe != PIPE_A)
1750 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1751 I915_WRITE(DPLL(pipe), val);
1752 POSTING_READ(DPLL(pipe));
1753
1754 mutex_lock(&dev_priv->dpio_lock);
1755
1756 /* Disable 10bit clock to display controller */
1757 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1758 val &= ~DPIO_DCLKP_EN;
1759 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1760
1761 /* disable left/right clock distribution */
1762 if (pipe != PIPE_B) {
1763 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1764 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1765 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1766 } else {
1767 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1768 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1769 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1770 }
1771
1772 mutex_unlock(&dev_priv->dpio_lock);
1773 }
1774
1775 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1776 struct intel_digital_port *dport)
1777 {
1778 u32 port_mask;
1779 int dpll_reg;
1780
1781 switch (dport->port) {
1782 case PORT_B:
1783 port_mask = DPLL_PORTB_READY_MASK;
1784 dpll_reg = DPLL(0);
1785 break;
1786 case PORT_C:
1787 port_mask = DPLL_PORTC_READY_MASK;
1788 dpll_reg = DPLL(0);
1789 break;
1790 case PORT_D:
1791 port_mask = DPLL_PORTD_READY_MASK;
1792 dpll_reg = DPIO_PHY_STATUS;
1793 break;
1794 default:
1795 BUG();
1796 }
1797
1798 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1799 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1800 port_name(dport->port), I915_READ(dpll_reg));
1801 }
1802
1803 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1804 {
1805 struct drm_device *dev = crtc->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809 if (WARN_ON(pll == NULL))
1810 return;
1811
1812 WARN_ON(!pll->config.crtc_mask);
1813 if (pll->active == 0) {
1814 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1815 WARN_ON(pll->on);
1816 assert_shared_dpll_disabled(dev_priv, pll);
1817
1818 pll->mode_set(dev_priv, pll);
1819 }
1820 }
1821
1822 /**
1823 * intel_enable_shared_dpll - enable PCH PLL
1824 * @dev_priv: i915 private structure
1825 * @pipe: pipe PLL to enable
1826 *
1827 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1828 * drives the transcoder clock.
1829 */
1830 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832 struct drm_device *dev = crtc->base.dev;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
1834 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836 if (WARN_ON(pll == NULL))
1837 return;
1838
1839 if (WARN_ON(pll->config.crtc_mask == 0))
1840 return;
1841
1842 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1843 pll->name, pll->active, pll->on,
1844 crtc->base.base.id);
1845
1846 if (pll->active++) {
1847 WARN_ON(!pll->on);
1848 assert_shared_dpll_enabled(dev_priv, pll);
1849 return;
1850 }
1851 WARN_ON(pll->on);
1852
1853 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1854
1855 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1856 pll->enable(dev_priv, pll);
1857 pll->on = true;
1858 }
1859
1860 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1861 {
1862 struct drm_device *dev = crtc->base.dev;
1863 struct drm_i915_private *dev_priv = dev->dev_private;
1864 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1865
1866 /* PCH only available on ILK+ */
1867 BUG_ON(INTEL_INFO(dev)->gen < 5);
1868 if (WARN_ON(pll == NULL))
1869 return;
1870
1871 if (WARN_ON(pll->config.crtc_mask == 0))
1872 return;
1873
1874 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1875 pll->name, pll->active, pll->on,
1876 crtc->base.base.id);
1877
1878 if (WARN_ON(pll->active == 0)) {
1879 assert_shared_dpll_disabled(dev_priv, pll);
1880 return;
1881 }
1882
1883 assert_shared_dpll_enabled(dev_priv, pll);
1884 WARN_ON(!pll->on);
1885 if (--pll->active)
1886 return;
1887
1888 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1889 pll->disable(dev_priv, pll);
1890 pll->on = false;
1891
1892 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1893 }
1894
1895 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1896 enum pipe pipe)
1897 {
1898 struct drm_device *dev = dev_priv->dev;
1899 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1901 uint32_t reg, val, pipeconf_val;
1902
1903 /* PCH only available on ILK+ */
1904 BUG_ON(!HAS_PCH_SPLIT(dev));
1905
1906 /* Make sure PCH DPLL is enabled */
1907 assert_shared_dpll_enabled(dev_priv,
1908 intel_crtc_to_shared_dpll(intel_crtc));
1909
1910 /* FDI must be feeding us bits for PCH ports */
1911 assert_fdi_tx_enabled(dev_priv, pipe);
1912 assert_fdi_rx_enabled(dev_priv, pipe);
1913
1914 if (HAS_PCH_CPT(dev)) {
1915 /* Workaround: Set the timing override bit before enabling the
1916 * pch transcoder. */
1917 reg = TRANS_CHICKEN2(pipe);
1918 val = I915_READ(reg);
1919 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1920 I915_WRITE(reg, val);
1921 }
1922
1923 reg = PCH_TRANSCONF(pipe);
1924 val = I915_READ(reg);
1925 pipeconf_val = I915_READ(PIPECONF(pipe));
1926
1927 if (HAS_PCH_IBX(dev_priv->dev)) {
1928 /*
1929 * make the BPC in transcoder be consistent with
1930 * that in pipeconf reg.
1931 */
1932 val &= ~PIPECONF_BPC_MASK;
1933 val |= pipeconf_val & PIPECONF_BPC_MASK;
1934 }
1935
1936 val &= ~TRANS_INTERLACE_MASK;
1937 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1938 if (HAS_PCH_IBX(dev_priv->dev) &&
1939 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1940 val |= TRANS_LEGACY_INTERLACED_ILK;
1941 else
1942 val |= TRANS_INTERLACED;
1943 else
1944 val |= TRANS_PROGRESSIVE;
1945
1946 I915_WRITE(reg, val | TRANS_ENABLE);
1947 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1948 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1949 }
1950
1951 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1952 enum transcoder cpu_transcoder)
1953 {
1954 u32 val, pipeconf_val;
1955
1956 /* PCH only available on ILK+ */
1957 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1958
1959 /* FDI must be feeding us bits for PCH ports */
1960 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1961 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1962
1963 /* Workaround: set timing override bit. */
1964 val = I915_READ(_TRANSA_CHICKEN2);
1965 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1966 I915_WRITE(_TRANSA_CHICKEN2, val);
1967
1968 val = TRANS_ENABLE;
1969 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1970
1971 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1972 PIPECONF_INTERLACED_ILK)
1973 val |= TRANS_INTERLACED;
1974 else
1975 val |= TRANS_PROGRESSIVE;
1976
1977 I915_WRITE(LPT_TRANSCONF, val);
1978 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1979 DRM_ERROR("Failed to enable PCH transcoder\n");
1980 }
1981
1982 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1983 enum pipe pipe)
1984 {
1985 struct drm_device *dev = dev_priv->dev;
1986 uint32_t reg, val;
1987
1988 /* FDI relies on the transcoder */
1989 assert_fdi_tx_disabled(dev_priv, pipe);
1990 assert_fdi_rx_disabled(dev_priv, pipe);
1991
1992 /* Ports must be off as well */
1993 assert_pch_ports_disabled(dev_priv, pipe);
1994
1995 reg = PCH_TRANSCONF(pipe);
1996 val = I915_READ(reg);
1997 val &= ~TRANS_ENABLE;
1998 I915_WRITE(reg, val);
1999 /* wait for PCH transcoder off, transcoder state */
2000 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2001 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2002
2003 if (!HAS_PCH_IBX(dev)) {
2004 /* Workaround: Clear the timing override chicken bit again. */
2005 reg = TRANS_CHICKEN2(pipe);
2006 val = I915_READ(reg);
2007 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2008 I915_WRITE(reg, val);
2009 }
2010 }
2011
2012 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2013 {
2014 u32 val;
2015
2016 val = I915_READ(LPT_TRANSCONF);
2017 val &= ~TRANS_ENABLE;
2018 I915_WRITE(LPT_TRANSCONF, val);
2019 /* wait for PCH transcoder off, transcoder state */
2020 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2021 DRM_ERROR("Failed to disable PCH transcoder\n");
2022
2023 /* Workaround: clear timing override bit. */
2024 val = I915_READ(_TRANSA_CHICKEN2);
2025 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2026 I915_WRITE(_TRANSA_CHICKEN2, val);
2027 }
2028
2029 /**
2030 * intel_enable_pipe - enable a pipe, asserting requirements
2031 * @crtc: crtc responsible for the pipe
2032 *
2033 * Enable @crtc's pipe, making sure that various hardware specific requirements
2034 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2035 */
2036 static void intel_enable_pipe(struct intel_crtc *crtc)
2037 {
2038 struct drm_device *dev = crtc->base.dev;
2039 struct drm_i915_private *dev_priv = dev->dev_private;
2040 enum pipe pipe = crtc->pipe;
2041 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2042 pipe);
2043 enum pipe pch_transcoder;
2044 int reg;
2045 u32 val;
2046
2047 assert_planes_disabled(dev_priv, pipe);
2048 assert_cursor_disabled(dev_priv, pipe);
2049 assert_sprites_disabled(dev_priv, pipe);
2050
2051 if (HAS_PCH_LPT(dev_priv->dev))
2052 pch_transcoder = TRANSCODER_A;
2053 else
2054 pch_transcoder = pipe;
2055
2056 /*
2057 * A pipe without a PLL won't actually be able to drive bits from
2058 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2059 * need the check.
2060 */
2061 if (!HAS_PCH_SPLIT(dev_priv->dev))
2062 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2063 assert_dsi_pll_enabled(dev_priv);
2064 else
2065 assert_pll_enabled(dev_priv, pipe);
2066 else {
2067 if (crtc->config->has_pch_encoder) {
2068 /* if driving the PCH, we need FDI enabled */
2069 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2070 assert_fdi_tx_pll_enabled(dev_priv,
2071 (enum pipe) cpu_transcoder);
2072 }
2073 /* FIXME: assert CPU port conditions for SNB+ */
2074 }
2075
2076 reg = PIPECONF(cpu_transcoder);
2077 val = I915_READ(reg);
2078 if (val & PIPECONF_ENABLE) {
2079 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2080 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2081 return;
2082 }
2083
2084 I915_WRITE(reg, val | PIPECONF_ENABLE);
2085 POSTING_READ(reg);
2086 }
2087
2088 /**
2089 * intel_disable_pipe - disable a pipe, asserting requirements
2090 * @crtc: crtc whose pipes is to be disabled
2091 *
2092 * Disable the pipe of @crtc, making sure that various hardware
2093 * specific requirements are met, if applicable, e.g. plane
2094 * disabled, panel fitter off, etc.
2095 *
2096 * Will wait until the pipe has shut down before returning.
2097 */
2098 static void intel_disable_pipe(struct intel_crtc *crtc)
2099 {
2100 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2101 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2102 enum pipe pipe = crtc->pipe;
2103 int reg;
2104 u32 val;
2105
2106 /*
2107 * Make sure planes won't keep trying to pump pixels to us,
2108 * or we might hang the display.
2109 */
2110 assert_planes_disabled(dev_priv, pipe);
2111 assert_cursor_disabled(dev_priv, pipe);
2112 assert_sprites_disabled(dev_priv, pipe);
2113
2114 reg = PIPECONF(cpu_transcoder);
2115 val = I915_READ(reg);
2116 if ((val & PIPECONF_ENABLE) == 0)
2117 return;
2118
2119 /*
2120 * Double wide has implications for planes
2121 * so best keep it disabled when not needed.
2122 */
2123 if (crtc->config->double_wide)
2124 val &= ~PIPECONF_DOUBLE_WIDE;
2125
2126 /* Don't disable pipe or pipe PLLs if needed */
2127 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2128 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2129 val &= ~PIPECONF_ENABLE;
2130
2131 I915_WRITE(reg, val);
2132 if ((val & PIPECONF_ENABLE) == 0)
2133 intel_wait_for_pipe_off(crtc);
2134 }
2135
2136 /*
2137 * Plane regs are double buffered, going from enabled->disabled needs a
2138 * trigger in order to latch. The display address reg provides this.
2139 */
2140 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2141 enum plane plane)
2142 {
2143 struct drm_device *dev = dev_priv->dev;
2144 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2145
2146 I915_WRITE(reg, I915_READ(reg));
2147 POSTING_READ(reg);
2148 }
2149
2150 /**
2151 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2152 * @plane: plane to be enabled
2153 * @crtc: crtc for the plane
2154 *
2155 * Enable @plane on @crtc, making sure that the pipe is running first.
2156 */
2157 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2158 struct drm_crtc *crtc)
2159 {
2160 struct drm_device *dev = plane->dev;
2161 struct drm_i915_private *dev_priv = dev->dev_private;
2162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2163
2164 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2165 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2166
2167 if (intel_crtc->primary_enabled)
2168 return;
2169
2170 intel_crtc->primary_enabled = true;
2171
2172 dev_priv->display.update_primary_plane(crtc, plane->fb,
2173 crtc->x, crtc->y);
2174
2175 /*
2176 * BDW signals flip done immediately if the plane
2177 * is disabled, even if the plane enable is already
2178 * armed to occur at the next vblank :(
2179 */
2180 if (IS_BROADWELL(dev))
2181 intel_wait_for_vblank(dev, intel_crtc->pipe);
2182 }
2183
2184 /**
2185 * intel_disable_primary_hw_plane - disable the primary hardware plane
2186 * @plane: plane to be disabled
2187 * @crtc: crtc for the plane
2188 *
2189 * Disable @plane on @crtc, making sure that the pipe is running first.
2190 */
2191 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2192 struct drm_crtc *crtc)
2193 {
2194 struct drm_device *dev = plane->dev;
2195 struct drm_i915_private *dev_priv = dev->dev_private;
2196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2197
2198 if (WARN_ON(!intel_crtc->active))
2199 return;
2200
2201 if (!intel_crtc->primary_enabled)
2202 return;
2203
2204 intel_crtc->primary_enabled = false;
2205
2206 dev_priv->display.update_primary_plane(crtc, plane->fb,
2207 crtc->x, crtc->y);
2208 }
2209
2210 static bool need_vtd_wa(struct drm_device *dev)
2211 {
2212 #ifdef CONFIG_INTEL_IOMMU
2213 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2214 return true;
2215 #endif
2216 return false;
2217 }
2218
2219 int
2220 intel_fb_align_height(struct drm_device *dev, int height,
2221 uint32_t pixel_format,
2222 uint64_t fb_format_modifier)
2223 {
2224 int tile_height;
2225 uint32_t bits_per_pixel;
2226
2227 switch (fb_format_modifier) {
2228 case DRM_FORMAT_MOD_NONE:
2229 tile_height = 1;
2230 break;
2231 case I915_FORMAT_MOD_X_TILED:
2232 tile_height = IS_GEN2(dev) ? 16 : 8;
2233 break;
2234 case I915_FORMAT_MOD_Y_TILED:
2235 tile_height = 32;
2236 break;
2237 case I915_FORMAT_MOD_Yf_TILED:
2238 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2239 switch (bits_per_pixel) {
2240 default:
2241 case 8:
2242 tile_height = 64;
2243 break;
2244 case 16:
2245 case 32:
2246 tile_height = 32;
2247 break;
2248 case 64:
2249 tile_height = 16;
2250 break;
2251 case 128:
2252 WARN_ONCE(1,
2253 "128-bit pixels are not supported for display!");
2254 tile_height = 16;
2255 break;
2256 }
2257 break;
2258 default:
2259 MISSING_CASE(fb_format_modifier);
2260 tile_height = 1;
2261 break;
2262 }
2263
2264 return ALIGN(height, tile_height);
2265 }
2266
2267 int
2268 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2269 struct drm_framebuffer *fb,
2270 struct intel_engine_cs *pipelined)
2271 {
2272 struct drm_device *dev = fb->dev;
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2275 u32 alignment;
2276 int ret;
2277
2278 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2279
2280 switch (fb->modifier[0]) {
2281 case DRM_FORMAT_MOD_NONE:
2282 if (INTEL_INFO(dev)->gen >= 9)
2283 alignment = 256 * 1024;
2284 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2285 alignment = 128 * 1024;
2286 else if (INTEL_INFO(dev)->gen >= 4)
2287 alignment = 4 * 1024;
2288 else
2289 alignment = 64 * 1024;
2290 break;
2291 case I915_FORMAT_MOD_X_TILED:
2292 if (INTEL_INFO(dev)->gen >= 9)
2293 alignment = 256 * 1024;
2294 else {
2295 /* pin() will align the object as required by fence */
2296 alignment = 0;
2297 }
2298 break;
2299 case I915_FORMAT_MOD_Y_TILED:
2300 case I915_FORMAT_MOD_Yf_TILED:
2301 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2302 "Y tiling bo slipped through, driver bug!\n"))
2303 return -EINVAL;
2304 alignment = 1 * 1024 * 1024;
2305 break;
2306 default:
2307 MISSING_CASE(fb->modifier[0]);
2308 return -EINVAL;
2309 }
2310
2311 /* Note that the w/a also requires 64 PTE of padding following the
2312 * bo. We currently fill all unused PTE with the shadow page and so
2313 * we should always have valid PTE following the scanout preventing
2314 * the VT-d warning.
2315 */
2316 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2317 alignment = 256 * 1024;
2318
2319 /*
2320 * Global gtt pte registers are special registers which actually forward
2321 * writes to a chunk of system memory. Which means that there is no risk
2322 * that the register values disappear as soon as we call
2323 * intel_runtime_pm_put(), so it is correct to wrap only the
2324 * pin/unpin/fence and not more.
2325 */
2326 intel_runtime_pm_get(dev_priv);
2327
2328 dev_priv->mm.interruptible = false;
2329 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2330 if (ret)
2331 goto err_interruptible;
2332
2333 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2334 * fence, whereas 965+ only requires a fence if using
2335 * framebuffer compression. For simplicity, we always install
2336 * a fence as the cost is not that onerous.
2337 */
2338 ret = i915_gem_object_get_fence(obj);
2339 if (ret)
2340 goto err_unpin;
2341
2342 i915_gem_object_pin_fence(obj);
2343
2344 dev_priv->mm.interruptible = true;
2345 intel_runtime_pm_put(dev_priv);
2346 return 0;
2347
2348 err_unpin:
2349 i915_gem_object_unpin_from_display_plane(obj);
2350 err_interruptible:
2351 dev_priv->mm.interruptible = true;
2352 intel_runtime_pm_put(dev_priv);
2353 return ret;
2354 }
2355
2356 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2357 {
2358 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2359
2360 i915_gem_object_unpin_fence(obj);
2361 i915_gem_object_unpin_from_display_plane(obj);
2362 }
2363
2364 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2365 * is assumed to be a power-of-two. */
2366 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2367 unsigned int tiling_mode,
2368 unsigned int cpp,
2369 unsigned int pitch)
2370 {
2371 if (tiling_mode != I915_TILING_NONE) {
2372 unsigned int tile_rows, tiles;
2373
2374 tile_rows = *y / 8;
2375 *y %= 8;
2376
2377 tiles = *x / (512/cpp);
2378 *x %= 512/cpp;
2379
2380 return tile_rows * pitch * 8 + tiles * 4096;
2381 } else {
2382 unsigned int offset;
2383
2384 offset = *y * pitch + *x * cpp;
2385 *y = 0;
2386 *x = (offset & 4095) / cpp;
2387 return offset & -4096;
2388 }
2389 }
2390
2391 static int i9xx_format_to_fourcc(int format)
2392 {
2393 switch (format) {
2394 case DISPPLANE_8BPP:
2395 return DRM_FORMAT_C8;
2396 case DISPPLANE_BGRX555:
2397 return DRM_FORMAT_XRGB1555;
2398 case DISPPLANE_BGRX565:
2399 return DRM_FORMAT_RGB565;
2400 default:
2401 case DISPPLANE_BGRX888:
2402 return DRM_FORMAT_XRGB8888;
2403 case DISPPLANE_RGBX888:
2404 return DRM_FORMAT_XBGR8888;
2405 case DISPPLANE_BGRX101010:
2406 return DRM_FORMAT_XRGB2101010;
2407 case DISPPLANE_RGBX101010:
2408 return DRM_FORMAT_XBGR2101010;
2409 }
2410 }
2411
2412 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2413 {
2414 switch (format) {
2415 case PLANE_CTL_FORMAT_RGB_565:
2416 return DRM_FORMAT_RGB565;
2417 default:
2418 case PLANE_CTL_FORMAT_XRGB_8888:
2419 if (rgb_order) {
2420 if (alpha)
2421 return DRM_FORMAT_ABGR8888;
2422 else
2423 return DRM_FORMAT_XBGR8888;
2424 } else {
2425 if (alpha)
2426 return DRM_FORMAT_ARGB8888;
2427 else
2428 return DRM_FORMAT_XRGB8888;
2429 }
2430 case PLANE_CTL_FORMAT_XRGB_2101010:
2431 if (rgb_order)
2432 return DRM_FORMAT_XBGR2101010;
2433 else
2434 return DRM_FORMAT_XRGB2101010;
2435 }
2436 }
2437
2438 static bool
2439 intel_alloc_plane_obj(struct intel_crtc *crtc,
2440 struct intel_initial_plane_config *plane_config)
2441 {
2442 struct drm_device *dev = crtc->base.dev;
2443 struct drm_i915_gem_object *obj = NULL;
2444 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2445 struct drm_framebuffer *fb = &plane_config->fb->base;
2446 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2447 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2448 PAGE_SIZE);
2449
2450 size_aligned -= base_aligned;
2451
2452 if (plane_config->size == 0)
2453 return false;
2454
2455 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2456 base_aligned,
2457 base_aligned,
2458 size_aligned);
2459 if (!obj)
2460 return false;
2461
2462 obj->tiling_mode = plane_config->tiling;
2463 if (obj->tiling_mode == I915_TILING_X)
2464 obj->stride = fb->pitches[0];
2465
2466 mode_cmd.pixel_format = fb->pixel_format;
2467 mode_cmd.width = fb->width;
2468 mode_cmd.height = fb->height;
2469 mode_cmd.pitches[0] = fb->pitches[0];
2470 mode_cmd.modifier[0] = fb->modifier[0];
2471 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2472
2473 mutex_lock(&dev->struct_mutex);
2474
2475 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2476 &mode_cmd, obj)) {
2477 DRM_DEBUG_KMS("intel fb init failed\n");
2478 goto out_unref_obj;
2479 }
2480
2481 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2482 mutex_unlock(&dev->struct_mutex);
2483
2484 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2485 return true;
2486
2487 out_unref_obj:
2488 drm_gem_object_unreference(&obj->base);
2489 mutex_unlock(&dev->struct_mutex);
2490 return false;
2491 }
2492
2493 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2494 static void
2495 update_state_fb(struct drm_plane *plane)
2496 {
2497 if (plane->fb == plane->state->fb)
2498 return;
2499
2500 if (plane->state->fb)
2501 drm_framebuffer_unreference(plane->state->fb);
2502 plane->state->fb = plane->fb;
2503 if (plane->state->fb)
2504 drm_framebuffer_reference(plane->state->fb);
2505 }
2506
2507 static void
2508 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2509 struct intel_initial_plane_config *plane_config)
2510 {
2511 struct drm_device *dev = intel_crtc->base.dev;
2512 struct drm_i915_private *dev_priv = dev->dev_private;
2513 struct drm_crtc *c;
2514 struct intel_crtc *i;
2515 struct drm_i915_gem_object *obj;
2516
2517 if (!plane_config->fb)
2518 return;
2519
2520 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2521 struct drm_plane *primary = intel_crtc->base.primary;
2522
2523 primary->fb = &plane_config->fb->base;
2524 primary->state->crtc = &intel_crtc->base;
2525 update_state_fb(primary);
2526
2527 return;
2528 }
2529
2530 kfree(plane_config->fb);
2531
2532 /*
2533 * Failed to alloc the obj, check to see if we should share
2534 * an fb with another CRTC instead
2535 */
2536 for_each_crtc(dev, c) {
2537 i = to_intel_crtc(c);
2538
2539 if (c == &intel_crtc->base)
2540 continue;
2541
2542 if (!i->active)
2543 continue;
2544
2545 obj = intel_fb_obj(c->primary->fb);
2546 if (obj == NULL)
2547 continue;
2548
2549 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2550 struct drm_plane *primary = intel_crtc->base.primary;
2551
2552 if (obj->tiling_mode != I915_TILING_NONE)
2553 dev_priv->preserve_bios_swizzle = true;
2554
2555 drm_framebuffer_reference(c->primary->fb);
2556 primary->fb = c->primary->fb;
2557 primary->state->crtc = &intel_crtc->base;
2558 update_state_fb(intel_crtc->base.primary);
2559 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2560 break;
2561 }
2562 }
2563 }
2564
2565 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2566 struct drm_framebuffer *fb,
2567 int x, int y)
2568 {
2569 struct drm_device *dev = crtc->dev;
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2572 struct drm_i915_gem_object *obj;
2573 int plane = intel_crtc->plane;
2574 unsigned long linear_offset;
2575 u32 dspcntr;
2576 u32 reg = DSPCNTR(plane);
2577 int pixel_size;
2578
2579 if (!intel_crtc->primary_enabled) {
2580 I915_WRITE(reg, 0);
2581 if (INTEL_INFO(dev)->gen >= 4)
2582 I915_WRITE(DSPSURF(plane), 0);
2583 else
2584 I915_WRITE(DSPADDR(plane), 0);
2585 POSTING_READ(reg);
2586 return;
2587 }
2588
2589 obj = intel_fb_obj(fb);
2590 if (WARN_ON(obj == NULL))
2591 return;
2592
2593 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2594
2595 dspcntr = DISPPLANE_GAMMA_ENABLE;
2596
2597 dspcntr |= DISPLAY_PLANE_ENABLE;
2598
2599 if (INTEL_INFO(dev)->gen < 4) {
2600 if (intel_crtc->pipe == PIPE_B)
2601 dspcntr |= DISPPLANE_SEL_PIPE_B;
2602
2603 /* pipesrc and dspsize control the size that is scaled from,
2604 * which should always be the user's requested size.
2605 */
2606 I915_WRITE(DSPSIZE(plane),
2607 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2608 (intel_crtc->config->pipe_src_w - 1));
2609 I915_WRITE(DSPPOS(plane), 0);
2610 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2611 I915_WRITE(PRIMSIZE(plane),
2612 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2613 (intel_crtc->config->pipe_src_w - 1));
2614 I915_WRITE(PRIMPOS(plane), 0);
2615 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2616 }
2617
2618 switch (fb->pixel_format) {
2619 case DRM_FORMAT_C8:
2620 dspcntr |= DISPPLANE_8BPP;
2621 break;
2622 case DRM_FORMAT_XRGB1555:
2623 case DRM_FORMAT_ARGB1555:
2624 dspcntr |= DISPPLANE_BGRX555;
2625 break;
2626 case DRM_FORMAT_RGB565:
2627 dspcntr |= DISPPLANE_BGRX565;
2628 break;
2629 case DRM_FORMAT_XRGB8888:
2630 case DRM_FORMAT_ARGB8888:
2631 dspcntr |= DISPPLANE_BGRX888;
2632 break;
2633 case DRM_FORMAT_XBGR8888:
2634 case DRM_FORMAT_ABGR8888:
2635 dspcntr |= DISPPLANE_RGBX888;
2636 break;
2637 case DRM_FORMAT_XRGB2101010:
2638 case DRM_FORMAT_ARGB2101010:
2639 dspcntr |= DISPPLANE_BGRX101010;
2640 break;
2641 case DRM_FORMAT_XBGR2101010:
2642 case DRM_FORMAT_ABGR2101010:
2643 dspcntr |= DISPPLANE_RGBX101010;
2644 break;
2645 default:
2646 BUG();
2647 }
2648
2649 if (INTEL_INFO(dev)->gen >= 4 &&
2650 obj->tiling_mode != I915_TILING_NONE)
2651 dspcntr |= DISPPLANE_TILED;
2652
2653 if (IS_G4X(dev))
2654 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2655
2656 linear_offset = y * fb->pitches[0] + x * pixel_size;
2657
2658 if (INTEL_INFO(dev)->gen >= 4) {
2659 intel_crtc->dspaddr_offset =
2660 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2661 pixel_size,
2662 fb->pitches[0]);
2663 linear_offset -= intel_crtc->dspaddr_offset;
2664 } else {
2665 intel_crtc->dspaddr_offset = linear_offset;
2666 }
2667
2668 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2669 dspcntr |= DISPPLANE_ROTATE_180;
2670
2671 x += (intel_crtc->config->pipe_src_w - 1);
2672 y += (intel_crtc->config->pipe_src_h - 1);
2673
2674 /* Finding the last pixel of the last line of the display
2675 data and adding to linear_offset*/
2676 linear_offset +=
2677 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2678 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2679 }
2680
2681 I915_WRITE(reg, dspcntr);
2682
2683 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2684 if (INTEL_INFO(dev)->gen >= 4) {
2685 I915_WRITE(DSPSURF(plane),
2686 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2687 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2688 I915_WRITE(DSPLINOFF(plane), linear_offset);
2689 } else
2690 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2691 POSTING_READ(reg);
2692 }
2693
2694 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2695 struct drm_framebuffer *fb,
2696 int x, int y)
2697 {
2698 struct drm_device *dev = crtc->dev;
2699 struct drm_i915_private *dev_priv = dev->dev_private;
2700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2701 struct drm_i915_gem_object *obj;
2702 int plane = intel_crtc->plane;
2703 unsigned long linear_offset;
2704 u32 dspcntr;
2705 u32 reg = DSPCNTR(plane);
2706 int pixel_size;
2707
2708 if (!intel_crtc->primary_enabled) {
2709 I915_WRITE(reg, 0);
2710 I915_WRITE(DSPSURF(plane), 0);
2711 POSTING_READ(reg);
2712 return;
2713 }
2714
2715 obj = intel_fb_obj(fb);
2716 if (WARN_ON(obj == NULL))
2717 return;
2718
2719 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2720
2721 dspcntr = DISPPLANE_GAMMA_ENABLE;
2722
2723 dspcntr |= DISPLAY_PLANE_ENABLE;
2724
2725 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2726 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2727
2728 switch (fb->pixel_format) {
2729 case DRM_FORMAT_C8:
2730 dspcntr |= DISPPLANE_8BPP;
2731 break;
2732 case DRM_FORMAT_RGB565:
2733 dspcntr |= DISPPLANE_BGRX565;
2734 break;
2735 case DRM_FORMAT_XRGB8888:
2736 case DRM_FORMAT_ARGB8888:
2737 dspcntr |= DISPPLANE_BGRX888;
2738 break;
2739 case DRM_FORMAT_XBGR8888:
2740 case DRM_FORMAT_ABGR8888:
2741 dspcntr |= DISPPLANE_RGBX888;
2742 break;
2743 case DRM_FORMAT_XRGB2101010:
2744 case DRM_FORMAT_ARGB2101010:
2745 dspcntr |= DISPPLANE_BGRX101010;
2746 break;
2747 case DRM_FORMAT_XBGR2101010:
2748 case DRM_FORMAT_ABGR2101010:
2749 dspcntr |= DISPPLANE_RGBX101010;
2750 break;
2751 default:
2752 BUG();
2753 }
2754
2755 if (obj->tiling_mode != I915_TILING_NONE)
2756 dspcntr |= DISPPLANE_TILED;
2757
2758 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2759 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2760
2761 linear_offset = y * fb->pitches[0] + x * pixel_size;
2762 intel_crtc->dspaddr_offset =
2763 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2764 pixel_size,
2765 fb->pitches[0]);
2766 linear_offset -= intel_crtc->dspaddr_offset;
2767 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2768 dspcntr |= DISPPLANE_ROTATE_180;
2769
2770 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2771 x += (intel_crtc->config->pipe_src_w - 1);
2772 y += (intel_crtc->config->pipe_src_h - 1);
2773
2774 /* Finding the last pixel of the last line of the display
2775 data and adding to linear_offset*/
2776 linear_offset +=
2777 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2778 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2779 }
2780 }
2781
2782 I915_WRITE(reg, dspcntr);
2783
2784 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2785 I915_WRITE(DSPSURF(plane),
2786 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2787 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2788 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2789 } else {
2790 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2791 I915_WRITE(DSPLINOFF(plane), linear_offset);
2792 }
2793 POSTING_READ(reg);
2794 }
2795
2796 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2797 uint32_t pixel_format)
2798 {
2799 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2800
2801 /*
2802 * The stride is either expressed as a multiple of 64 bytes
2803 * chunks for linear buffers or in number of tiles for tiled
2804 * buffers.
2805 */
2806 switch (fb_modifier) {
2807 case DRM_FORMAT_MOD_NONE:
2808 return 64;
2809 case I915_FORMAT_MOD_X_TILED:
2810 if (INTEL_INFO(dev)->gen == 2)
2811 return 128;
2812 return 512;
2813 case I915_FORMAT_MOD_Y_TILED:
2814 /* No need to check for old gens and Y tiling since this is
2815 * about the display engine and those will be blocked before
2816 * we get here.
2817 */
2818 return 128;
2819 case I915_FORMAT_MOD_Yf_TILED:
2820 if (bits_per_pixel == 8)
2821 return 64;
2822 else
2823 return 128;
2824 default:
2825 MISSING_CASE(fb_modifier);
2826 return 64;
2827 }
2828 }
2829
2830 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2831 struct drm_framebuffer *fb,
2832 int x, int y)
2833 {
2834 struct drm_device *dev = crtc->dev;
2835 struct drm_i915_private *dev_priv = dev->dev_private;
2836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2837 struct drm_i915_gem_object *obj;
2838 int pipe = intel_crtc->pipe;
2839 u32 plane_ctl, stride_div;
2840
2841 if (!intel_crtc->primary_enabled) {
2842 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2843 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2844 POSTING_READ(PLANE_CTL(pipe, 0));
2845 return;
2846 }
2847
2848 plane_ctl = PLANE_CTL_ENABLE |
2849 PLANE_CTL_PIPE_GAMMA_ENABLE |
2850 PLANE_CTL_PIPE_CSC_ENABLE;
2851
2852 switch (fb->pixel_format) {
2853 case DRM_FORMAT_RGB565:
2854 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2855 break;
2856 case DRM_FORMAT_XRGB8888:
2857 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2858 break;
2859 case DRM_FORMAT_ARGB8888:
2860 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2861 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2862 break;
2863 case DRM_FORMAT_XBGR8888:
2864 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2865 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2866 break;
2867 case DRM_FORMAT_ABGR8888:
2868 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2869 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2870 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2871 break;
2872 case DRM_FORMAT_XRGB2101010:
2873 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2874 break;
2875 case DRM_FORMAT_XBGR2101010:
2876 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2877 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2878 break;
2879 default:
2880 BUG();
2881 }
2882
2883 switch (fb->modifier[0]) {
2884 case DRM_FORMAT_MOD_NONE:
2885 break;
2886 case I915_FORMAT_MOD_X_TILED:
2887 plane_ctl |= PLANE_CTL_TILED_X;
2888 break;
2889 case I915_FORMAT_MOD_Y_TILED:
2890 plane_ctl |= PLANE_CTL_TILED_Y;
2891 break;
2892 case I915_FORMAT_MOD_Yf_TILED:
2893 plane_ctl |= PLANE_CTL_TILED_YF;
2894 break;
2895 default:
2896 MISSING_CASE(fb->modifier[0]);
2897 }
2898
2899 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2900 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2901 plane_ctl |= PLANE_CTL_ROTATE_180;
2902
2903 obj = intel_fb_obj(fb);
2904 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2905 fb->pixel_format);
2906
2907 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2908
2909 I915_WRITE(PLANE_POS(pipe, 0), 0);
2910 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2911 I915_WRITE(PLANE_SIZE(pipe, 0),
2912 (intel_crtc->config->pipe_src_h - 1) << 16 |
2913 (intel_crtc->config->pipe_src_w - 1));
2914 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2915 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2916
2917 POSTING_READ(PLANE_SURF(pipe, 0));
2918 }
2919
2920 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2921 static int
2922 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2923 int x, int y, enum mode_set_atomic state)
2924 {
2925 struct drm_device *dev = crtc->dev;
2926 struct drm_i915_private *dev_priv = dev->dev_private;
2927
2928 if (dev_priv->display.disable_fbc)
2929 dev_priv->display.disable_fbc(dev);
2930
2931 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2932
2933 return 0;
2934 }
2935
2936 static void intel_complete_page_flips(struct drm_device *dev)
2937 {
2938 struct drm_crtc *crtc;
2939
2940 for_each_crtc(dev, crtc) {
2941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2942 enum plane plane = intel_crtc->plane;
2943
2944 intel_prepare_page_flip(dev, plane);
2945 intel_finish_page_flip_plane(dev, plane);
2946 }
2947 }
2948
2949 static void intel_update_primary_planes(struct drm_device *dev)
2950 {
2951 struct drm_i915_private *dev_priv = dev->dev_private;
2952 struct drm_crtc *crtc;
2953
2954 for_each_crtc(dev, crtc) {
2955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2956
2957 drm_modeset_lock(&crtc->mutex, NULL);
2958 /*
2959 * FIXME: Once we have proper support for primary planes (and
2960 * disabling them without disabling the entire crtc) allow again
2961 * a NULL crtc->primary->fb.
2962 */
2963 if (intel_crtc->active && crtc->primary->fb)
2964 dev_priv->display.update_primary_plane(crtc,
2965 crtc->primary->fb,
2966 crtc->x,
2967 crtc->y);
2968 drm_modeset_unlock(&crtc->mutex);
2969 }
2970 }
2971
2972 void intel_prepare_reset(struct drm_device *dev)
2973 {
2974 struct drm_i915_private *dev_priv = to_i915(dev);
2975 struct intel_crtc *crtc;
2976
2977 /* no reset support for gen2 */
2978 if (IS_GEN2(dev))
2979 return;
2980
2981 /* reset doesn't touch the display */
2982 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2983 return;
2984
2985 drm_modeset_lock_all(dev);
2986
2987 /*
2988 * Disabling the crtcs gracefully seems nicer. Also the
2989 * g33 docs say we should at least disable all the planes.
2990 */
2991 for_each_intel_crtc(dev, crtc) {
2992 if (crtc->active)
2993 dev_priv->display.crtc_disable(&crtc->base);
2994 }
2995 }
2996
2997 void intel_finish_reset(struct drm_device *dev)
2998 {
2999 struct drm_i915_private *dev_priv = to_i915(dev);
3000
3001 /*
3002 * Flips in the rings will be nuked by the reset,
3003 * so complete all pending flips so that user space
3004 * will get its events and not get stuck.
3005 */
3006 intel_complete_page_flips(dev);
3007
3008 /* no reset support for gen2 */
3009 if (IS_GEN2(dev))
3010 return;
3011
3012 /* reset doesn't touch the display */
3013 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3014 /*
3015 * Flips in the rings have been nuked by the reset,
3016 * so update the base address of all primary
3017 * planes to the the last fb to make sure we're
3018 * showing the correct fb after a reset.
3019 */
3020 intel_update_primary_planes(dev);
3021 return;
3022 }
3023
3024 /*
3025 * The display has been reset as well,
3026 * so need a full re-initialization.
3027 */
3028 intel_runtime_pm_disable_interrupts(dev_priv);
3029 intel_runtime_pm_enable_interrupts(dev_priv);
3030
3031 intel_modeset_init_hw(dev);
3032
3033 spin_lock_irq(&dev_priv->irq_lock);
3034 if (dev_priv->display.hpd_irq_setup)
3035 dev_priv->display.hpd_irq_setup(dev);
3036 spin_unlock_irq(&dev_priv->irq_lock);
3037
3038 intel_modeset_setup_hw_state(dev, true);
3039
3040 intel_hpd_init(dev_priv);
3041
3042 drm_modeset_unlock_all(dev);
3043 }
3044
3045 static int
3046 intel_finish_fb(struct drm_framebuffer *old_fb)
3047 {
3048 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3049 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3050 bool was_interruptible = dev_priv->mm.interruptible;
3051 int ret;
3052
3053 /* Big Hammer, we also need to ensure that any pending
3054 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3055 * current scanout is retired before unpinning the old
3056 * framebuffer.
3057 *
3058 * This should only fail upon a hung GPU, in which case we
3059 * can safely continue.
3060 */
3061 dev_priv->mm.interruptible = false;
3062 ret = i915_gem_object_finish_gpu(obj);
3063 dev_priv->mm.interruptible = was_interruptible;
3064
3065 return ret;
3066 }
3067
3068 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3069 {
3070 struct drm_device *dev = crtc->dev;
3071 struct drm_i915_private *dev_priv = dev->dev_private;
3072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3073 bool pending;
3074
3075 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3076 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3077 return false;
3078
3079 spin_lock_irq(&dev->event_lock);
3080 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3081 spin_unlock_irq(&dev->event_lock);
3082
3083 return pending;
3084 }
3085
3086 static void intel_update_pipe_size(struct intel_crtc *crtc)
3087 {
3088 struct drm_device *dev = crtc->base.dev;
3089 struct drm_i915_private *dev_priv = dev->dev_private;
3090 const struct drm_display_mode *adjusted_mode;
3091
3092 if (!i915.fastboot)
3093 return;
3094
3095 /*
3096 * Update pipe size and adjust fitter if needed: the reason for this is
3097 * that in compute_mode_changes we check the native mode (not the pfit
3098 * mode) to see if we can flip rather than do a full mode set. In the
3099 * fastboot case, we'll flip, but if we don't update the pipesrc and
3100 * pfit state, we'll end up with a big fb scanned out into the wrong
3101 * sized surface.
3102 *
3103 * To fix this properly, we need to hoist the checks up into
3104 * compute_mode_changes (or above), check the actual pfit state and
3105 * whether the platform allows pfit disable with pipe active, and only
3106 * then update the pipesrc and pfit state, even on the flip path.
3107 */
3108
3109 adjusted_mode = &crtc->config->base.adjusted_mode;
3110
3111 I915_WRITE(PIPESRC(crtc->pipe),
3112 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3113 (adjusted_mode->crtc_vdisplay - 1));
3114 if (!crtc->config->pch_pfit.enabled &&
3115 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3116 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3117 I915_WRITE(PF_CTL(crtc->pipe), 0);
3118 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3119 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3120 }
3121 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3122 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3123 }
3124
3125 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3126 {
3127 struct drm_device *dev = crtc->dev;
3128 struct drm_i915_private *dev_priv = dev->dev_private;
3129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3130 int pipe = intel_crtc->pipe;
3131 u32 reg, temp;
3132
3133 /* enable normal train */
3134 reg = FDI_TX_CTL(pipe);
3135 temp = I915_READ(reg);
3136 if (IS_IVYBRIDGE(dev)) {
3137 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3138 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3139 } else {
3140 temp &= ~FDI_LINK_TRAIN_NONE;
3141 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3142 }
3143 I915_WRITE(reg, temp);
3144
3145 reg = FDI_RX_CTL(pipe);
3146 temp = I915_READ(reg);
3147 if (HAS_PCH_CPT(dev)) {
3148 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3149 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3150 } else {
3151 temp &= ~FDI_LINK_TRAIN_NONE;
3152 temp |= FDI_LINK_TRAIN_NONE;
3153 }
3154 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3155
3156 /* wait one idle pattern time */
3157 POSTING_READ(reg);
3158 udelay(1000);
3159
3160 /* IVB wants error correction enabled */
3161 if (IS_IVYBRIDGE(dev))
3162 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3163 FDI_FE_ERRC_ENABLE);
3164 }
3165
3166 /* The FDI link training functions for ILK/Ibexpeak. */
3167 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3168 {
3169 struct drm_device *dev = crtc->dev;
3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3172 int pipe = intel_crtc->pipe;
3173 u32 reg, temp, tries;
3174
3175 /* FDI needs bits from pipe first */
3176 assert_pipe_enabled(dev_priv, pipe);
3177
3178 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3179 for train result */
3180 reg = FDI_RX_IMR(pipe);
3181 temp = I915_READ(reg);
3182 temp &= ~FDI_RX_SYMBOL_LOCK;
3183 temp &= ~FDI_RX_BIT_LOCK;
3184 I915_WRITE(reg, temp);
3185 I915_READ(reg);
3186 udelay(150);
3187
3188 /* enable CPU FDI TX and PCH FDI RX */
3189 reg = FDI_TX_CTL(pipe);
3190 temp = I915_READ(reg);
3191 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3192 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3193 temp &= ~FDI_LINK_TRAIN_NONE;
3194 temp |= FDI_LINK_TRAIN_PATTERN_1;
3195 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3196
3197 reg = FDI_RX_CTL(pipe);
3198 temp = I915_READ(reg);
3199 temp &= ~FDI_LINK_TRAIN_NONE;
3200 temp |= FDI_LINK_TRAIN_PATTERN_1;
3201 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3202
3203 POSTING_READ(reg);
3204 udelay(150);
3205
3206 /* Ironlake workaround, enable clock pointer after FDI enable*/
3207 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3208 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3209 FDI_RX_PHASE_SYNC_POINTER_EN);
3210
3211 reg = FDI_RX_IIR(pipe);
3212 for (tries = 0; tries < 5; tries++) {
3213 temp = I915_READ(reg);
3214 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3215
3216 if ((temp & FDI_RX_BIT_LOCK)) {
3217 DRM_DEBUG_KMS("FDI train 1 done.\n");
3218 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3219 break;
3220 }
3221 }
3222 if (tries == 5)
3223 DRM_ERROR("FDI train 1 fail!\n");
3224
3225 /* Train 2 */
3226 reg = FDI_TX_CTL(pipe);
3227 temp = I915_READ(reg);
3228 temp &= ~FDI_LINK_TRAIN_NONE;
3229 temp |= FDI_LINK_TRAIN_PATTERN_2;
3230 I915_WRITE(reg, temp);
3231
3232 reg = FDI_RX_CTL(pipe);
3233 temp = I915_READ(reg);
3234 temp &= ~FDI_LINK_TRAIN_NONE;
3235 temp |= FDI_LINK_TRAIN_PATTERN_2;
3236 I915_WRITE(reg, temp);
3237
3238 POSTING_READ(reg);
3239 udelay(150);
3240
3241 reg = FDI_RX_IIR(pipe);
3242 for (tries = 0; tries < 5; tries++) {
3243 temp = I915_READ(reg);
3244 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3245
3246 if (temp & FDI_RX_SYMBOL_LOCK) {
3247 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3248 DRM_DEBUG_KMS("FDI train 2 done.\n");
3249 break;
3250 }
3251 }
3252 if (tries == 5)
3253 DRM_ERROR("FDI train 2 fail!\n");
3254
3255 DRM_DEBUG_KMS("FDI train done\n");
3256
3257 }
3258
3259 static const int snb_b_fdi_train_param[] = {
3260 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3261 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3262 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3263 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3264 };
3265
3266 /* The FDI link training functions for SNB/Cougarpoint. */
3267 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3268 {
3269 struct drm_device *dev = crtc->dev;
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3272 int pipe = intel_crtc->pipe;
3273 u32 reg, temp, i, retry;
3274
3275 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3276 for train result */
3277 reg = FDI_RX_IMR(pipe);
3278 temp = I915_READ(reg);
3279 temp &= ~FDI_RX_SYMBOL_LOCK;
3280 temp &= ~FDI_RX_BIT_LOCK;
3281 I915_WRITE(reg, temp);
3282
3283 POSTING_READ(reg);
3284 udelay(150);
3285
3286 /* enable CPU FDI TX and PCH FDI RX */
3287 reg = FDI_TX_CTL(pipe);
3288 temp = I915_READ(reg);
3289 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3290 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3291 temp &= ~FDI_LINK_TRAIN_NONE;
3292 temp |= FDI_LINK_TRAIN_PATTERN_1;
3293 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3294 /* SNB-B */
3295 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3296 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3297
3298 I915_WRITE(FDI_RX_MISC(pipe),
3299 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3300
3301 reg = FDI_RX_CTL(pipe);
3302 temp = I915_READ(reg);
3303 if (HAS_PCH_CPT(dev)) {
3304 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3305 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3306 } else {
3307 temp &= ~FDI_LINK_TRAIN_NONE;
3308 temp |= FDI_LINK_TRAIN_PATTERN_1;
3309 }
3310 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3311
3312 POSTING_READ(reg);
3313 udelay(150);
3314
3315 for (i = 0; i < 4; i++) {
3316 reg = FDI_TX_CTL(pipe);
3317 temp = I915_READ(reg);
3318 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3319 temp |= snb_b_fdi_train_param[i];
3320 I915_WRITE(reg, temp);
3321
3322 POSTING_READ(reg);
3323 udelay(500);
3324
3325 for (retry = 0; retry < 5; retry++) {
3326 reg = FDI_RX_IIR(pipe);
3327 temp = I915_READ(reg);
3328 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3329 if (temp & FDI_RX_BIT_LOCK) {
3330 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3331 DRM_DEBUG_KMS("FDI train 1 done.\n");
3332 break;
3333 }
3334 udelay(50);
3335 }
3336 if (retry < 5)
3337 break;
3338 }
3339 if (i == 4)
3340 DRM_ERROR("FDI train 1 fail!\n");
3341
3342 /* Train 2 */
3343 reg = FDI_TX_CTL(pipe);
3344 temp = I915_READ(reg);
3345 temp &= ~FDI_LINK_TRAIN_NONE;
3346 temp |= FDI_LINK_TRAIN_PATTERN_2;
3347 if (IS_GEN6(dev)) {
3348 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3349 /* SNB-B */
3350 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3351 }
3352 I915_WRITE(reg, temp);
3353
3354 reg = FDI_RX_CTL(pipe);
3355 temp = I915_READ(reg);
3356 if (HAS_PCH_CPT(dev)) {
3357 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3358 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3359 } else {
3360 temp &= ~FDI_LINK_TRAIN_NONE;
3361 temp |= FDI_LINK_TRAIN_PATTERN_2;
3362 }
3363 I915_WRITE(reg, temp);
3364
3365 POSTING_READ(reg);
3366 udelay(150);
3367
3368 for (i = 0; i < 4; i++) {
3369 reg = FDI_TX_CTL(pipe);
3370 temp = I915_READ(reg);
3371 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3372 temp |= snb_b_fdi_train_param[i];
3373 I915_WRITE(reg, temp);
3374
3375 POSTING_READ(reg);
3376 udelay(500);
3377
3378 for (retry = 0; retry < 5; retry++) {
3379 reg = FDI_RX_IIR(pipe);
3380 temp = I915_READ(reg);
3381 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3382 if (temp & FDI_RX_SYMBOL_LOCK) {
3383 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3384 DRM_DEBUG_KMS("FDI train 2 done.\n");
3385 break;
3386 }
3387 udelay(50);
3388 }
3389 if (retry < 5)
3390 break;
3391 }
3392 if (i == 4)
3393 DRM_ERROR("FDI train 2 fail!\n");
3394
3395 DRM_DEBUG_KMS("FDI train done.\n");
3396 }
3397
3398 /* Manual link training for Ivy Bridge A0 parts */
3399 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3400 {
3401 struct drm_device *dev = crtc->dev;
3402 struct drm_i915_private *dev_priv = dev->dev_private;
3403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3404 int pipe = intel_crtc->pipe;
3405 u32 reg, temp, i, j;
3406
3407 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3408 for train result */
3409 reg = FDI_RX_IMR(pipe);
3410 temp = I915_READ(reg);
3411 temp &= ~FDI_RX_SYMBOL_LOCK;
3412 temp &= ~FDI_RX_BIT_LOCK;
3413 I915_WRITE(reg, temp);
3414
3415 POSTING_READ(reg);
3416 udelay(150);
3417
3418 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3419 I915_READ(FDI_RX_IIR(pipe)));
3420
3421 /* Try each vswing and preemphasis setting twice before moving on */
3422 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3423 /* disable first in case we need to retry */
3424 reg = FDI_TX_CTL(pipe);
3425 temp = I915_READ(reg);
3426 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3427 temp &= ~FDI_TX_ENABLE;
3428 I915_WRITE(reg, temp);
3429
3430 reg = FDI_RX_CTL(pipe);
3431 temp = I915_READ(reg);
3432 temp &= ~FDI_LINK_TRAIN_AUTO;
3433 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3434 temp &= ~FDI_RX_ENABLE;
3435 I915_WRITE(reg, temp);
3436
3437 /* enable CPU FDI TX and PCH FDI RX */
3438 reg = FDI_TX_CTL(pipe);
3439 temp = I915_READ(reg);
3440 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3441 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3442 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3443 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3444 temp |= snb_b_fdi_train_param[j/2];
3445 temp |= FDI_COMPOSITE_SYNC;
3446 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3447
3448 I915_WRITE(FDI_RX_MISC(pipe),
3449 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3450
3451 reg = FDI_RX_CTL(pipe);
3452 temp = I915_READ(reg);
3453 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3454 temp |= FDI_COMPOSITE_SYNC;
3455 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3456
3457 POSTING_READ(reg);
3458 udelay(1); /* should be 0.5us */
3459
3460 for (i = 0; i < 4; i++) {
3461 reg = FDI_RX_IIR(pipe);
3462 temp = I915_READ(reg);
3463 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3464
3465 if (temp & FDI_RX_BIT_LOCK ||
3466 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3467 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3468 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3469 i);
3470 break;
3471 }
3472 udelay(1); /* should be 0.5us */
3473 }
3474 if (i == 4) {
3475 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3476 continue;
3477 }
3478
3479 /* Train 2 */
3480 reg = FDI_TX_CTL(pipe);
3481 temp = I915_READ(reg);
3482 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3483 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3484 I915_WRITE(reg, temp);
3485
3486 reg = FDI_RX_CTL(pipe);
3487 temp = I915_READ(reg);
3488 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3489 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3490 I915_WRITE(reg, temp);
3491
3492 POSTING_READ(reg);
3493 udelay(2); /* should be 1.5us */
3494
3495 for (i = 0; i < 4; i++) {
3496 reg = FDI_RX_IIR(pipe);
3497 temp = I915_READ(reg);
3498 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3499
3500 if (temp & FDI_RX_SYMBOL_LOCK ||
3501 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3502 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3503 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3504 i);
3505 goto train_done;
3506 }
3507 udelay(2); /* should be 1.5us */
3508 }
3509 if (i == 4)
3510 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3511 }
3512
3513 train_done:
3514 DRM_DEBUG_KMS("FDI train done.\n");
3515 }
3516
3517 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3518 {
3519 struct drm_device *dev = intel_crtc->base.dev;
3520 struct drm_i915_private *dev_priv = dev->dev_private;
3521 int pipe = intel_crtc->pipe;
3522 u32 reg, temp;
3523
3524
3525 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3526 reg = FDI_RX_CTL(pipe);
3527 temp = I915_READ(reg);
3528 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3530 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3531 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3532
3533 POSTING_READ(reg);
3534 udelay(200);
3535
3536 /* Switch from Rawclk to PCDclk */
3537 temp = I915_READ(reg);
3538 I915_WRITE(reg, temp | FDI_PCDCLK);
3539
3540 POSTING_READ(reg);
3541 udelay(200);
3542
3543 /* Enable CPU FDI TX PLL, always on for Ironlake */
3544 reg = FDI_TX_CTL(pipe);
3545 temp = I915_READ(reg);
3546 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3547 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3548
3549 POSTING_READ(reg);
3550 udelay(100);
3551 }
3552 }
3553
3554 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3555 {
3556 struct drm_device *dev = intel_crtc->base.dev;
3557 struct drm_i915_private *dev_priv = dev->dev_private;
3558 int pipe = intel_crtc->pipe;
3559 u32 reg, temp;
3560
3561 /* Switch from PCDclk to Rawclk */
3562 reg = FDI_RX_CTL(pipe);
3563 temp = I915_READ(reg);
3564 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3565
3566 /* Disable CPU FDI TX PLL */
3567 reg = FDI_TX_CTL(pipe);
3568 temp = I915_READ(reg);
3569 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3570
3571 POSTING_READ(reg);
3572 udelay(100);
3573
3574 reg = FDI_RX_CTL(pipe);
3575 temp = I915_READ(reg);
3576 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3577
3578 /* Wait for the clocks to turn off. */
3579 POSTING_READ(reg);
3580 udelay(100);
3581 }
3582
3583 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3584 {
3585 struct drm_device *dev = crtc->dev;
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3588 int pipe = intel_crtc->pipe;
3589 u32 reg, temp;
3590
3591 /* disable CPU FDI tx and PCH FDI rx */
3592 reg = FDI_TX_CTL(pipe);
3593 temp = I915_READ(reg);
3594 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3595 POSTING_READ(reg);
3596
3597 reg = FDI_RX_CTL(pipe);
3598 temp = I915_READ(reg);
3599 temp &= ~(0x7 << 16);
3600 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3601 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3602
3603 POSTING_READ(reg);
3604 udelay(100);
3605
3606 /* Ironlake workaround, disable clock pointer after downing FDI */
3607 if (HAS_PCH_IBX(dev))
3608 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3609
3610 /* still set train pattern 1 */
3611 reg = FDI_TX_CTL(pipe);
3612 temp = I915_READ(reg);
3613 temp &= ~FDI_LINK_TRAIN_NONE;
3614 temp |= FDI_LINK_TRAIN_PATTERN_1;
3615 I915_WRITE(reg, temp);
3616
3617 reg = FDI_RX_CTL(pipe);
3618 temp = I915_READ(reg);
3619 if (HAS_PCH_CPT(dev)) {
3620 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3621 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3622 } else {
3623 temp &= ~FDI_LINK_TRAIN_NONE;
3624 temp |= FDI_LINK_TRAIN_PATTERN_1;
3625 }
3626 /* BPC in FDI rx is consistent with that in PIPECONF */
3627 temp &= ~(0x07 << 16);
3628 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3629 I915_WRITE(reg, temp);
3630
3631 POSTING_READ(reg);
3632 udelay(100);
3633 }
3634
3635 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3636 {
3637 struct intel_crtc *crtc;
3638
3639 /* Note that we don't need to be called with mode_config.lock here
3640 * as our list of CRTC objects is static for the lifetime of the
3641 * device and so cannot disappear as we iterate. Similarly, we can
3642 * happily treat the predicates as racy, atomic checks as userspace
3643 * cannot claim and pin a new fb without at least acquring the
3644 * struct_mutex and so serialising with us.
3645 */
3646 for_each_intel_crtc(dev, crtc) {
3647 if (atomic_read(&crtc->unpin_work_count) == 0)
3648 continue;
3649
3650 if (crtc->unpin_work)
3651 intel_wait_for_vblank(dev, crtc->pipe);
3652
3653 return true;
3654 }
3655
3656 return false;
3657 }
3658
3659 static void page_flip_completed(struct intel_crtc *intel_crtc)
3660 {
3661 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3662 struct intel_unpin_work *work = intel_crtc->unpin_work;
3663
3664 /* ensure that the unpin work is consistent wrt ->pending. */
3665 smp_rmb();
3666 intel_crtc->unpin_work = NULL;
3667
3668 if (work->event)
3669 drm_send_vblank_event(intel_crtc->base.dev,
3670 intel_crtc->pipe,
3671 work->event);
3672
3673 drm_crtc_vblank_put(&intel_crtc->base);
3674
3675 wake_up_all(&dev_priv->pending_flip_queue);
3676 queue_work(dev_priv->wq, &work->work);
3677
3678 trace_i915_flip_complete(intel_crtc->plane,
3679 work->pending_flip_obj);
3680 }
3681
3682 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3683 {
3684 struct drm_device *dev = crtc->dev;
3685 struct drm_i915_private *dev_priv = dev->dev_private;
3686
3687 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3688 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3689 !intel_crtc_has_pending_flip(crtc),
3690 60*HZ) == 0)) {
3691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3692
3693 spin_lock_irq(&dev->event_lock);
3694 if (intel_crtc->unpin_work) {
3695 WARN_ONCE(1, "Removing stuck page flip\n");
3696 page_flip_completed(intel_crtc);
3697 }
3698 spin_unlock_irq(&dev->event_lock);
3699 }
3700
3701 if (crtc->primary->fb) {
3702 mutex_lock(&dev->struct_mutex);
3703 intel_finish_fb(crtc->primary->fb);
3704 mutex_unlock(&dev->struct_mutex);
3705 }
3706 }
3707
3708 /* Program iCLKIP clock to the desired frequency */
3709 static void lpt_program_iclkip(struct drm_crtc *crtc)
3710 {
3711 struct drm_device *dev = crtc->dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3714 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3715 u32 temp;
3716
3717 mutex_lock(&dev_priv->dpio_lock);
3718
3719 /* It is necessary to ungate the pixclk gate prior to programming
3720 * the divisors, and gate it back when it is done.
3721 */
3722 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3723
3724 /* Disable SSCCTL */
3725 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3726 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3727 SBI_SSCCTL_DISABLE,
3728 SBI_ICLK);
3729
3730 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3731 if (clock == 20000) {
3732 auxdiv = 1;
3733 divsel = 0x41;
3734 phaseinc = 0x20;
3735 } else {
3736 /* The iCLK virtual clock root frequency is in MHz,
3737 * but the adjusted_mode->crtc_clock in in KHz. To get the
3738 * divisors, it is necessary to divide one by another, so we
3739 * convert the virtual clock precision to KHz here for higher
3740 * precision.
3741 */
3742 u32 iclk_virtual_root_freq = 172800 * 1000;
3743 u32 iclk_pi_range = 64;
3744 u32 desired_divisor, msb_divisor_value, pi_value;
3745
3746 desired_divisor = (iclk_virtual_root_freq / clock);
3747 msb_divisor_value = desired_divisor / iclk_pi_range;
3748 pi_value = desired_divisor % iclk_pi_range;
3749
3750 auxdiv = 0;
3751 divsel = msb_divisor_value - 2;
3752 phaseinc = pi_value;
3753 }
3754
3755 /* This should not happen with any sane values */
3756 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3757 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3758 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3759 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3760
3761 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3762 clock,
3763 auxdiv,
3764 divsel,
3765 phasedir,
3766 phaseinc);
3767
3768 /* Program SSCDIVINTPHASE6 */
3769 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3770 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3771 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3772 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3773 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3774 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3775 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3776 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3777
3778 /* Program SSCAUXDIV */
3779 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3780 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3781 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3782 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3783
3784 /* Enable modulator and associated divider */
3785 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3786 temp &= ~SBI_SSCCTL_DISABLE;
3787 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3788
3789 /* Wait for initialization time */
3790 udelay(24);
3791
3792 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3793
3794 mutex_unlock(&dev_priv->dpio_lock);
3795 }
3796
3797 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3798 enum pipe pch_transcoder)
3799 {
3800 struct drm_device *dev = crtc->base.dev;
3801 struct drm_i915_private *dev_priv = dev->dev_private;
3802 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3803
3804 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3805 I915_READ(HTOTAL(cpu_transcoder)));
3806 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3807 I915_READ(HBLANK(cpu_transcoder)));
3808 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3809 I915_READ(HSYNC(cpu_transcoder)));
3810
3811 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3812 I915_READ(VTOTAL(cpu_transcoder)));
3813 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3814 I915_READ(VBLANK(cpu_transcoder)));
3815 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3816 I915_READ(VSYNC(cpu_transcoder)));
3817 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3818 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3819 }
3820
3821 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3822 {
3823 struct drm_i915_private *dev_priv = dev->dev_private;
3824 uint32_t temp;
3825
3826 temp = I915_READ(SOUTH_CHICKEN1);
3827 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3828 return;
3829
3830 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3831 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3832
3833 temp &= ~FDI_BC_BIFURCATION_SELECT;
3834 if (enable)
3835 temp |= FDI_BC_BIFURCATION_SELECT;
3836
3837 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3838 I915_WRITE(SOUTH_CHICKEN1, temp);
3839 POSTING_READ(SOUTH_CHICKEN1);
3840 }
3841
3842 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3843 {
3844 struct drm_device *dev = intel_crtc->base.dev;
3845
3846 switch (intel_crtc->pipe) {
3847 case PIPE_A:
3848 break;
3849 case PIPE_B:
3850 if (intel_crtc->config->fdi_lanes > 2)
3851 cpt_set_fdi_bc_bifurcation(dev, false);
3852 else
3853 cpt_set_fdi_bc_bifurcation(dev, true);
3854
3855 break;
3856 case PIPE_C:
3857 cpt_set_fdi_bc_bifurcation(dev, true);
3858
3859 break;
3860 default:
3861 BUG();
3862 }
3863 }
3864
3865 /*
3866 * Enable PCH resources required for PCH ports:
3867 * - PCH PLLs
3868 * - FDI training & RX/TX
3869 * - update transcoder timings
3870 * - DP transcoding bits
3871 * - transcoder
3872 */
3873 static void ironlake_pch_enable(struct drm_crtc *crtc)
3874 {
3875 struct drm_device *dev = crtc->dev;
3876 struct drm_i915_private *dev_priv = dev->dev_private;
3877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3878 int pipe = intel_crtc->pipe;
3879 u32 reg, temp;
3880
3881 assert_pch_transcoder_disabled(dev_priv, pipe);
3882
3883 if (IS_IVYBRIDGE(dev))
3884 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3885
3886 /* Write the TU size bits before fdi link training, so that error
3887 * detection works. */
3888 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3889 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3890
3891 /* For PCH output, training FDI link */
3892 dev_priv->display.fdi_link_train(crtc);
3893
3894 /* We need to program the right clock selection before writing the pixel
3895 * mutliplier into the DPLL. */
3896 if (HAS_PCH_CPT(dev)) {
3897 u32 sel;
3898
3899 temp = I915_READ(PCH_DPLL_SEL);
3900 temp |= TRANS_DPLL_ENABLE(pipe);
3901 sel = TRANS_DPLLB_SEL(pipe);
3902 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3903 temp |= sel;
3904 else
3905 temp &= ~sel;
3906 I915_WRITE(PCH_DPLL_SEL, temp);
3907 }
3908
3909 /* XXX: pch pll's can be enabled any time before we enable the PCH
3910 * transcoder, and we actually should do this to not upset any PCH
3911 * transcoder that already use the clock when we share it.
3912 *
3913 * Note that enable_shared_dpll tries to do the right thing, but
3914 * get_shared_dpll unconditionally resets the pll - we need that to have
3915 * the right LVDS enable sequence. */
3916 intel_enable_shared_dpll(intel_crtc);
3917
3918 /* set transcoder timing, panel must allow it */
3919 assert_panel_unlocked(dev_priv, pipe);
3920 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3921
3922 intel_fdi_normal_train(crtc);
3923
3924 /* For PCH DP, enable TRANS_DP_CTL */
3925 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3926 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3927 reg = TRANS_DP_CTL(pipe);
3928 temp = I915_READ(reg);
3929 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3930 TRANS_DP_SYNC_MASK |
3931 TRANS_DP_BPC_MASK);
3932 temp |= (TRANS_DP_OUTPUT_ENABLE |
3933 TRANS_DP_ENH_FRAMING);
3934 temp |= bpc << 9; /* same format but at 11:9 */
3935
3936 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3937 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3938 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3939 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3940
3941 switch (intel_trans_dp_port_sel(crtc)) {
3942 case PCH_DP_B:
3943 temp |= TRANS_DP_PORT_SEL_B;
3944 break;
3945 case PCH_DP_C:
3946 temp |= TRANS_DP_PORT_SEL_C;
3947 break;
3948 case PCH_DP_D:
3949 temp |= TRANS_DP_PORT_SEL_D;
3950 break;
3951 default:
3952 BUG();
3953 }
3954
3955 I915_WRITE(reg, temp);
3956 }
3957
3958 ironlake_enable_pch_transcoder(dev_priv, pipe);
3959 }
3960
3961 static void lpt_pch_enable(struct drm_crtc *crtc)
3962 {
3963 struct drm_device *dev = crtc->dev;
3964 struct drm_i915_private *dev_priv = dev->dev_private;
3965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3966 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3967
3968 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3969
3970 lpt_program_iclkip(crtc);
3971
3972 /* Set transcoder timing. */
3973 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3974
3975 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3976 }
3977
3978 void intel_put_shared_dpll(struct intel_crtc *crtc)
3979 {
3980 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3981
3982 if (pll == NULL)
3983 return;
3984
3985 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3986 WARN(1, "bad %s crtc mask\n", pll->name);
3987 return;
3988 }
3989
3990 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3991 if (pll->config.crtc_mask == 0) {
3992 WARN_ON(pll->on);
3993 WARN_ON(pll->active);
3994 }
3995
3996 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3997 }
3998
3999 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4000 struct intel_crtc_state *crtc_state)
4001 {
4002 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4003 struct intel_shared_dpll *pll;
4004 enum intel_dpll_id i;
4005
4006 if (HAS_PCH_IBX(dev_priv->dev)) {
4007 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4008 i = (enum intel_dpll_id) crtc->pipe;
4009 pll = &dev_priv->shared_dplls[i];
4010
4011 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4012 crtc->base.base.id, pll->name);
4013
4014 WARN_ON(pll->new_config->crtc_mask);
4015
4016 goto found;
4017 }
4018
4019 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4020 pll = &dev_priv->shared_dplls[i];
4021
4022 /* Only want to check enabled timings first */
4023 if (pll->new_config->crtc_mask == 0)
4024 continue;
4025
4026 if (memcmp(&crtc_state->dpll_hw_state,
4027 &pll->new_config->hw_state,
4028 sizeof(pll->new_config->hw_state)) == 0) {
4029 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4030 crtc->base.base.id, pll->name,
4031 pll->new_config->crtc_mask,
4032 pll->active);
4033 goto found;
4034 }
4035 }
4036
4037 /* Ok no matching timings, maybe there's a free one? */
4038 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4039 pll = &dev_priv->shared_dplls[i];
4040 if (pll->new_config->crtc_mask == 0) {
4041 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4042 crtc->base.base.id, pll->name);
4043 goto found;
4044 }
4045 }
4046
4047 return NULL;
4048
4049 found:
4050 if (pll->new_config->crtc_mask == 0)
4051 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4052
4053 crtc_state->shared_dpll = i;
4054 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4055 pipe_name(crtc->pipe));
4056
4057 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4058
4059 return pll;
4060 }
4061
4062 /**
4063 * intel_shared_dpll_start_config - start a new PLL staged config
4064 * @dev_priv: DRM device
4065 * @clear_pipes: mask of pipes that will have their PLLs freed
4066 *
4067 * Starts a new PLL staged config, copying the current config but
4068 * releasing the references of pipes specified in clear_pipes.
4069 */
4070 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4071 unsigned clear_pipes)
4072 {
4073 struct intel_shared_dpll *pll;
4074 enum intel_dpll_id i;
4075
4076 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4077 pll = &dev_priv->shared_dplls[i];
4078
4079 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4080 GFP_KERNEL);
4081 if (!pll->new_config)
4082 goto cleanup;
4083
4084 pll->new_config->crtc_mask &= ~clear_pipes;
4085 }
4086
4087 return 0;
4088
4089 cleanup:
4090 while (--i >= 0) {
4091 pll = &dev_priv->shared_dplls[i];
4092 kfree(pll->new_config);
4093 pll->new_config = NULL;
4094 }
4095
4096 return -ENOMEM;
4097 }
4098
4099 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4100 {
4101 struct intel_shared_dpll *pll;
4102 enum intel_dpll_id i;
4103
4104 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4105 pll = &dev_priv->shared_dplls[i];
4106
4107 WARN_ON(pll->new_config == &pll->config);
4108
4109 pll->config = *pll->new_config;
4110 kfree(pll->new_config);
4111 pll->new_config = NULL;
4112 }
4113 }
4114
4115 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4116 {
4117 struct intel_shared_dpll *pll;
4118 enum intel_dpll_id i;
4119
4120 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4121 pll = &dev_priv->shared_dplls[i];
4122
4123 WARN_ON(pll->new_config == &pll->config);
4124
4125 kfree(pll->new_config);
4126 pll->new_config = NULL;
4127 }
4128 }
4129
4130 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4131 {
4132 struct drm_i915_private *dev_priv = dev->dev_private;
4133 int dslreg = PIPEDSL(pipe);
4134 u32 temp;
4135
4136 temp = I915_READ(dslreg);
4137 udelay(500);
4138 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4139 if (wait_for(I915_READ(dslreg) != temp, 5))
4140 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4141 }
4142 }
4143
4144 static void skylake_pfit_enable(struct intel_crtc *crtc)
4145 {
4146 struct drm_device *dev = crtc->base.dev;
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 int pipe = crtc->pipe;
4149
4150 if (crtc->config->pch_pfit.enabled) {
4151 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4152 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4153 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4154 }
4155 }
4156
4157 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4158 {
4159 struct drm_device *dev = crtc->base.dev;
4160 struct drm_i915_private *dev_priv = dev->dev_private;
4161 int pipe = crtc->pipe;
4162
4163 if (crtc->config->pch_pfit.enabled) {
4164 /* Force use of hard-coded filter coefficients
4165 * as some pre-programmed values are broken,
4166 * e.g. x201.
4167 */
4168 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4169 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4170 PF_PIPE_SEL_IVB(pipe));
4171 else
4172 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4173 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4174 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4175 }
4176 }
4177
4178 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4179 {
4180 struct drm_device *dev = crtc->dev;
4181 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4182 struct drm_plane *plane;
4183 struct intel_plane *intel_plane;
4184
4185 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4186 intel_plane = to_intel_plane(plane);
4187 if (intel_plane->pipe == pipe)
4188 intel_plane_restore(&intel_plane->base);
4189 }
4190 }
4191
4192 /*
4193 * Disable a plane internally without actually modifying the plane's state.
4194 * This will allow us to easily restore the plane later by just reprogramming
4195 * its state.
4196 */
4197 static void disable_plane_internal(struct drm_plane *plane)
4198 {
4199 struct intel_plane *intel_plane = to_intel_plane(plane);
4200 struct drm_plane_state *state =
4201 plane->funcs->atomic_duplicate_state(plane);
4202 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4203
4204 intel_state->visible = false;
4205 intel_plane->commit_plane(plane, intel_state);
4206
4207 intel_plane_destroy_state(plane, state);
4208 }
4209
4210 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4211 {
4212 struct drm_device *dev = crtc->dev;
4213 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4214 struct drm_plane *plane;
4215 struct intel_plane *intel_plane;
4216
4217 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4218 intel_plane = to_intel_plane(plane);
4219 if (plane->fb && intel_plane->pipe == pipe)
4220 disable_plane_internal(plane);
4221 }
4222 }
4223
4224 void hsw_enable_ips(struct intel_crtc *crtc)
4225 {
4226 struct drm_device *dev = crtc->base.dev;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228
4229 if (!crtc->config->ips_enabled)
4230 return;
4231
4232 /* We can only enable IPS after we enable a plane and wait for a vblank */
4233 intel_wait_for_vblank(dev, crtc->pipe);
4234
4235 assert_plane_enabled(dev_priv, crtc->plane);
4236 if (IS_BROADWELL(dev)) {
4237 mutex_lock(&dev_priv->rps.hw_lock);
4238 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4239 mutex_unlock(&dev_priv->rps.hw_lock);
4240 /* Quoting Art Runyan: "its not safe to expect any particular
4241 * value in IPS_CTL bit 31 after enabling IPS through the
4242 * mailbox." Moreover, the mailbox may return a bogus state,
4243 * so we need to just enable it and continue on.
4244 */
4245 } else {
4246 I915_WRITE(IPS_CTL, IPS_ENABLE);
4247 /* The bit only becomes 1 in the next vblank, so this wait here
4248 * is essentially intel_wait_for_vblank. If we don't have this
4249 * and don't wait for vblanks until the end of crtc_enable, then
4250 * the HW state readout code will complain that the expected
4251 * IPS_CTL value is not the one we read. */
4252 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4253 DRM_ERROR("Timed out waiting for IPS enable\n");
4254 }
4255 }
4256
4257 void hsw_disable_ips(struct intel_crtc *crtc)
4258 {
4259 struct drm_device *dev = crtc->base.dev;
4260 struct drm_i915_private *dev_priv = dev->dev_private;
4261
4262 if (!crtc->config->ips_enabled)
4263 return;
4264
4265 assert_plane_enabled(dev_priv, crtc->plane);
4266 if (IS_BROADWELL(dev)) {
4267 mutex_lock(&dev_priv->rps.hw_lock);
4268 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4269 mutex_unlock(&dev_priv->rps.hw_lock);
4270 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4271 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4272 DRM_ERROR("Timed out waiting for IPS disable\n");
4273 } else {
4274 I915_WRITE(IPS_CTL, 0);
4275 POSTING_READ(IPS_CTL);
4276 }
4277
4278 /* We need to wait for a vblank before we can disable the plane. */
4279 intel_wait_for_vblank(dev, crtc->pipe);
4280 }
4281
4282 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4283 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4284 {
4285 struct drm_device *dev = crtc->dev;
4286 struct drm_i915_private *dev_priv = dev->dev_private;
4287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4288 enum pipe pipe = intel_crtc->pipe;
4289 int palreg = PALETTE(pipe);
4290 int i;
4291 bool reenable_ips = false;
4292
4293 /* The clocks have to be on to load the palette. */
4294 if (!crtc->state->enable || !intel_crtc->active)
4295 return;
4296
4297 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4298 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4299 assert_dsi_pll_enabled(dev_priv);
4300 else
4301 assert_pll_enabled(dev_priv, pipe);
4302 }
4303
4304 /* use legacy palette for Ironlake */
4305 if (!HAS_GMCH_DISPLAY(dev))
4306 palreg = LGC_PALETTE(pipe);
4307
4308 /* Workaround : Do not read or write the pipe palette/gamma data while
4309 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4310 */
4311 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4312 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4313 GAMMA_MODE_MODE_SPLIT)) {
4314 hsw_disable_ips(intel_crtc);
4315 reenable_ips = true;
4316 }
4317
4318 for (i = 0; i < 256; i++) {
4319 I915_WRITE(palreg + 4 * i,
4320 (intel_crtc->lut_r[i] << 16) |
4321 (intel_crtc->lut_g[i] << 8) |
4322 intel_crtc->lut_b[i]);
4323 }
4324
4325 if (reenable_ips)
4326 hsw_enable_ips(intel_crtc);
4327 }
4328
4329 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4330 {
4331 if (!enable && intel_crtc->overlay) {
4332 struct drm_device *dev = intel_crtc->base.dev;
4333 struct drm_i915_private *dev_priv = dev->dev_private;
4334
4335 mutex_lock(&dev->struct_mutex);
4336 dev_priv->mm.interruptible = false;
4337 (void) intel_overlay_switch_off(intel_crtc->overlay);
4338 dev_priv->mm.interruptible = true;
4339 mutex_unlock(&dev->struct_mutex);
4340 }
4341
4342 /* Let userspace switch the overlay on again. In most cases userspace
4343 * has to recompute where to put it anyway.
4344 */
4345 }
4346
4347 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4348 {
4349 struct drm_device *dev = crtc->dev;
4350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4351 int pipe = intel_crtc->pipe;
4352
4353 intel_enable_primary_hw_plane(crtc->primary, crtc);
4354 intel_enable_sprite_planes(crtc);
4355 intel_crtc_update_cursor(crtc, true);
4356 intel_crtc_dpms_overlay(intel_crtc, true);
4357
4358 hsw_enable_ips(intel_crtc);
4359
4360 mutex_lock(&dev->struct_mutex);
4361 intel_fbc_update(dev);
4362 mutex_unlock(&dev->struct_mutex);
4363
4364 /*
4365 * FIXME: Once we grow proper nuclear flip support out of this we need
4366 * to compute the mask of flip planes precisely. For the time being
4367 * consider this a flip from a NULL plane.
4368 */
4369 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4370 }
4371
4372 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4373 {
4374 struct drm_device *dev = crtc->dev;
4375 struct drm_i915_private *dev_priv = dev->dev_private;
4376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4377 int pipe = intel_crtc->pipe;
4378
4379 intel_crtc_wait_for_pending_flips(crtc);
4380
4381 if (dev_priv->fbc.crtc == intel_crtc)
4382 intel_fbc_disable(dev);
4383
4384 hsw_disable_ips(intel_crtc);
4385
4386 intel_crtc_dpms_overlay(intel_crtc, false);
4387 intel_crtc_update_cursor(crtc, false);
4388 intel_disable_sprite_planes(crtc);
4389 intel_disable_primary_hw_plane(crtc->primary, crtc);
4390
4391 /*
4392 * FIXME: Once we grow proper nuclear flip support out of this we need
4393 * to compute the mask of flip planes precisely. For the time being
4394 * consider this a flip to a NULL plane.
4395 */
4396 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4397 }
4398
4399 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4400 {
4401 struct drm_device *dev = crtc->dev;
4402 struct drm_i915_private *dev_priv = dev->dev_private;
4403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4404 struct intel_encoder *encoder;
4405 int pipe = intel_crtc->pipe;
4406
4407 WARN_ON(!crtc->state->enable);
4408
4409 if (intel_crtc->active)
4410 return;
4411
4412 if (intel_crtc->config->has_pch_encoder)
4413 intel_prepare_shared_dpll(intel_crtc);
4414
4415 if (intel_crtc->config->has_dp_encoder)
4416 intel_dp_set_m_n(intel_crtc, M1_N1);
4417
4418 intel_set_pipe_timings(intel_crtc);
4419
4420 if (intel_crtc->config->has_pch_encoder) {
4421 intel_cpu_transcoder_set_m_n(intel_crtc,
4422 &intel_crtc->config->fdi_m_n, NULL);
4423 }
4424
4425 ironlake_set_pipeconf(crtc);
4426
4427 intel_crtc->active = true;
4428
4429 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4430 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4431
4432 for_each_encoder_on_crtc(dev, crtc, encoder)
4433 if (encoder->pre_enable)
4434 encoder->pre_enable(encoder);
4435
4436 if (intel_crtc->config->has_pch_encoder) {
4437 /* Note: FDI PLL enabling _must_ be done before we enable the
4438 * cpu pipes, hence this is separate from all the other fdi/pch
4439 * enabling. */
4440 ironlake_fdi_pll_enable(intel_crtc);
4441 } else {
4442 assert_fdi_tx_disabled(dev_priv, pipe);
4443 assert_fdi_rx_disabled(dev_priv, pipe);
4444 }
4445
4446 ironlake_pfit_enable(intel_crtc);
4447
4448 /*
4449 * On ILK+ LUT must be loaded before the pipe is running but with
4450 * clocks enabled
4451 */
4452 intel_crtc_load_lut(crtc);
4453
4454 intel_update_watermarks(crtc);
4455 intel_enable_pipe(intel_crtc);
4456
4457 if (intel_crtc->config->has_pch_encoder)
4458 ironlake_pch_enable(crtc);
4459
4460 assert_vblank_disabled(crtc);
4461 drm_crtc_vblank_on(crtc);
4462
4463 for_each_encoder_on_crtc(dev, crtc, encoder)
4464 encoder->enable(encoder);
4465
4466 if (HAS_PCH_CPT(dev))
4467 cpt_verify_modeset(dev, intel_crtc->pipe);
4468
4469 intel_crtc_enable_planes(crtc);
4470 }
4471
4472 /* IPS only exists on ULT machines and is tied to pipe A. */
4473 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4474 {
4475 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4476 }
4477
4478 /*
4479 * This implements the workaround described in the "notes" section of the mode
4480 * set sequence documentation. When going from no pipes or single pipe to
4481 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4482 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4483 */
4484 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4485 {
4486 struct drm_device *dev = crtc->base.dev;
4487 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4488
4489 /* We want to get the other_active_crtc only if there's only 1 other
4490 * active crtc. */
4491 for_each_intel_crtc(dev, crtc_it) {
4492 if (!crtc_it->active || crtc_it == crtc)
4493 continue;
4494
4495 if (other_active_crtc)
4496 return;
4497
4498 other_active_crtc = crtc_it;
4499 }
4500 if (!other_active_crtc)
4501 return;
4502
4503 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4504 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4505 }
4506
4507 static void haswell_crtc_enable(struct drm_crtc *crtc)
4508 {
4509 struct drm_device *dev = crtc->dev;
4510 struct drm_i915_private *dev_priv = dev->dev_private;
4511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4512 struct intel_encoder *encoder;
4513 int pipe = intel_crtc->pipe;
4514
4515 WARN_ON(!crtc->state->enable);
4516
4517 if (intel_crtc->active)
4518 return;
4519
4520 if (intel_crtc_to_shared_dpll(intel_crtc))
4521 intel_enable_shared_dpll(intel_crtc);
4522
4523 if (intel_crtc->config->has_dp_encoder)
4524 intel_dp_set_m_n(intel_crtc, M1_N1);
4525
4526 intel_set_pipe_timings(intel_crtc);
4527
4528 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4529 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4530 intel_crtc->config->pixel_multiplier - 1);
4531 }
4532
4533 if (intel_crtc->config->has_pch_encoder) {
4534 intel_cpu_transcoder_set_m_n(intel_crtc,
4535 &intel_crtc->config->fdi_m_n, NULL);
4536 }
4537
4538 haswell_set_pipeconf(crtc);
4539
4540 intel_set_pipe_csc(crtc);
4541
4542 intel_crtc->active = true;
4543
4544 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4545 for_each_encoder_on_crtc(dev, crtc, encoder)
4546 if (encoder->pre_enable)
4547 encoder->pre_enable(encoder);
4548
4549 if (intel_crtc->config->has_pch_encoder) {
4550 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4551 true);
4552 dev_priv->display.fdi_link_train(crtc);
4553 }
4554
4555 intel_ddi_enable_pipe_clock(intel_crtc);
4556
4557 if (IS_SKYLAKE(dev))
4558 skylake_pfit_enable(intel_crtc);
4559 else
4560 ironlake_pfit_enable(intel_crtc);
4561
4562 /*
4563 * On ILK+ LUT must be loaded before the pipe is running but with
4564 * clocks enabled
4565 */
4566 intel_crtc_load_lut(crtc);
4567
4568 intel_ddi_set_pipe_settings(crtc);
4569 intel_ddi_enable_transcoder_func(crtc);
4570
4571 intel_update_watermarks(crtc);
4572 intel_enable_pipe(intel_crtc);
4573
4574 if (intel_crtc->config->has_pch_encoder)
4575 lpt_pch_enable(crtc);
4576
4577 if (intel_crtc->config->dp_encoder_is_mst)
4578 intel_ddi_set_vc_payload_alloc(crtc, true);
4579
4580 assert_vblank_disabled(crtc);
4581 drm_crtc_vblank_on(crtc);
4582
4583 for_each_encoder_on_crtc(dev, crtc, encoder) {
4584 encoder->enable(encoder);
4585 intel_opregion_notify_encoder(encoder, true);
4586 }
4587
4588 /* If we change the relative order between pipe/planes enabling, we need
4589 * to change the workaround. */
4590 haswell_mode_set_planes_workaround(intel_crtc);
4591 intel_crtc_enable_planes(crtc);
4592 }
4593
4594 static void skylake_pfit_disable(struct intel_crtc *crtc)
4595 {
4596 struct drm_device *dev = crtc->base.dev;
4597 struct drm_i915_private *dev_priv = dev->dev_private;
4598 int pipe = crtc->pipe;
4599
4600 /* To avoid upsetting the power well on haswell only disable the pfit if
4601 * it's in use. The hw state code will make sure we get this right. */
4602 if (crtc->config->pch_pfit.enabled) {
4603 I915_WRITE(PS_CTL(pipe), 0);
4604 I915_WRITE(PS_WIN_POS(pipe), 0);
4605 I915_WRITE(PS_WIN_SZ(pipe), 0);
4606 }
4607 }
4608
4609 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4610 {
4611 struct drm_device *dev = crtc->base.dev;
4612 struct drm_i915_private *dev_priv = dev->dev_private;
4613 int pipe = crtc->pipe;
4614
4615 /* To avoid upsetting the power well on haswell only disable the pfit if
4616 * it's in use. The hw state code will make sure we get this right. */
4617 if (crtc->config->pch_pfit.enabled) {
4618 I915_WRITE(PF_CTL(pipe), 0);
4619 I915_WRITE(PF_WIN_POS(pipe), 0);
4620 I915_WRITE(PF_WIN_SZ(pipe), 0);
4621 }
4622 }
4623
4624 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4625 {
4626 struct drm_device *dev = crtc->dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4629 struct intel_encoder *encoder;
4630 int pipe = intel_crtc->pipe;
4631 u32 reg, temp;
4632
4633 if (!intel_crtc->active)
4634 return;
4635
4636 intel_crtc_disable_planes(crtc);
4637
4638 for_each_encoder_on_crtc(dev, crtc, encoder)
4639 encoder->disable(encoder);
4640
4641 drm_crtc_vblank_off(crtc);
4642 assert_vblank_disabled(crtc);
4643
4644 if (intel_crtc->config->has_pch_encoder)
4645 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4646
4647 intel_disable_pipe(intel_crtc);
4648
4649 ironlake_pfit_disable(intel_crtc);
4650
4651 for_each_encoder_on_crtc(dev, crtc, encoder)
4652 if (encoder->post_disable)
4653 encoder->post_disable(encoder);
4654
4655 if (intel_crtc->config->has_pch_encoder) {
4656 ironlake_fdi_disable(crtc);
4657
4658 ironlake_disable_pch_transcoder(dev_priv, pipe);
4659
4660 if (HAS_PCH_CPT(dev)) {
4661 /* disable TRANS_DP_CTL */
4662 reg = TRANS_DP_CTL(pipe);
4663 temp = I915_READ(reg);
4664 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4665 TRANS_DP_PORT_SEL_MASK);
4666 temp |= TRANS_DP_PORT_SEL_NONE;
4667 I915_WRITE(reg, temp);
4668
4669 /* disable DPLL_SEL */
4670 temp = I915_READ(PCH_DPLL_SEL);
4671 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4672 I915_WRITE(PCH_DPLL_SEL, temp);
4673 }
4674
4675 /* disable PCH DPLL */
4676 intel_disable_shared_dpll(intel_crtc);
4677
4678 ironlake_fdi_pll_disable(intel_crtc);
4679 }
4680
4681 intel_crtc->active = false;
4682 intel_update_watermarks(crtc);
4683
4684 mutex_lock(&dev->struct_mutex);
4685 intel_fbc_update(dev);
4686 mutex_unlock(&dev->struct_mutex);
4687 }
4688
4689 static void haswell_crtc_disable(struct drm_crtc *crtc)
4690 {
4691 struct drm_device *dev = crtc->dev;
4692 struct drm_i915_private *dev_priv = dev->dev_private;
4693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4694 struct intel_encoder *encoder;
4695 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4696
4697 if (!intel_crtc->active)
4698 return;
4699
4700 intel_crtc_disable_planes(crtc);
4701
4702 for_each_encoder_on_crtc(dev, crtc, encoder) {
4703 intel_opregion_notify_encoder(encoder, false);
4704 encoder->disable(encoder);
4705 }
4706
4707 drm_crtc_vblank_off(crtc);
4708 assert_vblank_disabled(crtc);
4709
4710 if (intel_crtc->config->has_pch_encoder)
4711 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4712 false);
4713 intel_disable_pipe(intel_crtc);
4714
4715 if (intel_crtc->config->dp_encoder_is_mst)
4716 intel_ddi_set_vc_payload_alloc(crtc, false);
4717
4718 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4719
4720 if (IS_SKYLAKE(dev))
4721 skylake_pfit_disable(intel_crtc);
4722 else
4723 ironlake_pfit_disable(intel_crtc);
4724
4725 intel_ddi_disable_pipe_clock(intel_crtc);
4726
4727 if (intel_crtc->config->has_pch_encoder) {
4728 lpt_disable_pch_transcoder(dev_priv);
4729 intel_ddi_fdi_disable(crtc);
4730 }
4731
4732 for_each_encoder_on_crtc(dev, crtc, encoder)
4733 if (encoder->post_disable)
4734 encoder->post_disable(encoder);
4735
4736 intel_crtc->active = false;
4737 intel_update_watermarks(crtc);
4738
4739 mutex_lock(&dev->struct_mutex);
4740 intel_fbc_update(dev);
4741 mutex_unlock(&dev->struct_mutex);
4742
4743 if (intel_crtc_to_shared_dpll(intel_crtc))
4744 intel_disable_shared_dpll(intel_crtc);
4745 }
4746
4747 static void ironlake_crtc_off(struct drm_crtc *crtc)
4748 {
4749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4750 intel_put_shared_dpll(intel_crtc);
4751 }
4752
4753
4754 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4755 {
4756 struct drm_device *dev = crtc->base.dev;
4757 struct drm_i915_private *dev_priv = dev->dev_private;
4758 struct intel_crtc_state *pipe_config = crtc->config;
4759
4760 if (!pipe_config->gmch_pfit.control)
4761 return;
4762
4763 /*
4764 * The panel fitter should only be adjusted whilst the pipe is disabled,
4765 * according to register description and PRM.
4766 */
4767 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4768 assert_pipe_disabled(dev_priv, crtc->pipe);
4769
4770 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4771 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4772
4773 /* Border color in case we don't scale up to the full screen. Black by
4774 * default, change to something else for debugging. */
4775 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4776 }
4777
4778 static enum intel_display_power_domain port_to_power_domain(enum port port)
4779 {
4780 switch (port) {
4781 case PORT_A:
4782 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4783 case PORT_B:
4784 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4785 case PORT_C:
4786 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4787 case PORT_D:
4788 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4789 default:
4790 WARN_ON_ONCE(1);
4791 return POWER_DOMAIN_PORT_OTHER;
4792 }
4793 }
4794
4795 #define for_each_power_domain(domain, mask) \
4796 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4797 if ((1 << (domain)) & (mask))
4798
4799 enum intel_display_power_domain
4800 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4801 {
4802 struct drm_device *dev = intel_encoder->base.dev;
4803 struct intel_digital_port *intel_dig_port;
4804
4805 switch (intel_encoder->type) {
4806 case INTEL_OUTPUT_UNKNOWN:
4807 /* Only DDI platforms should ever use this output type */
4808 WARN_ON_ONCE(!HAS_DDI(dev));
4809 case INTEL_OUTPUT_DISPLAYPORT:
4810 case INTEL_OUTPUT_HDMI:
4811 case INTEL_OUTPUT_EDP:
4812 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4813 return port_to_power_domain(intel_dig_port->port);
4814 case INTEL_OUTPUT_DP_MST:
4815 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4816 return port_to_power_domain(intel_dig_port->port);
4817 case INTEL_OUTPUT_ANALOG:
4818 return POWER_DOMAIN_PORT_CRT;
4819 case INTEL_OUTPUT_DSI:
4820 return POWER_DOMAIN_PORT_DSI;
4821 default:
4822 return POWER_DOMAIN_PORT_OTHER;
4823 }
4824 }
4825
4826 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4827 {
4828 struct drm_device *dev = crtc->dev;
4829 struct intel_encoder *intel_encoder;
4830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4831 enum pipe pipe = intel_crtc->pipe;
4832 unsigned long mask;
4833 enum transcoder transcoder;
4834
4835 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4836
4837 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4838 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4839 if (intel_crtc->config->pch_pfit.enabled ||
4840 intel_crtc->config->pch_pfit.force_thru)
4841 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4842
4843 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4844 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4845
4846 return mask;
4847 }
4848
4849 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4850 {
4851 struct drm_i915_private *dev_priv = dev->dev_private;
4852 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4853 struct intel_crtc *crtc;
4854
4855 /*
4856 * First get all needed power domains, then put all unneeded, to avoid
4857 * any unnecessary toggling of the power wells.
4858 */
4859 for_each_intel_crtc(dev, crtc) {
4860 enum intel_display_power_domain domain;
4861
4862 if (!crtc->base.state->enable)
4863 continue;
4864
4865 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4866
4867 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4868 intel_display_power_get(dev_priv, domain);
4869 }
4870
4871 if (dev_priv->display.modeset_global_resources)
4872 dev_priv->display.modeset_global_resources(dev);
4873
4874 for_each_intel_crtc(dev, crtc) {
4875 enum intel_display_power_domain domain;
4876
4877 for_each_power_domain(domain, crtc->enabled_power_domains)
4878 intel_display_power_put(dev_priv, domain);
4879
4880 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4881 }
4882
4883 intel_display_set_init_power(dev_priv, false);
4884 }
4885
4886 /* returns HPLL frequency in kHz */
4887 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4888 {
4889 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4890
4891 /* Obtain SKU information */
4892 mutex_lock(&dev_priv->dpio_lock);
4893 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4894 CCK_FUSE_HPLL_FREQ_MASK;
4895 mutex_unlock(&dev_priv->dpio_lock);
4896
4897 return vco_freq[hpll_freq] * 1000;
4898 }
4899
4900 static void vlv_update_cdclk(struct drm_device *dev)
4901 {
4902 struct drm_i915_private *dev_priv = dev->dev_private;
4903
4904 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4905 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4906 dev_priv->vlv_cdclk_freq);
4907
4908 /*
4909 * Program the gmbus_freq based on the cdclk frequency.
4910 * BSpec erroneously claims we should aim for 4MHz, but
4911 * in fact 1MHz is the correct frequency.
4912 */
4913 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4914 }
4915
4916 /* Adjust CDclk dividers to allow high res or save power if possible */
4917 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4918 {
4919 struct drm_i915_private *dev_priv = dev->dev_private;
4920 u32 val, cmd;
4921
4922 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4923
4924 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4925 cmd = 2;
4926 else if (cdclk == 266667)
4927 cmd = 1;
4928 else
4929 cmd = 0;
4930
4931 mutex_lock(&dev_priv->rps.hw_lock);
4932 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4933 val &= ~DSPFREQGUAR_MASK;
4934 val |= (cmd << DSPFREQGUAR_SHIFT);
4935 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4936 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4937 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4938 50)) {
4939 DRM_ERROR("timed out waiting for CDclk change\n");
4940 }
4941 mutex_unlock(&dev_priv->rps.hw_lock);
4942
4943 if (cdclk == 400000) {
4944 u32 divider;
4945
4946 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4947
4948 mutex_lock(&dev_priv->dpio_lock);
4949 /* adjust cdclk divider */
4950 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4951 val &= ~DISPLAY_FREQUENCY_VALUES;
4952 val |= divider;
4953 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4954
4955 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4956 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4957 50))
4958 DRM_ERROR("timed out waiting for CDclk change\n");
4959 mutex_unlock(&dev_priv->dpio_lock);
4960 }
4961
4962 mutex_lock(&dev_priv->dpio_lock);
4963 /* adjust self-refresh exit latency value */
4964 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4965 val &= ~0x7f;
4966
4967 /*
4968 * For high bandwidth configs, we set a higher latency in the bunit
4969 * so that the core display fetch happens in time to avoid underruns.
4970 */
4971 if (cdclk == 400000)
4972 val |= 4500 / 250; /* 4.5 usec */
4973 else
4974 val |= 3000 / 250; /* 3.0 usec */
4975 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4976 mutex_unlock(&dev_priv->dpio_lock);
4977
4978 vlv_update_cdclk(dev);
4979 }
4980
4981 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4982 {
4983 struct drm_i915_private *dev_priv = dev->dev_private;
4984 u32 val, cmd;
4985
4986 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4987
4988 switch (cdclk) {
4989 case 333333:
4990 case 320000:
4991 case 266667:
4992 case 200000:
4993 break;
4994 default:
4995 MISSING_CASE(cdclk);
4996 return;
4997 }
4998
4999 /*
5000 * Specs are full of misinformation, but testing on actual
5001 * hardware has shown that we just need to write the desired
5002 * CCK divider into the Punit register.
5003 */
5004 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5005
5006 mutex_lock(&dev_priv->rps.hw_lock);
5007 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5008 val &= ~DSPFREQGUAR_MASK_CHV;
5009 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5010 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5011 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5012 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5013 50)) {
5014 DRM_ERROR("timed out waiting for CDclk change\n");
5015 }
5016 mutex_unlock(&dev_priv->rps.hw_lock);
5017
5018 vlv_update_cdclk(dev);
5019 }
5020
5021 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5022 int max_pixclk)
5023 {
5024 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5025 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5026
5027 /*
5028 * Really only a few cases to deal with, as only 4 CDclks are supported:
5029 * 200MHz
5030 * 267MHz
5031 * 320/333MHz (depends on HPLL freq)
5032 * 400MHz (VLV only)
5033 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5034 * of the lower bin and adjust if needed.
5035 *
5036 * We seem to get an unstable or solid color picture at 200MHz.
5037 * Not sure what's wrong. For now use 200MHz only when all pipes
5038 * are off.
5039 */
5040 if (!IS_CHERRYVIEW(dev_priv) &&
5041 max_pixclk > freq_320*limit/100)
5042 return 400000;
5043 else if (max_pixclk > 266667*limit/100)
5044 return freq_320;
5045 else if (max_pixclk > 0)
5046 return 266667;
5047 else
5048 return 200000;
5049 }
5050
5051 /* compute the max pixel clock for new configuration */
5052 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5053 {
5054 struct drm_device *dev = dev_priv->dev;
5055 struct intel_crtc *intel_crtc;
5056 int max_pixclk = 0;
5057
5058 for_each_intel_crtc(dev, intel_crtc) {
5059 if (intel_crtc->new_enabled)
5060 max_pixclk = max(max_pixclk,
5061 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5062 }
5063
5064 return max_pixclk;
5065 }
5066
5067 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5068 unsigned *prepare_pipes)
5069 {
5070 struct drm_i915_private *dev_priv = dev->dev_private;
5071 struct intel_crtc *intel_crtc;
5072 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5073
5074 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5075 dev_priv->vlv_cdclk_freq)
5076 return;
5077
5078 /* disable/enable all currently active pipes while we change cdclk */
5079 for_each_intel_crtc(dev, intel_crtc)
5080 if (intel_crtc->base.state->enable)
5081 *prepare_pipes |= (1 << intel_crtc->pipe);
5082 }
5083
5084 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5085 {
5086 unsigned int credits, default_credits;
5087
5088 if (IS_CHERRYVIEW(dev_priv))
5089 default_credits = PFI_CREDIT(12);
5090 else
5091 default_credits = PFI_CREDIT(8);
5092
5093 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5094 /* CHV suggested value is 31 or 63 */
5095 if (IS_CHERRYVIEW(dev_priv))
5096 credits = PFI_CREDIT_31;
5097 else
5098 credits = PFI_CREDIT(15);
5099 } else {
5100 credits = default_credits;
5101 }
5102
5103 /*
5104 * WA - write default credits before re-programming
5105 * FIXME: should we also set the resend bit here?
5106 */
5107 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5108 default_credits);
5109
5110 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5111 credits | PFI_CREDIT_RESEND);
5112
5113 /*
5114 * FIXME is this guaranteed to clear
5115 * immediately or should we poll for it?
5116 */
5117 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5118 }
5119
5120 static void valleyview_modeset_global_resources(struct drm_device *dev)
5121 {
5122 struct drm_i915_private *dev_priv = dev->dev_private;
5123 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5124 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5125
5126 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5127 /*
5128 * FIXME: We can end up here with all power domains off, yet
5129 * with a CDCLK frequency other than the minimum. To account
5130 * for this take the PIPE-A power domain, which covers the HW
5131 * blocks needed for the following programming. This can be
5132 * removed once it's guaranteed that we get here either with
5133 * the minimum CDCLK set, or the required power domains
5134 * enabled.
5135 */
5136 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5137
5138 if (IS_CHERRYVIEW(dev))
5139 cherryview_set_cdclk(dev, req_cdclk);
5140 else
5141 valleyview_set_cdclk(dev, req_cdclk);
5142
5143 vlv_program_pfi_credits(dev_priv);
5144
5145 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5146 }
5147 }
5148
5149 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5150 {
5151 struct drm_device *dev = crtc->dev;
5152 struct drm_i915_private *dev_priv = to_i915(dev);
5153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5154 struct intel_encoder *encoder;
5155 int pipe = intel_crtc->pipe;
5156 bool is_dsi;
5157
5158 WARN_ON(!crtc->state->enable);
5159
5160 if (intel_crtc->active)
5161 return;
5162
5163 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5164
5165 if (!is_dsi) {
5166 if (IS_CHERRYVIEW(dev))
5167 chv_prepare_pll(intel_crtc, intel_crtc->config);
5168 else
5169 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5170 }
5171
5172 if (intel_crtc->config->has_dp_encoder)
5173 intel_dp_set_m_n(intel_crtc, M1_N1);
5174
5175 intel_set_pipe_timings(intel_crtc);
5176
5177 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5178 struct drm_i915_private *dev_priv = dev->dev_private;
5179
5180 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5181 I915_WRITE(CHV_CANVAS(pipe), 0);
5182 }
5183
5184 i9xx_set_pipeconf(intel_crtc);
5185
5186 intel_crtc->active = true;
5187
5188 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5189
5190 for_each_encoder_on_crtc(dev, crtc, encoder)
5191 if (encoder->pre_pll_enable)
5192 encoder->pre_pll_enable(encoder);
5193
5194 if (!is_dsi) {
5195 if (IS_CHERRYVIEW(dev))
5196 chv_enable_pll(intel_crtc, intel_crtc->config);
5197 else
5198 vlv_enable_pll(intel_crtc, intel_crtc->config);
5199 }
5200
5201 for_each_encoder_on_crtc(dev, crtc, encoder)
5202 if (encoder->pre_enable)
5203 encoder->pre_enable(encoder);
5204
5205 i9xx_pfit_enable(intel_crtc);
5206
5207 intel_crtc_load_lut(crtc);
5208
5209 intel_update_watermarks(crtc);
5210 intel_enable_pipe(intel_crtc);
5211
5212 assert_vblank_disabled(crtc);
5213 drm_crtc_vblank_on(crtc);
5214
5215 for_each_encoder_on_crtc(dev, crtc, encoder)
5216 encoder->enable(encoder);
5217
5218 intel_crtc_enable_planes(crtc);
5219
5220 /* Underruns don't raise interrupts, so check manually. */
5221 i9xx_check_fifo_underruns(dev_priv);
5222 }
5223
5224 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5225 {
5226 struct drm_device *dev = crtc->base.dev;
5227 struct drm_i915_private *dev_priv = dev->dev_private;
5228
5229 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5230 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5231 }
5232
5233 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5234 {
5235 struct drm_device *dev = crtc->dev;
5236 struct drm_i915_private *dev_priv = to_i915(dev);
5237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238 struct intel_encoder *encoder;
5239 int pipe = intel_crtc->pipe;
5240
5241 WARN_ON(!crtc->state->enable);
5242
5243 if (intel_crtc->active)
5244 return;
5245
5246 i9xx_set_pll_dividers(intel_crtc);
5247
5248 if (intel_crtc->config->has_dp_encoder)
5249 intel_dp_set_m_n(intel_crtc, M1_N1);
5250
5251 intel_set_pipe_timings(intel_crtc);
5252
5253 i9xx_set_pipeconf(intel_crtc);
5254
5255 intel_crtc->active = true;
5256
5257 if (!IS_GEN2(dev))
5258 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5259
5260 for_each_encoder_on_crtc(dev, crtc, encoder)
5261 if (encoder->pre_enable)
5262 encoder->pre_enable(encoder);
5263
5264 i9xx_enable_pll(intel_crtc);
5265
5266 i9xx_pfit_enable(intel_crtc);
5267
5268 intel_crtc_load_lut(crtc);
5269
5270 intel_update_watermarks(crtc);
5271 intel_enable_pipe(intel_crtc);
5272
5273 assert_vblank_disabled(crtc);
5274 drm_crtc_vblank_on(crtc);
5275
5276 for_each_encoder_on_crtc(dev, crtc, encoder)
5277 encoder->enable(encoder);
5278
5279 intel_crtc_enable_planes(crtc);
5280
5281 /*
5282 * Gen2 reports pipe underruns whenever all planes are disabled.
5283 * So don't enable underrun reporting before at least some planes
5284 * are enabled.
5285 * FIXME: Need to fix the logic to work when we turn off all planes
5286 * but leave the pipe running.
5287 */
5288 if (IS_GEN2(dev))
5289 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5290
5291 /* Underruns don't raise interrupts, so check manually. */
5292 i9xx_check_fifo_underruns(dev_priv);
5293 }
5294
5295 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5296 {
5297 struct drm_device *dev = crtc->base.dev;
5298 struct drm_i915_private *dev_priv = dev->dev_private;
5299
5300 if (!crtc->config->gmch_pfit.control)
5301 return;
5302
5303 assert_pipe_disabled(dev_priv, crtc->pipe);
5304
5305 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5306 I915_READ(PFIT_CONTROL));
5307 I915_WRITE(PFIT_CONTROL, 0);
5308 }
5309
5310 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5311 {
5312 struct drm_device *dev = crtc->dev;
5313 struct drm_i915_private *dev_priv = dev->dev_private;
5314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5315 struct intel_encoder *encoder;
5316 int pipe = intel_crtc->pipe;
5317
5318 if (!intel_crtc->active)
5319 return;
5320
5321 /*
5322 * Gen2 reports pipe underruns whenever all planes are disabled.
5323 * So diasble underrun reporting before all the planes get disabled.
5324 * FIXME: Need to fix the logic to work when we turn off all planes
5325 * but leave the pipe running.
5326 */
5327 if (IS_GEN2(dev))
5328 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5329
5330 /*
5331 * Vblank time updates from the shadow to live plane control register
5332 * are blocked if the memory self-refresh mode is active at that
5333 * moment. So to make sure the plane gets truly disabled, disable
5334 * first the self-refresh mode. The self-refresh enable bit in turn
5335 * will be checked/applied by the HW only at the next frame start
5336 * event which is after the vblank start event, so we need to have a
5337 * wait-for-vblank between disabling the plane and the pipe.
5338 */
5339 intel_set_memory_cxsr(dev_priv, false);
5340 intel_crtc_disable_planes(crtc);
5341
5342 /*
5343 * On gen2 planes are double buffered but the pipe isn't, so we must
5344 * wait for planes to fully turn off before disabling the pipe.
5345 * We also need to wait on all gmch platforms because of the
5346 * self-refresh mode constraint explained above.
5347 */
5348 intel_wait_for_vblank(dev, pipe);
5349
5350 for_each_encoder_on_crtc(dev, crtc, encoder)
5351 encoder->disable(encoder);
5352
5353 drm_crtc_vblank_off(crtc);
5354 assert_vblank_disabled(crtc);
5355
5356 intel_disable_pipe(intel_crtc);
5357
5358 i9xx_pfit_disable(intel_crtc);
5359
5360 for_each_encoder_on_crtc(dev, crtc, encoder)
5361 if (encoder->post_disable)
5362 encoder->post_disable(encoder);
5363
5364 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5365 if (IS_CHERRYVIEW(dev))
5366 chv_disable_pll(dev_priv, pipe);
5367 else if (IS_VALLEYVIEW(dev))
5368 vlv_disable_pll(dev_priv, pipe);
5369 else
5370 i9xx_disable_pll(intel_crtc);
5371 }
5372
5373 if (!IS_GEN2(dev))
5374 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5375
5376 intel_crtc->active = false;
5377 intel_update_watermarks(crtc);
5378
5379 mutex_lock(&dev->struct_mutex);
5380 intel_fbc_update(dev);
5381 mutex_unlock(&dev->struct_mutex);
5382 }
5383
5384 static void i9xx_crtc_off(struct drm_crtc *crtc)
5385 {
5386 }
5387
5388 /* Master function to enable/disable CRTC and corresponding power wells */
5389 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5390 {
5391 struct drm_device *dev = crtc->dev;
5392 struct drm_i915_private *dev_priv = dev->dev_private;
5393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5394 enum intel_display_power_domain domain;
5395 unsigned long domains;
5396
5397 if (enable) {
5398 if (!intel_crtc->active) {
5399 domains = get_crtc_power_domains(crtc);
5400 for_each_power_domain(domain, domains)
5401 intel_display_power_get(dev_priv, domain);
5402 intel_crtc->enabled_power_domains = domains;
5403
5404 dev_priv->display.crtc_enable(crtc);
5405 }
5406 } else {
5407 if (intel_crtc->active) {
5408 dev_priv->display.crtc_disable(crtc);
5409
5410 domains = intel_crtc->enabled_power_domains;
5411 for_each_power_domain(domain, domains)
5412 intel_display_power_put(dev_priv, domain);
5413 intel_crtc->enabled_power_domains = 0;
5414 }
5415 }
5416 }
5417
5418 /**
5419 * Sets the power management mode of the pipe and plane.
5420 */
5421 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5422 {
5423 struct drm_device *dev = crtc->dev;
5424 struct intel_encoder *intel_encoder;
5425 bool enable = false;
5426
5427 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5428 enable |= intel_encoder->connectors_active;
5429
5430 intel_crtc_control(crtc, enable);
5431 }
5432
5433 static void intel_crtc_disable(struct drm_crtc *crtc)
5434 {
5435 struct drm_device *dev = crtc->dev;
5436 struct drm_connector *connector;
5437 struct drm_i915_private *dev_priv = dev->dev_private;
5438
5439 /* crtc should still be enabled when we disable it. */
5440 WARN_ON(!crtc->state->enable);
5441
5442 dev_priv->display.crtc_disable(crtc);
5443 dev_priv->display.off(crtc);
5444
5445 crtc->primary->funcs->disable_plane(crtc->primary);
5446
5447 /* Update computed state. */
5448 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5449 if (!connector->encoder || !connector->encoder->crtc)
5450 continue;
5451
5452 if (connector->encoder->crtc != crtc)
5453 continue;
5454
5455 connector->dpms = DRM_MODE_DPMS_OFF;
5456 to_intel_encoder(connector->encoder)->connectors_active = false;
5457 }
5458 }
5459
5460 void intel_encoder_destroy(struct drm_encoder *encoder)
5461 {
5462 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5463
5464 drm_encoder_cleanup(encoder);
5465 kfree(intel_encoder);
5466 }
5467
5468 /* Simple dpms helper for encoders with just one connector, no cloning and only
5469 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5470 * state of the entire output pipe. */
5471 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5472 {
5473 if (mode == DRM_MODE_DPMS_ON) {
5474 encoder->connectors_active = true;
5475
5476 intel_crtc_update_dpms(encoder->base.crtc);
5477 } else {
5478 encoder->connectors_active = false;
5479
5480 intel_crtc_update_dpms(encoder->base.crtc);
5481 }
5482 }
5483
5484 /* Cross check the actual hw state with our own modeset state tracking (and it's
5485 * internal consistency). */
5486 static void intel_connector_check_state(struct intel_connector *connector)
5487 {
5488 if (connector->get_hw_state(connector)) {
5489 struct intel_encoder *encoder = connector->encoder;
5490 struct drm_crtc *crtc;
5491 bool encoder_enabled;
5492 enum pipe pipe;
5493
5494 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5495 connector->base.base.id,
5496 connector->base.name);
5497
5498 /* there is no real hw state for MST connectors */
5499 if (connector->mst_port)
5500 return;
5501
5502 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5503 "wrong connector dpms state\n");
5504 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5505 "active connector not linked to encoder\n");
5506
5507 if (encoder) {
5508 I915_STATE_WARN(!encoder->connectors_active,
5509 "encoder->connectors_active not set\n");
5510
5511 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5512 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5513 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5514 return;
5515
5516 crtc = encoder->base.crtc;
5517
5518 I915_STATE_WARN(!crtc->state->enable,
5519 "crtc not enabled\n");
5520 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5521 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5522 "encoder active on the wrong pipe\n");
5523 }
5524 }
5525 }
5526
5527 /* Even simpler default implementation, if there's really no special case to
5528 * consider. */
5529 void intel_connector_dpms(struct drm_connector *connector, int mode)
5530 {
5531 /* All the simple cases only support two dpms states. */
5532 if (mode != DRM_MODE_DPMS_ON)
5533 mode = DRM_MODE_DPMS_OFF;
5534
5535 if (mode == connector->dpms)
5536 return;
5537
5538 connector->dpms = mode;
5539
5540 /* Only need to change hw state when actually enabled */
5541 if (connector->encoder)
5542 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5543
5544 intel_modeset_check_state(connector->dev);
5545 }
5546
5547 /* Simple connector->get_hw_state implementation for encoders that support only
5548 * one connector and no cloning and hence the encoder state determines the state
5549 * of the connector. */
5550 bool intel_connector_get_hw_state(struct intel_connector *connector)
5551 {
5552 enum pipe pipe = 0;
5553 struct intel_encoder *encoder = connector->encoder;
5554
5555 return encoder->get_hw_state(encoder, &pipe);
5556 }
5557
5558 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5559 {
5560 struct intel_crtc *crtc =
5561 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5562
5563 if (crtc->base.state->enable &&
5564 crtc->config->has_pch_encoder)
5565 return crtc->config->fdi_lanes;
5566
5567 return 0;
5568 }
5569
5570 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5571 struct intel_crtc_state *pipe_config)
5572 {
5573 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5574 pipe_name(pipe), pipe_config->fdi_lanes);
5575 if (pipe_config->fdi_lanes > 4) {
5576 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5577 pipe_name(pipe), pipe_config->fdi_lanes);
5578 return false;
5579 }
5580
5581 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5582 if (pipe_config->fdi_lanes > 2) {
5583 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5584 pipe_config->fdi_lanes);
5585 return false;
5586 } else {
5587 return true;
5588 }
5589 }
5590
5591 if (INTEL_INFO(dev)->num_pipes == 2)
5592 return true;
5593
5594 /* Ivybridge 3 pipe is really complicated */
5595 switch (pipe) {
5596 case PIPE_A:
5597 return true;
5598 case PIPE_B:
5599 if (pipe_config->fdi_lanes > 2 &&
5600 pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5601 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5602 pipe_name(pipe), pipe_config->fdi_lanes);
5603 return false;
5604 }
5605 return true;
5606 case PIPE_C:
5607 if (pipe_config->fdi_lanes > 2) {
5608 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5609 pipe_name(pipe), pipe_config->fdi_lanes);
5610 return false;
5611 }
5612 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5613 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5614 return false;
5615 }
5616 return true;
5617 default:
5618 BUG();
5619 }
5620 }
5621
5622 #define RETRY 1
5623 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5624 struct intel_crtc_state *pipe_config)
5625 {
5626 struct drm_device *dev = intel_crtc->base.dev;
5627 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5628 int lane, link_bw, fdi_dotclock;
5629 bool setup_ok, needs_recompute = false;
5630
5631 retry:
5632 /* FDI is a binary signal running at ~2.7GHz, encoding
5633 * each output octet as 10 bits. The actual frequency
5634 * is stored as a divider into a 100MHz clock, and the
5635 * mode pixel clock is stored in units of 1KHz.
5636 * Hence the bw of each lane in terms of the mode signal
5637 * is:
5638 */
5639 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5640
5641 fdi_dotclock = adjusted_mode->crtc_clock;
5642
5643 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5644 pipe_config->pipe_bpp);
5645
5646 pipe_config->fdi_lanes = lane;
5647
5648 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5649 link_bw, &pipe_config->fdi_m_n);
5650
5651 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5652 intel_crtc->pipe, pipe_config);
5653 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5654 pipe_config->pipe_bpp -= 2*3;
5655 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5656 pipe_config->pipe_bpp);
5657 needs_recompute = true;
5658 pipe_config->bw_constrained = true;
5659
5660 goto retry;
5661 }
5662
5663 if (needs_recompute)
5664 return RETRY;
5665
5666 return setup_ok ? 0 : -EINVAL;
5667 }
5668
5669 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5670 struct intel_crtc_state *pipe_config)
5671 {
5672 pipe_config->ips_enabled = i915.enable_ips &&
5673 hsw_crtc_supports_ips(crtc) &&
5674 pipe_config->pipe_bpp <= 24;
5675 }
5676
5677 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5678 struct intel_crtc_state *pipe_config)
5679 {
5680 struct drm_device *dev = crtc->base.dev;
5681 struct drm_i915_private *dev_priv = dev->dev_private;
5682 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5683
5684 /* FIXME should check pixel clock limits on all platforms */
5685 if (INTEL_INFO(dev)->gen < 4) {
5686 int clock_limit =
5687 dev_priv->display.get_display_clock_speed(dev);
5688
5689 /*
5690 * Enable pixel doubling when the dot clock
5691 * is > 90% of the (display) core speed.
5692 *
5693 * GDG double wide on either pipe,
5694 * otherwise pipe A only.
5695 */
5696 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5697 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5698 clock_limit *= 2;
5699 pipe_config->double_wide = true;
5700 }
5701
5702 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5703 return -EINVAL;
5704 }
5705
5706 /*
5707 * Pipe horizontal size must be even in:
5708 * - DVO ganged mode
5709 * - LVDS dual channel mode
5710 * - Double wide pipe
5711 */
5712 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5713 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5714 pipe_config->pipe_src_w &= ~1;
5715
5716 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5717 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5718 */
5719 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5720 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5721 return -EINVAL;
5722
5723 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5724 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5725 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5726 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5727 * for lvds. */
5728 pipe_config->pipe_bpp = 8*3;
5729 }
5730
5731 if (HAS_IPS(dev))
5732 hsw_compute_ips_config(crtc, pipe_config);
5733
5734 if (pipe_config->has_pch_encoder)
5735 return ironlake_fdi_compute_config(crtc, pipe_config);
5736
5737 return 0;
5738 }
5739
5740 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5741 {
5742 struct drm_i915_private *dev_priv = dev->dev_private;
5743 u32 val;
5744 int divider;
5745
5746 if (dev_priv->hpll_freq == 0)
5747 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5748
5749 mutex_lock(&dev_priv->dpio_lock);
5750 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5751 mutex_unlock(&dev_priv->dpio_lock);
5752
5753 divider = val & DISPLAY_FREQUENCY_VALUES;
5754
5755 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5756 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5757 "cdclk change in progress\n");
5758
5759 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5760 }
5761
5762 static int i945_get_display_clock_speed(struct drm_device *dev)
5763 {
5764 return 400000;
5765 }
5766
5767 static int i915_get_display_clock_speed(struct drm_device *dev)
5768 {
5769 return 333000;
5770 }
5771
5772 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5773 {
5774 return 200000;
5775 }
5776
5777 static int pnv_get_display_clock_speed(struct drm_device *dev)
5778 {
5779 u16 gcfgc = 0;
5780
5781 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5782
5783 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5784 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5785 return 267000;
5786 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5787 return 333000;
5788 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5789 return 444000;
5790 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5791 return 200000;
5792 default:
5793 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5794 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5795 return 133000;
5796 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5797 return 167000;
5798 }
5799 }
5800
5801 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5802 {
5803 u16 gcfgc = 0;
5804
5805 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5806
5807 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5808 return 133000;
5809 else {
5810 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5811 case GC_DISPLAY_CLOCK_333_MHZ:
5812 return 333000;
5813 default:
5814 case GC_DISPLAY_CLOCK_190_200_MHZ:
5815 return 190000;
5816 }
5817 }
5818 }
5819
5820 static int i865_get_display_clock_speed(struct drm_device *dev)
5821 {
5822 return 266000;
5823 }
5824
5825 static int i855_get_display_clock_speed(struct drm_device *dev)
5826 {
5827 u16 hpllcc = 0;
5828 /* Assume that the hardware is in the high speed state. This
5829 * should be the default.
5830 */
5831 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5832 case GC_CLOCK_133_200:
5833 case GC_CLOCK_100_200:
5834 return 200000;
5835 case GC_CLOCK_166_250:
5836 return 250000;
5837 case GC_CLOCK_100_133:
5838 return 133000;
5839 }
5840
5841 /* Shouldn't happen */
5842 return 0;
5843 }
5844
5845 static int i830_get_display_clock_speed(struct drm_device *dev)
5846 {
5847 return 133000;
5848 }
5849
5850 static void
5851 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5852 {
5853 while (*num > DATA_LINK_M_N_MASK ||
5854 *den > DATA_LINK_M_N_MASK) {
5855 *num >>= 1;
5856 *den >>= 1;
5857 }
5858 }
5859
5860 static void compute_m_n(unsigned int m, unsigned int n,
5861 uint32_t *ret_m, uint32_t *ret_n)
5862 {
5863 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5864 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5865 intel_reduce_m_n_ratio(ret_m, ret_n);
5866 }
5867
5868 void
5869 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5870 int pixel_clock, int link_clock,
5871 struct intel_link_m_n *m_n)
5872 {
5873 m_n->tu = 64;
5874
5875 compute_m_n(bits_per_pixel * pixel_clock,
5876 link_clock * nlanes * 8,
5877 &m_n->gmch_m, &m_n->gmch_n);
5878
5879 compute_m_n(pixel_clock, link_clock,
5880 &m_n->link_m, &m_n->link_n);
5881 }
5882
5883 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5884 {
5885 if (i915.panel_use_ssc >= 0)
5886 return i915.panel_use_ssc != 0;
5887 return dev_priv->vbt.lvds_use_ssc
5888 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5889 }
5890
5891 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5892 {
5893 struct drm_device *dev = crtc->base.dev;
5894 struct drm_i915_private *dev_priv = dev->dev_private;
5895 int refclk;
5896
5897 if (IS_VALLEYVIEW(dev)) {
5898 refclk = 100000;
5899 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5900 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5901 refclk = dev_priv->vbt.lvds_ssc_freq;
5902 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5903 } else if (!IS_GEN2(dev)) {
5904 refclk = 96000;
5905 } else {
5906 refclk = 48000;
5907 }
5908
5909 return refclk;
5910 }
5911
5912 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5913 {
5914 return (1 << dpll->n) << 16 | dpll->m2;
5915 }
5916
5917 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5918 {
5919 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5920 }
5921
5922 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5923 struct intel_crtc_state *crtc_state,
5924 intel_clock_t *reduced_clock)
5925 {
5926 struct drm_device *dev = crtc->base.dev;
5927 u32 fp, fp2 = 0;
5928
5929 if (IS_PINEVIEW(dev)) {
5930 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5931 if (reduced_clock)
5932 fp2 = pnv_dpll_compute_fp(reduced_clock);
5933 } else {
5934 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5935 if (reduced_clock)
5936 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5937 }
5938
5939 crtc_state->dpll_hw_state.fp0 = fp;
5940
5941 crtc->lowfreq_avail = false;
5942 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5943 reduced_clock && i915.powersave) {
5944 crtc_state->dpll_hw_state.fp1 = fp2;
5945 crtc->lowfreq_avail = true;
5946 } else {
5947 crtc_state->dpll_hw_state.fp1 = fp;
5948 }
5949 }
5950
5951 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5952 pipe)
5953 {
5954 u32 reg_val;
5955
5956 /*
5957 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5958 * and set it to a reasonable value instead.
5959 */
5960 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5961 reg_val &= 0xffffff00;
5962 reg_val |= 0x00000030;
5963 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5964
5965 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5966 reg_val &= 0x8cffffff;
5967 reg_val = 0x8c000000;
5968 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5969
5970 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5971 reg_val &= 0xffffff00;
5972 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5973
5974 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5975 reg_val &= 0x00ffffff;
5976 reg_val |= 0xb0000000;
5977 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5978 }
5979
5980 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5981 struct intel_link_m_n *m_n)
5982 {
5983 struct drm_device *dev = crtc->base.dev;
5984 struct drm_i915_private *dev_priv = dev->dev_private;
5985 int pipe = crtc->pipe;
5986
5987 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5988 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5989 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5990 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5991 }
5992
5993 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5994 struct intel_link_m_n *m_n,
5995 struct intel_link_m_n *m2_n2)
5996 {
5997 struct drm_device *dev = crtc->base.dev;
5998 struct drm_i915_private *dev_priv = dev->dev_private;
5999 int pipe = crtc->pipe;
6000 enum transcoder transcoder = crtc->config->cpu_transcoder;
6001
6002 if (INTEL_INFO(dev)->gen >= 5) {
6003 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6004 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6005 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6006 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6007 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6008 * for gen < 8) and if DRRS is supported (to make sure the
6009 * registers are not unnecessarily accessed).
6010 */
6011 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6012 crtc->config->has_drrs) {
6013 I915_WRITE(PIPE_DATA_M2(transcoder),
6014 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6015 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6016 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6017 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6018 }
6019 } else {
6020 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6021 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6022 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6023 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6024 }
6025 }
6026
6027 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6028 {
6029 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6030
6031 if (m_n == M1_N1) {
6032 dp_m_n = &crtc->config->dp_m_n;
6033 dp_m2_n2 = &crtc->config->dp_m2_n2;
6034 } else if (m_n == M2_N2) {
6035
6036 /*
6037 * M2_N2 registers are not supported. Hence m2_n2 divider value
6038 * needs to be programmed into M1_N1.
6039 */
6040 dp_m_n = &crtc->config->dp_m2_n2;
6041 } else {
6042 DRM_ERROR("Unsupported divider value\n");
6043 return;
6044 }
6045
6046 if (crtc->config->has_pch_encoder)
6047 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6048 else
6049 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6050 }
6051
6052 static void vlv_update_pll(struct intel_crtc *crtc,
6053 struct intel_crtc_state *pipe_config)
6054 {
6055 u32 dpll, dpll_md;
6056
6057 /*
6058 * Enable DPIO clock input. We should never disable the reference
6059 * clock for pipe B, since VGA hotplug / manual detection depends
6060 * on it.
6061 */
6062 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6063 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6064 /* We should never disable this, set it here for state tracking */
6065 if (crtc->pipe == PIPE_B)
6066 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6067 dpll |= DPLL_VCO_ENABLE;
6068 pipe_config->dpll_hw_state.dpll = dpll;
6069
6070 dpll_md = (pipe_config->pixel_multiplier - 1)
6071 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6072 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6073 }
6074
6075 static void vlv_prepare_pll(struct intel_crtc *crtc,
6076 const struct intel_crtc_state *pipe_config)
6077 {
6078 struct drm_device *dev = crtc->base.dev;
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6080 int pipe = crtc->pipe;
6081 u32 mdiv;
6082 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6083 u32 coreclk, reg_val;
6084
6085 mutex_lock(&dev_priv->dpio_lock);
6086
6087 bestn = pipe_config->dpll.n;
6088 bestm1 = pipe_config->dpll.m1;
6089 bestm2 = pipe_config->dpll.m2;
6090 bestp1 = pipe_config->dpll.p1;
6091 bestp2 = pipe_config->dpll.p2;
6092
6093 /* See eDP HDMI DPIO driver vbios notes doc */
6094
6095 /* PLL B needs special handling */
6096 if (pipe == PIPE_B)
6097 vlv_pllb_recal_opamp(dev_priv, pipe);
6098
6099 /* Set up Tx target for periodic Rcomp update */
6100 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6101
6102 /* Disable target IRef on PLL */
6103 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6104 reg_val &= 0x00ffffff;
6105 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6106
6107 /* Disable fast lock */
6108 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6109
6110 /* Set idtafcrecal before PLL is enabled */
6111 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6112 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6113 mdiv |= ((bestn << DPIO_N_SHIFT));
6114 mdiv |= (1 << DPIO_K_SHIFT);
6115
6116 /*
6117 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6118 * but we don't support that).
6119 * Note: don't use the DAC post divider as it seems unstable.
6120 */
6121 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6122 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6123
6124 mdiv |= DPIO_ENABLE_CALIBRATION;
6125 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6126
6127 /* Set HBR and RBR LPF coefficients */
6128 if (pipe_config->port_clock == 162000 ||
6129 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6130 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6131 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6132 0x009f0003);
6133 else
6134 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6135 0x00d0000f);
6136
6137 if (pipe_config->has_dp_encoder) {
6138 /* Use SSC source */
6139 if (pipe == PIPE_A)
6140 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6141 0x0df40000);
6142 else
6143 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6144 0x0df70000);
6145 } else { /* HDMI or VGA */
6146 /* Use bend source */
6147 if (pipe == PIPE_A)
6148 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6149 0x0df70000);
6150 else
6151 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6152 0x0df40000);
6153 }
6154
6155 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6156 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6157 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6158 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6159 coreclk |= 0x01000000;
6160 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6161
6162 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6163 mutex_unlock(&dev_priv->dpio_lock);
6164 }
6165
6166 static void chv_update_pll(struct intel_crtc *crtc,
6167 struct intel_crtc_state *pipe_config)
6168 {
6169 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6170 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6171 DPLL_VCO_ENABLE;
6172 if (crtc->pipe != PIPE_A)
6173 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6174
6175 pipe_config->dpll_hw_state.dpll_md =
6176 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6177 }
6178
6179 static void chv_prepare_pll(struct intel_crtc *crtc,
6180 const struct intel_crtc_state *pipe_config)
6181 {
6182 struct drm_device *dev = crtc->base.dev;
6183 struct drm_i915_private *dev_priv = dev->dev_private;
6184 int pipe = crtc->pipe;
6185 int dpll_reg = DPLL(crtc->pipe);
6186 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6187 u32 loopfilter, tribuf_calcntr;
6188 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6189 u32 dpio_val;
6190 int vco;
6191
6192 bestn = pipe_config->dpll.n;
6193 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6194 bestm1 = pipe_config->dpll.m1;
6195 bestm2 = pipe_config->dpll.m2 >> 22;
6196 bestp1 = pipe_config->dpll.p1;
6197 bestp2 = pipe_config->dpll.p2;
6198 vco = pipe_config->dpll.vco;
6199 dpio_val = 0;
6200 loopfilter = 0;
6201
6202 /*
6203 * Enable Refclk and SSC
6204 */
6205 I915_WRITE(dpll_reg,
6206 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6207
6208 mutex_lock(&dev_priv->dpio_lock);
6209
6210 /* p1 and p2 divider */
6211 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6212 5 << DPIO_CHV_S1_DIV_SHIFT |
6213 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6214 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6215 1 << DPIO_CHV_K_DIV_SHIFT);
6216
6217 /* Feedback post-divider - m2 */
6218 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6219
6220 /* Feedback refclk divider - n and m1 */
6221 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6222 DPIO_CHV_M1_DIV_BY_2 |
6223 1 << DPIO_CHV_N_DIV_SHIFT);
6224
6225 /* M2 fraction division */
6226 if (bestm2_frac)
6227 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6228
6229 /* M2 fraction division enable */
6230 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6231 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6232 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6233 if (bestm2_frac)
6234 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6235 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6236
6237 /* Program digital lock detect threshold */
6238 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6239 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6240 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6241 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6242 if (!bestm2_frac)
6243 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6244 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6245
6246 /* Loop filter */
6247 if (vco == 5400000) {
6248 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6249 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6250 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6251 tribuf_calcntr = 0x9;
6252 } else if (vco <= 6200000) {
6253 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6254 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6255 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6256 tribuf_calcntr = 0x9;
6257 } else if (vco <= 6480000) {
6258 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6259 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6260 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6261 tribuf_calcntr = 0x8;
6262 } else {
6263 /* Not supported. Apply the same limits as in the max case */
6264 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6265 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6266 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6267 tribuf_calcntr = 0;
6268 }
6269 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6270
6271 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6272 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6273 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6274 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6275
6276 /* AFC Recal */
6277 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6278 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6279 DPIO_AFC_RECAL);
6280
6281 mutex_unlock(&dev_priv->dpio_lock);
6282 }
6283
6284 /**
6285 * vlv_force_pll_on - forcibly enable just the PLL
6286 * @dev_priv: i915 private structure
6287 * @pipe: pipe PLL to enable
6288 * @dpll: PLL configuration
6289 *
6290 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6291 * in cases where we need the PLL enabled even when @pipe is not going to
6292 * be enabled.
6293 */
6294 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6295 const struct dpll *dpll)
6296 {
6297 struct intel_crtc *crtc =
6298 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6299 struct intel_crtc_state pipe_config = {
6300 .pixel_multiplier = 1,
6301 .dpll = *dpll,
6302 };
6303
6304 if (IS_CHERRYVIEW(dev)) {
6305 chv_update_pll(crtc, &pipe_config);
6306 chv_prepare_pll(crtc, &pipe_config);
6307 chv_enable_pll(crtc, &pipe_config);
6308 } else {
6309 vlv_update_pll(crtc, &pipe_config);
6310 vlv_prepare_pll(crtc, &pipe_config);
6311 vlv_enable_pll(crtc, &pipe_config);
6312 }
6313 }
6314
6315 /**
6316 * vlv_force_pll_off - forcibly disable just the PLL
6317 * @dev_priv: i915 private structure
6318 * @pipe: pipe PLL to disable
6319 *
6320 * Disable the PLL for @pipe. To be used in cases where we need
6321 * the PLL enabled even when @pipe is not going to be enabled.
6322 */
6323 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6324 {
6325 if (IS_CHERRYVIEW(dev))
6326 chv_disable_pll(to_i915(dev), pipe);
6327 else
6328 vlv_disable_pll(to_i915(dev), pipe);
6329 }
6330
6331 static void i9xx_update_pll(struct intel_crtc *crtc,
6332 struct intel_crtc_state *crtc_state,
6333 intel_clock_t *reduced_clock,
6334 int num_connectors)
6335 {
6336 struct drm_device *dev = crtc->base.dev;
6337 struct drm_i915_private *dev_priv = dev->dev_private;
6338 u32 dpll;
6339 bool is_sdvo;
6340 struct dpll *clock = &crtc_state->dpll;
6341
6342 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6343
6344 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6345 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6346
6347 dpll = DPLL_VGA_MODE_DIS;
6348
6349 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6350 dpll |= DPLLB_MODE_LVDS;
6351 else
6352 dpll |= DPLLB_MODE_DAC_SERIAL;
6353
6354 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6355 dpll |= (crtc_state->pixel_multiplier - 1)
6356 << SDVO_MULTIPLIER_SHIFT_HIRES;
6357 }
6358
6359 if (is_sdvo)
6360 dpll |= DPLL_SDVO_HIGH_SPEED;
6361
6362 if (crtc_state->has_dp_encoder)
6363 dpll |= DPLL_SDVO_HIGH_SPEED;
6364
6365 /* compute bitmask from p1 value */
6366 if (IS_PINEVIEW(dev))
6367 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6368 else {
6369 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6370 if (IS_G4X(dev) && reduced_clock)
6371 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6372 }
6373 switch (clock->p2) {
6374 case 5:
6375 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6376 break;
6377 case 7:
6378 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6379 break;
6380 case 10:
6381 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6382 break;
6383 case 14:
6384 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6385 break;
6386 }
6387 if (INTEL_INFO(dev)->gen >= 4)
6388 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6389
6390 if (crtc_state->sdvo_tv_clock)
6391 dpll |= PLL_REF_INPUT_TVCLKINBC;
6392 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6393 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6394 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6395 else
6396 dpll |= PLL_REF_INPUT_DREFCLK;
6397
6398 dpll |= DPLL_VCO_ENABLE;
6399 crtc_state->dpll_hw_state.dpll = dpll;
6400
6401 if (INTEL_INFO(dev)->gen >= 4) {
6402 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6403 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6404 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6405 }
6406 }
6407
6408 static void i8xx_update_pll(struct intel_crtc *crtc,
6409 struct intel_crtc_state *crtc_state,
6410 intel_clock_t *reduced_clock,
6411 int num_connectors)
6412 {
6413 struct drm_device *dev = crtc->base.dev;
6414 struct drm_i915_private *dev_priv = dev->dev_private;
6415 u32 dpll;
6416 struct dpll *clock = &crtc_state->dpll;
6417
6418 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6419
6420 dpll = DPLL_VGA_MODE_DIS;
6421
6422 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6423 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6424 } else {
6425 if (clock->p1 == 2)
6426 dpll |= PLL_P1_DIVIDE_BY_TWO;
6427 else
6428 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6429 if (clock->p2 == 4)
6430 dpll |= PLL_P2_DIVIDE_BY_4;
6431 }
6432
6433 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6434 dpll |= DPLL_DVO_2X_MODE;
6435
6436 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6437 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6438 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6439 else
6440 dpll |= PLL_REF_INPUT_DREFCLK;
6441
6442 dpll |= DPLL_VCO_ENABLE;
6443 crtc_state->dpll_hw_state.dpll = dpll;
6444 }
6445
6446 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6447 {
6448 struct drm_device *dev = intel_crtc->base.dev;
6449 struct drm_i915_private *dev_priv = dev->dev_private;
6450 enum pipe pipe = intel_crtc->pipe;
6451 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6452 struct drm_display_mode *adjusted_mode =
6453 &intel_crtc->config->base.adjusted_mode;
6454 uint32_t crtc_vtotal, crtc_vblank_end;
6455 int vsyncshift = 0;
6456
6457 /* We need to be careful not to changed the adjusted mode, for otherwise
6458 * the hw state checker will get angry at the mismatch. */
6459 crtc_vtotal = adjusted_mode->crtc_vtotal;
6460 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6461
6462 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6463 /* the chip adds 2 halflines automatically */
6464 crtc_vtotal -= 1;
6465 crtc_vblank_end -= 1;
6466
6467 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6468 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6469 else
6470 vsyncshift = adjusted_mode->crtc_hsync_start -
6471 adjusted_mode->crtc_htotal / 2;
6472 if (vsyncshift < 0)
6473 vsyncshift += adjusted_mode->crtc_htotal;
6474 }
6475
6476 if (INTEL_INFO(dev)->gen > 3)
6477 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6478
6479 I915_WRITE(HTOTAL(cpu_transcoder),
6480 (adjusted_mode->crtc_hdisplay - 1) |
6481 ((adjusted_mode->crtc_htotal - 1) << 16));
6482 I915_WRITE(HBLANK(cpu_transcoder),
6483 (adjusted_mode->crtc_hblank_start - 1) |
6484 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6485 I915_WRITE(HSYNC(cpu_transcoder),
6486 (adjusted_mode->crtc_hsync_start - 1) |
6487 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6488
6489 I915_WRITE(VTOTAL(cpu_transcoder),
6490 (adjusted_mode->crtc_vdisplay - 1) |
6491 ((crtc_vtotal - 1) << 16));
6492 I915_WRITE(VBLANK(cpu_transcoder),
6493 (adjusted_mode->crtc_vblank_start - 1) |
6494 ((crtc_vblank_end - 1) << 16));
6495 I915_WRITE(VSYNC(cpu_transcoder),
6496 (adjusted_mode->crtc_vsync_start - 1) |
6497 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6498
6499 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6500 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6501 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6502 * bits. */
6503 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6504 (pipe == PIPE_B || pipe == PIPE_C))
6505 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6506
6507 /* pipesrc controls the size that is scaled from, which should
6508 * always be the user's requested size.
6509 */
6510 I915_WRITE(PIPESRC(pipe),
6511 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6512 (intel_crtc->config->pipe_src_h - 1));
6513 }
6514
6515 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6516 struct intel_crtc_state *pipe_config)
6517 {
6518 struct drm_device *dev = crtc->base.dev;
6519 struct drm_i915_private *dev_priv = dev->dev_private;
6520 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6521 uint32_t tmp;
6522
6523 tmp = I915_READ(HTOTAL(cpu_transcoder));
6524 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6525 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6526 tmp = I915_READ(HBLANK(cpu_transcoder));
6527 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6528 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6529 tmp = I915_READ(HSYNC(cpu_transcoder));
6530 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6531 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6532
6533 tmp = I915_READ(VTOTAL(cpu_transcoder));
6534 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6535 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6536 tmp = I915_READ(VBLANK(cpu_transcoder));
6537 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6538 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6539 tmp = I915_READ(VSYNC(cpu_transcoder));
6540 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6541 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6542
6543 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6544 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6545 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6546 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6547 }
6548
6549 tmp = I915_READ(PIPESRC(crtc->pipe));
6550 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6551 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6552
6553 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6554 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6555 }
6556
6557 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6558 struct intel_crtc_state *pipe_config)
6559 {
6560 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6561 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6562 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6563 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6564
6565 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6566 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6567 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6568 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6569
6570 mode->flags = pipe_config->base.adjusted_mode.flags;
6571
6572 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6573 mode->flags |= pipe_config->base.adjusted_mode.flags;
6574 }
6575
6576 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6577 {
6578 struct drm_device *dev = intel_crtc->base.dev;
6579 struct drm_i915_private *dev_priv = dev->dev_private;
6580 uint32_t pipeconf;
6581
6582 pipeconf = 0;
6583
6584 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6585 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6586 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6587
6588 if (intel_crtc->config->double_wide)
6589 pipeconf |= PIPECONF_DOUBLE_WIDE;
6590
6591 /* only g4x and later have fancy bpc/dither controls */
6592 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6593 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6594 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6595 pipeconf |= PIPECONF_DITHER_EN |
6596 PIPECONF_DITHER_TYPE_SP;
6597
6598 switch (intel_crtc->config->pipe_bpp) {
6599 case 18:
6600 pipeconf |= PIPECONF_6BPC;
6601 break;
6602 case 24:
6603 pipeconf |= PIPECONF_8BPC;
6604 break;
6605 case 30:
6606 pipeconf |= PIPECONF_10BPC;
6607 break;
6608 default:
6609 /* Case prevented by intel_choose_pipe_bpp_dither. */
6610 BUG();
6611 }
6612 }
6613
6614 if (HAS_PIPE_CXSR(dev)) {
6615 if (intel_crtc->lowfreq_avail) {
6616 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6617 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6618 } else {
6619 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6620 }
6621 }
6622
6623 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6624 if (INTEL_INFO(dev)->gen < 4 ||
6625 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6626 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6627 else
6628 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6629 } else
6630 pipeconf |= PIPECONF_PROGRESSIVE;
6631
6632 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6633 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6634
6635 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6636 POSTING_READ(PIPECONF(intel_crtc->pipe));
6637 }
6638
6639 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6640 struct intel_crtc_state *crtc_state)
6641 {
6642 struct drm_device *dev = crtc->base.dev;
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644 int refclk, num_connectors = 0;
6645 intel_clock_t clock, reduced_clock;
6646 bool ok, has_reduced_clock = false;
6647 bool is_lvds = false, is_dsi = false;
6648 struct intel_encoder *encoder;
6649 const intel_limit_t *limit;
6650
6651 for_each_intel_encoder(dev, encoder) {
6652 if (encoder->new_crtc != crtc)
6653 continue;
6654
6655 switch (encoder->type) {
6656 case INTEL_OUTPUT_LVDS:
6657 is_lvds = true;
6658 break;
6659 case INTEL_OUTPUT_DSI:
6660 is_dsi = true;
6661 break;
6662 default:
6663 break;
6664 }
6665
6666 num_connectors++;
6667 }
6668
6669 if (is_dsi)
6670 return 0;
6671
6672 if (!crtc_state->clock_set) {
6673 refclk = i9xx_get_refclk(crtc, num_connectors);
6674
6675 /*
6676 * Returns a set of divisors for the desired target clock with
6677 * the given refclk, or FALSE. The returned values represent
6678 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6679 * 2) / p1 / p2.
6680 */
6681 limit = intel_limit(crtc, refclk);
6682 ok = dev_priv->display.find_dpll(limit, crtc,
6683 crtc_state->port_clock,
6684 refclk, NULL, &clock);
6685 if (!ok) {
6686 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6687 return -EINVAL;
6688 }
6689
6690 if (is_lvds && dev_priv->lvds_downclock_avail) {
6691 /*
6692 * Ensure we match the reduced clock's P to the target
6693 * clock. If the clocks don't match, we can't switch
6694 * the display clock by using the FP0/FP1. In such case
6695 * we will disable the LVDS downclock feature.
6696 */
6697 has_reduced_clock =
6698 dev_priv->display.find_dpll(limit, crtc,
6699 dev_priv->lvds_downclock,
6700 refclk, &clock,
6701 &reduced_clock);
6702 }
6703 /* Compat-code for transition, will disappear. */
6704 crtc_state->dpll.n = clock.n;
6705 crtc_state->dpll.m1 = clock.m1;
6706 crtc_state->dpll.m2 = clock.m2;
6707 crtc_state->dpll.p1 = clock.p1;
6708 crtc_state->dpll.p2 = clock.p2;
6709 }
6710
6711 if (IS_GEN2(dev)) {
6712 i8xx_update_pll(crtc, crtc_state,
6713 has_reduced_clock ? &reduced_clock : NULL,
6714 num_connectors);
6715 } else if (IS_CHERRYVIEW(dev)) {
6716 chv_update_pll(crtc, crtc_state);
6717 } else if (IS_VALLEYVIEW(dev)) {
6718 vlv_update_pll(crtc, crtc_state);
6719 } else {
6720 i9xx_update_pll(crtc, crtc_state,
6721 has_reduced_clock ? &reduced_clock : NULL,
6722 num_connectors);
6723 }
6724
6725 return 0;
6726 }
6727
6728 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6729 struct intel_crtc_state *pipe_config)
6730 {
6731 struct drm_device *dev = crtc->base.dev;
6732 struct drm_i915_private *dev_priv = dev->dev_private;
6733 uint32_t tmp;
6734
6735 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6736 return;
6737
6738 tmp = I915_READ(PFIT_CONTROL);
6739 if (!(tmp & PFIT_ENABLE))
6740 return;
6741
6742 /* Check whether the pfit is attached to our pipe. */
6743 if (INTEL_INFO(dev)->gen < 4) {
6744 if (crtc->pipe != PIPE_B)
6745 return;
6746 } else {
6747 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6748 return;
6749 }
6750
6751 pipe_config->gmch_pfit.control = tmp;
6752 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6753 if (INTEL_INFO(dev)->gen < 5)
6754 pipe_config->gmch_pfit.lvds_border_bits =
6755 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6756 }
6757
6758 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6759 struct intel_crtc_state *pipe_config)
6760 {
6761 struct drm_device *dev = crtc->base.dev;
6762 struct drm_i915_private *dev_priv = dev->dev_private;
6763 int pipe = pipe_config->cpu_transcoder;
6764 intel_clock_t clock;
6765 u32 mdiv;
6766 int refclk = 100000;
6767
6768 /* In case of MIPI DPLL will not even be used */
6769 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6770 return;
6771
6772 mutex_lock(&dev_priv->dpio_lock);
6773 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6774 mutex_unlock(&dev_priv->dpio_lock);
6775
6776 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6777 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6778 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6779 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6780 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6781
6782 vlv_clock(refclk, &clock);
6783
6784 /* clock.dot is the fast clock */
6785 pipe_config->port_clock = clock.dot / 5;
6786 }
6787
6788 static void
6789 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6790 struct intel_initial_plane_config *plane_config)
6791 {
6792 struct drm_device *dev = crtc->base.dev;
6793 struct drm_i915_private *dev_priv = dev->dev_private;
6794 u32 val, base, offset;
6795 int pipe = crtc->pipe, plane = crtc->plane;
6796 int fourcc, pixel_format;
6797 int aligned_height;
6798 struct drm_framebuffer *fb;
6799 struct intel_framebuffer *intel_fb;
6800
6801 val = I915_READ(DSPCNTR(plane));
6802 if (!(val & DISPLAY_PLANE_ENABLE))
6803 return;
6804
6805 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6806 if (!intel_fb) {
6807 DRM_DEBUG_KMS("failed to alloc fb\n");
6808 return;
6809 }
6810
6811 fb = &intel_fb->base;
6812
6813 if (INTEL_INFO(dev)->gen >= 4) {
6814 if (val & DISPPLANE_TILED) {
6815 plane_config->tiling = I915_TILING_X;
6816 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6817 }
6818 }
6819
6820 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6821 fourcc = i9xx_format_to_fourcc(pixel_format);
6822 fb->pixel_format = fourcc;
6823 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6824
6825 if (INTEL_INFO(dev)->gen >= 4) {
6826 if (plane_config->tiling)
6827 offset = I915_READ(DSPTILEOFF(plane));
6828 else
6829 offset = I915_READ(DSPLINOFF(plane));
6830 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6831 } else {
6832 base = I915_READ(DSPADDR(plane));
6833 }
6834 plane_config->base = base;
6835
6836 val = I915_READ(PIPESRC(pipe));
6837 fb->width = ((val >> 16) & 0xfff) + 1;
6838 fb->height = ((val >> 0) & 0xfff) + 1;
6839
6840 val = I915_READ(DSPSTRIDE(pipe));
6841 fb->pitches[0] = val & 0xffffffc0;
6842
6843 aligned_height = intel_fb_align_height(dev, fb->height,
6844 fb->pixel_format,
6845 fb->modifier[0]);
6846
6847 plane_config->size = fb->pitches[0] * aligned_height;
6848
6849 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6850 pipe_name(pipe), plane, fb->width, fb->height,
6851 fb->bits_per_pixel, base, fb->pitches[0],
6852 plane_config->size);
6853
6854 plane_config->fb = intel_fb;
6855 }
6856
6857 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6858 struct intel_crtc_state *pipe_config)
6859 {
6860 struct drm_device *dev = crtc->base.dev;
6861 struct drm_i915_private *dev_priv = dev->dev_private;
6862 int pipe = pipe_config->cpu_transcoder;
6863 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6864 intel_clock_t clock;
6865 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6866 int refclk = 100000;
6867
6868 mutex_lock(&dev_priv->dpio_lock);
6869 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6870 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6871 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6872 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6873 mutex_unlock(&dev_priv->dpio_lock);
6874
6875 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6876 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6877 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6878 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6879 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6880
6881 chv_clock(refclk, &clock);
6882
6883 /* clock.dot is the fast clock */
6884 pipe_config->port_clock = clock.dot / 5;
6885 }
6886
6887 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6888 struct intel_crtc_state *pipe_config)
6889 {
6890 struct drm_device *dev = crtc->base.dev;
6891 struct drm_i915_private *dev_priv = dev->dev_private;
6892 uint32_t tmp;
6893
6894 if (!intel_display_power_is_enabled(dev_priv,
6895 POWER_DOMAIN_PIPE(crtc->pipe)))
6896 return false;
6897
6898 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6899 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6900
6901 tmp = I915_READ(PIPECONF(crtc->pipe));
6902 if (!(tmp & PIPECONF_ENABLE))
6903 return false;
6904
6905 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6906 switch (tmp & PIPECONF_BPC_MASK) {
6907 case PIPECONF_6BPC:
6908 pipe_config->pipe_bpp = 18;
6909 break;
6910 case PIPECONF_8BPC:
6911 pipe_config->pipe_bpp = 24;
6912 break;
6913 case PIPECONF_10BPC:
6914 pipe_config->pipe_bpp = 30;
6915 break;
6916 default:
6917 break;
6918 }
6919 }
6920
6921 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6922 pipe_config->limited_color_range = true;
6923
6924 if (INTEL_INFO(dev)->gen < 4)
6925 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6926
6927 intel_get_pipe_timings(crtc, pipe_config);
6928
6929 i9xx_get_pfit_config(crtc, pipe_config);
6930
6931 if (INTEL_INFO(dev)->gen >= 4) {
6932 tmp = I915_READ(DPLL_MD(crtc->pipe));
6933 pipe_config->pixel_multiplier =
6934 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6935 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6936 pipe_config->dpll_hw_state.dpll_md = tmp;
6937 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6938 tmp = I915_READ(DPLL(crtc->pipe));
6939 pipe_config->pixel_multiplier =
6940 ((tmp & SDVO_MULTIPLIER_MASK)
6941 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6942 } else {
6943 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6944 * port and will be fixed up in the encoder->get_config
6945 * function. */
6946 pipe_config->pixel_multiplier = 1;
6947 }
6948 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6949 if (!IS_VALLEYVIEW(dev)) {
6950 /*
6951 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6952 * on 830. Filter it out here so that we don't
6953 * report errors due to that.
6954 */
6955 if (IS_I830(dev))
6956 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6957
6958 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6959 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6960 } else {
6961 /* Mask out read-only status bits. */
6962 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6963 DPLL_PORTC_READY_MASK |
6964 DPLL_PORTB_READY_MASK);
6965 }
6966
6967 if (IS_CHERRYVIEW(dev))
6968 chv_crtc_clock_get(crtc, pipe_config);
6969 else if (IS_VALLEYVIEW(dev))
6970 vlv_crtc_clock_get(crtc, pipe_config);
6971 else
6972 i9xx_crtc_clock_get(crtc, pipe_config);
6973
6974 return true;
6975 }
6976
6977 static void ironlake_init_pch_refclk(struct drm_device *dev)
6978 {
6979 struct drm_i915_private *dev_priv = dev->dev_private;
6980 struct intel_encoder *encoder;
6981 u32 val, final;
6982 bool has_lvds = false;
6983 bool has_cpu_edp = false;
6984 bool has_panel = false;
6985 bool has_ck505 = false;
6986 bool can_ssc = false;
6987
6988 /* We need to take the global config into account */
6989 for_each_intel_encoder(dev, encoder) {
6990 switch (encoder->type) {
6991 case INTEL_OUTPUT_LVDS:
6992 has_panel = true;
6993 has_lvds = true;
6994 break;
6995 case INTEL_OUTPUT_EDP:
6996 has_panel = true;
6997 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6998 has_cpu_edp = true;
6999 break;
7000 default:
7001 break;
7002 }
7003 }
7004
7005 if (HAS_PCH_IBX(dev)) {
7006 has_ck505 = dev_priv->vbt.display_clock_mode;
7007 can_ssc = has_ck505;
7008 } else {
7009 has_ck505 = false;
7010 can_ssc = true;
7011 }
7012
7013 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7014 has_panel, has_lvds, has_ck505);
7015
7016 /* Ironlake: try to setup display ref clock before DPLL
7017 * enabling. This is only under driver's control after
7018 * PCH B stepping, previous chipset stepping should be
7019 * ignoring this setting.
7020 */
7021 val = I915_READ(PCH_DREF_CONTROL);
7022
7023 /* As we must carefully and slowly disable/enable each source in turn,
7024 * compute the final state we want first and check if we need to
7025 * make any changes at all.
7026 */
7027 final = val;
7028 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7029 if (has_ck505)
7030 final |= DREF_NONSPREAD_CK505_ENABLE;
7031 else
7032 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7033
7034 final &= ~DREF_SSC_SOURCE_MASK;
7035 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7036 final &= ~DREF_SSC1_ENABLE;
7037
7038 if (has_panel) {
7039 final |= DREF_SSC_SOURCE_ENABLE;
7040
7041 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7042 final |= DREF_SSC1_ENABLE;
7043
7044 if (has_cpu_edp) {
7045 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7046 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7047 else
7048 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7049 } else
7050 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7051 } else {
7052 final |= DREF_SSC_SOURCE_DISABLE;
7053 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7054 }
7055
7056 if (final == val)
7057 return;
7058
7059 /* Always enable nonspread source */
7060 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7061
7062 if (has_ck505)
7063 val |= DREF_NONSPREAD_CK505_ENABLE;
7064 else
7065 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7066
7067 if (has_panel) {
7068 val &= ~DREF_SSC_SOURCE_MASK;
7069 val |= DREF_SSC_SOURCE_ENABLE;
7070
7071 /* SSC must be turned on before enabling the CPU output */
7072 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7073 DRM_DEBUG_KMS("Using SSC on panel\n");
7074 val |= DREF_SSC1_ENABLE;
7075 } else
7076 val &= ~DREF_SSC1_ENABLE;
7077
7078 /* Get SSC going before enabling the outputs */
7079 I915_WRITE(PCH_DREF_CONTROL, val);
7080 POSTING_READ(PCH_DREF_CONTROL);
7081 udelay(200);
7082
7083 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7084
7085 /* Enable CPU source on CPU attached eDP */
7086 if (has_cpu_edp) {
7087 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7088 DRM_DEBUG_KMS("Using SSC on eDP\n");
7089 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7090 } else
7091 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7092 } else
7093 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7094
7095 I915_WRITE(PCH_DREF_CONTROL, val);
7096 POSTING_READ(PCH_DREF_CONTROL);
7097 udelay(200);
7098 } else {
7099 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7100
7101 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7102
7103 /* Turn off CPU output */
7104 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7105
7106 I915_WRITE(PCH_DREF_CONTROL, val);
7107 POSTING_READ(PCH_DREF_CONTROL);
7108 udelay(200);
7109
7110 /* Turn off the SSC source */
7111 val &= ~DREF_SSC_SOURCE_MASK;
7112 val |= DREF_SSC_SOURCE_DISABLE;
7113
7114 /* Turn off SSC1 */
7115 val &= ~DREF_SSC1_ENABLE;
7116
7117 I915_WRITE(PCH_DREF_CONTROL, val);
7118 POSTING_READ(PCH_DREF_CONTROL);
7119 udelay(200);
7120 }
7121
7122 BUG_ON(val != final);
7123 }
7124
7125 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7126 {
7127 uint32_t tmp;
7128
7129 tmp = I915_READ(SOUTH_CHICKEN2);
7130 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7131 I915_WRITE(SOUTH_CHICKEN2, tmp);
7132
7133 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7134 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7135 DRM_ERROR("FDI mPHY reset assert timeout\n");
7136
7137 tmp = I915_READ(SOUTH_CHICKEN2);
7138 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7139 I915_WRITE(SOUTH_CHICKEN2, tmp);
7140
7141 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7142 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7143 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7144 }
7145
7146 /* WaMPhyProgramming:hsw */
7147 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7148 {
7149 uint32_t tmp;
7150
7151 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7152 tmp &= ~(0xFF << 24);
7153 tmp |= (0x12 << 24);
7154 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7155
7156 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7157 tmp |= (1 << 11);
7158 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7159
7160 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7161 tmp |= (1 << 11);
7162 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7163
7164 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7165 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7166 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7167
7168 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7169 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7170 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7171
7172 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7173 tmp &= ~(7 << 13);
7174 tmp |= (5 << 13);
7175 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7176
7177 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7178 tmp &= ~(7 << 13);
7179 tmp |= (5 << 13);
7180 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7181
7182 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7183 tmp &= ~0xFF;
7184 tmp |= 0x1C;
7185 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7186
7187 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7188 tmp &= ~0xFF;
7189 tmp |= 0x1C;
7190 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7191
7192 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7193 tmp &= ~(0xFF << 16);
7194 tmp |= (0x1C << 16);
7195 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7196
7197 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7198 tmp &= ~(0xFF << 16);
7199 tmp |= (0x1C << 16);
7200 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7201
7202 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7203 tmp |= (1 << 27);
7204 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7205
7206 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7207 tmp |= (1 << 27);
7208 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7209
7210 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7211 tmp &= ~(0xF << 28);
7212 tmp |= (4 << 28);
7213 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7214
7215 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7216 tmp &= ~(0xF << 28);
7217 tmp |= (4 << 28);
7218 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7219 }
7220
7221 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7222 * Programming" based on the parameters passed:
7223 * - Sequence to enable CLKOUT_DP
7224 * - Sequence to enable CLKOUT_DP without spread
7225 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7226 */
7227 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7228 bool with_fdi)
7229 {
7230 struct drm_i915_private *dev_priv = dev->dev_private;
7231 uint32_t reg, tmp;
7232
7233 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7234 with_spread = true;
7235 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7236 with_fdi, "LP PCH doesn't have FDI\n"))
7237 with_fdi = false;
7238
7239 mutex_lock(&dev_priv->dpio_lock);
7240
7241 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7242 tmp &= ~SBI_SSCCTL_DISABLE;
7243 tmp |= SBI_SSCCTL_PATHALT;
7244 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7245
7246 udelay(24);
7247
7248 if (with_spread) {
7249 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7250 tmp &= ~SBI_SSCCTL_PATHALT;
7251 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7252
7253 if (with_fdi) {
7254 lpt_reset_fdi_mphy(dev_priv);
7255 lpt_program_fdi_mphy(dev_priv);
7256 }
7257 }
7258
7259 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7260 SBI_GEN0 : SBI_DBUFF0;
7261 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7262 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7263 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7264
7265 mutex_unlock(&dev_priv->dpio_lock);
7266 }
7267
7268 /* Sequence to disable CLKOUT_DP */
7269 static void lpt_disable_clkout_dp(struct drm_device *dev)
7270 {
7271 struct drm_i915_private *dev_priv = dev->dev_private;
7272 uint32_t reg, tmp;
7273
7274 mutex_lock(&dev_priv->dpio_lock);
7275
7276 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7277 SBI_GEN0 : SBI_DBUFF0;
7278 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7279 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7280 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7281
7282 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7283 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7284 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7285 tmp |= SBI_SSCCTL_PATHALT;
7286 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7287 udelay(32);
7288 }
7289 tmp |= SBI_SSCCTL_DISABLE;
7290 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7291 }
7292
7293 mutex_unlock(&dev_priv->dpio_lock);
7294 }
7295
7296 static void lpt_init_pch_refclk(struct drm_device *dev)
7297 {
7298 struct intel_encoder *encoder;
7299 bool has_vga = false;
7300
7301 for_each_intel_encoder(dev, encoder) {
7302 switch (encoder->type) {
7303 case INTEL_OUTPUT_ANALOG:
7304 has_vga = true;
7305 break;
7306 default:
7307 break;
7308 }
7309 }
7310
7311 if (has_vga)
7312 lpt_enable_clkout_dp(dev, true, true);
7313 else
7314 lpt_disable_clkout_dp(dev);
7315 }
7316
7317 /*
7318 * Initialize reference clocks when the driver loads
7319 */
7320 void intel_init_pch_refclk(struct drm_device *dev)
7321 {
7322 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7323 ironlake_init_pch_refclk(dev);
7324 else if (HAS_PCH_LPT(dev))
7325 lpt_init_pch_refclk(dev);
7326 }
7327
7328 static int ironlake_get_refclk(struct drm_crtc *crtc)
7329 {
7330 struct drm_device *dev = crtc->dev;
7331 struct drm_i915_private *dev_priv = dev->dev_private;
7332 struct intel_encoder *encoder;
7333 int num_connectors = 0;
7334 bool is_lvds = false;
7335
7336 for_each_intel_encoder(dev, encoder) {
7337 if (encoder->new_crtc != to_intel_crtc(crtc))
7338 continue;
7339
7340 switch (encoder->type) {
7341 case INTEL_OUTPUT_LVDS:
7342 is_lvds = true;
7343 break;
7344 default:
7345 break;
7346 }
7347 num_connectors++;
7348 }
7349
7350 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7351 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7352 dev_priv->vbt.lvds_ssc_freq);
7353 return dev_priv->vbt.lvds_ssc_freq;
7354 }
7355
7356 return 120000;
7357 }
7358
7359 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7360 {
7361 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7363 int pipe = intel_crtc->pipe;
7364 uint32_t val;
7365
7366 val = 0;
7367
7368 switch (intel_crtc->config->pipe_bpp) {
7369 case 18:
7370 val |= PIPECONF_6BPC;
7371 break;
7372 case 24:
7373 val |= PIPECONF_8BPC;
7374 break;
7375 case 30:
7376 val |= PIPECONF_10BPC;
7377 break;
7378 case 36:
7379 val |= PIPECONF_12BPC;
7380 break;
7381 default:
7382 /* Case prevented by intel_choose_pipe_bpp_dither. */
7383 BUG();
7384 }
7385
7386 if (intel_crtc->config->dither)
7387 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7388
7389 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7390 val |= PIPECONF_INTERLACED_ILK;
7391 else
7392 val |= PIPECONF_PROGRESSIVE;
7393
7394 if (intel_crtc->config->limited_color_range)
7395 val |= PIPECONF_COLOR_RANGE_SELECT;
7396
7397 I915_WRITE(PIPECONF(pipe), val);
7398 POSTING_READ(PIPECONF(pipe));
7399 }
7400
7401 /*
7402 * Set up the pipe CSC unit.
7403 *
7404 * Currently only full range RGB to limited range RGB conversion
7405 * is supported, but eventually this should handle various
7406 * RGB<->YCbCr scenarios as well.
7407 */
7408 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7409 {
7410 struct drm_device *dev = crtc->dev;
7411 struct drm_i915_private *dev_priv = dev->dev_private;
7412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7413 int pipe = intel_crtc->pipe;
7414 uint16_t coeff = 0x7800; /* 1.0 */
7415
7416 /*
7417 * TODO: Check what kind of values actually come out of the pipe
7418 * with these coeff/postoff values and adjust to get the best
7419 * accuracy. Perhaps we even need to take the bpc value into
7420 * consideration.
7421 */
7422
7423 if (intel_crtc->config->limited_color_range)
7424 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7425
7426 /*
7427 * GY/GU and RY/RU should be the other way around according
7428 * to BSpec, but reality doesn't agree. Just set them up in
7429 * a way that results in the correct picture.
7430 */
7431 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7432 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7433
7434 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7435 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7436
7437 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7438 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7439
7440 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7441 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7442 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7443
7444 if (INTEL_INFO(dev)->gen > 6) {
7445 uint16_t postoff = 0;
7446
7447 if (intel_crtc->config->limited_color_range)
7448 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7449
7450 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7451 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7452 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7453
7454 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7455 } else {
7456 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7457
7458 if (intel_crtc->config->limited_color_range)
7459 mode |= CSC_BLACK_SCREEN_OFFSET;
7460
7461 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7462 }
7463 }
7464
7465 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7466 {
7467 struct drm_device *dev = crtc->dev;
7468 struct drm_i915_private *dev_priv = dev->dev_private;
7469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7470 enum pipe pipe = intel_crtc->pipe;
7471 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7472 uint32_t val;
7473
7474 val = 0;
7475
7476 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7477 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7478
7479 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7480 val |= PIPECONF_INTERLACED_ILK;
7481 else
7482 val |= PIPECONF_PROGRESSIVE;
7483
7484 I915_WRITE(PIPECONF(cpu_transcoder), val);
7485 POSTING_READ(PIPECONF(cpu_transcoder));
7486
7487 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7488 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7489
7490 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7491 val = 0;
7492
7493 switch (intel_crtc->config->pipe_bpp) {
7494 case 18:
7495 val |= PIPEMISC_DITHER_6_BPC;
7496 break;
7497 case 24:
7498 val |= PIPEMISC_DITHER_8_BPC;
7499 break;
7500 case 30:
7501 val |= PIPEMISC_DITHER_10_BPC;
7502 break;
7503 case 36:
7504 val |= PIPEMISC_DITHER_12_BPC;
7505 break;
7506 default:
7507 /* Case prevented by pipe_config_set_bpp. */
7508 BUG();
7509 }
7510
7511 if (intel_crtc->config->dither)
7512 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7513
7514 I915_WRITE(PIPEMISC(pipe), val);
7515 }
7516 }
7517
7518 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7519 struct intel_crtc_state *crtc_state,
7520 intel_clock_t *clock,
7521 bool *has_reduced_clock,
7522 intel_clock_t *reduced_clock)
7523 {
7524 struct drm_device *dev = crtc->dev;
7525 struct drm_i915_private *dev_priv = dev->dev_private;
7526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7527 int refclk;
7528 const intel_limit_t *limit;
7529 bool ret, is_lvds = false;
7530
7531 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7532
7533 refclk = ironlake_get_refclk(crtc);
7534
7535 /*
7536 * Returns a set of divisors for the desired target clock with the given
7537 * refclk, or FALSE. The returned values represent the clock equation:
7538 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7539 */
7540 limit = intel_limit(intel_crtc, refclk);
7541 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7542 crtc_state->port_clock,
7543 refclk, NULL, clock);
7544 if (!ret)
7545 return false;
7546
7547 if (is_lvds && dev_priv->lvds_downclock_avail) {
7548 /*
7549 * Ensure we match the reduced clock's P to the target clock.
7550 * If the clocks don't match, we can't switch the display clock
7551 * by using the FP0/FP1. In such case we will disable the LVDS
7552 * downclock feature.
7553 */
7554 *has_reduced_clock =
7555 dev_priv->display.find_dpll(limit, intel_crtc,
7556 dev_priv->lvds_downclock,
7557 refclk, clock,
7558 reduced_clock);
7559 }
7560
7561 return true;
7562 }
7563
7564 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7565 {
7566 /*
7567 * Account for spread spectrum to avoid
7568 * oversubscribing the link. Max center spread
7569 * is 2.5%; use 5% for safety's sake.
7570 */
7571 u32 bps = target_clock * bpp * 21 / 20;
7572 return DIV_ROUND_UP(bps, link_bw * 8);
7573 }
7574
7575 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7576 {
7577 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7578 }
7579
7580 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7581 struct intel_crtc_state *crtc_state,
7582 u32 *fp,
7583 intel_clock_t *reduced_clock, u32 *fp2)
7584 {
7585 struct drm_crtc *crtc = &intel_crtc->base;
7586 struct drm_device *dev = crtc->dev;
7587 struct drm_i915_private *dev_priv = dev->dev_private;
7588 struct intel_encoder *intel_encoder;
7589 uint32_t dpll;
7590 int factor, num_connectors = 0;
7591 bool is_lvds = false, is_sdvo = false;
7592
7593 for_each_intel_encoder(dev, intel_encoder) {
7594 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7595 continue;
7596
7597 switch (intel_encoder->type) {
7598 case INTEL_OUTPUT_LVDS:
7599 is_lvds = true;
7600 break;
7601 case INTEL_OUTPUT_SDVO:
7602 case INTEL_OUTPUT_HDMI:
7603 is_sdvo = true;
7604 break;
7605 default:
7606 break;
7607 }
7608
7609 num_connectors++;
7610 }
7611
7612 /* Enable autotuning of the PLL clock (if permissible) */
7613 factor = 21;
7614 if (is_lvds) {
7615 if ((intel_panel_use_ssc(dev_priv) &&
7616 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7617 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7618 factor = 25;
7619 } else if (crtc_state->sdvo_tv_clock)
7620 factor = 20;
7621
7622 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7623 *fp |= FP_CB_TUNE;
7624
7625 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7626 *fp2 |= FP_CB_TUNE;
7627
7628 dpll = 0;
7629
7630 if (is_lvds)
7631 dpll |= DPLLB_MODE_LVDS;
7632 else
7633 dpll |= DPLLB_MODE_DAC_SERIAL;
7634
7635 dpll |= (crtc_state->pixel_multiplier - 1)
7636 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7637
7638 if (is_sdvo)
7639 dpll |= DPLL_SDVO_HIGH_SPEED;
7640 if (crtc_state->has_dp_encoder)
7641 dpll |= DPLL_SDVO_HIGH_SPEED;
7642
7643 /* compute bitmask from p1 value */
7644 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7645 /* also FPA1 */
7646 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7647
7648 switch (crtc_state->dpll.p2) {
7649 case 5:
7650 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7651 break;
7652 case 7:
7653 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7654 break;
7655 case 10:
7656 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7657 break;
7658 case 14:
7659 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7660 break;
7661 }
7662
7663 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7664 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7665 else
7666 dpll |= PLL_REF_INPUT_DREFCLK;
7667
7668 return dpll | DPLL_VCO_ENABLE;
7669 }
7670
7671 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7672 struct intel_crtc_state *crtc_state)
7673 {
7674 struct drm_device *dev = crtc->base.dev;
7675 intel_clock_t clock, reduced_clock;
7676 u32 dpll = 0, fp = 0, fp2 = 0;
7677 bool ok, has_reduced_clock = false;
7678 bool is_lvds = false;
7679 struct intel_shared_dpll *pll;
7680
7681 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7682
7683 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7684 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7685
7686 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7687 &has_reduced_clock, &reduced_clock);
7688 if (!ok && !crtc_state->clock_set) {
7689 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7690 return -EINVAL;
7691 }
7692 /* Compat-code for transition, will disappear. */
7693 if (!crtc_state->clock_set) {
7694 crtc_state->dpll.n = clock.n;
7695 crtc_state->dpll.m1 = clock.m1;
7696 crtc_state->dpll.m2 = clock.m2;
7697 crtc_state->dpll.p1 = clock.p1;
7698 crtc_state->dpll.p2 = clock.p2;
7699 }
7700
7701 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7702 if (crtc_state->has_pch_encoder) {
7703 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7704 if (has_reduced_clock)
7705 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7706
7707 dpll = ironlake_compute_dpll(crtc, crtc_state,
7708 &fp, &reduced_clock,
7709 has_reduced_clock ? &fp2 : NULL);
7710
7711 crtc_state->dpll_hw_state.dpll = dpll;
7712 crtc_state->dpll_hw_state.fp0 = fp;
7713 if (has_reduced_clock)
7714 crtc_state->dpll_hw_state.fp1 = fp2;
7715 else
7716 crtc_state->dpll_hw_state.fp1 = fp;
7717
7718 pll = intel_get_shared_dpll(crtc, crtc_state);
7719 if (pll == NULL) {
7720 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7721 pipe_name(crtc->pipe));
7722 return -EINVAL;
7723 }
7724 }
7725
7726 if (is_lvds && has_reduced_clock && i915.powersave)
7727 crtc->lowfreq_avail = true;
7728 else
7729 crtc->lowfreq_avail = false;
7730
7731 return 0;
7732 }
7733
7734 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7735 struct intel_link_m_n *m_n)
7736 {
7737 struct drm_device *dev = crtc->base.dev;
7738 struct drm_i915_private *dev_priv = dev->dev_private;
7739 enum pipe pipe = crtc->pipe;
7740
7741 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7742 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7743 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7744 & ~TU_SIZE_MASK;
7745 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7746 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7747 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7748 }
7749
7750 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7751 enum transcoder transcoder,
7752 struct intel_link_m_n *m_n,
7753 struct intel_link_m_n *m2_n2)
7754 {
7755 struct drm_device *dev = crtc->base.dev;
7756 struct drm_i915_private *dev_priv = dev->dev_private;
7757 enum pipe pipe = crtc->pipe;
7758
7759 if (INTEL_INFO(dev)->gen >= 5) {
7760 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7761 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7762 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7763 & ~TU_SIZE_MASK;
7764 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7765 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7766 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7767 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7768 * gen < 8) and if DRRS is supported (to make sure the
7769 * registers are not unnecessarily read).
7770 */
7771 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7772 crtc->config->has_drrs) {
7773 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7774 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7775 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7776 & ~TU_SIZE_MASK;
7777 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7778 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7779 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7780 }
7781 } else {
7782 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7783 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7784 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7785 & ~TU_SIZE_MASK;
7786 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7787 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7788 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7789 }
7790 }
7791
7792 void intel_dp_get_m_n(struct intel_crtc *crtc,
7793 struct intel_crtc_state *pipe_config)
7794 {
7795 if (pipe_config->has_pch_encoder)
7796 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7797 else
7798 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7799 &pipe_config->dp_m_n,
7800 &pipe_config->dp_m2_n2);
7801 }
7802
7803 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7804 struct intel_crtc_state *pipe_config)
7805 {
7806 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7807 &pipe_config->fdi_m_n, NULL);
7808 }
7809
7810 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7811 struct intel_crtc_state *pipe_config)
7812 {
7813 struct drm_device *dev = crtc->base.dev;
7814 struct drm_i915_private *dev_priv = dev->dev_private;
7815 uint32_t tmp;
7816
7817 tmp = I915_READ(PS_CTL(crtc->pipe));
7818
7819 if (tmp & PS_ENABLE) {
7820 pipe_config->pch_pfit.enabled = true;
7821 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7822 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7823 }
7824 }
7825
7826 static void
7827 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7828 struct intel_initial_plane_config *plane_config)
7829 {
7830 struct drm_device *dev = crtc->base.dev;
7831 struct drm_i915_private *dev_priv = dev->dev_private;
7832 u32 val, base, offset, stride_mult, tiling;
7833 int pipe = crtc->pipe;
7834 int fourcc, pixel_format;
7835 int aligned_height;
7836 struct drm_framebuffer *fb;
7837 struct intel_framebuffer *intel_fb;
7838
7839 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7840 if (!intel_fb) {
7841 DRM_DEBUG_KMS("failed to alloc fb\n");
7842 return;
7843 }
7844
7845 fb = &intel_fb->base;
7846
7847 val = I915_READ(PLANE_CTL(pipe, 0));
7848 if (!(val & PLANE_CTL_ENABLE))
7849 goto error;
7850
7851 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7852 fourcc = skl_format_to_fourcc(pixel_format,
7853 val & PLANE_CTL_ORDER_RGBX,
7854 val & PLANE_CTL_ALPHA_MASK);
7855 fb->pixel_format = fourcc;
7856 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7857
7858 tiling = val & PLANE_CTL_TILED_MASK;
7859 switch (tiling) {
7860 case PLANE_CTL_TILED_LINEAR:
7861 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7862 break;
7863 case PLANE_CTL_TILED_X:
7864 plane_config->tiling = I915_TILING_X;
7865 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7866 break;
7867 case PLANE_CTL_TILED_Y:
7868 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7869 break;
7870 case PLANE_CTL_TILED_YF:
7871 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7872 break;
7873 default:
7874 MISSING_CASE(tiling);
7875 goto error;
7876 }
7877
7878 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7879 plane_config->base = base;
7880
7881 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7882
7883 val = I915_READ(PLANE_SIZE(pipe, 0));
7884 fb->height = ((val >> 16) & 0xfff) + 1;
7885 fb->width = ((val >> 0) & 0x1fff) + 1;
7886
7887 val = I915_READ(PLANE_STRIDE(pipe, 0));
7888 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7889 fb->pixel_format);
7890 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7891
7892 aligned_height = intel_fb_align_height(dev, fb->height,
7893 fb->pixel_format,
7894 fb->modifier[0]);
7895
7896 plane_config->size = fb->pitches[0] * aligned_height;
7897
7898 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7899 pipe_name(pipe), fb->width, fb->height,
7900 fb->bits_per_pixel, base, fb->pitches[0],
7901 plane_config->size);
7902
7903 plane_config->fb = intel_fb;
7904 return;
7905
7906 error:
7907 kfree(fb);
7908 }
7909
7910 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7911 struct intel_crtc_state *pipe_config)
7912 {
7913 struct drm_device *dev = crtc->base.dev;
7914 struct drm_i915_private *dev_priv = dev->dev_private;
7915 uint32_t tmp;
7916
7917 tmp = I915_READ(PF_CTL(crtc->pipe));
7918
7919 if (tmp & PF_ENABLE) {
7920 pipe_config->pch_pfit.enabled = true;
7921 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7922 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7923
7924 /* We currently do not free assignements of panel fitters on
7925 * ivb/hsw (since we don't use the higher upscaling modes which
7926 * differentiates them) so just WARN about this case for now. */
7927 if (IS_GEN7(dev)) {
7928 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7929 PF_PIPE_SEL_IVB(crtc->pipe));
7930 }
7931 }
7932 }
7933
7934 static void
7935 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7936 struct intel_initial_plane_config *plane_config)
7937 {
7938 struct drm_device *dev = crtc->base.dev;
7939 struct drm_i915_private *dev_priv = dev->dev_private;
7940 u32 val, base, offset;
7941 int pipe = crtc->pipe;
7942 int fourcc, pixel_format;
7943 int aligned_height;
7944 struct drm_framebuffer *fb;
7945 struct intel_framebuffer *intel_fb;
7946
7947 val = I915_READ(DSPCNTR(pipe));
7948 if (!(val & DISPLAY_PLANE_ENABLE))
7949 return;
7950
7951 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7952 if (!intel_fb) {
7953 DRM_DEBUG_KMS("failed to alloc fb\n");
7954 return;
7955 }
7956
7957 fb = &intel_fb->base;
7958
7959 if (INTEL_INFO(dev)->gen >= 4) {
7960 if (val & DISPPLANE_TILED) {
7961 plane_config->tiling = I915_TILING_X;
7962 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7963 }
7964 }
7965
7966 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7967 fourcc = i9xx_format_to_fourcc(pixel_format);
7968 fb->pixel_format = fourcc;
7969 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7970
7971 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7972 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7973 offset = I915_READ(DSPOFFSET(pipe));
7974 } else {
7975 if (plane_config->tiling)
7976 offset = I915_READ(DSPTILEOFF(pipe));
7977 else
7978 offset = I915_READ(DSPLINOFF(pipe));
7979 }
7980 plane_config->base = base;
7981
7982 val = I915_READ(PIPESRC(pipe));
7983 fb->width = ((val >> 16) & 0xfff) + 1;
7984 fb->height = ((val >> 0) & 0xfff) + 1;
7985
7986 val = I915_READ(DSPSTRIDE(pipe));
7987 fb->pitches[0] = val & 0xffffffc0;
7988
7989 aligned_height = intel_fb_align_height(dev, fb->height,
7990 fb->pixel_format,
7991 fb->modifier[0]);
7992
7993 plane_config->size = fb->pitches[0] * aligned_height;
7994
7995 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7996 pipe_name(pipe), fb->width, fb->height,
7997 fb->bits_per_pixel, base, fb->pitches[0],
7998 plane_config->size);
7999
8000 plane_config->fb = intel_fb;
8001 }
8002
8003 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8004 struct intel_crtc_state *pipe_config)
8005 {
8006 struct drm_device *dev = crtc->base.dev;
8007 struct drm_i915_private *dev_priv = dev->dev_private;
8008 uint32_t tmp;
8009
8010 if (!intel_display_power_is_enabled(dev_priv,
8011 POWER_DOMAIN_PIPE(crtc->pipe)))
8012 return false;
8013
8014 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8015 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8016
8017 tmp = I915_READ(PIPECONF(crtc->pipe));
8018 if (!(tmp & PIPECONF_ENABLE))
8019 return false;
8020
8021 switch (tmp & PIPECONF_BPC_MASK) {
8022 case PIPECONF_6BPC:
8023 pipe_config->pipe_bpp = 18;
8024 break;
8025 case PIPECONF_8BPC:
8026 pipe_config->pipe_bpp = 24;
8027 break;
8028 case PIPECONF_10BPC:
8029 pipe_config->pipe_bpp = 30;
8030 break;
8031 case PIPECONF_12BPC:
8032 pipe_config->pipe_bpp = 36;
8033 break;
8034 default:
8035 break;
8036 }
8037
8038 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8039 pipe_config->limited_color_range = true;
8040
8041 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8042 struct intel_shared_dpll *pll;
8043
8044 pipe_config->has_pch_encoder = true;
8045
8046 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8047 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8048 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8049
8050 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8051
8052 if (HAS_PCH_IBX(dev_priv->dev)) {
8053 pipe_config->shared_dpll =
8054 (enum intel_dpll_id) crtc->pipe;
8055 } else {
8056 tmp = I915_READ(PCH_DPLL_SEL);
8057 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8058 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8059 else
8060 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8061 }
8062
8063 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8064
8065 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8066 &pipe_config->dpll_hw_state));
8067
8068 tmp = pipe_config->dpll_hw_state.dpll;
8069 pipe_config->pixel_multiplier =
8070 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8071 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8072
8073 ironlake_pch_clock_get(crtc, pipe_config);
8074 } else {
8075 pipe_config->pixel_multiplier = 1;
8076 }
8077
8078 intel_get_pipe_timings(crtc, pipe_config);
8079
8080 ironlake_get_pfit_config(crtc, pipe_config);
8081
8082 return true;
8083 }
8084
8085 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8086 {
8087 struct drm_device *dev = dev_priv->dev;
8088 struct intel_crtc *crtc;
8089
8090 for_each_intel_crtc(dev, crtc)
8091 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8092 pipe_name(crtc->pipe));
8093
8094 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8095 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8096 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8097 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8098 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8099 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8100 "CPU PWM1 enabled\n");
8101 if (IS_HASWELL(dev))
8102 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8103 "CPU PWM2 enabled\n");
8104 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8105 "PCH PWM1 enabled\n");
8106 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8107 "Utility pin enabled\n");
8108 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8109
8110 /*
8111 * In theory we can still leave IRQs enabled, as long as only the HPD
8112 * interrupts remain enabled. We used to check for that, but since it's
8113 * gen-specific and since we only disable LCPLL after we fully disable
8114 * the interrupts, the check below should be enough.
8115 */
8116 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8117 }
8118
8119 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8120 {
8121 struct drm_device *dev = dev_priv->dev;
8122
8123 if (IS_HASWELL(dev))
8124 return I915_READ(D_COMP_HSW);
8125 else
8126 return I915_READ(D_COMP_BDW);
8127 }
8128
8129 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8130 {
8131 struct drm_device *dev = dev_priv->dev;
8132
8133 if (IS_HASWELL(dev)) {
8134 mutex_lock(&dev_priv->rps.hw_lock);
8135 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8136 val))
8137 DRM_ERROR("Failed to write to D_COMP\n");
8138 mutex_unlock(&dev_priv->rps.hw_lock);
8139 } else {
8140 I915_WRITE(D_COMP_BDW, val);
8141 POSTING_READ(D_COMP_BDW);
8142 }
8143 }
8144
8145 /*
8146 * This function implements pieces of two sequences from BSpec:
8147 * - Sequence for display software to disable LCPLL
8148 * - Sequence for display software to allow package C8+
8149 * The steps implemented here are just the steps that actually touch the LCPLL
8150 * register. Callers should take care of disabling all the display engine
8151 * functions, doing the mode unset, fixing interrupts, etc.
8152 */
8153 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8154 bool switch_to_fclk, bool allow_power_down)
8155 {
8156 uint32_t val;
8157
8158 assert_can_disable_lcpll(dev_priv);
8159
8160 val = I915_READ(LCPLL_CTL);
8161
8162 if (switch_to_fclk) {
8163 val |= LCPLL_CD_SOURCE_FCLK;
8164 I915_WRITE(LCPLL_CTL, val);
8165
8166 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8167 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8168 DRM_ERROR("Switching to FCLK failed\n");
8169
8170 val = I915_READ(LCPLL_CTL);
8171 }
8172
8173 val |= LCPLL_PLL_DISABLE;
8174 I915_WRITE(LCPLL_CTL, val);
8175 POSTING_READ(LCPLL_CTL);
8176
8177 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8178 DRM_ERROR("LCPLL still locked\n");
8179
8180 val = hsw_read_dcomp(dev_priv);
8181 val |= D_COMP_COMP_DISABLE;
8182 hsw_write_dcomp(dev_priv, val);
8183 ndelay(100);
8184
8185 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8186 1))
8187 DRM_ERROR("D_COMP RCOMP still in progress\n");
8188
8189 if (allow_power_down) {
8190 val = I915_READ(LCPLL_CTL);
8191 val |= LCPLL_POWER_DOWN_ALLOW;
8192 I915_WRITE(LCPLL_CTL, val);
8193 POSTING_READ(LCPLL_CTL);
8194 }
8195 }
8196
8197 /*
8198 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8199 * source.
8200 */
8201 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8202 {
8203 uint32_t val;
8204
8205 val = I915_READ(LCPLL_CTL);
8206
8207 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8208 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8209 return;
8210
8211 /*
8212 * Make sure we're not on PC8 state before disabling PC8, otherwise
8213 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8214 */
8215 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8216
8217 if (val & LCPLL_POWER_DOWN_ALLOW) {
8218 val &= ~LCPLL_POWER_DOWN_ALLOW;
8219 I915_WRITE(LCPLL_CTL, val);
8220 POSTING_READ(LCPLL_CTL);
8221 }
8222
8223 val = hsw_read_dcomp(dev_priv);
8224 val |= D_COMP_COMP_FORCE;
8225 val &= ~D_COMP_COMP_DISABLE;
8226 hsw_write_dcomp(dev_priv, val);
8227
8228 val = I915_READ(LCPLL_CTL);
8229 val &= ~LCPLL_PLL_DISABLE;
8230 I915_WRITE(LCPLL_CTL, val);
8231
8232 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8233 DRM_ERROR("LCPLL not locked yet\n");
8234
8235 if (val & LCPLL_CD_SOURCE_FCLK) {
8236 val = I915_READ(LCPLL_CTL);
8237 val &= ~LCPLL_CD_SOURCE_FCLK;
8238 I915_WRITE(LCPLL_CTL, val);
8239
8240 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8241 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8242 DRM_ERROR("Switching back to LCPLL failed\n");
8243 }
8244
8245 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8246 }
8247
8248 /*
8249 * Package states C8 and deeper are really deep PC states that can only be
8250 * reached when all the devices on the system allow it, so even if the graphics
8251 * device allows PC8+, it doesn't mean the system will actually get to these
8252 * states. Our driver only allows PC8+ when going into runtime PM.
8253 *
8254 * The requirements for PC8+ are that all the outputs are disabled, the power
8255 * well is disabled and most interrupts are disabled, and these are also
8256 * requirements for runtime PM. When these conditions are met, we manually do
8257 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8258 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8259 * hang the machine.
8260 *
8261 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8262 * the state of some registers, so when we come back from PC8+ we need to
8263 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8264 * need to take care of the registers kept by RC6. Notice that this happens even
8265 * if we don't put the device in PCI D3 state (which is what currently happens
8266 * because of the runtime PM support).
8267 *
8268 * For more, read "Display Sequences for Package C8" on the hardware
8269 * documentation.
8270 */
8271 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8272 {
8273 struct drm_device *dev = dev_priv->dev;
8274 uint32_t val;
8275
8276 DRM_DEBUG_KMS("Enabling package C8+\n");
8277
8278 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8279 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8280 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8281 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8282 }
8283
8284 lpt_disable_clkout_dp(dev);
8285 hsw_disable_lcpll(dev_priv, true, true);
8286 }
8287
8288 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8289 {
8290 struct drm_device *dev = dev_priv->dev;
8291 uint32_t val;
8292
8293 DRM_DEBUG_KMS("Disabling package C8+\n");
8294
8295 hsw_restore_lcpll(dev_priv);
8296 lpt_init_pch_refclk(dev);
8297
8298 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8299 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8300 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8301 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8302 }
8303
8304 intel_prepare_ddi(dev);
8305 }
8306
8307 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8308 struct intel_crtc_state *crtc_state)
8309 {
8310 if (!intel_ddi_pll_select(crtc, crtc_state))
8311 return -EINVAL;
8312
8313 crtc->lowfreq_avail = false;
8314
8315 return 0;
8316 }
8317
8318 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8319 enum port port,
8320 struct intel_crtc_state *pipe_config)
8321 {
8322 u32 temp, dpll_ctl1;
8323
8324 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8325 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8326
8327 switch (pipe_config->ddi_pll_sel) {
8328 case SKL_DPLL0:
8329 /*
8330 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8331 * of the shared DPLL framework and thus needs to be read out
8332 * separately
8333 */
8334 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8335 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8336 break;
8337 case SKL_DPLL1:
8338 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8339 break;
8340 case SKL_DPLL2:
8341 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8342 break;
8343 case SKL_DPLL3:
8344 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8345 break;
8346 }
8347 }
8348
8349 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8350 enum port port,
8351 struct intel_crtc_state *pipe_config)
8352 {
8353 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8354
8355 switch (pipe_config->ddi_pll_sel) {
8356 case PORT_CLK_SEL_WRPLL1:
8357 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8358 break;
8359 case PORT_CLK_SEL_WRPLL2:
8360 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8361 break;
8362 }
8363 }
8364
8365 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8366 struct intel_crtc_state *pipe_config)
8367 {
8368 struct drm_device *dev = crtc->base.dev;
8369 struct drm_i915_private *dev_priv = dev->dev_private;
8370 struct intel_shared_dpll *pll;
8371 enum port port;
8372 uint32_t tmp;
8373
8374 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8375
8376 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8377
8378 if (IS_SKYLAKE(dev))
8379 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8380 else
8381 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8382
8383 if (pipe_config->shared_dpll >= 0) {
8384 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8385
8386 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8387 &pipe_config->dpll_hw_state));
8388 }
8389
8390 /*
8391 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8392 * DDI E. So just check whether this pipe is wired to DDI E and whether
8393 * the PCH transcoder is on.
8394 */
8395 if (INTEL_INFO(dev)->gen < 9 &&
8396 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8397 pipe_config->has_pch_encoder = true;
8398
8399 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8400 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8401 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8402
8403 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8404 }
8405 }
8406
8407 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8408 struct intel_crtc_state *pipe_config)
8409 {
8410 struct drm_device *dev = crtc->base.dev;
8411 struct drm_i915_private *dev_priv = dev->dev_private;
8412 enum intel_display_power_domain pfit_domain;
8413 uint32_t tmp;
8414
8415 if (!intel_display_power_is_enabled(dev_priv,
8416 POWER_DOMAIN_PIPE(crtc->pipe)))
8417 return false;
8418
8419 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8420 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8421
8422 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8423 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8424 enum pipe trans_edp_pipe;
8425 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8426 default:
8427 WARN(1, "unknown pipe linked to edp transcoder\n");
8428 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8429 case TRANS_DDI_EDP_INPUT_A_ON:
8430 trans_edp_pipe = PIPE_A;
8431 break;
8432 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8433 trans_edp_pipe = PIPE_B;
8434 break;
8435 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8436 trans_edp_pipe = PIPE_C;
8437 break;
8438 }
8439
8440 if (trans_edp_pipe == crtc->pipe)
8441 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8442 }
8443
8444 if (!intel_display_power_is_enabled(dev_priv,
8445 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8446 return false;
8447
8448 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8449 if (!(tmp & PIPECONF_ENABLE))
8450 return false;
8451
8452 haswell_get_ddi_port_state(crtc, pipe_config);
8453
8454 intel_get_pipe_timings(crtc, pipe_config);
8455
8456 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8457 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8458 if (IS_SKYLAKE(dev))
8459 skylake_get_pfit_config(crtc, pipe_config);
8460 else
8461 ironlake_get_pfit_config(crtc, pipe_config);
8462 }
8463
8464 if (IS_HASWELL(dev))
8465 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8466 (I915_READ(IPS_CTL) & IPS_ENABLE);
8467
8468 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8469 pipe_config->pixel_multiplier =
8470 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8471 } else {
8472 pipe_config->pixel_multiplier = 1;
8473 }
8474
8475 return true;
8476 }
8477
8478 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8479 {
8480 struct drm_device *dev = crtc->dev;
8481 struct drm_i915_private *dev_priv = dev->dev_private;
8482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8483 uint32_t cntl = 0, size = 0;
8484
8485 if (base) {
8486 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8487 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8488 unsigned int stride = roundup_pow_of_two(width) * 4;
8489
8490 switch (stride) {
8491 default:
8492 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8493 width, stride);
8494 stride = 256;
8495 /* fallthrough */
8496 case 256:
8497 case 512:
8498 case 1024:
8499 case 2048:
8500 break;
8501 }
8502
8503 cntl |= CURSOR_ENABLE |
8504 CURSOR_GAMMA_ENABLE |
8505 CURSOR_FORMAT_ARGB |
8506 CURSOR_STRIDE(stride);
8507
8508 size = (height << 12) | width;
8509 }
8510
8511 if (intel_crtc->cursor_cntl != 0 &&
8512 (intel_crtc->cursor_base != base ||
8513 intel_crtc->cursor_size != size ||
8514 intel_crtc->cursor_cntl != cntl)) {
8515 /* On these chipsets we can only modify the base/size/stride
8516 * whilst the cursor is disabled.
8517 */
8518 I915_WRITE(_CURACNTR, 0);
8519 POSTING_READ(_CURACNTR);
8520 intel_crtc->cursor_cntl = 0;
8521 }
8522
8523 if (intel_crtc->cursor_base != base) {
8524 I915_WRITE(_CURABASE, base);
8525 intel_crtc->cursor_base = base;
8526 }
8527
8528 if (intel_crtc->cursor_size != size) {
8529 I915_WRITE(CURSIZE, size);
8530 intel_crtc->cursor_size = size;
8531 }
8532
8533 if (intel_crtc->cursor_cntl != cntl) {
8534 I915_WRITE(_CURACNTR, cntl);
8535 POSTING_READ(_CURACNTR);
8536 intel_crtc->cursor_cntl = cntl;
8537 }
8538 }
8539
8540 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8541 {
8542 struct drm_device *dev = crtc->dev;
8543 struct drm_i915_private *dev_priv = dev->dev_private;
8544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8545 int pipe = intel_crtc->pipe;
8546 uint32_t cntl;
8547
8548 cntl = 0;
8549 if (base) {
8550 cntl = MCURSOR_GAMMA_ENABLE;
8551 switch (intel_crtc->base.cursor->state->crtc_w) {
8552 case 64:
8553 cntl |= CURSOR_MODE_64_ARGB_AX;
8554 break;
8555 case 128:
8556 cntl |= CURSOR_MODE_128_ARGB_AX;
8557 break;
8558 case 256:
8559 cntl |= CURSOR_MODE_256_ARGB_AX;
8560 break;
8561 default:
8562 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8563 return;
8564 }
8565 cntl |= pipe << 28; /* Connect to correct pipe */
8566
8567 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8568 cntl |= CURSOR_PIPE_CSC_ENABLE;
8569 }
8570
8571 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8572 cntl |= CURSOR_ROTATE_180;
8573
8574 if (intel_crtc->cursor_cntl != cntl) {
8575 I915_WRITE(CURCNTR(pipe), cntl);
8576 POSTING_READ(CURCNTR(pipe));
8577 intel_crtc->cursor_cntl = cntl;
8578 }
8579
8580 /* and commit changes on next vblank */
8581 I915_WRITE(CURBASE(pipe), base);
8582 POSTING_READ(CURBASE(pipe));
8583
8584 intel_crtc->cursor_base = base;
8585 }
8586
8587 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8588 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8589 bool on)
8590 {
8591 struct drm_device *dev = crtc->dev;
8592 struct drm_i915_private *dev_priv = dev->dev_private;
8593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8594 int pipe = intel_crtc->pipe;
8595 int x = crtc->cursor_x;
8596 int y = crtc->cursor_y;
8597 u32 base = 0, pos = 0;
8598
8599 if (on)
8600 base = intel_crtc->cursor_addr;
8601
8602 if (x >= intel_crtc->config->pipe_src_w)
8603 base = 0;
8604
8605 if (y >= intel_crtc->config->pipe_src_h)
8606 base = 0;
8607
8608 if (x < 0) {
8609 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8610 base = 0;
8611
8612 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8613 x = -x;
8614 }
8615 pos |= x << CURSOR_X_SHIFT;
8616
8617 if (y < 0) {
8618 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8619 base = 0;
8620
8621 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8622 y = -y;
8623 }
8624 pos |= y << CURSOR_Y_SHIFT;
8625
8626 if (base == 0 && intel_crtc->cursor_base == 0)
8627 return;
8628
8629 I915_WRITE(CURPOS(pipe), pos);
8630
8631 /* ILK+ do this automagically */
8632 if (HAS_GMCH_DISPLAY(dev) &&
8633 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8634 base += (intel_crtc->base.cursor->state->crtc_h *
8635 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8636 }
8637
8638 if (IS_845G(dev) || IS_I865G(dev))
8639 i845_update_cursor(crtc, base);
8640 else
8641 i9xx_update_cursor(crtc, base);
8642 }
8643
8644 static bool cursor_size_ok(struct drm_device *dev,
8645 uint32_t width, uint32_t height)
8646 {
8647 if (width == 0 || height == 0)
8648 return false;
8649
8650 /*
8651 * 845g/865g are special in that they are only limited by
8652 * the width of their cursors, the height is arbitrary up to
8653 * the precision of the register. Everything else requires
8654 * square cursors, limited to a few power-of-two sizes.
8655 */
8656 if (IS_845G(dev) || IS_I865G(dev)) {
8657 if ((width & 63) != 0)
8658 return false;
8659
8660 if (width > (IS_845G(dev) ? 64 : 512))
8661 return false;
8662
8663 if (height > 1023)
8664 return false;
8665 } else {
8666 switch (width | height) {
8667 case 256:
8668 case 128:
8669 if (IS_GEN2(dev))
8670 return false;
8671 case 64:
8672 break;
8673 default:
8674 return false;
8675 }
8676 }
8677
8678 return true;
8679 }
8680
8681 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8682 u16 *blue, uint32_t start, uint32_t size)
8683 {
8684 int end = (start + size > 256) ? 256 : start + size, i;
8685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8686
8687 for (i = start; i < end; i++) {
8688 intel_crtc->lut_r[i] = red[i] >> 8;
8689 intel_crtc->lut_g[i] = green[i] >> 8;
8690 intel_crtc->lut_b[i] = blue[i] >> 8;
8691 }
8692
8693 intel_crtc_load_lut(crtc);
8694 }
8695
8696 /* VESA 640x480x72Hz mode to set on the pipe */
8697 static struct drm_display_mode load_detect_mode = {
8698 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8699 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8700 };
8701
8702 struct drm_framebuffer *
8703 __intel_framebuffer_create(struct drm_device *dev,
8704 struct drm_mode_fb_cmd2 *mode_cmd,
8705 struct drm_i915_gem_object *obj)
8706 {
8707 struct intel_framebuffer *intel_fb;
8708 int ret;
8709
8710 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8711 if (!intel_fb) {
8712 drm_gem_object_unreference(&obj->base);
8713 return ERR_PTR(-ENOMEM);
8714 }
8715
8716 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8717 if (ret)
8718 goto err;
8719
8720 return &intel_fb->base;
8721 err:
8722 drm_gem_object_unreference(&obj->base);
8723 kfree(intel_fb);
8724
8725 return ERR_PTR(ret);
8726 }
8727
8728 static struct drm_framebuffer *
8729 intel_framebuffer_create(struct drm_device *dev,
8730 struct drm_mode_fb_cmd2 *mode_cmd,
8731 struct drm_i915_gem_object *obj)
8732 {
8733 struct drm_framebuffer *fb;
8734 int ret;
8735
8736 ret = i915_mutex_lock_interruptible(dev);
8737 if (ret)
8738 return ERR_PTR(ret);
8739 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8740 mutex_unlock(&dev->struct_mutex);
8741
8742 return fb;
8743 }
8744
8745 static u32
8746 intel_framebuffer_pitch_for_width(int width, int bpp)
8747 {
8748 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8749 return ALIGN(pitch, 64);
8750 }
8751
8752 static u32
8753 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8754 {
8755 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8756 return PAGE_ALIGN(pitch * mode->vdisplay);
8757 }
8758
8759 static struct drm_framebuffer *
8760 intel_framebuffer_create_for_mode(struct drm_device *dev,
8761 struct drm_display_mode *mode,
8762 int depth, int bpp)
8763 {
8764 struct drm_i915_gem_object *obj;
8765 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8766
8767 obj = i915_gem_alloc_object(dev,
8768 intel_framebuffer_size_for_mode(mode, bpp));
8769 if (obj == NULL)
8770 return ERR_PTR(-ENOMEM);
8771
8772 mode_cmd.width = mode->hdisplay;
8773 mode_cmd.height = mode->vdisplay;
8774 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8775 bpp);
8776 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8777
8778 return intel_framebuffer_create(dev, &mode_cmd, obj);
8779 }
8780
8781 static struct drm_framebuffer *
8782 mode_fits_in_fbdev(struct drm_device *dev,
8783 struct drm_display_mode *mode)
8784 {
8785 #ifdef CONFIG_DRM_I915_FBDEV
8786 struct drm_i915_private *dev_priv = dev->dev_private;
8787 struct drm_i915_gem_object *obj;
8788 struct drm_framebuffer *fb;
8789
8790 if (!dev_priv->fbdev)
8791 return NULL;
8792
8793 if (!dev_priv->fbdev->fb)
8794 return NULL;
8795
8796 obj = dev_priv->fbdev->fb->obj;
8797 BUG_ON(!obj);
8798
8799 fb = &dev_priv->fbdev->fb->base;
8800 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8801 fb->bits_per_pixel))
8802 return NULL;
8803
8804 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8805 return NULL;
8806
8807 return fb;
8808 #else
8809 return NULL;
8810 #endif
8811 }
8812
8813 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8814 struct drm_display_mode *mode,
8815 struct intel_load_detect_pipe *old,
8816 struct drm_modeset_acquire_ctx *ctx)
8817 {
8818 struct intel_crtc *intel_crtc;
8819 struct intel_encoder *intel_encoder =
8820 intel_attached_encoder(connector);
8821 struct drm_crtc *possible_crtc;
8822 struct drm_encoder *encoder = &intel_encoder->base;
8823 struct drm_crtc *crtc = NULL;
8824 struct drm_device *dev = encoder->dev;
8825 struct drm_framebuffer *fb;
8826 struct drm_mode_config *config = &dev->mode_config;
8827 int ret, i = -1;
8828
8829 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8830 connector->base.id, connector->name,
8831 encoder->base.id, encoder->name);
8832
8833 retry:
8834 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8835 if (ret)
8836 goto fail_unlock;
8837
8838 /*
8839 * Algorithm gets a little messy:
8840 *
8841 * - if the connector already has an assigned crtc, use it (but make
8842 * sure it's on first)
8843 *
8844 * - try to find the first unused crtc that can drive this connector,
8845 * and use that if we find one
8846 */
8847
8848 /* See if we already have a CRTC for this connector */
8849 if (encoder->crtc) {
8850 crtc = encoder->crtc;
8851
8852 ret = drm_modeset_lock(&crtc->mutex, ctx);
8853 if (ret)
8854 goto fail_unlock;
8855 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8856 if (ret)
8857 goto fail_unlock;
8858
8859 old->dpms_mode = connector->dpms;
8860 old->load_detect_temp = false;
8861
8862 /* Make sure the crtc and connector are running */
8863 if (connector->dpms != DRM_MODE_DPMS_ON)
8864 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8865
8866 return true;
8867 }
8868
8869 /* Find an unused one (if possible) */
8870 for_each_crtc(dev, possible_crtc) {
8871 i++;
8872 if (!(encoder->possible_crtcs & (1 << i)))
8873 continue;
8874 if (possible_crtc->state->enable)
8875 continue;
8876 /* This can occur when applying the pipe A quirk on resume. */
8877 if (to_intel_crtc(possible_crtc)->new_enabled)
8878 continue;
8879
8880 crtc = possible_crtc;
8881 break;
8882 }
8883
8884 /*
8885 * If we didn't find an unused CRTC, don't use any.
8886 */
8887 if (!crtc) {
8888 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8889 goto fail_unlock;
8890 }
8891
8892 ret = drm_modeset_lock(&crtc->mutex, ctx);
8893 if (ret)
8894 goto fail_unlock;
8895 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8896 if (ret)
8897 goto fail_unlock;
8898 intel_encoder->new_crtc = to_intel_crtc(crtc);
8899 to_intel_connector(connector)->new_encoder = intel_encoder;
8900
8901 intel_crtc = to_intel_crtc(crtc);
8902 intel_crtc->new_enabled = true;
8903 intel_crtc->new_config = intel_crtc->config;
8904 old->dpms_mode = connector->dpms;
8905 old->load_detect_temp = true;
8906 old->release_fb = NULL;
8907
8908 if (!mode)
8909 mode = &load_detect_mode;
8910
8911 /* We need a framebuffer large enough to accommodate all accesses
8912 * that the plane may generate whilst we perform load detection.
8913 * We can not rely on the fbcon either being present (we get called
8914 * during its initialisation to detect all boot displays, or it may
8915 * not even exist) or that it is large enough to satisfy the
8916 * requested mode.
8917 */
8918 fb = mode_fits_in_fbdev(dev, mode);
8919 if (fb == NULL) {
8920 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8921 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8922 old->release_fb = fb;
8923 } else
8924 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8925 if (IS_ERR(fb)) {
8926 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8927 goto fail;
8928 }
8929
8930 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8931 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8932 if (old->release_fb)
8933 old->release_fb->funcs->destroy(old->release_fb);
8934 goto fail;
8935 }
8936 crtc->primary->crtc = crtc;
8937
8938 /* let the connector get through one full cycle before testing */
8939 intel_wait_for_vblank(dev, intel_crtc->pipe);
8940 return true;
8941
8942 fail:
8943 intel_crtc->new_enabled = crtc->state->enable;
8944 if (intel_crtc->new_enabled)
8945 intel_crtc->new_config = intel_crtc->config;
8946 else
8947 intel_crtc->new_config = NULL;
8948 fail_unlock:
8949 if (ret == -EDEADLK) {
8950 drm_modeset_backoff(ctx);
8951 goto retry;
8952 }
8953
8954 return false;
8955 }
8956
8957 void intel_release_load_detect_pipe(struct drm_connector *connector,
8958 struct intel_load_detect_pipe *old)
8959 {
8960 struct intel_encoder *intel_encoder =
8961 intel_attached_encoder(connector);
8962 struct drm_encoder *encoder = &intel_encoder->base;
8963 struct drm_crtc *crtc = encoder->crtc;
8964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8965
8966 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8967 connector->base.id, connector->name,
8968 encoder->base.id, encoder->name);
8969
8970 if (old->load_detect_temp) {
8971 to_intel_connector(connector)->new_encoder = NULL;
8972 intel_encoder->new_crtc = NULL;
8973 intel_crtc->new_enabled = false;
8974 intel_crtc->new_config = NULL;
8975 intel_set_mode(crtc, NULL, 0, 0, NULL);
8976
8977 if (old->release_fb) {
8978 drm_framebuffer_unregister_private(old->release_fb);
8979 drm_framebuffer_unreference(old->release_fb);
8980 }
8981
8982 return;
8983 }
8984
8985 /* Switch crtc and encoder back off if necessary */
8986 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8987 connector->funcs->dpms(connector, old->dpms_mode);
8988 }
8989
8990 static int i9xx_pll_refclk(struct drm_device *dev,
8991 const struct intel_crtc_state *pipe_config)
8992 {
8993 struct drm_i915_private *dev_priv = dev->dev_private;
8994 u32 dpll = pipe_config->dpll_hw_state.dpll;
8995
8996 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8997 return dev_priv->vbt.lvds_ssc_freq;
8998 else if (HAS_PCH_SPLIT(dev))
8999 return 120000;
9000 else if (!IS_GEN2(dev))
9001 return 96000;
9002 else
9003 return 48000;
9004 }
9005
9006 /* Returns the clock of the currently programmed mode of the given pipe. */
9007 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9008 struct intel_crtc_state *pipe_config)
9009 {
9010 struct drm_device *dev = crtc->base.dev;
9011 struct drm_i915_private *dev_priv = dev->dev_private;
9012 int pipe = pipe_config->cpu_transcoder;
9013 u32 dpll = pipe_config->dpll_hw_state.dpll;
9014 u32 fp;
9015 intel_clock_t clock;
9016 int refclk = i9xx_pll_refclk(dev, pipe_config);
9017
9018 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9019 fp = pipe_config->dpll_hw_state.fp0;
9020 else
9021 fp = pipe_config->dpll_hw_state.fp1;
9022
9023 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9024 if (IS_PINEVIEW(dev)) {
9025 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9026 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9027 } else {
9028 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9029 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9030 }
9031
9032 if (!IS_GEN2(dev)) {
9033 if (IS_PINEVIEW(dev))
9034 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9035 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9036 else
9037 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9038 DPLL_FPA01_P1_POST_DIV_SHIFT);
9039
9040 switch (dpll & DPLL_MODE_MASK) {
9041 case DPLLB_MODE_DAC_SERIAL:
9042 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9043 5 : 10;
9044 break;
9045 case DPLLB_MODE_LVDS:
9046 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9047 7 : 14;
9048 break;
9049 default:
9050 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9051 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9052 return;
9053 }
9054
9055 if (IS_PINEVIEW(dev))
9056 pineview_clock(refclk, &clock);
9057 else
9058 i9xx_clock(refclk, &clock);
9059 } else {
9060 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9061 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9062
9063 if (is_lvds) {
9064 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9065 DPLL_FPA01_P1_POST_DIV_SHIFT);
9066
9067 if (lvds & LVDS_CLKB_POWER_UP)
9068 clock.p2 = 7;
9069 else
9070 clock.p2 = 14;
9071 } else {
9072 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9073 clock.p1 = 2;
9074 else {
9075 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9076 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9077 }
9078 if (dpll & PLL_P2_DIVIDE_BY_4)
9079 clock.p2 = 4;
9080 else
9081 clock.p2 = 2;
9082 }
9083
9084 i9xx_clock(refclk, &clock);
9085 }
9086
9087 /*
9088 * This value includes pixel_multiplier. We will use
9089 * port_clock to compute adjusted_mode.crtc_clock in the
9090 * encoder's get_config() function.
9091 */
9092 pipe_config->port_clock = clock.dot;
9093 }
9094
9095 int intel_dotclock_calculate(int link_freq,
9096 const struct intel_link_m_n *m_n)
9097 {
9098 /*
9099 * The calculation for the data clock is:
9100 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9101 * But we want to avoid losing precison if possible, so:
9102 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9103 *
9104 * and the link clock is simpler:
9105 * link_clock = (m * link_clock) / n
9106 */
9107
9108 if (!m_n->link_n)
9109 return 0;
9110
9111 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9112 }
9113
9114 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9115 struct intel_crtc_state *pipe_config)
9116 {
9117 struct drm_device *dev = crtc->base.dev;
9118
9119 /* read out port_clock from the DPLL */
9120 i9xx_crtc_clock_get(crtc, pipe_config);
9121
9122 /*
9123 * This value does not include pixel_multiplier.
9124 * We will check that port_clock and adjusted_mode.crtc_clock
9125 * agree once we know their relationship in the encoder's
9126 * get_config() function.
9127 */
9128 pipe_config->base.adjusted_mode.crtc_clock =
9129 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9130 &pipe_config->fdi_m_n);
9131 }
9132
9133 /** Returns the currently programmed mode of the given pipe. */
9134 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9135 struct drm_crtc *crtc)
9136 {
9137 struct drm_i915_private *dev_priv = dev->dev_private;
9138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9139 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9140 struct drm_display_mode *mode;
9141 struct intel_crtc_state pipe_config;
9142 int htot = I915_READ(HTOTAL(cpu_transcoder));
9143 int hsync = I915_READ(HSYNC(cpu_transcoder));
9144 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9145 int vsync = I915_READ(VSYNC(cpu_transcoder));
9146 enum pipe pipe = intel_crtc->pipe;
9147
9148 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9149 if (!mode)
9150 return NULL;
9151
9152 /*
9153 * Construct a pipe_config sufficient for getting the clock info
9154 * back out of crtc_clock_get.
9155 *
9156 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9157 * to use a real value here instead.
9158 */
9159 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9160 pipe_config.pixel_multiplier = 1;
9161 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9162 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9163 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9164 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9165
9166 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9167 mode->hdisplay = (htot & 0xffff) + 1;
9168 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9169 mode->hsync_start = (hsync & 0xffff) + 1;
9170 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9171 mode->vdisplay = (vtot & 0xffff) + 1;
9172 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9173 mode->vsync_start = (vsync & 0xffff) + 1;
9174 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9175
9176 drm_mode_set_name(mode);
9177
9178 return mode;
9179 }
9180
9181 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9182 {
9183 struct drm_device *dev = crtc->dev;
9184 struct drm_i915_private *dev_priv = dev->dev_private;
9185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9186
9187 if (!HAS_GMCH_DISPLAY(dev))
9188 return;
9189
9190 if (!dev_priv->lvds_downclock_avail)
9191 return;
9192
9193 /*
9194 * Since this is called by a timer, we should never get here in
9195 * the manual case.
9196 */
9197 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9198 int pipe = intel_crtc->pipe;
9199 int dpll_reg = DPLL(pipe);
9200 int dpll;
9201
9202 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9203
9204 assert_panel_unlocked(dev_priv, pipe);
9205
9206 dpll = I915_READ(dpll_reg);
9207 dpll |= DISPLAY_RATE_SELECT_FPA1;
9208 I915_WRITE(dpll_reg, dpll);
9209 intel_wait_for_vblank(dev, pipe);
9210 dpll = I915_READ(dpll_reg);
9211 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9212 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9213 }
9214
9215 }
9216
9217 void intel_mark_busy(struct drm_device *dev)
9218 {
9219 struct drm_i915_private *dev_priv = dev->dev_private;
9220
9221 if (dev_priv->mm.busy)
9222 return;
9223
9224 intel_runtime_pm_get(dev_priv);
9225 i915_update_gfx_val(dev_priv);
9226 if (INTEL_INFO(dev)->gen >= 6)
9227 gen6_rps_busy(dev_priv);
9228 dev_priv->mm.busy = true;
9229 }
9230
9231 void intel_mark_idle(struct drm_device *dev)
9232 {
9233 struct drm_i915_private *dev_priv = dev->dev_private;
9234 struct drm_crtc *crtc;
9235
9236 if (!dev_priv->mm.busy)
9237 return;
9238
9239 dev_priv->mm.busy = false;
9240
9241 if (!i915.powersave)
9242 goto out;
9243
9244 for_each_crtc(dev, crtc) {
9245 if (!crtc->primary->fb)
9246 continue;
9247
9248 intel_decrease_pllclock(crtc);
9249 }
9250
9251 if (INTEL_INFO(dev)->gen >= 6)
9252 gen6_rps_idle(dev->dev_private);
9253
9254 out:
9255 intel_runtime_pm_put(dev_priv);
9256 }
9257
9258 static void intel_crtc_set_state(struct intel_crtc *crtc,
9259 struct intel_crtc_state *crtc_state)
9260 {
9261 kfree(crtc->config);
9262 crtc->config = crtc_state;
9263 crtc->base.state = &crtc_state->base;
9264 }
9265
9266 static void intel_crtc_destroy(struct drm_crtc *crtc)
9267 {
9268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9269 struct drm_device *dev = crtc->dev;
9270 struct intel_unpin_work *work;
9271
9272 spin_lock_irq(&dev->event_lock);
9273 work = intel_crtc->unpin_work;
9274 intel_crtc->unpin_work = NULL;
9275 spin_unlock_irq(&dev->event_lock);
9276
9277 if (work) {
9278 cancel_work_sync(&work->work);
9279 kfree(work);
9280 }
9281
9282 intel_crtc_set_state(intel_crtc, NULL);
9283 drm_crtc_cleanup(crtc);
9284
9285 kfree(intel_crtc);
9286 }
9287
9288 static void intel_unpin_work_fn(struct work_struct *__work)
9289 {
9290 struct intel_unpin_work *work =
9291 container_of(__work, struct intel_unpin_work, work);
9292 struct drm_device *dev = work->crtc->dev;
9293 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9294
9295 mutex_lock(&dev->struct_mutex);
9296 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9297 drm_gem_object_unreference(&work->pending_flip_obj->base);
9298
9299 intel_fbc_update(dev);
9300
9301 if (work->flip_queued_req)
9302 i915_gem_request_assign(&work->flip_queued_req, NULL);
9303 mutex_unlock(&dev->struct_mutex);
9304
9305 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9306 drm_framebuffer_unreference(work->old_fb);
9307
9308 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9309 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9310
9311 kfree(work);
9312 }
9313
9314 static void do_intel_finish_page_flip(struct drm_device *dev,
9315 struct drm_crtc *crtc)
9316 {
9317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9318 struct intel_unpin_work *work;
9319 unsigned long flags;
9320
9321 /* Ignore early vblank irqs */
9322 if (intel_crtc == NULL)
9323 return;
9324
9325 /*
9326 * This is called both by irq handlers and the reset code (to complete
9327 * lost pageflips) so needs the full irqsave spinlocks.
9328 */
9329 spin_lock_irqsave(&dev->event_lock, flags);
9330 work = intel_crtc->unpin_work;
9331
9332 /* Ensure we don't miss a work->pending update ... */
9333 smp_rmb();
9334
9335 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9336 spin_unlock_irqrestore(&dev->event_lock, flags);
9337 return;
9338 }
9339
9340 page_flip_completed(intel_crtc);
9341
9342 spin_unlock_irqrestore(&dev->event_lock, flags);
9343 }
9344
9345 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9346 {
9347 struct drm_i915_private *dev_priv = dev->dev_private;
9348 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9349
9350 do_intel_finish_page_flip(dev, crtc);
9351 }
9352
9353 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9354 {
9355 struct drm_i915_private *dev_priv = dev->dev_private;
9356 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9357
9358 do_intel_finish_page_flip(dev, crtc);
9359 }
9360
9361 /* Is 'a' after or equal to 'b'? */
9362 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9363 {
9364 return !((a - b) & 0x80000000);
9365 }
9366
9367 static bool page_flip_finished(struct intel_crtc *crtc)
9368 {
9369 struct drm_device *dev = crtc->base.dev;
9370 struct drm_i915_private *dev_priv = dev->dev_private;
9371
9372 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9373 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9374 return true;
9375
9376 /*
9377 * The relevant registers doen't exist on pre-ctg.
9378 * As the flip done interrupt doesn't trigger for mmio
9379 * flips on gmch platforms, a flip count check isn't
9380 * really needed there. But since ctg has the registers,
9381 * include it in the check anyway.
9382 */
9383 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9384 return true;
9385
9386 /*
9387 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9388 * used the same base address. In that case the mmio flip might
9389 * have completed, but the CS hasn't even executed the flip yet.
9390 *
9391 * A flip count check isn't enough as the CS might have updated
9392 * the base address just after start of vblank, but before we
9393 * managed to process the interrupt. This means we'd complete the
9394 * CS flip too soon.
9395 *
9396 * Combining both checks should get us a good enough result. It may
9397 * still happen that the CS flip has been executed, but has not
9398 * yet actually completed. But in case the base address is the same
9399 * anyway, we don't really care.
9400 */
9401 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9402 crtc->unpin_work->gtt_offset &&
9403 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9404 crtc->unpin_work->flip_count);
9405 }
9406
9407 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9408 {
9409 struct drm_i915_private *dev_priv = dev->dev_private;
9410 struct intel_crtc *intel_crtc =
9411 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9412 unsigned long flags;
9413
9414
9415 /*
9416 * This is called both by irq handlers and the reset code (to complete
9417 * lost pageflips) so needs the full irqsave spinlocks.
9418 *
9419 * NB: An MMIO update of the plane base pointer will also
9420 * generate a page-flip completion irq, i.e. every modeset
9421 * is also accompanied by a spurious intel_prepare_page_flip().
9422 */
9423 spin_lock_irqsave(&dev->event_lock, flags);
9424 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9425 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9426 spin_unlock_irqrestore(&dev->event_lock, flags);
9427 }
9428
9429 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9430 {
9431 /* Ensure that the work item is consistent when activating it ... */
9432 smp_wmb();
9433 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9434 /* and that it is marked active as soon as the irq could fire. */
9435 smp_wmb();
9436 }
9437
9438 static int intel_gen2_queue_flip(struct drm_device *dev,
9439 struct drm_crtc *crtc,
9440 struct drm_framebuffer *fb,
9441 struct drm_i915_gem_object *obj,
9442 struct intel_engine_cs *ring,
9443 uint32_t flags)
9444 {
9445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9446 u32 flip_mask;
9447 int ret;
9448
9449 ret = intel_ring_begin(ring, 6);
9450 if (ret)
9451 return ret;
9452
9453 /* Can't queue multiple flips, so wait for the previous
9454 * one to finish before executing the next.
9455 */
9456 if (intel_crtc->plane)
9457 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9458 else
9459 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9460 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9461 intel_ring_emit(ring, MI_NOOP);
9462 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9463 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9464 intel_ring_emit(ring, fb->pitches[0]);
9465 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9466 intel_ring_emit(ring, 0); /* aux display base address, unused */
9467
9468 intel_mark_page_flip_active(intel_crtc);
9469 __intel_ring_advance(ring);
9470 return 0;
9471 }
9472
9473 static int intel_gen3_queue_flip(struct drm_device *dev,
9474 struct drm_crtc *crtc,
9475 struct drm_framebuffer *fb,
9476 struct drm_i915_gem_object *obj,
9477 struct intel_engine_cs *ring,
9478 uint32_t flags)
9479 {
9480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9481 u32 flip_mask;
9482 int ret;
9483
9484 ret = intel_ring_begin(ring, 6);
9485 if (ret)
9486 return ret;
9487
9488 if (intel_crtc->plane)
9489 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9490 else
9491 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9492 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9493 intel_ring_emit(ring, MI_NOOP);
9494 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9495 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9496 intel_ring_emit(ring, fb->pitches[0]);
9497 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9498 intel_ring_emit(ring, MI_NOOP);
9499
9500 intel_mark_page_flip_active(intel_crtc);
9501 __intel_ring_advance(ring);
9502 return 0;
9503 }
9504
9505 static int intel_gen4_queue_flip(struct drm_device *dev,
9506 struct drm_crtc *crtc,
9507 struct drm_framebuffer *fb,
9508 struct drm_i915_gem_object *obj,
9509 struct intel_engine_cs *ring,
9510 uint32_t flags)
9511 {
9512 struct drm_i915_private *dev_priv = dev->dev_private;
9513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9514 uint32_t pf, pipesrc;
9515 int ret;
9516
9517 ret = intel_ring_begin(ring, 4);
9518 if (ret)
9519 return ret;
9520
9521 /* i965+ uses the linear or tiled offsets from the
9522 * Display Registers (which do not change across a page-flip)
9523 * so we need only reprogram the base address.
9524 */
9525 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9526 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9527 intel_ring_emit(ring, fb->pitches[0]);
9528 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9529 obj->tiling_mode);
9530
9531 /* XXX Enabling the panel-fitter across page-flip is so far
9532 * untested on non-native modes, so ignore it for now.
9533 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9534 */
9535 pf = 0;
9536 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9537 intel_ring_emit(ring, pf | pipesrc);
9538
9539 intel_mark_page_flip_active(intel_crtc);
9540 __intel_ring_advance(ring);
9541 return 0;
9542 }
9543
9544 static int intel_gen6_queue_flip(struct drm_device *dev,
9545 struct drm_crtc *crtc,
9546 struct drm_framebuffer *fb,
9547 struct drm_i915_gem_object *obj,
9548 struct intel_engine_cs *ring,
9549 uint32_t flags)
9550 {
9551 struct drm_i915_private *dev_priv = dev->dev_private;
9552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9553 uint32_t pf, pipesrc;
9554 int ret;
9555
9556 ret = intel_ring_begin(ring, 4);
9557 if (ret)
9558 return ret;
9559
9560 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9561 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9562 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9563 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9564
9565 /* Contrary to the suggestions in the documentation,
9566 * "Enable Panel Fitter" does not seem to be required when page
9567 * flipping with a non-native mode, and worse causes a normal
9568 * modeset to fail.
9569 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9570 */
9571 pf = 0;
9572 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9573 intel_ring_emit(ring, pf | pipesrc);
9574
9575 intel_mark_page_flip_active(intel_crtc);
9576 __intel_ring_advance(ring);
9577 return 0;
9578 }
9579
9580 static int intel_gen7_queue_flip(struct drm_device *dev,
9581 struct drm_crtc *crtc,
9582 struct drm_framebuffer *fb,
9583 struct drm_i915_gem_object *obj,
9584 struct intel_engine_cs *ring,
9585 uint32_t flags)
9586 {
9587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9588 uint32_t plane_bit = 0;
9589 int len, ret;
9590
9591 switch (intel_crtc->plane) {
9592 case PLANE_A:
9593 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9594 break;
9595 case PLANE_B:
9596 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9597 break;
9598 case PLANE_C:
9599 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9600 break;
9601 default:
9602 WARN_ONCE(1, "unknown plane in flip command\n");
9603 return -ENODEV;
9604 }
9605
9606 len = 4;
9607 if (ring->id == RCS) {
9608 len += 6;
9609 /*
9610 * On Gen 8, SRM is now taking an extra dword to accommodate
9611 * 48bits addresses, and we need a NOOP for the batch size to
9612 * stay even.
9613 */
9614 if (IS_GEN8(dev))
9615 len += 2;
9616 }
9617
9618 /*
9619 * BSpec MI_DISPLAY_FLIP for IVB:
9620 * "The full packet must be contained within the same cache line."
9621 *
9622 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9623 * cacheline, if we ever start emitting more commands before
9624 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9625 * then do the cacheline alignment, and finally emit the
9626 * MI_DISPLAY_FLIP.
9627 */
9628 ret = intel_ring_cacheline_align(ring);
9629 if (ret)
9630 return ret;
9631
9632 ret = intel_ring_begin(ring, len);
9633 if (ret)
9634 return ret;
9635
9636 /* Unmask the flip-done completion message. Note that the bspec says that
9637 * we should do this for both the BCS and RCS, and that we must not unmask
9638 * more than one flip event at any time (or ensure that one flip message
9639 * can be sent by waiting for flip-done prior to queueing new flips).
9640 * Experimentation says that BCS works despite DERRMR masking all
9641 * flip-done completion events and that unmasking all planes at once
9642 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9643 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9644 */
9645 if (ring->id == RCS) {
9646 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9647 intel_ring_emit(ring, DERRMR);
9648 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9649 DERRMR_PIPEB_PRI_FLIP_DONE |
9650 DERRMR_PIPEC_PRI_FLIP_DONE));
9651 if (IS_GEN8(dev))
9652 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9653 MI_SRM_LRM_GLOBAL_GTT);
9654 else
9655 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9656 MI_SRM_LRM_GLOBAL_GTT);
9657 intel_ring_emit(ring, DERRMR);
9658 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9659 if (IS_GEN8(dev)) {
9660 intel_ring_emit(ring, 0);
9661 intel_ring_emit(ring, MI_NOOP);
9662 }
9663 }
9664
9665 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9666 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9667 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9668 intel_ring_emit(ring, (MI_NOOP));
9669
9670 intel_mark_page_flip_active(intel_crtc);
9671 __intel_ring_advance(ring);
9672 return 0;
9673 }
9674
9675 static bool use_mmio_flip(struct intel_engine_cs *ring,
9676 struct drm_i915_gem_object *obj)
9677 {
9678 /*
9679 * This is not being used for older platforms, because
9680 * non-availability of flip done interrupt forces us to use
9681 * CS flips. Older platforms derive flip done using some clever
9682 * tricks involving the flip_pending status bits and vblank irqs.
9683 * So using MMIO flips there would disrupt this mechanism.
9684 */
9685
9686 if (ring == NULL)
9687 return true;
9688
9689 if (INTEL_INFO(ring->dev)->gen < 5)
9690 return false;
9691
9692 if (i915.use_mmio_flip < 0)
9693 return false;
9694 else if (i915.use_mmio_flip > 0)
9695 return true;
9696 else if (i915.enable_execlists)
9697 return true;
9698 else
9699 return ring != i915_gem_request_get_ring(obj->last_read_req);
9700 }
9701
9702 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9703 {
9704 struct drm_device *dev = intel_crtc->base.dev;
9705 struct drm_i915_private *dev_priv = dev->dev_private;
9706 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9707 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9708 struct drm_i915_gem_object *obj = intel_fb->obj;
9709 const enum pipe pipe = intel_crtc->pipe;
9710 u32 ctl, stride;
9711
9712 ctl = I915_READ(PLANE_CTL(pipe, 0));
9713 ctl &= ~PLANE_CTL_TILED_MASK;
9714 if (obj->tiling_mode == I915_TILING_X)
9715 ctl |= PLANE_CTL_TILED_X;
9716
9717 /*
9718 * The stride is either expressed as a multiple of 64 bytes chunks for
9719 * linear buffers or in number of tiles for tiled buffers.
9720 */
9721 stride = fb->pitches[0] >> 6;
9722 if (obj->tiling_mode == I915_TILING_X)
9723 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9724
9725 /*
9726 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9727 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9728 */
9729 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9730 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9731
9732 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9733 POSTING_READ(PLANE_SURF(pipe, 0));
9734 }
9735
9736 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9737 {
9738 struct drm_device *dev = intel_crtc->base.dev;
9739 struct drm_i915_private *dev_priv = dev->dev_private;
9740 struct intel_framebuffer *intel_fb =
9741 to_intel_framebuffer(intel_crtc->base.primary->fb);
9742 struct drm_i915_gem_object *obj = intel_fb->obj;
9743 u32 dspcntr;
9744 u32 reg;
9745
9746 reg = DSPCNTR(intel_crtc->plane);
9747 dspcntr = I915_READ(reg);
9748
9749 if (obj->tiling_mode != I915_TILING_NONE)
9750 dspcntr |= DISPPLANE_TILED;
9751 else
9752 dspcntr &= ~DISPPLANE_TILED;
9753
9754 I915_WRITE(reg, dspcntr);
9755
9756 I915_WRITE(DSPSURF(intel_crtc->plane),
9757 intel_crtc->unpin_work->gtt_offset);
9758 POSTING_READ(DSPSURF(intel_crtc->plane));
9759
9760 }
9761
9762 /*
9763 * XXX: This is the temporary way to update the plane registers until we get
9764 * around to using the usual plane update functions for MMIO flips
9765 */
9766 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9767 {
9768 struct drm_device *dev = intel_crtc->base.dev;
9769 bool atomic_update;
9770 u32 start_vbl_count;
9771
9772 intel_mark_page_flip_active(intel_crtc);
9773
9774 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9775
9776 if (INTEL_INFO(dev)->gen >= 9)
9777 skl_do_mmio_flip(intel_crtc);
9778 else
9779 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9780 ilk_do_mmio_flip(intel_crtc);
9781
9782 if (atomic_update)
9783 intel_pipe_update_end(intel_crtc, start_vbl_count);
9784 }
9785
9786 static void intel_mmio_flip_work_func(struct work_struct *work)
9787 {
9788 struct intel_crtc *crtc =
9789 container_of(work, struct intel_crtc, mmio_flip.work);
9790 struct intel_mmio_flip *mmio_flip;
9791
9792 mmio_flip = &crtc->mmio_flip;
9793 if (mmio_flip->req)
9794 WARN_ON(__i915_wait_request(mmio_flip->req,
9795 crtc->reset_counter,
9796 false, NULL, NULL) != 0);
9797
9798 intel_do_mmio_flip(crtc);
9799 if (mmio_flip->req) {
9800 mutex_lock(&crtc->base.dev->struct_mutex);
9801 i915_gem_request_assign(&mmio_flip->req, NULL);
9802 mutex_unlock(&crtc->base.dev->struct_mutex);
9803 }
9804 }
9805
9806 static int intel_queue_mmio_flip(struct drm_device *dev,
9807 struct drm_crtc *crtc,
9808 struct drm_framebuffer *fb,
9809 struct drm_i915_gem_object *obj,
9810 struct intel_engine_cs *ring,
9811 uint32_t flags)
9812 {
9813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9814
9815 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9816 obj->last_write_req);
9817
9818 schedule_work(&intel_crtc->mmio_flip.work);
9819
9820 return 0;
9821 }
9822
9823 static int intel_default_queue_flip(struct drm_device *dev,
9824 struct drm_crtc *crtc,
9825 struct drm_framebuffer *fb,
9826 struct drm_i915_gem_object *obj,
9827 struct intel_engine_cs *ring,
9828 uint32_t flags)
9829 {
9830 return -ENODEV;
9831 }
9832
9833 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9834 struct drm_crtc *crtc)
9835 {
9836 struct drm_i915_private *dev_priv = dev->dev_private;
9837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9838 struct intel_unpin_work *work = intel_crtc->unpin_work;
9839 u32 addr;
9840
9841 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9842 return true;
9843
9844 if (!work->enable_stall_check)
9845 return false;
9846
9847 if (work->flip_ready_vblank == 0) {
9848 if (work->flip_queued_req &&
9849 !i915_gem_request_completed(work->flip_queued_req, true))
9850 return false;
9851
9852 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9853 }
9854
9855 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9856 return false;
9857
9858 /* Potential stall - if we see that the flip has happened,
9859 * assume a missed interrupt. */
9860 if (INTEL_INFO(dev)->gen >= 4)
9861 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9862 else
9863 addr = I915_READ(DSPADDR(intel_crtc->plane));
9864
9865 /* There is a potential issue here with a false positive after a flip
9866 * to the same address. We could address this by checking for a
9867 * non-incrementing frame counter.
9868 */
9869 return addr == work->gtt_offset;
9870 }
9871
9872 void intel_check_page_flip(struct drm_device *dev, int pipe)
9873 {
9874 struct drm_i915_private *dev_priv = dev->dev_private;
9875 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9877
9878 WARN_ON(!in_interrupt());
9879
9880 if (crtc == NULL)
9881 return;
9882
9883 spin_lock(&dev->event_lock);
9884 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9885 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9886 intel_crtc->unpin_work->flip_queued_vblank,
9887 drm_vblank_count(dev, pipe));
9888 page_flip_completed(intel_crtc);
9889 }
9890 spin_unlock(&dev->event_lock);
9891 }
9892
9893 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9894 struct drm_framebuffer *fb,
9895 struct drm_pending_vblank_event *event,
9896 uint32_t page_flip_flags)
9897 {
9898 struct drm_device *dev = crtc->dev;
9899 struct drm_i915_private *dev_priv = dev->dev_private;
9900 struct drm_framebuffer *old_fb = crtc->primary->fb;
9901 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9903 struct drm_plane *primary = crtc->primary;
9904 enum pipe pipe = intel_crtc->pipe;
9905 struct intel_unpin_work *work;
9906 struct intel_engine_cs *ring;
9907 int ret;
9908
9909 /*
9910 * drm_mode_page_flip_ioctl() should already catch this, but double
9911 * check to be safe. In the future we may enable pageflipping from
9912 * a disabled primary plane.
9913 */
9914 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9915 return -EBUSY;
9916
9917 /* Can't change pixel format via MI display flips. */
9918 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9919 return -EINVAL;
9920
9921 /*
9922 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9923 * Note that pitch changes could also affect these register.
9924 */
9925 if (INTEL_INFO(dev)->gen > 3 &&
9926 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9927 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9928 return -EINVAL;
9929
9930 if (i915_terminally_wedged(&dev_priv->gpu_error))
9931 goto out_hang;
9932
9933 work = kzalloc(sizeof(*work), GFP_KERNEL);
9934 if (work == NULL)
9935 return -ENOMEM;
9936
9937 work->event = event;
9938 work->crtc = crtc;
9939 work->old_fb = old_fb;
9940 INIT_WORK(&work->work, intel_unpin_work_fn);
9941
9942 ret = drm_crtc_vblank_get(crtc);
9943 if (ret)
9944 goto free_work;
9945
9946 /* We borrow the event spin lock for protecting unpin_work */
9947 spin_lock_irq(&dev->event_lock);
9948 if (intel_crtc->unpin_work) {
9949 /* Before declaring the flip queue wedged, check if
9950 * the hardware completed the operation behind our backs.
9951 */
9952 if (__intel_pageflip_stall_check(dev, crtc)) {
9953 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9954 page_flip_completed(intel_crtc);
9955 } else {
9956 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9957 spin_unlock_irq(&dev->event_lock);
9958
9959 drm_crtc_vblank_put(crtc);
9960 kfree(work);
9961 return -EBUSY;
9962 }
9963 }
9964 intel_crtc->unpin_work = work;
9965 spin_unlock_irq(&dev->event_lock);
9966
9967 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9968 flush_workqueue(dev_priv->wq);
9969
9970 /* Reference the objects for the scheduled work. */
9971 drm_framebuffer_reference(work->old_fb);
9972 drm_gem_object_reference(&obj->base);
9973
9974 crtc->primary->fb = fb;
9975 update_state_fb(crtc->primary);
9976
9977 work->pending_flip_obj = obj;
9978
9979 ret = i915_mutex_lock_interruptible(dev);
9980 if (ret)
9981 goto cleanup;
9982
9983 atomic_inc(&intel_crtc->unpin_work_count);
9984 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9985
9986 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9987 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9988
9989 if (IS_VALLEYVIEW(dev)) {
9990 ring = &dev_priv->ring[BCS];
9991 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9992 /* vlv: DISPLAY_FLIP fails to change tiling */
9993 ring = NULL;
9994 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9995 ring = &dev_priv->ring[BCS];
9996 } else if (INTEL_INFO(dev)->gen >= 7) {
9997 ring = i915_gem_request_get_ring(obj->last_read_req);
9998 if (ring == NULL || ring->id != RCS)
9999 ring = &dev_priv->ring[BCS];
10000 } else {
10001 ring = &dev_priv->ring[RCS];
10002 }
10003
10004 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
10005 if (ret)
10006 goto cleanup_pending;
10007
10008 work->gtt_offset =
10009 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10010
10011 if (use_mmio_flip(ring, obj)) {
10012 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10013 page_flip_flags);
10014 if (ret)
10015 goto cleanup_unpin;
10016
10017 i915_gem_request_assign(&work->flip_queued_req,
10018 obj->last_write_req);
10019 } else {
10020 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10021 page_flip_flags);
10022 if (ret)
10023 goto cleanup_unpin;
10024
10025 i915_gem_request_assign(&work->flip_queued_req,
10026 intel_ring_get_request(ring));
10027 }
10028
10029 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10030 work->enable_stall_check = true;
10031
10032 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10033 INTEL_FRONTBUFFER_PRIMARY(pipe));
10034
10035 intel_fbc_disable(dev);
10036 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10037 mutex_unlock(&dev->struct_mutex);
10038
10039 trace_i915_flip_request(intel_crtc->plane, obj);
10040
10041 return 0;
10042
10043 cleanup_unpin:
10044 intel_unpin_fb_obj(obj);
10045 cleanup_pending:
10046 atomic_dec(&intel_crtc->unpin_work_count);
10047 mutex_unlock(&dev->struct_mutex);
10048 cleanup:
10049 crtc->primary->fb = old_fb;
10050 update_state_fb(crtc->primary);
10051
10052 drm_gem_object_unreference_unlocked(&obj->base);
10053 drm_framebuffer_unreference(work->old_fb);
10054
10055 spin_lock_irq(&dev->event_lock);
10056 intel_crtc->unpin_work = NULL;
10057 spin_unlock_irq(&dev->event_lock);
10058
10059 drm_crtc_vblank_put(crtc);
10060 free_work:
10061 kfree(work);
10062
10063 if (ret == -EIO) {
10064 out_hang:
10065 ret = intel_plane_restore(primary);
10066 if (ret == 0 && event) {
10067 spin_lock_irq(&dev->event_lock);
10068 drm_send_vblank_event(dev, pipe, event);
10069 spin_unlock_irq(&dev->event_lock);
10070 }
10071 }
10072 return ret;
10073 }
10074
10075 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10076 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10077 .load_lut = intel_crtc_load_lut,
10078 .atomic_begin = intel_begin_crtc_commit,
10079 .atomic_flush = intel_finish_crtc_commit,
10080 };
10081
10082 /**
10083 * intel_modeset_update_staged_output_state
10084 *
10085 * Updates the staged output configuration state, e.g. after we've read out the
10086 * current hw state.
10087 */
10088 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10089 {
10090 struct intel_crtc *crtc;
10091 struct intel_encoder *encoder;
10092 struct intel_connector *connector;
10093
10094 for_each_intel_connector(dev, connector) {
10095 connector->new_encoder =
10096 to_intel_encoder(connector->base.encoder);
10097 }
10098
10099 for_each_intel_encoder(dev, encoder) {
10100 encoder->new_crtc =
10101 to_intel_crtc(encoder->base.crtc);
10102 }
10103
10104 for_each_intel_crtc(dev, crtc) {
10105 crtc->new_enabled = crtc->base.state->enable;
10106
10107 if (crtc->new_enabled)
10108 crtc->new_config = crtc->config;
10109 else
10110 crtc->new_config = NULL;
10111 }
10112 }
10113
10114 /**
10115 * intel_modeset_commit_output_state
10116 *
10117 * This function copies the stage display pipe configuration to the real one.
10118 */
10119 static void intel_modeset_commit_output_state(struct drm_device *dev)
10120 {
10121 struct intel_crtc *crtc;
10122 struct intel_encoder *encoder;
10123 struct intel_connector *connector;
10124
10125 for_each_intel_connector(dev, connector) {
10126 connector->base.encoder = &connector->new_encoder->base;
10127 }
10128
10129 for_each_intel_encoder(dev, encoder) {
10130 encoder->base.crtc = &encoder->new_crtc->base;
10131 }
10132
10133 for_each_intel_crtc(dev, crtc) {
10134 crtc->base.state->enable = crtc->new_enabled;
10135 crtc->base.enabled = crtc->new_enabled;
10136 }
10137 }
10138
10139 static void
10140 connected_sink_compute_bpp(struct intel_connector *connector,
10141 struct intel_crtc_state *pipe_config)
10142 {
10143 int bpp = pipe_config->pipe_bpp;
10144
10145 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10146 connector->base.base.id,
10147 connector->base.name);
10148
10149 /* Don't use an invalid EDID bpc value */
10150 if (connector->base.display_info.bpc &&
10151 connector->base.display_info.bpc * 3 < bpp) {
10152 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10153 bpp, connector->base.display_info.bpc*3);
10154 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10155 }
10156
10157 /* Clamp bpp to 8 on screens without EDID 1.4 */
10158 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10159 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10160 bpp);
10161 pipe_config->pipe_bpp = 24;
10162 }
10163 }
10164
10165 static int
10166 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10167 struct drm_framebuffer *fb,
10168 struct intel_crtc_state *pipe_config)
10169 {
10170 struct drm_device *dev = crtc->base.dev;
10171 struct intel_connector *connector;
10172 int bpp;
10173
10174 switch (fb->pixel_format) {
10175 case DRM_FORMAT_C8:
10176 bpp = 8*3; /* since we go through a colormap */
10177 break;
10178 case DRM_FORMAT_XRGB1555:
10179 case DRM_FORMAT_ARGB1555:
10180 /* checked in intel_framebuffer_init already */
10181 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10182 return -EINVAL;
10183 case DRM_FORMAT_RGB565:
10184 bpp = 6*3; /* min is 18bpp */
10185 break;
10186 case DRM_FORMAT_XBGR8888:
10187 case DRM_FORMAT_ABGR8888:
10188 /* checked in intel_framebuffer_init already */
10189 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10190 return -EINVAL;
10191 case DRM_FORMAT_XRGB8888:
10192 case DRM_FORMAT_ARGB8888:
10193 bpp = 8*3;
10194 break;
10195 case DRM_FORMAT_XRGB2101010:
10196 case DRM_FORMAT_ARGB2101010:
10197 case DRM_FORMAT_XBGR2101010:
10198 case DRM_FORMAT_ABGR2101010:
10199 /* checked in intel_framebuffer_init already */
10200 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10201 return -EINVAL;
10202 bpp = 10*3;
10203 break;
10204 /* TODO: gen4+ supports 16 bpc floating point, too. */
10205 default:
10206 DRM_DEBUG_KMS("unsupported depth\n");
10207 return -EINVAL;
10208 }
10209
10210 pipe_config->pipe_bpp = bpp;
10211
10212 /* Clamp display bpp to EDID value */
10213 for_each_intel_connector(dev, connector) {
10214 if (!connector->new_encoder ||
10215 connector->new_encoder->new_crtc != crtc)
10216 continue;
10217
10218 connected_sink_compute_bpp(connector, pipe_config);
10219 }
10220
10221 return bpp;
10222 }
10223
10224 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10225 {
10226 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10227 "type: 0x%x flags: 0x%x\n",
10228 mode->crtc_clock,
10229 mode->crtc_hdisplay, mode->crtc_hsync_start,
10230 mode->crtc_hsync_end, mode->crtc_htotal,
10231 mode->crtc_vdisplay, mode->crtc_vsync_start,
10232 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10233 }
10234
10235 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10236 struct intel_crtc_state *pipe_config,
10237 const char *context)
10238 {
10239 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10240 context, pipe_name(crtc->pipe));
10241
10242 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10243 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10244 pipe_config->pipe_bpp, pipe_config->dither);
10245 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10246 pipe_config->has_pch_encoder,
10247 pipe_config->fdi_lanes,
10248 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10249 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10250 pipe_config->fdi_m_n.tu);
10251 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10252 pipe_config->has_dp_encoder,
10253 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10254 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10255 pipe_config->dp_m_n.tu);
10256
10257 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10258 pipe_config->has_dp_encoder,
10259 pipe_config->dp_m2_n2.gmch_m,
10260 pipe_config->dp_m2_n2.gmch_n,
10261 pipe_config->dp_m2_n2.link_m,
10262 pipe_config->dp_m2_n2.link_n,
10263 pipe_config->dp_m2_n2.tu);
10264
10265 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10266 pipe_config->has_audio,
10267 pipe_config->has_infoframe);
10268
10269 DRM_DEBUG_KMS("requested mode:\n");
10270 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10271 DRM_DEBUG_KMS("adjusted mode:\n");
10272 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10273 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10274 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10275 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10276 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10277 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10278 pipe_config->gmch_pfit.control,
10279 pipe_config->gmch_pfit.pgm_ratios,
10280 pipe_config->gmch_pfit.lvds_border_bits);
10281 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10282 pipe_config->pch_pfit.pos,
10283 pipe_config->pch_pfit.size,
10284 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10285 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10286 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10287 }
10288
10289 static bool encoders_cloneable(const struct intel_encoder *a,
10290 const struct intel_encoder *b)
10291 {
10292 /* masks could be asymmetric, so check both ways */
10293 return a == b || (a->cloneable & (1 << b->type) &&
10294 b->cloneable & (1 << a->type));
10295 }
10296
10297 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10298 struct intel_encoder *encoder)
10299 {
10300 struct drm_device *dev = crtc->base.dev;
10301 struct intel_encoder *source_encoder;
10302
10303 for_each_intel_encoder(dev, source_encoder) {
10304 if (source_encoder->new_crtc != crtc)
10305 continue;
10306
10307 if (!encoders_cloneable(encoder, source_encoder))
10308 return false;
10309 }
10310
10311 return true;
10312 }
10313
10314 static bool check_encoder_cloning(struct intel_crtc *crtc)
10315 {
10316 struct drm_device *dev = crtc->base.dev;
10317 struct intel_encoder *encoder;
10318
10319 for_each_intel_encoder(dev, encoder) {
10320 if (encoder->new_crtc != crtc)
10321 continue;
10322
10323 if (!check_single_encoder_cloning(crtc, encoder))
10324 return false;
10325 }
10326
10327 return true;
10328 }
10329
10330 static bool check_digital_port_conflicts(struct drm_device *dev)
10331 {
10332 struct intel_connector *connector;
10333 unsigned int used_ports = 0;
10334
10335 /*
10336 * Walk the connector list instead of the encoder
10337 * list to detect the problem on ddi platforms
10338 * where there's just one encoder per digital port.
10339 */
10340 for_each_intel_connector(dev, connector) {
10341 struct intel_encoder *encoder = connector->new_encoder;
10342
10343 if (!encoder)
10344 continue;
10345
10346 WARN_ON(!encoder->new_crtc);
10347
10348 switch (encoder->type) {
10349 unsigned int port_mask;
10350 case INTEL_OUTPUT_UNKNOWN:
10351 if (WARN_ON(!HAS_DDI(dev)))
10352 break;
10353 case INTEL_OUTPUT_DISPLAYPORT:
10354 case INTEL_OUTPUT_HDMI:
10355 case INTEL_OUTPUT_EDP:
10356 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10357
10358 /* the same port mustn't appear more than once */
10359 if (used_ports & port_mask)
10360 return false;
10361
10362 used_ports |= port_mask;
10363 default:
10364 break;
10365 }
10366 }
10367
10368 return true;
10369 }
10370
10371 static struct intel_crtc_state *
10372 intel_modeset_pipe_config(struct drm_crtc *crtc,
10373 struct drm_framebuffer *fb,
10374 struct drm_display_mode *mode)
10375 {
10376 struct drm_device *dev = crtc->dev;
10377 struct intel_encoder *encoder;
10378 struct intel_crtc_state *pipe_config;
10379 int plane_bpp, ret = -EINVAL;
10380 bool retry = true;
10381
10382 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10383 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10384 return ERR_PTR(-EINVAL);
10385 }
10386
10387 if (!check_digital_port_conflicts(dev)) {
10388 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10389 return ERR_PTR(-EINVAL);
10390 }
10391
10392 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10393 if (!pipe_config)
10394 return ERR_PTR(-ENOMEM);
10395
10396 pipe_config->base.crtc = crtc;
10397 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10398 drm_mode_copy(&pipe_config->base.mode, mode);
10399
10400 pipe_config->cpu_transcoder =
10401 (enum transcoder) to_intel_crtc(crtc)->pipe;
10402 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10403
10404 /*
10405 * Sanitize sync polarity flags based on requested ones. If neither
10406 * positive or negative polarity is requested, treat this as meaning
10407 * negative polarity.
10408 */
10409 if (!(pipe_config->base.adjusted_mode.flags &
10410 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10411 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10412
10413 if (!(pipe_config->base.adjusted_mode.flags &
10414 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10415 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10416
10417 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10418 * plane pixel format and any sink constraints into account. Returns the
10419 * source plane bpp so that dithering can be selected on mismatches
10420 * after encoders and crtc also have had their say. */
10421 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10422 fb, pipe_config);
10423 if (plane_bpp < 0)
10424 goto fail;
10425
10426 /*
10427 * Determine the real pipe dimensions. Note that stereo modes can
10428 * increase the actual pipe size due to the frame doubling and
10429 * insertion of additional space for blanks between the frame. This
10430 * is stored in the crtc timings. We use the requested mode to do this
10431 * computation to clearly distinguish it from the adjusted mode, which
10432 * can be changed by the connectors in the below retry loop.
10433 */
10434 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10435 &pipe_config->pipe_src_w,
10436 &pipe_config->pipe_src_h);
10437
10438 encoder_retry:
10439 /* Ensure the port clock defaults are reset when retrying. */
10440 pipe_config->port_clock = 0;
10441 pipe_config->pixel_multiplier = 1;
10442
10443 /* Fill in default crtc timings, allow encoders to overwrite them. */
10444 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10445 CRTC_STEREO_DOUBLE);
10446
10447 /* Pass our mode to the connectors and the CRTC to give them a chance to
10448 * adjust it according to limitations or connector properties, and also
10449 * a chance to reject the mode entirely.
10450 */
10451 for_each_intel_encoder(dev, encoder) {
10452
10453 if (&encoder->new_crtc->base != crtc)
10454 continue;
10455
10456 if (!(encoder->compute_config(encoder, pipe_config))) {
10457 DRM_DEBUG_KMS("Encoder config failure\n");
10458 goto fail;
10459 }
10460 }
10461
10462 /* Set default port clock if not overwritten by the encoder. Needs to be
10463 * done afterwards in case the encoder adjusts the mode. */
10464 if (!pipe_config->port_clock)
10465 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10466 * pipe_config->pixel_multiplier;
10467
10468 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10469 if (ret < 0) {
10470 DRM_DEBUG_KMS("CRTC fixup failed\n");
10471 goto fail;
10472 }
10473
10474 if (ret == RETRY) {
10475 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10476 ret = -EINVAL;
10477 goto fail;
10478 }
10479
10480 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10481 retry = false;
10482 goto encoder_retry;
10483 }
10484
10485 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10486 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10487 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10488
10489 return pipe_config;
10490 fail:
10491 kfree(pipe_config);
10492 return ERR_PTR(ret);
10493 }
10494
10495 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10496 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10497 static void
10498 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10499 unsigned *prepare_pipes, unsigned *disable_pipes)
10500 {
10501 struct intel_crtc *intel_crtc;
10502 struct drm_device *dev = crtc->dev;
10503 struct intel_encoder *encoder;
10504 struct intel_connector *connector;
10505 struct drm_crtc *tmp_crtc;
10506
10507 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10508
10509 /* Check which crtcs have changed outputs connected to them, these need
10510 * to be part of the prepare_pipes mask. We don't (yet) support global
10511 * modeset across multiple crtcs, so modeset_pipes will only have one
10512 * bit set at most. */
10513 for_each_intel_connector(dev, connector) {
10514 if (connector->base.encoder == &connector->new_encoder->base)
10515 continue;
10516
10517 if (connector->base.encoder) {
10518 tmp_crtc = connector->base.encoder->crtc;
10519
10520 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10521 }
10522
10523 if (connector->new_encoder)
10524 *prepare_pipes |=
10525 1 << connector->new_encoder->new_crtc->pipe;
10526 }
10527
10528 for_each_intel_encoder(dev, encoder) {
10529 if (encoder->base.crtc == &encoder->new_crtc->base)
10530 continue;
10531
10532 if (encoder->base.crtc) {
10533 tmp_crtc = encoder->base.crtc;
10534
10535 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10536 }
10537
10538 if (encoder->new_crtc)
10539 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10540 }
10541
10542 /* Check for pipes that will be enabled/disabled ... */
10543 for_each_intel_crtc(dev, intel_crtc) {
10544 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10545 continue;
10546
10547 if (!intel_crtc->new_enabled)
10548 *disable_pipes |= 1 << intel_crtc->pipe;
10549 else
10550 *prepare_pipes |= 1 << intel_crtc->pipe;
10551 }
10552
10553
10554 /* set_mode is also used to update properties on life display pipes. */
10555 intel_crtc = to_intel_crtc(crtc);
10556 if (intel_crtc->new_enabled)
10557 *prepare_pipes |= 1 << intel_crtc->pipe;
10558
10559 /*
10560 * For simplicity do a full modeset on any pipe where the output routing
10561 * changed. We could be more clever, but that would require us to be
10562 * more careful with calling the relevant encoder->mode_set functions.
10563 */
10564 if (*prepare_pipes)
10565 *modeset_pipes = *prepare_pipes;
10566
10567 /* ... and mask these out. */
10568 *modeset_pipes &= ~(*disable_pipes);
10569 *prepare_pipes &= ~(*disable_pipes);
10570
10571 /*
10572 * HACK: We don't (yet) fully support global modesets. intel_set_config
10573 * obies this rule, but the modeset restore mode of
10574 * intel_modeset_setup_hw_state does not.
10575 */
10576 *modeset_pipes &= 1 << intel_crtc->pipe;
10577 *prepare_pipes &= 1 << intel_crtc->pipe;
10578
10579 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10580 *modeset_pipes, *prepare_pipes, *disable_pipes);
10581 }
10582
10583 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10584 {
10585 struct drm_encoder *encoder;
10586 struct drm_device *dev = crtc->dev;
10587
10588 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10589 if (encoder->crtc == crtc)
10590 return true;
10591
10592 return false;
10593 }
10594
10595 static void
10596 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10597 {
10598 struct drm_i915_private *dev_priv = dev->dev_private;
10599 struct intel_encoder *intel_encoder;
10600 struct intel_crtc *intel_crtc;
10601 struct drm_connector *connector;
10602
10603 intel_shared_dpll_commit(dev_priv);
10604
10605 for_each_intel_encoder(dev, intel_encoder) {
10606 if (!intel_encoder->base.crtc)
10607 continue;
10608
10609 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10610
10611 if (prepare_pipes & (1 << intel_crtc->pipe))
10612 intel_encoder->connectors_active = false;
10613 }
10614
10615 intel_modeset_commit_output_state(dev);
10616
10617 /* Double check state. */
10618 for_each_intel_crtc(dev, intel_crtc) {
10619 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10620 WARN_ON(intel_crtc->new_config &&
10621 intel_crtc->new_config != intel_crtc->config);
10622 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10623 }
10624
10625 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10626 if (!connector->encoder || !connector->encoder->crtc)
10627 continue;
10628
10629 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10630
10631 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10632 struct drm_property *dpms_property =
10633 dev->mode_config.dpms_property;
10634
10635 connector->dpms = DRM_MODE_DPMS_ON;
10636 drm_object_property_set_value(&connector->base,
10637 dpms_property,
10638 DRM_MODE_DPMS_ON);
10639
10640 intel_encoder = to_intel_encoder(connector->encoder);
10641 intel_encoder->connectors_active = true;
10642 }
10643 }
10644
10645 }
10646
10647 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10648 {
10649 int diff;
10650
10651 if (clock1 == clock2)
10652 return true;
10653
10654 if (!clock1 || !clock2)
10655 return false;
10656
10657 diff = abs(clock1 - clock2);
10658
10659 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10660 return true;
10661
10662 return false;
10663 }
10664
10665 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10666 list_for_each_entry((intel_crtc), \
10667 &(dev)->mode_config.crtc_list, \
10668 base.head) \
10669 if (mask & (1 <<(intel_crtc)->pipe))
10670
10671 static bool
10672 intel_pipe_config_compare(struct drm_device *dev,
10673 struct intel_crtc_state *current_config,
10674 struct intel_crtc_state *pipe_config)
10675 {
10676 #define PIPE_CONF_CHECK_X(name) \
10677 if (current_config->name != pipe_config->name) { \
10678 DRM_ERROR("mismatch in " #name " " \
10679 "(expected 0x%08x, found 0x%08x)\n", \
10680 current_config->name, \
10681 pipe_config->name); \
10682 return false; \
10683 }
10684
10685 #define PIPE_CONF_CHECK_I(name) \
10686 if (current_config->name != pipe_config->name) { \
10687 DRM_ERROR("mismatch in " #name " " \
10688 "(expected %i, found %i)\n", \
10689 current_config->name, \
10690 pipe_config->name); \
10691 return false; \
10692 }
10693
10694 /* This is required for BDW+ where there is only one set of registers for
10695 * switching between high and low RR.
10696 * This macro can be used whenever a comparison has to be made between one
10697 * hw state and multiple sw state variables.
10698 */
10699 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10700 if ((current_config->name != pipe_config->name) && \
10701 (current_config->alt_name != pipe_config->name)) { \
10702 DRM_ERROR("mismatch in " #name " " \
10703 "(expected %i or %i, found %i)\n", \
10704 current_config->name, \
10705 current_config->alt_name, \
10706 pipe_config->name); \
10707 return false; \
10708 }
10709
10710 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10711 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10712 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10713 "(expected %i, found %i)\n", \
10714 current_config->name & (mask), \
10715 pipe_config->name & (mask)); \
10716 return false; \
10717 }
10718
10719 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10720 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10721 DRM_ERROR("mismatch in " #name " " \
10722 "(expected %i, found %i)\n", \
10723 current_config->name, \
10724 pipe_config->name); \
10725 return false; \
10726 }
10727
10728 #define PIPE_CONF_QUIRK(quirk) \
10729 ((current_config->quirks | pipe_config->quirks) & (quirk))
10730
10731 PIPE_CONF_CHECK_I(cpu_transcoder);
10732
10733 PIPE_CONF_CHECK_I(has_pch_encoder);
10734 PIPE_CONF_CHECK_I(fdi_lanes);
10735 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10736 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10737 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10738 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10739 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10740
10741 PIPE_CONF_CHECK_I(has_dp_encoder);
10742
10743 if (INTEL_INFO(dev)->gen < 8) {
10744 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10745 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10746 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10747 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10748 PIPE_CONF_CHECK_I(dp_m_n.tu);
10749
10750 if (current_config->has_drrs) {
10751 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10752 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10753 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10754 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10755 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10756 }
10757 } else {
10758 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10759 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10760 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10761 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10762 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10763 }
10764
10765 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10766 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10767 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10768 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10769 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10770 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10771
10772 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10773 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10774 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10775 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10776 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10777 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10778
10779 PIPE_CONF_CHECK_I(pixel_multiplier);
10780 PIPE_CONF_CHECK_I(has_hdmi_sink);
10781 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10782 IS_VALLEYVIEW(dev))
10783 PIPE_CONF_CHECK_I(limited_color_range);
10784 PIPE_CONF_CHECK_I(has_infoframe);
10785
10786 PIPE_CONF_CHECK_I(has_audio);
10787
10788 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10789 DRM_MODE_FLAG_INTERLACE);
10790
10791 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10792 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10793 DRM_MODE_FLAG_PHSYNC);
10794 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10795 DRM_MODE_FLAG_NHSYNC);
10796 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10797 DRM_MODE_FLAG_PVSYNC);
10798 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10799 DRM_MODE_FLAG_NVSYNC);
10800 }
10801
10802 PIPE_CONF_CHECK_I(pipe_src_w);
10803 PIPE_CONF_CHECK_I(pipe_src_h);
10804
10805 /*
10806 * FIXME: BIOS likes to set up a cloned config with lvds+external
10807 * screen. Since we don't yet re-compute the pipe config when moving
10808 * just the lvds port away to another pipe the sw tracking won't match.
10809 *
10810 * Proper atomic modesets with recomputed global state will fix this.
10811 * Until then just don't check gmch state for inherited modes.
10812 */
10813 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10814 PIPE_CONF_CHECK_I(gmch_pfit.control);
10815 /* pfit ratios are autocomputed by the hw on gen4+ */
10816 if (INTEL_INFO(dev)->gen < 4)
10817 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10818 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10819 }
10820
10821 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10822 if (current_config->pch_pfit.enabled) {
10823 PIPE_CONF_CHECK_I(pch_pfit.pos);
10824 PIPE_CONF_CHECK_I(pch_pfit.size);
10825 }
10826
10827 /* BDW+ don't expose a synchronous way to read the state */
10828 if (IS_HASWELL(dev))
10829 PIPE_CONF_CHECK_I(ips_enabled);
10830
10831 PIPE_CONF_CHECK_I(double_wide);
10832
10833 PIPE_CONF_CHECK_X(ddi_pll_sel);
10834
10835 PIPE_CONF_CHECK_I(shared_dpll);
10836 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10837 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10838 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10839 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10840 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10841 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10842 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10843 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10844
10845 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10846 PIPE_CONF_CHECK_I(pipe_bpp);
10847
10848 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10849 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10850
10851 #undef PIPE_CONF_CHECK_X
10852 #undef PIPE_CONF_CHECK_I
10853 #undef PIPE_CONF_CHECK_I_ALT
10854 #undef PIPE_CONF_CHECK_FLAGS
10855 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10856 #undef PIPE_CONF_QUIRK
10857
10858 return true;
10859 }
10860
10861 static void check_wm_state(struct drm_device *dev)
10862 {
10863 struct drm_i915_private *dev_priv = dev->dev_private;
10864 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10865 struct intel_crtc *intel_crtc;
10866 int plane;
10867
10868 if (INTEL_INFO(dev)->gen < 9)
10869 return;
10870
10871 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10872 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10873
10874 for_each_intel_crtc(dev, intel_crtc) {
10875 struct skl_ddb_entry *hw_entry, *sw_entry;
10876 const enum pipe pipe = intel_crtc->pipe;
10877
10878 if (!intel_crtc->active)
10879 continue;
10880
10881 /* planes */
10882 for_each_plane(dev_priv, pipe, plane) {
10883 hw_entry = &hw_ddb.plane[pipe][plane];
10884 sw_entry = &sw_ddb->plane[pipe][plane];
10885
10886 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10887 continue;
10888
10889 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10890 "(expected (%u,%u), found (%u,%u))\n",
10891 pipe_name(pipe), plane + 1,
10892 sw_entry->start, sw_entry->end,
10893 hw_entry->start, hw_entry->end);
10894 }
10895
10896 /* cursor */
10897 hw_entry = &hw_ddb.cursor[pipe];
10898 sw_entry = &sw_ddb->cursor[pipe];
10899
10900 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10901 continue;
10902
10903 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10904 "(expected (%u,%u), found (%u,%u))\n",
10905 pipe_name(pipe),
10906 sw_entry->start, sw_entry->end,
10907 hw_entry->start, hw_entry->end);
10908 }
10909 }
10910
10911 static void
10912 check_connector_state(struct drm_device *dev)
10913 {
10914 struct intel_connector *connector;
10915
10916 for_each_intel_connector(dev, connector) {
10917 /* This also checks the encoder/connector hw state with the
10918 * ->get_hw_state callbacks. */
10919 intel_connector_check_state(connector);
10920
10921 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10922 "connector's staged encoder doesn't match current encoder\n");
10923 }
10924 }
10925
10926 static void
10927 check_encoder_state(struct drm_device *dev)
10928 {
10929 struct intel_encoder *encoder;
10930 struct intel_connector *connector;
10931
10932 for_each_intel_encoder(dev, encoder) {
10933 bool enabled = false;
10934 bool active = false;
10935 enum pipe pipe, tracked_pipe;
10936
10937 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10938 encoder->base.base.id,
10939 encoder->base.name);
10940
10941 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10942 "encoder's stage crtc doesn't match current crtc\n");
10943 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10944 "encoder's active_connectors set, but no crtc\n");
10945
10946 for_each_intel_connector(dev, connector) {
10947 if (connector->base.encoder != &encoder->base)
10948 continue;
10949 enabled = true;
10950 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10951 active = true;
10952 }
10953 /*
10954 * for MST connectors if we unplug the connector is gone
10955 * away but the encoder is still connected to a crtc
10956 * until a modeset happens in response to the hotplug.
10957 */
10958 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10959 continue;
10960
10961 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10962 "encoder's enabled state mismatch "
10963 "(expected %i, found %i)\n",
10964 !!encoder->base.crtc, enabled);
10965 I915_STATE_WARN(active && !encoder->base.crtc,
10966 "active encoder with no crtc\n");
10967
10968 I915_STATE_WARN(encoder->connectors_active != active,
10969 "encoder's computed active state doesn't match tracked active state "
10970 "(expected %i, found %i)\n", active, encoder->connectors_active);
10971
10972 active = encoder->get_hw_state(encoder, &pipe);
10973 I915_STATE_WARN(active != encoder->connectors_active,
10974 "encoder's hw state doesn't match sw tracking "
10975 "(expected %i, found %i)\n",
10976 encoder->connectors_active, active);
10977
10978 if (!encoder->base.crtc)
10979 continue;
10980
10981 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10982 I915_STATE_WARN(active && pipe != tracked_pipe,
10983 "active encoder's pipe doesn't match"
10984 "(expected %i, found %i)\n",
10985 tracked_pipe, pipe);
10986
10987 }
10988 }
10989
10990 static void
10991 check_crtc_state(struct drm_device *dev)
10992 {
10993 struct drm_i915_private *dev_priv = dev->dev_private;
10994 struct intel_crtc *crtc;
10995 struct intel_encoder *encoder;
10996 struct intel_crtc_state pipe_config;
10997
10998 for_each_intel_crtc(dev, crtc) {
10999 bool enabled = false;
11000 bool active = false;
11001
11002 memset(&pipe_config, 0, sizeof(pipe_config));
11003
11004 DRM_DEBUG_KMS("[CRTC:%d]\n",
11005 crtc->base.base.id);
11006
11007 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11008 "active crtc, but not enabled in sw tracking\n");
11009
11010 for_each_intel_encoder(dev, encoder) {
11011 if (encoder->base.crtc != &crtc->base)
11012 continue;
11013 enabled = true;
11014 if (encoder->connectors_active)
11015 active = true;
11016 }
11017
11018 I915_STATE_WARN(active != crtc->active,
11019 "crtc's computed active state doesn't match tracked active state "
11020 "(expected %i, found %i)\n", active, crtc->active);
11021 I915_STATE_WARN(enabled != crtc->base.state->enable,
11022 "crtc's computed enabled state doesn't match tracked enabled state "
11023 "(expected %i, found %i)\n", enabled,
11024 crtc->base.state->enable);
11025
11026 active = dev_priv->display.get_pipe_config(crtc,
11027 &pipe_config);
11028
11029 /* hw state is inconsistent with the pipe quirk */
11030 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11031 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11032 active = crtc->active;
11033
11034 for_each_intel_encoder(dev, encoder) {
11035 enum pipe pipe;
11036 if (encoder->base.crtc != &crtc->base)
11037 continue;
11038 if (encoder->get_hw_state(encoder, &pipe))
11039 encoder->get_config(encoder, &pipe_config);
11040 }
11041
11042 I915_STATE_WARN(crtc->active != active,
11043 "crtc active state doesn't match with hw state "
11044 "(expected %i, found %i)\n", crtc->active, active);
11045
11046 if (active &&
11047 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11048 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11049 intel_dump_pipe_config(crtc, &pipe_config,
11050 "[hw state]");
11051 intel_dump_pipe_config(crtc, crtc->config,
11052 "[sw state]");
11053 }
11054 }
11055 }
11056
11057 static void
11058 check_shared_dpll_state(struct drm_device *dev)
11059 {
11060 struct drm_i915_private *dev_priv = dev->dev_private;
11061 struct intel_crtc *crtc;
11062 struct intel_dpll_hw_state dpll_hw_state;
11063 int i;
11064
11065 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11066 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11067 int enabled_crtcs = 0, active_crtcs = 0;
11068 bool active;
11069
11070 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11071
11072 DRM_DEBUG_KMS("%s\n", pll->name);
11073
11074 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11075
11076 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11077 "more active pll users than references: %i vs %i\n",
11078 pll->active, hweight32(pll->config.crtc_mask));
11079 I915_STATE_WARN(pll->active && !pll->on,
11080 "pll in active use but not on in sw tracking\n");
11081 I915_STATE_WARN(pll->on && !pll->active,
11082 "pll in on but not on in use in sw tracking\n");
11083 I915_STATE_WARN(pll->on != active,
11084 "pll on state mismatch (expected %i, found %i)\n",
11085 pll->on, active);
11086
11087 for_each_intel_crtc(dev, crtc) {
11088 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11089 enabled_crtcs++;
11090 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11091 active_crtcs++;
11092 }
11093 I915_STATE_WARN(pll->active != active_crtcs,
11094 "pll active crtcs mismatch (expected %i, found %i)\n",
11095 pll->active, active_crtcs);
11096 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11097 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11098 hweight32(pll->config.crtc_mask), enabled_crtcs);
11099
11100 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11101 sizeof(dpll_hw_state)),
11102 "pll hw state mismatch\n");
11103 }
11104 }
11105
11106 void
11107 intel_modeset_check_state(struct drm_device *dev)
11108 {
11109 check_wm_state(dev);
11110 check_connector_state(dev);
11111 check_encoder_state(dev);
11112 check_crtc_state(dev);
11113 check_shared_dpll_state(dev);
11114 }
11115
11116 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11117 int dotclock)
11118 {
11119 /*
11120 * FDI already provided one idea for the dotclock.
11121 * Yell if the encoder disagrees.
11122 */
11123 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11124 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11125 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11126 }
11127
11128 static void update_scanline_offset(struct intel_crtc *crtc)
11129 {
11130 struct drm_device *dev = crtc->base.dev;
11131
11132 /*
11133 * The scanline counter increments at the leading edge of hsync.
11134 *
11135 * On most platforms it starts counting from vtotal-1 on the
11136 * first active line. That means the scanline counter value is
11137 * always one less than what we would expect. Ie. just after
11138 * start of vblank, which also occurs at start of hsync (on the
11139 * last active line), the scanline counter will read vblank_start-1.
11140 *
11141 * On gen2 the scanline counter starts counting from 1 instead
11142 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11143 * to keep the value positive), instead of adding one.
11144 *
11145 * On HSW+ the behaviour of the scanline counter depends on the output
11146 * type. For DP ports it behaves like most other platforms, but on HDMI
11147 * there's an extra 1 line difference. So we need to add two instead of
11148 * one to the value.
11149 */
11150 if (IS_GEN2(dev)) {
11151 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11152 int vtotal;
11153
11154 vtotal = mode->crtc_vtotal;
11155 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11156 vtotal /= 2;
11157
11158 crtc->scanline_offset = vtotal - 1;
11159 } else if (HAS_DDI(dev) &&
11160 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11161 crtc->scanline_offset = 2;
11162 } else
11163 crtc->scanline_offset = 1;
11164 }
11165
11166 static struct intel_crtc_state *
11167 intel_modeset_compute_config(struct drm_crtc *crtc,
11168 struct drm_display_mode *mode,
11169 struct drm_framebuffer *fb,
11170 unsigned *modeset_pipes,
11171 unsigned *prepare_pipes,
11172 unsigned *disable_pipes)
11173 {
11174 struct intel_crtc_state *pipe_config = NULL;
11175
11176 intel_modeset_affected_pipes(crtc, modeset_pipes,
11177 prepare_pipes, disable_pipes);
11178
11179 if ((*modeset_pipes) == 0)
11180 goto out;
11181
11182 /*
11183 * Note this needs changes when we start tracking multiple modes
11184 * and crtcs. At that point we'll need to compute the whole config
11185 * (i.e. one pipe_config for each crtc) rather than just the one
11186 * for this crtc.
11187 */
11188 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11189 if (IS_ERR(pipe_config)) {
11190 goto out;
11191 }
11192 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11193 "[modeset]");
11194
11195 out:
11196 return pipe_config;
11197 }
11198
11199 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11200 unsigned modeset_pipes,
11201 unsigned disable_pipes)
11202 {
11203 struct drm_i915_private *dev_priv = to_i915(dev);
11204 unsigned clear_pipes = modeset_pipes | disable_pipes;
11205 struct intel_crtc *intel_crtc;
11206 int ret = 0;
11207
11208 if (!dev_priv->display.crtc_compute_clock)
11209 return 0;
11210
11211 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11212 if (ret)
11213 goto done;
11214
11215 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11216 struct intel_crtc_state *state = intel_crtc->new_config;
11217 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11218 state);
11219 if (ret) {
11220 intel_shared_dpll_abort_config(dev_priv);
11221 goto done;
11222 }
11223 }
11224
11225 done:
11226 return ret;
11227 }
11228
11229 static int __intel_set_mode(struct drm_crtc *crtc,
11230 struct drm_display_mode *mode,
11231 int x, int y, struct drm_framebuffer *fb,
11232 struct intel_crtc_state *pipe_config,
11233 unsigned modeset_pipes,
11234 unsigned prepare_pipes,
11235 unsigned disable_pipes)
11236 {
11237 struct drm_device *dev = crtc->dev;
11238 struct drm_i915_private *dev_priv = dev->dev_private;
11239 struct drm_display_mode *saved_mode;
11240 struct intel_crtc *intel_crtc;
11241 int ret = 0;
11242
11243 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11244 if (!saved_mode)
11245 return -ENOMEM;
11246
11247 *saved_mode = crtc->mode;
11248
11249 if (modeset_pipes)
11250 to_intel_crtc(crtc)->new_config = pipe_config;
11251
11252 /*
11253 * See if the config requires any additional preparation, e.g.
11254 * to adjust global state with pipes off. We need to do this
11255 * here so we can get the modeset_pipe updated config for the new
11256 * mode set on this crtc. For other crtcs we need to use the
11257 * adjusted_mode bits in the crtc directly.
11258 */
11259 if (IS_VALLEYVIEW(dev)) {
11260 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11261
11262 /* may have added more to prepare_pipes than we should */
11263 prepare_pipes &= ~disable_pipes;
11264 }
11265
11266 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11267 if (ret)
11268 goto done;
11269
11270 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11271 intel_crtc_disable(&intel_crtc->base);
11272
11273 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11274 if (intel_crtc->base.state->enable)
11275 dev_priv->display.crtc_disable(&intel_crtc->base);
11276 }
11277
11278 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11279 * to set it here already despite that we pass it down the callchain.
11280 *
11281 * Note we'll need to fix this up when we start tracking multiple
11282 * pipes; here we assume a single modeset_pipe and only track the
11283 * single crtc and mode.
11284 */
11285 if (modeset_pipes) {
11286 crtc->mode = *mode;
11287 /* mode_set/enable/disable functions rely on a correct pipe
11288 * config. */
11289 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11290
11291 /*
11292 * Calculate and store various constants which
11293 * are later needed by vblank and swap-completion
11294 * timestamping. They are derived from true hwmode.
11295 */
11296 drm_calc_timestamping_constants(crtc,
11297 &pipe_config->base.adjusted_mode);
11298 }
11299
11300 /* Only after disabling all output pipelines that will be changed can we
11301 * update the the output configuration. */
11302 intel_modeset_update_state(dev, prepare_pipes);
11303
11304 modeset_update_crtc_power_domains(dev);
11305
11306 /* Set up the DPLL and any encoders state that needs to adjust or depend
11307 * on the DPLL.
11308 */
11309 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11310 struct drm_plane *primary = intel_crtc->base.primary;
11311 int vdisplay, hdisplay;
11312
11313 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11314 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11315 fb, 0, 0,
11316 hdisplay, vdisplay,
11317 x << 16, y << 16,
11318 hdisplay << 16, vdisplay << 16);
11319 }
11320
11321 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11322 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11323 update_scanline_offset(intel_crtc);
11324
11325 dev_priv->display.crtc_enable(&intel_crtc->base);
11326 }
11327
11328 /* FIXME: add subpixel order */
11329 done:
11330 if (ret && crtc->state->enable)
11331 crtc->mode = *saved_mode;
11332
11333 kfree(saved_mode);
11334 return ret;
11335 }
11336
11337 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11338 struct drm_display_mode *mode,
11339 int x, int y, struct drm_framebuffer *fb,
11340 struct intel_crtc_state *pipe_config,
11341 unsigned modeset_pipes,
11342 unsigned prepare_pipes,
11343 unsigned disable_pipes)
11344 {
11345 int ret;
11346
11347 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11348 prepare_pipes, disable_pipes);
11349
11350 if (ret == 0)
11351 intel_modeset_check_state(crtc->dev);
11352
11353 return ret;
11354 }
11355
11356 static int intel_set_mode(struct drm_crtc *crtc,
11357 struct drm_display_mode *mode,
11358 int x, int y, struct drm_framebuffer *fb)
11359 {
11360 struct intel_crtc_state *pipe_config;
11361 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11362
11363 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11364 &modeset_pipes,
11365 &prepare_pipes,
11366 &disable_pipes);
11367
11368 if (IS_ERR(pipe_config))
11369 return PTR_ERR(pipe_config);
11370
11371 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11372 modeset_pipes, prepare_pipes,
11373 disable_pipes);
11374 }
11375
11376 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11377 {
11378 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11379 }
11380
11381 #undef for_each_intel_crtc_masked
11382
11383 static void intel_set_config_free(struct intel_set_config *config)
11384 {
11385 if (!config)
11386 return;
11387
11388 kfree(config->save_connector_encoders);
11389 kfree(config->save_encoder_crtcs);
11390 kfree(config->save_crtc_enabled);
11391 kfree(config);
11392 }
11393
11394 static int intel_set_config_save_state(struct drm_device *dev,
11395 struct intel_set_config *config)
11396 {
11397 struct drm_crtc *crtc;
11398 struct drm_encoder *encoder;
11399 struct drm_connector *connector;
11400 int count;
11401
11402 config->save_crtc_enabled =
11403 kcalloc(dev->mode_config.num_crtc,
11404 sizeof(bool), GFP_KERNEL);
11405 if (!config->save_crtc_enabled)
11406 return -ENOMEM;
11407
11408 config->save_encoder_crtcs =
11409 kcalloc(dev->mode_config.num_encoder,
11410 sizeof(struct drm_crtc *), GFP_KERNEL);
11411 if (!config->save_encoder_crtcs)
11412 return -ENOMEM;
11413
11414 config->save_connector_encoders =
11415 kcalloc(dev->mode_config.num_connector,
11416 sizeof(struct drm_encoder *), GFP_KERNEL);
11417 if (!config->save_connector_encoders)
11418 return -ENOMEM;
11419
11420 /* Copy data. Note that driver private data is not affected.
11421 * Should anything bad happen only the expected state is
11422 * restored, not the drivers personal bookkeeping.
11423 */
11424 count = 0;
11425 for_each_crtc(dev, crtc) {
11426 config->save_crtc_enabled[count++] = crtc->state->enable;
11427 }
11428
11429 count = 0;
11430 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11431 config->save_encoder_crtcs[count++] = encoder->crtc;
11432 }
11433
11434 count = 0;
11435 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11436 config->save_connector_encoders[count++] = connector->encoder;
11437 }
11438
11439 return 0;
11440 }
11441
11442 static void intel_set_config_restore_state(struct drm_device *dev,
11443 struct intel_set_config *config)
11444 {
11445 struct intel_crtc *crtc;
11446 struct intel_encoder *encoder;
11447 struct intel_connector *connector;
11448 int count;
11449
11450 count = 0;
11451 for_each_intel_crtc(dev, crtc) {
11452 crtc->new_enabled = config->save_crtc_enabled[count++];
11453
11454 if (crtc->new_enabled)
11455 crtc->new_config = crtc->config;
11456 else
11457 crtc->new_config = NULL;
11458 }
11459
11460 count = 0;
11461 for_each_intel_encoder(dev, encoder) {
11462 encoder->new_crtc =
11463 to_intel_crtc(config->save_encoder_crtcs[count++]);
11464 }
11465
11466 count = 0;
11467 for_each_intel_connector(dev, connector) {
11468 connector->new_encoder =
11469 to_intel_encoder(config->save_connector_encoders[count++]);
11470 }
11471 }
11472
11473 static bool
11474 is_crtc_connector_off(struct drm_mode_set *set)
11475 {
11476 int i;
11477
11478 if (set->num_connectors == 0)
11479 return false;
11480
11481 if (WARN_ON(set->connectors == NULL))
11482 return false;
11483
11484 for (i = 0; i < set->num_connectors; i++)
11485 if (set->connectors[i]->encoder &&
11486 set->connectors[i]->encoder->crtc == set->crtc &&
11487 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11488 return true;
11489
11490 return false;
11491 }
11492
11493 static void
11494 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11495 struct intel_set_config *config)
11496 {
11497
11498 /* We should be able to check here if the fb has the same properties
11499 * and then just flip_or_move it */
11500 if (is_crtc_connector_off(set)) {
11501 config->mode_changed = true;
11502 } else if (set->crtc->primary->fb != set->fb) {
11503 /*
11504 * If we have no fb, we can only flip as long as the crtc is
11505 * active, otherwise we need a full mode set. The crtc may
11506 * be active if we've only disabled the primary plane, or
11507 * in fastboot situations.
11508 */
11509 if (set->crtc->primary->fb == NULL) {
11510 struct intel_crtc *intel_crtc =
11511 to_intel_crtc(set->crtc);
11512
11513 if (intel_crtc->active) {
11514 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11515 config->fb_changed = true;
11516 } else {
11517 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11518 config->mode_changed = true;
11519 }
11520 } else if (set->fb == NULL) {
11521 config->mode_changed = true;
11522 } else if (set->fb->pixel_format !=
11523 set->crtc->primary->fb->pixel_format) {
11524 config->mode_changed = true;
11525 } else {
11526 config->fb_changed = true;
11527 }
11528 }
11529
11530 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11531 config->fb_changed = true;
11532
11533 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11534 DRM_DEBUG_KMS("modes are different, full mode set\n");
11535 drm_mode_debug_printmodeline(&set->crtc->mode);
11536 drm_mode_debug_printmodeline(set->mode);
11537 config->mode_changed = true;
11538 }
11539
11540 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11541 set->crtc->base.id, config->mode_changed, config->fb_changed);
11542 }
11543
11544 static int
11545 intel_modeset_stage_output_state(struct drm_device *dev,
11546 struct drm_mode_set *set,
11547 struct intel_set_config *config)
11548 {
11549 struct intel_connector *connector;
11550 struct intel_encoder *encoder;
11551 struct intel_crtc *crtc;
11552 int ro;
11553
11554 /* The upper layers ensure that we either disable a crtc or have a list
11555 * of connectors. For paranoia, double-check this. */
11556 WARN_ON(!set->fb && (set->num_connectors != 0));
11557 WARN_ON(set->fb && (set->num_connectors == 0));
11558
11559 for_each_intel_connector(dev, connector) {
11560 /* Otherwise traverse passed in connector list and get encoders
11561 * for them. */
11562 for (ro = 0; ro < set->num_connectors; ro++) {
11563 if (set->connectors[ro] == &connector->base) {
11564 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11565 break;
11566 }
11567 }
11568
11569 /* If we disable the crtc, disable all its connectors. Also, if
11570 * the connector is on the changing crtc but not on the new
11571 * connector list, disable it. */
11572 if ((!set->fb || ro == set->num_connectors) &&
11573 connector->base.encoder &&
11574 connector->base.encoder->crtc == set->crtc) {
11575 connector->new_encoder = NULL;
11576
11577 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11578 connector->base.base.id,
11579 connector->base.name);
11580 }
11581
11582
11583 if (&connector->new_encoder->base != connector->base.encoder) {
11584 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11585 connector->base.base.id,
11586 connector->base.name);
11587 config->mode_changed = true;
11588 }
11589 }
11590 /* connector->new_encoder is now updated for all connectors. */
11591
11592 /* Update crtc of enabled connectors. */
11593 for_each_intel_connector(dev, connector) {
11594 struct drm_crtc *new_crtc;
11595
11596 if (!connector->new_encoder)
11597 continue;
11598
11599 new_crtc = connector->new_encoder->base.crtc;
11600
11601 for (ro = 0; ro < set->num_connectors; ro++) {
11602 if (set->connectors[ro] == &connector->base)
11603 new_crtc = set->crtc;
11604 }
11605
11606 /* Make sure the new CRTC will work with the encoder */
11607 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11608 new_crtc)) {
11609 return -EINVAL;
11610 }
11611 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11612
11613 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11614 connector->base.base.id,
11615 connector->base.name,
11616 new_crtc->base.id);
11617 }
11618
11619 /* Check for any encoders that needs to be disabled. */
11620 for_each_intel_encoder(dev, encoder) {
11621 int num_connectors = 0;
11622 for_each_intel_connector(dev, connector) {
11623 if (connector->new_encoder == encoder) {
11624 WARN_ON(!connector->new_encoder->new_crtc);
11625 num_connectors++;
11626 }
11627 }
11628
11629 if (num_connectors == 0)
11630 encoder->new_crtc = NULL;
11631 else if (num_connectors > 1)
11632 return -EINVAL;
11633
11634 /* Only now check for crtc changes so we don't miss encoders
11635 * that will be disabled. */
11636 if (&encoder->new_crtc->base != encoder->base.crtc) {
11637 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11638 encoder->base.base.id,
11639 encoder->base.name);
11640 config->mode_changed = true;
11641 }
11642 }
11643 /* Now we've also updated encoder->new_crtc for all encoders. */
11644 for_each_intel_connector(dev, connector) {
11645 if (connector->new_encoder)
11646 if (connector->new_encoder != connector->encoder)
11647 connector->encoder = connector->new_encoder;
11648 }
11649 for_each_intel_crtc(dev, crtc) {
11650 crtc->new_enabled = false;
11651
11652 for_each_intel_encoder(dev, encoder) {
11653 if (encoder->new_crtc == crtc) {
11654 crtc->new_enabled = true;
11655 break;
11656 }
11657 }
11658
11659 if (crtc->new_enabled != crtc->base.state->enable) {
11660 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11661 crtc->base.base.id,
11662 crtc->new_enabled ? "en" : "dis");
11663 config->mode_changed = true;
11664 }
11665
11666 if (crtc->new_enabled)
11667 crtc->new_config = crtc->config;
11668 else
11669 crtc->new_config = NULL;
11670 }
11671
11672 return 0;
11673 }
11674
11675 static void disable_crtc_nofb(struct intel_crtc *crtc)
11676 {
11677 struct drm_device *dev = crtc->base.dev;
11678 struct intel_encoder *encoder;
11679 struct intel_connector *connector;
11680
11681 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11682 pipe_name(crtc->pipe));
11683
11684 for_each_intel_connector(dev, connector) {
11685 if (connector->new_encoder &&
11686 connector->new_encoder->new_crtc == crtc)
11687 connector->new_encoder = NULL;
11688 }
11689
11690 for_each_intel_encoder(dev, encoder) {
11691 if (encoder->new_crtc == crtc)
11692 encoder->new_crtc = NULL;
11693 }
11694
11695 crtc->new_enabled = false;
11696 crtc->new_config = NULL;
11697 }
11698
11699 static int intel_crtc_set_config(struct drm_mode_set *set)
11700 {
11701 struct drm_device *dev;
11702 struct drm_mode_set save_set;
11703 struct intel_set_config *config;
11704 struct intel_crtc_state *pipe_config;
11705 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11706 int ret;
11707
11708 BUG_ON(!set);
11709 BUG_ON(!set->crtc);
11710 BUG_ON(!set->crtc->helper_private);
11711
11712 /* Enforce sane interface api - has been abused by the fb helper. */
11713 BUG_ON(!set->mode && set->fb);
11714 BUG_ON(set->fb && set->num_connectors == 0);
11715
11716 if (set->fb) {
11717 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11718 set->crtc->base.id, set->fb->base.id,
11719 (int)set->num_connectors, set->x, set->y);
11720 } else {
11721 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11722 }
11723
11724 dev = set->crtc->dev;
11725
11726 ret = -ENOMEM;
11727 config = kzalloc(sizeof(*config), GFP_KERNEL);
11728 if (!config)
11729 goto out_config;
11730
11731 ret = intel_set_config_save_state(dev, config);
11732 if (ret)
11733 goto out_config;
11734
11735 save_set.crtc = set->crtc;
11736 save_set.mode = &set->crtc->mode;
11737 save_set.x = set->crtc->x;
11738 save_set.y = set->crtc->y;
11739 save_set.fb = set->crtc->primary->fb;
11740
11741 /* Compute whether we need a full modeset, only an fb base update or no
11742 * change at all. In the future we might also check whether only the
11743 * mode changed, e.g. for LVDS where we only change the panel fitter in
11744 * such cases. */
11745 intel_set_config_compute_mode_changes(set, config);
11746
11747 ret = intel_modeset_stage_output_state(dev, set, config);
11748 if (ret)
11749 goto fail;
11750
11751 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11752 set->fb,
11753 &modeset_pipes,
11754 &prepare_pipes,
11755 &disable_pipes);
11756 if (IS_ERR(pipe_config)) {
11757 ret = PTR_ERR(pipe_config);
11758 goto fail;
11759 } else if (pipe_config) {
11760 if (pipe_config->has_audio !=
11761 to_intel_crtc(set->crtc)->config->has_audio)
11762 config->mode_changed = true;
11763
11764 /*
11765 * Note we have an issue here with infoframes: current code
11766 * only updates them on the full mode set path per hw
11767 * requirements. So here we should be checking for any
11768 * required changes and forcing a mode set.
11769 */
11770 }
11771
11772 /* set_mode will free it in the mode_changed case */
11773 if (!config->mode_changed)
11774 kfree(pipe_config);
11775
11776 intel_update_pipe_size(to_intel_crtc(set->crtc));
11777
11778 if (config->mode_changed) {
11779 ret = intel_set_mode_pipes(set->crtc, set->mode,
11780 set->x, set->y, set->fb, pipe_config,
11781 modeset_pipes, prepare_pipes,
11782 disable_pipes);
11783 } else if (config->fb_changed) {
11784 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11785 struct drm_plane *primary = set->crtc->primary;
11786 int vdisplay, hdisplay;
11787
11788 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11789 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11790 0, 0, hdisplay, vdisplay,
11791 set->x << 16, set->y << 16,
11792 hdisplay << 16, vdisplay << 16);
11793
11794 /*
11795 * We need to make sure the primary plane is re-enabled if it
11796 * has previously been turned off.
11797 */
11798 if (!intel_crtc->primary_enabled && ret == 0) {
11799 WARN_ON(!intel_crtc->active);
11800 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11801 }
11802
11803 /*
11804 * In the fastboot case this may be our only check of the
11805 * state after boot. It would be better to only do it on
11806 * the first update, but we don't have a nice way of doing that
11807 * (and really, set_config isn't used much for high freq page
11808 * flipping, so increasing its cost here shouldn't be a big
11809 * deal).
11810 */
11811 if (i915.fastboot && ret == 0)
11812 intel_modeset_check_state(set->crtc->dev);
11813 }
11814
11815 if (ret) {
11816 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11817 set->crtc->base.id, ret);
11818 fail:
11819 intel_set_config_restore_state(dev, config);
11820
11821 /*
11822 * HACK: if the pipe was on, but we didn't have a framebuffer,
11823 * force the pipe off to avoid oopsing in the modeset code
11824 * due to fb==NULL. This should only happen during boot since
11825 * we don't yet reconstruct the FB from the hardware state.
11826 */
11827 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11828 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11829
11830 /* Try to restore the config */
11831 if (config->mode_changed &&
11832 intel_set_mode(save_set.crtc, save_set.mode,
11833 save_set.x, save_set.y, save_set.fb))
11834 DRM_ERROR("failed to restore config after modeset failure\n");
11835 }
11836
11837 out_config:
11838 intel_set_config_free(config);
11839 return ret;
11840 }
11841
11842 static const struct drm_crtc_funcs intel_crtc_funcs = {
11843 .gamma_set = intel_crtc_gamma_set,
11844 .set_config = intel_crtc_set_config,
11845 .destroy = intel_crtc_destroy,
11846 .page_flip = intel_crtc_page_flip,
11847 .atomic_duplicate_state = intel_crtc_duplicate_state,
11848 .atomic_destroy_state = intel_crtc_destroy_state,
11849 };
11850
11851 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11852 struct intel_shared_dpll *pll,
11853 struct intel_dpll_hw_state *hw_state)
11854 {
11855 uint32_t val;
11856
11857 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11858 return false;
11859
11860 val = I915_READ(PCH_DPLL(pll->id));
11861 hw_state->dpll = val;
11862 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11863 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11864
11865 return val & DPLL_VCO_ENABLE;
11866 }
11867
11868 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11869 struct intel_shared_dpll *pll)
11870 {
11871 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11872 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11873 }
11874
11875 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11876 struct intel_shared_dpll *pll)
11877 {
11878 /* PCH refclock must be enabled first */
11879 ibx_assert_pch_refclk_enabled(dev_priv);
11880
11881 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11882
11883 /* Wait for the clocks to stabilize. */
11884 POSTING_READ(PCH_DPLL(pll->id));
11885 udelay(150);
11886
11887 /* The pixel multiplier can only be updated once the
11888 * DPLL is enabled and the clocks are stable.
11889 *
11890 * So write it again.
11891 */
11892 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11893 POSTING_READ(PCH_DPLL(pll->id));
11894 udelay(200);
11895 }
11896
11897 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11898 struct intel_shared_dpll *pll)
11899 {
11900 struct drm_device *dev = dev_priv->dev;
11901 struct intel_crtc *crtc;
11902
11903 /* Make sure no transcoder isn't still depending on us. */
11904 for_each_intel_crtc(dev, crtc) {
11905 if (intel_crtc_to_shared_dpll(crtc) == pll)
11906 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11907 }
11908
11909 I915_WRITE(PCH_DPLL(pll->id), 0);
11910 POSTING_READ(PCH_DPLL(pll->id));
11911 udelay(200);
11912 }
11913
11914 static char *ibx_pch_dpll_names[] = {
11915 "PCH DPLL A",
11916 "PCH DPLL B",
11917 };
11918
11919 static void ibx_pch_dpll_init(struct drm_device *dev)
11920 {
11921 struct drm_i915_private *dev_priv = dev->dev_private;
11922 int i;
11923
11924 dev_priv->num_shared_dpll = 2;
11925
11926 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11927 dev_priv->shared_dplls[i].id = i;
11928 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11929 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11930 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11931 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11932 dev_priv->shared_dplls[i].get_hw_state =
11933 ibx_pch_dpll_get_hw_state;
11934 }
11935 }
11936
11937 static void intel_shared_dpll_init(struct drm_device *dev)
11938 {
11939 struct drm_i915_private *dev_priv = dev->dev_private;
11940
11941 if (HAS_DDI(dev))
11942 intel_ddi_pll_init(dev);
11943 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11944 ibx_pch_dpll_init(dev);
11945 else
11946 dev_priv->num_shared_dpll = 0;
11947
11948 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11949 }
11950
11951 /**
11952 * intel_prepare_plane_fb - Prepare fb for usage on plane
11953 * @plane: drm plane to prepare for
11954 * @fb: framebuffer to prepare for presentation
11955 *
11956 * Prepares a framebuffer for usage on a display plane. Generally this
11957 * involves pinning the underlying object and updating the frontbuffer tracking
11958 * bits. Some older platforms need special physical address handling for
11959 * cursor planes.
11960 *
11961 * Returns 0 on success, negative error code on failure.
11962 */
11963 int
11964 intel_prepare_plane_fb(struct drm_plane *plane,
11965 struct drm_framebuffer *fb,
11966 const struct drm_plane_state *new_state)
11967 {
11968 struct drm_device *dev = plane->dev;
11969 struct intel_plane *intel_plane = to_intel_plane(plane);
11970 enum pipe pipe = intel_plane->pipe;
11971 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11972 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11973 unsigned frontbuffer_bits = 0;
11974 int ret = 0;
11975
11976 if (!obj)
11977 return 0;
11978
11979 switch (plane->type) {
11980 case DRM_PLANE_TYPE_PRIMARY:
11981 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11982 break;
11983 case DRM_PLANE_TYPE_CURSOR:
11984 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11985 break;
11986 case DRM_PLANE_TYPE_OVERLAY:
11987 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11988 break;
11989 }
11990
11991 mutex_lock(&dev->struct_mutex);
11992
11993 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11994 INTEL_INFO(dev)->cursor_needs_physical) {
11995 int align = IS_I830(dev) ? 16 * 1024 : 256;
11996 ret = i915_gem_object_attach_phys(obj, align);
11997 if (ret)
11998 DRM_DEBUG_KMS("failed to attach phys object\n");
11999 } else {
12000 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
12001 }
12002
12003 if (ret == 0)
12004 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12005
12006 mutex_unlock(&dev->struct_mutex);
12007
12008 return ret;
12009 }
12010
12011 /**
12012 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12013 * @plane: drm plane to clean up for
12014 * @fb: old framebuffer that was on plane
12015 *
12016 * Cleans up a framebuffer that has just been removed from a plane.
12017 */
12018 void
12019 intel_cleanup_plane_fb(struct drm_plane *plane,
12020 struct drm_framebuffer *fb,
12021 const struct drm_plane_state *old_state)
12022 {
12023 struct drm_device *dev = plane->dev;
12024 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12025
12026 if (WARN_ON(!obj))
12027 return;
12028
12029 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12030 !INTEL_INFO(dev)->cursor_needs_physical) {
12031 mutex_lock(&dev->struct_mutex);
12032 intel_unpin_fb_obj(obj);
12033 mutex_unlock(&dev->struct_mutex);
12034 }
12035 }
12036
12037 static int
12038 intel_check_primary_plane(struct drm_plane *plane,
12039 struct intel_plane_state *state)
12040 {
12041 struct drm_device *dev = plane->dev;
12042 struct drm_i915_private *dev_priv = dev->dev_private;
12043 struct drm_crtc *crtc = state->base.crtc;
12044 struct intel_crtc *intel_crtc;
12045 struct drm_framebuffer *fb = state->base.fb;
12046 struct drm_rect *dest = &state->dst;
12047 struct drm_rect *src = &state->src;
12048 const struct drm_rect *clip = &state->clip;
12049 int ret;
12050
12051 crtc = crtc ? crtc : plane->crtc;
12052 intel_crtc = to_intel_crtc(crtc);
12053
12054 ret = drm_plane_helper_check_update(plane, crtc, fb,
12055 src, dest, clip,
12056 DRM_PLANE_HELPER_NO_SCALING,
12057 DRM_PLANE_HELPER_NO_SCALING,
12058 false, true, &state->visible);
12059 if (ret)
12060 return ret;
12061
12062 if (intel_crtc->active) {
12063 intel_crtc->atomic.wait_for_flips = true;
12064
12065 /*
12066 * FBC does not work on some platforms for rotated
12067 * planes, so disable it when rotation is not 0 and
12068 * update it when rotation is set back to 0.
12069 *
12070 * FIXME: This is redundant with the fbc update done in
12071 * the primary plane enable function except that that
12072 * one is done too late. We eventually need to unify
12073 * this.
12074 */
12075 if (intel_crtc->primary_enabled &&
12076 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12077 dev_priv->fbc.crtc == intel_crtc &&
12078 state->base.rotation != BIT(DRM_ROTATE_0)) {
12079 intel_crtc->atomic.disable_fbc = true;
12080 }
12081
12082 if (state->visible) {
12083 /*
12084 * BDW signals flip done immediately if the plane
12085 * is disabled, even if the plane enable is already
12086 * armed to occur at the next vblank :(
12087 */
12088 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12089 intel_crtc->atomic.wait_vblank = true;
12090 }
12091
12092 intel_crtc->atomic.fb_bits |=
12093 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12094
12095 intel_crtc->atomic.update_fbc = true;
12096
12097 /* Update watermarks on tiling changes. */
12098 if (!plane->state->fb || !state->base.fb ||
12099 plane->state->fb->modifier[0] !=
12100 state->base.fb->modifier[0])
12101 intel_crtc->atomic.update_wm = true;
12102 }
12103
12104 return 0;
12105 }
12106
12107 static void
12108 intel_commit_primary_plane(struct drm_plane *plane,
12109 struct intel_plane_state *state)
12110 {
12111 struct drm_crtc *crtc = state->base.crtc;
12112 struct drm_framebuffer *fb = state->base.fb;
12113 struct drm_device *dev = plane->dev;
12114 struct drm_i915_private *dev_priv = dev->dev_private;
12115 struct intel_crtc *intel_crtc;
12116 struct drm_rect *src = &state->src;
12117
12118 crtc = crtc ? crtc : plane->crtc;
12119 intel_crtc = to_intel_crtc(crtc);
12120
12121 plane->fb = fb;
12122 crtc->x = src->x1 >> 16;
12123 crtc->y = src->y1 >> 16;
12124
12125 if (intel_crtc->active) {
12126 if (state->visible) {
12127 /* FIXME: kill this fastboot hack */
12128 intel_update_pipe_size(intel_crtc);
12129
12130 intel_crtc->primary_enabled = true;
12131
12132 dev_priv->display.update_primary_plane(crtc, plane->fb,
12133 crtc->x, crtc->y);
12134 } else {
12135 /*
12136 * If clipping results in a non-visible primary plane,
12137 * we'll disable the primary plane. Note that this is
12138 * a bit different than what happens if userspace
12139 * explicitly disables the plane by passing fb=0
12140 * because plane->fb still gets set and pinned.
12141 */
12142 intel_disable_primary_hw_plane(plane, crtc);
12143 }
12144 }
12145 }
12146
12147 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12148 {
12149 struct drm_device *dev = crtc->dev;
12150 struct drm_i915_private *dev_priv = dev->dev_private;
12151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12152 struct intel_plane *intel_plane;
12153 struct drm_plane *p;
12154 unsigned fb_bits = 0;
12155
12156 /* Track fb's for any planes being disabled */
12157 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12158 intel_plane = to_intel_plane(p);
12159
12160 if (intel_crtc->atomic.disabled_planes &
12161 (1 << drm_plane_index(p))) {
12162 switch (p->type) {
12163 case DRM_PLANE_TYPE_PRIMARY:
12164 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12165 break;
12166 case DRM_PLANE_TYPE_CURSOR:
12167 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12168 break;
12169 case DRM_PLANE_TYPE_OVERLAY:
12170 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12171 break;
12172 }
12173
12174 mutex_lock(&dev->struct_mutex);
12175 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12176 mutex_unlock(&dev->struct_mutex);
12177 }
12178 }
12179
12180 if (intel_crtc->atomic.wait_for_flips)
12181 intel_crtc_wait_for_pending_flips(crtc);
12182
12183 if (intel_crtc->atomic.disable_fbc)
12184 intel_fbc_disable(dev);
12185
12186 if (intel_crtc->atomic.pre_disable_primary)
12187 intel_pre_disable_primary(crtc);
12188
12189 if (intel_crtc->atomic.update_wm)
12190 intel_update_watermarks(crtc);
12191
12192 intel_runtime_pm_get(dev_priv);
12193
12194 /* Perform vblank evasion around commit operation */
12195 if (intel_crtc->active)
12196 intel_crtc->atomic.evade =
12197 intel_pipe_update_start(intel_crtc,
12198 &intel_crtc->atomic.start_vbl_count);
12199 }
12200
12201 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12202 {
12203 struct drm_device *dev = crtc->dev;
12204 struct drm_i915_private *dev_priv = dev->dev_private;
12205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12206 struct drm_plane *p;
12207
12208 if (intel_crtc->atomic.evade)
12209 intel_pipe_update_end(intel_crtc,
12210 intel_crtc->atomic.start_vbl_count);
12211
12212 intel_runtime_pm_put(dev_priv);
12213
12214 if (intel_crtc->atomic.wait_vblank)
12215 intel_wait_for_vblank(dev, intel_crtc->pipe);
12216
12217 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12218
12219 if (intel_crtc->atomic.update_fbc) {
12220 mutex_lock(&dev->struct_mutex);
12221 intel_fbc_update(dev);
12222 mutex_unlock(&dev->struct_mutex);
12223 }
12224
12225 if (intel_crtc->atomic.post_enable_primary)
12226 intel_post_enable_primary(crtc);
12227
12228 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12229 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12230 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12231 false, false);
12232
12233 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12234 }
12235
12236 /**
12237 * intel_plane_destroy - destroy a plane
12238 * @plane: plane to destroy
12239 *
12240 * Common destruction function for all types of planes (primary, cursor,
12241 * sprite).
12242 */
12243 void intel_plane_destroy(struct drm_plane *plane)
12244 {
12245 struct intel_plane *intel_plane = to_intel_plane(plane);
12246 drm_plane_cleanup(plane);
12247 kfree(intel_plane);
12248 }
12249
12250 const struct drm_plane_funcs intel_plane_funcs = {
12251 .update_plane = drm_plane_helper_update,
12252 .disable_plane = drm_plane_helper_disable,
12253 .destroy = intel_plane_destroy,
12254 .set_property = drm_atomic_helper_plane_set_property,
12255 .atomic_get_property = intel_plane_atomic_get_property,
12256 .atomic_set_property = intel_plane_atomic_set_property,
12257 .atomic_duplicate_state = intel_plane_duplicate_state,
12258 .atomic_destroy_state = intel_plane_destroy_state,
12259
12260 };
12261
12262 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12263 int pipe)
12264 {
12265 struct intel_plane *primary;
12266 struct intel_plane_state *state;
12267 const uint32_t *intel_primary_formats;
12268 int num_formats;
12269
12270 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12271 if (primary == NULL)
12272 return NULL;
12273
12274 state = intel_create_plane_state(&primary->base);
12275 if (!state) {
12276 kfree(primary);
12277 return NULL;
12278 }
12279 primary->base.state = &state->base;
12280
12281 primary->can_scale = false;
12282 primary->max_downscale = 1;
12283 primary->pipe = pipe;
12284 primary->plane = pipe;
12285 primary->check_plane = intel_check_primary_plane;
12286 primary->commit_plane = intel_commit_primary_plane;
12287 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12288 primary->plane = !pipe;
12289
12290 if (INTEL_INFO(dev)->gen <= 3) {
12291 intel_primary_formats = intel_primary_formats_gen2;
12292 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12293 } else {
12294 intel_primary_formats = intel_primary_formats_gen4;
12295 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12296 }
12297
12298 drm_universal_plane_init(dev, &primary->base, 0,
12299 &intel_plane_funcs,
12300 intel_primary_formats, num_formats,
12301 DRM_PLANE_TYPE_PRIMARY);
12302
12303 if (INTEL_INFO(dev)->gen >= 4) {
12304 if (!dev->mode_config.rotation_property)
12305 dev->mode_config.rotation_property =
12306 drm_mode_create_rotation_property(dev,
12307 BIT(DRM_ROTATE_0) |
12308 BIT(DRM_ROTATE_180));
12309 if (dev->mode_config.rotation_property)
12310 drm_object_attach_property(&primary->base.base,
12311 dev->mode_config.rotation_property,
12312 state->base.rotation);
12313 }
12314
12315 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12316
12317 return &primary->base;
12318 }
12319
12320 static int
12321 intel_check_cursor_plane(struct drm_plane *plane,
12322 struct intel_plane_state *state)
12323 {
12324 struct drm_crtc *crtc = state->base.crtc;
12325 struct drm_device *dev = plane->dev;
12326 struct drm_framebuffer *fb = state->base.fb;
12327 struct drm_rect *dest = &state->dst;
12328 struct drm_rect *src = &state->src;
12329 const struct drm_rect *clip = &state->clip;
12330 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12331 struct intel_crtc *intel_crtc;
12332 unsigned stride;
12333 int ret;
12334
12335 crtc = crtc ? crtc : plane->crtc;
12336 intel_crtc = to_intel_crtc(crtc);
12337
12338 ret = drm_plane_helper_check_update(plane, crtc, fb,
12339 src, dest, clip,
12340 DRM_PLANE_HELPER_NO_SCALING,
12341 DRM_PLANE_HELPER_NO_SCALING,
12342 true, true, &state->visible);
12343 if (ret)
12344 return ret;
12345
12346
12347 /* if we want to turn off the cursor ignore width and height */
12348 if (!obj)
12349 goto finish;
12350
12351 /* Check for which cursor types we support */
12352 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12353 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12354 state->base.crtc_w, state->base.crtc_h);
12355 return -EINVAL;
12356 }
12357
12358 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12359 if (obj->base.size < stride * state->base.crtc_h) {
12360 DRM_DEBUG_KMS("buffer is too small\n");
12361 return -ENOMEM;
12362 }
12363
12364 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12365 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12366 ret = -EINVAL;
12367 }
12368
12369 finish:
12370 if (intel_crtc->active) {
12371 if (plane->state->crtc_w != state->base.crtc_w)
12372 intel_crtc->atomic.update_wm = true;
12373
12374 intel_crtc->atomic.fb_bits |=
12375 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12376 }
12377
12378 return ret;
12379 }
12380
12381 static void
12382 intel_commit_cursor_plane(struct drm_plane *plane,
12383 struct intel_plane_state *state)
12384 {
12385 struct drm_crtc *crtc = state->base.crtc;
12386 struct drm_device *dev = plane->dev;
12387 struct intel_crtc *intel_crtc;
12388 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12389 uint32_t addr;
12390
12391 crtc = crtc ? crtc : plane->crtc;
12392 intel_crtc = to_intel_crtc(crtc);
12393
12394 plane->fb = state->base.fb;
12395 crtc->cursor_x = state->base.crtc_x;
12396 crtc->cursor_y = state->base.crtc_y;
12397
12398 if (intel_crtc->cursor_bo == obj)
12399 goto update;
12400
12401 if (!obj)
12402 addr = 0;
12403 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12404 addr = i915_gem_obj_ggtt_offset(obj);
12405 else
12406 addr = obj->phys_handle->busaddr;
12407
12408 intel_crtc->cursor_addr = addr;
12409 intel_crtc->cursor_bo = obj;
12410 update:
12411
12412 if (intel_crtc->active)
12413 intel_crtc_update_cursor(crtc, state->visible);
12414 }
12415
12416 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12417 int pipe)
12418 {
12419 struct intel_plane *cursor;
12420 struct intel_plane_state *state;
12421
12422 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12423 if (cursor == NULL)
12424 return NULL;
12425
12426 state = intel_create_plane_state(&cursor->base);
12427 if (!state) {
12428 kfree(cursor);
12429 return NULL;
12430 }
12431 cursor->base.state = &state->base;
12432
12433 cursor->can_scale = false;
12434 cursor->max_downscale = 1;
12435 cursor->pipe = pipe;
12436 cursor->plane = pipe;
12437 cursor->check_plane = intel_check_cursor_plane;
12438 cursor->commit_plane = intel_commit_cursor_plane;
12439
12440 drm_universal_plane_init(dev, &cursor->base, 0,
12441 &intel_plane_funcs,
12442 intel_cursor_formats,
12443 ARRAY_SIZE(intel_cursor_formats),
12444 DRM_PLANE_TYPE_CURSOR);
12445
12446 if (INTEL_INFO(dev)->gen >= 4) {
12447 if (!dev->mode_config.rotation_property)
12448 dev->mode_config.rotation_property =
12449 drm_mode_create_rotation_property(dev,
12450 BIT(DRM_ROTATE_0) |
12451 BIT(DRM_ROTATE_180));
12452 if (dev->mode_config.rotation_property)
12453 drm_object_attach_property(&cursor->base.base,
12454 dev->mode_config.rotation_property,
12455 state->base.rotation);
12456 }
12457
12458 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12459
12460 return &cursor->base;
12461 }
12462
12463 static void intel_crtc_init(struct drm_device *dev, int pipe)
12464 {
12465 struct drm_i915_private *dev_priv = dev->dev_private;
12466 struct intel_crtc *intel_crtc;
12467 struct intel_crtc_state *crtc_state = NULL;
12468 struct drm_plane *primary = NULL;
12469 struct drm_plane *cursor = NULL;
12470 int i, ret;
12471
12472 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12473 if (intel_crtc == NULL)
12474 return;
12475
12476 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12477 if (!crtc_state)
12478 goto fail;
12479 intel_crtc_set_state(intel_crtc, crtc_state);
12480 crtc_state->base.crtc = &intel_crtc->base;
12481
12482 primary = intel_primary_plane_create(dev, pipe);
12483 if (!primary)
12484 goto fail;
12485
12486 cursor = intel_cursor_plane_create(dev, pipe);
12487 if (!cursor)
12488 goto fail;
12489
12490 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12491 cursor, &intel_crtc_funcs);
12492 if (ret)
12493 goto fail;
12494
12495 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12496 for (i = 0; i < 256; i++) {
12497 intel_crtc->lut_r[i] = i;
12498 intel_crtc->lut_g[i] = i;
12499 intel_crtc->lut_b[i] = i;
12500 }
12501
12502 /*
12503 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12504 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12505 */
12506 intel_crtc->pipe = pipe;
12507 intel_crtc->plane = pipe;
12508 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12509 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12510 intel_crtc->plane = !pipe;
12511 }
12512
12513 intel_crtc->cursor_base = ~0;
12514 intel_crtc->cursor_cntl = ~0;
12515 intel_crtc->cursor_size = ~0;
12516
12517 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12518 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12519 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12520 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12521
12522 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12523
12524 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12525
12526 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12527 return;
12528
12529 fail:
12530 if (primary)
12531 drm_plane_cleanup(primary);
12532 if (cursor)
12533 drm_plane_cleanup(cursor);
12534 kfree(crtc_state);
12535 kfree(intel_crtc);
12536 }
12537
12538 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12539 {
12540 struct drm_encoder *encoder = connector->base.encoder;
12541 struct drm_device *dev = connector->base.dev;
12542
12543 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12544
12545 if (!encoder || WARN_ON(!encoder->crtc))
12546 return INVALID_PIPE;
12547
12548 return to_intel_crtc(encoder->crtc)->pipe;
12549 }
12550
12551 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12552 struct drm_file *file)
12553 {
12554 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12555 struct drm_crtc *drmmode_crtc;
12556 struct intel_crtc *crtc;
12557
12558 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12559
12560 if (!drmmode_crtc) {
12561 DRM_ERROR("no such CRTC id\n");
12562 return -ENOENT;
12563 }
12564
12565 crtc = to_intel_crtc(drmmode_crtc);
12566 pipe_from_crtc_id->pipe = crtc->pipe;
12567
12568 return 0;
12569 }
12570
12571 static int intel_encoder_clones(struct intel_encoder *encoder)
12572 {
12573 struct drm_device *dev = encoder->base.dev;
12574 struct intel_encoder *source_encoder;
12575 int index_mask = 0;
12576 int entry = 0;
12577
12578 for_each_intel_encoder(dev, source_encoder) {
12579 if (encoders_cloneable(encoder, source_encoder))
12580 index_mask |= (1 << entry);
12581
12582 entry++;
12583 }
12584
12585 return index_mask;
12586 }
12587
12588 static bool has_edp_a(struct drm_device *dev)
12589 {
12590 struct drm_i915_private *dev_priv = dev->dev_private;
12591
12592 if (!IS_MOBILE(dev))
12593 return false;
12594
12595 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12596 return false;
12597
12598 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12599 return false;
12600
12601 return true;
12602 }
12603
12604 static bool intel_crt_present(struct drm_device *dev)
12605 {
12606 struct drm_i915_private *dev_priv = dev->dev_private;
12607
12608 if (INTEL_INFO(dev)->gen >= 9)
12609 return false;
12610
12611 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12612 return false;
12613
12614 if (IS_CHERRYVIEW(dev))
12615 return false;
12616
12617 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12618 return false;
12619
12620 return true;
12621 }
12622
12623 static void intel_setup_outputs(struct drm_device *dev)
12624 {
12625 struct drm_i915_private *dev_priv = dev->dev_private;
12626 struct intel_encoder *encoder;
12627 struct drm_connector *connector;
12628 bool dpd_is_edp = false;
12629
12630 intel_lvds_init(dev);
12631
12632 if (intel_crt_present(dev))
12633 intel_crt_init(dev);
12634
12635 if (HAS_DDI(dev)) {
12636 int found;
12637
12638 /*
12639 * Haswell uses DDI functions to detect digital outputs.
12640 * On SKL pre-D0 the strap isn't connected, so we assume
12641 * it's there.
12642 */
12643 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12644 /* WaIgnoreDDIAStrap: skl */
12645 if (found ||
12646 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12647 intel_ddi_init(dev, PORT_A);
12648
12649 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12650 * register */
12651 found = I915_READ(SFUSE_STRAP);
12652
12653 if (found & SFUSE_STRAP_DDIB_DETECTED)
12654 intel_ddi_init(dev, PORT_B);
12655 if (found & SFUSE_STRAP_DDIC_DETECTED)
12656 intel_ddi_init(dev, PORT_C);
12657 if (found & SFUSE_STRAP_DDID_DETECTED)
12658 intel_ddi_init(dev, PORT_D);
12659 } else if (HAS_PCH_SPLIT(dev)) {
12660 int found;
12661 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12662
12663 if (has_edp_a(dev))
12664 intel_dp_init(dev, DP_A, PORT_A);
12665
12666 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12667 /* PCH SDVOB multiplex with HDMIB */
12668 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12669 if (!found)
12670 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12671 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12672 intel_dp_init(dev, PCH_DP_B, PORT_B);
12673 }
12674
12675 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12676 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12677
12678 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12679 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12680
12681 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12682 intel_dp_init(dev, PCH_DP_C, PORT_C);
12683
12684 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12685 intel_dp_init(dev, PCH_DP_D, PORT_D);
12686 } else if (IS_VALLEYVIEW(dev)) {
12687 /*
12688 * The DP_DETECTED bit is the latched state of the DDC
12689 * SDA pin at boot. However since eDP doesn't require DDC
12690 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12691 * eDP ports may have been muxed to an alternate function.
12692 * Thus we can't rely on the DP_DETECTED bit alone to detect
12693 * eDP ports. Consult the VBT as well as DP_DETECTED to
12694 * detect eDP ports.
12695 */
12696 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12697 !intel_dp_is_edp(dev, PORT_B))
12698 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12699 PORT_B);
12700 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12701 intel_dp_is_edp(dev, PORT_B))
12702 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12703
12704 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12705 !intel_dp_is_edp(dev, PORT_C))
12706 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12707 PORT_C);
12708 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12709 intel_dp_is_edp(dev, PORT_C))
12710 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12711
12712 if (IS_CHERRYVIEW(dev)) {
12713 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12714 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12715 PORT_D);
12716 /* eDP not supported on port D, so don't check VBT */
12717 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12718 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12719 }
12720
12721 intel_dsi_init(dev);
12722 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12723 bool found = false;
12724
12725 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12726 DRM_DEBUG_KMS("probing SDVOB\n");
12727 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12728 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12729 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12730 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12731 }
12732
12733 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12734 intel_dp_init(dev, DP_B, PORT_B);
12735 }
12736
12737 /* Before G4X SDVOC doesn't have its own detect register */
12738
12739 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12740 DRM_DEBUG_KMS("probing SDVOC\n");
12741 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12742 }
12743
12744 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12745
12746 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12747 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12748 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12749 }
12750 if (SUPPORTS_INTEGRATED_DP(dev))
12751 intel_dp_init(dev, DP_C, PORT_C);
12752 }
12753
12754 if (SUPPORTS_INTEGRATED_DP(dev) &&
12755 (I915_READ(DP_D) & DP_DETECTED))
12756 intel_dp_init(dev, DP_D, PORT_D);
12757 } else if (IS_GEN2(dev))
12758 intel_dvo_init(dev);
12759
12760 if (SUPPORTS_TV(dev))
12761 intel_tv_init(dev);
12762
12763 /*
12764 * FIXME: We don't have full atomic support yet, but we want to be
12765 * able to enable/test plane updates via the atomic interface in the
12766 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12767 * will take some atomic codepaths to lookup properties during
12768 * drmModeGetConnector() that unconditionally dereference
12769 * connector->state.
12770 *
12771 * We create a dummy connector state here for each connector to ensure
12772 * the DRM core doesn't try to dereference a NULL connector->state.
12773 * The actual connector properties will never be updated or contain
12774 * useful information, but since we're doing this specifically for
12775 * testing/debug of the plane operations (and only when a specific
12776 * kernel module option is given), that shouldn't really matter.
12777 *
12778 * Once atomic support for crtc's + connectors lands, this loop should
12779 * be removed since we'll be setting up real connector state, which
12780 * will contain Intel-specific properties.
12781 */
12782 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12783 list_for_each_entry(connector,
12784 &dev->mode_config.connector_list,
12785 head) {
12786 if (!WARN_ON(connector->state)) {
12787 connector->state =
12788 kzalloc(sizeof(*connector->state),
12789 GFP_KERNEL);
12790 }
12791 }
12792 }
12793
12794 intel_psr_init(dev);
12795
12796 for_each_intel_encoder(dev, encoder) {
12797 encoder->base.possible_crtcs = encoder->crtc_mask;
12798 encoder->base.possible_clones =
12799 intel_encoder_clones(encoder);
12800 }
12801
12802 intel_init_pch_refclk(dev);
12803
12804 drm_helper_move_panel_connectors_to_head(dev);
12805 }
12806
12807 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12808 {
12809 struct drm_device *dev = fb->dev;
12810 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12811
12812 drm_framebuffer_cleanup(fb);
12813 mutex_lock(&dev->struct_mutex);
12814 WARN_ON(!intel_fb->obj->framebuffer_references--);
12815 drm_gem_object_unreference(&intel_fb->obj->base);
12816 mutex_unlock(&dev->struct_mutex);
12817 kfree(intel_fb);
12818 }
12819
12820 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12821 struct drm_file *file,
12822 unsigned int *handle)
12823 {
12824 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12825 struct drm_i915_gem_object *obj = intel_fb->obj;
12826
12827 return drm_gem_handle_create(file, &obj->base, handle);
12828 }
12829
12830 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12831 .destroy = intel_user_framebuffer_destroy,
12832 .create_handle = intel_user_framebuffer_create_handle,
12833 };
12834
12835 static
12836 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12837 uint32_t pixel_format)
12838 {
12839 u32 gen = INTEL_INFO(dev)->gen;
12840
12841 if (gen >= 9) {
12842 /* "The stride in bytes must not exceed the of the size of 8K
12843 * pixels and 32K bytes."
12844 */
12845 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12846 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12847 return 32*1024;
12848 } else if (gen >= 4) {
12849 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12850 return 16*1024;
12851 else
12852 return 32*1024;
12853 } else if (gen >= 3) {
12854 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12855 return 8*1024;
12856 else
12857 return 16*1024;
12858 } else {
12859 /* XXX DSPC is limited to 4k tiled */
12860 return 8*1024;
12861 }
12862 }
12863
12864 static int intel_framebuffer_init(struct drm_device *dev,
12865 struct intel_framebuffer *intel_fb,
12866 struct drm_mode_fb_cmd2 *mode_cmd,
12867 struct drm_i915_gem_object *obj)
12868 {
12869 int aligned_height;
12870 int ret;
12871 u32 pitch_limit, stride_alignment;
12872
12873 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12874
12875 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12876 /* Enforce that fb modifier and tiling mode match, but only for
12877 * X-tiled. This is needed for FBC. */
12878 if (!!(obj->tiling_mode == I915_TILING_X) !=
12879 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12880 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12881 return -EINVAL;
12882 }
12883 } else {
12884 if (obj->tiling_mode == I915_TILING_X)
12885 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12886 else if (obj->tiling_mode == I915_TILING_Y) {
12887 DRM_DEBUG("No Y tiling for legacy addfb\n");
12888 return -EINVAL;
12889 }
12890 }
12891
12892 /* Passed in modifier sanity checking. */
12893 switch (mode_cmd->modifier[0]) {
12894 case I915_FORMAT_MOD_Y_TILED:
12895 case I915_FORMAT_MOD_Yf_TILED:
12896 if (INTEL_INFO(dev)->gen < 9) {
12897 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12898 mode_cmd->modifier[0]);
12899 return -EINVAL;
12900 }
12901 case DRM_FORMAT_MOD_NONE:
12902 case I915_FORMAT_MOD_X_TILED:
12903 break;
12904 default:
12905 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12906 mode_cmd->modifier[0]);
12907 return -EINVAL;
12908 }
12909
12910 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12911 mode_cmd->pixel_format);
12912 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12913 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12914 mode_cmd->pitches[0], stride_alignment);
12915 return -EINVAL;
12916 }
12917
12918 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12919 mode_cmd->pixel_format);
12920 if (mode_cmd->pitches[0] > pitch_limit) {
12921 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12922 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12923 "tiled" : "linear",
12924 mode_cmd->pitches[0], pitch_limit);
12925 return -EINVAL;
12926 }
12927
12928 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12929 mode_cmd->pitches[0] != obj->stride) {
12930 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12931 mode_cmd->pitches[0], obj->stride);
12932 return -EINVAL;
12933 }
12934
12935 /* Reject formats not supported by any plane early. */
12936 switch (mode_cmd->pixel_format) {
12937 case DRM_FORMAT_C8:
12938 case DRM_FORMAT_RGB565:
12939 case DRM_FORMAT_XRGB8888:
12940 case DRM_FORMAT_ARGB8888:
12941 break;
12942 case DRM_FORMAT_XRGB1555:
12943 case DRM_FORMAT_ARGB1555:
12944 if (INTEL_INFO(dev)->gen > 3) {
12945 DRM_DEBUG("unsupported pixel format: %s\n",
12946 drm_get_format_name(mode_cmd->pixel_format));
12947 return -EINVAL;
12948 }
12949 break;
12950 case DRM_FORMAT_XBGR8888:
12951 case DRM_FORMAT_ABGR8888:
12952 case DRM_FORMAT_XRGB2101010:
12953 case DRM_FORMAT_ARGB2101010:
12954 case DRM_FORMAT_XBGR2101010:
12955 case DRM_FORMAT_ABGR2101010:
12956 if (INTEL_INFO(dev)->gen < 4) {
12957 DRM_DEBUG("unsupported pixel format: %s\n",
12958 drm_get_format_name(mode_cmd->pixel_format));
12959 return -EINVAL;
12960 }
12961 break;
12962 case DRM_FORMAT_YUYV:
12963 case DRM_FORMAT_UYVY:
12964 case DRM_FORMAT_YVYU:
12965 case DRM_FORMAT_VYUY:
12966 if (INTEL_INFO(dev)->gen < 5) {
12967 DRM_DEBUG("unsupported pixel format: %s\n",
12968 drm_get_format_name(mode_cmd->pixel_format));
12969 return -EINVAL;
12970 }
12971 break;
12972 default:
12973 DRM_DEBUG("unsupported pixel format: %s\n",
12974 drm_get_format_name(mode_cmd->pixel_format));
12975 return -EINVAL;
12976 }
12977
12978 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12979 if (mode_cmd->offsets[0] != 0)
12980 return -EINVAL;
12981
12982 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12983 mode_cmd->pixel_format,
12984 mode_cmd->modifier[0]);
12985 /* FIXME drm helper for size checks (especially planar formats)? */
12986 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12987 return -EINVAL;
12988
12989 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12990 intel_fb->obj = obj;
12991 intel_fb->obj->framebuffer_references++;
12992
12993 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12994 if (ret) {
12995 DRM_ERROR("framebuffer init failed %d\n", ret);
12996 return ret;
12997 }
12998
12999 return 0;
13000 }
13001
13002 static struct drm_framebuffer *
13003 intel_user_framebuffer_create(struct drm_device *dev,
13004 struct drm_file *filp,
13005 struct drm_mode_fb_cmd2 *mode_cmd)
13006 {
13007 struct drm_i915_gem_object *obj;
13008
13009 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13010 mode_cmd->handles[0]));
13011 if (&obj->base == NULL)
13012 return ERR_PTR(-ENOENT);
13013
13014 return intel_framebuffer_create(dev, mode_cmd, obj);
13015 }
13016
13017 #ifndef CONFIG_DRM_I915_FBDEV
13018 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13019 {
13020 }
13021 #endif
13022
13023 static const struct drm_mode_config_funcs intel_mode_funcs = {
13024 .fb_create = intel_user_framebuffer_create,
13025 .output_poll_changed = intel_fbdev_output_poll_changed,
13026 .atomic_check = intel_atomic_check,
13027 .atomic_commit = intel_atomic_commit,
13028 };
13029
13030 /* Set up chip specific display functions */
13031 static void intel_init_display(struct drm_device *dev)
13032 {
13033 struct drm_i915_private *dev_priv = dev->dev_private;
13034
13035 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13036 dev_priv->display.find_dpll = g4x_find_best_dpll;
13037 else if (IS_CHERRYVIEW(dev))
13038 dev_priv->display.find_dpll = chv_find_best_dpll;
13039 else if (IS_VALLEYVIEW(dev))
13040 dev_priv->display.find_dpll = vlv_find_best_dpll;
13041 else if (IS_PINEVIEW(dev))
13042 dev_priv->display.find_dpll = pnv_find_best_dpll;
13043 else
13044 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13045
13046 if (INTEL_INFO(dev)->gen >= 9) {
13047 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13048 dev_priv->display.get_initial_plane_config =
13049 skylake_get_initial_plane_config;
13050 dev_priv->display.crtc_compute_clock =
13051 haswell_crtc_compute_clock;
13052 dev_priv->display.crtc_enable = haswell_crtc_enable;
13053 dev_priv->display.crtc_disable = haswell_crtc_disable;
13054 dev_priv->display.off = ironlake_crtc_off;
13055 dev_priv->display.update_primary_plane =
13056 skylake_update_primary_plane;
13057 } else if (HAS_DDI(dev)) {
13058 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13059 dev_priv->display.get_initial_plane_config =
13060 ironlake_get_initial_plane_config;
13061 dev_priv->display.crtc_compute_clock =
13062 haswell_crtc_compute_clock;
13063 dev_priv->display.crtc_enable = haswell_crtc_enable;
13064 dev_priv->display.crtc_disable = haswell_crtc_disable;
13065 dev_priv->display.off = ironlake_crtc_off;
13066 dev_priv->display.update_primary_plane =
13067 ironlake_update_primary_plane;
13068 } else if (HAS_PCH_SPLIT(dev)) {
13069 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13070 dev_priv->display.get_initial_plane_config =
13071 ironlake_get_initial_plane_config;
13072 dev_priv->display.crtc_compute_clock =
13073 ironlake_crtc_compute_clock;
13074 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13075 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13076 dev_priv->display.off = ironlake_crtc_off;
13077 dev_priv->display.update_primary_plane =
13078 ironlake_update_primary_plane;
13079 } else if (IS_VALLEYVIEW(dev)) {
13080 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13081 dev_priv->display.get_initial_plane_config =
13082 i9xx_get_initial_plane_config;
13083 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13084 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13085 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13086 dev_priv->display.off = i9xx_crtc_off;
13087 dev_priv->display.update_primary_plane =
13088 i9xx_update_primary_plane;
13089 } else {
13090 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13091 dev_priv->display.get_initial_plane_config =
13092 i9xx_get_initial_plane_config;
13093 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13094 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13095 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13096 dev_priv->display.off = i9xx_crtc_off;
13097 dev_priv->display.update_primary_plane =
13098 i9xx_update_primary_plane;
13099 }
13100
13101 /* Returns the core display clock speed */
13102 if (IS_VALLEYVIEW(dev))
13103 dev_priv->display.get_display_clock_speed =
13104 valleyview_get_display_clock_speed;
13105 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13106 dev_priv->display.get_display_clock_speed =
13107 i945_get_display_clock_speed;
13108 else if (IS_I915G(dev))
13109 dev_priv->display.get_display_clock_speed =
13110 i915_get_display_clock_speed;
13111 else if (IS_I945GM(dev) || IS_845G(dev))
13112 dev_priv->display.get_display_clock_speed =
13113 i9xx_misc_get_display_clock_speed;
13114 else if (IS_PINEVIEW(dev))
13115 dev_priv->display.get_display_clock_speed =
13116 pnv_get_display_clock_speed;
13117 else if (IS_I915GM(dev))
13118 dev_priv->display.get_display_clock_speed =
13119 i915gm_get_display_clock_speed;
13120 else if (IS_I865G(dev))
13121 dev_priv->display.get_display_clock_speed =
13122 i865_get_display_clock_speed;
13123 else if (IS_I85X(dev))
13124 dev_priv->display.get_display_clock_speed =
13125 i855_get_display_clock_speed;
13126 else /* 852, 830 */
13127 dev_priv->display.get_display_clock_speed =
13128 i830_get_display_clock_speed;
13129
13130 if (IS_GEN5(dev)) {
13131 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13132 } else if (IS_GEN6(dev)) {
13133 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13134 } else if (IS_IVYBRIDGE(dev)) {
13135 /* FIXME: detect B0+ stepping and use auto training */
13136 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13137 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13138 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13139 } else if (IS_VALLEYVIEW(dev)) {
13140 dev_priv->display.modeset_global_resources =
13141 valleyview_modeset_global_resources;
13142 }
13143
13144 switch (INTEL_INFO(dev)->gen) {
13145 case 2:
13146 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13147 break;
13148
13149 case 3:
13150 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13151 break;
13152
13153 case 4:
13154 case 5:
13155 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13156 break;
13157
13158 case 6:
13159 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13160 break;
13161 case 7:
13162 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13163 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13164 break;
13165 case 9:
13166 /* Drop through - unsupported since execlist only. */
13167 default:
13168 /* Default just returns -ENODEV to indicate unsupported */
13169 dev_priv->display.queue_flip = intel_default_queue_flip;
13170 }
13171
13172 intel_panel_init_backlight_funcs(dev);
13173
13174 mutex_init(&dev_priv->pps_mutex);
13175 }
13176
13177 /*
13178 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13179 * resume, or other times. This quirk makes sure that's the case for
13180 * affected systems.
13181 */
13182 static void quirk_pipea_force(struct drm_device *dev)
13183 {
13184 struct drm_i915_private *dev_priv = dev->dev_private;
13185
13186 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13187 DRM_INFO("applying pipe a force quirk\n");
13188 }
13189
13190 static void quirk_pipeb_force(struct drm_device *dev)
13191 {
13192 struct drm_i915_private *dev_priv = dev->dev_private;
13193
13194 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13195 DRM_INFO("applying pipe b force quirk\n");
13196 }
13197
13198 /*
13199 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13200 */
13201 static void quirk_ssc_force_disable(struct drm_device *dev)
13202 {
13203 struct drm_i915_private *dev_priv = dev->dev_private;
13204 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13205 DRM_INFO("applying lvds SSC disable quirk\n");
13206 }
13207
13208 /*
13209 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13210 * brightness value
13211 */
13212 static void quirk_invert_brightness(struct drm_device *dev)
13213 {
13214 struct drm_i915_private *dev_priv = dev->dev_private;
13215 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13216 DRM_INFO("applying inverted panel brightness quirk\n");
13217 }
13218
13219 /* Some VBT's incorrectly indicate no backlight is present */
13220 static void quirk_backlight_present(struct drm_device *dev)
13221 {
13222 struct drm_i915_private *dev_priv = dev->dev_private;
13223 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13224 DRM_INFO("applying backlight present quirk\n");
13225 }
13226
13227 struct intel_quirk {
13228 int device;
13229 int subsystem_vendor;
13230 int subsystem_device;
13231 void (*hook)(struct drm_device *dev);
13232 };
13233
13234 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13235 struct intel_dmi_quirk {
13236 void (*hook)(struct drm_device *dev);
13237 const struct dmi_system_id (*dmi_id_list)[];
13238 };
13239
13240 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13241 {
13242 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13243 return 1;
13244 }
13245
13246 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13247 {
13248 .dmi_id_list = &(const struct dmi_system_id[]) {
13249 {
13250 .callback = intel_dmi_reverse_brightness,
13251 .ident = "NCR Corporation",
13252 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13253 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13254 },
13255 },
13256 { } /* terminating entry */
13257 },
13258 .hook = quirk_invert_brightness,
13259 },
13260 };
13261
13262 static struct intel_quirk intel_quirks[] = {
13263 /* HP Mini needs pipe A force quirk (LP: #322104) */
13264 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13265
13266 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13267 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13268
13269 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13270 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13271
13272 /* 830 needs to leave pipe A & dpll A up */
13273 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13274
13275 /* 830 needs to leave pipe B & dpll B up */
13276 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13277
13278 /* Lenovo U160 cannot use SSC on LVDS */
13279 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13280
13281 /* Sony Vaio Y cannot use SSC on LVDS */
13282 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13283
13284 /* Acer Aspire 5734Z must invert backlight brightness */
13285 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13286
13287 /* Acer/eMachines G725 */
13288 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13289
13290 /* Acer/eMachines e725 */
13291 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13292
13293 /* Acer/Packard Bell NCL20 */
13294 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13295
13296 /* Acer Aspire 4736Z */
13297 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13298
13299 /* Acer Aspire 5336 */
13300 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13301
13302 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13303 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13304
13305 /* Acer C720 Chromebook (Core i3 4005U) */
13306 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13307
13308 /* Apple Macbook 2,1 (Core 2 T7400) */
13309 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13310
13311 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13312 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13313
13314 /* HP Chromebook 14 (Celeron 2955U) */
13315 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13316
13317 /* Dell Chromebook 11 */
13318 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13319 };
13320
13321 static void intel_init_quirks(struct drm_device *dev)
13322 {
13323 struct pci_dev *d = dev->pdev;
13324 int i;
13325
13326 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13327 struct intel_quirk *q = &intel_quirks[i];
13328
13329 if (d->device == q->device &&
13330 (d->subsystem_vendor == q->subsystem_vendor ||
13331 q->subsystem_vendor == PCI_ANY_ID) &&
13332 (d->subsystem_device == q->subsystem_device ||
13333 q->subsystem_device == PCI_ANY_ID))
13334 q->hook(dev);
13335 }
13336 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13337 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13338 intel_dmi_quirks[i].hook(dev);
13339 }
13340 }
13341
13342 /* Disable the VGA plane that we never use */
13343 static void i915_disable_vga(struct drm_device *dev)
13344 {
13345 struct drm_i915_private *dev_priv = dev->dev_private;
13346 u8 sr1;
13347 u32 vga_reg = i915_vgacntrl_reg(dev);
13348
13349 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13350 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13351 outb(SR01, VGA_SR_INDEX);
13352 sr1 = inb(VGA_SR_DATA);
13353 outb(sr1 | 1<<5, VGA_SR_DATA);
13354 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13355 udelay(300);
13356
13357 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13358 POSTING_READ(vga_reg);
13359 }
13360
13361 void intel_modeset_init_hw(struct drm_device *dev)
13362 {
13363 intel_prepare_ddi(dev);
13364
13365 if (IS_VALLEYVIEW(dev))
13366 vlv_update_cdclk(dev);
13367
13368 intel_init_clock_gating(dev);
13369
13370 intel_enable_gt_powersave(dev);
13371 }
13372
13373 void intel_modeset_init(struct drm_device *dev)
13374 {
13375 struct drm_i915_private *dev_priv = dev->dev_private;
13376 int sprite, ret;
13377 enum pipe pipe;
13378 struct intel_crtc *crtc;
13379
13380 drm_mode_config_init(dev);
13381
13382 dev->mode_config.min_width = 0;
13383 dev->mode_config.min_height = 0;
13384
13385 dev->mode_config.preferred_depth = 24;
13386 dev->mode_config.prefer_shadow = 1;
13387
13388 dev->mode_config.allow_fb_modifiers = true;
13389
13390 dev->mode_config.funcs = &intel_mode_funcs;
13391
13392 intel_init_quirks(dev);
13393
13394 intel_init_pm(dev);
13395
13396 if (INTEL_INFO(dev)->num_pipes == 0)
13397 return;
13398
13399 intel_init_display(dev);
13400 intel_init_audio(dev);
13401
13402 if (IS_GEN2(dev)) {
13403 dev->mode_config.max_width = 2048;
13404 dev->mode_config.max_height = 2048;
13405 } else if (IS_GEN3(dev)) {
13406 dev->mode_config.max_width = 4096;
13407 dev->mode_config.max_height = 4096;
13408 } else {
13409 dev->mode_config.max_width = 8192;
13410 dev->mode_config.max_height = 8192;
13411 }
13412
13413 if (IS_845G(dev) || IS_I865G(dev)) {
13414 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13415 dev->mode_config.cursor_height = 1023;
13416 } else if (IS_GEN2(dev)) {
13417 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13418 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13419 } else {
13420 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13421 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13422 }
13423
13424 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13425
13426 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13427 INTEL_INFO(dev)->num_pipes,
13428 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13429
13430 for_each_pipe(dev_priv, pipe) {
13431 intel_crtc_init(dev, pipe);
13432 for_each_sprite(dev_priv, pipe, sprite) {
13433 ret = intel_plane_init(dev, pipe, sprite);
13434 if (ret)
13435 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13436 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13437 }
13438 }
13439
13440 intel_init_dpio(dev);
13441
13442 intel_shared_dpll_init(dev);
13443
13444 /* Just disable it once at startup */
13445 i915_disable_vga(dev);
13446 intel_setup_outputs(dev);
13447
13448 /* Just in case the BIOS is doing something questionable. */
13449 intel_fbc_disable(dev);
13450
13451 drm_modeset_lock_all(dev);
13452 intel_modeset_setup_hw_state(dev, false);
13453 drm_modeset_unlock_all(dev);
13454
13455 for_each_intel_crtc(dev, crtc) {
13456 if (!crtc->active)
13457 continue;
13458
13459 /*
13460 * Note that reserving the BIOS fb up front prevents us
13461 * from stuffing other stolen allocations like the ring
13462 * on top. This prevents some ugliness at boot time, and
13463 * can even allow for smooth boot transitions if the BIOS
13464 * fb is large enough for the active pipe configuration.
13465 */
13466 if (dev_priv->display.get_initial_plane_config) {
13467 dev_priv->display.get_initial_plane_config(crtc,
13468 &crtc->plane_config);
13469 /*
13470 * If the fb is shared between multiple heads, we'll
13471 * just get the first one.
13472 */
13473 intel_find_plane_obj(crtc, &crtc->plane_config);
13474 }
13475 }
13476 }
13477
13478 static void intel_enable_pipe_a(struct drm_device *dev)
13479 {
13480 struct intel_connector *connector;
13481 struct drm_connector *crt = NULL;
13482 struct intel_load_detect_pipe load_detect_temp;
13483 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13484
13485 /* We can't just switch on the pipe A, we need to set things up with a
13486 * proper mode and output configuration. As a gross hack, enable pipe A
13487 * by enabling the load detect pipe once. */
13488 for_each_intel_connector(dev, connector) {
13489 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13490 crt = &connector->base;
13491 break;
13492 }
13493 }
13494
13495 if (!crt)
13496 return;
13497
13498 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13499 intel_release_load_detect_pipe(crt, &load_detect_temp);
13500 }
13501
13502 static bool
13503 intel_check_plane_mapping(struct intel_crtc *crtc)
13504 {
13505 struct drm_device *dev = crtc->base.dev;
13506 struct drm_i915_private *dev_priv = dev->dev_private;
13507 u32 reg, val;
13508
13509 if (INTEL_INFO(dev)->num_pipes == 1)
13510 return true;
13511
13512 reg = DSPCNTR(!crtc->plane);
13513 val = I915_READ(reg);
13514
13515 if ((val & DISPLAY_PLANE_ENABLE) &&
13516 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13517 return false;
13518
13519 return true;
13520 }
13521
13522 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13523 {
13524 struct drm_device *dev = crtc->base.dev;
13525 struct drm_i915_private *dev_priv = dev->dev_private;
13526 u32 reg;
13527
13528 /* Clear any frame start delays used for debugging left by the BIOS */
13529 reg = PIPECONF(crtc->config->cpu_transcoder);
13530 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13531
13532 /* restore vblank interrupts to correct state */
13533 drm_crtc_vblank_reset(&crtc->base);
13534 if (crtc->active) {
13535 update_scanline_offset(crtc);
13536 drm_crtc_vblank_on(&crtc->base);
13537 }
13538
13539 /* We need to sanitize the plane -> pipe mapping first because this will
13540 * disable the crtc (and hence change the state) if it is wrong. Note
13541 * that gen4+ has a fixed plane -> pipe mapping. */
13542 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13543 struct intel_connector *connector;
13544 bool plane;
13545
13546 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13547 crtc->base.base.id);
13548
13549 /* Pipe has the wrong plane attached and the plane is active.
13550 * Temporarily change the plane mapping and disable everything
13551 * ... */
13552 plane = crtc->plane;
13553 crtc->plane = !plane;
13554 crtc->primary_enabled = true;
13555 dev_priv->display.crtc_disable(&crtc->base);
13556 crtc->plane = plane;
13557
13558 /* ... and break all links. */
13559 for_each_intel_connector(dev, connector) {
13560 if (connector->encoder->base.crtc != &crtc->base)
13561 continue;
13562
13563 connector->base.dpms = DRM_MODE_DPMS_OFF;
13564 connector->base.encoder = NULL;
13565 }
13566 /* multiple connectors may have the same encoder:
13567 * handle them and break crtc link separately */
13568 for_each_intel_connector(dev, connector)
13569 if (connector->encoder->base.crtc == &crtc->base) {
13570 connector->encoder->base.crtc = NULL;
13571 connector->encoder->connectors_active = false;
13572 }
13573
13574 WARN_ON(crtc->active);
13575 crtc->base.state->enable = false;
13576 crtc->base.enabled = false;
13577 }
13578
13579 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13580 crtc->pipe == PIPE_A && !crtc->active) {
13581 /* BIOS forgot to enable pipe A, this mostly happens after
13582 * resume. Force-enable the pipe to fix this, the update_dpms
13583 * call below we restore the pipe to the right state, but leave
13584 * the required bits on. */
13585 intel_enable_pipe_a(dev);
13586 }
13587
13588 /* Adjust the state of the output pipe according to whether we
13589 * have active connectors/encoders. */
13590 intel_crtc_update_dpms(&crtc->base);
13591
13592 if (crtc->active != crtc->base.state->enable) {
13593 struct intel_encoder *encoder;
13594
13595 /* This can happen either due to bugs in the get_hw_state
13596 * functions or because the pipe is force-enabled due to the
13597 * pipe A quirk. */
13598 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13599 crtc->base.base.id,
13600 crtc->base.state->enable ? "enabled" : "disabled",
13601 crtc->active ? "enabled" : "disabled");
13602
13603 crtc->base.state->enable = crtc->active;
13604 crtc->base.enabled = crtc->active;
13605
13606 /* Because we only establish the connector -> encoder ->
13607 * crtc links if something is active, this means the
13608 * crtc is now deactivated. Break the links. connector
13609 * -> encoder links are only establish when things are
13610 * actually up, hence no need to break them. */
13611 WARN_ON(crtc->active);
13612
13613 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13614 WARN_ON(encoder->connectors_active);
13615 encoder->base.crtc = NULL;
13616 }
13617 }
13618
13619 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13620 /*
13621 * We start out with underrun reporting disabled to avoid races.
13622 * For correct bookkeeping mark this on active crtcs.
13623 *
13624 * Also on gmch platforms we dont have any hardware bits to
13625 * disable the underrun reporting. Which means we need to start
13626 * out with underrun reporting disabled also on inactive pipes,
13627 * since otherwise we'll complain about the garbage we read when
13628 * e.g. coming up after runtime pm.
13629 *
13630 * No protection against concurrent access is required - at
13631 * worst a fifo underrun happens which also sets this to false.
13632 */
13633 crtc->cpu_fifo_underrun_disabled = true;
13634 crtc->pch_fifo_underrun_disabled = true;
13635 }
13636 }
13637
13638 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13639 {
13640 struct intel_connector *connector;
13641 struct drm_device *dev = encoder->base.dev;
13642
13643 /* We need to check both for a crtc link (meaning that the
13644 * encoder is active and trying to read from a pipe) and the
13645 * pipe itself being active. */
13646 bool has_active_crtc = encoder->base.crtc &&
13647 to_intel_crtc(encoder->base.crtc)->active;
13648
13649 if (encoder->connectors_active && !has_active_crtc) {
13650 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13651 encoder->base.base.id,
13652 encoder->base.name);
13653
13654 /* Connector is active, but has no active pipe. This is
13655 * fallout from our resume register restoring. Disable
13656 * the encoder manually again. */
13657 if (encoder->base.crtc) {
13658 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13659 encoder->base.base.id,
13660 encoder->base.name);
13661 encoder->disable(encoder);
13662 if (encoder->post_disable)
13663 encoder->post_disable(encoder);
13664 }
13665 encoder->base.crtc = NULL;
13666 encoder->connectors_active = false;
13667
13668 /* Inconsistent output/port/pipe state happens presumably due to
13669 * a bug in one of the get_hw_state functions. Or someplace else
13670 * in our code, like the register restore mess on resume. Clamp
13671 * things to off as a safer default. */
13672 for_each_intel_connector(dev, connector) {
13673 if (connector->encoder != encoder)
13674 continue;
13675 connector->base.dpms = DRM_MODE_DPMS_OFF;
13676 connector->base.encoder = NULL;
13677 }
13678 }
13679 /* Enabled encoders without active connectors will be fixed in
13680 * the crtc fixup. */
13681 }
13682
13683 void i915_redisable_vga_power_on(struct drm_device *dev)
13684 {
13685 struct drm_i915_private *dev_priv = dev->dev_private;
13686 u32 vga_reg = i915_vgacntrl_reg(dev);
13687
13688 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13689 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13690 i915_disable_vga(dev);
13691 }
13692 }
13693
13694 void i915_redisable_vga(struct drm_device *dev)
13695 {
13696 struct drm_i915_private *dev_priv = dev->dev_private;
13697
13698 /* This function can be called both from intel_modeset_setup_hw_state or
13699 * at a very early point in our resume sequence, where the power well
13700 * structures are not yet restored. Since this function is at a very
13701 * paranoid "someone might have enabled VGA while we were not looking"
13702 * level, just check if the power well is enabled instead of trying to
13703 * follow the "don't touch the power well if we don't need it" policy
13704 * the rest of the driver uses. */
13705 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13706 return;
13707
13708 i915_redisable_vga_power_on(dev);
13709 }
13710
13711 static bool primary_get_hw_state(struct intel_crtc *crtc)
13712 {
13713 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13714
13715 if (!crtc->active)
13716 return false;
13717
13718 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13719 }
13720
13721 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13722 {
13723 struct drm_i915_private *dev_priv = dev->dev_private;
13724 enum pipe pipe;
13725 struct intel_crtc *crtc;
13726 struct intel_encoder *encoder;
13727 struct intel_connector *connector;
13728 int i;
13729
13730 for_each_intel_crtc(dev, crtc) {
13731 memset(crtc->config, 0, sizeof(*crtc->config));
13732
13733 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13734
13735 crtc->active = dev_priv->display.get_pipe_config(crtc,
13736 crtc->config);
13737
13738 crtc->base.state->enable = crtc->active;
13739 crtc->base.enabled = crtc->active;
13740 crtc->primary_enabled = primary_get_hw_state(crtc);
13741
13742 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13743 crtc->base.base.id,
13744 crtc->active ? "enabled" : "disabled");
13745 }
13746
13747 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13748 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13749
13750 pll->on = pll->get_hw_state(dev_priv, pll,
13751 &pll->config.hw_state);
13752 pll->active = 0;
13753 pll->config.crtc_mask = 0;
13754 for_each_intel_crtc(dev, crtc) {
13755 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13756 pll->active++;
13757 pll->config.crtc_mask |= 1 << crtc->pipe;
13758 }
13759 }
13760
13761 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13762 pll->name, pll->config.crtc_mask, pll->on);
13763
13764 if (pll->config.crtc_mask)
13765 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13766 }
13767
13768 for_each_intel_encoder(dev, encoder) {
13769 pipe = 0;
13770
13771 if (encoder->get_hw_state(encoder, &pipe)) {
13772 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13773 encoder->base.crtc = &crtc->base;
13774 encoder->get_config(encoder, crtc->config);
13775 } else {
13776 encoder->base.crtc = NULL;
13777 }
13778
13779 encoder->connectors_active = false;
13780 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13781 encoder->base.base.id,
13782 encoder->base.name,
13783 encoder->base.crtc ? "enabled" : "disabled",
13784 pipe_name(pipe));
13785 }
13786
13787 for_each_intel_connector(dev, connector) {
13788 if (connector->get_hw_state(connector)) {
13789 connector->base.dpms = DRM_MODE_DPMS_ON;
13790 connector->encoder->connectors_active = true;
13791 connector->base.encoder = &connector->encoder->base;
13792 } else {
13793 connector->base.dpms = DRM_MODE_DPMS_OFF;
13794 connector->base.encoder = NULL;
13795 }
13796 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13797 connector->base.base.id,
13798 connector->base.name,
13799 connector->base.encoder ? "enabled" : "disabled");
13800 }
13801 }
13802
13803 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13804 * and i915 state tracking structures. */
13805 void intel_modeset_setup_hw_state(struct drm_device *dev,
13806 bool force_restore)
13807 {
13808 struct drm_i915_private *dev_priv = dev->dev_private;
13809 enum pipe pipe;
13810 struct intel_crtc *crtc;
13811 struct intel_encoder *encoder;
13812 int i;
13813
13814 intel_modeset_readout_hw_state(dev);
13815
13816 /*
13817 * Now that we have the config, copy it to each CRTC struct
13818 * Note that this could go away if we move to using crtc_config
13819 * checking everywhere.
13820 */
13821 for_each_intel_crtc(dev, crtc) {
13822 if (crtc->active && i915.fastboot) {
13823 intel_mode_from_pipe_config(&crtc->base.mode,
13824 crtc->config);
13825 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13826 crtc->base.base.id);
13827 drm_mode_debug_printmodeline(&crtc->base.mode);
13828 }
13829 }
13830
13831 /* HW state is read out, now we need to sanitize this mess. */
13832 for_each_intel_encoder(dev, encoder) {
13833 intel_sanitize_encoder(encoder);
13834 }
13835
13836 for_each_pipe(dev_priv, pipe) {
13837 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13838 intel_sanitize_crtc(crtc);
13839 intel_dump_pipe_config(crtc, crtc->config,
13840 "[setup_hw_state]");
13841 }
13842
13843 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13844 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13845
13846 if (!pll->on || pll->active)
13847 continue;
13848
13849 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13850
13851 pll->disable(dev_priv, pll);
13852 pll->on = false;
13853 }
13854
13855 if (IS_GEN9(dev))
13856 skl_wm_get_hw_state(dev);
13857 else if (HAS_PCH_SPLIT(dev))
13858 ilk_wm_get_hw_state(dev);
13859
13860 if (force_restore) {
13861 i915_redisable_vga(dev);
13862
13863 /*
13864 * We need to use raw interfaces for restoring state to avoid
13865 * checking (bogus) intermediate states.
13866 */
13867 for_each_pipe(dev_priv, pipe) {
13868 struct drm_crtc *crtc =
13869 dev_priv->pipe_to_crtc_mapping[pipe];
13870
13871 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13872 crtc->primary->fb);
13873 }
13874 } else {
13875 intel_modeset_update_staged_output_state(dev);
13876 }
13877
13878 intel_modeset_check_state(dev);
13879 }
13880
13881 void intel_modeset_gem_init(struct drm_device *dev)
13882 {
13883 struct drm_i915_private *dev_priv = dev->dev_private;
13884 struct drm_crtc *c;
13885 struct drm_i915_gem_object *obj;
13886
13887 mutex_lock(&dev->struct_mutex);
13888 intel_init_gt_powersave(dev);
13889 mutex_unlock(&dev->struct_mutex);
13890
13891 /*
13892 * There may be no VBT; and if the BIOS enabled SSC we can
13893 * just keep using it to avoid unnecessary flicker. Whereas if the
13894 * BIOS isn't using it, don't assume it will work even if the VBT
13895 * indicates as much.
13896 */
13897 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13898 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13899 DREF_SSC1_ENABLE);
13900
13901 intel_modeset_init_hw(dev);
13902
13903 intel_setup_overlay(dev);
13904
13905 /*
13906 * Make sure any fbs we allocated at startup are properly
13907 * pinned & fenced. When we do the allocation it's too early
13908 * for this.
13909 */
13910 mutex_lock(&dev->struct_mutex);
13911 for_each_crtc(dev, c) {
13912 obj = intel_fb_obj(c->primary->fb);
13913 if (obj == NULL)
13914 continue;
13915
13916 if (intel_pin_and_fence_fb_obj(c->primary,
13917 c->primary->fb,
13918 NULL)) {
13919 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13920 to_intel_crtc(c)->pipe);
13921 drm_framebuffer_unreference(c->primary->fb);
13922 c->primary->fb = NULL;
13923 update_state_fb(c->primary);
13924 }
13925 }
13926 mutex_unlock(&dev->struct_mutex);
13927
13928 intel_backlight_register(dev);
13929 }
13930
13931 void intel_connector_unregister(struct intel_connector *intel_connector)
13932 {
13933 struct drm_connector *connector = &intel_connector->base;
13934
13935 intel_panel_destroy_backlight(connector);
13936 drm_connector_unregister(connector);
13937 }
13938
13939 void intel_modeset_cleanup(struct drm_device *dev)
13940 {
13941 struct drm_i915_private *dev_priv = dev->dev_private;
13942 struct drm_connector *connector;
13943
13944 intel_disable_gt_powersave(dev);
13945
13946 intel_backlight_unregister(dev);
13947
13948 /*
13949 * Interrupts and polling as the first thing to avoid creating havoc.
13950 * Too much stuff here (turning of connectors, ...) would
13951 * experience fancy races otherwise.
13952 */
13953 intel_irq_uninstall(dev_priv);
13954
13955 /*
13956 * Due to the hpd irq storm handling the hotplug work can re-arm the
13957 * poll handlers. Hence disable polling after hpd handling is shut down.
13958 */
13959 drm_kms_helper_poll_fini(dev);
13960
13961 mutex_lock(&dev->struct_mutex);
13962
13963 intel_unregister_dsm_handler();
13964
13965 intel_fbc_disable(dev);
13966
13967 mutex_unlock(&dev->struct_mutex);
13968
13969 /* flush any delayed tasks or pending work */
13970 flush_scheduled_work();
13971
13972 /* destroy the backlight and sysfs files before encoders/connectors */
13973 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13974 struct intel_connector *intel_connector;
13975
13976 intel_connector = to_intel_connector(connector);
13977 intel_connector->unregister(intel_connector);
13978 }
13979
13980 drm_mode_config_cleanup(dev);
13981
13982 intel_cleanup_overlay(dev);
13983
13984 mutex_lock(&dev->struct_mutex);
13985 intel_cleanup_gt_powersave(dev);
13986 mutex_unlock(&dev->struct_mutex);
13987 }
13988
13989 /*
13990 * Return which encoder is currently attached for connector.
13991 */
13992 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13993 {
13994 return &intel_attached_encoder(connector)->base;
13995 }
13996
13997 void intel_connector_attach_encoder(struct intel_connector *connector,
13998 struct intel_encoder *encoder)
13999 {
14000 connector->encoder = encoder;
14001 drm_mode_connector_attach_encoder(&connector->base,
14002 &encoder->base);
14003 }
14004
14005 /*
14006 * set vga decode state - true == enable VGA decode
14007 */
14008 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14009 {
14010 struct drm_i915_private *dev_priv = dev->dev_private;
14011 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14012 u16 gmch_ctrl;
14013
14014 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14015 DRM_ERROR("failed to read control word\n");
14016 return -EIO;
14017 }
14018
14019 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14020 return 0;
14021
14022 if (state)
14023 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14024 else
14025 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14026
14027 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14028 DRM_ERROR("failed to write control word\n");
14029 return -EIO;
14030 }
14031
14032 return 0;
14033 }
14034
14035 struct intel_display_error_state {
14036
14037 u32 power_well_driver;
14038
14039 int num_transcoders;
14040
14041 struct intel_cursor_error_state {
14042 u32 control;
14043 u32 position;
14044 u32 base;
14045 u32 size;
14046 } cursor[I915_MAX_PIPES];
14047
14048 struct intel_pipe_error_state {
14049 bool power_domain_on;
14050 u32 source;
14051 u32 stat;
14052 } pipe[I915_MAX_PIPES];
14053
14054 struct intel_plane_error_state {
14055 u32 control;
14056 u32 stride;
14057 u32 size;
14058 u32 pos;
14059 u32 addr;
14060 u32 surface;
14061 u32 tile_offset;
14062 } plane[I915_MAX_PIPES];
14063
14064 struct intel_transcoder_error_state {
14065 bool power_domain_on;
14066 enum transcoder cpu_transcoder;
14067
14068 u32 conf;
14069
14070 u32 htotal;
14071 u32 hblank;
14072 u32 hsync;
14073 u32 vtotal;
14074 u32 vblank;
14075 u32 vsync;
14076 } transcoder[4];
14077 };
14078
14079 struct intel_display_error_state *
14080 intel_display_capture_error_state(struct drm_device *dev)
14081 {
14082 struct drm_i915_private *dev_priv = dev->dev_private;
14083 struct intel_display_error_state *error;
14084 int transcoders[] = {
14085 TRANSCODER_A,
14086 TRANSCODER_B,
14087 TRANSCODER_C,
14088 TRANSCODER_EDP,
14089 };
14090 int i;
14091
14092 if (INTEL_INFO(dev)->num_pipes == 0)
14093 return NULL;
14094
14095 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14096 if (error == NULL)
14097 return NULL;
14098
14099 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14100 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14101
14102 for_each_pipe(dev_priv, i) {
14103 error->pipe[i].power_domain_on =
14104 __intel_display_power_is_enabled(dev_priv,
14105 POWER_DOMAIN_PIPE(i));
14106 if (!error->pipe[i].power_domain_on)
14107 continue;
14108
14109 error->cursor[i].control = I915_READ(CURCNTR(i));
14110 error->cursor[i].position = I915_READ(CURPOS(i));
14111 error->cursor[i].base = I915_READ(CURBASE(i));
14112
14113 error->plane[i].control = I915_READ(DSPCNTR(i));
14114 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14115 if (INTEL_INFO(dev)->gen <= 3) {
14116 error->plane[i].size = I915_READ(DSPSIZE(i));
14117 error->plane[i].pos = I915_READ(DSPPOS(i));
14118 }
14119 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14120 error->plane[i].addr = I915_READ(DSPADDR(i));
14121 if (INTEL_INFO(dev)->gen >= 4) {
14122 error->plane[i].surface = I915_READ(DSPSURF(i));
14123 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14124 }
14125
14126 error->pipe[i].source = I915_READ(PIPESRC(i));
14127
14128 if (HAS_GMCH_DISPLAY(dev))
14129 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14130 }
14131
14132 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14133 if (HAS_DDI(dev_priv->dev))
14134 error->num_transcoders++; /* Account for eDP. */
14135
14136 for (i = 0; i < error->num_transcoders; i++) {
14137 enum transcoder cpu_transcoder = transcoders[i];
14138
14139 error->transcoder[i].power_domain_on =
14140 __intel_display_power_is_enabled(dev_priv,
14141 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14142 if (!error->transcoder[i].power_domain_on)
14143 continue;
14144
14145 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14146
14147 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14148 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14149 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14150 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14151 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14152 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14153 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14154 }
14155
14156 return error;
14157 }
14158
14159 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14160
14161 void
14162 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14163 struct drm_device *dev,
14164 struct intel_display_error_state *error)
14165 {
14166 struct drm_i915_private *dev_priv = dev->dev_private;
14167 int i;
14168
14169 if (!error)
14170 return;
14171
14172 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14173 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14174 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14175 error->power_well_driver);
14176 for_each_pipe(dev_priv, i) {
14177 err_printf(m, "Pipe [%d]:\n", i);
14178 err_printf(m, " Power: %s\n",
14179 error->pipe[i].power_domain_on ? "on" : "off");
14180 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14181 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14182
14183 err_printf(m, "Plane [%d]:\n", i);
14184 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14185 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14186 if (INTEL_INFO(dev)->gen <= 3) {
14187 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14188 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14189 }
14190 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14191 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14192 if (INTEL_INFO(dev)->gen >= 4) {
14193 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14194 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14195 }
14196
14197 err_printf(m, "Cursor [%d]:\n", i);
14198 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14199 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14200 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14201 }
14202
14203 for (i = 0; i < error->num_transcoders; i++) {
14204 err_printf(m, "CPU transcoder: %c\n",
14205 transcoder_name(error->transcoder[i].cpu_transcoder));
14206 err_printf(m, " Power: %s\n",
14207 error->transcoder[i].power_domain_on ? "on" : "off");
14208 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14209 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14210 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14211 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14212 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14213 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14214 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14215 }
14216 }
14217
14218 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14219 {
14220 struct intel_crtc *crtc;
14221
14222 for_each_intel_crtc(dev, crtc) {
14223 struct intel_unpin_work *work;
14224
14225 spin_lock_irq(&dev->event_lock);
14226
14227 work = crtc->unpin_work;
14228
14229 if (work && work->event &&
14230 work->event->base.file_priv == file) {
14231 kfree(work->event);
14232 work->event = NULL;
14233 }
14234
14235 spin_unlock_irq(&dev->event_lock);
14236 }
14237 }
Linux kernel - Deliverables
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