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drm/i915: Switch intel_fb_align_height to fb format modifiers
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_dp_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_rect.h>
45 #include <linux/dma_remapping.h>
46
47 /* Primary plane formats supported by all gen */
48 #define COMMON_PRIMARY_FORMATS \
49 DRM_FORMAT_C8, \
50 DRM_FORMAT_RGB565, \
51 DRM_FORMAT_XRGB8888, \
52 DRM_FORMAT_ARGB8888
53
54 /* Primary plane formats for gen <= 3 */
55 static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
57 DRM_FORMAT_XRGB1555,
58 DRM_FORMAT_ARGB1555,
59 };
60
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_ABGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
70 };
71
72 /* Cursor formats */
73 static const uint32_t intel_cursor_formats[] = {
74 DRM_FORMAT_ARGB8888,
75 };
76
77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78
79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
80 struct intel_crtc_state *pipe_config);
81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
82 struct intel_crtc_state *pipe_config);
83
84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
86 static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
98 static void vlv_prepare_pll(struct intel_crtc *crtc,
99 const struct intel_crtc_state *pipe_config);
100 static void chv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
415 {
416 struct drm_device *dev = crtc->base.dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 /**
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
430 * encoder->crtc.
431 */
432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
433 {
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
436
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
439 return true;
440
441 return false;
442 }
443
444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
445 int refclk)
446 {
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev)) {
452 if (refclk == 100000)
453 limit = &intel_limits_ironlake_dual_lvds_100m;
454 else
455 limit = &intel_limits_ironlake_dual_lvds;
456 } else {
457 if (refclk == 100000)
458 limit = &intel_limits_ironlake_single_lvds_100m;
459 else
460 limit = &intel_limits_ironlake_single_lvds;
461 }
462 } else
463 limit = &intel_limits_ironlake_dac;
464
465 return limit;
466 }
467
468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
469 {
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
472
473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (intel_is_dual_link_lvds(dev))
475 limit = &intel_limits_g4x_dual_channel_lvds;
476 else
477 limit = &intel_limits_g4x_single_channel_lvds;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
480 limit = &intel_limits_g4x_hdmi;
481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
482 limit = &intel_limits_g4x_sdvo;
483 } else /* The option is for other outputs */
484 limit = &intel_limits_i9xx_sdvo;
485
486 return limit;
487 }
488
489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
490 {
491 struct drm_device *dev = crtc->base.dev;
492 const intel_limit_t *limit;
493
494 if (HAS_PCH_SPLIT(dev))
495 limit = intel_ironlake_limit(crtc, refclk);
496 else if (IS_G4X(dev)) {
497 limit = intel_g4x_limit(crtc);
498 } else if (IS_PINEVIEW(dev)) {
499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
500 limit = &intel_limits_pineview_lvds;
501 else
502 limit = &intel_limits_pineview_sdvo;
503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
505 } else if (IS_VALLEYVIEW(dev)) {
506 limit = &intel_limits_vlv;
507 } else if (!IS_GEN2(dev)) {
508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
509 limit = &intel_limits_i9xx_lvds;
510 else
511 limit = &intel_limits_i9xx_sdvo;
512 } else {
513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
514 limit = &intel_limits_i8xx_lvds;
515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
516 limit = &intel_limits_i8xx_dvo;
517 else
518 limit = &intel_limits_i8xx_dac;
519 }
520 return limit;
521 }
522
523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
524 static void pineview_clock(int refclk, intel_clock_t *clock)
525 {
526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return;
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
532 }
533
534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
535 {
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
537 }
538
539 static void i9xx_clock(int refclk, intel_clock_t *clock)
540 {
541 clock->m = i9xx_dpll_compute_m(clock);
542 clock->p = clock->p1 * clock->p2;
543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
544 return;
545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
547 }
548
549 static void chv_clock(int refclk, intel_clock_t *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558 }
559
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561 /**
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
564 */
565
566 static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
569 {
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
578
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
582
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
588 }
589
590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
594 */
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
596 INTELPllInvalid("dot out of range\n");
597
598 return true;
599 }
600
601 static bool
602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
605 {
606 struct drm_device *dev = crtc->base.dev;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
611 /*
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
615 */
616 if (intel_is_dual_link_lvds(dev))
617 clock.p2 = limit->p2.p2_fast;
618 else
619 clock.p2 = limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
623 else
624 clock.p2 = limit->p2.p2_fast;
625 }
626
627 memset(best_clock, 0, sizeof(*best_clock));
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645 if (match_clock &&
646 clock.p != match_clock->p)
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
651 *best_clock = clock;
652 err = this_err;
653 }
654 }
655 }
656 }
657 }
658
659 return (err != target);
660 }
661
662 static bool
663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
666 {
667 struct drm_device *dev = crtc->base.dev;
668 intel_clock_t clock;
669 int err = target;
670
671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
672 /*
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
676 */
677 if (intel_is_dual_link_lvds(dev))
678 clock.p2 = limit->p2.p2_fast;
679 else
680 clock.p2 = limit->p2.p2_slow;
681 } else {
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
684 else
685 clock.p2 = limit->p2.p2_fast;
686 }
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
691 clock.m1++) {
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 pineview_clock(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 static bool
722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
725 {
726 struct drm_device *dev = crtc->base.dev;
727 intel_clock_t clock;
728 int max_n;
729 bool found;
730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
732 found = false;
733
734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
735 if (intel_is_dual_link_lvds(dev))
736 clock.p2 = limit->p2.p2_fast;
737 else
738 clock.p2 = limit->p2.p2_slow;
739 } else {
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
742 else
743 clock.p2 = limit->p2.p2_fast;
744 }
745
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_clock(refclk, &clock);
760 if (!intel_PLL_is_valid(dev, limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776 }
777
778 static bool
779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
782 {
783 struct drm_device *dev = crtc->base.dev;
784 intel_clock_t clock;
785 unsigned int bestppm = 1000000;
786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
788 bool found = false;
789
790 target *= 5; /* fast clock */
791
792 memset(best_clock, 0, sizeof(*best_clock));
793
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799 clock.p = clock.p1 * clock.p2;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
802 unsigned int ppm, diff;
803
804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
805 refclk * clock.m1);
806
807 vlv_clock(refclk, &clock);
808
809 if (!intel_PLL_is_valid(dev, limit,
810 &clock))
811 continue;
812
813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
815
816 if (ppm < 100 && clock.p > best_clock->p) {
817 bestppm = 0;
818 *best_clock = clock;
819 found = true;
820 }
821
822 if (bestppm >= 10 && ppm < bestppm - 10) {
823 bestppm = ppm;
824 *best_clock = clock;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831
832 return found;
833 }
834
835 static bool
836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 struct drm_device *dev = crtc->base.dev;
841 intel_clock_t clock;
842 uint64_t m2;
843 int found = false;
844
845 memset(best_clock, 0, sizeof(*best_clock));
846
847 /*
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
851 */
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
854
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
859
860 clock.p = clock.p1 * clock.p2;
861
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
864
865 if (m2 > INT_MAX/clock.m1)
866 continue;
867
868 clock.m2 = m2;
869
870 chv_clock(refclk, &clock);
871
872 if (!intel_PLL_is_valid(dev, limit, &clock))
873 continue;
874
875 /* based on hardware requirement, prefer bigger p
876 */
877 if (clock.p > best_clock->p) {
878 *best_clock = clock;
879 found = true;
880 }
881 }
882 }
883
884 return found;
885 }
886
887 bool intel_crtc_active(struct drm_crtc *crtc)
888 {
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
893 *
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
896 *
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
899 */
900 return intel_crtc->active && crtc->primary->fb &&
901 intel_crtc->config->base.adjusted_mode.crtc_clock;
902 }
903
904 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
905 enum pipe pipe)
906 {
907 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
909
910 return intel_crtc->config->cpu_transcoder;
911 }
912
913 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
914 {
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 u32 reg = PIPEDSL(pipe);
917 u32 line1, line2;
918 u32 line_mask;
919
920 if (IS_GEN2(dev))
921 line_mask = DSL_LINEMASK_GEN2;
922 else
923 line_mask = DSL_LINEMASK_GEN3;
924
925 line1 = I915_READ(reg) & line_mask;
926 mdelay(5);
927 line2 = I915_READ(reg) & line_mask;
928
929 return line1 == line2;
930 }
931
932 /*
933 * intel_wait_for_pipe_off - wait for pipe to turn off
934 * @crtc: crtc whose pipe to wait for
935 *
936 * After disabling a pipe, we can't wait for vblank in the usual way,
937 * spinning on the vblank interrupt status bit, since we won't actually
938 * see an interrupt when the pipe is disabled.
939 *
940 * On Gen4 and above:
941 * wait for the pipe register state bit to turn off
942 *
943 * Otherwise:
944 * wait for the display line value to settle (it usually
945 * ends up stopping at the start of the next frame).
946 *
947 */
948 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
949 {
950 struct drm_device *dev = crtc->base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
953 enum pipe pipe = crtc->pipe;
954
955 if (INTEL_INFO(dev)->gen >= 4) {
956 int reg = PIPECONF(cpu_transcoder);
957
958 /* Wait for the Pipe State to go off */
959 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
960 100))
961 WARN(1, "pipe_off wait timed out\n");
962 } else {
963 /* Wait for the display line to settle */
964 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
965 WARN(1, "pipe_off wait timed out\n");
966 }
967 }
968
969 /*
970 * ibx_digital_port_connected - is the specified port connected?
971 * @dev_priv: i915 private structure
972 * @port: the port to test
973 *
974 * Returns true if @port is connected, false otherwise.
975 */
976 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
977 struct intel_digital_port *port)
978 {
979 u32 bit;
980
981 if (HAS_PCH_IBX(dev_priv->dev)) {
982 switch (port->port) {
983 case PORT_B:
984 bit = SDE_PORTB_HOTPLUG;
985 break;
986 case PORT_C:
987 bit = SDE_PORTC_HOTPLUG;
988 break;
989 case PORT_D:
990 bit = SDE_PORTD_HOTPLUG;
991 break;
992 default:
993 return true;
994 }
995 } else {
996 switch (port->port) {
997 case PORT_B:
998 bit = SDE_PORTB_HOTPLUG_CPT;
999 break;
1000 case PORT_C:
1001 bit = SDE_PORTC_HOTPLUG_CPT;
1002 break;
1003 case PORT_D:
1004 bit = SDE_PORTD_HOTPLUG_CPT;
1005 break;
1006 default:
1007 return true;
1008 }
1009 }
1010
1011 return I915_READ(SDEISR) & bit;
1012 }
1013
1014 static const char *state_string(bool enabled)
1015 {
1016 return enabled ? "on" : "off";
1017 }
1018
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, bool state)
1022 {
1023 int reg;
1024 u32 val;
1025 bool cur_state;
1026
1027 reg = DPLL(pipe);
1028 val = I915_READ(reg);
1029 cur_state = !!(val & DPLL_VCO_ENABLE);
1030 I915_STATE_WARN(cur_state != state,
1031 "PLL state assertion failure (expected %s, current %s)\n",
1032 state_string(state), state_string(cur_state));
1033 }
1034
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1037 {
1038 u32 val;
1039 bool cur_state;
1040
1041 mutex_lock(&dev_priv->dpio_lock);
1042 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043 mutex_unlock(&dev_priv->dpio_lock);
1044
1045 cur_state = val & DSI_PLL_VCO_EN;
1046 I915_STATE_WARN(cur_state != state,
1047 "DSI PLL state assertion failure (expected %s, current %s)\n",
1048 state_string(state), state_string(cur_state));
1049 }
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052
1053 struct intel_shared_dpll *
1054 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1055 {
1056 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1057
1058 if (crtc->config->shared_dpll < 0)
1059 return NULL;
1060
1061 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1062 }
1063
1064 /* For ILK+ */
1065 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066 struct intel_shared_dpll *pll,
1067 bool state)
1068 {
1069 bool cur_state;
1070 struct intel_dpll_hw_state hw_state;
1071
1072 if (WARN (!pll,
1073 "asserting DPLL %s with no DPLL\n", state_string(state)))
1074 return;
1075
1076 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077 I915_STATE_WARN(cur_state != state,
1078 "%s assertion failure (expected %s, current %s)\n",
1079 pll->name, state_string(state), state_string(cur_state));
1080 }
1081
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083 enum pipe pipe, bool state)
1084 {
1085 int reg;
1086 u32 val;
1087 bool cur_state;
1088 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1089 pipe);
1090
1091 if (HAS_DDI(dev_priv->dev)) {
1092 /* DDI does not have a specific FDI_TX register */
1093 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094 val = I915_READ(reg);
1095 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1096 } else {
1097 reg = FDI_TX_CTL(pipe);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & FDI_TX_ENABLE);
1100 }
1101 I915_STATE_WARN(cur_state != state,
1102 "FDI TX state assertion failure (expected %s, current %s)\n",
1103 state_string(state), state_string(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109 enum pipe pipe, bool state)
1110 {
1111 int reg;
1112 u32 val;
1113 bool cur_state;
1114
1115 reg = FDI_RX_CTL(pipe);
1116 val = I915_READ(reg);
1117 cur_state = !!(val & FDI_RX_ENABLE);
1118 I915_STATE_WARN(cur_state != state,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 state_string(state), state_string(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127 {
1128 int reg;
1129 u32 val;
1130
1131 /* ILK FDI PLL is always enabled */
1132 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1133 return;
1134
1135 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136 if (HAS_DDI(dev_priv->dev))
1137 return;
1138
1139 reg = FDI_TX_CTL(pipe);
1140 val = I915_READ(reg);
1141 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1142 }
1143
1144 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154 I915_STATE_WARN(cur_state != state,
1155 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158
1159 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
1161 {
1162 struct drm_device *dev = dev_priv->dev;
1163 int pp_reg;
1164 u32 val;
1165 enum pipe panel_pipe = PIPE_A;
1166 bool locked = true;
1167
1168 if (WARN_ON(HAS_DDI(dev)))
1169 return;
1170
1171 if (HAS_PCH_SPLIT(dev)) {
1172 u32 port_sel;
1173
1174 pp_reg = PCH_PP_CONTROL;
1175 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1176
1177 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179 panel_pipe = PIPE_B;
1180 /* XXX: else fix for eDP */
1181 } else if (IS_VALLEYVIEW(dev)) {
1182 /* presumably write lock depends on pipe, not port select */
1183 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1184 panel_pipe = pipe;
1185 } else {
1186 pp_reg = PP_CONTROL;
1187 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188 panel_pipe = PIPE_B;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 I915_STATE_WARN(panel_pipe == pipe && locked,
1197 "panel assertion failure, pipe %c regs locked\n",
1198 pipe_name(pipe));
1199 }
1200
1201 static void assert_cursor(struct drm_i915_private *dev_priv,
1202 enum pipe pipe, bool state)
1203 {
1204 struct drm_device *dev = dev_priv->dev;
1205 bool cur_state;
1206
1207 if (IS_845G(dev) || IS_I865G(dev))
1208 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1209 else
1210 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1211
1212 I915_STATE_WARN(cur_state != state,
1213 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214 pipe_name(pipe), state_string(state), state_string(cur_state));
1215 }
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1221 {
1222 int reg;
1223 u32 val;
1224 bool cur_state;
1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 pipe);
1227
1228 /* if we need the pipe quirk it must be always on */
1229 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1231 state = true;
1232
1233 if (!intel_display_power_is_enabled(dev_priv,
1234 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1235 cur_state = false;
1236 } else {
1237 reg = PIPECONF(cpu_transcoder);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & PIPECONF_ENABLE);
1240 }
1241
1242 I915_STATE_WARN(cur_state != state,
1243 "pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248 enum plane plane, bool state)
1249 {
1250 int reg;
1251 u32 val;
1252 bool cur_state;
1253
1254 reg = DSPCNTR(plane);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257 I915_STATE_WARN(cur_state != state,
1258 "plane %c assertion failure (expected %s, current %s)\n",
1259 plane_name(plane), state_string(state), state_string(cur_state));
1260 }
1261
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267 {
1268 struct drm_device *dev = dev_priv->dev;
1269 int reg, i;
1270 u32 val;
1271 int cur_pipe;
1272
1273 /* Primary planes are fixed to pipes on gen4+ */
1274 if (INTEL_INFO(dev)->gen >= 4) {
1275 reg = DSPCNTR(pipe);
1276 val = I915_READ(reg);
1277 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278 "plane %c assertion failure, should be disabled but not\n",
1279 plane_name(pipe));
1280 return;
1281 }
1282
1283 /* Need to check both planes against the pipe */
1284 for_each_pipe(dev_priv, i) {
1285 reg = DSPCNTR(i);
1286 val = I915_READ(reg);
1287 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288 DISPPLANE_SEL_PIPE_SHIFT;
1289 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291 plane_name(i), pipe_name(pipe));
1292 }
1293 }
1294
1295 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe)
1297 {
1298 struct drm_device *dev = dev_priv->dev;
1299 int reg, sprite;
1300 u32 val;
1301
1302 if (INTEL_INFO(dev)->gen >= 9) {
1303 for_each_sprite(pipe, sprite) {
1304 val = I915_READ(PLANE_CTL(pipe, sprite));
1305 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307 sprite, pipe_name(pipe));
1308 }
1309 } else if (IS_VALLEYVIEW(dev)) {
1310 for_each_sprite(pipe, sprite) {
1311 reg = SPCNTR(pipe, sprite);
1312 val = I915_READ(reg);
1313 I915_STATE_WARN(val & SP_ENABLE,
1314 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315 sprite_name(pipe, sprite), pipe_name(pipe));
1316 }
1317 } else if (INTEL_INFO(dev)->gen >= 7) {
1318 reg = SPRCTL(pipe);
1319 val = I915_READ(reg);
1320 I915_STATE_WARN(val & SPRITE_ENABLE,
1321 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322 plane_name(pipe), pipe_name(pipe));
1323 } else if (INTEL_INFO(dev)->gen >= 5) {
1324 reg = DVSCNTR(pipe);
1325 val = I915_READ(reg);
1326 I915_STATE_WARN(val & DVS_ENABLE,
1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328 plane_name(pipe), pipe_name(pipe));
1329 }
1330 }
1331
1332 static void assert_vblank_disabled(struct drm_crtc *crtc)
1333 {
1334 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335 drm_crtc_vblank_put(crtc);
1336 }
1337
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1339 {
1340 u32 val;
1341 bool enabled;
1342
1343 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1344
1345 val = I915_READ(PCH_DREF_CONTROL);
1346 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347 DREF_SUPERSPREAD_SOURCE_MASK));
1348 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1349 }
1350
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe)
1353 {
1354 int reg;
1355 u32 val;
1356 bool enabled;
1357
1358 reg = PCH_TRANSCONF(pipe);
1359 val = I915_READ(reg);
1360 enabled = !!(val & TRANS_ENABLE);
1361 I915_STATE_WARN(enabled,
1362 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363 pipe_name(pipe));
1364 }
1365
1366 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367 enum pipe pipe, u32 port_sel, u32 val)
1368 {
1369 if ((val & DP_PORT_EN) == 0)
1370 return false;
1371
1372 if (HAS_PCH_CPT(dev_priv->dev)) {
1373 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376 return false;
1377 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379 return false;
1380 } else {
1381 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382 return false;
1383 }
1384 return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, u32 val)
1389 {
1390 if ((val & SDVO_ENABLE) == 0)
1391 return false;
1392
1393 if (HAS_PCH_CPT(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395 return false;
1396 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398 return false;
1399 } else {
1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401 return false;
1402 }
1403 return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, u32 val)
1408 {
1409 if ((val & LVDS_PORT_EN) == 0)
1410 return false;
1411
1412 if (HAS_PCH_CPT(dev_priv->dev)) {
1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414 return false;
1415 } else {
1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417 return false;
1418 }
1419 return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe, u32 val)
1424 {
1425 if ((val & ADPA_DAC_ENABLE) == 0)
1426 return false;
1427 if (HAS_PCH_CPT(dev_priv->dev)) {
1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429 return false;
1430 } else {
1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432 return false;
1433 }
1434 return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, int reg, u32 port_sel)
1439 {
1440 u32 val = I915_READ(reg);
1441 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443 reg, pipe_name(pipe));
1444
1445 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446 && (val & DP_PIPEB_SELECT),
1447 "IBX PCH dp port still using transcoder B\n");
1448 }
1449
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, int reg)
1452 {
1453 u32 val = I915_READ(reg);
1454 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456 reg, pipe_name(pipe));
1457
1458 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459 && (val & SDVO_PIPE_B_SELECT),
1460 "IBX PCH hdmi port still using transcoder B\n");
1461 }
1462
1463 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465 {
1466 int reg;
1467 u32 val;
1468
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473 reg = PCH_ADPA;
1474 val = I915_READ(reg);
1475 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476 "PCH VGA enabled on transcoder %c, should be disabled\n",
1477 pipe_name(pipe));
1478
1479 reg = PCH_LVDS;
1480 val = I915_READ(reg);
1481 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1483 pipe_name(pipe));
1484
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1488 }
1489
1490 static void intel_init_dpio(struct drm_device *dev)
1491 {
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493
1494 if (!IS_VALLEYVIEW(dev))
1495 return;
1496
1497 /*
1498 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499 * CHV x1 PHY (DP/HDMI D)
1500 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501 */
1502 if (IS_CHERRYVIEW(dev)) {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1505 } else {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507 }
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511 const struct intel_crtc_state *pipe_config)
1512 {
1513 struct drm_device *dev = crtc->base.dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 int reg = DPLL(crtc->pipe);
1516 u32 dpll = pipe_config->dpll_hw_state.dpll;
1517
1518 assert_pipe_disabled(dev_priv, crtc->pipe);
1519
1520 /* No really, not for ILK+ */
1521 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1522
1523 /* PLL is protected by panel, make sure we can write it */
1524 if (IS_MOBILE(dev_priv->dev))
1525 assert_panel_unlocked(dev_priv, crtc->pipe);
1526
1527 I915_WRITE(reg, dpll);
1528 POSTING_READ(reg);
1529 udelay(150);
1530
1531 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1533
1534 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535 POSTING_READ(DPLL_MD(crtc->pipe));
1536
1537 /* We do this three times for luck */
1538 I915_WRITE(reg, dpll);
1539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544 I915_WRITE(reg, dpll);
1545 POSTING_READ(reg);
1546 udelay(150); /* wait for warmup */
1547 }
1548
1549 static void chv_enable_pll(struct intel_crtc *crtc,
1550 const struct intel_crtc_state *pipe_config)
1551 {
1552 struct drm_device *dev = crtc->base.dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 int pipe = crtc->pipe;
1555 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1556 u32 tmp;
1557
1558 assert_pipe_disabled(dev_priv, crtc->pipe);
1559
1560 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1561
1562 mutex_lock(&dev_priv->dpio_lock);
1563
1564 /* Enable back the 10bit clock to display controller */
1565 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566 tmp |= DPIO_DCLKP_EN;
1567 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1568
1569 /*
1570 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1571 */
1572 udelay(1);
1573
1574 /* Enable PLL */
1575 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1576
1577 /* Check PLL is locked */
1578 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579 DRM_ERROR("PLL %d failed to lock\n", pipe);
1580
1581 /* not sure when this should be written */
1582 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583 POSTING_READ(DPLL_MD(pipe));
1584
1585 mutex_unlock(&dev_priv->dpio_lock);
1586 }
1587
1588 static int intel_num_dvo_pipes(struct drm_device *dev)
1589 {
1590 struct intel_crtc *crtc;
1591 int count = 0;
1592
1593 for_each_intel_crtc(dev, crtc)
1594 count += crtc->active &&
1595 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1596
1597 return count;
1598 }
1599
1600 static void i9xx_enable_pll(struct intel_crtc *crtc)
1601 {
1602 struct drm_device *dev = crtc->base.dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 int reg = DPLL(crtc->pipe);
1605 u32 dpll = crtc->config->dpll_hw_state.dpll;
1606
1607 assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609 /* No really, not for ILK+ */
1610 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1611
1612 /* PLL is protected by panel, make sure we can write it */
1613 if (IS_MOBILE(dev) && !IS_I830(dev))
1614 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616 /* Enable DVO 2x clock on both PLLs if necessary */
1617 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1618 /*
1619 * It appears to be important that we don't enable this
1620 * for the current pipe before otherwise configuring the
1621 * PLL. No idea how this should be handled if multiple
1622 * DVO outputs are enabled simultaneosly.
1623 */
1624 dpll |= DPLL_DVO_2X_MODE;
1625 I915_WRITE(DPLL(!crtc->pipe),
1626 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1627 }
1628
1629 /* Wait for the clocks to stabilize. */
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (INTEL_INFO(dev)->gen >= 4) {
1634 I915_WRITE(DPLL_MD(crtc->pipe),
1635 crtc->config->dpll_hw_state.dpll_md);
1636 } else {
1637 /* The pixel multiplier can only be updated once the
1638 * DPLL is enabled and the clocks are stable.
1639 *
1640 * So write it again.
1641 */
1642 I915_WRITE(reg, dpll);
1643 }
1644
1645 /* We do this three times for luck */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 I915_WRITE(reg, dpll);
1653 POSTING_READ(reg);
1654 udelay(150); /* wait for warmup */
1655 }
1656
1657 /**
1658 * i9xx_disable_pll - disable a PLL
1659 * @dev_priv: i915 private structure
1660 * @pipe: pipe PLL to disable
1661 *
1662 * Disable the PLL for @pipe, making sure the pipe is off first.
1663 *
1664 * Note! This is for pre-ILK only.
1665 */
1666 static void i9xx_disable_pll(struct intel_crtc *crtc)
1667 {
1668 struct drm_device *dev = crtc->base.dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 enum pipe pipe = crtc->pipe;
1671
1672 /* Disable DVO 2x clock on both PLLs if necessary */
1673 if (IS_I830(dev) &&
1674 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675 intel_num_dvo_pipes(dev) == 1) {
1676 I915_WRITE(DPLL(PIPE_B),
1677 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678 I915_WRITE(DPLL(PIPE_A),
1679 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1680 }
1681
1682 /* Don't disable pipe or pipe PLLs if needed */
1683 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1685 return;
1686
1687 /* Make sure the pipe isn't still relying on us */
1688 assert_pipe_disabled(dev_priv, pipe);
1689
1690 I915_WRITE(DPLL(pipe), 0);
1691 POSTING_READ(DPLL(pipe));
1692 }
1693
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696 u32 val = 0;
1697
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1700
1701 /*
1702 * Leave integrated clock source and reference clock enabled for pipe B.
1703 * The latter is needed for VGA hotplug / manual detection.
1704 */
1705 if (pipe == PIPE_B)
1706 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707 I915_WRITE(DPLL(pipe), val);
1708 POSTING_READ(DPLL(pipe));
1709
1710 }
1711
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1715 u32 val;
1716
1717 /* Make sure the pipe isn't still relying on us */
1718 assert_pipe_disabled(dev_priv, pipe);
1719
1720 /* Set PLL en = 0 */
1721 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1722 if (pipe != PIPE_A)
1723 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1726
1727 mutex_lock(&dev_priv->dpio_lock);
1728
1729 /* Disable 10bit clock to display controller */
1730 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731 val &= ~DPIO_DCLKP_EN;
1732 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
1734 /* disable left/right clock distribution */
1735 if (pipe != PIPE_B) {
1736 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739 } else {
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743 }
1744
1745 mutex_unlock(&dev_priv->dpio_lock);
1746 }
1747
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749 struct intel_digital_port *dport)
1750 {
1751 u32 port_mask;
1752 int dpll_reg;
1753
1754 switch (dport->port) {
1755 case PORT_B:
1756 port_mask = DPLL_PORTB_READY_MASK;
1757 dpll_reg = DPLL(0);
1758 break;
1759 case PORT_C:
1760 port_mask = DPLL_PORTC_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 break;
1763 case PORT_D:
1764 port_mask = DPLL_PORTD_READY_MASK;
1765 dpll_reg = DPIO_PHY_STATUS;
1766 break;
1767 default:
1768 BUG();
1769 }
1770
1771 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773 port_name(dport->port), I915_READ(dpll_reg));
1774 }
1775
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777 {
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782 if (WARN_ON(pll == NULL))
1783 return;
1784
1785 WARN_ON(!pll->config.crtc_mask);
1786 if (pll->active == 0) {
1787 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788 WARN_ON(pll->on);
1789 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791 pll->mode_set(dev_priv, pll);
1792 }
1793 }
1794
1795 /**
1796 * intel_enable_shared_dpll - enable PCH PLL
1797 * @dev_priv: i915 private structure
1798 * @pipe: pipe PLL to enable
1799 *
1800 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801 * drives the transcoder clock.
1802 */
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1804 {
1805 struct drm_device *dev = crtc->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809 if (WARN_ON(pll == NULL))
1810 return;
1811
1812 if (WARN_ON(pll->config.crtc_mask == 0))
1813 return;
1814
1815 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816 pll->name, pll->active, pll->on,
1817 crtc->base.base.id);
1818
1819 if (pll->active++) {
1820 WARN_ON(!pll->on);
1821 assert_shared_dpll_enabled(dev_priv, pll);
1822 return;
1823 }
1824 WARN_ON(pll->on);
1825
1826 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
1828 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829 pll->enable(dev_priv, pll);
1830 pll->on = true;
1831 }
1832
1833 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1834 {
1835 struct drm_device *dev = crtc->base.dev;
1836 struct drm_i915_private *dev_priv = dev->dev_private;
1837 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839 /* PCH only available on ILK+ */
1840 BUG_ON(INTEL_INFO(dev)->gen < 5);
1841 if (WARN_ON(pll == NULL))
1842 return;
1843
1844 if (WARN_ON(pll->config.crtc_mask == 0))
1845 return;
1846
1847 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848 pll->name, pll->active, pll->on,
1849 crtc->base.base.id);
1850
1851 if (WARN_ON(pll->active == 0)) {
1852 assert_shared_dpll_disabled(dev_priv, pll);
1853 return;
1854 }
1855
1856 assert_shared_dpll_enabled(dev_priv, pll);
1857 WARN_ON(!pll->on);
1858 if (--pll->active)
1859 return;
1860
1861 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862 pll->disable(dev_priv, pll);
1863 pll->on = false;
1864
1865 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1866 }
1867
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869 enum pipe pipe)
1870 {
1871 struct drm_device *dev = dev_priv->dev;
1872 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874 uint32_t reg, val, pipeconf_val;
1875
1876 /* PCH only available on ILK+ */
1877 BUG_ON(!HAS_PCH_SPLIT(dev));
1878
1879 /* Make sure PCH DPLL is enabled */
1880 assert_shared_dpll_enabled(dev_priv,
1881 intel_crtc_to_shared_dpll(intel_crtc));
1882
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, pipe);
1885 assert_fdi_rx_enabled(dev_priv, pipe);
1886
1887 if (HAS_PCH_CPT(dev)) {
1888 /* Workaround: Set the timing override bit before enabling the
1889 * pch transcoder. */
1890 reg = TRANS_CHICKEN2(pipe);
1891 val = I915_READ(reg);
1892 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893 I915_WRITE(reg, val);
1894 }
1895
1896 reg = PCH_TRANSCONF(pipe);
1897 val = I915_READ(reg);
1898 pipeconf_val = I915_READ(PIPECONF(pipe));
1899
1900 if (HAS_PCH_IBX(dev_priv->dev)) {
1901 /*
1902 * make the BPC in transcoder be consistent with
1903 * that in pipeconf reg.
1904 */
1905 val &= ~PIPECONF_BPC_MASK;
1906 val |= pipeconf_val & PIPECONF_BPC_MASK;
1907 }
1908
1909 val &= ~TRANS_INTERLACE_MASK;
1910 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911 if (HAS_PCH_IBX(dev_priv->dev) &&
1912 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913 val |= TRANS_LEGACY_INTERLACED_ILK;
1914 else
1915 val |= TRANS_INTERLACED;
1916 else
1917 val |= TRANS_PROGRESSIVE;
1918
1919 I915_WRITE(reg, val | TRANS_ENABLE);
1920 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1922 }
1923
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925 enum transcoder cpu_transcoder)
1926 {
1927 u32 val, pipeconf_val;
1928
1929 /* PCH only available on ILK+ */
1930 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1931
1932 /* FDI must be feeding us bits for PCH ports */
1933 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1935
1936 /* Workaround: set timing override bit. */
1937 val = I915_READ(_TRANSA_CHICKEN2);
1938 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939 I915_WRITE(_TRANSA_CHICKEN2, val);
1940
1941 val = TRANS_ENABLE;
1942 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1943
1944 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945 PIPECONF_INTERLACED_ILK)
1946 val |= TRANS_INTERLACED;
1947 else
1948 val |= TRANS_PROGRESSIVE;
1949
1950 I915_WRITE(LPT_TRANSCONF, val);
1951 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952 DRM_ERROR("Failed to enable PCH transcoder\n");
1953 }
1954
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956 enum pipe pipe)
1957 {
1958 struct drm_device *dev = dev_priv->dev;
1959 uint32_t reg, val;
1960
1961 /* FDI relies on the transcoder */
1962 assert_fdi_tx_disabled(dev_priv, pipe);
1963 assert_fdi_rx_disabled(dev_priv, pipe);
1964
1965 /* Ports must be off as well */
1966 assert_pch_ports_disabled(dev_priv, pipe);
1967
1968 reg = PCH_TRANSCONF(pipe);
1969 val = I915_READ(reg);
1970 val &= ~TRANS_ENABLE;
1971 I915_WRITE(reg, val);
1972 /* wait for PCH transcoder off, transcoder state */
1973 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1975
1976 if (!HAS_PCH_IBX(dev)) {
1977 /* Workaround: Clear the timing override chicken bit again. */
1978 reg = TRANS_CHICKEN2(pipe);
1979 val = I915_READ(reg);
1980 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981 I915_WRITE(reg, val);
1982 }
1983 }
1984
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 {
1987 u32 val;
1988
1989 val = I915_READ(LPT_TRANSCONF);
1990 val &= ~TRANS_ENABLE;
1991 I915_WRITE(LPT_TRANSCONF, val);
1992 /* wait for PCH transcoder off, transcoder state */
1993 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994 DRM_ERROR("Failed to disable PCH transcoder\n");
1995
1996 /* Workaround: clear timing override bit. */
1997 val = I915_READ(_TRANSA_CHICKEN2);
1998 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999 I915_WRITE(_TRANSA_CHICKEN2, val);
2000 }
2001
2002 /**
2003 * intel_enable_pipe - enable a pipe, asserting requirements
2004 * @crtc: crtc responsible for the pipe
2005 *
2006 * Enable @crtc's pipe, making sure that various hardware specific requirements
2007 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008 */
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2010 {
2011 struct drm_device *dev = crtc->base.dev;
2012 struct drm_i915_private *dev_priv = dev->dev_private;
2013 enum pipe pipe = crtc->pipe;
2014 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015 pipe);
2016 enum pipe pch_transcoder;
2017 int reg;
2018 u32 val;
2019
2020 assert_planes_disabled(dev_priv, pipe);
2021 assert_cursor_disabled(dev_priv, pipe);
2022 assert_sprites_disabled(dev_priv, pipe);
2023
2024 if (HAS_PCH_LPT(dev_priv->dev))
2025 pch_transcoder = TRANSCODER_A;
2026 else
2027 pch_transcoder = pipe;
2028
2029 /*
2030 * A pipe without a PLL won't actually be able to drive bits from
2031 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2032 * need the check.
2033 */
2034 if (!HAS_PCH_SPLIT(dev_priv->dev))
2035 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036 assert_dsi_pll_enabled(dev_priv);
2037 else
2038 assert_pll_enabled(dev_priv, pipe);
2039 else {
2040 if (crtc->config->has_pch_encoder) {
2041 /* if driving the PCH, we need FDI enabled */
2042 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043 assert_fdi_tx_pll_enabled(dev_priv,
2044 (enum pipe) cpu_transcoder);
2045 }
2046 /* FIXME: assert CPU port conditions for SNB+ */
2047 }
2048
2049 reg = PIPECONF(cpu_transcoder);
2050 val = I915_READ(reg);
2051 if (val & PIPECONF_ENABLE) {
2052 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054 return;
2055 }
2056
2057 I915_WRITE(reg, val | PIPECONF_ENABLE);
2058 POSTING_READ(reg);
2059 }
2060
2061 /**
2062 * intel_disable_pipe - disable a pipe, asserting requirements
2063 * @crtc: crtc whose pipes is to be disabled
2064 *
2065 * Disable the pipe of @crtc, making sure that various hardware
2066 * specific requirements are met, if applicable, e.g. plane
2067 * disabled, panel fitter off, etc.
2068 *
2069 * Will wait until the pipe has shut down before returning.
2070 */
2071 static void intel_disable_pipe(struct intel_crtc *crtc)
2072 {
2073 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075 enum pipe pipe = crtc->pipe;
2076 int reg;
2077 u32 val;
2078
2079 /*
2080 * Make sure planes won't keep trying to pump pixels to us,
2081 * or we might hang the display.
2082 */
2083 assert_planes_disabled(dev_priv, pipe);
2084 assert_cursor_disabled(dev_priv, pipe);
2085 assert_sprites_disabled(dev_priv, pipe);
2086
2087 reg = PIPECONF(cpu_transcoder);
2088 val = I915_READ(reg);
2089 if ((val & PIPECONF_ENABLE) == 0)
2090 return;
2091
2092 /*
2093 * Double wide has implications for planes
2094 * so best keep it disabled when not needed.
2095 */
2096 if (crtc->config->double_wide)
2097 val &= ~PIPECONF_DOUBLE_WIDE;
2098
2099 /* Don't disable pipe or pipe PLLs if needed */
2100 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102 val &= ~PIPECONF_ENABLE;
2103
2104 I915_WRITE(reg, val);
2105 if ((val & PIPECONF_ENABLE) == 0)
2106 intel_wait_for_pipe_off(crtc);
2107 }
2108
2109 /*
2110 * Plane regs are double buffered, going from enabled->disabled needs a
2111 * trigger in order to latch. The display address reg provides this.
2112 */
2113 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2114 enum plane plane)
2115 {
2116 struct drm_device *dev = dev_priv->dev;
2117 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2118
2119 I915_WRITE(reg, I915_READ(reg));
2120 POSTING_READ(reg);
2121 }
2122
2123 /**
2124 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125 * @plane: plane to be enabled
2126 * @crtc: crtc for the plane
2127 *
2128 * Enable @plane on @crtc, making sure that the pipe is running first.
2129 */
2130 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131 struct drm_crtc *crtc)
2132 {
2133 struct drm_device *dev = plane->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2139
2140 if (intel_crtc->primary_enabled)
2141 return;
2142
2143 intel_crtc->primary_enabled = true;
2144
2145 dev_priv->display.update_primary_plane(crtc, plane->fb,
2146 crtc->x, crtc->y);
2147
2148 /*
2149 * BDW signals flip done immediately if the plane
2150 * is disabled, even if the plane enable is already
2151 * armed to occur at the next vblank :(
2152 */
2153 if (IS_BROADWELL(dev))
2154 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 }
2156
2157 /**
2158 * intel_disable_primary_hw_plane - disable the primary hardware plane
2159 * @plane: plane to be disabled
2160 * @crtc: crtc for the plane
2161 *
2162 * Disable @plane on @crtc, making sure that the pipe is running first.
2163 */
2164 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165 struct drm_crtc *crtc)
2166 {
2167 struct drm_device *dev = plane->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170
2171 if (WARN_ON(!intel_crtc->active))
2172 return;
2173
2174 if (!intel_crtc->primary_enabled)
2175 return;
2176
2177 intel_crtc->primary_enabled = false;
2178
2179 dev_priv->display.update_primary_plane(crtc, plane->fb,
2180 crtc->x, crtc->y);
2181 }
2182
2183 static bool need_vtd_wa(struct drm_device *dev)
2184 {
2185 #ifdef CONFIG_INTEL_IOMMU
2186 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2187 return true;
2188 #endif
2189 return false;
2190 }
2191
2192 int
2193 intel_fb_align_height(struct drm_device *dev, int height,
2194 uint32_t pixel_format,
2195 uint64_t fb_format_modifier)
2196 {
2197 int tile_height;
2198
2199 tile_height = fb_format_modifier == I915_FORMAT_MOD_X_TILED ?
2200 (IS_GEN2(dev) ? 16 : 8) : 1;
2201
2202 return ALIGN(height, tile_height);
2203 }
2204
2205 int
2206 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2207 struct drm_framebuffer *fb,
2208 struct intel_engine_cs *pipelined)
2209 {
2210 struct drm_device *dev = fb->dev;
2211 struct drm_i915_private *dev_priv = dev->dev_private;
2212 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2213 u32 alignment;
2214 int ret;
2215
2216 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2217
2218 switch (obj->tiling_mode) {
2219 case I915_TILING_NONE:
2220 if (INTEL_INFO(dev)->gen >= 9)
2221 alignment = 256 * 1024;
2222 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2223 alignment = 128 * 1024;
2224 else if (INTEL_INFO(dev)->gen >= 4)
2225 alignment = 4 * 1024;
2226 else
2227 alignment = 64 * 1024;
2228 break;
2229 case I915_TILING_X:
2230 if (INTEL_INFO(dev)->gen >= 9)
2231 alignment = 256 * 1024;
2232 else {
2233 /* pin() will align the object as required by fence */
2234 alignment = 0;
2235 }
2236 break;
2237 case I915_TILING_Y:
2238 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2239 return -EINVAL;
2240 default:
2241 BUG();
2242 }
2243
2244 /* Note that the w/a also requires 64 PTE of padding following the
2245 * bo. We currently fill all unused PTE with the shadow page and so
2246 * we should always have valid PTE following the scanout preventing
2247 * the VT-d warning.
2248 */
2249 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2250 alignment = 256 * 1024;
2251
2252 /*
2253 * Global gtt pte registers are special registers which actually forward
2254 * writes to a chunk of system memory. Which means that there is no risk
2255 * that the register values disappear as soon as we call
2256 * intel_runtime_pm_put(), so it is correct to wrap only the
2257 * pin/unpin/fence and not more.
2258 */
2259 intel_runtime_pm_get(dev_priv);
2260
2261 dev_priv->mm.interruptible = false;
2262 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2263 if (ret)
2264 goto err_interruptible;
2265
2266 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2267 * fence, whereas 965+ only requires a fence if using
2268 * framebuffer compression. For simplicity, we always install
2269 * a fence as the cost is not that onerous.
2270 */
2271 ret = i915_gem_object_get_fence(obj);
2272 if (ret)
2273 goto err_unpin;
2274
2275 i915_gem_object_pin_fence(obj);
2276
2277 dev_priv->mm.interruptible = true;
2278 intel_runtime_pm_put(dev_priv);
2279 return 0;
2280
2281 err_unpin:
2282 i915_gem_object_unpin_from_display_plane(obj);
2283 err_interruptible:
2284 dev_priv->mm.interruptible = true;
2285 intel_runtime_pm_put(dev_priv);
2286 return ret;
2287 }
2288
2289 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2290 {
2291 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2292
2293 i915_gem_object_unpin_fence(obj);
2294 i915_gem_object_unpin_from_display_plane(obj);
2295 }
2296
2297 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2298 * is assumed to be a power-of-two. */
2299 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2300 unsigned int tiling_mode,
2301 unsigned int cpp,
2302 unsigned int pitch)
2303 {
2304 if (tiling_mode != I915_TILING_NONE) {
2305 unsigned int tile_rows, tiles;
2306
2307 tile_rows = *y / 8;
2308 *y %= 8;
2309
2310 tiles = *x / (512/cpp);
2311 *x %= 512/cpp;
2312
2313 return tile_rows * pitch * 8 + tiles * 4096;
2314 } else {
2315 unsigned int offset;
2316
2317 offset = *y * pitch + *x * cpp;
2318 *y = 0;
2319 *x = (offset & 4095) / cpp;
2320 return offset & -4096;
2321 }
2322 }
2323
2324 static int i9xx_format_to_fourcc(int format)
2325 {
2326 switch (format) {
2327 case DISPPLANE_8BPP:
2328 return DRM_FORMAT_C8;
2329 case DISPPLANE_BGRX555:
2330 return DRM_FORMAT_XRGB1555;
2331 case DISPPLANE_BGRX565:
2332 return DRM_FORMAT_RGB565;
2333 default:
2334 case DISPPLANE_BGRX888:
2335 return DRM_FORMAT_XRGB8888;
2336 case DISPPLANE_RGBX888:
2337 return DRM_FORMAT_XBGR8888;
2338 case DISPPLANE_BGRX101010:
2339 return DRM_FORMAT_XRGB2101010;
2340 case DISPPLANE_RGBX101010:
2341 return DRM_FORMAT_XBGR2101010;
2342 }
2343 }
2344
2345 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2346 {
2347 switch (format) {
2348 case PLANE_CTL_FORMAT_RGB_565:
2349 return DRM_FORMAT_RGB565;
2350 default:
2351 case PLANE_CTL_FORMAT_XRGB_8888:
2352 if (rgb_order) {
2353 if (alpha)
2354 return DRM_FORMAT_ABGR8888;
2355 else
2356 return DRM_FORMAT_XBGR8888;
2357 } else {
2358 if (alpha)
2359 return DRM_FORMAT_ARGB8888;
2360 else
2361 return DRM_FORMAT_XRGB8888;
2362 }
2363 case PLANE_CTL_FORMAT_XRGB_2101010:
2364 if (rgb_order)
2365 return DRM_FORMAT_XBGR2101010;
2366 else
2367 return DRM_FORMAT_XRGB2101010;
2368 }
2369 }
2370
2371 static bool
2372 intel_alloc_plane_obj(struct intel_crtc *crtc,
2373 struct intel_initial_plane_config *plane_config)
2374 {
2375 struct drm_device *dev = crtc->base.dev;
2376 struct drm_i915_gem_object *obj = NULL;
2377 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2378 struct drm_framebuffer *fb = &plane_config->fb->base;
2379 u32 base = plane_config->base;
2380
2381 if (plane_config->size == 0)
2382 return false;
2383
2384 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2385 plane_config->size);
2386 if (!obj)
2387 return false;
2388
2389 obj->tiling_mode = plane_config->tiling;
2390 if (obj->tiling_mode == I915_TILING_X)
2391 obj->stride = fb->pitches[0];
2392
2393 mode_cmd.pixel_format = fb->pixel_format;
2394 mode_cmd.width = fb->width;
2395 mode_cmd.height = fb->height;
2396 mode_cmd.pitches[0] = fb->pitches[0];
2397 mode_cmd.modifier[0] = fb->modifier[0];
2398 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2399
2400 mutex_lock(&dev->struct_mutex);
2401
2402 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2403 &mode_cmd, obj)) {
2404 DRM_DEBUG_KMS("intel fb init failed\n");
2405 goto out_unref_obj;
2406 }
2407
2408 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2409 mutex_unlock(&dev->struct_mutex);
2410
2411 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2412 return true;
2413
2414 out_unref_obj:
2415 drm_gem_object_unreference(&obj->base);
2416 mutex_unlock(&dev->struct_mutex);
2417 return false;
2418 }
2419
2420 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2421 static void
2422 update_state_fb(struct drm_plane *plane)
2423 {
2424 if (plane->fb == plane->state->fb)
2425 return;
2426
2427 if (plane->state->fb)
2428 drm_framebuffer_unreference(plane->state->fb);
2429 plane->state->fb = plane->fb;
2430 if (plane->state->fb)
2431 drm_framebuffer_reference(plane->state->fb);
2432 }
2433
2434 static void
2435 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2436 struct intel_initial_plane_config *plane_config)
2437 {
2438 struct drm_device *dev = intel_crtc->base.dev;
2439 struct drm_i915_private *dev_priv = dev->dev_private;
2440 struct drm_crtc *c;
2441 struct intel_crtc *i;
2442 struct drm_i915_gem_object *obj;
2443
2444 if (!plane_config->fb)
2445 return;
2446
2447 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2448 struct drm_plane *primary = intel_crtc->base.primary;
2449
2450 primary->fb = &plane_config->fb->base;
2451 primary->state->crtc = &intel_crtc->base;
2452 update_state_fb(primary);
2453
2454 return;
2455 }
2456
2457 kfree(plane_config->fb);
2458
2459 /*
2460 * Failed to alloc the obj, check to see if we should share
2461 * an fb with another CRTC instead
2462 */
2463 for_each_crtc(dev, c) {
2464 i = to_intel_crtc(c);
2465
2466 if (c == &intel_crtc->base)
2467 continue;
2468
2469 if (!i->active)
2470 continue;
2471
2472 obj = intel_fb_obj(c->primary->fb);
2473 if (obj == NULL)
2474 continue;
2475
2476 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2477 struct drm_plane *primary = intel_crtc->base.primary;
2478
2479 if (obj->tiling_mode != I915_TILING_NONE)
2480 dev_priv->preserve_bios_swizzle = true;
2481
2482 drm_framebuffer_reference(c->primary->fb);
2483 primary->fb = c->primary->fb;
2484 primary->state->crtc = &intel_crtc->base;
2485 update_state_fb(intel_crtc->base.primary);
2486 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2487 break;
2488 }
2489 }
2490
2491 }
2492
2493 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2494 struct drm_framebuffer *fb,
2495 int x, int y)
2496 {
2497 struct drm_device *dev = crtc->dev;
2498 struct drm_i915_private *dev_priv = dev->dev_private;
2499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2500 struct drm_i915_gem_object *obj;
2501 int plane = intel_crtc->plane;
2502 unsigned long linear_offset;
2503 u32 dspcntr;
2504 u32 reg = DSPCNTR(plane);
2505 int pixel_size;
2506
2507 if (!intel_crtc->primary_enabled) {
2508 I915_WRITE(reg, 0);
2509 if (INTEL_INFO(dev)->gen >= 4)
2510 I915_WRITE(DSPSURF(plane), 0);
2511 else
2512 I915_WRITE(DSPADDR(plane), 0);
2513 POSTING_READ(reg);
2514 return;
2515 }
2516
2517 obj = intel_fb_obj(fb);
2518 if (WARN_ON(obj == NULL))
2519 return;
2520
2521 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2522
2523 dspcntr = DISPPLANE_GAMMA_ENABLE;
2524
2525 dspcntr |= DISPLAY_PLANE_ENABLE;
2526
2527 if (INTEL_INFO(dev)->gen < 4) {
2528 if (intel_crtc->pipe == PIPE_B)
2529 dspcntr |= DISPPLANE_SEL_PIPE_B;
2530
2531 /* pipesrc and dspsize control the size that is scaled from,
2532 * which should always be the user's requested size.
2533 */
2534 I915_WRITE(DSPSIZE(plane),
2535 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2536 (intel_crtc->config->pipe_src_w - 1));
2537 I915_WRITE(DSPPOS(plane), 0);
2538 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2539 I915_WRITE(PRIMSIZE(plane),
2540 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2541 (intel_crtc->config->pipe_src_w - 1));
2542 I915_WRITE(PRIMPOS(plane), 0);
2543 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2544 }
2545
2546 switch (fb->pixel_format) {
2547 case DRM_FORMAT_C8:
2548 dspcntr |= DISPPLANE_8BPP;
2549 break;
2550 case DRM_FORMAT_XRGB1555:
2551 case DRM_FORMAT_ARGB1555:
2552 dspcntr |= DISPPLANE_BGRX555;
2553 break;
2554 case DRM_FORMAT_RGB565:
2555 dspcntr |= DISPPLANE_BGRX565;
2556 break;
2557 case DRM_FORMAT_XRGB8888:
2558 case DRM_FORMAT_ARGB8888:
2559 dspcntr |= DISPPLANE_BGRX888;
2560 break;
2561 case DRM_FORMAT_XBGR8888:
2562 case DRM_FORMAT_ABGR8888:
2563 dspcntr |= DISPPLANE_RGBX888;
2564 break;
2565 case DRM_FORMAT_XRGB2101010:
2566 case DRM_FORMAT_ARGB2101010:
2567 dspcntr |= DISPPLANE_BGRX101010;
2568 break;
2569 case DRM_FORMAT_XBGR2101010:
2570 case DRM_FORMAT_ABGR2101010:
2571 dspcntr |= DISPPLANE_RGBX101010;
2572 break;
2573 default:
2574 BUG();
2575 }
2576
2577 if (INTEL_INFO(dev)->gen >= 4 &&
2578 obj->tiling_mode != I915_TILING_NONE)
2579 dspcntr |= DISPPLANE_TILED;
2580
2581 if (IS_G4X(dev))
2582 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2583
2584 linear_offset = y * fb->pitches[0] + x * pixel_size;
2585
2586 if (INTEL_INFO(dev)->gen >= 4) {
2587 intel_crtc->dspaddr_offset =
2588 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2589 pixel_size,
2590 fb->pitches[0]);
2591 linear_offset -= intel_crtc->dspaddr_offset;
2592 } else {
2593 intel_crtc->dspaddr_offset = linear_offset;
2594 }
2595
2596 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2597 dspcntr |= DISPPLANE_ROTATE_180;
2598
2599 x += (intel_crtc->config->pipe_src_w - 1);
2600 y += (intel_crtc->config->pipe_src_h - 1);
2601
2602 /* Finding the last pixel of the last line of the display
2603 data and adding to linear_offset*/
2604 linear_offset +=
2605 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2606 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2607 }
2608
2609 I915_WRITE(reg, dspcntr);
2610
2611 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2612 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2613 fb->pitches[0]);
2614 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2615 if (INTEL_INFO(dev)->gen >= 4) {
2616 I915_WRITE(DSPSURF(plane),
2617 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2618 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2619 I915_WRITE(DSPLINOFF(plane), linear_offset);
2620 } else
2621 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2622 POSTING_READ(reg);
2623 }
2624
2625 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2626 struct drm_framebuffer *fb,
2627 int x, int y)
2628 {
2629 struct drm_device *dev = crtc->dev;
2630 struct drm_i915_private *dev_priv = dev->dev_private;
2631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2632 struct drm_i915_gem_object *obj;
2633 int plane = intel_crtc->plane;
2634 unsigned long linear_offset;
2635 u32 dspcntr;
2636 u32 reg = DSPCNTR(plane);
2637 int pixel_size;
2638
2639 if (!intel_crtc->primary_enabled) {
2640 I915_WRITE(reg, 0);
2641 I915_WRITE(DSPSURF(plane), 0);
2642 POSTING_READ(reg);
2643 return;
2644 }
2645
2646 obj = intel_fb_obj(fb);
2647 if (WARN_ON(obj == NULL))
2648 return;
2649
2650 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2651
2652 dspcntr = DISPPLANE_GAMMA_ENABLE;
2653
2654 dspcntr |= DISPLAY_PLANE_ENABLE;
2655
2656 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2657 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2658
2659 switch (fb->pixel_format) {
2660 case DRM_FORMAT_C8:
2661 dspcntr |= DISPPLANE_8BPP;
2662 break;
2663 case DRM_FORMAT_RGB565:
2664 dspcntr |= DISPPLANE_BGRX565;
2665 break;
2666 case DRM_FORMAT_XRGB8888:
2667 case DRM_FORMAT_ARGB8888:
2668 dspcntr |= DISPPLANE_BGRX888;
2669 break;
2670 case DRM_FORMAT_XBGR8888:
2671 case DRM_FORMAT_ABGR8888:
2672 dspcntr |= DISPPLANE_RGBX888;
2673 break;
2674 case DRM_FORMAT_XRGB2101010:
2675 case DRM_FORMAT_ARGB2101010:
2676 dspcntr |= DISPPLANE_BGRX101010;
2677 break;
2678 case DRM_FORMAT_XBGR2101010:
2679 case DRM_FORMAT_ABGR2101010:
2680 dspcntr |= DISPPLANE_RGBX101010;
2681 break;
2682 default:
2683 BUG();
2684 }
2685
2686 if (obj->tiling_mode != I915_TILING_NONE)
2687 dspcntr |= DISPPLANE_TILED;
2688
2689 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2690 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2691
2692 linear_offset = y * fb->pitches[0] + x * pixel_size;
2693 intel_crtc->dspaddr_offset =
2694 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2695 pixel_size,
2696 fb->pitches[0]);
2697 linear_offset -= intel_crtc->dspaddr_offset;
2698 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2699 dspcntr |= DISPPLANE_ROTATE_180;
2700
2701 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2702 x += (intel_crtc->config->pipe_src_w - 1);
2703 y += (intel_crtc->config->pipe_src_h - 1);
2704
2705 /* Finding the last pixel of the last line of the display
2706 data and adding to linear_offset*/
2707 linear_offset +=
2708 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2709 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2710 }
2711 }
2712
2713 I915_WRITE(reg, dspcntr);
2714
2715 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2716 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2717 fb->pitches[0]);
2718 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2719 I915_WRITE(DSPSURF(plane),
2720 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2721 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2722 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2723 } else {
2724 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2725 I915_WRITE(DSPLINOFF(plane), linear_offset);
2726 }
2727 POSTING_READ(reg);
2728 }
2729
2730 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2731 struct drm_framebuffer *fb,
2732 int x, int y)
2733 {
2734 struct drm_device *dev = crtc->dev;
2735 struct drm_i915_private *dev_priv = dev->dev_private;
2736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2737 struct intel_framebuffer *intel_fb;
2738 struct drm_i915_gem_object *obj;
2739 int pipe = intel_crtc->pipe;
2740 u32 plane_ctl, stride;
2741
2742 if (!intel_crtc->primary_enabled) {
2743 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2744 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2745 POSTING_READ(PLANE_CTL(pipe, 0));
2746 return;
2747 }
2748
2749 plane_ctl = PLANE_CTL_ENABLE |
2750 PLANE_CTL_PIPE_GAMMA_ENABLE |
2751 PLANE_CTL_PIPE_CSC_ENABLE;
2752
2753 switch (fb->pixel_format) {
2754 case DRM_FORMAT_RGB565:
2755 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2756 break;
2757 case DRM_FORMAT_XRGB8888:
2758 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2759 break;
2760 case DRM_FORMAT_XBGR8888:
2761 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2762 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2763 break;
2764 case DRM_FORMAT_XRGB2101010:
2765 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2766 break;
2767 case DRM_FORMAT_XBGR2101010:
2768 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2769 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2770 break;
2771 default:
2772 BUG();
2773 }
2774
2775 intel_fb = to_intel_framebuffer(fb);
2776 obj = intel_fb->obj;
2777
2778 /*
2779 * The stride is either expressed as a multiple of 64 bytes chunks for
2780 * linear buffers or in number of tiles for tiled buffers.
2781 */
2782 switch (obj->tiling_mode) {
2783 case I915_TILING_NONE:
2784 stride = fb->pitches[0] >> 6;
2785 break;
2786 case I915_TILING_X:
2787 plane_ctl |= PLANE_CTL_TILED_X;
2788 stride = fb->pitches[0] >> 9;
2789 break;
2790 default:
2791 BUG();
2792 }
2793
2794 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2795 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2796 plane_ctl |= PLANE_CTL_ROTATE_180;
2797
2798 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2799
2800 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2801 i915_gem_obj_ggtt_offset(obj),
2802 x, y, fb->width, fb->height,
2803 fb->pitches[0]);
2804
2805 I915_WRITE(PLANE_POS(pipe, 0), 0);
2806 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2807 I915_WRITE(PLANE_SIZE(pipe, 0),
2808 (intel_crtc->config->pipe_src_h - 1) << 16 |
2809 (intel_crtc->config->pipe_src_w - 1));
2810 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2811 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2812
2813 POSTING_READ(PLANE_SURF(pipe, 0));
2814 }
2815
2816 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2817 static int
2818 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2819 int x, int y, enum mode_set_atomic state)
2820 {
2821 struct drm_device *dev = crtc->dev;
2822 struct drm_i915_private *dev_priv = dev->dev_private;
2823
2824 if (dev_priv->display.disable_fbc)
2825 dev_priv->display.disable_fbc(dev);
2826
2827 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2828
2829 return 0;
2830 }
2831
2832 static void intel_complete_page_flips(struct drm_device *dev)
2833 {
2834 struct drm_crtc *crtc;
2835
2836 for_each_crtc(dev, crtc) {
2837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2838 enum plane plane = intel_crtc->plane;
2839
2840 intel_prepare_page_flip(dev, plane);
2841 intel_finish_page_flip_plane(dev, plane);
2842 }
2843 }
2844
2845 static void intel_update_primary_planes(struct drm_device *dev)
2846 {
2847 struct drm_i915_private *dev_priv = dev->dev_private;
2848 struct drm_crtc *crtc;
2849
2850 for_each_crtc(dev, crtc) {
2851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2852
2853 drm_modeset_lock(&crtc->mutex, NULL);
2854 /*
2855 * FIXME: Once we have proper support for primary planes (and
2856 * disabling them without disabling the entire crtc) allow again
2857 * a NULL crtc->primary->fb.
2858 */
2859 if (intel_crtc->active && crtc->primary->fb)
2860 dev_priv->display.update_primary_plane(crtc,
2861 crtc->primary->fb,
2862 crtc->x,
2863 crtc->y);
2864 drm_modeset_unlock(&crtc->mutex);
2865 }
2866 }
2867
2868 void intel_prepare_reset(struct drm_device *dev)
2869 {
2870 struct drm_i915_private *dev_priv = to_i915(dev);
2871 struct intel_crtc *crtc;
2872
2873 /* no reset support for gen2 */
2874 if (IS_GEN2(dev))
2875 return;
2876
2877 /* reset doesn't touch the display */
2878 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2879 return;
2880
2881 drm_modeset_lock_all(dev);
2882
2883 /*
2884 * Disabling the crtcs gracefully seems nicer. Also the
2885 * g33 docs say we should at least disable all the planes.
2886 */
2887 for_each_intel_crtc(dev, crtc) {
2888 if (crtc->active)
2889 dev_priv->display.crtc_disable(&crtc->base);
2890 }
2891 }
2892
2893 void intel_finish_reset(struct drm_device *dev)
2894 {
2895 struct drm_i915_private *dev_priv = to_i915(dev);
2896
2897 /*
2898 * Flips in the rings will be nuked by the reset,
2899 * so complete all pending flips so that user space
2900 * will get its events and not get stuck.
2901 */
2902 intel_complete_page_flips(dev);
2903
2904 /* no reset support for gen2 */
2905 if (IS_GEN2(dev))
2906 return;
2907
2908 /* reset doesn't touch the display */
2909 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2910 /*
2911 * Flips in the rings have been nuked by the reset,
2912 * so update the base address of all primary
2913 * planes to the the last fb to make sure we're
2914 * showing the correct fb after a reset.
2915 */
2916 intel_update_primary_planes(dev);
2917 return;
2918 }
2919
2920 /*
2921 * The display has been reset as well,
2922 * so need a full re-initialization.
2923 */
2924 intel_runtime_pm_disable_interrupts(dev_priv);
2925 intel_runtime_pm_enable_interrupts(dev_priv);
2926
2927 intel_modeset_init_hw(dev);
2928
2929 spin_lock_irq(&dev_priv->irq_lock);
2930 if (dev_priv->display.hpd_irq_setup)
2931 dev_priv->display.hpd_irq_setup(dev);
2932 spin_unlock_irq(&dev_priv->irq_lock);
2933
2934 intel_modeset_setup_hw_state(dev, true);
2935
2936 intel_hpd_init(dev_priv);
2937
2938 drm_modeset_unlock_all(dev);
2939 }
2940
2941 static int
2942 intel_finish_fb(struct drm_framebuffer *old_fb)
2943 {
2944 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2945 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2946 bool was_interruptible = dev_priv->mm.interruptible;
2947 int ret;
2948
2949 /* Big Hammer, we also need to ensure that any pending
2950 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2951 * current scanout is retired before unpinning the old
2952 * framebuffer.
2953 *
2954 * This should only fail upon a hung GPU, in which case we
2955 * can safely continue.
2956 */
2957 dev_priv->mm.interruptible = false;
2958 ret = i915_gem_object_finish_gpu(obj);
2959 dev_priv->mm.interruptible = was_interruptible;
2960
2961 return ret;
2962 }
2963
2964 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2965 {
2966 struct drm_device *dev = crtc->dev;
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2969 bool pending;
2970
2971 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2972 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2973 return false;
2974
2975 spin_lock_irq(&dev->event_lock);
2976 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2977 spin_unlock_irq(&dev->event_lock);
2978
2979 return pending;
2980 }
2981
2982 static void intel_update_pipe_size(struct intel_crtc *crtc)
2983 {
2984 struct drm_device *dev = crtc->base.dev;
2985 struct drm_i915_private *dev_priv = dev->dev_private;
2986 const struct drm_display_mode *adjusted_mode;
2987
2988 if (!i915.fastboot)
2989 return;
2990
2991 /*
2992 * Update pipe size and adjust fitter if needed: the reason for this is
2993 * that in compute_mode_changes we check the native mode (not the pfit
2994 * mode) to see if we can flip rather than do a full mode set. In the
2995 * fastboot case, we'll flip, but if we don't update the pipesrc and
2996 * pfit state, we'll end up with a big fb scanned out into the wrong
2997 * sized surface.
2998 *
2999 * To fix this properly, we need to hoist the checks up into
3000 * compute_mode_changes (or above), check the actual pfit state and
3001 * whether the platform allows pfit disable with pipe active, and only
3002 * then update the pipesrc and pfit state, even on the flip path.
3003 */
3004
3005 adjusted_mode = &crtc->config->base.adjusted_mode;
3006
3007 I915_WRITE(PIPESRC(crtc->pipe),
3008 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3009 (adjusted_mode->crtc_vdisplay - 1));
3010 if (!crtc->config->pch_pfit.enabled &&
3011 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3012 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3013 I915_WRITE(PF_CTL(crtc->pipe), 0);
3014 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3015 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3016 }
3017 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3018 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3019 }
3020
3021 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3022 {
3023 struct drm_device *dev = crtc->dev;
3024 struct drm_i915_private *dev_priv = dev->dev_private;
3025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3026 int pipe = intel_crtc->pipe;
3027 u32 reg, temp;
3028
3029 /* enable normal train */
3030 reg = FDI_TX_CTL(pipe);
3031 temp = I915_READ(reg);
3032 if (IS_IVYBRIDGE(dev)) {
3033 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3034 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3035 } else {
3036 temp &= ~FDI_LINK_TRAIN_NONE;
3037 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3038 }
3039 I915_WRITE(reg, temp);
3040
3041 reg = FDI_RX_CTL(pipe);
3042 temp = I915_READ(reg);
3043 if (HAS_PCH_CPT(dev)) {
3044 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3045 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3046 } else {
3047 temp &= ~FDI_LINK_TRAIN_NONE;
3048 temp |= FDI_LINK_TRAIN_NONE;
3049 }
3050 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3051
3052 /* wait one idle pattern time */
3053 POSTING_READ(reg);
3054 udelay(1000);
3055
3056 /* IVB wants error correction enabled */
3057 if (IS_IVYBRIDGE(dev))
3058 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3059 FDI_FE_ERRC_ENABLE);
3060 }
3061
3062 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3063 {
3064 return crtc->base.enabled && crtc->active &&
3065 crtc->config->has_pch_encoder;
3066 }
3067
3068 static void ivb_modeset_global_resources(struct drm_device *dev)
3069 {
3070 struct drm_i915_private *dev_priv = dev->dev_private;
3071 struct intel_crtc *pipe_B_crtc =
3072 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3073 struct intel_crtc *pipe_C_crtc =
3074 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3075 uint32_t temp;
3076
3077 /*
3078 * When everything is off disable fdi C so that we could enable fdi B
3079 * with all lanes. Note that we don't care about enabled pipes without
3080 * an enabled pch encoder.
3081 */
3082 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3083 !pipe_has_enabled_pch(pipe_C_crtc)) {
3084 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3085 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3086
3087 temp = I915_READ(SOUTH_CHICKEN1);
3088 temp &= ~FDI_BC_BIFURCATION_SELECT;
3089 DRM_DEBUG_KMS("disabling fdi C rx\n");
3090 I915_WRITE(SOUTH_CHICKEN1, temp);
3091 }
3092 }
3093
3094 /* The FDI link training functions for ILK/Ibexpeak. */
3095 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3096 {
3097 struct drm_device *dev = crtc->dev;
3098 struct drm_i915_private *dev_priv = dev->dev_private;
3099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3100 int pipe = intel_crtc->pipe;
3101 u32 reg, temp, tries;
3102
3103 /* FDI needs bits from pipe first */
3104 assert_pipe_enabled(dev_priv, pipe);
3105
3106 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3107 for train result */
3108 reg = FDI_RX_IMR(pipe);
3109 temp = I915_READ(reg);
3110 temp &= ~FDI_RX_SYMBOL_LOCK;
3111 temp &= ~FDI_RX_BIT_LOCK;
3112 I915_WRITE(reg, temp);
3113 I915_READ(reg);
3114 udelay(150);
3115
3116 /* enable CPU FDI TX and PCH FDI RX */
3117 reg = FDI_TX_CTL(pipe);
3118 temp = I915_READ(reg);
3119 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3120 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3121 temp &= ~FDI_LINK_TRAIN_NONE;
3122 temp |= FDI_LINK_TRAIN_PATTERN_1;
3123 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3124
3125 reg = FDI_RX_CTL(pipe);
3126 temp = I915_READ(reg);
3127 temp &= ~FDI_LINK_TRAIN_NONE;
3128 temp |= FDI_LINK_TRAIN_PATTERN_1;
3129 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3130
3131 POSTING_READ(reg);
3132 udelay(150);
3133
3134 /* Ironlake workaround, enable clock pointer after FDI enable*/
3135 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3136 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3137 FDI_RX_PHASE_SYNC_POINTER_EN);
3138
3139 reg = FDI_RX_IIR(pipe);
3140 for (tries = 0; tries < 5; tries++) {
3141 temp = I915_READ(reg);
3142 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3143
3144 if ((temp & FDI_RX_BIT_LOCK)) {
3145 DRM_DEBUG_KMS("FDI train 1 done.\n");
3146 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3147 break;
3148 }
3149 }
3150 if (tries == 5)
3151 DRM_ERROR("FDI train 1 fail!\n");
3152
3153 /* Train 2 */
3154 reg = FDI_TX_CTL(pipe);
3155 temp = I915_READ(reg);
3156 temp &= ~FDI_LINK_TRAIN_NONE;
3157 temp |= FDI_LINK_TRAIN_PATTERN_2;
3158 I915_WRITE(reg, temp);
3159
3160 reg = FDI_RX_CTL(pipe);
3161 temp = I915_READ(reg);
3162 temp &= ~FDI_LINK_TRAIN_NONE;
3163 temp |= FDI_LINK_TRAIN_PATTERN_2;
3164 I915_WRITE(reg, temp);
3165
3166 POSTING_READ(reg);
3167 udelay(150);
3168
3169 reg = FDI_RX_IIR(pipe);
3170 for (tries = 0; tries < 5; tries++) {
3171 temp = I915_READ(reg);
3172 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3173
3174 if (temp & FDI_RX_SYMBOL_LOCK) {
3175 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3176 DRM_DEBUG_KMS("FDI train 2 done.\n");
3177 break;
3178 }
3179 }
3180 if (tries == 5)
3181 DRM_ERROR("FDI train 2 fail!\n");
3182
3183 DRM_DEBUG_KMS("FDI train done\n");
3184
3185 }
3186
3187 static const int snb_b_fdi_train_param[] = {
3188 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3189 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3190 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3191 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3192 };
3193
3194 /* The FDI link training functions for SNB/Cougarpoint. */
3195 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3196 {
3197 struct drm_device *dev = crtc->dev;
3198 struct drm_i915_private *dev_priv = dev->dev_private;
3199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3200 int pipe = intel_crtc->pipe;
3201 u32 reg, temp, i, retry;
3202
3203 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3204 for train result */
3205 reg = FDI_RX_IMR(pipe);
3206 temp = I915_READ(reg);
3207 temp &= ~FDI_RX_SYMBOL_LOCK;
3208 temp &= ~FDI_RX_BIT_LOCK;
3209 I915_WRITE(reg, temp);
3210
3211 POSTING_READ(reg);
3212 udelay(150);
3213
3214 /* enable CPU FDI TX and PCH FDI RX */
3215 reg = FDI_TX_CTL(pipe);
3216 temp = I915_READ(reg);
3217 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3218 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3219 temp &= ~FDI_LINK_TRAIN_NONE;
3220 temp |= FDI_LINK_TRAIN_PATTERN_1;
3221 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3222 /* SNB-B */
3223 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3224 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3225
3226 I915_WRITE(FDI_RX_MISC(pipe),
3227 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3228
3229 reg = FDI_RX_CTL(pipe);
3230 temp = I915_READ(reg);
3231 if (HAS_PCH_CPT(dev)) {
3232 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3233 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3234 } else {
3235 temp &= ~FDI_LINK_TRAIN_NONE;
3236 temp |= FDI_LINK_TRAIN_PATTERN_1;
3237 }
3238 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3239
3240 POSTING_READ(reg);
3241 udelay(150);
3242
3243 for (i = 0; i < 4; i++) {
3244 reg = FDI_TX_CTL(pipe);
3245 temp = I915_READ(reg);
3246 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3247 temp |= snb_b_fdi_train_param[i];
3248 I915_WRITE(reg, temp);
3249
3250 POSTING_READ(reg);
3251 udelay(500);
3252
3253 for (retry = 0; retry < 5; retry++) {
3254 reg = FDI_RX_IIR(pipe);
3255 temp = I915_READ(reg);
3256 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3257 if (temp & FDI_RX_BIT_LOCK) {
3258 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3259 DRM_DEBUG_KMS("FDI train 1 done.\n");
3260 break;
3261 }
3262 udelay(50);
3263 }
3264 if (retry < 5)
3265 break;
3266 }
3267 if (i == 4)
3268 DRM_ERROR("FDI train 1 fail!\n");
3269
3270 /* Train 2 */
3271 reg = FDI_TX_CTL(pipe);
3272 temp = I915_READ(reg);
3273 temp &= ~FDI_LINK_TRAIN_NONE;
3274 temp |= FDI_LINK_TRAIN_PATTERN_2;
3275 if (IS_GEN6(dev)) {
3276 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3277 /* SNB-B */
3278 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3279 }
3280 I915_WRITE(reg, temp);
3281
3282 reg = FDI_RX_CTL(pipe);
3283 temp = I915_READ(reg);
3284 if (HAS_PCH_CPT(dev)) {
3285 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3286 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3287 } else {
3288 temp &= ~FDI_LINK_TRAIN_NONE;
3289 temp |= FDI_LINK_TRAIN_PATTERN_2;
3290 }
3291 I915_WRITE(reg, temp);
3292
3293 POSTING_READ(reg);
3294 udelay(150);
3295
3296 for (i = 0; i < 4; i++) {
3297 reg = FDI_TX_CTL(pipe);
3298 temp = I915_READ(reg);
3299 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3300 temp |= snb_b_fdi_train_param[i];
3301 I915_WRITE(reg, temp);
3302
3303 POSTING_READ(reg);
3304 udelay(500);
3305
3306 for (retry = 0; retry < 5; retry++) {
3307 reg = FDI_RX_IIR(pipe);
3308 temp = I915_READ(reg);
3309 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3310 if (temp & FDI_RX_SYMBOL_LOCK) {
3311 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3312 DRM_DEBUG_KMS("FDI train 2 done.\n");
3313 break;
3314 }
3315 udelay(50);
3316 }
3317 if (retry < 5)
3318 break;
3319 }
3320 if (i == 4)
3321 DRM_ERROR("FDI train 2 fail!\n");
3322
3323 DRM_DEBUG_KMS("FDI train done.\n");
3324 }
3325
3326 /* Manual link training for Ivy Bridge A0 parts */
3327 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3328 {
3329 struct drm_device *dev = crtc->dev;
3330 struct drm_i915_private *dev_priv = dev->dev_private;
3331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3332 int pipe = intel_crtc->pipe;
3333 u32 reg, temp, i, j;
3334
3335 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3336 for train result */
3337 reg = FDI_RX_IMR(pipe);
3338 temp = I915_READ(reg);
3339 temp &= ~FDI_RX_SYMBOL_LOCK;
3340 temp &= ~FDI_RX_BIT_LOCK;
3341 I915_WRITE(reg, temp);
3342
3343 POSTING_READ(reg);
3344 udelay(150);
3345
3346 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3347 I915_READ(FDI_RX_IIR(pipe)));
3348
3349 /* Try each vswing and preemphasis setting twice before moving on */
3350 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3351 /* disable first in case we need to retry */
3352 reg = FDI_TX_CTL(pipe);
3353 temp = I915_READ(reg);
3354 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3355 temp &= ~FDI_TX_ENABLE;
3356 I915_WRITE(reg, temp);
3357
3358 reg = FDI_RX_CTL(pipe);
3359 temp = I915_READ(reg);
3360 temp &= ~FDI_LINK_TRAIN_AUTO;
3361 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3362 temp &= ~FDI_RX_ENABLE;
3363 I915_WRITE(reg, temp);
3364
3365 /* enable CPU FDI TX and PCH FDI RX */
3366 reg = FDI_TX_CTL(pipe);
3367 temp = I915_READ(reg);
3368 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3369 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3370 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3371 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3372 temp |= snb_b_fdi_train_param[j/2];
3373 temp |= FDI_COMPOSITE_SYNC;
3374 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3375
3376 I915_WRITE(FDI_RX_MISC(pipe),
3377 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3378
3379 reg = FDI_RX_CTL(pipe);
3380 temp = I915_READ(reg);
3381 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3382 temp |= FDI_COMPOSITE_SYNC;
3383 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3384
3385 POSTING_READ(reg);
3386 udelay(1); /* should be 0.5us */
3387
3388 for (i = 0; i < 4; i++) {
3389 reg = FDI_RX_IIR(pipe);
3390 temp = I915_READ(reg);
3391 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3392
3393 if (temp & FDI_RX_BIT_LOCK ||
3394 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3395 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3396 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3397 i);
3398 break;
3399 }
3400 udelay(1); /* should be 0.5us */
3401 }
3402 if (i == 4) {
3403 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3404 continue;
3405 }
3406
3407 /* Train 2 */
3408 reg = FDI_TX_CTL(pipe);
3409 temp = I915_READ(reg);
3410 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3411 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3412 I915_WRITE(reg, temp);
3413
3414 reg = FDI_RX_CTL(pipe);
3415 temp = I915_READ(reg);
3416 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3417 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3418 I915_WRITE(reg, temp);
3419
3420 POSTING_READ(reg);
3421 udelay(2); /* should be 1.5us */
3422
3423 for (i = 0; i < 4; i++) {
3424 reg = FDI_RX_IIR(pipe);
3425 temp = I915_READ(reg);
3426 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3427
3428 if (temp & FDI_RX_SYMBOL_LOCK ||
3429 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3430 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3431 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3432 i);
3433 goto train_done;
3434 }
3435 udelay(2); /* should be 1.5us */
3436 }
3437 if (i == 4)
3438 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3439 }
3440
3441 train_done:
3442 DRM_DEBUG_KMS("FDI train done.\n");
3443 }
3444
3445 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3446 {
3447 struct drm_device *dev = intel_crtc->base.dev;
3448 struct drm_i915_private *dev_priv = dev->dev_private;
3449 int pipe = intel_crtc->pipe;
3450 u32 reg, temp;
3451
3452
3453 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3454 reg = FDI_RX_CTL(pipe);
3455 temp = I915_READ(reg);
3456 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3457 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3458 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3459 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3460
3461 POSTING_READ(reg);
3462 udelay(200);
3463
3464 /* Switch from Rawclk to PCDclk */
3465 temp = I915_READ(reg);
3466 I915_WRITE(reg, temp | FDI_PCDCLK);
3467
3468 POSTING_READ(reg);
3469 udelay(200);
3470
3471 /* Enable CPU FDI TX PLL, always on for Ironlake */
3472 reg = FDI_TX_CTL(pipe);
3473 temp = I915_READ(reg);
3474 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3475 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3476
3477 POSTING_READ(reg);
3478 udelay(100);
3479 }
3480 }
3481
3482 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3483 {
3484 struct drm_device *dev = intel_crtc->base.dev;
3485 struct drm_i915_private *dev_priv = dev->dev_private;
3486 int pipe = intel_crtc->pipe;
3487 u32 reg, temp;
3488
3489 /* Switch from PCDclk to Rawclk */
3490 reg = FDI_RX_CTL(pipe);
3491 temp = I915_READ(reg);
3492 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3493
3494 /* Disable CPU FDI TX PLL */
3495 reg = FDI_TX_CTL(pipe);
3496 temp = I915_READ(reg);
3497 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3498
3499 POSTING_READ(reg);
3500 udelay(100);
3501
3502 reg = FDI_RX_CTL(pipe);
3503 temp = I915_READ(reg);
3504 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3505
3506 /* Wait for the clocks to turn off. */
3507 POSTING_READ(reg);
3508 udelay(100);
3509 }
3510
3511 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3512 {
3513 struct drm_device *dev = crtc->dev;
3514 struct drm_i915_private *dev_priv = dev->dev_private;
3515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3516 int pipe = intel_crtc->pipe;
3517 u32 reg, temp;
3518
3519 /* disable CPU FDI tx and PCH FDI rx */
3520 reg = FDI_TX_CTL(pipe);
3521 temp = I915_READ(reg);
3522 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3523 POSTING_READ(reg);
3524
3525 reg = FDI_RX_CTL(pipe);
3526 temp = I915_READ(reg);
3527 temp &= ~(0x7 << 16);
3528 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3529 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3530
3531 POSTING_READ(reg);
3532 udelay(100);
3533
3534 /* Ironlake workaround, disable clock pointer after downing FDI */
3535 if (HAS_PCH_IBX(dev))
3536 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3537
3538 /* still set train pattern 1 */
3539 reg = FDI_TX_CTL(pipe);
3540 temp = I915_READ(reg);
3541 temp &= ~FDI_LINK_TRAIN_NONE;
3542 temp |= FDI_LINK_TRAIN_PATTERN_1;
3543 I915_WRITE(reg, temp);
3544
3545 reg = FDI_RX_CTL(pipe);
3546 temp = I915_READ(reg);
3547 if (HAS_PCH_CPT(dev)) {
3548 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3549 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3550 } else {
3551 temp &= ~FDI_LINK_TRAIN_NONE;
3552 temp |= FDI_LINK_TRAIN_PATTERN_1;
3553 }
3554 /* BPC in FDI rx is consistent with that in PIPECONF */
3555 temp &= ~(0x07 << 16);
3556 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3557 I915_WRITE(reg, temp);
3558
3559 POSTING_READ(reg);
3560 udelay(100);
3561 }
3562
3563 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3564 {
3565 struct intel_crtc *crtc;
3566
3567 /* Note that we don't need to be called with mode_config.lock here
3568 * as our list of CRTC objects is static for the lifetime of the
3569 * device and so cannot disappear as we iterate. Similarly, we can
3570 * happily treat the predicates as racy, atomic checks as userspace
3571 * cannot claim and pin a new fb without at least acquring the
3572 * struct_mutex and so serialising with us.
3573 */
3574 for_each_intel_crtc(dev, crtc) {
3575 if (atomic_read(&crtc->unpin_work_count) == 0)
3576 continue;
3577
3578 if (crtc->unpin_work)
3579 intel_wait_for_vblank(dev, crtc->pipe);
3580
3581 return true;
3582 }
3583
3584 return false;
3585 }
3586
3587 static void page_flip_completed(struct intel_crtc *intel_crtc)
3588 {
3589 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3590 struct intel_unpin_work *work = intel_crtc->unpin_work;
3591
3592 /* ensure that the unpin work is consistent wrt ->pending. */
3593 smp_rmb();
3594 intel_crtc->unpin_work = NULL;
3595
3596 if (work->event)
3597 drm_send_vblank_event(intel_crtc->base.dev,
3598 intel_crtc->pipe,
3599 work->event);
3600
3601 drm_crtc_vblank_put(&intel_crtc->base);
3602
3603 wake_up_all(&dev_priv->pending_flip_queue);
3604 queue_work(dev_priv->wq, &work->work);
3605
3606 trace_i915_flip_complete(intel_crtc->plane,
3607 work->pending_flip_obj);
3608 }
3609
3610 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3611 {
3612 struct drm_device *dev = crtc->dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614
3615 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3616 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3617 !intel_crtc_has_pending_flip(crtc),
3618 60*HZ) == 0)) {
3619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3620
3621 spin_lock_irq(&dev->event_lock);
3622 if (intel_crtc->unpin_work) {
3623 WARN_ONCE(1, "Removing stuck page flip\n");
3624 page_flip_completed(intel_crtc);
3625 }
3626 spin_unlock_irq(&dev->event_lock);
3627 }
3628
3629 if (crtc->primary->fb) {
3630 mutex_lock(&dev->struct_mutex);
3631 intel_finish_fb(crtc->primary->fb);
3632 mutex_unlock(&dev->struct_mutex);
3633 }
3634 }
3635
3636 /* Program iCLKIP clock to the desired frequency */
3637 static void lpt_program_iclkip(struct drm_crtc *crtc)
3638 {
3639 struct drm_device *dev = crtc->dev;
3640 struct drm_i915_private *dev_priv = dev->dev_private;
3641 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3642 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3643 u32 temp;
3644
3645 mutex_lock(&dev_priv->dpio_lock);
3646
3647 /* It is necessary to ungate the pixclk gate prior to programming
3648 * the divisors, and gate it back when it is done.
3649 */
3650 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3651
3652 /* Disable SSCCTL */
3653 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3654 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3655 SBI_SSCCTL_DISABLE,
3656 SBI_ICLK);
3657
3658 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3659 if (clock == 20000) {
3660 auxdiv = 1;
3661 divsel = 0x41;
3662 phaseinc = 0x20;
3663 } else {
3664 /* The iCLK virtual clock root frequency is in MHz,
3665 * but the adjusted_mode->crtc_clock in in KHz. To get the
3666 * divisors, it is necessary to divide one by another, so we
3667 * convert the virtual clock precision to KHz here for higher
3668 * precision.
3669 */
3670 u32 iclk_virtual_root_freq = 172800 * 1000;
3671 u32 iclk_pi_range = 64;
3672 u32 desired_divisor, msb_divisor_value, pi_value;
3673
3674 desired_divisor = (iclk_virtual_root_freq / clock);
3675 msb_divisor_value = desired_divisor / iclk_pi_range;
3676 pi_value = desired_divisor % iclk_pi_range;
3677
3678 auxdiv = 0;
3679 divsel = msb_divisor_value - 2;
3680 phaseinc = pi_value;
3681 }
3682
3683 /* This should not happen with any sane values */
3684 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3685 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3686 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3687 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3688
3689 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3690 clock,
3691 auxdiv,
3692 divsel,
3693 phasedir,
3694 phaseinc);
3695
3696 /* Program SSCDIVINTPHASE6 */
3697 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3698 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3699 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3700 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3701 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3702 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3703 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3704 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3705
3706 /* Program SSCAUXDIV */
3707 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3708 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3709 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3710 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3711
3712 /* Enable modulator and associated divider */
3713 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3714 temp &= ~SBI_SSCCTL_DISABLE;
3715 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3716
3717 /* Wait for initialization time */
3718 udelay(24);
3719
3720 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3721
3722 mutex_unlock(&dev_priv->dpio_lock);
3723 }
3724
3725 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3726 enum pipe pch_transcoder)
3727 {
3728 struct drm_device *dev = crtc->base.dev;
3729 struct drm_i915_private *dev_priv = dev->dev_private;
3730 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3731
3732 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3733 I915_READ(HTOTAL(cpu_transcoder)));
3734 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3735 I915_READ(HBLANK(cpu_transcoder)));
3736 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3737 I915_READ(HSYNC(cpu_transcoder)));
3738
3739 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3740 I915_READ(VTOTAL(cpu_transcoder)));
3741 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3742 I915_READ(VBLANK(cpu_transcoder)));
3743 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3744 I915_READ(VSYNC(cpu_transcoder)));
3745 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3746 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3747 }
3748
3749 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3750 {
3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 uint32_t temp;
3753
3754 temp = I915_READ(SOUTH_CHICKEN1);
3755 if (temp & FDI_BC_BIFURCATION_SELECT)
3756 return;
3757
3758 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3759 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3760
3761 temp |= FDI_BC_BIFURCATION_SELECT;
3762 DRM_DEBUG_KMS("enabling fdi C rx\n");
3763 I915_WRITE(SOUTH_CHICKEN1, temp);
3764 POSTING_READ(SOUTH_CHICKEN1);
3765 }
3766
3767 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3768 {
3769 struct drm_device *dev = intel_crtc->base.dev;
3770 struct drm_i915_private *dev_priv = dev->dev_private;
3771
3772 switch (intel_crtc->pipe) {
3773 case PIPE_A:
3774 break;
3775 case PIPE_B:
3776 if (intel_crtc->config->fdi_lanes > 2)
3777 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3778 else
3779 cpt_enable_fdi_bc_bifurcation(dev);
3780
3781 break;
3782 case PIPE_C:
3783 cpt_enable_fdi_bc_bifurcation(dev);
3784
3785 break;
3786 default:
3787 BUG();
3788 }
3789 }
3790
3791 /*
3792 * Enable PCH resources required for PCH ports:
3793 * - PCH PLLs
3794 * - FDI training & RX/TX
3795 * - update transcoder timings
3796 * - DP transcoding bits
3797 * - transcoder
3798 */
3799 static void ironlake_pch_enable(struct drm_crtc *crtc)
3800 {
3801 struct drm_device *dev = crtc->dev;
3802 struct drm_i915_private *dev_priv = dev->dev_private;
3803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3804 int pipe = intel_crtc->pipe;
3805 u32 reg, temp;
3806
3807 assert_pch_transcoder_disabled(dev_priv, pipe);
3808
3809 if (IS_IVYBRIDGE(dev))
3810 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3811
3812 /* Write the TU size bits before fdi link training, so that error
3813 * detection works. */
3814 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3815 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3816
3817 /* For PCH output, training FDI link */
3818 dev_priv->display.fdi_link_train(crtc);
3819
3820 /* We need to program the right clock selection before writing the pixel
3821 * mutliplier into the DPLL. */
3822 if (HAS_PCH_CPT(dev)) {
3823 u32 sel;
3824
3825 temp = I915_READ(PCH_DPLL_SEL);
3826 temp |= TRANS_DPLL_ENABLE(pipe);
3827 sel = TRANS_DPLLB_SEL(pipe);
3828 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3829 temp |= sel;
3830 else
3831 temp &= ~sel;
3832 I915_WRITE(PCH_DPLL_SEL, temp);
3833 }
3834
3835 /* XXX: pch pll's can be enabled any time before we enable the PCH
3836 * transcoder, and we actually should do this to not upset any PCH
3837 * transcoder that already use the clock when we share it.
3838 *
3839 * Note that enable_shared_dpll tries to do the right thing, but
3840 * get_shared_dpll unconditionally resets the pll - we need that to have
3841 * the right LVDS enable sequence. */
3842 intel_enable_shared_dpll(intel_crtc);
3843
3844 /* set transcoder timing, panel must allow it */
3845 assert_panel_unlocked(dev_priv, pipe);
3846 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3847
3848 intel_fdi_normal_train(crtc);
3849
3850 /* For PCH DP, enable TRANS_DP_CTL */
3851 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3852 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3853 reg = TRANS_DP_CTL(pipe);
3854 temp = I915_READ(reg);
3855 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3856 TRANS_DP_SYNC_MASK |
3857 TRANS_DP_BPC_MASK);
3858 temp |= (TRANS_DP_OUTPUT_ENABLE |
3859 TRANS_DP_ENH_FRAMING);
3860 temp |= bpc << 9; /* same format but at 11:9 */
3861
3862 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3863 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3864 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3865 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3866
3867 switch (intel_trans_dp_port_sel(crtc)) {
3868 case PCH_DP_B:
3869 temp |= TRANS_DP_PORT_SEL_B;
3870 break;
3871 case PCH_DP_C:
3872 temp |= TRANS_DP_PORT_SEL_C;
3873 break;
3874 case PCH_DP_D:
3875 temp |= TRANS_DP_PORT_SEL_D;
3876 break;
3877 default:
3878 BUG();
3879 }
3880
3881 I915_WRITE(reg, temp);
3882 }
3883
3884 ironlake_enable_pch_transcoder(dev_priv, pipe);
3885 }
3886
3887 static void lpt_pch_enable(struct drm_crtc *crtc)
3888 {
3889 struct drm_device *dev = crtc->dev;
3890 struct drm_i915_private *dev_priv = dev->dev_private;
3891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3892 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3893
3894 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3895
3896 lpt_program_iclkip(crtc);
3897
3898 /* Set transcoder timing. */
3899 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3900
3901 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3902 }
3903
3904 void intel_put_shared_dpll(struct intel_crtc *crtc)
3905 {
3906 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3907
3908 if (pll == NULL)
3909 return;
3910
3911 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3912 WARN(1, "bad %s crtc mask\n", pll->name);
3913 return;
3914 }
3915
3916 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3917 if (pll->config.crtc_mask == 0) {
3918 WARN_ON(pll->on);
3919 WARN_ON(pll->active);
3920 }
3921
3922 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3923 }
3924
3925 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3926 struct intel_crtc_state *crtc_state)
3927 {
3928 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3929 struct intel_shared_dpll *pll;
3930 enum intel_dpll_id i;
3931
3932 if (HAS_PCH_IBX(dev_priv->dev)) {
3933 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3934 i = (enum intel_dpll_id) crtc->pipe;
3935 pll = &dev_priv->shared_dplls[i];
3936
3937 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3938 crtc->base.base.id, pll->name);
3939
3940 WARN_ON(pll->new_config->crtc_mask);
3941
3942 goto found;
3943 }
3944
3945 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3946 pll = &dev_priv->shared_dplls[i];
3947
3948 /* Only want to check enabled timings first */
3949 if (pll->new_config->crtc_mask == 0)
3950 continue;
3951
3952 if (memcmp(&crtc_state->dpll_hw_state,
3953 &pll->new_config->hw_state,
3954 sizeof(pll->new_config->hw_state)) == 0) {
3955 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3956 crtc->base.base.id, pll->name,
3957 pll->new_config->crtc_mask,
3958 pll->active);
3959 goto found;
3960 }
3961 }
3962
3963 /* Ok no matching timings, maybe there's a free one? */
3964 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3965 pll = &dev_priv->shared_dplls[i];
3966 if (pll->new_config->crtc_mask == 0) {
3967 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3968 crtc->base.base.id, pll->name);
3969 goto found;
3970 }
3971 }
3972
3973 return NULL;
3974
3975 found:
3976 if (pll->new_config->crtc_mask == 0)
3977 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3978
3979 crtc_state->shared_dpll = i;
3980 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3981 pipe_name(crtc->pipe));
3982
3983 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3984
3985 return pll;
3986 }
3987
3988 /**
3989 * intel_shared_dpll_start_config - start a new PLL staged config
3990 * @dev_priv: DRM device
3991 * @clear_pipes: mask of pipes that will have their PLLs freed
3992 *
3993 * Starts a new PLL staged config, copying the current config but
3994 * releasing the references of pipes specified in clear_pipes.
3995 */
3996 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3997 unsigned clear_pipes)
3998 {
3999 struct intel_shared_dpll *pll;
4000 enum intel_dpll_id i;
4001
4002 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4003 pll = &dev_priv->shared_dplls[i];
4004
4005 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4006 GFP_KERNEL);
4007 if (!pll->new_config)
4008 goto cleanup;
4009
4010 pll->new_config->crtc_mask &= ~clear_pipes;
4011 }
4012
4013 return 0;
4014
4015 cleanup:
4016 while (--i >= 0) {
4017 pll = &dev_priv->shared_dplls[i];
4018 kfree(pll->new_config);
4019 pll->new_config = NULL;
4020 }
4021
4022 return -ENOMEM;
4023 }
4024
4025 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4026 {
4027 struct intel_shared_dpll *pll;
4028 enum intel_dpll_id i;
4029
4030 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4031 pll = &dev_priv->shared_dplls[i];
4032
4033 WARN_ON(pll->new_config == &pll->config);
4034
4035 pll->config = *pll->new_config;
4036 kfree(pll->new_config);
4037 pll->new_config = NULL;
4038 }
4039 }
4040
4041 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4042 {
4043 struct intel_shared_dpll *pll;
4044 enum intel_dpll_id i;
4045
4046 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4047 pll = &dev_priv->shared_dplls[i];
4048
4049 WARN_ON(pll->new_config == &pll->config);
4050
4051 kfree(pll->new_config);
4052 pll->new_config = NULL;
4053 }
4054 }
4055
4056 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4057 {
4058 struct drm_i915_private *dev_priv = dev->dev_private;
4059 int dslreg = PIPEDSL(pipe);
4060 u32 temp;
4061
4062 temp = I915_READ(dslreg);
4063 udelay(500);
4064 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4065 if (wait_for(I915_READ(dslreg) != temp, 5))
4066 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4067 }
4068 }
4069
4070 static void skylake_pfit_enable(struct intel_crtc *crtc)
4071 {
4072 struct drm_device *dev = crtc->base.dev;
4073 struct drm_i915_private *dev_priv = dev->dev_private;
4074 int pipe = crtc->pipe;
4075
4076 if (crtc->config->pch_pfit.enabled) {
4077 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4078 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4079 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4080 }
4081 }
4082
4083 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4084 {
4085 struct drm_device *dev = crtc->base.dev;
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 int pipe = crtc->pipe;
4088
4089 if (crtc->config->pch_pfit.enabled) {
4090 /* Force use of hard-coded filter coefficients
4091 * as some pre-programmed values are broken,
4092 * e.g. x201.
4093 */
4094 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4095 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4096 PF_PIPE_SEL_IVB(pipe));
4097 else
4098 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4099 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4100 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4101 }
4102 }
4103
4104 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4105 {
4106 struct drm_device *dev = crtc->dev;
4107 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4108 struct drm_plane *plane;
4109 struct intel_plane *intel_plane;
4110
4111 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4112 intel_plane = to_intel_plane(plane);
4113 if (intel_plane->pipe == pipe)
4114 intel_plane_restore(&intel_plane->base);
4115 }
4116 }
4117
4118 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4119 {
4120 struct drm_device *dev = crtc->dev;
4121 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4122 struct drm_plane *plane;
4123 struct intel_plane *intel_plane;
4124
4125 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4126 intel_plane = to_intel_plane(plane);
4127 if (intel_plane->pipe == pipe)
4128 plane->funcs->disable_plane(plane);
4129 }
4130 }
4131
4132 void hsw_enable_ips(struct intel_crtc *crtc)
4133 {
4134 struct drm_device *dev = crtc->base.dev;
4135 struct drm_i915_private *dev_priv = dev->dev_private;
4136
4137 if (!crtc->config->ips_enabled)
4138 return;
4139
4140 /* We can only enable IPS after we enable a plane and wait for a vblank */
4141 intel_wait_for_vblank(dev, crtc->pipe);
4142
4143 assert_plane_enabled(dev_priv, crtc->plane);
4144 if (IS_BROADWELL(dev)) {
4145 mutex_lock(&dev_priv->rps.hw_lock);
4146 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4147 mutex_unlock(&dev_priv->rps.hw_lock);
4148 /* Quoting Art Runyan: "its not safe to expect any particular
4149 * value in IPS_CTL bit 31 after enabling IPS through the
4150 * mailbox." Moreover, the mailbox may return a bogus state,
4151 * so we need to just enable it and continue on.
4152 */
4153 } else {
4154 I915_WRITE(IPS_CTL, IPS_ENABLE);
4155 /* The bit only becomes 1 in the next vblank, so this wait here
4156 * is essentially intel_wait_for_vblank. If we don't have this
4157 * and don't wait for vblanks until the end of crtc_enable, then
4158 * the HW state readout code will complain that the expected
4159 * IPS_CTL value is not the one we read. */
4160 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4161 DRM_ERROR("Timed out waiting for IPS enable\n");
4162 }
4163 }
4164
4165 void hsw_disable_ips(struct intel_crtc *crtc)
4166 {
4167 struct drm_device *dev = crtc->base.dev;
4168 struct drm_i915_private *dev_priv = dev->dev_private;
4169
4170 if (!crtc->config->ips_enabled)
4171 return;
4172
4173 assert_plane_enabled(dev_priv, crtc->plane);
4174 if (IS_BROADWELL(dev)) {
4175 mutex_lock(&dev_priv->rps.hw_lock);
4176 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4177 mutex_unlock(&dev_priv->rps.hw_lock);
4178 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4179 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4180 DRM_ERROR("Timed out waiting for IPS disable\n");
4181 } else {
4182 I915_WRITE(IPS_CTL, 0);
4183 POSTING_READ(IPS_CTL);
4184 }
4185
4186 /* We need to wait for a vblank before we can disable the plane. */
4187 intel_wait_for_vblank(dev, crtc->pipe);
4188 }
4189
4190 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4191 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4192 {
4193 struct drm_device *dev = crtc->dev;
4194 struct drm_i915_private *dev_priv = dev->dev_private;
4195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4196 enum pipe pipe = intel_crtc->pipe;
4197 int palreg = PALETTE(pipe);
4198 int i;
4199 bool reenable_ips = false;
4200
4201 /* The clocks have to be on to load the palette. */
4202 if (!crtc->enabled || !intel_crtc->active)
4203 return;
4204
4205 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4206 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4207 assert_dsi_pll_enabled(dev_priv);
4208 else
4209 assert_pll_enabled(dev_priv, pipe);
4210 }
4211
4212 /* use legacy palette for Ironlake */
4213 if (!HAS_GMCH_DISPLAY(dev))
4214 palreg = LGC_PALETTE(pipe);
4215
4216 /* Workaround : Do not read or write the pipe palette/gamma data while
4217 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4218 */
4219 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4220 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4221 GAMMA_MODE_MODE_SPLIT)) {
4222 hsw_disable_ips(intel_crtc);
4223 reenable_ips = true;
4224 }
4225
4226 for (i = 0; i < 256; i++) {
4227 I915_WRITE(palreg + 4 * i,
4228 (intel_crtc->lut_r[i] << 16) |
4229 (intel_crtc->lut_g[i] << 8) |
4230 intel_crtc->lut_b[i]);
4231 }
4232
4233 if (reenable_ips)
4234 hsw_enable_ips(intel_crtc);
4235 }
4236
4237 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4238 {
4239 if (!enable && intel_crtc->overlay) {
4240 struct drm_device *dev = intel_crtc->base.dev;
4241 struct drm_i915_private *dev_priv = dev->dev_private;
4242
4243 mutex_lock(&dev->struct_mutex);
4244 dev_priv->mm.interruptible = false;
4245 (void) intel_overlay_switch_off(intel_crtc->overlay);
4246 dev_priv->mm.interruptible = true;
4247 mutex_unlock(&dev->struct_mutex);
4248 }
4249
4250 /* Let userspace switch the overlay on again. In most cases userspace
4251 * has to recompute where to put it anyway.
4252 */
4253 }
4254
4255 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4256 {
4257 struct drm_device *dev = crtc->dev;
4258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4259 int pipe = intel_crtc->pipe;
4260
4261 intel_enable_primary_hw_plane(crtc->primary, crtc);
4262 intel_enable_sprite_planes(crtc);
4263 intel_crtc_update_cursor(crtc, true);
4264 intel_crtc_dpms_overlay(intel_crtc, true);
4265
4266 hsw_enable_ips(intel_crtc);
4267
4268 mutex_lock(&dev->struct_mutex);
4269 intel_fbc_update(dev);
4270 mutex_unlock(&dev->struct_mutex);
4271
4272 /*
4273 * FIXME: Once we grow proper nuclear flip support out of this we need
4274 * to compute the mask of flip planes precisely. For the time being
4275 * consider this a flip from a NULL plane.
4276 */
4277 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4278 }
4279
4280 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4281 {
4282 struct drm_device *dev = crtc->dev;
4283 struct drm_i915_private *dev_priv = dev->dev_private;
4284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4285 int pipe = intel_crtc->pipe;
4286
4287 intel_crtc_wait_for_pending_flips(crtc);
4288
4289 if (dev_priv->fbc.crtc == intel_crtc)
4290 intel_fbc_disable(dev);
4291
4292 hsw_disable_ips(intel_crtc);
4293
4294 intel_crtc_dpms_overlay(intel_crtc, false);
4295 intel_crtc_update_cursor(crtc, false);
4296 intel_disable_sprite_planes(crtc);
4297 intel_disable_primary_hw_plane(crtc->primary, crtc);
4298
4299 /*
4300 * FIXME: Once we grow proper nuclear flip support out of this we need
4301 * to compute the mask of flip planes precisely. For the time being
4302 * consider this a flip to a NULL plane.
4303 */
4304 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4305 }
4306
4307 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4308 {
4309 struct drm_device *dev = crtc->dev;
4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4312 struct intel_encoder *encoder;
4313 int pipe = intel_crtc->pipe;
4314
4315 WARN_ON(!crtc->enabled);
4316
4317 if (intel_crtc->active)
4318 return;
4319
4320 if (intel_crtc->config->has_pch_encoder)
4321 intel_prepare_shared_dpll(intel_crtc);
4322
4323 if (intel_crtc->config->has_dp_encoder)
4324 intel_dp_set_m_n(intel_crtc);
4325
4326 intel_set_pipe_timings(intel_crtc);
4327
4328 if (intel_crtc->config->has_pch_encoder) {
4329 intel_cpu_transcoder_set_m_n(intel_crtc,
4330 &intel_crtc->config->fdi_m_n, NULL);
4331 }
4332
4333 ironlake_set_pipeconf(crtc);
4334
4335 intel_crtc->active = true;
4336
4337 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4338 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4339
4340 for_each_encoder_on_crtc(dev, crtc, encoder)
4341 if (encoder->pre_enable)
4342 encoder->pre_enable(encoder);
4343
4344 if (intel_crtc->config->has_pch_encoder) {
4345 /* Note: FDI PLL enabling _must_ be done before we enable the
4346 * cpu pipes, hence this is separate from all the other fdi/pch
4347 * enabling. */
4348 ironlake_fdi_pll_enable(intel_crtc);
4349 } else {
4350 assert_fdi_tx_disabled(dev_priv, pipe);
4351 assert_fdi_rx_disabled(dev_priv, pipe);
4352 }
4353
4354 ironlake_pfit_enable(intel_crtc);
4355
4356 /*
4357 * On ILK+ LUT must be loaded before the pipe is running but with
4358 * clocks enabled
4359 */
4360 intel_crtc_load_lut(crtc);
4361
4362 intel_update_watermarks(crtc);
4363 intel_enable_pipe(intel_crtc);
4364
4365 if (intel_crtc->config->has_pch_encoder)
4366 ironlake_pch_enable(crtc);
4367
4368 assert_vblank_disabled(crtc);
4369 drm_crtc_vblank_on(crtc);
4370
4371 for_each_encoder_on_crtc(dev, crtc, encoder)
4372 encoder->enable(encoder);
4373
4374 if (HAS_PCH_CPT(dev))
4375 cpt_verify_modeset(dev, intel_crtc->pipe);
4376
4377 intel_crtc_enable_planes(crtc);
4378 }
4379
4380 /* IPS only exists on ULT machines and is tied to pipe A. */
4381 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4382 {
4383 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4384 }
4385
4386 /*
4387 * This implements the workaround described in the "notes" section of the mode
4388 * set sequence documentation. When going from no pipes or single pipe to
4389 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4390 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4391 */
4392 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4393 {
4394 struct drm_device *dev = crtc->base.dev;
4395 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4396
4397 /* We want to get the other_active_crtc only if there's only 1 other
4398 * active crtc. */
4399 for_each_intel_crtc(dev, crtc_it) {
4400 if (!crtc_it->active || crtc_it == crtc)
4401 continue;
4402
4403 if (other_active_crtc)
4404 return;
4405
4406 other_active_crtc = crtc_it;
4407 }
4408 if (!other_active_crtc)
4409 return;
4410
4411 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4412 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4413 }
4414
4415 static void haswell_crtc_enable(struct drm_crtc *crtc)
4416 {
4417 struct drm_device *dev = crtc->dev;
4418 struct drm_i915_private *dev_priv = dev->dev_private;
4419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4420 struct intel_encoder *encoder;
4421 int pipe = intel_crtc->pipe;
4422
4423 WARN_ON(!crtc->enabled);
4424
4425 if (intel_crtc->active)
4426 return;
4427
4428 if (intel_crtc_to_shared_dpll(intel_crtc))
4429 intel_enable_shared_dpll(intel_crtc);
4430
4431 if (intel_crtc->config->has_dp_encoder)
4432 intel_dp_set_m_n(intel_crtc);
4433
4434 intel_set_pipe_timings(intel_crtc);
4435
4436 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4437 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4438 intel_crtc->config->pixel_multiplier - 1);
4439 }
4440
4441 if (intel_crtc->config->has_pch_encoder) {
4442 intel_cpu_transcoder_set_m_n(intel_crtc,
4443 &intel_crtc->config->fdi_m_n, NULL);
4444 }
4445
4446 haswell_set_pipeconf(crtc);
4447
4448 intel_set_pipe_csc(crtc);
4449
4450 intel_crtc->active = true;
4451
4452 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4453 for_each_encoder_on_crtc(dev, crtc, encoder)
4454 if (encoder->pre_enable)
4455 encoder->pre_enable(encoder);
4456
4457 if (intel_crtc->config->has_pch_encoder) {
4458 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4459 true);
4460 dev_priv->display.fdi_link_train(crtc);
4461 }
4462
4463 intel_ddi_enable_pipe_clock(intel_crtc);
4464
4465 if (IS_SKYLAKE(dev))
4466 skylake_pfit_enable(intel_crtc);
4467 else
4468 ironlake_pfit_enable(intel_crtc);
4469
4470 /*
4471 * On ILK+ LUT must be loaded before the pipe is running but with
4472 * clocks enabled
4473 */
4474 intel_crtc_load_lut(crtc);
4475
4476 intel_ddi_set_pipe_settings(crtc);
4477 intel_ddi_enable_transcoder_func(crtc);
4478
4479 intel_update_watermarks(crtc);
4480 intel_enable_pipe(intel_crtc);
4481
4482 if (intel_crtc->config->has_pch_encoder)
4483 lpt_pch_enable(crtc);
4484
4485 if (intel_crtc->config->dp_encoder_is_mst)
4486 intel_ddi_set_vc_payload_alloc(crtc, true);
4487
4488 assert_vblank_disabled(crtc);
4489 drm_crtc_vblank_on(crtc);
4490
4491 for_each_encoder_on_crtc(dev, crtc, encoder) {
4492 encoder->enable(encoder);
4493 intel_opregion_notify_encoder(encoder, true);
4494 }
4495
4496 /* If we change the relative order between pipe/planes enabling, we need
4497 * to change the workaround. */
4498 haswell_mode_set_planes_workaround(intel_crtc);
4499 intel_crtc_enable_planes(crtc);
4500 }
4501
4502 static void skylake_pfit_disable(struct intel_crtc *crtc)
4503 {
4504 struct drm_device *dev = crtc->base.dev;
4505 struct drm_i915_private *dev_priv = dev->dev_private;
4506 int pipe = crtc->pipe;
4507
4508 /* To avoid upsetting the power well on haswell only disable the pfit if
4509 * it's in use. The hw state code will make sure we get this right. */
4510 if (crtc->config->pch_pfit.enabled) {
4511 I915_WRITE(PS_CTL(pipe), 0);
4512 I915_WRITE(PS_WIN_POS(pipe), 0);
4513 I915_WRITE(PS_WIN_SZ(pipe), 0);
4514 }
4515 }
4516
4517 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4518 {
4519 struct drm_device *dev = crtc->base.dev;
4520 struct drm_i915_private *dev_priv = dev->dev_private;
4521 int pipe = crtc->pipe;
4522
4523 /* To avoid upsetting the power well on haswell only disable the pfit if
4524 * it's in use. The hw state code will make sure we get this right. */
4525 if (crtc->config->pch_pfit.enabled) {
4526 I915_WRITE(PF_CTL(pipe), 0);
4527 I915_WRITE(PF_WIN_POS(pipe), 0);
4528 I915_WRITE(PF_WIN_SZ(pipe), 0);
4529 }
4530 }
4531
4532 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4533 {
4534 struct drm_device *dev = crtc->dev;
4535 struct drm_i915_private *dev_priv = dev->dev_private;
4536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4537 struct intel_encoder *encoder;
4538 int pipe = intel_crtc->pipe;
4539 u32 reg, temp;
4540
4541 if (!intel_crtc->active)
4542 return;
4543
4544 intel_crtc_disable_planes(crtc);
4545
4546 for_each_encoder_on_crtc(dev, crtc, encoder)
4547 encoder->disable(encoder);
4548
4549 drm_crtc_vblank_off(crtc);
4550 assert_vblank_disabled(crtc);
4551
4552 if (intel_crtc->config->has_pch_encoder)
4553 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4554
4555 intel_disable_pipe(intel_crtc);
4556
4557 ironlake_pfit_disable(intel_crtc);
4558
4559 for_each_encoder_on_crtc(dev, crtc, encoder)
4560 if (encoder->post_disable)
4561 encoder->post_disable(encoder);
4562
4563 if (intel_crtc->config->has_pch_encoder) {
4564 ironlake_fdi_disable(crtc);
4565
4566 ironlake_disable_pch_transcoder(dev_priv, pipe);
4567
4568 if (HAS_PCH_CPT(dev)) {
4569 /* disable TRANS_DP_CTL */
4570 reg = TRANS_DP_CTL(pipe);
4571 temp = I915_READ(reg);
4572 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4573 TRANS_DP_PORT_SEL_MASK);
4574 temp |= TRANS_DP_PORT_SEL_NONE;
4575 I915_WRITE(reg, temp);
4576
4577 /* disable DPLL_SEL */
4578 temp = I915_READ(PCH_DPLL_SEL);
4579 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4580 I915_WRITE(PCH_DPLL_SEL, temp);
4581 }
4582
4583 /* disable PCH DPLL */
4584 intel_disable_shared_dpll(intel_crtc);
4585
4586 ironlake_fdi_pll_disable(intel_crtc);
4587 }
4588
4589 intel_crtc->active = false;
4590 intel_update_watermarks(crtc);
4591
4592 mutex_lock(&dev->struct_mutex);
4593 intel_fbc_update(dev);
4594 mutex_unlock(&dev->struct_mutex);
4595 }
4596
4597 static void haswell_crtc_disable(struct drm_crtc *crtc)
4598 {
4599 struct drm_device *dev = crtc->dev;
4600 struct drm_i915_private *dev_priv = dev->dev_private;
4601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4602 struct intel_encoder *encoder;
4603 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4604
4605 if (!intel_crtc->active)
4606 return;
4607
4608 intel_crtc_disable_planes(crtc);
4609
4610 for_each_encoder_on_crtc(dev, crtc, encoder) {
4611 intel_opregion_notify_encoder(encoder, false);
4612 encoder->disable(encoder);
4613 }
4614
4615 drm_crtc_vblank_off(crtc);
4616 assert_vblank_disabled(crtc);
4617
4618 if (intel_crtc->config->has_pch_encoder)
4619 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4620 false);
4621 intel_disable_pipe(intel_crtc);
4622
4623 if (intel_crtc->config->dp_encoder_is_mst)
4624 intel_ddi_set_vc_payload_alloc(crtc, false);
4625
4626 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4627
4628 if (IS_SKYLAKE(dev))
4629 skylake_pfit_disable(intel_crtc);
4630 else
4631 ironlake_pfit_disable(intel_crtc);
4632
4633 intel_ddi_disable_pipe_clock(intel_crtc);
4634
4635 if (intel_crtc->config->has_pch_encoder) {
4636 lpt_disable_pch_transcoder(dev_priv);
4637 intel_ddi_fdi_disable(crtc);
4638 }
4639
4640 for_each_encoder_on_crtc(dev, crtc, encoder)
4641 if (encoder->post_disable)
4642 encoder->post_disable(encoder);
4643
4644 intel_crtc->active = false;
4645 intel_update_watermarks(crtc);
4646
4647 mutex_lock(&dev->struct_mutex);
4648 intel_fbc_update(dev);
4649 mutex_unlock(&dev->struct_mutex);
4650
4651 if (intel_crtc_to_shared_dpll(intel_crtc))
4652 intel_disable_shared_dpll(intel_crtc);
4653 }
4654
4655 static void ironlake_crtc_off(struct drm_crtc *crtc)
4656 {
4657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4658 intel_put_shared_dpll(intel_crtc);
4659 }
4660
4661
4662 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4663 {
4664 struct drm_device *dev = crtc->base.dev;
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4666 struct intel_crtc_state *pipe_config = crtc->config;
4667
4668 if (!pipe_config->gmch_pfit.control)
4669 return;
4670
4671 /*
4672 * The panel fitter should only be adjusted whilst the pipe is disabled,
4673 * according to register description and PRM.
4674 */
4675 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4676 assert_pipe_disabled(dev_priv, crtc->pipe);
4677
4678 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4679 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4680
4681 /* Border color in case we don't scale up to the full screen. Black by
4682 * default, change to something else for debugging. */
4683 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4684 }
4685
4686 static enum intel_display_power_domain port_to_power_domain(enum port port)
4687 {
4688 switch (port) {
4689 case PORT_A:
4690 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4691 case PORT_B:
4692 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4693 case PORT_C:
4694 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4695 case PORT_D:
4696 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4697 default:
4698 WARN_ON_ONCE(1);
4699 return POWER_DOMAIN_PORT_OTHER;
4700 }
4701 }
4702
4703 #define for_each_power_domain(domain, mask) \
4704 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4705 if ((1 << (domain)) & (mask))
4706
4707 enum intel_display_power_domain
4708 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4709 {
4710 struct drm_device *dev = intel_encoder->base.dev;
4711 struct intel_digital_port *intel_dig_port;
4712
4713 switch (intel_encoder->type) {
4714 case INTEL_OUTPUT_UNKNOWN:
4715 /* Only DDI platforms should ever use this output type */
4716 WARN_ON_ONCE(!HAS_DDI(dev));
4717 case INTEL_OUTPUT_DISPLAYPORT:
4718 case INTEL_OUTPUT_HDMI:
4719 case INTEL_OUTPUT_EDP:
4720 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4721 return port_to_power_domain(intel_dig_port->port);
4722 case INTEL_OUTPUT_DP_MST:
4723 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4724 return port_to_power_domain(intel_dig_port->port);
4725 case INTEL_OUTPUT_ANALOG:
4726 return POWER_DOMAIN_PORT_CRT;
4727 case INTEL_OUTPUT_DSI:
4728 return POWER_DOMAIN_PORT_DSI;
4729 default:
4730 return POWER_DOMAIN_PORT_OTHER;
4731 }
4732 }
4733
4734 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4735 {
4736 struct drm_device *dev = crtc->dev;
4737 struct intel_encoder *intel_encoder;
4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739 enum pipe pipe = intel_crtc->pipe;
4740 unsigned long mask;
4741 enum transcoder transcoder;
4742
4743 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4744
4745 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4746 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4747 if (intel_crtc->config->pch_pfit.enabled ||
4748 intel_crtc->config->pch_pfit.force_thru)
4749 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4750
4751 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4752 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4753
4754 return mask;
4755 }
4756
4757 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4758 {
4759 struct drm_i915_private *dev_priv = dev->dev_private;
4760 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4761 struct intel_crtc *crtc;
4762
4763 /*
4764 * First get all needed power domains, then put all unneeded, to avoid
4765 * any unnecessary toggling of the power wells.
4766 */
4767 for_each_intel_crtc(dev, crtc) {
4768 enum intel_display_power_domain domain;
4769
4770 if (!crtc->base.enabled)
4771 continue;
4772
4773 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4774
4775 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4776 intel_display_power_get(dev_priv, domain);
4777 }
4778
4779 if (dev_priv->display.modeset_global_resources)
4780 dev_priv->display.modeset_global_resources(dev);
4781
4782 for_each_intel_crtc(dev, crtc) {
4783 enum intel_display_power_domain domain;
4784
4785 for_each_power_domain(domain, crtc->enabled_power_domains)
4786 intel_display_power_put(dev_priv, domain);
4787
4788 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4789 }
4790
4791 intel_display_set_init_power(dev_priv, false);
4792 }
4793
4794 /* returns HPLL frequency in kHz */
4795 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4796 {
4797 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4798
4799 /* Obtain SKU information */
4800 mutex_lock(&dev_priv->dpio_lock);
4801 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4802 CCK_FUSE_HPLL_FREQ_MASK;
4803 mutex_unlock(&dev_priv->dpio_lock);
4804
4805 return vco_freq[hpll_freq] * 1000;
4806 }
4807
4808 static void vlv_update_cdclk(struct drm_device *dev)
4809 {
4810 struct drm_i915_private *dev_priv = dev->dev_private;
4811
4812 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4813 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4814 dev_priv->vlv_cdclk_freq);
4815
4816 /*
4817 * Program the gmbus_freq based on the cdclk frequency.
4818 * BSpec erroneously claims we should aim for 4MHz, but
4819 * in fact 1MHz is the correct frequency.
4820 */
4821 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4822 }
4823
4824 /* Adjust CDclk dividers to allow high res or save power if possible */
4825 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4826 {
4827 struct drm_i915_private *dev_priv = dev->dev_private;
4828 u32 val, cmd;
4829
4830 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4831
4832 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4833 cmd = 2;
4834 else if (cdclk == 266667)
4835 cmd = 1;
4836 else
4837 cmd = 0;
4838
4839 mutex_lock(&dev_priv->rps.hw_lock);
4840 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4841 val &= ~DSPFREQGUAR_MASK;
4842 val |= (cmd << DSPFREQGUAR_SHIFT);
4843 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4844 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4845 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4846 50)) {
4847 DRM_ERROR("timed out waiting for CDclk change\n");
4848 }
4849 mutex_unlock(&dev_priv->rps.hw_lock);
4850
4851 if (cdclk == 400000) {
4852 u32 divider;
4853
4854 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4855
4856 mutex_lock(&dev_priv->dpio_lock);
4857 /* adjust cdclk divider */
4858 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4859 val &= ~DISPLAY_FREQUENCY_VALUES;
4860 val |= divider;
4861 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4862
4863 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4864 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4865 50))
4866 DRM_ERROR("timed out waiting for CDclk change\n");
4867 mutex_unlock(&dev_priv->dpio_lock);
4868 }
4869
4870 mutex_lock(&dev_priv->dpio_lock);
4871 /* adjust self-refresh exit latency value */
4872 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4873 val &= ~0x7f;
4874
4875 /*
4876 * For high bandwidth configs, we set a higher latency in the bunit
4877 * so that the core display fetch happens in time to avoid underruns.
4878 */
4879 if (cdclk == 400000)
4880 val |= 4500 / 250; /* 4.5 usec */
4881 else
4882 val |= 3000 / 250; /* 3.0 usec */
4883 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4884 mutex_unlock(&dev_priv->dpio_lock);
4885
4886 vlv_update_cdclk(dev);
4887 }
4888
4889 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4890 {
4891 struct drm_i915_private *dev_priv = dev->dev_private;
4892 u32 val, cmd;
4893
4894 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4895
4896 switch (cdclk) {
4897 case 400000:
4898 cmd = 3;
4899 break;
4900 case 333333:
4901 case 320000:
4902 cmd = 2;
4903 break;
4904 case 266667:
4905 cmd = 1;
4906 break;
4907 case 200000:
4908 cmd = 0;
4909 break;
4910 default:
4911 MISSING_CASE(cdclk);
4912 return;
4913 }
4914
4915 mutex_lock(&dev_priv->rps.hw_lock);
4916 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4917 val &= ~DSPFREQGUAR_MASK_CHV;
4918 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4919 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4920 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4921 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4922 50)) {
4923 DRM_ERROR("timed out waiting for CDclk change\n");
4924 }
4925 mutex_unlock(&dev_priv->rps.hw_lock);
4926
4927 vlv_update_cdclk(dev);
4928 }
4929
4930 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4931 int max_pixclk)
4932 {
4933 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
4934
4935 /* FIXME: Punit isn't quite ready yet */
4936 if (IS_CHERRYVIEW(dev_priv->dev))
4937 return 400000;
4938
4939 /*
4940 * Really only a few cases to deal with, as only 4 CDclks are supported:
4941 * 200MHz
4942 * 267MHz
4943 * 320/333MHz (depends on HPLL freq)
4944 * 400MHz
4945 * So we check to see whether we're above 90% of the lower bin and
4946 * adjust if needed.
4947 *
4948 * We seem to get an unstable or solid color picture at 200MHz.
4949 * Not sure what's wrong. For now use 200MHz only when all pipes
4950 * are off.
4951 */
4952 if (max_pixclk > freq_320*9/10)
4953 return 400000;
4954 else if (max_pixclk > 266667*9/10)
4955 return freq_320;
4956 else if (max_pixclk > 0)
4957 return 266667;
4958 else
4959 return 200000;
4960 }
4961
4962 /* compute the max pixel clock for new configuration */
4963 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4964 {
4965 struct drm_device *dev = dev_priv->dev;
4966 struct intel_crtc *intel_crtc;
4967 int max_pixclk = 0;
4968
4969 for_each_intel_crtc(dev, intel_crtc) {
4970 if (intel_crtc->new_enabled)
4971 max_pixclk = max(max_pixclk,
4972 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4973 }
4974
4975 return max_pixclk;
4976 }
4977
4978 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4979 unsigned *prepare_pipes)
4980 {
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4982 struct intel_crtc *intel_crtc;
4983 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4984
4985 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4986 dev_priv->vlv_cdclk_freq)
4987 return;
4988
4989 /* disable/enable all currently active pipes while we change cdclk */
4990 for_each_intel_crtc(dev, intel_crtc)
4991 if (intel_crtc->base.enabled)
4992 *prepare_pipes |= (1 << intel_crtc->pipe);
4993 }
4994
4995 static void valleyview_modeset_global_resources(struct drm_device *dev)
4996 {
4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4999 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5000
5001 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5002 /*
5003 * FIXME: We can end up here with all power domains off, yet
5004 * with a CDCLK frequency other than the minimum. To account
5005 * for this take the PIPE-A power domain, which covers the HW
5006 * blocks needed for the following programming. This can be
5007 * removed once it's guaranteed that we get here either with
5008 * the minimum CDCLK set, or the required power domains
5009 * enabled.
5010 */
5011 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5012
5013 if (IS_CHERRYVIEW(dev))
5014 cherryview_set_cdclk(dev, req_cdclk);
5015 else
5016 valleyview_set_cdclk(dev, req_cdclk);
5017
5018 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5019 }
5020 }
5021
5022 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5023 {
5024 struct drm_device *dev = crtc->dev;
5025 struct drm_i915_private *dev_priv = to_i915(dev);
5026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5027 struct intel_encoder *encoder;
5028 int pipe = intel_crtc->pipe;
5029 bool is_dsi;
5030
5031 WARN_ON(!crtc->enabled);
5032
5033 if (intel_crtc->active)
5034 return;
5035
5036 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5037
5038 if (!is_dsi) {
5039 if (IS_CHERRYVIEW(dev))
5040 chv_prepare_pll(intel_crtc, intel_crtc->config);
5041 else
5042 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5043 }
5044
5045 if (intel_crtc->config->has_dp_encoder)
5046 intel_dp_set_m_n(intel_crtc);
5047
5048 intel_set_pipe_timings(intel_crtc);
5049
5050 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5051 struct drm_i915_private *dev_priv = dev->dev_private;
5052
5053 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5054 I915_WRITE(CHV_CANVAS(pipe), 0);
5055 }
5056
5057 i9xx_set_pipeconf(intel_crtc);
5058
5059 intel_crtc->active = true;
5060
5061 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5062
5063 for_each_encoder_on_crtc(dev, crtc, encoder)
5064 if (encoder->pre_pll_enable)
5065 encoder->pre_pll_enable(encoder);
5066
5067 if (!is_dsi) {
5068 if (IS_CHERRYVIEW(dev))
5069 chv_enable_pll(intel_crtc, intel_crtc->config);
5070 else
5071 vlv_enable_pll(intel_crtc, intel_crtc->config);
5072 }
5073
5074 for_each_encoder_on_crtc(dev, crtc, encoder)
5075 if (encoder->pre_enable)
5076 encoder->pre_enable(encoder);
5077
5078 i9xx_pfit_enable(intel_crtc);
5079
5080 intel_crtc_load_lut(crtc);
5081
5082 intel_update_watermarks(crtc);
5083 intel_enable_pipe(intel_crtc);
5084
5085 assert_vblank_disabled(crtc);
5086 drm_crtc_vblank_on(crtc);
5087
5088 for_each_encoder_on_crtc(dev, crtc, encoder)
5089 encoder->enable(encoder);
5090
5091 intel_crtc_enable_planes(crtc);
5092
5093 /* Underruns don't raise interrupts, so check manually. */
5094 i9xx_check_fifo_underruns(dev_priv);
5095 }
5096
5097 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5098 {
5099 struct drm_device *dev = crtc->base.dev;
5100 struct drm_i915_private *dev_priv = dev->dev_private;
5101
5102 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5103 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5104 }
5105
5106 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5107 {
5108 struct drm_device *dev = crtc->dev;
5109 struct drm_i915_private *dev_priv = to_i915(dev);
5110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5111 struct intel_encoder *encoder;
5112 int pipe = intel_crtc->pipe;
5113
5114 WARN_ON(!crtc->enabled);
5115
5116 if (intel_crtc->active)
5117 return;
5118
5119 i9xx_set_pll_dividers(intel_crtc);
5120
5121 if (intel_crtc->config->has_dp_encoder)
5122 intel_dp_set_m_n(intel_crtc);
5123
5124 intel_set_pipe_timings(intel_crtc);
5125
5126 i9xx_set_pipeconf(intel_crtc);
5127
5128 intel_crtc->active = true;
5129
5130 if (!IS_GEN2(dev))
5131 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5132
5133 for_each_encoder_on_crtc(dev, crtc, encoder)
5134 if (encoder->pre_enable)
5135 encoder->pre_enable(encoder);
5136
5137 i9xx_enable_pll(intel_crtc);
5138
5139 i9xx_pfit_enable(intel_crtc);
5140
5141 intel_crtc_load_lut(crtc);
5142
5143 intel_update_watermarks(crtc);
5144 intel_enable_pipe(intel_crtc);
5145
5146 assert_vblank_disabled(crtc);
5147 drm_crtc_vblank_on(crtc);
5148
5149 for_each_encoder_on_crtc(dev, crtc, encoder)
5150 encoder->enable(encoder);
5151
5152 intel_crtc_enable_planes(crtc);
5153
5154 /*
5155 * Gen2 reports pipe underruns whenever all planes are disabled.
5156 * So don't enable underrun reporting before at least some planes
5157 * are enabled.
5158 * FIXME: Need to fix the logic to work when we turn off all planes
5159 * but leave the pipe running.
5160 */
5161 if (IS_GEN2(dev))
5162 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5163
5164 /* Underruns don't raise interrupts, so check manually. */
5165 i9xx_check_fifo_underruns(dev_priv);
5166 }
5167
5168 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5169 {
5170 struct drm_device *dev = crtc->base.dev;
5171 struct drm_i915_private *dev_priv = dev->dev_private;
5172
5173 if (!crtc->config->gmch_pfit.control)
5174 return;
5175
5176 assert_pipe_disabled(dev_priv, crtc->pipe);
5177
5178 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5179 I915_READ(PFIT_CONTROL));
5180 I915_WRITE(PFIT_CONTROL, 0);
5181 }
5182
5183 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5184 {
5185 struct drm_device *dev = crtc->dev;
5186 struct drm_i915_private *dev_priv = dev->dev_private;
5187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5188 struct intel_encoder *encoder;
5189 int pipe = intel_crtc->pipe;
5190
5191 if (!intel_crtc->active)
5192 return;
5193
5194 /*
5195 * Gen2 reports pipe underruns whenever all planes are disabled.
5196 * So diasble underrun reporting before all the planes get disabled.
5197 * FIXME: Need to fix the logic to work when we turn off all planes
5198 * but leave the pipe running.
5199 */
5200 if (IS_GEN2(dev))
5201 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5202
5203 /*
5204 * Vblank time updates from the shadow to live plane control register
5205 * are blocked if the memory self-refresh mode is active at that
5206 * moment. So to make sure the plane gets truly disabled, disable
5207 * first the self-refresh mode. The self-refresh enable bit in turn
5208 * will be checked/applied by the HW only at the next frame start
5209 * event which is after the vblank start event, so we need to have a
5210 * wait-for-vblank between disabling the plane and the pipe.
5211 */
5212 intel_set_memory_cxsr(dev_priv, false);
5213 intel_crtc_disable_planes(crtc);
5214
5215 /*
5216 * On gen2 planes are double buffered but the pipe isn't, so we must
5217 * wait for planes to fully turn off before disabling the pipe.
5218 * We also need to wait on all gmch platforms because of the
5219 * self-refresh mode constraint explained above.
5220 */
5221 intel_wait_for_vblank(dev, pipe);
5222
5223 for_each_encoder_on_crtc(dev, crtc, encoder)
5224 encoder->disable(encoder);
5225
5226 drm_crtc_vblank_off(crtc);
5227 assert_vblank_disabled(crtc);
5228
5229 intel_disable_pipe(intel_crtc);
5230
5231 i9xx_pfit_disable(intel_crtc);
5232
5233 for_each_encoder_on_crtc(dev, crtc, encoder)
5234 if (encoder->post_disable)
5235 encoder->post_disable(encoder);
5236
5237 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5238 if (IS_CHERRYVIEW(dev))
5239 chv_disable_pll(dev_priv, pipe);
5240 else if (IS_VALLEYVIEW(dev))
5241 vlv_disable_pll(dev_priv, pipe);
5242 else
5243 i9xx_disable_pll(intel_crtc);
5244 }
5245
5246 if (!IS_GEN2(dev))
5247 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5248
5249 intel_crtc->active = false;
5250 intel_update_watermarks(crtc);
5251
5252 mutex_lock(&dev->struct_mutex);
5253 intel_fbc_update(dev);
5254 mutex_unlock(&dev->struct_mutex);
5255 }
5256
5257 static void i9xx_crtc_off(struct drm_crtc *crtc)
5258 {
5259 }
5260
5261 /* Master function to enable/disable CRTC and corresponding power wells */
5262 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5263 {
5264 struct drm_device *dev = crtc->dev;
5265 struct drm_i915_private *dev_priv = dev->dev_private;
5266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5267 enum intel_display_power_domain domain;
5268 unsigned long domains;
5269
5270 if (enable) {
5271 if (!intel_crtc->active) {
5272 domains = get_crtc_power_domains(crtc);
5273 for_each_power_domain(domain, domains)
5274 intel_display_power_get(dev_priv, domain);
5275 intel_crtc->enabled_power_domains = domains;
5276
5277 dev_priv->display.crtc_enable(crtc);
5278 }
5279 } else {
5280 if (intel_crtc->active) {
5281 dev_priv->display.crtc_disable(crtc);
5282
5283 domains = intel_crtc->enabled_power_domains;
5284 for_each_power_domain(domain, domains)
5285 intel_display_power_put(dev_priv, domain);
5286 intel_crtc->enabled_power_domains = 0;
5287 }
5288 }
5289 }
5290
5291 /**
5292 * Sets the power management mode of the pipe and plane.
5293 */
5294 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5295 {
5296 struct drm_device *dev = crtc->dev;
5297 struct intel_encoder *intel_encoder;
5298 bool enable = false;
5299
5300 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5301 enable |= intel_encoder->connectors_active;
5302
5303 intel_crtc_control(crtc, enable);
5304 }
5305
5306 static void intel_crtc_disable(struct drm_crtc *crtc)
5307 {
5308 struct drm_device *dev = crtc->dev;
5309 struct drm_connector *connector;
5310 struct drm_i915_private *dev_priv = dev->dev_private;
5311
5312 /* crtc should still be enabled when we disable it. */
5313 WARN_ON(!crtc->enabled);
5314
5315 dev_priv->display.crtc_disable(crtc);
5316 dev_priv->display.off(crtc);
5317
5318 crtc->primary->funcs->disable_plane(crtc->primary);
5319
5320 /* Update computed state. */
5321 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5322 if (!connector->encoder || !connector->encoder->crtc)
5323 continue;
5324
5325 if (connector->encoder->crtc != crtc)
5326 continue;
5327
5328 connector->dpms = DRM_MODE_DPMS_OFF;
5329 to_intel_encoder(connector->encoder)->connectors_active = false;
5330 }
5331 }
5332
5333 void intel_encoder_destroy(struct drm_encoder *encoder)
5334 {
5335 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5336
5337 drm_encoder_cleanup(encoder);
5338 kfree(intel_encoder);
5339 }
5340
5341 /* Simple dpms helper for encoders with just one connector, no cloning and only
5342 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5343 * state of the entire output pipe. */
5344 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5345 {
5346 if (mode == DRM_MODE_DPMS_ON) {
5347 encoder->connectors_active = true;
5348
5349 intel_crtc_update_dpms(encoder->base.crtc);
5350 } else {
5351 encoder->connectors_active = false;
5352
5353 intel_crtc_update_dpms(encoder->base.crtc);
5354 }
5355 }
5356
5357 /* Cross check the actual hw state with our own modeset state tracking (and it's
5358 * internal consistency). */
5359 static void intel_connector_check_state(struct intel_connector *connector)
5360 {
5361 if (connector->get_hw_state(connector)) {
5362 struct intel_encoder *encoder = connector->encoder;
5363 struct drm_crtc *crtc;
5364 bool encoder_enabled;
5365 enum pipe pipe;
5366
5367 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5368 connector->base.base.id,
5369 connector->base.name);
5370
5371 /* there is no real hw state for MST connectors */
5372 if (connector->mst_port)
5373 return;
5374
5375 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5376 "wrong connector dpms state\n");
5377 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5378 "active connector not linked to encoder\n");
5379
5380 if (encoder) {
5381 I915_STATE_WARN(!encoder->connectors_active,
5382 "encoder->connectors_active not set\n");
5383
5384 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5385 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5386 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5387 return;
5388
5389 crtc = encoder->base.crtc;
5390
5391 I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
5392 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5393 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5394 "encoder active on the wrong pipe\n");
5395 }
5396 }
5397 }
5398
5399 /* Even simpler default implementation, if there's really no special case to
5400 * consider. */
5401 void intel_connector_dpms(struct drm_connector *connector, int mode)
5402 {
5403 /* All the simple cases only support two dpms states. */
5404 if (mode != DRM_MODE_DPMS_ON)
5405 mode = DRM_MODE_DPMS_OFF;
5406
5407 if (mode == connector->dpms)
5408 return;
5409
5410 connector->dpms = mode;
5411
5412 /* Only need to change hw state when actually enabled */
5413 if (connector->encoder)
5414 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5415
5416 intel_modeset_check_state(connector->dev);
5417 }
5418
5419 /* Simple connector->get_hw_state implementation for encoders that support only
5420 * one connector and no cloning and hence the encoder state determines the state
5421 * of the connector. */
5422 bool intel_connector_get_hw_state(struct intel_connector *connector)
5423 {
5424 enum pipe pipe = 0;
5425 struct intel_encoder *encoder = connector->encoder;
5426
5427 return encoder->get_hw_state(encoder, &pipe);
5428 }
5429
5430 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5431 struct intel_crtc_state *pipe_config)
5432 {
5433 struct drm_i915_private *dev_priv = dev->dev_private;
5434 struct intel_crtc *pipe_B_crtc =
5435 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5436
5437 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5438 pipe_name(pipe), pipe_config->fdi_lanes);
5439 if (pipe_config->fdi_lanes > 4) {
5440 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5441 pipe_name(pipe), pipe_config->fdi_lanes);
5442 return false;
5443 }
5444
5445 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5446 if (pipe_config->fdi_lanes > 2) {
5447 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5448 pipe_config->fdi_lanes);
5449 return false;
5450 } else {
5451 return true;
5452 }
5453 }
5454
5455 if (INTEL_INFO(dev)->num_pipes == 2)
5456 return true;
5457
5458 /* Ivybridge 3 pipe is really complicated */
5459 switch (pipe) {
5460 case PIPE_A:
5461 return true;
5462 case PIPE_B:
5463 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5464 pipe_config->fdi_lanes > 2) {
5465 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5466 pipe_name(pipe), pipe_config->fdi_lanes);
5467 return false;
5468 }
5469 return true;
5470 case PIPE_C:
5471 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5472 pipe_B_crtc->config->fdi_lanes <= 2) {
5473 if (pipe_config->fdi_lanes > 2) {
5474 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5475 pipe_name(pipe), pipe_config->fdi_lanes);
5476 return false;
5477 }
5478 } else {
5479 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5480 return false;
5481 }
5482 return true;
5483 default:
5484 BUG();
5485 }
5486 }
5487
5488 #define RETRY 1
5489 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5490 struct intel_crtc_state *pipe_config)
5491 {
5492 struct drm_device *dev = intel_crtc->base.dev;
5493 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5494 int lane, link_bw, fdi_dotclock;
5495 bool setup_ok, needs_recompute = false;
5496
5497 retry:
5498 /* FDI is a binary signal running at ~2.7GHz, encoding
5499 * each output octet as 10 bits. The actual frequency
5500 * is stored as a divider into a 100MHz clock, and the
5501 * mode pixel clock is stored in units of 1KHz.
5502 * Hence the bw of each lane in terms of the mode signal
5503 * is:
5504 */
5505 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5506
5507 fdi_dotclock = adjusted_mode->crtc_clock;
5508
5509 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5510 pipe_config->pipe_bpp);
5511
5512 pipe_config->fdi_lanes = lane;
5513
5514 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5515 link_bw, &pipe_config->fdi_m_n);
5516
5517 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5518 intel_crtc->pipe, pipe_config);
5519 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5520 pipe_config->pipe_bpp -= 2*3;
5521 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5522 pipe_config->pipe_bpp);
5523 needs_recompute = true;
5524 pipe_config->bw_constrained = true;
5525
5526 goto retry;
5527 }
5528
5529 if (needs_recompute)
5530 return RETRY;
5531
5532 return setup_ok ? 0 : -EINVAL;
5533 }
5534
5535 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5536 struct intel_crtc_state *pipe_config)
5537 {
5538 pipe_config->ips_enabled = i915.enable_ips &&
5539 hsw_crtc_supports_ips(crtc) &&
5540 pipe_config->pipe_bpp <= 24;
5541 }
5542
5543 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5544 struct intel_crtc_state *pipe_config)
5545 {
5546 struct drm_device *dev = crtc->base.dev;
5547 struct drm_i915_private *dev_priv = dev->dev_private;
5548 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5549
5550 /* FIXME should check pixel clock limits on all platforms */
5551 if (INTEL_INFO(dev)->gen < 4) {
5552 int clock_limit =
5553 dev_priv->display.get_display_clock_speed(dev);
5554
5555 /*
5556 * Enable pixel doubling when the dot clock
5557 * is > 90% of the (display) core speed.
5558 *
5559 * GDG double wide on either pipe,
5560 * otherwise pipe A only.
5561 */
5562 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5563 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5564 clock_limit *= 2;
5565 pipe_config->double_wide = true;
5566 }
5567
5568 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5569 return -EINVAL;
5570 }
5571
5572 /*
5573 * Pipe horizontal size must be even in:
5574 * - DVO ganged mode
5575 * - LVDS dual channel mode
5576 * - Double wide pipe
5577 */
5578 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5579 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5580 pipe_config->pipe_src_w &= ~1;
5581
5582 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5583 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5584 */
5585 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5586 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5587 return -EINVAL;
5588
5589 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5590 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5591 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5592 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5593 * for lvds. */
5594 pipe_config->pipe_bpp = 8*3;
5595 }
5596
5597 if (HAS_IPS(dev))
5598 hsw_compute_ips_config(crtc, pipe_config);
5599
5600 if (pipe_config->has_pch_encoder)
5601 return ironlake_fdi_compute_config(crtc, pipe_config);
5602
5603 return 0;
5604 }
5605
5606 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5607 {
5608 struct drm_i915_private *dev_priv = dev->dev_private;
5609 u32 val;
5610 int divider;
5611
5612 /* FIXME: Punit isn't quite ready yet */
5613 if (IS_CHERRYVIEW(dev))
5614 return 400000;
5615
5616 if (dev_priv->hpll_freq == 0)
5617 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5618
5619 mutex_lock(&dev_priv->dpio_lock);
5620 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5621 mutex_unlock(&dev_priv->dpio_lock);
5622
5623 divider = val & DISPLAY_FREQUENCY_VALUES;
5624
5625 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5626 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5627 "cdclk change in progress\n");
5628
5629 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5630 }
5631
5632 static int i945_get_display_clock_speed(struct drm_device *dev)
5633 {
5634 return 400000;
5635 }
5636
5637 static int i915_get_display_clock_speed(struct drm_device *dev)
5638 {
5639 return 333000;
5640 }
5641
5642 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5643 {
5644 return 200000;
5645 }
5646
5647 static int pnv_get_display_clock_speed(struct drm_device *dev)
5648 {
5649 u16 gcfgc = 0;
5650
5651 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5652
5653 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5654 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5655 return 267000;
5656 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5657 return 333000;
5658 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5659 return 444000;
5660 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5661 return 200000;
5662 default:
5663 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5664 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5665 return 133000;
5666 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5667 return 167000;
5668 }
5669 }
5670
5671 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5672 {
5673 u16 gcfgc = 0;
5674
5675 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5676
5677 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5678 return 133000;
5679 else {
5680 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5681 case GC_DISPLAY_CLOCK_333_MHZ:
5682 return 333000;
5683 default:
5684 case GC_DISPLAY_CLOCK_190_200_MHZ:
5685 return 190000;
5686 }
5687 }
5688 }
5689
5690 static int i865_get_display_clock_speed(struct drm_device *dev)
5691 {
5692 return 266000;
5693 }
5694
5695 static int i855_get_display_clock_speed(struct drm_device *dev)
5696 {
5697 u16 hpllcc = 0;
5698 /* Assume that the hardware is in the high speed state. This
5699 * should be the default.
5700 */
5701 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5702 case GC_CLOCK_133_200:
5703 case GC_CLOCK_100_200:
5704 return 200000;
5705 case GC_CLOCK_166_250:
5706 return 250000;
5707 case GC_CLOCK_100_133:
5708 return 133000;
5709 }
5710
5711 /* Shouldn't happen */
5712 return 0;
5713 }
5714
5715 static int i830_get_display_clock_speed(struct drm_device *dev)
5716 {
5717 return 133000;
5718 }
5719
5720 static void
5721 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5722 {
5723 while (*num > DATA_LINK_M_N_MASK ||
5724 *den > DATA_LINK_M_N_MASK) {
5725 *num >>= 1;
5726 *den >>= 1;
5727 }
5728 }
5729
5730 static void compute_m_n(unsigned int m, unsigned int n,
5731 uint32_t *ret_m, uint32_t *ret_n)
5732 {
5733 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5734 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5735 intel_reduce_m_n_ratio(ret_m, ret_n);
5736 }
5737
5738 void
5739 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5740 int pixel_clock, int link_clock,
5741 struct intel_link_m_n *m_n)
5742 {
5743 m_n->tu = 64;
5744
5745 compute_m_n(bits_per_pixel * pixel_clock,
5746 link_clock * nlanes * 8,
5747 &m_n->gmch_m, &m_n->gmch_n);
5748
5749 compute_m_n(pixel_clock, link_clock,
5750 &m_n->link_m, &m_n->link_n);
5751 }
5752
5753 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5754 {
5755 if (i915.panel_use_ssc >= 0)
5756 return i915.panel_use_ssc != 0;
5757 return dev_priv->vbt.lvds_use_ssc
5758 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5759 }
5760
5761 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5762 {
5763 struct drm_device *dev = crtc->base.dev;
5764 struct drm_i915_private *dev_priv = dev->dev_private;
5765 int refclk;
5766
5767 if (IS_VALLEYVIEW(dev)) {
5768 refclk = 100000;
5769 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5770 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5771 refclk = dev_priv->vbt.lvds_ssc_freq;
5772 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5773 } else if (!IS_GEN2(dev)) {
5774 refclk = 96000;
5775 } else {
5776 refclk = 48000;
5777 }
5778
5779 return refclk;
5780 }
5781
5782 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5783 {
5784 return (1 << dpll->n) << 16 | dpll->m2;
5785 }
5786
5787 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5788 {
5789 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5790 }
5791
5792 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5793 struct intel_crtc_state *crtc_state,
5794 intel_clock_t *reduced_clock)
5795 {
5796 struct drm_device *dev = crtc->base.dev;
5797 u32 fp, fp2 = 0;
5798
5799 if (IS_PINEVIEW(dev)) {
5800 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5801 if (reduced_clock)
5802 fp2 = pnv_dpll_compute_fp(reduced_clock);
5803 } else {
5804 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5805 if (reduced_clock)
5806 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5807 }
5808
5809 crtc_state->dpll_hw_state.fp0 = fp;
5810
5811 crtc->lowfreq_avail = false;
5812 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5813 reduced_clock && i915.powersave) {
5814 crtc_state->dpll_hw_state.fp1 = fp2;
5815 crtc->lowfreq_avail = true;
5816 } else {
5817 crtc_state->dpll_hw_state.fp1 = fp;
5818 }
5819 }
5820
5821 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5822 pipe)
5823 {
5824 u32 reg_val;
5825
5826 /*
5827 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5828 * and set it to a reasonable value instead.
5829 */
5830 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5831 reg_val &= 0xffffff00;
5832 reg_val |= 0x00000030;
5833 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5834
5835 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5836 reg_val &= 0x8cffffff;
5837 reg_val = 0x8c000000;
5838 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5839
5840 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5841 reg_val &= 0xffffff00;
5842 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5843
5844 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5845 reg_val &= 0x00ffffff;
5846 reg_val |= 0xb0000000;
5847 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5848 }
5849
5850 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5851 struct intel_link_m_n *m_n)
5852 {
5853 struct drm_device *dev = crtc->base.dev;
5854 struct drm_i915_private *dev_priv = dev->dev_private;
5855 int pipe = crtc->pipe;
5856
5857 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5858 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5859 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5860 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5861 }
5862
5863 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5864 struct intel_link_m_n *m_n,
5865 struct intel_link_m_n *m2_n2)
5866 {
5867 struct drm_device *dev = crtc->base.dev;
5868 struct drm_i915_private *dev_priv = dev->dev_private;
5869 int pipe = crtc->pipe;
5870 enum transcoder transcoder = crtc->config->cpu_transcoder;
5871
5872 if (INTEL_INFO(dev)->gen >= 5) {
5873 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5874 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5875 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5876 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5877 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5878 * for gen < 8) and if DRRS is supported (to make sure the
5879 * registers are not unnecessarily accessed).
5880 */
5881 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5882 crtc->config->has_drrs) {
5883 I915_WRITE(PIPE_DATA_M2(transcoder),
5884 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5885 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5886 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5887 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5888 }
5889 } else {
5890 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5891 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5892 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5893 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5894 }
5895 }
5896
5897 void intel_dp_set_m_n(struct intel_crtc *crtc)
5898 {
5899 if (crtc->config->has_pch_encoder)
5900 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5901 else
5902 intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
5903 &crtc->config->dp_m2_n2);
5904 }
5905
5906 static void vlv_update_pll(struct intel_crtc *crtc,
5907 struct intel_crtc_state *pipe_config)
5908 {
5909 u32 dpll, dpll_md;
5910
5911 /*
5912 * Enable DPIO clock input. We should never disable the reference
5913 * clock for pipe B, since VGA hotplug / manual detection depends
5914 * on it.
5915 */
5916 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5917 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5918 /* We should never disable this, set it here for state tracking */
5919 if (crtc->pipe == PIPE_B)
5920 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5921 dpll |= DPLL_VCO_ENABLE;
5922 pipe_config->dpll_hw_state.dpll = dpll;
5923
5924 dpll_md = (pipe_config->pixel_multiplier - 1)
5925 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5926 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5927 }
5928
5929 static void vlv_prepare_pll(struct intel_crtc *crtc,
5930 const struct intel_crtc_state *pipe_config)
5931 {
5932 struct drm_device *dev = crtc->base.dev;
5933 struct drm_i915_private *dev_priv = dev->dev_private;
5934 int pipe = crtc->pipe;
5935 u32 mdiv;
5936 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5937 u32 coreclk, reg_val;
5938
5939 mutex_lock(&dev_priv->dpio_lock);
5940
5941 bestn = pipe_config->dpll.n;
5942 bestm1 = pipe_config->dpll.m1;
5943 bestm2 = pipe_config->dpll.m2;
5944 bestp1 = pipe_config->dpll.p1;
5945 bestp2 = pipe_config->dpll.p2;
5946
5947 /* See eDP HDMI DPIO driver vbios notes doc */
5948
5949 /* PLL B needs special handling */
5950 if (pipe == PIPE_B)
5951 vlv_pllb_recal_opamp(dev_priv, pipe);
5952
5953 /* Set up Tx target for periodic Rcomp update */
5954 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5955
5956 /* Disable target IRef on PLL */
5957 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5958 reg_val &= 0x00ffffff;
5959 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5960
5961 /* Disable fast lock */
5962 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5963
5964 /* Set idtafcrecal before PLL is enabled */
5965 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5966 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5967 mdiv |= ((bestn << DPIO_N_SHIFT));
5968 mdiv |= (1 << DPIO_K_SHIFT);
5969
5970 /*
5971 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5972 * but we don't support that).
5973 * Note: don't use the DAC post divider as it seems unstable.
5974 */
5975 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5976 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5977
5978 mdiv |= DPIO_ENABLE_CALIBRATION;
5979 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5980
5981 /* Set HBR and RBR LPF coefficients */
5982 if (pipe_config->port_clock == 162000 ||
5983 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5984 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5985 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5986 0x009f0003);
5987 else
5988 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5989 0x00d0000f);
5990
5991 if (pipe_config->has_dp_encoder) {
5992 /* Use SSC source */
5993 if (pipe == PIPE_A)
5994 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5995 0x0df40000);
5996 else
5997 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5998 0x0df70000);
5999 } else { /* HDMI or VGA */
6000 /* Use bend source */
6001 if (pipe == PIPE_A)
6002 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6003 0x0df70000);
6004 else
6005 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6006 0x0df40000);
6007 }
6008
6009 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6010 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6011 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6012 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6013 coreclk |= 0x01000000;
6014 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6015
6016 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6017 mutex_unlock(&dev_priv->dpio_lock);
6018 }
6019
6020 static void chv_update_pll(struct intel_crtc *crtc,
6021 struct intel_crtc_state *pipe_config)
6022 {
6023 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6024 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6025 DPLL_VCO_ENABLE;
6026 if (crtc->pipe != PIPE_A)
6027 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6028
6029 pipe_config->dpll_hw_state.dpll_md =
6030 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6031 }
6032
6033 static void chv_prepare_pll(struct intel_crtc *crtc,
6034 const struct intel_crtc_state *pipe_config)
6035 {
6036 struct drm_device *dev = crtc->base.dev;
6037 struct drm_i915_private *dev_priv = dev->dev_private;
6038 int pipe = crtc->pipe;
6039 int dpll_reg = DPLL(crtc->pipe);
6040 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6041 u32 loopfilter, intcoeff;
6042 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6043 int refclk;
6044
6045 bestn = pipe_config->dpll.n;
6046 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6047 bestm1 = pipe_config->dpll.m1;
6048 bestm2 = pipe_config->dpll.m2 >> 22;
6049 bestp1 = pipe_config->dpll.p1;
6050 bestp2 = pipe_config->dpll.p2;
6051
6052 /*
6053 * Enable Refclk and SSC
6054 */
6055 I915_WRITE(dpll_reg,
6056 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6057
6058 mutex_lock(&dev_priv->dpio_lock);
6059
6060 /* p1 and p2 divider */
6061 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6062 5 << DPIO_CHV_S1_DIV_SHIFT |
6063 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6064 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6065 1 << DPIO_CHV_K_DIV_SHIFT);
6066
6067 /* Feedback post-divider - m2 */
6068 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6069
6070 /* Feedback refclk divider - n and m1 */
6071 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6072 DPIO_CHV_M1_DIV_BY_2 |
6073 1 << DPIO_CHV_N_DIV_SHIFT);
6074
6075 /* M2 fraction division */
6076 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6077
6078 /* M2 fraction division enable */
6079 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6080 DPIO_CHV_FRAC_DIV_EN |
6081 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6082
6083 /* Loop filter */
6084 refclk = i9xx_get_refclk(crtc, 0);
6085 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6086 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6087 if (refclk == 100000)
6088 intcoeff = 11;
6089 else if (refclk == 38400)
6090 intcoeff = 10;
6091 else
6092 intcoeff = 9;
6093 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6094 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6095
6096 /* AFC Recal */
6097 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6098 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6099 DPIO_AFC_RECAL);
6100
6101 mutex_unlock(&dev_priv->dpio_lock);
6102 }
6103
6104 /**
6105 * vlv_force_pll_on - forcibly enable just the PLL
6106 * @dev_priv: i915 private structure
6107 * @pipe: pipe PLL to enable
6108 * @dpll: PLL configuration
6109 *
6110 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6111 * in cases where we need the PLL enabled even when @pipe is not going to
6112 * be enabled.
6113 */
6114 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6115 const struct dpll *dpll)
6116 {
6117 struct intel_crtc *crtc =
6118 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6119 struct intel_crtc_state pipe_config = {
6120 .pixel_multiplier = 1,
6121 .dpll = *dpll,
6122 };
6123
6124 if (IS_CHERRYVIEW(dev)) {
6125 chv_update_pll(crtc, &pipe_config);
6126 chv_prepare_pll(crtc, &pipe_config);
6127 chv_enable_pll(crtc, &pipe_config);
6128 } else {
6129 vlv_update_pll(crtc, &pipe_config);
6130 vlv_prepare_pll(crtc, &pipe_config);
6131 vlv_enable_pll(crtc, &pipe_config);
6132 }
6133 }
6134
6135 /**
6136 * vlv_force_pll_off - forcibly disable just the PLL
6137 * @dev_priv: i915 private structure
6138 * @pipe: pipe PLL to disable
6139 *
6140 * Disable the PLL for @pipe. To be used in cases where we need
6141 * the PLL enabled even when @pipe is not going to be enabled.
6142 */
6143 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6144 {
6145 if (IS_CHERRYVIEW(dev))
6146 chv_disable_pll(to_i915(dev), pipe);
6147 else
6148 vlv_disable_pll(to_i915(dev), pipe);
6149 }
6150
6151 static void i9xx_update_pll(struct intel_crtc *crtc,
6152 struct intel_crtc_state *crtc_state,
6153 intel_clock_t *reduced_clock,
6154 int num_connectors)
6155 {
6156 struct drm_device *dev = crtc->base.dev;
6157 struct drm_i915_private *dev_priv = dev->dev_private;
6158 u32 dpll;
6159 bool is_sdvo;
6160 struct dpll *clock = &crtc_state->dpll;
6161
6162 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6163
6164 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6165 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6166
6167 dpll = DPLL_VGA_MODE_DIS;
6168
6169 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6170 dpll |= DPLLB_MODE_LVDS;
6171 else
6172 dpll |= DPLLB_MODE_DAC_SERIAL;
6173
6174 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6175 dpll |= (crtc_state->pixel_multiplier - 1)
6176 << SDVO_MULTIPLIER_SHIFT_HIRES;
6177 }
6178
6179 if (is_sdvo)
6180 dpll |= DPLL_SDVO_HIGH_SPEED;
6181
6182 if (crtc_state->has_dp_encoder)
6183 dpll |= DPLL_SDVO_HIGH_SPEED;
6184
6185 /* compute bitmask from p1 value */
6186 if (IS_PINEVIEW(dev))
6187 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6188 else {
6189 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6190 if (IS_G4X(dev) && reduced_clock)
6191 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6192 }
6193 switch (clock->p2) {
6194 case 5:
6195 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6196 break;
6197 case 7:
6198 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6199 break;
6200 case 10:
6201 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6202 break;
6203 case 14:
6204 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6205 break;
6206 }
6207 if (INTEL_INFO(dev)->gen >= 4)
6208 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6209
6210 if (crtc_state->sdvo_tv_clock)
6211 dpll |= PLL_REF_INPUT_TVCLKINBC;
6212 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6213 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6214 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6215 else
6216 dpll |= PLL_REF_INPUT_DREFCLK;
6217
6218 dpll |= DPLL_VCO_ENABLE;
6219 crtc_state->dpll_hw_state.dpll = dpll;
6220
6221 if (INTEL_INFO(dev)->gen >= 4) {
6222 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6223 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6224 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6225 }
6226 }
6227
6228 static void i8xx_update_pll(struct intel_crtc *crtc,
6229 struct intel_crtc_state *crtc_state,
6230 intel_clock_t *reduced_clock,
6231 int num_connectors)
6232 {
6233 struct drm_device *dev = crtc->base.dev;
6234 struct drm_i915_private *dev_priv = dev->dev_private;
6235 u32 dpll;
6236 struct dpll *clock = &crtc_state->dpll;
6237
6238 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6239
6240 dpll = DPLL_VGA_MODE_DIS;
6241
6242 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6243 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6244 } else {
6245 if (clock->p1 == 2)
6246 dpll |= PLL_P1_DIVIDE_BY_TWO;
6247 else
6248 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6249 if (clock->p2 == 4)
6250 dpll |= PLL_P2_DIVIDE_BY_4;
6251 }
6252
6253 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6254 dpll |= DPLL_DVO_2X_MODE;
6255
6256 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6257 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6258 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6259 else
6260 dpll |= PLL_REF_INPUT_DREFCLK;
6261
6262 dpll |= DPLL_VCO_ENABLE;
6263 crtc_state->dpll_hw_state.dpll = dpll;
6264 }
6265
6266 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6267 {
6268 struct drm_device *dev = intel_crtc->base.dev;
6269 struct drm_i915_private *dev_priv = dev->dev_private;
6270 enum pipe pipe = intel_crtc->pipe;
6271 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6272 struct drm_display_mode *adjusted_mode =
6273 &intel_crtc->config->base.adjusted_mode;
6274 uint32_t crtc_vtotal, crtc_vblank_end;
6275 int vsyncshift = 0;
6276
6277 /* We need to be careful not to changed the adjusted mode, for otherwise
6278 * the hw state checker will get angry at the mismatch. */
6279 crtc_vtotal = adjusted_mode->crtc_vtotal;
6280 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6281
6282 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6283 /* the chip adds 2 halflines automatically */
6284 crtc_vtotal -= 1;
6285 crtc_vblank_end -= 1;
6286
6287 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6288 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6289 else
6290 vsyncshift = adjusted_mode->crtc_hsync_start -
6291 adjusted_mode->crtc_htotal / 2;
6292 if (vsyncshift < 0)
6293 vsyncshift += adjusted_mode->crtc_htotal;
6294 }
6295
6296 if (INTEL_INFO(dev)->gen > 3)
6297 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6298
6299 I915_WRITE(HTOTAL(cpu_transcoder),
6300 (adjusted_mode->crtc_hdisplay - 1) |
6301 ((adjusted_mode->crtc_htotal - 1) << 16));
6302 I915_WRITE(HBLANK(cpu_transcoder),
6303 (adjusted_mode->crtc_hblank_start - 1) |
6304 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6305 I915_WRITE(HSYNC(cpu_transcoder),
6306 (adjusted_mode->crtc_hsync_start - 1) |
6307 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6308
6309 I915_WRITE(VTOTAL(cpu_transcoder),
6310 (adjusted_mode->crtc_vdisplay - 1) |
6311 ((crtc_vtotal - 1) << 16));
6312 I915_WRITE(VBLANK(cpu_transcoder),
6313 (adjusted_mode->crtc_vblank_start - 1) |
6314 ((crtc_vblank_end - 1) << 16));
6315 I915_WRITE(VSYNC(cpu_transcoder),
6316 (adjusted_mode->crtc_vsync_start - 1) |
6317 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6318
6319 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6320 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6321 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6322 * bits. */
6323 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6324 (pipe == PIPE_B || pipe == PIPE_C))
6325 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6326
6327 /* pipesrc controls the size that is scaled from, which should
6328 * always be the user's requested size.
6329 */
6330 I915_WRITE(PIPESRC(pipe),
6331 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6332 (intel_crtc->config->pipe_src_h - 1));
6333 }
6334
6335 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6336 struct intel_crtc_state *pipe_config)
6337 {
6338 struct drm_device *dev = crtc->base.dev;
6339 struct drm_i915_private *dev_priv = dev->dev_private;
6340 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6341 uint32_t tmp;
6342
6343 tmp = I915_READ(HTOTAL(cpu_transcoder));
6344 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6345 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6346 tmp = I915_READ(HBLANK(cpu_transcoder));
6347 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6348 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6349 tmp = I915_READ(HSYNC(cpu_transcoder));
6350 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6351 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6352
6353 tmp = I915_READ(VTOTAL(cpu_transcoder));
6354 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6355 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6356 tmp = I915_READ(VBLANK(cpu_transcoder));
6357 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6358 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6359 tmp = I915_READ(VSYNC(cpu_transcoder));
6360 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6361 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6362
6363 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6364 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6365 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6366 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6367 }
6368
6369 tmp = I915_READ(PIPESRC(crtc->pipe));
6370 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6371 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6372
6373 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6374 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6375 }
6376
6377 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6378 struct intel_crtc_state *pipe_config)
6379 {
6380 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6381 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6382 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6383 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6384
6385 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6386 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6387 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6388 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6389
6390 mode->flags = pipe_config->base.adjusted_mode.flags;
6391
6392 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6393 mode->flags |= pipe_config->base.adjusted_mode.flags;
6394 }
6395
6396 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6397 {
6398 struct drm_device *dev = intel_crtc->base.dev;
6399 struct drm_i915_private *dev_priv = dev->dev_private;
6400 uint32_t pipeconf;
6401
6402 pipeconf = 0;
6403
6404 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6405 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6406 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6407
6408 if (intel_crtc->config->double_wide)
6409 pipeconf |= PIPECONF_DOUBLE_WIDE;
6410
6411 /* only g4x and later have fancy bpc/dither controls */
6412 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6413 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6414 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6415 pipeconf |= PIPECONF_DITHER_EN |
6416 PIPECONF_DITHER_TYPE_SP;
6417
6418 switch (intel_crtc->config->pipe_bpp) {
6419 case 18:
6420 pipeconf |= PIPECONF_6BPC;
6421 break;
6422 case 24:
6423 pipeconf |= PIPECONF_8BPC;
6424 break;
6425 case 30:
6426 pipeconf |= PIPECONF_10BPC;
6427 break;
6428 default:
6429 /* Case prevented by intel_choose_pipe_bpp_dither. */
6430 BUG();
6431 }
6432 }
6433
6434 if (HAS_PIPE_CXSR(dev)) {
6435 if (intel_crtc->lowfreq_avail) {
6436 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6437 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6438 } else {
6439 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6440 }
6441 }
6442
6443 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6444 if (INTEL_INFO(dev)->gen < 4 ||
6445 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6446 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6447 else
6448 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6449 } else
6450 pipeconf |= PIPECONF_PROGRESSIVE;
6451
6452 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6453 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6454
6455 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6456 POSTING_READ(PIPECONF(intel_crtc->pipe));
6457 }
6458
6459 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6460 struct intel_crtc_state *crtc_state)
6461 {
6462 struct drm_device *dev = crtc->base.dev;
6463 struct drm_i915_private *dev_priv = dev->dev_private;
6464 int refclk, num_connectors = 0;
6465 intel_clock_t clock, reduced_clock;
6466 bool ok, has_reduced_clock = false;
6467 bool is_lvds = false, is_dsi = false;
6468 struct intel_encoder *encoder;
6469 const intel_limit_t *limit;
6470
6471 for_each_intel_encoder(dev, encoder) {
6472 if (encoder->new_crtc != crtc)
6473 continue;
6474
6475 switch (encoder->type) {
6476 case INTEL_OUTPUT_LVDS:
6477 is_lvds = true;
6478 break;
6479 case INTEL_OUTPUT_DSI:
6480 is_dsi = true;
6481 break;
6482 default:
6483 break;
6484 }
6485
6486 num_connectors++;
6487 }
6488
6489 if (is_dsi)
6490 return 0;
6491
6492 if (!crtc_state->clock_set) {
6493 refclk = i9xx_get_refclk(crtc, num_connectors);
6494
6495 /*
6496 * Returns a set of divisors for the desired target clock with
6497 * the given refclk, or FALSE. The returned values represent
6498 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6499 * 2) / p1 / p2.
6500 */
6501 limit = intel_limit(crtc, refclk);
6502 ok = dev_priv->display.find_dpll(limit, crtc,
6503 crtc_state->port_clock,
6504 refclk, NULL, &clock);
6505 if (!ok) {
6506 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6507 return -EINVAL;
6508 }
6509
6510 if (is_lvds && dev_priv->lvds_downclock_avail) {
6511 /*
6512 * Ensure we match the reduced clock's P to the target
6513 * clock. If the clocks don't match, we can't switch
6514 * the display clock by using the FP0/FP1. In such case
6515 * we will disable the LVDS downclock feature.
6516 */
6517 has_reduced_clock =
6518 dev_priv->display.find_dpll(limit, crtc,
6519 dev_priv->lvds_downclock,
6520 refclk, &clock,
6521 &reduced_clock);
6522 }
6523 /* Compat-code for transition, will disappear. */
6524 crtc_state->dpll.n = clock.n;
6525 crtc_state->dpll.m1 = clock.m1;
6526 crtc_state->dpll.m2 = clock.m2;
6527 crtc_state->dpll.p1 = clock.p1;
6528 crtc_state->dpll.p2 = clock.p2;
6529 }
6530
6531 if (IS_GEN2(dev)) {
6532 i8xx_update_pll(crtc, crtc_state,
6533 has_reduced_clock ? &reduced_clock : NULL,
6534 num_connectors);
6535 } else if (IS_CHERRYVIEW(dev)) {
6536 chv_update_pll(crtc, crtc_state);
6537 } else if (IS_VALLEYVIEW(dev)) {
6538 vlv_update_pll(crtc, crtc_state);
6539 } else {
6540 i9xx_update_pll(crtc, crtc_state,
6541 has_reduced_clock ? &reduced_clock : NULL,
6542 num_connectors);
6543 }
6544
6545 return 0;
6546 }
6547
6548 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6549 struct intel_crtc_state *pipe_config)
6550 {
6551 struct drm_device *dev = crtc->base.dev;
6552 struct drm_i915_private *dev_priv = dev->dev_private;
6553 uint32_t tmp;
6554
6555 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6556 return;
6557
6558 tmp = I915_READ(PFIT_CONTROL);
6559 if (!(tmp & PFIT_ENABLE))
6560 return;
6561
6562 /* Check whether the pfit is attached to our pipe. */
6563 if (INTEL_INFO(dev)->gen < 4) {
6564 if (crtc->pipe != PIPE_B)
6565 return;
6566 } else {
6567 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6568 return;
6569 }
6570
6571 pipe_config->gmch_pfit.control = tmp;
6572 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6573 if (INTEL_INFO(dev)->gen < 5)
6574 pipe_config->gmch_pfit.lvds_border_bits =
6575 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6576 }
6577
6578 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6579 struct intel_crtc_state *pipe_config)
6580 {
6581 struct drm_device *dev = crtc->base.dev;
6582 struct drm_i915_private *dev_priv = dev->dev_private;
6583 int pipe = pipe_config->cpu_transcoder;
6584 intel_clock_t clock;
6585 u32 mdiv;
6586 int refclk = 100000;
6587
6588 /* In case of MIPI DPLL will not even be used */
6589 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6590 return;
6591
6592 mutex_lock(&dev_priv->dpio_lock);
6593 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6594 mutex_unlock(&dev_priv->dpio_lock);
6595
6596 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6597 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6598 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6599 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6600 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6601
6602 vlv_clock(refclk, &clock);
6603
6604 /* clock.dot is the fast clock */
6605 pipe_config->port_clock = clock.dot / 5;
6606 }
6607
6608 static void
6609 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6610 struct intel_initial_plane_config *plane_config)
6611 {
6612 struct drm_device *dev = crtc->base.dev;
6613 struct drm_i915_private *dev_priv = dev->dev_private;
6614 u32 val, base, offset;
6615 int pipe = crtc->pipe, plane = crtc->plane;
6616 int fourcc, pixel_format;
6617 int aligned_height;
6618 struct drm_framebuffer *fb;
6619 struct intel_framebuffer *intel_fb;
6620
6621 val = I915_READ(DSPCNTR(plane));
6622 if (!(val & DISPLAY_PLANE_ENABLE))
6623 return;
6624
6625 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6626 if (!intel_fb) {
6627 DRM_DEBUG_KMS("failed to alloc fb\n");
6628 return;
6629 }
6630
6631 fb = &intel_fb->base;
6632
6633 if (INTEL_INFO(dev)->gen >= 4) {
6634 if (val & DISPPLANE_TILED) {
6635 plane_config->tiling = I915_TILING_X;
6636 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6637 }
6638 }
6639
6640 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6641 fourcc = i9xx_format_to_fourcc(pixel_format);
6642 fb->pixel_format = fourcc;
6643 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6644
6645 if (INTEL_INFO(dev)->gen >= 4) {
6646 if (plane_config->tiling)
6647 offset = I915_READ(DSPTILEOFF(plane));
6648 else
6649 offset = I915_READ(DSPLINOFF(plane));
6650 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6651 } else {
6652 base = I915_READ(DSPADDR(plane));
6653 }
6654 plane_config->base = base;
6655
6656 val = I915_READ(PIPESRC(pipe));
6657 fb->width = ((val >> 16) & 0xfff) + 1;
6658 fb->height = ((val >> 0) & 0xfff) + 1;
6659
6660 val = I915_READ(DSPSTRIDE(pipe));
6661 fb->pitches[0] = val & 0xffffffc0;
6662
6663 aligned_height = intel_fb_align_height(dev, fb->height,
6664 fb->pixel_format,
6665 fb->modifier[0]);
6666
6667 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
6668
6669 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6670 pipe_name(pipe), plane, fb->width, fb->height,
6671 fb->bits_per_pixel, base, fb->pitches[0],
6672 plane_config->size);
6673
6674 plane_config->fb = intel_fb;
6675 }
6676
6677 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6678 struct intel_crtc_state *pipe_config)
6679 {
6680 struct drm_device *dev = crtc->base.dev;
6681 struct drm_i915_private *dev_priv = dev->dev_private;
6682 int pipe = pipe_config->cpu_transcoder;
6683 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6684 intel_clock_t clock;
6685 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6686 int refclk = 100000;
6687
6688 mutex_lock(&dev_priv->dpio_lock);
6689 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6690 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6691 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6692 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6693 mutex_unlock(&dev_priv->dpio_lock);
6694
6695 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6696 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6697 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6698 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6699 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6700
6701 chv_clock(refclk, &clock);
6702
6703 /* clock.dot is the fast clock */
6704 pipe_config->port_clock = clock.dot / 5;
6705 }
6706
6707 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6708 struct intel_crtc_state *pipe_config)
6709 {
6710 struct drm_device *dev = crtc->base.dev;
6711 struct drm_i915_private *dev_priv = dev->dev_private;
6712 uint32_t tmp;
6713
6714 if (!intel_display_power_is_enabled(dev_priv,
6715 POWER_DOMAIN_PIPE(crtc->pipe)))
6716 return false;
6717
6718 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6719 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6720
6721 tmp = I915_READ(PIPECONF(crtc->pipe));
6722 if (!(tmp & PIPECONF_ENABLE))
6723 return false;
6724
6725 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6726 switch (tmp & PIPECONF_BPC_MASK) {
6727 case PIPECONF_6BPC:
6728 pipe_config->pipe_bpp = 18;
6729 break;
6730 case PIPECONF_8BPC:
6731 pipe_config->pipe_bpp = 24;
6732 break;
6733 case PIPECONF_10BPC:
6734 pipe_config->pipe_bpp = 30;
6735 break;
6736 default:
6737 break;
6738 }
6739 }
6740
6741 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6742 pipe_config->limited_color_range = true;
6743
6744 if (INTEL_INFO(dev)->gen < 4)
6745 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6746
6747 intel_get_pipe_timings(crtc, pipe_config);
6748
6749 i9xx_get_pfit_config(crtc, pipe_config);
6750
6751 if (INTEL_INFO(dev)->gen >= 4) {
6752 tmp = I915_READ(DPLL_MD(crtc->pipe));
6753 pipe_config->pixel_multiplier =
6754 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6755 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6756 pipe_config->dpll_hw_state.dpll_md = tmp;
6757 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6758 tmp = I915_READ(DPLL(crtc->pipe));
6759 pipe_config->pixel_multiplier =
6760 ((tmp & SDVO_MULTIPLIER_MASK)
6761 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6762 } else {
6763 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6764 * port and will be fixed up in the encoder->get_config
6765 * function. */
6766 pipe_config->pixel_multiplier = 1;
6767 }
6768 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6769 if (!IS_VALLEYVIEW(dev)) {
6770 /*
6771 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6772 * on 830. Filter it out here so that we don't
6773 * report errors due to that.
6774 */
6775 if (IS_I830(dev))
6776 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6777
6778 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6779 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6780 } else {
6781 /* Mask out read-only status bits. */
6782 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6783 DPLL_PORTC_READY_MASK |
6784 DPLL_PORTB_READY_MASK);
6785 }
6786
6787 if (IS_CHERRYVIEW(dev))
6788 chv_crtc_clock_get(crtc, pipe_config);
6789 else if (IS_VALLEYVIEW(dev))
6790 vlv_crtc_clock_get(crtc, pipe_config);
6791 else
6792 i9xx_crtc_clock_get(crtc, pipe_config);
6793
6794 return true;
6795 }
6796
6797 static void ironlake_init_pch_refclk(struct drm_device *dev)
6798 {
6799 struct drm_i915_private *dev_priv = dev->dev_private;
6800 struct intel_encoder *encoder;
6801 u32 val, final;
6802 bool has_lvds = false;
6803 bool has_cpu_edp = false;
6804 bool has_panel = false;
6805 bool has_ck505 = false;
6806 bool can_ssc = false;
6807
6808 /* We need to take the global config into account */
6809 for_each_intel_encoder(dev, encoder) {
6810 switch (encoder->type) {
6811 case INTEL_OUTPUT_LVDS:
6812 has_panel = true;
6813 has_lvds = true;
6814 break;
6815 case INTEL_OUTPUT_EDP:
6816 has_panel = true;
6817 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6818 has_cpu_edp = true;
6819 break;
6820 default:
6821 break;
6822 }
6823 }
6824
6825 if (HAS_PCH_IBX(dev)) {
6826 has_ck505 = dev_priv->vbt.display_clock_mode;
6827 can_ssc = has_ck505;
6828 } else {
6829 has_ck505 = false;
6830 can_ssc = true;
6831 }
6832
6833 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6834 has_panel, has_lvds, has_ck505);
6835
6836 /* Ironlake: try to setup display ref clock before DPLL
6837 * enabling. This is only under driver's control after
6838 * PCH B stepping, previous chipset stepping should be
6839 * ignoring this setting.
6840 */
6841 val = I915_READ(PCH_DREF_CONTROL);
6842
6843 /* As we must carefully and slowly disable/enable each source in turn,
6844 * compute the final state we want first and check if we need to
6845 * make any changes at all.
6846 */
6847 final = val;
6848 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6849 if (has_ck505)
6850 final |= DREF_NONSPREAD_CK505_ENABLE;
6851 else
6852 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6853
6854 final &= ~DREF_SSC_SOURCE_MASK;
6855 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6856 final &= ~DREF_SSC1_ENABLE;
6857
6858 if (has_panel) {
6859 final |= DREF_SSC_SOURCE_ENABLE;
6860
6861 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6862 final |= DREF_SSC1_ENABLE;
6863
6864 if (has_cpu_edp) {
6865 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6866 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6867 else
6868 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6869 } else
6870 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6871 } else {
6872 final |= DREF_SSC_SOURCE_DISABLE;
6873 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6874 }
6875
6876 if (final == val)
6877 return;
6878
6879 /* Always enable nonspread source */
6880 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6881
6882 if (has_ck505)
6883 val |= DREF_NONSPREAD_CK505_ENABLE;
6884 else
6885 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6886
6887 if (has_panel) {
6888 val &= ~DREF_SSC_SOURCE_MASK;
6889 val |= DREF_SSC_SOURCE_ENABLE;
6890
6891 /* SSC must be turned on before enabling the CPU output */
6892 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6893 DRM_DEBUG_KMS("Using SSC on panel\n");
6894 val |= DREF_SSC1_ENABLE;
6895 } else
6896 val &= ~DREF_SSC1_ENABLE;
6897
6898 /* Get SSC going before enabling the outputs */
6899 I915_WRITE(PCH_DREF_CONTROL, val);
6900 POSTING_READ(PCH_DREF_CONTROL);
6901 udelay(200);
6902
6903 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6904
6905 /* Enable CPU source on CPU attached eDP */
6906 if (has_cpu_edp) {
6907 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6908 DRM_DEBUG_KMS("Using SSC on eDP\n");
6909 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6910 } else
6911 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6912 } else
6913 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6914
6915 I915_WRITE(PCH_DREF_CONTROL, val);
6916 POSTING_READ(PCH_DREF_CONTROL);
6917 udelay(200);
6918 } else {
6919 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6920
6921 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6922
6923 /* Turn off CPU output */
6924 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6925
6926 I915_WRITE(PCH_DREF_CONTROL, val);
6927 POSTING_READ(PCH_DREF_CONTROL);
6928 udelay(200);
6929
6930 /* Turn off the SSC source */
6931 val &= ~DREF_SSC_SOURCE_MASK;
6932 val |= DREF_SSC_SOURCE_DISABLE;
6933
6934 /* Turn off SSC1 */
6935 val &= ~DREF_SSC1_ENABLE;
6936
6937 I915_WRITE(PCH_DREF_CONTROL, val);
6938 POSTING_READ(PCH_DREF_CONTROL);
6939 udelay(200);
6940 }
6941
6942 BUG_ON(val != final);
6943 }
6944
6945 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6946 {
6947 uint32_t tmp;
6948
6949 tmp = I915_READ(SOUTH_CHICKEN2);
6950 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6951 I915_WRITE(SOUTH_CHICKEN2, tmp);
6952
6953 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6954 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6955 DRM_ERROR("FDI mPHY reset assert timeout\n");
6956
6957 tmp = I915_READ(SOUTH_CHICKEN2);
6958 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6959 I915_WRITE(SOUTH_CHICKEN2, tmp);
6960
6961 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6962 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6963 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6964 }
6965
6966 /* WaMPhyProgramming:hsw */
6967 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6968 {
6969 uint32_t tmp;
6970
6971 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6972 tmp &= ~(0xFF << 24);
6973 tmp |= (0x12 << 24);
6974 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6975
6976 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6977 tmp |= (1 << 11);
6978 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6979
6980 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6981 tmp |= (1 << 11);
6982 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6983
6984 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6985 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6986 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6987
6988 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6989 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6990 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6991
6992 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6993 tmp &= ~(7 << 13);
6994 tmp |= (5 << 13);
6995 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6996
6997 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6998 tmp &= ~(7 << 13);
6999 tmp |= (5 << 13);
7000 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7001
7002 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7003 tmp &= ~0xFF;
7004 tmp |= 0x1C;
7005 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7006
7007 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7008 tmp &= ~0xFF;
7009 tmp |= 0x1C;
7010 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7011
7012 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7013 tmp &= ~(0xFF << 16);
7014 tmp |= (0x1C << 16);
7015 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7016
7017 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7018 tmp &= ~(0xFF << 16);
7019 tmp |= (0x1C << 16);
7020 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7021
7022 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7023 tmp |= (1 << 27);
7024 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7025
7026 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7027 tmp |= (1 << 27);
7028 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7029
7030 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7031 tmp &= ~(0xF << 28);
7032 tmp |= (4 << 28);
7033 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7034
7035 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7036 tmp &= ~(0xF << 28);
7037 tmp |= (4 << 28);
7038 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7039 }
7040
7041 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7042 * Programming" based on the parameters passed:
7043 * - Sequence to enable CLKOUT_DP
7044 * - Sequence to enable CLKOUT_DP without spread
7045 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7046 */
7047 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7048 bool with_fdi)
7049 {
7050 struct drm_i915_private *dev_priv = dev->dev_private;
7051 uint32_t reg, tmp;
7052
7053 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7054 with_spread = true;
7055 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7056 with_fdi, "LP PCH doesn't have FDI\n"))
7057 with_fdi = false;
7058
7059 mutex_lock(&dev_priv->dpio_lock);
7060
7061 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7062 tmp &= ~SBI_SSCCTL_DISABLE;
7063 tmp |= SBI_SSCCTL_PATHALT;
7064 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7065
7066 udelay(24);
7067
7068 if (with_spread) {
7069 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7070 tmp &= ~SBI_SSCCTL_PATHALT;
7071 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7072
7073 if (with_fdi) {
7074 lpt_reset_fdi_mphy(dev_priv);
7075 lpt_program_fdi_mphy(dev_priv);
7076 }
7077 }
7078
7079 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7080 SBI_GEN0 : SBI_DBUFF0;
7081 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7082 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7083 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7084
7085 mutex_unlock(&dev_priv->dpio_lock);
7086 }
7087
7088 /* Sequence to disable CLKOUT_DP */
7089 static void lpt_disable_clkout_dp(struct drm_device *dev)
7090 {
7091 struct drm_i915_private *dev_priv = dev->dev_private;
7092 uint32_t reg, tmp;
7093
7094 mutex_lock(&dev_priv->dpio_lock);
7095
7096 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7097 SBI_GEN0 : SBI_DBUFF0;
7098 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7099 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7100 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7101
7102 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7103 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7104 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7105 tmp |= SBI_SSCCTL_PATHALT;
7106 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7107 udelay(32);
7108 }
7109 tmp |= SBI_SSCCTL_DISABLE;
7110 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7111 }
7112
7113 mutex_unlock(&dev_priv->dpio_lock);
7114 }
7115
7116 static void lpt_init_pch_refclk(struct drm_device *dev)
7117 {
7118 struct intel_encoder *encoder;
7119 bool has_vga = false;
7120
7121 for_each_intel_encoder(dev, encoder) {
7122 switch (encoder->type) {
7123 case INTEL_OUTPUT_ANALOG:
7124 has_vga = true;
7125 break;
7126 default:
7127 break;
7128 }
7129 }
7130
7131 if (has_vga)
7132 lpt_enable_clkout_dp(dev, true, true);
7133 else
7134 lpt_disable_clkout_dp(dev);
7135 }
7136
7137 /*
7138 * Initialize reference clocks when the driver loads
7139 */
7140 void intel_init_pch_refclk(struct drm_device *dev)
7141 {
7142 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7143 ironlake_init_pch_refclk(dev);
7144 else if (HAS_PCH_LPT(dev))
7145 lpt_init_pch_refclk(dev);
7146 }
7147
7148 static int ironlake_get_refclk(struct drm_crtc *crtc)
7149 {
7150 struct drm_device *dev = crtc->dev;
7151 struct drm_i915_private *dev_priv = dev->dev_private;
7152 struct intel_encoder *encoder;
7153 int num_connectors = 0;
7154 bool is_lvds = false;
7155
7156 for_each_intel_encoder(dev, encoder) {
7157 if (encoder->new_crtc != to_intel_crtc(crtc))
7158 continue;
7159
7160 switch (encoder->type) {
7161 case INTEL_OUTPUT_LVDS:
7162 is_lvds = true;
7163 break;
7164 default:
7165 break;
7166 }
7167 num_connectors++;
7168 }
7169
7170 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7171 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7172 dev_priv->vbt.lvds_ssc_freq);
7173 return dev_priv->vbt.lvds_ssc_freq;
7174 }
7175
7176 return 120000;
7177 }
7178
7179 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7180 {
7181 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7183 int pipe = intel_crtc->pipe;
7184 uint32_t val;
7185
7186 val = 0;
7187
7188 switch (intel_crtc->config->pipe_bpp) {
7189 case 18:
7190 val |= PIPECONF_6BPC;
7191 break;
7192 case 24:
7193 val |= PIPECONF_8BPC;
7194 break;
7195 case 30:
7196 val |= PIPECONF_10BPC;
7197 break;
7198 case 36:
7199 val |= PIPECONF_12BPC;
7200 break;
7201 default:
7202 /* Case prevented by intel_choose_pipe_bpp_dither. */
7203 BUG();
7204 }
7205
7206 if (intel_crtc->config->dither)
7207 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7208
7209 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7210 val |= PIPECONF_INTERLACED_ILK;
7211 else
7212 val |= PIPECONF_PROGRESSIVE;
7213
7214 if (intel_crtc->config->limited_color_range)
7215 val |= PIPECONF_COLOR_RANGE_SELECT;
7216
7217 I915_WRITE(PIPECONF(pipe), val);
7218 POSTING_READ(PIPECONF(pipe));
7219 }
7220
7221 /*
7222 * Set up the pipe CSC unit.
7223 *
7224 * Currently only full range RGB to limited range RGB conversion
7225 * is supported, but eventually this should handle various
7226 * RGB<->YCbCr scenarios as well.
7227 */
7228 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7229 {
7230 struct drm_device *dev = crtc->dev;
7231 struct drm_i915_private *dev_priv = dev->dev_private;
7232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7233 int pipe = intel_crtc->pipe;
7234 uint16_t coeff = 0x7800; /* 1.0 */
7235
7236 /*
7237 * TODO: Check what kind of values actually come out of the pipe
7238 * with these coeff/postoff values and adjust to get the best
7239 * accuracy. Perhaps we even need to take the bpc value into
7240 * consideration.
7241 */
7242
7243 if (intel_crtc->config->limited_color_range)
7244 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7245
7246 /*
7247 * GY/GU and RY/RU should be the other way around according
7248 * to BSpec, but reality doesn't agree. Just set them up in
7249 * a way that results in the correct picture.
7250 */
7251 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7252 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7253
7254 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7255 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7256
7257 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7258 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7259
7260 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7261 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7262 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7263
7264 if (INTEL_INFO(dev)->gen > 6) {
7265 uint16_t postoff = 0;
7266
7267 if (intel_crtc->config->limited_color_range)
7268 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7269
7270 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7271 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7272 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7273
7274 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7275 } else {
7276 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7277
7278 if (intel_crtc->config->limited_color_range)
7279 mode |= CSC_BLACK_SCREEN_OFFSET;
7280
7281 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7282 }
7283 }
7284
7285 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7286 {
7287 struct drm_device *dev = crtc->dev;
7288 struct drm_i915_private *dev_priv = dev->dev_private;
7289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7290 enum pipe pipe = intel_crtc->pipe;
7291 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7292 uint32_t val;
7293
7294 val = 0;
7295
7296 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7297 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7298
7299 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7300 val |= PIPECONF_INTERLACED_ILK;
7301 else
7302 val |= PIPECONF_PROGRESSIVE;
7303
7304 I915_WRITE(PIPECONF(cpu_transcoder), val);
7305 POSTING_READ(PIPECONF(cpu_transcoder));
7306
7307 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7308 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7309
7310 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7311 val = 0;
7312
7313 switch (intel_crtc->config->pipe_bpp) {
7314 case 18:
7315 val |= PIPEMISC_DITHER_6_BPC;
7316 break;
7317 case 24:
7318 val |= PIPEMISC_DITHER_8_BPC;
7319 break;
7320 case 30:
7321 val |= PIPEMISC_DITHER_10_BPC;
7322 break;
7323 case 36:
7324 val |= PIPEMISC_DITHER_12_BPC;
7325 break;
7326 default:
7327 /* Case prevented by pipe_config_set_bpp. */
7328 BUG();
7329 }
7330
7331 if (intel_crtc->config->dither)
7332 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7333
7334 I915_WRITE(PIPEMISC(pipe), val);
7335 }
7336 }
7337
7338 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7339 struct intel_crtc_state *crtc_state,
7340 intel_clock_t *clock,
7341 bool *has_reduced_clock,
7342 intel_clock_t *reduced_clock)
7343 {
7344 struct drm_device *dev = crtc->dev;
7345 struct drm_i915_private *dev_priv = dev->dev_private;
7346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7347 int refclk;
7348 const intel_limit_t *limit;
7349 bool ret, is_lvds = false;
7350
7351 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7352
7353 refclk = ironlake_get_refclk(crtc);
7354
7355 /*
7356 * Returns a set of divisors for the desired target clock with the given
7357 * refclk, or FALSE. The returned values represent the clock equation:
7358 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7359 */
7360 limit = intel_limit(intel_crtc, refclk);
7361 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7362 crtc_state->port_clock,
7363 refclk, NULL, clock);
7364 if (!ret)
7365 return false;
7366
7367 if (is_lvds && dev_priv->lvds_downclock_avail) {
7368 /*
7369 * Ensure we match the reduced clock's P to the target clock.
7370 * If the clocks don't match, we can't switch the display clock
7371 * by using the FP0/FP1. In such case we will disable the LVDS
7372 * downclock feature.
7373 */
7374 *has_reduced_clock =
7375 dev_priv->display.find_dpll(limit, intel_crtc,
7376 dev_priv->lvds_downclock,
7377 refclk, clock,
7378 reduced_clock);
7379 }
7380
7381 return true;
7382 }
7383
7384 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7385 {
7386 /*
7387 * Account for spread spectrum to avoid
7388 * oversubscribing the link. Max center spread
7389 * is 2.5%; use 5% for safety's sake.
7390 */
7391 u32 bps = target_clock * bpp * 21 / 20;
7392 return DIV_ROUND_UP(bps, link_bw * 8);
7393 }
7394
7395 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7396 {
7397 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7398 }
7399
7400 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7401 struct intel_crtc_state *crtc_state,
7402 u32 *fp,
7403 intel_clock_t *reduced_clock, u32 *fp2)
7404 {
7405 struct drm_crtc *crtc = &intel_crtc->base;
7406 struct drm_device *dev = crtc->dev;
7407 struct drm_i915_private *dev_priv = dev->dev_private;
7408 struct intel_encoder *intel_encoder;
7409 uint32_t dpll;
7410 int factor, num_connectors = 0;
7411 bool is_lvds = false, is_sdvo = false;
7412
7413 for_each_intel_encoder(dev, intel_encoder) {
7414 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7415 continue;
7416
7417 switch (intel_encoder->type) {
7418 case INTEL_OUTPUT_LVDS:
7419 is_lvds = true;
7420 break;
7421 case INTEL_OUTPUT_SDVO:
7422 case INTEL_OUTPUT_HDMI:
7423 is_sdvo = true;
7424 break;
7425 default:
7426 break;
7427 }
7428
7429 num_connectors++;
7430 }
7431
7432 /* Enable autotuning of the PLL clock (if permissible) */
7433 factor = 21;
7434 if (is_lvds) {
7435 if ((intel_panel_use_ssc(dev_priv) &&
7436 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7437 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7438 factor = 25;
7439 } else if (crtc_state->sdvo_tv_clock)
7440 factor = 20;
7441
7442 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7443 *fp |= FP_CB_TUNE;
7444
7445 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7446 *fp2 |= FP_CB_TUNE;
7447
7448 dpll = 0;
7449
7450 if (is_lvds)
7451 dpll |= DPLLB_MODE_LVDS;
7452 else
7453 dpll |= DPLLB_MODE_DAC_SERIAL;
7454
7455 dpll |= (crtc_state->pixel_multiplier - 1)
7456 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7457
7458 if (is_sdvo)
7459 dpll |= DPLL_SDVO_HIGH_SPEED;
7460 if (crtc_state->has_dp_encoder)
7461 dpll |= DPLL_SDVO_HIGH_SPEED;
7462
7463 /* compute bitmask from p1 value */
7464 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7465 /* also FPA1 */
7466 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7467
7468 switch (crtc_state->dpll.p2) {
7469 case 5:
7470 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7471 break;
7472 case 7:
7473 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7474 break;
7475 case 10:
7476 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7477 break;
7478 case 14:
7479 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7480 break;
7481 }
7482
7483 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7484 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7485 else
7486 dpll |= PLL_REF_INPUT_DREFCLK;
7487
7488 return dpll | DPLL_VCO_ENABLE;
7489 }
7490
7491 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7492 struct intel_crtc_state *crtc_state)
7493 {
7494 struct drm_device *dev = crtc->base.dev;
7495 intel_clock_t clock, reduced_clock;
7496 u32 dpll = 0, fp = 0, fp2 = 0;
7497 bool ok, has_reduced_clock = false;
7498 bool is_lvds = false;
7499 struct intel_shared_dpll *pll;
7500
7501 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7502
7503 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7504 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7505
7506 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7507 &has_reduced_clock, &reduced_clock);
7508 if (!ok && !crtc_state->clock_set) {
7509 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7510 return -EINVAL;
7511 }
7512 /* Compat-code for transition, will disappear. */
7513 if (!crtc_state->clock_set) {
7514 crtc_state->dpll.n = clock.n;
7515 crtc_state->dpll.m1 = clock.m1;
7516 crtc_state->dpll.m2 = clock.m2;
7517 crtc_state->dpll.p1 = clock.p1;
7518 crtc_state->dpll.p2 = clock.p2;
7519 }
7520
7521 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7522 if (crtc_state->has_pch_encoder) {
7523 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7524 if (has_reduced_clock)
7525 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7526
7527 dpll = ironlake_compute_dpll(crtc, crtc_state,
7528 &fp, &reduced_clock,
7529 has_reduced_clock ? &fp2 : NULL);
7530
7531 crtc_state->dpll_hw_state.dpll = dpll;
7532 crtc_state->dpll_hw_state.fp0 = fp;
7533 if (has_reduced_clock)
7534 crtc_state->dpll_hw_state.fp1 = fp2;
7535 else
7536 crtc_state->dpll_hw_state.fp1 = fp;
7537
7538 pll = intel_get_shared_dpll(crtc, crtc_state);
7539 if (pll == NULL) {
7540 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7541 pipe_name(crtc->pipe));
7542 return -EINVAL;
7543 }
7544 }
7545
7546 if (is_lvds && has_reduced_clock && i915.powersave)
7547 crtc->lowfreq_avail = true;
7548 else
7549 crtc->lowfreq_avail = false;
7550
7551 return 0;
7552 }
7553
7554 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7555 struct intel_link_m_n *m_n)
7556 {
7557 struct drm_device *dev = crtc->base.dev;
7558 struct drm_i915_private *dev_priv = dev->dev_private;
7559 enum pipe pipe = crtc->pipe;
7560
7561 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7562 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7563 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7564 & ~TU_SIZE_MASK;
7565 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7566 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7567 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7568 }
7569
7570 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7571 enum transcoder transcoder,
7572 struct intel_link_m_n *m_n,
7573 struct intel_link_m_n *m2_n2)
7574 {
7575 struct drm_device *dev = crtc->base.dev;
7576 struct drm_i915_private *dev_priv = dev->dev_private;
7577 enum pipe pipe = crtc->pipe;
7578
7579 if (INTEL_INFO(dev)->gen >= 5) {
7580 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7581 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7582 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7583 & ~TU_SIZE_MASK;
7584 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7585 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7586 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7587 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7588 * gen < 8) and if DRRS is supported (to make sure the
7589 * registers are not unnecessarily read).
7590 */
7591 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7592 crtc->config->has_drrs) {
7593 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7594 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7595 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7596 & ~TU_SIZE_MASK;
7597 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7598 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7599 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7600 }
7601 } else {
7602 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7603 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7604 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7605 & ~TU_SIZE_MASK;
7606 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7607 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7608 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7609 }
7610 }
7611
7612 void intel_dp_get_m_n(struct intel_crtc *crtc,
7613 struct intel_crtc_state *pipe_config)
7614 {
7615 if (pipe_config->has_pch_encoder)
7616 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7617 else
7618 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7619 &pipe_config->dp_m_n,
7620 &pipe_config->dp_m2_n2);
7621 }
7622
7623 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7624 struct intel_crtc_state *pipe_config)
7625 {
7626 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7627 &pipe_config->fdi_m_n, NULL);
7628 }
7629
7630 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7631 struct intel_crtc_state *pipe_config)
7632 {
7633 struct drm_device *dev = crtc->base.dev;
7634 struct drm_i915_private *dev_priv = dev->dev_private;
7635 uint32_t tmp;
7636
7637 tmp = I915_READ(PS_CTL(crtc->pipe));
7638
7639 if (tmp & PS_ENABLE) {
7640 pipe_config->pch_pfit.enabled = true;
7641 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7642 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7643 }
7644 }
7645
7646 static void
7647 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7648 struct intel_initial_plane_config *plane_config)
7649 {
7650 struct drm_device *dev = crtc->base.dev;
7651 struct drm_i915_private *dev_priv = dev->dev_private;
7652 u32 val, base, offset, stride_mult;
7653 int pipe = crtc->pipe;
7654 int fourcc, pixel_format;
7655 int aligned_height;
7656 struct drm_framebuffer *fb;
7657 struct intel_framebuffer *intel_fb;
7658
7659 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7660 if (!intel_fb) {
7661 DRM_DEBUG_KMS("failed to alloc fb\n");
7662 return;
7663 }
7664
7665 fb = &intel_fb->base;
7666
7667 val = I915_READ(PLANE_CTL(pipe, 0));
7668 if (!(val & PLANE_CTL_ENABLE))
7669 goto error;
7670
7671 if (val & PLANE_CTL_TILED_MASK) {
7672 plane_config->tiling = I915_TILING_X;
7673 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7674 }
7675
7676 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7677 fourcc = skl_format_to_fourcc(pixel_format,
7678 val & PLANE_CTL_ORDER_RGBX,
7679 val & PLANE_CTL_ALPHA_MASK);
7680 fb->pixel_format = fourcc;
7681 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7682
7683 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7684 plane_config->base = base;
7685
7686 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7687
7688 val = I915_READ(PLANE_SIZE(pipe, 0));
7689 fb->height = ((val >> 16) & 0xfff) + 1;
7690 fb->width = ((val >> 0) & 0x1fff) + 1;
7691
7692 val = I915_READ(PLANE_STRIDE(pipe, 0));
7693 switch (plane_config->tiling) {
7694 case I915_TILING_NONE:
7695 stride_mult = 64;
7696 break;
7697 case I915_TILING_X:
7698 stride_mult = 512;
7699 break;
7700 default:
7701 MISSING_CASE(plane_config->tiling);
7702 goto error;
7703 }
7704 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7705
7706 aligned_height = intel_fb_align_height(dev, fb->height,
7707 fb->pixel_format,
7708 fb->modifier[0]);
7709
7710 plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
7711
7712 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7713 pipe_name(pipe), fb->width, fb->height,
7714 fb->bits_per_pixel, base, fb->pitches[0],
7715 plane_config->size);
7716
7717 plane_config->fb = intel_fb;
7718 return;
7719
7720 error:
7721 kfree(fb);
7722 }
7723
7724 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7725 struct intel_crtc_state *pipe_config)
7726 {
7727 struct drm_device *dev = crtc->base.dev;
7728 struct drm_i915_private *dev_priv = dev->dev_private;
7729 uint32_t tmp;
7730
7731 tmp = I915_READ(PF_CTL(crtc->pipe));
7732
7733 if (tmp & PF_ENABLE) {
7734 pipe_config->pch_pfit.enabled = true;
7735 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7736 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7737
7738 /* We currently do not free assignements of panel fitters on
7739 * ivb/hsw (since we don't use the higher upscaling modes which
7740 * differentiates them) so just WARN about this case for now. */
7741 if (IS_GEN7(dev)) {
7742 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7743 PF_PIPE_SEL_IVB(crtc->pipe));
7744 }
7745 }
7746 }
7747
7748 static void
7749 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7750 struct intel_initial_plane_config *plane_config)
7751 {
7752 struct drm_device *dev = crtc->base.dev;
7753 struct drm_i915_private *dev_priv = dev->dev_private;
7754 u32 val, base, offset;
7755 int pipe = crtc->pipe;
7756 int fourcc, pixel_format;
7757 int aligned_height;
7758 struct drm_framebuffer *fb;
7759 struct intel_framebuffer *intel_fb;
7760
7761 val = I915_READ(DSPCNTR(pipe));
7762 if (!(val & DISPLAY_PLANE_ENABLE))
7763 return;
7764
7765 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7766 if (!intel_fb) {
7767 DRM_DEBUG_KMS("failed to alloc fb\n");
7768 return;
7769 }
7770
7771 fb = &intel_fb->base;
7772
7773 if (INTEL_INFO(dev)->gen >= 4) {
7774 if (val & DISPPLANE_TILED) {
7775 plane_config->tiling = I915_TILING_X;
7776 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7777 }
7778 }
7779
7780 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7781 fourcc = i9xx_format_to_fourcc(pixel_format);
7782 fb->pixel_format = fourcc;
7783 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7784
7785 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7786 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7787 offset = I915_READ(DSPOFFSET(pipe));
7788 } else {
7789 if (plane_config->tiling)
7790 offset = I915_READ(DSPTILEOFF(pipe));
7791 else
7792 offset = I915_READ(DSPLINOFF(pipe));
7793 }
7794 plane_config->base = base;
7795
7796 val = I915_READ(PIPESRC(pipe));
7797 fb->width = ((val >> 16) & 0xfff) + 1;
7798 fb->height = ((val >> 0) & 0xfff) + 1;
7799
7800 val = I915_READ(DSPSTRIDE(pipe));
7801 fb->pitches[0] = val & 0xffffffc0;
7802
7803 aligned_height = intel_fb_align_height(dev, fb->height,
7804 fb->pixel_format,
7805 fb->modifier[0]);
7806
7807 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
7808
7809 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7810 pipe_name(pipe), fb->width, fb->height,
7811 fb->bits_per_pixel, base, fb->pitches[0],
7812 plane_config->size);
7813
7814 plane_config->fb = intel_fb;
7815 }
7816
7817 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7818 struct intel_crtc_state *pipe_config)
7819 {
7820 struct drm_device *dev = crtc->base.dev;
7821 struct drm_i915_private *dev_priv = dev->dev_private;
7822 uint32_t tmp;
7823
7824 if (!intel_display_power_is_enabled(dev_priv,
7825 POWER_DOMAIN_PIPE(crtc->pipe)))
7826 return false;
7827
7828 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7829 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7830
7831 tmp = I915_READ(PIPECONF(crtc->pipe));
7832 if (!(tmp & PIPECONF_ENABLE))
7833 return false;
7834
7835 switch (tmp & PIPECONF_BPC_MASK) {
7836 case PIPECONF_6BPC:
7837 pipe_config->pipe_bpp = 18;
7838 break;
7839 case PIPECONF_8BPC:
7840 pipe_config->pipe_bpp = 24;
7841 break;
7842 case PIPECONF_10BPC:
7843 pipe_config->pipe_bpp = 30;
7844 break;
7845 case PIPECONF_12BPC:
7846 pipe_config->pipe_bpp = 36;
7847 break;
7848 default:
7849 break;
7850 }
7851
7852 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7853 pipe_config->limited_color_range = true;
7854
7855 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7856 struct intel_shared_dpll *pll;
7857
7858 pipe_config->has_pch_encoder = true;
7859
7860 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7861 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7862 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7863
7864 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7865
7866 if (HAS_PCH_IBX(dev_priv->dev)) {
7867 pipe_config->shared_dpll =
7868 (enum intel_dpll_id) crtc->pipe;
7869 } else {
7870 tmp = I915_READ(PCH_DPLL_SEL);
7871 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7872 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7873 else
7874 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7875 }
7876
7877 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7878
7879 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7880 &pipe_config->dpll_hw_state));
7881
7882 tmp = pipe_config->dpll_hw_state.dpll;
7883 pipe_config->pixel_multiplier =
7884 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7885 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7886
7887 ironlake_pch_clock_get(crtc, pipe_config);
7888 } else {
7889 pipe_config->pixel_multiplier = 1;
7890 }
7891
7892 intel_get_pipe_timings(crtc, pipe_config);
7893
7894 ironlake_get_pfit_config(crtc, pipe_config);
7895
7896 return true;
7897 }
7898
7899 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7900 {
7901 struct drm_device *dev = dev_priv->dev;
7902 struct intel_crtc *crtc;
7903
7904 for_each_intel_crtc(dev, crtc)
7905 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7906 pipe_name(crtc->pipe));
7907
7908 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7909 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7910 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7911 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7912 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7913 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7914 "CPU PWM1 enabled\n");
7915 if (IS_HASWELL(dev))
7916 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7917 "CPU PWM2 enabled\n");
7918 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7919 "PCH PWM1 enabled\n");
7920 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7921 "Utility pin enabled\n");
7922 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7923
7924 /*
7925 * In theory we can still leave IRQs enabled, as long as only the HPD
7926 * interrupts remain enabled. We used to check for that, but since it's
7927 * gen-specific and since we only disable LCPLL after we fully disable
7928 * the interrupts, the check below should be enough.
7929 */
7930 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7931 }
7932
7933 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7934 {
7935 struct drm_device *dev = dev_priv->dev;
7936
7937 if (IS_HASWELL(dev))
7938 return I915_READ(D_COMP_HSW);
7939 else
7940 return I915_READ(D_COMP_BDW);
7941 }
7942
7943 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7944 {
7945 struct drm_device *dev = dev_priv->dev;
7946
7947 if (IS_HASWELL(dev)) {
7948 mutex_lock(&dev_priv->rps.hw_lock);
7949 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7950 val))
7951 DRM_ERROR("Failed to write to D_COMP\n");
7952 mutex_unlock(&dev_priv->rps.hw_lock);
7953 } else {
7954 I915_WRITE(D_COMP_BDW, val);
7955 POSTING_READ(D_COMP_BDW);
7956 }
7957 }
7958
7959 /*
7960 * This function implements pieces of two sequences from BSpec:
7961 * - Sequence for display software to disable LCPLL
7962 * - Sequence for display software to allow package C8+
7963 * The steps implemented here are just the steps that actually touch the LCPLL
7964 * register. Callers should take care of disabling all the display engine
7965 * functions, doing the mode unset, fixing interrupts, etc.
7966 */
7967 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7968 bool switch_to_fclk, bool allow_power_down)
7969 {
7970 uint32_t val;
7971
7972 assert_can_disable_lcpll(dev_priv);
7973
7974 val = I915_READ(LCPLL_CTL);
7975
7976 if (switch_to_fclk) {
7977 val |= LCPLL_CD_SOURCE_FCLK;
7978 I915_WRITE(LCPLL_CTL, val);
7979
7980 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7981 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7982 DRM_ERROR("Switching to FCLK failed\n");
7983
7984 val = I915_READ(LCPLL_CTL);
7985 }
7986
7987 val |= LCPLL_PLL_DISABLE;
7988 I915_WRITE(LCPLL_CTL, val);
7989 POSTING_READ(LCPLL_CTL);
7990
7991 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7992 DRM_ERROR("LCPLL still locked\n");
7993
7994 val = hsw_read_dcomp(dev_priv);
7995 val |= D_COMP_COMP_DISABLE;
7996 hsw_write_dcomp(dev_priv, val);
7997 ndelay(100);
7998
7999 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8000 1))
8001 DRM_ERROR("D_COMP RCOMP still in progress\n");
8002
8003 if (allow_power_down) {
8004 val = I915_READ(LCPLL_CTL);
8005 val |= LCPLL_POWER_DOWN_ALLOW;
8006 I915_WRITE(LCPLL_CTL, val);
8007 POSTING_READ(LCPLL_CTL);
8008 }
8009 }
8010
8011 /*
8012 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8013 * source.
8014 */
8015 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8016 {
8017 uint32_t val;
8018
8019 val = I915_READ(LCPLL_CTL);
8020
8021 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8022 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8023 return;
8024
8025 /*
8026 * Make sure we're not on PC8 state before disabling PC8, otherwise
8027 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8028 */
8029 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8030
8031 if (val & LCPLL_POWER_DOWN_ALLOW) {
8032 val &= ~LCPLL_POWER_DOWN_ALLOW;
8033 I915_WRITE(LCPLL_CTL, val);
8034 POSTING_READ(LCPLL_CTL);
8035 }
8036
8037 val = hsw_read_dcomp(dev_priv);
8038 val |= D_COMP_COMP_FORCE;
8039 val &= ~D_COMP_COMP_DISABLE;
8040 hsw_write_dcomp(dev_priv, val);
8041
8042 val = I915_READ(LCPLL_CTL);
8043 val &= ~LCPLL_PLL_DISABLE;
8044 I915_WRITE(LCPLL_CTL, val);
8045
8046 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8047 DRM_ERROR("LCPLL not locked yet\n");
8048
8049 if (val & LCPLL_CD_SOURCE_FCLK) {
8050 val = I915_READ(LCPLL_CTL);
8051 val &= ~LCPLL_CD_SOURCE_FCLK;
8052 I915_WRITE(LCPLL_CTL, val);
8053
8054 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8055 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8056 DRM_ERROR("Switching back to LCPLL failed\n");
8057 }
8058
8059 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8060 }
8061
8062 /*
8063 * Package states C8 and deeper are really deep PC states that can only be
8064 * reached when all the devices on the system allow it, so even if the graphics
8065 * device allows PC8+, it doesn't mean the system will actually get to these
8066 * states. Our driver only allows PC8+ when going into runtime PM.
8067 *
8068 * The requirements for PC8+ are that all the outputs are disabled, the power
8069 * well is disabled and most interrupts are disabled, and these are also
8070 * requirements for runtime PM. When these conditions are met, we manually do
8071 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8072 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8073 * hang the machine.
8074 *
8075 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8076 * the state of some registers, so when we come back from PC8+ we need to
8077 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8078 * need to take care of the registers kept by RC6. Notice that this happens even
8079 * if we don't put the device in PCI D3 state (which is what currently happens
8080 * because of the runtime PM support).
8081 *
8082 * For more, read "Display Sequences for Package C8" on the hardware
8083 * documentation.
8084 */
8085 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8086 {
8087 struct drm_device *dev = dev_priv->dev;
8088 uint32_t val;
8089
8090 DRM_DEBUG_KMS("Enabling package C8+\n");
8091
8092 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8093 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8094 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8095 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8096 }
8097
8098 lpt_disable_clkout_dp(dev);
8099 hsw_disable_lcpll(dev_priv, true, true);
8100 }
8101
8102 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8103 {
8104 struct drm_device *dev = dev_priv->dev;
8105 uint32_t val;
8106
8107 DRM_DEBUG_KMS("Disabling package C8+\n");
8108
8109 hsw_restore_lcpll(dev_priv);
8110 lpt_init_pch_refclk(dev);
8111
8112 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8113 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8114 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8115 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8116 }
8117
8118 intel_prepare_ddi(dev);
8119 }
8120
8121 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8122 struct intel_crtc_state *crtc_state)
8123 {
8124 if (!intel_ddi_pll_select(crtc, crtc_state))
8125 return -EINVAL;
8126
8127 crtc->lowfreq_avail = false;
8128
8129 return 0;
8130 }
8131
8132 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8133 enum port port,
8134 struct intel_crtc_state *pipe_config)
8135 {
8136 u32 temp, dpll_ctl1;
8137
8138 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8139 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8140
8141 switch (pipe_config->ddi_pll_sel) {
8142 case SKL_DPLL0:
8143 /*
8144 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8145 * of the shared DPLL framework and thus needs to be read out
8146 * separately
8147 */
8148 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8149 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8150 break;
8151 case SKL_DPLL1:
8152 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8153 break;
8154 case SKL_DPLL2:
8155 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8156 break;
8157 case SKL_DPLL3:
8158 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8159 break;
8160 }
8161 }
8162
8163 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8164 enum port port,
8165 struct intel_crtc_state *pipe_config)
8166 {
8167 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8168
8169 switch (pipe_config->ddi_pll_sel) {
8170 case PORT_CLK_SEL_WRPLL1:
8171 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8172 break;
8173 case PORT_CLK_SEL_WRPLL2:
8174 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8175 break;
8176 }
8177 }
8178
8179 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8180 struct intel_crtc_state *pipe_config)
8181 {
8182 struct drm_device *dev = crtc->base.dev;
8183 struct drm_i915_private *dev_priv = dev->dev_private;
8184 struct intel_shared_dpll *pll;
8185 enum port port;
8186 uint32_t tmp;
8187
8188 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8189
8190 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8191
8192 if (IS_SKYLAKE(dev))
8193 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8194 else
8195 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8196
8197 if (pipe_config->shared_dpll >= 0) {
8198 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8199
8200 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8201 &pipe_config->dpll_hw_state));
8202 }
8203
8204 /*
8205 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8206 * DDI E. So just check whether this pipe is wired to DDI E and whether
8207 * the PCH transcoder is on.
8208 */
8209 if (INTEL_INFO(dev)->gen < 9 &&
8210 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8211 pipe_config->has_pch_encoder = true;
8212
8213 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8214 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8215 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8216
8217 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8218 }
8219 }
8220
8221 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8222 struct intel_crtc_state *pipe_config)
8223 {
8224 struct drm_device *dev = crtc->base.dev;
8225 struct drm_i915_private *dev_priv = dev->dev_private;
8226 enum intel_display_power_domain pfit_domain;
8227 uint32_t tmp;
8228
8229 if (!intel_display_power_is_enabled(dev_priv,
8230 POWER_DOMAIN_PIPE(crtc->pipe)))
8231 return false;
8232
8233 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8234 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8235
8236 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8237 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8238 enum pipe trans_edp_pipe;
8239 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8240 default:
8241 WARN(1, "unknown pipe linked to edp transcoder\n");
8242 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8243 case TRANS_DDI_EDP_INPUT_A_ON:
8244 trans_edp_pipe = PIPE_A;
8245 break;
8246 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8247 trans_edp_pipe = PIPE_B;
8248 break;
8249 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8250 trans_edp_pipe = PIPE_C;
8251 break;
8252 }
8253
8254 if (trans_edp_pipe == crtc->pipe)
8255 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8256 }
8257
8258 if (!intel_display_power_is_enabled(dev_priv,
8259 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8260 return false;
8261
8262 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8263 if (!(tmp & PIPECONF_ENABLE))
8264 return false;
8265
8266 haswell_get_ddi_port_state(crtc, pipe_config);
8267
8268 intel_get_pipe_timings(crtc, pipe_config);
8269
8270 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8271 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8272 if (IS_SKYLAKE(dev))
8273 skylake_get_pfit_config(crtc, pipe_config);
8274 else
8275 ironlake_get_pfit_config(crtc, pipe_config);
8276 }
8277
8278 if (IS_HASWELL(dev))
8279 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8280 (I915_READ(IPS_CTL) & IPS_ENABLE);
8281
8282 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8283 pipe_config->pixel_multiplier =
8284 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8285 } else {
8286 pipe_config->pixel_multiplier = 1;
8287 }
8288
8289 return true;
8290 }
8291
8292 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8293 {
8294 struct drm_device *dev = crtc->dev;
8295 struct drm_i915_private *dev_priv = dev->dev_private;
8296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8297 uint32_t cntl = 0, size = 0;
8298
8299 if (base) {
8300 unsigned int width = intel_crtc->cursor_width;
8301 unsigned int height = intel_crtc->cursor_height;
8302 unsigned int stride = roundup_pow_of_two(width) * 4;
8303
8304 switch (stride) {
8305 default:
8306 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8307 width, stride);
8308 stride = 256;
8309 /* fallthrough */
8310 case 256:
8311 case 512:
8312 case 1024:
8313 case 2048:
8314 break;
8315 }
8316
8317 cntl |= CURSOR_ENABLE |
8318 CURSOR_GAMMA_ENABLE |
8319 CURSOR_FORMAT_ARGB |
8320 CURSOR_STRIDE(stride);
8321
8322 size = (height << 12) | width;
8323 }
8324
8325 if (intel_crtc->cursor_cntl != 0 &&
8326 (intel_crtc->cursor_base != base ||
8327 intel_crtc->cursor_size != size ||
8328 intel_crtc->cursor_cntl != cntl)) {
8329 /* On these chipsets we can only modify the base/size/stride
8330 * whilst the cursor is disabled.
8331 */
8332 I915_WRITE(_CURACNTR, 0);
8333 POSTING_READ(_CURACNTR);
8334 intel_crtc->cursor_cntl = 0;
8335 }
8336
8337 if (intel_crtc->cursor_base != base) {
8338 I915_WRITE(_CURABASE, base);
8339 intel_crtc->cursor_base = base;
8340 }
8341
8342 if (intel_crtc->cursor_size != size) {
8343 I915_WRITE(CURSIZE, size);
8344 intel_crtc->cursor_size = size;
8345 }
8346
8347 if (intel_crtc->cursor_cntl != cntl) {
8348 I915_WRITE(_CURACNTR, cntl);
8349 POSTING_READ(_CURACNTR);
8350 intel_crtc->cursor_cntl = cntl;
8351 }
8352 }
8353
8354 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8355 {
8356 struct drm_device *dev = crtc->dev;
8357 struct drm_i915_private *dev_priv = dev->dev_private;
8358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8359 int pipe = intel_crtc->pipe;
8360 uint32_t cntl;
8361
8362 cntl = 0;
8363 if (base) {
8364 cntl = MCURSOR_GAMMA_ENABLE;
8365 switch (intel_crtc->cursor_width) {
8366 case 64:
8367 cntl |= CURSOR_MODE_64_ARGB_AX;
8368 break;
8369 case 128:
8370 cntl |= CURSOR_MODE_128_ARGB_AX;
8371 break;
8372 case 256:
8373 cntl |= CURSOR_MODE_256_ARGB_AX;
8374 break;
8375 default:
8376 MISSING_CASE(intel_crtc->cursor_width);
8377 return;
8378 }
8379 cntl |= pipe << 28; /* Connect to correct pipe */
8380
8381 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8382 cntl |= CURSOR_PIPE_CSC_ENABLE;
8383 }
8384
8385 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8386 cntl |= CURSOR_ROTATE_180;
8387
8388 if (intel_crtc->cursor_cntl != cntl) {
8389 I915_WRITE(CURCNTR(pipe), cntl);
8390 POSTING_READ(CURCNTR(pipe));
8391 intel_crtc->cursor_cntl = cntl;
8392 }
8393
8394 /* and commit changes on next vblank */
8395 I915_WRITE(CURBASE(pipe), base);
8396 POSTING_READ(CURBASE(pipe));
8397
8398 intel_crtc->cursor_base = base;
8399 }
8400
8401 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8402 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8403 bool on)
8404 {
8405 struct drm_device *dev = crtc->dev;
8406 struct drm_i915_private *dev_priv = dev->dev_private;
8407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8408 int pipe = intel_crtc->pipe;
8409 int x = crtc->cursor_x;
8410 int y = crtc->cursor_y;
8411 u32 base = 0, pos = 0;
8412
8413 if (on)
8414 base = intel_crtc->cursor_addr;
8415
8416 if (x >= intel_crtc->config->pipe_src_w)
8417 base = 0;
8418
8419 if (y >= intel_crtc->config->pipe_src_h)
8420 base = 0;
8421
8422 if (x < 0) {
8423 if (x + intel_crtc->cursor_width <= 0)
8424 base = 0;
8425
8426 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8427 x = -x;
8428 }
8429 pos |= x << CURSOR_X_SHIFT;
8430
8431 if (y < 0) {
8432 if (y + intel_crtc->cursor_height <= 0)
8433 base = 0;
8434
8435 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8436 y = -y;
8437 }
8438 pos |= y << CURSOR_Y_SHIFT;
8439
8440 if (base == 0 && intel_crtc->cursor_base == 0)
8441 return;
8442
8443 I915_WRITE(CURPOS(pipe), pos);
8444
8445 /* ILK+ do this automagically */
8446 if (HAS_GMCH_DISPLAY(dev) &&
8447 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8448 base += (intel_crtc->cursor_height *
8449 intel_crtc->cursor_width - 1) * 4;
8450 }
8451
8452 if (IS_845G(dev) || IS_I865G(dev))
8453 i845_update_cursor(crtc, base);
8454 else
8455 i9xx_update_cursor(crtc, base);
8456 }
8457
8458 static bool cursor_size_ok(struct drm_device *dev,
8459 uint32_t width, uint32_t height)
8460 {
8461 if (width == 0 || height == 0)
8462 return false;
8463
8464 /*
8465 * 845g/865g are special in that they are only limited by
8466 * the width of their cursors, the height is arbitrary up to
8467 * the precision of the register. Everything else requires
8468 * square cursors, limited to a few power-of-two sizes.
8469 */
8470 if (IS_845G(dev) || IS_I865G(dev)) {
8471 if ((width & 63) != 0)
8472 return false;
8473
8474 if (width > (IS_845G(dev) ? 64 : 512))
8475 return false;
8476
8477 if (height > 1023)
8478 return false;
8479 } else {
8480 switch (width | height) {
8481 case 256:
8482 case 128:
8483 if (IS_GEN2(dev))
8484 return false;
8485 case 64:
8486 break;
8487 default:
8488 return false;
8489 }
8490 }
8491
8492 return true;
8493 }
8494
8495 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8496 u16 *blue, uint32_t start, uint32_t size)
8497 {
8498 int end = (start + size > 256) ? 256 : start + size, i;
8499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8500
8501 for (i = start; i < end; i++) {
8502 intel_crtc->lut_r[i] = red[i] >> 8;
8503 intel_crtc->lut_g[i] = green[i] >> 8;
8504 intel_crtc->lut_b[i] = blue[i] >> 8;
8505 }
8506
8507 intel_crtc_load_lut(crtc);
8508 }
8509
8510 /* VESA 640x480x72Hz mode to set on the pipe */
8511 static struct drm_display_mode load_detect_mode = {
8512 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8513 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8514 };
8515
8516 struct drm_framebuffer *
8517 __intel_framebuffer_create(struct drm_device *dev,
8518 struct drm_mode_fb_cmd2 *mode_cmd,
8519 struct drm_i915_gem_object *obj)
8520 {
8521 struct intel_framebuffer *intel_fb;
8522 int ret;
8523
8524 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8525 if (!intel_fb) {
8526 drm_gem_object_unreference(&obj->base);
8527 return ERR_PTR(-ENOMEM);
8528 }
8529
8530 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8531 if (ret)
8532 goto err;
8533
8534 return &intel_fb->base;
8535 err:
8536 drm_gem_object_unreference(&obj->base);
8537 kfree(intel_fb);
8538
8539 return ERR_PTR(ret);
8540 }
8541
8542 static struct drm_framebuffer *
8543 intel_framebuffer_create(struct drm_device *dev,
8544 struct drm_mode_fb_cmd2 *mode_cmd,
8545 struct drm_i915_gem_object *obj)
8546 {
8547 struct drm_framebuffer *fb;
8548 int ret;
8549
8550 ret = i915_mutex_lock_interruptible(dev);
8551 if (ret)
8552 return ERR_PTR(ret);
8553 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8554 mutex_unlock(&dev->struct_mutex);
8555
8556 return fb;
8557 }
8558
8559 static u32
8560 intel_framebuffer_pitch_for_width(int width, int bpp)
8561 {
8562 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8563 return ALIGN(pitch, 64);
8564 }
8565
8566 static u32
8567 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8568 {
8569 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8570 return PAGE_ALIGN(pitch * mode->vdisplay);
8571 }
8572
8573 static struct drm_framebuffer *
8574 intel_framebuffer_create_for_mode(struct drm_device *dev,
8575 struct drm_display_mode *mode,
8576 int depth, int bpp)
8577 {
8578 struct drm_i915_gem_object *obj;
8579 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8580
8581 obj = i915_gem_alloc_object(dev,
8582 intel_framebuffer_size_for_mode(mode, bpp));
8583 if (obj == NULL)
8584 return ERR_PTR(-ENOMEM);
8585
8586 mode_cmd.width = mode->hdisplay;
8587 mode_cmd.height = mode->vdisplay;
8588 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8589 bpp);
8590 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8591
8592 return intel_framebuffer_create(dev, &mode_cmd, obj);
8593 }
8594
8595 static struct drm_framebuffer *
8596 mode_fits_in_fbdev(struct drm_device *dev,
8597 struct drm_display_mode *mode)
8598 {
8599 #ifdef CONFIG_DRM_I915_FBDEV
8600 struct drm_i915_private *dev_priv = dev->dev_private;
8601 struct drm_i915_gem_object *obj;
8602 struct drm_framebuffer *fb;
8603
8604 if (!dev_priv->fbdev)
8605 return NULL;
8606
8607 if (!dev_priv->fbdev->fb)
8608 return NULL;
8609
8610 obj = dev_priv->fbdev->fb->obj;
8611 BUG_ON(!obj);
8612
8613 fb = &dev_priv->fbdev->fb->base;
8614 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8615 fb->bits_per_pixel))
8616 return NULL;
8617
8618 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8619 return NULL;
8620
8621 return fb;
8622 #else
8623 return NULL;
8624 #endif
8625 }
8626
8627 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8628 struct drm_display_mode *mode,
8629 struct intel_load_detect_pipe *old,
8630 struct drm_modeset_acquire_ctx *ctx)
8631 {
8632 struct intel_crtc *intel_crtc;
8633 struct intel_encoder *intel_encoder =
8634 intel_attached_encoder(connector);
8635 struct drm_crtc *possible_crtc;
8636 struct drm_encoder *encoder = &intel_encoder->base;
8637 struct drm_crtc *crtc = NULL;
8638 struct drm_device *dev = encoder->dev;
8639 struct drm_framebuffer *fb;
8640 struct drm_mode_config *config = &dev->mode_config;
8641 int ret, i = -1;
8642
8643 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8644 connector->base.id, connector->name,
8645 encoder->base.id, encoder->name);
8646
8647 retry:
8648 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8649 if (ret)
8650 goto fail_unlock;
8651
8652 /*
8653 * Algorithm gets a little messy:
8654 *
8655 * - if the connector already has an assigned crtc, use it (but make
8656 * sure it's on first)
8657 *
8658 * - try to find the first unused crtc that can drive this connector,
8659 * and use that if we find one
8660 */
8661
8662 /* See if we already have a CRTC for this connector */
8663 if (encoder->crtc) {
8664 crtc = encoder->crtc;
8665
8666 ret = drm_modeset_lock(&crtc->mutex, ctx);
8667 if (ret)
8668 goto fail_unlock;
8669 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8670 if (ret)
8671 goto fail_unlock;
8672
8673 old->dpms_mode = connector->dpms;
8674 old->load_detect_temp = false;
8675
8676 /* Make sure the crtc and connector are running */
8677 if (connector->dpms != DRM_MODE_DPMS_ON)
8678 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8679
8680 return true;
8681 }
8682
8683 /* Find an unused one (if possible) */
8684 for_each_crtc(dev, possible_crtc) {
8685 i++;
8686 if (!(encoder->possible_crtcs & (1 << i)))
8687 continue;
8688 if (possible_crtc->enabled)
8689 continue;
8690 /* This can occur when applying the pipe A quirk on resume. */
8691 if (to_intel_crtc(possible_crtc)->new_enabled)
8692 continue;
8693
8694 crtc = possible_crtc;
8695 break;
8696 }
8697
8698 /*
8699 * If we didn't find an unused CRTC, don't use any.
8700 */
8701 if (!crtc) {
8702 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8703 goto fail_unlock;
8704 }
8705
8706 ret = drm_modeset_lock(&crtc->mutex, ctx);
8707 if (ret)
8708 goto fail_unlock;
8709 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8710 if (ret)
8711 goto fail_unlock;
8712 intel_encoder->new_crtc = to_intel_crtc(crtc);
8713 to_intel_connector(connector)->new_encoder = intel_encoder;
8714
8715 intel_crtc = to_intel_crtc(crtc);
8716 intel_crtc->new_enabled = true;
8717 intel_crtc->new_config = intel_crtc->config;
8718 old->dpms_mode = connector->dpms;
8719 old->load_detect_temp = true;
8720 old->release_fb = NULL;
8721
8722 if (!mode)
8723 mode = &load_detect_mode;
8724
8725 /* We need a framebuffer large enough to accommodate all accesses
8726 * that the plane may generate whilst we perform load detection.
8727 * We can not rely on the fbcon either being present (we get called
8728 * during its initialisation to detect all boot displays, or it may
8729 * not even exist) or that it is large enough to satisfy the
8730 * requested mode.
8731 */
8732 fb = mode_fits_in_fbdev(dev, mode);
8733 if (fb == NULL) {
8734 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8735 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8736 old->release_fb = fb;
8737 } else
8738 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8739 if (IS_ERR(fb)) {
8740 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8741 goto fail;
8742 }
8743
8744 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8745 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8746 if (old->release_fb)
8747 old->release_fb->funcs->destroy(old->release_fb);
8748 goto fail;
8749 }
8750
8751 /* let the connector get through one full cycle before testing */
8752 intel_wait_for_vblank(dev, intel_crtc->pipe);
8753 return true;
8754
8755 fail:
8756 intel_crtc->new_enabled = crtc->enabled;
8757 if (intel_crtc->new_enabled)
8758 intel_crtc->new_config = intel_crtc->config;
8759 else
8760 intel_crtc->new_config = NULL;
8761 fail_unlock:
8762 if (ret == -EDEADLK) {
8763 drm_modeset_backoff(ctx);
8764 goto retry;
8765 }
8766
8767 return false;
8768 }
8769
8770 void intel_release_load_detect_pipe(struct drm_connector *connector,
8771 struct intel_load_detect_pipe *old)
8772 {
8773 struct intel_encoder *intel_encoder =
8774 intel_attached_encoder(connector);
8775 struct drm_encoder *encoder = &intel_encoder->base;
8776 struct drm_crtc *crtc = encoder->crtc;
8777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8778
8779 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8780 connector->base.id, connector->name,
8781 encoder->base.id, encoder->name);
8782
8783 if (old->load_detect_temp) {
8784 to_intel_connector(connector)->new_encoder = NULL;
8785 intel_encoder->new_crtc = NULL;
8786 intel_crtc->new_enabled = false;
8787 intel_crtc->new_config = NULL;
8788 intel_set_mode(crtc, NULL, 0, 0, NULL);
8789
8790 if (old->release_fb) {
8791 drm_framebuffer_unregister_private(old->release_fb);
8792 drm_framebuffer_unreference(old->release_fb);
8793 }
8794
8795 return;
8796 }
8797
8798 /* Switch crtc and encoder back off if necessary */
8799 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8800 connector->funcs->dpms(connector, old->dpms_mode);
8801 }
8802
8803 static int i9xx_pll_refclk(struct drm_device *dev,
8804 const struct intel_crtc_state *pipe_config)
8805 {
8806 struct drm_i915_private *dev_priv = dev->dev_private;
8807 u32 dpll = pipe_config->dpll_hw_state.dpll;
8808
8809 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8810 return dev_priv->vbt.lvds_ssc_freq;
8811 else if (HAS_PCH_SPLIT(dev))
8812 return 120000;
8813 else if (!IS_GEN2(dev))
8814 return 96000;
8815 else
8816 return 48000;
8817 }
8818
8819 /* Returns the clock of the currently programmed mode of the given pipe. */
8820 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8821 struct intel_crtc_state *pipe_config)
8822 {
8823 struct drm_device *dev = crtc->base.dev;
8824 struct drm_i915_private *dev_priv = dev->dev_private;
8825 int pipe = pipe_config->cpu_transcoder;
8826 u32 dpll = pipe_config->dpll_hw_state.dpll;
8827 u32 fp;
8828 intel_clock_t clock;
8829 int refclk = i9xx_pll_refclk(dev, pipe_config);
8830
8831 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8832 fp = pipe_config->dpll_hw_state.fp0;
8833 else
8834 fp = pipe_config->dpll_hw_state.fp1;
8835
8836 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8837 if (IS_PINEVIEW(dev)) {
8838 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8839 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8840 } else {
8841 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8842 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8843 }
8844
8845 if (!IS_GEN2(dev)) {
8846 if (IS_PINEVIEW(dev))
8847 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8848 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8849 else
8850 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8851 DPLL_FPA01_P1_POST_DIV_SHIFT);
8852
8853 switch (dpll & DPLL_MODE_MASK) {
8854 case DPLLB_MODE_DAC_SERIAL:
8855 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8856 5 : 10;
8857 break;
8858 case DPLLB_MODE_LVDS:
8859 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8860 7 : 14;
8861 break;
8862 default:
8863 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8864 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8865 return;
8866 }
8867
8868 if (IS_PINEVIEW(dev))
8869 pineview_clock(refclk, &clock);
8870 else
8871 i9xx_clock(refclk, &clock);
8872 } else {
8873 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8874 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8875
8876 if (is_lvds) {
8877 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8878 DPLL_FPA01_P1_POST_DIV_SHIFT);
8879
8880 if (lvds & LVDS_CLKB_POWER_UP)
8881 clock.p2 = 7;
8882 else
8883 clock.p2 = 14;
8884 } else {
8885 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8886 clock.p1 = 2;
8887 else {
8888 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8889 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8890 }
8891 if (dpll & PLL_P2_DIVIDE_BY_4)
8892 clock.p2 = 4;
8893 else
8894 clock.p2 = 2;
8895 }
8896
8897 i9xx_clock(refclk, &clock);
8898 }
8899
8900 /*
8901 * This value includes pixel_multiplier. We will use
8902 * port_clock to compute adjusted_mode.crtc_clock in the
8903 * encoder's get_config() function.
8904 */
8905 pipe_config->port_clock = clock.dot;
8906 }
8907
8908 int intel_dotclock_calculate(int link_freq,
8909 const struct intel_link_m_n *m_n)
8910 {
8911 /*
8912 * The calculation for the data clock is:
8913 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8914 * But we want to avoid losing precison if possible, so:
8915 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8916 *
8917 * and the link clock is simpler:
8918 * link_clock = (m * link_clock) / n
8919 */
8920
8921 if (!m_n->link_n)
8922 return 0;
8923
8924 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8925 }
8926
8927 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8928 struct intel_crtc_state *pipe_config)
8929 {
8930 struct drm_device *dev = crtc->base.dev;
8931
8932 /* read out port_clock from the DPLL */
8933 i9xx_crtc_clock_get(crtc, pipe_config);
8934
8935 /*
8936 * This value does not include pixel_multiplier.
8937 * We will check that port_clock and adjusted_mode.crtc_clock
8938 * agree once we know their relationship in the encoder's
8939 * get_config() function.
8940 */
8941 pipe_config->base.adjusted_mode.crtc_clock =
8942 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8943 &pipe_config->fdi_m_n);
8944 }
8945
8946 /** Returns the currently programmed mode of the given pipe. */
8947 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8948 struct drm_crtc *crtc)
8949 {
8950 struct drm_i915_private *dev_priv = dev->dev_private;
8951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8952 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8953 struct drm_display_mode *mode;
8954 struct intel_crtc_state pipe_config;
8955 int htot = I915_READ(HTOTAL(cpu_transcoder));
8956 int hsync = I915_READ(HSYNC(cpu_transcoder));
8957 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8958 int vsync = I915_READ(VSYNC(cpu_transcoder));
8959 enum pipe pipe = intel_crtc->pipe;
8960
8961 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8962 if (!mode)
8963 return NULL;
8964
8965 /*
8966 * Construct a pipe_config sufficient for getting the clock info
8967 * back out of crtc_clock_get.
8968 *
8969 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8970 * to use a real value here instead.
8971 */
8972 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8973 pipe_config.pixel_multiplier = 1;
8974 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8975 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8976 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8977 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8978
8979 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8980 mode->hdisplay = (htot & 0xffff) + 1;
8981 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8982 mode->hsync_start = (hsync & 0xffff) + 1;
8983 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8984 mode->vdisplay = (vtot & 0xffff) + 1;
8985 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8986 mode->vsync_start = (vsync & 0xffff) + 1;
8987 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8988
8989 drm_mode_set_name(mode);
8990
8991 return mode;
8992 }
8993
8994 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8995 {
8996 struct drm_device *dev = crtc->dev;
8997 struct drm_i915_private *dev_priv = dev->dev_private;
8998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8999
9000 if (!HAS_GMCH_DISPLAY(dev))
9001 return;
9002
9003 if (!dev_priv->lvds_downclock_avail)
9004 return;
9005
9006 /*
9007 * Since this is called by a timer, we should never get here in
9008 * the manual case.
9009 */
9010 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9011 int pipe = intel_crtc->pipe;
9012 int dpll_reg = DPLL(pipe);
9013 int dpll;
9014
9015 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9016
9017 assert_panel_unlocked(dev_priv, pipe);
9018
9019 dpll = I915_READ(dpll_reg);
9020 dpll |= DISPLAY_RATE_SELECT_FPA1;
9021 I915_WRITE(dpll_reg, dpll);
9022 intel_wait_for_vblank(dev, pipe);
9023 dpll = I915_READ(dpll_reg);
9024 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9025 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9026 }
9027
9028 }
9029
9030 void intel_mark_busy(struct drm_device *dev)
9031 {
9032 struct drm_i915_private *dev_priv = dev->dev_private;
9033
9034 if (dev_priv->mm.busy)
9035 return;
9036
9037 intel_runtime_pm_get(dev_priv);
9038 i915_update_gfx_val(dev_priv);
9039 dev_priv->mm.busy = true;
9040 }
9041
9042 void intel_mark_idle(struct drm_device *dev)
9043 {
9044 struct drm_i915_private *dev_priv = dev->dev_private;
9045 struct drm_crtc *crtc;
9046
9047 if (!dev_priv->mm.busy)
9048 return;
9049
9050 dev_priv->mm.busy = false;
9051
9052 if (!i915.powersave)
9053 goto out;
9054
9055 for_each_crtc(dev, crtc) {
9056 if (!crtc->primary->fb)
9057 continue;
9058
9059 intel_decrease_pllclock(crtc);
9060 }
9061
9062 if (INTEL_INFO(dev)->gen >= 6)
9063 gen6_rps_idle(dev->dev_private);
9064
9065 out:
9066 intel_runtime_pm_put(dev_priv);
9067 }
9068
9069 static void intel_crtc_set_state(struct intel_crtc *crtc,
9070 struct intel_crtc_state *crtc_state)
9071 {
9072 kfree(crtc->config);
9073 crtc->config = crtc_state;
9074 crtc->base.state = &crtc_state->base;
9075 }
9076
9077 static void intel_crtc_destroy(struct drm_crtc *crtc)
9078 {
9079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9080 struct drm_device *dev = crtc->dev;
9081 struct intel_unpin_work *work;
9082
9083 spin_lock_irq(&dev->event_lock);
9084 work = intel_crtc->unpin_work;
9085 intel_crtc->unpin_work = NULL;
9086 spin_unlock_irq(&dev->event_lock);
9087
9088 if (work) {
9089 cancel_work_sync(&work->work);
9090 kfree(work);
9091 }
9092
9093 intel_crtc_set_state(intel_crtc, NULL);
9094 drm_crtc_cleanup(crtc);
9095
9096 kfree(intel_crtc);
9097 }
9098
9099 static void intel_unpin_work_fn(struct work_struct *__work)
9100 {
9101 struct intel_unpin_work *work =
9102 container_of(__work, struct intel_unpin_work, work);
9103 struct drm_device *dev = work->crtc->dev;
9104 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9105
9106 mutex_lock(&dev->struct_mutex);
9107 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9108 drm_gem_object_unreference(&work->pending_flip_obj->base);
9109 drm_framebuffer_unreference(work->old_fb);
9110
9111 intel_fbc_update(dev);
9112
9113 if (work->flip_queued_req)
9114 i915_gem_request_assign(&work->flip_queued_req, NULL);
9115 mutex_unlock(&dev->struct_mutex);
9116
9117 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9118
9119 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9120 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9121
9122 kfree(work);
9123 }
9124
9125 static void do_intel_finish_page_flip(struct drm_device *dev,
9126 struct drm_crtc *crtc)
9127 {
9128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9129 struct intel_unpin_work *work;
9130 unsigned long flags;
9131
9132 /* Ignore early vblank irqs */
9133 if (intel_crtc == NULL)
9134 return;
9135
9136 /*
9137 * This is called both by irq handlers and the reset code (to complete
9138 * lost pageflips) so needs the full irqsave spinlocks.
9139 */
9140 spin_lock_irqsave(&dev->event_lock, flags);
9141 work = intel_crtc->unpin_work;
9142
9143 /* Ensure we don't miss a work->pending update ... */
9144 smp_rmb();
9145
9146 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9147 spin_unlock_irqrestore(&dev->event_lock, flags);
9148 return;
9149 }
9150
9151 page_flip_completed(intel_crtc);
9152
9153 spin_unlock_irqrestore(&dev->event_lock, flags);
9154 }
9155
9156 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9157 {
9158 struct drm_i915_private *dev_priv = dev->dev_private;
9159 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9160
9161 do_intel_finish_page_flip(dev, crtc);
9162 }
9163
9164 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9165 {
9166 struct drm_i915_private *dev_priv = dev->dev_private;
9167 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9168
9169 do_intel_finish_page_flip(dev, crtc);
9170 }
9171
9172 /* Is 'a' after or equal to 'b'? */
9173 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9174 {
9175 return !((a - b) & 0x80000000);
9176 }
9177
9178 static bool page_flip_finished(struct intel_crtc *crtc)
9179 {
9180 struct drm_device *dev = crtc->base.dev;
9181 struct drm_i915_private *dev_priv = dev->dev_private;
9182
9183 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9184 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9185 return true;
9186
9187 /*
9188 * The relevant registers doen't exist on pre-ctg.
9189 * As the flip done interrupt doesn't trigger for mmio
9190 * flips on gmch platforms, a flip count check isn't
9191 * really needed there. But since ctg has the registers,
9192 * include it in the check anyway.
9193 */
9194 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9195 return true;
9196
9197 /*
9198 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9199 * used the same base address. In that case the mmio flip might
9200 * have completed, but the CS hasn't even executed the flip yet.
9201 *
9202 * A flip count check isn't enough as the CS might have updated
9203 * the base address just after start of vblank, but before we
9204 * managed to process the interrupt. This means we'd complete the
9205 * CS flip too soon.
9206 *
9207 * Combining both checks should get us a good enough result. It may
9208 * still happen that the CS flip has been executed, but has not
9209 * yet actually completed. But in case the base address is the same
9210 * anyway, we don't really care.
9211 */
9212 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9213 crtc->unpin_work->gtt_offset &&
9214 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9215 crtc->unpin_work->flip_count);
9216 }
9217
9218 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9219 {
9220 struct drm_i915_private *dev_priv = dev->dev_private;
9221 struct intel_crtc *intel_crtc =
9222 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9223 unsigned long flags;
9224
9225
9226 /*
9227 * This is called both by irq handlers and the reset code (to complete
9228 * lost pageflips) so needs the full irqsave spinlocks.
9229 *
9230 * NB: An MMIO update of the plane base pointer will also
9231 * generate a page-flip completion irq, i.e. every modeset
9232 * is also accompanied by a spurious intel_prepare_page_flip().
9233 */
9234 spin_lock_irqsave(&dev->event_lock, flags);
9235 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9236 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9237 spin_unlock_irqrestore(&dev->event_lock, flags);
9238 }
9239
9240 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9241 {
9242 /* Ensure that the work item is consistent when activating it ... */
9243 smp_wmb();
9244 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9245 /* and that it is marked active as soon as the irq could fire. */
9246 smp_wmb();
9247 }
9248
9249 static int intel_gen2_queue_flip(struct drm_device *dev,
9250 struct drm_crtc *crtc,
9251 struct drm_framebuffer *fb,
9252 struct drm_i915_gem_object *obj,
9253 struct intel_engine_cs *ring,
9254 uint32_t flags)
9255 {
9256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9257 u32 flip_mask;
9258 int ret;
9259
9260 ret = intel_ring_begin(ring, 6);
9261 if (ret)
9262 return ret;
9263
9264 /* Can't queue multiple flips, so wait for the previous
9265 * one to finish before executing the next.
9266 */
9267 if (intel_crtc->plane)
9268 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9269 else
9270 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9271 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9272 intel_ring_emit(ring, MI_NOOP);
9273 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9274 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9275 intel_ring_emit(ring, fb->pitches[0]);
9276 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9277 intel_ring_emit(ring, 0); /* aux display base address, unused */
9278
9279 intel_mark_page_flip_active(intel_crtc);
9280 __intel_ring_advance(ring);
9281 return 0;
9282 }
9283
9284 static int intel_gen3_queue_flip(struct drm_device *dev,
9285 struct drm_crtc *crtc,
9286 struct drm_framebuffer *fb,
9287 struct drm_i915_gem_object *obj,
9288 struct intel_engine_cs *ring,
9289 uint32_t flags)
9290 {
9291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9292 u32 flip_mask;
9293 int ret;
9294
9295 ret = intel_ring_begin(ring, 6);
9296 if (ret)
9297 return ret;
9298
9299 if (intel_crtc->plane)
9300 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9301 else
9302 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9303 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9304 intel_ring_emit(ring, MI_NOOP);
9305 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9306 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9307 intel_ring_emit(ring, fb->pitches[0]);
9308 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9309 intel_ring_emit(ring, MI_NOOP);
9310
9311 intel_mark_page_flip_active(intel_crtc);
9312 __intel_ring_advance(ring);
9313 return 0;
9314 }
9315
9316 static int intel_gen4_queue_flip(struct drm_device *dev,
9317 struct drm_crtc *crtc,
9318 struct drm_framebuffer *fb,
9319 struct drm_i915_gem_object *obj,
9320 struct intel_engine_cs *ring,
9321 uint32_t flags)
9322 {
9323 struct drm_i915_private *dev_priv = dev->dev_private;
9324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9325 uint32_t pf, pipesrc;
9326 int ret;
9327
9328 ret = intel_ring_begin(ring, 4);
9329 if (ret)
9330 return ret;
9331
9332 /* i965+ uses the linear or tiled offsets from the
9333 * Display Registers (which do not change across a page-flip)
9334 * so we need only reprogram the base address.
9335 */
9336 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9337 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9338 intel_ring_emit(ring, fb->pitches[0]);
9339 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9340 obj->tiling_mode);
9341
9342 /* XXX Enabling the panel-fitter across page-flip is so far
9343 * untested on non-native modes, so ignore it for now.
9344 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9345 */
9346 pf = 0;
9347 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9348 intel_ring_emit(ring, pf | pipesrc);
9349
9350 intel_mark_page_flip_active(intel_crtc);
9351 __intel_ring_advance(ring);
9352 return 0;
9353 }
9354
9355 static int intel_gen6_queue_flip(struct drm_device *dev,
9356 struct drm_crtc *crtc,
9357 struct drm_framebuffer *fb,
9358 struct drm_i915_gem_object *obj,
9359 struct intel_engine_cs *ring,
9360 uint32_t flags)
9361 {
9362 struct drm_i915_private *dev_priv = dev->dev_private;
9363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9364 uint32_t pf, pipesrc;
9365 int ret;
9366
9367 ret = intel_ring_begin(ring, 4);
9368 if (ret)
9369 return ret;
9370
9371 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9372 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9373 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9374 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9375
9376 /* Contrary to the suggestions in the documentation,
9377 * "Enable Panel Fitter" does not seem to be required when page
9378 * flipping with a non-native mode, and worse causes a normal
9379 * modeset to fail.
9380 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9381 */
9382 pf = 0;
9383 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9384 intel_ring_emit(ring, pf | pipesrc);
9385
9386 intel_mark_page_flip_active(intel_crtc);
9387 __intel_ring_advance(ring);
9388 return 0;
9389 }
9390
9391 static int intel_gen7_queue_flip(struct drm_device *dev,
9392 struct drm_crtc *crtc,
9393 struct drm_framebuffer *fb,
9394 struct drm_i915_gem_object *obj,
9395 struct intel_engine_cs *ring,
9396 uint32_t flags)
9397 {
9398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9399 uint32_t plane_bit = 0;
9400 int len, ret;
9401
9402 switch (intel_crtc->plane) {
9403 case PLANE_A:
9404 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9405 break;
9406 case PLANE_B:
9407 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9408 break;
9409 case PLANE_C:
9410 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9411 break;
9412 default:
9413 WARN_ONCE(1, "unknown plane in flip command\n");
9414 return -ENODEV;
9415 }
9416
9417 len = 4;
9418 if (ring->id == RCS) {
9419 len += 6;
9420 /*
9421 * On Gen 8, SRM is now taking an extra dword to accommodate
9422 * 48bits addresses, and we need a NOOP for the batch size to
9423 * stay even.
9424 */
9425 if (IS_GEN8(dev))
9426 len += 2;
9427 }
9428
9429 /*
9430 * BSpec MI_DISPLAY_FLIP for IVB:
9431 * "The full packet must be contained within the same cache line."
9432 *
9433 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9434 * cacheline, if we ever start emitting more commands before
9435 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9436 * then do the cacheline alignment, and finally emit the
9437 * MI_DISPLAY_FLIP.
9438 */
9439 ret = intel_ring_cacheline_align(ring);
9440 if (ret)
9441 return ret;
9442
9443 ret = intel_ring_begin(ring, len);
9444 if (ret)
9445 return ret;
9446
9447 /* Unmask the flip-done completion message. Note that the bspec says that
9448 * we should do this for both the BCS and RCS, and that we must not unmask
9449 * more than one flip event at any time (or ensure that one flip message
9450 * can be sent by waiting for flip-done prior to queueing new flips).
9451 * Experimentation says that BCS works despite DERRMR masking all
9452 * flip-done completion events and that unmasking all planes at once
9453 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9454 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9455 */
9456 if (ring->id == RCS) {
9457 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9458 intel_ring_emit(ring, DERRMR);
9459 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9460 DERRMR_PIPEB_PRI_FLIP_DONE |
9461 DERRMR_PIPEC_PRI_FLIP_DONE));
9462 if (IS_GEN8(dev))
9463 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9464 MI_SRM_LRM_GLOBAL_GTT);
9465 else
9466 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9467 MI_SRM_LRM_GLOBAL_GTT);
9468 intel_ring_emit(ring, DERRMR);
9469 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9470 if (IS_GEN8(dev)) {
9471 intel_ring_emit(ring, 0);
9472 intel_ring_emit(ring, MI_NOOP);
9473 }
9474 }
9475
9476 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9477 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9478 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9479 intel_ring_emit(ring, (MI_NOOP));
9480
9481 intel_mark_page_flip_active(intel_crtc);
9482 __intel_ring_advance(ring);
9483 return 0;
9484 }
9485
9486 static bool use_mmio_flip(struct intel_engine_cs *ring,
9487 struct drm_i915_gem_object *obj)
9488 {
9489 /*
9490 * This is not being used for older platforms, because
9491 * non-availability of flip done interrupt forces us to use
9492 * CS flips. Older platforms derive flip done using some clever
9493 * tricks involving the flip_pending status bits and vblank irqs.
9494 * So using MMIO flips there would disrupt this mechanism.
9495 */
9496
9497 if (ring == NULL)
9498 return true;
9499
9500 if (INTEL_INFO(ring->dev)->gen < 5)
9501 return false;
9502
9503 if (i915.use_mmio_flip < 0)
9504 return false;
9505 else if (i915.use_mmio_flip > 0)
9506 return true;
9507 else if (i915.enable_execlists)
9508 return true;
9509 else
9510 return ring != i915_gem_request_get_ring(obj->last_read_req);
9511 }
9512
9513 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9514 {
9515 struct drm_device *dev = intel_crtc->base.dev;
9516 struct drm_i915_private *dev_priv = dev->dev_private;
9517 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9518 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9519 struct drm_i915_gem_object *obj = intel_fb->obj;
9520 const enum pipe pipe = intel_crtc->pipe;
9521 u32 ctl, stride;
9522
9523 ctl = I915_READ(PLANE_CTL(pipe, 0));
9524 ctl &= ~PLANE_CTL_TILED_MASK;
9525 if (obj->tiling_mode == I915_TILING_X)
9526 ctl |= PLANE_CTL_TILED_X;
9527
9528 /*
9529 * The stride is either expressed as a multiple of 64 bytes chunks for
9530 * linear buffers or in number of tiles for tiled buffers.
9531 */
9532 stride = fb->pitches[0] >> 6;
9533 if (obj->tiling_mode == I915_TILING_X)
9534 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9535
9536 /*
9537 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9538 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9539 */
9540 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9541 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9542
9543 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9544 POSTING_READ(PLANE_SURF(pipe, 0));
9545 }
9546
9547 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9548 {
9549 struct drm_device *dev = intel_crtc->base.dev;
9550 struct drm_i915_private *dev_priv = dev->dev_private;
9551 struct intel_framebuffer *intel_fb =
9552 to_intel_framebuffer(intel_crtc->base.primary->fb);
9553 struct drm_i915_gem_object *obj = intel_fb->obj;
9554 u32 dspcntr;
9555 u32 reg;
9556
9557 reg = DSPCNTR(intel_crtc->plane);
9558 dspcntr = I915_READ(reg);
9559
9560 if (obj->tiling_mode != I915_TILING_NONE)
9561 dspcntr |= DISPPLANE_TILED;
9562 else
9563 dspcntr &= ~DISPPLANE_TILED;
9564
9565 I915_WRITE(reg, dspcntr);
9566
9567 I915_WRITE(DSPSURF(intel_crtc->plane),
9568 intel_crtc->unpin_work->gtt_offset);
9569 POSTING_READ(DSPSURF(intel_crtc->plane));
9570
9571 }
9572
9573 /*
9574 * XXX: This is the temporary way to update the plane registers until we get
9575 * around to using the usual plane update functions for MMIO flips
9576 */
9577 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9578 {
9579 struct drm_device *dev = intel_crtc->base.dev;
9580 bool atomic_update;
9581 u32 start_vbl_count;
9582
9583 intel_mark_page_flip_active(intel_crtc);
9584
9585 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9586
9587 if (INTEL_INFO(dev)->gen >= 9)
9588 skl_do_mmio_flip(intel_crtc);
9589 else
9590 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9591 ilk_do_mmio_flip(intel_crtc);
9592
9593 if (atomic_update)
9594 intel_pipe_update_end(intel_crtc, start_vbl_count);
9595 }
9596
9597 static void intel_mmio_flip_work_func(struct work_struct *work)
9598 {
9599 struct intel_crtc *crtc =
9600 container_of(work, struct intel_crtc, mmio_flip.work);
9601 struct intel_mmio_flip *mmio_flip;
9602
9603 mmio_flip = &crtc->mmio_flip;
9604 if (mmio_flip->req)
9605 WARN_ON(__i915_wait_request(mmio_flip->req,
9606 crtc->reset_counter,
9607 false, NULL, NULL) != 0);
9608
9609 intel_do_mmio_flip(crtc);
9610 if (mmio_flip->req) {
9611 mutex_lock(&crtc->base.dev->struct_mutex);
9612 i915_gem_request_assign(&mmio_flip->req, NULL);
9613 mutex_unlock(&crtc->base.dev->struct_mutex);
9614 }
9615 }
9616
9617 static int intel_queue_mmio_flip(struct drm_device *dev,
9618 struct drm_crtc *crtc,
9619 struct drm_framebuffer *fb,
9620 struct drm_i915_gem_object *obj,
9621 struct intel_engine_cs *ring,
9622 uint32_t flags)
9623 {
9624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9625
9626 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9627 obj->last_write_req);
9628
9629 schedule_work(&intel_crtc->mmio_flip.work);
9630
9631 return 0;
9632 }
9633
9634 static int intel_gen9_queue_flip(struct drm_device *dev,
9635 struct drm_crtc *crtc,
9636 struct drm_framebuffer *fb,
9637 struct drm_i915_gem_object *obj,
9638 struct intel_engine_cs *ring,
9639 uint32_t flags)
9640 {
9641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9642 uint32_t plane = 0, stride;
9643 int ret;
9644
9645 switch(intel_crtc->pipe) {
9646 case PIPE_A:
9647 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9648 break;
9649 case PIPE_B:
9650 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9651 break;
9652 case PIPE_C:
9653 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9654 break;
9655 default:
9656 WARN_ONCE(1, "unknown plane in flip command\n");
9657 return -ENODEV;
9658 }
9659
9660 switch (obj->tiling_mode) {
9661 case I915_TILING_NONE:
9662 stride = fb->pitches[0] >> 6;
9663 break;
9664 case I915_TILING_X:
9665 stride = fb->pitches[0] >> 9;
9666 break;
9667 default:
9668 WARN_ONCE(1, "unknown tiling in flip command\n");
9669 return -ENODEV;
9670 }
9671
9672 ret = intel_ring_begin(ring, 10);
9673 if (ret)
9674 return ret;
9675
9676 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9677 intel_ring_emit(ring, DERRMR);
9678 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9679 DERRMR_PIPEB_PRI_FLIP_DONE |
9680 DERRMR_PIPEC_PRI_FLIP_DONE));
9681 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9682 MI_SRM_LRM_GLOBAL_GTT);
9683 intel_ring_emit(ring, DERRMR);
9684 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9685 intel_ring_emit(ring, 0);
9686
9687 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9688 intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9689 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9690
9691 intel_mark_page_flip_active(intel_crtc);
9692 __intel_ring_advance(ring);
9693
9694 return 0;
9695 }
9696
9697 static int intel_default_queue_flip(struct drm_device *dev,
9698 struct drm_crtc *crtc,
9699 struct drm_framebuffer *fb,
9700 struct drm_i915_gem_object *obj,
9701 struct intel_engine_cs *ring,
9702 uint32_t flags)
9703 {
9704 return -ENODEV;
9705 }
9706
9707 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9708 struct drm_crtc *crtc)
9709 {
9710 struct drm_i915_private *dev_priv = dev->dev_private;
9711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9712 struct intel_unpin_work *work = intel_crtc->unpin_work;
9713 u32 addr;
9714
9715 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9716 return true;
9717
9718 if (!work->enable_stall_check)
9719 return false;
9720
9721 if (work->flip_ready_vblank == 0) {
9722 if (work->flip_queued_req &&
9723 !i915_gem_request_completed(work->flip_queued_req, true))
9724 return false;
9725
9726 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9727 }
9728
9729 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9730 return false;
9731
9732 /* Potential stall - if we see that the flip has happened,
9733 * assume a missed interrupt. */
9734 if (INTEL_INFO(dev)->gen >= 4)
9735 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9736 else
9737 addr = I915_READ(DSPADDR(intel_crtc->plane));
9738
9739 /* There is a potential issue here with a false positive after a flip
9740 * to the same address. We could address this by checking for a
9741 * non-incrementing frame counter.
9742 */
9743 return addr == work->gtt_offset;
9744 }
9745
9746 void intel_check_page_flip(struct drm_device *dev, int pipe)
9747 {
9748 struct drm_i915_private *dev_priv = dev->dev_private;
9749 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9751
9752 WARN_ON(!in_irq());
9753
9754 if (crtc == NULL)
9755 return;
9756
9757 spin_lock(&dev->event_lock);
9758 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9759 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9760 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9761 page_flip_completed(intel_crtc);
9762 }
9763 spin_unlock(&dev->event_lock);
9764 }
9765
9766 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9767 struct drm_framebuffer *fb,
9768 struct drm_pending_vblank_event *event,
9769 uint32_t page_flip_flags)
9770 {
9771 struct drm_device *dev = crtc->dev;
9772 struct drm_i915_private *dev_priv = dev->dev_private;
9773 struct drm_framebuffer *old_fb = crtc->primary->fb;
9774 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9776 struct drm_plane *primary = crtc->primary;
9777 enum pipe pipe = intel_crtc->pipe;
9778 struct intel_unpin_work *work;
9779 struct intel_engine_cs *ring;
9780 int ret;
9781
9782 /*
9783 * drm_mode_page_flip_ioctl() should already catch this, but double
9784 * check to be safe. In the future we may enable pageflipping from
9785 * a disabled primary plane.
9786 */
9787 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9788 return -EBUSY;
9789
9790 /* Can't change pixel format via MI display flips. */
9791 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9792 return -EINVAL;
9793
9794 /*
9795 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9796 * Note that pitch changes could also affect these register.
9797 */
9798 if (INTEL_INFO(dev)->gen > 3 &&
9799 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9800 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9801 return -EINVAL;
9802
9803 if (i915_terminally_wedged(&dev_priv->gpu_error))
9804 goto out_hang;
9805
9806 work = kzalloc(sizeof(*work), GFP_KERNEL);
9807 if (work == NULL)
9808 return -ENOMEM;
9809
9810 work->event = event;
9811 work->crtc = crtc;
9812 work->old_fb = old_fb;
9813 INIT_WORK(&work->work, intel_unpin_work_fn);
9814
9815 ret = drm_crtc_vblank_get(crtc);
9816 if (ret)
9817 goto free_work;
9818
9819 /* We borrow the event spin lock for protecting unpin_work */
9820 spin_lock_irq(&dev->event_lock);
9821 if (intel_crtc->unpin_work) {
9822 /* Before declaring the flip queue wedged, check if
9823 * the hardware completed the operation behind our backs.
9824 */
9825 if (__intel_pageflip_stall_check(dev, crtc)) {
9826 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9827 page_flip_completed(intel_crtc);
9828 } else {
9829 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9830 spin_unlock_irq(&dev->event_lock);
9831
9832 drm_crtc_vblank_put(crtc);
9833 kfree(work);
9834 return -EBUSY;
9835 }
9836 }
9837 intel_crtc->unpin_work = work;
9838 spin_unlock_irq(&dev->event_lock);
9839
9840 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9841 flush_workqueue(dev_priv->wq);
9842
9843 ret = i915_mutex_lock_interruptible(dev);
9844 if (ret)
9845 goto cleanup;
9846
9847 /* Reference the objects for the scheduled work. */
9848 drm_framebuffer_reference(work->old_fb);
9849 drm_gem_object_reference(&obj->base);
9850
9851 crtc->primary->fb = fb;
9852 update_state_fb(crtc->primary);
9853
9854 work->pending_flip_obj = obj;
9855
9856 atomic_inc(&intel_crtc->unpin_work_count);
9857 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9858
9859 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9860 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9861
9862 if (IS_VALLEYVIEW(dev)) {
9863 ring = &dev_priv->ring[BCS];
9864 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9865 /* vlv: DISPLAY_FLIP fails to change tiling */
9866 ring = NULL;
9867 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9868 ring = &dev_priv->ring[BCS];
9869 } else if (INTEL_INFO(dev)->gen >= 7) {
9870 ring = i915_gem_request_get_ring(obj->last_read_req);
9871 if (ring == NULL || ring->id != RCS)
9872 ring = &dev_priv->ring[BCS];
9873 } else {
9874 ring = &dev_priv->ring[RCS];
9875 }
9876
9877 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9878 if (ret)
9879 goto cleanup_pending;
9880
9881 work->gtt_offset =
9882 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9883
9884 if (use_mmio_flip(ring, obj)) {
9885 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9886 page_flip_flags);
9887 if (ret)
9888 goto cleanup_unpin;
9889
9890 i915_gem_request_assign(&work->flip_queued_req,
9891 obj->last_write_req);
9892 } else {
9893 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9894 page_flip_flags);
9895 if (ret)
9896 goto cleanup_unpin;
9897
9898 i915_gem_request_assign(&work->flip_queued_req,
9899 intel_ring_get_request(ring));
9900 }
9901
9902 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9903 work->enable_stall_check = true;
9904
9905 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9906 INTEL_FRONTBUFFER_PRIMARY(pipe));
9907
9908 intel_fbc_disable(dev);
9909 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9910 mutex_unlock(&dev->struct_mutex);
9911
9912 trace_i915_flip_request(intel_crtc->plane, obj);
9913
9914 return 0;
9915
9916 cleanup_unpin:
9917 intel_unpin_fb_obj(obj);
9918 cleanup_pending:
9919 atomic_dec(&intel_crtc->unpin_work_count);
9920 crtc->primary->fb = old_fb;
9921 update_state_fb(crtc->primary);
9922 drm_framebuffer_unreference(work->old_fb);
9923 drm_gem_object_unreference(&obj->base);
9924 mutex_unlock(&dev->struct_mutex);
9925
9926 cleanup:
9927 spin_lock_irq(&dev->event_lock);
9928 intel_crtc->unpin_work = NULL;
9929 spin_unlock_irq(&dev->event_lock);
9930
9931 drm_crtc_vblank_put(crtc);
9932 free_work:
9933 kfree(work);
9934
9935 if (ret == -EIO) {
9936 out_hang:
9937 ret = intel_plane_restore(primary);
9938 if (ret == 0 && event) {
9939 spin_lock_irq(&dev->event_lock);
9940 drm_send_vblank_event(dev, pipe, event);
9941 spin_unlock_irq(&dev->event_lock);
9942 }
9943 }
9944 return ret;
9945 }
9946
9947 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9948 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9949 .load_lut = intel_crtc_load_lut,
9950 .atomic_begin = intel_begin_crtc_commit,
9951 .atomic_flush = intel_finish_crtc_commit,
9952 };
9953
9954 /**
9955 * intel_modeset_update_staged_output_state
9956 *
9957 * Updates the staged output configuration state, e.g. after we've read out the
9958 * current hw state.
9959 */
9960 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9961 {
9962 struct intel_crtc *crtc;
9963 struct intel_encoder *encoder;
9964 struct intel_connector *connector;
9965
9966 list_for_each_entry(connector, &dev->mode_config.connector_list,
9967 base.head) {
9968 connector->new_encoder =
9969 to_intel_encoder(connector->base.encoder);
9970 }
9971
9972 for_each_intel_encoder(dev, encoder) {
9973 encoder->new_crtc =
9974 to_intel_crtc(encoder->base.crtc);
9975 }
9976
9977 for_each_intel_crtc(dev, crtc) {
9978 crtc->new_enabled = crtc->base.enabled;
9979
9980 if (crtc->new_enabled)
9981 crtc->new_config = crtc->config;
9982 else
9983 crtc->new_config = NULL;
9984 }
9985 }
9986
9987 /**
9988 * intel_modeset_commit_output_state
9989 *
9990 * This function copies the stage display pipe configuration to the real one.
9991 */
9992 static void intel_modeset_commit_output_state(struct drm_device *dev)
9993 {
9994 struct intel_crtc *crtc;
9995 struct intel_encoder *encoder;
9996 struct intel_connector *connector;
9997
9998 list_for_each_entry(connector, &dev->mode_config.connector_list,
9999 base.head) {
10000 connector->base.encoder = &connector->new_encoder->base;
10001 }
10002
10003 for_each_intel_encoder(dev, encoder) {
10004 encoder->base.crtc = &encoder->new_crtc->base;
10005 }
10006
10007 for_each_intel_crtc(dev, crtc) {
10008 crtc->base.enabled = crtc->new_enabled;
10009 }
10010 }
10011
10012 static void
10013 connected_sink_compute_bpp(struct intel_connector *connector,
10014 struct intel_crtc_state *pipe_config)
10015 {
10016 int bpp = pipe_config->pipe_bpp;
10017
10018 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10019 connector->base.base.id,
10020 connector->base.name);
10021
10022 /* Don't use an invalid EDID bpc value */
10023 if (connector->base.display_info.bpc &&
10024 connector->base.display_info.bpc * 3 < bpp) {
10025 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10026 bpp, connector->base.display_info.bpc*3);
10027 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10028 }
10029
10030 /* Clamp bpp to 8 on screens without EDID 1.4 */
10031 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10032 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10033 bpp);
10034 pipe_config->pipe_bpp = 24;
10035 }
10036 }
10037
10038 static int
10039 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10040 struct drm_framebuffer *fb,
10041 struct intel_crtc_state *pipe_config)
10042 {
10043 struct drm_device *dev = crtc->base.dev;
10044 struct intel_connector *connector;
10045 int bpp;
10046
10047 switch (fb->pixel_format) {
10048 case DRM_FORMAT_C8:
10049 bpp = 8*3; /* since we go through a colormap */
10050 break;
10051 case DRM_FORMAT_XRGB1555:
10052 case DRM_FORMAT_ARGB1555:
10053 /* checked in intel_framebuffer_init already */
10054 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10055 return -EINVAL;
10056 case DRM_FORMAT_RGB565:
10057 bpp = 6*3; /* min is 18bpp */
10058 break;
10059 case DRM_FORMAT_XBGR8888:
10060 case DRM_FORMAT_ABGR8888:
10061 /* checked in intel_framebuffer_init already */
10062 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10063 return -EINVAL;
10064 case DRM_FORMAT_XRGB8888:
10065 case DRM_FORMAT_ARGB8888:
10066 bpp = 8*3;
10067 break;
10068 case DRM_FORMAT_XRGB2101010:
10069 case DRM_FORMAT_ARGB2101010:
10070 case DRM_FORMAT_XBGR2101010:
10071 case DRM_FORMAT_ABGR2101010:
10072 /* checked in intel_framebuffer_init already */
10073 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10074 return -EINVAL;
10075 bpp = 10*3;
10076 break;
10077 /* TODO: gen4+ supports 16 bpc floating point, too. */
10078 default:
10079 DRM_DEBUG_KMS("unsupported depth\n");
10080 return -EINVAL;
10081 }
10082
10083 pipe_config->pipe_bpp = bpp;
10084
10085 /* Clamp display bpp to EDID value */
10086 list_for_each_entry(connector, &dev->mode_config.connector_list,
10087 base.head) {
10088 if (!connector->new_encoder ||
10089 connector->new_encoder->new_crtc != crtc)
10090 continue;
10091
10092 connected_sink_compute_bpp(connector, pipe_config);
10093 }
10094
10095 return bpp;
10096 }
10097
10098 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10099 {
10100 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10101 "type: 0x%x flags: 0x%x\n",
10102 mode->crtc_clock,
10103 mode->crtc_hdisplay, mode->crtc_hsync_start,
10104 mode->crtc_hsync_end, mode->crtc_htotal,
10105 mode->crtc_vdisplay, mode->crtc_vsync_start,
10106 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10107 }
10108
10109 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10110 struct intel_crtc_state *pipe_config,
10111 const char *context)
10112 {
10113 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10114 context, pipe_name(crtc->pipe));
10115
10116 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10117 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10118 pipe_config->pipe_bpp, pipe_config->dither);
10119 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10120 pipe_config->has_pch_encoder,
10121 pipe_config->fdi_lanes,
10122 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10123 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10124 pipe_config->fdi_m_n.tu);
10125 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10126 pipe_config->has_dp_encoder,
10127 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10128 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10129 pipe_config->dp_m_n.tu);
10130
10131 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10132 pipe_config->has_dp_encoder,
10133 pipe_config->dp_m2_n2.gmch_m,
10134 pipe_config->dp_m2_n2.gmch_n,
10135 pipe_config->dp_m2_n2.link_m,
10136 pipe_config->dp_m2_n2.link_n,
10137 pipe_config->dp_m2_n2.tu);
10138
10139 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10140 pipe_config->has_audio,
10141 pipe_config->has_infoframe);
10142
10143 DRM_DEBUG_KMS("requested mode:\n");
10144 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10145 DRM_DEBUG_KMS("adjusted mode:\n");
10146 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10147 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10148 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10149 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10150 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10151 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10152 pipe_config->gmch_pfit.control,
10153 pipe_config->gmch_pfit.pgm_ratios,
10154 pipe_config->gmch_pfit.lvds_border_bits);
10155 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10156 pipe_config->pch_pfit.pos,
10157 pipe_config->pch_pfit.size,
10158 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10159 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10160 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10161 }
10162
10163 static bool encoders_cloneable(const struct intel_encoder *a,
10164 const struct intel_encoder *b)
10165 {
10166 /* masks could be asymmetric, so check both ways */
10167 return a == b || (a->cloneable & (1 << b->type) &&
10168 b->cloneable & (1 << a->type));
10169 }
10170
10171 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10172 struct intel_encoder *encoder)
10173 {
10174 struct drm_device *dev = crtc->base.dev;
10175 struct intel_encoder *source_encoder;
10176
10177 for_each_intel_encoder(dev, source_encoder) {
10178 if (source_encoder->new_crtc != crtc)
10179 continue;
10180
10181 if (!encoders_cloneable(encoder, source_encoder))
10182 return false;
10183 }
10184
10185 return true;
10186 }
10187
10188 static bool check_encoder_cloning(struct intel_crtc *crtc)
10189 {
10190 struct drm_device *dev = crtc->base.dev;
10191 struct intel_encoder *encoder;
10192
10193 for_each_intel_encoder(dev, encoder) {
10194 if (encoder->new_crtc != crtc)
10195 continue;
10196
10197 if (!check_single_encoder_cloning(crtc, encoder))
10198 return false;
10199 }
10200
10201 return true;
10202 }
10203
10204 static bool check_digital_port_conflicts(struct drm_device *dev)
10205 {
10206 struct intel_connector *connector;
10207 unsigned int used_ports = 0;
10208
10209 /*
10210 * Walk the connector list instead of the encoder
10211 * list to detect the problem on ddi platforms
10212 * where there's just one encoder per digital port.
10213 */
10214 list_for_each_entry(connector,
10215 &dev->mode_config.connector_list, base.head) {
10216 struct intel_encoder *encoder = connector->new_encoder;
10217
10218 if (!encoder)
10219 continue;
10220
10221 WARN_ON(!encoder->new_crtc);
10222
10223 switch (encoder->type) {
10224 unsigned int port_mask;
10225 case INTEL_OUTPUT_UNKNOWN:
10226 if (WARN_ON(!HAS_DDI(dev)))
10227 break;
10228 case INTEL_OUTPUT_DISPLAYPORT:
10229 case INTEL_OUTPUT_HDMI:
10230 case INTEL_OUTPUT_EDP:
10231 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10232
10233 /* the same port mustn't appear more than once */
10234 if (used_ports & port_mask)
10235 return false;
10236
10237 used_ports |= port_mask;
10238 default:
10239 break;
10240 }
10241 }
10242
10243 return true;
10244 }
10245
10246 static struct intel_crtc_state *
10247 intel_modeset_pipe_config(struct drm_crtc *crtc,
10248 struct drm_framebuffer *fb,
10249 struct drm_display_mode *mode)
10250 {
10251 struct drm_device *dev = crtc->dev;
10252 struct intel_encoder *encoder;
10253 struct intel_crtc_state *pipe_config;
10254 int plane_bpp, ret = -EINVAL;
10255 bool retry = true;
10256
10257 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10258 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10259 return ERR_PTR(-EINVAL);
10260 }
10261
10262 if (!check_digital_port_conflicts(dev)) {
10263 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10264 return ERR_PTR(-EINVAL);
10265 }
10266
10267 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10268 if (!pipe_config)
10269 return ERR_PTR(-ENOMEM);
10270
10271 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10272 drm_mode_copy(&pipe_config->base.mode, mode);
10273
10274 pipe_config->cpu_transcoder =
10275 (enum transcoder) to_intel_crtc(crtc)->pipe;
10276 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10277
10278 /*
10279 * Sanitize sync polarity flags based on requested ones. If neither
10280 * positive or negative polarity is requested, treat this as meaning
10281 * negative polarity.
10282 */
10283 if (!(pipe_config->base.adjusted_mode.flags &
10284 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10285 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10286
10287 if (!(pipe_config->base.adjusted_mode.flags &
10288 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10289 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10290
10291 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10292 * plane pixel format and any sink constraints into account. Returns the
10293 * source plane bpp so that dithering can be selected on mismatches
10294 * after encoders and crtc also have had their say. */
10295 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10296 fb, pipe_config);
10297 if (plane_bpp < 0)
10298 goto fail;
10299
10300 /*
10301 * Determine the real pipe dimensions. Note that stereo modes can
10302 * increase the actual pipe size due to the frame doubling and
10303 * insertion of additional space for blanks between the frame. This
10304 * is stored in the crtc timings. We use the requested mode to do this
10305 * computation to clearly distinguish it from the adjusted mode, which
10306 * can be changed by the connectors in the below retry loop.
10307 */
10308 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10309 &pipe_config->pipe_src_w,
10310 &pipe_config->pipe_src_h);
10311
10312 encoder_retry:
10313 /* Ensure the port clock defaults are reset when retrying. */
10314 pipe_config->port_clock = 0;
10315 pipe_config->pixel_multiplier = 1;
10316
10317 /* Fill in default crtc timings, allow encoders to overwrite them. */
10318 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10319 CRTC_STEREO_DOUBLE);
10320
10321 /* Pass our mode to the connectors and the CRTC to give them a chance to
10322 * adjust it according to limitations or connector properties, and also
10323 * a chance to reject the mode entirely.
10324 */
10325 for_each_intel_encoder(dev, encoder) {
10326
10327 if (&encoder->new_crtc->base != crtc)
10328 continue;
10329
10330 if (!(encoder->compute_config(encoder, pipe_config))) {
10331 DRM_DEBUG_KMS("Encoder config failure\n");
10332 goto fail;
10333 }
10334 }
10335
10336 /* Set default port clock if not overwritten by the encoder. Needs to be
10337 * done afterwards in case the encoder adjusts the mode. */
10338 if (!pipe_config->port_clock)
10339 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10340 * pipe_config->pixel_multiplier;
10341
10342 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10343 if (ret < 0) {
10344 DRM_DEBUG_KMS("CRTC fixup failed\n");
10345 goto fail;
10346 }
10347
10348 if (ret == RETRY) {
10349 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10350 ret = -EINVAL;
10351 goto fail;
10352 }
10353
10354 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10355 retry = false;
10356 goto encoder_retry;
10357 }
10358
10359 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10360 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10361 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10362
10363 return pipe_config;
10364 fail:
10365 kfree(pipe_config);
10366 return ERR_PTR(ret);
10367 }
10368
10369 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10370 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10371 static void
10372 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10373 unsigned *prepare_pipes, unsigned *disable_pipes)
10374 {
10375 struct intel_crtc *intel_crtc;
10376 struct drm_device *dev = crtc->dev;
10377 struct intel_encoder *encoder;
10378 struct intel_connector *connector;
10379 struct drm_crtc *tmp_crtc;
10380
10381 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10382
10383 /* Check which crtcs have changed outputs connected to them, these need
10384 * to be part of the prepare_pipes mask. We don't (yet) support global
10385 * modeset across multiple crtcs, so modeset_pipes will only have one
10386 * bit set at most. */
10387 list_for_each_entry(connector, &dev->mode_config.connector_list,
10388 base.head) {
10389 if (connector->base.encoder == &connector->new_encoder->base)
10390 continue;
10391
10392 if (connector->base.encoder) {
10393 tmp_crtc = connector->base.encoder->crtc;
10394
10395 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10396 }
10397
10398 if (connector->new_encoder)
10399 *prepare_pipes |=
10400 1 << connector->new_encoder->new_crtc->pipe;
10401 }
10402
10403 for_each_intel_encoder(dev, encoder) {
10404 if (encoder->base.crtc == &encoder->new_crtc->base)
10405 continue;
10406
10407 if (encoder->base.crtc) {
10408 tmp_crtc = encoder->base.crtc;
10409
10410 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10411 }
10412
10413 if (encoder->new_crtc)
10414 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10415 }
10416
10417 /* Check for pipes that will be enabled/disabled ... */
10418 for_each_intel_crtc(dev, intel_crtc) {
10419 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10420 continue;
10421
10422 if (!intel_crtc->new_enabled)
10423 *disable_pipes |= 1 << intel_crtc->pipe;
10424 else
10425 *prepare_pipes |= 1 << intel_crtc->pipe;
10426 }
10427
10428
10429 /* set_mode is also used to update properties on life display pipes. */
10430 intel_crtc = to_intel_crtc(crtc);
10431 if (intel_crtc->new_enabled)
10432 *prepare_pipes |= 1 << intel_crtc->pipe;
10433
10434 /*
10435 * For simplicity do a full modeset on any pipe where the output routing
10436 * changed. We could be more clever, but that would require us to be
10437 * more careful with calling the relevant encoder->mode_set functions.
10438 */
10439 if (*prepare_pipes)
10440 *modeset_pipes = *prepare_pipes;
10441
10442 /* ... and mask these out. */
10443 *modeset_pipes &= ~(*disable_pipes);
10444 *prepare_pipes &= ~(*disable_pipes);
10445
10446 /*
10447 * HACK: We don't (yet) fully support global modesets. intel_set_config
10448 * obies this rule, but the modeset restore mode of
10449 * intel_modeset_setup_hw_state does not.
10450 */
10451 *modeset_pipes &= 1 << intel_crtc->pipe;
10452 *prepare_pipes &= 1 << intel_crtc->pipe;
10453
10454 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10455 *modeset_pipes, *prepare_pipes, *disable_pipes);
10456 }
10457
10458 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10459 {
10460 struct drm_encoder *encoder;
10461 struct drm_device *dev = crtc->dev;
10462
10463 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10464 if (encoder->crtc == crtc)
10465 return true;
10466
10467 return false;
10468 }
10469
10470 static void
10471 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10472 {
10473 struct drm_i915_private *dev_priv = dev->dev_private;
10474 struct intel_encoder *intel_encoder;
10475 struct intel_crtc *intel_crtc;
10476 struct drm_connector *connector;
10477
10478 intel_shared_dpll_commit(dev_priv);
10479
10480 for_each_intel_encoder(dev, intel_encoder) {
10481 if (!intel_encoder->base.crtc)
10482 continue;
10483
10484 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10485
10486 if (prepare_pipes & (1 << intel_crtc->pipe))
10487 intel_encoder->connectors_active = false;
10488 }
10489
10490 intel_modeset_commit_output_state(dev);
10491
10492 /* Double check state. */
10493 for_each_intel_crtc(dev, intel_crtc) {
10494 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10495 WARN_ON(intel_crtc->new_config &&
10496 intel_crtc->new_config != intel_crtc->config);
10497 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10498 }
10499
10500 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10501 if (!connector->encoder || !connector->encoder->crtc)
10502 continue;
10503
10504 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10505
10506 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10507 struct drm_property *dpms_property =
10508 dev->mode_config.dpms_property;
10509
10510 connector->dpms = DRM_MODE_DPMS_ON;
10511 drm_object_property_set_value(&connector->base,
10512 dpms_property,
10513 DRM_MODE_DPMS_ON);
10514
10515 intel_encoder = to_intel_encoder(connector->encoder);
10516 intel_encoder->connectors_active = true;
10517 }
10518 }
10519
10520 }
10521
10522 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10523 {
10524 int diff;
10525
10526 if (clock1 == clock2)
10527 return true;
10528
10529 if (!clock1 || !clock2)
10530 return false;
10531
10532 diff = abs(clock1 - clock2);
10533
10534 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10535 return true;
10536
10537 return false;
10538 }
10539
10540 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10541 list_for_each_entry((intel_crtc), \
10542 &(dev)->mode_config.crtc_list, \
10543 base.head) \
10544 if (mask & (1 <<(intel_crtc)->pipe))
10545
10546 static bool
10547 intel_pipe_config_compare(struct drm_device *dev,
10548 struct intel_crtc_state *current_config,
10549 struct intel_crtc_state *pipe_config)
10550 {
10551 #define PIPE_CONF_CHECK_X(name) \
10552 if (current_config->name != pipe_config->name) { \
10553 DRM_ERROR("mismatch in " #name " " \
10554 "(expected 0x%08x, found 0x%08x)\n", \
10555 current_config->name, \
10556 pipe_config->name); \
10557 return false; \
10558 }
10559
10560 #define PIPE_CONF_CHECK_I(name) \
10561 if (current_config->name != pipe_config->name) { \
10562 DRM_ERROR("mismatch in " #name " " \
10563 "(expected %i, found %i)\n", \
10564 current_config->name, \
10565 pipe_config->name); \
10566 return false; \
10567 }
10568
10569 /* This is required for BDW+ where there is only one set of registers for
10570 * switching between high and low RR.
10571 * This macro can be used whenever a comparison has to be made between one
10572 * hw state and multiple sw state variables.
10573 */
10574 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10575 if ((current_config->name != pipe_config->name) && \
10576 (current_config->alt_name != pipe_config->name)) { \
10577 DRM_ERROR("mismatch in " #name " " \
10578 "(expected %i or %i, found %i)\n", \
10579 current_config->name, \
10580 current_config->alt_name, \
10581 pipe_config->name); \
10582 return false; \
10583 }
10584
10585 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10586 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10587 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10588 "(expected %i, found %i)\n", \
10589 current_config->name & (mask), \
10590 pipe_config->name & (mask)); \
10591 return false; \
10592 }
10593
10594 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10595 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10596 DRM_ERROR("mismatch in " #name " " \
10597 "(expected %i, found %i)\n", \
10598 current_config->name, \
10599 pipe_config->name); \
10600 return false; \
10601 }
10602
10603 #define PIPE_CONF_QUIRK(quirk) \
10604 ((current_config->quirks | pipe_config->quirks) & (quirk))
10605
10606 PIPE_CONF_CHECK_I(cpu_transcoder);
10607
10608 PIPE_CONF_CHECK_I(has_pch_encoder);
10609 PIPE_CONF_CHECK_I(fdi_lanes);
10610 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10611 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10612 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10613 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10614 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10615
10616 PIPE_CONF_CHECK_I(has_dp_encoder);
10617
10618 if (INTEL_INFO(dev)->gen < 8) {
10619 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10620 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10621 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10622 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10623 PIPE_CONF_CHECK_I(dp_m_n.tu);
10624
10625 if (current_config->has_drrs) {
10626 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10627 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10628 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10629 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10630 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10631 }
10632 } else {
10633 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10634 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10635 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10636 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10637 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10638 }
10639
10640 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10641 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10642 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10643 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10644 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10645 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10646
10647 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10648 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10649 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10650 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10651 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10652 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10653
10654 PIPE_CONF_CHECK_I(pixel_multiplier);
10655 PIPE_CONF_CHECK_I(has_hdmi_sink);
10656 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10657 IS_VALLEYVIEW(dev))
10658 PIPE_CONF_CHECK_I(limited_color_range);
10659 PIPE_CONF_CHECK_I(has_infoframe);
10660
10661 PIPE_CONF_CHECK_I(has_audio);
10662
10663 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10664 DRM_MODE_FLAG_INTERLACE);
10665
10666 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10667 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10668 DRM_MODE_FLAG_PHSYNC);
10669 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10670 DRM_MODE_FLAG_NHSYNC);
10671 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10672 DRM_MODE_FLAG_PVSYNC);
10673 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10674 DRM_MODE_FLAG_NVSYNC);
10675 }
10676
10677 PIPE_CONF_CHECK_I(pipe_src_w);
10678 PIPE_CONF_CHECK_I(pipe_src_h);
10679
10680 /*
10681 * FIXME: BIOS likes to set up a cloned config with lvds+external
10682 * screen. Since we don't yet re-compute the pipe config when moving
10683 * just the lvds port away to another pipe the sw tracking won't match.
10684 *
10685 * Proper atomic modesets with recomputed global state will fix this.
10686 * Until then just don't check gmch state for inherited modes.
10687 */
10688 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10689 PIPE_CONF_CHECK_I(gmch_pfit.control);
10690 /* pfit ratios are autocomputed by the hw on gen4+ */
10691 if (INTEL_INFO(dev)->gen < 4)
10692 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10693 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10694 }
10695
10696 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10697 if (current_config->pch_pfit.enabled) {
10698 PIPE_CONF_CHECK_I(pch_pfit.pos);
10699 PIPE_CONF_CHECK_I(pch_pfit.size);
10700 }
10701
10702 /* BDW+ don't expose a synchronous way to read the state */
10703 if (IS_HASWELL(dev))
10704 PIPE_CONF_CHECK_I(ips_enabled);
10705
10706 PIPE_CONF_CHECK_I(double_wide);
10707
10708 PIPE_CONF_CHECK_X(ddi_pll_sel);
10709
10710 PIPE_CONF_CHECK_I(shared_dpll);
10711 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10712 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10713 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10714 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10715 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10716 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10717 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10718 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10719
10720 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10721 PIPE_CONF_CHECK_I(pipe_bpp);
10722
10723 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10724 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10725
10726 #undef PIPE_CONF_CHECK_X
10727 #undef PIPE_CONF_CHECK_I
10728 #undef PIPE_CONF_CHECK_I_ALT
10729 #undef PIPE_CONF_CHECK_FLAGS
10730 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10731 #undef PIPE_CONF_QUIRK
10732
10733 return true;
10734 }
10735
10736 static void check_wm_state(struct drm_device *dev)
10737 {
10738 struct drm_i915_private *dev_priv = dev->dev_private;
10739 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10740 struct intel_crtc *intel_crtc;
10741 int plane;
10742
10743 if (INTEL_INFO(dev)->gen < 9)
10744 return;
10745
10746 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10747 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10748
10749 for_each_intel_crtc(dev, intel_crtc) {
10750 struct skl_ddb_entry *hw_entry, *sw_entry;
10751 const enum pipe pipe = intel_crtc->pipe;
10752
10753 if (!intel_crtc->active)
10754 continue;
10755
10756 /* planes */
10757 for_each_plane(pipe, plane) {
10758 hw_entry = &hw_ddb.plane[pipe][plane];
10759 sw_entry = &sw_ddb->plane[pipe][plane];
10760
10761 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10762 continue;
10763
10764 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10765 "(expected (%u,%u), found (%u,%u))\n",
10766 pipe_name(pipe), plane + 1,
10767 sw_entry->start, sw_entry->end,
10768 hw_entry->start, hw_entry->end);
10769 }
10770
10771 /* cursor */
10772 hw_entry = &hw_ddb.cursor[pipe];
10773 sw_entry = &sw_ddb->cursor[pipe];
10774
10775 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10776 continue;
10777
10778 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10779 "(expected (%u,%u), found (%u,%u))\n",
10780 pipe_name(pipe),
10781 sw_entry->start, sw_entry->end,
10782 hw_entry->start, hw_entry->end);
10783 }
10784 }
10785
10786 static void
10787 check_connector_state(struct drm_device *dev)
10788 {
10789 struct intel_connector *connector;
10790
10791 list_for_each_entry(connector, &dev->mode_config.connector_list,
10792 base.head) {
10793 /* This also checks the encoder/connector hw state with the
10794 * ->get_hw_state callbacks. */
10795 intel_connector_check_state(connector);
10796
10797 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10798 "connector's staged encoder doesn't match current encoder\n");
10799 }
10800 }
10801
10802 static void
10803 check_encoder_state(struct drm_device *dev)
10804 {
10805 struct intel_encoder *encoder;
10806 struct intel_connector *connector;
10807
10808 for_each_intel_encoder(dev, encoder) {
10809 bool enabled = false;
10810 bool active = false;
10811 enum pipe pipe, tracked_pipe;
10812
10813 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10814 encoder->base.base.id,
10815 encoder->base.name);
10816
10817 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10818 "encoder's stage crtc doesn't match current crtc\n");
10819 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10820 "encoder's active_connectors set, but no crtc\n");
10821
10822 list_for_each_entry(connector, &dev->mode_config.connector_list,
10823 base.head) {
10824 if (connector->base.encoder != &encoder->base)
10825 continue;
10826 enabled = true;
10827 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10828 active = true;
10829 }
10830 /*
10831 * for MST connectors if we unplug the connector is gone
10832 * away but the encoder is still connected to a crtc
10833 * until a modeset happens in response to the hotplug.
10834 */
10835 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10836 continue;
10837
10838 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10839 "encoder's enabled state mismatch "
10840 "(expected %i, found %i)\n",
10841 !!encoder->base.crtc, enabled);
10842 I915_STATE_WARN(active && !encoder->base.crtc,
10843 "active encoder with no crtc\n");
10844
10845 I915_STATE_WARN(encoder->connectors_active != active,
10846 "encoder's computed active state doesn't match tracked active state "
10847 "(expected %i, found %i)\n", active, encoder->connectors_active);
10848
10849 active = encoder->get_hw_state(encoder, &pipe);
10850 I915_STATE_WARN(active != encoder->connectors_active,
10851 "encoder's hw state doesn't match sw tracking "
10852 "(expected %i, found %i)\n",
10853 encoder->connectors_active, active);
10854
10855 if (!encoder->base.crtc)
10856 continue;
10857
10858 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10859 I915_STATE_WARN(active && pipe != tracked_pipe,
10860 "active encoder's pipe doesn't match"
10861 "(expected %i, found %i)\n",
10862 tracked_pipe, pipe);
10863
10864 }
10865 }
10866
10867 static void
10868 check_crtc_state(struct drm_device *dev)
10869 {
10870 struct drm_i915_private *dev_priv = dev->dev_private;
10871 struct intel_crtc *crtc;
10872 struct intel_encoder *encoder;
10873 struct intel_crtc_state pipe_config;
10874
10875 for_each_intel_crtc(dev, crtc) {
10876 bool enabled = false;
10877 bool active = false;
10878
10879 memset(&pipe_config, 0, sizeof(pipe_config));
10880
10881 DRM_DEBUG_KMS("[CRTC:%d]\n",
10882 crtc->base.base.id);
10883
10884 I915_STATE_WARN(crtc->active && !crtc->base.enabled,
10885 "active crtc, but not enabled in sw tracking\n");
10886
10887 for_each_intel_encoder(dev, encoder) {
10888 if (encoder->base.crtc != &crtc->base)
10889 continue;
10890 enabled = true;
10891 if (encoder->connectors_active)
10892 active = true;
10893 }
10894
10895 I915_STATE_WARN(active != crtc->active,
10896 "crtc's computed active state doesn't match tracked active state "
10897 "(expected %i, found %i)\n", active, crtc->active);
10898 I915_STATE_WARN(enabled != crtc->base.enabled,
10899 "crtc's computed enabled state doesn't match tracked enabled state "
10900 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10901
10902 active = dev_priv->display.get_pipe_config(crtc,
10903 &pipe_config);
10904
10905 /* hw state is inconsistent with the pipe quirk */
10906 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10907 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10908 active = crtc->active;
10909
10910 for_each_intel_encoder(dev, encoder) {
10911 enum pipe pipe;
10912 if (encoder->base.crtc != &crtc->base)
10913 continue;
10914 if (encoder->get_hw_state(encoder, &pipe))
10915 encoder->get_config(encoder, &pipe_config);
10916 }
10917
10918 I915_STATE_WARN(crtc->active != active,
10919 "crtc active state doesn't match with hw state "
10920 "(expected %i, found %i)\n", crtc->active, active);
10921
10922 if (active &&
10923 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10924 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10925 intel_dump_pipe_config(crtc, &pipe_config,
10926 "[hw state]");
10927 intel_dump_pipe_config(crtc, crtc->config,
10928 "[sw state]");
10929 }
10930 }
10931 }
10932
10933 static void
10934 check_shared_dpll_state(struct drm_device *dev)
10935 {
10936 struct drm_i915_private *dev_priv = dev->dev_private;
10937 struct intel_crtc *crtc;
10938 struct intel_dpll_hw_state dpll_hw_state;
10939 int i;
10940
10941 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10942 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10943 int enabled_crtcs = 0, active_crtcs = 0;
10944 bool active;
10945
10946 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10947
10948 DRM_DEBUG_KMS("%s\n", pll->name);
10949
10950 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10951
10952 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10953 "more active pll users than references: %i vs %i\n",
10954 pll->active, hweight32(pll->config.crtc_mask));
10955 I915_STATE_WARN(pll->active && !pll->on,
10956 "pll in active use but not on in sw tracking\n");
10957 I915_STATE_WARN(pll->on && !pll->active,
10958 "pll in on but not on in use in sw tracking\n");
10959 I915_STATE_WARN(pll->on != active,
10960 "pll on state mismatch (expected %i, found %i)\n",
10961 pll->on, active);
10962
10963 for_each_intel_crtc(dev, crtc) {
10964 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10965 enabled_crtcs++;
10966 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10967 active_crtcs++;
10968 }
10969 I915_STATE_WARN(pll->active != active_crtcs,
10970 "pll active crtcs mismatch (expected %i, found %i)\n",
10971 pll->active, active_crtcs);
10972 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10973 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10974 hweight32(pll->config.crtc_mask), enabled_crtcs);
10975
10976 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10977 sizeof(dpll_hw_state)),
10978 "pll hw state mismatch\n");
10979 }
10980 }
10981
10982 void
10983 intel_modeset_check_state(struct drm_device *dev)
10984 {
10985 check_wm_state(dev);
10986 check_connector_state(dev);
10987 check_encoder_state(dev);
10988 check_crtc_state(dev);
10989 check_shared_dpll_state(dev);
10990 }
10991
10992 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10993 int dotclock)
10994 {
10995 /*
10996 * FDI already provided one idea for the dotclock.
10997 * Yell if the encoder disagrees.
10998 */
10999 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11000 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11001 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11002 }
11003
11004 static void update_scanline_offset(struct intel_crtc *crtc)
11005 {
11006 struct drm_device *dev = crtc->base.dev;
11007
11008 /*
11009 * The scanline counter increments at the leading edge of hsync.
11010 *
11011 * On most platforms it starts counting from vtotal-1 on the
11012 * first active line. That means the scanline counter value is
11013 * always one less than what we would expect. Ie. just after
11014 * start of vblank, which also occurs at start of hsync (on the
11015 * last active line), the scanline counter will read vblank_start-1.
11016 *
11017 * On gen2 the scanline counter starts counting from 1 instead
11018 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11019 * to keep the value positive), instead of adding one.
11020 *
11021 * On HSW+ the behaviour of the scanline counter depends on the output
11022 * type. For DP ports it behaves like most other platforms, but on HDMI
11023 * there's an extra 1 line difference. So we need to add two instead of
11024 * one to the value.
11025 */
11026 if (IS_GEN2(dev)) {
11027 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11028 int vtotal;
11029
11030 vtotal = mode->crtc_vtotal;
11031 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11032 vtotal /= 2;
11033
11034 crtc->scanline_offset = vtotal - 1;
11035 } else if (HAS_DDI(dev) &&
11036 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11037 crtc->scanline_offset = 2;
11038 } else
11039 crtc->scanline_offset = 1;
11040 }
11041
11042 static struct intel_crtc_state *
11043 intel_modeset_compute_config(struct drm_crtc *crtc,
11044 struct drm_display_mode *mode,
11045 struct drm_framebuffer *fb,
11046 unsigned *modeset_pipes,
11047 unsigned *prepare_pipes,
11048 unsigned *disable_pipes)
11049 {
11050 struct intel_crtc_state *pipe_config = NULL;
11051
11052 intel_modeset_affected_pipes(crtc, modeset_pipes,
11053 prepare_pipes, disable_pipes);
11054
11055 if ((*modeset_pipes) == 0)
11056 goto out;
11057
11058 /*
11059 * Note this needs changes when we start tracking multiple modes
11060 * and crtcs. At that point we'll need to compute the whole config
11061 * (i.e. one pipe_config for each crtc) rather than just the one
11062 * for this crtc.
11063 */
11064 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11065 if (IS_ERR(pipe_config)) {
11066 goto out;
11067 }
11068 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11069 "[modeset]");
11070
11071 out:
11072 return pipe_config;
11073 }
11074
11075 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11076 unsigned modeset_pipes,
11077 unsigned disable_pipes)
11078 {
11079 struct drm_i915_private *dev_priv = to_i915(dev);
11080 unsigned clear_pipes = modeset_pipes | disable_pipes;
11081 struct intel_crtc *intel_crtc;
11082 int ret = 0;
11083
11084 if (!dev_priv->display.crtc_compute_clock)
11085 return 0;
11086
11087 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11088 if (ret)
11089 goto done;
11090
11091 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11092 struct intel_crtc_state *state = intel_crtc->new_config;
11093 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11094 state);
11095 if (ret) {
11096 intel_shared_dpll_abort_config(dev_priv);
11097 goto done;
11098 }
11099 }
11100
11101 done:
11102 return ret;
11103 }
11104
11105 static int __intel_set_mode(struct drm_crtc *crtc,
11106 struct drm_display_mode *mode,
11107 int x, int y, struct drm_framebuffer *fb,
11108 struct intel_crtc_state *pipe_config,
11109 unsigned modeset_pipes,
11110 unsigned prepare_pipes,
11111 unsigned disable_pipes)
11112 {
11113 struct drm_device *dev = crtc->dev;
11114 struct drm_i915_private *dev_priv = dev->dev_private;
11115 struct drm_display_mode *saved_mode;
11116 struct intel_crtc *intel_crtc;
11117 int ret = 0;
11118
11119 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11120 if (!saved_mode)
11121 return -ENOMEM;
11122
11123 *saved_mode = crtc->mode;
11124
11125 if (modeset_pipes)
11126 to_intel_crtc(crtc)->new_config = pipe_config;
11127
11128 /*
11129 * See if the config requires any additional preparation, e.g.
11130 * to adjust global state with pipes off. We need to do this
11131 * here so we can get the modeset_pipe updated config for the new
11132 * mode set on this crtc. For other crtcs we need to use the
11133 * adjusted_mode bits in the crtc directly.
11134 */
11135 if (IS_VALLEYVIEW(dev)) {
11136 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11137
11138 /* may have added more to prepare_pipes than we should */
11139 prepare_pipes &= ~disable_pipes;
11140 }
11141
11142 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11143 if (ret)
11144 goto done;
11145
11146 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11147 intel_crtc_disable(&intel_crtc->base);
11148
11149 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11150 if (intel_crtc->base.enabled)
11151 dev_priv->display.crtc_disable(&intel_crtc->base);
11152 }
11153
11154 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11155 * to set it here already despite that we pass it down the callchain.
11156 *
11157 * Note we'll need to fix this up when we start tracking multiple
11158 * pipes; here we assume a single modeset_pipe and only track the
11159 * single crtc and mode.
11160 */
11161 if (modeset_pipes) {
11162 crtc->mode = *mode;
11163 /* mode_set/enable/disable functions rely on a correct pipe
11164 * config. */
11165 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11166
11167 /*
11168 * Calculate and store various constants which
11169 * are later needed by vblank and swap-completion
11170 * timestamping. They are derived from true hwmode.
11171 */
11172 drm_calc_timestamping_constants(crtc,
11173 &pipe_config->base.adjusted_mode);
11174 }
11175
11176 /* Only after disabling all output pipelines that will be changed can we
11177 * update the the output configuration. */
11178 intel_modeset_update_state(dev, prepare_pipes);
11179
11180 modeset_update_crtc_power_domains(dev);
11181
11182 /* Set up the DPLL and any encoders state that needs to adjust or depend
11183 * on the DPLL.
11184 */
11185 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11186 struct drm_plane *primary = intel_crtc->base.primary;
11187 int vdisplay, hdisplay;
11188
11189 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11190 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11191 fb, 0, 0,
11192 hdisplay, vdisplay,
11193 x << 16, y << 16,
11194 hdisplay << 16, vdisplay << 16);
11195 }
11196
11197 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11198 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11199 update_scanline_offset(intel_crtc);
11200
11201 dev_priv->display.crtc_enable(&intel_crtc->base);
11202 }
11203
11204 /* FIXME: add subpixel order */
11205 done:
11206 if (ret && crtc->enabled)
11207 crtc->mode = *saved_mode;
11208
11209 kfree(saved_mode);
11210 return ret;
11211 }
11212
11213 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11214 struct drm_display_mode *mode,
11215 int x, int y, struct drm_framebuffer *fb,
11216 struct intel_crtc_state *pipe_config,
11217 unsigned modeset_pipes,
11218 unsigned prepare_pipes,
11219 unsigned disable_pipes)
11220 {
11221 int ret;
11222
11223 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11224 prepare_pipes, disable_pipes);
11225
11226 if (ret == 0)
11227 intel_modeset_check_state(crtc->dev);
11228
11229 return ret;
11230 }
11231
11232 static int intel_set_mode(struct drm_crtc *crtc,
11233 struct drm_display_mode *mode,
11234 int x, int y, struct drm_framebuffer *fb)
11235 {
11236 struct intel_crtc_state *pipe_config;
11237 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11238
11239 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11240 &modeset_pipes,
11241 &prepare_pipes,
11242 &disable_pipes);
11243
11244 if (IS_ERR(pipe_config))
11245 return PTR_ERR(pipe_config);
11246
11247 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11248 modeset_pipes, prepare_pipes,
11249 disable_pipes);
11250 }
11251
11252 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11253 {
11254 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11255 }
11256
11257 #undef for_each_intel_crtc_masked
11258
11259 static void intel_set_config_free(struct intel_set_config *config)
11260 {
11261 if (!config)
11262 return;
11263
11264 kfree(config->save_connector_encoders);
11265 kfree(config->save_encoder_crtcs);
11266 kfree(config->save_crtc_enabled);
11267 kfree(config);
11268 }
11269
11270 static int intel_set_config_save_state(struct drm_device *dev,
11271 struct intel_set_config *config)
11272 {
11273 struct drm_crtc *crtc;
11274 struct drm_encoder *encoder;
11275 struct drm_connector *connector;
11276 int count;
11277
11278 config->save_crtc_enabled =
11279 kcalloc(dev->mode_config.num_crtc,
11280 sizeof(bool), GFP_KERNEL);
11281 if (!config->save_crtc_enabled)
11282 return -ENOMEM;
11283
11284 config->save_encoder_crtcs =
11285 kcalloc(dev->mode_config.num_encoder,
11286 sizeof(struct drm_crtc *), GFP_KERNEL);
11287 if (!config->save_encoder_crtcs)
11288 return -ENOMEM;
11289
11290 config->save_connector_encoders =
11291 kcalloc(dev->mode_config.num_connector,
11292 sizeof(struct drm_encoder *), GFP_KERNEL);
11293 if (!config->save_connector_encoders)
11294 return -ENOMEM;
11295
11296 /* Copy data. Note that driver private data is not affected.
11297 * Should anything bad happen only the expected state is
11298 * restored, not the drivers personal bookkeeping.
11299 */
11300 count = 0;
11301 for_each_crtc(dev, crtc) {
11302 config->save_crtc_enabled[count++] = crtc->enabled;
11303 }
11304
11305 count = 0;
11306 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11307 config->save_encoder_crtcs[count++] = encoder->crtc;
11308 }
11309
11310 count = 0;
11311 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11312 config->save_connector_encoders[count++] = connector->encoder;
11313 }
11314
11315 return 0;
11316 }
11317
11318 static void intel_set_config_restore_state(struct drm_device *dev,
11319 struct intel_set_config *config)
11320 {
11321 struct intel_crtc *crtc;
11322 struct intel_encoder *encoder;
11323 struct intel_connector *connector;
11324 int count;
11325
11326 count = 0;
11327 for_each_intel_crtc(dev, crtc) {
11328 crtc->new_enabled = config->save_crtc_enabled[count++];
11329
11330 if (crtc->new_enabled)
11331 crtc->new_config = crtc->config;
11332 else
11333 crtc->new_config = NULL;
11334 }
11335
11336 count = 0;
11337 for_each_intel_encoder(dev, encoder) {
11338 encoder->new_crtc =
11339 to_intel_crtc(config->save_encoder_crtcs[count++]);
11340 }
11341
11342 count = 0;
11343 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11344 connector->new_encoder =
11345 to_intel_encoder(config->save_connector_encoders[count++]);
11346 }
11347 }
11348
11349 static bool
11350 is_crtc_connector_off(struct drm_mode_set *set)
11351 {
11352 int i;
11353
11354 if (set->num_connectors == 0)
11355 return false;
11356
11357 if (WARN_ON(set->connectors == NULL))
11358 return false;
11359
11360 for (i = 0; i < set->num_connectors; i++)
11361 if (set->connectors[i]->encoder &&
11362 set->connectors[i]->encoder->crtc == set->crtc &&
11363 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11364 return true;
11365
11366 return false;
11367 }
11368
11369 static void
11370 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11371 struct intel_set_config *config)
11372 {
11373
11374 /* We should be able to check here if the fb has the same properties
11375 * and then just flip_or_move it */
11376 if (is_crtc_connector_off(set)) {
11377 config->mode_changed = true;
11378 } else if (set->crtc->primary->fb != set->fb) {
11379 /*
11380 * If we have no fb, we can only flip as long as the crtc is
11381 * active, otherwise we need a full mode set. The crtc may
11382 * be active if we've only disabled the primary plane, or
11383 * in fastboot situations.
11384 */
11385 if (set->crtc->primary->fb == NULL) {
11386 struct intel_crtc *intel_crtc =
11387 to_intel_crtc(set->crtc);
11388
11389 if (intel_crtc->active) {
11390 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11391 config->fb_changed = true;
11392 } else {
11393 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11394 config->mode_changed = true;
11395 }
11396 } else if (set->fb == NULL) {
11397 config->mode_changed = true;
11398 } else if (set->fb->pixel_format !=
11399 set->crtc->primary->fb->pixel_format) {
11400 config->mode_changed = true;
11401 } else {
11402 config->fb_changed = true;
11403 }
11404 }
11405
11406 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11407 config->fb_changed = true;
11408
11409 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11410 DRM_DEBUG_KMS("modes are different, full mode set\n");
11411 drm_mode_debug_printmodeline(&set->crtc->mode);
11412 drm_mode_debug_printmodeline(set->mode);
11413 config->mode_changed = true;
11414 }
11415
11416 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11417 set->crtc->base.id, config->mode_changed, config->fb_changed);
11418 }
11419
11420 static int
11421 intel_modeset_stage_output_state(struct drm_device *dev,
11422 struct drm_mode_set *set,
11423 struct intel_set_config *config)
11424 {
11425 struct intel_connector *connector;
11426 struct intel_encoder *encoder;
11427 struct intel_crtc *crtc;
11428 int ro;
11429
11430 /* The upper layers ensure that we either disable a crtc or have a list
11431 * of connectors. For paranoia, double-check this. */
11432 WARN_ON(!set->fb && (set->num_connectors != 0));
11433 WARN_ON(set->fb && (set->num_connectors == 0));
11434
11435 list_for_each_entry(connector, &dev->mode_config.connector_list,
11436 base.head) {
11437 /* Otherwise traverse passed in connector list and get encoders
11438 * for them. */
11439 for (ro = 0; ro < set->num_connectors; ro++) {
11440 if (set->connectors[ro] == &connector->base) {
11441 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11442 break;
11443 }
11444 }
11445
11446 /* If we disable the crtc, disable all its connectors. Also, if
11447 * the connector is on the changing crtc but not on the new
11448 * connector list, disable it. */
11449 if ((!set->fb || ro == set->num_connectors) &&
11450 connector->base.encoder &&
11451 connector->base.encoder->crtc == set->crtc) {
11452 connector->new_encoder = NULL;
11453
11454 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11455 connector->base.base.id,
11456 connector->base.name);
11457 }
11458
11459
11460 if (&connector->new_encoder->base != connector->base.encoder) {
11461 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11462 config->mode_changed = true;
11463 }
11464 }
11465 /* connector->new_encoder is now updated for all connectors. */
11466
11467 /* Update crtc of enabled connectors. */
11468 list_for_each_entry(connector, &dev->mode_config.connector_list,
11469 base.head) {
11470 struct drm_crtc *new_crtc;
11471
11472 if (!connector->new_encoder)
11473 continue;
11474
11475 new_crtc = connector->new_encoder->base.crtc;
11476
11477 for (ro = 0; ro < set->num_connectors; ro++) {
11478 if (set->connectors[ro] == &connector->base)
11479 new_crtc = set->crtc;
11480 }
11481
11482 /* Make sure the new CRTC will work with the encoder */
11483 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11484 new_crtc)) {
11485 return -EINVAL;
11486 }
11487 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11488
11489 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11490 connector->base.base.id,
11491 connector->base.name,
11492 new_crtc->base.id);
11493 }
11494
11495 /* Check for any encoders that needs to be disabled. */
11496 for_each_intel_encoder(dev, encoder) {
11497 int num_connectors = 0;
11498 list_for_each_entry(connector,
11499 &dev->mode_config.connector_list,
11500 base.head) {
11501 if (connector->new_encoder == encoder) {
11502 WARN_ON(!connector->new_encoder->new_crtc);
11503 num_connectors++;
11504 }
11505 }
11506
11507 if (num_connectors == 0)
11508 encoder->new_crtc = NULL;
11509 else if (num_connectors > 1)
11510 return -EINVAL;
11511
11512 /* Only now check for crtc changes so we don't miss encoders
11513 * that will be disabled. */
11514 if (&encoder->new_crtc->base != encoder->base.crtc) {
11515 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11516 config->mode_changed = true;
11517 }
11518 }
11519 /* Now we've also updated encoder->new_crtc for all encoders. */
11520 list_for_each_entry(connector, &dev->mode_config.connector_list,
11521 base.head) {
11522 if (connector->new_encoder)
11523 if (connector->new_encoder != connector->encoder)
11524 connector->encoder = connector->new_encoder;
11525 }
11526 for_each_intel_crtc(dev, crtc) {
11527 crtc->new_enabled = false;
11528
11529 for_each_intel_encoder(dev, encoder) {
11530 if (encoder->new_crtc == crtc) {
11531 crtc->new_enabled = true;
11532 break;
11533 }
11534 }
11535
11536 if (crtc->new_enabled != crtc->base.enabled) {
11537 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11538 crtc->new_enabled ? "en" : "dis");
11539 config->mode_changed = true;
11540 }
11541
11542 if (crtc->new_enabled)
11543 crtc->new_config = crtc->config;
11544 else
11545 crtc->new_config = NULL;
11546 }
11547
11548 return 0;
11549 }
11550
11551 static void disable_crtc_nofb(struct intel_crtc *crtc)
11552 {
11553 struct drm_device *dev = crtc->base.dev;
11554 struct intel_encoder *encoder;
11555 struct intel_connector *connector;
11556
11557 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11558 pipe_name(crtc->pipe));
11559
11560 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11561 if (connector->new_encoder &&
11562 connector->new_encoder->new_crtc == crtc)
11563 connector->new_encoder = NULL;
11564 }
11565
11566 for_each_intel_encoder(dev, encoder) {
11567 if (encoder->new_crtc == crtc)
11568 encoder->new_crtc = NULL;
11569 }
11570
11571 crtc->new_enabled = false;
11572 crtc->new_config = NULL;
11573 }
11574
11575 static int intel_crtc_set_config(struct drm_mode_set *set)
11576 {
11577 struct drm_device *dev;
11578 struct drm_mode_set save_set;
11579 struct intel_set_config *config;
11580 struct intel_crtc_state *pipe_config;
11581 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11582 int ret;
11583
11584 BUG_ON(!set);
11585 BUG_ON(!set->crtc);
11586 BUG_ON(!set->crtc->helper_private);
11587
11588 /* Enforce sane interface api - has been abused by the fb helper. */
11589 BUG_ON(!set->mode && set->fb);
11590 BUG_ON(set->fb && set->num_connectors == 0);
11591
11592 if (set->fb) {
11593 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11594 set->crtc->base.id, set->fb->base.id,
11595 (int)set->num_connectors, set->x, set->y);
11596 } else {
11597 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11598 }
11599
11600 dev = set->crtc->dev;
11601
11602 ret = -ENOMEM;
11603 config = kzalloc(sizeof(*config), GFP_KERNEL);
11604 if (!config)
11605 goto out_config;
11606
11607 ret = intel_set_config_save_state(dev, config);
11608 if (ret)
11609 goto out_config;
11610
11611 save_set.crtc = set->crtc;
11612 save_set.mode = &set->crtc->mode;
11613 save_set.x = set->crtc->x;
11614 save_set.y = set->crtc->y;
11615 save_set.fb = set->crtc->primary->fb;
11616
11617 /* Compute whether we need a full modeset, only an fb base update or no
11618 * change at all. In the future we might also check whether only the
11619 * mode changed, e.g. for LVDS where we only change the panel fitter in
11620 * such cases. */
11621 intel_set_config_compute_mode_changes(set, config);
11622
11623 ret = intel_modeset_stage_output_state(dev, set, config);
11624 if (ret)
11625 goto fail;
11626
11627 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11628 set->fb,
11629 &modeset_pipes,
11630 &prepare_pipes,
11631 &disable_pipes);
11632 if (IS_ERR(pipe_config)) {
11633 ret = PTR_ERR(pipe_config);
11634 goto fail;
11635 } else if (pipe_config) {
11636 if (pipe_config->has_audio !=
11637 to_intel_crtc(set->crtc)->config->has_audio)
11638 config->mode_changed = true;
11639
11640 /*
11641 * Note we have an issue here with infoframes: current code
11642 * only updates them on the full mode set path per hw
11643 * requirements. So here we should be checking for any
11644 * required changes and forcing a mode set.
11645 */
11646 }
11647
11648 /* set_mode will free it in the mode_changed case */
11649 if (!config->mode_changed)
11650 kfree(pipe_config);
11651
11652 intel_update_pipe_size(to_intel_crtc(set->crtc));
11653
11654 if (config->mode_changed) {
11655 ret = intel_set_mode_pipes(set->crtc, set->mode,
11656 set->x, set->y, set->fb, pipe_config,
11657 modeset_pipes, prepare_pipes,
11658 disable_pipes);
11659 } else if (config->fb_changed) {
11660 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11661 struct drm_plane *primary = set->crtc->primary;
11662 int vdisplay, hdisplay;
11663
11664 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11665 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11666 0, 0, hdisplay, vdisplay,
11667 set->x << 16, set->y << 16,
11668 hdisplay << 16, vdisplay << 16);
11669
11670 /*
11671 * We need to make sure the primary plane is re-enabled if it
11672 * has previously been turned off.
11673 */
11674 if (!intel_crtc->primary_enabled && ret == 0) {
11675 WARN_ON(!intel_crtc->active);
11676 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11677 }
11678
11679 /*
11680 * In the fastboot case this may be our only check of the
11681 * state after boot. It would be better to only do it on
11682 * the first update, but we don't have a nice way of doing that
11683 * (and really, set_config isn't used much for high freq page
11684 * flipping, so increasing its cost here shouldn't be a big
11685 * deal).
11686 */
11687 if (i915.fastboot && ret == 0)
11688 intel_modeset_check_state(set->crtc->dev);
11689 }
11690
11691 if (ret) {
11692 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11693 set->crtc->base.id, ret);
11694 fail:
11695 intel_set_config_restore_state(dev, config);
11696
11697 /*
11698 * HACK: if the pipe was on, but we didn't have a framebuffer,
11699 * force the pipe off to avoid oopsing in the modeset code
11700 * due to fb==NULL. This should only happen during boot since
11701 * we don't yet reconstruct the FB from the hardware state.
11702 */
11703 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11704 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11705
11706 /* Try to restore the config */
11707 if (config->mode_changed &&
11708 intel_set_mode(save_set.crtc, save_set.mode,
11709 save_set.x, save_set.y, save_set.fb))
11710 DRM_ERROR("failed to restore config after modeset failure\n");
11711 }
11712
11713 out_config:
11714 intel_set_config_free(config);
11715 return ret;
11716 }
11717
11718 static const struct drm_crtc_funcs intel_crtc_funcs = {
11719 .gamma_set = intel_crtc_gamma_set,
11720 .set_config = intel_crtc_set_config,
11721 .destroy = intel_crtc_destroy,
11722 .page_flip = intel_crtc_page_flip,
11723 .atomic_duplicate_state = intel_crtc_duplicate_state,
11724 .atomic_destroy_state = intel_crtc_destroy_state,
11725 };
11726
11727 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11728 struct intel_shared_dpll *pll,
11729 struct intel_dpll_hw_state *hw_state)
11730 {
11731 uint32_t val;
11732
11733 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11734 return false;
11735
11736 val = I915_READ(PCH_DPLL(pll->id));
11737 hw_state->dpll = val;
11738 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11739 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11740
11741 return val & DPLL_VCO_ENABLE;
11742 }
11743
11744 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11745 struct intel_shared_dpll *pll)
11746 {
11747 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11748 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11749 }
11750
11751 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11752 struct intel_shared_dpll *pll)
11753 {
11754 /* PCH refclock must be enabled first */
11755 ibx_assert_pch_refclk_enabled(dev_priv);
11756
11757 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11758
11759 /* Wait for the clocks to stabilize. */
11760 POSTING_READ(PCH_DPLL(pll->id));
11761 udelay(150);
11762
11763 /* The pixel multiplier can only be updated once the
11764 * DPLL is enabled and the clocks are stable.
11765 *
11766 * So write it again.
11767 */
11768 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11769 POSTING_READ(PCH_DPLL(pll->id));
11770 udelay(200);
11771 }
11772
11773 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11774 struct intel_shared_dpll *pll)
11775 {
11776 struct drm_device *dev = dev_priv->dev;
11777 struct intel_crtc *crtc;
11778
11779 /* Make sure no transcoder isn't still depending on us. */
11780 for_each_intel_crtc(dev, crtc) {
11781 if (intel_crtc_to_shared_dpll(crtc) == pll)
11782 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11783 }
11784
11785 I915_WRITE(PCH_DPLL(pll->id), 0);
11786 POSTING_READ(PCH_DPLL(pll->id));
11787 udelay(200);
11788 }
11789
11790 static char *ibx_pch_dpll_names[] = {
11791 "PCH DPLL A",
11792 "PCH DPLL B",
11793 };
11794
11795 static void ibx_pch_dpll_init(struct drm_device *dev)
11796 {
11797 struct drm_i915_private *dev_priv = dev->dev_private;
11798 int i;
11799
11800 dev_priv->num_shared_dpll = 2;
11801
11802 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11803 dev_priv->shared_dplls[i].id = i;
11804 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11805 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11806 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11807 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11808 dev_priv->shared_dplls[i].get_hw_state =
11809 ibx_pch_dpll_get_hw_state;
11810 }
11811 }
11812
11813 static void intel_shared_dpll_init(struct drm_device *dev)
11814 {
11815 struct drm_i915_private *dev_priv = dev->dev_private;
11816
11817 if (HAS_DDI(dev))
11818 intel_ddi_pll_init(dev);
11819 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11820 ibx_pch_dpll_init(dev);
11821 else
11822 dev_priv->num_shared_dpll = 0;
11823
11824 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11825 }
11826
11827 /**
11828 * intel_prepare_plane_fb - Prepare fb for usage on plane
11829 * @plane: drm plane to prepare for
11830 * @fb: framebuffer to prepare for presentation
11831 *
11832 * Prepares a framebuffer for usage on a display plane. Generally this
11833 * involves pinning the underlying object and updating the frontbuffer tracking
11834 * bits. Some older platforms need special physical address handling for
11835 * cursor planes.
11836 *
11837 * Returns 0 on success, negative error code on failure.
11838 */
11839 int
11840 intel_prepare_plane_fb(struct drm_plane *plane,
11841 struct drm_framebuffer *fb)
11842 {
11843 struct drm_device *dev = plane->dev;
11844 struct intel_plane *intel_plane = to_intel_plane(plane);
11845 enum pipe pipe = intel_plane->pipe;
11846 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11847 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11848 unsigned frontbuffer_bits = 0;
11849 int ret = 0;
11850
11851 if (!obj)
11852 return 0;
11853
11854 switch (plane->type) {
11855 case DRM_PLANE_TYPE_PRIMARY:
11856 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11857 break;
11858 case DRM_PLANE_TYPE_CURSOR:
11859 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11860 break;
11861 case DRM_PLANE_TYPE_OVERLAY:
11862 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11863 break;
11864 }
11865
11866 mutex_lock(&dev->struct_mutex);
11867
11868 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11869 INTEL_INFO(dev)->cursor_needs_physical) {
11870 int align = IS_I830(dev) ? 16 * 1024 : 256;
11871 ret = i915_gem_object_attach_phys(obj, align);
11872 if (ret)
11873 DRM_DEBUG_KMS("failed to attach phys object\n");
11874 } else {
11875 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11876 }
11877
11878 if (ret == 0)
11879 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11880
11881 mutex_unlock(&dev->struct_mutex);
11882
11883 return ret;
11884 }
11885
11886 /**
11887 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11888 * @plane: drm plane to clean up for
11889 * @fb: old framebuffer that was on plane
11890 *
11891 * Cleans up a framebuffer that has just been removed from a plane.
11892 */
11893 void
11894 intel_cleanup_plane_fb(struct drm_plane *plane,
11895 struct drm_framebuffer *fb)
11896 {
11897 struct drm_device *dev = plane->dev;
11898 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11899
11900 if (WARN_ON(!obj))
11901 return;
11902
11903 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11904 !INTEL_INFO(dev)->cursor_needs_physical) {
11905 mutex_lock(&dev->struct_mutex);
11906 intel_unpin_fb_obj(obj);
11907 mutex_unlock(&dev->struct_mutex);
11908 }
11909 }
11910
11911 static int
11912 intel_check_primary_plane(struct drm_plane *plane,
11913 struct intel_plane_state *state)
11914 {
11915 struct drm_device *dev = plane->dev;
11916 struct drm_i915_private *dev_priv = dev->dev_private;
11917 struct drm_crtc *crtc = state->base.crtc;
11918 struct intel_crtc *intel_crtc;
11919 struct drm_framebuffer *fb = state->base.fb;
11920 struct drm_rect *dest = &state->dst;
11921 struct drm_rect *src = &state->src;
11922 const struct drm_rect *clip = &state->clip;
11923 int ret;
11924
11925 crtc = crtc ? crtc : plane->crtc;
11926 intel_crtc = to_intel_crtc(crtc);
11927
11928 ret = drm_plane_helper_check_update(plane, crtc, fb,
11929 src, dest, clip,
11930 DRM_PLANE_HELPER_NO_SCALING,
11931 DRM_PLANE_HELPER_NO_SCALING,
11932 false, true, &state->visible);
11933 if (ret)
11934 return ret;
11935
11936 if (intel_crtc->active) {
11937 intel_crtc->atomic.wait_for_flips = true;
11938
11939 /*
11940 * FBC does not work on some platforms for rotated
11941 * planes, so disable it when rotation is not 0 and
11942 * update it when rotation is set back to 0.
11943 *
11944 * FIXME: This is redundant with the fbc update done in
11945 * the primary plane enable function except that that
11946 * one is done too late. We eventually need to unify
11947 * this.
11948 */
11949 if (intel_crtc->primary_enabled &&
11950 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11951 dev_priv->fbc.crtc == intel_crtc &&
11952 state->base.rotation != BIT(DRM_ROTATE_0)) {
11953 intel_crtc->atomic.disable_fbc = true;
11954 }
11955
11956 if (state->visible) {
11957 /*
11958 * BDW signals flip done immediately if the plane
11959 * is disabled, even if the plane enable is already
11960 * armed to occur at the next vblank :(
11961 */
11962 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
11963 intel_crtc->atomic.wait_vblank = true;
11964 }
11965
11966 intel_crtc->atomic.fb_bits |=
11967 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11968
11969 intel_crtc->atomic.update_fbc = true;
11970 }
11971
11972 return 0;
11973 }
11974
11975 static void
11976 intel_commit_primary_plane(struct drm_plane *plane,
11977 struct intel_plane_state *state)
11978 {
11979 struct drm_crtc *crtc = state->base.crtc;
11980 struct drm_framebuffer *fb = state->base.fb;
11981 struct drm_device *dev = plane->dev;
11982 struct drm_i915_private *dev_priv = dev->dev_private;
11983 struct intel_crtc *intel_crtc;
11984 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11985 struct intel_plane *intel_plane = to_intel_plane(plane);
11986 struct drm_rect *src = &state->src;
11987
11988 crtc = crtc ? crtc : plane->crtc;
11989 intel_crtc = to_intel_crtc(crtc);
11990
11991 plane->fb = fb;
11992 crtc->x = src->x1 >> 16;
11993 crtc->y = src->y1 >> 16;
11994
11995 intel_plane->obj = obj;
11996
11997 if (intel_crtc->active) {
11998 if (state->visible) {
11999 /* FIXME: kill this fastboot hack */
12000 intel_update_pipe_size(intel_crtc);
12001
12002 intel_crtc->primary_enabled = true;
12003
12004 dev_priv->display.update_primary_plane(crtc, plane->fb,
12005 crtc->x, crtc->y);
12006 } else {
12007 /*
12008 * If clipping results in a non-visible primary plane,
12009 * we'll disable the primary plane. Note that this is
12010 * a bit different than what happens if userspace
12011 * explicitly disables the plane by passing fb=0
12012 * because plane->fb still gets set and pinned.
12013 */
12014 intel_disable_primary_hw_plane(plane, crtc);
12015 }
12016 }
12017 }
12018
12019 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12020 {
12021 struct drm_device *dev = crtc->dev;
12022 struct drm_i915_private *dev_priv = dev->dev_private;
12023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12024 struct intel_plane *intel_plane;
12025 struct drm_plane *p;
12026 unsigned fb_bits = 0;
12027
12028 /* Track fb's for any planes being disabled */
12029 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12030 intel_plane = to_intel_plane(p);
12031
12032 if (intel_crtc->atomic.disabled_planes &
12033 (1 << drm_plane_index(p))) {
12034 switch (p->type) {
12035 case DRM_PLANE_TYPE_PRIMARY:
12036 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12037 break;
12038 case DRM_PLANE_TYPE_CURSOR:
12039 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12040 break;
12041 case DRM_PLANE_TYPE_OVERLAY:
12042 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12043 break;
12044 }
12045
12046 mutex_lock(&dev->struct_mutex);
12047 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12048 mutex_unlock(&dev->struct_mutex);
12049 }
12050 }
12051
12052 if (intel_crtc->atomic.wait_for_flips)
12053 intel_crtc_wait_for_pending_flips(crtc);
12054
12055 if (intel_crtc->atomic.disable_fbc)
12056 intel_fbc_disable(dev);
12057
12058 if (intel_crtc->atomic.pre_disable_primary)
12059 intel_pre_disable_primary(crtc);
12060
12061 if (intel_crtc->atomic.update_wm)
12062 intel_update_watermarks(crtc);
12063
12064 intel_runtime_pm_get(dev_priv);
12065
12066 /* Perform vblank evasion around commit operation */
12067 if (intel_crtc->active)
12068 intel_crtc->atomic.evade =
12069 intel_pipe_update_start(intel_crtc,
12070 &intel_crtc->atomic.start_vbl_count);
12071 }
12072
12073 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12074 {
12075 struct drm_device *dev = crtc->dev;
12076 struct drm_i915_private *dev_priv = dev->dev_private;
12077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12078 struct drm_plane *p;
12079
12080 if (intel_crtc->atomic.evade)
12081 intel_pipe_update_end(intel_crtc,
12082 intel_crtc->atomic.start_vbl_count);
12083
12084 intel_runtime_pm_put(dev_priv);
12085
12086 if (intel_crtc->atomic.wait_vblank)
12087 intel_wait_for_vblank(dev, intel_crtc->pipe);
12088
12089 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12090
12091 if (intel_crtc->atomic.update_fbc) {
12092 mutex_lock(&dev->struct_mutex);
12093 intel_fbc_update(dev);
12094 mutex_unlock(&dev->struct_mutex);
12095 }
12096
12097 if (intel_crtc->atomic.post_enable_primary)
12098 intel_post_enable_primary(crtc);
12099
12100 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12101 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12102 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12103 false, false);
12104
12105 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12106 }
12107
12108 /**
12109 * intel_plane_destroy - destroy a plane
12110 * @plane: plane to destroy
12111 *
12112 * Common destruction function for all types of planes (primary, cursor,
12113 * sprite).
12114 */
12115 void intel_plane_destroy(struct drm_plane *plane)
12116 {
12117 struct intel_plane *intel_plane = to_intel_plane(plane);
12118 drm_plane_cleanup(plane);
12119 kfree(intel_plane);
12120 }
12121
12122 const struct drm_plane_funcs intel_plane_funcs = {
12123 .update_plane = drm_atomic_helper_update_plane,
12124 .disable_plane = drm_atomic_helper_disable_plane,
12125 .destroy = intel_plane_destroy,
12126 .set_property = drm_atomic_helper_plane_set_property,
12127 .atomic_get_property = intel_plane_atomic_get_property,
12128 .atomic_set_property = intel_plane_atomic_set_property,
12129 .atomic_duplicate_state = intel_plane_duplicate_state,
12130 .atomic_destroy_state = intel_plane_destroy_state,
12131
12132 };
12133
12134 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12135 int pipe)
12136 {
12137 struct intel_plane *primary;
12138 struct intel_plane_state *state;
12139 const uint32_t *intel_primary_formats;
12140 int num_formats;
12141
12142 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12143 if (primary == NULL)
12144 return NULL;
12145
12146 state = intel_create_plane_state(&primary->base);
12147 if (!state) {
12148 kfree(primary);
12149 return NULL;
12150 }
12151 primary->base.state = &state->base;
12152
12153 primary->can_scale = false;
12154 primary->max_downscale = 1;
12155 primary->pipe = pipe;
12156 primary->plane = pipe;
12157 primary->check_plane = intel_check_primary_plane;
12158 primary->commit_plane = intel_commit_primary_plane;
12159 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12160 primary->plane = !pipe;
12161
12162 if (INTEL_INFO(dev)->gen <= 3) {
12163 intel_primary_formats = intel_primary_formats_gen2;
12164 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12165 } else {
12166 intel_primary_formats = intel_primary_formats_gen4;
12167 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12168 }
12169
12170 drm_universal_plane_init(dev, &primary->base, 0,
12171 &intel_plane_funcs,
12172 intel_primary_formats, num_formats,
12173 DRM_PLANE_TYPE_PRIMARY);
12174
12175 if (INTEL_INFO(dev)->gen >= 4) {
12176 if (!dev->mode_config.rotation_property)
12177 dev->mode_config.rotation_property =
12178 drm_mode_create_rotation_property(dev,
12179 BIT(DRM_ROTATE_0) |
12180 BIT(DRM_ROTATE_180));
12181 if (dev->mode_config.rotation_property)
12182 drm_object_attach_property(&primary->base.base,
12183 dev->mode_config.rotation_property,
12184 state->base.rotation);
12185 }
12186
12187 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12188
12189 return &primary->base;
12190 }
12191
12192 static int
12193 intel_check_cursor_plane(struct drm_plane *plane,
12194 struct intel_plane_state *state)
12195 {
12196 struct drm_crtc *crtc = state->base.crtc;
12197 struct drm_device *dev = plane->dev;
12198 struct drm_framebuffer *fb = state->base.fb;
12199 struct drm_rect *dest = &state->dst;
12200 struct drm_rect *src = &state->src;
12201 const struct drm_rect *clip = &state->clip;
12202 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12203 struct intel_crtc *intel_crtc;
12204 unsigned stride;
12205 int ret;
12206
12207 crtc = crtc ? crtc : plane->crtc;
12208 intel_crtc = to_intel_crtc(crtc);
12209
12210 ret = drm_plane_helper_check_update(plane, crtc, fb,
12211 src, dest, clip,
12212 DRM_PLANE_HELPER_NO_SCALING,
12213 DRM_PLANE_HELPER_NO_SCALING,
12214 true, true, &state->visible);
12215 if (ret)
12216 return ret;
12217
12218
12219 /* if we want to turn off the cursor ignore width and height */
12220 if (!obj)
12221 goto finish;
12222
12223 /* Check for which cursor types we support */
12224 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12225 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12226 state->base.crtc_w, state->base.crtc_h);
12227 return -EINVAL;
12228 }
12229
12230 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12231 if (obj->base.size < stride * state->base.crtc_h) {
12232 DRM_DEBUG_KMS("buffer is too small\n");
12233 return -ENOMEM;
12234 }
12235
12236 if (fb == crtc->cursor->fb)
12237 return 0;
12238
12239 /* we only need to pin inside GTT if cursor is non-phy */
12240 mutex_lock(&dev->struct_mutex);
12241 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12242 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12243 ret = -EINVAL;
12244 }
12245 mutex_unlock(&dev->struct_mutex);
12246
12247 finish:
12248 if (intel_crtc->active) {
12249 if (intel_crtc->cursor_width != state->base.crtc_w)
12250 intel_crtc->atomic.update_wm = true;
12251
12252 intel_crtc->atomic.fb_bits |=
12253 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12254 }
12255
12256 return ret;
12257 }
12258
12259 static void
12260 intel_commit_cursor_plane(struct drm_plane *plane,
12261 struct intel_plane_state *state)
12262 {
12263 struct drm_crtc *crtc = state->base.crtc;
12264 struct drm_device *dev = plane->dev;
12265 struct intel_crtc *intel_crtc;
12266 struct intel_plane *intel_plane = to_intel_plane(plane);
12267 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12268 uint32_t addr;
12269
12270 crtc = crtc ? crtc : plane->crtc;
12271 intel_crtc = to_intel_crtc(crtc);
12272
12273 plane->fb = state->base.fb;
12274 crtc->cursor_x = state->base.crtc_x;
12275 crtc->cursor_y = state->base.crtc_y;
12276
12277 intel_plane->obj = obj;
12278
12279 if (intel_crtc->cursor_bo == obj)
12280 goto update;
12281
12282 if (!obj)
12283 addr = 0;
12284 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12285 addr = i915_gem_obj_ggtt_offset(obj);
12286 else
12287 addr = obj->phys_handle->busaddr;
12288
12289 intel_crtc->cursor_addr = addr;
12290 intel_crtc->cursor_bo = obj;
12291 update:
12292 intel_crtc->cursor_width = state->base.crtc_w;
12293 intel_crtc->cursor_height = state->base.crtc_h;
12294
12295 if (intel_crtc->active)
12296 intel_crtc_update_cursor(crtc, state->visible);
12297 }
12298
12299 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12300 int pipe)
12301 {
12302 struct intel_plane *cursor;
12303 struct intel_plane_state *state;
12304
12305 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12306 if (cursor == NULL)
12307 return NULL;
12308
12309 state = intel_create_plane_state(&cursor->base);
12310 if (!state) {
12311 kfree(cursor);
12312 return NULL;
12313 }
12314 cursor->base.state = &state->base;
12315
12316 cursor->can_scale = false;
12317 cursor->max_downscale = 1;
12318 cursor->pipe = pipe;
12319 cursor->plane = pipe;
12320 cursor->check_plane = intel_check_cursor_plane;
12321 cursor->commit_plane = intel_commit_cursor_plane;
12322
12323 drm_universal_plane_init(dev, &cursor->base, 0,
12324 &intel_plane_funcs,
12325 intel_cursor_formats,
12326 ARRAY_SIZE(intel_cursor_formats),
12327 DRM_PLANE_TYPE_CURSOR);
12328
12329 if (INTEL_INFO(dev)->gen >= 4) {
12330 if (!dev->mode_config.rotation_property)
12331 dev->mode_config.rotation_property =
12332 drm_mode_create_rotation_property(dev,
12333 BIT(DRM_ROTATE_0) |
12334 BIT(DRM_ROTATE_180));
12335 if (dev->mode_config.rotation_property)
12336 drm_object_attach_property(&cursor->base.base,
12337 dev->mode_config.rotation_property,
12338 state->base.rotation);
12339 }
12340
12341 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12342
12343 return &cursor->base;
12344 }
12345
12346 static void intel_crtc_init(struct drm_device *dev, int pipe)
12347 {
12348 struct drm_i915_private *dev_priv = dev->dev_private;
12349 struct intel_crtc *intel_crtc;
12350 struct intel_crtc_state *crtc_state = NULL;
12351 struct drm_plane *primary = NULL;
12352 struct drm_plane *cursor = NULL;
12353 int i, ret;
12354
12355 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12356 if (intel_crtc == NULL)
12357 return;
12358
12359 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12360 if (!crtc_state)
12361 goto fail;
12362 intel_crtc_set_state(intel_crtc, crtc_state);
12363
12364 primary = intel_primary_plane_create(dev, pipe);
12365 if (!primary)
12366 goto fail;
12367
12368 cursor = intel_cursor_plane_create(dev, pipe);
12369 if (!cursor)
12370 goto fail;
12371
12372 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12373 cursor, &intel_crtc_funcs);
12374 if (ret)
12375 goto fail;
12376
12377 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12378 for (i = 0; i < 256; i++) {
12379 intel_crtc->lut_r[i] = i;
12380 intel_crtc->lut_g[i] = i;
12381 intel_crtc->lut_b[i] = i;
12382 }
12383
12384 /*
12385 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12386 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12387 */
12388 intel_crtc->pipe = pipe;
12389 intel_crtc->plane = pipe;
12390 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12391 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12392 intel_crtc->plane = !pipe;
12393 }
12394
12395 intel_crtc->cursor_base = ~0;
12396 intel_crtc->cursor_cntl = ~0;
12397 intel_crtc->cursor_size = ~0;
12398
12399 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12400 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12401 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12402 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12403
12404 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12405
12406 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12407
12408 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12409 return;
12410
12411 fail:
12412 if (primary)
12413 drm_plane_cleanup(primary);
12414 if (cursor)
12415 drm_plane_cleanup(cursor);
12416 kfree(crtc_state);
12417 kfree(intel_crtc);
12418 }
12419
12420 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12421 {
12422 struct drm_encoder *encoder = connector->base.encoder;
12423 struct drm_device *dev = connector->base.dev;
12424
12425 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12426
12427 if (!encoder || WARN_ON(!encoder->crtc))
12428 return INVALID_PIPE;
12429
12430 return to_intel_crtc(encoder->crtc)->pipe;
12431 }
12432
12433 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12434 struct drm_file *file)
12435 {
12436 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12437 struct drm_crtc *drmmode_crtc;
12438 struct intel_crtc *crtc;
12439
12440 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12441 return -ENODEV;
12442
12443 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12444
12445 if (!drmmode_crtc) {
12446 DRM_ERROR("no such CRTC id\n");
12447 return -ENOENT;
12448 }
12449
12450 crtc = to_intel_crtc(drmmode_crtc);
12451 pipe_from_crtc_id->pipe = crtc->pipe;
12452
12453 return 0;
12454 }
12455
12456 static int intel_encoder_clones(struct intel_encoder *encoder)
12457 {
12458 struct drm_device *dev = encoder->base.dev;
12459 struct intel_encoder *source_encoder;
12460 int index_mask = 0;
12461 int entry = 0;
12462
12463 for_each_intel_encoder(dev, source_encoder) {
12464 if (encoders_cloneable(encoder, source_encoder))
12465 index_mask |= (1 << entry);
12466
12467 entry++;
12468 }
12469
12470 return index_mask;
12471 }
12472
12473 static bool has_edp_a(struct drm_device *dev)
12474 {
12475 struct drm_i915_private *dev_priv = dev->dev_private;
12476
12477 if (!IS_MOBILE(dev))
12478 return false;
12479
12480 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12481 return false;
12482
12483 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12484 return false;
12485
12486 return true;
12487 }
12488
12489 static bool intel_crt_present(struct drm_device *dev)
12490 {
12491 struct drm_i915_private *dev_priv = dev->dev_private;
12492
12493 if (INTEL_INFO(dev)->gen >= 9)
12494 return false;
12495
12496 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12497 return false;
12498
12499 if (IS_CHERRYVIEW(dev))
12500 return false;
12501
12502 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12503 return false;
12504
12505 return true;
12506 }
12507
12508 static void intel_setup_outputs(struct drm_device *dev)
12509 {
12510 struct drm_i915_private *dev_priv = dev->dev_private;
12511 struct intel_encoder *encoder;
12512 struct drm_connector *connector;
12513 bool dpd_is_edp = false;
12514
12515 intel_lvds_init(dev);
12516
12517 if (intel_crt_present(dev))
12518 intel_crt_init(dev);
12519
12520 if (HAS_DDI(dev)) {
12521 int found;
12522
12523 /* Haswell uses DDI functions to detect digital outputs */
12524 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12525 /* DDI A only supports eDP */
12526 if (found)
12527 intel_ddi_init(dev, PORT_A);
12528
12529 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12530 * register */
12531 found = I915_READ(SFUSE_STRAP);
12532
12533 if (found & SFUSE_STRAP_DDIB_DETECTED)
12534 intel_ddi_init(dev, PORT_B);
12535 if (found & SFUSE_STRAP_DDIC_DETECTED)
12536 intel_ddi_init(dev, PORT_C);
12537 if (found & SFUSE_STRAP_DDID_DETECTED)
12538 intel_ddi_init(dev, PORT_D);
12539 } else if (HAS_PCH_SPLIT(dev)) {
12540 int found;
12541 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12542
12543 if (has_edp_a(dev))
12544 intel_dp_init(dev, DP_A, PORT_A);
12545
12546 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12547 /* PCH SDVOB multiplex with HDMIB */
12548 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12549 if (!found)
12550 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12551 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12552 intel_dp_init(dev, PCH_DP_B, PORT_B);
12553 }
12554
12555 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12556 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12557
12558 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12559 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12560
12561 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12562 intel_dp_init(dev, PCH_DP_C, PORT_C);
12563
12564 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12565 intel_dp_init(dev, PCH_DP_D, PORT_D);
12566 } else if (IS_VALLEYVIEW(dev)) {
12567 /*
12568 * The DP_DETECTED bit is the latched state of the DDC
12569 * SDA pin at boot. However since eDP doesn't require DDC
12570 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12571 * eDP ports may have been muxed to an alternate function.
12572 * Thus we can't rely on the DP_DETECTED bit alone to detect
12573 * eDP ports. Consult the VBT as well as DP_DETECTED to
12574 * detect eDP ports.
12575 */
12576 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12577 !intel_dp_is_edp(dev, PORT_B))
12578 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12579 PORT_B);
12580 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12581 intel_dp_is_edp(dev, PORT_B))
12582 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12583
12584 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12585 !intel_dp_is_edp(dev, PORT_C))
12586 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12587 PORT_C);
12588 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12589 intel_dp_is_edp(dev, PORT_C))
12590 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12591
12592 if (IS_CHERRYVIEW(dev)) {
12593 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12594 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12595 PORT_D);
12596 /* eDP not supported on port D, so don't check VBT */
12597 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12598 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12599 }
12600
12601 intel_dsi_init(dev);
12602 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12603 bool found = false;
12604
12605 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12606 DRM_DEBUG_KMS("probing SDVOB\n");
12607 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12608 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12609 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12610 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12611 }
12612
12613 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12614 intel_dp_init(dev, DP_B, PORT_B);
12615 }
12616
12617 /* Before G4X SDVOC doesn't have its own detect register */
12618
12619 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12620 DRM_DEBUG_KMS("probing SDVOC\n");
12621 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12622 }
12623
12624 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12625
12626 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12627 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12628 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12629 }
12630 if (SUPPORTS_INTEGRATED_DP(dev))
12631 intel_dp_init(dev, DP_C, PORT_C);
12632 }
12633
12634 if (SUPPORTS_INTEGRATED_DP(dev) &&
12635 (I915_READ(DP_D) & DP_DETECTED))
12636 intel_dp_init(dev, DP_D, PORT_D);
12637 } else if (IS_GEN2(dev))
12638 intel_dvo_init(dev);
12639
12640 if (SUPPORTS_TV(dev))
12641 intel_tv_init(dev);
12642
12643 /*
12644 * FIXME: We don't have full atomic support yet, but we want to be
12645 * able to enable/test plane updates via the atomic interface in the
12646 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12647 * will take some atomic codepaths to lookup properties during
12648 * drmModeGetConnector() that unconditionally dereference
12649 * connector->state.
12650 *
12651 * We create a dummy connector state here for each connector to ensure
12652 * the DRM core doesn't try to dereference a NULL connector->state.
12653 * The actual connector properties will never be updated or contain
12654 * useful information, but since we're doing this specifically for
12655 * testing/debug of the plane operations (and only when a specific
12656 * kernel module option is given), that shouldn't really matter.
12657 *
12658 * Once atomic support for crtc's + connectors lands, this loop should
12659 * be removed since we'll be setting up real connector state, which
12660 * will contain Intel-specific properties.
12661 */
12662 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12663 list_for_each_entry(connector,
12664 &dev->mode_config.connector_list,
12665 head) {
12666 if (!WARN_ON(connector->state)) {
12667 connector->state =
12668 kzalloc(sizeof(*connector->state),
12669 GFP_KERNEL);
12670 }
12671 }
12672 }
12673
12674 intel_psr_init(dev);
12675
12676 for_each_intel_encoder(dev, encoder) {
12677 encoder->base.possible_crtcs = encoder->crtc_mask;
12678 encoder->base.possible_clones =
12679 intel_encoder_clones(encoder);
12680 }
12681
12682 intel_init_pch_refclk(dev);
12683
12684 drm_helper_move_panel_connectors_to_head(dev);
12685 }
12686
12687 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12688 {
12689 struct drm_device *dev = fb->dev;
12690 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12691
12692 drm_framebuffer_cleanup(fb);
12693 mutex_lock(&dev->struct_mutex);
12694 WARN_ON(!intel_fb->obj->framebuffer_references--);
12695 drm_gem_object_unreference(&intel_fb->obj->base);
12696 mutex_unlock(&dev->struct_mutex);
12697 kfree(intel_fb);
12698 }
12699
12700 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12701 struct drm_file *file,
12702 unsigned int *handle)
12703 {
12704 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12705 struct drm_i915_gem_object *obj = intel_fb->obj;
12706
12707 return drm_gem_handle_create(file, &obj->base, handle);
12708 }
12709
12710 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12711 .destroy = intel_user_framebuffer_destroy,
12712 .create_handle = intel_user_framebuffer_create_handle,
12713 };
12714
12715 static int intel_framebuffer_init(struct drm_device *dev,
12716 struct intel_framebuffer *intel_fb,
12717 struct drm_mode_fb_cmd2 *mode_cmd,
12718 struct drm_i915_gem_object *obj)
12719 {
12720 int aligned_height;
12721 int pitch_limit;
12722 int ret;
12723
12724 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12725
12726 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12727 /* Enforce that fb modifier and tiling mode match, but only for
12728 * X-tiled. This is needed for FBC. */
12729 if (!!(obj->tiling_mode == I915_TILING_X) !=
12730 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12731 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12732 return -EINVAL;
12733 }
12734 } else {
12735 if (obj->tiling_mode == I915_TILING_X)
12736 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12737 else if (obj->tiling_mode == I915_TILING_Y) {
12738 DRM_DEBUG("No Y tiling for legacy addfb\n");
12739 return -EINVAL;
12740 }
12741 }
12742
12743 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED) {
12744 DRM_DEBUG("hardware does not support tiling Y\n");
12745 return -EINVAL;
12746 }
12747
12748 if (mode_cmd->pitches[0] & 63) {
12749 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12750 mode_cmd->pitches[0]);
12751 return -EINVAL;
12752 }
12753
12754 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12755 pitch_limit = 32*1024;
12756 } else if (INTEL_INFO(dev)->gen >= 4) {
12757 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)
12758 pitch_limit = 16*1024;
12759 else
12760 pitch_limit = 32*1024;
12761 } else if (INTEL_INFO(dev)->gen >= 3) {
12762 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)
12763 pitch_limit = 8*1024;
12764 else
12765 pitch_limit = 16*1024;
12766 } else
12767 /* XXX DSPC is limited to 4k tiled */
12768 pitch_limit = 8*1024;
12769
12770 if (mode_cmd->pitches[0] > pitch_limit) {
12771 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12772 mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED ?
12773 "tiled" : "linear",
12774 mode_cmd->pitches[0], pitch_limit);
12775 return -EINVAL;
12776 }
12777
12778 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12779 mode_cmd->pitches[0] != obj->stride) {
12780 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12781 mode_cmd->pitches[0], obj->stride);
12782 return -EINVAL;
12783 }
12784
12785 /* Reject formats not supported by any plane early. */
12786 switch (mode_cmd->pixel_format) {
12787 case DRM_FORMAT_C8:
12788 case DRM_FORMAT_RGB565:
12789 case DRM_FORMAT_XRGB8888:
12790 case DRM_FORMAT_ARGB8888:
12791 break;
12792 case DRM_FORMAT_XRGB1555:
12793 case DRM_FORMAT_ARGB1555:
12794 if (INTEL_INFO(dev)->gen > 3) {
12795 DRM_DEBUG("unsupported pixel format: %s\n",
12796 drm_get_format_name(mode_cmd->pixel_format));
12797 return -EINVAL;
12798 }
12799 break;
12800 case DRM_FORMAT_XBGR8888:
12801 case DRM_FORMAT_ABGR8888:
12802 case DRM_FORMAT_XRGB2101010:
12803 case DRM_FORMAT_ARGB2101010:
12804 case DRM_FORMAT_XBGR2101010:
12805 case DRM_FORMAT_ABGR2101010:
12806 if (INTEL_INFO(dev)->gen < 4) {
12807 DRM_DEBUG("unsupported pixel format: %s\n",
12808 drm_get_format_name(mode_cmd->pixel_format));
12809 return -EINVAL;
12810 }
12811 break;
12812 case DRM_FORMAT_YUYV:
12813 case DRM_FORMAT_UYVY:
12814 case DRM_FORMAT_YVYU:
12815 case DRM_FORMAT_VYUY:
12816 if (INTEL_INFO(dev)->gen < 5) {
12817 DRM_DEBUG("unsupported pixel format: %s\n",
12818 drm_get_format_name(mode_cmd->pixel_format));
12819 return -EINVAL;
12820 }
12821 break;
12822 default:
12823 DRM_DEBUG("unsupported pixel format: %s\n",
12824 drm_get_format_name(mode_cmd->pixel_format));
12825 return -EINVAL;
12826 }
12827
12828 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12829 if (mode_cmd->offsets[0] != 0)
12830 return -EINVAL;
12831
12832 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12833 mode_cmd->pixel_format,
12834 mode_cmd->modifier[0]);
12835 /* FIXME drm helper for size checks (especially planar formats)? */
12836 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12837 return -EINVAL;
12838
12839 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12840 intel_fb->obj = obj;
12841 intel_fb->obj->framebuffer_references++;
12842
12843 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12844 if (ret) {
12845 DRM_ERROR("framebuffer init failed %d\n", ret);
12846 return ret;
12847 }
12848
12849 return 0;
12850 }
12851
12852 static struct drm_framebuffer *
12853 intel_user_framebuffer_create(struct drm_device *dev,
12854 struct drm_file *filp,
12855 struct drm_mode_fb_cmd2 *mode_cmd)
12856 {
12857 struct drm_i915_gem_object *obj;
12858
12859 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12860 mode_cmd->handles[0]));
12861 if (&obj->base == NULL)
12862 return ERR_PTR(-ENOENT);
12863
12864 return intel_framebuffer_create(dev, mode_cmd, obj);
12865 }
12866
12867 #ifndef CONFIG_DRM_I915_FBDEV
12868 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12869 {
12870 }
12871 #endif
12872
12873 static const struct drm_mode_config_funcs intel_mode_funcs = {
12874 .fb_create = intel_user_framebuffer_create,
12875 .output_poll_changed = intel_fbdev_output_poll_changed,
12876 .atomic_check = intel_atomic_check,
12877 .atomic_commit = intel_atomic_commit,
12878 };
12879
12880 /* Set up chip specific display functions */
12881 static void intel_init_display(struct drm_device *dev)
12882 {
12883 struct drm_i915_private *dev_priv = dev->dev_private;
12884
12885 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12886 dev_priv->display.find_dpll = g4x_find_best_dpll;
12887 else if (IS_CHERRYVIEW(dev))
12888 dev_priv->display.find_dpll = chv_find_best_dpll;
12889 else if (IS_VALLEYVIEW(dev))
12890 dev_priv->display.find_dpll = vlv_find_best_dpll;
12891 else if (IS_PINEVIEW(dev))
12892 dev_priv->display.find_dpll = pnv_find_best_dpll;
12893 else
12894 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12895
12896 if (INTEL_INFO(dev)->gen >= 9) {
12897 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12898 dev_priv->display.get_initial_plane_config =
12899 skylake_get_initial_plane_config;
12900 dev_priv->display.crtc_compute_clock =
12901 haswell_crtc_compute_clock;
12902 dev_priv->display.crtc_enable = haswell_crtc_enable;
12903 dev_priv->display.crtc_disable = haswell_crtc_disable;
12904 dev_priv->display.off = ironlake_crtc_off;
12905 dev_priv->display.update_primary_plane =
12906 skylake_update_primary_plane;
12907 } else if (HAS_DDI(dev)) {
12908 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12909 dev_priv->display.get_initial_plane_config =
12910 ironlake_get_initial_plane_config;
12911 dev_priv->display.crtc_compute_clock =
12912 haswell_crtc_compute_clock;
12913 dev_priv->display.crtc_enable = haswell_crtc_enable;
12914 dev_priv->display.crtc_disable = haswell_crtc_disable;
12915 dev_priv->display.off = ironlake_crtc_off;
12916 dev_priv->display.update_primary_plane =
12917 ironlake_update_primary_plane;
12918 } else if (HAS_PCH_SPLIT(dev)) {
12919 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12920 dev_priv->display.get_initial_plane_config =
12921 ironlake_get_initial_plane_config;
12922 dev_priv->display.crtc_compute_clock =
12923 ironlake_crtc_compute_clock;
12924 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12925 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12926 dev_priv->display.off = ironlake_crtc_off;
12927 dev_priv->display.update_primary_plane =
12928 ironlake_update_primary_plane;
12929 } else if (IS_VALLEYVIEW(dev)) {
12930 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12931 dev_priv->display.get_initial_plane_config =
12932 i9xx_get_initial_plane_config;
12933 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12934 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12935 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12936 dev_priv->display.off = i9xx_crtc_off;
12937 dev_priv->display.update_primary_plane =
12938 i9xx_update_primary_plane;
12939 } else {
12940 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12941 dev_priv->display.get_initial_plane_config =
12942 i9xx_get_initial_plane_config;
12943 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12944 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12945 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12946 dev_priv->display.off = i9xx_crtc_off;
12947 dev_priv->display.update_primary_plane =
12948 i9xx_update_primary_plane;
12949 }
12950
12951 /* Returns the core display clock speed */
12952 if (IS_VALLEYVIEW(dev))
12953 dev_priv->display.get_display_clock_speed =
12954 valleyview_get_display_clock_speed;
12955 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12956 dev_priv->display.get_display_clock_speed =
12957 i945_get_display_clock_speed;
12958 else if (IS_I915G(dev))
12959 dev_priv->display.get_display_clock_speed =
12960 i915_get_display_clock_speed;
12961 else if (IS_I945GM(dev) || IS_845G(dev))
12962 dev_priv->display.get_display_clock_speed =
12963 i9xx_misc_get_display_clock_speed;
12964 else if (IS_PINEVIEW(dev))
12965 dev_priv->display.get_display_clock_speed =
12966 pnv_get_display_clock_speed;
12967 else if (IS_I915GM(dev))
12968 dev_priv->display.get_display_clock_speed =
12969 i915gm_get_display_clock_speed;
12970 else if (IS_I865G(dev))
12971 dev_priv->display.get_display_clock_speed =
12972 i865_get_display_clock_speed;
12973 else if (IS_I85X(dev))
12974 dev_priv->display.get_display_clock_speed =
12975 i855_get_display_clock_speed;
12976 else /* 852, 830 */
12977 dev_priv->display.get_display_clock_speed =
12978 i830_get_display_clock_speed;
12979
12980 if (IS_GEN5(dev)) {
12981 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12982 } else if (IS_GEN6(dev)) {
12983 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12984 } else if (IS_IVYBRIDGE(dev)) {
12985 /* FIXME: detect B0+ stepping and use auto training */
12986 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12987 dev_priv->display.modeset_global_resources =
12988 ivb_modeset_global_resources;
12989 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12990 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12991 } else if (IS_VALLEYVIEW(dev)) {
12992 dev_priv->display.modeset_global_resources =
12993 valleyview_modeset_global_resources;
12994 }
12995
12996 /* Default just returns -ENODEV to indicate unsupported */
12997 dev_priv->display.queue_flip = intel_default_queue_flip;
12998
12999 switch (INTEL_INFO(dev)->gen) {
13000 case 2:
13001 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13002 break;
13003
13004 case 3:
13005 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13006 break;
13007
13008 case 4:
13009 case 5:
13010 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13011 break;
13012
13013 case 6:
13014 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13015 break;
13016 case 7:
13017 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13018 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13019 break;
13020 case 9:
13021 dev_priv->display.queue_flip = intel_gen9_queue_flip;
13022 break;
13023 }
13024
13025 intel_panel_init_backlight_funcs(dev);
13026
13027 mutex_init(&dev_priv->pps_mutex);
13028 }
13029
13030 /*
13031 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13032 * resume, or other times. This quirk makes sure that's the case for
13033 * affected systems.
13034 */
13035 static void quirk_pipea_force(struct drm_device *dev)
13036 {
13037 struct drm_i915_private *dev_priv = dev->dev_private;
13038
13039 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13040 DRM_INFO("applying pipe a force quirk\n");
13041 }
13042
13043 static void quirk_pipeb_force(struct drm_device *dev)
13044 {
13045 struct drm_i915_private *dev_priv = dev->dev_private;
13046
13047 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13048 DRM_INFO("applying pipe b force quirk\n");
13049 }
13050
13051 /*
13052 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13053 */
13054 static void quirk_ssc_force_disable(struct drm_device *dev)
13055 {
13056 struct drm_i915_private *dev_priv = dev->dev_private;
13057 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13058 DRM_INFO("applying lvds SSC disable quirk\n");
13059 }
13060
13061 /*
13062 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13063 * brightness value
13064 */
13065 static void quirk_invert_brightness(struct drm_device *dev)
13066 {
13067 struct drm_i915_private *dev_priv = dev->dev_private;
13068 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13069 DRM_INFO("applying inverted panel brightness quirk\n");
13070 }
13071
13072 /* Some VBT's incorrectly indicate no backlight is present */
13073 static void quirk_backlight_present(struct drm_device *dev)
13074 {
13075 struct drm_i915_private *dev_priv = dev->dev_private;
13076 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13077 DRM_INFO("applying backlight present quirk\n");
13078 }
13079
13080 struct intel_quirk {
13081 int device;
13082 int subsystem_vendor;
13083 int subsystem_device;
13084 void (*hook)(struct drm_device *dev);
13085 };
13086
13087 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13088 struct intel_dmi_quirk {
13089 void (*hook)(struct drm_device *dev);
13090 const struct dmi_system_id (*dmi_id_list)[];
13091 };
13092
13093 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13094 {
13095 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13096 return 1;
13097 }
13098
13099 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13100 {
13101 .dmi_id_list = &(const struct dmi_system_id[]) {
13102 {
13103 .callback = intel_dmi_reverse_brightness,
13104 .ident = "NCR Corporation",
13105 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13106 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13107 },
13108 },
13109 { } /* terminating entry */
13110 },
13111 .hook = quirk_invert_brightness,
13112 },
13113 };
13114
13115 static struct intel_quirk intel_quirks[] = {
13116 /* HP Mini needs pipe A force quirk (LP: #322104) */
13117 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13118
13119 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13120 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13121
13122 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13123 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13124
13125 /* 830 needs to leave pipe A & dpll A up */
13126 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13127
13128 /* 830 needs to leave pipe B & dpll B up */
13129 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13130
13131 /* Lenovo U160 cannot use SSC on LVDS */
13132 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13133
13134 /* Sony Vaio Y cannot use SSC on LVDS */
13135 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13136
13137 /* Acer Aspire 5734Z must invert backlight brightness */
13138 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13139
13140 /* Acer/eMachines G725 */
13141 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13142
13143 /* Acer/eMachines e725 */
13144 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13145
13146 /* Acer/Packard Bell NCL20 */
13147 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13148
13149 /* Acer Aspire 4736Z */
13150 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13151
13152 /* Acer Aspire 5336 */
13153 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13154
13155 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13156 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13157
13158 /* Acer C720 Chromebook (Core i3 4005U) */
13159 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13160
13161 /* Apple Macbook 2,1 (Core 2 T7400) */
13162 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13163
13164 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13165 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13166
13167 /* HP Chromebook 14 (Celeron 2955U) */
13168 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13169 };
13170
13171 static void intel_init_quirks(struct drm_device *dev)
13172 {
13173 struct pci_dev *d = dev->pdev;
13174 int i;
13175
13176 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13177 struct intel_quirk *q = &intel_quirks[i];
13178
13179 if (d->device == q->device &&
13180 (d->subsystem_vendor == q->subsystem_vendor ||
13181 q->subsystem_vendor == PCI_ANY_ID) &&
13182 (d->subsystem_device == q->subsystem_device ||
13183 q->subsystem_device == PCI_ANY_ID))
13184 q->hook(dev);
13185 }
13186 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13187 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13188 intel_dmi_quirks[i].hook(dev);
13189 }
13190 }
13191
13192 /* Disable the VGA plane that we never use */
13193 static void i915_disable_vga(struct drm_device *dev)
13194 {
13195 struct drm_i915_private *dev_priv = dev->dev_private;
13196 u8 sr1;
13197 u32 vga_reg = i915_vgacntrl_reg(dev);
13198
13199 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13200 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13201 outb(SR01, VGA_SR_INDEX);
13202 sr1 = inb(VGA_SR_DATA);
13203 outb(sr1 | 1<<5, VGA_SR_DATA);
13204 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13205 udelay(300);
13206
13207 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13208 POSTING_READ(vga_reg);
13209 }
13210
13211 void intel_modeset_init_hw(struct drm_device *dev)
13212 {
13213 intel_prepare_ddi(dev);
13214
13215 if (IS_VALLEYVIEW(dev))
13216 vlv_update_cdclk(dev);
13217
13218 intel_init_clock_gating(dev);
13219
13220 intel_enable_gt_powersave(dev);
13221 }
13222
13223 void intel_modeset_init(struct drm_device *dev)
13224 {
13225 struct drm_i915_private *dev_priv = dev->dev_private;
13226 int sprite, ret;
13227 enum pipe pipe;
13228 struct intel_crtc *crtc;
13229
13230 drm_mode_config_init(dev);
13231
13232 dev->mode_config.min_width = 0;
13233 dev->mode_config.min_height = 0;
13234
13235 dev->mode_config.preferred_depth = 24;
13236 dev->mode_config.prefer_shadow = 1;
13237
13238 dev->mode_config.funcs = &intel_mode_funcs;
13239
13240 intel_init_quirks(dev);
13241
13242 intel_init_pm(dev);
13243
13244 if (INTEL_INFO(dev)->num_pipes == 0)
13245 return;
13246
13247 intel_init_display(dev);
13248 intel_init_audio(dev);
13249
13250 if (IS_GEN2(dev)) {
13251 dev->mode_config.max_width = 2048;
13252 dev->mode_config.max_height = 2048;
13253 } else if (IS_GEN3(dev)) {
13254 dev->mode_config.max_width = 4096;
13255 dev->mode_config.max_height = 4096;
13256 } else {
13257 dev->mode_config.max_width = 8192;
13258 dev->mode_config.max_height = 8192;
13259 }
13260
13261 if (IS_845G(dev) || IS_I865G(dev)) {
13262 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13263 dev->mode_config.cursor_height = 1023;
13264 } else if (IS_GEN2(dev)) {
13265 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13266 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13267 } else {
13268 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13269 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13270 }
13271
13272 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13273
13274 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13275 INTEL_INFO(dev)->num_pipes,
13276 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13277
13278 for_each_pipe(dev_priv, pipe) {
13279 intel_crtc_init(dev, pipe);
13280 for_each_sprite(pipe, sprite) {
13281 ret = intel_plane_init(dev, pipe, sprite);
13282 if (ret)
13283 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13284 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13285 }
13286 }
13287
13288 intel_init_dpio(dev);
13289
13290 intel_shared_dpll_init(dev);
13291
13292 /* Just disable it once at startup */
13293 i915_disable_vga(dev);
13294 intel_setup_outputs(dev);
13295
13296 /* Just in case the BIOS is doing something questionable. */
13297 intel_fbc_disable(dev);
13298
13299 drm_modeset_lock_all(dev);
13300 intel_modeset_setup_hw_state(dev, false);
13301 drm_modeset_unlock_all(dev);
13302
13303 for_each_intel_crtc(dev, crtc) {
13304 if (!crtc->active)
13305 continue;
13306
13307 /*
13308 * Note that reserving the BIOS fb up front prevents us
13309 * from stuffing other stolen allocations like the ring
13310 * on top. This prevents some ugliness at boot time, and
13311 * can even allow for smooth boot transitions if the BIOS
13312 * fb is large enough for the active pipe configuration.
13313 */
13314 if (dev_priv->display.get_initial_plane_config) {
13315 dev_priv->display.get_initial_plane_config(crtc,
13316 &crtc->plane_config);
13317 /*
13318 * If the fb is shared between multiple heads, we'll
13319 * just get the first one.
13320 */
13321 intel_find_plane_obj(crtc, &crtc->plane_config);
13322 }
13323 }
13324 }
13325
13326 static void intel_enable_pipe_a(struct drm_device *dev)
13327 {
13328 struct intel_connector *connector;
13329 struct drm_connector *crt = NULL;
13330 struct intel_load_detect_pipe load_detect_temp;
13331 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13332
13333 /* We can't just switch on the pipe A, we need to set things up with a
13334 * proper mode and output configuration. As a gross hack, enable pipe A
13335 * by enabling the load detect pipe once. */
13336 list_for_each_entry(connector,
13337 &dev->mode_config.connector_list,
13338 base.head) {
13339 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13340 crt = &connector->base;
13341 break;
13342 }
13343 }
13344
13345 if (!crt)
13346 return;
13347
13348 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13349 intel_release_load_detect_pipe(crt, &load_detect_temp);
13350 }
13351
13352 static bool
13353 intel_check_plane_mapping(struct intel_crtc *crtc)
13354 {
13355 struct drm_device *dev = crtc->base.dev;
13356 struct drm_i915_private *dev_priv = dev->dev_private;
13357 u32 reg, val;
13358
13359 if (INTEL_INFO(dev)->num_pipes == 1)
13360 return true;
13361
13362 reg = DSPCNTR(!crtc->plane);
13363 val = I915_READ(reg);
13364
13365 if ((val & DISPLAY_PLANE_ENABLE) &&
13366 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13367 return false;
13368
13369 return true;
13370 }
13371
13372 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13373 {
13374 struct drm_device *dev = crtc->base.dev;
13375 struct drm_i915_private *dev_priv = dev->dev_private;
13376 u32 reg;
13377
13378 /* Clear any frame start delays used for debugging left by the BIOS */
13379 reg = PIPECONF(crtc->config->cpu_transcoder);
13380 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13381
13382 /* restore vblank interrupts to correct state */
13383 if (crtc->active) {
13384 update_scanline_offset(crtc);
13385 drm_vblank_on(dev, crtc->pipe);
13386 } else
13387 drm_vblank_off(dev, crtc->pipe);
13388
13389 /* We need to sanitize the plane -> pipe mapping first because this will
13390 * disable the crtc (and hence change the state) if it is wrong. Note
13391 * that gen4+ has a fixed plane -> pipe mapping. */
13392 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13393 struct intel_connector *connector;
13394 bool plane;
13395
13396 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13397 crtc->base.base.id);
13398
13399 /* Pipe has the wrong plane attached and the plane is active.
13400 * Temporarily change the plane mapping and disable everything
13401 * ... */
13402 plane = crtc->plane;
13403 crtc->plane = !plane;
13404 crtc->primary_enabled = true;
13405 dev_priv->display.crtc_disable(&crtc->base);
13406 crtc->plane = plane;
13407
13408 /* ... and break all links. */
13409 list_for_each_entry(connector, &dev->mode_config.connector_list,
13410 base.head) {
13411 if (connector->encoder->base.crtc != &crtc->base)
13412 continue;
13413
13414 connector->base.dpms = DRM_MODE_DPMS_OFF;
13415 connector->base.encoder = NULL;
13416 }
13417 /* multiple connectors may have the same encoder:
13418 * handle them and break crtc link separately */
13419 list_for_each_entry(connector, &dev->mode_config.connector_list,
13420 base.head)
13421 if (connector->encoder->base.crtc == &crtc->base) {
13422 connector->encoder->base.crtc = NULL;
13423 connector->encoder->connectors_active = false;
13424 }
13425
13426 WARN_ON(crtc->active);
13427 crtc->base.enabled = false;
13428 }
13429
13430 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13431 crtc->pipe == PIPE_A && !crtc->active) {
13432 /* BIOS forgot to enable pipe A, this mostly happens after
13433 * resume. Force-enable the pipe to fix this, the update_dpms
13434 * call below we restore the pipe to the right state, but leave
13435 * the required bits on. */
13436 intel_enable_pipe_a(dev);
13437 }
13438
13439 /* Adjust the state of the output pipe according to whether we
13440 * have active connectors/encoders. */
13441 intel_crtc_update_dpms(&crtc->base);
13442
13443 if (crtc->active != crtc->base.enabled) {
13444 struct intel_encoder *encoder;
13445
13446 /* This can happen either due to bugs in the get_hw_state
13447 * functions or because the pipe is force-enabled due to the
13448 * pipe A quirk. */
13449 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13450 crtc->base.base.id,
13451 crtc->base.enabled ? "enabled" : "disabled",
13452 crtc->active ? "enabled" : "disabled");
13453
13454 crtc->base.enabled = crtc->active;
13455
13456 /* Because we only establish the connector -> encoder ->
13457 * crtc links if something is active, this means the
13458 * crtc is now deactivated. Break the links. connector
13459 * -> encoder links are only establish when things are
13460 * actually up, hence no need to break them. */
13461 WARN_ON(crtc->active);
13462
13463 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13464 WARN_ON(encoder->connectors_active);
13465 encoder->base.crtc = NULL;
13466 }
13467 }
13468
13469 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13470 /*
13471 * We start out with underrun reporting disabled to avoid races.
13472 * For correct bookkeeping mark this on active crtcs.
13473 *
13474 * Also on gmch platforms we dont have any hardware bits to
13475 * disable the underrun reporting. Which means we need to start
13476 * out with underrun reporting disabled also on inactive pipes,
13477 * since otherwise we'll complain about the garbage we read when
13478 * e.g. coming up after runtime pm.
13479 *
13480 * No protection against concurrent access is required - at
13481 * worst a fifo underrun happens which also sets this to false.
13482 */
13483 crtc->cpu_fifo_underrun_disabled = true;
13484 crtc->pch_fifo_underrun_disabled = true;
13485 }
13486 }
13487
13488 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13489 {
13490 struct intel_connector *connector;
13491 struct drm_device *dev = encoder->base.dev;
13492
13493 /* We need to check both for a crtc link (meaning that the
13494 * encoder is active and trying to read from a pipe) and the
13495 * pipe itself being active. */
13496 bool has_active_crtc = encoder->base.crtc &&
13497 to_intel_crtc(encoder->base.crtc)->active;
13498
13499 if (encoder->connectors_active && !has_active_crtc) {
13500 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13501 encoder->base.base.id,
13502 encoder->base.name);
13503
13504 /* Connector is active, but has no active pipe. This is
13505 * fallout from our resume register restoring. Disable
13506 * the encoder manually again. */
13507 if (encoder->base.crtc) {
13508 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13509 encoder->base.base.id,
13510 encoder->base.name);
13511 encoder->disable(encoder);
13512 if (encoder->post_disable)
13513 encoder->post_disable(encoder);
13514 }
13515 encoder->base.crtc = NULL;
13516 encoder->connectors_active = false;
13517
13518 /* Inconsistent output/port/pipe state happens presumably due to
13519 * a bug in one of the get_hw_state functions. Or someplace else
13520 * in our code, like the register restore mess on resume. Clamp
13521 * things to off as a safer default. */
13522 list_for_each_entry(connector,
13523 &dev->mode_config.connector_list,
13524 base.head) {
13525 if (connector->encoder != encoder)
13526 continue;
13527 connector->base.dpms = DRM_MODE_DPMS_OFF;
13528 connector->base.encoder = NULL;
13529 }
13530 }
13531 /* Enabled encoders without active connectors will be fixed in
13532 * the crtc fixup. */
13533 }
13534
13535 void i915_redisable_vga_power_on(struct drm_device *dev)
13536 {
13537 struct drm_i915_private *dev_priv = dev->dev_private;
13538 u32 vga_reg = i915_vgacntrl_reg(dev);
13539
13540 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13541 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13542 i915_disable_vga(dev);
13543 }
13544 }
13545
13546 void i915_redisable_vga(struct drm_device *dev)
13547 {
13548 struct drm_i915_private *dev_priv = dev->dev_private;
13549
13550 /* This function can be called both from intel_modeset_setup_hw_state or
13551 * at a very early point in our resume sequence, where the power well
13552 * structures are not yet restored. Since this function is at a very
13553 * paranoid "someone might have enabled VGA while we were not looking"
13554 * level, just check if the power well is enabled instead of trying to
13555 * follow the "don't touch the power well if we don't need it" policy
13556 * the rest of the driver uses. */
13557 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13558 return;
13559
13560 i915_redisable_vga_power_on(dev);
13561 }
13562
13563 static bool primary_get_hw_state(struct intel_crtc *crtc)
13564 {
13565 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13566
13567 if (!crtc->active)
13568 return false;
13569
13570 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13571 }
13572
13573 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13574 {
13575 struct drm_i915_private *dev_priv = dev->dev_private;
13576 enum pipe pipe;
13577 struct intel_crtc *crtc;
13578 struct intel_encoder *encoder;
13579 struct intel_connector *connector;
13580 int i;
13581
13582 for_each_intel_crtc(dev, crtc) {
13583 memset(crtc->config, 0, sizeof(*crtc->config));
13584
13585 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13586
13587 crtc->active = dev_priv->display.get_pipe_config(crtc,
13588 crtc->config);
13589
13590 crtc->base.enabled = crtc->active;
13591 crtc->primary_enabled = primary_get_hw_state(crtc);
13592
13593 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13594 crtc->base.base.id,
13595 crtc->active ? "enabled" : "disabled");
13596 }
13597
13598 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13599 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13600
13601 pll->on = pll->get_hw_state(dev_priv, pll,
13602 &pll->config.hw_state);
13603 pll->active = 0;
13604 pll->config.crtc_mask = 0;
13605 for_each_intel_crtc(dev, crtc) {
13606 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13607 pll->active++;
13608 pll->config.crtc_mask |= 1 << crtc->pipe;
13609 }
13610 }
13611
13612 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13613 pll->name, pll->config.crtc_mask, pll->on);
13614
13615 if (pll->config.crtc_mask)
13616 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13617 }
13618
13619 for_each_intel_encoder(dev, encoder) {
13620 pipe = 0;
13621
13622 if (encoder->get_hw_state(encoder, &pipe)) {
13623 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13624 encoder->base.crtc = &crtc->base;
13625 encoder->get_config(encoder, crtc->config);
13626 } else {
13627 encoder->base.crtc = NULL;
13628 }
13629
13630 encoder->connectors_active = false;
13631 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13632 encoder->base.base.id,
13633 encoder->base.name,
13634 encoder->base.crtc ? "enabled" : "disabled",
13635 pipe_name(pipe));
13636 }
13637
13638 list_for_each_entry(connector, &dev->mode_config.connector_list,
13639 base.head) {
13640 if (connector->get_hw_state(connector)) {
13641 connector->base.dpms = DRM_MODE_DPMS_ON;
13642 connector->encoder->connectors_active = true;
13643 connector->base.encoder = &connector->encoder->base;
13644 } else {
13645 connector->base.dpms = DRM_MODE_DPMS_OFF;
13646 connector->base.encoder = NULL;
13647 }
13648 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13649 connector->base.base.id,
13650 connector->base.name,
13651 connector->base.encoder ? "enabled" : "disabled");
13652 }
13653 }
13654
13655 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13656 * and i915 state tracking structures. */
13657 void intel_modeset_setup_hw_state(struct drm_device *dev,
13658 bool force_restore)
13659 {
13660 struct drm_i915_private *dev_priv = dev->dev_private;
13661 enum pipe pipe;
13662 struct intel_crtc *crtc;
13663 struct intel_encoder *encoder;
13664 int i;
13665
13666 intel_modeset_readout_hw_state(dev);
13667
13668 /*
13669 * Now that we have the config, copy it to each CRTC struct
13670 * Note that this could go away if we move to using crtc_config
13671 * checking everywhere.
13672 */
13673 for_each_intel_crtc(dev, crtc) {
13674 if (crtc->active && i915.fastboot) {
13675 intel_mode_from_pipe_config(&crtc->base.mode,
13676 crtc->config);
13677 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13678 crtc->base.base.id);
13679 drm_mode_debug_printmodeline(&crtc->base.mode);
13680 }
13681 }
13682
13683 /* HW state is read out, now we need to sanitize this mess. */
13684 for_each_intel_encoder(dev, encoder) {
13685 intel_sanitize_encoder(encoder);
13686 }
13687
13688 for_each_pipe(dev_priv, pipe) {
13689 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13690 intel_sanitize_crtc(crtc);
13691 intel_dump_pipe_config(crtc, crtc->config,
13692 "[setup_hw_state]");
13693 }
13694
13695 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13696 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13697
13698 if (!pll->on || pll->active)
13699 continue;
13700
13701 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13702
13703 pll->disable(dev_priv, pll);
13704 pll->on = false;
13705 }
13706
13707 if (IS_GEN9(dev))
13708 skl_wm_get_hw_state(dev);
13709 else if (HAS_PCH_SPLIT(dev))
13710 ilk_wm_get_hw_state(dev);
13711
13712 if (force_restore) {
13713 i915_redisable_vga(dev);
13714
13715 /*
13716 * We need to use raw interfaces for restoring state to avoid
13717 * checking (bogus) intermediate states.
13718 */
13719 for_each_pipe(dev_priv, pipe) {
13720 struct drm_crtc *crtc =
13721 dev_priv->pipe_to_crtc_mapping[pipe];
13722
13723 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13724 crtc->primary->fb);
13725 }
13726 } else {
13727 intel_modeset_update_staged_output_state(dev);
13728 }
13729
13730 intel_modeset_check_state(dev);
13731 }
13732
13733 void intel_modeset_gem_init(struct drm_device *dev)
13734 {
13735 struct drm_i915_private *dev_priv = dev->dev_private;
13736 struct drm_crtc *c;
13737 struct drm_i915_gem_object *obj;
13738
13739 mutex_lock(&dev->struct_mutex);
13740 intel_init_gt_powersave(dev);
13741 mutex_unlock(&dev->struct_mutex);
13742
13743 /*
13744 * There may be no VBT; and if the BIOS enabled SSC we can
13745 * just keep using it to avoid unnecessary flicker. Whereas if the
13746 * BIOS isn't using it, don't assume it will work even if the VBT
13747 * indicates as much.
13748 */
13749 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13750 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13751 DREF_SSC1_ENABLE);
13752
13753 intel_modeset_init_hw(dev);
13754
13755 intel_setup_overlay(dev);
13756
13757 /*
13758 * Make sure any fbs we allocated at startup are properly
13759 * pinned & fenced. When we do the allocation it's too early
13760 * for this.
13761 */
13762 mutex_lock(&dev->struct_mutex);
13763 for_each_crtc(dev, c) {
13764 obj = intel_fb_obj(c->primary->fb);
13765 if (obj == NULL)
13766 continue;
13767
13768 if (intel_pin_and_fence_fb_obj(c->primary,
13769 c->primary->fb,
13770 NULL)) {
13771 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13772 to_intel_crtc(c)->pipe);
13773 drm_framebuffer_unreference(c->primary->fb);
13774 c->primary->fb = NULL;
13775 update_state_fb(c->primary);
13776 }
13777 }
13778 mutex_unlock(&dev->struct_mutex);
13779
13780 intel_backlight_register(dev);
13781 }
13782
13783 void intel_connector_unregister(struct intel_connector *intel_connector)
13784 {
13785 struct drm_connector *connector = &intel_connector->base;
13786
13787 intel_panel_destroy_backlight(connector);
13788 drm_connector_unregister(connector);
13789 }
13790
13791 void intel_modeset_cleanup(struct drm_device *dev)
13792 {
13793 struct drm_i915_private *dev_priv = dev->dev_private;
13794 struct drm_connector *connector;
13795
13796 intel_disable_gt_powersave(dev);
13797
13798 intel_backlight_unregister(dev);
13799
13800 /*
13801 * Interrupts and polling as the first thing to avoid creating havoc.
13802 * Too much stuff here (turning of connectors, ...) would
13803 * experience fancy races otherwise.
13804 */
13805 intel_irq_uninstall(dev_priv);
13806
13807 /*
13808 * Due to the hpd irq storm handling the hotplug work can re-arm the
13809 * poll handlers. Hence disable polling after hpd handling is shut down.
13810 */
13811 drm_kms_helper_poll_fini(dev);
13812
13813 mutex_lock(&dev->struct_mutex);
13814
13815 intel_unregister_dsm_handler();
13816
13817 intel_fbc_disable(dev);
13818
13819 ironlake_teardown_rc6(dev);
13820
13821 mutex_unlock(&dev->struct_mutex);
13822
13823 /* flush any delayed tasks or pending work */
13824 flush_scheduled_work();
13825
13826 /* destroy the backlight and sysfs files before encoders/connectors */
13827 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13828 struct intel_connector *intel_connector;
13829
13830 intel_connector = to_intel_connector(connector);
13831 intel_connector->unregister(intel_connector);
13832 }
13833
13834 drm_mode_config_cleanup(dev);
13835
13836 intel_cleanup_overlay(dev);
13837
13838 mutex_lock(&dev->struct_mutex);
13839 intel_cleanup_gt_powersave(dev);
13840 mutex_unlock(&dev->struct_mutex);
13841 }
13842
13843 /*
13844 * Return which encoder is currently attached for connector.
13845 */
13846 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13847 {
13848 return &intel_attached_encoder(connector)->base;
13849 }
13850
13851 void intel_connector_attach_encoder(struct intel_connector *connector,
13852 struct intel_encoder *encoder)
13853 {
13854 connector->encoder = encoder;
13855 drm_mode_connector_attach_encoder(&connector->base,
13856 &encoder->base);
13857 }
13858
13859 /*
13860 * set vga decode state - true == enable VGA decode
13861 */
13862 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13863 {
13864 struct drm_i915_private *dev_priv = dev->dev_private;
13865 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13866 u16 gmch_ctrl;
13867
13868 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13869 DRM_ERROR("failed to read control word\n");
13870 return -EIO;
13871 }
13872
13873 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13874 return 0;
13875
13876 if (state)
13877 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13878 else
13879 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13880
13881 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13882 DRM_ERROR("failed to write control word\n");
13883 return -EIO;
13884 }
13885
13886 return 0;
13887 }
13888
13889 struct intel_display_error_state {
13890
13891 u32 power_well_driver;
13892
13893 int num_transcoders;
13894
13895 struct intel_cursor_error_state {
13896 u32 control;
13897 u32 position;
13898 u32 base;
13899 u32 size;
13900 } cursor[I915_MAX_PIPES];
13901
13902 struct intel_pipe_error_state {
13903 bool power_domain_on;
13904 u32 source;
13905 u32 stat;
13906 } pipe[I915_MAX_PIPES];
13907
13908 struct intel_plane_error_state {
13909 u32 control;
13910 u32 stride;
13911 u32 size;
13912 u32 pos;
13913 u32 addr;
13914 u32 surface;
13915 u32 tile_offset;
13916 } plane[I915_MAX_PIPES];
13917
13918 struct intel_transcoder_error_state {
13919 bool power_domain_on;
13920 enum transcoder cpu_transcoder;
13921
13922 u32 conf;
13923
13924 u32 htotal;
13925 u32 hblank;
13926 u32 hsync;
13927 u32 vtotal;
13928 u32 vblank;
13929 u32 vsync;
13930 } transcoder[4];
13931 };
13932
13933 struct intel_display_error_state *
13934 intel_display_capture_error_state(struct drm_device *dev)
13935 {
13936 struct drm_i915_private *dev_priv = dev->dev_private;
13937 struct intel_display_error_state *error;
13938 int transcoders[] = {
13939 TRANSCODER_A,
13940 TRANSCODER_B,
13941 TRANSCODER_C,
13942 TRANSCODER_EDP,
13943 };
13944 int i;
13945
13946 if (INTEL_INFO(dev)->num_pipes == 0)
13947 return NULL;
13948
13949 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13950 if (error == NULL)
13951 return NULL;
13952
13953 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13954 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13955
13956 for_each_pipe(dev_priv, i) {
13957 error->pipe[i].power_domain_on =
13958 __intel_display_power_is_enabled(dev_priv,
13959 POWER_DOMAIN_PIPE(i));
13960 if (!error->pipe[i].power_domain_on)
13961 continue;
13962
13963 error->cursor[i].control = I915_READ(CURCNTR(i));
13964 error->cursor[i].position = I915_READ(CURPOS(i));
13965 error->cursor[i].base = I915_READ(CURBASE(i));
13966
13967 error->plane[i].control = I915_READ(DSPCNTR(i));
13968 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13969 if (INTEL_INFO(dev)->gen <= 3) {
13970 error->plane[i].size = I915_READ(DSPSIZE(i));
13971 error->plane[i].pos = I915_READ(DSPPOS(i));
13972 }
13973 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13974 error->plane[i].addr = I915_READ(DSPADDR(i));
13975 if (INTEL_INFO(dev)->gen >= 4) {
13976 error->plane[i].surface = I915_READ(DSPSURF(i));
13977 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13978 }
13979
13980 error->pipe[i].source = I915_READ(PIPESRC(i));
13981
13982 if (HAS_GMCH_DISPLAY(dev))
13983 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13984 }
13985
13986 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13987 if (HAS_DDI(dev_priv->dev))
13988 error->num_transcoders++; /* Account for eDP. */
13989
13990 for (i = 0; i < error->num_transcoders; i++) {
13991 enum transcoder cpu_transcoder = transcoders[i];
13992
13993 error->transcoder[i].power_domain_on =
13994 __intel_display_power_is_enabled(dev_priv,
13995 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13996 if (!error->transcoder[i].power_domain_on)
13997 continue;
13998
13999 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14000
14001 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14002 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14003 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14004 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14005 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14006 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14007 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14008 }
14009
14010 return error;
14011 }
14012
14013 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14014
14015 void
14016 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14017 struct drm_device *dev,
14018 struct intel_display_error_state *error)
14019 {
14020 struct drm_i915_private *dev_priv = dev->dev_private;
14021 int i;
14022
14023 if (!error)
14024 return;
14025
14026 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14027 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14028 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14029 error->power_well_driver);
14030 for_each_pipe(dev_priv, i) {
14031 err_printf(m, "Pipe [%d]:\n", i);
14032 err_printf(m, " Power: %s\n",
14033 error->pipe[i].power_domain_on ? "on" : "off");
14034 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14035 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14036
14037 err_printf(m, "Plane [%d]:\n", i);
14038 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14039 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14040 if (INTEL_INFO(dev)->gen <= 3) {
14041 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14042 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14043 }
14044 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14045 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14046 if (INTEL_INFO(dev)->gen >= 4) {
14047 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14048 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14049 }
14050
14051 err_printf(m, "Cursor [%d]:\n", i);
14052 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14053 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14054 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14055 }
14056
14057 for (i = 0; i < error->num_transcoders; i++) {
14058 err_printf(m, "CPU transcoder: %c\n",
14059 transcoder_name(error->transcoder[i].cpu_transcoder));
14060 err_printf(m, " Power: %s\n",
14061 error->transcoder[i].power_domain_on ? "on" : "off");
14062 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14063 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14064 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14065 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14066 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14067 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14068 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14069 }
14070 }
14071
14072 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14073 {
14074 struct intel_crtc *crtc;
14075
14076 for_each_intel_crtc(dev, crtc) {
14077 struct intel_unpin_work *work;
14078
14079 spin_lock_irq(&dev->event_lock);
14080
14081 work = crtc->unpin_work;
14082
14083 if (work && work->event &&
14084 work->event->base.file_priv == file) {
14085 kfree(work->event);
14086 work->event = NULL;
14087 }
14088
14089 spin_unlock_irq(&dev->event_lock);
14090 }
14091 }
Linux kernel - Deliverables
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