2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
51 /* Primary plane formats for gen <= 3 */
52 static const uint32_t i8xx_primary_formats
[] = {
59 /* Primary plane formats for gen >= 4 */
60 static const uint32_t i965_primary_formats
[] = {
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_XBGR2101010
,
69 static const uint32_t skl_primary_formats
[] = {
76 DRM_FORMAT_XRGB2101010
,
77 DRM_FORMAT_XBGR2101010
,
85 static const uint32_t intel_cursor_formats
[] = {
89 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
90 struct intel_crtc_state
*pipe_config
);
91 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
92 struct intel_crtc_state
*pipe_config
);
94 static int intel_framebuffer_init(struct drm_device
*dev
,
95 struct intel_framebuffer
*ifb
,
96 struct drm_mode_fb_cmd2
*mode_cmd
,
97 struct drm_i915_gem_object
*obj
);
98 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
99 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
100 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
102 struct intel_link_m_n
*m_n
,
103 struct intel_link_m_n
*m2_n2
);
104 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
105 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
106 static void haswell_set_pipemisc(struct drm_crtc
*crtc
);
107 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
108 const struct intel_crtc_state
*pipe_config
);
109 static void chv_prepare_pll(struct intel_crtc
*crtc
,
110 const struct intel_crtc_state
*pipe_config
);
111 static void intel_begin_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
112 static void intel_finish_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
113 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
114 struct intel_crtc_state
*crtc_state
);
115 static void skylake_pfit_enable(struct intel_crtc
*crtc
);
116 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
);
117 static void ironlake_pfit_enable(struct intel_crtc
*crtc
);
118 static void intel_modeset_setup_hw_state(struct drm_device
*dev
);
119 static void intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
);
127 int p2_slow
, p2_fast
;
130 typedef struct intel_limit intel_limit_t
;
132 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
139 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv
->sb_lock
);
143 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
144 CCK_FUSE_HPLL_FREQ_MASK
;
145 mutex_unlock(&dev_priv
->sb_lock
);
147 return vco_freq
[hpll_freq
] * 1000;
150 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
151 const char *name
, u32 reg
, int ref_freq
)
156 mutex_lock(&dev_priv
->sb_lock
);
157 val
= vlv_cck_read(dev_priv
, reg
);
158 mutex_unlock(&dev_priv
->sb_lock
);
160 divider
= val
& CCK_FREQUENCY_VALUES
;
162 WARN((val
& CCK_FREQUENCY_STATUS
) !=
163 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
164 "%s change in progress\n", name
);
166 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
169 static int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
170 const char *name
, u32 reg
)
172 if (dev_priv
->hpll_freq
== 0)
173 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
175 return vlv_get_cck_clock(dev_priv
, name
, reg
,
176 dev_priv
->hpll_freq
);
180 intel_pch_rawclk(struct drm_i915_private
*dev_priv
)
182 return (I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
) * 1000;
186 intel_vlv_hrawclk(struct drm_i915_private
*dev_priv
)
188 /* RAWCLK_FREQ_VLV register updated from power well code */
189 return vlv_get_cck_clock_hpll(dev_priv
, "hrawclk",
190 CCK_DISPLAY_REF_CLOCK_CONTROL
);
194 intel_g4x_hrawclk(struct drm_i915_private
*dev_priv
)
198 /* hrawclock is 1/4 the FSB frequency */
199 clkcfg
= I915_READ(CLKCFG
);
200 switch (clkcfg
& CLKCFG_FSB_MASK
) {
209 case CLKCFG_FSB_1067
:
211 case CLKCFG_FSB_1333
:
213 /* these two are just a guess; one of them might be right */
214 case CLKCFG_FSB_1600
:
215 case CLKCFG_FSB_1600_ALT
:
222 void intel_update_rawclk(struct drm_i915_private
*dev_priv
)
224 if (HAS_PCH_SPLIT(dev_priv
))
225 dev_priv
->rawclk_freq
= intel_pch_rawclk(dev_priv
);
226 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
227 dev_priv
->rawclk_freq
= intel_vlv_hrawclk(dev_priv
);
228 else if (IS_G4X(dev_priv
) || IS_PINEVIEW(dev_priv
))
229 dev_priv
->rawclk_freq
= intel_g4x_hrawclk(dev_priv
);
231 return; /* no rawclk on other platforms, or no need to know it */
233 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv
->rawclk_freq
);
236 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
238 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
241 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
242 CCK_CZ_CLOCK_CONTROL
);
244 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
247 static inline u32
/* units of 100MHz */
248 intel_fdi_link_freq(struct drm_i915_private
*dev_priv
,
249 const struct intel_crtc_state
*pipe_config
)
251 if (HAS_DDI(dev_priv
))
252 return pipe_config
->port_clock
; /* SPLL */
253 else if (IS_GEN5(dev_priv
))
254 return ((I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2) * 10000;
259 static const intel_limit_t intel_limits_i8xx_dac
= {
260 .dot
= { .min
= 25000, .max
= 350000 },
261 .vco
= { .min
= 908000, .max
= 1512000 },
262 .n
= { .min
= 2, .max
= 16 },
263 .m
= { .min
= 96, .max
= 140 },
264 .m1
= { .min
= 18, .max
= 26 },
265 .m2
= { .min
= 6, .max
= 16 },
266 .p
= { .min
= 4, .max
= 128 },
267 .p1
= { .min
= 2, .max
= 33 },
268 .p2
= { .dot_limit
= 165000,
269 .p2_slow
= 4, .p2_fast
= 2 },
272 static const intel_limit_t intel_limits_i8xx_dvo
= {
273 .dot
= { .min
= 25000, .max
= 350000 },
274 .vco
= { .min
= 908000, .max
= 1512000 },
275 .n
= { .min
= 2, .max
= 16 },
276 .m
= { .min
= 96, .max
= 140 },
277 .m1
= { .min
= 18, .max
= 26 },
278 .m2
= { .min
= 6, .max
= 16 },
279 .p
= { .min
= 4, .max
= 128 },
280 .p1
= { .min
= 2, .max
= 33 },
281 .p2
= { .dot_limit
= 165000,
282 .p2_slow
= 4, .p2_fast
= 4 },
285 static const intel_limit_t intel_limits_i8xx_lvds
= {
286 .dot
= { .min
= 25000, .max
= 350000 },
287 .vco
= { .min
= 908000, .max
= 1512000 },
288 .n
= { .min
= 2, .max
= 16 },
289 .m
= { .min
= 96, .max
= 140 },
290 .m1
= { .min
= 18, .max
= 26 },
291 .m2
= { .min
= 6, .max
= 16 },
292 .p
= { .min
= 4, .max
= 128 },
293 .p1
= { .min
= 1, .max
= 6 },
294 .p2
= { .dot_limit
= 165000,
295 .p2_slow
= 14, .p2_fast
= 7 },
298 static const intel_limit_t intel_limits_i9xx_sdvo
= {
299 .dot
= { .min
= 20000, .max
= 400000 },
300 .vco
= { .min
= 1400000, .max
= 2800000 },
301 .n
= { .min
= 1, .max
= 6 },
302 .m
= { .min
= 70, .max
= 120 },
303 .m1
= { .min
= 8, .max
= 18 },
304 .m2
= { .min
= 3, .max
= 7 },
305 .p
= { .min
= 5, .max
= 80 },
306 .p1
= { .min
= 1, .max
= 8 },
307 .p2
= { .dot_limit
= 200000,
308 .p2_slow
= 10, .p2_fast
= 5 },
311 static const intel_limit_t intel_limits_i9xx_lvds
= {
312 .dot
= { .min
= 20000, .max
= 400000 },
313 .vco
= { .min
= 1400000, .max
= 2800000 },
314 .n
= { .min
= 1, .max
= 6 },
315 .m
= { .min
= 70, .max
= 120 },
316 .m1
= { .min
= 8, .max
= 18 },
317 .m2
= { .min
= 3, .max
= 7 },
318 .p
= { .min
= 7, .max
= 98 },
319 .p1
= { .min
= 1, .max
= 8 },
320 .p2
= { .dot_limit
= 112000,
321 .p2_slow
= 14, .p2_fast
= 7 },
325 static const intel_limit_t intel_limits_g4x_sdvo
= {
326 .dot
= { .min
= 25000, .max
= 270000 },
327 .vco
= { .min
= 1750000, .max
= 3500000},
328 .n
= { .min
= 1, .max
= 4 },
329 .m
= { .min
= 104, .max
= 138 },
330 .m1
= { .min
= 17, .max
= 23 },
331 .m2
= { .min
= 5, .max
= 11 },
332 .p
= { .min
= 10, .max
= 30 },
333 .p1
= { .min
= 1, .max
= 3},
334 .p2
= { .dot_limit
= 270000,
340 static const intel_limit_t intel_limits_g4x_hdmi
= {
341 .dot
= { .min
= 22000, .max
= 400000 },
342 .vco
= { .min
= 1750000, .max
= 3500000},
343 .n
= { .min
= 1, .max
= 4 },
344 .m
= { .min
= 104, .max
= 138 },
345 .m1
= { .min
= 16, .max
= 23 },
346 .m2
= { .min
= 5, .max
= 11 },
347 .p
= { .min
= 5, .max
= 80 },
348 .p1
= { .min
= 1, .max
= 8},
349 .p2
= { .dot_limit
= 165000,
350 .p2_slow
= 10, .p2_fast
= 5 },
353 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
354 .dot
= { .min
= 20000, .max
= 115000 },
355 .vco
= { .min
= 1750000, .max
= 3500000 },
356 .n
= { .min
= 1, .max
= 3 },
357 .m
= { .min
= 104, .max
= 138 },
358 .m1
= { .min
= 17, .max
= 23 },
359 .m2
= { .min
= 5, .max
= 11 },
360 .p
= { .min
= 28, .max
= 112 },
361 .p1
= { .min
= 2, .max
= 8 },
362 .p2
= { .dot_limit
= 0,
363 .p2_slow
= 14, .p2_fast
= 14
367 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
368 .dot
= { .min
= 80000, .max
= 224000 },
369 .vco
= { .min
= 1750000, .max
= 3500000 },
370 .n
= { .min
= 1, .max
= 3 },
371 .m
= { .min
= 104, .max
= 138 },
372 .m1
= { .min
= 17, .max
= 23 },
373 .m2
= { .min
= 5, .max
= 11 },
374 .p
= { .min
= 14, .max
= 42 },
375 .p1
= { .min
= 2, .max
= 6 },
376 .p2
= { .dot_limit
= 0,
377 .p2_slow
= 7, .p2_fast
= 7
381 static const intel_limit_t intel_limits_pineview_sdvo
= {
382 .dot
= { .min
= 20000, .max
= 400000},
383 .vco
= { .min
= 1700000, .max
= 3500000 },
384 /* Pineview's Ncounter is a ring counter */
385 .n
= { .min
= 3, .max
= 6 },
386 .m
= { .min
= 2, .max
= 256 },
387 /* Pineview only has one combined m divider, which we treat as m2. */
388 .m1
= { .min
= 0, .max
= 0 },
389 .m2
= { .min
= 0, .max
= 254 },
390 .p
= { .min
= 5, .max
= 80 },
391 .p1
= { .min
= 1, .max
= 8 },
392 .p2
= { .dot_limit
= 200000,
393 .p2_slow
= 10, .p2_fast
= 5 },
396 static const intel_limit_t intel_limits_pineview_lvds
= {
397 .dot
= { .min
= 20000, .max
= 400000 },
398 .vco
= { .min
= 1700000, .max
= 3500000 },
399 .n
= { .min
= 3, .max
= 6 },
400 .m
= { .min
= 2, .max
= 256 },
401 .m1
= { .min
= 0, .max
= 0 },
402 .m2
= { .min
= 0, .max
= 254 },
403 .p
= { .min
= 7, .max
= 112 },
404 .p1
= { .min
= 1, .max
= 8 },
405 .p2
= { .dot_limit
= 112000,
406 .p2_slow
= 14, .p2_fast
= 14 },
409 /* Ironlake / Sandybridge
411 * We calculate clock using (register_value + 2) for N/M1/M2, so here
412 * the range value for them is (actual_value - 2).
414 static const intel_limit_t intel_limits_ironlake_dac
= {
415 .dot
= { .min
= 25000, .max
= 350000 },
416 .vco
= { .min
= 1760000, .max
= 3510000 },
417 .n
= { .min
= 1, .max
= 5 },
418 .m
= { .min
= 79, .max
= 127 },
419 .m1
= { .min
= 12, .max
= 22 },
420 .m2
= { .min
= 5, .max
= 9 },
421 .p
= { .min
= 5, .max
= 80 },
422 .p1
= { .min
= 1, .max
= 8 },
423 .p2
= { .dot_limit
= 225000,
424 .p2_slow
= 10, .p2_fast
= 5 },
427 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
428 .dot
= { .min
= 25000, .max
= 350000 },
429 .vco
= { .min
= 1760000, .max
= 3510000 },
430 .n
= { .min
= 1, .max
= 3 },
431 .m
= { .min
= 79, .max
= 118 },
432 .m1
= { .min
= 12, .max
= 22 },
433 .m2
= { .min
= 5, .max
= 9 },
434 .p
= { .min
= 28, .max
= 112 },
435 .p1
= { .min
= 2, .max
= 8 },
436 .p2
= { .dot_limit
= 225000,
437 .p2_slow
= 14, .p2_fast
= 14 },
440 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
441 .dot
= { .min
= 25000, .max
= 350000 },
442 .vco
= { .min
= 1760000, .max
= 3510000 },
443 .n
= { .min
= 1, .max
= 3 },
444 .m
= { .min
= 79, .max
= 127 },
445 .m1
= { .min
= 12, .max
= 22 },
446 .m2
= { .min
= 5, .max
= 9 },
447 .p
= { .min
= 14, .max
= 56 },
448 .p1
= { .min
= 2, .max
= 8 },
449 .p2
= { .dot_limit
= 225000,
450 .p2_slow
= 7, .p2_fast
= 7 },
453 /* LVDS 100mhz refclk limits. */
454 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
455 .dot
= { .min
= 25000, .max
= 350000 },
456 .vco
= { .min
= 1760000, .max
= 3510000 },
457 .n
= { .min
= 1, .max
= 2 },
458 .m
= { .min
= 79, .max
= 126 },
459 .m1
= { .min
= 12, .max
= 22 },
460 .m2
= { .min
= 5, .max
= 9 },
461 .p
= { .min
= 28, .max
= 112 },
462 .p1
= { .min
= 2, .max
= 8 },
463 .p2
= { .dot_limit
= 225000,
464 .p2_slow
= 14, .p2_fast
= 14 },
467 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
468 .dot
= { .min
= 25000, .max
= 350000 },
469 .vco
= { .min
= 1760000, .max
= 3510000 },
470 .n
= { .min
= 1, .max
= 3 },
471 .m
= { .min
= 79, .max
= 126 },
472 .m1
= { .min
= 12, .max
= 22 },
473 .m2
= { .min
= 5, .max
= 9 },
474 .p
= { .min
= 14, .max
= 42 },
475 .p1
= { .min
= 2, .max
= 6 },
476 .p2
= { .dot_limit
= 225000,
477 .p2_slow
= 7, .p2_fast
= 7 },
480 static const intel_limit_t intel_limits_vlv
= {
482 * These are the data rate limits (measured in fast clocks)
483 * since those are the strictest limits we have. The fast
484 * clock and actual rate limits are more relaxed, so checking
485 * them would make no difference.
487 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
488 .vco
= { .min
= 4000000, .max
= 6000000 },
489 .n
= { .min
= 1, .max
= 7 },
490 .m1
= { .min
= 2, .max
= 3 },
491 .m2
= { .min
= 11, .max
= 156 },
492 .p1
= { .min
= 2, .max
= 3 },
493 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
496 static const intel_limit_t intel_limits_chv
= {
498 * These are the data rate limits (measured in fast clocks)
499 * since those are the strictest limits we have. The fast
500 * clock and actual rate limits are more relaxed, so checking
501 * them would make no difference.
503 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
504 .vco
= { .min
= 4800000, .max
= 6480000 },
505 .n
= { .min
= 1, .max
= 1 },
506 .m1
= { .min
= 2, .max
= 2 },
507 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
508 .p1
= { .min
= 2, .max
= 4 },
509 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
512 static const intel_limit_t intel_limits_bxt
= {
513 /* FIXME: find real dot limits */
514 .dot
= { .min
= 0, .max
= INT_MAX
},
515 .vco
= { .min
= 4800000, .max
= 6700000 },
516 .n
= { .min
= 1, .max
= 1 },
517 .m1
= { .min
= 2, .max
= 2 },
518 /* FIXME: find real m2 limits */
519 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
520 .p1
= { .min
= 2, .max
= 4 },
521 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
525 needs_modeset(struct drm_crtc_state
*state
)
527 return drm_atomic_crtc_needs_modeset(state
);
531 * Returns whether any output on the specified pipe is of the specified type
533 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
535 struct drm_device
*dev
= crtc
->base
.dev
;
536 struct intel_encoder
*encoder
;
538 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
539 if (encoder
->type
== type
)
546 * Returns whether any output on the specified pipe will have the specified
547 * type after a staged modeset is complete, i.e., the same as
548 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
551 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
554 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
555 struct drm_connector
*connector
;
556 struct drm_connector_state
*connector_state
;
557 struct intel_encoder
*encoder
;
558 int i
, num_connectors
= 0;
560 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
561 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
566 encoder
= to_intel_encoder(connector_state
->best_encoder
);
567 if (encoder
->type
== type
)
571 WARN_ON(num_connectors
== 0);
577 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
578 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
579 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
580 * The helpers' return value is the rate of the clock that is fed to the
581 * display engine's pipe which can be the above fast dot clock rate or a
582 * divided-down version of it.
584 /* m1 is reserved as 0 in Pineview, n is a ring counter */
585 static int pnv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
587 clock
->m
= clock
->m2
+ 2;
588 clock
->p
= clock
->p1
* clock
->p2
;
589 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
591 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
592 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
597 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
599 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
602 static int i9xx_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
604 clock
->m
= i9xx_dpll_compute_m(clock
);
605 clock
->p
= clock
->p1
* clock
->p2
;
606 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
608 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
609 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
614 static int vlv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
616 clock
->m
= clock
->m1
* clock
->m2
;
617 clock
->p
= clock
->p1
* clock
->p2
;
618 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
620 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
621 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
623 return clock
->dot
/ 5;
626 int chv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
628 clock
->m
= clock
->m1
* clock
->m2
;
629 clock
->p
= clock
->p1
* clock
->p2
;
630 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
632 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
634 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
636 return clock
->dot
/ 5;
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
645 static bool intel_PLL_is_valid(struct drm_device
*dev
,
646 const intel_limit_t
*limit
,
647 const intel_clock_t
*clock
)
649 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
650 INTELPllInvalid("n out of range\n");
651 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
652 INTELPllInvalid("p1 out of range\n");
653 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
656 INTELPllInvalid("m1 out of range\n");
658 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) &&
659 !IS_CHERRYVIEW(dev
) && !IS_BROXTON(dev
))
660 if (clock
->m1
<= clock
->m2
)
661 INTELPllInvalid("m1 <= m2\n");
663 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) && !IS_BROXTON(dev
)) {
664 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
665 INTELPllInvalid("p out of range\n");
666 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
667 INTELPllInvalid("m out of range\n");
670 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
671 INTELPllInvalid("vco out of range\n");
672 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
673 * connector, etc., rather than just a single range.
675 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
676 INTELPllInvalid("dot out of range\n");
682 i9xx_select_p2_div(const intel_limit_t
*limit
,
683 const struct intel_crtc_state
*crtc_state
,
686 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
688 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
690 * For LVDS just rely on its current settings for dual-channel.
691 * We haven't figured out how to reliably set up different
692 * single/dual channel state, if we even can.
694 if (intel_is_dual_link_lvds(dev
))
695 return limit
->p2
.p2_fast
;
697 return limit
->p2
.p2_slow
;
699 if (target
< limit
->p2
.dot_limit
)
700 return limit
->p2
.p2_slow
;
702 return limit
->p2
.p2_fast
;
707 * Returns a set of divisors for the desired target clock with the given
708 * refclk, or FALSE. The returned values represent the clock equation:
709 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
711 * Target and reference clocks are specified in kHz.
713 * If match_clock is provided, then best_clock P divider must match the P
714 * divider from @match_clock used for LVDS downclocking.
717 i9xx_find_best_dpll(const intel_limit_t
*limit
,
718 struct intel_crtc_state
*crtc_state
,
719 int target
, int refclk
, intel_clock_t
*match_clock
,
720 intel_clock_t
*best_clock
)
722 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
726 memset(best_clock
, 0, sizeof(*best_clock
));
728 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
730 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
732 for (clock
.m2
= limit
->m2
.min
;
733 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
734 if (clock
.m2
>= clock
.m1
)
736 for (clock
.n
= limit
->n
.min
;
737 clock
.n
<= limit
->n
.max
; clock
.n
++) {
738 for (clock
.p1
= limit
->p1
.min
;
739 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
742 i9xx_calc_dpll_params(refclk
, &clock
);
743 if (!intel_PLL_is_valid(dev
, limit
,
747 clock
.p
!= match_clock
->p
)
750 this_err
= abs(clock
.dot
- target
);
751 if (this_err
< err
) {
760 return (err
!= target
);
764 * Returns a set of divisors for the desired target clock with the given
765 * refclk, or FALSE. The returned values represent the clock equation:
766 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
768 * Target and reference clocks are specified in kHz.
770 * If match_clock is provided, then best_clock P divider must match the P
771 * divider from @match_clock used for LVDS downclocking.
774 pnv_find_best_dpll(const intel_limit_t
*limit
,
775 struct intel_crtc_state
*crtc_state
,
776 int target
, int refclk
, intel_clock_t
*match_clock
,
777 intel_clock_t
*best_clock
)
779 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
783 memset(best_clock
, 0, sizeof(*best_clock
));
785 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
787 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
789 for (clock
.m2
= limit
->m2
.min
;
790 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
791 for (clock
.n
= limit
->n
.min
;
792 clock
.n
<= limit
->n
.max
; clock
.n
++) {
793 for (clock
.p1
= limit
->p1
.min
;
794 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
797 pnv_calc_dpll_params(refclk
, &clock
);
798 if (!intel_PLL_is_valid(dev
, limit
,
802 clock
.p
!= match_clock
->p
)
805 this_err
= abs(clock
.dot
- target
);
806 if (this_err
< err
) {
815 return (err
!= target
);
819 * Returns a set of divisors for the desired target clock with the given
820 * refclk, or FALSE. The returned values represent the clock equation:
821 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
823 * Target and reference clocks are specified in kHz.
825 * If match_clock is provided, then best_clock P divider must match the P
826 * divider from @match_clock used for LVDS downclocking.
829 g4x_find_best_dpll(const intel_limit_t
*limit
,
830 struct intel_crtc_state
*crtc_state
,
831 int target
, int refclk
, intel_clock_t
*match_clock
,
832 intel_clock_t
*best_clock
)
834 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
838 /* approximately equals target * 0.00585 */
839 int err_most
= (target
>> 8) + (target
>> 9);
841 memset(best_clock
, 0, sizeof(*best_clock
));
843 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
845 max_n
= limit
->n
.max
;
846 /* based on hardware requirement, prefer smaller n to precision */
847 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
848 /* based on hardware requirement, prefere larger m1,m2 */
849 for (clock
.m1
= limit
->m1
.max
;
850 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
851 for (clock
.m2
= limit
->m2
.max
;
852 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
853 for (clock
.p1
= limit
->p1
.max
;
854 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
857 i9xx_calc_dpll_params(refclk
, &clock
);
858 if (!intel_PLL_is_valid(dev
, limit
,
862 this_err
= abs(clock
.dot
- target
);
863 if (this_err
< err_most
) {
877 * Check if the calculated PLL configuration is more optimal compared to the
878 * best configuration and error found so far. Return the calculated error.
880 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
881 const intel_clock_t
*calculated_clock
,
882 const intel_clock_t
*best_clock
,
883 unsigned int best_error_ppm
,
884 unsigned int *error_ppm
)
887 * For CHV ignore the error and consider only the P value.
888 * Prefer a bigger P value based on HW requirements.
890 if (IS_CHERRYVIEW(dev
)) {
893 return calculated_clock
->p
> best_clock
->p
;
896 if (WARN_ON_ONCE(!target_freq
))
899 *error_ppm
= div_u64(1000000ULL *
900 abs(target_freq
- calculated_clock
->dot
),
903 * Prefer a better P value over a better (smaller) error if the error
904 * is small. Ensure this preference for future configurations too by
905 * setting the error to 0.
907 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
913 return *error_ppm
+ 10 < best_error_ppm
;
917 * Returns a set of divisors for the desired target clock with the given
918 * refclk, or FALSE. The returned values represent the clock equation:
919 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
922 vlv_find_best_dpll(const intel_limit_t
*limit
,
923 struct intel_crtc_state
*crtc_state
,
924 int target
, int refclk
, intel_clock_t
*match_clock
,
925 intel_clock_t
*best_clock
)
927 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
928 struct drm_device
*dev
= crtc
->base
.dev
;
930 unsigned int bestppm
= 1000000;
931 /* min update 19.2 MHz */
932 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
935 target
*= 5; /* fast clock */
937 memset(best_clock
, 0, sizeof(*best_clock
));
939 /* based on hardware requirement, prefer smaller n to precision */
940 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
941 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
942 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
943 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
944 clock
.p
= clock
.p1
* clock
.p2
;
945 /* based on hardware requirement, prefer bigger m1,m2 values */
946 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
949 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
952 vlv_calc_dpll_params(refclk
, &clock
);
954 if (!intel_PLL_is_valid(dev
, limit
,
958 if (!vlv_PLL_is_optimal(dev
, target
,
976 * Returns a set of divisors for the desired target clock with the given
977 * refclk, or FALSE. The returned values represent the clock equation:
978 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
981 chv_find_best_dpll(const intel_limit_t
*limit
,
982 struct intel_crtc_state
*crtc_state
,
983 int target
, int refclk
, intel_clock_t
*match_clock
,
984 intel_clock_t
*best_clock
)
986 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
987 struct drm_device
*dev
= crtc
->base
.dev
;
988 unsigned int best_error_ppm
;
993 memset(best_clock
, 0, sizeof(*best_clock
));
994 best_error_ppm
= 1000000;
997 * Based on hardware doc, the n always set to 1, and m1 always
998 * set to 2. If requires to support 200Mhz refclk, we need to
999 * revisit this because n may not 1 anymore.
1001 clock
.n
= 1, clock
.m1
= 2;
1002 target
*= 5; /* fast clock */
1004 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
1005 for (clock
.p2
= limit
->p2
.p2_fast
;
1006 clock
.p2
>= limit
->p2
.p2_slow
;
1007 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
1008 unsigned int error_ppm
;
1010 clock
.p
= clock
.p1
* clock
.p2
;
1012 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
1013 clock
.n
) << 22, refclk
* clock
.m1
);
1015 if (m2
> INT_MAX
/clock
.m1
)
1020 chv_calc_dpll_params(refclk
, &clock
);
1022 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
1025 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
1026 best_error_ppm
, &error_ppm
))
1029 *best_clock
= clock
;
1030 best_error_ppm
= error_ppm
;
1038 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1039 intel_clock_t
*best_clock
)
1041 int refclk
= 100000;
1042 const intel_limit_t
*limit
= &intel_limits_bxt
;
1044 return chv_find_best_dpll(limit
, crtc_state
,
1045 target_clock
, refclk
, NULL
, best_clock
);
1048 bool intel_crtc_active(struct drm_crtc
*crtc
)
1050 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1052 /* Be paranoid as we can arrive here with only partial
1053 * state retrieved from the hardware during setup.
1055 * We can ditch the adjusted_mode.crtc_clock check as soon
1056 * as Haswell has gained clock readout/fastboot support.
1058 * We can ditch the crtc->primary->fb check as soon as we can
1059 * properly reconstruct framebuffers.
1061 * FIXME: The intel_crtc->active here should be switched to
1062 * crtc->state->active once we have proper CRTC states wired up
1065 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
1066 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1069 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1072 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1073 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1075 return intel_crtc
->config
->cpu_transcoder
;
1078 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1081 i915_reg_t reg
= PIPEDSL(pipe
);
1086 line_mask
= DSL_LINEMASK_GEN2
;
1088 line_mask
= DSL_LINEMASK_GEN3
;
1090 line1
= I915_READ(reg
) & line_mask
;
1092 line2
= I915_READ(reg
) & line_mask
;
1094 return line1
== line2
;
1098 * intel_wait_for_pipe_off - wait for pipe to turn off
1099 * @crtc: crtc whose pipe to wait for
1101 * After disabling a pipe, we can't wait for vblank in the usual way,
1102 * spinning on the vblank interrupt status bit, since we won't actually
1103 * see an interrupt when the pipe is disabled.
1105 * On Gen4 and above:
1106 * wait for the pipe register state bit to turn off
1109 * wait for the display line value to settle (it usually
1110 * ends up stopping at the start of the next frame).
1113 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1115 struct drm_device
*dev
= crtc
->base
.dev
;
1116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1117 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1118 enum pipe pipe
= crtc
->pipe
;
1120 if (INTEL_INFO(dev
)->gen
>= 4) {
1121 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
1123 /* Wait for the Pipe State to go off */
1124 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1126 WARN(1, "pipe_off wait timed out\n");
1128 /* Wait for the display line to settle */
1129 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1130 WARN(1, "pipe_off wait timed out\n");
1134 /* Only for pre-ILK configs */
1135 void assert_pll(struct drm_i915_private
*dev_priv
,
1136 enum pipe pipe
, bool state
)
1141 val
= I915_READ(DPLL(pipe
));
1142 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1143 I915_STATE_WARN(cur_state
!= state
,
1144 "PLL state assertion failure (expected %s, current %s)\n",
1145 onoff(state
), onoff(cur_state
));
1148 /* XXX: the dsi pll is shared between MIPI DSI ports */
1149 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1154 mutex_lock(&dev_priv
->sb_lock
);
1155 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1156 mutex_unlock(&dev_priv
->sb_lock
);
1158 cur_state
= val
& DSI_PLL_VCO_EN
;
1159 I915_STATE_WARN(cur_state
!= state
,
1160 "DSI PLL state assertion failure (expected %s, current %s)\n",
1161 onoff(state
), onoff(cur_state
));
1164 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1165 enum pipe pipe
, bool state
)
1168 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1171 if (HAS_DDI(dev_priv
)) {
1172 /* DDI does not have a specific FDI_TX register */
1173 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1174 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1176 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1177 cur_state
= !!(val
& FDI_TX_ENABLE
);
1179 I915_STATE_WARN(cur_state
!= state
,
1180 "FDI TX state assertion failure (expected %s, current %s)\n",
1181 onoff(state
), onoff(cur_state
));
1183 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1184 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1186 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1187 enum pipe pipe
, bool state
)
1192 val
= I915_READ(FDI_RX_CTL(pipe
));
1193 cur_state
= !!(val
& FDI_RX_ENABLE
);
1194 I915_STATE_WARN(cur_state
!= state
,
1195 "FDI RX state assertion failure (expected %s, current %s)\n",
1196 onoff(state
), onoff(cur_state
));
1198 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1199 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1201 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1206 /* ILK FDI PLL is always enabled */
1207 if (INTEL_INFO(dev_priv
)->gen
== 5)
1210 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1211 if (HAS_DDI(dev_priv
))
1214 val
= I915_READ(FDI_TX_CTL(pipe
));
1215 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1218 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1219 enum pipe pipe
, bool state
)
1224 val
= I915_READ(FDI_RX_CTL(pipe
));
1225 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1226 I915_STATE_WARN(cur_state
!= state
,
1227 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1228 onoff(state
), onoff(cur_state
));
1231 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1234 struct drm_device
*dev
= dev_priv
->dev
;
1237 enum pipe panel_pipe
= PIPE_A
;
1240 if (WARN_ON(HAS_DDI(dev
)))
1243 if (HAS_PCH_SPLIT(dev
)) {
1246 pp_reg
= PCH_PP_CONTROL
;
1247 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1249 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1250 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1251 panel_pipe
= PIPE_B
;
1252 /* XXX: else fix for eDP */
1253 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1254 /* presumably write lock depends on pipe, not port select */
1255 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1258 pp_reg
= PP_CONTROL
;
1259 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1260 panel_pipe
= PIPE_B
;
1263 val
= I915_READ(pp_reg
);
1264 if (!(val
& PANEL_POWER_ON
) ||
1265 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1268 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1269 "panel assertion failure, pipe %c regs locked\n",
1273 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1274 enum pipe pipe
, bool state
)
1276 struct drm_device
*dev
= dev_priv
->dev
;
1279 if (IS_845G(dev
) || IS_I865G(dev
))
1280 cur_state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
1282 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1284 I915_STATE_WARN(cur_state
!= state
,
1285 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1286 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1288 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1289 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1291 void assert_pipe(struct drm_i915_private
*dev_priv
,
1292 enum pipe pipe
, bool state
)
1295 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1297 enum intel_display_power_domain power_domain
;
1299 /* if we need the pipe quirk it must be always on */
1300 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1301 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1304 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
1305 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
1306 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1307 cur_state
= !!(val
& PIPECONF_ENABLE
);
1309 intel_display_power_put(dev_priv
, power_domain
);
1314 I915_STATE_WARN(cur_state
!= state
,
1315 "pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1319 static void assert_plane(struct drm_i915_private
*dev_priv
,
1320 enum plane plane
, bool state
)
1325 val
= I915_READ(DSPCNTR(plane
));
1326 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1327 I915_STATE_WARN(cur_state
!= state
,
1328 "plane %c assertion failure (expected %s, current %s)\n",
1329 plane_name(plane
), onoff(state
), onoff(cur_state
));
1332 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1333 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1335 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1338 struct drm_device
*dev
= dev_priv
->dev
;
1341 /* Primary planes are fixed to pipes on gen4+ */
1342 if (INTEL_INFO(dev
)->gen
>= 4) {
1343 u32 val
= I915_READ(DSPCNTR(pipe
));
1344 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1345 "plane %c assertion failure, should be disabled but not\n",
1350 /* Need to check both planes against the pipe */
1351 for_each_pipe(dev_priv
, i
) {
1352 u32 val
= I915_READ(DSPCNTR(i
));
1353 enum pipe cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1354 DISPPLANE_SEL_PIPE_SHIFT
;
1355 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1356 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1357 plane_name(i
), pipe_name(pipe
));
1361 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1364 struct drm_device
*dev
= dev_priv
->dev
;
1367 if (INTEL_INFO(dev
)->gen
>= 9) {
1368 for_each_sprite(dev_priv
, pipe
, sprite
) {
1369 u32 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1370 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1371 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1372 sprite
, pipe_name(pipe
));
1374 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1375 for_each_sprite(dev_priv
, pipe
, sprite
) {
1376 u32 val
= I915_READ(SPCNTR(pipe
, sprite
));
1377 I915_STATE_WARN(val
& SP_ENABLE
,
1378 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1379 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1381 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1382 u32 val
= I915_READ(SPRCTL(pipe
));
1383 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1384 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1385 plane_name(pipe
), pipe_name(pipe
));
1386 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1387 u32 val
= I915_READ(DVSCNTR(pipe
));
1388 I915_STATE_WARN(val
& DVS_ENABLE
,
1389 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1390 plane_name(pipe
), pipe_name(pipe
));
1394 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1396 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1397 drm_crtc_vblank_put(crtc
);
1400 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1406 val
= I915_READ(PCH_TRANSCONF(pipe
));
1407 enabled
= !!(val
& TRANS_ENABLE
);
1408 I915_STATE_WARN(enabled
,
1409 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1413 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1414 enum pipe pipe
, u32 port_sel
, u32 val
)
1416 if ((val
& DP_PORT_EN
) == 0)
1419 if (HAS_PCH_CPT(dev_priv
)) {
1420 u32 trans_dp_ctl
= I915_READ(TRANS_DP_CTL(pipe
));
1421 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1423 } else if (IS_CHERRYVIEW(dev_priv
)) {
1424 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1427 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1433 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1434 enum pipe pipe
, u32 val
)
1436 if ((val
& SDVO_ENABLE
) == 0)
1439 if (HAS_PCH_CPT(dev_priv
)) {
1440 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1442 } else if (IS_CHERRYVIEW(dev_priv
)) {
1443 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1446 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1452 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1453 enum pipe pipe
, u32 val
)
1455 if ((val
& LVDS_PORT_EN
) == 0)
1458 if (HAS_PCH_CPT(dev_priv
)) {
1459 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1462 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1468 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1469 enum pipe pipe
, u32 val
)
1471 if ((val
& ADPA_DAC_ENABLE
) == 0)
1473 if (HAS_PCH_CPT(dev_priv
)) {
1474 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1477 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1483 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1484 enum pipe pipe
, i915_reg_t reg
,
1487 u32 val
= I915_READ(reg
);
1488 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1489 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1490 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1492 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& DP_PORT_EN
) == 0
1493 && (val
& DP_PIPEB_SELECT
),
1494 "IBX PCH dp port still using transcoder B\n");
1497 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1498 enum pipe pipe
, i915_reg_t reg
)
1500 u32 val
= I915_READ(reg
);
1501 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1502 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1503 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1505 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& SDVO_ENABLE
) == 0
1506 && (val
& SDVO_PIPE_B_SELECT
),
1507 "IBX PCH hdmi port still using transcoder B\n");
1510 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1515 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1516 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1517 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1519 val
= I915_READ(PCH_ADPA
);
1520 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1521 "PCH VGA enabled on transcoder %c, should be disabled\n",
1524 val
= I915_READ(PCH_LVDS
);
1525 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1526 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1529 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1530 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1531 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1534 static void _vlv_enable_pll(struct intel_crtc
*crtc
,
1535 const struct intel_crtc_state
*pipe_config
)
1537 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1538 enum pipe pipe
= crtc
->pipe
;
1540 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1541 POSTING_READ(DPLL(pipe
));
1544 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1545 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
1548 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1549 const struct intel_crtc_state
*pipe_config
)
1551 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1552 enum pipe pipe
= crtc
->pipe
;
1554 assert_pipe_disabled(dev_priv
, pipe
);
1556 /* PLL is protected by panel, make sure we can write it */
1557 assert_panel_unlocked(dev_priv
, pipe
);
1559 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1560 _vlv_enable_pll(crtc
, pipe_config
);
1562 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1563 POSTING_READ(DPLL_MD(pipe
));
1567 static void _chv_enable_pll(struct intel_crtc
*crtc
,
1568 const struct intel_crtc_state
*pipe_config
)
1570 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1571 enum pipe pipe
= crtc
->pipe
;
1572 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1575 mutex_lock(&dev_priv
->sb_lock
);
1577 /* Enable back the 10bit clock to display controller */
1578 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1579 tmp
|= DPIO_DCLKP_EN
;
1580 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1582 mutex_unlock(&dev_priv
->sb_lock
);
1585 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1590 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1592 /* Check PLL is locked */
1593 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1594 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1597 static void chv_enable_pll(struct intel_crtc
*crtc
,
1598 const struct intel_crtc_state
*pipe_config
)
1600 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1601 enum pipe pipe
= crtc
->pipe
;
1603 assert_pipe_disabled(dev_priv
, pipe
);
1605 /* PLL is protected by panel, make sure we can write it */
1606 assert_panel_unlocked(dev_priv
, pipe
);
1608 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1609 _chv_enable_pll(crtc
, pipe_config
);
1611 if (pipe
!= PIPE_A
) {
1613 * WaPixelRepeatModeFixForC0:chv
1615 * DPLLCMD is AWOL. Use chicken bits to propagate
1616 * the value from DPLLBMD to either pipe B or C.
1618 I915_WRITE(CBR4_VLV
, pipe
== PIPE_B
? CBR_DPLLBMD_PIPE_B
: CBR_DPLLBMD_PIPE_C
);
1619 I915_WRITE(DPLL_MD(PIPE_B
), pipe_config
->dpll_hw_state
.dpll_md
);
1620 I915_WRITE(CBR4_VLV
, 0);
1621 dev_priv
->chv_dpll_md
[pipe
] = pipe_config
->dpll_hw_state
.dpll_md
;
1624 * DPLLB VGA mode also seems to cause problems.
1625 * We should always have it disabled.
1627 WARN_ON((I915_READ(DPLL(PIPE_B
)) & DPLL_VGA_MODE_DIS
) == 0);
1629 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1630 POSTING_READ(DPLL_MD(pipe
));
1634 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1636 struct intel_crtc
*crtc
;
1639 for_each_intel_crtc(dev
, crtc
)
1640 count
+= crtc
->base
.state
->active
&&
1641 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1646 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1648 struct drm_device
*dev
= crtc
->base
.dev
;
1649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1650 i915_reg_t reg
= DPLL(crtc
->pipe
);
1651 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1653 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1655 /* PLL is protected by panel, make sure we can write it */
1656 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1657 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1659 /* Enable DVO 2x clock on both PLLs if necessary */
1660 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1662 * It appears to be important that we don't enable this
1663 * for the current pipe before otherwise configuring the
1664 * PLL. No idea how this should be handled if multiple
1665 * DVO outputs are enabled simultaneosly.
1667 dpll
|= DPLL_DVO_2X_MODE
;
1668 I915_WRITE(DPLL(!crtc
->pipe
),
1669 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1673 * Apparently we need to have VGA mode enabled prior to changing
1674 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1675 * dividers, even though the register value does change.
1679 I915_WRITE(reg
, dpll
);
1681 /* Wait for the clocks to stabilize. */
1685 if (INTEL_INFO(dev
)->gen
>= 4) {
1686 I915_WRITE(DPLL_MD(crtc
->pipe
),
1687 crtc
->config
->dpll_hw_state
.dpll_md
);
1689 /* The pixel multiplier can only be updated once the
1690 * DPLL is enabled and the clocks are stable.
1692 * So write it again.
1694 I915_WRITE(reg
, dpll
);
1697 /* We do this three times for luck */
1698 I915_WRITE(reg
, dpll
);
1700 udelay(150); /* wait for warmup */
1701 I915_WRITE(reg
, dpll
);
1703 udelay(150); /* wait for warmup */
1704 I915_WRITE(reg
, dpll
);
1706 udelay(150); /* wait for warmup */
1710 * i9xx_disable_pll - disable a PLL
1711 * @dev_priv: i915 private structure
1712 * @pipe: pipe PLL to disable
1714 * Disable the PLL for @pipe, making sure the pipe is off first.
1716 * Note! This is for pre-ILK only.
1718 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1720 struct drm_device
*dev
= crtc
->base
.dev
;
1721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1722 enum pipe pipe
= crtc
->pipe
;
1724 /* Disable DVO 2x clock on both PLLs if necessary */
1726 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1727 !intel_num_dvo_pipes(dev
)) {
1728 I915_WRITE(DPLL(PIPE_B
),
1729 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1730 I915_WRITE(DPLL(PIPE_A
),
1731 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1734 /* Don't disable pipe or pipe PLLs if needed */
1735 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1736 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1739 /* Make sure the pipe isn't still relying on us */
1740 assert_pipe_disabled(dev_priv
, pipe
);
1742 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1743 POSTING_READ(DPLL(pipe
));
1746 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1750 /* Make sure the pipe isn't still relying on us */
1751 assert_pipe_disabled(dev_priv
, pipe
);
1753 val
= DPLL_INTEGRATED_REF_CLK_VLV
|
1754 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1756 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1758 I915_WRITE(DPLL(pipe
), val
);
1759 POSTING_READ(DPLL(pipe
));
1762 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1764 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1767 /* Make sure the pipe isn't still relying on us */
1768 assert_pipe_disabled(dev_priv
, pipe
);
1770 val
= DPLL_SSC_REF_CLK_CHV
|
1771 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1773 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1775 I915_WRITE(DPLL(pipe
), val
);
1776 POSTING_READ(DPLL(pipe
));
1778 mutex_lock(&dev_priv
->sb_lock
);
1780 /* Disable 10bit clock to display controller */
1781 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1782 val
&= ~DPIO_DCLKP_EN
;
1783 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1785 mutex_unlock(&dev_priv
->sb_lock
);
1788 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1789 struct intel_digital_port
*dport
,
1790 unsigned int expected_mask
)
1793 i915_reg_t dpll_reg
;
1795 switch (dport
->port
) {
1797 port_mask
= DPLL_PORTB_READY_MASK
;
1801 port_mask
= DPLL_PORTC_READY_MASK
;
1803 expected_mask
<<= 4;
1806 port_mask
= DPLL_PORTD_READY_MASK
;
1807 dpll_reg
= DPIO_PHY_STATUS
;
1813 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == expected_mask
, 1000))
1814 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1815 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1818 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1821 struct drm_device
*dev
= dev_priv
->dev
;
1822 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1823 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1825 uint32_t val
, pipeconf_val
;
1827 /* Make sure PCH DPLL is enabled */
1828 assert_shared_dpll_enabled(dev_priv
, intel_crtc
->config
->shared_dpll
);
1830 /* FDI must be feeding us bits for PCH ports */
1831 assert_fdi_tx_enabled(dev_priv
, pipe
);
1832 assert_fdi_rx_enabled(dev_priv
, pipe
);
1834 if (HAS_PCH_CPT(dev
)) {
1835 /* Workaround: Set the timing override bit before enabling the
1836 * pch transcoder. */
1837 reg
= TRANS_CHICKEN2(pipe
);
1838 val
= I915_READ(reg
);
1839 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1840 I915_WRITE(reg
, val
);
1843 reg
= PCH_TRANSCONF(pipe
);
1844 val
= I915_READ(reg
);
1845 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1847 if (HAS_PCH_IBX(dev_priv
)) {
1849 * Make the BPC in transcoder be consistent with
1850 * that in pipeconf reg. For HDMI we must use 8bpc
1851 * here for both 8bpc and 12bpc.
1853 val
&= ~PIPECONF_BPC_MASK
;
1854 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_HDMI
))
1855 val
|= PIPECONF_8BPC
;
1857 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1860 val
&= ~TRANS_INTERLACE_MASK
;
1861 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1862 if (HAS_PCH_IBX(dev_priv
) &&
1863 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1864 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1866 val
|= TRANS_INTERLACED
;
1868 val
|= TRANS_PROGRESSIVE
;
1870 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1871 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1872 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1875 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1876 enum transcoder cpu_transcoder
)
1878 u32 val
, pipeconf_val
;
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1882 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1884 /* Workaround: set timing override bit. */
1885 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1886 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1887 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1890 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1892 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1893 PIPECONF_INTERLACED_ILK
)
1894 val
|= TRANS_INTERLACED
;
1896 val
|= TRANS_PROGRESSIVE
;
1898 I915_WRITE(LPT_TRANSCONF
, val
);
1899 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1900 DRM_ERROR("Failed to enable PCH transcoder\n");
1903 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1906 struct drm_device
*dev
= dev_priv
->dev
;
1910 /* FDI relies on the transcoder */
1911 assert_fdi_tx_disabled(dev_priv
, pipe
);
1912 assert_fdi_rx_disabled(dev_priv
, pipe
);
1914 /* Ports must be off as well */
1915 assert_pch_ports_disabled(dev_priv
, pipe
);
1917 reg
= PCH_TRANSCONF(pipe
);
1918 val
= I915_READ(reg
);
1919 val
&= ~TRANS_ENABLE
;
1920 I915_WRITE(reg
, val
);
1921 /* wait for PCH transcoder off, transcoder state */
1922 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1923 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1925 if (HAS_PCH_CPT(dev
)) {
1926 /* Workaround: Clear the timing override chicken bit again. */
1927 reg
= TRANS_CHICKEN2(pipe
);
1928 val
= I915_READ(reg
);
1929 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1930 I915_WRITE(reg
, val
);
1934 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1938 val
= I915_READ(LPT_TRANSCONF
);
1939 val
&= ~TRANS_ENABLE
;
1940 I915_WRITE(LPT_TRANSCONF
, val
);
1941 /* wait for PCH transcoder off, transcoder state */
1942 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1943 DRM_ERROR("Failed to disable PCH transcoder\n");
1945 /* Workaround: clear timing override bit. */
1946 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1947 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1948 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1952 * intel_enable_pipe - enable a pipe, asserting requirements
1953 * @crtc: crtc responsible for the pipe
1955 * Enable @crtc's pipe, making sure that various hardware specific requirements
1956 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1958 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1960 struct drm_device
*dev
= crtc
->base
.dev
;
1961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1962 enum pipe pipe
= crtc
->pipe
;
1963 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1964 enum pipe pch_transcoder
;
1968 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
1970 assert_planes_disabled(dev_priv
, pipe
);
1971 assert_cursor_disabled(dev_priv
, pipe
);
1972 assert_sprites_disabled(dev_priv
, pipe
);
1974 if (HAS_PCH_LPT(dev_priv
))
1975 pch_transcoder
= TRANSCODER_A
;
1977 pch_transcoder
= pipe
;
1980 * A pipe without a PLL won't actually be able to drive bits from
1981 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1984 if (HAS_GMCH_DISPLAY(dev_priv
))
1985 if (crtc
->config
->has_dsi_encoder
)
1986 assert_dsi_pll_enabled(dev_priv
);
1988 assert_pll_enabled(dev_priv
, pipe
);
1990 if (crtc
->config
->has_pch_encoder
) {
1991 /* if driving the PCH, we need FDI enabled */
1992 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1993 assert_fdi_tx_pll_enabled(dev_priv
,
1994 (enum pipe
) cpu_transcoder
);
1996 /* FIXME: assert CPU port conditions for SNB+ */
1999 reg
= PIPECONF(cpu_transcoder
);
2000 val
= I915_READ(reg
);
2001 if (val
& PIPECONF_ENABLE
) {
2002 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2003 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2007 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2011 * Until the pipe starts DSL will read as 0, which would cause
2012 * an apparent vblank timestamp jump, which messes up also the
2013 * frame count when it's derived from the timestamps. So let's
2014 * wait for the pipe to start properly before we call
2015 * drm_crtc_vblank_on()
2017 if (dev
->max_vblank_count
== 0 &&
2018 wait_for(intel_get_crtc_scanline(crtc
) != crtc
->scanline_offset
, 50))
2019 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe
));
2023 * intel_disable_pipe - disable a pipe, asserting requirements
2024 * @crtc: crtc whose pipes is to be disabled
2026 * Disable the pipe of @crtc, making sure that various hardware
2027 * specific requirements are met, if applicable, e.g. plane
2028 * disabled, panel fitter off, etc.
2030 * Will wait until the pipe has shut down before returning.
2032 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2034 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2035 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2036 enum pipe pipe
= crtc
->pipe
;
2040 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
2043 * Make sure planes won't keep trying to pump pixels to us,
2044 * or we might hang the display.
2046 assert_planes_disabled(dev_priv
, pipe
);
2047 assert_cursor_disabled(dev_priv
, pipe
);
2048 assert_sprites_disabled(dev_priv
, pipe
);
2050 reg
= PIPECONF(cpu_transcoder
);
2051 val
= I915_READ(reg
);
2052 if ((val
& PIPECONF_ENABLE
) == 0)
2056 * Double wide has implications for planes
2057 * so best keep it disabled when not needed.
2059 if (crtc
->config
->double_wide
)
2060 val
&= ~PIPECONF_DOUBLE_WIDE
;
2062 /* Don't disable pipe or pipe PLLs if needed */
2063 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2064 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2065 val
&= ~PIPECONF_ENABLE
;
2067 I915_WRITE(reg
, val
);
2068 if ((val
& PIPECONF_ENABLE
) == 0)
2069 intel_wait_for_pipe_off(crtc
);
2072 static bool need_vtd_wa(struct drm_device
*dev
)
2074 #ifdef CONFIG_INTEL_IOMMU
2075 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2081 static unsigned int intel_tile_size(const struct drm_i915_private
*dev_priv
)
2083 return IS_GEN2(dev_priv
) ? 2048 : 4096;
2086 static unsigned int intel_tile_width_bytes(const struct drm_i915_private
*dev_priv
,
2087 uint64_t fb_modifier
, unsigned int cpp
)
2089 switch (fb_modifier
) {
2090 case DRM_FORMAT_MOD_NONE
:
2092 case I915_FORMAT_MOD_X_TILED
:
2093 if (IS_GEN2(dev_priv
))
2097 case I915_FORMAT_MOD_Y_TILED
:
2098 if (IS_GEN2(dev_priv
) || HAS_128_BYTE_Y_TILING(dev_priv
))
2102 case I915_FORMAT_MOD_Yf_TILED
:
2118 MISSING_CASE(fb_modifier
);
2123 unsigned int intel_tile_height(const struct drm_i915_private
*dev_priv
,
2124 uint64_t fb_modifier
, unsigned int cpp
)
2126 if (fb_modifier
== DRM_FORMAT_MOD_NONE
)
2129 return intel_tile_size(dev_priv
) /
2130 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2133 /* Return the tile dimensions in pixel units */
2134 static void intel_tile_dims(const struct drm_i915_private
*dev_priv
,
2135 unsigned int *tile_width
,
2136 unsigned int *tile_height
,
2137 uint64_t fb_modifier
,
2140 unsigned int tile_width_bytes
=
2141 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2143 *tile_width
= tile_width_bytes
/ cpp
;
2144 *tile_height
= intel_tile_size(dev_priv
) / tile_width_bytes
;
2148 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2149 uint32_t pixel_format
, uint64_t fb_modifier
)
2151 unsigned int cpp
= drm_format_plane_cpp(pixel_format
, 0);
2152 unsigned int tile_height
= intel_tile_height(to_i915(dev
), fb_modifier
, cpp
);
2154 return ALIGN(height
, tile_height
);
2157 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
2159 unsigned int size
= 0;
2162 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
2163 size
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2169 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
,
2170 const struct drm_framebuffer
*fb
,
2171 unsigned int rotation
)
2173 if (intel_rotation_90_or_270(rotation
)) {
2174 *view
= i915_ggtt_view_rotated
;
2175 view
->params
.rotated
= to_intel_framebuffer(fb
)->rot_info
;
2177 *view
= i915_ggtt_view_normal
;
2182 intel_fill_fb_info(struct drm_i915_private
*dev_priv
,
2183 struct drm_framebuffer
*fb
)
2185 struct intel_rotation_info
*info
= &to_intel_framebuffer(fb
)->rot_info
;
2186 unsigned int tile_size
, tile_width
, tile_height
, cpp
;
2188 tile_size
= intel_tile_size(dev_priv
);
2190 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2191 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2192 fb
->modifier
[0], cpp
);
2194 info
->plane
[0].width
= DIV_ROUND_UP(fb
->pitches
[0], tile_width
* cpp
);
2195 info
->plane
[0].height
= DIV_ROUND_UP(fb
->height
, tile_height
);
2197 if (info
->pixel_format
== DRM_FORMAT_NV12
) {
2198 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 1);
2199 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2200 fb
->modifier
[1], cpp
);
2202 info
->uv_offset
= fb
->offsets
[1];
2203 info
->plane
[1].width
= DIV_ROUND_UP(fb
->pitches
[1], tile_width
* cpp
);
2204 info
->plane
[1].height
= DIV_ROUND_UP(fb
->height
/ 2, tile_height
);
2208 static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv
)
2210 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2212 else if (IS_BROADWATER(dev_priv
) || IS_CRESTLINE(dev_priv
) ||
2213 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2215 else if (INTEL_INFO(dev_priv
)->gen
>= 4)
2221 static unsigned int intel_surf_alignment(const struct drm_i915_private
*dev_priv
,
2222 uint64_t fb_modifier
)
2224 switch (fb_modifier
) {
2225 case DRM_FORMAT_MOD_NONE
:
2226 return intel_linear_alignment(dev_priv
);
2227 case I915_FORMAT_MOD_X_TILED
:
2228 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2231 case I915_FORMAT_MOD_Y_TILED
:
2232 case I915_FORMAT_MOD_Yf_TILED
:
2233 return 1 * 1024 * 1024;
2235 MISSING_CASE(fb_modifier
);
2241 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
2242 unsigned int rotation
)
2244 struct drm_device
*dev
= fb
->dev
;
2245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2246 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2247 struct i915_ggtt_view view
;
2251 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2253 alignment
= intel_surf_alignment(dev_priv
, fb
->modifier
[0]);
2255 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2257 /* Note that the w/a also requires 64 PTE of padding following the
2258 * bo. We currently fill all unused PTE with the shadow page and so
2259 * we should always have valid PTE following the scanout preventing
2262 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2263 alignment
= 256 * 1024;
2266 * Global gtt pte registers are special registers which actually forward
2267 * writes to a chunk of system memory. Which means that there is no risk
2268 * that the register values disappear as soon as we call
2269 * intel_runtime_pm_put(), so it is correct to wrap only the
2270 * pin/unpin/fence and not more.
2272 intel_runtime_pm_get(dev_priv
);
2274 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
,
2279 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2280 * fence, whereas 965+ only requires a fence if using
2281 * framebuffer compression. For simplicity, we always install
2282 * a fence as the cost is not that onerous.
2284 if (view
.type
== I915_GGTT_VIEW_NORMAL
) {
2285 ret
= i915_gem_object_get_fence(obj
);
2286 if (ret
== -EDEADLK
) {
2288 * -EDEADLK means there are no free fences
2291 * This is propagated to atomic, but it uses
2292 * -EDEADLK to force a locking recovery, so
2293 * change the returned error to -EBUSY.
2300 i915_gem_object_pin_fence(obj
);
2303 intel_runtime_pm_put(dev_priv
);
2307 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2309 intel_runtime_pm_put(dev_priv
);
2313 void intel_unpin_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
)
2315 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2316 struct i915_ggtt_view view
;
2318 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2320 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2322 if (view
.type
== I915_GGTT_VIEW_NORMAL
)
2323 i915_gem_object_unpin_fence(obj
);
2325 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2329 * Adjust the tile offset by moving the difference into
2332 * Input tile dimensions and pitch must already be
2333 * rotated to match x and y, and in pixel units.
2335 static u32
intel_adjust_tile_offset(int *x
, int *y
,
2336 unsigned int tile_width
,
2337 unsigned int tile_height
,
2338 unsigned int tile_size
,
2339 unsigned int pitch_tiles
,
2345 WARN_ON(old_offset
& (tile_size
- 1));
2346 WARN_ON(new_offset
& (tile_size
- 1));
2347 WARN_ON(new_offset
> old_offset
);
2349 tiles
= (old_offset
- new_offset
) / tile_size
;
2351 *y
+= tiles
/ pitch_tiles
* tile_height
;
2352 *x
+= tiles
% pitch_tiles
* tile_width
;
2358 * Computes the linear offset to the base tile and adjusts
2359 * x, y. bytes per pixel is assumed to be a power-of-two.
2361 * In the 90/270 rotated case, x and y are assumed
2362 * to be already rotated to match the rotated GTT view, and
2363 * pitch is the tile_height aligned framebuffer height.
2365 u32
intel_compute_tile_offset(int *x
, int *y
,
2366 const struct drm_framebuffer
*fb
, int plane
,
2368 unsigned int rotation
)
2370 const struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2371 uint64_t fb_modifier
= fb
->modifier
[plane
];
2372 unsigned int cpp
= drm_format_plane_cpp(fb
->pixel_format
, plane
);
2373 u32 offset
, offset_aligned
, alignment
;
2375 alignment
= intel_surf_alignment(dev_priv
, fb_modifier
);
2379 if (fb_modifier
!= DRM_FORMAT_MOD_NONE
) {
2380 unsigned int tile_size
, tile_width
, tile_height
;
2381 unsigned int tile_rows
, tiles
, pitch_tiles
;
2383 tile_size
= intel_tile_size(dev_priv
);
2384 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2387 if (intel_rotation_90_or_270(rotation
)) {
2388 pitch_tiles
= pitch
/ tile_height
;
2389 swap(tile_width
, tile_height
);
2391 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2394 tile_rows
= *y
/ tile_height
;
2397 tiles
= *x
/ tile_width
;
2400 offset
= (tile_rows
* pitch_tiles
+ tiles
) * tile_size
;
2401 offset_aligned
= offset
& ~alignment
;
2403 intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2404 tile_size
, pitch_tiles
,
2405 offset
, offset_aligned
);
2407 offset
= *y
* pitch
+ *x
* cpp
;
2408 offset_aligned
= offset
& ~alignment
;
2410 *y
= (offset
& alignment
) / pitch
;
2411 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2414 return offset_aligned
;
2417 static int i9xx_format_to_fourcc(int format
)
2420 case DISPPLANE_8BPP
:
2421 return DRM_FORMAT_C8
;
2422 case DISPPLANE_BGRX555
:
2423 return DRM_FORMAT_XRGB1555
;
2424 case DISPPLANE_BGRX565
:
2425 return DRM_FORMAT_RGB565
;
2427 case DISPPLANE_BGRX888
:
2428 return DRM_FORMAT_XRGB8888
;
2429 case DISPPLANE_RGBX888
:
2430 return DRM_FORMAT_XBGR8888
;
2431 case DISPPLANE_BGRX101010
:
2432 return DRM_FORMAT_XRGB2101010
;
2433 case DISPPLANE_RGBX101010
:
2434 return DRM_FORMAT_XBGR2101010
;
2438 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2441 case PLANE_CTL_FORMAT_RGB_565
:
2442 return DRM_FORMAT_RGB565
;
2444 case PLANE_CTL_FORMAT_XRGB_8888
:
2447 return DRM_FORMAT_ABGR8888
;
2449 return DRM_FORMAT_XBGR8888
;
2452 return DRM_FORMAT_ARGB8888
;
2454 return DRM_FORMAT_XRGB8888
;
2456 case PLANE_CTL_FORMAT_XRGB_2101010
:
2458 return DRM_FORMAT_XBGR2101010
;
2460 return DRM_FORMAT_XRGB2101010
;
2465 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2466 struct intel_initial_plane_config
*plane_config
)
2468 struct drm_device
*dev
= crtc
->base
.dev
;
2469 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2470 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2471 struct drm_i915_gem_object
*obj
= NULL
;
2472 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2473 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2474 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2475 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2478 size_aligned
-= base_aligned
;
2480 if (plane_config
->size
== 0)
2483 /* If the FB is too big, just don't use it since fbdev is not very
2484 * important and we should probably use that space with FBC or other
2486 if (size_aligned
* 2 > ggtt
->stolen_usable_size
)
2489 mutex_lock(&dev
->struct_mutex
);
2491 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2496 mutex_unlock(&dev
->struct_mutex
);
2500 obj
->tiling_mode
= plane_config
->tiling
;
2501 if (obj
->tiling_mode
== I915_TILING_X
)
2502 obj
->stride
= fb
->pitches
[0];
2504 mode_cmd
.pixel_format
= fb
->pixel_format
;
2505 mode_cmd
.width
= fb
->width
;
2506 mode_cmd
.height
= fb
->height
;
2507 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2508 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2509 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2511 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2513 DRM_DEBUG_KMS("intel fb init failed\n");
2517 mutex_unlock(&dev
->struct_mutex
);
2519 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2523 drm_gem_object_unreference(&obj
->base
);
2524 mutex_unlock(&dev
->struct_mutex
);
2528 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2530 update_state_fb(struct drm_plane
*plane
)
2532 if (plane
->fb
== plane
->state
->fb
)
2535 if (plane
->state
->fb
)
2536 drm_framebuffer_unreference(plane
->state
->fb
);
2537 plane
->state
->fb
= plane
->fb
;
2538 if (plane
->state
->fb
)
2539 drm_framebuffer_reference(plane
->state
->fb
);
2543 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2544 struct intel_initial_plane_config
*plane_config
)
2546 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2549 struct intel_crtc
*i
;
2550 struct drm_i915_gem_object
*obj
;
2551 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2552 struct drm_plane_state
*plane_state
= primary
->state
;
2553 struct drm_crtc_state
*crtc_state
= intel_crtc
->base
.state
;
2554 struct intel_plane
*intel_plane
= to_intel_plane(primary
);
2555 struct intel_plane_state
*intel_state
=
2556 to_intel_plane_state(plane_state
);
2557 struct drm_framebuffer
*fb
;
2559 if (!plane_config
->fb
)
2562 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2563 fb
= &plane_config
->fb
->base
;
2567 kfree(plane_config
->fb
);
2570 * Failed to alloc the obj, check to see if we should share
2571 * an fb with another CRTC instead
2573 for_each_crtc(dev
, c
) {
2574 i
= to_intel_crtc(c
);
2576 if (c
== &intel_crtc
->base
)
2582 fb
= c
->primary
->fb
;
2586 obj
= intel_fb_obj(fb
);
2587 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2588 drm_framebuffer_reference(fb
);
2594 * We've failed to reconstruct the BIOS FB. Current display state
2595 * indicates that the primary plane is visible, but has a NULL FB,
2596 * which will lead to problems later if we don't fix it up. The
2597 * simplest solution is to just disable the primary plane now and
2598 * pretend the BIOS never had it enabled.
2600 to_intel_plane_state(plane_state
)->visible
= false;
2601 crtc_state
->plane_mask
&= ~(1 << drm_plane_index(primary
));
2602 intel_pre_disable_primary_noatomic(&intel_crtc
->base
);
2603 intel_plane
->disable_plane(primary
, &intel_crtc
->base
);
2608 plane_state
->src_x
= 0;
2609 plane_state
->src_y
= 0;
2610 plane_state
->src_w
= fb
->width
<< 16;
2611 plane_state
->src_h
= fb
->height
<< 16;
2613 plane_state
->crtc_x
= 0;
2614 plane_state
->crtc_y
= 0;
2615 plane_state
->crtc_w
= fb
->width
;
2616 plane_state
->crtc_h
= fb
->height
;
2618 intel_state
->src
.x1
= plane_state
->src_x
;
2619 intel_state
->src
.y1
= plane_state
->src_y
;
2620 intel_state
->src
.x2
= plane_state
->src_x
+ plane_state
->src_w
;
2621 intel_state
->src
.y2
= plane_state
->src_y
+ plane_state
->src_h
;
2622 intel_state
->dst
.x1
= plane_state
->crtc_x
;
2623 intel_state
->dst
.y1
= plane_state
->crtc_y
;
2624 intel_state
->dst
.x2
= plane_state
->crtc_x
+ plane_state
->crtc_w
;
2625 intel_state
->dst
.y2
= plane_state
->crtc_y
+ plane_state
->crtc_h
;
2627 obj
= intel_fb_obj(fb
);
2628 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2629 dev_priv
->preserve_bios_swizzle
= true;
2631 drm_framebuffer_reference(fb
);
2632 primary
->fb
= primary
->state
->fb
= fb
;
2633 primary
->crtc
= primary
->state
->crtc
= &intel_crtc
->base
;
2634 intel_crtc
->base
.state
->plane_mask
|= (1 << drm_plane_index(primary
));
2635 obj
->frontbuffer_bits
|= to_intel_plane(primary
)->frontbuffer_bit
;
2638 static void i9xx_update_primary_plane(struct drm_plane
*primary
,
2639 const struct intel_crtc_state
*crtc_state
,
2640 const struct intel_plane_state
*plane_state
)
2642 struct drm_device
*dev
= primary
->dev
;
2643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2644 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2645 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2646 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2647 int plane
= intel_crtc
->plane
;
2650 i915_reg_t reg
= DSPCNTR(plane
);
2651 unsigned int rotation
= plane_state
->base
.rotation
;
2652 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2653 int x
= plane_state
->src
.x1
>> 16;
2654 int y
= plane_state
->src
.y1
>> 16;
2656 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2658 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2660 if (INTEL_INFO(dev
)->gen
< 4) {
2661 if (intel_crtc
->pipe
== PIPE_B
)
2662 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2664 /* pipesrc and dspsize control the size that is scaled from,
2665 * which should always be the user's requested size.
2667 I915_WRITE(DSPSIZE(plane
),
2668 ((crtc_state
->pipe_src_h
- 1) << 16) |
2669 (crtc_state
->pipe_src_w
- 1));
2670 I915_WRITE(DSPPOS(plane
), 0);
2671 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2672 I915_WRITE(PRIMSIZE(plane
),
2673 ((crtc_state
->pipe_src_h
- 1) << 16) |
2674 (crtc_state
->pipe_src_w
- 1));
2675 I915_WRITE(PRIMPOS(plane
), 0);
2676 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2679 switch (fb
->pixel_format
) {
2681 dspcntr
|= DISPPLANE_8BPP
;
2683 case DRM_FORMAT_XRGB1555
:
2684 dspcntr
|= DISPPLANE_BGRX555
;
2686 case DRM_FORMAT_RGB565
:
2687 dspcntr
|= DISPPLANE_BGRX565
;
2689 case DRM_FORMAT_XRGB8888
:
2690 dspcntr
|= DISPPLANE_BGRX888
;
2692 case DRM_FORMAT_XBGR8888
:
2693 dspcntr
|= DISPPLANE_RGBX888
;
2695 case DRM_FORMAT_XRGB2101010
:
2696 dspcntr
|= DISPPLANE_BGRX101010
;
2698 case DRM_FORMAT_XBGR2101010
:
2699 dspcntr
|= DISPPLANE_RGBX101010
;
2705 if (INTEL_INFO(dev
)->gen
>= 4 &&
2706 obj
->tiling_mode
!= I915_TILING_NONE
)
2707 dspcntr
|= DISPPLANE_TILED
;
2710 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2712 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
2714 if (INTEL_INFO(dev
)->gen
>= 4) {
2715 intel_crtc
->dspaddr_offset
=
2716 intel_compute_tile_offset(&x
, &y
, fb
, 0,
2717 fb
->pitches
[0], rotation
);
2718 linear_offset
-= intel_crtc
->dspaddr_offset
;
2720 intel_crtc
->dspaddr_offset
= linear_offset
;
2723 if (rotation
== BIT(DRM_ROTATE_180
)) {
2724 dspcntr
|= DISPPLANE_ROTATE_180
;
2726 x
+= (crtc_state
->pipe_src_w
- 1);
2727 y
+= (crtc_state
->pipe_src_h
- 1);
2729 /* Finding the last pixel of the last line of the display
2730 data and adding to linear_offset*/
2732 (crtc_state
->pipe_src_h
- 1) * fb
->pitches
[0] +
2733 (crtc_state
->pipe_src_w
- 1) * cpp
;
2736 intel_crtc
->adjusted_x
= x
;
2737 intel_crtc
->adjusted_y
= y
;
2739 I915_WRITE(reg
, dspcntr
);
2741 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2742 if (INTEL_INFO(dev
)->gen
>= 4) {
2743 I915_WRITE(DSPSURF(plane
),
2744 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2745 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2746 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2748 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2752 static void i9xx_disable_primary_plane(struct drm_plane
*primary
,
2753 struct drm_crtc
*crtc
)
2755 struct drm_device
*dev
= crtc
->dev
;
2756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2757 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2758 int plane
= intel_crtc
->plane
;
2760 I915_WRITE(DSPCNTR(plane
), 0);
2761 if (INTEL_INFO(dev_priv
)->gen
>= 4)
2762 I915_WRITE(DSPSURF(plane
), 0);
2764 I915_WRITE(DSPADDR(plane
), 0);
2765 POSTING_READ(DSPCNTR(plane
));
2768 static void ironlake_update_primary_plane(struct drm_plane
*primary
,
2769 const struct intel_crtc_state
*crtc_state
,
2770 const struct intel_plane_state
*plane_state
)
2772 struct drm_device
*dev
= primary
->dev
;
2773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2774 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2775 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2776 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2777 int plane
= intel_crtc
->plane
;
2780 i915_reg_t reg
= DSPCNTR(plane
);
2781 unsigned int rotation
= plane_state
->base
.rotation
;
2782 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2783 int x
= plane_state
->src
.x1
>> 16;
2784 int y
= plane_state
->src
.y1
>> 16;
2786 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2787 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2789 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2790 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2792 switch (fb
->pixel_format
) {
2794 dspcntr
|= DISPPLANE_8BPP
;
2796 case DRM_FORMAT_RGB565
:
2797 dspcntr
|= DISPPLANE_BGRX565
;
2799 case DRM_FORMAT_XRGB8888
:
2800 dspcntr
|= DISPPLANE_BGRX888
;
2802 case DRM_FORMAT_XBGR8888
:
2803 dspcntr
|= DISPPLANE_RGBX888
;
2805 case DRM_FORMAT_XRGB2101010
:
2806 dspcntr
|= DISPPLANE_BGRX101010
;
2808 case DRM_FORMAT_XBGR2101010
:
2809 dspcntr
|= DISPPLANE_RGBX101010
;
2815 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2816 dspcntr
|= DISPPLANE_TILED
;
2818 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2819 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2821 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
2822 intel_crtc
->dspaddr_offset
=
2823 intel_compute_tile_offset(&x
, &y
, fb
, 0,
2824 fb
->pitches
[0], rotation
);
2825 linear_offset
-= intel_crtc
->dspaddr_offset
;
2826 if (rotation
== BIT(DRM_ROTATE_180
)) {
2827 dspcntr
|= DISPPLANE_ROTATE_180
;
2829 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2830 x
+= (crtc_state
->pipe_src_w
- 1);
2831 y
+= (crtc_state
->pipe_src_h
- 1);
2833 /* Finding the last pixel of the last line of the display
2834 data and adding to linear_offset*/
2836 (crtc_state
->pipe_src_h
- 1) * fb
->pitches
[0] +
2837 (crtc_state
->pipe_src_w
- 1) * cpp
;
2841 intel_crtc
->adjusted_x
= x
;
2842 intel_crtc
->adjusted_y
= y
;
2844 I915_WRITE(reg
, dspcntr
);
2846 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2847 I915_WRITE(DSPSURF(plane
),
2848 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2849 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2850 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2852 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2853 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2858 u32
intel_fb_stride_alignment(const struct drm_i915_private
*dev_priv
,
2859 uint64_t fb_modifier
, uint32_t pixel_format
)
2861 if (fb_modifier
== DRM_FORMAT_MOD_NONE
) {
2864 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
2866 return intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2870 u32
intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2871 struct drm_i915_gem_object
*obj
,
2874 struct i915_ggtt_view view
;
2875 struct i915_vma
*vma
;
2878 intel_fill_fb_ggtt_view(&view
, intel_plane
->base
.state
->fb
,
2879 intel_plane
->base
.state
->rotation
);
2881 vma
= i915_gem_obj_to_ggtt_view(obj
, &view
);
2882 if (WARN(!vma
, "ggtt vma for display object not found! (view=%u)\n",
2886 offset
= vma
->node
.start
;
2889 offset
+= vma
->ggtt_view
.params
.rotated
.uv_start_page
*
2893 WARN_ON(upper_32_bits(offset
));
2895 return lower_32_bits(offset
);
2898 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
2900 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2903 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
2904 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
2905 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
2909 * This function detaches (aka. unbinds) unused scalers in hardware
2911 static void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2913 struct intel_crtc_scaler_state
*scaler_state
;
2916 scaler_state
= &intel_crtc
->config
->scaler_state
;
2918 /* loop through and disable scalers that aren't in use */
2919 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2920 if (!scaler_state
->scalers
[i
].in_use
)
2921 skl_detach_scaler(intel_crtc
, i
);
2925 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2927 switch (pixel_format
) {
2929 return PLANE_CTL_FORMAT_INDEXED
;
2930 case DRM_FORMAT_RGB565
:
2931 return PLANE_CTL_FORMAT_RGB_565
;
2932 case DRM_FORMAT_XBGR8888
:
2933 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2934 case DRM_FORMAT_XRGB8888
:
2935 return PLANE_CTL_FORMAT_XRGB_8888
;
2937 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2938 * to be already pre-multiplied. We need to add a knob (or a different
2939 * DRM_FORMAT) for user-space to configure that.
2941 case DRM_FORMAT_ABGR8888
:
2942 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
2943 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2944 case DRM_FORMAT_ARGB8888
:
2945 return PLANE_CTL_FORMAT_XRGB_8888
|
2946 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2947 case DRM_FORMAT_XRGB2101010
:
2948 return PLANE_CTL_FORMAT_XRGB_2101010
;
2949 case DRM_FORMAT_XBGR2101010
:
2950 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
2951 case DRM_FORMAT_YUYV
:
2952 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
2953 case DRM_FORMAT_YVYU
:
2954 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
2955 case DRM_FORMAT_UYVY
:
2956 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
2957 case DRM_FORMAT_VYUY
:
2958 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
2960 MISSING_CASE(pixel_format
);
2966 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
2968 switch (fb_modifier
) {
2969 case DRM_FORMAT_MOD_NONE
:
2971 case I915_FORMAT_MOD_X_TILED
:
2972 return PLANE_CTL_TILED_X
;
2973 case I915_FORMAT_MOD_Y_TILED
:
2974 return PLANE_CTL_TILED_Y
;
2975 case I915_FORMAT_MOD_Yf_TILED
:
2976 return PLANE_CTL_TILED_YF
;
2978 MISSING_CASE(fb_modifier
);
2984 u32
skl_plane_ctl_rotation(unsigned int rotation
)
2987 case BIT(DRM_ROTATE_0
):
2990 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2991 * while i915 HW rotation is clockwise, thats why this swapping.
2993 case BIT(DRM_ROTATE_90
):
2994 return PLANE_CTL_ROTATE_270
;
2995 case BIT(DRM_ROTATE_180
):
2996 return PLANE_CTL_ROTATE_180
;
2997 case BIT(DRM_ROTATE_270
):
2998 return PLANE_CTL_ROTATE_90
;
3000 MISSING_CASE(rotation
);
3006 static void skylake_update_primary_plane(struct drm_plane
*plane
,
3007 const struct intel_crtc_state
*crtc_state
,
3008 const struct intel_plane_state
*plane_state
)
3010 struct drm_device
*dev
= plane
->dev
;
3011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3012 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3013 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3014 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
3015 int pipe
= intel_crtc
->pipe
;
3016 u32 plane_ctl
, stride_div
, stride
;
3017 u32 tile_height
, plane_offset
, plane_size
;
3018 unsigned int rotation
= plane_state
->base
.rotation
;
3019 int x_offset
, y_offset
;
3021 int scaler_id
= plane_state
->scaler_id
;
3022 int src_x
= plane_state
->src
.x1
>> 16;
3023 int src_y
= plane_state
->src
.y1
>> 16;
3024 int src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3025 int src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3026 int dst_x
= plane_state
->dst
.x1
;
3027 int dst_y
= plane_state
->dst
.y1
;
3028 int dst_w
= drm_rect_width(&plane_state
->dst
);
3029 int dst_h
= drm_rect_height(&plane_state
->dst
);
3031 plane_ctl
= PLANE_CTL_ENABLE
|
3032 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3033 PLANE_CTL_PIPE_CSC_ENABLE
;
3035 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3036 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3037 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3038 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3040 stride_div
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
3042 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
, 0);
3044 WARN_ON(drm_rect_width(&plane_state
->src
) == 0);
3046 if (intel_rotation_90_or_270(rotation
)) {
3047 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
3049 /* stride = Surface height in tiles */
3050 tile_height
= intel_tile_height(dev_priv
, fb
->modifier
[0], cpp
);
3051 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3052 x_offset
= stride
* tile_height
- src_y
- src_h
;
3054 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3056 stride
= fb
->pitches
[0] / stride_div
;
3059 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3061 plane_offset
= y_offset
<< 16 | x_offset
;
3063 intel_crtc
->adjusted_x
= x_offset
;
3064 intel_crtc
->adjusted_y
= y_offset
;
3066 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3067 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3068 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3069 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3071 if (scaler_id
>= 0) {
3072 uint32_t ps_ctrl
= 0;
3074 WARN_ON(!dst_w
|| !dst_h
);
3075 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3076 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3077 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3078 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3079 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3080 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3081 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3083 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3086 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3088 POSTING_READ(PLANE_SURF(pipe
, 0));
3091 static void skylake_disable_primary_plane(struct drm_plane
*primary
,
3092 struct drm_crtc
*crtc
)
3094 struct drm_device
*dev
= crtc
->dev
;
3095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3096 int pipe
= to_intel_crtc(crtc
)->pipe
;
3098 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3099 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3100 POSTING_READ(PLANE_SURF(pipe
, 0));
3103 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3105 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3106 int x
, int y
, enum mode_set_atomic state
)
3108 /* Support for kgdboc is disabled, this needs a major rework. */
3109 DRM_ERROR("legacy panic handler not supported any more.\n");
3114 static void intel_complete_page_flips(struct drm_i915_private
*dev_priv
)
3116 struct drm_crtc
*crtc
;
3118 for_each_crtc(dev_priv
->dev
, crtc
) {
3119 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3120 enum plane plane
= intel_crtc
->plane
;
3122 intel_prepare_page_flip(dev_priv
, plane
);
3123 intel_finish_page_flip_plane(dev_priv
, plane
);
3127 static void intel_update_primary_planes(struct drm_device
*dev
)
3129 struct drm_crtc
*crtc
;
3131 for_each_crtc(dev
, crtc
) {
3132 struct intel_plane
*plane
= to_intel_plane(crtc
->primary
);
3133 struct intel_plane_state
*plane_state
;
3135 drm_modeset_lock_crtc(crtc
, &plane
->base
);
3136 plane_state
= to_intel_plane_state(plane
->base
.state
);
3138 if (plane_state
->visible
)
3139 plane
->update_plane(&plane
->base
,
3140 to_intel_crtc_state(crtc
->state
),
3143 drm_modeset_unlock_crtc(crtc
);
3147 void intel_prepare_reset(struct drm_i915_private
*dev_priv
)
3149 /* no reset support for gen2 */
3150 if (IS_GEN2(dev_priv
))
3153 /* reset doesn't touch the display */
3154 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
3157 drm_modeset_lock_all(dev_priv
->dev
);
3159 * Disabling the crtcs gracefully seems nicer. Also the
3160 * g33 docs say we should at least disable all the planes.
3162 intel_display_suspend(dev_priv
->dev
);
3165 void intel_finish_reset(struct drm_i915_private
*dev_priv
)
3168 * Flips in the rings will be nuked by the reset,
3169 * so complete all pending flips so that user space
3170 * will get its events and not get stuck.
3172 intel_complete_page_flips(dev_priv
);
3174 /* no reset support for gen2 */
3175 if (IS_GEN2(dev_priv
))
3178 /* reset doesn't touch the display */
3179 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
)) {
3181 * Flips in the rings have been nuked by the reset,
3182 * so update the base address of all primary
3183 * planes to the the last fb to make sure we're
3184 * showing the correct fb after a reset.
3186 * FIXME: Atomic will make this obsolete since we won't schedule
3187 * CS-based flips (which might get lost in gpu resets) any more.
3189 intel_update_primary_planes(dev_priv
->dev
);
3194 * The display has been reset as well,
3195 * so need a full re-initialization.
3197 intel_runtime_pm_disable_interrupts(dev_priv
);
3198 intel_runtime_pm_enable_interrupts(dev_priv
);
3200 intel_modeset_init_hw(dev_priv
->dev
);
3202 spin_lock_irq(&dev_priv
->irq_lock
);
3203 if (dev_priv
->display
.hpd_irq_setup
)
3204 dev_priv
->display
.hpd_irq_setup(dev_priv
);
3205 spin_unlock_irq(&dev_priv
->irq_lock
);
3207 intel_display_resume(dev_priv
->dev
);
3209 intel_hpd_init(dev_priv
);
3211 drm_modeset_unlock_all(dev_priv
->dev
);
3214 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3216 struct drm_device
*dev
= crtc
->dev
;
3217 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3218 unsigned reset_counter
;
3221 reset_counter
= i915_reset_counter(&to_i915(dev
)->gpu_error
);
3222 if (intel_crtc
->reset_counter
!= reset_counter
)
3225 spin_lock_irq(&dev
->event_lock
);
3226 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3227 spin_unlock_irq(&dev
->event_lock
);
3232 static void intel_update_pipe_config(struct intel_crtc
*crtc
,
3233 struct intel_crtc_state
*old_crtc_state
)
3235 struct drm_device
*dev
= crtc
->base
.dev
;
3236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3237 struct intel_crtc_state
*pipe_config
=
3238 to_intel_crtc_state(crtc
->base
.state
);
3240 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3241 crtc
->base
.mode
= crtc
->base
.state
->mode
;
3243 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3244 old_crtc_state
->pipe_src_w
, old_crtc_state
->pipe_src_h
,
3245 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
3248 * Update pipe size and adjust fitter if needed: the reason for this is
3249 * that in compute_mode_changes we check the native mode (not the pfit
3250 * mode) to see if we can flip rather than do a full mode set. In the
3251 * fastboot case, we'll flip, but if we don't update the pipesrc and
3252 * pfit state, we'll end up with a big fb scanned out into the wrong
3256 I915_WRITE(PIPESRC(crtc
->pipe
),
3257 ((pipe_config
->pipe_src_w
- 1) << 16) |
3258 (pipe_config
->pipe_src_h
- 1));
3260 /* on skylake this is done by detaching scalers */
3261 if (INTEL_INFO(dev
)->gen
>= 9) {
3262 skl_detach_scalers(crtc
);
3264 if (pipe_config
->pch_pfit
.enabled
)
3265 skylake_pfit_enable(crtc
);
3266 } else if (HAS_PCH_SPLIT(dev
)) {
3267 if (pipe_config
->pch_pfit
.enabled
)
3268 ironlake_pfit_enable(crtc
);
3269 else if (old_crtc_state
->pch_pfit
.enabled
)
3270 ironlake_pfit_disable(crtc
, true);
3274 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3276 struct drm_device
*dev
= crtc
->dev
;
3277 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3278 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3279 int pipe
= intel_crtc
->pipe
;
3283 /* enable normal train */
3284 reg
= FDI_TX_CTL(pipe
);
3285 temp
= I915_READ(reg
);
3286 if (IS_IVYBRIDGE(dev
)) {
3287 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3288 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3290 temp
&= ~FDI_LINK_TRAIN_NONE
;
3291 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3293 I915_WRITE(reg
, temp
);
3295 reg
= FDI_RX_CTL(pipe
);
3296 temp
= I915_READ(reg
);
3297 if (HAS_PCH_CPT(dev
)) {
3298 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3299 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3301 temp
&= ~FDI_LINK_TRAIN_NONE
;
3302 temp
|= FDI_LINK_TRAIN_NONE
;
3304 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3306 /* wait one idle pattern time */
3310 /* IVB wants error correction enabled */
3311 if (IS_IVYBRIDGE(dev
))
3312 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3313 FDI_FE_ERRC_ENABLE
);
3316 /* The FDI link training functions for ILK/Ibexpeak. */
3317 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3319 struct drm_device
*dev
= crtc
->dev
;
3320 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3321 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3322 int pipe
= intel_crtc
->pipe
;
3326 /* FDI needs bits from pipe first */
3327 assert_pipe_enabled(dev_priv
, pipe
);
3329 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3331 reg
= FDI_RX_IMR(pipe
);
3332 temp
= I915_READ(reg
);
3333 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3334 temp
&= ~FDI_RX_BIT_LOCK
;
3335 I915_WRITE(reg
, temp
);
3339 /* enable CPU FDI TX and PCH FDI RX */
3340 reg
= FDI_TX_CTL(pipe
);
3341 temp
= I915_READ(reg
);
3342 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3343 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3344 temp
&= ~FDI_LINK_TRAIN_NONE
;
3345 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3346 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3348 reg
= FDI_RX_CTL(pipe
);
3349 temp
= I915_READ(reg
);
3350 temp
&= ~FDI_LINK_TRAIN_NONE
;
3351 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3352 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3357 /* Ironlake workaround, enable clock pointer after FDI enable*/
3358 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3359 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3360 FDI_RX_PHASE_SYNC_POINTER_EN
);
3362 reg
= FDI_RX_IIR(pipe
);
3363 for (tries
= 0; tries
< 5; tries
++) {
3364 temp
= I915_READ(reg
);
3365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3367 if ((temp
& FDI_RX_BIT_LOCK
)) {
3368 DRM_DEBUG_KMS("FDI train 1 done.\n");
3369 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3374 DRM_ERROR("FDI train 1 fail!\n");
3377 reg
= FDI_TX_CTL(pipe
);
3378 temp
= I915_READ(reg
);
3379 temp
&= ~FDI_LINK_TRAIN_NONE
;
3380 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3381 I915_WRITE(reg
, temp
);
3383 reg
= FDI_RX_CTL(pipe
);
3384 temp
= I915_READ(reg
);
3385 temp
&= ~FDI_LINK_TRAIN_NONE
;
3386 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3387 I915_WRITE(reg
, temp
);
3392 reg
= FDI_RX_IIR(pipe
);
3393 for (tries
= 0; tries
< 5; tries
++) {
3394 temp
= I915_READ(reg
);
3395 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3397 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3398 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3399 DRM_DEBUG_KMS("FDI train 2 done.\n");
3404 DRM_ERROR("FDI train 2 fail!\n");
3406 DRM_DEBUG_KMS("FDI train done\n");
3410 static const int snb_b_fdi_train_param
[] = {
3411 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3412 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3413 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3414 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3417 /* The FDI link training functions for SNB/Cougarpoint. */
3418 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3420 struct drm_device
*dev
= crtc
->dev
;
3421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3422 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3423 int pipe
= intel_crtc
->pipe
;
3427 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3429 reg
= FDI_RX_IMR(pipe
);
3430 temp
= I915_READ(reg
);
3431 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3432 temp
&= ~FDI_RX_BIT_LOCK
;
3433 I915_WRITE(reg
, temp
);
3438 /* enable CPU FDI TX and PCH FDI RX */
3439 reg
= FDI_TX_CTL(pipe
);
3440 temp
= I915_READ(reg
);
3441 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3442 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3443 temp
&= ~FDI_LINK_TRAIN_NONE
;
3444 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3445 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3447 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3448 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3450 I915_WRITE(FDI_RX_MISC(pipe
),
3451 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3453 reg
= FDI_RX_CTL(pipe
);
3454 temp
= I915_READ(reg
);
3455 if (HAS_PCH_CPT(dev
)) {
3456 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3457 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3459 temp
&= ~FDI_LINK_TRAIN_NONE
;
3460 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3462 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3467 for (i
= 0; i
< 4; i
++) {
3468 reg
= FDI_TX_CTL(pipe
);
3469 temp
= I915_READ(reg
);
3470 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3471 temp
|= snb_b_fdi_train_param
[i
];
3472 I915_WRITE(reg
, temp
);
3477 for (retry
= 0; retry
< 5; retry
++) {
3478 reg
= FDI_RX_IIR(pipe
);
3479 temp
= I915_READ(reg
);
3480 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3481 if (temp
& FDI_RX_BIT_LOCK
) {
3482 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3483 DRM_DEBUG_KMS("FDI train 1 done.\n");
3492 DRM_ERROR("FDI train 1 fail!\n");
3495 reg
= FDI_TX_CTL(pipe
);
3496 temp
= I915_READ(reg
);
3497 temp
&= ~FDI_LINK_TRAIN_NONE
;
3498 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3500 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3502 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3504 I915_WRITE(reg
, temp
);
3506 reg
= FDI_RX_CTL(pipe
);
3507 temp
= I915_READ(reg
);
3508 if (HAS_PCH_CPT(dev
)) {
3509 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3510 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3512 temp
&= ~FDI_LINK_TRAIN_NONE
;
3513 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3515 I915_WRITE(reg
, temp
);
3520 for (i
= 0; i
< 4; i
++) {
3521 reg
= FDI_TX_CTL(pipe
);
3522 temp
= I915_READ(reg
);
3523 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3524 temp
|= snb_b_fdi_train_param
[i
];
3525 I915_WRITE(reg
, temp
);
3530 for (retry
= 0; retry
< 5; retry
++) {
3531 reg
= FDI_RX_IIR(pipe
);
3532 temp
= I915_READ(reg
);
3533 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3534 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3535 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3536 DRM_DEBUG_KMS("FDI train 2 done.\n");
3545 DRM_ERROR("FDI train 2 fail!\n");
3547 DRM_DEBUG_KMS("FDI train done.\n");
3550 /* Manual link training for Ivy Bridge A0 parts */
3551 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3553 struct drm_device
*dev
= crtc
->dev
;
3554 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3555 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3556 int pipe
= intel_crtc
->pipe
;
3560 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3562 reg
= FDI_RX_IMR(pipe
);
3563 temp
= I915_READ(reg
);
3564 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3565 temp
&= ~FDI_RX_BIT_LOCK
;
3566 I915_WRITE(reg
, temp
);
3571 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3572 I915_READ(FDI_RX_IIR(pipe
)));
3574 /* Try each vswing and preemphasis setting twice before moving on */
3575 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3576 /* disable first in case we need to retry */
3577 reg
= FDI_TX_CTL(pipe
);
3578 temp
= I915_READ(reg
);
3579 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3580 temp
&= ~FDI_TX_ENABLE
;
3581 I915_WRITE(reg
, temp
);
3583 reg
= FDI_RX_CTL(pipe
);
3584 temp
= I915_READ(reg
);
3585 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3586 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3587 temp
&= ~FDI_RX_ENABLE
;
3588 I915_WRITE(reg
, temp
);
3590 /* enable CPU FDI TX and PCH FDI RX */
3591 reg
= FDI_TX_CTL(pipe
);
3592 temp
= I915_READ(reg
);
3593 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3594 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3595 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3596 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3597 temp
|= snb_b_fdi_train_param
[j
/2];
3598 temp
|= FDI_COMPOSITE_SYNC
;
3599 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3601 I915_WRITE(FDI_RX_MISC(pipe
),
3602 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3604 reg
= FDI_RX_CTL(pipe
);
3605 temp
= I915_READ(reg
);
3606 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3607 temp
|= FDI_COMPOSITE_SYNC
;
3608 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3611 udelay(1); /* should be 0.5us */
3613 for (i
= 0; i
< 4; i
++) {
3614 reg
= FDI_RX_IIR(pipe
);
3615 temp
= I915_READ(reg
);
3616 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3618 if (temp
& FDI_RX_BIT_LOCK
||
3619 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3620 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3621 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3625 udelay(1); /* should be 0.5us */
3628 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3633 reg
= FDI_TX_CTL(pipe
);
3634 temp
= I915_READ(reg
);
3635 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3636 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3637 I915_WRITE(reg
, temp
);
3639 reg
= FDI_RX_CTL(pipe
);
3640 temp
= I915_READ(reg
);
3641 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3642 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3643 I915_WRITE(reg
, temp
);
3646 udelay(2); /* should be 1.5us */
3648 for (i
= 0; i
< 4; i
++) {
3649 reg
= FDI_RX_IIR(pipe
);
3650 temp
= I915_READ(reg
);
3651 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3653 if (temp
& FDI_RX_SYMBOL_LOCK
||
3654 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3655 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3656 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3660 udelay(2); /* should be 1.5us */
3663 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3667 DRM_DEBUG_KMS("FDI train done.\n");
3670 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3672 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3674 int pipe
= intel_crtc
->pipe
;
3678 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3679 reg
= FDI_RX_CTL(pipe
);
3680 temp
= I915_READ(reg
);
3681 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3682 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3683 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3684 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3689 /* Switch from Rawclk to PCDclk */
3690 temp
= I915_READ(reg
);
3691 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3696 /* Enable CPU FDI TX PLL, always on for Ironlake */
3697 reg
= FDI_TX_CTL(pipe
);
3698 temp
= I915_READ(reg
);
3699 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3700 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3707 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3709 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3711 int pipe
= intel_crtc
->pipe
;
3715 /* Switch from PCDclk to Rawclk */
3716 reg
= FDI_RX_CTL(pipe
);
3717 temp
= I915_READ(reg
);
3718 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3720 /* Disable CPU FDI TX PLL */
3721 reg
= FDI_TX_CTL(pipe
);
3722 temp
= I915_READ(reg
);
3723 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3728 reg
= FDI_RX_CTL(pipe
);
3729 temp
= I915_READ(reg
);
3730 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3732 /* Wait for the clocks to turn off. */
3737 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3739 struct drm_device
*dev
= crtc
->dev
;
3740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3741 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3742 int pipe
= intel_crtc
->pipe
;
3746 /* disable CPU FDI tx and PCH FDI rx */
3747 reg
= FDI_TX_CTL(pipe
);
3748 temp
= I915_READ(reg
);
3749 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3752 reg
= FDI_RX_CTL(pipe
);
3753 temp
= I915_READ(reg
);
3754 temp
&= ~(0x7 << 16);
3755 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3756 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3761 /* Ironlake workaround, disable clock pointer after downing FDI */
3762 if (HAS_PCH_IBX(dev
))
3763 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3765 /* still set train pattern 1 */
3766 reg
= FDI_TX_CTL(pipe
);
3767 temp
= I915_READ(reg
);
3768 temp
&= ~FDI_LINK_TRAIN_NONE
;
3769 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3770 I915_WRITE(reg
, temp
);
3772 reg
= FDI_RX_CTL(pipe
);
3773 temp
= I915_READ(reg
);
3774 if (HAS_PCH_CPT(dev
)) {
3775 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3776 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3778 temp
&= ~FDI_LINK_TRAIN_NONE
;
3779 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3781 /* BPC in FDI rx is consistent with that in PIPECONF */
3782 temp
&= ~(0x07 << 16);
3783 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3784 I915_WRITE(reg
, temp
);
3790 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3792 struct intel_crtc
*crtc
;
3794 /* Note that we don't need to be called with mode_config.lock here
3795 * as our list of CRTC objects is static for the lifetime of the
3796 * device and so cannot disappear as we iterate. Similarly, we can
3797 * happily treat the predicates as racy, atomic checks as userspace
3798 * cannot claim and pin a new fb without at least acquring the
3799 * struct_mutex and so serialising with us.
3801 for_each_intel_crtc(dev
, crtc
) {
3802 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3805 if (crtc
->unpin_work
)
3806 intel_wait_for_vblank(dev
, crtc
->pipe
);
3814 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3816 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3817 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3819 /* ensure that the unpin work is consistent wrt ->pending. */
3821 intel_crtc
->unpin_work
= NULL
;
3824 drm_crtc_send_vblank_event(&intel_crtc
->base
, work
->event
);
3826 drm_crtc_vblank_put(&intel_crtc
->base
);
3828 wake_up_all(&dev_priv
->pending_flip_queue
);
3829 queue_work(dev_priv
->wq
, &work
->work
);
3831 trace_i915_flip_complete(intel_crtc
->plane
,
3832 work
->pending_flip_obj
);
3835 static int intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3837 struct drm_device
*dev
= crtc
->dev
;
3838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3841 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3843 ret
= wait_event_interruptible_timeout(
3844 dev_priv
->pending_flip_queue
,
3845 !intel_crtc_has_pending_flip(crtc
),
3852 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3854 spin_lock_irq(&dev
->event_lock
);
3855 if (intel_crtc
->unpin_work
) {
3856 WARN_ONCE(1, "Removing stuck page flip\n");
3857 page_flip_completed(intel_crtc
);
3859 spin_unlock_irq(&dev
->event_lock
);
3865 static void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
)
3869 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3871 mutex_lock(&dev_priv
->sb_lock
);
3873 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3874 temp
|= SBI_SSCCTL_DISABLE
;
3875 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3877 mutex_unlock(&dev_priv
->sb_lock
);
3880 /* Program iCLKIP clock to the desired frequency */
3881 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3883 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
3884 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3885 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3888 lpt_disable_iclkip(dev_priv
);
3890 /* The iCLK virtual clock root frequency is in MHz,
3891 * but the adjusted_mode->crtc_clock in in KHz. To get the
3892 * divisors, it is necessary to divide one by another, so we
3893 * convert the virtual clock precision to KHz here for higher
3896 for (auxdiv
= 0; auxdiv
< 2; auxdiv
++) {
3897 u32 iclk_virtual_root_freq
= 172800 * 1000;
3898 u32 iclk_pi_range
= 64;
3899 u32 desired_divisor
;
3901 desired_divisor
= DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
3903 divsel
= (desired_divisor
/ iclk_pi_range
) - 2;
3904 phaseinc
= desired_divisor
% iclk_pi_range
;
3907 * Near 20MHz is a corner case which is
3908 * out of range for the 7-bit divisor
3914 /* This should not happen with any sane values */
3915 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3916 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3917 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3918 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3920 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3927 mutex_lock(&dev_priv
->sb_lock
);
3929 /* Program SSCDIVINTPHASE6 */
3930 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3931 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3932 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3933 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3934 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3935 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3936 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3937 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3939 /* Program SSCAUXDIV */
3940 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3941 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3942 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3943 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3945 /* Enable modulator and associated divider */
3946 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3947 temp
&= ~SBI_SSCCTL_DISABLE
;
3948 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3950 mutex_unlock(&dev_priv
->sb_lock
);
3952 /* Wait for initialization time */
3955 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3958 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
)
3960 u32 divsel
, phaseinc
, auxdiv
;
3961 u32 iclk_virtual_root_freq
= 172800 * 1000;
3962 u32 iclk_pi_range
= 64;
3963 u32 desired_divisor
;
3966 if ((I915_READ(PIXCLK_GATE
) & PIXCLK_GATE_UNGATE
) == 0)
3969 mutex_lock(&dev_priv
->sb_lock
);
3971 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3972 if (temp
& SBI_SSCCTL_DISABLE
) {
3973 mutex_unlock(&dev_priv
->sb_lock
);
3977 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3978 divsel
= (temp
& SBI_SSCDIVINTPHASE_DIVSEL_MASK
) >>
3979 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT
;
3980 phaseinc
= (temp
& SBI_SSCDIVINTPHASE_INCVAL_MASK
) >>
3981 SBI_SSCDIVINTPHASE_INCVAL_SHIFT
;
3983 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3984 auxdiv
= (temp
& SBI_SSCAUXDIV_FINALDIV2SEL_MASK
) >>
3985 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT
;
3987 mutex_unlock(&dev_priv
->sb_lock
);
3989 desired_divisor
= (divsel
+ 2) * iclk_pi_range
+ phaseinc
;
3991 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
3992 desired_divisor
<< auxdiv
);
3995 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3996 enum pipe pch_transcoder
)
3998 struct drm_device
*dev
= crtc
->base
.dev
;
3999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4000 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4002 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4003 I915_READ(HTOTAL(cpu_transcoder
)));
4004 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4005 I915_READ(HBLANK(cpu_transcoder
)));
4006 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4007 I915_READ(HSYNC(cpu_transcoder
)));
4009 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4010 I915_READ(VTOTAL(cpu_transcoder
)));
4011 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4012 I915_READ(VBLANK(cpu_transcoder
)));
4013 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4014 I915_READ(VSYNC(cpu_transcoder
)));
4015 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4016 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4019 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4024 temp
= I915_READ(SOUTH_CHICKEN1
);
4025 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4028 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4029 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4031 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4033 temp
|= FDI_BC_BIFURCATION_SELECT
;
4035 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4036 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4037 POSTING_READ(SOUTH_CHICKEN1
);
4040 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4042 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4044 switch (intel_crtc
->pipe
) {
4048 if (intel_crtc
->config
->fdi_lanes
> 2)
4049 cpt_set_fdi_bc_bifurcation(dev
, false);
4051 cpt_set_fdi_bc_bifurcation(dev
, true);
4055 cpt_set_fdi_bc_bifurcation(dev
, true);
4063 /* Return which DP Port should be selected for Transcoder DP control */
4065 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4067 struct drm_device
*dev
= crtc
->dev
;
4068 struct intel_encoder
*encoder
;
4070 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4071 if (encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4072 encoder
->type
== INTEL_OUTPUT_EDP
)
4073 return enc_to_dig_port(&encoder
->base
)->port
;
4080 * Enable PCH resources required for PCH ports:
4082 * - FDI training & RX/TX
4083 * - update transcoder timings
4084 * - DP transcoding bits
4087 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4089 struct drm_device
*dev
= crtc
->dev
;
4090 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4091 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4092 int pipe
= intel_crtc
->pipe
;
4095 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4097 if (IS_IVYBRIDGE(dev
))
4098 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4100 /* Write the TU size bits before fdi link training, so that error
4101 * detection works. */
4102 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4103 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4105 /* For PCH output, training FDI link */
4106 dev_priv
->display
.fdi_link_train(crtc
);
4108 /* We need to program the right clock selection before writing the pixel
4109 * mutliplier into the DPLL. */
4110 if (HAS_PCH_CPT(dev
)) {
4113 temp
= I915_READ(PCH_DPLL_SEL
);
4114 temp
|= TRANS_DPLL_ENABLE(pipe
);
4115 sel
= TRANS_DPLLB_SEL(pipe
);
4116 if (intel_crtc
->config
->shared_dpll
==
4117 intel_get_shared_dpll_by_id(dev_priv
, DPLL_ID_PCH_PLL_B
))
4121 I915_WRITE(PCH_DPLL_SEL
, temp
);
4124 /* XXX: pch pll's can be enabled any time before we enable the PCH
4125 * transcoder, and we actually should do this to not upset any PCH
4126 * transcoder that already use the clock when we share it.
4128 * Note that enable_shared_dpll tries to do the right thing, but
4129 * get_shared_dpll unconditionally resets the pll - we need that to have
4130 * the right LVDS enable sequence. */
4131 intel_enable_shared_dpll(intel_crtc
);
4133 /* set transcoder timing, panel must allow it */
4134 assert_panel_unlocked(dev_priv
, pipe
);
4135 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4137 intel_fdi_normal_train(crtc
);
4139 /* For PCH DP, enable TRANS_DP_CTL */
4140 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4141 const struct drm_display_mode
*adjusted_mode
=
4142 &intel_crtc
->config
->base
.adjusted_mode
;
4143 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4144 i915_reg_t reg
= TRANS_DP_CTL(pipe
);
4145 temp
= I915_READ(reg
);
4146 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4147 TRANS_DP_SYNC_MASK
|
4149 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4150 temp
|= bpc
<< 9; /* same format but at 11:9 */
4152 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
4153 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4154 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
4155 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4157 switch (intel_trans_dp_port_sel(crtc
)) {
4159 temp
|= TRANS_DP_PORT_SEL_B
;
4162 temp
|= TRANS_DP_PORT_SEL_C
;
4165 temp
|= TRANS_DP_PORT_SEL_D
;
4171 I915_WRITE(reg
, temp
);
4174 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4177 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4179 struct drm_device
*dev
= crtc
->dev
;
4180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4181 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4182 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4184 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4186 lpt_program_iclkip(crtc
);
4188 /* Set transcoder timing. */
4189 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4191 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4194 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4197 i915_reg_t dslreg
= PIPEDSL(pipe
);
4200 temp
= I915_READ(dslreg
);
4202 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4203 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4204 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4209 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
4210 unsigned scaler_user
, int *scaler_id
, unsigned int rotation
,
4211 int src_w
, int src_h
, int dst_w
, int dst_h
)
4213 struct intel_crtc_scaler_state
*scaler_state
=
4214 &crtc_state
->scaler_state
;
4215 struct intel_crtc
*intel_crtc
=
4216 to_intel_crtc(crtc_state
->base
.crtc
);
4219 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4220 (src_h
!= dst_w
|| src_w
!= dst_h
):
4221 (src_w
!= dst_w
|| src_h
!= dst_h
);
4224 * if plane is being disabled or scaler is no more required or force detach
4225 * - free scaler binded to this plane/crtc
4226 * - in order to do this, update crtc->scaler_usage
4228 * Here scaler state in crtc_state is set free so that
4229 * scaler can be assigned to other user. Actual register
4230 * update to free the scaler is done in plane/panel-fit programming.
4231 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4233 if (force_detach
|| !need_scaling
) {
4234 if (*scaler_id
>= 0) {
4235 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
4236 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4238 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4239 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4240 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
4241 scaler_state
->scaler_users
);
4248 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4249 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4251 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4252 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4253 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4254 "size is out of scaler range\n",
4255 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
4259 /* mark this plane as a scaler user in crtc_state */
4260 scaler_state
->scaler_users
|= (1 << scaler_user
);
4261 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4262 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4263 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
4264 scaler_state
->scaler_users
);
4270 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4272 * @state: crtc's scaler state
4275 * 0 - scaler_usage updated successfully
4276 * error - requested scaling cannot be supported or other error condition
4278 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
4280 struct intel_crtc
*intel_crtc
= to_intel_crtc(state
->base
.crtc
);
4281 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
4283 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4284 intel_crtc
->base
.base
.id
, intel_crtc
->pipe
, SKL_CRTC_INDEX
);
4286 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
4287 &state
->scaler_state
.scaler_id
, BIT(DRM_ROTATE_0
),
4288 state
->pipe_src_w
, state
->pipe_src_h
,
4289 adjusted_mode
->crtc_hdisplay
, adjusted_mode
->crtc_vdisplay
);
4293 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4295 * @state: crtc's scaler state
4296 * @plane_state: atomic plane state to update
4299 * 0 - scaler_usage updated successfully
4300 * error - requested scaling cannot be supported or other error condition
4302 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
4303 struct intel_plane_state
*plane_state
)
4306 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4307 struct intel_plane
*intel_plane
=
4308 to_intel_plane(plane_state
->base
.plane
);
4309 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4312 bool force_detach
= !fb
|| !plane_state
->visible
;
4314 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4315 intel_plane
->base
.base
.id
, intel_crtc
->pipe
,
4316 drm_plane_index(&intel_plane
->base
));
4318 ret
= skl_update_scaler(crtc_state
, force_detach
,
4319 drm_plane_index(&intel_plane
->base
),
4320 &plane_state
->scaler_id
,
4321 plane_state
->base
.rotation
,
4322 drm_rect_width(&plane_state
->src
) >> 16,
4323 drm_rect_height(&plane_state
->src
) >> 16,
4324 drm_rect_width(&plane_state
->dst
),
4325 drm_rect_height(&plane_state
->dst
));
4327 if (ret
|| plane_state
->scaler_id
< 0)
4330 /* check colorkey */
4331 if (plane_state
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4332 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4333 intel_plane
->base
.base
.id
);
4337 /* Check src format */
4338 switch (fb
->pixel_format
) {
4339 case DRM_FORMAT_RGB565
:
4340 case DRM_FORMAT_XBGR8888
:
4341 case DRM_FORMAT_XRGB8888
:
4342 case DRM_FORMAT_ABGR8888
:
4343 case DRM_FORMAT_ARGB8888
:
4344 case DRM_FORMAT_XRGB2101010
:
4345 case DRM_FORMAT_XBGR2101010
:
4346 case DRM_FORMAT_YUYV
:
4347 case DRM_FORMAT_YVYU
:
4348 case DRM_FORMAT_UYVY
:
4349 case DRM_FORMAT_VYUY
:
4352 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4353 intel_plane
->base
.base
.id
, fb
->base
.id
, fb
->pixel_format
);
4360 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
4364 for (i
= 0; i
< crtc
->num_scalers
; i
++)
4365 skl_detach_scaler(crtc
, i
);
4368 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4370 struct drm_device
*dev
= crtc
->base
.dev
;
4371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4372 int pipe
= crtc
->pipe
;
4373 struct intel_crtc_scaler_state
*scaler_state
=
4374 &crtc
->config
->scaler_state
;
4376 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4378 if (crtc
->config
->pch_pfit
.enabled
) {
4381 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4382 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4386 id
= scaler_state
->scaler_id
;
4387 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4388 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4389 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4390 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4392 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4396 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4398 struct drm_device
*dev
= crtc
->base
.dev
;
4399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4400 int pipe
= crtc
->pipe
;
4402 if (crtc
->config
->pch_pfit
.enabled
) {
4403 /* Force use of hard-coded filter coefficients
4404 * as some pre-programmed values are broken,
4407 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4408 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4409 PF_PIPE_SEL_IVB(pipe
));
4411 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4412 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4413 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4417 void hsw_enable_ips(struct intel_crtc
*crtc
)
4419 struct drm_device
*dev
= crtc
->base
.dev
;
4420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4422 if (!crtc
->config
->ips_enabled
)
4426 * We can only enable IPS after we enable a plane and wait for a vblank
4427 * This function is called from post_plane_update, which is run after
4431 assert_plane_enabled(dev_priv
, crtc
->plane
);
4432 if (IS_BROADWELL(dev
)) {
4433 mutex_lock(&dev_priv
->rps
.hw_lock
);
4434 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4435 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4436 /* Quoting Art Runyan: "its not safe to expect any particular
4437 * value in IPS_CTL bit 31 after enabling IPS through the
4438 * mailbox." Moreover, the mailbox may return a bogus state,
4439 * so we need to just enable it and continue on.
4442 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4443 /* The bit only becomes 1 in the next vblank, so this wait here
4444 * is essentially intel_wait_for_vblank. If we don't have this
4445 * and don't wait for vblanks until the end of crtc_enable, then
4446 * the HW state readout code will complain that the expected
4447 * IPS_CTL value is not the one we read. */
4448 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4449 DRM_ERROR("Timed out waiting for IPS enable\n");
4453 void hsw_disable_ips(struct intel_crtc
*crtc
)
4455 struct drm_device
*dev
= crtc
->base
.dev
;
4456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4458 if (!crtc
->config
->ips_enabled
)
4461 assert_plane_enabled(dev_priv
, crtc
->plane
);
4462 if (IS_BROADWELL(dev
)) {
4463 mutex_lock(&dev_priv
->rps
.hw_lock
);
4464 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4465 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4466 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4467 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4468 DRM_ERROR("Timed out waiting for IPS disable\n");
4470 I915_WRITE(IPS_CTL
, 0);
4471 POSTING_READ(IPS_CTL
);
4474 /* We need to wait for a vblank before we can disable the plane. */
4475 intel_wait_for_vblank(dev
, crtc
->pipe
);
4478 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4480 if (intel_crtc
->overlay
) {
4481 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4484 mutex_lock(&dev
->struct_mutex
);
4485 dev_priv
->mm
.interruptible
= false;
4486 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4487 dev_priv
->mm
.interruptible
= true;
4488 mutex_unlock(&dev
->struct_mutex
);
4491 /* Let userspace switch the overlay on again. In most cases userspace
4492 * has to recompute where to put it anyway.
4497 * intel_post_enable_primary - Perform operations after enabling primary plane
4498 * @crtc: the CRTC whose primary plane was just enabled
4500 * Performs potentially sleeping operations that must be done after the primary
4501 * plane is enabled, such as updating FBC and IPS. Note that this may be
4502 * called due to an explicit primary plane update, or due to an implicit
4503 * re-enable that is caused when a sprite plane is updated to no longer
4504 * completely hide the primary plane.
4507 intel_post_enable_primary(struct drm_crtc
*crtc
)
4509 struct drm_device
*dev
= crtc
->dev
;
4510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4511 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4512 int pipe
= intel_crtc
->pipe
;
4515 * FIXME IPS should be fine as long as one plane is
4516 * enabled, but in practice it seems to have problems
4517 * when going from primary only to sprite only and vice
4520 hsw_enable_ips(intel_crtc
);
4523 * Gen2 reports pipe underruns whenever all planes are disabled.
4524 * So don't enable underrun reporting before at least some planes
4526 * FIXME: Need to fix the logic to work when we turn off all planes
4527 * but leave the pipe running.
4530 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4532 /* Underruns don't always raise interrupts, so check manually. */
4533 intel_check_cpu_fifo_underruns(dev_priv
);
4534 intel_check_pch_fifo_underruns(dev_priv
);
4537 /* FIXME move all this to pre_plane_update() with proper state tracking */
4539 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4541 struct drm_device
*dev
= crtc
->dev
;
4542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4543 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4544 int pipe
= intel_crtc
->pipe
;
4547 * Gen2 reports pipe underruns whenever all planes are disabled.
4548 * So diasble underrun reporting before all the planes get disabled.
4549 * FIXME: Need to fix the logic to work when we turn off all planes
4550 * but leave the pipe running.
4553 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4556 * FIXME IPS should be fine as long as one plane is
4557 * enabled, but in practice it seems to have problems
4558 * when going from primary only to sprite only and vice
4561 hsw_disable_ips(intel_crtc
);
4564 /* FIXME get rid of this and use pre_plane_update */
4566 intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
)
4568 struct drm_device
*dev
= crtc
->dev
;
4569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4570 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4571 int pipe
= intel_crtc
->pipe
;
4573 intel_pre_disable_primary(crtc
);
4576 * Vblank time updates from the shadow to live plane control register
4577 * are blocked if the memory self-refresh mode is active at that
4578 * moment. So to make sure the plane gets truly disabled, disable
4579 * first the self-refresh mode. The self-refresh enable bit in turn
4580 * will be checked/applied by the HW only at the next frame start
4581 * event which is after the vblank start event, so we need to have a
4582 * wait-for-vblank between disabling the plane and the pipe.
4584 if (HAS_GMCH_DISPLAY(dev
)) {
4585 intel_set_memory_cxsr(dev_priv
, false);
4586 dev_priv
->wm
.vlv
.cxsr
= false;
4587 intel_wait_for_vblank(dev
, pipe
);
4591 static void intel_post_plane_update(struct intel_crtc_state
*old_crtc_state
)
4593 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
4594 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
4595 struct intel_crtc_state
*pipe_config
=
4596 to_intel_crtc_state(crtc
->base
.state
);
4597 struct drm_device
*dev
= crtc
->base
.dev
;
4598 struct drm_plane
*primary
= crtc
->base
.primary
;
4599 struct drm_plane_state
*old_pri_state
=
4600 drm_atomic_get_existing_plane_state(old_state
, primary
);
4602 intel_frontbuffer_flip(dev
, pipe_config
->fb_bits
);
4604 crtc
->wm
.cxsr_allowed
= true;
4606 if (pipe_config
->update_wm_post
&& pipe_config
->base
.active
)
4607 intel_update_watermarks(&crtc
->base
);
4609 if (old_pri_state
) {
4610 struct intel_plane_state
*primary_state
=
4611 to_intel_plane_state(primary
->state
);
4612 struct intel_plane_state
*old_primary_state
=
4613 to_intel_plane_state(old_pri_state
);
4615 intel_fbc_post_update(crtc
);
4617 if (primary_state
->visible
&&
4618 (needs_modeset(&pipe_config
->base
) ||
4619 !old_primary_state
->visible
))
4620 intel_post_enable_primary(&crtc
->base
);
4624 static void intel_pre_plane_update(struct intel_crtc_state
*old_crtc_state
)
4626 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
4627 struct drm_device
*dev
= crtc
->base
.dev
;
4628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4629 struct intel_crtc_state
*pipe_config
=
4630 to_intel_crtc_state(crtc
->base
.state
);
4631 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
4632 struct drm_plane
*primary
= crtc
->base
.primary
;
4633 struct drm_plane_state
*old_pri_state
=
4634 drm_atomic_get_existing_plane_state(old_state
, primary
);
4635 bool modeset
= needs_modeset(&pipe_config
->base
);
4637 if (old_pri_state
) {
4638 struct intel_plane_state
*primary_state
=
4639 to_intel_plane_state(primary
->state
);
4640 struct intel_plane_state
*old_primary_state
=
4641 to_intel_plane_state(old_pri_state
);
4643 intel_fbc_pre_update(crtc
);
4645 if (old_primary_state
->visible
&&
4646 (modeset
|| !primary_state
->visible
))
4647 intel_pre_disable_primary(&crtc
->base
);
4650 if (pipe_config
->disable_cxsr
) {
4651 crtc
->wm
.cxsr_allowed
= false;
4654 * Vblank time updates from the shadow to live plane control register
4655 * are blocked if the memory self-refresh mode is active at that
4656 * moment. So to make sure the plane gets truly disabled, disable
4657 * first the self-refresh mode. The self-refresh enable bit in turn
4658 * will be checked/applied by the HW only at the next frame start
4659 * event which is after the vblank start event, so we need to have a
4660 * wait-for-vblank between disabling the plane and the pipe.
4662 if (old_crtc_state
->base
.active
) {
4663 intel_set_memory_cxsr(dev_priv
, false);
4664 dev_priv
->wm
.vlv
.cxsr
= false;
4665 intel_wait_for_vblank(dev
, crtc
->pipe
);
4670 * IVB workaround: must disable low power watermarks for at least
4671 * one frame before enabling scaling. LP watermarks can be re-enabled
4672 * when scaling is disabled.
4674 * WaCxSRDisabledForSpriteScaling:ivb
4676 if (pipe_config
->disable_lp_wm
) {
4677 ilk_disable_lp_wm(dev
);
4678 intel_wait_for_vblank(dev
, crtc
->pipe
);
4682 * If we're doing a modeset, we're done. No need to do any pre-vblank
4683 * watermark programming here.
4685 if (needs_modeset(&pipe_config
->base
))
4689 * For platforms that support atomic watermarks, program the
4690 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4691 * will be the intermediate values that are safe for both pre- and
4692 * post- vblank; when vblank happens, the 'active' values will be set
4693 * to the final 'target' values and we'll do this again to get the
4694 * optimal watermarks. For gen9+ platforms, the values we program here
4695 * will be the final target values which will get automatically latched
4696 * at vblank time; no further programming will be necessary.
4698 * If a platform hasn't been transitioned to atomic watermarks yet,
4699 * we'll continue to update watermarks the old way, if flags tell
4702 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4703 dev_priv
->display
.initial_watermarks(pipe_config
);
4704 else if (pipe_config
->update_wm_pre
)
4705 intel_update_watermarks(&crtc
->base
);
4708 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
, unsigned plane_mask
)
4710 struct drm_device
*dev
= crtc
->dev
;
4711 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4712 struct drm_plane
*p
;
4713 int pipe
= intel_crtc
->pipe
;
4715 intel_crtc_dpms_overlay_disable(intel_crtc
);
4717 drm_for_each_plane_mask(p
, dev
, plane_mask
)
4718 to_intel_plane(p
)->disable_plane(p
, crtc
);
4721 * FIXME: Once we grow proper nuclear flip support out of this we need
4722 * to compute the mask of flip planes precisely. For the time being
4723 * consider this a flip to a NULL plane.
4725 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4728 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4730 struct drm_device
*dev
= crtc
->dev
;
4731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4732 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4733 struct intel_encoder
*encoder
;
4734 int pipe
= intel_crtc
->pipe
;
4735 struct intel_crtc_state
*pipe_config
=
4736 to_intel_crtc_state(crtc
->state
);
4738 if (WARN_ON(intel_crtc
->active
))
4742 * Sometimes spurious CPU pipe underruns happen during FDI
4743 * training, at least with VGA+HDMI cloning. Suppress them.
4745 * On ILK we get an occasional spurious CPU pipe underruns
4746 * between eDP port A enable and vdd enable. Also PCH port
4747 * enable seems to result in the occasional CPU pipe underrun.
4749 * Spurious PCH underruns also occur during PCH enabling.
4751 if (intel_crtc
->config
->has_pch_encoder
|| IS_GEN5(dev_priv
))
4752 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4753 if (intel_crtc
->config
->has_pch_encoder
)
4754 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4756 if (intel_crtc
->config
->has_pch_encoder
)
4757 intel_prepare_shared_dpll(intel_crtc
);
4759 if (intel_crtc
->config
->has_dp_encoder
)
4760 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4762 intel_set_pipe_timings(intel_crtc
);
4763 intel_set_pipe_src_size(intel_crtc
);
4765 if (intel_crtc
->config
->has_pch_encoder
) {
4766 intel_cpu_transcoder_set_m_n(intel_crtc
,
4767 &intel_crtc
->config
->fdi_m_n
, NULL
);
4770 ironlake_set_pipeconf(crtc
);
4772 intel_crtc
->active
= true;
4774 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4775 if (encoder
->pre_enable
)
4776 encoder
->pre_enable(encoder
);
4778 if (intel_crtc
->config
->has_pch_encoder
) {
4779 /* Note: FDI PLL enabling _must_ be done before we enable the
4780 * cpu pipes, hence this is separate from all the other fdi/pch
4782 ironlake_fdi_pll_enable(intel_crtc
);
4784 assert_fdi_tx_disabled(dev_priv
, pipe
);
4785 assert_fdi_rx_disabled(dev_priv
, pipe
);
4788 ironlake_pfit_enable(intel_crtc
);
4791 * On ILK+ LUT must be loaded before the pipe is running but with
4794 intel_color_load_luts(&pipe_config
->base
);
4796 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4797 dev_priv
->display
.initial_watermarks(intel_crtc
->config
);
4798 intel_enable_pipe(intel_crtc
);
4800 if (intel_crtc
->config
->has_pch_encoder
)
4801 ironlake_pch_enable(crtc
);
4803 assert_vblank_disabled(crtc
);
4804 drm_crtc_vblank_on(crtc
);
4806 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4807 encoder
->enable(encoder
);
4809 if (HAS_PCH_CPT(dev
))
4810 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4812 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4813 if (intel_crtc
->config
->has_pch_encoder
)
4814 intel_wait_for_vblank(dev
, pipe
);
4815 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4816 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4819 /* IPS only exists on ULT machines and is tied to pipe A. */
4820 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4822 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4825 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4827 struct drm_device
*dev
= crtc
->dev
;
4828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4829 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4830 struct intel_encoder
*encoder
;
4831 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
4832 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4833 struct intel_crtc_state
*pipe_config
=
4834 to_intel_crtc_state(crtc
->state
);
4836 if (WARN_ON(intel_crtc
->active
))
4839 if (intel_crtc
->config
->has_pch_encoder
)
4840 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4843 if (intel_crtc
->config
->shared_dpll
)
4844 intel_enable_shared_dpll(intel_crtc
);
4846 if (intel_crtc
->config
->has_dp_encoder
)
4847 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4849 if (!intel_crtc
->config
->has_dsi_encoder
)
4850 intel_set_pipe_timings(intel_crtc
);
4852 intel_set_pipe_src_size(intel_crtc
);
4854 if (cpu_transcoder
!= TRANSCODER_EDP
&&
4855 !transcoder_is_dsi(cpu_transcoder
)) {
4856 I915_WRITE(PIPE_MULT(cpu_transcoder
),
4857 intel_crtc
->config
->pixel_multiplier
- 1);
4860 if (intel_crtc
->config
->has_pch_encoder
) {
4861 intel_cpu_transcoder_set_m_n(intel_crtc
,
4862 &intel_crtc
->config
->fdi_m_n
, NULL
);
4865 if (!intel_crtc
->config
->has_dsi_encoder
)
4866 haswell_set_pipeconf(crtc
);
4868 haswell_set_pipemisc(crtc
);
4870 intel_color_set_csc(&pipe_config
->base
);
4872 intel_crtc
->active
= true;
4874 if (intel_crtc
->config
->has_pch_encoder
)
4875 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4877 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4879 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4880 if (encoder
->pre_enable
)
4881 encoder
->pre_enable(encoder
);
4884 if (intel_crtc
->config
->has_pch_encoder
)
4885 dev_priv
->display
.fdi_link_train(crtc
);
4887 if (!intel_crtc
->config
->has_dsi_encoder
)
4888 intel_ddi_enable_pipe_clock(intel_crtc
);
4890 if (INTEL_INFO(dev
)->gen
>= 9)
4891 skylake_pfit_enable(intel_crtc
);
4893 ironlake_pfit_enable(intel_crtc
);
4896 * On ILK+ LUT must be loaded before the pipe is running but with
4899 intel_color_load_luts(&pipe_config
->base
);
4901 intel_ddi_set_pipe_settings(crtc
);
4902 if (!intel_crtc
->config
->has_dsi_encoder
)
4903 intel_ddi_enable_transcoder_func(crtc
);
4905 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4906 dev_priv
->display
.initial_watermarks(pipe_config
);
4908 intel_update_watermarks(crtc
);
4910 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4911 if (!intel_crtc
->config
->has_dsi_encoder
)
4912 intel_enable_pipe(intel_crtc
);
4914 if (intel_crtc
->config
->has_pch_encoder
)
4915 lpt_pch_enable(crtc
);
4917 if (intel_crtc
->config
->dp_encoder_is_mst
)
4918 intel_ddi_set_vc_payload_alloc(crtc
, true);
4920 assert_vblank_disabled(crtc
);
4921 drm_crtc_vblank_on(crtc
);
4923 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4924 encoder
->enable(encoder
);
4925 intel_opregion_notify_encoder(encoder
, true);
4928 if (intel_crtc
->config
->has_pch_encoder
) {
4929 intel_wait_for_vblank(dev
, pipe
);
4930 intel_wait_for_vblank(dev
, pipe
);
4931 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4932 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4936 /* If we change the relative order between pipe/planes enabling, we need
4937 * to change the workaround. */
4938 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
4939 if (IS_HASWELL(dev
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
4940 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
4941 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
4945 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
)
4947 struct drm_device
*dev
= crtc
->base
.dev
;
4948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4949 int pipe
= crtc
->pipe
;
4951 /* To avoid upsetting the power well on haswell only disable the pfit if
4952 * it's in use. The hw state code will make sure we get this right. */
4953 if (force
|| crtc
->config
->pch_pfit
.enabled
) {
4954 I915_WRITE(PF_CTL(pipe
), 0);
4955 I915_WRITE(PF_WIN_POS(pipe
), 0);
4956 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4960 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4962 struct drm_device
*dev
= crtc
->dev
;
4963 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4964 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4965 struct intel_encoder
*encoder
;
4966 int pipe
= intel_crtc
->pipe
;
4969 * Sometimes spurious CPU pipe underruns happen when the
4970 * pipe is already disabled, but FDI RX/TX is still enabled.
4971 * Happens at least with VGA+HDMI cloning. Suppress them.
4973 if (intel_crtc
->config
->has_pch_encoder
) {
4974 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4975 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4978 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4979 encoder
->disable(encoder
);
4981 drm_crtc_vblank_off(crtc
);
4982 assert_vblank_disabled(crtc
);
4984 intel_disable_pipe(intel_crtc
);
4986 ironlake_pfit_disable(intel_crtc
, false);
4988 if (intel_crtc
->config
->has_pch_encoder
)
4989 ironlake_fdi_disable(crtc
);
4991 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4992 if (encoder
->post_disable
)
4993 encoder
->post_disable(encoder
);
4995 if (intel_crtc
->config
->has_pch_encoder
) {
4996 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4998 if (HAS_PCH_CPT(dev
)) {
5002 /* disable TRANS_DP_CTL */
5003 reg
= TRANS_DP_CTL(pipe
);
5004 temp
= I915_READ(reg
);
5005 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5006 TRANS_DP_PORT_SEL_MASK
);
5007 temp
|= TRANS_DP_PORT_SEL_NONE
;
5008 I915_WRITE(reg
, temp
);
5010 /* disable DPLL_SEL */
5011 temp
= I915_READ(PCH_DPLL_SEL
);
5012 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5013 I915_WRITE(PCH_DPLL_SEL
, temp
);
5016 ironlake_fdi_pll_disable(intel_crtc
);
5019 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5020 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5023 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5025 struct drm_device
*dev
= crtc
->dev
;
5026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5027 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5028 struct intel_encoder
*encoder
;
5029 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5031 if (intel_crtc
->config
->has_pch_encoder
)
5032 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5035 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5036 intel_opregion_notify_encoder(encoder
, false);
5037 encoder
->disable(encoder
);
5040 drm_crtc_vblank_off(crtc
);
5041 assert_vblank_disabled(crtc
);
5043 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5044 if (!intel_crtc
->config
->has_dsi_encoder
)
5045 intel_disable_pipe(intel_crtc
);
5047 if (intel_crtc
->config
->dp_encoder_is_mst
)
5048 intel_ddi_set_vc_payload_alloc(crtc
, false);
5050 if (!intel_crtc
->config
->has_dsi_encoder
)
5051 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5053 if (INTEL_INFO(dev
)->gen
>= 9)
5054 skylake_scaler_disable(intel_crtc
);
5056 ironlake_pfit_disable(intel_crtc
, false);
5058 if (!intel_crtc
->config
->has_dsi_encoder
)
5059 intel_ddi_disable_pipe_clock(intel_crtc
);
5061 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5062 if (encoder
->post_disable
)
5063 encoder
->post_disable(encoder
);
5065 if (intel_crtc
->config
->has_pch_encoder
) {
5066 lpt_disable_pch_transcoder(dev_priv
);
5067 lpt_disable_iclkip(dev_priv
);
5068 intel_ddi_fdi_disable(crtc
);
5070 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5075 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5077 struct drm_device
*dev
= crtc
->base
.dev
;
5078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5079 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5081 if (!pipe_config
->gmch_pfit
.control
)
5085 * The panel fitter should only be adjusted whilst the pipe is disabled,
5086 * according to register description and PRM.
5088 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5089 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5091 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5092 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5094 /* Border color in case we don't scale up to the full screen. Black by
5095 * default, change to something else for debugging. */
5096 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5099 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5103 return POWER_DOMAIN_PORT_DDI_A_LANES
;
5105 return POWER_DOMAIN_PORT_DDI_B_LANES
;
5107 return POWER_DOMAIN_PORT_DDI_C_LANES
;
5109 return POWER_DOMAIN_PORT_DDI_D_LANES
;
5111 return POWER_DOMAIN_PORT_DDI_E_LANES
;
5114 return POWER_DOMAIN_PORT_OTHER
;
5118 static enum intel_display_power_domain
port_to_aux_power_domain(enum port port
)
5122 return POWER_DOMAIN_AUX_A
;
5124 return POWER_DOMAIN_AUX_B
;
5126 return POWER_DOMAIN_AUX_C
;
5128 return POWER_DOMAIN_AUX_D
;
5130 /* FIXME: Check VBT for actual wiring of PORT E */
5131 return POWER_DOMAIN_AUX_D
;
5134 return POWER_DOMAIN_AUX_A
;
5138 enum intel_display_power_domain
5139 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5141 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5142 struct intel_digital_port
*intel_dig_port
;
5144 switch (intel_encoder
->type
) {
5145 case INTEL_OUTPUT_UNKNOWN
:
5146 /* Only DDI platforms should ever use this output type */
5147 WARN_ON_ONCE(!HAS_DDI(dev
));
5148 case INTEL_OUTPUT_DISPLAYPORT
:
5149 case INTEL_OUTPUT_HDMI
:
5150 case INTEL_OUTPUT_EDP
:
5151 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5152 return port_to_power_domain(intel_dig_port
->port
);
5153 case INTEL_OUTPUT_DP_MST
:
5154 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5155 return port_to_power_domain(intel_dig_port
->port
);
5156 case INTEL_OUTPUT_ANALOG
:
5157 return POWER_DOMAIN_PORT_CRT
;
5158 case INTEL_OUTPUT_DSI
:
5159 return POWER_DOMAIN_PORT_DSI
;
5161 return POWER_DOMAIN_PORT_OTHER
;
5165 enum intel_display_power_domain
5166 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
)
5168 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5169 struct intel_digital_port
*intel_dig_port
;
5171 switch (intel_encoder
->type
) {
5172 case INTEL_OUTPUT_UNKNOWN
:
5173 case INTEL_OUTPUT_HDMI
:
5175 * Only DDI platforms should ever use these output types.
5176 * We can get here after the HDMI detect code has already set
5177 * the type of the shared encoder. Since we can't be sure
5178 * what's the status of the given connectors, play safe and
5179 * run the DP detection too.
5181 WARN_ON_ONCE(!HAS_DDI(dev
));
5182 case INTEL_OUTPUT_DISPLAYPORT
:
5183 case INTEL_OUTPUT_EDP
:
5184 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5185 return port_to_aux_power_domain(intel_dig_port
->port
);
5186 case INTEL_OUTPUT_DP_MST
:
5187 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5188 return port_to_aux_power_domain(intel_dig_port
->port
);
5190 MISSING_CASE(intel_encoder
->type
);
5191 return POWER_DOMAIN_AUX_A
;
5195 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
,
5196 struct intel_crtc_state
*crtc_state
)
5198 struct drm_device
*dev
= crtc
->dev
;
5199 struct drm_encoder
*encoder
;
5200 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5201 enum pipe pipe
= intel_crtc
->pipe
;
5203 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
5205 if (!crtc_state
->base
.active
)
5208 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5209 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5210 if (crtc_state
->pch_pfit
.enabled
||
5211 crtc_state
->pch_pfit
.force_thru
)
5212 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5214 drm_for_each_encoder_mask(encoder
, dev
, crtc_state
->base
.encoder_mask
) {
5215 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5217 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5220 if (crtc_state
->shared_dpll
)
5221 mask
|= BIT(POWER_DOMAIN_PLLS
);
5226 static unsigned long
5227 modeset_get_crtc_power_domains(struct drm_crtc
*crtc
,
5228 struct intel_crtc_state
*crtc_state
)
5230 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5231 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5232 enum intel_display_power_domain domain
;
5233 unsigned long domains
, new_domains
, old_domains
;
5235 old_domains
= intel_crtc
->enabled_power_domains
;
5236 intel_crtc
->enabled_power_domains
= new_domains
=
5237 get_crtc_power_domains(crtc
, crtc_state
);
5239 domains
= new_domains
& ~old_domains
;
5241 for_each_power_domain(domain
, domains
)
5242 intel_display_power_get(dev_priv
, domain
);
5244 return old_domains
& ~new_domains
;
5247 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
5248 unsigned long domains
)
5250 enum intel_display_power_domain domain
;
5252 for_each_power_domain(domain
, domains
)
5253 intel_display_power_put(dev_priv
, domain
);
5256 static int intel_compute_max_dotclk(struct drm_i915_private
*dev_priv
)
5258 int max_cdclk_freq
= dev_priv
->max_cdclk_freq
;
5260 if (INTEL_INFO(dev_priv
)->gen
>= 9 ||
5261 IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5262 return max_cdclk_freq
;
5263 else if (IS_CHERRYVIEW(dev_priv
))
5264 return max_cdclk_freq
*95/100;
5265 else if (INTEL_INFO(dev_priv
)->gen
< 4)
5266 return 2*max_cdclk_freq
*90/100;
5268 return max_cdclk_freq
*90/100;
5271 static void intel_update_max_cdclk(struct drm_device
*dev
)
5273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5275 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
5276 u32 limit
= I915_READ(SKL_DFSM
) & SKL_DFSM_CDCLK_LIMIT_MASK
;
5278 if (limit
== SKL_DFSM_CDCLK_LIMIT_675
)
5279 dev_priv
->max_cdclk_freq
= 675000;
5280 else if (limit
== SKL_DFSM_CDCLK_LIMIT_540
)
5281 dev_priv
->max_cdclk_freq
= 540000;
5282 else if (limit
== SKL_DFSM_CDCLK_LIMIT_450
)
5283 dev_priv
->max_cdclk_freq
= 450000;
5285 dev_priv
->max_cdclk_freq
= 337500;
5286 } else if (IS_BROXTON(dev
)) {
5287 dev_priv
->max_cdclk_freq
= 624000;
5288 } else if (IS_BROADWELL(dev
)) {
5290 * FIXME with extra cooling we can allow
5291 * 540 MHz for ULX and 675 Mhz for ULT.
5292 * How can we know if extra cooling is
5293 * available? PCI ID, VTB, something else?
5295 if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5296 dev_priv
->max_cdclk_freq
= 450000;
5297 else if (IS_BDW_ULX(dev
))
5298 dev_priv
->max_cdclk_freq
= 450000;
5299 else if (IS_BDW_ULT(dev
))
5300 dev_priv
->max_cdclk_freq
= 540000;
5302 dev_priv
->max_cdclk_freq
= 675000;
5303 } else if (IS_CHERRYVIEW(dev
)) {
5304 dev_priv
->max_cdclk_freq
= 320000;
5305 } else if (IS_VALLEYVIEW(dev
)) {
5306 dev_priv
->max_cdclk_freq
= 400000;
5308 /* otherwise assume cdclk is fixed */
5309 dev_priv
->max_cdclk_freq
= dev_priv
->cdclk_freq
;
5312 dev_priv
->max_dotclk_freq
= intel_compute_max_dotclk(dev_priv
);
5314 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5315 dev_priv
->max_cdclk_freq
);
5317 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5318 dev_priv
->max_dotclk_freq
);
5321 static void intel_update_cdclk(struct drm_device
*dev
)
5323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5325 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5326 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5327 dev_priv
->cdclk_freq
);
5330 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5331 * Programmng [sic] note: bit[9:2] should be programmed to the number
5332 * of cdclk that generates 4MHz reference clock freq which is used to
5333 * generate GMBus clock. This will vary with the cdclk freq.
5335 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5336 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5338 if (dev_priv
->max_cdclk_freq
== 0)
5339 intel_update_max_cdclk(dev
);
5342 static void broxton_set_cdclk(struct drm_i915_private
*dev_priv
, int frequency
)
5346 uint32_t current_freq
;
5349 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5350 switch (frequency
) {
5352 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5353 ratio
= BXT_DE_PLL_RATIO(60);
5356 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5357 ratio
= BXT_DE_PLL_RATIO(60);
5360 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5361 ratio
= BXT_DE_PLL_RATIO(60);
5364 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5365 ratio
= BXT_DE_PLL_RATIO(60);
5368 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5369 ratio
= BXT_DE_PLL_RATIO(65);
5373 * Bypass frequency with DE PLL disabled. Init ratio, divider
5374 * to suppress GCC warning.
5380 DRM_ERROR("unsupported CDCLK freq %d", frequency
);
5385 mutex_lock(&dev_priv
->rps
.hw_lock
);
5386 /* Inform power controller of upcoming frequency change */
5387 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5389 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5392 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5397 current_freq
= I915_READ(CDCLK_CTL
) & CDCLK_FREQ_DECIMAL_MASK
;
5398 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5399 current_freq
= current_freq
* 500 + 1000;
5402 * DE PLL has to be disabled when
5403 * - setting to 19.2MHz (bypass, PLL isn't used)
5404 * - before setting to 624MHz (PLL needs toggling)
5405 * - before setting to any frequency from 624MHz (PLL needs toggling)
5407 if (frequency
== 19200 || frequency
== 624000 ||
5408 current_freq
== 624000) {
5409 I915_WRITE(BXT_DE_PLL_ENABLE
, ~BXT_DE_PLL_PLL_ENABLE
);
5411 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
),
5413 DRM_ERROR("timout waiting for DE PLL unlock\n");
5416 if (frequency
!= 19200) {
5419 val
= I915_READ(BXT_DE_PLL_CTL
);
5420 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5422 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5424 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5426 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
, 1))
5427 DRM_ERROR("timeout waiting for DE PLL lock\n");
5429 val
= I915_READ(CDCLK_CTL
);
5430 val
&= ~BXT_CDCLK_CD2X_DIV_SEL_MASK
;
5433 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5436 val
&= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5437 if (frequency
>= 500000)
5438 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5440 val
&= ~CDCLK_FREQ_DECIMAL_MASK
;
5441 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5442 val
|= (frequency
- 1000) / 500;
5443 I915_WRITE(CDCLK_CTL
, val
);
5446 mutex_lock(&dev_priv
->rps
.hw_lock
);
5447 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5448 DIV_ROUND_UP(frequency
, 25000));
5449 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5452 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5457 intel_update_cdclk(dev_priv
->dev
);
5460 static bool broxton_cdclk_is_enabled(struct drm_i915_private
*dev_priv
)
5462 if (!(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_PLL_ENABLE
))
5465 /* TODO: Check for a valid CDCLK rate */
5467 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_REQUEST
)) {
5468 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
5473 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)) {
5474 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
5482 bool broxton_cdclk_verify_state(struct drm_i915_private
*dev_priv
)
5484 return broxton_cdclk_is_enabled(dev_priv
);
5487 void broxton_init_cdclk(struct drm_i915_private
*dev_priv
)
5489 /* check if cd clock is enabled */
5490 if (broxton_cdclk_is_enabled(dev_priv
)) {
5491 DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
5495 DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
5499 * - The initial CDCLK needs to be read from VBT.
5500 * Need to make this change after VBT has changes for BXT.
5501 * - check if setting the max (or any) cdclk freq is really necessary
5502 * here, it belongs to modeset time
5504 broxton_set_cdclk(dev_priv
, 624000);
5506 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5507 POSTING_READ(DBUF_CTL
);
5511 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5512 DRM_ERROR("DBuf power enable timeout!\n");
5515 void broxton_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5517 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5518 POSTING_READ(DBUF_CTL
);
5522 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5523 DRM_ERROR("DBuf power disable timeout!\n");
5525 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5526 broxton_set_cdclk(dev_priv
, 19200);
5529 static const struct skl_cdclk_entry
{
5532 } skl_cdclk_frequencies
[] = {
5533 { .freq
= 308570, .vco
= 8640 },
5534 { .freq
= 337500, .vco
= 8100 },
5535 { .freq
= 432000, .vco
= 8640 },
5536 { .freq
= 450000, .vco
= 8100 },
5537 { .freq
= 540000, .vco
= 8100 },
5538 { .freq
= 617140, .vco
= 8640 },
5539 { .freq
= 675000, .vco
= 8100 },
5542 static unsigned int skl_cdclk_decimal(unsigned int freq
)
5544 return (freq
- 1000) / 500;
5547 static unsigned int skl_cdclk_get_vco(unsigned int freq
)
5551 for (i
= 0; i
< ARRAY_SIZE(skl_cdclk_frequencies
); i
++) {
5552 const struct skl_cdclk_entry
*e
= &skl_cdclk_frequencies
[i
];
5554 if (e
->freq
== freq
)
5562 skl_dpll0_enable(struct drm_i915_private
*dev_priv
, unsigned int required_vco
)
5564 unsigned int min_freq
;
5567 /* select the minimum CDCLK before enabling DPLL 0 */
5568 val
= I915_READ(CDCLK_CTL
);
5569 val
&= ~CDCLK_FREQ_SEL_MASK
| ~CDCLK_FREQ_DECIMAL_MASK
;
5570 val
|= CDCLK_FREQ_337_308
;
5572 if (required_vco
== 8640)
5577 val
= CDCLK_FREQ_337_308
| skl_cdclk_decimal(min_freq
);
5579 I915_WRITE(CDCLK_CTL
, val
);
5580 POSTING_READ(CDCLK_CTL
);
5583 * We always enable DPLL0 with the lowest link rate possible, but still
5584 * taking into account the VCO required to operate the eDP panel at the
5585 * desired frequency. The usual DP link rates operate with a VCO of
5586 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5587 * The modeset code is responsible for the selection of the exact link
5588 * rate later on, with the constraint of choosing a frequency that
5589 * works with required_vco.
5591 val
= I915_READ(DPLL_CTRL1
);
5593 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
5594 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5595 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
5596 if (required_vco
== 8640)
5597 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
5600 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
5603 I915_WRITE(DPLL_CTRL1
, val
);
5604 POSTING_READ(DPLL_CTRL1
);
5606 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
5608 if (wait_for(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
, 5))
5609 DRM_ERROR("DPLL0 not locked\n");
5612 static bool skl_cdclk_pcu_ready(struct drm_i915_private
*dev_priv
)
5617 /* inform PCU we want to change CDCLK */
5618 val
= SKL_CDCLK_PREPARE_FOR_CHANGE
;
5619 mutex_lock(&dev_priv
->rps
.hw_lock
);
5620 ret
= sandybridge_pcode_read(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, &val
);
5621 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5623 return ret
== 0 && (val
& SKL_CDCLK_READY_FOR_CHANGE
);
5626 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private
*dev_priv
)
5630 for (i
= 0; i
< 15; i
++) {
5631 if (skl_cdclk_pcu_ready(dev_priv
))
5639 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
, unsigned int freq
)
5641 struct drm_device
*dev
= dev_priv
->dev
;
5642 u32 freq_select
, pcu_ack
;
5644 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq
);
5646 if (!skl_cdclk_wait_for_pcu_ready(dev_priv
)) {
5647 DRM_ERROR("failed to inform PCU about cdclk change\n");
5655 freq_select
= CDCLK_FREQ_450_432
;
5659 freq_select
= CDCLK_FREQ_540
;
5665 freq_select
= CDCLK_FREQ_337_308
;
5670 freq_select
= CDCLK_FREQ_675_617
;
5675 I915_WRITE(CDCLK_CTL
, freq_select
| skl_cdclk_decimal(freq
));
5676 POSTING_READ(CDCLK_CTL
);
5678 /* inform PCU of the change */
5679 mutex_lock(&dev_priv
->rps
.hw_lock
);
5680 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
5681 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5683 intel_update_cdclk(dev
);
5686 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5688 /* disable DBUF power */
5689 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5690 POSTING_READ(DBUF_CTL
);
5694 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5695 DRM_ERROR("DBuf power disable timeout\n");
5698 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) & ~LCPLL_PLL_ENABLE
);
5699 if (wait_for(!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
), 1))
5700 DRM_ERROR("Couldn't disable DPLL0\n");
5703 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
5705 unsigned int required_vco
;
5707 /* DPLL0 not enabled (happens on early BIOS versions) */
5708 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
)) {
5710 required_vco
= skl_cdclk_get_vco(dev_priv
->skl_boot_cdclk
);
5711 skl_dpll0_enable(dev_priv
, required_vco
);
5714 /* set CDCLK to the frequency the BIOS chose */
5715 skl_set_cdclk(dev_priv
, dev_priv
->skl_boot_cdclk
);
5717 /* enable DBUF power */
5718 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5719 POSTING_READ(DBUF_CTL
);
5723 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5724 DRM_ERROR("DBuf power enable timeout\n");
5727 int skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
5729 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
5730 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
5731 int freq
= dev_priv
->skl_boot_cdclk
;
5734 * check if the pre-os intialized the display
5735 * There is SWF18 scratchpad register defined which is set by the
5736 * pre-os which can be used by the OS drivers to check the status
5738 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5741 /* Is PLL enabled and locked ? */
5742 if (!((lcpll1
& LCPLL_PLL_ENABLE
) && (lcpll1
& LCPLL_PLL_LOCK
)))
5745 /* DPLL okay; verify the cdclock
5747 * Noticed in some instances that the freq selection is correct but
5748 * decimal part is programmed wrong from BIOS where pre-os does not
5749 * enable display. Verify the same as well.
5751 if (cdctl
== ((cdctl
& CDCLK_FREQ_SEL_MASK
) | skl_cdclk_decimal(freq
)))
5752 /* All well; nothing to sanitize */
5756 * As of now initialize with max cdclk till
5757 * we get dynamic cdclk support
5759 dev_priv
->skl_boot_cdclk
= dev_priv
->max_cdclk_freq
;
5760 skl_init_cdclk(dev_priv
);
5762 /* we did have to sanitize */
5766 /* Adjust CDclk dividers to allow high res or save power if possible */
5767 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5772 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5773 != dev_priv
->cdclk_freq
);
5775 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5777 else if (cdclk
== 266667)
5782 mutex_lock(&dev_priv
->rps
.hw_lock
);
5783 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5784 val
&= ~DSPFREQGUAR_MASK
;
5785 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5786 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5787 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5788 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5790 DRM_ERROR("timed out waiting for CDclk change\n");
5792 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5794 mutex_lock(&dev_priv
->sb_lock
);
5796 if (cdclk
== 400000) {
5799 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5801 /* adjust cdclk divider */
5802 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5803 val
&= ~CCK_FREQUENCY_VALUES
;
5805 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5807 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5808 CCK_FREQUENCY_STATUS
) == (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
5810 DRM_ERROR("timed out waiting for CDclk change\n");
5813 /* adjust self-refresh exit latency value */
5814 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5818 * For high bandwidth configs, we set a higher latency in the bunit
5819 * so that the core display fetch happens in time to avoid underruns.
5821 if (cdclk
== 400000)
5822 val
|= 4500 / 250; /* 4.5 usec */
5824 val
|= 3000 / 250; /* 3.0 usec */
5825 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5827 mutex_unlock(&dev_priv
->sb_lock
);
5829 intel_update_cdclk(dev
);
5832 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5837 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5838 != dev_priv
->cdclk_freq
);
5847 MISSING_CASE(cdclk
);
5852 * Specs are full of misinformation, but testing on actual
5853 * hardware has shown that we just need to write the desired
5854 * CCK divider into the Punit register.
5856 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5858 mutex_lock(&dev_priv
->rps
.hw_lock
);
5859 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5860 val
&= ~DSPFREQGUAR_MASK_CHV
;
5861 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5862 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5863 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5864 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5866 DRM_ERROR("timed out waiting for CDclk change\n");
5868 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5870 intel_update_cdclk(dev
);
5873 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5876 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5877 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5880 * Really only a few cases to deal with, as only 4 CDclks are supported:
5883 * 320/333MHz (depends on HPLL freq)
5885 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5886 * of the lower bin and adjust if needed.
5888 * We seem to get an unstable or solid color picture at 200MHz.
5889 * Not sure what's wrong. For now use 200MHz only when all pipes
5892 if (!IS_CHERRYVIEW(dev_priv
) &&
5893 max_pixclk
> freq_320
*limit
/100)
5895 else if (max_pixclk
> 266667*limit
/100)
5897 else if (max_pixclk
> 0)
5903 static int broxton_calc_cdclk(struct drm_i915_private
*dev_priv
,
5908 * - remove the guardband, it's not needed on BXT
5909 * - set 19.2MHz bypass frequency if there are no active pipes
5911 if (max_pixclk
> 576000*9/10)
5913 else if (max_pixclk
> 384000*9/10)
5915 else if (max_pixclk
> 288000*9/10)
5917 else if (max_pixclk
> 144000*9/10)
5923 /* Compute the max pixel clock for new configuration. */
5924 static int intel_mode_max_pixclk(struct drm_device
*dev
,
5925 struct drm_atomic_state
*state
)
5927 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
5928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5929 struct drm_crtc
*crtc
;
5930 struct drm_crtc_state
*crtc_state
;
5931 unsigned max_pixclk
= 0, i
;
5934 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
5935 sizeof(intel_state
->min_pixclk
));
5937 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5940 if (crtc_state
->enable
)
5941 pixclk
= crtc_state
->adjusted_mode
.crtc_clock
;
5943 intel_state
->min_pixclk
[i
] = pixclk
;
5946 for_each_pipe(dev_priv
, pipe
)
5947 max_pixclk
= max(intel_state
->min_pixclk
[pipe
], max_pixclk
);
5952 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state
*state
)
5954 struct drm_device
*dev
= state
->dev
;
5955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5956 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
5957 struct intel_atomic_state
*intel_state
=
5958 to_intel_atomic_state(state
);
5963 intel_state
->cdclk
= intel_state
->dev_cdclk
=
5964 valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5966 if (!intel_state
->active_crtcs
)
5967 intel_state
->dev_cdclk
= valleyview_calc_cdclk(dev_priv
, 0);
5972 static int broxton_modeset_calc_cdclk(struct drm_atomic_state
*state
)
5974 struct drm_device
*dev
= state
->dev
;
5975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5976 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
5977 struct intel_atomic_state
*intel_state
=
5978 to_intel_atomic_state(state
);
5983 intel_state
->cdclk
= intel_state
->dev_cdclk
=
5984 broxton_calc_cdclk(dev_priv
, max_pixclk
);
5986 if (!intel_state
->active_crtcs
)
5987 intel_state
->dev_cdclk
= broxton_calc_cdclk(dev_priv
, 0);
5992 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
5994 unsigned int credits
, default_credits
;
5996 if (IS_CHERRYVIEW(dev_priv
))
5997 default_credits
= PFI_CREDIT(12);
5999 default_credits
= PFI_CREDIT(8);
6001 if (dev_priv
->cdclk_freq
>= dev_priv
->czclk_freq
) {
6002 /* CHV suggested value is 31 or 63 */
6003 if (IS_CHERRYVIEW(dev_priv
))
6004 credits
= PFI_CREDIT_63
;
6006 credits
= PFI_CREDIT(15);
6008 credits
= default_credits
;
6012 * WA - write default credits before re-programming
6013 * FIXME: should we also set the resend bit here?
6015 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6018 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6019 credits
| PFI_CREDIT_RESEND
);
6022 * FIXME is this guaranteed to clear
6023 * immediately or should we poll for it?
6025 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
6028 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
6030 struct drm_device
*dev
= old_state
->dev
;
6031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6032 struct intel_atomic_state
*old_intel_state
=
6033 to_intel_atomic_state(old_state
);
6034 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
6037 * FIXME: We can end up here with all power domains off, yet
6038 * with a CDCLK frequency other than the minimum. To account
6039 * for this take the PIPE-A power domain, which covers the HW
6040 * blocks needed for the following programming. This can be
6041 * removed once it's guaranteed that we get here either with
6042 * the minimum CDCLK set, or the required power domains
6045 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
6047 if (IS_CHERRYVIEW(dev
))
6048 cherryview_set_cdclk(dev
, req_cdclk
);
6050 valleyview_set_cdclk(dev
, req_cdclk
);
6052 vlv_program_pfi_credits(dev_priv
);
6054 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
6057 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
6059 struct drm_device
*dev
= crtc
->dev
;
6060 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6061 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6062 struct intel_encoder
*encoder
;
6063 struct intel_crtc_state
*pipe_config
=
6064 to_intel_crtc_state(crtc
->state
);
6065 int pipe
= intel_crtc
->pipe
;
6067 if (WARN_ON(intel_crtc
->active
))
6070 if (intel_crtc
->config
->has_dp_encoder
)
6071 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6073 intel_set_pipe_timings(intel_crtc
);
6074 intel_set_pipe_src_size(intel_crtc
);
6076 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
6077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6079 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6080 I915_WRITE(CHV_CANVAS(pipe
), 0);
6083 i9xx_set_pipeconf(intel_crtc
);
6085 intel_crtc
->active
= true;
6087 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6089 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6090 if (encoder
->pre_pll_enable
)
6091 encoder
->pre_pll_enable(encoder
);
6093 if (IS_CHERRYVIEW(dev
)) {
6094 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6095 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
6097 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6098 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
6101 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6102 if (encoder
->pre_enable
)
6103 encoder
->pre_enable(encoder
);
6105 i9xx_pfit_enable(intel_crtc
);
6107 intel_color_load_luts(&pipe_config
->base
);
6109 intel_update_watermarks(crtc
);
6110 intel_enable_pipe(intel_crtc
);
6112 assert_vblank_disabled(crtc
);
6113 drm_crtc_vblank_on(crtc
);
6115 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6116 encoder
->enable(encoder
);
6119 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
6121 struct drm_device
*dev
= crtc
->base
.dev
;
6122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6124 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
6125 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
6128 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
6130 struct drm_device
*dev
= crtc
->dev
;
6131 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6132 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6133 struct intel_encoder
*encoder
;
6134 struct intel_crtc_state
*pipe_config
=
6135 to_intel_crtc_state(crtc
->state
);
6136 enum pipe pipe
= intel_crtc
->pipe
;
6138 if (WARN_ON(intel_crtc
->active
))
6141 i9xx_set_pll_dividers(intel_crtc
);
6143 if (intel_crtc
->config
->has_dp_encoder
)
6144 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6146 intel_set_pipe_timings(intel_crtc
);
6147 intel_set_pipe_src_size(intel_crtc
);
6149 i9xx_set_pipeconf(intel_crtc
);
6151 intel_crtc
->active
= true;
6154 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6156 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6157 if (encoder
->pre_enable
)
6158 encoder
->pre_enable(encoder
);
6160 i9xx_enable_pll(intel_crtc
);
6162 i9xx_pfit_enable(intel_crtc
);
6164 intel_color_load_luts(&pipe_config
->base
);
6166 intel_update_watermarks(crtc
);
6167 intel_enable_pipe(intel_crtc
);
6169 assert_vblank_disabled(crtc
);
6170 drm_crtc_vblank_on(crtc
);
6172 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6173 encoder
->enable(encoder
);
6176 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6178 struct drm_device
*dev
= crtc
->base
.dev
;
6179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6181 if (!crtc
->config
->gmch_pfit
.control
)
6184 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6186 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6187 I915_READ(PFIT_CONTROL
));
6188 I915_WRITE(PFIT_CONTROL
, 0);
6191 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6193 struct drm_device
*dev
= crtc
->dev
;
6194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6195 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6196 struct intel_encoder
*encoder
;
6197 int pipe
= intel_crtc
->pipe
;
6200 * On gen2 planes are double buffered but the pipe isn't, so we must
6201 * wait for planes to fully turn off before disabling the pipe.
6204 intel_wait_for_vblank(dev
, pipe
);
6206 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6207 encoder
->disable(encoder
);
6209 drm_crtc_vblank_off(crtc
);
6210 assert_vblank_disabled(crtc
);
6212 intel_disable_pipe(intel_crtc
);
6214 i9xx_pfit_disable(intel_crtc
);
6216 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6217 if (encoder
->post_disable
)
6218 encoder
->post_disable(encoder
);
6220 if (!intel_crtc
->config
->has_dsi_encoder
) {
6221 if (IS_CHERRYVIEW(dev
))
6222 chv_disable_pll(dev_priv
, pipe
);
6223 else if (IS_VALLEYVIEW(dev
))
6224 vlv_disable_pll(dev_priv
, pipe
);
6226 i9xx_disable_pll(intel_crtc
);
6229 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6230 if (encoder
->post_pll_disable
)
6231 encoder
->post_pll_disable(encoder
);
6234 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6237 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
)
6239 struct intel_encoder
*encoder
;
6240 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6241 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6242 enum intel_display_power_domain domain
;
6243 unsigned long domains
;
6245 if (!intel_crtc
->active
)
6248 if (to_intel_plane_state(crtc
->primary
->state
)->visible
) {
6249 WARN_ON(intel_crtc
->unpin_work
);
6251 intel_pre_disable_primary_noatomic(crtc
);
6253 intel_crtc_disable_planes(crtc
, 1 << drm_plane_index(crtc
->primary
));
6254 to_intel_plane_state(crtc
->primary
->state
)->visible
= false;
6257 dev_priv
->display
.crtc_disable(crtc
);
6259 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6262 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->state
, NULL
) < 0);
6263 crtc
->state
->active
= false;
6264 intel_crtc
->active
= false;
6265 crtc
->enabled
= false;
6266 crtc
->state
->connector_mask
= 0;
6267 crtc
->state
->encoder_mask
= 0;
6269 for_each_encoder_on_crtc(crtc
->dev
, crtc
, encoder
)
6270 encoder
->base
.crtc
= NULL
;
6272 intel_fbc_disable(intel_crtc
);
6273 intel_update_watermarks(crtc
);
6274 intel_disable_shared_dpll(intel_crtc
);
6276 domains
= intel_crtc
->enabled_power_domains
;
6277 for_each_power_domain(domain
, domains
)
6278 intel_display_power_put(dev_priv
, domain
);
6279 intel_crtc
->enabled_power_domains
= 0;
6281 dev_priv
->active_crtcs
&= ~(1 << intel_crtc
->pipe
);
6282 dev_priv
->min_pixclk
[intel_crtc
->pipe
] = 0;
6286 * turn all crtc's off, but do not adjust state
6287 * This has to be paired with a call to intel_modeset_setup_hw_state.
6289 int intel_display_suspend(struct drm_device
*dev
)
6291 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6292 struct drm_atomic_state
*state
;
6295 state
= drm_atomic_helper_suspend(dev
);
6296 ret
= PTR_ERR_OR_ZERO(state
);
6298 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6300 dev_priv
->modeset_restore_state
= state
;
6304 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6306 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6308 drm_encoder_cleanup(encoder
);
6309 kfree(intel_encoder
);
6312 /* Cross check the actual hw state with our own modeset state tracking (and it's
6313 * internal consistency). */
6314 static void intel_connector_verify_state(struct intel_connector
*connector
)
6316 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
6318 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6319 connector
->base
.base
.id
,
6320 connector
->base
.name
);
6322 if (connector
->get_hw_state(connector
)) {
6323 struct intel_encoder
*encoder
= connector
->encoder
;
6324 struct drm_connector_state
*conn_state
= connector
->base
.state
;
6326 I915_STATE_WARN(!crtc
,
6327 "connector enabled without attached crtc\n");
6332 I915_STATE_WARN(!crtc
->state
->active
,
6333 "connector is active, but attached crtc isn't\n");
6335 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
6338 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
6339 "atomic encoder doesn't match attached encoder\n");
6341 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
6342 "attached encoder crtc differs from connector crtc\n");
6344 I915_STATE_WARN(crtc
&& crtc
->state
->active
,
6345 "attached crtc is active, but connector isn't\n");
6346 I915_STATE_WARN(!crtc
&& connector
->base
.state
->best_encoder
,
6347 "best encoder set without crtc!\n");
6351 int intel_connector_init(struct intel_connector
*connector
)
6353 drm_atomic_helper_connector_reset(&connector
->base
);
6355 if (!connector
->base
.state
)
6361 struct intel_connector
*intel_connector_alloc(void)
6363 struct intel_connector
*connector
;
6365 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6369 if (intel_connector_init(connector
) < 0) {
6377 /* Simple connector->get_hw_state implementation for encoders that support only
6378 * one connector and no cloning and hence the encoder state determines the state
6379 * of the connector. */
6380 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6383 struct intel_encoder
*encoder
= connector
->encoder
;
6385 return encoder
->get_hw_state(encoder
, &pipe
);
6388 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6390 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6391 return crtc_state
->fdi_lanes
;
6396 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6397 struct intel_crtc_state
*pipe_config
)
6399 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6400 struct intel_crtc
*other_crtc
;
6401 struct intel_crtc_state
*other_crtc_state
;
6403 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6404 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6405 if (pipe_config
->fdi_lanes
> 4) {
6406 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6407 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6411 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6412 if (pipe_config
->fdi_lanes
> 2) {
6413 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6414 pipe_config
->fdi_lanes
);
6421 if (INTEL_INFO(dev
)->num_pipes
== 2)
6424 /* Ivybridge 3 pipe is really complicated */
6429 if (pipe_config
->fdi_lanes
<= 2)
6432 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6434 intel_atomic_get_crtc_state(state
, other_crtc
);
6435 if (IS_ERR(other_crtc_state
))
6436 return PTR_ERR(other_crtc_state
);
6438 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6439 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6440 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6445 if (pipe_config
->fdi_lanes
> 2) {
6446 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6447 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6451 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6453 intel_atomic_get_crtc_state(state
, other_crtc
);
6454 if (IS_ERR(other_crtc_state
))
6455 return PTR_ERR(other_crtc_state
);
6457 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6458 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6468 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6469 struct intel_crtc_state
*pipe_config
)
6471 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6472 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6473 int lane
, link_bw
, fdi_dotclock
, ret
;
6474 bool needs_recompute
= false;
6477 /* FDI is a binary signal running at ~2.7GHz, encoding
6478 * each output octet as 10 bits. The actual frequency
6479 * is stored as a divider into a 100MHz clock, and the
6480 * mode pixel clock is stored in units of 1KHz.
6481 * Hence the bw of each lane in terms of the mode signal
6484 link_bw
= intel_fdi_link_freq(to_i915(dev
), pipe_config
);
6486 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6488 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6489 pipe_config
->pipe_bpp
);
6491 pipe_config
->fdi_lanes
= lane
;
6493 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6494 link_bw
, &pipe_config
->fdi_m_n
);
6496 ret
= ironlake_check_fdi_lanes(dev
, intel_crtc
->pipe
, pipe_config
);
6497 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6498 pipe_config
->pipe_bpp
-= 2*3;
6499 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6500 pipe_config
->pipe_bpp
);
6501 needs_recompute
= true;
6502 pipe_config
->bw_constrained
= true;
6507 if (needs_recompute
)
6513 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
6514 struct intel_crtc_state
*pipe_config
)
6516 if (pipe_config
->pipe_bpp
> 24)
6519 /* HSW can handle pixel rate up to cdclk? */
6520 if (IS_HASWELL(dev_priv
))
6524 * We compare against max which means we must take
6525 * the increased cdclk requirement into account when
6526 * calculating the new cdclk.
6528 * Should measure whether using a lower cdclk w/o IPS
6530 return ilk_pipe_pixel_rate(pipe_config
) <=
6531 dev_priv
->max_cdclk_freq
* 95 / 100;
6534 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6535 struct intel_crtc_state
*pipe_config
)
6537 struct drm_device
*dev
= crtc
->base
.dev
;
6538 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6540 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6541 hsw_crtc_supports_ips(crtc
) &&
6542 pipe_config_supports_ips(dev_priv
, pipe_config
);
6545 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
6547 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6549 /* GDG double wide on either pipe, otherwise pipe A only */
6550 return INTEL_INFO(dev_priv
)->gen
< 4 &&
6551 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
6554 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6555 struct intel_crtc_state
*pipe_config
)
6557 struct drm_device
*dev
= crtc
->base
.dev
;
6558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6559 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6561 /* FIXME should check pixel clock limits on all platforms */
6562 if (INTEL_INFO(dev
)->gen
< 4) {
6563 int clock_limit
= dev_priv
->max_cdclk_freq
* 9 / 10;
6566 * Enable double wide mode when the dot clock
6567 * is > 90% of the (display) core speed.
6569 if (intel_crtc_supports_double_wide(crtc
) &&
6570 adjusted_mode
->crtc_clock
> clock_limit
) {
6572 pipe_config
->double_wide
= true;
6575 if (adjusted_mode
->crtc_clock
> clock_limit
) {
6576 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6577 adjusted_mode
->crtc_clock
, clock_limit
,
6578 yesno(pipe_config
->double_wide
));
6584 * Pipe horizontal size must be even in:
6586 * - LVDS dual channel mode
6587 * - Double wide pipe
6589 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6590 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6591 pipe_config
->pipe_src_w
&= ~1;
6593 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6594 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6596 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6597 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
6601 hsw_compute_ips_config(crtc
, pipe_config
);
6603 if (pipe_config
->has_pch_encoder
)
6604 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6609 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6611 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6612 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
6613 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6616 if (!(lcpll1
& LCPLL_PLL_ENABLE
))
6617 return 24000; /* 24MHz is the cd freq with NSSC ref */
6619 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
6622 linkrate
= (I915_READ(DPLL_CTRL1
) &
6623 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
6625 if (linkrate
== DPLL_CTRL1_LINK_RATE_2160
||
6626 linkrate
== DPLL_CTRL1_LINK_RATE_1080
) {
6628 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6629 case CDCLK_FREQ_450_432
:
6631 case CDCLK_FREQ_337_308
:
6633 case CDCLK_FREQ_675_617
:
6636 WARN(1, "Unknown cd freq selection\n");
6640 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6641 case CDCLK_FREQ_450_432
:
6643 case CDCLK_FREQ_337_308
:
6645 case CDCLK_FREQ_675_617
:
6648 WARN(1, "Unknown cd freq selection\n");
6652 /* error case, do as if DPLL0 isn't enabled */
6656 static int broxton_get_display_clock_speed(struct drm_device
*dev
)
6658 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6659 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6660 uint32_t pll_ratio
= I915_READ(BXT_DE_PLL_CTL
) & BXT_DE_PLL_RATIO_MASK
;
6661 uint32_t pll_enab
= I915_READ(BXT_DE_PLL_ENABLE
);
6664 if (!(pll_enab
& BXT_DE_PLL_PLL_ENABLE
))
6667 cdclk
= 19200 * pll_ratio
/ 2;
6669 switch (cdctl
& BXT_CDCLK_CD2X_DIV_SEL_MASK
) {
6670 case BXT_CDCLK_CD2X_DIV_SEL_1
:
6671 return cdclk
; /* 576MHz or 624MHz */
6672 case BXT_CDCLK_CD2X_DIV_SEL_1_5
:
6673 return cdclk
* 2 / 3; /* 384MHz */
6674 case BXT_CDCLK_CD2X_DIV_SEL_2
:
6675 return cdclk
/ 2; /* 288MHz */
6676 case BXT_CDCLK_CD2X_DIV_SEL_4
:
6677 return cdclk
/ 4; /* 144MHz */
6680 /* error case, do as if DE PLL isn't enabled */
6684 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6687 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6688 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6690 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6692 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6694 else if (freq
== LCPLL_CLK_FREQ_450
)
6696 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6698 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6704 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6707 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6708 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6710 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6712 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6714 else if (freq
== LCPLL_CLK_FREQ_450
)
6716 else if (IS_HSW_ULT(dev
))
6722 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6724 return vlv_get_cck_clock_hpll(to_i915(dev
), "cdclk",
6725 CCK_DISPLAY_CLOCK_CONTROL
);
6728 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6733 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6738 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6743 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6748 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6752 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6754 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6755 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6757 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6759 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6761 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6764 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6765 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6767 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6772 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6776 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6778 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6781 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6782 case GC_DISPLAY_CLOCK_333_MHZ
:
6785 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6791 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6796 static int i85x_get_display_clock_speed(struct drm_device
*dev
)
6801 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6802 * encoding is different :(
6803 * FIXME is this the right way to detect 852GM/852GMV?
6805 if (dev
->pdev
->revision
== 0x1)
6808 pci_bus_read_config_word(dev
->pdev
->bus
,
6809 PCI_DEVFN(0, 3), HPLLCC
, &hpllcc
);
6811 /* Assume that the hardware is in the high speed state. This
6812 * should be the default.
6814 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6815 case GC_CLOCK_133_200
:
6816 case GC_CLOCK_133_200_2
:
6817 case GC_CLOCK_100_200
:
6819 case GC_CLOCK_166_250
:
6821 case GC_CLOCK_100_133
:
6823 case GC_CLOCK_133_266
:
6824 case GC_CLOCK_133_266_2
:
6825 case GC_CLOCK_166_266
:
6829 /* Shouldn't happen */
6833 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6838 static unsigned int intel_hpll_vco(struct drm_device
*dev
)
6840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6841 static const unsigned int blb_vco
[8] = {
6848 static const unsigned int pnv_vco
[8] = {
6855 static const unsigned int cl_vco
[8] = {
6864 static const unsigned int elk_vco
[8] = {
6870 static const unsigned int ctg_vco
[8] = {
6878 const unsigned int *vco_table
;
6882 /* FIXME other chipsets? */
6884 vco_table
= ctg_vco
;
6885 else if (IS_G4X(dev
))
6886 vco_table
= elk_vco
;
6887 else if (IS_CRESTLINE(dev
))
6889 else if (IS_PINEVIEW(dev
))
6890 vco_table
= pnv_vco
;
6891 else if (IS_G33(dev
))
6892 vco_table
= blb_vco
;
6896 tmp
= I915_READ(IS_MOBILE(dev
) ? HPLLVCO_MOBILE
: HPLLVCO
);
6898 vco
= vco_table
[tmp
& 0x7];
6900 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp
);
6902 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco
);
6907 static int gm45_get_display_clock_speed(struct drm_device
*dev
)
6909 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6912 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6914 cdclk_sel
= (tmp
>> 12) & 0x1;
6920 return cdclk_sel
? 333333 : 222222;
6922 return cdclk_sel
? 320000 : 228571;
6924 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco
, tmp
);
6929 static int i965gm_get_display_clock_speed(struct drm_device
*dev
)
6931 static const uint8_t div_3200
[] = { 16, 10, 8 };
6932 static const uint8_t div_4000
[] = { 20, 12, 10 };
6933 static const uint8_t div_5333
[] = { 24, 16, 14 };
6934 const uint8_t *div_table
;
6935 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6938 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6940 cdclk_sel
= ((tmp
>> 8) & 0x1f) - 1;
6942 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
6947 div_table
= div_3200
;
6950 div_table
= div_4000
;
6953 div_table
= div_5333
;
6959 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
6962 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco
, tmp
);
6966 static int g33_get_display_clock_speed(struct drm_device
*dev
)
6968 static const uint8_t div_3200
[] = { 12, 10, 8, 7, 5, 16 };
6969 static const uint8_t div_4000
[] = { 14, 12, 10, 8, 6, 20 };
6970 static const uint8_t div_4800
[] = { 20, 14, 12, 10, 8, 24 };
6971 static const uint8_t div_5333
[] = { 20, 16, 12, 12, 8, 28 };
6972 const uint8_t *div_table
;
6973 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6976 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6978 cdclk_sel
= (tmp
>> 4) & 0x7;
6980 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
6985 div_table
= div_3200
;
6988 div_table
= div_4000
;
6991 div_table
= div_4800
;
6994 div_table
= div_5333
;
7000 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7003 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco
, tmp
);
7008 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
7010 while (*num
> DATA_LINK_M_N_MASK
||
7011 *den
> DATA_LINK_M_N_MASK
) {
7017 static void compute_m_n(unsigned int m
, unsigned int n
,
7018 uint32_t *ret_m
, uint32_t *ret_n
)
7020 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7021 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
7022 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7026 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
7027 int pixel_clock
, int link_clock
,
7028 struct intel_link_m_n
*m_n
)
7032 compute_m_n(bits_per_pixel
* pixel_clock
,
7033 link_clock
* nlanes
* 8,
7034 &m_n
->gmch_m
, &m_n
->gmch_n
);
7036 compute_m_n(pixel_clock
, link_clock
,
7037 &m_n
->link_m
, &m_n
->link_n
);
7040 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7042 if (i915
.panel_use_ssc
>= 0)
7043 return i915
.panel_use_ssc
!= 0;
7044 return dev_priv
->vbt
.lvds_use_ssc
7045 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7048 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
7050 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7053 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
7055 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7058 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7059 struct intel_crtc_state
*crtc_state
,
7060 intel_clock_t
*reduced_clock
)
7062 struct drm_device
*dev
= crtc
->base
.dev
;
7065 if (IS_PINEVIEW(dev
)) {
7066 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7068 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7070 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7072 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7075 crtc_state
->dpll_hw_state
.fp0
= fp
;
7077 crtc
->lowfreq_avail
= false;
7078 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7080 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7081 crtc
->lowfreq_avail
= true;
7083 crtc_state
->dpll_hw_state
.fp1
= fp
;
7087 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7093 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7094 * and set it to a reasonable value instead.
7096 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7097 reg_val
&= 0xffffff00;
7098 reg_val
|= 0x00000030;
7099 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7101 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7102 reg_val
&= 0x8cffffff;
7103 reg_val
= 0x8c000000;
7104 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7106 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7107 reg_val
&= 0xffffff00;
7108 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7110 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7111 reg_val
&= 0x00ffffff;
7112 reg_val
|= 0xb0000000;
7113 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7116 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
7117 struct intel_link_m_n
*m_n
)
7119 struct drm_device
*dev
= crtc
->base
.dev
;
7120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7121 int pipe
= crtc
->pipe
;
7123 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7124 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7125 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7126 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7129 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
7130 struct intel_link_m_n
*m_n
,
7131 struct intel_link_m_n
*m2_n2
)
7133 struct drm_device
*dev
= crtc
->base
.dev
;
7134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7135 int pipe
= crtc
->pipe
;
7136 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
7138 if (INTEL_INFO(dev
)->gen
>= 5) {
7139 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7140 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7141 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7142 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7143 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7144 * for gen < 8) and if DRRS is supported (to make sure the
7145 * registers are not unnecessarily accessed).
7147 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
7148 crtc
->config
->has_drrs
) {
7149 I915_WRITE(PIPE_DATA_M2(transcoder
),
7150 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7151 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7152 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7153 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7156 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7157 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7158 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7159 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7163 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
7165 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7168 dp_m_n
= &crtc
->config
->dp_m_n
;
7169 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
7170 } else if (m_n
== M2_N2
) {
7173 * M2_N2 registers are not supported. Hence m2_n2 divider value
7174 * needs to be programmed into M1_N1.
7176 dp_m_n
= &crtc
->config
->dp_m2_n2
;
7178 DRM_ERROR("Unsupported divider value\n");
7182 if (crtc
->config
->has_pch_encoder
)
7183 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
7185 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
7188 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7189 struct intel_crtc_state
*pipe_config
)
7191 pipe_config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
7192 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7193 if (crtc
->pipe
!= PIPE_A
)
7194 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7196 /* DPLL not used with DSI, but still need the rest set up */
7197 if (!pipe_config
->has_dsi_encoder
)
7198 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
|
7199 DPLL_EXT_BUFFER_ENABLE_VLV
;
7201 pipe_config
->dpll_hw_state
.dpll_md
=
7202 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7205 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7206 struct intel_crtc_state
*pipe_config
)
7208 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7209 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7210 if (crtc
->pipe
!= PIPE_A
)
7211 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7213 /* DPLL not used with DSI, but still need the rest set up */
7214 if (!pipe_config
->has_dsi_encoder
)
7215 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
;
7217 pipe_config
->dpll_hw_state
.dpll_md
=
7218 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7221 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7222 const struct intel_crtc_state
*pipe_config
)
7224 struct drm_device
*dev
= crtc
->base
.dev
;
7225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7226 enum pipe pipe
= crtc
->pipe
;
7228 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7229 u32 coreclk
, reg_val
;
7232 I915_WRITE(DPLL(pipe
),
7233 pipe_config
->dpll_hw_state
.dpll
&
7234 ~(DPLL_VCO_ENABLE
| DPLL_EXT_BUFFER_ENABLE_VLV
));
7236 /* No need to actually set up the DPLL with DSI */
7237 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7240 mutex_lock(&dev_priv
->sb_lock
);
7242 bestn
= pipe_config
->dpll
.n
;
7243 bestm1
= pipe_config
->dpll
.m1
;
7244 bestm2
= pipe_config
->dpll
.m2
;
7245 bestp1
= pipe_config
->dpll
.p1
;
7246 bestp2
= pipe_config
->dpll
.p2
;
7248 /* See eDP HDMI DPIO driver vbios notes doc */
7250 /* PLL B needs special handling */
7252 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7254 /* Set up Tx target for periodic Rcomp update */
7255 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7257 /* Disable target IRef on PLL */
7258 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7259 reg_val
&= 0x00ffffff;
7260 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7262 /* Disable fast lock */
7263 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7265 /* Set idtafcrecal before PLL is enabled */
7266 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7267 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7268 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7269 mdiv
|= (1 << DPIO_K_SHIFT
);
7272 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7273 * but we don't support that).
7274 * Note: don't use the DAC post divider as it seems unstable.
7276 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7277 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7279 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7280 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7282 /* Set HBR and RBR LPF coefficients */
7283 if (pipe_config
->port_clock
== 162000 ||
7284 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
7285 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
7286 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7289 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7292 if (pipe_config
->has_dp_encoder
) {
7293 /* Use SSC source */
7295 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7298 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7300 } else { /* HDMI or VGA */
7301 /* Use bend source */
7303 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7306 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7310 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7311 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7312 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
7313 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
7314 coreclk
|= 0x01000000;
7315 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7317 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7318 mutex_unlock(&dev_priv
->sb_lock
);
7321 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7322 const struct intel_crtc_state
*pipe_config
)
7324 struct drm_device
*dev
= crtc
->base
.dev
;
7325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7326 enum pipe pipe
= crtc
->pipe
;
7327 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7328 u32 loopfilter
, tribuf_calcntr
;
7329 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7333 /* Enable Refclk and SSC */
7334 I915_WRITE(DPLL(pipe
),
7335 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7337 /* No need to actually set up the DPLL with DSI */
7338 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7341 bestn
= pipe_config
->dpll
.n
;
7342 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7343 bestm1
= pipe_config
->dpll
.m1
;
7344 bestm2
= pipe_config
->dpll
.m2
>> 22;
7345 bestp1
= pipe_config
->dpll
.p1
;
7346 bestp2
= pipe_config
->dpll
.p2
;
7347 vco
= pipe_config
->dpll
.vco
;
7351 mutex_lock(&dev_priv
->sb_lock
);
7353 /* p1 and p2 divider */
7354 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7355 5 << DPIO_CHV_S1_DIV_SHIFT
|
7356 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7357 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7358 1 << DPIO_CHV_K_DIV_SHIFT
);
7360 /* Feedback post-divider - m2 */
7361 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7363 /* Feedback refclk divider - n and m1 */
7364 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7365 DPIO_CHV_M1_DIV_BY_2
|
7366 1 << DPIO_CHV_N_DIV_SHIFT
);
7368 /* M2 fraction division */
7369 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7371 /* M2 fraction division enable */
7372 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7373 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7374 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7376 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7377 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7379 /* Program digital lock detect threshold */
7380 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7381 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7382 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7383 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7385 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7386 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7389 if (vco
== 5400000) {
7390 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7391 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7392 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7393 tribuf_calcntr
= 0x9;
7394 } else if (vco
<= 6200000) {
7395 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7396 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7397 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7398 tribuf_calcntr
= 0x9;
7399 } else if (vco
<= 6480000) {
7400 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7401 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7402 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7403 tribuf_calcntr
= 0x8;
7405 /* Not supported. Apply the same limits as in the max case */
7406 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7407 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7408 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7411 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7413 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7414 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7415 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7416 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7419 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7420 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7423 mutex_unlock(&dev_priv
->sb_lock
);
7427 * vlv_force_pll_on - forcibly enable just the PLL
7428 * @dev_priv: i915 private structure
7429 * @pipe: pipe PLL to enable
7430 * @dpll: PLL configuration
7432 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7433 * in cases where we need the PLL enabled even when @pipe is not going to
7436 int vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7437 const struct dpll
*dpll
)
7439 struct intel_crtc
*crtc
=
7440 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7441 struct intel_crtc_state
*pipe_config
;
7443 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7447 pipe_config
->base
.crtc
= &crtc
->base
;
7448 pipe_config
->pixel_multiplier
= 1;
7449 pipe_config
->dpll
= *dpll
;
7451 if (IS_CHERRYVIEW(dev
)) {
7452 chv_compute_dpll(crtc
, pipe_config
);
7453 chv_prepare_pll(crtc
, pipe_config
);
7454 chv_enable_pll(crtc
, pipe_config
);
7456 vlv_compute_dpll(crtc
, pipe_config
);
7457 vlv_prepare_pll(crtc
, pipe_config
);
7458 vlv_enable_pll(crtc
, pipe_config
);
7467 * vlv_force_pll_off - forcibly disable just the PLL
7468 * @dev_priv: i915 private structure
7469 * @pipe: pipe PLL to disable
7471 * Disable the PLL for @pipe. To be used in cases where we need
7472 * the PLL enabled even when @pipe is not going to be enabled.
7474 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7476 if (IS_CHERRYVIEW(dev
))
7477 chv_disable_pll(to_i915(dev
), pipe
);
7479 vlv_disable_pll(to_i915(dev
), pipe
);
7482 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
7483 struct intel_crtc_state
*crtc_state
,
7484 intel_clock_t
*reduced_clock
)
7486 struct drm_device
*dev
= crtc
->base
.dev
;
7487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7490 struct dpll
*clock
= &crtc_state
->dpll
;
7492 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7494 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7495 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
7497 dpll
= DPLL_VGA_MODE_DIS
;
7499 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7500 dpll
|= DPLLB_MODE_LVDS
;
7502 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7504 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7505 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7506 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7510 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7512 if (crtc_state
->has_dp_encoder
)
7513 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7515 /* compute bitmask from p1 value */
7516 if (IS_PINEVIEW(dev
))
7517 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7519 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7520 if (IS_G4X(dev
) && reduced_clock
)
7521 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7523 switch (clock
->p2
) {
7525 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7528 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7531 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7534 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7537 if (INTEL_INFO(dev
)->gen
>= 4)
7538 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7540 if (crtc_state
->sdvo_tv_clock
)
7541 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7542 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7543 intel_panel_use_ssc(dev_priv
))
7544 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7546 dpll
|= PLL_REF_INPUT_DREFCLK
;
7548 dpll
|= DPLL_VCO_ENABLE
;
7549 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7551 if (INTEL_INFO(dev
)->gen
>= 4) {
7552 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7553 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7554 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7558 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
7559 struct intel_crtc_state
*crtc_state
,
7560 intel_clock_t
*reduced_clock
)
7562 struct drm_device
*dev
= crtc
->base
.dev
;
7563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7565 struct dpll
*clock
= &crtc_state
->dpll
;
7567 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7569 dpll
= DPLL_VGA_MODE_DIS
;
7571 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7572 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7575 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7577 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7579 dpll
|= PLL_P2_DIVIDE_BY_4
;
7582 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
7583 dpll
|= DPLL_DVO_2X_MODE
;
7585 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7586 intel_panel_use_ssc(dev_priv
))
7587 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7589 dpll
|= PLL_REF_INPUT_DREFCLK
;
7591 dpll
|= DPLL_VCO_ENABLE
;
7592 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7595 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7597 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7599 enum pipe pipe
= intel_crtc
->pipe
;
7600 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7601 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
7602 uint32_t crtc_vtotal
, crtc_vblank_end
;
7605 /* We need to be careful not to changed the adjusted mode, for otherwise
7606 * the hw state checker will get angry at the mismatch. */
7607 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7608 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7610 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7611 /* the chip adds 2 halflines automatically */
7613 crtc_vblank_end
-= 1;
7615 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7616 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7618 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7619 adjusted_mode
->crtc_htotal
/ 2;
7621 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7624 if (INTEL_INFO(dev
)->gen
> 3)
7625 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7627 I915_WRITE(HTOTAL(cpu_transcoder
),
7628 (adjusted_mode
->crtc_hdisplay
- 1) |
7629 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7630 I915_WRITE(HBLANK(cpu_transcoder
),
7631 (adjusted_mode
->crtc_hblank_start
- 1) |
7632 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7633 I915_WRITE(HSYNC(cpu_transcoder
),
7634 (adjusted_mode
->crtc_hsync_start
- 1) |
7635 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7637 I915_WRITE(VTOTAL(cpu_transcoder
),
7638 (adjusted_mode
->crtc_vdisplay
- 1) |
7639 ((crtc_vtotal
- 1) << 16));
7640 I915_WRITE(VBLANK(cpu_transcoder
),
7641 (adjusted_mode
->crtc_vblank_start
- 1) |
7642 ((crtc_vblank_end
- 1) << 16));
7643 I915_WRITE(VSYNC(cpu_transcoder
),
7644 (adjusted_mode
->crtc_vsync_start
- 1) |
7645 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7647 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7648 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7649 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7651 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7652 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7653 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7657 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
)
7659 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7661 enum pipe pipe
= intel_crtc
->pipe
;
7663 /* pipesrc controls the size that is scaled from, which should
7664 * always be the user's requested size.
7666 I915_WRITE(PIPESRC(pipe
),
7667 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7668 (intel_crtc
->config
->pipe_src_h
- 1));
7671 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7672 struct intel_crtc_state
*pipe_config
)
7674 struct drm_device
*dev
= crtc
->base
.dev
;
7675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7676 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7679 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7680 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7681 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7682 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7683 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7684 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7685 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7686 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7687 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7689 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7690 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7691 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7692 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7693 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7694 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7695 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7696 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7697 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7699 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7700 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7701 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7702 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7706 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
7707 struct intel_crtc_state
*pipe_config
)
7709 struct drm_device
*dev
= crtc
->base
.dev
;
7710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7713 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7714 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7715 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7717 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7718 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7721 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7722 struct intel_crtc_state
*pipe_config
)
7724 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7725 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7726 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7727 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7729 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7730 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7731 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7732 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7734 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7735 mode
->type
= DRM_MODE_TYPE_DRIVER
;
7737 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7738 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7740 mode
->hsync
= drm_mode_hsync(mode
);
7741 mode
->vrefresh
= drm_mode_vrefresh(mode
);
7742 drm_mode_set_name(mode
);
7745 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7747 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7753 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7754 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7755 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7757 if (intel_crtc
->config
->double_wide
)
7758 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7760 /* only g4x and later have fancy bpc/dither controls */
7761 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
7762 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7763 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7764 pipeconf
|= PIPECONF_DITHER_EN
|
7765 PIPECONF_DITHER_TYPE_SP
;
7767 switch (intel_crtc
->config
->pipe_bpp
) {
7769 pipeconf
|= PIPECONF_6BPC
;
7772 pipeconf
|= PIPECONF_8BPC
;
7775 pipeconf
|= PIPECONF_10BPC
;
7778 /* Case prevented by intel_choose_pipe_bpp_dither. */
7783 if (HAS_PIPE_CXSR(dev
)) {
7784 if (intel_crtc
->lowfreq_avail
) {
7785 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7786 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7788 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7792 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7793 if (INTEL_INFO(dev
)->gen
< 4 ||
7794 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7795 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7797 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7799 pipeconf
|= PIPECONF_PROGRESSIVE
;
7801 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
7802 intel_crtc
->config
->limited_color_range
)
7803 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7805 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7806 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7809 static int i8xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7810 struct intel_crtc_state
*crtc_state
)
7812 struct drm_device
*dev
= crtc
->base
.dev
;
7813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7814 const intel_limit_t
*limit
;
7817 memset(&crtc_state
->dpll_hw_state
, 0,
7818 sizeof(crtc_state
->dpll_hw_state
));
7820 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7821 if (intel_panel_use_ssc(dev_priv
)) {
7822 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7823 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7826 limit
= &intel_limits_i8xx_lvds
;
7827 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
)) {
7828 limit
= &intel_limits_i8xx_dvo
;
7830 limit
= &intel_limits_i8xx_dac
;
7833 if (!crtc_state
->clock_set
&&
7834 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7835 refclk
, NULL
, &crtc_state
->dpll
)) {
7836 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7840 i8xx_compute_dpll(crtc
, crtc_state
, NULL
);
7845 static int g4x_crtc_compute_clock(struct intel_crtc
*crtc
,
7846 struct intel_crtc_state
*crtc_state
)
7848 struct drm_device
*dev
= crtc
->base
.dev
;
7849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7850 const intel_limit_t
*limit
;
7853 memset(&crtc_state
->dpll_hw_state
, 0,
7854 sizeof(crtc_state
->dpll_hw_state
));
7856 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7857 if (intel_panel_use_ssc(dev_priv
)) {
7858 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7859 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7862 if (intel_is_dual_link_lvds(dev
))
7863 limit
= &intel_limits_g4x_dual_channel_lvds
;
7865 limit
= &intel_limits_g4x_single_channel_lvds
;
7866 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
7867 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
7868 limit
= &intel_limits_g4x_hdmi
;
7869 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
7870 limit
= &intel_limits_g4x_sdvo
;
7872 /* The option is for other outputs */
7873 limit
= &intel_limits_i9xx_sdvo
;
7876 if (!crtc_state
->clock_set
&&
7877 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7878 refclk
, NULL
, &crtc_state
->dpll
)) {
7879 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7883 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7888 static int pnv_crtc_compute_clock(struct intel_crtc
*crtc
,
7889 struct intel_crtc_state
*crtc_state
)
7891 struct drm_device
*dev
= crtc
->base
.dev
;
7892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7893 const intel_limit_t
*limit
;
7896 memset(&crtc_state
->dpll_hw_state
, 0,
7897 sizeof(crtc_state
->dpll_hw_state
));
7899 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7900 if (intel_panel_use_ssc(dev_priv
)) {
7901 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7902 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7905 limit
= &intel_limits_pineview_lvds
;
7907 limit
= &intel_limits_pineview_sdvo
;
7910 if (!crtc_state
->clock_set
&&
7911 !pnv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7912 refclk
, NULL
, &crtc_state
->dpll
)) {
7913 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7917 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7922 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7923 struct intel_crtc_state
*crtc_state
)
7925 struct drm_device
*dev
= crtc
->base
.dev
;
7926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7927 const intel_limit_t
*limit
;
7930 memset(&crtc_state
->dpll_hw_state
, 0,
7931 sizeof(crtc_state
->dpll_hw_state
));
7933 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7934 if (intel_panel_use_ssc(dev_priv
)) {
7935 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7936 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7939 limit
= &intel_limits_i9xx_lvds
;
7941 limit
= &intel_limits_i9xx_sdvo
;
7944 if (!crtc_state
->clock_set
&&
7945 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7946 refclk
, NULL
, &crtc_state
->dpll
)) {
7947 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7951 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7956 static int chv_crtc_compute_clock(struct intel_crtc
*crtc
,
7957 struct intel_crtc_state
*crtc_state
)
7959 int refclk
= 100000;
7960 const intel_limit_t
*limit
= &intel_limits_chv
;
7962 memset(&crtc_state
->dpll_hw_state
, 0,
7963 sizeof(crtc_state
->dpll_hw_state
));
7965 if (!crtc_state
->clock_set
&&
7966 !chv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7967 refclk
, NULL
, &crtc_state
->dpll
)) {
7968 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7972 chv_compute_dpll(crtc
, crtc_state
);
7977 static int vlv_crtc_compute_clock(struct intel_crtc
*crtc
,
7978 struct intel_crtc_state
*crtc_state
)
7980 int refclk
= 100000;
7981 const intel_limit_t
*limit
= &intel_limits_vlv
;
7983 memset(&crtc_state
->dpll_hw_state
, 0,
7984 sizeof(crtc_state
->dpll_hw_state
));
7986 if (!crtc_state
->clock_set
&&
7987 !vlv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7988 refclk
, NULL
, &crtc_state
->dpll
)) {
7989 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7993 vlv_compute_dpll(crtc
, crtc_state
);
7998 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7999 struct intel_crtc_state
*pipe_config
)
8001 struct drm_device
*dev
= crtc
->base
.dev
;
8002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8005 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
8008 tmp
= I915_READ(PFIT_CONTROL
);
8009 if (!(tmp
& PFIT_ENABLE
))
8012 /* Check whether the pfit is attached to our pipe. */
8013 if (INTEL_INFO(dev
)->gen
< 4) {
8014 if (crtc
->pipe
!= PIPE_B
)
8017 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
8021 pipe_config
->gmch_pfit
.control
= tmp
;
8022 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
8025 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
8026 struct intel_crtc_state
*pipe_config
)
8028 struct drm_device
*dev
= crtc
->base
.dev
;
8029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8030 int pipe
= pipe_config
->cpu_transcoder
;
8031 intel_clock_t clock
;
8033 int refclk
= 100000;
8035 /* In case of DSI, DPLL will not be used */
8036 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8039 mutex_lock(&dev_priv
->sb_lock
);
8040 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8041 mutex_unlock(&dev_priv
->sb_lock
);
8043 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8044 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8045 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8046 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8047 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8049 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
8053 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8054 struct intel_initial_plane_config
*plane_config
)
8056 struct drm_device
*dev
= crtc
->base
.dev
;
8057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8058 u32 val
, base
, offset
;
8059 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
8060 int fourcc
, pixel_format
;
8061 unsigned int aligned_height
;
8062 struct drm_framebuffer
*fb
;
8063 struct intel_framebuffer
*intel_fb
;
8065 val
= I915_READ(DSPCNTR(plane
));
8066 if (!(val
& DISPLAY_PLANE_ENABLE
))
8069 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8071 DRM_DEBUG_KMS("failed to alloc fb\n");
8075 fb
= &intel_fb
->base
;
8077 if (INTEL_INFO(dev
)->gen
>= 4) {
8078 if (val
& DISPPLANE_TILED
) {
8079 plane_config
->tiling
= I915_TILING_X
;
8080 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8084 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8085 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8086 fb
->pixel_format
= fourcc
;
8087 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8089 if (INTEL_INFO(dev
)->gen
>= 4) {
8090 if (plane_config
->tiling
)
8091 offset
= I915_READ(DSPTILEOFF(plane
));
8093 offset
= I915_READ(DSPLINOFF(plane
));
8094 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
8096 base
= I915_READ(DSPADDR(plane
));
8098 plane_config
->base
= base
;
8100 val
= I915_READ(PIPESRC(pipe
));
8101 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8102 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8104 val
= I915_READ(DSPSTRIDE(pipe
));
8105 fb
->pitches
[0] = val
& 0xffffffc0;
8107 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8111 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8113 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8114 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
8115 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8116 plane_config
->size
);
8118 plane_config
->fb
= intel_fb
;
8121 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8122 struct intel_crtc_state
*pipe_config
)
8124 struct drm_device
*dev
= crtc
->base
.dev
;
8125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8126 int pipe
= pipe_config
->cpu_transcoder
;
8127 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8128 intel_clock_t clock
;
8129 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
8130 int refclk
= 100000;
8132 /* In case of DSI, DPLL will not be used */
8133 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8136 mutex_lock(&dev_priv
->sb_lock
);
8137 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8138 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8139 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8140 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8141 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8142 mutex_unlock(&dev_priv
->sb_lock
);
8144 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8145 clock
.m2
= (pll_dw0
& 0xff) << 22;
8146 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
8147 clock
.m2
|= pll_dw2
& 0x3fffff;
8148 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8149 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8150 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8152 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8155 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8156 struct intel_crtc_state
*pipe_config
)
8158 struct drm_device
*dev
= crtc
->base
.dev
;
8159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8160 enum intel_display_power_domain power_domain
;
8164 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
8165 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
8168 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8169 pipe_config
->shared_dpll
= NULL
;
8173 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8174 if (!(tmp
& PIPECONF_ENABLE
))
8177 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
8178 switch (tmp
& PIPECONF_BPC_MASK
) {
8180 pipe_config
->pipe_bpp
= 18;
8183 pipe_config
->pipe_bpp
= 24;
8185 case PIPECONF_10BPC
:
8186 pipe_config
->pipe_bpp
= 30;
8193 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
8194 (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8195 pipe_config
->limited_color_range
= true;
8197 if (INTEL_INFO(dev
)->gen
< 4)
8198 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8200 intel_get_pipe_timings(crtc
, pipe_config
);
8201 intel_get_pipe_src_size(crtc
, pipe_config
);
8203 i9xx_get_pfit_config(crtc
, pipe_config
);
8205 if (INTEL_INFO(dev
)->gen
>= 4) {
8206 /* No way to read it out on pipes B and C */
8207 if (IS_CHERRYVIEW(dev
) && crtc
->pipe
!= PIPE_A
)
8208 tmp
= dev_priv
->chv_dpll_md
[crtc
->pipe
];
8210 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8211 pipe_config
->pixel_multiplier
=
8212 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8213 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8214 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8215 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
8216 tmp
= I915_READ(DPLL(crtc
->pipe
));
8217 pipe_config
->pixel_multiplier
=
8218 ((tmp
& SDVO_MULTIPLIER_MASK
)
8219 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8221 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8222 * port and will be fixed up in the encoder->get_config
8224 pipe_config
->pixel_multiplier
= 1;
8226 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8227 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
8229 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8230 * on 830. Filter it out here so that we don't
8231 * report errors due to that.
8234 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
8236 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8237 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8239 /* Mask out read-only status bits. */
8240 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8241 DPLL_PORTC_READY_MASK
|
8242 DPLL_PORTB_READY_MASK
);
8245 if (IS_CHERRYVIEW(dev
))
8246 chv_crtc_clock_get(crtc
, pipe_config
);
8247 else if (IS_VALLEYVIEW(dev
))
8248 vlv_crtc_clock_get(crtc
, pipe_config
);
8250 i9xx_crtc_clock_get(crtc
, pipe_config
);
8253 * Normally the dotclock is filled in by the encoder .get_config()
8254 * but in case the pipe is enabled w/o any ports we need a sane
8257 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8258 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8263 intel_display_power_put(dev_priv
, power_domain
);
8268 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
8270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8271 struct intel_encoder
*encoder
;
8273 bool has_lvds
= false;
8274 bool has_cpu_edp
= false;
8275 bool has_panel
= false;
8276 bool has_ck505
= false;
8277 bool can_ssc
= false;
8279 /* We need to take the global config into account */
8280 for_each_intel_encoder(dev
, encoder
) {
8281 switch (encoder
->type
) {
8282 case INTEL_OUTPUT_LVDS
:
8286 case INTEL_OUTPUT_EDP
:
8288 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
8296 if (HAS_PCH_IBX(dev
)) {
8297 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8298 can_ssc
= has_ck505
;
8304 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8305 has_panel
, has_lvds
, has_ck505
);
8307 /* Ironlake: try to setup display ref clock before DPLL
8308 * enabling. This is only under driver's control after
8309 * PCH B stepping, previous chipset stepping should be
8310 * ignoring this setting.
8312 val
= I915_READ(PCH_DREF_CONTROL
);
8314 /* As we must carefully and slowly disable/enable each source in turn,
8315 * compute the final state we want first and check if we need to
8316 * make any changes at all.
8319 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8321 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8323 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8325 final
&= ~DREF_SSC_SOURCE_MASK
;
8326 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8327 final
&= ~DREF_SSC1_ENABLE
;
8330 final
|= DREF_SSC_SOURCE_ENABLE
;
8332 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8333 final
|= DREF_SSC1_ENABLE
;
8336 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8337 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8339 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8341 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8343 final
|= DREF_SSC_SOURCE_DISABLE
;
8344 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8350 /* Always enable nonspread source */
8351 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8354 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8356 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8359 val
&= ~DREF_SSC_SOURCE_MASK
;
8360 val
|= DREF_SSC_SOURCE_ENABLE
;
8362 /* SSC must be turned on before enabling the CPU output */
8363 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8364 DRM_DEBUG_KMS("Using SSC on panel\n");
8365 val
|= DREF_SSC1_ENABLE
;
8367 val
&= ~DREF_SSC1_ENABLE
;
8369 /* Get SSC going before enabling the outputs */
8370 I915_WRITE(PCH_DREF_CONTROL
, val
);
8371 POSTING_READ(PCH_DREF_CONTROL
);
8374 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8376 /* Enable CPU source on CPU attached eDP */
8378 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8379 DRM_DEBUG_KMS("Using SSC on eDP\n");
8380 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8382 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8384 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8386 I915_WRITE(PCH_DREF_CONTROL
, val
);
8387 POSTING_READ(PCH_DREF_CONTROL
);
8390 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8392 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8394 /* Turn off CPU output */
8395 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8397 I915_WRITE(PCH_DREF_CONTROL
, val
);
8398 POSTING_READ(PCH_DREF_CONTROL
);
8401 /* Turn off the SSC source */
8402 val
&= ~DREF_SSC_SOURCE_MASK
;
8403 val
|= DREF_SSC_SOURCE_DISABLE
;
8406 val
&= ~DREF_SSC1_ENABLE
;
8408 I915_WRITE(PCH_DREF_CONTROL
, val
);
8409 POSTING_READ(PCH_DREF_CONTROL
);
8413 BUG_ON(val
!= final
);
8416 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8420 tmp
= I915_READ(SOUTH_CHICKEN2
);
8421 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8422 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8424 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
8425 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8426 DRM_ERROR("FDI mPHY reset assert timeout\n");
8428 tmp
= I915_READ(SOUTH_CHICKEN2
);
8429 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8430 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8432 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
8433 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8434 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8437 /* WaMPhyProgramming:hsw */
8438 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8442 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8443 tmp
&= ~(0xFF << 24);
8444 tmp
|= (0x12 << 24);
8445 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8447 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8449 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8451 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8453 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8455 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8456 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8457 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8459 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8460 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8461 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8463 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8466 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8468 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8471 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8473 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8476 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8478 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8481 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8483 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8484 tmp
&= ~(0xFF << 16);
8485 tmp
|= (0x1C << 16);
8486 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8488 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8489 tmp
&= ~(0xFF << 16);
8490 tmp
|= (0x1C << 16);
8491 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8493 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8495 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8497 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8499 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8501 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8502 tmp
&= ~(0xF << 28);
8504 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8506 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8507 tmp
&= ~(0xF << 28);
8509 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8512 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8513 * Programming" based on the parameters passed:
8514 * - Sequence to enable CLKOUT_DP
8515 * - Sequence to enable CLKOUT_DP without spread
8516 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8518 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8524 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8526 if (WARN(HAS_PCH_LPT_LP(dev
) && with_fdi
, "LP PCH doesn't have FDI\n"))
8529 mutex_lock(&dev_priv
->sb_lock
);
8531 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8532 tmp
&= ~SBI_SSCCTL_DISABLE
;
8533 tmp
|= SBI_SSCCTL_PATHALT
;
8534 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8539 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8540 tmp
&= ~SBI_SSCCTL_PATHALT
;
8541 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8544 lpt_reset_fdi_mphy(dev_priv
);
8545 lpt_program_fdi_mphy(dev_priv
);
8549 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8550 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8551 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8552 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8554 mutex_unlock(&dev_priv
->sb_lock
);
8557 /* Sequence to disable CLKOUT_DP */
8558 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8563 mutex_lock(&dev_priv
->sb_lock
);
8565 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8566 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8567 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8568 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8570 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8571 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8572 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8573 tmp
|= SBI_SSCCTL_PATHALT
;
8574 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8577 tmp
|= SBI_SSCCTL_DISABLE
;
8578 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8581 mutex_unlock(&dev_priv
->sb_lock
);
8584 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8586 static const uint16_t sscdivintphase
[] = {
8587 [BEND_IDX( 50)] = 0x3B23,
8588 [BEND_IDX( 45)] = 0x3B23,
8589 [BEND_IDX( 40)] = 0x3C23,
8590 [BEND_IDX( 35)] = 0x3C23,
8591 [BEND_IDX( 30)] = 0x3D23,
8592 [BEND_IDX( 25)] = 0x3D23,
8593 [BEND_IDX( 20)] = 0x3E23,
8594 [BEND_IDX( 15)] = 0x3E23,
8595 [BEND_IDX( 10)] = 0x3F23,
8596 [BEND_IDX( 5)] = 0x3F23,
8597 [BEND_IDX( 0)] = 0x0025,
8598 [BEND_IDX( -5)] = 0x0025,
8599 [BEND_IDX(-10)] = 0x0125,
8600 [BEND_IDX(-15)] = 0x0125,
8601 [BEND_IDX(-20)] = 0x0225,
8602 [BEND_IDX(-25)] = 0x0225,
8603 [BEND_IDX(-30)] = 0x0325,
8604 [BEND_IDX(-35)] = 0x0325,
8605 [BEND_IDX(-40)] = 0x0425,
8606 [BEND_IDX(-45)] = 0x0425,
8607 [BEND_IDX(-50)] = 0x0525,
8612 * steps -50 to 50 inclusive, in steps of 5
8613 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8614 * change in clock period = -(steps / 10) * 5.787 ps
8616 static void lpt_bend_clkout_dp(struct drm_i915_private
*dev_priv
, int steps
)
8619 int idx
= BEND_IDX(steps
);
8621 if (WARN_ON(steps
% 5 != 0))
8624 if (WARN_ON(idx
>= ARRAY_SIZE(sscdivintphase
)))
8627 mutex_lock(&dev_priv
->sb_lock
);
8629 if (steps
% 10 != 0)
8633 intel_sbi_write(dev_priv
, SBI_SSCDITHPHASE
, tmp
, SBI_ICLK
);
8635 tmp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE
, SBI_ICLK
);
8637 tmp
|= sscdivintphase
[idx
];
8638 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE
, tmp
, SBI_ICLK
);
8640 mutex_unlock(&dev_priv
->sb_lock
);
8645 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8647 struct intel_encoder
*encoder
;
8648 bool has_vga
= false;
8650 for_each_intel_encoder(dev
, encoder
) {
8651 switch (encoder
->type
) {
8652 case INTEL_OUTPUT_ANALOG
:
8661 lpt_bend_clkout_dp(to_i915(dev
), 0);
8662 lpt_enable_clkout_dp(dev
, true, true);
8664 lpt_disable_clkout_dp(dev
);
8669 * Initialize reference clocks when the driver loads
8671 void intel_init_pch_refclk(struct drm_device
*dev
)
8673 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8674 ironlake_init_pch_refclk(dev
);
8675 else if (HAS_PCH_LPT(dev
))
8676 lpt_init_pch_refclk(dev
);
8679 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8681 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8682 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8683 int pipe
= intel_crtc
->pipe
;
8688 switch (intel_crtc
->config
->pipe_bpp
) {
8690 val
|= PIPECONF_6BPC
;
8693 val
|= PIPECONF_8BPC
;
8696 val
|= PIPECONF_10BPC
;
8699 val
|= PIPECONF_12BPC
;
8702 /* Case prevented by intel_choose_pipe_bpp_dither. */
8706 if (intel_crtc
->config
->dither
)
8707 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8709 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8710 val
|= PIPECONF_INTERLACED_ILK
;
8712 val
|= PIPECONF_PROGRESSIVE
;
8714 if (intel_crtc
->config
->limited_color_range
)
8715 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8717 I915_WRITE(PIPECONF(pipe
), val
);
8718 POSTING_READ(PIPECONF(pipe
));
8721 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8723 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8724 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8725 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8728 if (IS_HASWELL(dev_priv
) && intel_crtc
->config
->dither
)
8729 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8731 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8732 val
|= PIPECONF_INTERLACED_ILK
;
8734 val
|= PIPECONF_PROGRESSIVE
;
8736 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8737 POSTING_READ(PIPECONF(cpu_transcoder
));
8740 static void haswell_set_pipemisc(struct drm_crtc
*crtc
)
8742 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8743 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8745 if (IS_BROADWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 9) {
8748 switch (intel_crtc
->config
->pipe_bpp
) {
8750 val
|= PIPEMISC_DITHER_6_BPC
;
8753 val
|= PIPEMISC_DITHER_8_BPC
;
8756 val
|= PIPEMISC_DITHER_10_BPC
;
8759 val
|= PIPEMISC_DITHER_12_BPC
;
8762 /* Case prevented by pipe_config_set_bpp. */
8766 if (intel_crtc
->config
->dither
)
8767 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8769 I915_WRITE(PIPEMISC(intel_crtc
->pipe
), val
);
8773 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8776 * Account for spread spectrum to avoid
8777 * oversubscribing the link. Max center spread
8778 * is 2.5%; use 5% for safety's sake.
8780 u32 bps
= target_clock
* bpp
* 21 / 20;
8781 return DIV_ROUND_UP(bps
, link_bw
* 8);
8784 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8786 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8789 static void ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8790 struct intel_crtc_state
*crtc_state
,
8791 intel_clock_t
*reduced_clock
)
8793 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8794 struct drm_device
*dev
= crtc
->dev
;
8795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8796 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8797 struct drm_connector
*connector
;
8798 struct drm_connector_state
*connector_state
;
8799 struct intel_encoder
*encoder
;
8802 bool is_lvds
= false, is_sdvo
= false;
8804 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8805 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8808 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8810 switch (encoder
->type
) {
8811 case INTEL_OUTPUT_LVDS
:
8814 case INTEL_OUTPUT_SDVO
:
8815 case INTEL_OUTPUT_HDMI
:
8823 /* Enable autotuning of the PLL clock (if permissible) */
8826 if ((intel_panel_use_ssc(dev_priv
) &&
8827 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8828 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8830 } else if (crtc_state
->sdvo_tv_clock
)
8833 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8835 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8838 if (reduced_clock
) {
8839 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
8841 if (reduced_clock
->m
< factor
* reduced_clock
->n
)
8850 dpll
|= DPLLB_MODE_LVDS
;
8852 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8854 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8855 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8858 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8859 if (crtc_state
->has_dp_encoder
)
8860 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8862 /* compute bitmask from p1 value */
8863 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8865 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8867 switch (crtc_state
->dpll
.p2
) {
8869 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8872 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8875 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8878 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8882 if (is_lvds
&& intel_panel_use_ssc(dev_priv
))
8883 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8885 dpll
|= PLL_REF_INPUT_DREFCLK
;
8887 dpll
|= DPLL_VCO_ENABLE
;
8889 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8890 crtc_state
->dpll_hw_state
.fp0
= fp
;
8891 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8894 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8895 struct intel_crtc_state
*crtc_state
)
8897 struct drm_device
*dev
= crtc
->base
.dev
;
8898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8899 intel_clock_t reduced_clock
;
8900 bool has_reduced_clock
= false;
8901 struct intel_shared_dpll
*pll
;
8902 const intel_limit_t
*limit
;
8903 int refclk
= 120000;
8905 memset(&crtc_state
->dpll_hw_state
, 0,
8906 sizeof(crtc_state
->dpll_hw_state
));
8908 crtc
->lowfreq_avail
= false;
8910 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8911 if (!crtc_state
->has_pch_encoder
)
8914 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8915 if (intel_panel_use_ssc(dev_priv
)) {
8916 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8917 dev_priv
->vbt
.lvds_ssc_freq
);
8918 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8921 if (intel_is_dual_link_lvds(dev
)) {
8922 if (refclk
== 100000)
8923 limit
= &intel_limits_ironlake_dual_lvds_100m
;
8925 limit
= &intel_limits_ironlake_dual_lvds
;
8927 if (refclk
== 100000)
8928 limit
= &intel_limits_ironlake_single_lvds_100m
;
8930 limit
= &intel_limits_ironlake_single_lvds
;
8933 limit
= &intel_limits_ironlake_dac
;
8936 if (!crtc_state
->clock_set
&&
8937 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8938 refclk
, NULL
, &crtc_state
->dpll
)) {
8939 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8943 ironlake_compute_dpll(crtc
, crtc_state
,
8944 has_reduced_clock
? &reduced_clock
: NULL
);
8946 pll
= intel_get_shared_dpll(crtc
, crtc_state
, NULL
);
8948 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8949 pipe_name(crtc
->pipe
));
8953 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
8955 crtc
->lowfreq_avail
= true;
8960 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
8961 struct intel_link_m_n
*m_n
)
8963 struct drm_device
*dev
= crtc
->base
.dev
;
8964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8965 enum pipe pipe
= crtc
->pipe
;
8967 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
8968 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
8969 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
8971 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
8972 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
8973 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8976 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
8977 enum transcoder transcoder
,
8978 struct intel_link_m_n
*m_n
,
8979 struct intel_link_m_n
*m2_n2
)
8981 struct drm_device
*dev
= crtc
->base
.dev
;
8982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8983 enum pipe pipe
= crtc
->pipe
;
8985 if (INTEL_INFO(dev
)->gen
>= 5) {
8986 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8987 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8988 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8990 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8991 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8992 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8993 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8994 * gen < 8) and if DRRS is supported (to make sure the
8995 * registers are not unnecessarily read).
8997 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
8998 crtc
->config
->has_drrs
) {
8999 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
9000 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
9001 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
9003 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
9004 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
9005 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9008 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
9009 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
9010 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
9012 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
9013 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
9014 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9018 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
9019 struct intel_crtc_state
*pipe_config
)
9021 if (pipe_config
->has_pch_encoder
)
9022 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
9024 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9025 &pipe_config
->dp_m_n
,
9026 &pipe_config
->dp_m2_n2
);
9029 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9030 struct intel_crtc_state
*pipe_config
)
9032 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9033 &pipe_config
->fdi_m_n
, NULL
);
9036 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9037 struct intel_crtc_state
*pipe_config
)
9039 struct drm_device
*dev
= crtc
->base
.dev
;
9040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9041 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9042 uint32_t ps_ctrl
= 0;
9046 /* find scaler attached to this pipe */
9047 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9048 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9049 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9051 pipe_config
->pch_pfit
.enabled
= true;
9052 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9053 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9058 scaler_state
->scaler_id
= id
;
9060 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9062 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9067 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9068 struct intel_initial_plane_config
*plane_config
)
9070 struct drm_device
*dev
= crtc
->base
.dev
;
9071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9072 u32 val
, base
, offset
, stride_mult
, tiling
;
9073 int pipe
= crtc
->pipe
;
9074 int fourcc
, pixel_format
;
9075 unsigned int aligned_height
;
9076 struct drm_framebuffer
*fb
;
9077 struct intel_framebuffer
*intel_fb
;
9079 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9081 DRM_DEBUG_KMS("failed to alloc fb\n");
9085 fb
= &intel_fb
->base
;
9087 val
= I915_READ(PLANE_CTL(pipe
, 0));
9088 if (!(val
& PLANE_CTL_ENABLE
))
9091 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9092 fourcc
= skl_format_to_fourcc(pixel_format
,
9093 val
& PLANE_CTL_ORDER_RGBX
,
9094 val
& PLANE_CTL_ALPHA_MASK
);
9095 fb
->pixel_format
= fourcc
;
9096 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9098 tiling
= val
& PLANE_CTL_TILED_MASK
;
9100 case PLANE_CTL_TILED_LINEAR
:
9101 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
9103 case PLANE_CTL_TILED_X
:
9104 plane_config
->tiling
= I915_TILING_X
;
9105 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9107 case PLANE_CTL_TILED_Y
:
9108 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
9110 case PLANE_CTL_TILED_YF
:
9111 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
9114 MISSING_CASE(tiling
);
9118 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
9119 plane_config
->base
= base
;
9121 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
9123 val
= I915_READ(PLANE_SIZE(pipe
, 0));
9124 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9125 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9127 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
9128 stride_mult
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
9130 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9132 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9136 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9138 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9139 pipe_name(pipe
), fb
->width
, fb
->height
,
9140 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9141 plane_config
->size
);
9143 plane_config
->fb
= intel_fb
;
9150 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9151 struct intel_crtc_state
*pipe_config
)
9153 struct drm_device
*dev
= crtc
->base
.dev
;
9154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9157 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9159 if (tmp
& PF_ENABLE
) {
9160 pipe_config
->pch_pfit
.enabled
= true;
9161 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9162 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9164 /* We currently do not free assignements of panel fitters on
9165 * ivb/hsw (since we don't use the higher upscaling modes which
9166 * differentiates them) so just WARN about this case for now. */
9168 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9169 PF_PIPE_SEL_IVB(crtc
->pipe
));
9175 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
9176 struct intel_initial_plane_config
*plane_config
)
9178 struct drm_device
*dev
= crtc
->base
.dev
;
9179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9180 u32 val
, base
, offset
;
9181 int pipe
= crtc
->pipe
;
9182 int fourcc
, pixel_format
;
9183 unsigned int aligned_height
;
9184 struct drm_framebuffer
*fb
;
9185 struct intel_framebuffer
*intel_fb
;
9187 val
= I915_READ(DSPCNTR(pipe
));
9188 if (!(val
& DISPLAY_PLANE_ENABLE
))
9191 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9193 DRM_DEBUG_KMS("failed to alloc fb\n");
9197 fb
= &intel_fb
->base
;
9199 if (INTEL_INFO(dev
)->gen
>= 4) {
9200 if (val
& DISPPLANE_TILED
) {
9201 plane_config
->tiling
= I915_TILING_X
;
9202 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9206 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
9207 fourcc
= i9xx_format_to_fourcc(pixel_format
);
9208 fb
->pixel_format
= fourcc
;
9209 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9211 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
9212 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
9213 offset
= I915_READ(DSPOFFSET(pipe
));
9215 if (plane_config
->tiling
)
9216 offset
= I915_READ(DSPTILEOFF(pipe
));
9218 offset
= I915_READ(DSPLINOFF(pipe
));
9220 plane_config
->base
= base
;
9222 val
= I915_READ(PIPESRC(pipe
));
9223 fb
->width
= ((val
>> 16) & 0xfff) + 1;
9224 fb
->height
= ((val
>> 0) & 0xfff) + 1;
9226 val
= I915_READ(DSPSTRIDE(pipe
));
9227 fb
->pitches
[0] = val
& 0xffffffc0;
9229 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9233 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9235 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9236 pipe_name(pipe
), fb
->width
, fb
->height
,
9237 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9238 plane_config
->size
);
9240 plane_config
->fb
= intel_fb
;
9243 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9244 struct intel_crtc_state
*pipe_config
)
9246 struct drm_device
*dev
= crtc
->base
.dev
;
9247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9248 enum intel_display_power_domain power_domain
;
9252 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9253 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9256 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9257 pipe_config
->shared_dpll
= NULL
;
9260 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9261 if (!(tmp
& PIPECONF_ENABLE
))
9264 switch (tmp
& PIPECONF_BPC_MASK
) {
9266 pipe_config
->pipe_bpp
= 18;
9269 pipe_config
->pipe_bpp
= 24;
9271 case PIPECONF_10BPC
:
9272 pipe_config
->pipe_bpp
= 30;
9274 case PIPECONF_12BPC
:
9275 pipe_config
->pipe_bpp
= 36;
9281 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9282 pipe_config
->limited_color_range
= true;
9284 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9285 struct intel_shared_dpll
*pll
;
9286 enum intel_dpll_id pll_id
;
9288 pipe_config
->has_pch_encoder
= true;
9290 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9291 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9292 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9294 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9296 if (HAS_PCH_IBX(dev_priv
)) {
9297 pll_id
= (enum intel_dpll_id
) crtc
->pipe
;
9299 tmp
= I915_READ(PCH_DPLL_SEL
);
9300 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9301 pll_id
= DPLL_ID_PCH_PLL_B
;
9303 pll_id
= DPLL_ID_PCH_PLL_A
;
9306 pipe_config
->shared_dpll
=
9307 intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
9308 pll
= pipe_config
->shared_dpll
;
9310 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
9311 &pipe_config
->dpll_hw_state
));
9313 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9314 pipe_config
->pixel_multiplier
=
9315 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9316 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9318 ironlake_pch_clock_get(crtc
, pipe_config
);
9320 pipe_config
->pixel_multiplier
= 1;
9323 intel_get_pipe_timings(crtc
, pipe_config
);
9324 intel_get_pipe_src_size(crtc
, pipe_config
);
9326 ironlake_get_pfit_config(crtc
, pipe_config
);
9331 intel_display_power_put(dev_priv
, power_domain
);
9336 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
9338 struct drm_device
*dev
= dev_priv
->dev
;
9339 struct intel_crtc
*crtc
;
9341 for_each_intel_crtc(dev
, crtc
)
9342 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
9343 pipe_name(crtc
->pipe
));
9345 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
9346 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
9347 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
9348 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
9349 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
9350 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
9351 "CPU PWM1 enabled\n");
9352 if (IS_HASWELL(dev
))
9353 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
9354 "CPU PWM2 enabled\n");
9355 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
9356 "PCH PWM1 enabled\n");
9357 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
9358 "Utility pin enabled\n");
9359 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
9362 * In theory we can still leave IRQs enabled, as long as only the HPD
9363 * interrupts remain enabled. We used to check for that, but since it's
9364 * gen-specific and since we only disable LCPLL after we fully disable
9365 * the interrupts, the check below should be enough.
9367 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
9370 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
9372 struct drm_device
*dev
= dev_priv
->dev
;
9374 if (IS_HASWELL(dev
))
9375 return I915_READ(D_COMP_HSW
);
9377 return I915_READ(D_COMP_BDW
);
9380 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
9382 struct drm_device
*dev
= dev_priv
->dev
;
9384 if (IS_HASWELL(dev
)) {
9385 mutex_lock(&dev_priv
->rps
.hw_lock
);
9386 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
9388 DRM_ERROR("Failed to write to D_COMP\n");
9389 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9391 I915_WRITE(D_COMP_BDW
, val
);
9392 POSTING_READ(D_COMP_BDW
);
9397 * This function implements pieces of two sequences from BSpec:
9398 * - Sequence for display software to disable LCPLL
9399 * - Sequence for display software to allow package C8+
9400 * The steps implemented here are just the steps that actually touch the LCPLL
9401 * register. Callers should take care of disabling all the display engine
9402 * functions, doing the mode unset, fixing interrupts, etc.
9404 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9405 bool switch_to_fclk
, bool allow_power_down
)
9409 assert_can_disable_lcpll(dev_priv
);
9411 val
= I915_READ(LCPLL_CTL
);
9413 if (switch_to_fclk
) {
9414 val
|= LCPLL_CD_SOURCE_FCLK
;
9415 I915_WRITE(LCPLL_CTL
, val
);
9417 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9418 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9419 DRM_ERROR("Switching to FCLK failed\n");
9421 val
= I915_READ(LCPLL_CTL
);
9424 val
|= LCPLL_PLL_DISABLE
;
9425 I915_WRITE(LCPLL_CTL
, val
);
9426 POSTING_READ(LCPLL_CTL
);
9428 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
9429 DRM_ERROR("LCPLL still locked\n");
9431 val
= hsw_read_dcomp(dev_priv
);
9432 val
|= D_COMP_COMP_DISABLE
;
9433 hsw_write_dcomp(dev_priv
, val
);
9436 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9438 DRM_ERROR("D_COMP RCOMP still in progress\n");
9440 if (allow_power_down
) {
9441 val
= I915_READ(LCPLL_CTL
);
9442 val
|= LCPLL_POWER_DOWN_ALLOW
;
9443 I915_WRITE(LCPLL_CTL
, val
);
9444 POSTING_READ(LCPLL_CTL
);
9449 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9452 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9456 val
= I915_READ(LCPLL_CTL
);
9458 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9459 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9463 * Make sure we're not on PC8 state before disabling PC8, otherwise
9464 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9466 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9468 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9469 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9470 I915_WRITE(LCPLL_CTL
, val
);
9471 POSTING_READ(LCPLL_CTL
);
9474 val
= hsw_read_dcomp(dev_priv
);
9475 val
|= D_COMP_COMP_FORCE
;
9476 val
&= ~D_COMP_COMP_DISABLE
;
9477 hsw_write_dcomp(dev_priv
, val
);
9479 val
= I915_READ(LCPLL_CTL
);
9480 val
&= ~LCPLL_PLL_DISABLE
;
9481 I915_WRITE(LCPLL_CTL
, val
);
9483 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
9484 DRM_ERROR("LCPLL not locked yet\n");
9486 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9487 val
= I915_READ(LCPLL_CTL
);
9488 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9489 I915_WRITE(LCPLL_CTL
, val
);
9491 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9492 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9493 DRM_ERROR("Switching back to LCPLL failed\n");
9496 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9497 intel_update_cdclk(dev_priv
->dev
);
9501 * Package states C8 and deeper are really deep PC states that can only be
9502 * reached when all the devices on the system allow it, so even if the graphics
9503 * device allows PC8+, it doesn't mean the system will actually get to these
9504 * states. Our driver only allows PC8+ when going into runtime PM.
9506 * The requirements for PC8+ are that all the outputs are disabled, the power
9507 * well is disabled and most interrupts are disabled, and these are also
9508 * requirements for runtime PM. When these conditions are met, we manually do
9509 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9510 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9513 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9514 * the state of some registers, so when we come back from PC8+ we need to
9515 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9516 * need to take care of the registers kept by RC6. Notice that this happens even
9517 * if we don't put the device in PCI D3 state (which is what currently happens
9518 * because of the runtime PM support).
9520 * For more, read "Display Sequences for Package C8" on the hardware
9523 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9525 struct drm_device
*dev
= dev_priv
->dev
;
9528 DRM_DEBUG_KMS("Enabling package C8+\n");
9530 if (HAS_PCH_LPT_LP(dev
)) {
9531 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9532 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9533 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9536 lpt_disable_clkout_dp(dev
);
9537 hsw_disable_lcpll(dev_priv
, true, true);
9540 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9542 struct drm_device
*dev
= dev_priv
->dev
;
9545 DRM_DEBUG_KMS("Disabling package C8+\n");
9547 hsw_restore_lcpll(dev_priv
);
9548 lpt_init_pch_refclk(dev
);
9550 if (HAS_PCH_LPT_LP(dev
)) {
9551 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9552 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9553 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9557 static void broxton_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9559 struct drm_device
*dev
= old_state
->dev
;
9560 struct intel_atomic_state
*old_intel_state
=
9561 to_intel_atomic_state(old_state
);
9562 unsigned int req_cdclk
= old_intel_state
->dev_cdclk
;
9564 broxton_set_cdclk(to_i915(dev
), req_cdclk
);
9567 /* compute the max rate for new configuration */
9568 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
)
9570 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
9571 struct drm_i915_private
*dev_priv
= state
->dev
->dev_private
;
9572 struct drm_crtc
*crtc
;
9573 struct drm_crtc_state
*cstate
;
9574 struct intel_crtc_state
*crtc_state
;
9575 unsigned max_pixel_rate
= 0, i
;
9578 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
9579 sizeof(intel_state
->min_pixclk
));
9581 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
9584 crtc_state
= to_intel_crtc_state(cstate
);
9585 if (!crtc_state
->base
.enable
) {
9586 intel_state
->min_pixclk
[i
] = 0;
9590 pixel_rate
= ilk_pipe_pixel_rate(crtc_state
);
9592 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9593 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
9594 pixel_rate
= DIV_ROUND_UP(pixel_rate
* 100, 95);
9596 intel_state
->min_pixclk
[i
] = pixel_rate
;
9599 for_each_pipe(dev_priv
, pipe
)
9600 max_pixel_rate
= max(intel_state
->min_pixclk
[pipe
], max_pixel_rate
);
9602 return max_pixel_rate
;
9605 static void broadwell_set_cdclk(struct drm_device
*dev
, int cdclk
)
9607 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9611 if (WARN((I915_READ(LCPLL_CTL
) &
9612 (LCPLL_PLL_DISABLE
| LCPLL_PLL_LOCK
|
9613 LCPLL_CD_CLOCK_DISABLE
| LCPLL_ROOT_CD_CLOCK_DISABLE
|
9614 LCPLL_CD2X_CLOCK_DISABLE
| LCPLL_POWER_DOWN_ALLOW
|
9615 LCPLL_CD_SOURCE_FCLK
)) != LCPLL_PLL_LOCK
,
9616 "trying to change cdclk frequency with cdclk not enabled\n"))
9619 mutex_lock(&dev_priv
->rps
.hw_lock
);
9620 ret
= sandybridge_pcode_write(dev_priv
,
9621 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
, 0x0);
9622 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9624 DRM_ERROR("failed to inform pcode about cdclk change\n");
9628 val
= I915_READ(LCPLL_CTL
);
9629 val
|= LCPLL_CD_SOURCE_FCLK
;
9630 I915_WRITE(LCPLL_CTL
, val
);
9632 if (wait_for_us(I915_READ(LCPLL_CTL
) &
9633 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9634 DRM_ERROR("Switching to FCLK failed\n");
9636 val
= I915_READ(LCPLL_CTL
);
9637 val
&= ~LCPLL_CLK_FREQ_MASK
;
9641 val
|= LCPLL_CLK_FREQ_450
;
9645 val
|= LCPLL_CLK_FREQ_54O_BDW
;
9649 val
|= LCPLL_CLK_FREQ_337_5_BDW
;
9653 val
|= LCPLL_CLK_FREQ_675_BDW
;
9657 WARN(1, "invalid cdclk frequency\n");
9661 I915_WRITE(LCPLL_CTL
, val
);
9663 val
= I915_READ(LCPLL_CTL
);
9664 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9665 I915_WRITE(LCPLL_CTL
, val
);
9667 if (wait_for_us((I915_READ(LCPLL_CTL
) &
9668 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9669 DRM_ERROR("Switching back to LCPLL failed\n");
9671 mutex_lock(&dev_priv
->rps
.hw_lock
);
9672 sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
, data
);
9673 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9675 I915_WRITE(CDCLK_FREQ
, DIV_ROUND_CLOSEST(cdclk
, 1000) - 1);
9677 intel_update_cdclk(dev
);
9679 WARN(cdclk
!= dev_priv
->cdclk_freq
,
9680 "cdclk requested %d kHz but got %d kHz\n",
9681 cdclk
, dev_priv
->cdclk_freq
);
9684 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state
*state
)
9686 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9687 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
9688 int max_pixclk
= ilk_max_pixel_rate(state
);
9692 * FIXME should also account for plane ratio
9693 * once 64bpp pixel formats are supported.
9695 if (max_pixclk
> 540000)
9697 else if (max_pixclk
> 450000)
9699 else if (max_pixclk
> 337500)
9704 if (cdclk
> dev_priv
->max_cdclk_freq
) {
9705 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9706 cdclk
, dev_priv
->max_cdclk_freq
);
9710 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
9711 if (!intel_state
->active_crtcs
)
9712 intel_state
->dev_cdclk
= 337500;
9717 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9719 struct drm_device
*dev
= old_state
->dev
;
9720 struct intel_atomic_state
*old_intel_state
=
9721 to_intel_atomic_state(old_state
);
9722 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
9724 broadwell_set_cdclk(dev
, req_cdclk
);
9727 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9728 struct intel_crtc_state
*crtc_state
)
9730 struct intel_encoder
*intel_encoder
=
9731 intel_ddi_get_crtc_new_encoder(crtc_state
);
9733 if (intel_encoder
->type
!= INTEL_OUTPUT_DSI
) {
9734 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9738 crtc
->lowfreq_avail
= false;
9743 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9745 struct intel_crtc_state
*pipe_config
)
9747 enum intel_dpll_id id
;
9751 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9752 id
= DPLL_ID_SKL_DPLL0
;
9755 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9756 id
= DPLL_ID_SKL_DPLL1
;
9759 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9760 id
= DPLL_ID_SKL_DPLL2
;
9763 DRM_ERROR("Incorrect port type\n");
9767 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9770 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9772 struct intel_crtc_state
*pipe_config
)
9774 enum intel_dpll_id id
;
9777 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9778 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9780 switch (pipe_config
->ddi_pll_sel
) {
9782 id
= DPLL_ID_SKL_DPLL0
;
9785 id
= DPLL_ID_SKL_DPLL1
;
9788 id
= DPLL_ID_SKL_DPLL2
;
9791 id
= DPLL_ID_SKL_DPLL3
;
9794 MISSING_CASE(pipe_config
->ddi_pll_sel
);
9798 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9801 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9803 struct intel_crtc_state
*pipe_config
)
9805 enum intel_dpll_id id
;
9807 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9809 switch (pipe_config
->ddi_pll_sel
) {
9810 case PORT_CLK_SEL_WRPLL1
:
9811 id
= DPLL_ID_WRPLL1
;
9813 case PORT_CLK_SEL_WRPLL2
:
9814 id
= DPLL_ID_WRPLL2
;
9816 case PORT_CLK_SEL_SPLL
:
9819 case PORT_CLK_SEL_LCPLL_810
:
9820 id
= DPLL_ID_LCPLL_810
;
9822 case PORT_CLK_SEL_LCPLL_1350
:
9823 id
= DPLL_ID_LCPLL_1350
;
9825 case PORT_CLK_SEL_LCPLL_2700
:
9826 id
= DPLL_ID_LCPLL_2700
;
9829 MISSING_CASE(pipe_config
->ddi_pll_sel
);
9831 case PORT_CLK_SEL_NONE
:
9835 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9838 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
9839 struct intel_crtc_state
*pipe_config
,
9840 unsigned long *power_domain_mask
)
9842 struct drm_device
*dev
= crtc
->base
.dev
;
9843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9844 enum intel_display_power_domain power_domain
;
9847 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9850 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9851 * consistency and less surprising code; it's in always on power).
9853 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9854 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9855 enum pipe trans_edp_pipe
;
9856 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9858 WARN(1, "unknown pipe linked to edp transcoder\n");
9859 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9860 case TRANS_DDI_EDP_INPUT_A_ON
:
9861 trans_edp_pipe
= PIPE_A
;
9863 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9864 trans_edp_pipe
= PIPE_B
;
9866 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9867 trans_edp_pipe
= PIPE_C
;
9871 if (trans_edp_pipe
== crtc
->pipe
)
9872 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9875 power_domain
= POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
);
9876 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9878 *power_domain_mask
|= BIT(power_domain
);
9880 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9882 return tmp
& PIPECONF_ENABLE
;
9885 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
9886 struct intel_crtc_state
*pipe_config
,
9887 unsigned long *power_domain_mask
)
9889 struct drm_device
*dev
= crtc
->base
.dev
;
9890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9891 enum intel_display_power_domain power_domain
;
9893 enum transcoder cpu_transcoder
;
9896 pipe_config
->has_dsi_encoder
= false;
9898 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
9900 cpu_transcoder
= TRANSCODER_DSI_A
;
9902 cpu_transcoder
= TRANSCODER_DSI_C
;
9904 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
9905 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9907 *power_domain_mask
|= BIT(power_domain
);
9910 * The PLL needs to be enabled with a valid divider
9911 * configuration, otherwise accessing DSI registers will hang
9912 * the machine. See BSpec North Display Engine
9913 * registers/MIPI[BXT]. We can break out here early, since we
9914 * need the same DSI PLL to be enabled for both DSI ports.
9916 if (!intel_dsi_pll_is_enabled(dev_priv
))
9919 /* XXX: this works for video mode only */
9920 tmp
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
9921 if (!(tmp
& DPI_ENABLE
))
9924 tmp
= I915_READ(MIPI_CTRL(port
));
9925 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
9928 pipe_config
->cpu_transcoder
= cpu_transcoder
;
9929 pipe_config
->has_dsi_encoder
= true;
9933 return pipe_config
->has_dsi_encoder
;
9936 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9937 struct intel_crtc_state
*pipe_config
)
9939 struct drm_device
*dev
= crtc
->base
.dev
;
9940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9941 struct intel_shared_dpll
*pll
;
9945 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9947 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9949 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
9950 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9951 else if (IS_BROXTON(dev
))
9952 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9954 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9956 pll
= pipe_config
->shared_dpll
;
9958 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
9959 &pipe_config
->dpll_hw_state
));
9963 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9964 * DDI E. So just check whether this pipe is wired to DDI E and whether
9965 * the PCH transcoder is on.
9967 if (INTEL_INFO(dev
)->gen
< 9 &&
9968 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9969 pipe_config
->has_pch_encoder
= true;
9971 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9972 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9973 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9975 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9979 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9980 struct intel_crtc_state
*pipe_config
)
9982 struct drm_device
*dev
= crtc
->base
.dev
;
9983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9984 enum intel_display_power_domain power_domain
;
9985 unsigned long power_domain_mask
;
9988 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9989 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9991 power_domain_mask
= BIT(power_domain
);
9993 pipe_config
->shared_dpll
= NULL
;
9995 active
= hsw_get_transcoder_state(crtc
, pipe_config
, &power_domain_mask
);
9997 if (IS_BROXTON(dev_priv
)) {
9998 bxt_get_dsi_transcoder_state(crtc
, pipe_config
,
9999 &power_domain_mask
);
10000 WARN_ON(active
&& pipe_config
->has_dsi_encoder
);
10001 if (pipe_config
->has_dsi_encoder
)
10008 if (!pipe_config
->has_dsi_encoder
) {
10009 haswell_get_ddi_port_state(crtc
, pipe_config
);
10010 intel_get_pipe_timings(crtc
, pipe_config
);
10013 intel_get_pipe_src_size(crtc
, pipe_config
);
10015 pipe_config
->gamma_mode
=
10016 I915_READ(GAMMA_MODE(crtc
->pipe
)) & GAMMA_MODE_MODE_MASK
;
10018 if (INTEL_INFO(dev
)->gen
>= 9) {
10019 skl_init_scalers(dev
, crtc
, pipe_config
);
10022 if (INTEL_INFO(dev
)->gen
>= 9) {
10023 pipe_config
->scaler_state
.scaler_id
= -1;
10024 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
10027 power_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
10028 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
10029 power_domain_mask
|= BIT(power_domain
);
10030 if (INTEL_INFO(dev
)->gen
>= 9)
10031 skylake_get_pfit_config(crtc
, pipe_config
);
10033 ironlake_get_pfit_config(crtc
, pipe_config
);
10036 if (IS_HASWELL(dev
))
10037 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
10038 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
10040 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
10041 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10042 pipe_config
->pixel_multiplier
=
10043 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
10045 pipe_config
->pixel_multiplier
= 1;
10049 for_each_power_domain(power_domain
, power_domain_mask
)
10050 intel_display_power_put(dev_priv
, power_domain
);
10055 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10056 const struct intel_plane_state
*plane_state
)
10058 struct drm_device
*dev
= crtc
->dev
;
10059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10060 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10061 uint32_t cntl
= 0, size
= 0;
10063 if (plane_state
&& plane_state
->visible
) {
10064 unsigned int width
= plane_state
->base
.crtc_w
;
10065 unsigned int height
= plane_state
->base
.crtc_h
;
10066 unsigned int stride
= roundup_pow_of_two(width
) * 4;
10070 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10081 cntl
|= CURSOR_ENABLE
|
10082 CURSOR_GAMMA_ENABLE
|
10083 CURSOR_FORMAT_ARGB
|
10084 CURSOR_STRIDE(stride
);
10086 size
= (height
<< 12) | width
;
10089 if (intel_crtc
->cursor_cntl
!= 0 &&
10090 (intel_crtc
->cursor_base
!= base
||
10091 intel_crtc
->cursor_size
!= size
||
10092 intel_crtc
->cursor_cntl
!= cntl
)) {
10093 /* On these chipsets we can only modify the base/size/stride
10094 * whilst the cursor is disabled.
10096 I915_WRITE(CURCNTR(PIPE_A
), 0);
10097 POSTING_READ(CURCNTR(PIPE_A
));
10098 intel_crtc
->cursor_cntl
= 0;
10101 if (intel_crtc
->cursor_base
!= base
) {
10102 I915_WRITE(CURBASE(PIPE_A
), base
);
10103 intel_crtc
->cursor_base
= base
;
10106 if (intel_crtc
->cursor_size
!= size
) {
10107 I915_WRITE(CURSIZE
, size
);
10108 intel_crtc
->cursor_size
= size
;
10111 if (intel_crtc
->cursor_cntl
!= cntl
) {
10112 I915_WRITE(CURCNTR(PIPE_A
), cntl
);
10113 POSTING_READ(CURCNTR(PIPE_A
));
10114 intel_crtc
->cursor_cntl
= cntl
;
10118 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10119 const struct intel_plane_state
*plane_state
)
10121 struct drm_device
*dev
= crtc
->dev
;
10122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10123 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10124 int pipe
= intel_crtc
->pipe
;
10127 if (plane_state
&& plane_state
->visible
) {
10128 cntl
= MCURSOR_GAMMA_ENABLE
;
10129 switch (plane_state
->base
.crtc_w
) {
10131 cntl
|= CURSOR_MODE_64_ARGB_AX
;
10134 cntl
|= CURSOR_MODE_128_ARGB_AX
;
10137 cntl
|= CURSOR_MODE_256_ARGB_AX
;
10140 MISSING_CASE(plane_state
->base
.crtc_w
);
10143 cntl
|= pipe
<< 28; /* Connect to correct pipe */
10146 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
10148 if (plane_state
->base
.rotation
== BIT(DRM_ROTATE_180
))
10149 cntl
|= CURSOR_ROTATE_180
;
10152 if (intel_crtc
->cursor_cntl
!= cntl
) {
10153 I915_WRITE(CURCNTR(pipe
), cntl
);
10154 POSTING_READ(CURCNTR(pipe
));
10155 intel_crtc
->cursor_cntl
= cntl
;
10158 /* and commit changes on next vblank */
10159 I915_WRITE(CURBASE(pipe
), base
);
10160 POSTING_READ(CURBASE(pipe
));
10162 intel_crtc
->cursor_base
= base
;
10165 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10166 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
10167 const struct intel_plane_state
*plane_state
)
10169 struct drm_device
*dev
= crtc
->dev
;
10170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10171 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10172 int pipe
= intel_crtc
->pipe
;
10173 u32 base
= intel_crtc
->cursor_addr
;
10177 int x
= plane_state
->base
.crtc_x
;
10178 int y
= plane_state
->base
.crtc_y
;
10181 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10184 pos
|= x
<< CURSOR_X_SHIFT
;
10187 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10190 pos
|= y
<< CURSOR_Y_SHIFT
;
10192 /* ILK+ do this automagically */
10193 if (HAS_GMCH_DISPLAY(dev
) &&
10194 plane_state
->base
.rotation
== BIT(DRM_ROTATE_180
)) {
10195 base
+= (plane_state
->base
.crtc_h
*
10196 plane_state
->base
.crtc_w
- 1) * 4;
10200 I915_WRITE(CURPOS(pipe
), pos
);
10202 if (IS_845G(dev
) || IS_I865G(dev
))
10203 i845_update_cursor(crtc
, base
, plane_state
);
10205 i9xx_update_cursor(crtc
, base
, plane_state
);
10208 static bool cursor_size_ok(struct drm_device
*dev
,
10209 uint32_t width
, uint32_t height
)
10211 if (width
== 0 || height
== 0)
10215 * 845g/865g are special in that they are only limited by
10216 * the width of their cursors, the height is arbitrary up to
10217 * the precision of the register. Everything else requires
10218 * square cursors, limited to a few power-of-two sizes.
10220 if (IS_845G(dev
) || IS_I865G(dev
)) {
10221 if ((width
& 63) != 0)
10224 if (width
> (IS_845G(dev
) ? 64 : 512))
10230 switch (width
| height
) {
10245 /* VESA 640x480x72Hz mode to set on the pipe */
10246 static struct drm_display_mode load_detect_mode
= {
10247 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10248 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10251 struct drm_framebuffer
*
10252 __intel_framebuffer_create(struct drm_device
*dev
,
10253 struct drm_mode_fb_cmd2
*mode_cmd
,
10254 struct drm_i915_gem_object
*obj
)
10256 struct intel_framebuffer
*intel_fb
;
10259 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10261 return ERR_PTR(-ENOMEM
);
10263 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
10267 return &intel_fb
->base
;
10271 return ERR_PTR(ret
);
10274 static struct drm_framebuffer
*
10275 intel_framebuffer_create(struct drm_device
*dev
,
10276 struct drm_mode_fb_cmd2
*mode_cmd
,
10277 struct drm_i915_gem_object
*obj
)
10279 struct drm_framebuffer
*fb
;
10282 ret
= i915_mutex_lock_interruptible(dev
);
10284 return ERR_PTR(ret
);
10285 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
10286 mutex_unlock(&dev
->struct_mutex
);
10292 intel_framebuffer_pitch_for_width(int width
, int bpp
)
10294 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
10295 return ALIGN(pitch
, 64);
10299 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
10301 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
10302 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
10305 static struct drm_framebuffer
*
10306 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
10307 struct drm_display_mode
*mode
,
10308 int depth
, int bpp
)
10310 struct drm_framebuffer
*fb
;
10311 struct drm_i915_gem_object
*obj
;
10312 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
10314 obj
= i915_gem_object_create(dev
,
10315 intel_framebuffer_size_for_mode(mode
, bpp
));
10317 return ERR_CAST(obj
);
10319 mode_cmd
.width
= mode
->hdisplay
;
10320 mode_cmd
.height
= mode
->vdisplay
;
10321 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
10323 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
10325 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
10327 drm_gem_object_unreference_unlocked(&obj
->base
);
10332 static struct drm_framebuffer
*
10333 mode_fits_in_fbdev(struct drm_device
*dev
,
10334 struct drm_display_mode
*mode
)
10336 #ifdef CONFIG_DRM_FBDEV_EMULATION
10337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10338 struct drm_i915_gem_object
*obj
;
10339 struct drm_framebuffer
*fb
;
10341 if (!dev_priv
->fbdev
)
10344 if (!dev_priv
->fbdev
->fb
)
10347 obj
= dev_priv
->fbdev
->fb
->obj
;
10350 fb
= &dev_priv
->fbdev
->fb
->base
;
10351 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
10352 fb
->bits_per_pixel
))
10355 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
10358 drm_framebuffer_reference(fb
);
10365 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
10366 struct drm_crtc
*crtc
,
10367 struct drm_display_mode
*mode
,
10368 struct drm_framebuffer
*fb
,
10371 struct drm_plane_state
*plane_state
;
10372 int hdisplay
, vdisplay
;
10375 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
10376 if (IS_ERR(plane_state
))
10377 return PTR_ERR(plane_state
);
10380 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
10382 hdisplay
= vdisplay
= 0;
10384 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
10387 drm_atomic_set_fb_for_plane(plane_state
, fb
);
10388 plane_state
->crtc_x
= 0;
10389 plane_state
->crtc_y
= 0;
10390 plane_state
->crtc_w
= hdisplay
;
10391 plane_state
->crtc_h
= vdisplay
;
10392 plane_state
->src_x
= x
<< 16;
10393 plane_state
->src_y
= y
<< 16;
10394 plane_state
->src_w
= hdisplay
<< 16;
10395 plane_state
->src_h
= vdisplay
<< 16;
10400 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
10401 struct drm_display_mode
*mode
,
10402 struct intel_load_detect_pipe
*old
,
10403 struct drm_modeset_acquire_ctx
*ctx
)
10405 struct intel_crtc
*intel_crtc
;
10406 struct intel_encoder
*intel_encoder
=
10407 intel_attached_encoder(connector
);
10408 struct drm_crtc
*possible_crtc
;
10409 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10410 struct drm_crtc
*crtc
= NULL
;
10411 struct drm_device
*dev
= encoder
->dev
;
10412 struct drm_framebuffer
*fb
;
10413 struct drm_mode_config
*config
= &dev
->mode_config
;
10414 struct drm_atomic_state
*state
= NULL
, *restore_state
= NULL
;
10415 struct drm_connector_state
*connector_state
;
10416 struct intel_crtc_state
*crtc_state
;
10419 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10420 connector
->base
.id
, connector
->name
,
10421 encoder
->base
.id
, encoder
->name
);
10423 old
->restore_state
= NULL
;
10426 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
10431 * Algorithm gets a little messy:
10433 * - if the connector already has an assigned crtc, use it (but make
10434 * sure it's on first)
10436 * - try to find the first unused crtc that can drive this connector,
10437 * and use that if we find one
10440 /* See if we already have a CRTC for this connector */
10441 if (connector
->state
->crtc
) {
10442 crtc
= connector
->state
->crtc
;
10444 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10448 /* Make sure the crtc and connector are running */
10452 /* Find an unused one (if possible) */
10453 for_each_crtc(dev
, possible_crtc
) {
10455 if (!(encoder
->possible_crtcs
& (1 << i
)))
10458 ret
= drm_modeset_lock(&possible_crtc
->mutex
, ctx
);
10462 if (possible_crtc
->state
->enable
) {
10463 drm_modeset_unlock(&possible_crtc
->mutex
);
10467 crtc
= possible_crtc
;
10472 * If we didn't find an unused CRTC, don't use any.
10475 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10480 intel_crtc
= to_intel_crtc(crtc
);
10482 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10486 state
= drm_atomic_state_alloc(dev
);
10487 restore_state
= drm_atomic_state_alloc(dev
);
10488 if (!state
|| !restore_state
) {
10493 state
->acquire_ctx
= ctx
;
10494 restore_state
->acquire_ctx
= ctx
;
10496 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10497 if (IS_ERR(connector_state
)) {
10498 ret
= PTR_ERR(connector_state
);
10502 ret
= drm_atomic_set_crtc_for_connector(connector_state
, crtc
);
10506 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10507 if (IS_ERR(crtc_state
)) {
10508 ret
= PTR_ERR(crtc_state
);
10512 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10515 mode
= &load_detect_mode
;
10517 /* We need a framebuffer large enough to accommodate all accesses
10518 * that the plane may generate whilst we perform load detection.
10519 * We can not rely on the fbcon either being present (we get called
10520 * during its initialisation to detect all boot displays, or it may
10521 * not even exist) or that it is large enough to satisfy the
10524 fb
= mode_fits_in_fbdev(dev
, mode
);
10526 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10527 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
10529 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10531 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10535 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
10539 drm_framebuffer_unreference(fb
);
10541 ret
= drm_atomic_set_mode_for_crtc(&crtc_state
->base
, mode
);
10545 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state
, connector
));
10547 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state
, crtc
));
10549 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state
, crtc
->primary
));
10551 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret
);
10555 ret
= drm_atomic_commit(state
);
10557 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10561 old
->restore_state
= restore_state
;
10563 /* let the connector get through one full cycle before testing */
10564 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
10568 drm_atomic_state_free(state
);
10569 drm_atomic_state_free(restore_state
);
10570 restore_state
= state
= NULL
;
10572 if (ret
== -EDEADLK
) {
10573 drm_modeset_backoff(ctx
);
10580 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10581 struct intel_load_detect_pipe
*old
,
10582 struct drm_modeset_acquire_ctx
*ctx
)
10584 struct intel_encoder
*intel_encoder
=
10585 intel_attached_encoder(connector
);
10586 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10587 struct drm_atomic_state
*state
= old
->restore_state
;
10590 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10591 connector
->base
.id
, connector
->name
,
10592 encoder
->base
.id
, encoder
->name
);
10597 ret
= drm_atomic_commit(state
);
10599 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret
);
10600 drm_atomic_state_free(state
);
10604 static int i9xx_pll_refclk(struct drm_device
*dev
,
10605 const struct intel_crtc_state
*pipe_config
)
10607 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10608 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10610 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10611 return dev_priv
->vbt
.lvds_ssc_freq
;
10612 else if (HAS_PCH_SPLIT(dev
))
10614 else if (!IS_GEN2(dev
))
10620 /* Returns the clock of the currently programmed mode of the given pipe. */
10621 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10622 struct intel_crtc_state
*pipe_config
)
10624 struct drm_device
*dev
= crtc
->base
.dev
;
10625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10626 int pipe
= pipe_config
->cpu_transcoder
;
10627 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10629 intel_clock_t clock
;
10631 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10633 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10634 fp
= pipe_config
->dpll_hw_state
.fp0
;
10636 fp
= pipe_config
->dpll_hw_state
.fp1
;
10638 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10639 if (IS_PINEVIEW(dev
)) {
10640 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10641 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10643 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10644 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10647 if (!IS_GEN2(dev
)) {
10648 if (IS_PINEVIEW(dev
))
10649 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10650 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10652 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10653 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10655 switch (dpll
& DPLL_MODE_MASK
) {
10656 case DPLLB_MODE_DAC_SERIAL
:
10657 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10660 case DPLLB_MODE_LVDS
:
10661 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10665 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10666 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10670 if (IS_PINEVIEW(dev
))
10671 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
10673 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10675 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10676 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10679 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10680 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10682 if (lvds
& LVDS_CLKB_POWER_UP
)
10687 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10690 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10691 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10693 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10699 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10703 * This value includes pixel_multiplier. We will use
10704 * port_clock to compute adjusted_mode.crtc_clock in the
10705 * encoder's get_config() function.
10707 pipe_config
->port_clock
= port_clock
;
10710 int intel_dotclock_calculate(int link_freq
,
10711 const struct intel_link_m_n
*m_n
)
10714 * The calculation for the data clock is:
10715 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10716 * But we want to avoid losing precison if possible, so:
10717 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10719 * and the link clock is simpler:
10720 * link_clock = (m * link_clock) / n
10726 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10729 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10730 struct intel_crtc_state
*pipe_config
)
10732 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10734 /* read out port_clock from the DPLL */
10735 i9xx_crtc_clock_get(crtc
, pipe_config
);
10738 * In case there is an active pipe without active ports,
10739 * we may need some idea for the dotclock anyway.
10740 * Calculate one based on the FDI configuration.
10742 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10743 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
10744 &pipe_config
->fdi_m_n
);
10747 /** Returns the currently programmed mode of the given pipe. */
10748 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10749 struct drm_crtc
*crtc
)
10751 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10752 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10753 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10754 struct drm_display_mode
*mode
;
10755 struct intel_crtc_state
*pipe_config
;
10756 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10757 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10758 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10759 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10760 enum pipe pipe
= intel_crtc
->pipe
;
10762 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10766 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10767 if (!pipe_config
) {
10773 * Construct a pipe_config sufficient for getting the clock info
10774 * back out of crtc_clock_get.
10776 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10777 * to use a real value here instead.
10779 pipe_config
->cpu_transcoder
= (enum transcoder
) pipe
;
10780 pipe_config
->pixel_multiplier
= 1;
10781 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10782 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10783 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10784 i9xx_crtc_clock_get(intel_crtc
, pipe_config
);
10786 mode
->clock
= pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
10787 mode
->hdisplay
= (htot
& 0xffff) + 1;
10788 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10789 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10790 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10791 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10792 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10793 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10794 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10796 drm_mode_set_name(mode
);
10798 kfree(pipe_config
);
10803 void intel_mark_busy(struct drm_i915_private
*dev_priv
)
10805 if (dev_priv
->mm
.busy
)
10808 intel_runtime_pm_get(dev_priv
);
10809 i915_update_gfx_val(dev_priv
);
10810 if (INTEL_GEN(dev_priv
) >= 6)
10811 gen6_rps_busy(dev_priv
);
10812 dev_priv
->mm
.busy
= true;
10815 void intel_mark_idle(struct drm_i915_private
*dev_priv
)
10817 if (!dev_priv
->mm
.busy
)
10820 dev_priv
->mm
.busy
= false;
10822 if (INTEL_GEN(dev_priv
) >= 6)
10823 gen6_rps_idle(dev_priv
);
10825 intel_runtime_pm_put(dev_priv
);
10828 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10830 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10831 struct drm_device
*dev
= crtc
->dev
;
10832 struct intel_unpin_work
*work
;
10834 spin_lock_irq(&dev
->event_lock
);
10835 work
= intel_crtc
->unpin_work
;
10836 intel_crtc
->unpin_work
= NULL
;
10837 spin_unlock_irq(&dev
->event_lock
);
10840 cancel_work_sync(&work
->work
);
10844 drm_crtc_cleanup(crtc
);
10849 static void intel_unpin_work_fn(struct work_struct
*__work
)
10851 struct intel_unpin_work
*work
=
10852 container_of(__work
, struct intel_unpin_work
, work
);
10853 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
10854 struct drm_device
*dev
= crtc
->base
.dev
;
10855 struct drm_plane
*primary
= crtc
->base
.primary
;
10857 mutex_lock(&dev
->struct_mutex
);
10858 intel_unpin_fb_obj(work
->old_fb
, primary
->state
->rotation
);
10859 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10861 if (work
->flip_queued_req
)
10862 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10863 mutex_unlock(&dev
->struct_mutex
);
10865 intel_frontbuffer_flip_complete(dev
, to_intel_plane(primary
)->frontbuffer_bit
);
10866 intel_fbc_post_update(crtc
);
10867 drm_framebuffer_unreference(work
->old_fb
);
10869 BUG_ON(atomic_read(&crtc
->unpin_work_count
) == 0);
10870 atomic_dec(&crtc
->unpin_work_count
);
10875 static void do_intel_finish_page_flip(struct drm_i915_private
*dev_priv
,
10876 struct drm_crtc
*crtc
)
10878 struct drm_device
*dev
= dev_priv
->dev
;
10879 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10880 struct intel_unpin_work
*work
;
10881 unsigned long flags
;
10883 /* Ignore early vblank irqs */
10884 if (intel_crtc
== NULL
)
10888 * This is called both by irq handlers and the reset code (to complete
10889 * lost pageflips) so needs the full irqsave spinlocks.
10891 spin_lock_irqsave(&dev
->event_lock
, flags
);
10892 work
= intel_crtc
->unpin_work
;
10894 /* Ensure we don't miss a work->pending update ... */
10897 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
10898 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10902 page_flip_completed(intel_crtc
);
10904 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10907 void intel_finish_page_flip(struct drm_i915_private
*dev_priv
, int pipe
)
10909 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10911 do_intel_finish_page_flip(dev_priv
, crtc
);
10914 void intel_finish_page_flip_plane(struct drm_i915_private
*dev_priv
, int plane
)
10916 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
10918 do_intel_finish_page_flip(dev_priv
, crtc
);
10921 /* Is 'a' after or equal to 'b'? */
10922 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10924 return !((a
- b
) & 0x80000000);
10927 static bool page_flip_finished(struct intel_crtc
*crtc
)
10929 struct drm_device
*dev
= crtc
->base
.dev
;
10930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10931 unsigned reset_counter
;
10933 reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
10934 if (crtc
->reset_counter
!= reset_counter
)
10938 * The relevant registers doen't exist on pre-ctg.
10939 * As the flip done interrupt doesn't trigger for mmio
10940 * flips on gmch platforms, a flip count check isn't
10941 * really needed there. But since ctg has the registers,
10942 * include it in the check anyway.
10944 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
10948 * BDW signals flip done immediately if the plane
10949 * is disabled, even if the plane enable is already
10950 * armed to occur at the next vblank :(
10954 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10955 * used the same base address. In that case the mmio flip might
10956 * have completed, but the CS hasn't even executed the flip yet.
10958 * A flip count check isn't enough as the CS might have updated
10959 * the base address just after start of vblank, but before we
10960 * managed to process the interrupt. This means we'd complete the
10961 * CS flip too soon.
10963 * Combining both checks should get us a good enough result. It may
10964 * still happen that the CS flip has been executed, but has not
10965 * yet actually completed. But in case the base address is the same
10966 * anyway, we don't really care.
10968 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
10969 crtc
->unpin_work
->gtt_offset
&&
10970 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc
->pipe
)),
10971 crtc
->unpin_work
->flip_count
);
10974 void intel_prepare_page_flip(struct drm_i915_private
*dev_priv
, int plane
)
10976 struct drm_device
*dev
= dev_priv
->dev
;
10977 struct intel_crtc
*intel_crtc
=
10978 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
10979 unsigned long flags
;
10983 * This is called both by irq handlers and the reset code (to complete
10984 * lost pageflips) so needs the full irqsave spinlocks.
10986 * NB: An MMIO update of the plane base pointer will also
10987 * generate a page-flip completion irq, i.e. every modeset
10988 * is also accompanied by a spurious intel_prepare_page_flip().
10990 spin_lock_irqsave(&dev
->event_lock
, flags
);
10991 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
10992 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
10993 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10996 static inline void intel_mark_page_flip_active(struct intel_unpin_work
*work
)
10998 /* Ensure that the work item is consistent when activating it ... */
11000 atomic_set(&work
->pending
, INTEL_FLIP_PENDING
);
11001 /* and that it is marked active as soon as the irq could fire. */
11005 static int intel_gen2_queue_flip(struct drm_device
*dev
,
11006 struct drm_crtc
*crtc
,
11007 struct drm_framebuffer
*fb
,
11008 struct drm_i915_gem_object
*obj
,
11009 struct drm_i915_gem_request
*req
,
11012 struct intel_engine_cs
*engine
= req
->engine
;
11013 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11017 ret
= intel_ring_begin(req
, 6);
11021 /* Can't queue multiple flips, so wait for the previous
11022 * one to finish before executing the next.
11024 if (intel_crtc
->plane
)
11025 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11027 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11028 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| flip_mask
);
11029 intel_ring_emit(engine
, MI_NOOP
);
11030 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11031 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11032 intel_ring_emit(engine
, fb
->pitches
[0]);
11033 intel_ring_emit(engine
, intel_crtc
->unpin_work
->gtt_offset
);
11034 intel_ring_emit(engine
, 0); /* aux display base address, unused */
11036 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
11040 static int intel_gen3_queue_flip(struct drm_device
*dev
,
11041 struct drm_crtc
*crtc
,
11042 struct drm_framebuffer
*fb
,
11043 struct drm_i915_gem_object
*obj
,
11044 struct drm_i915_gem_request
*req
,
11047 struct intel_engine_cs
*engine
= req
->engine
;
11048 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11052 ret
= intel_ring_begin(req
, 6);
11056 if (intel_crtc
->plane
)
11057 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11059 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11060 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| flip_mask
);
11061 intel_ring_emit(engine
, MI_NOOP
);
11062 intel_ring_emit(engine
, MI_DISPLAY_FLIP_I915
|
11063 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11064 intel_ring_emit(engine
, fb
->pitches
[0]);
11065 intel_ring_emit(engine
, intel_crtc
->unpin_work
->gtt_offset
);
11066 intel_ring_emit(engine
, MI_NOOP
);
11068 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
11072 static int intel_gen4_queue_flip(struct drm_device
*dev
,
11073 struct drm_crtc
*crtc
,
11074 struct drm_framebuffer
*fb
,
11075 struct drm_i915_gem_object
*obj
,
11076 struct drm_i915_gem_request
*req
,
11079 struct intel_engine_cs
*engine
= req
->engine
;
11080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11081 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11082 uint32_t pf
, pipesrc
;
11085 ret
= intel_ring_begin(req
, 4);
11089 /* i965+ uses the linear or tiled offsets from the
11090 * Display Registers (which do not change across a page-flip)
11091 * so we need only reprogram the base address.
11093 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11094 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11095 intel_ring_emit(engine
, fb
->pitches
[0]);
11096 intel_ring_emit(engine
, intel_crtc
->unpin_work
->gtt_offset
|
11099 /* XXX Enabling the panel-fitter across page-flip is so far
11100 * untested on non-native modes, so ignore it for now.
11101 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11104 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11105 intel_ring_emit(engine
, pf
| pipesrc
);
11107 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
11111 static int intel_gen6_queue_flip(struct drm_device
*dev
,
11112 struct drm_crtc
*crtc
,
11113 struct drm_framebuffer
*fb
,
11114 struct drm_i915_gem_object
*obj
,
11115 struct drm_i915_gem_request
*req
,
11118 struct intel_engine_cs
*engine
= req
->engine
;
11119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11120 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11121 uint32_t pf
, pipesrc
;
11124 ret
= intel_ring_begin(req
, 4);
11128 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11129 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11130 intel_ring_emit(engine
, fb
->pitches
[0] | obj
->tiling_mode
);
11131 intel_ring_emit(engine
, intel_crtc
->unpin_work
->gtt_offset
);
11133 /* Contrary to the suggestions in the documentation,
11134 * "Enable Panel Fitter" does not seem to be required when page
11135 * flipping with a non-native mode, and worse causes a normal
11137 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11140 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11141 intel_ring_emit(engine
, pf
| pipesrc
);
11143 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
11147 static int intel_gen7_queue_flip(struct drm_device
*dev
,
11148 struct drm_crtc
*crtc
,
11149 struct drm_framebuffer
*fb
,
11150 struct drm_i915_gem_object
*obj
,
11151 struct drm_i915_gem_request
*req
,
11154 struct intel_engine_cs
*engine
= req
->engine
;
11155 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11156 uint32_t plane_bit
= 0;
11159 switch (intel_crtc
->plane
) {
11161 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
11164 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
11167 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
11170 WARN_ONCE(1, "unknown plane in flip command\n");
11175 if (engine
->id
== RCS
) {
11178 * On Gen 8, SRM is now taking an extra dword to accommodate
11179 * 48bits addresses, and we need a NOOP for the batch size to
11187 * BSpec MI_DISPLAY_FLIP for IVB:
11188 * "The full packet must be contained within the same cache line."
11190 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11191 * cacheline, if we ever start emitting more commands before
11192 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11193 * then do the cacheline alignment, and finally emit the
11196 ret
= intel_ring_cacheline_align(req
);
11200 ret
= intel_ring_begin(req
, len
);
11204 /* Unmask the flip-done completion message. Note that the bspec says that
11205 * we should do this for both the BCS and RCS, and that we must not unmask
11206 * more than one flip event at any time (or ensure that one flip message
11207 * can be sent by waiting for flip-done prior to queueing new flips).
11208 * Experimentation says that BCS works despite DERRMR masking all
11209 * flip-done completion events and that unmasking all planes at once
11210 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11211 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11213 if (engine
->id
== RCS
) {
11214 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
11215 intel_ring_emit_reg(engine
, DERRMR
);
11216 intel_ring_emit(engine
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
11217 DERRMR_PIPEB_PRI_FLIP_DONE
|
11218 DERRMR_PIPEC_PRI_FLIP_DONE
));
11220 intel_ring_emit(engine
, MI_STORE_REGISTER_MEM_GEN8
|
11221 MI_SRM_LRM_GLOBAL_GTT
);
11223 intel_ring_emit(engine
, MI_STORE_REGISTER_MEM
|
11224 MI_SRM_LRM_GLOBAL_GTT
);
11225 intel_ring_emit_reg(engine
, DERRMR
);
11226 intel_ring_emit(engine
, engine
->scratch
.gtt_offset
+ 256);
11227 if (IS_GEN8(dev
)) {
11228 intel_ring_emit(engine
, 0);
11229 intel_ring_emit(engine
, MI_NOOP
);
11233 intel_ring_emit(engine
, MI_DISPLAY_FLIP_I915
| plane_bit
);
11234 intel_ring_emit(engine
, (fb
->pitches
[0] | obj
->tiling_mode
));
11235 intel_ring_emit(engine
, intel_crtc
->unpin_work
->gtt_offset
);
11236 intel_ring_emit(engine
, (MI_NOOP
));
11238 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
11242 static bool use_mmio_flip(struct intel_engine_cs
*engine
,
11243 struct drm_i915_gem_object
*obj
)
11246 * This is not being used for older platforms, because
11247 * non-availability of flip done interrupt forces us to use
11248 * CS flips. Older platforms derive flip done using some clever
11249 * tricks involving the flip_pending status bits and vblank irqs.
11250 * So using MMIO flips there would disrupt this mechanism.
11253 if (engine
== NULL
)
11256 if (INTEL_GEN(engine
->i915
) < 5)
11259 if (i915
.use_mmio_flip
< 0)
11261 else if (i915
.use_mmio_flip
> 0)
11263 else if (i915
.enable_execlists
)
11265 else if (obj
->base
.dma_buf
&&
11266 !reservation_object_test_signaled_rcu(obj
->base
.dma_buf
->resv
,
11270 return engine
!= i915_gem_request_get_engine(obj
->last_write_req
);
11273 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
,
11274 unsigned int rotation
,
11275 struct intel_unpin_work
*work
)
11277 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11278 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11279 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
11280 const enum pipe pipe
= intel_crtc
->pipe
;
11281 u32 ctl
, stride
, tile_height
;
11283 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
11284 ctl
&= ~PLANE_CTL_TILED_MASK
;
11285 switch (fb
->modifier
[0]) {
11286 case DRM_FORMAT_MOD_NONE
:
11288 case I915_FORMAT_MOD_X_TILED
:
11289 ctl
|= PLANE_CTL_TILED_X
;
11291 case I915_FORMAT_MOD_Y_TILED
:
11292 ctl
|= PLANE_CTL_TILED_Y
;
11294 case I915_FORMAT_MOD_Yf_TILED
:
11295 ctl
|= PLANE_CTL_TILED_YF
;
11298 MISSING_CASE(fb
->modifier
[0]);
11302 * The stride is either expressed as a multiple of 64 bytes chunks for
11303 * linear buffers or in number of tiles for tiled buffers.
11305 if (intel_rotation_90_or_270(rotation
)) {
11306 /* stride = Surface height in tiles */
11307 tile_height
= intel_tile_height(dev_priv
, fb
->modifier
[0], 0);
11308 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
11310 stride
= fb
->pitches
[0] /
11311 intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
11316 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11317 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11319 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
11320 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
11322 I915_WRITE(PLANE_SURF(pipe
, 0), work
->gtt_offset
);
11323 POSTING_READ(PLANE_SURF(pipe
, 0));
11326 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
,
11327 struct intel_unpin_work
*work
)
11329 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11331 struct intel_framebuffer
*intel_fb
=
11332 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
11333 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11334 i915_reg_t reg
= DSPCNTR(intel_crtc
->plane
);
11337 dspcntr
= I915_READ(reg
);
11339 if (obj
->tiling_mode
!= I915_TILING_NONE
)
11340 dspcntr
|= DISPPLANE_TILED
;
11342 dspcntr
&= ~DISPPLANE_TILED
;
11344 I915_WRITE(reg
, dspcntr
);
11346 I915_WRITE(DSPSURF(intel_crtc
->plane
), work
->gtt_offset
);
11347 POSTING_READ(DSPSURF(intel_crtc
->plane
));
11351 * XXX: This is the temporary way to update the plane registers until we get
11352 * around to using the usual plane update functions for MMIO flips
11354 static void intel_do_mmio_flip(struct intel_mmio_flip
*mmio_flip
)
11356 struct intel_crtc
*crtc
= mmio_flip
->crtc
;
11357 struct intel_unpin_work
*work
;
11359 spin_lock_irq(&crtc
->base
.dev
->event_lock
);
11360 work
= crtc
->unpin_work
;
11361 spin_unlock_irq(&crtc
->base
.dev
->event_lock
);
11365 intel_mark_page_flip_active(work
);
11367 intel_pipe_update_start(crtc
);
11369 if (INTEL_INFO(mmio_flip
->i915
)->gen
>= 9)
11370 skl_do_mmio_flip(crtc
, mmio_flip
->rotation
, work
);
11372 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11373 ilk_do_mmio_flip(crtc
, work
);
11375 intel_pipe_update_end(crtc
);
11378 static void intel_mmio_flip_work_func(struct work_struct
*work
)
11380 struct intel_mmio_flip
*mmio_flip
=
11381 container_of(work
, struct intel_mmio_flip
, work
);
11382 struct intel_framebuffer
*intel_fb
=
11383 to_intel_framebuffer(mmio_flip
->crtc
->base
.primary
->fb
);
11384 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11386 if (mmio_flip
->req
) {
11387 WARN_ON(__i915_wait_request(mmio_flip
->req
,
11389 &mmio_flip
->i915
->rps
.mmioflips
));
11390 i915_gem_request_unreference(mmio_flip
->req
);
11393 /* For framebuffer backed by dmabuf, wait for fence */
11394 if (obj
->base
.dma_buf
)
11395 WARN_ON(reservation_object_wait_timeout_rcu(obj
->base
.dma_buf
->resv
,
11397 MAX_SCHEDULE_TIMEOUT
) < 0);
11399 intel_do_mmio_flip(mmio_flip
);
11403 static int intel_queue_mmio_flip(struct drm_device
*dev
,
11404 struct drm_crtc
*crtc
,
11405 struct drm_i915_gem_object
*obj
)
11407 struct intel_mmio_flip
*mmio_flip
;
11409 mmio_flip
= kmalloc(sizeof(*mmio_flip
), GFP_KERNEL
);
11410 if (mmio_flip
== NULL
)
11413 mmio_flip
->i915
= to_i915(dev
);
11414 mmio_flip
->req
= i915_gem_request_reference(obj
->last_write_req
);
11415 mmio_flip
->crtc
= to_intel_crtc(crtc
);
11416 mmio_flip
->rotation
= crtc
->primary
->state
->rotation
;
11418 INIT_WORK(&mmio_flip
->work
, intel_mmio_flip_work_func
);
11419 schedule_work(&mmio_flip
->work
);
11424 static int intel_default_queue_flip(struct drm_device
*dev
,
11425 struct drm_crtc
*crtc
,
11426 struct drm_framebuffer
*fb
,
11427 struct drm_i915_gem_object
*obj
,
11428 struct drm_i915_gem_request
*req
,
11434 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
11435 struct drm_crtc
*crtc
)
11437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11438 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11439 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
11442 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
11445 if (atomic_read(&work
->pending
) < INTEL_FLIP_PENDING
)
11448 if (!work
->enable_stall_check
)
11451 if (work
->flip_ready_vblank
== 0) {
11452 if (work
->flip_queued_req
&&
11453 !i915_gem_request_completed(work
->flip_queued_req
, true))
11456 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
11459 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
11462 /* Potential stall - if we see that the flip has happened,
11463 * assume a missed interrupt. */
11464 if (INTEL_INFO(dev
)->gen
>= 4)
11465 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
11467 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
11469 /* There is a potential issue here with a false positive after a flip
11470 * to the same address. We could address this by checking for a
11471 * non-incrementing frame counter.
11473 return addr
== work
->gtt_offset
;
11476 void intel_check_page_flip(struct drm_i915_private
*dev_priv
, int pipe
)
11478 struct drm_device
*dev
= dev_priv
->dev
;
11479 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11480 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11481 struct intel_unpin_work
*work
;
11483 WARN_ON(!in_interrupt());
11488 spin_lock(&dev
->event_lock
);
11489 work
= intel_crtc
->unpin_work
;
11490 if (work
!= NULL
&& __intel_pageflip_stall_check(dev
, crtc
)) {
11491 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11492 work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
11493 page_flip_completed(intel_crtc
);
11496 if (work
!= NULL
&&
11497 drm_vblank_count(dev
, pipe
) - work
->flip_queued_vblank
> 1)
11498 intel_queue_rps_boost_for_request(work
->flip_queued_req
);
11499 spin_unlock(&dev
->event_lock
);
11502 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
11503 struct drm_framebuffer
*fb
,
11504 struct drm_pending_vblank_event
*event
,
11505 uint32_t page_flip_flags
)
11507 struct drm_device
*dev
= crtc
->dev
;
11508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11509 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11510 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11511 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11512 struct drm_plane
*primary
= crtc
->primary
;
11513 enum pipe pipe
= intel_crtc
->pipe
;
11514 struct intel_unpin_work
*work
;
11515 struct intel_engine_cs
*engine
;
11517 struct drm_i915_gem_request
*request
= NULL
;
11521 * drm_mode_page_flip_ioctl() should already catch this, but double
11522 * check to be safe. In the future we may enable pageflipping from
11523 * a disabled primary plane.
11525 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
11528 /* Can't change pixel format via MI display flips. */
11529 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
11533 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11534 * Note that pitch changes could also affect these register.
11536 if (INTEL_INFO(dev
)->gen
> 3 &&
11537 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
11538 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
11541 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
11544 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
11548 work
->event
= event
;
11550 work
->old_fb
= old_fb
;
11551 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
11553 ret
= drm_crtc_vblank_get(crtc
);
11557 /* We borrow the event spin lock for protecting unpin_work */
11558 spin_lock_irq(&dev
->event_lock
);
11559 if (intel_crtc
->unpin_work
) {
11560 /* Before declaring the flip queue wedged, check if
11561 * the hardware completed the operation behind our backs.
11563 if (__intel_pageflip_stall_check(dev
, crtc
)) {
11564 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11565 page_flip_completed(intel_crtc
);
11567 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11568 spin_unlock_irq(&dev
->event_lock
);
11570 drm_crtc_vblank_put(crtc
);
11575 intel_crtc
->unpin_work
= work
;
11576 spin_unlock_irq(&dev
->event_lock
);
11578 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
11579 flush_workqueue(dev_priv
->wq
);
11581 /* Reference the objects for the scheduled work. */
11582 drm_framebuffer_reference(work
->old_fb
);
11583 drm_gem_object_reference(&obj
->base
);
11585 crtc
->primary
->fb
= fb
;
11586 update_state_fb(crtc
->primary
);
11587 intel_fbc_pre_update(intel_crtc
);
11589 work
->pending_flip_obj
= obj
;
11591 ret
= i915_mutex_lock_interruptible(dev
);
11595 intel_crtc
->reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
11596 if (__i915_reset_in_progress_or_wedged(intel_crtc
->reset_counter
)) {
11601 atomic_inc(&intel_crtc
->unpin_work_count
);
11603 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
11604 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_G4X(pipe
)) + 1;
11606 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
11607 engine
= &dev_priv
->engine
[BCS
];
11608 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
11609 /* vlv: DISPLAY_FLIP fails to change tiling */
11611 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
11612 engine
= &dev_priv
->engine
[BCS
];
11613 } else if (INTEL_INFO(dev
)->gen
>= 7) {
11614 engine
= i915_gem_request_get_engine(obj
->last_write_req
);
11615 if (engine
== NULL
|| engine
->id
!= RCS
)
11616 engine
= &dev_priv
->engine
[BCS
];
11618 engine
= &dev_priv
->engine
[RCS
];
11621 mmio_flip
= use_mmio_flip(engine
, obj
);
11623 /* When using CS flips, we want to emit semaphores between rings.
11624 * However, when using mmio flips we will create a task to do the
11625 * synchronisation, so all we want here is to pin the framebuffer
11626 * into the display plane and skip any waits.
11629 ret
= i915_gem_object_sync(obj
, engine
, &request
);
11631 goto cleanup_pending
;
11634 ret
= intel_pin_and_fence_fb_obj(fb
, primary
->state
->rotation
);
11636 goto cleanup_pending
;
11638 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
),
11640 work
->gtt_offset
+= intel_crtc
->dspaddr_offset
;
11643 ret
= intel_queue_mmio_flip(dev
, crtc
, obj
);
11645 goto cleanup_unpin
;
11647 i915_gem_request_assign(&work
->flip_queued_req
,
11648 obj
->last_write_req
);
11651 request
= i915_gem_request_alloc(engine
, NULL
);
11652 if (IS_ERR(request
)) {
11653 ret
= PTR_ERR(request
);
11654 goto cleanup_unpin
;
11658 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, request
,
11661 goto cleanup_unpin
;
11663 i915_gem_request_assign(&work
->flip_queued_req
, request
);
11667 i915_add_request_no_flush(request
);
11669 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
11670 work
->enable_stall_check
= true;
11672 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
11673 to_intel_plane(primary
)->frontbuffer_bit
);
11674 mutex_unlock(&dev
->struct_mutex
);
11676 intel_frontbuffer_flip_prepare(dev
,
11677 to_intel_plane(primary
)->frontbuffer_bit
);
11679 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11684 intel_unpin_fb_obj(fb
, crtc
->primary
->state
->rotation
);
11686 if (!IS_ERR_OR_NULL(request
))
11687 i915_add_request_no_flush(request
);
11688 atomic_dec(&intel_crtc
->unpin_work_count
);
11689 mutex_unlock(&dev
->struct_mutex
);
11691 crtc
->primary
->fb
= old_fb
;
11692 update_state_fb(crtc
->primary
);
11694 drm_gem_object_unreference_unlocked(&obj
->base
);
11695 drm_framebuffer_unreference(work
->old_fb
);
11697 spin_lock_irq(&dev
->event_lock
);
11698 intel_crtc
->unpin_work
= NULL
;
11699 spin_unlock_irq(&dev
->event_lock
);
11701 drm_crtc_vblank_put(crtc
);
11706 struct drm_atomic_state
*state
;
11707 struct drm_plane_state
*plane_state
;
11710 state
= drm_atomic_state_alloc(dev
);
11713 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
11716 plane_state
= drm_atomic_get_plane_state(state
, primary
);
11717 ret
= PTR_ERR_OR_ZERO(plane_state
);
11719 drm_atomic_set_fb_for_plane(plane_state
, fb
);
11721 ret
= drm_atomic_set_crtc_for_plane(plane_state
, crtc
);
11723 ret
= drm_atomic_commit(state
);
11726 if (ret
== -EDEADLK
) {
11727 drm_modeset_backoff(state
->acquire_ctx
);
11728 drm_atomic_state_clear(state
);
11733 drm_atomic_state_free(state
);
11735 if (ret
== 0 && event
) {
11736 spin_lock_irq(&dev
->event_lock
);
11737 drm_crtc_send_vblank_event(crtc
, event
);
11738 spin_unlock_irq(&dev
->event_lock
);
11746 * intel_wm_need_update - Check whether watermarks need updating
11747 * @plane: drm plane
11748 * @state: new plane state
11750 * Check current plane state versus the new one to determine whether
11751 * watermarks need to be recalculated.
11753 * Returns true or false.
11755 static bool intel_wm_need_update(struct drm_plane
*plane
,
11756 struct drm_plane_state
*state
)
11758 struct intel_plane_state
*new = to_intel_plane_state(state
);
11759 struct intel_plane_state
*cur
= to_intel_plane_state(plane
->state
);
11761 /* Update watermarks on tiling or size changes. */
11762 if (new->visible
!= cur
->visible
)
11765 if (!cur
->base
.fb
|| !new->base
.fb
)
11768 if (cur
->base
.fb
->modifier
[0] != new->base
.fb
->modifier
[0] ||
11769 cur
->base
.rotation
!= new->base
.rotation
||
11770 drm_rect_width(&new->src
) != drm_rect_width(&cur
->src
) ||
11771 drm_rect_height(&new->src
) != drm_rect_height(&cur
->src
) ||
11772 drm_rect_width(&new->dst
) != drm_rect_width(&cur
->dst
) ||
11773 drm_rect_height(&new->dst
) != drm_rect_height(&cur
->dst
))
11779 static bool needs_scaling(struct intel_plane_state
*state
)
11781 int src_w
= drm_rect_width(&state
->src
) >> 16;
11782 int src_h
= drm_rect_height(&state
->src
) >> 16;
11783 int dst_w
= drm_rect_width(&state
->dst
);
11784 int dst_h
= drm_rect_height(&state
->dst
);
11786 return (src_w
!= dst_w
|| src_h
!= dst_h
);
11789 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
11790 struct drm_plane_state
*plane_state
)
11792 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc_state
);
11793 struct drm_crtc
*crtc
= crtc_state
->crtc
;
11794 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11795 struct drm_plane
*plane
= plane_state
->plane
;
11796 struct drm_device
*dev
= crtc
->dev
;
11797 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11798 struct intel_plane_state
*old_plane_state
=
11799 to_intel_plane_state(plane
->state
);
11800 int idx
= intel_crtc
->base
.base
.id
, ret
;
11801 bool mode_changed
= needs_modeset(crtc_state
);
11802 bool was_crtc_enabled
= crtc
->state
->active
;
11803 bool is_crtc_enabled
= crtc_state
->active
;
11804 bool turn_off
, turn_on
, visible
, was_visible
;
11805 struct drm_framebuffer
*fb
= plane_state
->fb
;
11807 if (crtc_state
&& INTEL_INFO(dev
)->gen
>= 9 &&
11808 plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11809 ret
= skl_update_scaler_plane(
11810 to_intel_crtc_state(crtc_state
),
11811 to_intel_plane_state(plane_state
));
11816 was_visible
= old_plane_state
->visible
;
11817 visible
= to_intel_plane_state(plane_state
)->visible
;
11819 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
11820 was_visible
= false;
11823 * Visibility is calculated as if the crtc was on, but
11824 * after scaler setup everything depends on it being off
11825 * when the crtc isn't active.
11827 if (!is_crtc_enabled
)
11828 to_intel_plane_state(plane_state
)->visible
= visible
= false;
11830 if (!was_visible
&& !visible
)
11833 if (fb
!= old_plane_state
->base
.fb
)
11834 pipe_config
->fb_changed
= true;
11836 turn_off
= was_visible
&& (!visible
|| mode_changed
);
11837 turn_on
= visible
&& (!was_visible
|| mode_changed
);
11839 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx
,
11840 plane
->base
.id
, fb
? fb
->base
.id
: -1);
11842 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11843 plane
->base
.id
, was_visible
, visible
,
11844 turn_off
, turn_on
, mode_changed
);
11847 pipe_config
->update_wm_pre
= true;
11849 /* must disable cxsr around plane enable/disable */
11850 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
11851 pipe_config
->disable_cxsr
= true;
11852 } else if (turn_off
) {
11853 pipe_config
->update_wm_post
= true;
11855 /* must disable cxsr around plane enable/disable */
11856 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
11857 pipe_config
->disable_cxsr
= true;
11858 } else if (intel_wm_need_update(plane
, plane_state
)) {
11859 /* FIXME bollocks */
11860 pipe_config
->update_wm_pre
= true;
11861 pipe_config
->update_wm_post
= true;
11864 /* Pre-gen9 platforms need two-step watermark updates */
11865 if ((pipe_config
->update_wm_pre
|| pipe_config
->update_wm_post
) &&
11866 INTEL_INFO(dev
)->gen
< 9 && dev_priv
->display
.optimize_watermarks
)
11867 to_intel_crtc_state(crtc_state
)->wm
.need_postvbl_update
= true;
11869 if (visible
|| was_visible
)
11870 pipe_config
->fb_bits
|= to_intel_plane(plane
)->frontbuffer_bit
;
11873 * WaCxSRDisabledForSpriteScaling:ivb
11875 * cstate->update_wm was already set above, so this flag will
11876 * take effect when we commit and program watermarks.
11878 if (plane
->type
== DRM_PLANE_TYPE_OVERLAY
&& IS_IVYBRIDGE(dev
) &&
11879 needs_scaling(to_intel_plane_state(plane_state
)) &&
11880 !needs_scaling(old_plane_state
))
11881 pipe_config
->disable_lp_wm
= true;
11886 static bool encoders_cloneable(const struct intel_encoder
*a
,
11887 const struct intel_encoder
*b
)
11889 /* masks could be asymmetric, so check both ways */
11890 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11891 b
->cloneable
& (1 << a
->type
));
11894 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11895 struct intel_crtc
*crtc
,
11896 struct intel_encoder
*encoder
)
11898 struct intel_encoder
*source_encoder
;
11899 struct drm_connector
*connector
;
11900 struct drm_connector_state
*connector_state
;
11903 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11904 if (connector_state
->crtc
!= &crtc
->base
)
11908 to_intel_encoder(connector_state
->best_encoder
);
11909 if (!encoders_cloneable(encoder
, source_encoder
))
11916 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
11917 struct intel_crtc
*crtc
)
11919 struct intel_encoder
*encoder
;
11920 struct drm_connector
*connector
;
11921 struct drm_connector_state
*connector_state
;
11924 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11925 if (connector_state
->crtc
!= &crtc
->base
)
11928 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11929 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
11936 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
11937 struct drm_crtc_state
*crtc_state
)
11939 struct drm_device
*dev
= crtc
->dev
;
11940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11941 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11942 struct intel_crtc_state
*pipe_config
=
11943 to_intel_crtc_state(crtc_state
);
11944 struct drm_atomic_state
*state
= crtc_state
->state
;
11946 bool mode_changed
= needs_modeset(crtc_state
);
11948 if (mode_changed
&& !check_encoder_cloning(state
, intel_crtc
)) {
11949 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11953 if (mode_changed
&& !crtc_state
->active
)
11954 pipe_config
->update_wm_post
= true;
11956 if (mode_changed
&& crtc_state
->enable
&&
11957 dev_priv
->display
.crtc_compute_clock
&&
11958 !WARN_ON(pipe_config
->shared_dpll
)) {
11959 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11965 if (crtc_state
->color_mgmt_changed
) {
11966 ret
= intel_color_check(crtc
, crtc_state
);
11972 if (dev_priv
->display
.compute_pipe_wm
) {
11973 ret
= dev_priv
->display
.compute_pipe_wm(pipe_config
);
11975 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11980 if (dev_priv
->display
.compute_intermediate_wm
&&
11981 !to_intel_atomic_state(state
)->skip_intermediate_wm
) {
11982 if (WARN_ON(!dev_priv
->display
.compute_pipe_wm
))
11986 * Calculate 'intermediate' watermarks that satisfy both the
11987 * old state and the new state. We can program these
11990 ret
= dev_priv
->display
.compute_intermediate_wm(crtc
->dev
,
11994 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11999 if (INTEL_INFO(dev
)->gen
>= 9) {
12001 ret
= skl_update_scaler_crtc(pipe_config
);
12004 ret
= intel_atomic_setup_scalers(dev
, intel_crtc
,
12011 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
12012 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
12013 .atomic_begin
= intel_begin_crtc_commit
,
12014 .atomic_flush
= intel_finish_crtc_commit
,
12015 .atomic_check
= intel_crtc_atomic_check
,
12018 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
12020 struct intel_connector
*connector
;
12022 for_each_intel_connector(dev
, connector
) {
12023 if (connector
->base
.encoder
) {
12024 connector
->base
.state
->best_encoder
=
12025 connector
->base
.encoder
;
12026 connector
->base
.state
->crtc
=
12027 connector
->base
.encoder
->crtc
;
12029 connector
->base
.state
->best_encoder
= NULL
;
12030 connector
->base
.state
->crtc
= NULL
;
12036 connected_sink_compute_bpp(struct intel_connector
*connector
,
12037 struct intel_crtc_state
*pipe_config
)
12039 int bpp
= pipe_config
->pipe_bpp
;
12041 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12042 connector
->base
.base
.id
,
12043 connector
->base
.name
);
12045 /* Don't use an invalid EDID bpc value */
12046 if (connector
->base
.display_info
.bpc
&&
12047 connector
->base
.display_info
.bpc
* 3 < bpp
) {
12048 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12049 bpp
, connector
->base
.display_info
.bpc
*3);
12050 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
12053 /* Clamp bpp to default limit on screens without EDID 1.4 */
12054 if (connector
->base
.display_info
.bpc
== 0) {
12055 int type
= connector
->base
.connector_type
;
12056 int clamp_bpp
= 24;
12058 /* Fall back to 18 bpp when DP sink capability is unknown. */
12059 if (type
== DRM_MODE_CONNECTOR_DisplayPort
||
12060 type
== DRM_MODE_CONNECTOR_eDP
)
12063 if (bpp
> clamp_bpp
) {
12064 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12066 pipe_config
->pipe_bpp
= clamp_bpp
;
12072 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
12073 struct intel_crtc_state
*pipe_config
)
12075 struct drm_device
*dev
= crtc
->base
.dev
;
12076 struct drm_atomic_state
*state
;
12077 struct drm_connector
*connector
;
12078 struct drm_connector_state
*connector_state
;
12081 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)))
12083 else if (INTEL_INFO(dev
)->gen
>= 5)
12089 pipe_config
->pipe_bpp
= bpp
;
12091 state
= pipe_config
->base
.state
;
12093 /* Clamp display bpp to EDID value */
12094 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12095 if (connector_state
->crtc
!= &crtc
->base
)
12098 connected_sink_compute_bpp(to_intel_connector(connector
),
12105 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
12107 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12108 "type: 0x%x flags: 0x%x\n",
12110 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
12111 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
12112 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
12113 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
12116 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
12117 struct intel_crtc_state
*pipe_config
,
12118 const char *context
)
12120 struct drm_device
*dev
= crtc
->base
.dev
;
12121 struct drm_plane
*plane
;
12122 struct intel_plane
*intel_plane
;
12123 struct intel_plane_state
*state
;
12124 struct drm_framebuffer
*fb
;
12126 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc
->base
.base
.id
,
12127 context
, pipe_config
, pipe_name(crtc
->pipe
));
12129 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config
->cpu_transcoder
));
12130 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12131 pipe_config
->pipe_bpp
, pipe_config
->dither
);
12132 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12133 pipe_config
->has_pch_encoder
,
12134 pipe_config
->fdi_lanes
,
12135 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
12136 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
12137 pipe_config
->fdi_m_n
.tu
);
12138 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12139 pipe_config
->has_dp_encoder
,
12140 pipe_config
->lane_count
,
12141 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
12142 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
12143 pipe_config
->dp_m_n
.tu
);
12145 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12146 pipe_config
->has_dp_encoder
,
12147 pipe_config
->lane_count
,
12148 pipe_config
->dp_m2_n2
.gmch_m
,
12149 pipe_config
->dp_m2_n2
.gmch_n
,
12150 pipe_config
->dp_m2_n2
.link_m
,
12151 pipe_config
->dp_m2_n2
.link_n
,
12152 pipe_config
->dp_m2_n2
.tu
);
12154 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12155 pipe_config
->has_audio
,
12156 pipe_config
->has_infoframe
);
12158 DRM_DEBUG_KMS("requested mode:\n");
12159 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
12160 DRM_DEBUG_KMS("adjusted mode:\n");
12161 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
12162 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
12163 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
12164 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12165 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
12166 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12168 pipe_config
->scaler_state
.scaler_users
,
12169 pipe_config
->scaler_state
.scaler_id
);
12170 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12171 pipe_config
->gmch_pfit
.control
,
12172 pipe_config
->gmch_pfit
.pgm_ratios
,
12173 pipe_config
->gmch_pfit
.lvds_border_bits
);
12174 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12175 pipe_config
->pch_pfit
.pos
,
12176 pipe_config
->pch_pfit
.size
,
12177 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
12178 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
12179 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
12181 if (IS_BROXTON(dev
)) {
12182 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12183 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12184 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12185 pipe_config
->ddi_pll_sel
,
12186 pipe_config
->dpll_hw_state
.ebb0
,
12187 pipe_config
->dpll_hw_state
.ebb4
,
12188 pipe_config
->dpll_hw_state
.pll0
,
12189 pipe_config
->dpll_hw_state
.pll1
,
12190 pipe_config
->dpll_hw_state
.pll2
,
12191 pipe_config
->dpll_hw_state
.pll3
,
12192 pipe_config
->dpll_hw_state
.pll6
,
12193 pipe_config
->dpll_hw_state
.pll8
,
12194 pipe_config
->dpll_hw_state
.pll9
,
12195 pipe_config
->dpll_hw_state
.pll10
,
12196 pipe_config
->dpll_hw_state
.pcsdw12
);
12197 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
12198 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12199 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12200 pipe_config
->ddi_pll_sel
,
12201 pipe_config
->dpll_hw_state
.ctrl1
,
12202 pipe_config
->dpll_hw_state
.cfgcr1
,
12203 pipe_config
->dpll_hw_state
.cfgcr2
);
12204 } else if (HAS_DDI(dev
)) {
12205 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12206 pipe_config
->ddi_pll_sel
,
12207 pipe_config
->dpll_hw_state
.wrpll
,
12208 pipe_config
->dpll_hw_state
.spll
);
12210 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12211 "fp0: 0x%x, fp1: 0x%x\n",
12212 pipe_config
->dpll_hw_state
.dpll
,
12213 pipe_config
->dpll_hw_state
.dpll_md
,
12214 pipe_config
->dpll_hw_state
.fp0
,
12215 pipe_config
->dpll_hw_state
.fp1
);
12218 DRM_DEBUG_KMS("planes on this crtc\n");
12219 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
12220 intel_plane
= to_intel_plane(plane
);
12221 if (intel_plane
->pipe
!= crtc
->pipe
)
12224 state
= to_intel_plane_state(plane
->state
);
12225 fb
= state
->base
.fb
;
12227 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12228 "disabled, scaler_id = %d\n",
12229 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12230 plane
->base
.id
, intel_plane
->pipe
,
12231 (crtc
->base
.primary
== plane
) ? 0 : intel_plane
->plane
+ 1,
12232 drm_plane_index(plane
), state
->scaler_id
);
12236 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12237 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12238 plane
->base
.id
, intel_plane
->pipe
,
12239 crtc
->base
.primary
== plane
? 0 : intel_plane
->plane
+ 1,
12240 drm_plane_index(plane
));
12241 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12242 fb
->base
.id
, fb
->width
, fb
->height
, fb
->pixel_format
);
12243 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12245 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
12246 drm_rect_width(&state
->src
) >> 16,
12247 drm_rect_height(&state
->src
) >> 16,
12248 state
->dst
.x1
, state
->dst
.y1
,
12249 drm_rect_width(&state
->dst
), drm_rect_height(&state
->dst
));
12253 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
12255 struct drm_device
*dev
= state
->dev
;
12256 struct drm_connector
*connector
;
12257 unsigned int used_ports
= 0;
12260 * Walk the connector list instead of the encoder
12261 * list to detect the problem on ddi platforms
12262 * where there's just one encoder per digital port.
12264 drm_for_each_connector(connector
, dev
) {
12265 struct drm_connector_state
*connector_state
;
12266 struct intel_encoder
*encoder
;
12268 connector_state
= drm_atomic_get_existing_connector_state(state
, connector
);
12269 if (!connector_state
)
12270 connector_state
= connector
->state
;
12272 if (!connector_state
->best_encoder
)
12275 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12277 WARN_ON(!connector_state
->crtc
);
12279 switch (encoder
->type
) {
12280 unsigned int port_mask
;
12281 case INTEL_OUTPUT_UNKNOWN
:
12282 if (WARN_ON(!HAS_DDI(dev
)))
12284 case INTEL_OUTPUT_DISPLAYPORT
:
12285 case INTEL_OUTPUT_HDMI
:
12286 case INTEL_OUTPUT_EDP
:
12287 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
12289 /* the same port mustn't appear more than once */
12290 if (used_ports
& port_mask
)
12293 used_ports
|= port_mask
;
12303 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
12305 struct drm_crtc_state tmp_state
;
12306 struct intel_crtc_scaler_state scaler_state
;
12307 struct intel_dpll_hw_state dpll_hw_state
;
12308 struct intel_shared_dpll
*shared_dpll
;
12309 uint32_t ddi_pll_sel
;
12312 /* FIXME: before the switch to atomic started, a new pipe_config was
12313 * kzalloc'd. Code that depends on any field being zero should be
12314 * fixed, so that the crtc_state can be safely duplicated. For now,
12315 * only fields that are know to not cause problems are preserved. */
12317 tmp_state
= crtc_state
->base
;
12318 scaler_state
= crtc_state
->scaler_state
;
12319 shared_dpll
= crtc_state
->shared_dpll
;
12320 dpll_hw_state
= crtc_state
->dpll_hw_state
;
12321 ddi_pll_sel
= crtc_state
->ddi_pll_sel
;
12322 force_thru
= crtc_state
->pch_pfit
.force_thru
;
12324 memset(crtc_state
, 0, sizeof *crtc_state
);
12326 crtc_state
->base
= tmp_state
;
12327 crtc_state
->scaler_state
= scaler_state
;
12328 crtc_state
->shared_dpll
= shared_dpll
;
12329 crtc_state
->dpll_hw_state
= dpll_hw_state
;
12330 crtc_state
->ddi_pll_sel
= ddi_pll_sel
;
12331 crtc_state
->pch_pfit
.force_thru
= force_thru
;
12335 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
12336 struct intel_crtc_state
*pipe_config
)
12338 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12339 struct intel_encoder
*encoder
;
12340 struct drm_connector
*connector
;
12341 struct drm_connector_state
*connector_state
;
12342 int base_bpp
, ret
= -EINVAL
;
12346 clear_intel_crtc_state(pipe_config
);
12348 pipe_config
->cpu_transcoder
=
12349 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
12352 * Sanitize sync polarity flags based on requested ones. If neither
12353 * positive or negative polarity is requested, treat this as meaning
12354 * negative polarity.
12356 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12357 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
12358 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
12360 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12361 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
12362 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
12364 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
12370 * Determine the real pipe dimensions. Note that stereo modes can
12371 * increase the actual pipe size due to the frame doubling and
12372 * insertion of additional space for blanks between the frame. This
12373 * is stored in the crtc timings. We use the requested mode to do this
12374 * computation to clearly distinguish it from the adjusted mode, which
12375 * can be changed by the connectors in the below retry loop.
12377 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
12378 &pipe_config
->pipe_src_w
,
12379 &pipe_config
->pipe_src_h
);
12382 /* Ensure the port clock defaults are reset when retrying. */
12383 pipe_config
->port_clock
= 0;
12384 pipe_config
->pixel_multiplier
= 1;
12386 /* Fill in default crtc timings, allow encoders to overwrite them. */
12387 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
12388 CRTC_STEREO_DOUBLE
);
12390 /* Pass our mode to the connectors and the CRTC to give them a chance to
12391 * adjust it according to limitations or connector properties, and also
12392 * a chance to reject the mode entirely.
12394 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12395 if (connector_state
->crtc
!= crtc
)
12398 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12400 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
12401 DRM_DEBUG_KMS("Encoder config failure\n");
12406 /* Set default port clock if not overwritten by the encoder. Needs to be
12407 * done afterwards in case the encoder adjusts the mode. */
12408 if (!pipe_config
->port_clock
)
12409 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
12410 * pipe_config
->pixel_multiplier
;
12412 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
12414 DRM_DEBUG_KMS("CRTC fixup failed\n");
12418 if (ret
== RETRY
) {
12419 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
12424 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12426 goto encoder_retry
;
12429 /* Dithering seems to not pass-through bits correctly when it should, so
12430 * only enable it on 6bpc panels. */
12431 pipe_config
->dither
= pipe_config
->pipe_bpp
== 6*3;
12432 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12433 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
12440 intel_modeset_update_crtc_state(struct drm_atomic_state
*state
)
12442 struct drm_crtc
*crtc
;
12443 struct drm_crtc_state
*crtc_state
;
12446 /* Double check state. */
12447 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12448 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(crtc
->state
);
12450 /* Update hwmode for vblank functions */
12451 if (crtc
->state
->active
)
12452 crtc
->hwmode
= crtc
->state
->adjusted_mode
;
12454 crtc
->hwmode
.crtc_clock
= 0;
12457 * Update legacy state to satisfy fbc code. This can
12458 * be removed when fbc uses the atomic state.
12460 if (drm_atomic_get_existing_plane_state(state
, crtc
->primary
)) {
12461 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
12463 crtc
->primary
->fb
= plane_state
->fb
;
12464 crtc
->x
= plane_state
->src_x
>> 16;
12465 crtc
->y
= plane_state
->src_y
>> 16;
12470 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
12474 if (clock1
== clock2
)
12477 if (!clock1
|| !clock2
)
12480 diff
= abs(clock1
- clock2
);
12482 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
12488 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12489 list_for_each_entry((intel_crtc), \
12490 &(dev)->mode_config.crtc_list, \
12492 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12495 intel_compare_m_n(unsigned int m
, unsigned int n
,
12496 unsigned int m2
, unsigned int n2
,
12499 if (m
== m2
&& n
== n2
)
12502 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
12505 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
12512 } else if (n
< n2
) {
12522 return intel_fuzzy_clock_check(m
, m2
);
12526 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
12527 struct intel_link_m_n
*m2_n2
,
12530 if (m_n
->tu
== m2_n2
->tu
&&
12531 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
12532 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
12533 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
12534 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
12545 intel_pipe_config_compare(struct drm_device
*dev
,
12546 struct intel_crtc_state
*current_config
,
12547 struct intel_crtc_state
*pipe_config
,
12552 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12555 DRM_ERROR(fmt, ##__VA_ARGS__); \
12557 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12560 #define PIPE_CONF_CHECK_X(name) \
12561 if (current_config->name != pipe_config->name) { \
12562 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12563 "(expected 0x%08x, found 0x%08x)\n", \
12564 current_config->name, \
12565 pipe_config->name); \
12569 #define PIPE_CONF_CHECK_I(name) \
12570 if (current_config->name != pipe_config->name) { \
12571 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12572 "(expected %i, found %i)\n", \
12573 current_config->name, \
12574 pipe_config->name); \
12578 #define PIPE_CONF_CHECK_P(name) \
12579 if (current_config->name != pipe_config->name) { \
12580 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12581 "(expected %p, found %p)\n", \
12582 current_config->name, \
12583 pipe_config->name); \
12587 #define PIPE_CONF_CHECK_M_N(name) \
12588 if (!intel_compare_link_m_n(¤t_config->name, \
12589 &pipe_config->name,\
12591 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12592 "(expected tu %i gmch %i/%i link %i/%i, " \
12593 "found tu %i, gmch %i/%i link %i/%i)\n", \
12594 current_config->name.tu, \
12595 current_config->name.gmch_m, \
12596 current_config->name.gmch_n, \
12597 current_config->name.link_m, \
12598 current_config->name.link_n, \
12599 pipe_config->name.tu, \
12600 pipe_config->name.gmch_m, \
12601 pipe_config->name.gmch_n, \
12602 pipe_config->name.link_m, \
12603 pipe_config->name.link_n); \
12607 /* This is required for BDW+ where there is only one set of registers for
12608 * switching between high and low RR.
12609 * This macro can be used whenever a comparison has to be made between one
12610 * hw state and multiple sw state variables.
12612 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12613 if (!intel_compare_link_m_n(¤t_config->name, \
12614 &pipe_config->name, adjust) && \
12615 !intel_compare_link_m_n(¤t_config->alt_name, \
12616 &pipe_config->name, adjust)) { \
12617 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12618 "(expected tu %i gmch %i/%i link %i/%i, " \
12619 "or tu %i gmch %i/%i link %i/%i, " \
12620 "found tu %i, gmch %i/%i link %i/%i)\n", \
12621 current_config->name.tu, \
12622 current_config->name.gmch_m, \
12623 current_config->name.gmch_n, \
12624 current_config->name.link_m, \
12625 current_config->name.link_n, \
12626 current_config->alt_name.tu, \
12627 current_config->alt_name.gmch_m, \
12628 current_config->alt_name.gmch_n, \
12629 current_config->alt_name.link_m, \
12630 current_config->alt_name.link_n, \
12631 pipe_config->name.tu, \
12632 pipe_config->name.gmch_m, \
12633 pipe_config->name.gmch_n, \
12634 pipe_config->name.link_m, \
12635 pipe_config->name.link_n); \
12639 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12640 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12641 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12642 "(expected %i, found %i)\n", \
12643 current_config->name & (mask), \
12644 pipe_config->name & (mask)); \
12648 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12649 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12650 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12651 "(expected %i, found %i)\n", \
12652 current_config->name, \
12653 pipe_config->name); \
12657 #define PIPE_CONF_QUIRK(quirk) \
12658 ((current_config->quirks | pipe_config->quirks) & (quirk))
12660 PIPE_CONF_CHECK_I(cpu_transcoder
);
12662 PIPE_CONF_CHECK_I(has_pch_encoder
);
12663 PIPE_CONF_CHECK_I(fdi_lanes
);
12664 PIPE_CONF_CHECK_M_N(fdi_m_n
);
12666 PIPE_CONF_CHECK_I(has_dp_encoder
);
12667 PIPE_CONF_CHECK_I(lane_count
);
12669 if (INTEL_INFO(dev
)->gen
< 8) {
12670 PIPE_CONF_CHECK_M_N(dp_m_n
);
12672 if (current_config
->has_drrs
)
12673 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
12675 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
12677 PIPE_CONF_CHECK_I(has_dsi_encoder
);
12679 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12680 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12681 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12682 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12683 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12684 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12686 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12687 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12688 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12689 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12690 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12691 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12693 PIPE_CONF_CHECK_I(pixel_multiplier
);
12694 PIPE_CONF_CHECK_I(has_hdmi_sink
);
12695 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
12696 IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
12697 PIPE_CONF_CHECK_I(limited_color_range
);
12698 PIPE_CONF_CHECK_I(has_infoframe
);
12700 PIPE_CONF_CHECK_I(has_audio
);
12702 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12703 DRM_MODE_FLAG_INTERLACE
);
12705 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12706 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12707 DRM_MODE_FLAG_PHSYNC
);
12708 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12709 DRM_MODE_FLAG_NHSYNC
);
12710 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12711 DRM_MODE_FLAG_PVSYNC
);
12712 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12713 DRM_MODE_FLAG_NVSYNC
);
12716 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
12717 /* pfit ratios are autocomputed by the hw on gen4+ */
12718 if (INTEL_INFO(dev
)->gen
< 4)
12719 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
12720 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
12723 PIPE_CONF_CHECK_I(pipe_src_w
);
12724 PIPE_CONF_CHECK_I(pipe_src_h
);
12726 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
12727 if (current_config
->pch_pfit
.enabled
) {
12728 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
12729 PIPE_CONF_CHECK_X(pch_pfit
.size
);
12732 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12735 /* BDW+ don't expose a synchronous way to read the state */
12736 if (IS_HASWELL(dev
))
12737 PIPE_CONF_CHECK_I(ips_enabled
);
12739 PIPE_CONF_CHECK_I(double_wide
);
12741 PIPE_CONF_CHECK_X(ddi_pll_sel
);
12743 PIPE_CONF_CHECK_P(shared_dpll
);
12744 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12745 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12746 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12747 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12748 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12749 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
12750 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12751 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12752 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12754 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
12755 PIPE_CONF_CHECK_X(dsi_pll
.div
);
12757 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
12758 PIPE_CONF_CHECK_I(pipe_bpp
);
12760 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12761 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12763 #undef PIPE_CONF_CHECK_X
12764 #undef PIPE_CONF_CHECK_I
12765 #undef PIPE_CONF_CHECK_P
12766 #undef PIPE_CONF_CHECK_FLAGS
12767 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12768 #undef PIPE_CONF_QUIRK
12769 #undef INTEL_ERR_OR_DBG_KMS
12774 static void intel_pipe_config_sanity_check(struct drm_i915_private
*dev_priv
,
12775 const struct intel_crtc_state
*pipe_config
)
12777 if (pipe_config
->has_pch_encoder
) {
12778 int fdi_dotclock
= intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
12779 &pipe_config
->fdi_m_n
);
12780 int dotclock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
12783 * FDI already provided one idea for the dotclock.
12784 * Yell if the encoder disagrees.
12786 WARN(!intel_fuzzy_clock_check(fdi_dotclock
, dotclock
),
12787 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12788 fdi_dotclock
, dotclock
);
12792 static void verify_wm_state(struct drm_crtc
*crtc
,
12793 struct drm_crtc_state
*new_state
)
12795 struct drm_device
*dev
= crtc
->dev
;
12796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12797 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
12798 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
12799 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12800 const enum pipe pipe
= intel_crtc
->pipe
;
12803 if (INTEL_INFO(dev
)->gen
< 9 || !new_state
->active
)
12806 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
12807 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12810 for_each_plane(dev_priv
, pipe
, plane
) {
12811 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
12812 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
12814 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12817 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12818 "(expected (%u,%u), found (%u,%u))\n",
12819 pipe_name(pipe
), plane
+ 1,
12820 sw_entry
->start
, sw_entry
->end
,
12821 hw_entry
->start
, hw_entry
->end
);
12825 hw_entry
= &hw_ddb
.plane
[pipe
][PLANE_CURSOR
];
12826 sw_entry
= &sw_ddb
->plane
[pipe
][PLANE_CURSOR
];
12828 if (!skl_ddb_entry_equal(hw_entry
, sw_entry
)) {
12829 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12830 "(expected (%u,%u), found (%u,%u))\n",
12832 sw_entry
->start
, sw_entry
->end
,
12833 hw_entry
->start
, hw_entry
->end
);
12838 verify_connector_state(struct drm_device
*dev
, struct drm_crtc
*crtc
)
12840 struct drm_connector
*connector
;
12842 drm_for_each_connector(connector
, dev
) {
12843 struct drm_encoder
*encoder
= connector
->encoder
;
12844 struct drm_connector_state
*state
= connector
->state
;
12846 if (state
->crtc
!= crtc
)
12849 intel_connector_verify_state(to_intel_connector(connector
));
12851 I915_STATE_WARN(state
->best_encoder
!= encoder
,
12852 "connector's atomic encoder doesn't match legacy encoder\n");
12857 verify_encoder_state(struct drm_device
*dev
)
12859 struct intel_encoder
*encoder
;
12860 struct intel_connector
*connector
;
12862 for_each_intel_encoder(dev
, encoder
) {
12863 bool enabled
= false;
12866 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12867 encoder
->base
.base
.id
,
12868 encoder
->base
.name
);
12870 for_each_intel_connector(dev
, connector
) {
12871 if (connector
->base
.state
->best_encoder
!= &encoder
->base
)
12875 I915_STATE_WARN(connector
->base
.state
->crtc
!=
12876 encoder
->base
.crtc
,
12877 "connector's crtc doesn't match encoder crtc\n");
12880 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12881 "encoder's enabled state mismatch "
12882 "(expected %i, found %i)\n",
12883 !!encoder
->base
.crtc
, enabled
);
12885 if (!encoder
->base
.crtc
) {
12888 active
= encoder
->get_hw_state(encoder
, &pipe
);
12889 I915_STATE_WARN(active
,
12890 "encoder detached but still enabled on pipe %c.\n",
12897 verify_crtc_state(struct drm_crtc
*crtc
,
12898 struct drm_crtc_state
*old_crtc_state
,
12899 struct drm_crtc_state
*new_crtc_state
)
12901 struct drm_device
*dev
= crtc
->dev
;
12902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12903 struct intel_encoder
*encoder
;
12904 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12905 struct intel_crtc_state
*pipe_config
, *sw_config
;
12906 struct drm_atomic_state
*old_state
;
12909 old_state
= old_crtc_state
->state
;
12910 __drm_atomic_helper_crtc_destroy_state(crtc
, old_crtc_state
);
12911 pipe_config
= to_intel_crtc_state(old_crtc_state
);
12912 memset(pipe_config
, 0, sizeof(*pipe_config
));
12913 pipe_config
->base
.crtc
= crtc
;
12914 pipe_config
->base
.state
= old_state
;
12916 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
12918 active
= dev_priv
->display
.get_pipe_config(intel_crtc
, pipe_config
);
12920 /* hw state is inconsistent with the pipe quirk */
12921 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
12922 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
12923 active
= new_crtc_state
->active
;
12925 I915_STATE_WARN(new_crtc_state
->active
!= active
,
12926 "crtc active state doesn't match with hw state "
12927 "(expected %i, found %i)\n", new_crtc_state
->active
, active
);
12929 I915_STATE_WARN(intel_crtc
->active
!= new_crtc_state
->active
,
12930 "transitional active state does not match atomic hw state "
12931 "(expected %i, found %i)\n", new_crtc_state
->active
, intel_crtc
->active
);
12933 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
12936 active
= encoder
->get_hw_state(encoder
, &pipe
);
12937 I915_STATE_WARN(active
!= new_crtc_state
->active
,
12938 "[ENCODER:%i] active %i with crtc active %i\n",
12939 encoder
->base
.base
.id
, active
, new_crtc_state
->active
);
12941 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
12942 "Encoder connected to wrong pipe %c\n",
12946 encoder
->get_config(encoder
, pipe_config
);
12949 if (!new_crtc_state
->active
)
12952 intel_pipe_config_sanity_check(dev_priv
, pipe_config
);
12954 sw_config
= to_intel_crtc_state(crtc
->state
);
12955 if (!intel_pipe_config_compare(dev
, sw_config
,
12956 pipe_config
, false)) {
12957 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12958 intel_dump_pipe_config(intel_crtc
, pipe_config
,
12960 intel_dump_pipe_config(intel_crtc
, sw_config
,
12966 verify_single_dpll_state(struct drm_i915_private
*dev_priv
,
12967 struct intel_shared_dpll
*pll
,
12968 struct drm_crtc
*crtc
,
12969 struct drm_crtc_state
*new_state
)
12971 struct intel_dpll_hw_state dpll_hw_state
;
12972 unsigned crtc_mask
;
12975 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12977 DRM_DEBUG_KMS("%s\n", pll
->name
);
12979 active
= pll
->funcs
.get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12981 if (!(pll
->flags
& INTEL_DPLL_ALWAYS_ON
)) {
12982 I915_STATE_WARN(!pll
->on
&& pll
->active_mask
,
12983 "pll in active use but not on in sw tracking\n");
12984 I915_STATE_WARN(pll
->on
&& !pll
->active_mask
,
12985 "pll is on but not used by any active crtc\n");
12986 I915_STATE_WARN(pll
->on
!= active
,
12987 "pll on state mismatch (expected %i, found %i)\n",
12992 I915_STATE_WARN(pll
->active_mask
& ~pll
->config
.crtc_mask
,
12993 "more active pll users than references: %x vs %x\n",
12994 pll
->active_mask
, pll
->config
.crtc_mask
);
12999 crtc_mask
= 1 << drm_crtc_index(crtc
);
13001 if (new_state
->active
)
13002 I915_STATE_WARN(!(pll
->active_mask
& crtc_mask
),
13003 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13004 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
13006 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13007 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13008 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
13010 I915_STATE_WARN(!(pll
->config
.crtc_mask
& crtc_mask
),
13011 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13012 crtc_mask
, pll
->config
.crtc_mask
);
13014 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
,
13016 sizeof(dpll_hw_state
)),
13017 "pll hw state mismatch\n");
13021 verify_shared_dpll_state(struct drm_device
*dev
, struct drm_crtc
*crtc
,
13022 struct drm_crtc_state
*old_crtc_state
,
13023 struct drm_crtc_state
*new_crtc_state
)
13025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13026 struct intel_crtc_state
*old_state
= to_intel_crtc_state(old_crtc_state
);
13027 struct intel_crtc_state
*new_state
= to_intel_crtc_state(new_crtc_state
);
13029 if (new_state
->shared_dpll
)
13030 verify_single_dpll_state(dev_priv
, new_state
->shared_dpll
, crtc
, new_crtc_state
);
13032 if (old_state
->shared_dpll
&&
13033 old_state
->shared_dpll
!= new_state
->shared_dpll
) {
13034 unsigned crtc_mask
= 1 << drm_crtc_index(crtc
);
13035 struct intel_shared_dpll
*pll
= old_state
->shared_dpll
;
13037 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13038 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13039 pipe_name(drm_crtc_index(crtc
)));
13040 I915_STATE_WARN(pll
->config
.crtc_mask
& crtc_mask
,
13041 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13042 pipe_name(drm_crtc_index(crtc
)));
13047 intel_modeset_verify_crtc(struct drm_crtc
*crtc
,
13048 struct drm_crtc_state
*old_state
,
13049 struct drm_crtc_state
*new_state
)
13051 if (!needs_modeset(new_state
) &&
13052 !to_intel_crtc_state(new_state
)->update_pipe
)
13055 verify_wm_state(crtc
, new_state
);
13056 verify_connector_state(crtc
->dev
, crtc
);
13057 verify_crtc_state(crtc
, old_state
, new_state
);
13058 verify_shared_dpll_state(crtc
->dev
, crtc
, old_state
, new_state
);
13062 verify_disabled_dpll_state(struct drm_device
*dev
)
13064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13067 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++)
13068 verify_single_dpll_state(dev_priv
, &dev_priv
->shared_dplls
[i
], NULL
, NULL
);
13072 intel_modeset_verify_disabled(struct drm_device
*dev
)
13074 verify_encoder_state(dev
);
13075 verify_connector_state(dev
, NULL
);
13076 verify_disabled_dpll_state(dev
);
13079 static void update_scanline_offset(struct intel_crtc
*crtc
)
13081 struct drm_device
*dev
= crtc
->base
.dev
;
13084 * The scanline counter increments at the leading edge of hsync.
13086 * On most platforms it starts counting from vtotal-1 on the
13087 * first active line. That means the scanline counter value is
13088 * always one less than what we would expect. Ie. just after
13089 * start of vblank, which also occurs at start of hsync (on the
13090 * last active line), the scanline counter will read vblank_start-1.
13092 * On gen2 the scanline counter starts counting from 1 instead
13093 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13094 * to keep the value positive), instead of adding one.
13096 * On HSW+ the behaviour of the scanline counter depends on the output
13097 * type. For DP ports it behaves like most other platforms, but on HDMI
13098 * there's an extra 1 line difference. So we need to add two instead of
13099 * one to the value.
13101 if (IS_GEN2(dev
)) {
13102 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
13105 vtotal
= adjusted_mode
->crtc_vtotal
;
13106 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
13109 crtc
->scanline_offset
= vtotal
- 1;
13110 } else if (HAS_DDI(dev
) &&
13111 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
13112 crtc
->scanline_offset
= 2;
13114 crtc
->scanline_offset
= 1;
13117 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
13119 struct drm_device
*dev
= state
->dev
;
13120 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13121 struct intel_shared_dpll_config
*shared_dpll
= NULL
;
13122 struct drm_crtc
*crtc
;
13123 struct drm_crtc_state
*crtc_state
;
13126 if (!dev_priv
->display
.crtc_compute_clock
)
13129 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13130 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13131 struct intel_shared_dpll
*old_dpll
=
13132 to_intel_crtc_state(crtc
->state
)->shared_dpll
;
13134 if (!needs_modeset(crtc_state
))
13137 to_intel_crtc_state(crtc_state
)->shared_dpll
= NULL
;
13143 shared_dpll
= intel_atomic_get_shared_dpll_state(state
);
13145 intel_shared_dpll_config_put(shared_dpll
, old_dpll
, intel_crtc
);
13150 * This implements the workaround described in the "notes" section of the mode
13151 * set sequence documentation. When going from no pipes or single pipe to
13152 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13153 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13155 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
13157 struct drm_crtc_state
*crtc_state
;
13158 struct intel_crtc
*intel_crtc
;
13159 struct drm_crtc
*crtc
;
13160 struct intel_crtc_state
*first_crtc_state
= NULL
;
13161 struct intel_crtc_state
*other_crtc_state
= NULL
;
13162 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
13165 /* look at all crtc's that are going to be enabled in during modeset */
13166 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13167 intel_crtc
= to_intel_crtc(crtc
);
13169 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
13172 if (first_crtc_state
) {
13173 other_crtc_state
= to_intel_crtc_state(crtc_state
);
13176 first_crtc_state
= to_intel_crtc_state(crtc_state
);
13177 first_pipe
= intel_crtc
->pipe
;
13181 /* No workaround needed? */
13182 if (!first_crtc_state
)
13185 /* w/a possibly needed, check how many crtc's are already enabled. */
13186 for_each_intel_crtc(state
->dev
, intel_crtc
) {
13187 struct intel_crtc_state
*pipe_config
;
13189 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
13190 if (IS_ERR(pipe_config
))
13191 return PTR_ERR(pipe_config
);
13193 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
13195 if (!pipe_config
->base
.active
||
13196 needs_modeset(&pipe_config
->base
))
13199 /* 2 or more enabled crtcs means no need for w/a */
13200 if (enabled_pipe
!= INVALID_PIPE
)
13203 enabled_pipe
= intel_crtc
->pipe
;
13206 if (enabled_pipe
!= INVALID_PIPE
)
13207 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
13208 else if (other_crtc_state
)
13209 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
13214 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
13216 struct drm_crtc
*crtc
;
13217 struct drm_crtc_state
*crtc_state
;
13220 /* add all active pipes to the state */
13221 for_each_crtc(state
->dev
, crtc
) {
13222 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13223 if (IS_ERR(crtc_state
))
13224 return PTR_ERR(crtc_state
);
13226 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
13229 crtc_state
->mode_changed
= true;
13231 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13235 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13243 static int intel_modeset_checks(struct drm_atomic_state
*state
)
13245 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13246 struct drm_i915_private
*dev_priv
= state
->dev
->dev_private
;
13247 struct drm_crtc
*crtc
;
13248 struct drm_crtc_state
*crtc_state
;
13251 if (!check_digital_port_conflicts(state
)) {
13252 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13256 intel_state
->modeset
= true;
13257 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
13259 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13260 if (crtc_state
->active
)
13261 intel_state
->active_crtcs
|= 1 << i
;
13263 intel_state
->active_crtcs
&= ~(1 << i
);
13267 * See if the config requires any additional preparation, e.g.
13268 * to adjust global state with pipes off. We need to do this
13269 * here so we can get the modeset_pipe updated config for the new
13270 * mode set on this crtc. For other crtcs we need to use the
13271 * adjusted_mode bits in the crtc directly.
13273 if (dev_priv
->display
.modeset_calc_cdclk
) {
13274 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
13276 if (!ret
&& intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
)
13277 ret
= intel_modeset_all_pipes(state
);
13282 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13283 intel_state
->cdclk
, intel_state
->dev_cdclk
);
13285 to_intel_atomic_state(state
)->cdclk
= dev_priv
->atomic_cdclk_freq
;
13287 intel_modeset_clear_plls(state
);
13289 if (IS_HASWELL(dev_priv
))
13290 return haswell_mode_set_planes_workaround(state
);
13296 * Handle calculation of various watermark data at the end of the atomic check
13297 * phase. The code here should be run after the per-crtc and per-plane 'check'
13298 * handlers to ensure that all derived state has been updated.
13300 static void calc_watermark_data(struct drm_atomic_state
*state
)
13302 struct drm_device
*dev
= state
->dev
;
13303 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13304 struct drm_crtc
*crtc
;
13305 struct drm_crtc_state
*cstate
;
13306 struct drm_plane
*plane
;
13307 struct drm_plane_state
*pstate
;
13310 * Calculate watermark configuration details now that derived
13311 * plane/crtc state is all properly updated.
13313 drm_for_each_crtc(crtc
, dev
) {
13314 cstate
= drm_atomic_get_existing_crtc_state(state
, crtc
) ?:
13317 if (cstate
->active
)
13318 intel_state
->wm_config
.num_pipes_active
++;
13320 drm_for_each_legacy_plane(plane
, dev
) {
13321 pstate
= drm_atomic_get_existing_plane_state(state
, plane
) ?:
13324 if (!to_intel_plane_state(pstate
)->visible
)
13327 intel_state
->wm_config
.sprites_enabled
= true;
13328 if (pstate
->crtc_w
!= pstate
->src_w
>> 16 ||
13329 pstate
->crtc_h
!= pstate
->src_h
>> 16)
13330 intel_state
->wm_config
.sprites_scaled
= true;
13335 * intel_atomic_check - validate state object
13337 * @state: state to validate
13339 static int intel_atomic_check(struct drm_device
*dev
,
13340 struct drm_atomic_state
*state
)
13342 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13343 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13344 struct drm_crtc
*crtc
;
13345 struct drm_crtc_state
*crtc_state
;
13347 bool any_ms
= false;
13349 ret
= drm_atomic_helper_check_modeset(dev
, state
);
13353 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13354 struct intel_crtc_state
*pipe_config
=
13355 to_intel_crtc_state(crtc_state
);
13357 /* Catch I915_MODE_FLAG_INHERITED */
13358 if (crtc_state
->mode
.private_flags
!= crtc
->state
->mode
.private_flags
)
13359 crtc_state
->mode_changed
= true;
13361 if (!crtc_state
->enable
) {
13362 if (needs_modeset(crtc_state
))
13367 if (!needs_modeset(crtc_state
))
13370 /* FIXME: For only active_changed we shouldn't need to do any
13371 * state recomputation at all. */
13373 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13377 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
13379 intel_dump_pipe_config(to_intel_crtc(crtc
),
13380 pipe_config
, "[failed]");
13384 if (i915
.fastboot
&&
13385 intel_pipe_config_compare(dev
,
13386 to_intel_crtc_state(crtc
->state
),
13387 pipe_config
, true)) {
13388 crtc_state
->mode_changed
= false;
13389 to_intel_crtc_state(crtc_state
)->update_pipe
= true;
13392 if (needs_modeset(crtc_state
)) {
13395 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13400 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
13401 needs_modeset(crtc_state
) ?
13402 "[modeset]" : "[fastset]");
13406 ret
= intel_modeset_checks(state
);
13411 intel_state
->cdclk
= dev_priv
->cdclk_freq
;
13413 ret
= drm_atomic_helper_check_planes(dev
, state
);
13417 intel_fbc_choose_crtc(dev_priv
, state
);
13418 calc_watermark_data(state
);
13423 static int intel_atomic_prepare_commit(struct drm_device
*dev
,
13424 struct drm_atomic_state
*state
,
13427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13428 struct drm_plane_state
*plane_state
;
13429 struct drm_crtc_state
*crtc_state
;
13430 struct drm_plane
*plane
;
13431 struct drm_crtc
*crtc
;
13435 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13439 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13440 if (state
->legacy_cursor_update
)
13443 ret
= intel_crtc_wait_for_pending_flips(crtc
);
13447 if (atomic_read(&to_intel_crtc(crtc
)->unpin_work_count
) >= 2)
13448 flush_workqueue(dev_priv
->wq
);
13451 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
13455 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
13456 mutex_unlock(&dev
->struct_mutex
);
13458 if (!ret
&& !async
) {
13459 for_each_plane_in_state(state
, plane
, plane_state
, i
) {
13460 struct intel_plane_state
*intel_plane_state
=
13461 to_intel_plane_state(plane_state
);
13463 if (!intel_plane_state
->wait_req
)
13466 ret
= __i915_wait_request(intel_plane_state
->wait_req
,
13469 /* Any hang should be swallowed by the wait */
13470 WARN_ON(ret
== -EIO
);
13471 mutex_lock(&dev
->struct_mutex
);
13472 drm_atomic_helper_cleanup_planes(dev
, state
);
13473 mutex_unlock(&dev
->struct_mutex
);
13482 static void intel_atomic_wait_for_vblanks(struct drm_device
*dev
,
13483 struct drm_i915_private
*dev_priv
,
13484 unsigned crtc_mask
)
13486 unsigned last_vblank_count
[I915_MAX_PIPES
];
13493 for_each_pipe(dev_priv
, pipe
) {
13494 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
13496 if (!((1 << pipe
) & crtc_mask
))
13499 ret
= drm_crtc_vblank_get(crtc
);
13500 if (WARN_ON(ret
!= 0)) {
13501 crtc_mask
&= ~(1 << pipe
);
13505 last_vblank_count
[pipe
] = drm_crtc_vblank_count(crtc
);
13508 for_each_pipe(dev_priv
, pipe
) {
13509 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
13512 if (!((1 << pipe
) & crtc_mask
))
13515 lret
= wait_event_timeout(dev
->vblank
[pipe
].queue
,
13516 last_vblank_count
[pipe
] !=
13517 drm_crtc_vblank_count(crtc
),
13518 msecs_to_jiffies(50));
13520 WARN(!lret
, "pipe %c vblank wait timed out\n", pipe_name(pipe
));
13522 drm_crtc_vblank_put(crtc
);
13526 static bool needs_vblank_wait(struct intel_crtc_state
*crtc_state
)
13528 /* fb updated, need to unpin old fb */
13529 if (crtc_state
->fb_changed
)
13532 /* wm changes, need vblank before final wm's */
13533 if (crtc_state
->update_wm_post
)
13537 * cxsr is re-enabled after vblank.
13538 * This is already handled by crtc_state->update_wm_post,
13539 * but added for clarity.
13541 if (crtc_state
->disable_cxsr
)
13548 * intel_atomic_commit - commit validated state object
13550 * @state: the top-level driver state object
13551 * @async: asynchronous commit
13553 * This function commits a top-level state object that has been validated
13554 * with drm_atomic_helper_check().
13556 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13557 * we can only handle plane-related operations and do not yet support
13558 * asynchronous commit.
13561 * Zero for success or -errno.
13563 static int intel_atomic_commit(struct drm_device
*dev
,
13564 struct drm_atomic_state
*state
,
13567 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13569 struct drm_crtc_state
*old_crtc_state
;
13570 struct drm_crtc
*crtc
;
13571 struct intel_crtc_state
*intel_cstate
;
13573 bool hw_check
= intel_state
->modeset
;
13574 unsigned long put_domains
[I915_MAX_PIPES
] = {};
13575 unsigned crtc_vblank_mask
= 0;
13577 ret
= intel_atomic_prepare_commit(dev
, state
, async
);
13579 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret
);
13583 drm_atomic_helper_swap_state(dev
, state
);
13584 dev_priv
->wm
.config
= intel_state
->wm_config
;
13585 intel_shared_dpll_commit(state
);
13587 if (intel_state
->modeset
) {
13588 memcpy(dev_priv
->min_pixclk
, intel_state
->min_pixclk
,
13589 sizeof(intel_state
->min_pixclk
));
13590 dev_priv
->active_crtcs
= intel_state
->active_crtcs
;
13591 dev_priv
->atomic_cdclk_freq
= intel_state
->cdclk
;
13593 intel_display_power_get(dev_priv
, POWER_DOMAIN_MODESET
);
13596 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13597 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13599 if (needs_modeset(crtc
->state
) ||
13600 to_intel_crtc_state(crtc
->state
)->update_pipe
) {
13603 put_domains
[to_intel_crtc(crtc
)->pipe
] =
13604 modeset_get_crtc_power_domains(crtc
,
13605 to_intel_crtc_state(crtc
->state
));
13608 if (!needs_modeset(crtc
->state
))
13611 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
13613 if (old_crtc_state
->active
) {
13614 intel_crtc_disable_planes(crtc
, old_crtc_state
->plane_mask
);
13615 dev_priv
->display
.crtc_disable(crtc
);
13616 intel_crtc
->active
= false;
13617 intel_fbc_disable(intel_crtc
);
13618 intel_disable_shared_dpll(intel_crtc
);
13621 * Underruns don't always raise
13622 * interrupts, so check manually.
13624 intel_check_cpu_fifo_underruns(dev_priv
);
13625 intel_check_pch_fifo_underruns(dev_priv
);
13627 if (!crtc
->state
->active
)
13628 intel_update_watermarks(crtc
);
13632 /* Only after disabling all output pipelines that will be changed can we
13633 * update the the output configuration. */
13634 intel_modeset_update_crtc_state(state
);
13636 if (intel_state
->modeset
) {
13637 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
13639 if (dev_priv
->display
.modeset_commit_cdclk
&&
13640 intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
)
13641 dev_priv
->display
.modeset_commit_cdclk(state
);
13643 intel_modeset_verify_disabled(dev
);
13646 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13647 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13648 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13649 bool modeset
= needs_modeset(crtc
->state
);
13650 struct intel_crtc_state
*pipe_config
=
13651 to_intel_crtc_state(crtc
->state
);
13652 bool update_pipe
= !modeset
&& pipe_config
->update_pipe
;
13654 if (modeset
&& crtc
->state
->active
) {
13655 update_scanline_offset(to_intel_crtc(crtc
));
13656 dev_priv
->display
.crtc_enable(crtc
);
13660 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
13662 if (crtc
->state
->active
&&
13663 drm_atomic_get_existing_plane_state(state
, crtc
->primary
))
13664 intel_fbc_enable(intel_crtc
);
13666 if (crtc
->state
->active
&&
13667 (crtc
->state
->planes_changed
|| update_pipe
))
13668 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state
);
13670 if (pipe_config
->base
.active
&& needs_vblank_wait(pipe_config
))
13671 crtc_vblank_mask
|= 1 << i
;
13674 /* FIXME: add subpixel order */
13676 if (!state
->legacy_cursor_update
)
13677 intel_atomic_wait_for_vblanks(dev
, dev_priv
, crtc_vblank_mask
);
13680 * Now that the vblank has passed, we can go ahead and program the
13681 * optimal watermarks on platforms that need two-step watermark
13684 * TODO: Move this (and other cleanup) to an async worker eventually.
13686 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13687 intel_cstate
= to_intel_crtc_state(crtc
->state
);
13689 if (dev_priv
->display
.optimize_watermarks
)
13690 dev_priv
->display
.optimize_watermarks(intel_cstate
);
13693 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13694 intel_post_plane_update(to_intel_crtc_state(old_crtc_state
));
13696 if (put_domains
[i
])
13697 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
13699 intel_modeset_verify_crtc(crtc
, old_crtc_state
, crtc
->state
);
13702 if (intel_state
->modeset
)
13703 intel_display_power_put(dev_priv
, POWER_DOMAIN_MODESET
);
13705 mutex_lock(&dev
->struct_mutex
);
13706 drm_atomic_helper_cleanup_planes(dev
, state
);
13707 mutex_unlock(&dev
->struct_mutex
);
13709 drm_atomic_state_free(state
);
13711 /* As one of the primary mmio accessors, KMS has a high likelihood
13712 * of triggering bugs in unclaimed access. After we finish
13713 * modesetting, see if an error has been flagged, and if so
13714 * enable debugging for the next modeset - and hope we catch
13717 * XXX note that we assume display power is on at this point.
13718 * This might hold true now but we need to add pm helper to check
13719 * unclaimed only when the hardware is on, as atomic commits
13720 * can happen also when the device is completely off.
13722 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
13727 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
13729 struct drm_device
*dev
= crtc
->dev
;
13730 struct drm_atomic_state
*state
;
13731 struct drm_crtc_state
*crtc_state
;
13734 state
= drm_atomic_state_alloc(dev
);
13736 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13741 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
13744 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13745 ret
= PTR_ERR_OR_ZERO(crtc_state
);
13747 if (!crtc_state
->active
)
13750 crtc_state
->mode_changed
= true;
13751 ret
= drm_atomic_commit(state
);
13754 if (ret
== -EDEADLK
) {
13755 drm_atomic_state_clear(state
);
13756 drm_modeset_backoff(state
->acquire_ctx
);
13762 drm_atomic_state_free(state
);
13765 #undef for_each_intel_crtc_masked
13767 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13768 .gamma_set
= drm_atomic_helper_legacy_gamma_set
,
13769 .set_config
= drm_atomic_helper_set_config
,
13770 .set_property
= drm_atomic_helper_crtc_set_property
,
13771 .destroy
= intel_crtc_destroy
,
13772 .page_flip
= intel_crtc_page_flip
,
13773 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13774 .atomic_destroy_state
= intel_crtc_destroy_state
,
13778 * intel_prepare_plane_fb - Prepare fb for usage on plane
13779 * @plane: drm plane to prepare for
13780 * @fb: framebuffer to prepare for presentation
13782 * Prepares a framebuffer for usage on a display plane. Generally this
13783 * involves pinning the underlying object and updating the frontbuffer tracking
13784 * bits. Some older platforms need special physical address handling for
13787 * Must be called with struct_mutex held.
13789 * Returns 0 on success, negative error code on failure.
13792 intel_prepare_plane_fb(struct drm_plane
*plane
,
13793 const struct drm_plane_state
*new_state
)
13795 struct drm_device
*dev
= plane
->dev
;
13796 struct drm_framebuffer
*fb
= new_state
->fb
;
13797 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13798 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13799 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->state
->fb
);
13802 if (!obj
&& !old_obj
)
13806 struct drm_crtc_state
*crtc_state
=
13807 drm_atomic_get_existing_crtc_state(new_state
->state
, plane
->state
->crtc
);
13809 /* Big Hammer, we also need to ensure that any pending
13810 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13811 * current scanout is retired before unpinning the old
13812 * framebuffer. Note that we rely on userspace rendering
13813 * into the buffer attached to the pipe they are waiting
13814 * on. If not, userspace generates a GPU hang with IPEHR
13815 * point to the MI_WAIT_FOR_EVENT.
13817 * This should only fail upon a hung GPU, in which case we
13818 * can safely continue.
13820 if (needs_modeset(crtc_state
))
13821 ret
= i915_gem_object_wait_rendering(old_obj
, true);
13823 /* GPU hangs should have been swallowed by the wait */
13824 WARN_ON(ret
== -EIO
);
13829 /* For framebuffer backed by dmabuf, wait for fence */
13830 if (obj
&& obj
->base
.dma_buf
) {
13833 lret
= reservation_object_wait_timeout_rcu(obj
->base
.dma_buf
->resv
,
13835 MAX_SCHEDULE_TIMEOUT
);
13836 if (lret
== -ERESTARTSYS
)
13839 WARN(lret
< 0, "waiting returns %li\n", lret
);
13844 } else if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
13845 INTEL_INFO(dev
)->cursor_needs_physical
) {
13846 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
13847 ret
= i915_gem_object_attach_phys(obj
, align
);
13849 DRM_DEBUG_KMS("failed to attach phys object\n");
13851 ret
= intel_pin_and_fence_fb_obj(fb
, new_state
->rotation
);
13856 struct intel_plane_state
*plane_state
=
13857 to_intel_plane_state(new_state
);
13859 i915_gem_request_assign(&plane_state
->wait_req
,
13860 obj
->last_write_req
);
13863 i915_gem_track_fb(old_obj
, obj
, intel_plane
->frontbuffer_bit
);
13870 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13871 * @plane: drm plane to clean up for
13872 * @fb: old framebuffer that was on plane
13874 * Cleans up a framebuffer that has just been removed from a plane.
13876 * Must be called with struct_mutex held.
13879 intel_cleanup_plane_fb(struct drm_plane
*plane
,
13880 const struct drm_plane_state
*old_state
)
13882 struct drm_device
*dev
= plane
->dev
;
13883 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13884 struct intel_plane_state
*old_intel_state
;
13885 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_state
->fb
);
13886 struct drm_i915_gem_object
*obj
= intel_fb_obj(plane
->state
->fb
);
13888 old_intel_state
= to_intel_plane_state(old_state
);
13890 if (!obj
&& !old_obj
)
13893 if (old_obj
&& (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
13894 !INTEL_INFO(dev
)->cursor_needs_physical
))
13895 intel_unpin_fb_obj(old_state
->fb
, old_state
->rotation
);
13897 /* prepare_fb aborted? */
13898 if ((old_obj
&& (old_obj
->frontbuffer_bits
& intel_plane
->frontbuffer_bit
)) ||
13899 (obj
&& !(obj
->frontbuffer_bits
& intel_plane
->frontbuffer_bit
)))
13900 i915_gem_track_fb(old_obj
, obj
, intel_plane
->frontbuffer_bit
);
13902 i915_gem_request_assign(&old_intel_state
->wait_req
, NULL
);
13906 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
13909 struct drm_device
*dev
;
13910 struct drm_i915_private
*dev_priv
;
13911 int crtc_clock
, cdclk
;
13913 if (!intel_crtc
|| !crtc_state
->base
.enable
)
13914 return DRM_PLANE_HELPER_NO_SCALING
;
13916 dev
= intel_crtc
->base
.dev
;
13917 dev_priv
= dev
->dev_private
;
13918 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
13919 cdclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
;
13921 if (WARN_ON_ONCE(!crtc_clock
|| cdclk
< crtc_clock
))
13922 return DRM_PLANE_HELPER_NO_SCALING
;
13925 * skl max scale is lower of:
13926 * close to 3 but not 3, -1 is for that purpose
13930 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
13936 intel_check_primary_plane(struct drm_plane
*plane
,
13937 struct intel_crtc_state
*crtc_state
,
13938 struct intel_plane_state
*state
)
13940 struct drm_crtc
*crtc
= state
->base
.crtc
;
13941 struct drm_framebuffer
*fb
= state
->base
.fb
;
13942 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13943 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13944 bool can_position
= false;
13946 if (INTEL_INFO(plane
->dev
)->gen
>= 9) {
13947 /* use scaler when colorkey is not required */
13948 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
13950 max_scale
= skl_max_scale(to_intel_crtc(crtc
), crtc_state
);
13952 can_position
= true;
13955 return drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
13956 &state
->dst
, &state
->clip
,
13957 min_scale
, max_scale
,
13958 can_position
, true,
13962 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
,
13963 struct drm_crtc_state
*old_crtc_state
)
13965 struct drm_device
*dev
= crtc
->dev
;
13966 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13967 struct intel_crtc_state
*old_intel_state
=
13968 to_intel_crtc_state(old_crtc_state
);
13969 bool modeset
= needs_modeset(crtc
->state
);
13971 /* Perform vblank evasion around commit operation */
13972 intel_pipe_update_start(intel_crtc
);
13977 if (crtc
->state
->color_mgmt_changed
|| to_intel_crtc_state(crtc
->state
)->update_pipe
) {
13978 intel_color_set_csc(crtc
->state
);
13979 intel_color_load_luts(crtc
->state
);
13982 if (to_intel_crtc_state(crtc
->state
)->update_pipe
)
13983 intel_update_pipe_config(intel_crtc
, old_intel_state
);
13984 else if (INTEL_INFO(dev
)->gen
>= 9)
13985 skl_detach_scalers(intel_crtc
);
13988 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
,
13989 struct drm_crtc_state
*old_crtc_state
)
13991 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13993 intel_pipe_update_end(intel_crtc
);
13997 * intel_plane_destroy - destroy a plane
13998 * @plane: plane to destroy
14000 * Common destruction function for all types of planes (primary, cursor,
14003 void intel_plane_destroy(struct drm_plane
*plane
)
14005 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
14006 drm_plane_cleanup(plane
);
14007 kfree(intel_plane
);
14010 const struct drm_plane_funcs intel_plane_funcs
= {
14011 .update_plane
= drm_atomic_helper_update_plane
,
14012 .disable_plane
= drm_atomic_helper_disable_plane
,
14013 .destroy
= intel_plane_destroy
,
14014 .set_property
= drm_atomic_helper_plane_set_property
,
14015 .atomic_get_property
= intel_plane_atomic_get_property
,
14016 .atomic_set_property
= intel_plane_atomic_set_property
,
14017 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14018 .atomic_destroy_state
= intel_plane_destroy_state
,
14022 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
14025 struct intel_plane
*primary
= NULL
;
14026 struct intel_plane_state
*state
= NULL
;
14027 const uint32_t *intel_primary_formats
;
14028 unsigned int num_formats
;
14031 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
14035 state
= intel_create_plane_state(&primary
->base
);
14038 primary
->base
.state
= &state
->base
;
14040 primary
->can_scale
= false;
14041 primary
->max_downscale
= 1;
14042 if (INTEL_INFO(dev
)->gen
>= 9) {
14043 primary
->can_scale
= true;
14044 state
->scaler_id
= -1;
14046 primary
->pipe
= pipe
;
14047 primary
->plane
= pipe
;
14048 primary
->frontbuffer_bit
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
14049 primary
->check_plane
= intel_check_primary_plane
;
14050 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
14051 primary
->plane
= !pipe
;
14053 if (INTEL_INFO(dev
)->gen
>= 9) {
14054 intel_primary_formats
= skl_primary_formats
;
14055 num_formats
= ARRAY_SIZE(skl_primary_formats
);
14057 primary
->update_plane
= skylake_update_primary_plane
;
14058 primary
->disable_plane
= skylake_disable_primary_plane
;
14059 } else if (HAS_PCH_SPLIT(dev
)) {
14060 intel_primary_formats
= i965_primary_formats
;
14061 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14063 primary
->update_plane
= ironlake_update_primary_plane
;
14064 primary
->disable_plane
= i9xx_disable_primary_plane
;
14065 } else if (INTEL_INFO(dev
)->gen
>= 4) {
14066 intel_primary_formats
= i965_primary_formats
;
14067 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14069 primary
->update_plane
= i9xx_update_primary_plane
;
14070 primary
->disable_plane
= i9xx_disable_primary_plane
;
14072 intel_primary_formats
= i8xx_primary_formats
;
14073 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
14075 primary
->update_plane
= i9xx_update_primary_plane
;
14076 primary
->disable_plane
= i9xx_disable_primary_plane
;
14079 ret
= drm_universal_plane_init(dev
, &primary
->base
, 0,
14080 &intel_plane_funcs
,
14081 intel_primary_formats
, num_formats
,
14082 DRM_PLANE_TYPE_PRIMARY
, NULL
);
14086 if (INTEL_INFO(dev
)->gen
>= 4)
14087 intel_create_rotation_property(dev
, primary
);
14089 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
14091 return &primary
->base
;
14100 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
14102 if (!dev
->mode_config
.rotation_property
) {
14103 unsigned long flags
= BIT(DRM_ROTATE_0
) |
14104 BIT(DRM_ROTATE_180
);
14106 if (INTEL_INFO(dev
)->gen
>= 9)
14107 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
14109 dev
->mode_config
.rotation_property
=
14110 drm_mode_create_rotation_property(dev
, flags
);
14112 if (dev
->mode_config
.rotation_property
)
14113 drm_object_attach_property(&plane
->base
.base
,
14114 dev
->mode_config
.rotation_property
,
14115 plane
->base
.state
->rotation
);
14119 intel_check_cursor_plane(struct drm_plane
*plane
,
14120 struct intel_crtc_state
*crtc_state
,
14121 struct intel_plane_state
*state
)
14123 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
14124 struct drm_framebuffer
*fb
= state
->base
.fb
;
14125 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
14126 enum pipe pipe
= to_intel_plane(plane
)->pipe
;
14130 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
14131 &state
->dst
, &state
->clip
,
14132 DRM_PLANE_HELPER_NO_SCALING
,
14133 DRM_PLANE_HELPER_NO_SCALING
,
14134 true, true, &state
->visible
);
14138 /* if we want to turn off the cursor ignore width and height */
14142 /* Check for which cursor types we support */
14143 if (!cursor_size_ok(plane
->dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
14144 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14145 state
->base
.crtc_w
, state
->base
.crtc_h
);
14149 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
14150 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
14151 DRM_DEBUG_KMS("buffer is too small\n");
14155 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
14156 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14161 * There's something wrong with the cursor on CHV pipe C.
14162 * If it straddles the left edge of the screen then
14163 * moving it away from the edge or disabling it often
14164 * results in a pipe underrun, and often that can lead to
14165 * dead pipe (constant underrun reported, and it scans
14166 * out just a solid color). To recover from that, the
14167 * display power well must be turned off and on again.
14168 * Refuse the put the cursor into that compromised position.
14170 if (IS_CHERRYVIEW(plane
->dev
) && pipe
== PIPE_C
&&
14171 state
->visible
&& state
->base
.crtc_x
< 0) {
14172 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14180 intel_disable_cursor_plane(struct drm_plane
*plane
,
14181 struct drm_crtc
*crtc
)
14183 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14185 intel_crtc
->cursor_addr
= 0;
14186 intel_crtc_update_cursor(crtc
, NULL
);
14190 intel_update_cursor_plane(struct drm_plane
*plane
,
14191 const struct intel_crtc_state
*crtc_state
,
14192 const struct intel_plane_state
*state
)
14194 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
14195 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14196 struct drm_device
*dev
= plane
->dev
;
14197 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
14202 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
14203 addr
= i915_gem_obj_ggtt_offset(obj
);
14205 addr
= obj
->phys_handle
->busaddr
;
14207 intel_crtc
->cursor_addr
= addr
;
14208 intel_crtc_update_cursor(crtc
, state
);
14211 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
14214 struct intel_plane
*cursor
= NULL
;
14215 struct intel_plane_state
*state
= NULL
;
14218 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
14222 state
= intel_create_plane_state(&cursor
->base
);
14225 cursor
->base
.state
= &state
->base
;
14227 cursor
->can_scale
= false;
14228 cursor
->max_downscale
= 1;
14229 cursor
->pipe
= pipe
;
14230 cursor
->plane
= pipe
;
14231 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER_CURSOR(pipe
);
14232 cursor
->check_plane
= intel_check_cursor_plane
;
14233 cursor
->update_plane
= intel_update_cursor_plane
;
14234 cursor
->disable_plane
= intel_disable_cursor_plane
;
14236 ret
= drm_universal_plane_init(dev
, &cursor
->base
, 0,
14237 &intel_plane_funcs
,
14238 intel_cursor_formats
,
14239 ARRAY_SIZE(intel_cursor_formats
),
14240 DRM_PLANE_TYPE_CURSOR
, NULL
);
14244 if (INTEL_INFO(dev
)->gen
>= 4) {
14245 if (!dev
->mode_config
.rotation_property
)
14246 dev
->mode_config
.rotation_property
=
14247 drm_mode_create_rotation_property(dev
,
14248 BIT(DRM_ROTATE_0
) |
14249 BIT(DRM_ROTATE_180
));
14250 if (dev
->mode_config
.rotation_property
)
14251 drm_object_attach_property(&cursor
->base
.base
,
14252 dev
->mode_config
.rotation_property
,
14253 state
->base
.rotation
);
14256 if (INTEL_INFO(dev
)->gen
>=9)
14257 state
->scaler_id
= -1;
14259 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
14261 return &cursor
->base
;
14270 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
14271 struct intel_crtc_state
*crtc_state
)
14274 struct intel_scaler
*intel_scaler
;
14275 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
14277 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
14278 intel_scaler
= &scaler_state
->scalers
[i
];
14279 intel_scaler
->in_use
= 0;
14280 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
14283 scaler_state
->scaler_id
= -1;
14286 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
14288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14289 struct intel_crtc
*intel_crtc
;
14290 struct intel_crtc_state
*crtc_state
= NULL
;
14291 struct drm_plane
*primary
= NULL
;
14292 struct drm_plane
*cursor
= NULL
;
14295 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
14296 if (intel_crtc
== NULL
)
14299 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
14302 intel_crtc
->config
= crtc_state
;
14303 intel_crtc
->base
.state
= &crtc_state
->base
;
14304 crtc_state
->base
.crtc
= &intel_crtc
->base
;
14306 /* initialize shared scalers */
14307 if (INTEL_INFO(dev
)->gen
>= 9) {
14308 if (pipe
== PIPE_C
)
14309 intel_crtc
->num_scalers
= 1;
14311 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
14313 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
14316 primary
= intel_primary_plane_create(dev
, pipe
);
14320 cursor
= intel_cursor_plane_create(dev
, pipe
);
14324 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
14325 cursor
, &intel_crtc_funcs
, NULL
);
14330 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14331 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14333 intel_crtc
->pipe
= pipe
;
14334 intel_crtc
->plane
= pipe
;
14335 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
14336 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14337 intel_crtc
->plane
= !pipe
;
14340 intel_crtc
->cursor_base
= ~0;
14341 intel_crtc
->cursor_cntl
= ~0;
14342 intel_crtc
->cursor_size
= ~0;
14344 intel_crtc
->wm
.cxsr_allowed
= true;
14346 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
14347 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
14348 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
14349 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
14351 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
14353 intel_color_init(&intel_crtc
->base
);
14355 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
14360 drm_plane_cleanup(primary
);
14362 drm_plane_cleanup(cursor
);
14367 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
14369 struct drm_encoder
*encoder
= connector
->base
.encoder
;
14370 struct drm_device
*dev
= connector
->base
.dev
;
14372 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
14374 if (!encoder
|| WARN_ON(!encoder
->crtc
))
14375 return INVALID_PIPE
;
14377 return to_intel_crtc(encoder
->crtc
)->pipe
;
14380 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
14381 struct drm_file
*file
)
14383 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
14384 struct drm_crtc
*drmmode_crtc
;
14385 struct intel_crtc
*crtc
;
14387 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
14389 if (!drmmode_crtc
) {
14390 DRM_ERROR("no such CRTC id\n");
14394 crtc
= to_intel_crtc(drmmode_crtc
);
14395 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
14400 static int intel_encoder_clones(struct intel_encoder
*encoder
)
14402 struct drm_device
*dev
= encoder
->base
.dev
;
14403 struct intel_encoder
*source_encoder
;
14404 int index_mask
= 0;
14407 for_each_intel_encoder(dev
, source_encoder
) {
14408 if (encoders_cloneable(encoder
, source_encoder
))
14409 index_mask
|= (1 << entry
);
14417 static bool has_edp_a(struct drm_device
*dev
)
14419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14421 if (!IS_MOBILE(dev
))
14424 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
14427 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
14433 static bool intel_crt_present(struct drm_device
*dev
)
14435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14437 if (INTEL_INFO(dev
)->gen
>= 9)
14440 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
14443 if (IS_CHERRYVIEW(dev
))
14446 if (HAS_PCH_LPT_H(dev
) && I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
14449 /* DDI E can't be used if DDI A requires 4 lanes */
14450 if (HAS_DDI(dev
) && I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
14453 if (!dev_priv
->vbt
.int_crt_support
)
14459 static void intel_setup_outputs(struct drm_device
*dev
)
14461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14462 struct intel_encoder
*encoder
;
14463 bool dpd_is_edp
= false;
14465 intel_lvds_init(dev
);
14467 if (intel_crt_present(dev
))
14468 intel_crt_init(dev
);
14470 if (IS_BROXTON(dev
)) {
14472 * FIXME: Broxton doesn't support port detection via the
14473 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14474 * detect the ports.
14476 intel_ddi_init(dev
, PORT_A
);
14477 intel_ddi_init(dev
, PORT_B
);
14478 intel_ddi_init(dev
, PORT_C
);
14480 intel_dsi_init(dev
);
14481 } else if (HAS_DDI(dev
)) {
14485 * Haswell uses DDI functions to detect digital outputs.
14486 * On SKL pre-D0 the strap isn't connected, so we assume
14489 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
14490 /* WaIgnoreDDIAStrap: skl */
14491 if (found
|| IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
14492 intel_ddi_init(dev
, PORT_A
);
14494 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14496 found
= I915_READ(SFUSE_STRAP
);
14498 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
14499 intel_ddi_init(dev
, PORT_B
);
14500 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
14501 intel_ddi_init(dev
, PORT_C
);
14502 if (found
& SFUSE_STRAP_DDID_DETECTED
)
14503 intel_ddi_init(dev
, PORT_D
);
14505 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14507 if ((IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) &&
14508 (dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dp
||
14509 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dvi
||
14510 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_hdmi
))
14511 intel_ddi_init(dev
, PORT_E
);
14513 } else if (HAS_PCH_SPLIT(dev
)) {
14515 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
14517 if (has_edp_a(dev
))
14518 intel_dp_init(dev
, DP_A
, PORT_A
);
14520 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
14521 /* PCH SDVOB multiplex with HDMIB */
14522 found
= intel_sdvo_init(dev
, PCH_SDVOB
, PORT_B
);
14524 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
14525 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
14526 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
14529 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
14530 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
14532 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
14533 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
14535 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
14536 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
14538 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
14539 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
14540 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
14542 * The DP_DETECTED bit is the latched state of the DDC
14543 * SDA pin at boot. However since eDP doesn't require DDC
14544 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14545 * eDP ports may have been muxed to an alternate function.
14546 * Thus we can't rely on the DP_DETECTED bit alone to detect
14547 * eDP ports. Consult the VBT as well as DP_DETECTED to
14548 * detect eDP ports.
14550 if (I915_READ(VLV_HDMIB
) & SDVO_DETECTED
&&
14551 !intel_dp_is_edp(dev
, PORT_B
))
14552 intel_hdmi_init(dev
, VLV_HDMIB
, PORT_B
);
14553 if (I915_READ(VLV_DP_B
) & DP_DETECTED
||
14554 intel_dp_is_edp(dev
, PORT_B
))
14555 intel_dp_init(dev
, VLV_DP_B
, PORT_B
);
14557 if (I915_READ(VLV_HDMIC
) & SDVO_DETECTED
&&
14558 !intel_dp_is_edp(dev
, PORT_C
))
14559 intel_hdmi_init(dev
, VLV_HDMIC
, PORT_C
);
14560 if (I915_READ(VLV_DP_C
) & DP_DETECTED
||
14561 intel_dp_is_edp(dev
, PORT_C
))
14562 intel_dp_init(dev
, VLV_DP_C
, PORT_C
);
14564 if (IS_CHERRYVIEW(dev
)) {
14565 /* eDP not supported on port D, so don't check VBT */
14566 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
)
14567 intel_hdmi_init(dev
, CHV_HDMID
, PORT_D
);
14568 if (I915_READ(CHV_DP_D
) & DP_DETECTED
)
14569 intel_dp_init(dev
, CHV_DP_D
, PORT_D
);
14572 intel_dsi_init(dev
);
14573 } else if (!IS_GEN2(dev
) && !IS_PINEVIEW(dev
)) {
14574 bool found
= false;
14576 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14577 DRM_DEBUG_KMS("probing SDVOB\n");
14578 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, PORT_B
);
14579 if (!found
&& IS_G4X(dev
)) {
14580 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14581 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
14584 if (!found
&& IS_G4X(dev
))
14585 intel_dp_init(dev
, DP_B
, PORT_B
);
14588 /* Before G4X SDVOC doesn't have its own detect register */
14590 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14591 DRM_DEBUG_KMS("probing SDVOC\n");
14592 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, PORT_C
);
14595 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14598 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14599 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
14602 intel_dp_init(dev
, DP_C
, PORT_C
);
14606 (I915_READ(DP_D
) & DP_DETECTED
))
14607 intel_dp_init(dev
, DP_D
, PORT_D
);
14608 } else if (IS_GEN2(dev
))
14609 intel_dvo_init(dev
);
14611 if (SUPPORTS_TV(dev
))
14612 intel_tv_init(dev
);
14614 intel_psr_init(dev
);
14616 for_each_intel_encoder(dev
, encoder
) {
14617 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
14618 encoder
->base
.possible_clones
=
14619 intel_encoder_clones(encoder
);
14622 intel_init_pch_refclk(dev
);
14624 drm_helper_move_panel_connectors_to_head(dev
);
14627 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
14629 struct drm_device
*dev
= fb
->dev
;
14630 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14632 drm_framebuffer_cleanup(fb
);
14633 mutex_lock(&dev
->struct_mutex
);
14634 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
14635 drm_gem_object_unreference(&intel_fb
->obj
->base
);
14636 mutex_unlock(&dev
->struct_mutex
);
14640 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
14641 struct drm_file
*file
,
14642 unsigned int *handle
)
14644 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14645 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14647 if (obj
->userptr
.mm
) {
14648 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14652 return drm_gem_handle_create(file
, &obj
->base
, handle
);
14655 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
14656 struct drm_file
*file
,
14657 unsigned flags
, unsigned color
,
14658 struct drm_clip_rect
*clips
,
14659 unsigned num_clips
)
14661 struct drm_device
*dev
= fb
->dev
;
14662 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14663 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14665 mutex_lock(&dev
->struct_mutex
);
14666 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
14667 mutex_unlock(&dev
->struct_mutex
);
14672 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
14673 .destroy
= intel_user_framebuffer_destroy
,
14674 .create_handle
= intel_user_framebuffer_create_handle
,
14675 .dirty
= intel_user_framebuffer_dirty
,
14679 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
14680 uint32_t pixel_format
)
14682 u32 gen
= INTEL_INFO(dev
)->gen
;
14685 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
14687 /* "The stride in bytes must not exceed the of the size of 8K
14688 * pixels and 32K bytes."
14690 return min(8192 * cpp
, 32768);
14691 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
14693 } else if (gen
>= 4) {
14694 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14698 } else if (gen
>= 3) {
14699 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14704 /* XXX DSPC is limited to 4k tiled */
14709 static int intel_framebuffer_init(struct drm_device
*dev
,
14710 struct intel_framebuffer
*intel_fb
,
14711 struct drm_mode_fb_cmd2
*mode_cmd
,
14712 struct drm_i915_gem_object
*obj
)
14714 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14715 unsigned int aligned_height
;
14717 u32 pitch_limit
, stride_alignment
;
14719 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
14721 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
14722 /* Enforce that fb modifier and tiling mode match, but only for
14723 * X-tiled. This is needed for FBC. */
14724 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
14725 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
14726 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14730 if (obj
->tiling_mode
== I915_TILING_X
)
14731 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
14732 else if (obj
->tiling_mode
== I915_TILING_Y
) {
14733 DRM_DEBUG("No Y tiling for legacy addfb\n");
14738 /* Passed in modifier sanity checking. */
14739 switch (mode_cmd
->modifier
[0]) {
14740 case I915_FORMAT_MOD_Y_TILED
:
14741 case I915_FORMAT_MOD_Yf_TILED
:
14742 if (INTEL_INFO(dev
)->gen
< 9) {
14743 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14744 mode_cmd
->modifier
[0]);
14747 case DRM_FORMAT_MOD_NONE
:
14748 case I915_FORMAT_MOD_X_TILED
:
14751 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14752 mode_cmd
->modifier
[0]);
14756 stride_alignment
= intel_fb_stride_alignment(dev_priv
,
14757 mode_cmd
->modifier
[0],
14758 mode_cmd
->pixel_format
);
14759 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
14760 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14761 mode_cmd
->pitches
[0], stride_alignment
);
14765 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
14766 mode_cmd
->pixel_format
);
14767 if (mode_cmd
->pitches
[0] > pitch_limit
) {
14768 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14769 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
14770 "tiled" : "linear",
14771 mode_cmd
->pitches
[0], pitch_limit
);
14775 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
14776 mode_cmd
->pitches
[0] != obj
->stride
) {
14777 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14778 mode_cmd
->pitches
[0], obj
->stride
);
14782 /* Reject formats not supported by any plane early. */
14783 switch (mode_cmd
->pixel_format
) {
14784 case DRM_FORMAT_C8
:
14785 case DRM_FORMAT_RGB565
:
14786 case DRM_FORMAT_XRGB8888
:
14787 case DRM_FORMAT_ARGB8888
:
14789 case DRM_FORMAT_XRGB1555
:
14790 if (INTEL_INFO(dev
)->gen
> 3) {
14791 DRM_DEBUG("unsupported pixel format: %s\n",
14792 drm_get_format_name(mode_cmd
->pixel_format
));
14796 case DRM_FORMAT_ABGR8888
:
14797 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
14798 INTEL_INFO(dev
)->gen
< 9) {
14799 DRM_DEBUG("unsupported pixel format: %s\n",
14800 drm_get_format_name(mode_cmd
->pixel_format
));
14804 case DRM_FORMAT_XBGR8888
:
14805 case DRM_FORMAT_XRGB2101010
:
14806 case DRM_FORMAT_XBGR2101010
:
14807 if (INTEL_INFO(dev
)->gen
< 4) {
14808 DRM_DEBUG("unsupported pixel format: %s\n",
14809 drm_get_format_name(mode_cmd
->pixel_format
));
14813 case DRM_FORMAT_ABGR2101010
:
14814 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
14815 DRM_DEBUG("unsupported pixel format: %s\n",
14816 drm_get_format_name(mode_cmd
->pixel_format
));
14820 case DRM_FORMAT_YUYV
:
14821 case DRM_FORMAT_UYVY
:
14822 case DRM_FORMAT_YVYU
:
14823 case DRM_FORMAT_VYUY
:
14824 if (INTEL_INFO(dev
)->gen
< 5) {
14825 DRM_DEBUG("unsupported pixel format: %s\n",
14826 drm_get_format_name(mode_cmd
->pixel_format
));
14831 DRM_DEBUG("unsupported pixel format: %s\n",
14832 drm_get_format_name(mode_cmd
->pixel_format
));
14836 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14837 if (mode_cmd
->offsets
[0] != 0)
14840 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
14841 mode_cmd
->pixel_format
,
14842 mode_cmd
->modifier
[0]);
14843 /* FIXME drm helper for size checks (especially planar formats)? */
14844 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
14847 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
14848 intel_fb
->obj
= obj
;
14850 intel_fill_fb_info(dev_priv
, &intel_fb
->base
);
14852 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
14854 DRM_ERROR("framebuffer init failed %d\n", ret
);
14858 intel_fb
->obj
->framebuffer_references
++;
14863 static struct drm_framebuffer
*
14864 intel_user_framebuffer_create(struct drm_device
*dev
,
14865 struct drm_file
*filp
,
14866 const struct drm_mode_fb_cmd2
*user_mode_cmd
)
14868 struct drm_framebuffer
*fb
;
14869 struct drm_i915_gem_object
*obj
;
14870 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
14872 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
14873 mode_cmd
.handles
[0]));
14874 if (&obj
->base
== NULL
)
14875 return ERR_PTR(-ENOENT
);
14877 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
14879 drm_gem_object_unreference_unlocked(&obj
->base
);
14884 #ifndef CONFIG_DRM_FBDEV_EMULATION
14885 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
14890 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14891 .fb_create
= intel_user_framebuffer_create
,
14892 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14893 .atomic_check
= intel_atomic_check
,
14894 .atomic_commit
= intel_atomic_commit
,
14895 .atomic_state_alloc
= intel_atomic_state_alloc
,
14896 .atomic_state_clear
= intel_atomic_state_clear
,
14900 * intel_init_display_hooks - initialize the display modesetting hooks
14901 * @dev_priv: device private
14903 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
14905 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
14906 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14907 dev_priv
->display
.get_initial_plane_config
=
14908 skylake_get_initial_plane_config
;
14909 dev_priv
->display
.crtc_compute_clock
=
14910 haswell_crtc_compute_clock
;
14911 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14912 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14913 } else if (HAS_DDI(dev_priv
)) {
14914 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14915 dev_priv
->display
.get_initial_plane_config
=
14916 ironlake_get_initial_plane_config
;
14917 dev_priv
->display
.crtc_compute_clock
=
14918 haswell_crtc_compute_clock
;
14919 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14920 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14921 } else if (HAS_PCH_SPLIT(dev_priv
)) {
14922 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14923 dev_priv
->display
.get_initial_plane_config
=
14924 ironlake_get_initial_plane_config
;
14925 dev_priv
->display
.crtc_compute_clock
=
14926 ironlake_crtc_compute_clock
;
14927 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14928 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14929 } else if (IS_CHERRYVIEW(dev_priv
)) {
14930 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14931 dev_priv
->display
.get_initial_plane_config
=
14932 i9xx_get_initial_plane_config
;
14933 dev_priv
->display
.crtc_compute_clock
= chv_crtc_compute_clock
;
14934 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14935 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14936 } else if (IS_VALLEYVIEW(dev_priv
)) {
14937 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14938 dev_priv
->display
.get_initial_plane_config
=
14939 i9xx_get_initial_plane_config
;
14940 dev_priv
->display
.crtc_compute_clock
= vlv_crtc_compute_clock
;
14941 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14942 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14943 } else if (IS_G4X(dev_priv
)) {
14944 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14945 dev_priv
->display
.get_initial_plane_config
=
14946 i9xx_get_initial_plane_config
;
14947 dev_priv
->display
.crtc_compute_clock
= g4x_crtc_compute_clock
;
14948 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14949 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14950 } else if (IS_PINEVIEW(dev_priv
)) {
14951 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14952 dev_priv
->display
.get_initial_plane_config
=
14953 i9xx_get_initial_plane_config
;
14954 dev_priv
->display
.crtc_compute_clock
= pnv_crtc_compute_clock
;
14955 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14956 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14957 } else if (!IS_GEN2(dev_priv
)) {
14958 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14959 dev_priv
->display
.get_initial_plane_config
=
14960 i9xx_get_initial_plane_config
;
14961 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14962 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14963 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14965 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14966 dev_priv
->display
.get_initial_plane_config
=
14967 i9xx_get_initial_plane_config
;
14968 dev_priv
->display
.crtc_compute_clock
= i8xx_crtc_compute_clock
;
14969 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14970 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14973 /* Returns the core display clock speed */
14974 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
14975 dev_priv
->display
.get_display_clock_speed
=
14976 skylake_get_display_clock_speed
;
14977 else if (IS_BROXTON(dev_priv
))
14978 dev_priv
->display
.get_display_clock_speed
=
14979 broxton_get_display_clock_speed
;
14980 else if (IS_BROADWELL(dev_priv
))
14981 dev_priv
->display
.get_display_clock_speed
=
14982 broadwell_get_display_clock_speed
;
14983 else if (IS_HASWELL(dev_priv
))
14984 dev_priv
->display
.get_display_clock_speed
=
14985 haswell_get_display_clock_speed
;
14986 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
14987 dev_priv
->display
.get_display_clock_speed
=
14988 valleyview_get_display_clock_speed
;
14989 else if (IS_GEN5(dev_priv
))
14990 dev_priv
->display
.get_display_clock_speed
=
14991 ilk_get_display_clock_speed
;
14992 else if (IS_I945G(dev_priv
) || IS_BROADWATER(dev_priv
) ||
14993 IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
))
14994 dev_priv
->display
.get_display_clock_speed
=
14995 i945_get_display_clock_speed
;
14996 else if (IS_GM45(dev_priv
))
14997 dev_priv
->display
.get_display_clock_speed
=
14998 gm45_get_display_clock_speed
;
14999 else if (IS_CRESTLINE(dev_priv
))
15000 dev_priv
->display
.get_display_clock_speed
=
15001 i965gm_get_display_clock_speed
;
15002 else if (IS_PINEVIEW(dev_priv
))
15003 dev_priv
->display
.get_display_clock_speed
=
15004 pnv_get_display_clock_speed
;
15005 else if (IS_G33(dev_priv
) || IS_G4X(dev_priv
))
15006 dev_priv
->display
.get_display_clock_speed
=
15007 g33_get_display_clock_speed
;
15008 else if (IS_I915G(dev_priv
))
15009 dev_priv
->display
.get_display_clock_speed
=
15010 i915_get_display_clock_speed
;
15011 else if (IS_I945GM(dev_priv
) || IS_845G(dev_priv
))
15012 dev_priv
->display
.get_display_clock_speed
=
15013 i9xx_misc_get_display_clock_speed
;
15014 else if (IS_I915GM(dev_priv
))
15015 dev_priv
->display
.get_display_clock_speed
=
15016 i915gm_get_display_clock_speed
;
15017 else if (IS_I865G(dev_priv
))
15018 dev_priv
->display
.get_display_clock_speed
=
15019 i865_get_display_clock_speed
;
15020 else if (IS_I85X(dev_priv
))
15021 dev_priv
->display
.get_display_clock_speed
=
15022 i85x_get_display_clock_speed
;
15024 WARN(!IS_I830(dev_priv
), "Unknown platform. Assuming 133 MHz CDCLK\n");
15025 dev_priv
->display
.get_display_clock_speed
=
15026 i830_get_display_clock_speed
;
15029 if (IS_GEN5(dev_priv
)) {
15030 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
15031 } else if (IS_GEN6(dev_priv
)) {
15032 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
15033 } else if (IS_IVYBRIDGE(dev_priv
)) {
15034 /* FIXME: detect B0+ stepping and use auto training */
15035 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
15036 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
15037 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
15038 if (IS_BROADWELL(dev_priv
)) {
15039 dev_priv
->display
.modeset_commit_cdclk
=
15040 broadwell_modeset_commit_cdclk
;
15041 dev_priv
->display
.modeset_calc_cdclk
=
15042 broadwell_modeset_calc_cdclk
;
15044 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
15045 dev_priv
->display
.modeset_commit_cdclk
=
15046 valleyview_modeset_commit_cdclk
;
15047 dev_priv
->display
.modeset_calc_cdclk
=
15048 valleyview_modeset_calc_cdclk
;
15049 } else if (IS_BROXTON(dev_priv
)) {
15050 dev_priv
->display
.modeset_commit_cdclk
=
15051 broxton_modeset_commit_cdclk
;
15052 dev_priv
->display
.modeset_calc_cdclk
=
15053 broxton_modeset_calc_cdclk
;
15056 switch (INTEL_INFO(dev_priv
)->gen
) {
15058 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
15062 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
15067 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
15071 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
15074 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15075 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
15078 /* Drop through - unsupported since execlist only. */
15080 /* Default just returns -ENODEV to indicate unsupported */
15081 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
15086 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15087 * resume, or other times. This quirk makes sure that's the case for
15088 * affected systems.
15090 static void quirk_pipea_force(struct drm_device
*dev
)
15092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15094 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
15095 DRM_INFO("applying pipe a force quirk\n");
15098 static void quirk_pipeb_force(struct drm_device
*dev
)
15100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15102 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
15103 DRM_INFO("applying pipe b force quirk\n");
15107 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15109 static void quirk_ssc_force_disable(struct drm_device
*dev
)
15111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15112 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
15113 DRM_INFO("applying lvds SSC disable quirk\n");
15117 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15120 static void quirk_invert_brightness(struct drm_device
*dev
)
15122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15123 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
15124 DRM_INFO("applying inverted panel brightness quirk\n");
15127 /* Some VBT's incorrectly indicate no backlight is present */
15128 static void quirk_backlight_present(struct drm_device
*dev
)
15130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15131 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
15132 DRM_INFO("applying backlight present quirk\n");
15135 struct intel_quirk
{
15137 int subsystem_vendor
;
15138 int subsystem_device
;
15139 void (*hook
)(struct drm_device
*dev
);
15142 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15143 struct intel_dmi_quirk
{
15144 void (*hook
)(struct drm_device
*dev
);
15145 const struct dmi_system_id (*dmi_id_list
)[];
15148 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
15150 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
15154 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
15156 .dmi_id_list
= &(const struct dmi_system_id
[]) {
15158 .callback
= intel_dmi_reverse_brightness
,
15159 .ident
= "NCR Corporation",
15160 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
15161 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
15164 { } /* terminating entry */
15166 .hook
= quirk_invert_brightness
,
15170 static struct intel_quirk intel_quirks
[] = {
15171 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15172 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
15174 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15175 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
15177 /* 830 needs to leave pipe A & dpll A up */
15178 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
15180 /* 830 needs to leave pipe B & dpll B up */
15181 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
15183 /* Lenovo U160 cannot use SSC on LVDS */
15184 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
15186 /* Sony Vaio Y cannot use SSC on LVDS */
15187 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
15189 /* Acer Aspire 5734Z must invert backlight brightness */
15190 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
15192 /* Acer/eMachines G725 */
15193 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
15195 /* Acer/eMachines e725 */
15196 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
15198 /* Acer/Packard Bell NCL20 */
15199 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
15201 /* Acer Aspire 4736Z */
15202 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
15204 /* Acer Aspire 5336 */
15205 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
15207 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15208 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
15210 /* Acer C720 Chromebook (Core i3 4005U) */
15211 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
15213 /* Apple Macbook 2,1 (Core 2 T7400) */
15214 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
15216 /* Apple Macbook 4,1 */
15217 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present
},
15219 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15220 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
15222 /* HP Chromebook 14 (Celeron 2955U) */
15223 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
15225 /* Dell Chromebook 11 */
15226 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
15228 /* Dell Chromebook 11 (2015 version) */
15229 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present
},
15232 static void intel_init_quirks(struct drm_device
*dev
)
15234 struct pci_dev
*d
= dev
->pdev
;
15237 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
15238 struct intel_quirk
*q
= &intel_quirks
[i
];
15240 if (d
->device
== q
->device
&&
15241 (d
->subsystem_vendor
== q
->subsystem_vendor
||
15242 q
->subsystem_vendor
== PCI_ANY_ID
) &&
15243 (d
->subsystem_device
== q
->subsystem_device
||
15244 q
->subsystem_device
== PCI_ANY_ID
))
15247 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
15248 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
15249 intel_dmi_quirks
[i
].hook(dev
);
15253 /* Disable the VGA plane that we never use */
15254 static void i915_disable_vga(struct drm_device
*dev
)
15256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15258 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev
);
15260 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15261 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15262 outb(SR01
, VGA_SR_INDEX
);
15263 sr1
= inb(VGA_SR_DATA
);
15264 outb(sr1
| 1<<5, VGA_SR_DATA
);
15265 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15268 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
15269 POSTING_READ(vga_reg
);
15272 void intel_modeset_init_hw(struct drm_device
*dev
)
15274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15276 intel_update_cdclk(dev
);
15278 dev_priv
->atomic_cdclk_freq
= dev_priv
->cdclk_freq
;
15280 intel_init_clock_gating(dev
);
15281 intel_enable_gt_powersave(dev
);
15285 * Calculate what we think the watermarks should be for the state we've read
15286 * out of the hardware and then immediately program those watermarks so that
15287 * we ensure the hardware settings match our internal state.
15289 * We can calculate what we think WM's should be by creating a duplicate of the
15290 * current state (which was constructed during hardware readout) and running it
15291 * through the atomic check code to calculate new watermark values in the
15294 static void sanitize_watermarks(struct drm_device
*dev
)
15296 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15297 struct drm_atomic_state
*state
;
15298 struct drm_crtc
*crtc
;
15299 struct drm_crtc_state
*cstate
;
15300 struct drm_modeset_acquire_ctx ctx
;
15304 /* Only supported on platforms that use atomic watermark design */
15305 if (!dev_priv
->display
.optimize_watermarks
)
15309 * We need to hold connection_mutex before calling duplicate_state so
15310 * that the connector loop is protected.
15312 drm_modeset_acquire_init(&ctx
, 0);
15314 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
15315 if (ret
== -EDEADLK
) {
15316 drm_modeset_backoff(&ctx
);
15318 } else if (WARN_ON(ret
)) {
15322 state
= drm_atomic_helper_duplicate_state(dev
, &ctx
);
15323 if (WARN_ON(IS_ERR(state
)))
15327 * Hardware readout is the only time we don't want to calculate
15328 * intermediate watermarks (since we don't trust the current
15331 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
15333 ret
= intel_atomic_check(dev
, state
);
15336 * If we fail here, it means that the hardware appears to be
15337 * programmed in a way that shouldn't be possible, given our
15338 * understanding of watermark requirements. This might mean a
15339 * mistake in the hardware readout code or a mistake in the
15340 * watermark calculations for a given platform. Raise a WARN
15341 * so that this is noticeable.
15343 * If this actually happens, we'll have to just leave the
15344 * BIOS-programmed watermarks untouched and hope for the best.
15346 WARN(true, "Could not determine valid watermarks for inherited state\n");
15350 /* Write calculated watermark values back */
15351 to_i915(dev
)->wm
.config
= to_intel_atomic_state(state
)->wm_config
;
15352 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
15353 struct intel_crtc_state
*cs
= to_intel_crtc_state(cstate
);
15355 cs
->wm
.need_postvbl_update
= true;
15356 dev_priv
->display
.optimize_watermarks(cs
);
15359 drm_atomic_state_free(state
);
15361 drm_modeset_drop_locks(&ctx
);
15362 drm_modeset_acquire_fini(&ctx
);
15365 void intel_modeset_init(struct drm_device
*dev
)
15367 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15368 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
15371 struct intel_crtc
*crtc
;
15373 drm_mode_config_init(dev
);
15375 dev
->mode_config
.min_width
= 0;
15376 dev
->mode_config
.min_height
= 0;
15378 dev
->mode_config
.preferred_depth
= 24;
15379 dev
->mode_config
.prefer_shadow
= 1;
15381 dev
->mode_config
.allow_fb_modifiers
= true;
15383 dev
->mode_config
.funcs
= &intel_mode_funcs
;
15385 intel_init_quirks(dev
);
15387 intel_init_pm(dev
);
15389 if (INTEL_INFO(dev
)->num_pipes
== 0)
15393 * There may be no VBT; and if the BIOS enabled SSC we can
15394 * just keep using it to avoid unnecessary flicker. Whereas if the
15395 * BIOS isn't using it, don't assume it will work even if the VBT
15396 * indicates as much.
15398 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
15399 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15402 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
15403 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15404 bios_lvds_use_ssc
? "en" : "dis",
15405 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
15406 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
15410 if (IS_GEN2(dev
)) {
15411 dev
->mode_config
.max_width
= 2048;
15412 dev
->mode_config
.max_height
= 2048;
15413 } else if (IS_GEN3(dev
)) {
15414 dev
->mode_config
.max_width
= 4096;
15415 dev
->mode_config
.max_height
= 4096;
15417 dev
->mode_config
.max_width
= 8192;
15418 dev
->mode_config
.max_height
= 8192;
15421 if (IS_845G(dev
) || IS_I865G(dev
)) {
15422 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
15423 dev
->mode_config
.cursor_height
= 1023;
15424 } else if (IS_GEN2(dev
)) {
15425 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
15426 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
15428 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
15429 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
15432 dev
->mode_config
.fb_base
= ggtt
->mappable_base
;
15434 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15435 INTEL_INFO(dev
)->num_pipes
,
15436 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
15438 for_each_pipe(dev_priv
, pipe
) {
15439 intel_crtc_init(dev
, pipe
);
15440 for_each_sprite(dev_priv
, pipe
, sprite
) {
15441 ret
= intel_plane_init(dev
, pipe
, sprite
);
15443 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15444 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
15448 intel_update_czclk(dev_priv
);
15449 intel_update_cdclk(dev
);
15451 intel_shared_dpll_init(dev
);
15453 /* Just disable it once at startup */
15454 i915_disable_vga(dev
);
15455 intel_setup_outputs(dev
);
15457 drm_modeset_lock_all(dev
);
15458 intel_modeset_setup_hw_state(dev
);
15459 drm_modeset_unlock_all(dev
);
15461 for_each_intel_crtc(dev
, crtc
) {
15462 struct intel_initial_plane_config plane_config
= {};
15468 * Note that reserving the BIOS fb up front prevents us
15469 * from stuffing other stolen allocations like the ring
15470 * on top. This prevents some ugliness at boot time, and
15471 * can even allow for smooth boot transitions if the BIOS
15472 * fb is large enough for the active pipe configuration.
15474 dev_priv
->display
.get_initial_plane_config(crtc
,
15478 * If the fb is shared between multiple heads, we'll
15479 * just get the first one.
15481 intel_find_initial_plane_obj(crtc
, &plane_config
);
15485 * Make sure hardware watermarks really match the state we read out.
15486 * Note that we need to do this after reconstructing the BIOS fb's
15487 * since the watermark calculation done here will use pstate->fb.
15489 sanitize_watermarks(dev
);
15492 static void intel_enable_pipe_a(struct drm_device
*dev
)
15494 struct intel_connector
*connector
;
15495 struct drm_connector
*crt
= NULL
;
15496 struct intel_load_detect_pipe load_detect_temp
;
15497 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
15499 /* We can't just switch on the pipe A, we need to set things up with a
15500 * proper mode and output configuration. As a gross hack, enable pipe A
15501 * by enabling the load detect pipe once. */
15502 for_each_intel_connector(dev
, connector
) {
15503 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
15504 crt
= &connector
->base
;
15512 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
15513 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
15517 intel_check_plane_mapping(struct intel_crtc
*crtc
)
15519 struct drm_device
*dev
= crtc
->base
.dev
;
15520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15523 if (INTEL_INFO(dev
)->num_pipes
== 1)
15526 val
= I915_READ(DSPCNTR(!crtc
->plane
));
15528 if ((val
& DISPLAY_PLANE_ENABLE
) &&
15529 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
15535 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
15537 struct drm_device
*dev
= crtc
->base
.dev
;
15538 struct intel_encoder
*encoder
;
15540 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
15546 static bool intel_encoder_has_connectors(struct intel_encoder
*encoder
)
15548 struct drm_device
*dev
= encoder
->base
.dev
;
15549 struct intel_connector
*connector
;
15551 for_each_connector_on_encoder(dev
, &encoder
->base
, connector
)
15557 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
15559 struct drm_device
*dev
= crtc
->base
.dev
;
15560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15561 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
15563 /* Clear any frame start delays used for debugging left by the BIOS */
15564 if (!transcoder_is_dsi(cpu_transcoder
)) {
15565 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
15568 I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
15571 /* restore vblank interrupts to correct state */
15572 drm_crtc_vblank_reset(&crtc
->base
);
15573 if (crtc
->active
) {
15574 struct intel_plane
*plane
;
15576 drm_crtc_vblank_on(&crtc
->base
);
15578 /* Disable everything but the primary plane */
15579 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
15580 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
15583 plane
->disable_plane(&plane
->base
, &crtc
->base
);
15587 /* We need to sanitize the plane -> pipe mapping first because this will
15588 * disable the crtc (and hence change the state) if it is wrong. Note
15589 * that gen4+ has a fixed plane -> pipe mapping. */
15590 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
15593 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15594 crtc
->base
.base
.id
);
15596 /* Pipe has the wrong plane attached and the plane is active.
15597 * Temporarily change the plane mapping and disable everything
15599 plane
= crtc
->plane
;
15600 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
15601 crtc
->plane
= !plane
;
15602 intel_crtc_disable_noatomic(&crtc
->base
);
15603 crtc
->plane
= plane
;
15606 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
15607 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
15608 /* BIOS forgot to enable pipe A, this mostly happens after
15609 * resume. Force-enable the pipe to fix this, the update_dpms
15610 * call below we restore the pipe to the right state, but leave
15611 * the required bits on. */
15612 intel_enable_pipe_a(dev
);
15615 /* Adjust the state of the output pipe according to whether we
15616 * have active connectors/encoders. */
15617 if (crtc
->active
&& !intel_crtc_has_encoders(crtc
))
15618 intel_crtc_disable_noatomic(&crtc
->base
);
15620 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
15622 * We start out with underrun reporting disabled to avoid races.
15623 * For correct bookkeeping mark this on active crtcs.
15625 * Also on gmch platforms we dont have any hardware bits to
15626 * disable the underrun reporting. Which means we need to start
15627 * out with underrun reporting disabled also on inactive pipes,
15628 * since otherwise we'll complain about the garbage we read when
15629 * e.g. coming up after runtime pm.
15631 * No protection against concurrent access is required - at
15632 * worst a fifo underrun happens which also sets this to false.
15634 crtc
->cpu_fifo_underrun_disabled
= true;
15635 crtc
->pch_fifo_underrun_disabled
= true;
15639 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
15641 struct intel_connector
*connector
;
15642 struct drm_device
*dev
= encoder
->base
.dev
;
15644 /* We need to check both for a crtc link (meaning that the
15645 * encoder is active and trying to read from a pipe) and the
15646 * pipe itself being active. */
15647 bool has_active_crtc
= encoder
->base
.crtc
&&
15648 to_intel_crtc(encoder
->base
.crtc
)->active
;
15650 if (intel_encoder_has_connectors(encoder
) && !has_active_crtc
) {
15651 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15652 encoder
->base
.base
.id
,
15653 encoder
->base
.name
);
15655 /* Connector is active, but has no active pipe. This is
15656 * fallout from our resume register restoring. Disable
15657 * the encoder manually again. */
15658 if (encoder
->base
.crtc
) {
15659 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15660 encoder
->base
.base
.id
,
15661 encoder
->base
.name
);
15662 encoder
->disable(encoder
);
15663 if (encoder
->post_disable
)
15664 encoder
->post_disable(encoder
);
15666 encoder
->base
.crtc
= NULL
;
15668 /* Inconsistent output/port/pipe state happens presumably due to
15669 * a bug in one of the get_hw_state functions. Or someplace else
15670 * in our code, like the register restore mess on resume. Clamp
15671 * things to off as a safer default. */
15672 for_each_intel_connector(dev
, connector
) {
15673 if (connector
->encoder
!= encoder
)
15675 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15676 connector
->base
.encoder
= NULL
;
15679 /* Enabled encoders without active connectors will be fixed in
15680 * the crtc fixup. */
15683 void i915_redisable_vga_power_on(struct drm_device
*dev
)
15685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15686 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev
);
15688 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
15689 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15690 i915_disable_vga(dev
);
15694 void i915_redisable_vga(struct drm_device
*dev
)
15696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15698 /* This function can be called both from intel_modeset_setup_hw_state or
15699 * at a very early point in our resume sequence, where the power well
15700 * structures are not yet restored. Since this function is at a very
15701 * paranoid "someone might have enabled VGA while we were not looking"
15702 * level, just check if the power well is enabled instead of trying to
15703 * follow the "don't touch the power well if we don't need it" policy
15704 * the rest of the driver uses. */
15705 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_VGA
))
15708 i915_redisable_vga_power_on(dev
);
15710 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
);
15713 static bool primary_get_hw_state(struct intel_plane
*plane
)
15715 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
15717 return I915_READ(DSPCNTR(plane
->plane
)) & DISPLAY_PLANE_ENABLE
;
15720 /* FIXME read out full plane state for all planes */
15721 static void readout_plane_state(struct intel_crtc
*crtc
)
15723 struct drm_plane
*primary
= crtc
->base
.primary
;
15724 struct intel_plane_state
*plane_state
=
15725 to_intel_plane_state(primary
->state
);
15727 plane_state
->visible
= crtc
->active
&&
15728 primary_get_hw_state(to_intel_plane(primary
));
15730 if (plane_state
->visible
)
15731 crtc
->base
.state
->plane_mask
|= 1 << drm_plane_index(primary
);
15734 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
15736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15738 struct intel_crtc
*crtc
;
15739 struct intel_encoder
*encoder
;
15740 struct intel_connector
*connector
;
15743 dev_priv
->active_crtcs
= 0;
15745 for_each_intel_crtc(dev
, crtc
) {
15746 struct intel_crtc_state
*crtc_state
= crtc
->config
;
15749 __drm_atomic_helper_crtc_destroy_state(&crtc
->base
, &crtc_state
->base
);
15750 memset(crtc_state
, 0, sizeof(*crtc_state
));
15751 crtc_state
->base
.crtc
= &crtc
->base
;
15753 crtc_state
->base
.active
= crtc_state
->base
.enable
=
15754 dev_priv
->display
.get_pipe_config(crtc
, crtc_state
);
15756 crtc
->base
.enabled
= crtc_state
->base
.enable
;
15757 crtc
->active
= crtc_state
->base
.active
;
15759 if (crtc_state
->base
.active
) {
15760 dev_priv
->active_crtcs
|= 1 << crtc
->pipe
;
15762 if (IS_BROADWELL(dev_priv
)) {
15763 pixclk
= ilk_pipe_pixel_rate(crtc_state
);
15765 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15766 if (crtc_state
->ips_enabled
)
15767 pixclk
= DIV_ROUND_UP(pixclk
* 100, 95);
15768 } else if (IS_VALLEYVIEW(dev_priv
) ||
15769 IS_CHERRYVIEW(dev_priv
) ||
15770 IS_BROXTON(dev_priv
))
15771 pixclk
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
15773 WARN_ON(dev_priv
->display
.modeset_calc_cdclk
);
15776 dev_priv
->min_pixclk
[crtc
->pipe
] = pixclk
;
15778 readout_plane_state(crtc
);
15780 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15781 crtc
->base
.base
.id
,
15782 crtc
->active
? "enabled" : "disabled");
15785 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15786 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15788 pll
->on
= pll
->funcs
.get_hw_state(dev_priv
, pll
,
15789 &pll
->config
.hw_state
);
15790 pll
->config
.crtc_mask
= 0;
15791 for_each_intel_crtc(dev
, crtc
) {
15792 if (crtc
->active
&& crtc
->config
->shared_dpll
== pll
)
15793 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
15795 pll
->active_mask
= pll
->config
.crtc_mask
;
15797 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15798 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
15801 for_each_intel_encoder(dev
, encoder
) {
15804 if (encoder
->get_hw_state(encoder
, &pipe
)) {
15805 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15806 encoder
->base
.crtc
= &crtc
->base
;
15807 encoder
->get_config(encoder
, crtc
->config
);
15809 encoder
->base
.crtc
= NULL
;
15812 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15813 encoder
->base
.base
.id
,
15814 encoder
->base
.name
,
15815 encoder
->base
.crtc
? "enabled" : "disabled",
15819 for_each_intel_connector(dev
, connector
) {
15820 if (connector
->get_hw_state(connector
)) {
15821 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
15823 encoder
= connector
->encoder
;
15824 connector
->base
.encoder
= &encoder
->base
;
15826 if (encoder
->base
.crtc
&&
15827 encoder
->base
.crtc
->state
->active
) {
15829 * This has to be done during hardware readout
15830 * because anything calling .crtc_disable may
15831 * rely on the connector_mask being accurate.
15833 encoder
->base
.crtc
->state
->connector_mask
|=
15834 1 << drm_connector_index(&connector
->base
);
15835 encoder
->base
.crtc
->state
->encoder_mask
|=
15836 1 << drm_encoder_index(&encoder
->base
);
15840 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15841 connector
->base
.encoder
= NULL
;
15843 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15844 connector
->base
.base
.id
,
15845 connector
->base
.name
,
15846 connector
->base
.encoder
? "enabled" : "disabled");
15849 for_each_intel_crtc(dev
, crtc
) {
15850 crtc
->base
.hwmode
= crtc
->config
->base
.adjusted_mode
;
15852 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
15853 if (crtc
->base
.state
->active
) {
15854 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc
->config
);
15855 intel_mode_from_pipe_config(&crtc
->base
.state
->adjusted_mode
, crtc
->config
);
15856 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
15859 * The initial mode needs to be set in order to keep
15860 * the atomic core happy. It wants a valid mode if the
15861 * crtc's enabled, so we do the above call.
15863 * At this point some state updated by the connectors
15864 * in their ->detect() callback has not run yet, so
15865 * no recalculation can be done yet.
15867 * Even if we could do a recalculation and modeset
15868 * right now it would cause a double modeset if
15869 * fbdev or userspace chooses a different initial mode.
15871 * If that happens, someone indicated they wanted a
15872 * mode change, which means it's safe to do a full
15875 crtc
->base
.state
->mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
15877 drm_calc_timestamping_constants(&crtc
->base
, &crtc
->base
.hwmode
);
15878 update_scanline_offset(crtc
);
15881 intel_pipe_config_sanity_check(dev_priv
, crtc
->config
);
15885 /* Scan out the current hw modeset state,
15886 * and sanitizes it to the current state
15889 intel_modeset_setup_hw_state(struct drm_device
*dev
)
15891 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15893 struct intel_crtc
*crtc
;
15894 struct intel_encoder
*encoder
;
15897 intel_modeset_readout_hw_state(dev
);
15899 /* HW state is read out, now we need to sanitize this mess. */
15900 for_each_intel_encoder(dev
, encoder
) {
15901 intel_sanitize_encoder(encoder
);
15904 for_each_pipe(dev_priv
, pipe
) {
15905 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15906 intel_sanitize_crtc(crtc
);
15907 intel_dump_pipe_config(crtc
, crtc
->config
,
15908 "[setup_hw_state]");
15911 intel_modeset_update_connector_atomic_state(dev
);
15913 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15914 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15916 if (!pll
->on
|| pll
->active_mask
)
15919 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
15921 pll
->funcs
.disable(dev_priv
, pll
);
15925 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
15926 vlv_wm_get_hw_state(dev
);
15927 else if (IS_GEN9(dev
))
15928 skl_wm_get_hw_state(dev
);
15929 else if (HAS_PCH_SPLIT(dev
))
15930 ilk_wm_get_hw_state(dev
);
15932 for_each_intel_crtc(dev
, crtc
) {
15933 unsigned long put_domains
;
15935 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
, crtc
->config
);
15936 if (WARN_ON(put_domains
))
15937 modeset_put_power_domains(dev_priv
, put_domains
);
15939 intel_display_set_init_power(dev_priv
, false);
15941 intel_fbc_init_pipe_state(dev_priv
);
15944 void intel_display_resume(struct drm_device
*dev
)
15946 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15947 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
15948 struct drm_modeset_acquire_ctx ctx
;
15950 bool setup
= false;
15952 dev_priv
->modeset_restore_state
= NULL
;
15955 * This is a cludge because with real atomic modeset mode_config.mutex
15956 * won't be taken. Unfortunately some probed state like
15957 * audio_codec_enable is still protected by mode_config.mutex, so lock
15960 mutex_lock(&dev
->mode_config
.mutex
);
15961 drm_modeset_acquire_init(&ctx
, 0);
15964 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
15966 if (ret
== 0 && !setup
) {
15969 intel_modeset_setup_hw_state(dev
);
15970 i915_redisable_vga(dev
);
15973 if (ret
== 0 && state
) {
15974 struct drm_crtc_state
*crtc_state
;
15975 struct drm_crtc
*crtc
;
15978 state
->acquire_ctx
= &ctx
;
15980 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
15982 * Force recalculation even if we restore
15983 * current state. With fast modeset this may not result
15984 * in a modeset when the state is compatible.
15986 crtc_state
->mode_changed
= true;
15989 ret
= drm_atomic_commit(state
);
15992 if (ret
== -EDEADLK
) {
15993 drm_modeset_backoff(&ctx
);
15997 drm_modeset_drop_locks(&ctx
);
15998 drm_modeset_acquire_fini(&ctx
);
15999 mutex_unlock(&dev
->mode_config
.mutex
);
16002 DRM_ERROR("Restoring old state failed with %i\n", ret
);
16003 drm_atomic_state_free(state
);
16007 void intel_modeset_gem_init(struct drm_device
*dev
)
16009 struct drm_crtc
*c
;
16010 struct drm_i915_gem_object
*obj
;
16013 intel_init_gt_powersave(dev
);
16015 intel_modeset_init_hw(dev
);
16017 intel_setup_overlay(dev
);
16020 * Make sure any fbs we allocated at startup are properly
16021 * pinned & fenced. When we do the allocation it's too early
16024 for_each_crtc(dev
, c
) {
16025 obj
= intel_fb_obj(c
->primary
->fb
);
16029 mutex_lock(&dev
->struct_mutex
);
16030 ret
= intel_pin_and_fence_fb_obj(c
->primary
->fb
,
16031 c
->primary
->state
->rotation
);
16032 mutex_unlock(&dev
->struct_mutex
);
16034 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16035 to_intel_crtc(c
)->pipe
);
16036 drm_framebuffer_unreference(c
->primary
->fb
);
16037 c
->primary
->fb
= NULL
;
16038 c
->primary
->crtc
= c
->primary
->state
->crtc
= NULL
;
16039 update_state_fb(c
->primary
);
16040 c
->state
->plane_mask
&= ~(1 << drm_plane_index(c
->primary
));
16044 intel_backlight_register(dev
);
16047 void intel_connector_unregister(struct intel_connector
*intel_connector
)
16049 struct drm_connector
*connector
= &intel_connector
->base
;
16051 intel_panel_destroy_backlight(connector
);
16052 drm_connector_unregister(connector
);
16055 void intel_modeset_cleanup(struct drm_device
*dev
)
16057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
16058 struct intel_connector
*connector
;
16060 intel_disable_gt_powersave(dev
);
16062 intel_backlight_unregister(dev
);
16065 * Interrupts and polling as the first thing to avoid creating havoc.
16066 * Too much stuff here (turning of connectors, ...) would
16067 * experience fancy races otherwise.
16069 intel_irq_uninstall(dev_priv
);
16072 * Due to the hpd irq storm handling the hotplug work can re-arm the
16073 * poll handlers. Hence disable polling after hpd handling is shut down.
16075 drm_kms_helper_poll_fini(dev
);
16077 intel_unregister_dsm_handler();
16079 intel_fbc_global_disable(dev_priv
);
16081 /* flush any delayed tasks or pending work */
16082 flush_scheduled_work();
16084 /* destroy the backlight and sysfs files before encoders/connectors */
16085 for_each_intel_connector(dev
, connector
)
16086 connector
->unregister(connector
);
16088 drm_mode_config_cleanup(dev
);
16090 intel_cleanup_overlay(dev
);
16092 intel_cleanup_gt_powersave(dev
);
16094 intel_teardown_gmbus(dev
);
16098 * Return which encoder is currently attached for connector.
16100 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
16102 return &intel_attached_encoder(connector
)->base
;
16105 void intel_connector_attach_encoder(struct intel_connector
*connector
,
16106 struct intel_encoder
*encoder
)
16108 connector
->encoder
= encoder
;
16109 drm_mode_connector_attach_encoder(&connector
->base
,
16114 * set vga decode state - true == enable VGA decode
16116 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
16118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
16119 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
16122 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
16123 DRM_ERROR("failed to read control word\n");
16127 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
16131 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
16133 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
16135 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
16136 DRM_ERROR("failed to write control word\n");
16143 struct intel_display_error_state
{
16145 u32 power_well_driver
;
16147 int num_transcoders
;
16149 struct intel_cursor_error_state
{
16154 } cursor
[I915_MAX_PIPES
];
16156 struct intel_pipe_error_state
{
16157 bool power_domain_on
;
16160 } pipe
[I915_MAX_PIPES
];
16162 struct intel_plane_error_state
{
16170 } plane
[I915_MAX_PIPES
];
16172 struct intel_transcoder_error_state
{
16173 bool power_domain_on
;
16174 enum transcoder cpu_transcoder
;
16187 struct intel_display_error_state
*
16188 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
)
16190 struct intel_display_error_state
*error
;
16191 int transcoders
[] = {
16199 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
16202 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
16206 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
16207 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
16209 for_each_pipe(dev_priv
, i
) {
16210 error
->pipe
[i
].power_domain_on
=
16211 __intel_display_power_is_enabled(dev_priv
,
16212 POWER_DOMAIN_PIPE(i
));
16213 if (!error
->pipe
[i
].power_domain_on
)
16216 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
16217 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
16218 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
16220 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
16221 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
16222 if (INTEL_GEN(dev_priv
) <= 3) {
16223 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
16224 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
16226 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
16227 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
16228 if (INTEL_GEN(dev_priv
) >= 4) {
16229 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
16230 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
16233 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
16235 if (HAS_GMCH_DISPLAY(dev_priv
))
16236 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
16239 /* Note: this does not include DSI transcoders. */
16240 error
->num_transcoders
= INTEL_INFO(dev_priv
)->num_pipes
;
16241 if (HAS_DDI(dev_priv
))
16242 error
->num_transcoders
++; /* Account for eDP. */
16244 for (i
= 0; i
< error
->num_transcoders
; i
++) {
16245 enum transcoder cpu_transcoder
= transcoders
[i
];
16247 error
->transcoder
[i
].power_domain_on
=
16248 __intel_display_power_is_enabled(dev_priv
,
16249 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
16250 if (!error
->transcoder
[i
].power_domain_on
)
16253 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
16255 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
16256 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
16257 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
16258 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
16259 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
16260 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
16261 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
16267 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16270 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
16271 struct drm_device
*dev
,
16272 struct intel_display_error_state
*error
)
16274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
16280 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
16281 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
16282 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
16283 error
->power_well_driver
);
16284 for_each_pipe(dev_priv
, i
) {
16285 err_printf(m
, "Pipe [%d]:\n", i
);
16286 err_printf(m
, " Power: %s\n",
16287 onoff(error
->pipe
[i
].power_domain_on
));
16288 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
16289 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
16291 err_printf(m
, "Plane [%d]:\n", i
);
16292 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
16293 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
16294 if (INTEL_INFO(dev
)->gen
<= 3) {
16295 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
16296 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
16298 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
16299 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
16300 if (INTEL_INFO(dev
)->gen
>= 4) {
16301 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
16302 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
16305 err_printf(m
, "Cursor [%d]:\n", i
);
16306 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
16307 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
16308 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
16311 for (i
= 0; i
< error
->num_transcoders
; i
++) {
16312 err_printf(m
, "CPU transcoder: %s\n",
16313 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
16314 err_printf(m
, " Power: %s\n",
16315 onoff(error
->transcoder
[i
].power_domain_on
));
16316 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
16317 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
16318 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
16319 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
16320 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
16321 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
16322 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);