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drm/i915: Only call commit_planes when there are things to commit.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
79 };
80
81 /* Cursor formats */
82 static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84 };
85
86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119
120 typedef struct {
121 int min, max;
122 } intel_range_t;
123
124 typedef struct {
125 int dot_limit;
126 int p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
133 };
134
135 /* returns HPLL frequency in kHz */
136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137 {
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147 }
148
149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151 {
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169 }
170
171 int
172 intel_pch_rawclk(struct drm_device *dev)
173 {
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179 }
180
181 /* hrawclock is 1/4 the FSB frequency */
182 int intel_hrawclk(struct drm_device *dev)
183 {
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212 }
213
214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
215 {
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223 }
224
225 static inline u32 /* units of 100MHz */
226 intel_fdi_link_freq(struct drm_device *dev)
227 {
228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
233 }
234
235 static const intel_limit_t intel_limits_i8xx_dac = {
236 .dot = { .min = 25000, .max = 350000 },
237 .vco = { .min = 908000, .max = 1512000 },
238 .n = { .min = 2, .max = 16 },
239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
246 };
247
248 static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
250 .vco = { .min = 908000, .max = 1512000 },
251 .n = { .min = 2, .max = 16 },
252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259 };
260
261 static const intel_limit_t intel_limits_i8xx_lvds = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 908000, .max = 1512000 },
264 .n = { .min = 2, .max = 16 },
265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
272 };
273
274 static const intel_limit_t intel_limits_i9xx_sdvo = {
275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
285 };
286
287 static const intel_limit_t intel_limits_i9xx_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
298 };
299
300
301 static const intel_limit_t intel_limits_g4x_sdvo = {
302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
313 },
314 };
315
316 static const intel_limit_t intel_limits_g4x_hdmi = {
317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
327 };
328
329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
340 },
341 };
342
343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
354 },
355 };
356
357 static const intel_limit_t intel_limits_pineview_sdvo = {
358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
360 /* Pineview's Ncounter is a ring counter */
361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
363 /* Pineview only has one combined m divider, which we treat as m2. */
364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
370 };
371
372 static const intel_limit_t intel_limits_pineview_lvds = {
373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
383 };
384
385 /* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
390 static const intel_limit_t intel_limits_ironlake_dac = {
391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
401 };
402
403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
414 };
415
416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
427 };
428
429 /* LVDS 100mhz refclk limits. */
430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
451 .p1 = { .min = 2, .max = 6 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 static const intel_limit_t intel_limits_vlv = {
457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
464 .vco = { .min = 4000000, .max = 6000000 },
465 .n = { .min = 1, .max = 7 },
466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
468 .p1 = { .min = 2, .max = 3 },
469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
470 };
471
472 static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
480 .vco = { .min = 4800000, .max = 6480000 },
481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486 };
487
488 static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
491 .vco = { .min = 4800000, .max = 6700000 },
492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498 };
499
500 static bool
501 needs_modeset(struct drm_crtc_state *state)
502 {
503 return drm_atomic_crtc_needs_modeset(state);
504 }
505
506 /**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
510 {
511 struct drm_device *dev = crtc->base.dev;
512 struct intel_encoder *encoder;
513
514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
515 if (encoder->type == type)
516 return true;
517
518 return false;
519 }
520
521 /**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
529 {
530 struct drm_atomic_state *state = crtc_state->base.state;
531 struct drm_connector *connector;
532 struct drm_connector_state *connector_state;
533 struct intel_encoder *encoder;
534 int i, num_connectors = 0;
535
536 for_each_connector_in_state(state, connector, connector_state, i) {
537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
541
542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
544 return true;
545 }
546
547 WARN_ON(num_connectors == 0);
548
549 return false;
550 }
551
552 static const intel_limit_t *
553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
554 {
555 struct drm_device *dev = crtc_state->base.crtc->dev;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
559 if (intel_is_dual_link_lvds(dev)) {
560 if (refclk == 100000)
561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
565 if (refclk == 100000)
566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
570 } else
571 limit = &intel_limits_ironlake_dac;
572
573 return limit;
574 }
575
576 static const intel_limit_t *
577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
578 {
579 struct drm_device *dev = crtc_state->base.crtc->dev;
580 const intel_limit_t *limit;
581
582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
583 if (intel_is_dual_link_lvds(dev))
584 limit = &intel_limits_g4x_dual_channel_lvds;
585 else
586 limit = &intel_limits_g4x_single_channel_lvds;
587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
589 limit = &intel_limits_g4x_hdmi;
590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
591 limit = &intel_limits_g4x_sdvo;
592 } else /* The option is for other outputs */
593 limit = &intel_limits_i9xx_sdvo;
594
595 return limit;
596 }
597
598 static const intel_limit_t *
599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
600 {
601 struct drm_device *dev = crtc_state->base.crtc->dev;
602 const intel_limit_t *limit;
603
604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
607 limit = intel_ironlake_limit(crtc_state, refclk);
608 else if (IS_G4X(dev)) {
609 limit = intel_g4x_limit(crtc_state);
610 } else if (IS_PINEVIEW(dev)) {
611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
612 limit = &intel_limits_pineview_lvds;
613 else
614 limit = &intel_limits_pineview_sdvo;
615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
617 } else if (IS_VALLEYVIEW(dev)) {
618 limit = &intel_limits_vlv;
619 } else if (!IS_GEN2(dev)) {
620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
624 } else {
625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
626 limit = &intel_limits_i8xx_lvds;
627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
628 limit = &intel_limits_i8xx_dvo;
629 else
630 limit = &intel_limits_i8xx_dac;
631 }
632 return limit;
633 }
634
635 /*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
645 {
646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
648 if (WARN_ON(clock->n == 0 || clock->p == 0))
649 return 0;
650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
652
653 return clock->dot;
654 }
655
656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657 {
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659 }
660
661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
662 {
663 clock->m = i9xx_dpll_compute_m(clock);
664 clock->p = clock->p1 * clock->p2;
665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
666 return 0;
667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
669
670 return clock->dot;
671 }
672
673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
674 {
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
678 return 0;
679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
681
682 return clock->dot / 5;
683 }
684
685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
686 {
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
690 return 0;
691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
694
695 return clock->dot / 5;
696 }
697
698 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
699 /**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
704 static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
707 {
708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
711 INTELPllInvalid("p1 out of range\n");
712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
713 INTELPllInvalid("m2 out of range\n");
714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
715 INTELPllInvalid("m1 out of range\n");
716
717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
729 INTELPllInvalid("vco out of range\n");
730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
734 INTELPllInvalid("dot out of range\n");
735
736 return true;
737 }
738
739 static int
740 i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
743 {
744 struct drm_device *dev = crtc_state->base.crtc->dev;
745
746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
747 /*
748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
751 */
752 if (intel_is_dual_link_lvds(dev))
753 return limit->p2.p2_fast;
754 else
755 return limit->p2.p2_slow;
756 } else {
757 if (target < limit->p2.dot_limit)
758 return limit->p2.p2_slow;
759 else
760 return limit->p2.p2_fast;
761 }
762 }
763
764 static bool
765 i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769 {
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
782 if (clock.m2 >= clock.m1)
783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
788 int this_err;
789
790 i9xx_calc_dpll_params(refclk, &clock);
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809 }
810
811 static bool
812 pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
816 {
817 struct drm_device *dev = crtc_state->base.crtc->dev;
818 intel_clock_t clock;
819 int err = target;
820
821 memset(best_clock, 0, sizeof(*best_clock));
822
823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
833 int this_err;
834
835 pnv_calc_dpll_params(refclk, &clock);
836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
838 continue;
839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854 }
855
856 static bool
857 g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
861 {
862 struct drm_device *dev = crtc_state->base.crtc->dev;
863 intel_clock_t clock;
864 int max_n;
865 bool found = false;
866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
868
869 memset(best_clock, 0, sizeof(*best_clock));
870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
873 max_n = limit->n.max;
874 /* based on hardware requirement, prefer smaller n to precision */
875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
876 /* based on hardware requirement, prefere larger m1,m2 */
877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
885 i9xx_calc_dpll_params(refclk, &clock);
886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
888 continue;
889
890 this_err = abs(clock.dot - target);
891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
901 return found;
902 }
903
904 /*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913 {
914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942 }
943
944 static bool
945 vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
949 {
950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
951 struct drm_device *dev = crtc->base.dev;
952 intel_clock_t clock;
953 unsigned int bestppm = 1000000;
954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
956 bool found = false;
957
958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
961
962 /* based on hardware requirement, prefer smaller n to precision */
963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
967 clock.p = clock.p1 * clock.p2;
968 /* based on hardware requirement, prefer bigger m1,m2 values */
969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
970 unsigned int ppm;
971
972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
975 vlv_calc_dpll_params(refclk, &clock);
976
977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
979 continue;
980
981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
986
987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
990 }
991 }
992 }
993 }
994
995 return found;
996 }
997
998 static bool
999 chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003 {
1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005 struct drm_device *dev = crtc->base.dev;
1006 unsigned int best_error_ppm;
1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
1012 best_error_ppm = 1000000;
1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026 unsigned int error_ppm;
1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
1038 chv_calc_dpll_params(refclk, &clock);
1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
1050 }
1051 }
1052
1053 return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058 {
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
1072 * We can ditch the adjusted_mode.crtc_clock check as soon
1073 * as Haswell has gained clock readout/fastboot support.
1074 *
1075 * We can ditch the crtc->primary->fb check as soon as we can
1076 * properly reconstruct framebuffers.
1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
1081 */
1082 return intel_crtc->active && crtc->primary->state->fb &&
1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088 {
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092 return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
1108 msleep(5);
1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112 }
1113
1114 /*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
1116 * @crtc: crtc whose pipe to wait for
1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
1128 *
1129 */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132 struct drm_device *dev = crtc->base.dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135 enum pipe pipe = crtc->pipe;
1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
1138 int reg = PIPECONF(cpu_transcoder);
1139
1140 /* Wait for the Pipe State to go off */
1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
1143 WARN(1, "pipe_off wait timed out\n");
1144 } else {
1145 /* Wait for the display line to settle */
1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147 WARN(1, "pipe_off wait timed out\n");
1148 }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153 return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
1159 {
1160 u32 val;
1161 bool cur_state;
1162
1163 val = I915_READ(DPLL(pipe));
1164 cur_state = !!(val & DPLL_VCO_ENABLE);
1165 I915_STATE_WARN(cur_state != state,
1166 "PLL state assertion failure (expected %s, current %s)\n",
1167 state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173 u32 val;
1174 bool cur_state;
1175
1176 mutex_lock(&dev_priv->sb_lock);
1177 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178 mutex_unlock(&dev_priv->sb_lock);
1179
1180 cur_state = val & DSI_PLL_VCO_EN;
1181 I915_STATE_WARN(cur_state != state,
1182 "DSI PLL state assertion failure (expected %s, current %s)\n",
1183 state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193 if (crtc->config->shared_dpll < 0)
1194 return NULL;
1195
1196 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201 struct intel_shared_dpll *pll,
1202 bool state)
1203 {
1204 bool cur_state;
1205 struct intel_dpll_hw_state hw_state;
1206
1207 if (WARN (!pll,
1208 "asserting DPLL %s with no DPLL\n", state_string(state)))
1209 return;
1210
1211 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212 I915_STATE_WARN(cur_state != state,
1213 "%s assertion failure (expected %s, current %s)\n",
1214 pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 bool cur_state;
1221 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222 pipe);
1223
1224 if (HAS_DDI(dev_priv->dev)) {
1225 /* DDI does not have a specific FDI_TX register */
1226 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228 } else {
1229 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230 cur_state = !!(val & FDI_TX_ENABLE);
1231 }
1232 I915_STATE_WARN(cur_state != state,
1233 "FDI TX state assertion failure (expected %s, current %s)\n",
1234 state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241 {
1242 u32 val;
1243 bool cur_state;
1244
1245 val = I915_READ(FDI_RX_CTL(pipe));
1246 cur_state = !!(val & FDI_RX_ENABLE);
1247 I915_STATE_WARN(cur_state != state,
1248 "FDI RX state assertion failure (expected %s, current %s)\n",
1249 state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256 {
1257 u32 val;
1258
1259 /* ILK FDI PLL is always enabled */
1260 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261 return;
1262
1263 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264 if (HAS_DDI(dev_priv->dev))
1265 return;
1266
1267 val = I915_READ(FDI_TX_CTL(pipe));
1268 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
1273 {
1274 u32 val;
1275 bool cur_state;
1276
1277 val = I915_READ(FDI_RX_CTL(pipe));
1278 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279 I915_STATE_WARN(cur_state != state,
1280 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281 state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285 enum pipe pipe)
1286 {
1287 struct drm_device *dev = dev_priv->dev;
1288 int pp_reg;
1289 u32 val;
1290 enum pipe panel_pipe = PIPE_A;
1291 bool locked = true;
1292
1293 if (WARN_ON(HAS_DDI(dev)))
1294 return;
1295
1296 if (HAS_PCH_SPLIT(dev)) {
1297 u32 port_sel;
1298
1299 pp_reg = PCH_PP_CONTROL;
1300 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304 panel_pipe = PIPE_B;
1305 /* XXX: else fix for eDP */
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 /* presumably write lock depends on pipe, not port select */
1308 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309 panel_pipe = pipe;
1310 } else {
1311 pp_reg = PP_CONTROL;
1312 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313 panel_pipe = PIPE_B;
1314 }
1315
1316 val = I915_READ(pp_reg);
1317 if (!(val & PANEL_POWER_ON) ||
1318 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319 locked = false;
1320
1321 I915_STATE_WARN(panel_pipe == pipe && locked,
1322 "panel assertion failure, pipe %c regs locked\n",
1323 pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328 {
1329 struct drm_device *dev = dev_priv->dev;
1330 bool cur_state;
1331
1332 if (IS_845G(dev) || IS_I865G(dev))
1333 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334 else
1335 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337 I915_STATE_WARN(cur_state != state,
1338 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, bool state)
1346 {
1347 bool cur_state;
1348 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349 pipe);
1350
1351 /* if we need the pipe quirk it must be always on */
1352 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354 state = true;
1355
1356 if (!intel_display_power_is_enabled(dev_priv,
1357 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358 cur_state = false;
1359 } else {
1360 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361 cur_state = !!(val & PIPECONF_ENABLE);
1362 }
1363
1364 I915_STATE_WARN(cur_state != state,
1365 "pipe %c assertion failure (expected %s, current %s)\n",
1366 pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370 enum plane plane, bool state)
1371 {
1372 u32 val;
1373 bool cur_state;
1374
1375 val = I915_READ(DSPCNTR(plane));
1376 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377 I915_STATE_WARN(cur_state != state,
1378 "plane %c assertion failure (expected %s, current %s)\n",
1379 plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387 {
1388 struct drm_device *dev = dev_priv->dev;
1389 int i;
1390
1391 /* Primary planes are fixed to pipes on gen4+ */
1392 if (INTEL_INFO(dev)->gen >= 4) {
1393 u32 val = I915_READ(DSPCNTR(pipe));
1394 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395 "plane %c assertion failure, should be disabled but not\n",
1396 plane_name(pipe));
1397 return;
1398 }
1399
1400 /* Need to check both planes against the pipe */
1401 for_each_pipe(dev_priv, i) {
1402 u32 val = I915_READ(DSPCNTR(i));
1403 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404 DISPPLANE_SEL_PIPE_SHIFT;
1405 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407 plane_name(i), pipe_name(pipe));
1408 }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413 {
1414 struct drm_device *dev = dev_priv->dev;
1415 int sprite;
1416
1417 if (INTEL_INFO(dev)->gen >= 9) {
1418 for_each_sprite(dev_priv, pipe, sprite) {
1419 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422 sprite, pipe_name(pipe));
1423 }
1424 } else if (IS_VALLEYVIEW(dev)) {
1425 for_each_sprite(dev_priv, pipe, sprite) {
1426 u32 val = I915_READ(SPCNTR(pipe, sprite));
1427 I915_STATE_WARN(val & SP_ENABLE,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 sprite_name(pipe, sprite), pipe_name(pipe));
1430 }
1431 } else if (INTEL_INFO(dev)->gen >= 7) {
1432 u32 val = I915_READ(SPRCTL(pipe));
1433 I915_STATE_WARN(val & SPRITE_ENABLE,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe), pipe_name(pipe));
1436 } else if (INTEL_INFO(dev)->gen >= 5) {
1437 u32 val = I915_READ(DVSCNTR(pipe));
1438 I915_STATE_WARN(val & DVS_ENABLE,
1439 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440 plane_name(pipe), pipe_name(pipe));
1441 }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452 u32 val;
1453 bool enabled;
1454
1455 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457 val = I915_READ(PCH_DREF_CONTROL);
1458 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459 DREF_SUPERSPREAD_SOURCE_MASK));
1460 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465 {
1466 u32 val;
1467 bool enabled;
1468
1469 val = I915_READ(PCH_TRANSCONF(pipe));
1470 enabled = !!(val & TRANS_ENABLE);
1471 I915_STATE_WARN(enabled,
1472 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473 pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479 if ((val & DP_PORT_EN) == 0)
1480 return false;
1481
1482 if (HAS_PCH_CPT(dev_priv->dev)) {
1483 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486 return false;
1487 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489 return false;
1490 } else {
1491 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492 return false;
1493 }
1494 return true;
1495 }
1496
1497 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, u32 val)
1499 {
1500 if ((val & SDVO_ENABLE) == 0)
1501 return false;
1502
1503 if (HAS_PCH_CPT(dev_priv->dev)) {
1504 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1505 return false;
1506 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508 return false;
1509 } else {
1510 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1511 return false;
1512 }
1513 return true;
1514 }
1515
1516 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517 enum pipe pipe, u32 val)
1518 {
1519 if ((val & LVDS_PORT_EN) == 0)
1520 return false;
1521
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527 return false;
1528 }
1529 return true;
1530 }
1531
1532 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, u32 val)
1534 {
1535 if ((val & ADPA_DAC_ENABLE) == 0)
1536 return false;
1537 if (HAS_PCH_CPT(dev_priv->dev)) {
1538 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539 return false;
1540 } else {
1541 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542 return false;
1543 }
1544 return true;
1545 }
1546
1547 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1548 enum pipe pipe, int reg, u32 port_sel)
1549 {
1550 u32 val = I915_READ(reg);
1551 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553 reg, pipe_name(pipe));
1554
1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556 && (val & DP_PIPEB_SELECT),
1557 "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561 enum pipe pipe, int reg)
1562 {
1563 u32 val = I915_READ(reg);
1564 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566 reg, pipe_name(pipe));
1567
1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569 && (val & SDVO_PIPE_B_SELECT),
1570 "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574 enum pipe pipe)
1575 {
1576 u32 val;
1577
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582 val = I915_READ(PCH_ADPA);
1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
1585 pipe_name(pipe));
1586
1587 val = I915_READ(PCH_LVDS);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590 pipe_name(pipe));
1591
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598 const struct intel_crtc_state *pipe_config)
1599 {
1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605 assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
1611 if (IS_MOBILE(dev_priv->dev))
1612 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622 POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624 /* We do this three times for luck */
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
1628 I915_WRITE(reg, dpll);
1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
1631 I915_WRITE(reg, dpll);
1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637 const struct intel_crtc_state *pipe_config)
1638 {
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649 mutex_lock(&dev_priv->sb_lock);
1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656 mutex_unlock(&dev_priv->sb_lock);
1657
1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666 /* Check PLL is locked */
1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670 /* not sure when this should be written */
1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672 POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
1681 count += crtc->base.state->active &&
1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684 return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694 assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696 /* No really, not for ILK+ */
1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699 /* PLL is protected by panel, make sure we can write it */
1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
1722 crtc->config->dpll_hw_state.dpll_md);
1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
1731
1732 /* We do this three times for luck */
1733 I915_WRITE(reg, dpll);
1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
1736 I915_WRITE(reg, dpll);
1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
1739 I915_WRITE(reg, dpll);
1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742 }
1743
1744 /**
1745 * i9xx_disable_pll - disable a PLL
1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1753 static void i9xx_disable_pll(struct intel_crtc *crtc)
1754 {
1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1762 !intel_num_dvo_pipes(dev)) {
1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
1777 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1778 POSTING_READ(DPLL(pipe));
1779 }
1780
1781 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782 {
1783 u32 val;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
1792 val = DPLL_VGA_MODE_DIS;
1793 if (pipe == PIPE_B)
1794 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1795 I915_WRITE(DPLL(pipe), val);
1796 POSTING_READ(DPLL(pipe));
1797
1798 }
1799
1800 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801 {
1802 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1803 u32 val;
1804
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1807
1808 /* Set PLL en = 0 */
1809 val = DPLL_SSC_REF_CLK_CHV |
1810 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1811 if (pipe != PIPE_A)
1812 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813 I915_WRITE(DPLL(pipe), val);
1814 POSTING_READ(DPLL(pipe));
1815
1816 mutex_lock(&dev_priv->sb_lock);
1817
1818 /* Disable 10bit clock to display controller */
1819 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820 val &= ~DPIO_DCLKP_EN;
1821 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1822
1823 mutex_unlock(&dev_priv->sb_lock);
1824 }
1825
1826 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1827 struct intel_digital_port *dport,
1828 unsigned int expected_mask)
1829 {
1830 u32 port_mask;
1831 int dpll_reg;
1832
1833 switch (dport->port) {
1834 case PORT_B:
1835 port_mask = DPLL_PORTB_READY_MASK;
1836 dpll_reg = DPLL(0);
1837 break;
1838 case PORT_C:
1839 port_mask = DPLL_PORTC_READY_MASK;
1840 dpll_reg = DPLL(0);
1841 expected_mask <<= 4;
1842 break;
1843 case PORT_D:
1844 port_mask = DPLL_PORTD_READY_MASK;
1845 dpll_reg = DPIO_PHY_STATUS;
1846 break;
1847 default:
1848 BUG();
1849 }
1850
1851 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1854 }
1855
1856 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1857 {
1858 struct drm_device *dev = crtc->base.dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1861
1862 if (WARN_ON(pll == NULL))
1863 return;
1864
1865 WARN_ON(!pll->config.crtc_mask);
1866 if (pll->active == 0) {
1867 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1868 WARN_ON(pll->on);
1869 assert_shared_dpll_disabled(dev_priv, pll);
1870
1871 pll->mode_set(dev_priv, pll);
1872 }
1873 }
1874
1875 /**
1876 * intel_enable_shared_dpll - enable PCH PLL
1877 * @dev_priv: i915 private structure
1878 * @pipe: pipe PLL to enable
1879 *
1880 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881 * drives the transcoder clock.
1882 */
1883 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1884 {
1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1888
1889 if (WARN_ON(pll == NULL))
1890 return;
1891
1892 if (WARN_ON(pll->config.crtc_mask == 0))
1893 return;
1894
1895 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1896 pll->name, pll->active, pll->on,
1897 crtc->base.base.id);
1898
1899 if (pll->active++) {
1900 WARN_ON(!pll->on);
1901 assert_shared_dpll_enabled(dev_priv, pll);
1902 return;
1903 }
1904 WARN_ON(pll->on);
1905
1906 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1907
1908 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1909 pll->enable(dev_priv, pll);
1910 pll->on = true;
1911 }
1912
1913 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1914 {
1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1918
1919 /* PCH only available on ILK+ */
1920 if (INTEL_INFO(dev)->gen < 5)
1921 return;
1922
1923 if (pll == NULL)
1924 return;
1925
1926 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1927 return;
1928
1929 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930 pll->name, pll->active, pll->on,
1931 crtc->base.base.id);
1932
1933 if (WARN_ON(pll->active == 0)) {
1934 assert_shared_dpll_disabled(dev_priv, pll);
1935 return;
1936 }
1937
1938 assert_shared_dpll_enabled(dev_priv, pll);
1939 WARN_ON(!pll->on);
1940 if (--pll->active)
1941 return;
1942
1943 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1944 pll->disable(dev_priv, pll);
1945 pll->on = false;
1946
1947 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1948 }
1949
1950 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1951 enum pipe pipe)
1952 {
1953 struct drm_device *dev = dev_priv->dev;
1954 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1956 uint32_t reg, val, pipeconf_val;
1957
1958 /* PCH only available on ILK+ */
1959 BUG_ON(!HAS_PCH_SPLIT(dev));
1960
1961 /* Make sure PCH DPLL is enabled */
1962 assert_shared_dpll_enabled(dev_priv,
1963 intel_crtc_to_shared_dpll(intel_crtc));
1964
1965 /* FDI must be feeding us bits for PCH ports */
1966 assert_fdi_tx_enabled(dev_priv, pipe);
1967 assert_fdi_rx_enabled(dev_priv, pipe);
1968
1969 if (HAS_PCH_CPT(dev)) {
1970 /* Workaround: Set the timing override bit before enabling the
1971 * pch transcoder. */
1972 reg = TRANS_CHICKEN2(pipe);
1973 val = I915_READ(reg);
1974 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1975 I915_WRITE(reg, val);
1976 }
1977
1978 reg = PCH_TRANSCONF(pipe);
1979 val = I915_READ(reg);
1980 pipeconf_val = I915_READ(PIPECONF(pipe));
1981
1982 if (HAS_PCH_IBX(dev_priv->dev)) {
1983 /*
1984 * Make the BPC in transcoder be consistent with
1985 * that in pipeconf reg. For HDMI we must use 8bpc
1986 * here for both 8bpc and 12bpc.
1987 */
1988 val &= ~PIPECONF_BPC_MASK;
1989 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1990 val |= PIPECONF_8BPC;
1991 else
1992 val |= pipeconf_val & PIPECONF_BPC_MASK;
1993 }
1994
1995 val &= ~TRANS_INTERLACE_MASK;
1996 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1997 if (HAS_PCH_IBX(dev_priv->dev) &&
1998 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1999 val |= TRANS_LEGACY_INTERLACED_ILK;
2000 else
2001 val |= TRANS_INTERLACED;
2002 else
2003 val |= TRANS_PROGRESSIVE;
2004
2005 I915_WRITE(reg, val | TRANS_ENABLE);
2006 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2007 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2008 }
2009
2010 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2011 enum transcoder cpu_transcoder)
2012 {
2013 u32 val, pipeconf_val;
2014
2015 /* PCH only available on ILK+ */
2016 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2017
2018 /* FDI must be feeding us bits for PCH ports */
2019 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2020 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2021
2022 /* Workaround: set timing override bit. */
2023 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2024 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2025 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2026
2027 val = TRANS_ENABLE;
2028 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2029
2030 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2031 PIPECONF_INTERLACED_ILK)
2032 val |= TRANS_INTERLACED;
2033 else
2034 val |= TRANS_PROGRESSIVE;
2035
2036 I915_WRITE(LPT_TRANSCONF, val);
2037 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2038 DRM_ERROR("Failed to enable PCH transcoder\n");
2039 }
2040
2041 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2042 enum pipe pipe)
2043 {
2044 struct drm_device *dev = dev_priv->dev;
2045 uint32_t reg, val;
2046
2047 /* FDI relies on the transcoder */
2048 assert_fdi_tx_disabled(dev_priv, pipe);
2049 assert_fdi_rx_disabled(dev_priv, pipe);
2050
2051 /* Ports must be off as well */
2052 assert_pch_ports_disabled(dev_priv, pipe);
2053
2054 reg = PCH_TRANSCONF(pipe);
2055 val = I915_READ(reg);
2056 val &= ~TRANS_ENABLE;
2057 I915_WRITE(reg, val);
2058 /* wait for PCH transcoder off, transcoder state */
2059 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2060 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2061
2062 if (!HAS_PCH_IBX(dev)) {
2063 /* Workaround: Clear the timing override chicken bit again. */
2064 reg = TRANS_CHICKEN2(pipe);
2065 val = I915_READ(reg);
2066 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2067 I915_WRITE(reg, val);
2068 }
2069 }
2070
2071 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2072 {
2073 u32 val;
2074
2075 val = I915_READ(LPT_TRANSCONF);
2076 val &= ~TRANS_ENABLE;
2077 I915_WRITE(LPT_TRANSCONF, val);
2078 /* wait for PCH transcoder off, transcoder state */
2079 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2080 DRM_ERROR("Failed to disable PCH transcoder\n");
2081
2082 /* Workaround: clear timing override bit. */
2083 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2086 }
2087
2088 /**
2089 * intel_enable_pipe - enable a pipe, asserting requirements
2090 * @crtc: crtc responsible for the pipe
2091 *
2092 * Enable @crtc's pipe, making sure that various hardware specific requirements
2093 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2094 */
2095 static void intel_enable_pipe(struct intel_crtc *crtc)
2096 {
2097 struct drm_device *dev = crtc->base.dev;
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099 enum pipe pipe = crtc->pipe;
2100 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2101 pipe);
2102 enum pipe pch_transcoder;
2103 int reg;
2104 u32 val;
2105
2106 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2107
2108 assert_planes_disabled(dev_priv, pipe);
2109 assert_cursor_disabled(dev_priv, pipe);
2110 assert_sprites_disabled(dev_priv, pipe);
2111
2112 if (HAS_PCH_LPT(dev_priv->dev))
2113 pch_transcoder = TRANSCODER_A;
2114 else
2115 pch_transcoder = pipe;
2116
2117 /*
2118 * A pipe without a PLL won't actually be able to drive bits from
2119 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2120 * need the check.
2121 */
2122 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2123 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2124 assert_dsi_pll_enabled(dev_priv);
2125 else
2126 assert_pll_enabled(dev_priv, pipe);
2127 else {
2128 if (crtc->config->has_pch_encoder) {
2129 /* if driving the PCH, we need FDI enabled */
2130 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2131 assert_fdi_tx_pll_enabled(dev_priv,
2132 (enum pipe) cpu_transcoder);
2133 }
2134 /* FIXME: assert CPU port conditions for SNB+ */
2135 }
2136
2137 reg = PIPECONF(cpu_transcoder);
2138 val = I915_READ(reg);
2139 if (val & PIPECONF_ENABLE) {
2140 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2141 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2142 return;
2143 }
2144
2145 I915_WRITE(reg, val | PIPECONF_ENABLE);
2146 POSTING_READ(reg);
2147 }
2148
2149 /**
2150 * intel_disable_pipe - disable a pipe, asserting requirements
2151 * @crtc: crtc whose pipes is to be disabled
2152 *
2153 * Disable the pipe of @crtc, making sure that various hardware
2154 * specific requirements are met, if applicable, e.g. plane
2155 * disabled, panel fitter off, etc.
2156 *
2157 * Will wait until the pipe has shut down before returning.
2158 */
2159 static void intel_disable_pipe(struct intel_crtc *crtc)
2160 {
2161 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2162 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2163 enum pipe pipe = crtc->pipe;
2164 int reg;
2165 u32 val;
2166
2167 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2168
2169 /*
2170 * Make sure planes won't keep trying to pump pixels to us,
2171 * or we might hang the display.
2172 */
2173 assert_planes_disabled(dev_priv, pipe);
2174 assert_cursor_disabled(dev_priv, pipe);
2175 assert_sprites_disabled(dev_priv, pipe);
2176
2177 reg = PIPECONF(cpu_transcoder);
2178 val = I915_READ(reg);
2179 if ((val & PIPECONF_ENABLE) == 0)
2180 return;
2181
2182 /*
2183 * Double wide has implications for planes
2184 * so best keep it disabled when not needed.
2185 */
2186 if (crtc->config->double_wide)
2187 val &= ~PIPECONF_DOUBLE_WIDE;
2188
2189 /* Don't disable pipe or pipe PLLs if needed */
2190 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2191 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2192 val &= ~PIPECONF_ENABLE;
2193
2194 I915_WRITE(reg, val);
2195 if ((val & PIPECONF_ENABLE) == 0)
2196 intel_wait_for_pipe_off(crtc);
2197 }
2198
2199 static bool need_vtd_wa(struct drm_device *dev)
2200 {
2201 #ifdef CONFIG_INTEL_IOMMU
2202 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2203 return true;
2204 #endif
2205 return false;
2206 }
2207
2208 unsigned int
2209 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2210 uint64_t fb_format_modifier, unsigned int plane)
2211 {
2212 unsigned int tile_height;
2213 uint32_t pixel_bytes;
2214
2215 switch (fb_format_modifier) {
2216 case DRM_FORMAT_MOD_NONE:
2217 tile_height = 1;
2218 break;
2219 case I915_FORMAT_MOD_X_TILED:
2220 tile_height = IS_GEN2(dev) ? 16 : 8;
2221 break;
2222 case I915_FORMAT_MOD_Y_TILED:
2223 tile_height = 32;
2224 break;
2225 case I915_FORMAT_MOD_Yf_TILED:
2226 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2227 switch (pixel_bytes) {
2228 default:
2229 case 1:
2230 tile_height = 64;
2231 break;
2232 case 2:
2233 case 4:
2234 tile_height = 32;
2235 break;
2236 case 8:
2237 tile_height = 16;
2238 break;
2239 case 16:
2240 WARN_ONCE(1,
2241 "128-bit pixels are not supported for display!");
2242 tile_height = 16;
2243 break;
2244 }
2245 break;
2246 default:
2247 MISSING_CASE(fb_format_modifier);
2248 tile_height = 1;
2249 break;
2250 }
2251
2252 return tile_height;
2253 }
2254
2255 unsigned int
2256 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2257 uint32_t pixel_format, uint64_t fb_format_modifier)
2258 {
2259 return ALIGN(height, intel_tile_height(dev, pixel_format,
2260 fb_format_modifier, 0));
2261 }
2262
2263 static int
2264 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2265 const struct drm_plane_state *plane_state)
2266 {
2267 struct intel_rotation_info *info = &view->rotation_info;
2268 unsigned int tile_height, tile_pitch;
2269
2270 *view = i915_ggtt_view_normal;
2271
2272 if (!plane_state)
2273 return 0;
2274
2275 if (!intel_rotation_90_or_270(plane_state->rotation))
2276 return 0;
2277
2278 *view = i915_ggtt_view_rotated;
2279
2280 info->height = fb->height;
2281 info->pixel_format = fb->pixel_format;
2282 info->pitch = fb->pitches[0];
2283 info->uv_offset = fb->offsets[1];
2284 info->fb_modifier = fb->modifier[0];
2285
2286 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2287 fb->modifier[0], 0);
2288 tile_pitch = PAGE_SIZE / tile_height;
2289 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2290 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2291 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2292
2293 if (info->pixel_format == DRM_FORMAT_NV12) {
2294 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2295 fb->modifier[0], 1);
2296 tile_pitch = PAGE_SIZE / tile_height;
2297 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2298 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2299 tile_height);
2300 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2301 PAGE_SIZE;
2302 }
2303
2304 return 0;
2305 }
2306
2307 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2308 {
2309 if (INTEL_INFO(dev_priv)->gen >= 9)
2310 return 256 * 1024;
2311 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2312 IS_VALLEYVIEW(dev_priv))
2313 return 128 * 1024;
2314 else if (INTEL_INFO(dev_priv)->gen >= 4)
2315 return 4 * 1024;
2316 else
2317 return 0;
2318 }
2319
2320 int
2321 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2322 struct drm_framebuffer *fb,
2323 const struct drm_plane_state *plane_state,
2324 struct intel_engine_cs *pipelined,
2325 struct drm_i915_gem_request **pipelined_request)
2326 {
2327 struct drm_device *dev = fb->dev;
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2330 struct i915_ggtt_view view;
2331 u32 alignment;
2332 int ret;
2333
2334 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2335
2336 switch (fb->modifier[0]) {
2337 case DRM_FORMAT_MOD_NONE:
2338 alignment = intel_linear_alignment(dev_priv);
2339 break;
2340 case I915_FORMAT_MOD_X_TILED:
2341 if (INTEL_INFO(dev)->gen >= 9)
2342 alignment = 256 * 1024;
2343 else {
2344 /* pin() will align the object as required by fence */
2345 alignment = 0;
2346 }
2347 break;
2348 case I915_FORMAT_MOD_Y_TILED:
2349 case I915_FORMAT_MOD_Yf_TILED:
2350 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2351 "Y tiling bo slipped through, driver bug!\n"))
2352 return -EINVAL;
2353 alignment = 1 * 1024 * 1024;
2354 break;
2355 default:
2356 MISSING_CASE(fb->modifier[0]);
2357 return -EINVAL;
2358 }
2359
2360 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2361 if (ret)
2362 return ret;
2363
2364 /* Note that the w/a also requires 64 PTE of padding following the
2365 * bo. We currently fill all unused PTE with the shadow page and so
2366 * we should always have valid PTE following the scanout preventing
2367 * the VT-d warning.
2368 */
2369 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2370 alignment = 256 * 1024;
2371
2372 /*
2373 * Global gtt pte registers are special registers which actually forward
2374 * writes to a chunk of system memory. Which means that there is no risk
2375 * that the register values disappear as soon as we call
2376 * intel_runtime_pm_put(), so it is correct to wrap only the
2377 * pin/unpin/fence and not more.
2378 */
2379 intel_runtime_pm_get(dev_priv);
2380
2381 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2382 pipelined_request, &view);
2383 if (ret)
2384 goto err_pm;
2385
2386 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2387 * fence, whereas 965+ only requires a fence if using
2388 * framebuffer compression. For simplicity, we always install
2389 * a fence as the cost is not that onerous.
2390 */
2391 ret = i915_gem_object_get_fence(obj);
2392 if (ret == -EDEADLK) {
2393 /*
2394 * -EDEADLK means there are no free fences
2395 * no pending flips.
2396 *
2397 * This is propagated to atomic, but it uses
2398 * -EDEADLK to force a locking recovery, so
2399 * change the returned error to -EBUSY.
2400 */
2401 ret = -EBUSY;
2402 goto err_unpin;
2403 } else if (ret)
2404 goto err_unpin;
2405
2406 i915_gem_object_pin_fence(obj);
2407
2408 intel_runtime_pm_put(dev_priv);
2409 return 0;
2410
2411 err_unpin:
2412 i915_gem_object_unpin_from_display_plane(obj, &view);
2413 err_pm:
2414 intel_runtime_pm_put(dev_priv);
2415 return ret;
2416 }
2417
2418 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2419 const struct drm_plane_state *plane_state)
2420 {
2421 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2422 struct i915_ggtt_view view;
2423 int ret;
2424
2425 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2426
2427 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2428 WARN_ONCE(ret, "Couldn't get view from plane state!");
2429
2430 i915_gem_object_unpin_fence(obj);
2431 i915_gem_object_unpin_from_display_plane(obj, &view);
2432 }
2433
2434 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2435 * is assumed to be a power-of-two. */
2436 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2437 int *x, int *y,
2438 unsigned int tiling_mode,
2439 unsigned int cpp,
2440 unsigned int pitch)
2441 {
2442 if (tiling_mode != I915_TILING_NONE) {
2443 unsigned int tile_rows, tiles;
2444
2445 tile_rows = *y / 8;
2446 *y %= 8;
2447
2448 tiles = *x / (512/cpp);
2449 *x %= 512/cpp;
2450
2451 return tile_rows * pitch * 8 + tiles * 4096;
2452 } else {
2453 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2454 unsigned int offset;
2455
2456 offset = *y * pitch + *x * cpp;
2457 *y = (offset & alignment) / pitch;
2458 *x = ((offset & alignment) - *y * pitch) / cpp;
2459 return offset & ~alignment;
2460 }
2461 }
2462
2463 static int i9xx_format_to_fourcc(int format)
2464 {
2465 switch (format) {
2466 case DISPPLANE_8BPP:
2467 return DRM_FORMAT_C8;
2468 case DISPPLANE_BGRX555:
2469 return DRM_FORMAT_XRGB1555;
2470 case DISPPLANE_BGRX565:
2471 return DRM_FORMAT_RGB565;
2472 default:
2473 case DISPPLANE_BGRX888:
2474 return DRM_FORMAT_XRGB8888;
2475 case DISPPLANE_RGBX888:
2476 return DRM_FORMAT_XBGR8888;
2477 case DISPPLANE_BGRX101010:
2478 return DRM_FORMAT_XRGB2101010;
2479 case DISPPLANE_RGBX101010:
2480 return DRM_FORMAT_XBGR2101010;
2481 }
2482 }
2483
2484 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2485 {
2486 switch (format) {
2487 case PLANE_CTL_FORMAT_RGB_565:
2488 return DRM_FORMAT_RGB565;
2489 default:
2490 case PLANE_CTL_FORMAT_XRGB_8888:
2491 if (rgb_order) {
2492 if (alpha)
2493 return DRM_FORMAT_ABGR8888;
2494 else
2495 return DRM_FORMAT_XBGR8888;
2496 } else {
2497 if (alpha)
2498 return DRM_FORMAT_ARGB8888;
2499 else
2500 return DRM_FORMAT_XRGB8888;
2501 }
2502 case PLANE_CTL_FORMAT_XRGB_2101010:
2503 if (rgb_order)
2504 return DRM_FORMAT_XBGR2101010;
2505 else
2506 return DRM_FORMAT_XRGB2101010;
2507 }
2508 }
2509
2510 static bool
2511 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2512 struct intel_initial_plane_config *plane_config)
2513 {
2514 struct drm_device *dev = crtc->base.dev;
2515 struct drm_i915_private *dev_priv = to_i915(dev);
2516 struct drm_i915_gem_object *obj = NULL;
2517 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2518 struct drm_framebuffer *fb = &plane_config->fb->base;
2519 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2520 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2521 PAGE_SIZE);
2522
2523 size_aligned -= base_aligned;
2524
2525 if (plane_config->size == 0)
2526 return false;
2527
2528 /* If the FB is too big, just don't use it since fbdev is not very
2529 * important and we should probably use that space with FBC or other
2530 * features. */
2531 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2532 return false;
2533
2534 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2535 base_aligned,
2536 base_aligned,
2537 size_aligned);
2538 if (!obj)
2539 return false;
2540
2541 obj->tiling_mode = plane_config->tiling;
2542 if (obj->tiling_mode == I915_TILING_X)
2543 obj->stride = fb->pitches[0];
2544
2545 mode_cmd.pixel_format = fb->pixel_format;
2546 mode_cmd.width = fb->width;
2547 mode_cmd.height = fb->height;
2548 mode_cmd.pitches[0] = fb->pitches[0];
2549 mode_cmd.modifier[0] = fb->modifier[0];
2550 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2551
2552 mutex_lock(&dev->struct_mutex);
2553 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2554 &mode_cmd, obj)) {
2555 DRM_DEBUG_KMS("intel fb init failed\n");
2556 goto out_unref_obj;
2557 }
2558 mutex_unlock(&dev->struct_mutex);
2559
2560 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2561 return true;
2562
2563 out_unref_obj:
2564 drm_gem_object_unreference(&obj->base);
2565 mutex_unlock(&dev->struct_mutex);
2566 return false;
2567 }
2568
2569 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2570 static void
2571 update_state_fb(struct drm_plane *plane)
2572 {
2573 if (plane->fb == plane->state->fb)
2574 return;
2575
2576 if (plane->state->fb)
2577 drm_framebuffer_unreference(plane->state->fb);
2578 plane->state->fb = plane->fb;
2579 if (plane->state->fb)
2580 drm_framebuffer_reference(plane->state->fb);
2581 }
2582
2583 static void
2584 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2585 struct intel_initial_plane_config *plane_config)
2586 {
2587 struct drm_device *dev = intel_crtc->base.dev;
2588 struct drm_i915_private *dev_priv = dev->dev_private;
2589 struct drm_crtc *c;
2590 struct intel_crtc *i;
2591 struct drm_i915_gem_object *obj;
2592 struct drm_plane *primary = intel_crtc->base.primary;
2593 struct drm_plane_state *plane_state = primary->state;
2594 struct drm_framebuffer *fb;
2595
2596 if (!plane_config->fb)
2597 return;
2598
2599 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2600 fb = &plane_config->fb->base;
2601 goto valid_fb;
2602 }
2603
2604 kfree(plane_config->fb);
2605
2606 /*
2607 * Failed to alloc the obj, check to see if we should share
2608 * an fb with another CRTC instead
2609 */
2610 for_each_crtc(dev, c) {
2611 i = to_intel_crtc(c);
2612
2613 if (c == &intel_crtc->base)
2614 continue;
2615
2616 if (!i->active)
2617 continue;
2618
2619 fb = c->primary->fb;
2620 if (!fb)
2621 continue;
2622
2623 obj = intel_fb_obj(fb);
2624 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2625 drm_framebuffer_reference(fb);
2626 goto valid_fb;
2627 }
2628 }
2629
2630 return;
2631
2632 valid_fb:
2633 plane_state->src_x = plane_state->src_y = 0;
2634 plane_state->src_w = fb->width << 16;
2635 plane_state->src_h = fb->height << 16;
2636
2637 plane_state->crtc_x = plane_state->src_y = 0;
2638 plane_state->crtc_w = fb->width;
2639 plane_state->crtc_h = fb->height;
2640
2641 obj = intel_fb_obj(fb);
2642 if (obj->tiling_mode != I915_TILING_NONE)
2643 dev_priv->preserve_bios_swizzle = true;
2644
2645 drm_framebuffer_reference(fb);
2646 primary->fb = primary->state->fb = fb;
2647 primary->crtc = primary->state->crtc = &intel_crtc->base;
2648 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2649 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2650 }
2651
2652 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2653 struct drm_framebuffer *fb,
2654 int x, int y)
2655 {
2656 struct drm_device *dev = crtc->dev;
2657 struct drm_i915_private *dev_priv = dev->dev_private;
2658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2659 struct drm_plane *primary = crtc->primary;
2660 bool visible = to_intel_plane_state(primary->state)->visible;
2661 struct drm_i915_gem_object *obj;
2662 int plane = intel_crtc->plane;
2663 unsigned long linear_offset;
2664 u32 dspcntr;
2665 u32 reg = DSPCNTR(plane);
2666 int pixel_size;
2667
2668 if (!visible || !fb) {
2669 I915_WRITE(reg, 0);
2670 if (INTEL_INFO(dev)->gen >= 4)
2671 I915_WRITE(DSPSURF(plane), 0);
2672 else
2673 I915_WRITE(DSPADDR(plane), 0);
2674 POSTING_READ(reg);
2675 return;
2676 }
2677
2678 obj = intel_fb_obj(fb);
2679 if (WARN_ON(obj == NULL))
2680 return;
2681
2682 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2683
2684 dspcntr = DISPPLANE_GAMMA_ENABLE;
2685
2686 dspcntr |= DISPLAY_PLANE_ENABLE;
2687
2688 if (INTEL_INFO(dev)->gen < 4) {
2689 if (intel_crtc->pipe == PIPE_B)
2690 dspcntr |= DISPPLANE_SEL_PIPE_B;
2691
2692 /* pipesrc and dspsize control the size that is scaled from,
2693 * which should always be the user's requested size.
2694 */
2695 I915_WRITE(DSPSIZE(plane),
2696 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2697 (intel_crtc->config->pipe_src_w - 1));
2698 I915_WRITE(DSPPOS(plane), 0);
2699 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2700 I915_WRITE(PRIMSIZE(plane),
2701 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2702 (intel_crtc->config->pipe_src_w - 1));
2703 I915_WRITE(PRIMPOS(plane), 0);
2704 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2705 }
2706
2707 switch (fb->pixel_format) {
2708 case DRM_FORMAT_C8:
2709 dspcntr |= DISPPLANE_8BPP;
2710 break;
2711 case DRM_FORMAT_XRGB1555:
2712 dspcntr |= DISPPLANE_BGRX555;
2713 break;
2714 case DRM_FORMAT_RGB565:
2715 dspcntr |= DISPPLANE_BGRX565;
2716 break;
2717 case DRM_FORMAT_XRGB8888:
2718 dspcntr |= DISPPLANE_BGRX888;
2719 break;
2720 case DRM_FORMAT_XBGR8888:
2721 dspcntr |= DISPPLANE_RGBX888;
2722 break;
2723 case DRM_FORMAT_XRGB2101010:
2724 dspcntr |= DISPPLANE_BGRX101010;
2725 break;
2726 case DRM_FORMAT_XBGR2101010:
2727 dspcntr |= DISPPLANE_RGBX101010;
2728 break;
2729 default:
2730 BUG();
2731 }
2732
2733 if (INTEL_INFO(dev)->gen >= 4 &&
2734 obj->tiling_mode != I915_TILING_NONE)
2735 dspcntr |= DISPPLANE_TILED;
2736
2737 if (IS_G4X(dev))
2738 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2739
2740 linear_offset = y * fb->pitches[0] + x * pixel_size;
2741
2742 if (INTEL_INFO(dev)->gen >= 4) {
2743 intel_crtc->dspaddr_offset =
2744 intel_gen4_compute_page_offset(dev_priv,
2745 &x, &y, obj->tiling_mode,
2746 pixel_size,
2747 fb->pitches[0]);
2748 linear_offset -= intel_crtc->dspaddr_offset;
2749 } else {
2750 intel_crtc->dspaddr_offset = linear_offset;
2751 }
2752
2753 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2754 dspcntr |= DISPPLANE_ROTATE_180;
2755
2756 x += (intel_crtc->config->pipe_src_w - 1);
2757 y += (intel_crtc->config->pipe_src_h - 1);
2758
2759 /* Finding the last pixel of the last line of the display
2760 data and adding to linear_offset*/
2761 linear_offset +=
2762 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2763 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2764 }
2765
2766 intel_crtc->adjusted_x = x;
2767 intel_crtc->adjusted_y = y;
2768
2769 I915_WRITE(reg, dspcntr);
2770
2771 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2772 if (INTEL_INFO(dev)->gen >= 4) {
2773 I915_WRITE(DSPSURF(plane),
2774 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2775 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2776 I915_WRITE(DSPLINOFF(plane), linear_offset);
2777 } else
2778 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2779 POSTING_READ(reg);
2780 }
2781
2782 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2783 struct drm_framebuffer *fb,
2784 int x, int y)
2785 {
2786 struct drm_device *dev = crtc->dev;
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789 struct drm_plane *primary = crtc->primary;
2790 bool visible = to_intel_plane_state(primary->state)->visible;
2791 struct drm_i915_gem_object *obj;
2792 int plane = intel_crtc->plane;
2793 unsigned long linear_offset;
2794 u32 dspcntr;
2795 u32 reg = DSPCNTR(plane);
2796 int pixel_size;
2797
2798 if (!visible || !fb) {
2799 I915_WRITE(reg, 0);
2800 I915_WRITE(DSPSURF(plane), 0);
2801 POSTING_READ(reg);
2802 return;
2803 }
2804
2805 obj = intel_fb_obj(fb);
2806 if (WARN_ON(obj == NULL))
2807 return;
2808
2809 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2810
2811 dspcntr = DISPPLANE_GAMMA_ENABLE;
2812
2813 dspcntr |= DISPLAY_PLANE_ENABLE;
2814
2815 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2816 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2817
2818 switch (fb->pixel_format) {
2819 case DRM_FORMAT_C8:
2820 dspcntr |= DISPPLANE_8BPP;
2821 break;
2822 case DRM_FORMAT_RGB565:
2823 dspcntr |= DISPPLANE_BGRX565;
2824 break;
2825 case DRM_FORMAT_XRGB8888:
2826 dspcntr |= DISPPLANE_BGRX888;
2827 break;
2828 case DRM_FORMAT_XBGR8888:
2829 dspcntr |= DISPPLANE_RGBX888;
2830 break;
2831 case DRM_FORMAT_XRGB2101010:
2832 dspcntr |= DISPPLANE_BGRX101010;
2833 break;
2834 case DRM_FORMAT_XBGR2101010:
2835 dspcntr |= DISPPLANE_RGBX101010;
2836 break;
2837 default:
2838 BUG();
2839 }
2840
2841 if (obj->tiling_mode != I915_TILING_NONE)
2842 dspcntr |= DISPPLANE_TILED;
2843
2844 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2845 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2846
2847 linear_offset = y * fb->pitches[0] + x * pixel_size;
2848 intel_crtc->dspaddr_offset =
2849 intel_gen4_compute_page_offset(dev_priv,
2850 &x, &y, obj->tiling_mode,
2851 pixel_size,
2852 fb->pitches[0]);
2853 linear_offset -= intel_crtc->dspaddr_offset;
2854 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2855 dspcntr |= DISPPLANE_ROTATE_180;
2856
2857 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2858 x += (intel_crtc->config->pipe_src_w - 1);
2859 y += (intel_crtc->config->pipe_src_h - 1);
2860
2861 /* Finding the last pixel of the last line of the display
2862 data and adding to linear_offset*/
2863 linear_offset +=
2864 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2865 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2866 }
2867 }
2868
2869 intel_crtc->adjusted_x = x;
2870 intel_crtc->adjusted_y = y;
2871
2872 I915_WRITE(reg, dspcntr);
2873
2874 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2875 I915_WRITE(DSPSURF(plane),
2876 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2877 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2878 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2879 } else {
2880 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2881 I915_WRITE(DSPLINOFF(plane), linear_offset);
2882 }
2883 POSTING_READ(reg);
2884 }
2885
2886 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2887 uint32_t pixel_format)
2888 {
2889 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2890
2891 /*
2892 * The stride is either expressed as a multiple of 64 bytes
2893 * chunks for linear buffers or in number of tiles for tiled
2894 * buffers.
2895 */
2896 switch (fb_modifier) {
2897 case DRM_FORMAT_MOD_NONE:
2898 return 64;
2899 case I915_FORMAT_MOD_X_TILED:
2900 if (INTEL_INFO(dev)->gen == 2)
2901 return 128;
2902 return 512;
2903 case I915_FORMAT_MOD_Y_TILED:
2904 /* No need to check for old gens and Y tiling since this is
2905 * about the display engine and those will be blocked before
2906 * we get here.
2907 */
2908 return 128;
2909 case I915_FORMAT_MOD_Yf_TILED:
2910 if (bits_per_pixel == 8)
2911 return 64;
2912 else
2913 return 128;
2914 default:
2915 MISSING_CASE(fb_modifier);
2916 return 64;
2917 }
2918 }
2919
2920 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2921 struct drm_i915_gem_object *obj,
2922 unsigned int plane)
2923 {
2924 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2925 struct i915_vma *vma;
2926 unsigned char *offset;
2927
2928 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2929 view = &i915_ggtt_view_rotated;
2930
2931 vma = i915_gem_obj_to_ggtt_view(obj, view);
2932 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2933 view->type))
2934 return -1;
2935
2936 offset = (unsigned char *)vma->node.start;
2937
2938 if (plane == 1) {
2939 offset += vma->ggtt_view.rotation_info.uv_start_page *
2940 PAGE_SIZE;
2941 }
2942
2943 return (unsigned long)offset;
2944 }
2945
2946 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2947 {
2948 struct drm_device *dev = intel_crtc->base.dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950
2951 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2952 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2953 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2954 }
2955
2956 /*
2957 * This function detaches (aka. unbinds) unused scalers in hardware
2958 */
2959 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2960 {
2961 struct intel_crtc_scaler_state *scaler_state;
2962 int i;
2963
2964 scaler_state = &intel_crtc->config->scaler_state;
2965
2966 /* loop through and disable scalers that aren't in use */
2967 for (i = 0; i < intel_crtc->num_scalers; i++) {
2968 if (!scaler_state->scalers[i].in_use)
2969 skl_detach_scaler(intel_crtc, i);
2970 }
2971 }
2972
2973 u32 skl_plane_ctl_format(uint32_t pixel_format)
2974 {
2975 switch (pixel_format) {
2976 case DRM_FORMAT_C8:
2977 return PLANE_CTL_FORMAT_INDEXED;
2978 case DRM_FORMAT_RGB565:
2979 return PLANE_CTL_FORMAT_RGB_565;
2980 case DRM_FORMAT_XBGR8888:
2981 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2982 case DRM_FORMAT_XRGB8888:
2983 return PLANE_CTL_FORMAT_XRGB_8888;
2984 /*
2985 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2986 * to be already pre-multiplied. We need to add a knob (or a different
2987 * DRM_FORMAT) for user-space to configure that.
2988 */
2989 case DRM_FORMAT_ABGR8888:
2990 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2991 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2992 case DRM_FORMAT_ARGB8888:
2993 return PLANE_CTL_FORMAT_XRGB_8888 |
2994 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2995 case DRM_FORMAT_XRGB2101010:
2996 return PLANE_CTL_FORMAT_XRGB_2101010;
2997 case DRM_FORMAT_XBGR2101010:
2998 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2999 case DRM_FORMAT_YUYV:
3000 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3001 case DRM_FORMAT_YVYU:
3002 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3003 case DRM_FORMAT_UYVY:
3004 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3005 case DRM_FORMAT_VYUY:
3006 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3007 default:
3008 MISSING_CASE(pixel_format);
3009 }
3010
3011 return 0;
3012 }
3013
3014 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3015 {
3016 switch (fb_modifier) {
3017 case DRM_FORMAT_MOD_NONE:
3018 break;
3019 case I915_FORMAT_MOD_X_TILED:
3020 return PLANE_CTL_TILED_X;
3021 case I915_FORMAT_MOD_Y_TILED:
3022 return PLANE_CTL_TILED_Y;
3023 case I915_FORMAT_MOD_Yf_TILED:
3024 return PLANE_CTL_TILED_YF;
3025 default:
3026 MISSING_CASE(fb_modifier);
3027 }
3028
3029 return 0;
3030 }
3031
3032 u32 skl_plane_ctl_rotation(unsigned int rotation)
3033 {
3034 switch (rotation) {
3035 case BIT(DRM_ROTATE_0):
3036 break;
3037 /*
3038 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3039 * while i915 HW rotation is clockwise, thats why this swapping.
3040 */
3041 case BIT(DRM_ROTATE_90):
3042 return PLANE_CTL_ROTATE_270;
3043 case BIT(DRM_ROTATE_180):
3044 return PLANE_CTL_ROTATE_180;
3045 case BIT(DRM_ROTATE_270):
3046 return PLANE_CTL_ROTATE_90;
3047 default:
3048 MISSING_CASE(rotation);
3049 }
3050
3051 return 0;
3052 }
3053
3054 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3055 struct drm_framebuffer *fb,
3056 int x, int y)
3057 {
3058 struct drm_device *dev = crtc->dev;
3059 struct drm_i915_private *dev_priv = dev->dev_private;
3060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3061 struct drm_plane *plane = crtc->primary;
3062 bool visible = to_intel_plane_state(plane->state)->visible;
3063 struct drm_i915_gem_object *obj;
3064 int pipe = intel_crtc->pipe;
3065 u32 plane_ctl, stride_div, stride;
3066 u32 tile_height, plane_offset, plane_size;
3067 unsigned int rotation;
3068 int x_offset, y_offset;
3069 unsigned long surf_addr;
3070 struct intel_crtc_state *crtc_state = intel_crtc->config;
3071 struct intel_plane_state *plane_state;
3072 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3073 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3074 int scaler_id = -1;
3075
3076 plane_state = to_intel_plane_state(plane->state);
3077
3078 if (!visible || !fb) {
3079 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3080 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3081 POSTING_READ(PLANE_CTL(pipe, 0));
3082 return;
3083 }
3084
3085 plane_ctl = PLANE_CTL_ENABLE |
3086 PLANE_CTL_PIPE_GAMMA_ENABLE |
3087 PLANE_CTL_PIPE_CSC_ENABLE;
3088
3089 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3090 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3091 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3092
3093 rotation = plane->state->rotation;
3094 plane_ctl |= skl_plane_ctl_rotation(rotation);
3095
3096 obj = intel_fb_obj(fb);
3097 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3098 fb->pixel_format);
3099 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3100
3101 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3102
3103 scaler_id = plane_state->scaler_id;
3104 src_x = plane_state->src.x1 >> 16;
3105 src_y = plane_state->src.y1 >> 16;
3106 src_w = drm_rect_width(&plane_state->src) >> 16;
3107 src_h = drm_rect_height(&plane_state->src) >> 16;
3108 dst_x = plane_state->dst.x1;
3109 dst_y = plane_state->dst.y1;
3110 dst_w = drm_rect_width(&plane_state->dst);
3111 dst_h = drm_rect_height(&plane_state->dst);
3112
3113 WARN_ON(x != src_x || y != src_y);
3114
3115 if (intel_rotation_90_or_270(rotation)) {
3116 /* stride = Surface height in tiles */
3117 tile_height = intel_tile_height(dev, fb->pixel_format,
3118 fb->modifier[0], 0);
3119 stride = DIV_ROUND_UP(fb->height, tile_height);
3120 x_offset = stride * tile_height - y - src_h;
3121 y_offset = x;
3122 plane_size = (src_w - 1) << 16 | (src_h - 1);
3123 } else {
3124 stride = fb->pitches[0] / stride_div;
3125 x_offset = x;
3126 y_offset = y;
3127 plane_size = (src_h - 1) << 16 | (src_w - 1);
3128 }
3129 plane_offset = y_offset << 16 | x_offset;
3130
3131 intel_crtc->adjusted_x = x_offset;
3132 intel_crtc->adjusted_y = y_offset;
3133
3134 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3135 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3136 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3137 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3138
3139 if (scaler_id >= 0) {
3140 uint32_t ps_ctrl = 0;
3141
3142 WARN_ON(!dst_w || !dst_h);
3143 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3144 crtc_state->scaler_state.scalers[scaler_id].mode;
3145 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3146 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3147 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3148 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3149 I915_WRITE(PLANE_POS(pipe, 0), 0);
3150 } else {
3151 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3152 }
3153
3154 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3155
3156 POSTING_READ(PLANE_SURF(pipe, 0));
3157 }
3158
3159 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3160 static int
3161 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3162 int x, int y, enum mode_set_atomic state)
3163 {
3164 struct drm_device *dev = crtc->dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166
3167 if (dev_priv->fbc.disable_fbc)
3168 dev_priv->fbc.disable_fbc(dev_priv);
3169
3170 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3171
3172 return 0;
3173 }
3174
3175 static void intel_complete_page_flips(struct drm_device *dev)
3176 {
3177 struct drm_crtc *crtc;
3178
3179 for_each_crtc(dev, crtc) {
3180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3181 enum plane plane = intel_crtc->plane;
3182
3183 intel_prepare_page_flip(dev, plane);
3184 intel_finish_page_flip_plane(dev, plane);
3185 }
3186 }
3187
3188 static void intel_update_primary_planes(struct drm_device *dev)
3189 {
3190 struct drm_crtc *crtc;
3191
3192 for_each_crtc(dev, crtc) {
3193 struct intel_plane *plane = to_intel_plane(crtc->primary);
3194 struct intel_plane_state *plane_state;
3195
3196 drm_modeset_lock_crtc(crtc, &plane->base);
3197 plane_state = to_intel_plane_state(plane->base.state);
3198
3199 if (crtc->state->active && plane_state->base.fb)
3200 plane->commit_plane(&plane->base, plane_state);
3201
3202 drm_modeset_unlock_crtc(crtc);
3203 }
3204 }
3205
3206 void intel_prepare_reset(struct drm_device *dev)
3207 {
3208 /* no reset support for gen2 */
3209 if (IS_GEN2(dev))
3210 return;
3211
3212 /* reset doesn't touch the display */
3213 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3214 return;
3215
3216 drm_modeset_lock_all(dev);
3217 /*
3218 * Disabling the crtcs gracefully seems nicer. Also the
3219 * g33 docs say we should at least disable all the planes.
3220 */
3221 intel_display_suspend(dev);
3222 }
3223
3224 void intel_finish_reset(struct drm_device *dev)
3225 {
3226 struct drm_i915_private *dev_priv = to_i915(dev);
3227
3228 /*
3229 * Flips in the rings will be nuked by the reset,
3230 * so complete all pending flips so that user space
3231 * will get its events and not get stuck.
3232 */
3233 intel_complete_page_flips(dev);
3234
3235 /* no reset support for gen2 */
3236 if (IS_GEN2(dev))
3237 return;
3238
3239 /* reset doesn't touch the display */
3240 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3241 /*
3242 * Flips in the rings have been nuked by the reset,
3243 * so update the base address of all primary
3244 * planes to the the last fb to make sure we're
3245 * showing the correct fb after a reset.
3246 *
3247 * FIXME: Atomic will make this obsolete since we won't schedule
3248 * CS-based flips (which might get lost in gpu resets) any more.
3249 */
3250 intel_update_primary_planes(dev);
3251 return;
3252 }
3253
3254 /*
3255 * The display has been reset as well,
3256 * so need a full re-initialization.
3257 */
3258 intel_runtime_pm_disable_interrupts(dev_priv);
3259 intel_runtime_pm_enable_interrupts(dev_priv);
3260
3261 intel_modeset_init_hw(dev);
3262
3263 spin_lock_irq(&dev_priv->irq_lock);
3264 if (dev_priv->display.hpd_irq_setup)
3265 dev_priv->display.hpd_irq_setup(dev);
3266 spin_unlock_irq(&dev_priv->irq_lock);
3267
3268 intel_display_resume(dev);
3269
3270 intel_hpd_init(dev_priv);
3271
3272 drm_modeset_unlock_all(dev);
3273 }
3274
3275 static void
3276 intel_finish_fb(struct drm_framebuffer *old_fb)
3277 {
3278 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3279 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3280 bool was_interruptible = dev_priv->mm.interruptible;
3281 int ret;
3282
3283 /* Big Hammer, we also need to ensure that any pending
3284 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3285 * current scanout is retired before unpinning the old
3286 * framebuffer. Note that we rely on userspace rendering
3287 * into the buffer attached to the pipe they are waiting
3288 * on. If not, userspace generates a GPU hang with IPEHR
3289 * point to the MI_WAIT_FOR_EVENT.
3290 *
3291 * This should only fail upon a hung GPU, in which case we
3292 * can safely continue.
3293 */
3294 dev_priv->mm.interruptible = false;
3295 ret = i915_gem_object_wait_rendering(obj, true);
3296 dev_priv->mm.interruptible = was_interruptible;
3297
3298 WARN_ON(ret);
3299 }
3300
3301 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3302 {
3303 struct drm_device *dev = crtc->dev;
3304 struct drm_i915_private *dev_priv = dev->dev_private;
3305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306 bool pending;
3307
3308 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3309 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3310 return false;
3311
3312 spin_lock_irq(&dev->event_lock);
3313 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3314 spin_unlock_irq(&dev->event_lock);
3315
3316 return pending;
3317 }
3318
3319 static void intel_update_pipe_config(struct intel_crtc *crtc,
3320 struct intel_crtc_state *old_crtc_state)
3321 {
3322 struct drm_device *dev = crtc->base.dev;
3323 struct drm_i915_private *dev_priv = dev->dev_private;
3324 struct intel_crtc_state *pipe_config =
3325 to_intel_crtc_state(crtc->base.state);
3326
3327 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3328 crtc->base.mode = crtc->base.state->mode;
3329
3330 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3331 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3332 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3333
3334 if (HAS_DDI(dev))
3335 intel_set_pipe_csc(&crtc->base);
3336
3337 /*
3338 * Update pipe size and adjust fitter if needed: the reason for this is
3339 * that in compute_mode_changes we check the native mode (not the pfit
3340 * mode) to see if we can flip rather than do a full mode set. In the
3341 * fastboot case, we'll flip, but if we don't update the pipesrc and
3342 * pfit state, we'll end up with a big fb scanned out into the wrong
3343 * sized surface.
3344 */
3345
3346 I915_WRITE(PIPESRC(crtc->pipe),
3347 ((pipe_config->pipe_src_w - 1) << 16) |
3348 (pipe_config->pipe_src_h - 1));
3349
3350 /* on skylake this is done by detaching scalers */
3351 if (INTEL_INFO(dev)->gen >= 9) {
3352 skl_detach_scalers(crtc);
3353
3354 if (pipe_config->pch_pfit.enabled)
3355 skylake_pfit_enable(crtc);
3356 } else if (HAS_PCH_SPLIT(dev)) {
3357 if (pipe_config->pch_pfit.enabled)
3358 ironlake_pfit_enable(crtc);
3359 else if (old_crtc_state->pch_pfit.enabled)
3360 ironlake_pfit_disable(crtc, true);
3361 }
3362 }
3363
3364 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3365 {
3366 struct drm_device *dev = crtc->dev;
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3369 int pipe = intel_crtc->pipe;
3370 u32 reg, temp;
3371
3372 /* enable normal train */
3373 reg = FDI_TX_CTL(pipe);
3374 temp = I915_READ(reg);
3375 if (IS_IVYBRIDGE(dev)) {
3376 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3377 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3378 } else {
3379 temp &= ~FDI_LINK_TRAIN_NONE;
3380 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3381 }
3382 I915_WRITE(reg, temp);
3383
3384 reg = FDI_RX_CTL(pipe);
3385 temp = I915_READ(reg);
3386 if (HAS_PCH_CPT(dev)) {
3387 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3388 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3389 } else {
3390 temp &= ~FDI_LINK_TRAIN_NONE;
3391 temp |= FDI_LINK_TRAIN_NONE;
3392 }
3393 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3394
3395 /* wait one idle pattern time */
3396 POSTING_READ(reg);
3397 udelay(1000);
3398
3399 /* IVB wants error correction enabled */
3400 if (IS_IVYBRIDGE(dev))
3401 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3402 FDI_FE_ERRC_ENABLE);
3403 }
3404
3405 /* The FDI link training functions for ILK/Ibexpeak. */
3406 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3407 {
3408 struct drm_device *dev = crtc->dev;
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3411 int pipe = intel_crtc->pipe;
3412 u32 reg, temp, tries;
3413
3414 /* FDI needs bits from pipe first */
3415 assert_pipe_enabled(dev_priv, pipe);
3416
3417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3418 for train result */
3419 reg = FDI_RX_IMR(pipe);
3420 temp = I915_READ(reg);
3421 temp &= ~FDI_RX_SYMBOL_LOCK;
3422 temp &= ~FDI_RX_BIT_LOCK;
3423 I915_WRITE(reg, temp);
3424 I915_READ(reg);
3425 udelay(150);
3426
3427 /* enable CPU FDI TX and PCH FDI RX */
3428 reg = FDI_TX_CTL(pipe);
3429 temp = I915_READ(reg);
3430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3432 temp &= ~FDI_LINK_TRAIN_NONE;
3433 temp |= FDI_LINK_TRAIN_PATTERN_1;
3434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3435
3436 reg = FDI_RX_CTL(pipe);
3437 temp = I915_READ(reg);
3438 temp &= ~FDI_LINK_TRAIN_NONE;
3439 temp |= FDI_LINK_TRAIN_PATTERN_1;
3440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3441
3442 POSTING_READ(reg);
3443 udelay(150);
3444
3445 /* Ironlake workaround, enable clock pointer after FDI enable*/
3446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3448 FDI_RX_PHASE_SYNC_POINTER_EN);
3449
3450 reg = FDI_RX_IIR(pipe);
3451 for (tries = 0; tries < 5; tries++) {
3452 temp = I915_READ(reg);
3453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3454
3455 if ((temp & FDI_RX_BIT_LOCK)) {
3456 DRM_DEBUG_KMS("FDI train 1 done.\n");
3457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3458 break;
3459 }
3460 }
3461 if (tries == 5)
3462 DRM_ERROR("FDI train 1 fail!\n");
3463
3464 /* Train 2 */
3465 reg = FDI_TX_CTL(pipe);
3466 temp = I915_READ(reg);
3467 temp &= ~FDI_LINK_TRAIN_NONE;
3468 temp |= FDI_LINK_TRAIN_PATTERN_2;
3469 I915_WRITE(reg, temp);
3470
3471 reg = FDI_RX_CTL(pipe);
3472 temp = I915_READ(reg);
3473 temp &= ~FDI_LINK_TRAIN_NONE;
3474 temp |= FDI_LINK_TRAIN_PATTERN_2;
3475 I915_WRITE(reg, temp);
3476
3477 POSTING_READ(reg);
3478 udelay(150);
3479
3480 reg = FDI_RX_IIR(pipe);
3481 for (tries = 0; tries < 5; tries++) {
3482 temp = I915_READ(reg);
3483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3484
3485 if (temp & FDI_RX_SYMBOL_LOCK) {
3486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3487 DRM_DEBUG_KMS("FDI train 2 done.\n");
3488 break;
3489 }
3490 }
3491 if (tries == 5)
3492 DRM_ERROR("FDI train 2 fail!\n");
3493
3494 DRM_DEBUG_KMS("FDI train done\n");
3495
3496 }
3497
3498 static const int snb_b_fdi_train_param[] = {
3499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3503 };
3504
3505 /* The FDI link training functions for SNB/Cougarpoint. */
3506 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3507 {
3508 struct drm_device *dev = crtc->dev;
3509 struct drm_i915_private *dev_priv = dev->dev_private;
3510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511 int pipe = intel_crtc->pipe;
3512 u32 reg, temp, i, retry;
3513
3514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3515 for train result */
3516 reg = FDI_RX_IMR(pipe);
3517 temp = I915_READ(reg);
3518 temp &= ~FDI_RX_SYMBOL_LOCK;
3519 temp &= ~FDI_RX_BIT_LOCK;
3520 I915_WRITE(reg, temp);
3521
3522 POSTING_READ(reg);
3523 udelay(150);
3524
3525 /* enable CPU FDI TX and PCH FDI RX */
3526 reg = FDI_TX_CTL(pipe);
3527 temp = I915_READ(reg);
3528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3530 temp &= ~FDI_LINK_TRAIN_NONE;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1;
3532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3533 /* SNB-B */
3534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3536
3537 I915_WRITE(FDI_RX_MISC(pipe),
3538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3539
3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 if (HAS_PCH_CPT(dev)) {
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3545 } else {
3546 temp &= ~FDI_LINK_TRAIN_NONE;
3547 temp |= FDI_LINK_TRAIN_PATTERN_1;
3548 }
3549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3550
3551 POSTING_READ(reg);
3552 udelay(150);
3553
3554 for (i = 0; i < 4; i++) {
3555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
3557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3558 temp |= snb_b_fdi_train_param[i];
3559 I915_WRITE(reg, temp);
3560
3561 POSTING_READ(reg);
3562 udelay(500);
3563
3564 for (retry = 0; retry < 5; retry++) {
3565 reg = FDI_RX_IIR(pipe);
3566 temp = I915_READ(reg);
3567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568 if (temp & FDI_RX_BIT_LOCK) {
3569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3570 DRM_DEBUG_KMS("FDI train 1 done.\n");
3571 break;
3572 }
3573 udelay(50);
3574 }
3575 if (retry < 5)
3576 break;
3577 }
3578 if (i == 4)
3579 DRM_ERROR("FDI train 1 fail!\n");
3580
3581 /* Train 2 */
3582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
3584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2;
3586 if (IS_GEN6(dev)) {
3587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3588 /* SNB-B */
3589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3590 }
3591 I915_WRITE(reg, temp);
3592
3593 reg = FDI_RX_CTL(pipe);
3594 temp = I915_READ(reg);
3595 if (HAS_PCH_CPT(dev)) {
3596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3598 } else {
3599 temp &= ~FDI_LINK_TRAIN_NONE;
3600 temp |= FDI_LINK_TRAIN_PATTERN_2;
3601 }
3602 I915_WRITE(reg, temp);
3603
3604 POSTING_READ(reg);
3605 udelay(150);
3606
3607 for (i = 0; i < 4; i++) {
3608 reg = FDI_TX_CTL(pipe);
3609 temp = I915_READ(reg);
3610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3611 temp |= snb_b_fdi_train_param[i];
3612 I915_WRITE(reg, temp);
3613
3614 POSTING_READ(reg);
3615 udelay(500);
3616
3617 for (retry = 0; retry < 5; retry++) {
3618 reg = FDI_RX_IIR(pipe);
3619 temp = I915_READ(reg);
3620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3621 if (temp & FDI_RX_SYMBOL_LOCK) {
3622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3623 DRM_DEBUG_KMS("FDI train 2 done.\n");
3624 break;
3625 }
3626 udelay(50);
3627 }
3628 if (retry < 5)
3629 break;
3630 }
3631 if (i == 4)
3632 DRM_ERROR("FDI train 2 fail!\n");
3633
3634 DRM_DEBUG_KMS("FDI train done.\n");
3635 }
3636
3637 /* Manual link training for Ivy Bridge A0 parts */
3638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3639 {
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643 int pipe = intel_crtc->pipe;
3644 u32 reg, temp, i, j;
3645
3646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3647 for train result */
3648 reg = FDI_RX_IMR(pipe);
3649 temp = I915_READ(reg);
3650 temp &= ~FDI_RX_SYMBOL_LOCK;
3651 temp &= ~FDI_RX_BIT_LOCK;
3652 I915_WRITE(reg, temp);
3653
3654 POSTING_READ(reg);
3655 udelay(150);
3656
3657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3658 I915_READ(FDI_RX_IIR(pipe)));
3659
3660 /* Try each vswing and preemphasis setting twice before moving on */
3661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3662 /* disable first in case we need to retry */
3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3666 temp &= ~FDI_TX_ENABLE;
3667 I915_WRITE(reg, temp);
3668
3669 reg = FDI_RX_CTL(pipe);
3670 temp = I915_READ(reg);
3671 temp &= ~FDI_LINK_TRAIN_AUTO;
3672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3673 temp &= ~FDI_RX_ENABLE;
3674 I915_WRITE(reg, temp);
3675
3676 /* enable CPU FDI TX and PCH FDI RX */
3677 reg = FDI_TX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3683 temp |= snb_b_fdi_train_param[j/2];
3684 temp |= FDI_COMPOSITE_SYNC;
3685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3686
3687 I915_WRITE(FDI_RX_MISC(pipe),
3688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3689
3690 reg = FDI_RX_CTL(pipe);
3691 temp = I915_READ(reg);
3692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3693 temp |= FDI_COMPOSITE_SYNC;
3694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3695
3696 POSTING_READ(reg);
3697 udelay(1); /* should be 0.5us */
3698
3699 for (i = 0; i < 4; i++) {
3700 reg = FDI_RX_IIR(pipe);
3701 temp = I915_READ(reg);
3702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3703
3704 if (temp & FDI_RX_BIT_LOCK ||
3705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3708 i);
3709 break;
3710 }
3711 udelay(1); /* should be 0.5us */
3712 }
3713 if (i == 4) {
3714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3715 continue;
3716 }
3717
3718 /* Train 2 */
3719 reg = FDI_TX_CTL(pipe);
3720 temp = I915_READ(reg);
3721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3723 I915_WRITE(reg, temp);
3724
3725 reg = FDI_RX_CTL(pipe);
3726 temp = I915_READ(reg);
3727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3729 I915_WRITE(reg, temp);
3730
3731 POSTING_READ(reg);
3732 udelay(2); /* should be 1.5us */
3733
3734 for (i = 0; i < 4; i++) {
3735 reg = FDI_RX_IIR(pipe);
3736 temp = I915_READ(reg);
3737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3738
3739 if (temp & FDI_RX_SYMBOL_LOCK ||
3740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3743 i);
3744 goto train_done;
3745 }
3746 udelay(2); /* should be 1.5us */
3747 }
3748 if (i == 4)
3749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3750 }
3751
3752 train_done:
3753 DRM_DEBUG_KMS("FDI train done.\n");
3754 }
3755
3756 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3757 {
3758 struct drm_device *dev = intel_crtc->base.dev;
3759 struct drm_i915_private *dev_priv = dev->dev_private;
3760 int pipe = intel_crtc->pipe;
3761 u32 reg, temp;
3762
3763
3764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3765 reg = FDI_RX_CTL(pipe);
3766 temp = I915_READ(reg);
3767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3771
3772 POSTING_READ(reg);
3773 udelay(200);
3774
3775 /* Switch from Rawclk to PCDclk */
3776 temp = I915_READ(reg);
3777 I915_WRITE(reg, temp | FDI_PCDCLK);
3778
3779 POSTING_READ(reg);
3780 udelay(200);
3781
3782 /* Enable CPU FDI TX PLL, always on for Ironlake */
3783 reg = FDI_TX_CTL(pipe);
3784 temp = I915_READ(reg);
3785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3787
3788 POSTING_READ(reg);
3789 udelay(100);
3790 }
3791 }
3792
3793 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3794 {
3795 struct drm_device *dev = intel_crtc->base.dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 int pipe = intel_crtc->pipe;
3798 u32 reg, temp;
3799
3800 /* Switch from PCDclk to Rawclk */
3801 reg = FDI_RX_CTL(pipe);
3802 temp = I915_READ(reg);
3803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3804
3805 /* Disable CPU FDI TX PLL */
3806 reg = FDI_TX_CTL(pipe);
3807 temp = I915_READ(reg);
3808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3809
3810 POSTING_READ(reg);
3811 udelay(100);
3812
3813 reg = FDI_RX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3816
3817 /* Wait for the clocks to turn off. */
3818 POSTING_READ(reg);
3819 udelay(100);
3820 }
3821
3822 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3823 {
3824 struct drm_device *dev = crtc->dev;
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3827 int pipe = intel_crtc->pipe;
3828 u32 reg, temp;
3829
3830 /* disable CPU FDI tx and PCH FDI rx */
3831 reg = FDI_TX_CTL(pipe);
3832 temp = I915_READ(reg);
3833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3834 POSTING_READ(reg);
3835
3836 reg = FDI_RX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~(0x7 << 16);
3839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3841
3842 POSTING_READ(reg);
3843 udelay(100);
3844
3845 /* Ironlake workaround, disable clock pointer after downing FDI */
3846 if (HAS_PCH_IBX(dev))
3847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3848
3849 /* still set train pattern 1 */
3850 reg = FDI_TX_CTL(pipe);
3851 temp = I915_READ(reg);
3852 temp &= ~FDI_LINK_TRAIN_NONE;
3853 temp |= FDI_LINK_TRAIN_PATTERN_1;
3854 I915_WRITE(reg, temp);
3855
3856 reg = FDI_RX_CTL(pipe);
3857 temp = I915_READ(reg);
3858 if (HAS_PCH_CPT(dev)) {
3859 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3860 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3861 } else {
3862 temp &= ~FDI_LINK_TRAIN_NONE;
3863 temp |= FDI_LINK_TRAIN_PATTERN_1;
3864 }
3865 /* BPC in FDI rx is consistent with that in PIPECONF */
3866 temp &= ~(0x07 << 16);
3867 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3868 I915_WRITE(reg, temp);
3869
3870 POSTING_READ(reg);
3871 udelay(100);
3872 }
3873
3874 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3875 {
3876 struct intel_crtc *crtc;
3877
3878 /* Note that we don't need to be called with mode_config.lock here
3879 * as our list of CRTC objects is static for the lifetime of the
3880 * device and so cannot disappear as we iterate. Similarly, we can
3881 * happily treat the predicates as racy, atomic checks as userspace
3882 * cannot claim and pin a new fb without at least acquring the
3883 * struct_mutex and so serialising with us.
3884 */
3885 for_each_intel_crtc(dev, crtc) {
3886 if (atomic_read(&crtc->unpin_work_count) == 0)
3887 continue;
3888
3889 if (crtc->unpin_work)
3890 intel_wait_for_vblank(dev, crtc->pipe);
3891
3892 return true;
3893 }
3894
3895 return false;
3896 }
3897
3898 static void page_flip_completed(struct intel_crtc *intel_crtc)
3899 {
3900 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3901 struct intel_unpin_work *work = intel_crtc->unpin_work;
3902
3903 /* ensure that the unpin work is consistent wrt ->pending. */
3904 smp_rmb();
3905 intel_crtc->unpin_work = NULL;
3906
3907 if (work->event)
3908 drm_send_vblank_event(intel_crtc->base.dev,
3909 intel_crtc->pipe,
3910 work->event);
3911
3912 drm_crtc_vblank_put(&intel_crtc->base);
3913
3914 wake_up_all(&dev_priv->pending_flip_queue);
3915 queue_work(dev_priv->wq, &work->work);
3916
3917 trace_i915_flip_complete(intel_crtc->plane,
3918 work->pending_flip_obj);
3919 }
3920
3921 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3922 {
3923 struct drm_device *dev = crtc->dev;
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925
3926 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3927 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3928 !intel_crtc_has_pending_flip(crtc),
3929 60*HZ) == 0)) {
3930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3931
3932 spin_lock_irq(&dev->event_lock);
3933 if (intel_crtc->unpin_work) {
3934 WARN_ONCE(1, "Removing stuck page flip\n");
3935 page_flip_completed(intel_crtc);
3936 }
3937 spin_unlock_irq(&dev->event_lock);
3938 }
3939
3940 if (crtc->primary->fb) {
3941 mutex_lock(&dev->struct_mutex);
3942 intel_finish_fb(crtc->primary->fb);
3943 mutex_unlock(&dev->struct_mutex);
3944 }
3945 }
3946
3947 /* Program iCLKIP clock to the desired frequency */
3948 static void lpt_program_iclkip(struct drm_crtc *crtc)
3949 {
3950 struct drm_device *dev = crtc->dev;
3951 struct drm_i915_private *dev_priv = dev->dev_private;
3952 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3953 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3954 u32 temp;
3955
3956 mutex_lock(&dev_priv->sb_lock);
3957
3958 /* It is necessary to ungate the pixclk gate prior to programming
3959 * the divisors, and gate it back when it is done.
3960 */
3961 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3962
3963 /* Disable SSCCTL */
3964 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3965 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3966 SBI_SSCCTL_DISABLE,
3967 SBI_ICLK);
3968
3969 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3970 if (clock == 20000) {
3971 auxdiv = 1;
3972 divsel = 0x41;
3973 phaseinc = 0x20;
3974 } else {
3975 /* The iCLK virtual clock root frequency is in MHz,
3976 * but the adjusted_mode->crtc_clock in in KHz. To get the
3977 * divisors, it is necessary to divide one by another, so we
3978 * convert the virtual clock precision to KHz here for higher
3979 * precision.
3980 */
3981 u32 iclk_virtual_root_freq = 172800 * 1000;
3982 u32 iclk_pi_range = 64;
3983 u32 desired_divisor, msb_divisor_value, pi_value;
3984
3985 desired_divisor = (iclk_virtual_root_freq / clock);
3986 msb_divisor_value = desired_divisor / iclk_pi_range;
3987 pi_value = desired_divisor % iclk_pi_range;
3988
3989 auxdiv = 0;
3990 divsel = msb_divisor_value - 2;
3991 phaseinc = pi_value;
3992 }
3993
3994 /* This should not happen with any sane values */
3995 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3996 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3997 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3998 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3999
4000 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4001 clock,
4002 auxdiv,
4003 divsel,
4004 phasedir,
4005 phaseinc);
4006
4007 /* Program SSCDIVINTPHASE6 */
4008 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4009 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4010 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4011 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4012 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4013 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4014 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4015 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4016
4017 /* Program SSCAUXDIV */
4018 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4019 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4020 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4021 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4022
4023 /* Enable modulator and associated divider */
4024 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4025 temp &= ~SBI_SSCCTL_DISABLE;
4026 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4027
4028 /* Wait for initialization time */
4029 udelay(24);
4030
4031 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4032
4033 mutex_unlock(&dev_priv->sb_lock);
4034 }
4035
4036 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4037 enum pipe pch_transcoder)
4038 {
4039 struct drm_device *dev = crtc->base.dev;
4040 struct drm_i915_private *dev_priv = dev->dev_private;
4041 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4042
4043 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4044 I915_READ(HTOTAL(cpu_transcoder)));
4045 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4046 I915_READ(HBLANK(cpu_transcoder)));
4047 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4048 I915_READ(HSYNC(cpu_transcoder)));
4049
4050 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4051 I915_READ(VTOTAL(cpu_transcoder)));
4052 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4053 I915_READ(VBLANK(cpu_transcoder)));
4054 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4055 I915_READ(VSYNC(cpu_transcoder)));
4056 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4057 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4058 }
4059
4060 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4061 {
4062 struct drm_i915_private *dev_priv = dev->dev_private;
4063 uint32_t temp;
4064
4065 temp = I915_READ(SOUTH_CHICKEN1);
4066 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4067 return;
4068
4069 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4070 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4071
4072 temp &= ~FDI_BC_BIFURCATION_SELECT;
4073 if (enable)
4074 temp |= FDI_BC_BIFURCATION_SELECT;
4075
4076 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4077 I915_WRITE(SOUTH_CHICKEN1, temp);
4078 POSTING_READ(SOUTH_CHICKEN1);
4079 }
4080
4081 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4082 {
4083 struct drm_device *dev = intel_crtc->base.dev;
4084
4085 switch (intel_crtc->pipe) {
4086 case PIPE_A:
4087 break;
4088 case PIPE_B:
4089 if (intel_crtc->config->fdi_lanes > 2)
4090 cpt_set_fdi_bc_bifurcation(dev, false);
4091 else
4092 cpt_set_fdi_bc_bifurcation(dev, true);
4093
4094 break;
4095 case PIPE_C:
4096 cpt_set_fdi_bc_bifurcation(dev, true);
4097
4098 break;
4099 default:
4100 BUG();
4101 }
4102 }
4103
4104 /*
4105 * Enable PCH resources required for PCH ports:
4106 * - PCH PLLs
4107 * - FDI training & RX/TX
4108 * - update transcoder timings
4109 * - DP transcoding bits
4110 * - transcoder
4111 */
4112 static void ironlake_pch_enable(struct drm_crtc *crtc)
4113 {
4114 struct drm_device *dev = crtc->dev;
4115 struct drm_i915_private *dev_priv = dev->dev_private;
4116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4117 int pipe = intel_crtc->pipe;
4118 u32 reg, temp;
4119
4120 assert_pch_transcoder_disabled(dev_priv, pipe);
4121
4122 if (IS_IVYBRIDGE(dev))
4123 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4124
4125 /* Write the TU size bits before fdi link training, so that error
4126 * detection works. */
4127 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4128 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4129
4130 /* For PCH output, training FDI link */
4131 dev_priv->display.fdi_link_train(crtc);
4132
4133 /* We need to program the right clock selection before writing the pixel
4134 * mutliplier into the DPLL. */
4135 if (HAS_PCH_CPT(dev)) {
4136 u32 sel;
4137
4138 temp = I915_READ(PCH_DPLL_SEL);
4139 temp |= TRANS_DPLL_ENABLE(pipe);
4140 sel = TRANS_DPLLB_SEL(pipe);
4141 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4142 temp |= sel;
4143 else
4144 temp &= ~sel;
4145 I915_WRITE(PCH_DPLL_SEL, temp);
4146 }
4147
4148 /* XXX: pch pll's can be enabled any time before we enable the PCH
4149 * transcoder, and we actually should do this to not upset any PCH
4150 * transcoder that already use the clock when we share it.
4151 *
4152 * Note that enable_shared_dpll tries to do the right thing, but
4153 * get_shared_dpll unconditionally resets the pll - we need that to have
4154 * the right LVDS enable sequence. */
4155 intel_enable_shared_dpll(intel_crtc);
4156
4157 /* set transcoder timing, panel must allow it */
4158 assert_panel_unlocked(dev_priv, pipe);
4159 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4160
4161 intel_fdi_normal_train(crtc);
4162
4163 /* For PCH DP, enable TRANS_DP_CTL */
4164 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4165 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4166 reg = TRANS_DP_CTL(pipe);
4167 temp = I915_READ(reg);
4168 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4169 TRANS_DP_SYNC_MASK |
4170 TRANS_DP_BPC_MASK);
4171 temp |= TRANS_DP_OUTPUT_ENABLE;
4172 temp |= bpc << 9; /* same format but at 11:9 */
4173
4174 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4175 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4176 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4177 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4178
4179 switch (intel_trans_dp_port_sel(crtc)) {
4180 case PCH_DP_B:
4181 temp |= TRANS_DP_PORT_SEL_B;
4182 break;
4183 case PCH_DP_C:
4184 temp |= TRANS_DP_PORT_SEL_C;
4185 break;
4186 case PCH_DP_D:
4187 temp |= TRANS_DP_PORT_SEL_D;
4188 break;
4189 default:
4190 BUG();
4191 }
4192
4193 I915_WRITE(reg, temp);
4194 }
4195
4196 ironlake_enable_pch_transcoder(dev_priv, pipe);
4197 }
4198
4199 static void lpt_pch_enable(struct drm_crtc *crtc)
4200 {
4201 struct drm_device *dev = crtc->dev;
4202 struct drm_i915_private *dev_priv = dev->dev_private;
4203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4204 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4205
4206 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4207
4208 lpt_program_iclkip(crtc);
4209
4210 /* Set transcoder timing. */
4211 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4212
4213 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4214 }
4215
4216 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4217 struct intel_crtc_state *crtc_state)
4218 {
4219 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4220 struct intel_shared_dpll *pll;
4221 struct intel_shared_dpll_config *shared_dpll;
4222 enum intel_dpll_id i;
4223
4224 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4225
4226 if (HAS_PCH_IBX(dev_priv->dev)) {
4227 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4228 i = (enum intel_dpll_id) crtc->pipe;
4229 pll = &dev_priv->shared_dplls[i];
4230
4231 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4232 crtc->base.base.id, pll->name);
4233
4234 WARN_ON(shared_dpll[i].crtc_mask);
4235
4236 goto found;
4237 }
4238
4239 if (IS_BROXTON(dev_priv->dev)) {
4240 /* PLL is attached to port in bxt */
4241 struct intel_encoder *encoder;
4242 struct intel_digital_port *intel_dig_port;
4243
4244 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4245 if (WARN_ON(!encoder))
4246 return NULL;
4247
4248 intel_dig_port = enc_to_dig_port(&encoder->base);
4249 /* 1:1 mapping between ports and PLLs */
4250 i = (enum intel_dpll_id)intel_dig_port->port;
4251 pll = &dev_priv->shared_dplls[i];
4252 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4253 crtc->base.base.id, pll->name);
4254 WARN_ON(shared_dpll[i].crtc_mask);
4255
4256 goto found;
4257 }
4258
4259 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4260 pll = &dev_priv->shared_dplls[i];
4261
4262 /* Only want to check enabled timings first */
4263 if (shared_dpll[i].crtc_mask == 0)
4264 continue;
4265
4266 if (memcmp(&crtc_state->dpll_hw_state,
4267 &shared_dpll[i].hw_state,
4268 sizeof(crtc_state->dpll_hw_state)) == 0) {
4269 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4270 crtc->base.base.id, pll->name,
4271 shared_dpll[i].crtc_mask,
4272 pll->active);
4273 goto found;
4274 }
4275 }
4276
4277 /* Ok no matching timings, maybe there's a free one? */
4278 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4279 pll = &dev_priv->shared_dplls[i];
4280 if (shared_dpll[i].crtc_mask == 0) {
4281 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4282 crtc->base.base.id, pll->name);
4283 goto found;
4284 }
4285 }
4286
4287 return NULL;
4288
4289 found:
4290 if (shared_dpll[i].crtc_mask == 0)
4291 shared_dpll[i].hw_state =
4292 crtc_state->dpll_hw_state;
4293
4294 crtc_state->shared_dpll = i;
4295 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4296 pipe_name(crtc->pipe));
4297
4298 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4299
4300 return pll;
4301 }
4302
4303 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4304 {
4305 struct drm_i915_private *dev_priv = to_i915(state->dev);
4306 struct intel_shared_dpll_config *shared_dpll;
4307 struct intel_shared_dpll *pll;
4308 enum intel_dpll_id i;
4309
4310 if (!to_intel_atomic_state(state)->dpll_set)
4311 return;
4312
4313 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4314 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4315 pll = &dev_priv->shared_dplls[i];
4316 pll->config = shared_dpll[i];
4317 }
4318 }
4319
4320 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4321 {
4322 struct drm_i915_private *dev_priv = dev->dev_private;
4323 int dslreg = PIPEDSL(pipe);
4324 u32 temp;
4325
4326 temp = I915_READ(dslreg);
4327 udelay(500);
4328 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4329 if (wait_for(I915_READ(dslreg) != temp, 5))
4330 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4331 }
4332 }
4333
4334 static int
4335 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4336 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4337 int src_w, int src_h, int dst_w, int dst_h)
4338 {
4339 struct intel_crtc_scaler_state *scaler_state =
4340 &crtc_state->scaler_state;
4341 struct intel_crtc *intel_crtc =
4342 to_intel_crtc(crtc_state->base.crtc);
4343 int need_scaling;
4344
4345 need_scaling = intel_rotation_90_or_270(rotation) ?
4346 (src_h != dst_w || src_w != dst_h):
4347 (src_w != dst_w || src_h != dst_h);
4348
4349 /*
4350 * if plane is being disabled or scaler is no more required or force detach
4351 * - free scaler binded to this plane/crtc
4352 * - in order to do this, update crtc->scaler_usage
4353 *
4354 * Here scaler state in crtc_state is set free so that
4355 * scaler can be assigned to other user. Actual register
4356 * update to free the scaler is done in plane/panel-fit programming.
4357 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4358 */
4359 if (force_detach || !need_scaling) {
4360 if (*scaler_id >= 0) {
4361 scaler_state->scaler_users &= ~(1 << scaler_user);
4362 scaler_state->scalers[*scaler_id].in_use = 0;
4363
4364 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4365 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4366 intel_crtc->pipe, scaler_user, *scaler_id,
4367 scaler_state->scaler_users);
4368 *scaler_id = -1;
4369 }
4370 return 0;
4371 }
4372
4373 /* range checks */
4374 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4375 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4376
4377 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4378 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4379 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4380 "size is out of scaler range\n",
4381 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4382 return -EINVAL;
4383 }
4384
4385 /* mark this plane as a scaler user in crtc_state */
4386 scaler_state->scaler_users |= (1 << scaler_user);
4387 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4388 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4389 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4390 scaler_state->scaler_users);
4391
4392 return 0;
4393 }
4394
4395 /**
4396 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4397 *
4398 * @state: crtc's scaler state
4399 *
4400 * Return
4401 * 0 - scaler_usage updated successfully
4402 * error - requested scaling cannot be supported or other error condition
4403 */
4404 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4405 {
4406 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4407 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4408
4409 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4410 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4411
4412 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4413 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4414 state->pipe_src_w, state->pipe_src_h,
4415 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4416 }
4417
4418 /**
4419 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4420 *
4421 * @state: crtc's scaler state
4422 * @plane_state: atomic plane state to update
4423 *
4424 * Return
4425 * 0 - scaler_usage updated successfully
4426 * error - requested scaling cannot be supported or other error condition
4427 */
4428 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4429 struct intel_plane_state *plane_state)
4430 {
4431
4432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4433 struct intel_plane *intel_plane =
4434 to_intel_plane(plane_state->base.plane);
4435 struct drm_framebuffer *fb = plane_state->base.fb;
4436 int ret;
4437
4438 bool force_detach = !fb || !plane_state->visible;
4439
4440 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4441 intel_plane->base.base.id, intel_crtc->pipe,
4442 drm_plane_index(&intel_plane->base));
4443
4444 ret = skl_update_scaler(crtc_state, force_detach,
4445 drm_plane_index(&intel_plane->base),
4446 &plane_state->scaler_id,
4447 plane_state->base.rotation,
4448 drm_rect_width(&plane_state->src) >> 16,
4449 drm_rect_height(&plane_state->src) >> 16,
4450 drm_rect_width(&plane_state->dst),
4451 drm_rect_height(&plane_state->dst));
4452
4453 if (ret || plane_state->scaler_id < 0)
4454 return ret;
4455
4456 /* check colorkey */
4457 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4458 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4459 intel_plane->base.base.id);
4460 return -EINVAL;
4461 }
4462
4463 /* Check src format */
4464 switch (fb->pixel_format) {
4465 case DRM_FORMAT_RGB565:
4466 case DRM_FORMAT_XBGR8888:
4467 case DRM_FORMAT_XRGB8888:
4468 case DRM_FORMAT_ABGR8888:
4469 case DRM_FORMAT_ARGB8888:
4470 case DRM_FORMAT_XRGB2101010:
4471 case DRM_FORMAT_XBGR2101010:
4472 case DRM_FORMAT_YUYV:
4473 case DRM_FORMAT_YVYU:
4474 case DRM_FORMAT_UYVY:
4475 case DRM_FORMAT_VYUY:
4476 break;
4477 default:
4478 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4479 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4480 return -EINVAL;
4481 }
4482
4483 return 0;
4484 }
4485
4486 static void skylake_scaler_disable(struct intel_crtc *crtc)
4487 {
4488 int i;
4489
4490 for (i = 0; i < crtc->num_scalers; i++)
4491 skl_detach_scaler(crtc, i);
4492 }
4493
4494 static void skylake_pfit_enable(struct intel_crtc *crtc)
4495 {
4496 struct drm_device *dev = crtc->base.dev;
4497 struct drm_i915_private *dev_priv = dev->dev_private;
4498 int pipe = crtc->pipe;
4499 struct intel_crtc_scaler_state *scaler_state =
4500 &crtc->config->scaler_state;
4501
4502 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4503
4504 if (crtc->config->pch_pfit.enabled) {
4505 int id;
4506
4507 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4508 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4509 return;
4510 }
4511
4512 id = scaler_state->scaler_id;
4513 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4514 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4515 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4516 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4517
4518 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4519 }
4520 }
4521
4522 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4523 {
4524 struct drm_device *dev = crtc->base.dev;
4525 struct drm_i915_private *dev_priv = dev->dev_private;
4526 int pipe = crtc->pipe;
4527
4528 if (crtc->config->pch_pfit.enabled) {
4529 /* Force use of hard-coded filter coefficients
4530 * as some pre-programmed values are broken,
4531 * e.g. x201.
4532 */
4533 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4534 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4535 PF_PIPE_SEL_IVB(pipe));
4536 else
4537 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4538 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4539 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4540 }
4541 }
4542
4543 void hsw_enable_ips(struct intel_crtc *crtc)
4544 {
4545 struct drm_device *dev = crtc->base.dev;
4546 struct drm_i915_private *dev_priv = dev->dev_private;
4547
4548 if (!crtc->config->ips_enabled)
4549 return;
4550
4551 /* We can only enable IPS after we enable a plane and wait for a vblank */
4552 intel_wait_for_vblank(dev, crtc->pipe);
4553
4554 assert_plane_enabled(dev_priv, crtc->plane);
4555 if (IS_BROADWELL(dev)) {
4556 mutex_lock(&dev_priv->rps.hw_lock);
4557 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4558 mutex_unlock(&dev_priv->rps.hw_lock);
4559 /* Quoting Art Runyan: "its not safe to expect any particular
4560 * value in IPS_CTL bit 31 after enabling IPS through the
4561 * mailbox." Moreover, the mailbox may return a bogus state,
4562 * so we need to just enable it and continue on.
4563 */
4564 } else {
4565 I915_WRITE(IPS_CTL, IPS_ENABLE);
4566 /* The bit only becomes 1 in the next vblank, so this wait here
4567 * is essentially intel_wait_for_vblank. If we don't have this
4568 * and don't wait for vblanks until the end of crtc_enable, then
4569 * the HW state readout code will complain that the expected
4570 * IPS_CTL value is not the one we read. */
4571 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4572 DRM_ERROR("Timed out waiting for IPS enable\n");
4573 }
4574 }
4575
4576 void hsw_disable_ips(struct intel_crtc *crtc)
4577 {
4578 struct drm_device *dev = crtc->base.dev;
4579 struct drm_i915_private *dev_priv = dev->dev_private;
4580
4581 if (!crtc->config->ips_enabled)
4582 return;
4583
4584 assert_plane_enabled(dev_priv, crtc->plane);
4585 if (IS_BROADWELL(dev)) {
4586 mutex_lock(&dev_priv->rps.hw_lock);
4587 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4588 mutex_unlock(&dev_priv->rps.hw_lock);
4589 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4590 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4591 DRM_ERROR("Timed out waiting for IPS disable\n");
4592 } else {
4593 I915_WRITE(IPS_CTL, 0);
4594 POSTING_READ(IPS_CTL);
4595 }
4596
4597 /* We need to wait for a vblank before we can disable the plane. */
4598 intel_wait_for_vblank(dev, crtc->pipe);
4599 }
4600
4601 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4602 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4603 {
4604 struct drm_device *dev = crtc->dev;
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4607 enum pipe pipe = intel_crtc->pipe;
4608 int i;
4609 bool reenable_ips = false;
4610
4611 /* The clocks have to be on to load the palette. */
4612 if (!crtc->state->active)
4613 return;
4614
4615 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4616 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4617 assert_dsi_pll_enabled(dev_priv);
4618 else
4619 assert_pll_enabled(dev_priv, pipe);
4620 }
4621
4622 /* Workaround : Do not read or write the pipe palette/gamma data while
4623 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4624 */
4625 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4626 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4627 GAMMA_MODE_MODE_SPLIT)) {
4628 hsw_disable_ips(intel_crtc);
4629 reenable_ips = true;
4630 }
4631
4632 for (i = 0; i < 256; i++) {
4633 u32 palreg;
4634
4635 if (HAS_GMCH_DISPLAY(dev))
4636 palreg = PALETTE(pipe, i);
4637 else
4638 palreg = LGC_PALETTE(pipe, i);
4639
4640 I915_WRITE(palreg,
4641 (intel_crtc->lut_r[i] << 16) |
4642 (intel_crtc->lut_g[i] << 8) |
4643 intel_crtc->lut_b[i]);
4644 }
4645
4646 if (reenable_ips)
4647 hsw_enable_ips(intel_crtc);
4648 }
4649
4650 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4651 {
4652 if (intel_crtc->overlay) {
4653 struct drm_device *dev = intel_crtc->base.dev;
4654 struct drm_i915_private *dev_priv = dev->dev_private;
4655
4656 mutex_lock(&dev->struct_mutex);
4657 dev_priv->mm.interruptible = false;
4658 (void) intel_overlay_switch_off(intel_crtc->overlay);
4659 dev_priv->mm.interruptible = true;
4660 mutex_unlock(&dev->struct_mutex);
4661 }
4662
4663 /* Let userspace switch the overlay on again. In most cases userspace
4664 * has to recompute where to put it anyway.
4665 */
4666 }
4667
4668 /**
4669 * intel_post_enable_primary - Perform operations after enabling primary plane
4670 * @crtc: the CRTC whose primary plane was just enabled
4671 *
4672 * Performs potentially sleeping operations that must be done after the primary
4673 * plane is enabled, such as updating FBC and IPS. Note that this may be
4674 * called due to an explicit primary plane update, or due to an implicit
4675 * re-enable that is caused when a sprite plane is updated to no longer
4676 * completely hide the primary plane.
4677 */
4678 static void
4679 intel_post_enable_primary(struct drm_crtc *crtc)
4680 {
4681 struct drm_device *dev = crtc->dev;
4682 struct drm_i915_private *dev_priv = dev->dev_private;
4683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4684 int pipe = intel_crtc->pipe;
4685
4686 /*
4687 * BDW signals flip done immediately if the plane
4688 * is disabled, even if the plane enable is already
4689 * armed to occur at the next vblank :(
4690 */
4691 if (IS_BROADWELL(dev))
4692 intel_wait_for_vblank(dev, pipe);
4693
4694 /*
4695 * FIXME IPS should be fine as long as one plane is
4696 * enabled, but in practice it seems to have problems
4697 * when going from primary only to sprite only and vice
4698 * versa.
4699 */
4700 hsw_enable_ips(intel_crtc);
4701
4702 /*
4703 * Gen2 reports pipe underruns whenever all planes are disabled.
4704 * So don't enable underrun reporting before at least some planes
4705 * are enabled.
4706 * FIXME: Need to fix the logic to work when we turn off all planes
4707 * but leave the pipe running.
4708 */
4709 if (IS_GEN2(dev))
4710 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4711
4712 /* Underruns don't raise interrupts, so check manually. */
4713 if (HAS_GMCH_DISPLAY(dev))
4714 i9xx_check_fifo_underruns(dev_priv);
4715 }
4716
4717 /**
4718 * intel_pre_disable_primary - Perform operations before disabling primary plane
4719 * @crtc: the CRTC whose primary plane is to be disabled
4720 *
4721 * Performs potentially sleeping operations that must be done before the
4722 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4723 * be called due to an explicit primary plane update, or due to an implicit
4724 * disable that is caused when a sprite plane completely hides the primary
4725 * plane.
4726 */
4727 static void
4728 intel_pre_disable_primary(struct drm_crtc *crtc)
4729 {
4730 struct drm_device *dev = crtc->dev;
4731 struct drm_i915_private *dev_priv = dev->dev_private;
4732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4733 int pipe = intel_crtc->pipe;
4734
4735 /*
4736 * Gen2 reports pipe underruns whenever all planes are disabled.
4737 * So diasble underrun reporting before all the planes get disabled.
4738 * FIXME: Need to fix the logic to work when we turn off all planes
4739 * but leave the pipe running.
4740 */
4741 if (IS_GEN2(dev))
4742 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4743
4744 /*
4745 * Vblank time updates from the shadow to live plane control register
4746 * are blocked if the memory self-refresh mode is active at that
4747 * moment. So to make sure the plane gets truly disabled, disable
4748 * first the self-refresh mode. The self-refresh enable bit in turn
4749 * will be checked/applied by the HW only at the next frame start
4750 * event which is after the vblank start event, so we need to have a
4751 * wait-for-vblank between disabling the plane and the pipe.
4752 */
4753 if (HAS_GMCH_DISPLAY(dev)) {
4754 intel_set_memory_cxsr(dev_priv, false);
4755 dev_priv->wm.vlv.cxsr = false;
4756 intel_wait_for_vblank(dev, pipe);
4757 }
4758
4759 /*
4760 * FIXME IPS should be fine as long as one plane is
4761 * enabled, but in practice it seems to have problems
4762 * when going from primary only to sprite only and vice
4763 * versa.
4764 */
4765 hsw_disable_ips(intel_crtc);
4766 }
4767
4768 static void intel_post_plane_update(struct intel_crtc *crtc)
4769 {
4770 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4771 struct drm_device *dev = crtc->base.dev;
4772 struct drm_i915_private *dev_priv = dev->dev_private;
4773 struct drm_plane *plane;
4774
4775 if (atomic->wait_vblank)
4776 intel_wait_for_vblank(dev, crtc->pipe);
4777
4778 intel_frontbuffer_flip(dev, atomic->fb_bits);
4779
4780 if (atomic->disable_cxsr)
4781 crtc->wm.cxsr_allowed = true;
4782
4783 if (crtc->atomic.update_wm_post)
4784 intel_update_watermarks(&crtc->base);
4785
4786 if (atomic->update_fbc)
4787 intel_fbc_update(dev_priv);
4788
4789 if (atomic->post_enable_primary)
4790 intel_post_enable_primary(&crtc->base);
4791
4792 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4793 intel_update_sprite_watermarks(plane, &crtc->base,
4794 0, 0, 0, false, false);
4795
4796 memset(atomic, 0, sizeof(*atomic));
4797 }
4798
4799 static void intel_pre_plane_update(struct intel_crtc *crtc)
4800 {
4801 struct drm_device *dev = crtc->base.dev;
4802 struct drm_i915_private *dev_priv = dev->dev_private;
4803 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4804
4805 if (atomic->wait_for_flips)
4806 intel_crtc_wait_for_pending_flips(&crtc->base);
4807
4808 if (atomic->disable_fbc)
4809 intel_fbc_disable_crtc(crtc);
4810
4811 if (crtc->atomic.disable_ips)
4812 hsw_disable_ips(crtc);
4813
4814 if (atomic->pre_disable_primary)
4815 intel_pre_disable_primary(&crtc->base);
4816
4817 if (atomic->disable_cxsr) {
4818 crtc->wm.cxsr_allowed = false;
4819 intel_set_memory_cxsr(dev_priv, false);
4820 }
4821 }
4822
4823 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4824 {
4825 struct drm_device *dev = crtc->dev;
4826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4827 struct drm_plane *p;
4828 int pipe = intel_crtc->pipe;
4829
4830 intel_crtc_dpms_overlay_disable(intel_crtc);
4831
4832 drm_for_each_plane_mask(p, dev, plane_mask)
4833 to_intel_plane(p)->disable_plane(p, crtc);
4834
4835 /*
4836 * FIXME: Once we grow proper nuclear flip support out of this we need
4837 * to compute the mask of flip planes precisely. For the time being
4838 * consider this a flip to a NULL plane.
4839 */
4840 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4841 }
4842
4843 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4844 {
4845 struct drm_device *dev = crtc->dev;
4846 struct drm_i915_private *dev_priv = dev->dev_private;
4847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4848 struct intel_encoder *encoder;
4849 int pipe = intel_crtc->pipe;
4850
4851 if (WARN_ON(intel_crtc->active))
4852 return;
4853
4854 if (intel_crtc->config->has_pch_encoder)
4855 intel_prepare_shared_dpll(intel_crtc);
4856
4857 if (intel_crtc->config->has_dp_encoder)
4858 intel_dp_set_m_n(intel_crtc, M1_N1);
4859
4860 intel_set_pipe_timings(intel_crtc);
4861
4862 if (intel_crtc->config->has_pch_encoder) {
4863 intel_cpu_transcoder_set_m_n(intel_crtc,
4864 &intel_crtc->config->fdi_m_n, NULL);
4865 }
4866
4867 ironlake_set_pipeconf(crtc);
4868
4869 intel_crtc->active = true;
4870
4871 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4872 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4873
4874 for_each_encoder_on_crtc(dev, crtc, encoder)
4875 if (encoder->pre_enable)
4876 encoder->pre_enable(encoder);
4877
4878 if (intel_crtc->config->has_pch_encoder) {
4879 /* Note: FDI PLL enabling _must_ be done before we enable the
4880 * cpu pipes, hence this is separate from all the other fdi/pch
4881 * enabling. */
4882 ironlake_fdi_pll_enable(intel_crtc);
4883 } else {
4884 assert_fdi_tx_disabled(dev_priv, pipe);
4885 assert_fdi_rx_disabled(dev_priv, pipe);
4886 }
4887
4888 ironlake_pfit_enable(intel_crtc);
4889
4890 /*
4891 * On ILK+ LUT must be loaded before the pipe is running but with
4892 * clocks enabled
4893 */
4894 intel_crtc_load_lut(crtc);
4895
4896 intel_update_watermarks(crtc);
4897 intel_enable_pipe(intel_crtc);
4898
4899 if (intel_crtc->config->has_pch_encoder)
4900 ironlake_pch_enable(crtc);
4901
4902 assert_vblank_disabled(crtc);
4903 drm_crtc_vblank_on(crtc);
4904
4905 for_each_encoder_on_crtc(dev, crtc, encoder)
4906 encoder->enable(encoder);
4907
4908 if (HAS_PCH_CPT(dev))
4909 cpt_verify_modeset(dev, intel_crtc->pipe);
4910 }
4911
4912 /* IPS only exists on ULT machines and is tied to pipe A. */
4913 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4914 {
4915 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4916 }
4917
4918 static void haswell_crtc_enable(struct drm_crtc *crtc)
4919 {
4920 struct drm_device *dev = crtc->dev;
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4923 struct intel_encoder *encoder;
4924 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4925 struct intel_crtc_state *pipe_config =
4926 to_intel_crtc_state(crtc->state);
4927 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4928
4929 if (WARN_ON(intel_crtc->active))
4930 return;
4931
4932 if (intel_crtc_to_shared_dpll(intel_crtc))
4933 intel_enable_shared_dpll(intel_crtc);
4934
4935 if (intel_crtc->config->has_dp_encoder)
4936 intel_dp_set_m_n(intel_crtc, M1_N1);
4937
4938 intel_set_pipe_timings(intel_crtc);
4939
4940 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4941 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4942 intel_crtc->config->pixel_multiplier - 1);
4943 }
4944
4945 if (intel_crtc->config->has_pch_encoder) {
4946 intel_cpu_transcoder_set_m_n(intel_crtc,
4947 &intel_crtc->config->fdi_m_n, NULL);
4948 }
4949
4950 haswell_set_pipeconf(crtc);
4951
4952 intel_set_pipe_csc(crtc);
4953
4954 intel_crtc->active = true;
4955
4956 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4957 for_each_encoder_on_crtc(dev, crtc, encoder) {
4958 if (encoder->pre_pll_enable)
4959 encoder->pre_pll_enable(encoder);
4960 if (encoder->pre_enable)
4961 encoder->pre_enable(encoder);
4962 }
4963
4964 if (intel_crtc->config->has_pch_encoder) {
4965 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4966 true);
4967 dev_priv->display.fdi_link_train(crtc);
4968 }
4969
4970 if (!is_dsi)
4971 intel_ddi_enable_pipe_clock(intel_crtc);
4972
4973 if (INTEL_INFO(dev)->gen >= 9)
4974 skylake_pfit_enable(intel_crtc);
4975 else
4976 ironlake_pfit_enable(intel_crtc);
4977
4978 /*
4979 * On ILK+ LUT must be loaded before the pipe is running but with
4980 * clocks enabled
4981 */
4982 intel_crtc_load_lut(crtc);
4983
4984 intel_ddi_set_pipe_settings(crtc);
4985 if (!is_dsi)
4986 intel_ddi_enable_transcoder_func(crtc);
4987
4988 intel_update_watermarks(crtc);
4989 intel_enable_pipe(intel_crtc);
4990
4991 if (intel_crtc->config->has_pch_encoder)
4992 lpt_pch_enable(crtc);
4993
4994 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
4995 intel_ddi_set_vc_payload_alloc(crtc, true);
4996
4997 assert_vblank_disabled(crtc);
4998 drm_crtc_vblank_on(crtc);
4999
5000 for_each_encoder_on_crtc(dev, crtc, encoder) {
5001 encoder->enable(encoder);
5002 intel_opregion_notify_encoder(encoder, true);
5003 }
5004
5005 /* If we change the relative order between pipe/planes enabling, we need
5006 * to change the workaround. */
5007 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5008 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5009 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5010 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5011 }
5012 }
5013
5014 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5015 {
5016 struct drm_device *dev = crtc->base.dev;
5017 struct drm_i915_private *dev_priv = dev->dev_private;
5018 int pipe = crtc->pipe;
5019
5020 /* To avoid upsetting the power well on haswell only disable the pfit if
5021 * it's in use. The hw state code will make sure we get this right. */
5022 if (force || crtc->config->pch_pfit.enabled) {
5023 I915_WRITE(PF_CTL(pipe), 0);
5024 I915_WRITE(PF_WIN_POS(pipe), 0);
5025 I915_WRITE(PF_WIN_SZ(pipe), 0);
5026 }
5027 }
5028
5029 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5030 {
5031 struct drm_device *dev = crtc->dev;
5032 struct drm_i915_private *dev_priv = dev->dev_private;
5033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5034 struct intel_encoder *encoder;
5035 int pipe = intel_crtc->pipe;
5036 u32 reg, temp;
5037
5038 for_each_encoder_on_crtc(dev, crtc, encoder)
5039 encoder->disable(encoder);
5040
5041 drm_crtc_vblank_off(crtc);
5042 assert_vblank_disabled(crtc);
5043
5044 if (intel_crtc->config->has_pch_encoder)
5045 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5046
5047 intel_disable_pipe(intel_crtc);
5048
5049 ironlake_pfit_disable(intel_crtc, false);
5050
5051 if (intel_crtc->config->has_pch_encoder)
5052 ironlake_fdi_disable(crtc);
5053
5054 for_each_encoder_on_crtc(dev, crtc, encoder)
5055 if (encoder->post_disable)
5056 encoder->post_disable(encoder);
5057
5058 if (intel_crtc->config->has_pch_encoder) {
5059 ironlake_disable_pch_transcoder(dev_priv, pipe);
5060
5061 if (HAS_PCH_CPT(dev)) {
5062 /* disable TRANS_DP_CTL */
5063 reg = TRANS_DP_CTL(pipe);
5064 temp = I915_READ(reg);
5065 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5066 TRANS_DP_PORT_SEL_MASK);
5067 temp |= TRANS_DP_PORT_SEL_NONE;
5068 I915_WRITE(reg, temp);
5069
5070 /* disable DPLL_SEL */
5071 temp = I915_READ(PCH_DPLL_SEL);
5072 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5073 I915_WRITE(PCH_DPLL_SEL, temp);
5074 }
5075
5076 ironlake_fdi_pll_disable(intel_crtc);
5077 }
5078 }
5079
5080 static void haswell_crtc_disable(struct drm_crtc *crtc)
5081 {
5082 struct drm_device *dev = crtc->dev;
5083 struct drm_i915_private *dev_priv = dev->dev_private;
5084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5085 struct intel_encoder *encoder;
5086 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5087 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5088
5089 for_each_encoder_on_crtc(dev, crtc, encoder) {
5090 intel_opregion_notify_encoder(encoder, false);
5091 encoder->disable(encoder);
5092 }
5093
5094 drm_crtc_vblank_off(crtc);
5095 assert_vblank_disabled(crtc);
5096
5097 if (intel_crtc->config->has_pch_encoder)
5098 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5099 false);
5100 intel_disable_pipe(intel_crtc);
5101
5102 if (intel_crtc->config->dp_encoder_is_mst)
5103 intel_ddi_set_vc_payload_alloc(crtc, false);
5104
5105 if (!is_dsi)
5106 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5107
5108 if (INTEL_INFO(dev)->gen >= 9)
5109 skylake_scaler_disable(intel_crtc);
5110 else
5111 ironlake_pfit_disable(intel_crtc, false);
5112
5113 if (!is_dsi)
5114 intel_ddi_disable_pipe_clock(intel_crtc);
5115
5116 if (intel_crtc->config->has_pch_encoder) {
5117 lpt_disable_pch_transcoder(dev_priv);
5118 intel_ddi_fdi_disable(crtc);
5119 }
5120
5121 for_each_encoder_on_crtc(dev, crtc, encoder)
5122 if (encoder->post_disable)
5123 encoder->post_disable(encoder);
5124 }
5125
5126 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5127 {
5128 struct drm_device *dev = crtc->base.dev;
5129 struct drm_i915_private *dev_priv = dev->dev_private;
5130 struct intel_crtc_state *pipe_config = crtc->config;
5131
5132 if (!pipe_config->gmch_pfit.control)
5133 return;
5134
5135 /*
5136 * The panel fitter should only be adjusted whilst the pipe is disabled,
5137 * according to register description and PRM.
5138 */
5139 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5140 assert_pipe_disabled(dev_priv, crtc->pipe);
5141
5142 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5143 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5144
5145 /* Border color in case we don't scale up to the full screen. Black by
5146 * default, change to something else for debugging. */
5147 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5148 }
5149
5150 static enum intel_display_power_domain port_to_power_domain(enum port port)
5151 {
5152 switch (port) {
5153 case PORT_A:
5154 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5155 case PORT_B:
5156 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5157 case PORT_C:
5158 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5159 case PORT_D:
5160 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5161 case PORT_E:
5162 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5163 default:
5164 WARN_ON_ONCE(1);
5165 return POWER_DOMAIN_PORT_OTHER;
5166 }
5167 }
5168
5169 #define for_each_power_domain(domain, mask) \
5170 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5171 if ((1 << (domain)) & (mask))
5172
5173 enum intel_display_power_domain
5174 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5175 {
5176 struct drm_device *dev = intel_encoder->base.dev;
5177 struct intel_digital_port *intel_dig_port;
5178
5179 switch (intel_encoder->type) {
5180 case INTEL_OUTPUT_UNKNOWN:
5181 /* Only DDI platforms should ever use this output type */
5182 WARN_ON_ONCE(!HAS_DDI(dev));
5183 case INTEL_OUTPUT_DISPLAYPORT:
5184 case INTEL_OUTPUT_HDMI:
5185 case INTEL_OUTPUT_EDP:
5186 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5187 return port_to_power_domain(intel_dig_port->port);
5188 case INTEL_OUTPUT_DP_MST:
5189 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5190 return port_to_power_domain(intel_dig_port->port);
5191 case INTEL_OUTPUT_ANALOG:
5192 return POWER_DOMAIN_PORT_CRT;
5193 case INTEL_OUTPUT_DSI:
5194 return POWER_DOMAIN_PORT_DSI;
5195 default:
5196 return POWER_DOMAIN_PORT_OTHER;
5197 }
5198 }
5199
5200 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5201 {
5202 struct drm_device *dev = crtc->dev;
5203 struct intel_encoder *intel_encoder;
5204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5205 enum pipe pipe = intel_crtc->pipe;
5206 unsigned long mask;
5207 enum transcoder transcoder;
5208
5209 if (!crtc->state->active)
5210 return 0;
5211
5212 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5213
5214 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5215 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5216 if (intel_crtc->config->pch_pfit.enabled ||
5217 intel_crtc->config->pch_pfit.force_thru)
5218 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5219
5220 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5221 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5222
5223 return mask;
5224 }
5225
5226 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5227 {
5228 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5230 enum intel_display_power_domain domain;
5231 unsigned long domains, new_domains, old_domains;
5232
5233 old_domains = intel_crtc->enabled_power_domains;
5234 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5235
5236 domains = new_domains & ~old_domains;
5237
5238 for_each_power_domain(domain, domains)
5239 intel_display_power_get(dev_priv, domain);
5240
5241 return old_domains & ~new_domains;
5242 }
5243
5244 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5245 unsigned long domains)
5246 {
5247 enum intel_display_power_domain domain;
5248
5249 for_each_power_domain(domain, domains)
5250 intel_display_power_put(dev_priv, domain);
5251 }
5252
5253 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5254 {
5255 struct drm_device *dev = state->dev;
5256 struct drm_i915_private *dev_priv = dev->dev_private;
5257 unsigned long put_domains[I915_MAX_PIPES] = {};
5258 struct drm_crtc_state *crtc_state;
5259 struct drm_crtc *crtc;
5260 int i;
5261
5262 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5263 if (needs_modeset(crtc->state))
5264 put_domains[to_intel_crtc(crtc)->pipe] =
5265 modeset_get_crtc_power_domains(crtc);
5266 }
5267
5268 if (dev_priv->display.modeset_commit_cdclk) {
5269 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5270
5271 if (cdclk != dev_priv->cdclk_freq &&
5272 !WARN_ON(!state->allow_modeset))
5273 dev_priv->display.modeset_commit_cdclk(state);
5274 }
5275
5276 for (i = 0; i < I915_MAX_PIPES; i++)
5277 if (put_domains[i])
5278 modeset_put_power_domains(dev_priv, put_domains[i]);
5279 }
5280
5281 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5282 {
5283 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5284
5285 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5286 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5287 return max_cdclk_freq;
5288 else if (IS_CHERRYVIEW(dev_priv))
5289 return max_cdclk_freq*95/100;
5290 else if (INTEL_INFO(dev_priv)->gen < 4)
5291 return 2*max_cdclk_freq*90/100;
5292 else
5293 return max_cdclk_freq*90/100;
5294 }
5295
5296 static void intel_update_max_cdclk(struct drm_device *dev)
5297 {
5298 struct drm_i915_private *dev_priv = dev->dev_private;
5299
5300 if (IS_SKYLAKE(dev)) {
5301 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5302
5303 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5304 dev_priv->max_cdclk_freq = 675000;
5305 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5306 dev_priv->max_cdclk_freq = 540000;
5307 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5308 dev_priv->max_cdclk_freq = 450000;
5309 else
5310 dev_priv->max_cdclk_freq = 337500;
5311 } else if (IS_BROADWELL(dev)) {
5312 /*
5313 * FIXME with extra cooling we can allow
5314 * 540 MHz for ULX and 675 Mhz for ULT.
5315 * How can we know if extra cooling is
5316 * available? PCI ID, VTB, something else?
5317 */
5318 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5319 dev_priv->max_cdclk_freq = 450000;
5320 else if (IS_BDW_ULX(dev))
5321 dev_priv->max_cdclk_freq = 450000;
5322 else if (IS_BDW_ULT(dev))
5323 dev_priv->max_cdclk_freq = 540000;
5324 else
5325 dev_priv->max_cdclk_freq = 675000;
5326 } else if (IS_CHERRYVIEW(dev)) {
5327 dev_priv->max_cdclk_freq = 320000;
5328 } else if (IS_VALLEYVIEW(dev)) {
5329 dev_priv->max_cdclk_freq = 400000;
5330 } else {
5331 /* otherwise assume cdclk is fixed */
5332 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5333 }
5334
5335 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5336
5337 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5338 dev_priv->max_cdclk_freq);
5339
5340 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5341 dev_priv->max_dotclk_freq);
5342 }
5343
5344 static void intel_update_cdclk(struct drm_device *dev)
5345 {
5346 struct drm_i915_private *dev_priv = dev->dev_private;
5347
5348 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5349 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5350 dev_priv->cdclk_freq);
5351
5352 /*
5353 * Program the gmbus_freq based on the cdclk frequency.
5354 * BSpec erroneously claims we should aim for 4MHz, but
5355 * in fact 1MHz is the correct frequency.
5356 */
5357 if (IS_VALLEYVIEW(dev)) {
5358 /*
5359 * Program the gmbus_freq based on the cdclk frequency.
5360 * BSpec erroneously claims we should aim for 4MHz, but
5361 * in fact 1MHz is the correct frequency.
5362 */
5363 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5364 }
5365
5366 if (dev_priv->max_cdclk_freq == 0)
5367 intel_update_max_cdclk(dev);
5368 }
5369
5370 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5371 {
5372 struct drm_i915_private *dev_priv = dev->dev_private;
5373 uint32_t divider;
5374 uint32_t ratio;
5375 uint32_t current_freq;
5376 int ret;
5377
5378 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5379 switch (frequency) {
5380 case 144000:
5381 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5382 ratio = BXT_DE_PLL_RATIO(60);
5383 break;
5384 case 288000:
5385 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5386 ratio = BXT_DE_PLL_RATIO(60);
5387 break;
5388 case 384000:
5389 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5390 ratio = BXT_DE_PLL_RATIO(60);
5391 break;
5392 case 576000:
5393 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5394 ratio = BXT_DE_PLL_RATIO(60);
5395 break;
5396 case 624000:
5397 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5398 ratio = BXT_DE_PLL_RATIO(65);
5399 break;
5400 case 19200:
5401 /*
5402 * Bypass frequency with DE PLL disabled. Init ratio, divider
5403 * to suppress GCC warning.
5404 */
5405 ratio = 0;
5406 divider = 0;
5407 break;
5408 default:
5409 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5410
5411 return;
5412 }
5413
5414 mutex_lock(&dev_priv->rps.hw_lock);
5415 /* Inform power controller of upcoming frequency change */
5416 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5417 0x80000000);
5418 mutex_unlock(&dev_priv->rps.hw_lock);
5419
5420 if (ret) {
5421 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5422 ret, frequency);
5423 return;
5424 }
5425
5426 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5427 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5428 current_freq = current_freq * 500 + 1000;
5429
5430 /*
5431 * DE PLL has to be disabled when
5432 * - setting to 19.2MHz (bypass, PLL isn't used)
5433 * - before setting to 624MHz (PLL needs toggling)
5434 * - before setting to any frequency from 624MHz (PLL needs toggling)
5435 */
5436 if (frequency == 19200 || frequency == 624000 ||
5437 current_freq == 624000) {
5438 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5439 /* Timeout 200us */
5440 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5441 1))
5442 DRM_ERROR("timout waiting for DE PLL unlock\n");
5443 }
5444
5445 if (frequency != 19200) {
5446 uint32_t val;
5447
5448 val = I915_READ(BXT_DE_PLL_CTL);
5449 val &= ~BXT_DE_PLL_RATIO_MASK;
5450 val |= ratio;
5451 I915_WRITE(BXT_DE_PLL_CTL, val);
5452
5453 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5454 /* Timeout 200us */
5455 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5456 DRM_ERROR("timeout waiting for DE PLL lock\n");
5457
5458 val = I915_READ(CDCLK_CTL);
5459 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5460 val |= divider;
5461 /*
5462 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5463 * enable otherwise.
5464 */
5465 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5466 if (frequency >= 500000)
5467 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5468
5469 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5470 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5471 val |= (frequency - 1000) / 500;
5472 I915_WRITE(CDCLK_CTL, val);
5473 }
5474
5475 mutex_lock(&dev_priv->rps.hw_lock);
5476 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5477 DIV_ROUND_UP(frequency, 25000));
5478 mutex_unlock(&dev_priv->rps.hw_lock);
5479
5480 if (ret) {
5481 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5482 ret, frequency);
5483 return;
5484 }
5485
5486 intel_update_cdclk(dev);
5487 }
5488
5489 void broxton_init_cdclk(struct drm_device *dev)
5490 {
5491 struct drm_i915_private *dev_priv = dev->dev_private;
5492 uint32_t val;
5493
5494 /*
5495 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5496 * or else the reset will hang because there is no PCH to respond.
5497 * Move the handshake programming to initialization sequence.
5498 * Previously was left up to BIOS.
5499 */
5500 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5501 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5502 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5503
5504 /* Enable PG1 for cdclk */
5505 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5506
5507 /* check if cd clock is enabled */
5508 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5509 DRM_DEBUG_KMS("Display already initialized\n");
5510 return;
5511 }
5512
5513 /*
5514 * FIXME:
5515 * - The initial CDCLK needs to be read from VBT.
5516 * Need to make this change after VBT has changes for BXT.
5517 * - check if setting the max (or any) cdclk freq is really necessary
5518 * here, it belongs to modeset time
5519 */
5520 broxton_set_cdclk(dev, 624000);
5521
5522 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5523 POSTING_READ(DBUF_CTL);
5524
5525 udelay(10);
5526
5527 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5528 DRM_ERROR("DBuf power enable timeout!\n");
5529 }
5530
5531 void broxton_uninit_cdclk(struct drm_device *dev)
5532 {
5533 struct drm_i915_private *dev_priv = dev->dev_private;
5534
5535 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5536 POSTING_READ(DBUF_CTL);
5537
5538 udelay(10);
5539
5540 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5541 DRM_ERROR("DBuf power disable timeout!\n");
5542
5543 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5544 broxton_set_cdclk(dev, 19200);
5545
5546 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5547 }
5548
5549 static const struct skl_cdclk_entry {
5550 unsigned int freq;
5551 unsigned int vco;
5552 } skl_cdclk_frequencies[] = {
5553 { .freq = 308570, .vco = 8640 },
5554 { .freq = 337500, .vco = 8100 },
5555 { .freq = 432000, .vco = 8640 },
5556 { .freq = 450000, .vco = 8100 },
5557 { .freq = 540000, .vco = 8100 },
5558 { .freq = 617140, .vco = 8640 },
5559 { .freq = 675000, .vco = 8100 },
5560 };
5561
5562 static unsigned int skl_cdclk_decimal(unsigned int freq)
5563 {
5564 return (freq - 1000) / 500;
5565 }
5566
5567 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5568 {
5569 unsigned int i;
5570
5571 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5572 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5573
5574 if (e->freq == freq)
5575 return e->vco;
5576 }
5577
5578 return 8100;
5579 }
5580
5581 static void
5582 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5583 {
5584 unsigned int min_freq;
5585 u32 val;
5586
5587 /* select the minimum CDCLK before enabling DPLL 0 */
5588 val = I915_READ(CDCLK_CTL);
5589 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5590 val |= CDCLK_FREQ_337_308;
5591
5592 if (required_vco == 8640)
5593 min_freq = 308570;
5594 else
5595 min_freq = 337500;
5596
5597 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5598
5599 I915_WRITE(CDCLK_CTL, val);
5600 POSTING_READ(CDCLK_CTL);
5601
5602 /*
5603 * We always enable DPLL0 with the lowest link rate possible, but still
5604 * taking into account the VCO required to operate the eDP panel at the
5605 * desired frequency. The usual DP link rates operate with a VCO of
5606 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5607 * The modeset code is responsible for the selection of the exact link
5608 * rate later on, with the constraint of choosing a frequency that
5609 * works with required_vco.
5610 */
5611 val = I915_READ(DPLL_CTRL1);
5612
5613 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5614 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5615 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5616 if (required_vco == 8640)
5617 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5618 SKL_DPLL0);
5619 else
5620 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5621 SKL_DPLL0);
5622
5623 I915_WRITE(DPLL_CTRL1, val);
5624 POSTING_READ(DPLL_CTRL1);
5625
5626 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5627
5628 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5629 DRM_ERROR("DPLL0 not locked\n");
5630 }
5631
5632 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5633 {
5634 int ret;
5635 u32 val;
5636
5637 /* inform PCU we want to change CDCLK */
5638 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5639 mutex_lock(&dev_priv->rps.hw_lock);
5640 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5641 mutex_unlock(&dev_priv->rps.hw_lock);
5642
5643 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5644 }
5645
5646 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5647 {
5648 unsigned int i;
5649
5650 for (i = 0; i < 15; i++) {
5651 if (skl_cdclk_pcu_ready(dev_priv))
5652 return true;
5653 udelay(10);
5654 }
5655
5656 return false;
5657 }
5658
5659 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5660 {
5661 struct drm_device *dev = dev_priv->dev;
5662 u32 freq_select, pcu_ack;
5663
5664 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5665
5666 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5667 DRM_ERROR("failed to inform PCU about cdclk change\n");
5668 return;
5669 }
5670
5671 /* set CDCLK_CTL */
5672 switch(freq) {
5673 case 450000:
5674 case 432000:
5675 freq_select = CDCLK_FREQ_450_432;
5676 pcu_ack = 1;
5677 break;
5678 case 540000:
5679 freq_select = CDCLK_FREQ_540;
5680 pcu_ack = 2;
5681 break;
5682 case 308570:
5683 case 337500:
5684 default:
5685 freq_select = CDCLK_FREQ_337_308;
5686 pcu_ack = 0;
5687 break;
5688 case 617140:
5689 case 675000:
5690 freq_select = CDCLK_FREQ_675_617;
5691 pcu_ack = 3;
5692 break;
5693 }
5694
5695 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5696 POSTING_READ(CDCLK_CTL);
5697
5698 /* inform PCU of the change */
5699 mutex_lock(&dev_priv->rps.hw_lock);
5700 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5701 mutex_unlock(&dev_priv->rps.hw_lock);
5702
5703 intel_update_cdclk(dev);
5704 }
5705
5706 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5707 {
5708 /* disable DBUF power */
5709 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5710 POSTING_READ(DBUF_CTL);
5711
5712 udelay(10);
5713
5714 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5715 DRM_ERROR("DBuf power disable timeout\n");
5716
5717 /*
5718 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5719 */
5720 if (dev_priv->csr.dmc_payload) {
5721 /* disable DPLL0 */
5722 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5723 ~LCPLL_PLL_ENABLE);
5724 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5725 DRM_ERROR("Couldn't disable DPLL0\n");
5726 }
5727
5728 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5729 }
5730
5731 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5732 {
5733 u32 val;
5734 unsigned int required_vco;
5735
5736 /* enable PCH reset handshake */
5737 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5738 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5739
5740 /* enable PG1 and Misc I/O */
5741 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5742
5743 /* DPLL0 not enabled (happens on early BIOS versions) */
5744 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5745 /* enable DPLL0 */
5746 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5747 skl_dpll0_enable(dev_priv, required_vco);
5748 }
5749
5750 /* set CDCLK to the frequency the BIOS chose */
5751 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5752
5753 /* enable DBUF power */
5754 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5755 POSTING_READ(DBUF_CTL);
5756
5757 udelay(10);
5758
5759 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5760 DRM_ERROR("DBuf power enable timeout\n");
5761 }
5762
5763 /* Adjust CDclk dividers to allow high res or save power if possible */
5764 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5765 {
5766 struct drm_i915_private *dev_priv = dev->dev_private;
5767 u32 val, cmd;
5768
5769 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5770 != dev_priv->cdclk_freq);
5771
5772 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5773 cmd = 2;
5774 else if (cdclk == 266667)
5775 cmd = 1;
5776 else
5777 cmd = 0;
5778
5779 mutex_lock(&dev_priv->rps.hw_lock);
5780 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5781 val &= ~DSPFREQGUAR_MASK;
5782 val |= (cmd << DSPFREQGUAR_SHIFT);
5783 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5784 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5785 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5786 50)) {
5787 DRM_ERROR("timed out waiting for CDclk change\n");
5788 }
5789 mutex_unlock(&dev_priv->rps.hw_lock);
5790
5791 mutex_lock(&dev_priv->sb_lock);
5792
5793 if (cdclk == 400000) {
5794 u32 divider;
5795
5796 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5797
5798 /* adjust cdclk divider */
5799 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5800 val &= ~CCK_FREQUENCY_VALUES;
5801 val |= divider;
5802 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5803
5804 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5805 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5806 50))
5807 DRM_ERROR("timed out waiting for CDclk change\n");
5808 }
5809
5810 /* adjust self-refresh exit latency value */
5811 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5812 val &= ~0x7f;
5813
5814 /*
5815 * For high bandwidth configs, we set a higher latency in the bunit
5816 * so that the core display fetch happens in time to avoid underruns.
5817 */
5818 if (cdclk == 400000)
5819 val |= 4500 / 250; /* 4.5 usec */
5820 else
5821 val |= 3000 / 250; /* 3.0 usec */
5822 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5823
5824 mutex_unlock(&dev_priv->sb_lock);
5825
5826 intel_update_cdclk(dev);
5827 }
5828
5829 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5830 {
5831 struct drm_i915_private *dev_priv = dev->dev_private;
5832 u32 val, cmd;
5833
5834 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5835 != dev_priv->cdclk_freq);
5836
5837 switch (cdclk) {
5838 case 333333:
5839 case 320000:
5840 case 266667:
5841 case 200000:
5842 break;
5843 default:
5844 MISSING_CASE(cdclk);
5845 return;
5846 }
5847
5848 /*
5849 * Specs are full of misinformation, but testing on actual
5850 * hardware has shown that we just need to write the desired
5851 * CCK divider into the Punit register.
5852 */
5853 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5854
5855 mutex_lock(&dev_priv->rps.hw_lock);
5856 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5857 val &= ~DSPFREQGUAR_MASK_CHV;
5858 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5859 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5860 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5861 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5862 50)) {
5863 DRM_ERROR("timed out waiting for CDclk change\n");
5864 }
5865 mutex_unlock(&dev_priv->rps.hw_lock);
5866
5867 intel_update_cdclk(dev);
5868 }
5869
5870 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5871 int max_pixclk)
5872 {
5873 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5874 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5875
5876 /*
5877 * Really only a few cases to deal with, as only 4 CDclks are supported:
5878 * 200MHz
5879 * 267MHz
5880 * 320/333MHz (depends on HPLL freq)
5881 * 400MHz (VLV only)
5882 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5883 * of the lower bin and adjust if needed.
5884 *
5885 * We seem to get an unstable or solid color picture at 200MHz.
5886 * Not sure what's wrong. For now use 200MHz only when all pipes
5887 * are off.
5888 */
5889 if (!IS_CHERRYVIEW(dev_priv) &&
5890 max_pixclk > freq_320*limit/100)
5891 return 400000;
5892 else if (max_pixclk > 266667*limit/100)
5893 return freq_320;
5894 else if (max_pixclk > 0)
5895 return 266667;
5896 else
5897 return 200000;
5898 }
5899
5900 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5901 int max_pixclk)
5902 {
5903 /*
5904 * FIXME:
5905 * - remove the guardband, it's not needed on BXT
5906 * - set 19.2MHz bypass frequency if there are no active pipes
5907 */
5908 if (max_pixclk > 576000*9/10)
5909 return 624000;
5910 else if (max_pixclk > 384000*9/10)
5911 return 576000;
5912 else if (max_pixclk > 288000*9/10)
5913 return 384000;
5914 else if (max_pixclk > 144000*9/10)
5915 return 288000;
5916 else
5917 return 144000;
5918 }
5919
5920 /* Compute the max pixel clock for new configuration. Uses atomic state if
5921 * that's non-NULL, look at current state otherwise. */
5922 static int intel_mode_max_pixclk(struct drm_device *dev,
5923 struct drm_atomic_state *state)
5924 {
5925 struct intel_crtc *intel_crtc;
5926 struct intel_crtc_state *crtc_state;
5927 int max_pixclk = 0;
5928
5929 for_each_intel_crtc(dev, intel_crtc) {
5930 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5931 if (IS_ERR(crtc_state))
5932 return PTR_ERR(crtc_state);
5933
5934 if (!crtc_state->base.enable)
5935 continue;
5936
5937 max_pixclk = max(max_pixclk,
5938 crtc_state->base.adjusted_mode.crtc_clock);
5939 }
5940
5941 return max_pixclk;
5942 }
5943
5944 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5945 {
5946 struct drm_device *dev = state->dev;
5947 struct drm_i915_private *dev_priv = dev->dev_private;
5948 int max_pixclk = intel_mode_max_pixclk(dev, state);
5949
5950 if (max_pixclk < 0)
5951 return max_pixclk;
5952
5953 to_intel_atomic_state(state)->cdclk =
5954 valleyview_calc_cdclk(dev_priv, max_pixclk);
5955
5956 return 0;
5957 }
5958
5959 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5960 {
5961 struct drm_device *dev = state->dev;
5962 struct drm_i915_private *dev_priv = dev->dev_private;
5963 int max_pixclk = intel_mode_max_pixclk(dev, state);
5964
5965 if (max_pixclk < 0)
5966 return max_pixclk;
5967
5968 to_intel_atomic_state(state)->cdclk =
5969 broxton_calc_cdclk(dev_priv, max_pixclk);
5970
5971 return 0;
5972 }
5973
5974 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5975 {
5976 unsigned int credits, default_credits;
5977
5978 if (IS_CHERRYVIEW(dev_priv))
5979 default_credits = PFI_CREDIT(12);
5980 else
5981 default_credits = PFI_CREDIT(8);
5982
5983 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5984 /* CHV suggested value is 31 or 63 */
5985 if (IS_CHERRYVIEW(dev_priv))
5986 credits = PFI_CREDIT_63;
5987 else
5988 credits = PFI_CREDIT(15);
5989 } else {
5990 credits = default_credits;
5991 }
5992
5993 /*
5994 * WA - write default credits before re-programming
5995 * FIXME: should we also set the resend bit here?
5996 */
5997 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5998 default_credits);
5999
6000 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6001 credits | PFI_CREDIT_RESEND);
6002
6003 /*
6004 * FIXME is this guaranteed to clear
6005 * immediately or should we poll for it?
6006 */
6007 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6008 }
6009
6010 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6011 {
6012 struct drm_device *dev = old_state->dev;
6013 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6014 struct drm_i915_private *dev_priv = dev->dev_private;
6015
6016 /*
6017 * FIXME: We can end up here with all power domains off, yet
6018 * with a CDCLK frequency other than the minimum. To account
6019 * for this take the PIPE-A power domain, which covers the HW
6020 * blocks needed for the following programming. This can be
6021 * removed once it's guaranteed that we get here either with
6022 * the minimum CDCLK set, or the required power domains
6023 * enabled.
6024 */
6025 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6026
6027 if (IS_CHERRYVIEW(dev))
6028 cherryview_set_cdclk(dev, req_cdclk);
6029 else
6030 valleyview_set_cdclk(dev, req_cdclk);
6031
6032 vlv_program_pfi_credits(dev_priv);
6033
6034 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6035 }
6036
6037 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6038 {
6039 struct drm_device *dev = crtc->dev;
6040 struct drm_i915_private *dev_priv = to_i915(dev);
6041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6042 struct intel_encoder *encoder;
6043 int pipe = intel_crtc->pipe;
6044 bool is_dsi;
6045
6046 if (WARN_ON(intel_crtc->active))
6047 return;
6048
6049 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6050
6051 if (intel_crtc->config->has_dp_encoder)
6052 intel_dp_set_m_n(intel_crtc, M1_N1);
6053
6054 intel_set_pipe_timings(intel_crtc);
6055
6056 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058
6059 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6060 I915_WRITE(CHV_CANVAS(pipe), 0);
6061 }
6062
6063 i9xx_set_pipeconf(intel_crtc);
6064
6065 intel_crtc->active = true;
6066
6067 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6068
6069 for_each_encoder_on_crtc(dev, crtc, encoder)
6070 if (encoder->pre_pll_enable)
6071 encoder->pre_pll_enable(encoder);
6072
6073 if (!is_dsi) {
6074 if (IS_CHERRYVIEW(dev)) {
6075 chv_prepare_pll(intel_crtc, intel_crtc->config);
6076 chv_enable_pll(intel_crtc, intel_crtc->config);
6077 } else {
6078 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6079 vlv_enable_pll(intel_crtc, intel_crtc->config);
6080 }
6081 }
6082
6083 for_each_encoder_on_crtc(dev, crtc, encoder)
6084 if (encoder->pre_enable)
6085 encoder->pre_enable(encoder);
6086
6087 i9xx_pfit_enable(intel_crtc);
6088
6089 intel_crtc_load_lut(crtc);
6090
6091 intel_enable_pipe(intel_crtc);
6092
6093 assert_vblank_disabled(crtc);
6094 drm_crtc_vblank_on(crtc);
6095
6096 for_each_encoder_on_crtc(dev, crtc, encoder)
6097 encoder->enable(encoder);
6098 }
6099
6100 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6101 {
6102 struct drm_device *dev = crtc->base.dev;
6103 struct drm_i915_private *dev_priv = dev->dev_private;
6104
6105 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6106 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6107 }
6108
6109 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6110 {
6111 struct drm_device *dev = crtc->dev;
6112 struct drm_i915_private *dev_priv = to_i915(dev);
6113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6114 struct intel_encoder *encoder;
6115 int pipe = intel_crtc->pipe;
6116
6117 if (WARN_ON(intel_crtc->active))
6118 return;
6119
6120 i9xx_set_pll_dividers(intel_crtc);
6121
6122 if (intel_crtc->config->has_dp_encoder)
6123 intel_dp_set_m_n(intel_crtc, M1_N1);
6124
6125 intel_set_pipe_timings(intel_crtc);
6126
6127 i9xx_set_pipeconf(intel_crtc);
6128
6129 intel_crtc->active = true;
6130
6131 if (!IS_GEN2(dev))
6132 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6133
6134 for_each_encoder_on_crtc(dev, crtc, encoder)
6135 if (encoder->pre_enable)
6136 encoder->pre_enable(encoder);
6137
6138 i9xx_enable_pll(intel_crtc);
6139
6140 i9xx_pfit_enable(intel_crtc);
6141
6142 intel_crtc_load_lut(crtc);
6143
6144 intel_update_watermarks(crtc);
6145 intel_enable_pipe(intel_crtc);
6146
6147 assert_vblank_disabled(crtc);
6148 drm_crtc_vblank_on(crtc);
6149
6150 for_each_encoder_on_crtc(dev, crtc, encoder)
6151 encoder->enable(encoder);
6152 }
6153
6154 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6155 {
6156 struct drm_device *dev = crtc->base.dev;
6157 struct drm_i915_private *dev_priv = dev->dev_private;
6158
6159 if (!crtc->config->gmch_pfit.control)
6160 return;
6161
6162 assert_pipe_disabled(dev_priv, crtc->pipe);
6163
6164 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6165 I915_READ(PFIT_CONTROL));
6166 I915_WRITE(PFIT_CONTROL, 0);
6167 }
6168
6169 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6170 {
6171 struct drm_device *dev = crtc->dev;
6172 struct drm_i915_private *dev_priv = dev->dev_private;
6173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6174 struct intel_encoder *encoder;
6175 int pipe = intel_crtc->pipe;
6176
6177 /*
6178 * On gen2 planes are double buffered but the pipe isn't, so we must
6179 * wait for planes to fully turn off before disabling the pipe.
6180 * We also need to wait on all gmch platforms because of the
6181 * self-refresh mode constraint explained above.
6182 */
6183 intel_wait_for_vblank(dev, pipe);
6184
6185 for_each_encoder_on_crtc(dev, crtc, encoder)
6186 encoder->disable(encoder);
6187
6188 drm_crtc_vblank_off(crtc);
6189 assert_vblank_disabled(crtc);
6190
6191 intel_disable_pipe(intel_crtc);
6192
6193 i9xx_pfit_disable(intel_crtc);
6194
6195 for_each_encoder_on_crtc(dev, crtc, encoder)
6196 if (encoder->post_disable)
6197 encoder->post_disable(encoder);
6198
6199 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6200 if (IS_CHERRYVIEW(dev))
6201 chv_disable_pll(dev_priv, pipe);
6202 else if (IS_VALLEYVIEW(dev))
6203 vlv_disable_pll(dev_priv, pipe);
6204 else
6205 i9xx_disable_pll(intel_crtc);
6206 }
6207
6208 for_each_encoder_on_crtc(dev, crtc, encoder)
6209 if (encoder->post_pll_disable)
6210 encoder->post_pll_disable(encoder);
6211
6212 if (!IS_GEN2(dev))
6213 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6214 }
6215
6216 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6217 {
6218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6219 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6220 enum intel_display_power_domain domain;
6221 unsigned long domains;
6222
6223 if (!intel_crtc->active)
6224 return;
6225
6226 if (to_intel_plane_state(crtc->primary->state)->visible) {
6227 intel_crtc_wait_for_pending_flips(crtc);
6228 intel_pre_disable_primary(crtc);
6229 }
6230
6231 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6232 dev_priv->display.crtc_disable(crtc);
6233 intel_crtc->active = false;
6234 intel_update_watermarks(crtc);
6235 intel_disable_shared_dpll(intel_crtc);
6236
6237 domains = intel_crtc->enabled_power_domains;
6238 for_each_power_domain(domain, domains)
6239 intel_display_power_put(dev_priv, domain);
6240 intel_crtc->enabled_power_domains = 0;
6241 }
6242
6243 /*
6244 * turn all crtc's off, but do not adjust state
6245 * This has to be paired with a call to intel_modeset_setup_hw_state.
6246 */
6247 int intel_display_suspend(struct drm_device *dev)
6248 {
6249 struct drm_mode_config *config = &dev->mode_config;
6250 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6251 struct drm_atomic_state *state;
6252 struct drm_crtc *crtc;
6253 unsigned crtc_mask = 0;
6254 int ret = 0;
6255
6256 if (WARN_ON(!ctx))
6257 return 0;
6258
6259 lockdep_assert_held(&ctx->ww_ctx);
6260 state = drm_atomic_state_alloc(dev);
6261 if (WARN_ON(!state))
6262 return -ENOMEM;
6263
6264 state->acquire_ctx = ctx;
6265 state->allow_modeset = true;
6266
6267 for_each_crtc(dev, crtc) {
6268 struct drm_crtc_state *crtc_state =
6269 drm_atomic_get_crtc_state(state, crtc);
6270
6271 ret = PTR_ERR_OR_ZERO(crtc_state);
6272 if (ret)
6273 goto free;
6274
6275 if (!crtc_state->active)
6276 continue;
6277
6278 crtc_state->active = false;
6279 crtc_mask |= 1 << drm_crtc_index(crtc);
6280 }
6281
6282 if (crtc_mask) {
6283 ret = drm_atomic_commit(state);
6284
6285 if (!ret) {
6286 for_each_crtc(dev, crtc)
6287 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6288 crtc->state->active = true;
6289
6290 return ret;
6291 }
6292 }
6293
6294 free:
6295 if (ret)
6296 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6297 drm_atomic_state_free(state);
6298 return ret;
6299 }
6300
6301 void intel_encoder_destroy(struct drm_encoder *encoder)
6302 {
6303 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6304
6305 drm_encoder_cleanup(encoder);
6306 kfree(intel_encoder);
6307 }
6308
6309 /* Cross check the actual hw state with our own modeset state tracking (and it's
6310 * internal consistency). */
6311 static void intel_connector_check_state(struct intel_connector *connector)
6312 {
6313 struct drm_crtc *crtc = connector->base.state->crtc;
6314
6315 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6316 connector->base.base.id,
6317 connector->base.name);
6318
6319 if (connector->get_hw_state(connector)) {
6320 struct intel_encoder *encoder = connector->encoder;
6321 struct drm_connector_state *conn_state = connector->base.state;
6322
6323 I915_STATE_WARN(!crtc,
6324 "connector enabled without attached crtc\n");
6325
6326 if (!crtc)
6327 return;
6328
6329 I915_STATE_WARN(!crtc->state->active,
6330 "connector is active, but attached crtc isn't\n");
6331
6332 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6333 return;
6334
6335 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6336 "atomic encoder doesn't match attached encoder\n");
6337
6338 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6339 "attached encoder crtc differs from connector crtc\n");
6340 } else {
6341 I915_STATE_WARN(crtc && crtc->state->active,
6342 "attached crtc is active, but connector isn't\n");
6343 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6344 "best encoder set without crtc!\n");
6345 }
6346 }
6347
6348 int intel_connector_init(struct intel_connector *connector)
6349 {
6350 struct drm_connector_state *connector_state;
6351
6352 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6353 if (!connector_state)
6354 return -ENOMEM;
6355
6356 connector->base.state = connector_state;
6357 return 0;
6358 }
6359
6360 struct intel_connector *intel_connector_alloc(void)
6361 {
6362 struct intel_connector *connector;
6363
6364 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6365 if (!connector)
6366 return NULL;
6367
6368 if (intel_connector_init(connector) < 0) {
6369 kfree(connector);
6370 return NULL;
6371 }
6372
6373 return connector;
6374 }
6375
6376 /* Simple connector->get_hw_state implementation for encoders that support only
6377 * one connector and no cloning and hence the encoder state determines the state
6378 * of the connector. */
6379 bool intel_connector_get_hw_state(struct intel_connector *connector)
6380 {
6381 enum pipe pipe = 0;
6382 struct intel_encoder *encoder = connector->encoder;
6383
6384 return encoder->get_hw_state(encoder, &pipe);
6385 }
6386
6387 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6388 {
6389 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6390 return crtc_state->fdi_lanes;
6391
6392 return 0;
6393 }
6394
6395 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6396 struct intel_crtc_state *pipe_config)
6397 {
6398 struct drm_atomic_state *state = pipe_config->base.state;
6399 struct intel_crtc *other_crtc;
6400 struct intel_crtc_state *other_crtc_state;
6401
6402 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6403 pipe_name(pipe), pipe_config->fdi_lanes);
6404 if (pipe_config->fdi_lanes > 4) {
6405 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6406 pipe_name(pipe), pipe_config->fdi_lanes);
6407 return -EINVAL;
6408 }
6409
6410 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6411 if (pipe_config->fdi_lanes > 2) {
6412 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6413 pipe_config->fdi_lanes);
6414 return -EINVAL;
6415 } else {
6416 return 0;
6417 }
6418 }
6419
6420 if (INTEL_INFO(dev)->num_pipes == 2)
6421 return 0;
6422
6423 /* Ivybridge 3 pipe is really complicated */
6424 switch (pipe) {
6425 case PIPE_A:
6426 return 0;
6427 case PIPE_B:
6428 if (pipe_config->fdi_lanes <= 2)
6429 return 0;
6430
6431 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6432 other_crtc_state =
6433 intel_atomic_get_crtc_state(state, other_crtc);
6434 if (IS_ERR(other_crtc_state))
6435 return PTR_ERR(other_crtc_state);
6436
6437 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6438 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6439 pipe_name(pipe), pipe_config->fdi_lanes);
6440 return -EINVAL;
6441 }
6442 return 0;
6443 case PIPE_C:
6444 if (pipe_config->fdi_lanes > 2) {
6445 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6446 pipe_name(pipe), pipe_config->fdi_lanes);
6447 return -EINVAL;
6448 }
6449
6450 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6451 other_crtc_state =
6452 intel_atomic_get_crtc_state(state, other_crtc);
6453 if (IS_ERR(other_crtc_state))
6454 return PTR_ERR(other_crtc_state);
6455
6456 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6457 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6458 return -EINVAL;
6459 }
6460 return 0;
6461 default:
6462 BUG();
6463 }
6464 }
6465
6466 #define RETRY 1
6467 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6468 struct intel_crtc_state *pipe_config)
6469 {
6470 struct drm_device *dev = intel_crtc->base.dev;
6471 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6472 int lane, link_bw, fdi_dotclock, ret;
6473 bool needs_recompute = false;
6474
6475 retry:
6476 /* FDI is a binary signal running at ~2.7GHz, encoding
6477 * each output octet as 10 bits. The actual frequency
6478 * is stored as a divider into a 100MHz clock, and the
6479 * mode pixel clock is stored in units of 1KHz.
6480 * Hence the bw of each lane in terms of the mode signal
6481 * is:
6482 */
6483 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6484
6485 fdi_dotclock = adjusted_mode->crtc_clock;
6486
6487 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6488 pipe_config->pipe_bpp);
6489
6490 pipe_config->fdi_lanes = lane;
6491
6492 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6493 link_bw, &pipe_config->fdi_m_n);
6494
6495 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6496 intel_crtc->pipe, pipe_config);
6497 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6498 pipe_config->pipe_bpp -= 2*3;
6499 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6500 pipe_config->pipe_bpp);
6501 needs_recompute = true;
6502 pipe_config->bw_constrained = true;
6503
6504 goto retry;
6505 }
6506
6507 if (needs_recompute)
6508 return RETRY;
6509
6510 return ret;
6511 }
6512
6513 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6514 struct intel_crtc_state *pipe_config)
6515 {
6516 if (pipe_config->pipe_bpp > 24)
6517 return false;
6518
6519 /* HSW can handle pixel rate up to cdclk? */
6520 if (IS_HASWELL(dev_priv->dev))
6521 return true;
6522
6523 /*
6524 * We compare against max which means we must take
6525 * the increased cdclk requirement into account when
6526 * calculating the new cdclk.
6527 *
6528 * Should measure whether using a lower cdclk w/o IPS
6529 */
6530 return ilk_pipe_pixel_rate(pipe_config) <=
6531 dev_priv->max_cdclk_freq * 95 / 100;
6532 }
6533
6534 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6535 struct intel_crtc_state *pipe_config)
6536 {
6537 struct drm_device *dev = crtc->base.dev;
6538 struct drm_i915_private *dev_priv = dev->dev_private;
6539
6540 pipe_config->ips_enabled = i915.enable_ips &&
6541 hsw_crtc_supports_ips(crtc) &&
6542 pipe_config_supports_ips(dev_priv, pipe_config);
6543 }
6544
6545 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6546 struct intel_crtc_state *pipe_config)
6547 {
6548 struct drm_device *dev = crtc->base.dev;
6549 struct drm_i915_private *dev_priv = dev->dev_private;
6550 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6551
6552 /* FIXME should check pixel clock limits on all platforms */
6553 if (INTEL_INFO(dev)->gen < 4) {
6554 int clock_limit = dev_priv->max_cdclk_freq;
6555
6556 /*
6557 * Enable pixel doubling when the dot clock
6558 * is > 90% of the (display) core speed.
6559 *
6560 * GDG double wide on either pipe,
6561 * otherwise pipe A only.
6562 */
6563 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6564 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6565 clock_limit *= 2;
6566 pipe_config->double_wide = true;
6567 }
6568
6569 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6570 return -EINVAL;
6571 }
6572
6573 /*
6574 * Pipe horizontal size must be even in:
6575 * - DVO ganged mode
6576 * - LVDS dual channel mode
6577 * - Double wide pipe
6578 */
6579 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6580 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6581 pipe_config->pipe_src_w &= ~1;
6582
6583 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6584 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6585 */
6586 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6587 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6588 return -EINVAL;
6589
6590 if (HAS_IPS(dev))
6591 hsw_compute_ips_config(crtc, pipe_config);
6592
6593 if (pipe_config->has_pch_encoder)
6594 return ironlake_fdi_compute_config(crtc, pipe_config);
6595
6596 return 0;
6597 }
6598
6599 static int skylake_get_display_clock_speed(struct drm_device *dev)
6600 {
6601 struct drm_i915_private *dev_priv = to_i915(dev);
6602 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6603 uint32_t cdctl = I915_READ(CDCLK_CTL);
6604 uint32_t linkrate;
6605
6606 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6607 return 24000; /* 24MHz is the cd freq with NSSC ref */
6608
6609 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6610 return 540000;
6611
6612 linkrate = (I915_READ(DPLL_CTRL1) &
6613 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6614
6615 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6616 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6617 /* vco 8640 */
6618 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6619 case CDCLK_FREQ_450_432:
6620 return 432000;
6621 case CDCLK_FREQ_337_308:
6622 return 308570;
6623 case CDCLK_FREQ_675_617:
6624 return 617140;
6625 default:
6626 WARN(1, "Unknown cd freq selection\n");
6627 }
6628 } else {
6629 /* vco 8100 */
6630 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6631 case CDCLK_FREQ_450_432:
6632 return 450000;
6633 case CDCLK_FREQ_337_308:
6634 return 337500;
6635 case CDCLK_FREQ_675_617:
6636 return 675000;
6637 default:
6638 WARN(1, "Unknown cd freq selection\n");
6639 }
6640 }
6641
6642 /* error case, do as if DPLL0 isn't enabled */
6643 return 24000;
6644 }
6645
6646 static int broxton_get_display_clock_speed(struct drm_device *dev)
6647 {
6648 struct drm_i915_private *dev_priv = to_i915(dev);
6649 uint32_t cdctl = I915_READ(CDCLK_CTL);
6650 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6651 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6652 int cdclk;
6653
6654 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6655 return 19200;
6656
6657 cdclk = 19200 * pll_ratio / 2;
6658
6659 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6660 case BXT_CDCLK_CD2X_DIV_SEL_1:
6661 return cdclk; /* 576MHz or 624MHz */
6662 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6663 return cdclk * 2 / 3; /* 384MHz */
6664 case BXT_CDCLK_CD2X_DIV_SEL_2:
6665 return cdclk / 2; /* 288MHz */
6666 case BXT_CDCLK_CD2X_DIV_SEL_4:
6667 return cdclk / 4; /* 144MHz */
6668 }
6669
6670 /* error case, do as if DE PLL isn't enabled */
6671 return 19200;
6672 }
6673
6674 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6675 {
6676 struct drm_i915_private *dev_priv = dev->dev_private;
6677 uint32_t lcpll = I915_READ(LCPLL_CTL);
6678 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6679
6680 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6681 return 800000;
6682 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6683 return 450000;
6684 else if (freq == LCPLL_CLK_FREQ_450)
6685 return 450000;
6686 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6687 return 540000;
6688 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6689 return 337500;
6690 else
6691 return 675000;
6692 }
6693
6694 static int haswell_get_display_clock_speed(struct drm_device *dev)
6695 {
6696 struct drm_i915_private *dev_priv = dev->dev_private;
6697 uint32_t lcpll = I915_READ(LCPLL_CTL);
6698 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6699
6700 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6701 return 800000;
6702 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6703 return 450000;
6704 else if (freq == LCPLL_CLK_FREQ_450)
6705 return 450000;
6706 else if (IS_HSW_ULT(dev))
6707 return 337500;
6708 else
6709 return 540000;
6710 }
6711
6712 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6713 {
6714 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6715 CCK_DISPLAY_CLOCK_CONTROL);
6716 }
6717
6718 static int ilk_get_display_clock_speed(struct drm_device *dev)
6719 {
6720 return 450000;
6721 }
6722
6723 static int i945_get_display_clock_speed(struct drm_device *dev)
6724 {
6725 return 400000;
6726 }
6727
6728 static int i915_get_display_clock_speed(struct drm_device *dev)
6729 {
6730 return 333333;
6731 }
6732
6733 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6734 {
6735 return 200000;
6736 }
6737
6738 static int pnv_get_display_clock_speed(struct drm_device *dev)
6739 {
6740 u16 gcfgc = 0;
6741
6742 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6743
6744 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6745 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6746 return 266667;
6747 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6748 return 333333;
6749 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6750 return 444444;
6751 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6752 return 200000;
6753 default:
6754 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6755 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6756 return 133333;
6757 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6758 return 166667;
6759 }
6760 }
6761
6762 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6763 {
6764 u16 gcfgc = 0;
6765
6766 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6767
6768 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6769 return 133333;
6770 else {
6771 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6772 case GC_DISPLAY_CLOCK_333_MHZ:
6773 return 333333;
6774 default:
6775 case GC_DISPLAY_CLOCK_190_200_MHZ:
6776 return 190000;
6777 }
6778 }
6779 }
6780
6781 static int i865_get_display_clock_speed(struct drm_device *dev)
6782 {
6783 return 266667;
6784 }
6785
6786 static int i85x_get_display_clock_speed(struct drm_device *dev)
6787 {
6788 u16 hpllcc = 0;
6789
6790 /*
6791 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6792 * encoding is different :(
6793 * FIXME is this the right way to detect 852GM/852GMV?
6794 */
6795 if (dev->pdev->revision == 0x1)
6796 return 133333;
6797
6798 pci_bus_read_config_word(dev->pdev->bus,
6799 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6800
6801 /* Assume that the hardware is in the high speed state. This
6802 * should be the default.
6803 */
6804 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6805 case GC_CLOCK_133_200:
6806 case GC_CLOCK_133_200_2:
6807 case GC_CLOCK_100_200:
6808 return 200000;
6809 case GC_CLOCK_166_250:
6810 return 250000;
6811 case GC_CLOCK_100_133:
6812 return 133333;
6813 case GC_CLOCK_133_266:
6814 case GC_CLOCK_133_266_2:
6815 case GC_CLOCK_166_266:
6816 return 266667;
6817 }
6818
6819 /* Shouldn't happen */
6820 return 0;
6821 }
6822
6823 static int i830_get_display_clock_speed(struct drm_device *dev)
6824 {
6825 return 133333;
6826 }
6827
6828 static unsigned int intel_hpll_vco(struct drm_device *dev)
6829 {
6830 struct drm_i915_private *dev_priv = dev->dev_private;
6831 static const unsigned int blb_vco[8] = {
6832 [0] = 3200000,
6833 [1] = 4000000,
6834 [2] = 5333333,
6835 [3] = 4800000,
6836 [4] = 6400000,
6837 };
6838 static const unsigned int pnv_vco[8] = {
6839 [0] = 3200000,
6840 [1] = 4000000,
6841 [2] = 5333333,
6842 [3] = 4800000,
6843 [4] = 2666667,
6844 };
6845 static const unsigned int cl_vco[8] = {
6846 [0] = 3200000,
6847 [1] = 4000000,
6848 [2] = 5333333,
6849 [3] = 6400000,
6850 [4] = 3333333,
6851 [5] = 3566667,
6852 [6] = 4266667,
6853 };
6854 static const unsigned int elk_vco[8] = {
6855 [0] = 3200000,
6856 [1] = 4000000,
6857 [2] = 5333333,
6858 [3] = 4800000,
6859 };
6860 static const unsigned int ctg_vco[8] = {
6861 [0] = 3200000,
6862 [1] = 4000000,
6863 [2] = 5333333,
6864 [3] = 6400000,
6865 [4] = 2666667,
6866 [5] = 4266667,
6867 };
6868 const unsigned int *vco_table;
6869 unsigned int vco;
6870 uint8_t tmp = 0;
6871
6872 /* FIXME other chipsets? */
6873 if (IS_GM45(dev))
6874 vco_table = ctg_vco;
6875 else if (IS_G4X(dev))
6876 vco_table = elk_vco;
6877 else if (IS_CRESTLINE(dev))
6878 vco_table = cl_vco;
6879 else if (IS_PINEVIEW(dev))
6880 vco_table = pnv_vco;
6881 else if (IS_G33(dev))
6882 vco_table = blb_vco;
6883 else
6884 return 0;
6885
6886 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6887
6888 vco = vco_table[tmp & 0x7];
6889 if (vco == 0)
6890 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6891 else
6892 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6893
6894 return vco;
6895 }
6896
6897 static int gm45_get_display_clock_speed(struct drm_device *dev)
6898 {
6899 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6900 uint16_t tmp = 0;
6901
6902 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6903
6904 cdclk_sel = (tmp >> 12) & 0x1;
6905
6906 switch (vco) {
6907 case 2666667:
6908 case 4000000:
6909 case 5333333:
6910 return cdclk_sel ? 333333 : 222222;
6911 case 3200000:
6912 return cdclk_sel ? 320000 : 228571;
6913 default:
6914 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6915 return 222222;
6916 }
6917 }
6918
6919 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6920 {
6921 static const uint8_t div_3200[] = { 16, 10, 8 };
6922 static const uint8_t div_4000[] = { 20, 12, 10 };
6923 static const uint8_t div_5333[] = { 24, 16, 14 };
6924 const uint8_t *div_table;
6925 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6926 uint16_t tmp = 0;
6927
6928 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6929
6930 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6931
6932 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6933 goto fail;
6934
6935 switch (vco) {
6936 case 3200000:
6937 div_table = div_3200;
6938 break;
6939 case 4000000:
6940 div_table = div_4000;
6941 break;
6942 case 5333333:
6943 div_table = div_5333;
6944 break;
6945 default:
6946 goto fail;
6947 }
6948
6949 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6950
6951 fail:
6952 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6953 return 200000;
6954 }
6955
6956 static int g33_get_display_clock_speed(struct drm_device *dev)
6957 {
6958 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6959 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6960 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6961 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6962 const uint8_t *div_table;
6963 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6964 uint16_t tmp = 0;
6965
6966 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6967
6968 cdclk_sel = (tmp >> 4) & 0x7;
6969
6970 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6971 goto fail;
6972
6973 switch (vco) {
6974 case 3200000:
6975 div_table = div_3200;
6976 break;
6977 case 4000000:
6978 div_table = div_4000;
6979 break;
6980 case 4800000:
6981 div_table = div_4800;
6982 break;
6983 case 5333333:
6984 div_table = div_5333;
6985 break;
6986 default:
6987 goto fail;
6988 }
6989
6990 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6991
6992 fail:
6993 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6994 return 190476;
6995 }
6996
6997 static void
6998 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6999 {
7000 while (*num > DATA_LINK_M_N_MASK ||
7001 *den > DATA_LINK_M_N_MASK) {
7002 *num >>= 1;
7003 *den >>= 1;
7004 }
7005 }
7006
7007 static void compute_m_n(unsigned int m, unsigned int n,
7008 uint32_t *ret_m, uint32_t *ret_n)
7009 {
7010 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7011 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7012 intel_reduce_m_n_ratio(ret_m, ret_n);
7013 }
7014
7015 void
7016 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7017 int pixel_clock, int link_clock,
7018 struct intel_link_m_n *m_n)
7019 {
7020 m_n->tu = 64;
7021
7022 compute_m_n(bits_per_pixel * pixel_clock,
7023 link_clock * nlanes * 8,
7024 &m_n->gmch_m, &m_n->gmch_n);
7025
7026 compute_m_n(pixel_clock, link_clock,
7027 &m_n->link_m, &m_n->link_n);
7028 }
7029
7030 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7031 {
7032 if (i915.panel_use_ssc >= 0)
7033 return i915.panel_use_ssc != 0;
7034 return dev_priv->vbt.lvds_use_ssc
7035 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7036 }
7037
7038 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7039 int num_connectors)
7040 {
7041 struct drm_device *dev = crtc_state->base.crtc->dev;
7042 struct drm_i915_private *dev_priv = dev->dev_private;
7043 int refclk;
7044
7045 WARN_ON(!crtc_state->base.state);
7046
7047 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7048 refclk = 100000;
7049 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7050 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7051 refclk = dev_priv->vbt.lvds_ssc_freq;
7052 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7053 } else if (!IS_GEN2(dev)) {
7054 refclk = 96000;
7055 } else {
7056 refclk = 48000;
7057 }
7058
7059 return refclk;
7060 }
7061
7062 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7063 {
7064 return (1 << dpll->n) << 16 | dpll->m2;
7065 }
7066
7067 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7068 {
7069 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7070 }
7071
7072 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7073 struct intel_crtc_state *crtc_state,
7074 intel_clock_t *reduced_clock)
7075 {
7076 struct drm_device *dev = crtc->base.dev;
7077 u32 fp, fp2 = 0;
7078
7079 if (IS_PINEVIEW(dev)) {
7080 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7081 if (reduced_clock)
7082 fp2 = pnv_dpll_compute_fp(reduced_clock);
7083 } else {
7084 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7085 if (reduced_clock)
7086 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7087 }
7088
7089 crtc_state->dpll_hw_state.fp0 = fp;
7090
7091 crtc->lowfreq_avail = false;
7092 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7093 reduced_clock) {
7094 crtc_state->dpll_hw_state.fp1 = fp2;
7095 crtc->lowfreq_avail = true;
7096 } else {
7097 crtc_state->dpll_hw_state.fp1 = fp;
7098 }
7099 }
7100
7101 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7102 pipe)
7103 {
7104 u32 reg_val;
7105
7106 /*
7107 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7108 * and set it to a reasonable value instead.
7109 */
7110 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7111 reg_val &= 0xffffff00;
7112 reg_val |= 0x00000030;
7113 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7114
7115 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7116 reg_val &= 0x8cffffff;
7117 reg_val = 0x8c000000;
7118 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7119
7120 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7121 reg_val &= 0xffffff00;
7122 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7123
7124 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7125 reg_val &= 0x00ffffff;
7126 reg_val |= 0xb0000000;
7127 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7128 }
7129
7130 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7131 struct intel_link_m_n *m_n)
7132 {
7133 struct drm_device *dev = crtc->base.dev;
7134 struct drm_i915_private *dev_priv = dev->dev_private;
7135 int pipe = crtc->pipe;
7136
7137 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7138 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7139 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7140 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7141 }
7142
7143 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7144 struct intel_link_m_n *m_n,
7145 struct intel_link_m_n *m2_n2)
7146 {
7147 struct drm_device *dev = crtc->base.dev;
7148 struct drm_i915_private *dev_priv = dev->dev_private;
7149 int pipe = crtc->pipe;
7150 enum transcoder transcoder = crtc->config->cpu_transcoder;
7151
7152 if (INTEL_INFO(dev)->gen >= 5) {
7153 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7154 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7155 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7156 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7157 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7158 * for gen < 8) and if DRRS is supported (to make sure the
7159 * registers are not unnecessarily accessed).
7160 */
7161 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7162 crtc->config->has_drrs) {
7163 I915_WRITE(PIPE_DATA_M2(transcoder),
7164 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7165 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7166 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7167 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7168 }
7169 } else {
7170 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7171 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7172 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7173 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7174 }
7175 }
7176
7177 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7178 {
7179 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7180
7181 if (m_n == M1_N1) {
7182 dp_m_n = &crtc->config->dp_m_n;
7183 dp_m2_n2 = &crtc->config->dp_m2_n2;
7184 } else if (m_n == M2_N2) {
7185
7186 /*
7187 * M2_N2 registers are not supported. Hence m2_n2 divider value
7188 * needs to be programmed into M1_N1.
7189 */
7190 dp_m_n = &crtc->config->dp_m2_n2;
7191 } else {
7192 DRM_ERROR("Unsupported divider value\n");
7193 return;
7194 }
7195
7196 if (crtc->config->has_pch_encoder)
7197 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7198 else
7199 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7200 }
7201
7202 static void vlv_compute_dpll(struct intel_crtc *crtc,
7203 struct intel_crtc_state *pipe_config)
7204 {
7205 u32 dpll, dpll_md;
7206
7207 /*
7208 * Enable DPIO clock input. We should never disable the reference
7209 * clock for pipe B, since VGA hotplug / manual detection depends
7210 * on it.
7211 */
7212 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7213 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7214 /* We should never disable this, set it here for state tracking */
7215 if (crtc->pipe == PIPE_B)
7216 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7217 dpll |= DPLL_VCO_ENABLE;
7218 pipe_config->dpll_hw_state.dpll = dpll;
7219
7220 dpll_md = (pipe_config->pixel_multiplier - 1)
7221 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7222 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7223 }
7224
7225 static void vlv_prepare_pll(struct intel_crtc *crtc,
7226 const struct intel_crtc_state *pipe_config)
7227 {
7228 struct drm_device *dev = crtc->base.dev;
7229 struct drm_i915_private *dev_priv = dev->dev_private;
7230 int pipe = crtc->pipe;
7231 u32 mdiv;
7232 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7233 u32 coreclk, reg_val;
7234
7235 mutex_lock(&dev_priv->sb_lock);
7236
7237 bestn = pipe_config->dpll.n;
7238 bestm1 = pipe_config->dpll.m1;
7239 bestm2 = pipe_config->dpll.m2;
7240 bestp1 = pipe_config->dpll.p1;
7241 bestp2 = pipe_config->dpll.p2;
7242
7243 /* See eDP HDMI DPIO driver vbios notes doc */
7244
7245 /* PLL B needs special handling */
7246 if (pipe == PIPE_B)
7247 vlv_pllb_recal_opamp(dev_priv, pipe);
7248
7249 /* Set up Tx target for periodic Rcomp update */
7250 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7251
7252 /* Disable target IRef on PLL */
7253 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7254 reg_val &= 0x00ffffff;
7255 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7256
7257 /* Disable fast lock */
7258 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7259
7260 /* Set idtafcrecal before PLL is enabled */
7261 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7262 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7263 mdiv |= ((bestn << DPIO_N_SHIFT));
7264 mdiv |= (1 << DPIO_K_SHIFT);
7265
7266 /*
7267 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7268 * but we don't support that).
7269 * Note: don't use the DAC post divider as it seems unstable.
7270 */
7271 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7272 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7273
7274 mdiv |= DPIO_ENABLE_CALIBRATION;
7275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7276
7277 /* Set HBR and RBR LPF coefficients */
7278 if (pipe_config->port_clock == 162000 ||
7279 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7280 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7281 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7282 0x009f0003);
7283 else
7284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7285 0x00d0000f);
7286
7287 if (pipe_config->has_dp_encoder) {
7288 /* Use SSC source */
7289 if (pipe == PIPE_A)
7290 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7291 0x0df40000);
7292 else
7293 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7294 0x0df70000);
7295 } else { /* HDMI or VGA */
7296 /* Use bend source */
7297 if (pipe == PIPE_A)
7298 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7299 0x0df70000);
7300 else
7301 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7302 0x0df40000);
7303 }
7304
7305 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7306 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7307 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7308 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7309 coreclk |= 0x01000000;
7310 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7311
7312 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7313 mutex_unlock(&dev_priv->sb_lock);
7314 }
7315
7316 static void chv_compute_dpll(struct intel_crtc *crtc,
7317 struct intel_crtc_state *pipe_config)
7318 {
7319 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7320 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7321 DPLL_VCO_ENABLE;
7322 if (crtc->pipe != PIPE_A)
7323 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7324
7325 pipe_config->dpll_hw_state.dpll_md =
7326 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7327 }
7328
7329 static void chv_prepare_pll(struct intel_crtc *crtc,
7330 const struct intel_crtc_state *pipe_config)
7331 {
7332 struct drm_device *dev = crtc->base.dev;
7333 struct drm_i915_private *dev_priv = dev->dev_private;
7334 int pipe = crtc->pipe;
7335 int dpll_reg = DPLL(crtc->pipe);
7336 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7337 u32 loopfilter, tribuf_calcntr;
7338 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7339 u32 dpio_val;
7340 int vco;
7341
7342 bestn = pipe_config->dpll.n;
7343 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7344 bestm1 = pipe_config->dpll.m1;
7345 bestm2 = pipe_config->dpll.m2 >> 22;
7346 bestp1 = pipe_config->dpll.p1;
7347 bestp2 = pipe_config->dpll.p2;
7348 vco = pipe_config->dpll.vco;
7349 dpio_val = 0;
7350 loopfilter = 0;
7351
7352 /*
7353 * Enable Refclk and SSC
7354 */
7355 I915_WRITE(dpll_reg,
7356 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7357
7358 mutex_lock(&dev_priv->sb_lock);
7359
7360 /* p1 and p2 divider */
7361 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7362 5 << DPIO_CHV_S1_DIV_SHIFT |
7363 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7364 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7365 1 << DPIO_CHV_K_DIV_SHIFT);
7366
7367 /* Feedback post-divider - m2 */
7368 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7369
7370 /* Feedback refclk divider - n and m1 */
7371 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7372 DPIO_CHV_M1_DIV_BY_2 |
7373 1 << DPIO_CHV_N_DIV_SHIFT);
7374
7375 /* M2 fraction division */
7376 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7377
7378 /* M2 fraction division enable */
7379 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7380 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7381 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7382 if (bestm2_frac)
7383 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7384 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7385
7386 /* Program digital lock detect threshold */
7387 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7388 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7389 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7390 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7391 if (!bestm2_frac)
7392 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7393 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7394
7395 /* Loop filter */
7396 if (vco == 5400000) {
7397 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7398 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7399 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7400 tribuf_calcntr = 0x9;
7401 } else if (vco <= 6200000) {
7402 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7403 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7404 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7405 tribuf_calcntr = 0x9;
7406 } else if (vco <= 6480000) {
7407 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7408 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7409 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7410 tribuf_calcntr = 0x8;
7411 } else {
7412 /* Not supported. Apply the same limits as in the max case */
7413 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7414 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7415 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7416 tribuf_calcntr = 0;
7417 }
7418 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7419
7420 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7421 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7422 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7423 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7424
7425 /* AFC Recal */
7426 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7427 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7428 DPIO_AFC_RECAL);
7429
7430 mutex_unlock(&dev_priv->sb_lock);
7431 }
7432
7433 /**
7434 * vlv_force_pll_on - forcibly enable just the PLL
7435 * @dev_priv: i915 private structure
7436 * @pipe: pipe PLL to enable
7437 * @dpll: PLL configuration
7438 *
7439 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7440 * in cases where we need the PLL enabled even when @pipe is not going to
7441 * be enabled.
7442 */
7443 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7444 const struct dpll *dpll)
7445 {
7446 struct intel_crtc *crtc =
7447 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7448 struct intel_crtc_state pipe_config = {
7449 .base.crtc = &crtc->base,
7450 .pixel_multiplier = 1,
7451 .dpll = *dpll,
7452 };
7453
7454 if (IS_CHERRYVIEW(dev)) {
7455 chv_compute_dpll(crtc, &pipe_config);
7456 chv_prepare_pll(crtc, &pipe_config);
7457 chv_enable_pll(crtc, &pipe_config);
7458 } else {
7459 vlv_compute_dpll(crtc, &pipe_config);
7460 vlv_prepare_pll(crtc, &pipe_config);
7461 vlv_enable_pll(crtc, &pipe_config);
7462 }
7463 }
7464
7465 /**
7466 * vlv_force_pll_off - forcibly disable just the PLL
7467 * @dev_priv: i915 private structure
7468 * @pipe: pipe PLL to disable
7469 *
7470 * Disable the PLL for @pipe. To be used in cases where we need
7471 * the PLL enabled even when @pipe is not going to be enabled.
7472 */
7473 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7474 {
7475 if (IS_CHERRYVIEW(dev))
7476 chv_disable_pll(to_i915(dev), pipe);
7477 else
7478 vlv_disable_pll(to_i915(dev), pipe);
7479 }
7480
7481 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7482 struct intel_crtc_state *crtc_state,
7483 intel_clock_t *reduced_clock,
7484 int num_connectors)
7485 {
7486 struct drm_device *dev = crtc->base.dev;
7487 struct drm_i915_private *dev_priv = dev->dev_private;
7488 u32 dpll;
7489 bool is_sdvo;
7490 struct dpll *clock = &crtc_state->dpll;
7491
7492 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7493
7494 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7495 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7496
7497 dpll = DPLL_VGA_MODE_DIS;
7498
7499 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7500 dpll |= DPLLB_MODE_LVDS;
7501 else
7502 dpll |= DPLLB_MODE_DAC_SERIAL;
7503
7504 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7505 dpll |= (crtc_state->pixel_multiplier - 1)
7506 << SDVO_MULTIPLIER_SHIFT_HIRES;
7507 }
7508
7509 if (is_sdvo)
7510 dpll |= DPLL_SDVO_HIGH_SPEED;
7511
7512 if (crtc_state->has_dp_encoder)
7513 dpll |= DPLL_SDVO_HIGH_SPEED;
7514
7515 /* compute bitmask from p1 value */
7516 if (IS_PINEVIEW(dev))
7517 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7518 else {
7519 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7520 if (IS_G4X(dev) && reduced_clock)
7521 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7522 }
7523 switch (clock->p2) {
7524 case 5:
7525 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7526 break;
7527 case 7:
7528 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7529 break;
7530 case 10:
7531 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7532 break;
7533 case 14:
7534 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7535 break;
7536 }
7537 if (INTEL_INFO(dev)->gen >= 4)
7538 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7539
7540 if (crtc_state->sdvo_tv_clock)
7541 dpll |= PLL_REF_INPUT_TVCLKINBC;
7542 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7543 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7544 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7545 else
7546 dpll |= PLL_REF_INPUT_DREFCLK;
7547
7548 dpll |= DPLL_VCO_ENABLE;
7549 crtc_state->dpll_hw_state.dpll = dpll;
7550
7551 if (INTEL_INFO(dev)->gen >= 4) {
7552 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7553 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7554 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7555 }
7556 }
7557
7558 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7559 struct intel_crtc_state *crtc_state,
7560 intel_clock_t *reduced_clock,
7561 int num_connectors)
7562 {
7563 struct drm_device *dev = crtc->base.dev;
7564 struct drm_i915_private *dev_priv = dev->dev_private;
7565 u32 dpll;
7566 struct dpll *clock = &crtc_state->dpll;
7567
7568 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7569
7570 dpll = DPLL_VGA_MODE_DIS;
7571
7572 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7573 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7574 } else {
7575 if (clock->p1 == 2)
7576 dpll |= PLL_P1_DIVIDE_BY_TWO;
7577 else
7578 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7579 if (clock->p2 == 4)
7580 dpll |= PLL_P2_DIVIDE_BY_4;
7581 }
7582
7583 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7584 dpll |= DPLL_DVO_2X_MODE;
7585
7586 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7587 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7588 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7589 else
7590 dpll |= PLL_REF_INPUT_DREFCLK;
7591
7592 dpll |= DPLL_VCO_ENABLE;
7593 crtc_state->dpll_hw_state.dpll = dpll;
7594 }
7595
7596 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7597 {
7598 struct drm_device *dev = intel_crtc->base.dev;
7599 struct drm_i915_private *dev_priv = dev->dev_private;
7600 enum pipe pipe = intel_crtc->pipe;
7601 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7602 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7603 uint32_t crtc_vtotal, crtc_vblank_end;
7604 int vsyncshift = 0;
7605
7606 /* We need to be careful not to changed the adjusted mode, for otherwise
7607 * the hw state checker will get angry at the mismatch. */
7608 crtc_vtotal = adjusted_mode->crtc_vtotal;
7609 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7610
7611 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7612 /* the chip adds 2 halflines automatically */
7613 crtc_vtotal -= 1;
7614 crtc_vblank_end -= 1;
7615
7616 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7617 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7618 else
7619 vsyncshift = adjusted_mode->crtc_hsync_start -
7620 adjusted_mode->crtc_htotal / 2;
7621 if (vsyncshift < 0)
7622 vsyncshift += adjusted_mode->crtc_htotal;
7623 }
7624
7625 if (INTEL_INFO(dev)->gen > 3)
7626 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7627
7628 I915_WRITE(HTOTAL(cpu_transcoder),
7629 (adjusted_mode->crtc_hdisplay - 1) |
7630 ((adjusted_mode->crtc_htotal - 1) << 16));
7631 I915_WRITE(HBLANK(cpu_transcoder),
7632 (adjusted_mode->crtc_hblank_start - 1) |
7633 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7634 I915_WRITE(HSYNC(cpu_transcoder),
7635 (adjusted_mode->crtc_hsync_start - 1) |
7636 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7637
7638 I915_WRITE(VTOTAL(cpu_transcoder),
7639 (adjusted_mode->crtc_vdisplay - 1) |
7640 ((crtc_vtotal - 1) << 16));
7641 I915_WRITE(VBLANK(cpu_transcoder),
7642 (adjusted_mode->crtc_vblank_start - 1) |
7643 ((crtc_vblank_end - 1) << 16));
7644 I915_WRITE(VSYNC(cpu_transcoder),
7645 (adjusted_mode->crtc_vsync_start - 1) |
7646 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7647
7648 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7649 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7650 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7651 * bits. */
7652 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7653 (pipe == PIPE_B || pipe == PIPE_C))
7654 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7655
7656 /* pipesrc controls the size that is scaled from, which should
7657 * always be the user's requested size.
7658 */
7659 I915_WRITE(PIPESRC(pipe),
7660 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7661 (intel_crtc->config->pipe_src_h - 1));
7662 }
7663
7664 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7665 struct intel_crtc_state *pipe_config)
7666 {
7667 struct drm_device *dev = crtc->base.dev;
7668 struct drm_i915_private *dev_priv = dev->dev_private;
7669 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7670 uint32_t tmp;
7671
7672 tmp = I915_READ(HTOTAL(cpu_transcoder));
7673 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7674 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7675 tmp = I915_READ(HBLANK(cpu_transcoder));
7676 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7677 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7678 tmp = I915_READ(HSYNC(cpu_transcoder));
7679 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7680 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7681
7682 tmp = I915_READ(VTOTAL(cpu_transcoder));
7683 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7684 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7685 tmp = I915_READ(VBLANK(cpu_transcoder));
7686 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7687 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7688 tmp = I915_READ(VSYNC(cpu_transcoder));
7689 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7690 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7691
7692 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7693 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7694 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7695 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7696 }
7697
7698 tmp = I915_READ(PIPESRC(crtc->pipe));
7699 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7700 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7701
7702 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7703 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7704 }
7705
7706 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7707 struct intel_crtc_state *pipe_config)
7708 {
7709 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7710 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7711 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7712 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7713
7714 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7715 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7716 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7717 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7718
7719 mode->flags = pipe_config->base.adjusted_mode.flags;
7720 mode->type = DRM_MODE_TYPE_DRIVER;
7721
7722 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7723 mode->flags |= pipe_config->base.adjusted_mode.flags;
7724
7725 mode->hsync = drm_mode_hsync(mode);
7726 mode->vrefresh = drm_mode_vrefresh(mode);
7727 drm_mode_set_name(mode);
7728 }
7729
7730 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7731 {
7732 struct drm_device *dev = intel_crtc->base.dev;
7733 struct drm_i915_private *dev_priv = dev->dev_private;
7734 uint32_t pipeconf;
7735
7736 pipeconf = 0;
7737
7738 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7739 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7740 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7741
7742 if (intel_crtc->config->double_wide)
7743 pipeconf |= PIPECONF_DOUBLE_WIDE;
7744
7745 /* only g4x and later have fancy bpc/dither controls */
7746 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7747 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7748 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7749 pipeconf |= PIPECONF_DITHER_EN |
7750 PIPECONF_DITHER_TYPE_SP;
7751
7752 switch (intel_crtc->config->pipe_bpp) {
7753 case 18:
7754 pipeconf |= PIPECONF_6BPC;
7755 break;
7756 case 24:
7757 pipeconf |= PIPECONF_8BPC;
7758 break;
7759 case 30:
7760 pipeconf |= PIPECONF_10BPC;
7761 break;
7762 default:
7763 /* Case prevented by intel_choose_pipe_bpp_dither. */
7764 BUG();
7765 }
7766 }
7767
7768 if (HAS_PIPE_CXSR(dev)) {
7769 if (intel_crtc->lowfreq_avail) {
7770 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7771 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7772 } else {
7773 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7774 }
7775 }
7776
7777 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7778 if (INTEL_INFO(dev)->gen < 4 ||
7779 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7780 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7781 else
7782 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7783 } else
7784 pipeconf |= PIPECONF_PROGRESSIVE;
7785
7786 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7787 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7788
7789 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7790 POSTING_READ(PIPECONF(intel_crtc->pipe));
7791 }
7792
7793 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7794 struct intel_crtc_state *crtc_state)
7795 {
7796 struct drm_device *dev = crtc->base.dev;
7797 struct drm_i915_private *dev_priv = dev->dev_private;
7798 int refclk, num_connectors = 0;
7799 intel_clock_t clock;
7800 bool ok;
7801 bool is_dsi = false;
7802 struct intel_encoder *encoder;
7803 const intel_limit_t *limit;
7804 struct drm_atomic_state *state = crtc_state->base.state;
7805 struct drm_connector *connector;
7806 struct drm_connector_state *connector_state;
7807 int i;
7808
7809 memset(&crtc_state->dpll_hw_state, 0,
7810 sizeof(crtc_state->dpll_hw_state));
7811
7812 for_each_connector_in_state(state, connector, connector_state, i) {
7813 if (connector_state->crtc != &crtc->base)
7814 continue;
7815
7816 encoder = to_intel_encoder(connector_state->best_encoder);
7817
7818 switch (encoder->type) {
7819 case INTEL_OUTPUT_DSI:
7820 is_dsi = true;
7821 break;
7822 default:
7823 break;
7824 }
7825
7826 num_connectors++;
7827 }
7828
7829 if (is_dsi)
7830 return 0;
7831
7832 if (!crtc_state->clock_set) {
7833 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7834
7835 /*
7836 * Returns a set of divisors for the desired target clock with
7837 * the given refclk, or FALSE. The returned values represent
7838 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7839 * 2) / p1 / p2.
7840 */
7841 limit = intel_limit(crtc_state, refclk);
7842 ok = dev_priv->display.find_dpll(limit, crtc_state,
7843 crtc_state->port_clock,
7844 refclk, NULL, &clock);
7845 if (!ok) {
7846 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7847 return -EINVAL;
7848 }
7849
7850 /* Compat-code for transition, will disappear. */
7851 crtc_state->dpll.n = clock.n;
7852 crtc_state->dpll.m1 = clock.m1;
7853 crtc_state->dpll.m2 = clock.m2;
7854 crtc_state->dpll.p1 = clock.p1;
7855 crtc_state->dpll.p2 = clock.p2;
7856 }
7857
7858 if (IS_GEN2(dev)) {
7859 i8xx_compute_dpll(crtc, crtc_state, NULL,
7860 num_connectors);
7861 } else if (IS_CHERRYVIEW(dev)) {
7862 chv_compute_dpll(crtc, crtc_state);
7863 } else if (IS_VALLEYVIEW(dev)) {
7864 vlv_compute_dpll(crtc, crtc_state);
7865 } else {
7866 i9xx_compute_dpll(crtc, crtc_state, NULL,
7867 num_connectors);
7868 }
7869
7870 return 0;
7871 }
7872
7873 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7874 struct intel_crtc_state *pipe_config)
7875 {
7876 struct drm_device *dev = crtc->base.dev;
7877 struct drm_i915_private *dev_priv = dev->dev_private;
7878 uint32_t tmp;
7879
7880 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7881 return;
7882
7883 tmp = I915_READ(PFIT_CONTROL);
7884 if (!(tmp & PFIT_ENABLE))
7885 return;
7886
7887 /* Check whether the pfit is attached to our pipe. */
7888 if (INTEL_INFO(dev)->gen < 4) {
7889 if (crtc->pipe != PIPE_B)
7890 return;
7891 } else {
7892 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7893 return;
7894 }
7895
7896 pipe_config->gmch_pfit.control = tmp;
7897 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7898 if (INTEL_INFO(dev)->gen < 5)
7899 pipe_config->gmch_pfit.lvds_border_bits =
7900 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7901 }
7902
7903 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7904 struct intel_crtc_state *pipe_config)
7905 {
7906 struct drm_device *dev = crtc->base.dev;
7907 struct drm_i915_private *dev_priv = dev->dev_private;
7908 int pipe = pipe_config->cpu_transcoder;
7909 intel_clock_t clock;
7910 u32 mdiv;
7911 int refclk = 100000;
7912
7913 /* In case of MIPI DPLL will not even be used */
7914 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7915 return;
7916
7917 mutex_lock(&dev_priv->sb_lock);
7918 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7919 mutex_unlock(&dev_priv->sb_lock);
7920
7921 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7922 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7923 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7924 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7925 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7926
7927 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7928 }
7929
7930 static void
7931 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7932 struct intel_initial_plane_config *plane_config)
7933 {
7934 struct drm_device *dev = crtc->base.dev;
7935 struct drm_i915_private *dev_priv = dev->dev_private;
7936 u32 val, base, offset;
7937 int pipe = crtc->pipe, plane = crtc->plane;
7938 int fourcc, pixel_format;
7939 unsigned int aligned_height;
7940 struct drm_framebuffer *fb;
7941 struct intel_framebuffer *intel_fb;
7942
7943 val = I915_READ(DSPCNTR(plane));
7944 if (!(val & DISPLAY_PLANE_ENABLE))
7945 return;
7946
7947 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7948 if (!intel_fb) {
7949 DRM_DEBUG_KMS("failed to alloc fb\n");
7950 return;
7951 }
7952
7953 fb = &intel_fb->base;
7954
7955 if (INTEL_INFO(dev)->gen >= 4) {
7956 if (val & DISPPLANE_TILED) {
7957 plane_config->tiling = I915_TILING_X;
7958 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7959 }
7960 }
7961
7962 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7963 fourcc = i9xx_format_to_fourcc(pixel_format);
7964 fb->pixel_format = fourcc;
7965 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7966
7967 if (INTEL_INFO(dev)->gen >= 4) {
7968 if (plane_config->tiling)
7969 offset = I915_READ(DSPTILEOFF(plane));
7970 else
7971 offset = I915_READ(DSPLINOFF(plane));
7972 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7973 } else {
7974 base = I915_READ(DSPADDR(plane));
7975 }
7976 plane_config->base = base;
7977
7978 val = I915_READ(PIPESRC(pipe));
7979 fb->width = ((val >> 16) & 0xfff) + 1;
7980 fb->height = ((val >> 0) & 0xfff) + 1;
7981
7982 val = I915_READ(DSPSTRIDE(pipe));
7983 fb->pitches[0] = val & 0xffffffc0;
7984
7985 aligned_height = intel_fb_align_height(dev, fb->height,
7986 fb->pixel_format,
7987 fb->modifier[0]);
7988
7989 plane_config->size = fb->pitches[0] * aligned_height;
7990
7991 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7992 pipe_name(pipe), plane, fb->width, fb->height,
7993 fb->bits_per_pixel, base, fb->pitches[0],
7994 plane_config->size);
7995
7996 plane_config->fb = intel_fb;
7997 }
7998
7999 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8000 struct intel_crtc_state *pipe_config)
8001 {
8002 struct drm_device *dev = crtc->base.dev;
8003 struct drm_i915_private *dev_priv = dev->dev_private;
8004 int pipe = pipe_config->cpu_transcoder;
8005 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8006 intel_clock_t clock;
8007 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8008 int refclk = 100000;
8009
8010 mutex_lock(&dev_priv->sb_lock);
8011 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8012 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8013 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8014 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8015 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8016 mutex_unlock(&dev_priv->sb_lock);
8017
8018 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8019 clock.m2 = (pll_dw0 & 0xff) << 22;
8020 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8021 clock.m2 |= pll_dw2 & 0x3fffff;
8022 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8023 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8024 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8025
8026 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8027 }
8028
8029 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8030 struct intel_crtc_state *pipe_config)
8031 {
8032 struct drm_device *dev = crtc->base.dev;
8033 struct drm_i915_private *dev_priv = dev->dev_private;
8034 uint32_t tmp;
8035
8036 if (!intel_display_power_is_enabled(dev_priv,
8037 POWER_DOMAIN_PIPE(crtc->pipe)))
8038 return false;
8039
8040 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8041 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8042
8043 tmp = I915_READ(PIPECONF(crtc->pipe));
8044 if (!(tmp & PIPECONF_ENABLE))
8045 return false;
8046
8047 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8048 switch (tmp & PIPECONF_BPC_MASK) {
8049 case PIPECONF_6BPC:
8050 pipe_config->pipe_bpp = 18;
8051 break;
8052 case PIPECONF_8BPC:
8053 pipe_config->pipe_bpp = 24;
8054 break;
8055 case PIPECONF_10BPC:
8056 pipe_config->pipe_bpp = 30;
8057 break;
8058 default:
8059 break;
8060 }
8061 }
8062
8063 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8064 pipe_config->limited_color_range = true;
8065
8066 if (INTEL_INFO(dev)->gen < 4)
8067 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8068
8069 intel_get_pipe_timings(crtc, pipe_config);
8070
8071 i9xx_get_pfit_config(crtc, pipe_config);
8072
8073 if (INTEL_INFO(dev)->gen >= 4) {
8074 tmp = I915_READ(DPLL_MD(crtc->pipe));
8075 pipe_config->pixel_multiplier =
8076 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8077 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8078 pipe_config->dpll_hw_state.dpll_md = tmp;
8079 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8080 tmp = I915_READ(DPLL(crtc->pipe));
8081 pipe_config->pixel_multiplier =
8082 ((tmp & SDVO_MULTIPLIER_MASK)
8083 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8084 } else {
8085 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8086 * port and will be fixed up in the encoder->get_config
8087 * function. */
8088 pipe_config->pixel_multiplier = 1;
8089 }
8090 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8091 if (!IS_VALLEYVIEW(dev)) {
8092 /*
8093 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8094 * on 830. Filter it out here so that we don't
8095 * report errors due to that.
8096 */
8097 if (IS_I830(dev))
8098 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8099
8100 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8101 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8102 } else {
8103 /* Mask out read-only status bits. */
8104 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8105 DPLL_PORTC_READY_MASK |
8106 DPLL_PORTB_READY_MASK);
8107 }
8108
8109 if (IS_CHERRYVIEW(dev))
8110 chv_crtc_clock_get(crtc, pipe_config);
8111 else if (IS_VALLEYVIEW(dev))
8112 vlv_crtc_clock_get(crtc, pipe_config);
8113 else
8114 i9xx_crtc_clock_get(crtc, pipe_config);
8115
8116 /*
8117 * Normally the dotclock is filled in by the encoder .get_config()
8118 * but in case the pipe is enabled w/o any ports we need a sane
8119 * default.
8120 */
8121 pipe_config->base.adjusted_mode.crtc_clock =
8122 pipe_config->port_clock / pipe_config->pixel_multiplier;
8123
8124 return true;
8125 }
8126
8127 static void ironlake_init_pch_refclk(struct drm_device *dev)
8128 {
8129 struct drm_i915_private *dev_priv = dev->dev_private;
8130 struct intel_encoder *encoder;
8131 u32 val, final;
8132 bool has_lvds = false;
8133 bool has_cpu_edp = false;
8134 bool has_panel = false;
8135 bool has_ck505 = false;
8136 bool can_ssc = false;
8137
8138 /* We need to take the global config into account */
8139 for_each_intel_encoder(dev, encoder) {
8140 switch (encoder->type) {
8141 case INTEL_OUTPUT_LVDS:
8142 has_panel = true;
8143 has_lvds = true;
8144 break;
8145 case INTEL_OUTPUT_EDP:
8146 has_panel = true;
8147 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8148 has_cpu_edp = true;
8149 break;
8150 default:
8151 break;
8152 }
8153 }
8154
8155 if (HAS_PCH_IBX(dev)) {
8156 has_ck505 = dev_priv->vbt.display_clock_mode;
8157 can_ssc = has_ck505;
8158 } else {
8159 has_ck505 = false;
8160 can_ssc = true;
8161 }
8162
8163 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8164 has_panel, has_lvds, has_ck505);
8165
8166 /* Ironlake: try to setup display ref clock before DPLL
8167 * enabling. This is only under driver's control after
8168 * PCH B stepping, previous chipset stepping should be
8169 * ignoring this setting.
8170 */
8171 val = I915_READ(PCH_DREF_CONTROL);
8172
8173 /* As we must carefully and slowly disable/enable each source in turn,
8174 * compute the final state we want first and check if we need to
8175 * make any changes at all.
8176 */
8177 final = val;
8178 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8179 if (has_ck505)
8180 final |= DREF_NONSPREAD_CK505_ENABLE;
8181 else
8182 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8183
8184 final &= ~DREF_SSC_SOURCE_MASK;
8185 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8186 final &= ~DREF_SSC1_ENABLE;
8187
8188 if (has_panel) {
8189 final |= DREF_SSC_SOURCE_ENABLE;
8190
8191 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8192 final |= DREF_SSC1_ENABLE;
8193
8194 if (has_cpu_edp) {
8195 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8196 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8197 else
8198 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8199 } else
8200 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8201 } else {
8202 final |= DREF_SSC_SOURCE_DISABLE;
8203 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8204 }
8205
8206 if (final == val)
8207 return;
8208
8209 /* Always enable nonspread source */
8210 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8211
8212 if (has_ck505)
8213 val |= DREF_NONSPREAD_CK505_ENABLE;
8214 else
8215 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8216
8217 if (has_panel) {
8218 val &= ~DREF_SSC_SOURCE_MASK;
8219 val |= DREF_SSC_SOURCE_ENABLE;
8220
8221 /* SSC must be turned on before enabling the CPU output */
8222 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8223 DRM_DEBUG_KMS("Using SSC on panel\n");
8224 val |= DREF_SSC1_ENABLE;
8225 } else
8226 val &= ~DREF_SSC1_ENABLE;
8227
8228 /* Get SSC going before enabling the outputs */
8229 I915_WRITE(PCH_DREF_CONTROL, val);
8230 POSTING_READ(PCH_DREF_CONTROL);
8231 udelay(200);
8232
8233 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8234
8235 /* Enable CPU source on CPU attached eDP */
8236 if (has_cpu_edp) {
8237 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8238 DRM_DEBUG_KMS("Using SSC on eDP\n");
8239 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8240 } else
8241 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8242 } else
8243 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8244
8245 I915_WRITE(PCH_DREF_CONTROL, val);
8246 POSTING_READ(PCH_DREF_CONTROL);
8247 udelay(200);
8248 } else {
8249 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8250
8251 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8252
8253 /* Turn off CPU output */
8254 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8255
8256 I915_WRITE(PCH_DREF_CONTROL, val);
8257 POSTING_READ(PCH_DREF_CONTROL);
8258 udelay(200);
8259
8260 /* Turn off the SSC source */
8261 val &= ~DREF_SSC_SOURCE_MASK;
8262 val |= DREF_SSC_SOURCE_DISABLE;
8263
8264 /* Turn off SSC1 */
8265 val &= ~DREF_SSC1_ENABLE;
8266
8267 I915_WRITE(PCH_DREF_CONTROL, val);
8268 POSTING_READ(PCH_DREF_CONTROL);
8269 udelay(200);
8270 }
8271
8272 BUG_ON(val != final);
8273 }
8274
8275 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8276 {
8277 uint32_t tmp;
8278
8279 tmp = I915_READ(SOUTH_CHICKEN2);
8280 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8281 I915_WRITE(SOUTH_CHICKEN2, tmp);
8282
8283 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8284 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8285 DRM_ERROR("FDI mPHY reset assert timeout\n");
8286
8287 tmp = I915_READ(SOUTH_CHICKEN2);
8288 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8289 I915_WRITE(SOUTH_CHICKEN2, tmp);
8290
8291 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8292 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8293 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8294 }
8295
8296 /* WaMPhyProgramming:hsw */
8297 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8298 {
8299 uint32_t tmp;
8300
8301 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8302 tmp &= ~(0xFF << 24);
8303 tmp |= (0x12 << 24);
8304 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8305
8306 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8307 tmp |= (1 << 11);
8308 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8309
8310 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8311 tmp |= (1 << 11);
8312 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8313
8314 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8315 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8316 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8317
8318 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8319 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8320 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8321
8322 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8323 tmp &= ~(7 << 13);
8324 tmp |= (5 << 13);
8325 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8326
8327 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8328 tmp &= ~(7 << 13);
8329 tmp |= (5 << 13);
8330 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8331
8332 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8333 tmp &= ~0xFF;
8334 tmp |= 0x1C;
8335 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8336
8337 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8338 tmp &= ~0xFF;
8339 tmp |= 0x1C;
8340 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8341
8342 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8343 tmp &= ~(0xFF << 16);
8344 tmp |= (0x1C << 16);
8345 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8346
8347 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8348 tmp &= ~(0xFF << 16);
8349 tmp |= (0x1C << 16);
8350 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8351
8352 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8353 tmp |= (1 << 27);
8354 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8355
8356 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8357 tmp |= (1 << 27);
8358 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8359
8360 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8361 tmp &= ~(0xF << 28);
8362 tmp |= (4 << 28);
8363 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8364
8365 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8366 tmp &= ~(0xF << 28);
8367 tmp |= (4 << 28);
8368 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8369 }
8370
8371 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8372 * Programming" based on the parameters passed:
8373 * - Sequence to enable CLKOUT_DP
8374 * - Sequence to enable CLKOUT_DP without spread
8375 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8376 */
8377 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8378 bool with_fdi)
8379 {
8380 struct drm_i915_private *dev_priv = dev->dev_private;
8381 uint32_t reg, tmp;
8382
8383 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8384 with_spread = true;
8385 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8386 with_fdi = false;
8387
8388 mutex_lock(&dev_priv->sb_lock);
8389
8390 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8391 tmp &= ~SBI_SSCCTL_DISABLE;
8392 tmp |= SBI_SSCCTL_PATHALT;
8393 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8394
8395 udelay(24);
8396
8397 if (with_spread) {
8398 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8399 tmp &= ~SBI_SSCCTL_PATHALT;
8400 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8401
8402 if (with_fdi) {
8403 lpt_reset_fdi_mphy(dev_priv);
8404 lpt_program_fdi_mphy(dev_priv);
8405 }
8406 }
8407
8408 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8409 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8410 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8411 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8412
8413 mutex_unlock(&dev_priv->sb_lock);
8414 }
8415
8416 /* Sequence to disable CLKOUT_DP */
8417 static void lpt_disable_clkout_dp(struct drm_device *dev)
8418 {
8419 struct drm_i915_private *dev_priv = dev->dev_private;
8420 uint32_t reg, tmp;
8421
8422 mutex_lock(&dev_priv->sb_lock);
8423
8424 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8425 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8426 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8427 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8428
8429 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8430 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8431 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8432 tmp |= SBI_SSCCTL_PATHALT;
8433 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8434 udelay(32);
8435 }
8436 tmp |= SBI_SSCCTL_DISABLE;
8437 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8438 }
8439
8440 mutex_unlock(&dev_priv->sb_lock);
8441 }
8442
8443 static void lpt_init_pch_refclk(struct drm_device *dev)
8444 {
8445 struct intel_encoder *encoder;
8446 bool has_vga = false;
8447
8448 for_each_intel_encoder(dev, encoder) {
8449 switch (encoder->type) {
8450 case INTEL_OUTPUT_ANALOG:
8451 has_vga = true;
8452 break;
8453 default:
8454 break;
8455 }
8456 }
8457
8458 if (has_vga)
8459 lpt_enable_clkout_dp(dev, true, true);
8460 else
8461 lpt_disable_clkout_dp(dev);
8462 }
8463
8464 /*
8465 * Initialize reference clocks when the driver loads
8466 */
8467 void intel_init_pch_refclk(struct drm_device *dev)
8468 {
8469 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8470 ironlake_init_pch_refclk(dev);
8471 else if (HAS_PCH_LPT(dev))
8472 lpt_init_pch_refclk(dev);
8473 }
8474
8475 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8476 {
8477 struct drm_device *dev = crtc_state->base.crtc->dev;
8478 struct drm_i915_private *dev_priv = dev->dev_private;
8479 struct drm_atomic_state *state = crtc_state->base.state;
8480 struct drm_connector *connector;
8481 struct drm_connector_state *connector_state;
8482 struct intel_encoder *encoder;
8483 int num_connectors = 0, i;
8484 bool is_lvds = false;
8485
8486 for_each_connector_in_state(state, connector, connector_state, i) {
8487 if (connector_state->crtc != crtc_state->base.crtc)
8488 continue;
8489
8490 encoder = to_intel_encoder(connector_state->best_encoder);
8491
8492 switch (encoder->type) {
8493 case INTEL_OUTPUT_LVDS:
8494 is_lvds = true;
8495 break;
8496 default:
8497 break;
8498 }
8499 num_connectors++;
8500 }
8501
8502 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8503 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8504 dev_priv->vbt.lvds_ssc_freq);
8505 return dev_priv->vbt.lvds_ssc_freq;
8506 }
8507
8508 return 120000;
8509 }
8510
8511 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8512 {
8513 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8515 int pipe = intel_crtc->pipe;
8516 uint32_t val;
8517
8518 val = 0;
8519
8520 switch (intel_crtc->config->pipe_bpp) {
8521 case 18:
8522 val |= PIPECONF_6BPC;
8523 break;
8524 case 24:
8525 val |= PIPECONF_8BPC;
8526 break;
8527 case 30:
8528 val |= PIPECONF_10BPC;
8529 break;
8530 case 36:
8531 val |= PIPECONF_12BPC;
8532 break;
8533 default:
8534 /* Case prevented by intel_choose_pipe_bpp_dither. */
8535 BUG();
8536 }
8537
8538 if (intel_crtc->config->dither)
8539 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8540
8541 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8542 val |= PIPECONF_INTERLACED_ILK;
8543 else
8544 val |= PIPECONF_PROGRESSIVE;
8545
8546 if (intel_crtc->config->limited_color_range)
8547 val |= PIPECONF_COLOR_RANGE_SELECT;
8548
8549 I915_WRITE(PIPECONF(pipe), val);
8550 POSTING_READ(PIPECONF(pipe));
8551 }
8552
8553 /*
8554 * Set up the pipe CSC unit.
8555 *
8556 * Currently only full range RGB to limited range RGB conversion
8557 * is supported, but eventually this should handle various
8558 * RGB<->YCbCr scenarios as well.
8559 */
8560 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8561 {
8562 struct drm_device *dev = crtc->dev;
8563 struct drm_i915_private *dev_priv = dev->dev_private;
8564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8565 int pipe = intel_crtc->pipe;
8566 uint16_t coeff = 0x7800; /* 1.0 */
8567
8568 /*
8569 * TODO: Check what kind of values actually come out of the pipe
8570 * with these coeff/postoff values and adjust to get the best
8571 * accuracy. Perhaps we even need to take the bpc value into
8572 * consideration.
8573 */
8574
8575 if (intel_crtc->config->limited_color_range)
8576 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8577
8578 /*
8579 * GY/GU and RY/RU should be the other way around according
8580 * to BSpec, but reality doesn't agree. Just set them up in
8581 * a way that results in the correct picture.
8582 */
8583 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8584 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8585
8586 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8587 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8588
8589 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8590 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8591
8592 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8593 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8594 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8595
8596 if (INTEL_INFO(dev)->gen > 6) {
8597 uint16_t postoff = 0;
8598
8599 if (intel_crtc->config->limited_color_range)
8600 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8601
8602 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8603 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8604 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8605
8606 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8607 } else {
8608 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8609
8610 if (intel_crtc->config->limited_color_range)
8611 mode |= CSC_BLACK_SCREEN_OFFSET;
8612
8613 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8614 }
8615 }
8616
8617 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8618 {
8619 struct drm_device *dev = crtc->dev;
8620 struct drm_i915_private *dev_priv = dev->dev_private;
8621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8622 enum pipe pipe = intel_crtc->pipe;
8623 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8624 uint32_t val;
8625
8626 val = 0;
8627
8628 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8629 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8630
8631 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8632 val |= PIPECONF_INTERLACED_ILK;
8633 else
8634 val |= PIPECONF_PROGRESSIVE;
8635
8636 I915_WRITE(PIPECONF(cpu_transcoder), val);
8637 POSTING_READ(PIPECONF(cpu_transcoder));
8638
8639 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8640 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8641
8642 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8643 val = 0;
8644
8645 switch (intel_crtc->config->pipe_bpp) {
8646 case 18:
8647 val |= PIPEMISC_DITHER_6_BPC;
8648 break;
8649 case 24:
8650 val |= PIPEMISC_DITHER_8_BPC;
8651 break;
8652 case 30:
8653 val |= PIPEMISC_DITHER_10_BPC;
8654 break;
8655 case 36:
8656 val |= PIPEMISC_DITHER_12_BPC;
8657 break;
8658 default:
8659 /* Case prevented by pipe_config_set_bpp. */
8660 BUG();
8661 }
8662
8663 if (intel_crtc->config->dither)
8664 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8665
8666 I915_WRITE(PIPEMISC(pipe), val);
8667 }
8668 }
8669
8670 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8671 struct intel_crtc_state *crtc_state,
8672 intel_clock_t *clock,
8673 bool *has_reduced_clock,
8674 intel_clock_t *reduced_clock)
8675 {
8676 struct drm_device *dev = crtc->dev;
8677 struct drm_i915_private *dev_priv = dev->dev_private;
8678 int refclk;
8679 const intel_limit_t *limit;
8680 bool ret;
8681
8682 refclk = ironlake_get_refclk(crtc_state);
8683
8684 /*
8685 * Returns a set of divisors for the desired target clock with the given
8686 * refclk, or FALSE. The returned values represent the clock equation:
8687 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8688 */
8689 limit = intel_limit(crtc_state, refclk);
8690 ret = dev_priv->display.find_dpll(limit, crtc_state,
8691 crtc_state->port_clock,
8692 refclk, NULL, clock);
8693 if (!ret)
8694 return false;
8695
8696 return true;
8697 }
8698
8699 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8700 {
8701 /*
8702 * Account for spread spectrum to avoid
8703 * oversubscribing the link. Max center spread
8704 * is 2.5%; use 5% for safety's sake.
8705 */
8706 u32 bps = target_clock * bpp * 21 / 20;
8707 return DIV_ROUND_UP(bps, link_bw * 8);
8708 }
8709
8710 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8711 {
8712 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8713 }
8714
8715 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8716 struct intel_crtc_state *crtc_state,
8717 u32 *fp,
8718 intel_clock_t *reduced_clock, u32 *fp2)
8719 {
8720 struct drm_crtc *crtc = &intel_crtc->base;
8721 struct drm_device *dev = crtc->dev;
8722 struct drm_i915_private *dev_priv = dev->dev_private;
8723 struct drm_atomic_state *state = crtc_state->base.state;
8724 struct drm_connector *connector;
8725 struct drm_connector_state *connector_state;
8726 struct intel_encoder *encoder;
8727 uint32_t dpll;
8728 int factor, num_connectors = 0, i;
8729 bool is_lvds = false, is_sdvo = false;
8730
8731 for_each_connector_in_state(state, connector, connector_state, i) {
8732 if (connector_state->crtc != crtc_state->base.crtc)
8733 continue;
8734
8735 encoder = to_intel_encoder(connector_state->best_encoder);
8736
8737 switch (encoder->type) {
8738 case INTEL_OUTPUT_LVDS:
8739 is_lvds = true;
8740 break;
8741 case INTEL_OUTPUT_SDVO:
8742 case INTEL_OUTPUT_HDMI:
8743 is_sdvo = true;
8744 break;
8745 default:
8746 break;
8747 }
8748
8749 num_connectors++;
8750 }
8751
8752 /* Enable autotuning of the PLL clock (if permissible) */
8753 factor = 21;
8754 if (is_lvds) {
8755 if ((intel_panel_use_ssc(dev_priv) &&
8756 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8757 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8758 factor = 25;
8759 } else if (crtc_state->sdvo_tv_clock)
8760 factor = 20;
8761
8762 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8763 *fp |= FP_CB_TUNE;
8764
8765 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8766 *fp2 |= FP_CB_TUNE;
8767
8768 dpll = 0;
8769
8770 if (is_lvds)
8771 dpll |= DPLLB_MODE_LVDS;
8772 else
8773 dpll |= DPLLB_MODE_DAC_SERIAL;
8774
8775 dpll |= (crtc_state->pixel_multiplier - 1)
8776 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8777
8778 if (is_sdvo)
8779 dpll |= DPLL_SDVO_HIGH_SPEED;
8780 if (crtc_state->has_dp_encoder)
8781 dpll |= DPLL_SDVO_HIGH_SPEED;
8782
8783 /* compute bitmask from p1 value */
8784 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8785 /* also FPA1 */
8786 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8787
8788 switch (crtc_state->dpll.p2) {
8789 case 5:
8790 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8791 break;
8792 case 7:
8793 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8794 break;
8795 case 10:
8796 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8797 break;
8798 case 14:
8799 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8800 break;
8801 }
8802
8803 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8804 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8805 else
8806 dpll |= PLL_REF_INPUT_DREFCLK;
8807
8808 return dpll | DPLL_VCO_ENABLE;
8809 }
8810
8811 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8812 struct intel_crtc_state *crtc_state)
8813 {
8814 struct drm_device *dev = crtc->base.dev;
8815 intel_clock_t clock, reduced_clock;
8816 u32 dpll = 0, fp = 0, fp2 = 0;
8817 bool ok, has_reduced_clock = false;
8818 bool is_lvds = false;
8819 struct intel_shared_dpll *pll;
8820
8821 memset(&crtc_state->dpll_hw_state, 0,
8822 sizeof(crtc_state->dpll_hw_state));
8823
8824 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8825
8826 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8827 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8828
8829 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8830 &has_reduced_clock, &reduced_clock);
8831 if (!ok && !crtc_state->clock_set) {
8832 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8833 return -EINVAL;
8834 }
8835 /* Compat-code for transition, will disappear. */
8836 if (!crtc_state->clock_set) {
8837 crtc_state->dpll.n = clock.n;
8838 crtc_state->dpll.m1 = clock.m1;
8839 crtc_state->dpll.m2 = clock.m2;
8840 crtc_state->dpll.p1 = clock.p1;
8841 crtc_state->dpll.p2 = clock.p2;
8842 }
8843
8844 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8845 if (crtc_state->has_pch_encoder) {
8846 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8847 if (has_reduced_clock)
8848 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8849
8850 dpll = ironlake_compute_dpll(crtc, crtc_state,
8851 &fp, &reduced_clock,
8852 has_reduced_clock ? &fp2 : NULL);
8853
8854 crtc_state->dpll_hw_state.dpll = dpll;
8855 crtc_state->dpll_hw_state.fp0 = fp;
8856 if (has_reduced_clock)
8857 crtc_state->dpll_hw_state.fp1 = fp2;
8858 else
8859 crtc_state->dpll_hw_state.fp1 = fp;
8860
8861 pll = intel_get_shared_dpll(crtc, crtc_state);
8862 if (pll == NULL) {
8863 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8864 pipe_name(crtc->pipe));
8865 return -EINVAL;
8866 }
8867 }
8868
8869 if (is_lvds && has_reduced_clock)
8870 crtc->lowfreq_avail = true;
8871 else
8872 crtc->lowfreq_avail = false;
8873
8874 return 0;
8875 }
8876
8877 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8878 struct intel_link_m_n *m_n)
8879 {
8880 struct drm_device *dev = crtc->base.dev;
8881 struct drm_i915_private *dev_priv = dev->dev_private;
8882 enum pipe pipe = crtc->pipe;
8883
8884 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8885 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8886 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8887 & ~TU_SIZE_MASK;
8888 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8889 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8890 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8891 }
8892
8893 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8894 enum transcoder transcoder,
8895 struct intel_link_m_n *m_n,
8896 struct intel_link_m_n *m2_n2)
8897 {
8898 struct drm_device *dev = crtc->base.dev;
8899 struct drm_i915_private *dev_priv = dev->dev_private;
8900 enum pipe pipe = crtc->pipe;
8901
8902 if (INTEL_INFO(dev)->gen >= 5) {
8903 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8904 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8905 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8906 & ~TU_SIZE_MASK;
8907 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8908 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8909 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8910 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8911 * gen < 8) and if DRRS is supported (to make sure the
8912 * registers are not unnecessarily read).
8913 */
8914 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8915 crtc->config->has_drrs) {
8916 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8917 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8918 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8919 & ~TU_SIZE_MASK;
8920 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8921 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8922 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8923 }
8924 } else {
8925 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8926 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8927 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8928 & ~TU_SIZE_MASK;
8929 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8930 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8931 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8932 }
8933 }
8934
8935 void intel_dp_get_m_n(struct intel_crtc *crtc,
8936 struct intel_crtc_state *pipe_config)
8937 {
8938 if (pipe_config->has_pch_encoder)
8939 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8940 else
8941 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8942 &pipe_config->dp_m_n,
8943 &pipe_config->dp_m2_n2);
8944 }
8945
8946 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8947 struct intel_crtc_state *pipe_config)
8948 {
8949 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8950 &pipe_config->fdi_m_n, NULL);
8951 }
8952
8953 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8954 struct intel_crtc_state *pipe_config)
8955 {
8956 struct drm_device *dev = crtc->base.dev;
8957 struct drm_i915_private *dev_priv = dev->dev_private;
8958 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8959 uint32_t ps_ctrl = 0;
8960 int id = -1;
8961 int i;
8962
8963 /* find scaler attached to this pipe */
8964 for (i = 0; i < crtc->num_scalers; i++) {
8965 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8966 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8967 id = i;
8968 pipe_config->pch_pfit.enabled = true;
8969 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8970 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8971 break;
8972 }
8973 }
8974
8975 scaler_state->scaler_id = id;
8976 if (id >= 0) {
8977 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8978 } else {
8979 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8980 }
8981 }
8982
8983 static void
8984 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8985 struct intel_initial_plane_config *plane_config)
8986 {
8987 struct drm_device *dev = crtc->base.dev;
8988 struct drm_i915_private *dev_priv = dev->dev_private;
8989 u32 val, base, offset, stride_mult, tiling;
8990 int pipe = crtc->pipe;
8991 int fourcc, pixel_format;
8992 unsigned int aligned_height;
8993 struct drm_framebuffer *fb;
8994 struct intel_framebuffer *intel_fb;
8995
8996 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8997 if (!intel_fb) {
8998 DRM_DEBUG_KMS("failed to alloc fb\n");
8999 return;
9000 }
9001
9002 fb = &intel_fb->base;
9003
9004 val = I915_READ(PLANE_CTL(pipe, 0));
9005 if (!(val & PLANE_CTL_ENABLE))
9006 goto error;
9007
9008 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9009 fourcc = skl_format_to_fourcc(pixel_format,
9010 val & PLANE_CTL_ORDER_RGBX,
9011 val & PLANE_CTL_ALPHA_MASK);
9012 fb->pixel_format = fourcc;
9013 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9014
9015 tiling = val & PLANE_CTL_TILED_MASK;
9016 switch (tiling) {
9017 case PLANE_CTL_TILED_LINEAR:
9018 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9019 break;
9020 case PLANE_CTL_TILED_X:
9021 plane_config->tiling = I915_TILING_X;
9022 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9023 break;
9024 case PLANE_CTL_TILED_Y:
9025 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9026 break;
9027 case PLANE_CTL_TILED_YF:
9028 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9029 break;
9030 default:
9031 MISSING_CASE(tiling);
9032 goto error;
9033 }
9034
9035 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9036 plane_config->base = base;
9037
9038 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9039
9040 val = I915_READ(PLANE_SIZE(pipe, 0));
9041 fb->height = ((val >> 16) & 0xfff) + 1;
9042 fb->width = ((val >> 0) & 0x1fff) + 1;
9043
9044 val = I915_READ(PLANE_STRIDE(pipe, 0));
9045 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9046 fb->pixel_format);
9047 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9048
9049 aligned_height = intel_fb_align_height(dev, fb->height,
9050 fb->pixel_format,
9051 fb->modifier[0]);
9052
9053 plane_config->size = fb->pitches[0] * aligned_height;
9054
9055 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9056 pipe_name(pipe), fb->width, fb->height,
9057 fb->bits_per_pixel, base, fb->pitches[0],
9058 plane_config->size);
9059
9060 plane_config->fb = intel_fb;
9061 return;
9062
9063 error:
9064 kfree(fb);
9065 }
9066
9067 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9068 struct intel_crtc_state *pipe_config)
9069 {
9070 struct drm_device *dev = crtc->base.dev;
9071 struct drm_i915_private *dev_priv = dev->dev_private;
9072 uint32_t tmp;
9073
9074 tmp = I915_READ(PF_CTL(crtc->pipe));
9075
9076 if (tmp & PF_ENABLE) {
9077 pipe_config->pch_pfit.enabled = true;
9078 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9079 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9080
9081 /* We currently do not free assignements of panel fitters on
9082 * ivb/hsw (since we don't use the higher upscaling modes which
9083 * differentiates them) so just WARN about this case for now. */
9084 if (IS_GEN7(dev)) {
9085 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9086 PF_PIPE_SEL_IVB(crtc->pipe));
9087 }
9088 }
9089 }
9090
9091 static void
9092 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9093 struct intel_initial_plane_config *plane_config)
9094 {
9095 struct drm_device *dev = crtc->base.dev;
9096 struct drm_i915_private *dev_priv = dev->dev_private;
9097 u32 val, base, offset;
9098 int pipe = crtc->pipe;
9099 int fourcc, pixel_format;
9100 unsigned int aligned_height;
9101 struct drm_framebuffer *fb;
9102 struct intel_framebuffer *intel_fb;
9103
9104 val = I915_READ(DSPCNTR(pipe));
9105 if (!(val & DISPLAY_PLANE_ENABLE))
9106 return;
9107
9108 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9109 if (!intel_fb) {
9110 DRM_DEBUG_KMS("failed to alloc fb\n");
9111 return;
9112 }
9113
9114 fb = &intel_fb->base;
9115
9116 if (INTEL_INFO(dev)->gen >= 4) {
9117 if (val & DISPPLANE_TILED) {
9118 plane_config->tiling = I915_TILING_X;
9119 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9120 }
9121 }
9122
9123 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9124 fourcc = i9xx_format_to_fourcc(pixel_format);
9125 fb->pixel_format = fourcc;
9126 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9127
9128 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9129 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9130 offset = I915_READ(DSPOFFSET(pipe));
9131 } else {
9132 if (plane_config->tiling)
9133 offset = I915_READ(DSPTILEOFF(pipe));
9134 else
9135 offset = I915_READ(DSPLINOFF(pipe));
9136 }
9137 plane_config->base = base;
9138
9139 val = I915_READ(PIPESRC(pipe));
9140 fb->width = ((val >> 16) & 0xfff) + 1;
9141 fb->height = ((val >> 0) & 0xfff) + 1;
9142
9143 val = I915_READ(DSPSTRIDE(pipe));
9144 fb->pitches[0] = val & 0xffffffc0;
9145
9146 aligned_height = intel_fb_align_height(dev, fb->height,
9147 fb->pixel_format,
9148 fb->modifier[0]);
9149
9150 plane_config->size = fb->pitches[0] * aligned_height;
9151
9152 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9153 pipe_name(pipe), fb->width, fb->height,
9154 fb->bits_per_pixel, base, fb->pitches[0],
9155 plane_config->size);
9156
9157 plane_config->fb = intel_fb;
9158 }
9159
9160 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9161 struct intel_crtc_state *pipe_config)
9162 {
9163 struct drm_device *dev = crtc->base.dev;
9164 struct drm_i915_private *dev_priv = dev->dev_private;
9165 uint32_t tmp;
9166
9167 if (!intel_display_power_is_enabled(dev_priv,
9168 POWER_DOMAIN_PIPE(crtc->pipe)))
9169 return false;
9170
9171 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9172 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9173
9174 tmp = I915_READ(PIPECONF(crtc->pipe));
9175 if (!(tmp & PIPECONF_ENABLE))
9176 return false;
9177
9178 switch (tmp & PIPECONF_BPC_MASK) {
9179 case PIPECONF_6BPC:
9180 pipe_config->pipe_bpp = 18;
9181 break;
9182 case PIPECONF_8BPC:
9183 pipe_config->pipe_bpp = 24;
9184 break;
9185 case PIPECONF_10BPC:
9186 pipe_config->pipe_bpp = 30;
9187 break;
9188 case PIPECONF_12BPC:
9189 pipe_config->pipe_bpp = 36;
9190 break;
9191 default:
9192 break;
9193 }
9194
9195 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9196 pipe_config->limited_color_range = true;
9197
9198 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9199 struct intel_shared_dpll *pll;
9200
9201 pipe_config->has_pch_encoder = true;
9202
9203 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9204 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9205 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9206
9207 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9208
9209 if (HAS_PCH_IBX(dev_priv->dev)) {
9210 pipe_config->shared_dpll =
9211 (enum intel_dpll_id) crtc->pipe;
9212 } else {
9213 tmp = I915_READ(PCH_DPLL_SEL);
9214 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9215 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9216 else
9217 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9218 }
9219
9220 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9221
9222 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9223 &pipe_config->dpll_hw_state));
9224
9225 tmp = pipe_config->dpll_hw_state.dpll;
9226 pipe_config->pixel_multiplier =
9227 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9228 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9229
9230 ironlake_pch_clock_get(crtc, pipe_config);
9231 } else {
9232 pipe_config->pixel_multiplier = 1;
9233 }
9234
9235 intel_get_pipe_timings(crtc, pipe_config);
9236
9237 ironlake_get_pfit_config(crtc, pipe_config);
9238
9239 return true;
9240 }
9241
9242 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9243 {
9244 struct drm_device *dev = dev_priv->dev;
9245 struct intel_crtc *crtc;
9246
9247 for_each_intel_crtc(dev, crtc)
9248 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9249 pipe_name(crtc->pipe));
9250
9251 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9252 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9253 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9254 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9255 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9256 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9257 "CPU PWM1 enabled\n");
9258 if (IS_HASWELL(dev))
9259 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9260 "CPU PWM2 enabled\n");
9261 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9262 "PCH PWM1 enabled\n");
9263 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9264 "Utility pin enabled\n");
9265 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9266
9267 /*
9268 * In theory we can still leave IRQs enabled, as long as only the HPD
9269 * interrupts remain enabled. We used to check for that, but since it's
9270 * gen-specific and since we only disable LCPLL after we fully disable
9271 * the interrupts, the check below should be enough.
9272 */
9273 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9274 }
9275
9276 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9277 {
9278 struct drm_device *dev = dev_priv->dev;
9279
9280 if (IS_HASWELL(dev))
9281 return I915_READ(D_COMP_HSW);
9282 else
9283 return I915_READ(D_COMP_BDW);
9284 }
9285
9286 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9287 {
9288 struct drm_device *dev = dev_priv->dev;
9289
9290 if (IS_HASWELL(dev)) {
9291 mutex_lock(&dev_priv->rps.hw_lock);
9292 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9293 val))
9294 DRM_ERROR("Failed to write to D_COMP\n");
9295 mutex_unlock(&dev_priv->rps.hw_lock);
9296 } else {
9297 I915_WRITE(D_COMP_BDW, val);
9298 POSTING_READ(D_COMP_BDW);
9299 }
9300 }
9301
9302 /*
9303 * This function implements pieces of two sequences from BSpec:
9304 * - Sequence for display software to disable LCPLL
9305 * - Sequence for display software to allow package C8+
9306 * The steps implemented here are just the steps that actually touch the LCPLL
9307 * register. Callers should take care of disabling all the display engine
9308 * functions, doing the mode unset, fixing interrupts, etc.
9309 */
9310 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9311 bool switch_to_fclk, bool allow_power_down)
9312 {
9313 uint32_t val;
9314
9315 assert_can_disable_lcpll(dev_priv);
9316
9317 val = I915_READ(LCPLL_CTL);
9318
9319 if (switch_to_fclk) {
9320 val |= LCPLL_CD_SOURCE_FCLK;
9321 I915_WRITE(LCPLL_CTL, val);
9322
9323 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9324 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9325 DRM_ERROR("Switching to FCLK failed\n");
9326
9327 val = I915_READ(LCPLL_CTL);
9328 }
9329
9330 val |= LCPLL_PLL_DISABLE;
9331 I915_WRITE(LCPLL_CTL, val);
9332 POSTING_READ(LCPLL_CTL);
9333
9334 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9335 DRM_ERROR("LCPLL still locked\n");
9336
9337 val = hsw_read_dcomp(dev_priv);
9338 val |= D_COMP_COMP_DISABLE;
9339 hsw_write_dcomp(dev_priv, val);
9340 ndelay(100);
9341
9342 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9343 1))
9344 DRM_ERROR("D_COMP RCOMP still in progress\n");
9345
9346 if (allow_power_down) {
9347 val = I915_READ(LCPLL_CTL);
9348 val |= LCPLL_POWER_DOWN_ALLOW;
9349 I915_WRITE(LCPLL_CTL, val);
9350 POSTING_READ(LCPLL_CTL);
9351 }
9352 }
9353
9354 /*
9355 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9356 * source.
9357 */
9358 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9359 {
9360 uint32_t val;
9361
9362 val = I915_READ(LCPLL_CTL);
9363
9364 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9365 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9366 return;
9367
9368 /*
9369 * Make sure we're not on PC8 state before disabling PC8, otherwise
9370 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9371 */
9372 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9373
9374 if (val & LCPLL_POWER_DOWN_ALLOW) {
9375 val &= ~LCPLL_POWER_DOWN_ALLOW;
9376 I915_WRITE(LCPLL_CTL, val);
9377 POSTING_READ(LCPLL_CTL);
9378 }
9379
9380 val = hsw_read_dcomp(dev_priv);
9381 val |= D_COMP_COMP_FORCE;
9382 val &= ~D_COMP_COMP_DISABLE;
9383 hsw_write_dcomp(dev_priv, val);
9384
9385 val = I915_READ(LCPLL_CTL);
9386 val &= ~LCPLL_PLL_DISABLE;
9387 I915_WRITE(LCPLL_CTL, val);
9388
9389 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9390 DRM_ERROR("LCPLL not locked yet\n");
9391
9392 if (val & LCPLL_CD_SOURCE_FCLK) {
9393 val = I915_READ(LCPLL_CTL);
9394 val &= ~LCPLL_CD_SOURCE_FCLK;
9395 I915_WRITE(LCPLL_CTL, val);
9396
9397 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9398 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9399 DRM_ERROR("Switching back to LCPLL failed\n");
9400 }
9401
9402 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9403 intel_update_cdclk(dev_priv->dev);
9404 }
9405
9406 /*
9407 * Package states C8 and deeper are really deep PC states that can only be
9408 * reached when all the devices on the system allow it, so even if the graphics
9409 * device allows PC8+, it doesn't mean the system will actually get to these
9410 * states. Our driver only allows PC8+ when going into runtime PM.
9411 *
9412 * The requirements for PC8+ are that all the outputs are disabled, the power
9413 * well is disabled and most interrupts are disabled, and these are also
9414 * requirements for runtime PM. When these conditions are met, we manually do
9415 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9416 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9417 * hang the machine.
9418 *
9419 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9420 * the state of some registers, so when we come back from PC8+ we need to
9421 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9422 * need to take care of the registers kept by RC6. Notice that this happens even
9423 * if we don't put the device in PCI D3 state (which is what currently happens
9424 * because of the runtime PM support).
9425 *
9426 * For more, read "Display Sequences for Package C8" on the hardware
9427 * documentation.
9428 */
9429 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9430 {
9431 struct drm_device *dev = dev_priv->dev;
9432 uint32_t val;
9433
9434 DRM_DEBUG_KMS("Enabling package C8+\n");
9435
9436 if (HAS_PCH_LPT_LP(dev)) {
9437 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9438 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9439 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9440 }
9441
9442 lpt_disable_clkout_dp(dev);
9443 hsw_disable_lcpll(dev_priv, true, true);
9444 }
9445
9446 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9447 {
9448 struct drm_device *dev = dev_priv->dev;
9449 uint32_t val;
9450
9451 DRM_DEBUG_KMS("Disabling package C8+\n");
9452
9453 hsw_restore_lcpll(dev_priv);
9454 lpt_init_pch_refclk(dev);
9455
9456 if (HAS_PCH_LPT_LP(dev)) {
9457 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9458 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9459 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9460 }
9461
9462 intel_prepare_ddi(dev);
9463 }
9464
9465 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9466 {
9467 struct drm_device *dev = old_state->dev;
9468 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9469
9470 broxton_set_cdclk(dev, req_cdclk);
9471 }
9472
9473 /* compute the max rate for new configuration */
9474 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9475 {
9476 struct intel_crtc *intel_crtc;
9477 struct intel_crtc_state *crtc_state;
9478 int max_pixel_rate = 0;
9479
9480 for_each_intel_crtc(state->dev, intel_crtc) {
9481 int pixel_rate;
9482
9483 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9484 if (IS_ERR(crtc_state))
9485 return PTR_ERR(crtc_state);
9486
9487 if (!crtc_state->base.enable)
9488 continue;
9489
9490 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9491
9492 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9493 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9494 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9495
9496 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9497 }
9498
9499 return max_pixel_rate;
9500 }
9501
9502 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9503 {
9504 struct drm_i915_private *dev_priv = dev->dev_private;
9505 uint32_t val, data;
9506 int ret;
9507
9508 if (WARN((I915_READ(LCPLL_CTL) &
9509 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9510 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9511 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9512 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9513 "trying to change cdclk frequency with cdclk not enabled\n"))
9514 return;
9515
9516 mutex_lock(&dev_priv->rps.hw_lock);
9517 ret = sandybridge_pcode_write(dev_priv,
9518 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9519 mutex_unlock(&dev_priv->rps.hw_lock);
9520 if (ret) {
9521 DRM_ERROR("failed to inform pcode about cdclk change\n");
9522 return;
9523 }
9524
9525 val = I915_READ(LCPLL_CTL);
9526 val |= LCPLL_CD_SOURCE_FCLK;
9527 I915_WRITE(LCPLL_CTL, val);
9528
9529 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9530 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9531 DRM_ERROR("Switching to FCLK failed\n");
9532
9533 val = I915_READ(LCPLL_CTL);
9534 val &= ~LCPLL_CLK_FREQ_MASK;
9535
9536 switch (cdclk) {
9537 case 450000:
9538 val |= LCPLL_CLK_FREQ_450;
9539 data = 0;
9540 break;
9541 case 540000:
9542 val |= LCPLL_CLK_FREQ_54O_BDW;
9543 data = 1;
9544 break;
9545 case 337500:
9546 val |= LCPLL_CLK_FREQ_337_5_BDW;
9547 data = 2;
9548 break;
9549 case 675000:
9550 val |= LCPLL_CLK_FREQ_675_BDW;
9551 data = 3;
9552 break;
9553 default:
9554 WARN(1, "invalid cdclk frequency\n");
9555 return;
9556 }
9557
9558 I915_WRITE(LCPLL_CTL, val);
9559
9560 val = I915_READ(LCPLL_CTL);
9561 val &= ~LCPLL_CD_SOURCE_FCLK;
9562 I915_WRITE(LCPLL_CTL, val);
9563
9564 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9565 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9566 DRM_ERROR("Switching back to LCPLL failed\n");
9567
9568 mutex_lock(&dev_priv->rps.hw_lock);
9569 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9570 mutex_unlock(&dev_priv->rps.hw_lock);
9571
9572 intel_update_cdclk(dev);
9573
9574 WARN(cdclk != dev_priv->cdclk_freq,
9575 "cdclk requested %d kHz but got %d kHz\n",
9576 cdclk, dev_priv->cdclk_freq);
9577 }
9578
9579 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9580 {
9581 struct drm_i915_private *dev_priv = to_i915(state->dev);
9582 int max_pixclk = ilk_max_pixel_rate(state);
9583 int cdclk;
9584
9585 /*
9586 * FIXME should also account for plane ratio
9587 * once 64bpp pixel formats are supported.
9588 */
9589 if (max_pixclk > 540000)
9590 cdclk = 675000;
9591 else if (max_pixclk > 450000)
9592 cdclk = 540000;
9593 else if (max_pixclk > 337500)
9594 cdclk = 450000;
9595 else
9596 cdclk = 337500;
9597
9598 /*
9599 * FIXME move the cdclk caclulation to
9600 * compute_config() so we can fail gracegully.
9601 */
9602 if (cdclk > dev_priv->max_cdclk_freq) {
9603 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9604 cdclk, dev_priv->max_cdclk_freq);
9605 cdclk = dev_priv->max_cdclk_freq;
9606 }
9607
9608 to_intel_atomic_state(state)->cdclk = cdclk;
9609
9610 return 0;
9611 }
9612
9613 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9614 {
9615 struct drm_device *dev = old_state->dev;
9616 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9617
9618 broadwell_set_cdclk(dev, req_cdclk);
9619 }
9620
9621 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9622 struct intel_crtc_state *crtc_state)
9623 {
9624 if (!intel_ddi_pll_select(crtc, crtc_state))
9625 return -EINVAL;
9626
9627 crtc->lowfreq_avail = false;
9628
9629 return 0;
9630 }
9631
9632 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9633 enum port port,
9634 struct intel_crtc_state *pipe_config)
9635 {
9636 switch (port) {
9637 case PORT_A:
9638 pipe_config->ddi_pll_sel = SKL_DPLL0;
9639 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9640 break;
9641 case PORT_B:
9642 pipe_config->ddi_pll_sel = SKL_DPLL1;
9643 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9644 break;
9645 case PORT_C:
9646 pipe_config->ddi_pll_sel = SKL_DPLL2;
9647 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9648 break;
9649 default:
9650 DRM_ERROR("Incorrect port type\n");
9651 }
9652 }
9653
9654 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9655 enum port port,
9656 struct intel_crtc_state *pipe_config)
9657 {
9658 u32 temp, dpll_ctl1;
9659
9660 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9661 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9662
9663 switch (pipe_config->ddi_pll_sel) {
9664 case SKL_DPLL0:
9665 /*
9666 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9667 * of the shared DPLL framework and thus needs to be read out
9668 * separately
9669 */
9670 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9671 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9672 break;
9673 case SKL_DPLL1:
9674 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9675 break;
9676 case SKL_DPLL2:
9677 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9678 break;
9679 case SKL_DPLL3:
9680 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9681 break;
9682 }
9683 }
9684
9685 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9686 enum port port,
9687 struct intel_crtc_state *pipe_config)
9688 {
9689 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9690
9691 switch (pipe_config->ddi_pll_sel) {
9692 case PORT_CLK_SEL_WRPLL1:
9693 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9694 break;
9695 case PORT_CLK_SEL_WRPLL2:
9696 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9697 break;
9698 }
9699 }
9700
9701 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9702 struct intel_crtc_state *pipe_config)
9703 {
9704 struct drm_device *dev = crtc->base.dev;
9705 struct drm_i915_private *dev_priv = dev->dev_private;
9706 struct intel_shared_dpll *pll;
9707 enum port port;
9708 uint32_t tmp;
9709
9710 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9711
9712 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9713
9714 if (IS_SKYLAKE(dev))
9715 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9716 else if (IS_BROXTON(dev))
9717 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9718 else
9719 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9720
9721 if (pipe_config->shared_dpll >= 0) {
9722 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9723
9724 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9725 &pipe_config->dpll_hw_state));
9726 }
9727
9728 /*
9729 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9730 * DDI E. So just check whether this pipe is wired to DDI E and whether
9731 * the PCH transcoder is on.
9732 */
9733 if (INTEL_INFO(dev)->gen < 9 &&
9734 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9735 pipe_config->has_pch_encoder = true;
9736
9737 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9738 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9739 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9740
9741 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9742 }
9743 }
9744
9745 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9746 struct intel_crtc_state *pipe_config)
9747 {
9748 struct drm_device *dev = crtc->base.dev;
9749 struct drm_i915_private *dev_priv = dev->dev_private;
9750 enum intel_display_power_domain pfit_domain;
9751 uint32_t tmp;
9752
9753 if (!intel_display_power_is_enabled(dev_priv,
9754 POWER_DOMAIN_PIPE(crtc->pipe)))
9755 return false;
9756
9757 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9758 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9759
9760 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9761 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9762 enum pipe trans_edp_pipe;
9763 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9764 default:
9765 WARN(1, "unknown pipe linked to edp transcoder\n");
9766 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9767 case TRANS_DDI_EDP_INPUT_A_ON:
9768 trans_edp_pipe = PIPE_A;
9769 break;
9770 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9771 trans_edp_pipe = PIPE_B;
9772 break;
9773 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9774 trans_edp_pipe = PIPE_C;
9775 break;
9776 }
9777
9778 if (trans_edp_pipe == crtc->pipe)
9779 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9780 }
9781
9782 if (!intel_display_power_is_enabled(dev_priv,
9783 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9784 return false;
9785
9786 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9787 if (!(tmp & PIPECONF_ENABLE))
9788 return false;
9789
9790 haswell_get_ddi_port_state(crtc, pipe_config);
9791
9792 intel_get_pipe_timings(crtc, pipe_config);
9793
9794 if (INTEL_INFO(dev)->gen >= 9) {
9795 skl_init_scalers(dev, crtc, pipe_config);
9796 }
9797
9798 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9799
9800 if (INTEL_INFO(dev)->gen >= 9) {
9801 pipe_config->scaler_state.scaler_id = -1;
9802 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9803 }
9804
9805 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9806 if (INTEL_INFO(dev)->gen >= 9)
9807 skylake_get_pfit_config(crtc, pipe_config);
9808 else
9809 ironlake_get_pfit_config(crtc, pipe_config);
9810 }
9811
9812 if (IS_HASWELL(dev))
9813 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9814 (I915_READ(IPS_CTL) & IPS_ENABLE);
9815
9816 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9817 pipe_config->pixel_multiplier =
9818 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9819 } else {
9820 pipe_config->pixel_multiplier = 1;
9821 }
9822
9823 return true;
9824 }
9825
9826 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9827 {
9828 struct drm_device *dev = crtc->dev;
9829 struct drm_i915_private *dev_priv = dev->dev_private;
9830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9831 uint32_t cntl = 0, size = 0;
9832
9833 if (base) {
9834 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9835 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9836 unsigned int stride = roundup_pow_of_two(width) * 4;
9837
9838 switch (stride) {
9839 default:
9840 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9841 width, stride);
9842 stride = 256;
9843 /* fallthrough */
9844 case 256:
9845 case 512:
9846 case 1024:
9847 case 2048:
9848 break;
9849 }
9850
9851 cntl |= CURSOR_ENABLE |
9852 CURSOR_GAMMA_ENABLE |
9853 CURSOR_FORMAT_ARGB |
9854 CURSOR_STRIDE(stride);
9855
9856 size = (height << 12) | width;
9857 }
9858
9859 if (intel_crtc->cursor_cntl != 0 &&
9860 (intel_crtc->cursor_base != base ||
9861 intel_crtc->cursor_size != size ||
9862 intel_crtc->cursor_cntl != cntl)) {
9863 /* On these chipsets we can only modify the base/size/stride
9864 * whilst the cursor is disabled.
9865 */
9866 I915_WRITE(CURCNTR(PIPE_A), 0);
9867 POSTING_READ(CURCNTR(PIPE_A));
9868 intel_crtc->cursor_cntl = 0;
9869 }
9870
9871 if (intel_crtc->cursor_base != base) {
9872 I915_WRITE(CURBASE(PIPE_A), base);
9873 intel_crtc->cursor_base = base;
9874 }
9875
9876 if (intel_crtc->cursor_size != size) {
9877 I915_WRITE(CURSIZE, size);
9878 intel_crtc->cursor_size = size;
9879 }
9880
9881 if (intel_crtc->cursor_cntl != cntl) {
9882 I915_WRITE(CURCNTR(PIPE_A), cntl);
9883 POSTING_READ(CURCNTR(PIPE_A));
9884 intel_crtc->cursor_cntl = cntl;
9885 }
9886 }
9887
9888 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9889 {
9890 struct drm_device *dev = crtc->dev;
9891 struct drm_i915_private *dev_priv = dev->dev_private;
9892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9893 int pipe = intel_crtc->pipe;
9894 uint32_t cntl;
9895
9896 cntl = 0;
9897 if (base) {
9898 cntl = MCURSOR_GAMMA_ENABLE;
9899 switch (intel_crtc->base.cursor->state->crtc_w) {
9900 case 64:
9901 cntl |= CURSOR_MODE_64_ARGB_AX;
9902 break;
9903 case 128:
9904 cntl |= CURSOR_MODE_128_ARGB_AX;
9905 break;
9906 case 256:
9907 cntl |= CURSOR_MODE_256_ARGB_AX;
9908 break;
9909 default:
9910 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9911 return;
9912 }
9913 cntl |= pipe << 28; /* Connect to correct pipe */
9914
9915 if (HAS_DDI(dev))
9916 cntl |= CURSOR_PIPE_CSC_ENABLE;
9917 }
9918
9919 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9920 cntl |= CURSOR_ROTATE_180;
9921
9922 if (intel_crtc->cursor_cntl != cntl) {
9923 I915_WRITE(CURCNTR(pipe), cntl);
9924 POSTING_READ(CURCNTR(pipe));
9925 intel_crtc->cursor_cntl = cntl;
9926 }
9927
9928 /* and commit changes on next vblank */
9929 I915_WRITE(CURBASE(pipe), base);
9930 POSTING_READ(CURBASE(pipe));
9931
9932 intel_crtc->cursor_base = base;
9933 }
9934
9935 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9936 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9937 bool on)
9938 {
9939 struct drm_device *dev = crtc->dev;
9940 struct drm_i915_private *dev_priv = dev->dev_private;
9941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9942 int pipe = intel_crtc->pipe;
9943 struct drm_plane_state *cursor_state = crtc->cursor->state;
9944 int x = cursor_state->crtc_x;
9945 int y = cursor_state->crtc_y;
9946 u32 base = 0, pos = 0;
9947
9948 if (on)
9949 base = intel_crtc->cursor_addr;
9950
9951 if (x >= intel_crtc->config->pipe_src_w)
9952 base = 0;
9953
9954 if (y >= intel_crtc->config->pipe_src_h)
9955 base = 0;
9956
9957 if (x < 0) {
9958 if (x + cursor_state->crtc_w <= 0)
9959 base = 0;
9960
9961 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9962 x = -x;
9963 }
9964 pos |= x << CURSOR_X_SHIFT;
9965
9966 if (y < 0) {
9967 if (y + cursor_state->crtc_h <= 0)
9968 base = 0;
9969
9970 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9971 y = -y;
9972 }
9973 pos |= y << CURSOR_Y_SHIFT;
9974
9975 if (base == 0 && intel_crtc->cursor_base == 0)
9976 return;
9977
9978 I915_WRITE(CURPOS(pipe), pos);
9979
9980 /* ILK+ do this automagically */
9981 if (HAS_GMCH_DISPLAY(dev) &&
9982 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9983 base += (cursor_state->crtc_h *
9984 cursor_state->crtc_w - 1) * 4;
9985 }
9986
9987 if (IS_845G(dev) || IS_I865G(dev))
9988 i845_update_cursor(crtc, base);
9989 else
9990 i9xx_update_cursor(crtc, base);
9991 }
9992
9993 static bool cursor_size_ok(struct drm_device *dev,
9994 uint32_t width, uint32_t height)
9995 {
9996 if (width == 0 || height == 0)
9997 return false;
9998
9999 /*
10000 * 845g/865g are special in that they are only limited by
10001 * the width of their cursors, the height is arbitrary up to
10002 * the precision of the register. Everything else requires
10003 * square cursors, limited to a few power-of-two sizes.
10004 */
10005 if (IS_845G(dev) || IS_I865G(dev)) {
10006 if ((width & 63) != 0)
10007 return false;
10008
10009 if (width > (IS_845G(dev) ? 64 : 512))
10010 return false;
10011
10012 if (height > 1023)
10013 return false;
10014 } else {
10015 switch (width | height) {
10016 case 256:
10017 case 128:
10018 if (IS_GEN2(dev))
10019 return false;
10020 case 64:
10021 break;
10022 default:
10023 return false;
10024 }
10025 }
10026
10027 return true;
10028 }
10029
10030 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10031 u16 *blue, uint32_t start, uint32_t size)
10032 {
10033 int end = (start + size > 256) ? 256 : start + size, i;
10034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10035
10036 for (i = start; i < end; i++) {
10037 intel_crtc->lut_r[i] = red[i] >> 8;
10038 intel_crtc->lut_g[i] = green[i] >> 8;
10039 intel_crtc->lut_b[i] = blue[i] >> 8;
10040 }
10041
10042 intel_crtc_load_lut(crtc);
10043 }
10044
10045 /* VESA 640x480x72Hz mode to set on the pipe */
10046 static struct drm_display_mode load_detect_mode = {
10047 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10048 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10049 };
10050
10051 struct drm_framebuffer *
10052 __intel_framebuffer_create(struct drm_device *dev,
10053 struct drm_mode_fb_cmd2 *mode_cmd,
10054 struct drm_i915_gem_object *obj)
10055 {
10056 struct intel_framebuffer *intel_fb;
10057 int ret;
10058
10059 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10060 if (!intel_fb) {
10061 drm_gem_object_unreference(&obj->base);
10062 return ERR_PTR(-ENOMEM);
10063 }
10064
10065 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10066 if (ret)
10067 goto err;
10068
10069 return &intel_fb->base;
10070 err:
10071 drm_gem_object_unreference(&obj->base);
10072 kfree(intel_fb);
10073
10074 return ERR_PTR(ret);
10075 }
10076
10077 static struct drm_framebuffer *
10078 intel_framebuffer_create(struct drm_device *dev,
10079 struct drm_mode_fb_cmd2 *mode_cmd,
10080 struct drm_i915_gem_object *obj)
10081 {
10082 struct drm_framebuffer *fb;
10083 int ret;
10084
10085 ret = i915_mutex_lock_interruptible(dev);
10086 if (ret)
10087 return ERR_PTR(ret);
10088 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10089 mutex_unlock(&dev->struct_mutex);
10090
10091 return fb;
10092 }
10093
10094 static u32
10095 intel_framebuffer_pitch_for_width(int width, int bpp)
10096 {
10097 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10098 return ALIGN(pitch, 64);
10099 }
10100
10101 static u32
10102 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10103 {
10104 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10105 return PAGE_ALIGN(pitch * mode->vdisplay);
10106 }
10107
10108 static struct drm_framebuffer *
10109 intel_framebuffer_create_for_mode(struct drm_device *dev,
10110 struct drm_display_mode *mode,
10111 int depth, int bpp)
10112 {
10113 struct drm_i915_gem_object *obj;
10114 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10115
10116 obj = i915_gem_alloc_object(dev,
10117 intel_framebuffer_size_for_mode(mode, bpp));
10118 if (obj == NULL)
10119 return ERR_PTR(-ENOMEM);
10120
10121 mode_cmd.width = mode->hdisplay;
10122 mode_cmd.height = mode->vdisplay;
10123 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10124 bpp);
10125 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10126
10127 return intel_framebuffer_create(dev, &mode_cmd, obj);
10128 }
10129
10130 static struct drm_framebuffer *
10131 mode_fits_in_fbdev(struct drm_device *dev,
10132 struct drm_display_mode *mode)
10133 {
10134 #ifdef CONFIG_DRM_FBDEV_EMULATION
10135 struct drm_i915_private *dev_priv = dev->dev_private;
10136 struct drm_i915_gem_object *obj;
10137 struct drm_framebuffer *fb;
10138
10139 if (!dev_priv->fbdev)
10140 return NULL;
10141
10142 if (!dev_priv->fbdev->fb)
10143 return NULL;
10144
10145 obj = dev_priv->fbdev->fb->obj;
10146 BUG_ON(!obj);
10147
10148 fb = &dev_priv->fbdev->fb->base;
10149 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10150 fb->bits_per_pixel))
10151 return NULL;
10152
10153 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10154 return NULL;
10155
10156 return fb;
10157 #else
10158 return NULL;
10159 #endif
10160 }
10161
10162 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10163 struct drm_crtc *crtc,
10164 struct drm_display_mode *mode,
10165 struct drm_framebuffer *fb,
10166 int x, int y)
10167 {
10168 struct drm_plane_state *plane_state;
10169 int hdisplay, vdisplay;
10170 int ret;
10171
10172 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10173 if (IS_ERR(plane_state))
10174 return PTR_ERR(plane_state);
10175
10176 if (mode)
10177 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10178 else
10179 hdisplay = vdisplay = 0;
10180
10181 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10182 if (ret)
10183 return ret;
10184 drm_atomic_set_fb_for_plane(plane_state, fb);
10185 plane_state->crtc_x = 0;
10186 plane_state->crtc_y = 0;
10187 plane_state->crtc_w = hdisplay;
10188 plane_state->crtc_h = vdisplay;
10189 plane_state->src_x = x << 16;
10190 plane_state->src_y = y << 16;
10191 plane_state->src_w = hdisplay << 16;
10192 plane_state->src_h = vdisplay << 16;
10193
10194 return 0;
10195 }
10196
10197 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10198 struct drm_display_mode *mode,
10199 struct intel_load_detect_pipe *old,
10200 struct drm_modeset_acquire_ctx *ctx)
10201 {
10202 struct intel_crtc *intel_crtc;
10203 struct intel_encoder *intel_encoder =
10204 intel_attached_encoder(connector);
10205 struct drm_crtc *possible_crtc;
10206 struct drm_encoder *encoder = &intel_encoder->base;
10207 struct drm_crtc *crtc = NULL;
10208 struct drm_device *dev = encoder->dev;
10209 struct drm_framebuffer *fb;
10210 struct drm_mode_config *config = &dev->mode_config;
10211 struct drm_atomic_state *state = NULL;
10212 struct drm_connector_state *connector_state;
10213 struct intel_crtc_state *crtc_state;
10214 int ret, i = -1;
10215
10216 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10217 connector->base.id, connector->name,
10218 encoder->base.id, encoder->name);
10219
10220 retry:
10221 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10222 if (ret)
10223 goto fail;
10224
10225 /*
10226 * Algorithm gets a little messy:
10227 *
10228 * - if the connector already has an assigned crtc, use it (but make
10229 * sure it's on first)
10230 *
10231 * - try to find the first unused crtc that can drive this connector,
10232 * and use that if we find one
10233 */
10234
10235 /* See if we already have a CRTC for this connector */
10236 if (encoder->crtc) {
10237 crtc = encoder->crtc;
10238
10239 ret = drm_modeset_lock(&crtc->mutex, ctx);
10240 if (ret)
10241 goto fail;
10242 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10243 if (ret)
10244 goto fail;
10245
10246 old->dpms_mode = connector->dpms;
10247 old->load_detect_temp = false;
10248
10249 /* Make sure the crtc and connector are running */
10250 if (connector->dpms != DRM_MODE_DPMS_ON)
10251 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10252
10253 return true;
10254 }
10255
10256 /* Find an unused one (if possible) */
10257 for_each_crtc(dev, possible_crtc) {
10258 i++;
10259 if (!(encoder->possible_crtcs & (1 << i)))
10260 continue;
10261 if (possible_crtc->state->enable)
10262 continue;
10263
10264 crtc = possible_crtc;
10265 break;
10266 }
10267
10268 /*
10269 * If we didn't find an unused CRTC, don't use any.
10270 */
10271 if (!crtc) {
10272 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10273 goto fail;
10274 }
10275
10276 ret = drm_modeset_lock(&crtc->mutex, ctx);
10277 if (ret)
10278 goto fail;
10279 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10280 if (ret)
10281 goto fail;
10282
10283 intel_crtc = to_intel_crtc(crtc);
10284 old->dpms_mode = connector->dpms;
10285 old->load_detect_temp = true;
10286 old->release_fb = NULL;
10287
10288 state = drm_atomic_state_alloc(dev);
10289 if (!state)
10290 return false;
10291
10292 state->acquire_ctx = ctx;
10293
10294 connector_state = drm_atomic_get_connector_state(state, connector);
10295 if (IS_ERR(connector_state)) {
10296 ret = PTR_ERR(connector_state);
10297 goto fail;
10298 }
10299
10300 connector_state->crtc = crtc;
10301 connector_state->best_encoder = &intel_encoder->base;
10302
10303 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10304 if (IS_ERR(crtc_state)) {
10305 ret = PTR_ERR(crtc_state);
10306 goto fail;
10307 }
10308
10309 crtc_state->base.active = crtc_state->base.enable = true;
10310
10311 if (!mode)
10312 mode = &load_detect_mode;
10313
10314 /* We need a framebuffer large enough to accommodate all accesses
10315 * that the plane may generate whilst we perform load detection.
10316 * We can not rely on the fbcon either being present (we get called
10317 * during its initialisation to detect all boot displays, or it may
10318 * not even exist) or that it is large enough to satisfy the
10319 * requested mode.
10320 */
10321 fb = mode_fits_in_fbdev(dev, mode);
10322 if (fb == NULL) {
10323 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10324 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10325 old->release_fb = fb;
10326 } else
10327 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10328 if (IS_ERR(fb)) {
10329 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10330 goto fail;
10331 }
10332
10333 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10334 if (ret)
10335 goto fail;
10336
10337 drm_mode_copy(&crtc_state->base.mode, mode);
10338
10339 if (drm_atomic_commit(state)) {
10340 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10341 if (old->release_fb)
10342 old->release_fb->funcs->destroy(old->release_fb);
10343 goto fail;
10344 }
10345 crtc->primary->crtc = crtc;
10346
10347 /* let the connector get through one full cycle before testing */
10348 intel_wait_for_vblank(dev, intel_crtc->pipe);
10349 return true;
10350
10351 fail:
10352 drm_atomic_state_free(state);
10353 state = NULL;
10354
10355 if (ret == -EDEADLK) {
10356 drm_modeset_backoff(ctx);
10357 goto retry;
10358 }
10359
10360 return false;
10361 }
10362
10363 void intel_release_load_detect_pipe(struct drm_connector *connector,
10364 struct intel_load_detect_pipe *old,
10365 struct drm_modeset_acquire_ctx *ctx)
10366 {
10367 struct drm_device *dev = connector->dev;
10368 struct intel_encoder *intel_encoder =
10369 intel_attached_encoder(connector);
10370 struct drm_encoder *encoder = &intel_encoder->base;
10371 struct drm_crtc *crtc = encoder->crtc;
10372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10373 struct drm_atomic_state *state;
10374 struct drm_connector_state *connector_state;
10375 struct intel_crtc_state *crtc_state;
10376 int ret;
10377
10378 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10379 connector->base.id, connector->name,
10380 encoder->base.id, encoder->name);
10381
10382 if (old->load_detect_temp) {
10383 state = drm_atomic_state_alloc(dev);
10384 if (!state)
10385 goto fail;
10386
10387 state->acquire_ctx = ctx;
10388
10389 connector_state = drm_atomic_get_connector_state(state, connector);
10390 if (IS_ERR(connector_state))
10391 goto fail;
10392
10393 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10394 if (IS_ERR(crtc_state))
10395 goto fail;
10396
10397 connector_state->best_encoder = NULL;
10398 connector_state->crtc = NULL;
10399
10400 crtc_state->base.enable = crtc_state->base.active = false;
10401
10402 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10403 0, 0);
10404 if (ret)
10405 goto fail;
10406
10407 ret = drm_atomic_commit(state);
10408 if (ret)
10409 goto fail;
10410
10411 if (old->release_fb) {
10412 drm_framebuffer_unregister_private(old->release_fb);
10413 drm_framebuffer_unreference(old->release_fb);
10414 }
10415
10416 return;
10417 }
10418
10419 /* Switch crtc and encoder back off if necessary */
10420 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10421 connector->funcs->dpms(connector, old->dpms_mode);
10422
10423 return;
10424 fail:
10425 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10426 drm_atomic_state_free(state);
10427 }
10428
10429 static int i9xx_pll_refclk(struct drm_device *dev,
10430 const struct intel_crtc_state *pipe_config)
10431 {
10432 struct drm_i915_private *dev_priv = dev->dev_private;
10433 u32 dpll = pipe_config->dpll_hw_state.dpll;
10434
10435 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10436 return dev_priv->vbt.lvds_ssc_freq;
10437 else if (HAS_PCH_SPLIT(dev))
10438 return 120000;
10439 else if (!IS_GEN2(dev))
10440 return 96000;
10441 else
10442 return 48000;
10443 }
10444
10445 /* Returns the clock of the currently programmed mode of the given pipe. */
10446 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10447 struct intel_crtc_state *pipe_config)
10448 {
10449 struct drm_device *dev = crtc->base.dev;
10450 struct drm_i915_private *dev_priv = dev->dev_private;
10451 int pipe = pipe_config->cpu_transcoder;
10452 u32 dpll = pipe_config->dpll_hw_state.dpll;
10453 u32 fp;
10454 intel_clock_t clock;
10455 int port_clock;
10456 int refclk = i9xx_pll_refclk(dev, pipe_config);
10457
10458 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10459 fp = pipe_config->dpll_hw_state.fp0;
10460 else
10461 fp = pipe_config->dpll_hw_state.fp1;
10462
10463 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10464 if (IS_PINEVIEW(dev)) {
10465 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10466 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10467 } else {
10468 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10469 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10470 }
10471
10472 if (!IS_GEN2(dev)) {
10473 if (IS_PINEVIEW(dev))
10474 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10475 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10476 else
10477 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10478 DPLL_FPA01_P1_POST_DIV_SHIFT);
10479
10480 switch (dpll & DPLL_MODE_MASK) {
10481 case DPLLB_MODE_DAC_SERIAL:
10482 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10483 5 : 10;
10484 break;
10485 case DPLLB_MODE_LVDS:
10486 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10487 7 : 14;
10488 break;
10489 default:
10490 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10491 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10492 return;
10493 }
10494
10495 if (IS_PINEVIEW(dev))
10496 port_clock = pnv_calc_dpll_params(refclk, &clock);
10497 else
10498 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10499 } else {
10500 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10501 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10502
10503 if (is_lvds) {
10504 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10505 DPLL_FPA01_P1_POST_DIV_SHIFT);
10506
10507 if (lvds & LVDS_CLKB_POWER_UP)
10508 clock.p2 = 7;
10509 else
10510 clock.p2 = 14;
10511 } else {
10512 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10513 clock.p1 = 2;
10514 else {
10515 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10516 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10517 }
10518 if (dpll & PLL_P2_DIVIDE_BY_4)
10519 clock.p2 = 4;
10520 else
10521 clock.p2 = 2;
10522 }
10523
10524 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10525 }
10526
10527 /*
10528 * This value includes pixel_multiplier. We will use
10529 * port_clock to compute adjusted_mode.crtc_clock in the
10530 * encoder's get_config() function.
10531 */
10532 pipe_config->port_clock = port_clock;
10533 }
10534
10535 int intel_dotclock_calculate(int link_freq,
10536 const struct intel_link_m_n *m_n)
10537 {
10538 /*
10539 * The calculation for the data clock is:
10540 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10541 * But we want to avoid losing precison if possible, so:
10542 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10543 *
10544 * and the link clock is simpler:
10545 * link_clock = (m * link_clock) / n
10546 */
10547
10548 if (!m_n->link_n)
10549 return 0;
10550
10551 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10552 }
10553
10554 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10555 struct intel_crtc_state *pipe_config)
10556 {
10557 struct drm_device *dev = crtc->base.dev;
10558
10559 /* read out port_clock from the DPLL */
10560 i9xx_crtc_clock_get(crtc, pipe_config);
10561
10562 /*
10563 * This value does not include pixel_multiplier.
10564 * We will check that port_clock and adjusted_mode.crtc_clock
10565 * agree once we know their relationship in the encoder's
10566 * get_config() function.
10567 */
10568 pipe_config->base.adjusted_mode.crtc_clock =
10569 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10570 &pipe_config->fdi_m_n);
10571 }
10572
10573 /** Returns the currently programmed mode of the given pipe. */
10574 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10575 struct drm_crtc *crtc)
10576 {
10577 struct drm_i915_private *dev_priv = dev->dev_private;
10578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10579 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10580 struct drm_display_mode *mode;
10581 struct intel_crtc_state pipe_config;
10582 int htot = I915_READ(HTOTAL(cpu_transcoder));
10583 int hsync = I915_READ(HSYNC(cpu_transcoder));
10584 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10585 int vsync = I915_READ(VSYNC(cpu_transcoder));
10586 enum pipe pipe = intel_crtc->pipe;
10587
10588 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10589 if (!mode)
10590 return NULL;
10591
10592 /*
10593 * Construct a pipe_config sufficient for getting the clock info
10594 * back out of crtc_clock_get.
10595 *
10596 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10597 * to use a real value here instead.
10598 */
10599 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10600 pipe_config.pixel_multiplier = 1;
10601 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10602 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10603 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10604 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10605
10606 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10607 mode->hdisplay = (htot & 0xffff) + 1;
10608 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10609 mode->hsync_start = (hsync & 0xffff) + 1;
10610 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10611 mode->vdisplay = (vtot & 0xffff) + 1;
10612 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10613 mode->vsync_start = (vsync & 0xffff) + 1;
10614 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10615
10616 drm_mode_set_name(mode);
10617
10618 return mode;
10619 }
10620
10621 void intel_mark_busy(struct drm_device *dev)
10622 {
10623 struct drm_i915_private *dev_priv = dev->dev_private;
10624
10625 if (dev_priv->mm.busy)
10626 return;
10627
10628 intel_runtime_pm_get(dev_priv);
10629 i915_update_gfx_val(dev_priv);
10630 if (INTEL_INFO(dev)->gen >= 6)
10631 gen6_rps_busy(dev_priv);
10632 dev_priv->mm.busy = true;
10633 }
10634
10635 void intel_mark_idle(struct drm_device *dev)
10636 {
10637 struct drm_i915_private *dev_priv = dev->dev_private;
10638
10639 if (!dev_priv->mm.busy)
10640 return;
10641
10642 dev_priv->mm.busy = false;
10643
10644 if (INTEL_INFO(dev)->gen >= 6)
10645 gen6_rps_idle(dev->dev_private);
10646
10647 intel_runtime_pm_put(dev_priv);
10648 }
10649
10650 static void intel_crtc_destroy(struct drm_crtc *crtc)
10651 {
10652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10653 struct drm_device *dev = crtc->dev;
10654 struct intel_unpin_work *work;
10655
10656 spin_lock_irq(&dev->event_lock);
10657 work = intel_crtc->unpin_work;
10658 intel_crtc->unpin_work = NULL;
10659 spin_unlock_irq(&dev->event_lock);
10660
10661 if (work) {
10662 cancel_work_sync(&work->work);
10663 kfree(work);
10664 }
10665
10666 drm_crtc_cleanup(crtc);
10667
10668 kfree(intel_crtc);
10669 }
10670
10671 static void intel_unpin_work_fn(struct work_struct *__work)
10672 {
10673 struct intel_unpin_work *work =
10674 container_of(__work, struct intel_unpin_work, work);
10675 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10676 struct drm_device *dev = crtc->base.dev;
10677 struct drm_plane *primary = crtc->base.primary;
10678
10679 mutex_lock(&dev->struct_mutex);
10680 intel_unpin_fb_obj(work->old_fb, primary->state);
10681 drm_gem_object_unreference(&work->pending_flip_obj->base);
10682
10683 if (work->flip_queued_req)
10684 i915_gem_request_assign(&work->flip_queued_req, NULL);
10685 mutex_unlock(&dev->struct_mutex);
10686
10687 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10688 drm_framebuffer_unreference(work->old_fb);
10689
10690 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10691 atomic_dec(&crtc->unpin_work_count);
10692
10693 kfree(work);
10694 }
10695
10696 static void do_intel_finish_page_flip(struct drm_device *dev,
10697 struct drm_crtc *crtc)
10698 {
10699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10700 struct intel_unpin_work *work;
10701 unsigned long flags;
10702
10703 /* Ignore early vblank irqs */
10704 if (intel_crtc == NULL)
10705 return;
10706
10707 /*
10708 * This is called both by irq handlers and the reset code (to complete
10709 * lost pageflips) so needs the full irqsave spinlocks.
10710 */
10711 spin_lock_irqsave(&dev->event_lock, flags);
10712 work = intel_crtc->unpin_work;
10713
10714 /* Ensure we don't miss a work->pending update ... */
10715 smp_rmb();
10716
10717 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10718 spin_unlock_irqrestore(&dev->event_lock, flags);
10719 return;
10720 }
10721
10722 page_flip_completed(intel_crtc);
10723
10724 spin_unlock_irqrestore(&dev->event_lock, flags);
10725 }
10726
10727 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10728 {
10729 struct drm_i915_private *dev_priv = dev->dev_private;
10730 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10731
10732 do_intel_finish_page_flip(dev, crtc);
10733 }
10734
10735 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10736 {
10737 struct drm_i915_private *dev_priv = dev->dev_private;
10738 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10739
10740 do_intel_finish_page_flip(dev, crtc);
10741 }
10742
10743 /* Is 'a' after or equal to 'b'? */
10744 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10745 {
10746 return !((a - b) & 0x80000000);
10747 }
10748
10749 static bool page_flip_finished(struct intel_crtc *crtc)
10750 {
10751 struct drm_device *dev = crtc->base.dev;
10752 struct drm_i915_private *dev_priv = dev->dev_private;
10753
10754 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10755 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10756 return true;
10757
10758 /*
10759 * The relevant registers doen't exist on pre-ctg.
10760 * As the flip done interrupt doesn't trigger for mmio
10761 * flips on gmch platforms, a flip count check isn't
10762 * really needed there. But since ctg has the registers,
10763 * include it in the check anyway.
10764 */
10765 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10766 return true;
10767
10768 /*
10769 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10770 * used the same base address. In that case the mmio flip might
10771 * have completed, but the CS hasn't even executed the flip yet.
10772 *
10773 * A flip count check isn't enough as the CS might have updated
10774 * the base address just after start of vblank, but before we
10775 * managed to process the interrupt. This means we'd complete the
10776 * CS flip too soon.
10777 *
10778 * Combining both checks should get us a good enough result. It may
10779 * still happen that the CS flip has been executed, but has not
10780 * yet actually completed. But in case the base address is the same
10781 * anyway, we don't really care.
10782 */
10783 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10784 crtc->unpin_work->gtt_offset &&
10785 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10786 crtc->unpin_work->flip_count);
10787 }
10788
10789 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10790 {
10791 struct drm_i915_private *dev_priv = dev->dev_private;
10792 struct intel_crtc *intel_crtc =
10793 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10794 unsigned long flags;
10795
10796
10797 /*
10798 * This is called both by irq handlers and the reset code (to complete
10799 * lost pageflips) so needs the full irqsave spinlocks.
10800 *
10801 * NB: An MMIO update of the plane base pointer will also
10802 * generate a page-flip completion irq, i.e. every modeset
10803 * is also accompanied by a spurious intel_prepare_page_flip().
10804 */
10805 spin_lock_irqsave(&dev->event_lock, flags);
10806 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10807 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10808 spin_unlock_irqrestore(&dev->event_lock, flags);
10809 }
10810
10811 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10812 {
10813 /* Ensure that the work item is consistent when activating it ... */
10814 smp_wmb();
10815 atomic_set(&work->pending, INTEL_FLIP_PENDING);
10816 /* and that it is marked active as soon as the irq could fire. */
10817 smp_wmb();
10818 }
10819
10820 static int intel_gen2_queue_flip(struct drm_device *dev,
10821 struct drm_crtc *crtc,
10822 struct drm_framebuffer *fb,
10823 struct drm_i915_gem_object *obj,
10824 struct drm_i915_gem_request *req,
10825 uint32_t flags)
10826 {
10827 struct intel_engine_cs *ring = req->ring;
10828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10829 u32 flip_mask;
10830 int ret;
10831
10832 ret = intel_ring_begin(req, 6);
10833 if (ret)
10834 return ret;
10835
10836 /* Can't queue multiple flips, so wait for the previous
10837 * one to finish before executing the next.
10838 */
10839 if (intel_crtc->plane)
10840 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10841 else
10842 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10843 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10844 intel_ring_emit(ring, MI_NOOP);
10845 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10846 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10847 intel_ring_emit(ring, fb->pitches[0]);
10848 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10849 intel_ring_emit(ring, 0); /* aux display base address, unused */
10850
10851 intel_mark_page_flip_active(intel_crtc->unpin_work);
10852 return 0;
10853 }
10854
10855 static int intel_gen3_queue_flip(struct drm_device *dev,
10856 struct drm_crtc *crtc,
10857 struct drm_framebuffer *fb,
10858 struct drm_i915_gem_object *obj,
10859 struct drm_i915_gem_request *req,
10860 uint32_t flags)
10861 {
10862 struct intel_engine_cs *ring = req->ring;
10863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10864 u32 flip_mask;
10865 int ret;
10866
10867 ret = intel_ring_begin(req, 6);
10868 if (ret)
10869 return ret;
10870
10871 if (intel_crtc->plane)
10872 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10873 else
10874 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10875 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10876 intel_ring_emit(ring, MI_NOOP);
10877 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10878 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10879 intel_ring_emit(ring, fb->pitches[0]);
10880 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10881 intel_ring_emit(ring, MI_NOOP);
10882
10883 intel_mark_page_flip_active(intel_crtc->unpin_work);
10884 return 0;
10885 }
10886
10887 static int intel_gen4_queue_flip(struct drm_device *dev,
10888 struct drm_crtc *crtc,
10889 struct drm_framebuffer *fb,
10890 struct drm_i915_gem_object *obj,
10891 struct drm_i915_gem_request *req,
10892 uint32_t flags)
10893 {
10894 struct intel_engine_cs *ring = req->ring;
10895 struct drm_i915_private *dev_priv = dev->dev_private;
10896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10897 uint32_t pf, pipesrc;
10898 int ret;
10899
10900 ret = intel_ring_begin(req, 4);
10901 if (ret)
10902 return ret;
10903
10904 /* i965+ uses the linear or tiled offsets from the
10905 * Display Registers (which do not change across a page-flip)
10906 * so we need only reprogram the base address.
10907 */
10908 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10909 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10910 intel_ring_emit(ring, fb->pitches[0]);
10911 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10912 obj->tiling_mode);
10913
10914 /* XXX Enabling the panel-fitter across page-flip is so far
10915 * untested on non-native modes, so ignore it for now.
10916 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10917 */
10918 pf = 0;
10919 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10920 intel_ring_emit(ring, pf | pipesrc);
10921
10922 intel_mark_page_flip_active(intel_crtc->unpin_work);
10923 return 0;
10924 }
10925
10926 static int intel_gen6_queue_flip(struct drm_device *dev,
10927 struct drm_crtc *crtc,
10928 struct drm_framebuffer *fb,
10929 struct drm_i915_gem_object *obj,
10930 struct drm_i915_gem_request *req,
10931 uint32_t flags)
10932 {
10933 struct intel_engine_cs *ring = req->ring;
10934 struct drm_i915_private *dev_priv = dev->dev_private;
10935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10936 uint32_t pf, pipesrc;
10937 int ret;
10938
10939 ret = intel_ring_begin(req, 4);
10940 if (ret)
10941 return ret;
10942
10943 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10944 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10945 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10946 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10947
10948 /* Contrary to the suggestions in the documentation,
10949 * "Enable Panel Fitter" does not seem to be required when page
10950 * flipping with a non-native mode, and worse causes a normal
10951 * modeset to fail.
10952 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10953 */
10954 pf = 0;
10955 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10956 intel_ring_emit(ring, pf | pipesrc);
10957
10958 intel_mark_page_flip_active(intel_crtc->unpin_work);
10959 return 0;
10960 }
10961
10962 static int intel_gen7_queue_flip(struct drm_device *dev,
10963 struct drm_crtc *crtc,
10964 struct drm_framebuffer *fb,
10965 struct drm_i915_gem_object *obj,
10966 struct drm_i915_gem_request *req,
10967 uint32_t flags)
10968 {
10969 struct intel_engine_cs *ring = req->ring;
10970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10971 uint32_t plane_bit = 0;
10972 int len, ret;
10973
10974 switch (intel_crtc->plane) {
10975 case PLANE_A:
10976 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10977 break;
10978 case PLANE_B:
10979 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10980 break;
10981 case PLANE_C:
10982 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10983 break;
10984 default:
10985 WARN_ONCE(1, "unknown plane in flip command\n");
10986 return -ENODEV;
10987 }
10988
10989 len = 4;
10990 if (ring->id == RCS) {
10991 len += 6;
10992 /*
10993 * On Gen 8, SRM is now taking an extra dword to accommodate
10994 * 48bits addresses, and we need a NOOP for the batch size to
10995 * stay even.
10996 */
10997 if (IS_GEN8(dev))
10998 len += 2;
10999 }
11000
11001 /*
11002 * BSpec MI_DISPLAY_FLIP for IVB:
11003 * "The full packet must be contained within the same cache line."
11004 *
11005 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11006 * cacheline, if we ever start emitting more commands before
11007 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11008 * then do the cacheline alignment, and finally emit the
11009 * MI_DISPLAY_FLIP.
11010 */
11011 ret = intel_ring_cacheline_align(req);
11012 if (ret)
11013 return ret;
11014
11015 ret = intel_ring_begin(req, len);
11016 if (ret)
11017 return ret;
11018
11019 /* Unmask the flip-done completion message. Note that the bspec says that
11020 * we should do this for both the BCS and RCS, and that we must not unmask
11021 * more than one flip event at any time (or ensure that one flip message
11022 * can be sent by waiting for flip-done prior to queueing new flips).
11023 * Experimentation says that BCS works despite DERRMR masking all
11024 * flip-done completion events and that unmasking all planes at once
11025 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11026 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11027 */
11028 if (ring->id == RCS) {
11029 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11030 intel_ring_emit(ring, DERRMR);
11031 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11032 DERRMR_PIPEB_PRI_FLIP_DONE |
11033 DERRMR_PIPEC_PRI_FLIP_DONE));
11034 if (IS_GEN8(dev))
11035 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11036 MI_SRM_LRM_GLOBAL_GTT);
11037 else
11038 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11039 MI_SRM_LRM_GLOBAL_GTT);
11040 intel_ring_emit(ring, DERRMR);
11041 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11042 if (IS_GEN8(dev)) {
11043 intel_ring_emit(ring, 0);
11044 intel_ring_emit(ring, MI_NOOP);
11045 }
11046 }
11047
11048 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11049 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11050 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11051 intel_ring_emit(ring, (MI_NOOP));
11052
11053 intel_mark_page_flip_active(intel_crtc->unpin_work);
11054 return 0;
11055 }
11056
11057 static bool use_mmio_flip(struct intel_engine_cs *ring,
11058 struct drm_i915_gem_object *obj)
11059 {
11060 /*
11061 * This is not being used for older platforms, because
11062 * non-availability of flip done interrupt forces us to use
11063 * CS flips. Older platforms derive flip done using some clever
11064 * tricks involving the flip_pending status bits and vblank irqs.
11065 * So using MMIO flips there would disrupt this mechanism.
11066 */
11067
11068 if (ring == NULL)
11069 return true;
11070
11071 if (INTEL_INFO(ring->dev)->gen < 5)
11072 return false;
11073
11074 if (i915.use_mmio_flip < 0)
11075 return false;
11076 else if (i915.use_mmio_flip > 0)
11077 return true;
11078 else if (i915.enable_execlists)
11079 return true;
11080 else
11081 return ring != i915_gem_request_get_ring(obj->last_write_req);
11082 }
11083
11084 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11085 struct intel_unpin_work *work)
11086 {
11087 struct drm_device *dev = intel_crtc->base.dev;
11088 struct drm_i915_private *dev_priv = dev->dev_private;
11089 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11090 const enum pipe pipe = intel_crtc->pipe;
11091 u32 ctl, stride;
11092
11093 ctl = I915_READ(PLANE_CTL(pipe, 0));
11094 ctl &= ~PLANE_CTL_TILED_MASK;
11095 switch (fb->modifier[0]) {
11096 case DRM_FORMAT_MOD_NONE:
11097 break;
11098 case I915_FORMAT_MOD_X_TILED:
11099 ctl |= PLANE_CTL_TILED_X;
11100 break;
11101 case I915_FORMAT_MOD_Y_TILED:
11102 ctl |= PLANE_CTL_TILED_Y;
11103 break;
11104 case I915_FORMAT_MOD_Yf_TILED:
11105 ctl |= PLANE_CTL_TILED_YF;
11106 break;
11107 default:
11108 MISSING_CASE(fb->modifier[0]);
11109 }
11110
11111 /*
11112 * The stride is either expressed as a multiple of 64 bytes chunks for
11113 * linear buffers or in number of tiles for tiled buffers.
11114 */
11115 stride = fb->pitches[0] /
11116 intel_fb_stride_alignment(dev, fb->modifier[0],
11117 fb->pixel_format);
11118
11119 /*
11120 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11121 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11122 */
11123 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11124 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11125
11126 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11127 POSTING_READ(PLANE_SURF(pipe, 0));
11128 }
11129
11130 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11131 struct intel_unpin_work *work)
11132 {
11133 struct drm_device *dev = intel_crtc->base.dev;
11134 struct drm_i915_private *dev_priv = dev->dev_private;
11135 struct intel_framebuffer *intel_fb =
11136 to_intel_framebuffer(intel_crtc->base.primary->fb);
11137 struct drm_i915_gem_object *obj = intel_fb->obj;
11138 u32 dspcntr;
11139 u32 reg;
11140
11141 reg = DSPCNTR(intel_crtc->plane);
11142 dspcntr = I915_READ(reg);
11143
11144 if (obj->tiling_mode != I915_TILING_NONE)
11145 dspcntr |= DISPPLANE_TILED;
11146 else
11147 dspcntr &= ~DISPPLANE_TILED;
11148
11149 I915_WRITE(reg, dspcntr);
11150
11151 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11152 POSTING_READ(DSPSURF(intel_crtc->plane));
11153 }
11154
11155 /*
11156 * XXX: This is the temporary way to update the plane registers until we get
11157 * around to using the usual plane update functions for MMIO flips
11158 */
11159 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11160 {
11161 struct intel_crtc *crtc = mmio_flip->crtc;
11162 struct intel_unpin_work *work;
11163
11164 spin_lock_irq(&crtc->base.dev->event_lock);
11165 work = crtc->unpin_work;
11166 spin_unlock_irq(&crtc->base.dev->event_lock);
11167 if (work == NULL)
11168 return;
11169
11170 intel_mark_page_flip_active(work);
11171
11172 intel_pipe_update_start(crtc);
11173
11174 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11175 skl_do_mmio_flip(crtc, work);
11176 else
11177 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11178 ilk_do_mmio_flip(crtc, work);
11179
11180 intel_pipe_update_end(crtc);
11181 }
11182
11183 static void intel_mmio_flip_work_func(struct work_struct *work)
11184 {
11185 struct intel_mmio_flip *mmio_flip =
11186 container_of(work, struct intel_mmio_flip, work);
11187
11188 if (mmio_flip->req) {
11189 WARN_ON(__i915_wait_request(mmio_flip->req,
11190 mmio_flip->crtc->reset_counter,
11191 false, NULL,
11192 &mmio_flip->i915->rps.mmioflips));
11193 i915_gem_request_unreference__unlocked(mmio_flip->req);
11194 }
11195
11196 intel_do_mmio_flip(mmio_flip);
11197 kfree(mmio_flip);
11198 }
11199
11200 static int intel_queue_mmio_flip(struct drm_device *dev,
11201 struct drm_crtc *crtc,
11202 struct drm_framebuffer *fb,
11203 struct drm_i915_gem_object *obj,
11204 struct intel_engine_cs *ring,
11205 uint32_t flags)
11206 {
11207 struct intel_mmio_flip *mmio_flip;
11208
11209 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11210 if (mmio_flip == NULL)
11211 return -ENOMEM;
11212
11213 mmio_flip->i915 = to_i915(dev);
11214 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11215 mmio_flip->crtc = to_intel_crtc(crtc);
11216
11217 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11218 schedule_work(&mmio_flip->work);
11219
11220 return 0;
11221 }
11222
11223 static int intel_default_queue_flip(struct drm_device *dev,
11224 struct drm_crtc *crtc,
11225 struct drm_framebuffer *fb,
11226 struct drm_i915_gem_object *obj,
11227 struct drm_i915_gem_request *req,
11228 uint32_t flags)
11229 {
11230 return -ENODEV;
11231 }
11232
11233 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11234 struct drm_crtc *crtc)
11235 {
11236 struct drm_i915_private *dev_priv = dev->dev_private;
11237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11238 struct intel_unpin_work *work = intel_crtc->unpin_work;
11239 u32 addr;
11240
11241 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11242 return true;
11243
11244 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11245 return false;
11246
11247 if (!work->enable_stall_check)
11248 return false;
11249
11250 if (work->flip_ready_vblank == 0) {
11251 if (work->flip_queued_req &&
11252 !i915_gem_request_completed(work->flip_queued_req, true))
11253 return false;
11254
11255 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11256 }
11257
11258 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11259 return false;
11260
11261 /* Potential stall - if we see that the flip has happened,
11262 * assume a missed interrupt. */
11263 if (INTEL_INFO(dev)->gen >= 4)
11264 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11265 else
11266 addr = I915_READ(DSPADDR(intel_crtc->plane));
11267
11268 /* There is a potential issue here with a false positive after a flip
11269 * to the same address. We could address this by checking for a
11270 * non-incrementing frame counter.
11271 */
11272 return addr == work->gtt_offset;
11273 }
11274
11275 void intel_check_page_flip(struct drm_device *dev, int pipe)
11276 {
11277 struct drm_i915_private *dev_priv = dev->dev_private;
11278 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11280 struct intel_unpin_work *work;
11281
11282 WARN_ON(!in_interrupt());
11283
11284 if (crtc == NULL)
11285 return;
11286
11287 spin_lock(&dev->event_lock);
11288 work = intel_crtc->unpin_work;
11289 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11290 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11291 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11292 page_flip_completed(intel_crtc);
11293 work = NULL;
11294 }
11295 if (work != NULL &&
11296 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11297 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11298 spin_unlock(&dev->event_lock);
11299 }
11300
11301 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11302 struct drm_framebuffer *fb,
11303 struct drm_pending_vblank_event *event,
11304 uint32_t page_flip_flags)
11305 {
11306 struct drm_device *dev = crtc->dev;
11307 struct drm_i915_private *dev_priv = dev->dev_private;
11308 struct drm_framebuffer *old_fb = crtc->primary->fb;
11309 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11311 struct drm_plane *primary = crtc->primary;
11312 enum pipe pipe = intel_crtc->pipe;
11313 struct intel_unpin_work *work;
11314 struct intel_engine_cs *ring;
11315 bool mmio_flip;
11316 struct drm_i915_gem_request *request = NULL;
11317 int ret;
11318
11319 /*
11320 * drm_mode_page_flip_ioctl() should already catch this, but double
11321 * check to be safe. In the future we may enable pageflipping from
11322 * a disabled primary plane.
11323 */
11324 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11325 return -EBUSY;
11326
11327 /* Can't change pixel format via MI display flips. */
11328 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11329 return -EINVAL;
11330
11331 /*
11332 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11333 * Note that pitch changes could also affect these register.
11334 */
11335 if (INTEL_INFO(dev)->gen > 3 &&
11336 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11337 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11338 return -EINVAL;
11339
11340 if (i915_terminally_wedged(&dev_priv->gpu_error))
11341 goto out_hang;
11342
11343 work = kzalloc(sizeof(*work), GFP_KERNEL);
11344 if (work == NULL)
11345 return -ENOMEM;
11346
11347 work->event = event;
11348 work->crtc = crtc;
11349 work->old_fb = old_fb;
11350 INIT_WORK(&work->work, intel_unpin_work_fn);
11351
11352 ret = drm_crtc_vblank_get(crtc);
11353 if (ret)
11354 goto free_work;
11355
11356 /* We borrow the event spin lock for protecting unpin_work */
11357 spin_lock_irq(&dev->event_lock);
11358 if (intel_crtc->unpin_work) {
11359 /* Before declaring the flip queue wedged, check if
11360 * the hardware completed the operation behind our backs.
11361 */
11362 if (__intel_pageflip_stall_check(dev, crtc)) {
11363 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11364 page_flip_completed(intel_crtc);
11365 } else {
11366 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11367 spin_unlock_irq(&dev->event_lock);
11368
11369 drm_crtc_vblank_put(crtc);
11370 kfree(work);
11371 return -EBUSY;
11372 }
11373 }
11374 intel_crtc->unpin_work = work;
11375 spin_unlock_irq(&dev->event_lock);
11376
11377 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11378 flush_workqueue(dev_priv->wq);
11379
11380 /* Reference the objects for the scheduled work. */
11381 drm_framebuffer_reference(work->old_fb);
11382 drm_gem_object_reference(&obj->base);
11383
11384 crtc->primary->fb = fb;
11385 update_state_fb(crtc->primary);
11386
11387 work->pending_flip_obj = obj;
11388
11389 ret = i915_mutex_lock_interruptible(dev);
11390 if (ret)
11391 goto cleanup;
11392
11393 atomic_inc(&intel_crtc->unpin_work_count);
11394 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11395
11396 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11397 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11398
11399 if (IS_VALLEYVIEW(dev)) {
11400 ring = &dev_priv->ring[BCS];
11401 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11402 /* vlv: DISPLAY_FLIP fails to change tiling */
11403 ring = NULL;
11404 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11405 ring = &dev_priv->ring[BCS];
11406 } else if (INTEL_INFO(dev)->gen >= 7) {
11407 ring = i915_gem_request_get_ring(obj->last_write_req);
11408 if (ring == NULL || ring->id != RCS)
11409 ring = &dev_priv->ring[BCS];
11410 } else {
11411 ring = &dev_priv->ring[RCS];
11412 }
11413
11414 mmio_flip = use_mmio_flip(ring, obj);
11415
11416 /* When using CS flips, we want to emit semaphores between rings.
11417 * However, when using mmio flips we will create a task to do the
11418 * synchronisation, so all we want here is to pin the framebuffer
11419 * into the display plane and skip any waits.
11420 */
11421 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11422 crtc->primary->state,
11423 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11424 if (ret)
11425 goto cleanup_pending;
11426
11427 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11428 obj, 0);
11429 work->gtt_offset += intel_crtc->dspaddr_offset;
11430
11431 if (mmio_flip) {
11432 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11433 page_flip_flags);
11434 if (ret)
11435 goto cleanup_unpin;
11436
11437 i915_gem_request_assign(&work->flip_queued_req,
11438 obj->last_write_req);
11439 } else {
11440 if (!request) {
11441 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11442 if (ret)
11443 goto cleanup_unpin;
11444 }
11445
11446 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11447 page_flip_flags);
11448 if (ret)
11449 goto cleanup_unpin;
11450
11451 i915_gem_request_assign(&work->flip_queued_req, request);
11452 }
11453
11454 if (request)
11455 i915_add_request_no_flush(request);
11456
11457 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11458 work->enable_stall_check = true;
11459
11460 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11461 to_intel_plane(primary)->frontbuffer_bit);
11462 mutex_unlock(&dev->struct_mutex);
11463
11464 intel_fbc_disable_crtc(intel_crtc);
11465 intel_frontbuffer_flip_prepare(dev,
11466 to_intel_plane(primary)->frontbuffer_bit);
11467
11468 trace_i915_flip_request(intel_crtc->plane, obj);
11469
11470 return 0;
11471
11472 cleanup_unpin:
11473 intel_unpin_fb_obj(fb, crtc->primary->state);
11474 cleanup_pending:
11475 if (request)
11476 i915_gem_request_cancel(request);
11477 atomic_dec(&intel_crtc->unpin_work_count);
11478 mutex_unlock(&dev->struct_mutex);
11479 cleanup:
11480 crtc->primary->fb = old_fb;
11481 update_state_fb(crtc->primary);
11482
11483 drm_gem_object_unreference_unlocked(&obj->base);
11484 drm_framebuffer_unreference(work->old_fb);
11485
11486 spin_lock_irq(&dev->event_lock);
11487 intel_crtc->unpin_work = NULL;
11488 spin_unlock_irq(&dev->event_lock);
11489
11490 drm_crtc_vblank_put(crtc);
11491 free_work:
11492 kfree(work);
11493
11494 if (ret == -EIO) {
11495 struct drm_atomic_state *state;
11496 struct drm_plane_state *plane_state;
11497
11498 out_hang:
11499 state = drm_atomic_state_alloc(dev);
11500 if (!state)
11501 return -ENOMEM;
11502 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11503
11504 retry:
11505 plane_state = drm_atomic_get_plane_state(state, primary);
11506 ret = PTR_ERR_OR_ZERO(plane_state);
11507 if (!ret) {
11508 drm_atomic_set_fb_for_plane(plane_state, fb);
11509
11510 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11511 if (!ret)
11512 ret = drm_atomic_commit(state);
11513 }
11514
11515 if (ret == -EDEADLK) {
11516 drm_modeset_backoff(state->acquire_ctx);
11517 drm_atomic_state_clear(state);
11518 goto retry;
11519 }
11520
11521 if (ret)
11522 drm_atomic_state_free(state);
11523
11524 if (ret == 0 && event) {
11525 spin_lock_irq(&dev->event_lock);
11526 drm_send_vblank_event(dev, pipe, event);
11527 spin_unlock_irq(&dev->event_lock);
11528 }
11529 }
11530 return ret;
11531 }
11532
11533
11534 /**
11535 * intel_wm_need_update - Check whether watermarks need updating
11536 * @plane: drm plane
11537 * @state: new plane state
11538 *
11539 * Check current plane state versus the new one to determine whether
11540 * watermarks need to be recalculated.
11541 *
11542 * Returns true or false.
11543 */
11544 static bool intel_wm_need_update(struct drm_plane *plane,
11545 struct drm_plane_state *state)
11546 {
11547 /* Update watermarks on tiling changes. */
11548 if (!plane->state->fb || !state->fb ||
11549 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11550 plane->state->rotation != state->rotation)
11551 return true;
11552
11553 if (plane->state->crtc_w != state->crtc_w)
11554 return true;
11555
11556 return false;
11557 }
11558
11559 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11560 struct drm_plane_state *plane_state)
11561 {
11562 struct drm_crtc *crtc = crtc_state->crtc;
11563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11564 struct drm_plane *plane = plane_state->plane;
11565 struct drm_device *dev = crtc->dev;
11566 struct drm_i915_private *dev_priv = dev->dev_private;
11567 struct intel_plane_state *old_plane_state =
11568 to_intel_plane_state(plane->state);
11569 int idx = intel_crtc->base.base.id, ret;
11570 int i = drm_plane_index(plane);
11571 bool mode_changed = needs_modeset(crtc_state);
11572 bool was_crtc_enabled = crtc->state->active;
11573 bool is_crtc_enabled = crtc_state->active;
11574
11575 bool turn_off, turn_on, visible, was_visible;
11576 struct drm_framebuffer *fb = plane_state->fb;
11577
11578 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11579 plane->type != DRM_PLANE_TYPE_CURSOR) {
11580 ret = skl_update_scaler_plane(
11581 to_intel_crtc_state(crtc_state),
11582 to_intel_plane_state(plane_state));
11583 if (ret)
11584 return ret;
11585 }
11586
11587 was_visible = old_plane_state->visible;
11588 visible = to_intel_plane_state(plane_state)->visible;
11589
11590 if (!was_crtc_enabled && WARN_ON(was_visible))
11591 was_visible = false;
11592
11593 if (!is_crtc_enabled && WARN_ON(visible))
11594 visible = false;
11595
11596 if (!was_visible && !visible)
11597 return 0;
11598
11599 turn_off = was_visible && (!visible || mode_changed);
11600 turn_on = visible && (!was_visible || mode_changed);
11601
11602 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11603 plane->base.id, fb ? fb->base.id : -1);
11604
11605 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11606 plane->base.id, was_visible, visible,
11607 turn_off, turn_on, mode_changed);
11608
11609 if (turn_on) {
11610 intel_crtc->atomic.update_wm_pre = true;
11611 /* must disable cxsr around plane enable/disable */
11612 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11613 intel_crtc->atomic.disable_cxsr = true;
11614 /* to potentially re-enable cxsr */
11615 intel_crtc->atomic.wait_vblank = true;
11616 intel_crtc->atomic.update_wm_post = true;
11617 }
11618 } else if (turn_off) {
11619 intel_crtc->atomic.update_wm_post = true;
11620 /* must disable cxsr around plane enable/disable */
11621 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11622 if (is_crtc_enabled)
11623 intel_crtc->atomic.wait_vblank = true;
11624 intel_crtc->atomic.disable_cxsr = true;
11625 }
11626 } else if (intel_wm_need_update(plane, plane_state)) {
11627 intel_crtc->atomic.update_wm_pre = true;
11628 }
11629
11630 if (visible || was_visible)
11631 intel_crtc->atomic.fb_bits |=
11632 to_intel_plane(plane)->frontbuffer_bit;
11633
11634 switch (plane->type) {
11635 case DRM_PLANE_TYPE_PRIMARY:
11636 intel_crtc->atomic.wait_for_flips = true;
11637 intel_crtc->atomic.pre_disable_primary = turn_off;
11638 intel_crtc->atomic.post_enable_primary = turn_on;
11639
11640 if (turn_off) {
11641 /*
11642 * FIXME: Actually if we will still have any other
11643 * plane enabled on the pipe we could let IPS enabled
11644 * still, but for now lets consider that when we make
11645 * primary invisible by setting DSPCNTR to 0 on
11646 * update_primary_plane function IPS needs to be
11647 * disable.
11648 */
11649 intel_crtc->atomic.disable_ips = true;
11650
11651 intel_crtc->atomic.disable_fbc = true;
11652 }
11653
11654 /*
11655 * FBC does not work on some platforms for rotated
11656 * planes, so disable it when rotation is not 0 and
11657 * update it when rotation is set back to 0.
11658 *
11659 * FIXME: This is redundant with the fbc update done in
11660 * the primary plane enable function except that that
11661 * one is done too late. We eventually need to unify
11662 * this.
11663 */
11664
11665 if (visible &&
11666 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11667 dev_priv->fbc.crtc == intel_crtc &&
11668 plane_state->rotation != BIT(DRM_ROTATE_0))
11669 intel_crtc->atomic.disable_fbc = true;
11670
11671 /*
11672 * BDW signals flip done immediately if the plane
11673 * is disabled, even if the plane enable is already
11674 * armed to occur at the next vblank :(
11675 */
11676 if (turn_on && IS_BROADWELL(dev))
11677 intel_crtc->atomic.wait_vblank = true;
11678
11679 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11680 break;
11681 case DRM_PLANE_TYPE_CURSOR:
11682 break;
11683 case DRM_PLANE_TYPE_OVERLAY:
11684 if (turn_off && !mode_changed) {
11685 intel_crtc->atomic.wait_vblank = true;
11686 intel_crtc->atomic.update_sprite_watermarks |=
11687 1 << i;
11688 }
11689 }
11690 return 0;
11691 }
11692
11693 static bool encoders_cloneable(const struct intel_encoder *a,
11694 const struct intel_encoder *b)
11695 {
11696 /* masks could be asymmetric, so check both ways */
11697 return a == b || (a->cloneable & (1 << b->type) &&
11698 b->cloneable & (1 << a->type));
11699 }
11700
11701 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11702 struct intel_crtc *crtc,
11703 struct intel_encoder *encoder)
11704 {
11705 struct intel_encoder *source_encoder;
11706 struct drm_connector *connector;
11707 struct drm_connector_state *connector_state;
11708 int i;
11709
11710 for_each_connector_in_state(state, connector, connector_state, i) {
11711 if (connector_state->crtc != &crtc->base)
11712 continue;
11713
11714 source_encoder =
11715 to_intel_encoder(connector_state->best_encoder);
11716 if (!encoders_cloneable(encoder, source_encoder))
11717 return false;
11718 }
11719
11720 return true;
11721 }
11722
11723 static bool check_encoder_cloning(struct drm_atomic_state *state,
11724 struct intel_crtc *crtc)
11725 {
11726 struct intel_encoder *encoder;
11727 struct drm_connector *connector;
11728 struct drm_connector_state *connector_state;
11729 int i;
11730
11731 for_each_connector_in_state(state, connector, connector_state, i) {
11732 if (connector_state->crtc != &crtc->base)
11733 continue;
11734
11735 encoder = to_intel_encoder(connector_state->best_encoder);
11736 if (!check_single_encoder_cloning(state, crtc, encoder))
11737 return false;
11738 }
11739
11740 return true;
11741 }
11742
11743 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11744 struct drm_crtc_state *crtc_state)
11745 {
11746 struct drm_device *dev = crtc->dev;
11747 struct drm_i915_private *dev_priv = dev->dev_private;
11748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11749 struct intel_crtc_state *pipe_config =
11750 to_intel_crtc_state(crtc_state);
11751 struct drm_atomic_state *state = crtc_state->state;
11752 int ret;
11753 bool mode_changed = needs_modeset(crtc_state);
11754
11755 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11756 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11757 return -EINVAL;
11758 }
11759
11760 if (mode_changed && !crtc_state->active)
11761 intel_crtc->atomic.update_wm_post = true;
11762
11763 if (mode_changed && crtc_state->enable &&
11764 dev_priv->display.crtc_compute_clock &&
11765 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11766 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11767 pipe_config);
11768 if (ret)
11769 return ret;
11770 }
11771
11772 ret = 0;
11773 if (INTEL_INFO(dev)->gen >= 9) {
11774 if (mode_changed)
11775 ret = skl_update_scaler_crtc(pipe_config);
11776
11777 if (!ret)
11778 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11779 pipe_config);
11780 }
11781
11782 return ret;
11783 }
11784
11785 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11786 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11787 .load_lut = intel_crtc_load_lut,
11788 .atomic_begin = intel_begin_crtc_commit,
11789 .atomic_flush = intel_finish_crtc_commit,
11790 .atomic_check = intel_crtc_atomic_check,
11791 };
11792
11793 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11794 {
11795 struct intel_connector *connector;
11796
11797 for_each_intel_connector(dev, connector) {
11798 if (connector->base.encoder) {
11799 connector->base.state->best_encoder =
11800 connector->base.encoder;
11801 connector->base.state->crtc =
11802 connector->base.encoder->crtc;
11803 } else {
11804 connector->base.state->best_encoder = NULL;
11805 connector->base.state->crtc = NULL;
11806 }
11807 }
11808 }
11809
11810 static void
11811 connected_sink_compute_bpp(struct intel_connector *connector,
11812 struct intel_crtc_state *pipe_config)
11813 {
11814 int bpp = pipe_config->pipe_bpp;
11815
11816 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11817 connector->base.base.id,
11818 connector->base.name);
11819
11820 /* Don't use an invalid EDID bpc value */
11821 if (connector->base.display_info.bpc &&
11822 connector->base.display_info.bpc * 3 < bpp) {
11823 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11824 bpp, connector->base.display_info.bpc*3);
11825 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11826 }
11827
11828 /* Clamp bpp to 8 on screens without EDID 1.4 */
11829 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11830 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11831 bpp);
11832 pipe_config->pipe_bpp = 24;
11833 }
11834 }
11835
11836 static int
11837 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11838 struct intel_crtc_state *pipe_config)
11839 {
11840 struct drm_device *dev = crtc->base.dev;
11841 struct drm_atomic_state *state;
11842 struct drm_connector *connector;
11843 struct drm_connector_state *connector_state;
11844 int bpp, i;
11845
11846 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11847 bpp = 10*3;
11848 else if (INTEL_INFO(dev)->gen >= 5)
11849 bpp = 12*3;
11850 else
11851 bpp = 8*3;
11852
11853
11854 pipe_config->pipe_bpp = bpp;
11855
11856 state = pipe_config->base.state;
11857
11858 /* Clamp display bpp to EDID value */
11859 for_each_connector_in_state(state, connector, connector_state, i) {
11860 if (connector_state->crtc != &crtc->base)
11861 continue;
11862
11863 connected_sink_compute_bpp(to_intel_connector(connector),
11864 pipe_config);
11865 }
11866
11867 return bpp;
11868 }
11869
11870 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11871 {
11872 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11873 "type: 0x%x flags: 0x%x\n",
11874 mode->crtc_clock,
11875 mode->crtc_hdisplay, mode->crtc_hsync_start,
11876 mode->crtc_hsync_end, mode->crtc_htotal,
11877 mode->crtc_vdisplay, mode->crtc_vsync_start,
11878 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11879 }
11880
11881 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11882 struct intel_crtc_state *pipe_config,
11883 const char *context)
11884 {
11885 struct drm_device *dev = crtc->base.dev;
11886 struct drm_plane *plane;
11887 struct intel_plane *intel_plane;
11888 struct intel_plane_state *state;
11889 struct drm_framebuffer *fb;
11890
11891 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11892 context, pipe_config, pipe_name(crtc->pipe));
11893
11894 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11895 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11896 pipe_config->pipe_bpp, pipe_config->dither);
11897 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11898 pipe_config->has_pch_encoder,
11899 pipe_config->fdi_lanes,
11900 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11901 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11902 pipe_config->fdi_m_n.tu);
11903 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11904 pipe_config->has_dp_encoder,
11905 pipe_config->lane_count,
11906 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11907 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11908 pipe_config->dp_m_n.tu);
11909
11910 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11911 pipe_config->has_dp_encoder,
11912 pipe_config->lane_count,
11913 pipe_config->dp_m2_n2.gmch_m,
11914 pipe_config->dp_m2_n2.gmch_n,
11915 pipe_config->dp_m2_n2.link_m,
11916 pipe_config->dp_m2_n2.link_n,
11917 pipe_config->dp_m2_n2.tu);
11918
11919 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11920 pipe_config->has_audio,
11921 pipe_config->has_infoframe);
11922
11923 DRM_DEBUG_KMS("requested mode:\n");
11924 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11925 DRM_DEBUG_KMS("adjusted mode:\n");
11926 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11927 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11928 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11929 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11930 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11931 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11932 crtc->num_scalers,
11933 pipe_config->scaler_state.scaler_users,
11934 pipe_config->scaler_state.scaler_id);
11935 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11936 pipe_config->gmch_pfit.control,
11937 pipe_config->gmch_pfit.pgm_ratios,
11938 pipe_config->gmch_pfit.lvds_border_bits);
11939 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11940 pipe_config->pch_pfit.pos,
11941 pipe_config->pch_pfit.size,
11942 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11943 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11944 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11945
11946 if (IS_BROXTON(dev)) {
11947 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11948 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11949 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11950 pipe_config->ddi_pll_sel,
11951 pipe_config->dpll_hw_state.ebb0,
11952 pipe_config->dpll_hw_state.ebb4,
11953 pipe_config->dpll_hw_state.pll0,
11954 pipe_config->dpll_hw_state.pll1,
11955 pipe_config->dpll_hw_state.pll2,
11956 pipe_config->dpll_hw_state.pll3,
11957 pipe_config->dpll_hw_state.pll6,
11958 pipe_config->dpll_hw_state.pll8,
11959 pipe_config->dpll_hw_state.pll9,
11960 pipe_config->dpll_hw_state.pll10,
11961 pipe_config->dpll_hw_state.pcsdw12);
11962 } else if (IS_SKYLAKE(dev)) {
11963 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11964 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11965 pipe_config->ddi_pll_sel,
11966 pipe_config->dpll_hw_state.ctrl1,
11967 pipe_config->dpll_hw_state.cfgcr1,
11968 pipe_config->dpll_hw_state.cfgcr2);
11969 } else if (HAS_DDI(dev)) {
11970 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11971 pipe_config->ddi_pll_sel,
11972 pipe_config->dpll_hw_state.wrpll);
11973 } else {
11974 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11975 "fp0: 0x%x, fp1: 0x%x\n",
11976 pipe_config->dpll_hw_state.dpll,
11977 pipe_config->dpll_hw_state.dpll_md,
11978 pipe_config->dpll_hw_state.fp0,
11979 pipe_config->dpll_hw_state.fp1);
11980 }
11981
11982 DRM_DEBUG_KMS("planes on this crtc\n");
11983 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11984 intel_plane = to_intel_plane(plane);
11985 if (intel_plane->pipe != crtc->pipe)
11986 continue;
11987
11988 state = to_intel_plane_state(plane->state);
11989 fb = state->base.fb;
11990 if (!fb) {
11991 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11992 "disabled, scaler_id = %d\n",
11993 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11994 plane->base.id, intel_plane->pipe,
11995 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11996 drm_plane_index(plane), state->scaler_id);
11997 continue;
11998 }
11999
12000 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12001 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12002 plane->base.id, intel_plane->pipe,
12003 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12004 drm_plane_index(plane));
12005 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12006 fb->base.id, fb->width, fb->height, fb->pixel_format);
12007 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12008 state->scaler_id,
12009 state->src.x1 >> 16, state->src.y1 >> 16,
12010 drm_rect_width(&state->src) >> 16,
12011 drm_rect_height(&state->src) >> 16,
12012 state->dst.x1, state->dst.y1,
12013 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12014 }
12015 }
12016
12017 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12018 {
12019 struct drm_device *dev = state->dev;
12020 struct intel_encoder *encoder;
12021 struct drm_connector *connector;
12022 struct drm_connector_state *connector_state;
12023 unsigned int used_ports = 0;
12024 int i;
12025
12026 /*
12027 * Walk the connector list instead of the encoder
12028 * list to detect the problem on ddi platforms
12029 * where there's just one encoder per digital port.
12030 */
12031 for_each_connector_in_state(state, connector, connector_state, i) {
12032 if (!connector_state->best_encoder)
12033 continue;
12034
12035 encoder = to_intel_encoder(connector_state->best_encoder);
12036
12037 WARN_ON(!connector_state->crtc);
12038
12039 switch (encoder->type) {
12040 unsigned int port_mask;
12041 case INTEL_OUTPUT_UNKNOWN:
12042 if (WARN_ON(!HAS_DDI(dev)))
12043 break;
12044 case INTEL_OUTPUT_DISPLAYPORT:
12045 case INTEL_OUTPUT_HDMI:
12046 case INTEL_OUTPUT_EDP:
12047 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12048
12049 /* the same port mustn't appear more than once */
12050 if (used_ports & port_mask)
12051 return false;
12052
12053 used_ports |= port_mask;
12054 default:
12055 break;
12056 }
12057 }
12058
12059 return true;
12060 }
12061
12062 static void
12063 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12064 {
12065 struct drm_crtc_state tmp_state;
12066 struct intel_crtc_scaler_state scaler_state;
12067 struct intel_dpll_hw_state dpll_hw_state;
12068 enum intel_dpll_id shared_dpll;
12069 uint32_t ddi_pll_sel;
12070 bool force_thru;
12071
12072 /* FIXME: before the switch to atomic started, a new pipe_config was
12073 * kzalloc'd. Code that depends on any field being zero should be
12074 * fixed, so that the crtc_state can be safely duplicated. For now,
12075 * only fields that are know to not cause problems are preserved. */
12076
12077 tmp_state = crtc_state->base;
12078 scaler_state = crtc_state->scaler_state;
12079 shared_dpll = crtc_state->shared_dpll;
12080 dpll_hw_state = crtc_state->dpll_hw_state;
12081 ddi_pll_sel = crtc_state->ddi_pll_sel;
12082 force_thru = crtc_state->pch_pfit.force_thru;
12083
12084 memset(crtc_state, 0, sizeof *crtc_state);
12085
12086 crtc_state->base = tmp_state;
12087 crtc_state->scaler_state = scaler_state;
12088 crtc_state->shared_dpll = shared_dpll;
12089 crtc_state->dpll_hw_state = dpll_hw_state;
12090 crtc_state->ddi_pll_sel = ddi_pll_sel;
12091 crtc_state->pch_pfit.force_thru = force_thru;
12092 }
12093
12094 static int
12095 intel_modeset_pipe_config(struct drm_crtc *crtc,
12096 struct intel_crtc_state *pipe_config)
12097 {
12098 struct drm_atomic_state *state = pipe_config->base.state;
12099 struct intel_encoder *encoder;
12100 struct drm_connector *connector;
12101 struct drm_connector_state *connector_state;
12102 int base_bpp, ret = -EINVAL;
12103 int i;
12104 bool retry = true;
12105
12106 clear_intel_crtc_state(pipe_config);
12107
12108 pipe_config->cpu_transcoder =
12109 (enum transcoder) to_intel_crtc(crtc)->pipe;
12110
12111 /*
12112 * Sanitize sync polarity flags based on requested ones. If neither
12113 * positive or negative polarity is requested, treat this as meaning
12114 * negative polarity.
12115 */
12116 if (!(pipe_config->base.adjusted_mode.flags &
12117 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12118 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12119
12120 if (!(pipe_config->base.adjusted_mode.flags &
12121 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12122 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12123
12124 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12125 pipe_config);
12126 if (base_bpp < 0)
12127 goto fail;
12128
12129 /*
12130 * Determine the real pipe dimensions. Note that stereo modes can
12131 * increase the actual pipe size due to the frame doubling and
12132 * insertion of additional space for blanks between the frame. This
12133 * is stored in the crtc timings. We use the requested mode to do this
12134 * computation to clearly distinguish it from the adjusted mode, which
12135 * can be changed by the connectors in the below retry loop.
12136 */
12137 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12138 &pipe_config->pipe_src_w,
12139 &pipe_config->pipe_src_h);
12140
12141 encoder_retry:
12142 /* Ensure the port clock defaults are reset when retrying. */
12143 pipe_config->port_clock = 0;
12144 pipe_config->pixel_multiplier = 1;
12145
12146 /* Fill in default crtc timings, allow encoders to overwrite them. */
12147 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12148 CRTC_STEREO_DOUBLE);
12149
12150 /* Pass our mode to the connectors and the CRTC to give them a chance to
12151 * adjust it according to limitations or connector properties, and also
12152 * a chance to reject the mode entirely.
12153 */
12154 for_each_connector_in_state(state, connector, connector_state, i) {
12155 if (connector_state->crtc != crtc)
12156 continue;
12157
12158 encoder = to_intel_encoder(connector_state->best_encoder);
12159
12160 if (!(encoder->compute_config(encoder, pipe_config))) {
12161 DRM_DEBUG_KMS("Encoder config failure\n");
12162 goto fail;
12163 }
12164 }
12165
12166 /* Set default port clock if not overwritten by the encoder. Needs to be
12167 * done afterwards in case the encoder adjusts the mode. */
12168 if (!pipe_config->port_clock)
12169 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12170 * pipe_config->pixel_multiplier;
12171
12172 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12173 if (ret < 0) {
12174 DRM_DEBUG_KMS("CRTC fixup failed\n");
12175 goto fail;
12176 }
12177
12178 if (ret == RETRY) {
12179 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12180 ret = -EINVAL;
12181 goto fail;
12182 }
12183
12184 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12185 retry = false;
12186 goto encoder_retry;
12187 }
12188
12189 /* Dithering seems to not pass-through bits correctly when it should, so
12190 * only enable it on 6bpc panels. */
12191 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12192 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12193 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12194
12195 fail:
12196 return ret;
12197 }
12198
12199 static void
12200 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12201 {
12202 struct drm_crtc *crtc;
12203 struct drm_crtc_state *crtc_state;
12204 int i;
12205
12206 /* Double check state. */
12207 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12208 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12209
12210 /* Update hwmode for vblank functions */
12211 if (crtc->state->active)
12212 crtc->hwmode = crtc->state->adjusted_mode;
12213 else
12214 crtc->hwmode.crtc_clock = 0;
12215
12216 /*
12217 * Update legacy state to satisfy fbc code. This can
12218 * be removed when fbc uses the atomic state.
12219 */
12220 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12221 struct drm_plane_state *plane_state = crtc->primary->state;
12222
12223 crtc->primary->fb = plane_state->fb;
12224 crtc->x = plane_state->src_x >> 16;
12225 crtc->y = plane_state->src_y >> 16;
12226 }
12227 }
12228 }
12229
12230 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12231 {
12232 int diff;
12233
12234 if (clock1 == clock2)
12235 return true;
12236
12237 if (!clock1 || !clock2)
12238 return false;
12239
12240 diff = abs(clock1 - clock2);
12241
12242 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12243 return true;
12244
12245 return false;
12246 }
12247
12248 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12249 list_for_each_entry((intel_crtc), \
12250 &(dev)->mode_config.crtc_list, \
12251 base.head) \
12252 if (mask & (1 <<(intel_crtc)->pipe))
12253
12254 static bool
12255 intel_compare_m_n(unsigned int m, unsigned int n,
12256 unsigned int m2, unsigned int n2,
12257 bool exact)
12258 {
12259 if (m == m2 && n == n2)
12260 return true;
12261
12262 if (exact || !m || !n || !m2 || !n2)
12263 return false;
12264
12265 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12266
12267 if (m > m2) {
12268 while (m > m2) {
12269 m2 <<= 1;
12270 n2 <<= 1;
12271 }
12272 } else if (m < m2) {
12273 while (m < m2) {
12274 m <<= 1;
12275 n <<= 1;
12276 }
12277 }
12278
12279 return m == m2 && n == n2;
12280 }
12281
12282 static bool
12283 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12284 struct intel_link_m_n *m2_n2,
12285 bool adjust)
12286 {
12287 if (m_n->tu == m2_n2->tu &&
12288 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12289 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12290 intel_compare_m_n(m_n->link_m, m_n->link_n,
12291 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12292 if (adjust)
12293 *m2_n2 = *m_n;
12294
12295 return true;
12296 }
12297
12298 return false;
12299 }
12300
12301 static bool
12302 intel_pipe_config_compare(struct drm_device *dev,
12303 struct intel_crtc_state *current_config,
12304 struct intel_crtc_state *pipe_config,
12305 bool adjust)
12306 {
12307 bool ret = true;
12308
12309 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12310 do { \
12311 if (!adjust) \
12312 DRM_ERROR(fmt, ##__VA_ARGS__); \
12313 else \
12314 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12315 } while (0)
12316
12317 #define PIPE_CONF_CHECK_X(name) \
12318 if (current_config->name != pipe_config->name) { \
12319 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12320 "(expected 0x%08x, found 0x%08x)\n", \
12321 current_config->name, \
12322 pipe_config->name); \
12323 ret = false; \
12324 }
12325
12326 #define PIPE_CONF_CHECK_I(name) \
12327 if (current_config->name != pipe_config->name) { \
12328 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12329 "(expected %i, found %i)\n", \
12330 current_config->name, \
12331 pipe_config->name); \
12332 ret = false; \
12333 }
12334
12335 #define PIPE_CONF_CHECK_M_N(name) \
12336 if (!intel_compare_link_m_n(&current_config->name, \
12337 &pipe_config->name,\
12338 adjust)) { \
12339 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12340 "(expected tu %i gmch %i/%i link %i/%i, " \
12341 "found tu %i, gmch %i/%i link %i/%i)\n", \
12342 current_config->name.tu, \
12343 current_config->name.gmch_m, \
12344 current_config->name.gmch_n, \
12345 current_config->name.link_m, \
12346 current_config->name.link_n, \
12347 pipe_config->name.tu, \
12348 pipe_config->name.gmch_m, \
12349 pipe_config->name.gmch_n, \
12350 pipe_config->name.link_m, \
12351 pipe_config->name.link_n); \
12352 ret = false; \
12353 }
12354
12355 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12356 if (!intel_compare_link_m_n(&current_config->name, \
12357 &pipe_config->name, adjust) && \
12358 !intel_compare_link_m_n(&current_config->alt_name, \
12359 &pipe_config->name, adjust)) { \
12360 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12361 "(expected tu %i gmch %i/%i link %i/%i, " \
12362 "or tu %i gmch %i/%i link %i/%i, " \
12363 "found tu %i, gmch %i/%i link %i/%i)\n", \
12364 current_config->name.tu, \
12365 current_config->name.gmch_m, \
12366 current_config->name.gmch_n, \
12367 current_config->name.link_m, \
12368 current_config->name.link_n, \
12369 current_config->alt_name.tu, \
12370 current_config->alt_name.gmch_m, \
12371 current_config->alt_name.gmch_n, \
12372 current_config->alt_name.link_m, \
12373 current_config->alt_name.link_n, \
12374 pipe_config->name.tu, \
12375 pipe_config->name.gmch_m, \
12376 pipe_config->name.gmch_n, \
12377 pipe_config->name.link_m, \
12378 pipe_config->name.link_n); \
12379 ret = false; \
12380 }
12381
12382 /* This is required for BDW+ where there is only one set of registers for
12383 * switching between high and low RR.
12384 * This macro can be used whenever a comparison has to be made between one
12385 * hw state and multiple sw state variables.
12386 */
12387 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12388 if ((current_config->name != pipe_config->name) && \
12389 (current_config->alt_name != pipe_config->name)) { \
12390 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12391 "(expected %i or %i, found %i)\n", \
12392 current_config->name, \
12393 current_config->alt_name, \
12394 pipe_config->name); \
12395 ret = false; \
12396 }
12397
12398 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12399 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12400 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12401 "(expected %i, found %i)\n", \
12402 current_config->name & (mask), \
12403 pipe_config->name & (mask)); \
12404 ret = false; \
12405 }
12406
12407 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12408 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12409 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12410 "(expected %i, found %i)\n", \
12411 current_config->name, \
12412 pipe_config->name); \
12413 ret = false; \
12414 }
12415
12416 #define PIPE_CONF_QUIRK(quirk) \
12417 ((current_config->quirks | pipe_config->quirks) & (quirk))
12418
12419 PIPE_CONF_CHECK_I(cpu_transcoder);
12420
12421 PIPE_CONF_CHECK_I(has_pch_encoder);
12422 PIPE_CONF_CHECK_I(fdi_lanes);
12423 PIPE_CONF_CHECK_M_N(fdi_m_n);
12424
12425 PIPE_CONF_CHECK_I(has_dp_encoder);
12426 PIPE_CONF_CHECK_I(lane_count);
12427
12428 if (INTEL_INFO(dev)->gen < 8) {
12429 PIPE_CONF_CHECK_M_N(dp_m_n);
12430
12431 PIPE_CONF_CHECK_I(has_drrs);
12432 if (current_config->has_drrs)
12433 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12434 } else
12435 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12436
12437 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12438 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12439 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12440 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12441 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12442 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12443
12444 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12445 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12446 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12447 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12448 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12449 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12450
12451 PIPE_CONF_CHECK_I(pixel_multiplier);
12452 PIPE_CONF_CHECK_I(has_hdmi_sink);
12453 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12454 IS_VALLEYVIEW(dev))
12455 PIPE_CONF_CHECK_I(limited_color_range);
12456 PIPE_CONF_CHECK_I(has_infoframe);
12457
12458 PIPE_CONF_CHECK_I(has_audio);
12459
12460 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12461 DRM_MODE_FLAG_INTERLACE);
12462
12463 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12464 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12465 DRM_MODE_FLAG_PHSYNC);
12466 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12467 DRM_MODE_FLAG_NHSYNC);
12468 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12469 DRM_MODE_FLAG_PVSYNC);
12470 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12471 DRM_MODE_FLAG_NVSYNC);
12472 }
12473
12474 PIPE_CONF_CHECK_X(gmch_pfit.control);
12475 /* pfit ratios are autocomputed by the hw on gen4+ */
12476 if (INTEL_INFO(dev)->gen < 4)
12477 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12478 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12479
12480 if (!adjust) {
12481 PIPE_CONF_CHECK_I(pipe_src_w);
12482 PIPE_CONF_CHECK_I(pipe_src_h);
12483
12484 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12485 if (current_config->pch_pfit.enabled) {
12486 PIPE_CONF_CHECK_X(pch_pfit.pos);
12487 PIPE_CONF_CHECK_X(pch_pfit.size);
12488 }
12489
12490 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12491 }
12492
12493 /* BDW+ don't expose a synchronous way to read the state */
12494 if (IS_HASWELL(dev))
12495 PIPE_CONF_CHECK_I(ips_enabled);
12496
12497 PIPE_CONF_CHECK_I(double_wide);
12498
12499 PIPE_CONF_CHECK_X(ddi_pll_sel);
12500
12501 PIPE_CONF_CHECK_I(shared_dpll);
12502 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12503 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12504 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12505 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12506 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12507 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12508 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12509 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12510
12511 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12512 PIPE_CONF_CHECK_I(pipe_bpp);
12513
12514 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12515 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12516
12517 #undef PIPE_CONF_CHECK_X
12518 #undef PIPE_CONF_CHECK_I
12519 #undef PIPE_CONF_CHECK_I_ALT
12520 #undef PIPE_CONF_CHECK_FLAGS
12521 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12522 #undef PIPE_CONF_QUIRK
12523 #undef INTEL_ERR_OR_DBG_KMS
12524
12525 return ret;
12526 }
12527
12528 static void check_wm_state(struct drm_device *dev)
12529 {
12530 struct drm_i915_private *dev_priv = dev->dev_private;
12531 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12532 struct intel_crtc *intel_crtc;
12533 int plane;
12534
12535 if (INTEL_INFO(dev)->gen < 9)
12536 return;
12537
12538 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12539 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12540
12541 for_each_intel_crtc(dev, intel_crtc) {
12542 struct skl_ddb_entry *hw_entry, *sw_entry;
12543 const enum pipe pipe = intel_crtc->pipe;
12544
12545 if (!intel_crtc->active)
12546 continue;
12547
12548 /* planes */
12549 for_each_plane(dev_priv, pipe, plane) {
12550 hw_entry = &hw_ddb.plane[pipe][plane];
12551 sw_entry = &sw_ddb->plane[pipe][plane];
12552
12553 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12554 continue;
12555
12556 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12557 "(expected (%u,%u), found (%u,%u))\n",
12558 pipe_name(pipe), plane + 1,
12559 sw_entry->start, sw_entry->end,
12560 hw_entry->start, hw_entry->end);
12561 }
12562
12563 /* cursor */
12564 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12565 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12566
12567 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12568 continue;
12569
12570 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12571 "(expected (%u,%u), found (%u,%u))\n",
12572 pipe_name(pipe),
12573 sw_entry->start, sw_entry->end,
12574 hw_entry->start, hw_entry->end);
12575 }
12576 }
12577
12578 static void
12579 check_connector_state(struct drm_device *dev,
12580 struct drm_atomic_state *old_state)
12581 {
12582 struct drm_connector_state *old_conn_state;
12583 struct drm_connector *connector;
12584 int i;
12585
12586 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12587 struct drm_encoder *encoder = connector->encoder;
12588 struct drm_connector_state *state = connector->state;
12589
12590 /* This also checks the encoder/connector hw state with the
12591 * ->get_hw_state callbacks. */
12592 intel_connector_check_state(to_intel_connector(connector));
12593
12594 I915_STATE_WARN(state->best_encoder != encoder,
12595 "connector's atomic encoder doesn't match legacy encoder\n");
12596 }
12597 }
12598
12599 static void
12600 check_encoder_state(struct drm_device *dev)
12601 {
12602 struct intel_encoder *encoder;
12603 struct intel_connector *connector;
12604
12605 for_each_intel_encoder(dev, encoder) {
12606 bool enabled = false;
12607 enum pipe pipe;
12608
12609 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12610 encoder->base.base.id,
12611 encoder->base.name);
12612
12613 for_each_intel_connector(dev, connector) {
12614 if (connector->base.state->best_encoder != &encoder->base)
12615 continue;
12616 enabled = true;
12617
12618 I915_STATE_WARN(connector->base.state->crtc !=
12619 encoder->base.crtc,
12620 "connector's crtc doesn't match encoder crtc\n");
12621 }
12622
12623 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12624 "encoder's enabled state mismatch "
12625 "(expected %i, found %i)\n",
12626 !!encoder->base.crtc, enabled);
12627
12628 if (!encoder->base.crtc) {
12629 bool active;
12630
12631 active = encoder->get_hw_state(encoder, &pipe);
12632 I915_STATE_WARN(active,
12633 "encoder detached but still enabled on pipe %c.\n",
12634 pipe_name(pipe));
12635 }
12636 }
12637 }
12638
12639 static void
12640 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12641 {
12642 struct drm_i915_private *dev_priv = dev->dev_private;
12643 struct intel_encoder *encoder;
12644 struct drm_crtc_state *old_crtc_state;
12645 struct drm_crtc *crtc;
12646 int i;
12647
12648 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12650 struct intel_crtc_state *pipe_config, *sw_config;
12651 bool active;
12652
12653 if (!needs_modeset(crtc->state) &&
12654 !to_intel_crtc_state(crtc->state)->update_pipe)
12655 continue;
12656
12657 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12658 pipe_config = to_intel_crtc_state(old_crtc_state);
12659 memset(pipe_config, 0, sizeof(*pipe_config));
12660 pipe_config->base.crtc = crtc;
12661 pipe_config->base.state = old_state;
12662
12663 DRM_DEBUG_KMS("[CRTC:%d]\n",
12664 crtc->base.id);
12665
12666 active = dev_priv->display.get_pipe_config(intel_crtc,
12667 pipe_config);
12668
12669 /* hw state is inconsistent with the pipe quirk */
12670 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12671 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12672 active = crtc->state->active;
12673
12674 I915_STATE_WARN(crtc->state->active != active,
12675 "crtc active state doesn't match with hw state "
12676 "(expected %i, found %i)\n", crtc->state->active, active);
12677
12678 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12679 "transitional active state does not match atomic hw state "
12680 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12681
12682 for_each_encoder_on_crtc(dev, crtc, encoder) {
12683 enum pipe pipe;
12684
12685 active = encoder->get_hw_state(encoder, &pipe);
12686 I915_STATE_WARN(active != crtc->state->active,
12687 "[ENCODER:%i] active %i with crtc active %i\n",
12688 encoder->base.base.id, active, crtc->state->active);
12689
12690 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12691 "Encoder connected to wrong pipe %c\n",
12692 pipe_name(pipe));
12693
12694 if (active)
12695 encoder->get_config(encoder, pipe_config);
12696 }
12697
12698 if (!crtc->state->active)
12699 continue;
12700
12701 sw_config = to_intel_crtc_state(crtc->state);
12702 if (!intel_pipe_config_compare(dev, sw_config,
12703 pipe_config, false)) {
12704 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12705 intel_dump_pipe_config(intel_crtc, pipe_config,
12706 "[hw state]");
12707 intel_dump_pipe_config(intel_crtc, sw_config,
12708 "[sw state]");
12709 }
12710 }
12711 }
12712
12713 static void
12714 check_shared_dpll_state(struct drm_device *dev)
12715 {
12716 struct drm_i915_private *dev_priv = dev->dev_private;
12717 struct intel_crtc *crtc;
12718 struct intel_dpll_hw_state dpll_hw_state;
12719 int i;
12720
12721 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12722 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12723 int enabled_crtcs = 0, active_crtcs = 0;
12724 bool active;
12725
12726 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12727
12728 DRM_DEBUG_KMS("%s\n", pll->name);
12729
12730 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12731
12732 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12733 "more active pll users than references: %i vs %i\n",
12734 pll->active, hweight32(pll->config.crtc_mask));
12735 I915_STATE_WARN(pll->active && !pll->on,
12736 "pll in active use but not on in sw tracking\n");
12737 I915_STATE_WARN(pll->on && !pll->active,
12738 "pll in on but not on in use in sw tracking\n");
12739 I915_STATE_WARN(pll->on != active,
12740 "pll on state mismatch (expected %i, found %i)\n",
12741 pll->on, active);
12742
12743 for_each_intel_crtc(dev, crtc) {
12744 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12745 enabled_crtcs++;
12746 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12747 active_crtcs++;
12748 }
12749 I915_STATE_WARN(pll->active != active_crtcs,
12750 "pll active crtcs mismatch (expected %i, found %i)\n",
12751 pll->active, active_crtcs);
12752 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12753 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12754 hweight32(pll->config.crtc_mask), enabled_crtcs);
12755
12756 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12757 sizeof(dpll_hw_state)),
12758 "pll hw state mismatch\n");
12759 }
12760 }
12761
12762 static void
12763 intel_modeset_check_state(struct drm_device *dev,
12764 struct drm_atomic_state *old_state)
12765 {
12766 check_wm_state(dev);
12767 check_connector_state(dev, old_state);
12768 check_encoder_state(dev);
12769 check_crtc_state(dev, old_state);
12770 check_shared_dpll_state(dev);
12771 }
12772
12773 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12774 int dotclock)
12775 {
12776 /*
12777 * FDI already provided one idea for the dotclock.
12778 * Yell if the encoder disagrees.
12779 */
12780 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12781 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12782 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12783 }
12784
12785 static void update_scanline_offset(struct intel_crtc *crtc)
12786 {
12787 struct drm_device *dev = crtc->base.dev;
12788
12789 /*
12790 * The scanline counter increments at the leading edge of hsync.
12791 *
12792 * On most platforms it starts counting from vtotal-1 on the
12793 * first active line. That means the scanline counter value is
12794 * always one less than what we would expect. Ie. just after
12795 * start of vblank, which also occurs at start of hsync (on the
12796 * last active line), the scanline counter will read vblank_start-1.
12797 *
12798 * On gen2 the scanline counter starts counting from 1 instead
12799 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12800 * to keep the value positive), instead of adding one.
12801 *
12802 * On HSW+ the behaviour of the scanline counter depends on the output
12803 * type. For DP ports it behaves like most other platforms, but on HDMI
12804 * there's an extra 1 line difference. So we need to add two instead of
12805 * one to the value.
12806 */
12807 if (IS_GEN2(dev)) {
12808 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12809 int vtotal;
12810
12811 vtotal = adjusted_mode->crtc_vtotal;
12812 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12813 vtotal /= 2;
12814
12815 crtc->scanline_offset = vtotal - 1;
12816 } else if (HAS_DDI(dev) &&
12817 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12818 crtc->scanline_offset = 2;
12819 } else
12820 crtc->scanline_offset = 1;
12821 }
12822
12823 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12824 {
12825 struct drm_device *dev = state->dev;
12826 struct drm_i915_private *dev_priv = to_i915(dev);
12827 struct intel_shared_dpll_config *shared_dpll = NULL;
12828 struct intel_crtc *intel_crtc;
12829 struct intel_crtc_state *intel_crtc_state;
12830 struct drm_crtc *crtc;
12831 struct drm_crtc_state *crtc_state;
12832 int i;
12833
12834 if (!dev_priv->display.crtc_compute_clock)
12835 return;
12836
12837 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12838 int dpll;
12839
12840 intel_crtc = to_intel_crtc(crtc);
12841 intel_crtc_state = to_intel_crtc_state(crtc_state);
12842 dpll = intel_crtc_state->shared_dpll;
12843
12844 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12845 continue;
12846
12847 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12848
12849 if (!shared_dpll)
12850 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12851
12852 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12853 }
12854 }
12855
12856 /*
12857 * This implements the workaround described in the "notes" section of the mode
12858 * set sequence documentation. When going from no pipes or single pipe to
12859 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12860 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12861 */
12862 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12863 {
12864 struct drm_crtc_state *crtc_state;
12865 struct intel_crtc *intel_crtc;
12866 struct drm_crtc *crtc;
12867 struct intel_crtc_state *first_crtc_state = NULL;
12868 struct intel_crtc_state *other_crtc_state = NULL;
12869 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12870 int i;
12871
12872 /* look at all crtc's that are going to be enabled in during modeset */
12873 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12874 intel_crtc = to_intel_crtc(crtc);
12875
12876 if (!crtc_state->active || !needs_modeset(crtc_state))
12877 continue;
12878
12879 if (first_crtc_state) {
12880 other_crtc_state = to_intel_crtc_state(crtc_state);
12881 break;
12882 } else {
12883 first_crtc_state = to_intel_crtc_state(crtc_state);
12884 first_pipe = intel_crtc->pipe;
12885 }
12886 }
12887
12888 /* No workaround needed? */
12889 if (!first_crtc_state)
12890 return 0;
12891
12892 /* w/a possibly needed, check how many crtc's are already enabled. */
12893 for_each_intel_crtc(state->dev, intel_crtc) {
12894 struct intel_crtc_state *pipe_config;
12895
12896 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12897 if (IS_ERR(pipe_config))
12898 return PTR_ERR(pipe_config);
12899
12900 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12901
12902 if (!pipe_config->base.active ||
12903 needs_modeset(&pipe_config->base))
12904 continue;
12905
12906 /* 2 or more enabled crtcs means no need for w/a */
12907 if (enabled_pipe != INVALID_PIPE)
12908 return 0;
12909
12910 enabled_pipe = intel_crtc->pipe;
12911 }
12912
12913 if (enabled_pipe != INVALID_PIPE)
12914 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12915 else if (other_crtc_state)
12916 other_crtc_state->hsw_workaround_pipe = first_pipe;
12917
12918 return 0;
12919 }
12920
12921 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12922 {
12923 struct drm_crtc *crtc;
12924 struct drm_crtc_state *crtc_state;
12925 int ret = 0;
12926
12927 /* add all active pipes to the state */
12928 for_each_crtc(state->dev, crtc) {
12929 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12930 if (IS_ERR(crtc_state))
12931 return PTR_ERR(crtc_state);
12932
12933 if (!crtc_state->active || needs_modeset(crtc_state))
12934 continue;
12935
12936 crtc_state->mode_changed = true;
12937
12938 ret = drm_atomic_add_affected_connectors(state, crtc);
12939 if (ret)
12940 break;
12941
12942 ret = drm_atomic_add_affected_planes(state, crtc);
12943 if (ret)
12944 break;
12945 }
12946
12947 return ret;
12948 }
12949
12950 static int intel_modeset_checks(struct drm_atomic_state *state)
12951 {
12952 struct drm_device *dev = state->dev;
12953 struct drm_i915_private *dev_priv = dev->dev_private;
12954 int ret;
12955
12956 if (!check_digital_port_conflicts(state)) {
12957 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12958 return -EINVAL;
12959 }
12960
12961 /*
12962 * See if the config requires any additional preparation, e.g.
12963 * to adjust global state with pipes off. We need to do this
12964 * here so we can get the modeset_pipe updated config for the new
12965 * mode set on this crtc. For other crtcs we need to use the
12966 * adjusted_mode bits in the crtc directly.
12967 */
12968 if (dev_priv->display.modeset_calc_cdclk) {
12969 unsigned int cdclk;
12970
12971 ret = dev_priv->display.modeset_calc_cdclk(state);
12972
12973 cdclk = to_intel_atomic_state(state)->cdclk;
12974 if (!ret && cdclk != dev_priv->cdclk_freq)
12975 ret = intel_modeset_all_pipes(state);
12976
12977 if (ret < 0)
12978 return ret;
12979 } else
12980 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12981
12982 intel_modeset_clear_plls(state);
12983
12984 if (IS_HASWELL(dev))
12985 return haswell_mode_set_planes_workaround(state);
12986
12987 return 0;
12988 }
12989
12990 /**
12991 * intel_atomic_check - validate state object
12992 * @dev: drm device
12993 * @state: state to validate
12994 */
12995 static int intel_atomic_check(struct drm_device *dev,
12996 struct drm_atomic_state *state)
12997 {
12998 struct drm_crtc *crtc;
12999 struct drm_crtc_state *crtc_state;
13000 int ret, i;
13001 bool any_ms = false;
13002
13003 ret = drm_atomic_helper_check_modeset(dev, state);
13004 if (ret)
13005 return ret;
13006
13007 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13008 struct intel_crtc_state *pipe_config =
13009 to_intel_crtc_state(crtc_state);
13010
13011 /* Catch I915_MODE_FLAG_INHERITED */
13012 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13013 crtc_state->mode_changed = true;
13014
13015 if (!crtc_state->enable) {
13016 if (needs_modeset(crtc_state))
13017 any_ms = true;
13018 continue;
13019 }
13020
13021 if (!needs_modeset(crtc_state))
13022 continue;
13023
13024 /* FIXME: For only active_changed we shouldn't need to do any
13025 * state recomputation at all. */
13026
13027 ret = drm_atomic_add_affected_connectors(state, crtc);
13028 if (ret)
13029 return ret;
13030
13031 ret = intel_modeset_pipe_config(crtc, pipe_config);
13032 if (ret)
13033 return ret;
13034
13035 if (intel_pipe_config_compare(state->dev,
13036 to_intel_crtc_state(crtc->state),
13037 pipe_config, true)) {
13038 crtc_state->mode_changed = false;
13039 to_intel_crtc_state(crtc_state)->update_pipe = true;
13040 }
13041
13042 if (needs_modeset(crtc_state)) {
13043 any_ms = true;
13044
13045 ret = drm_atomic_add_affected_planes(state, crtc);
13046 if (ret)
13047 return ret;
13048 }
13049
13050 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13051 needs_modeset(crtc_state) ?
13052 "[modeset]" : "[fastset]");
13053 }
13054
13055 if (any_ms) {
13056 ret = intel_modeset_checks(state);
13057
13058 if (ret)
13059 return ret;
13060 } else
13061 to_intel_atomic_state(state)->cdclk =
13062 to_i915(state->dev)->cdclk_freq;
13063
13064 return drm_atomic_helper_check_planes(state->dev, state);
13065 }
13066
13067 /**
13068 * intel_atomic_commit - commit validated state object
13069 * @dev: DRM device
13070 * @state: the top-level driver state object
13071 * @async: asynchronous commit
13072 *
13073 * This function commits a top-level state object that has been validated
13074 * with drm_atomic_helper_check().
13075 *
13076 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13077 * we can only handle plane-related operations and do not yet support
13078 * asynchronous commit.
13079 *
13080 * RETURNS
13081 * Zero for success or -errno.
13082 */
13083 static int intel_atomic_commit(struct drm_device *dev,
13084 struct drm_atomic_state *state,
13085 bool async)
13086 {
13087 struct drm_i915_private *dev_priv = dev->dev_private;
13088 struct drm_crtc *crtc;
13089 struct drm_crtc_state *crtc_state;
13090 int ret = 0;
13091 int i;
13092 bool any_ms = false;
13093
13094 if (async) {
13095 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13096 return -EINVAL;
13097 }
13098
13099 ret = drm_atomic_helper_prepare_planes(dev, state);
13100 if (ret)
13101 return ret;
13102
13103 drm_atomic_helper_swap_state(dev, state);
13104
13105 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13107
13108 if (!needs_modeset(crtc->state))
13109 continue;
13110
13111 any_ms = true;
13112 intel_pre_plane_update(intel_crtc);
13113
13114 if (crtc_state->active) {
13115 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13116 dev_priv->display.crtc_disable(crtc);
13117 intel_crtc->active = false;
13118 intel_disable_shared_dpll(intel_crtc);
13119 }
13120 }
13121
13122 /* Only after disabling all output pipelines that will be changed can we
13123 * update the the output configuration. */
13124 intel_modeset_update_crtc_state(state);
13125
13126 if (any_ms) {
13127 intel_shared_dpll_commit(state);
13128
13129 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13130 modeset_update_crtc_power_domains(state);
13131 }
13132
13133 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13134 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13136 bool modeset = needs_modeset(crtc->state);
13137 bool update_pipe = !modeset &&
13138 to_intel_crtc_state(crtc->state)->update_pipe;
13139 unsigned long put_domains = 0;
13140
13141 if (modeset && crtc->state->active) {
13142 update_scanline_offset(to_intel_crtc(crtc));
13143 dev_priv->display.crtc_enable(crtc);
13144 }
13145
13146 if (update_pipe) {
13147 put_domains = modeset_get_crtc_power_domains(crtc);
13148
13149 /* make sure intel_modeset_check_state runs */
13150 any_ms = true;
13151 }
13152
13153 if (!modeset)
13154 intel_pre_plane_update(intel_crtc);
13155
13156 if (crtc->state->active &&
13157 (crtc->state->planes_changed || update_pipe))
13158 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13159
13160 if (put_domains)
13161 modeset_put_power_domains(dev_priv, put_domains);
13162
13163 intel_post_plane_update(intel_crtc);
13164 }
13165
13166 /* FIXME: add subpixel order */
13167
13168 drm_atomic_helper_wait_for_vblanks(dev, state);
13169 drm_atomic_helper_cleanup_planes(dev, state);
13170
13171 if (any_ms)
13172 intel_modeset_check_state(dev, state);
13173
13174 drm_atomic_state_free(state);
13175
13176 return 0;
13177 }
13178
13179 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13180 {
13181 struct drm_device *dev = crtc->dev;
13182 struct drm_atomic_state *state;
13183 struct drm_crtc_state *crtc_state;
13184 int ret;
13185
13186 state = drm_atomic_state_alloc(dev);
13187 if (!state) {
13188 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13189 crtc->base.id);
13190 return;
13191 }
13192
13193 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13194
13195 retry:
13196 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13197 ret = PTR_ERR_OR_ZERO(crtc_state);
13198 if (!ret) {
13199 if (!crtc_state->active)
13200 goto out;
13201
13202 crtc_state->mode_changed = true;
13203 ret = drm_atomic_commit(state);
13204 }
13205
13206 if (ret == -EDEADLK) {
13207 drm_atomic_state_clear(state);
13208 drm_modeset_backoff(state->acquire_ctx);
13209 goto retry;
13210 }
13211
13212 if (ret)
13213 out:
13214 drm_atomic_state_free(state);
13215 }
13216
13217 #undef for_each_intel_crtc_masked
13218
13219 static const struct drm_crtc_funcs intel_crtc_funcs = {
13220 .gamma_set = intel_crtc_gamma_set,
13221 .set_config = drm_atomic_helper_set_config,
13222 .destroy = intel_crtc_destroy,
13223 .page_flip = intel_crtc_page_flip,
13224 .atomic_duplicate_state = intel_crtc_duplicate_state,
13225 .atomic_destroy_state = intel_crtc_destroy_state,
13226 };
13227
13228 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13229 struct intel_shared_dpll *pll,
13230 struct intel_dpll_hw_state *hw_state)
13231 {
13232 uint32_t val;
13233
13234 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13235 return false;
13236
13237 val = I915_READ(PCH_DPLL(pll->id));
13238 hw_state->dpll = val;
13239 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13240 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13241
13242 return val & DPLL_VCO_ENABLE;
13243 }
13244
13245 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13246 struct intel_shared_dpll *pll)
13247 {
13248 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13249 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13250 }
13251
13252 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13253 struct intel_shared_dpll *pll)
13254 {
13255 /* PCH refclock must be enabled first */
13256 ibx_assert_pch_refclk_enabled(dev_priv);
13257
13258 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13259
13260 /* Wait for the clocks to stabilize. */
13261 POSTING_READ(PCH_DPLL(pll->id));
13262 udelay(150);
13263
13264 /* The pixel multiplier can only be updated once the
13265 * DPLL is enabled and the clocks are stable.
13266 *
13267 * So write it again.
13268 */
13269 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13270 POSTING_READ(PCH_DPLL(pll->id));
13271 udelay(200);
13272 }
13273
13274 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13275 struct intel_shared_dpll *pll)
13276 {
13277 struct drm_device *dev = dev_priv->dev;
13278 struct intel_crtc *crtc;
13279
13280 /* Make sure no transcoder isn't still depending on us. */
13281 for_each_intel_crtc(dev, crtc) {
13282 if (intel_crtc_to_shared_dpll(crtc) == pll)
13283 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13284 }
13285
13286 I915_WRITE(PCH_DPLL(pll->id), 0);
13287 POSTING_READ(PCH_DPLL(pll->id));
13288 udelay(200);
13289 }
13290
13291 static char *ibx_pch_dpll_names[] = {
13292 "PCH DPLL A",
13293 "PCH DPLL B",
13294 };
13295
13296 static void ibx_pch_dpll_init(struct drm_device *dev)
13297 {
13298 struct drm_i915_private *dev_priv = dev->dev_private;
13299 int i;
13300
13301 dev_priv->num_shared_dpll = 2;
13302
13303 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13304 dev_priv->shared_dplls[i].id = i;
13305 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13306 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13307 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13308 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13309 dev_priv->shared_dplls[i].get_hw_state =
13310 ibx_pch_dpll_get_hw_state;
13311 }
13312 }
13313
13314 static void intel_shared_dpll_init(struct drm_device *dev)
13315 {
13316 struct drm_i915_private *dev_priv = dev->dev_private;
13317
13318 if (HAS_DDI(dev))
13319 intel_ddi_pll_init(dev);
13320 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13321 ibx_pch_dpll_init(dev);
13322 else
13323 dev_priv->num_shared_dpll = 0;
13324
13325 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13326 }
13327
13328 /**
13329 * intel_prepare_plane_fb - Prepare fb for usage on plane
13330 * @plane: drm plane to prepare for
13331 * @fb: framebuffer to prepare for presentation
13332 *
13333 * Prepares a framebuffer for usage on a display plane. Generally this
13334 * involves pinning the underlying object and updating the frontbuffer tracking
13335 * bits. Some older platforms need special physical address handling for
13336 * cursor planes.
13337 *
13338 * Returns 0 on success, negative error code on failure.
13339 */
13340 int
13341 intel_prepare_plane_fb(struct drm_plane *plane,
13342 const struct drm_plane_state *new_state)
13343 {
13344 struct drm_device *dev = plane->dev;
13345 struct drm_framebuffer *fb = new_state->fb;
13346 struct intel_plane *intel_plane = to_intel_plane(plane);
13347 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13348 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13349 int ret = 0;
13350
13351 if (!obj && !old_obj)
13352 return 0;
13353
13354 ret = i915_mutex_lock_interruptible(dev);
13355 if (ret)
13356 return ret;
13357
13358 if (!obj) {
13359 ret = 0;
13360 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13361 INTEL_INFO(dev)->cursor_needs_physical) {
13362 int align = IS_I830(dev) ? 16 * 1024 : 256;
13363 ret = i915_gem_object_attach_phys(obj, align);
13364 if (ret)
13365 DRM_DEBUG_KMS("failed to attach phys object\n");
13366 } else {
13367 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13368 }
13369
13370 if (ret == 0)
13371 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13372
13373 mutex_unlock(&dev->struct_mutex);
13374
13375 return ret;
13376 }
13377
13378 /**
13379 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13380 * @plane: drm plane to clean up for
13381 * @fb: old framebuffer that was on plane
13382 *
13383 * Cleans up a framebuffer that has just been removed from a plane.
13384 */
13385 void
13386 intel_cleanup_plane_fb(struct drm_plane *plane,
13387 const struct drm_plane_state *old_state)
13388 {
13389 struct drm_device *dev = plane->dev;
13390 struct intel_plane *intel_plane = to_intel_plane(plane);
13391 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13392 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13393
13394 if (!obj && !old_obj)
13395 return;
13396
13397 mutex_lock(&dev->struct_mutex);
13398 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13399 !INTEL_INFO(dev)->cursor_needs_physical))
13400 intel_unpin_fb_obj(old_state->fb, old_state);
13401
13402 /* prepare_fb aborted? */
13403 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13404 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13405 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13406 mutex_unlock(&dev->struct_mutex);
13407 }
13408
13409 int
13410 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13411 {
13412 int max_scale;
13413 struct drm_device *dev;
13414 struct drm_i915_private *dev_priv;
13415 int crtc_clock, cdclk;
13416
13417 if (!intel_crtc || !crtc_state)
13418 return DRM_PLANE_HELPER_NO_SCALING;
13419
13420 dev = intel_crtc->base.dev;
13421 dev_priv = dev->dev_private;
13422 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13423 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13424
13425 if (!crtc_clock || !cdclk)
13426 return DRM_PLANE_HELPER_NO_SCALING;
13427
13428 /*
13429 * skl max scale is lower of:
13430 * close to 3 but not 3, -1 is for that purpose
13431 * or
13432 * cdclk/crtc_clock
13433 */
13434 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13435
13436 return max_scale;
13437 }
13438
13439 static int
13440 intel_check_primary_plane(struct drm_plane *plane,
13441 struct intel_crtc_state *crtc_state,
13442 struct intel_plane_state *state)
13443 {
13444 struct drm_crtc *crtc = state->base.crtc;
13445 struct drm_framebuffer *fb = state->base.fb;
13446 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13447 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13448 bool can_position = false;
13449
13450 /* use scaler when colorkey is not required */
13451 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13452 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13453 min_scale = 1;
13454 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13455 can_position = true;
13456 }
13457
13458 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13459 &state->dst, &state->clip,
13460 min_scale, max_scale,
13461 can_position, true,
13462 &state->visible);
13463 }
13464
13465 static void
13466 intel_commit_primary_plane(struct drm_plane *plane,
13467 struct intel_plane_state *state)
13468 {
13469 struct drm_crtc *crtc = state->base.crtc;
13470 struct drm_framebuffer *fb = state->base.fb;
13471 struct drm_device *dev = plane->dev;
13472 struct drm_i915_private *dev_priv = dev->dev_private;
13473
13474 crtc = crtc ? crtc : plane->crtc;
13475
13476 dev_priv->display.update_primary_plane(crtc, fb,
13477 state->src.x1 >> 16,
13478 state->src.y1 >> 16);
13479 }
13480
13481 static void
13482 intel_disable_primary_plane(struct drm_plane *plane,
13483 struct drm_crtc *crtc)
13484 {
13485 struct drm_device *dev = plane->dev;
13486 struct drm_i915_private *dev_priv = dev->dev_private;
13487
13488 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13489 }
13490
13491 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13492 struct drm_crtc_state *old_crtc_state)
13493 {
13494 struct drm_device *dev = crtc->dev;
13495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13496 struct intel_crtc_state *old_intel_state =
13497 to_intel_crtc_state(old_crtc_state);
13498 bool modeset = needs_modeset(crtc->state);
13499
13500 if (intel_crtc->atomic.update_wm_pre)
13501 intel_update_watermarks(crtc);
13502
13503 /* Perform vblank evasion around commit operation */
13504 intel_pipe_update_start(intel_crtc);
13505
13506 if (modeset)
13507 return;
13508
13509 if (to_intel_crtc_state(crtc->state)->update_pipe)
13510 intel_update_pipe_config(intel_crtc, old_intel_state);
13511 else if (INTEL_INFO(dev)->gen >= 9)
13512 skl_detach_scalers(intel_crtc);
13513 }
13514
13515 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13516 struct drm_crtc_state *old_crtc_state)
13517 {
13518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13519
13520 intel_pipe_update_end(intel_crtc);
13521 }
13522
13523 /**
13524 * intel_plane_destroy - destroy a plane
13525 * @plane: plane to destroy
13526 *
13527 * Common destruction function for all types of planes (primary, cursor,
13528 * sprite).
13529 */
13530 void intel_plane_destroy(struct drm_plane *plane)
13531 {
13532 struct intel_plane *intel_plane = to_intel_plane(plane);
13533 drm_plane_cleanup(plane);
13534 kfree(intel_plane);
13535 }
13536
13537 const struct drm_plane_funcs intel_plane_funcs = {
13538 .update_plane = drm_atomic_helper_update_plane,
13539 .disable_plane = drm_atomic_helper_disable_plane,
13540 .destroy = intel_plane_destroy,
13541 .set_property = drm_atomic_helper_plane_set_property,
13542 .atomic_get_property = intel_plane_atomic_get_property,
13543 .atomic_set_property = intel_plane_atomic_set_property,
13544 .atomic_duplicate_state = intel_plane_duplicate_state,
13545 .atomic_destroy_state = intel_plane_destroy_state,
13546
13547 };
13548
13549 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13550 int pipe)
13551 {
13552 struct intel_plane *primary;
13553 struct intel_plane_state *state;
13554 const uint32_t *intel_primary_formats;
13555 unsigned int num_formats;
13556
13557 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13558 if (primary == NULL)
13559 return NULL;
13560
13561 state = intel_create_plane_state(&primary->base);
13562 if (!state) {
13563 kfree(primary);
13564 return NULL;
13565 }
13566 primary->base.state = &state->base;
13567
13568 primary->can_scale = false;
13569 primary->max_downscale = 1;
13570 if (INTEL_INFO(dev)->gen >= 9) {
13571 primary->can_scale = true;
13572 state->scaler_id = -1;
13573 }
13574 primary->pipe = pipe;
13575 primary->plane = pipe;
13576 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13577 primary->check_plane = intel_check_primary_plane;
13578 primary->commit_plane = intel_commit_primary_plane;
13579 primary->disable_plane = intel_disable_primary_plane;
13580 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13581 primary->plane = !pipe;
13582
13583 if (INTEL_INFO(dev)->gen >= 9) {
13584 intel_primary_formats = skl_primary_formats;
13585 num_formats = ARRAY_SIZE(skl_primary_formats);
13586 } else if (INTEL_INFO(dev)->gen >= 4) {
13587 intel_primary_formats = i965_primary_formats;
13588 num_formats = ARRAY_SIZE(i965_primary_formats);
13589 } else {
13590 intel_primary_formats = i8xx_primary_formats;
13591 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13592 }
13593
13594 drm_universal_plane_init(dev, &primary->base, 0,
13595 &intel_plane_funcs,
13596 intel_primary_formats, num_formats,
13597 DRM_PLANE_TYPE_PRIMARY);
13598
13599 if (INTEL_INFO(dev)->gen >= 4)
13600 intel_create_rotation_property(dev, primary);
13601
13602 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13603
13604 return &primary->base;
13605 }
13606
13607 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13608 {
13609 if (!dev->mode_config.rotation_property) {
13610 unsigned long flags = BIT(DRM_ROTATE_0) |
13611 BIT(DRM_ROTATE_180);
13612
13613 if (INTEL_INFO(dev)->gen >= 9)
13614 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13615
13616 dev->mode_config.rotation_property =
13617 drm_mode_create_rotation_property(dev, flags);
13618 }
13619 if (dev->mode_config.rotation_property)
13620 drm_object_attach_property(&plane->base.base,
13621 dev->mode_config.rotation_property,
13622 plane->base.state->rotation);
13623 }
13624
13625 static int
13626 intel_check_cursor_plane(struct drm_plane *plane,
13627 struct intel_crtc_state *crtc_state,
13628 struct intel_plane_state *state)
13629 {
13630 struct drm_crtc *crtc = crtc_state->base.crtc;
13631 struct drm_framebuffer *fb = state->base.fb;
13632 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13633 unsigned stride;
13634 int ret;
13635
13636 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13637 &state->dst, &state->clip,
13638 DRM_PLANE_HELPER_NO_SCALING,
13639 DRM_PLANE_HELPER_NO_SCALING,
13640 true, true, &state->visible);
13641 if (ret)
13642 return ret;
13643
13644 /* if we want to turn off the cursor ignore width and height */
13645 if (!obj)
13646 return 0;
13647
13648 /* Check for which cursor types we support */
13649 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13650 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13651 state->base.crtc_w, state->base.crtc_h);
13652 return -EINVAL;
13653 }
13654
13655 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13656 if (obj->base.size < stride * state->base.crtc_h) {
13657 DRM_DEBUG_KMS("buffer is too small\n");
13658 return -ENOMEM;
13659 }
13660
13661 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13662 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13663 return -EINVAL;
13664 }
13665
13666 return 0;
13667 }
13668
13669 static void
13670 intel_disable_cursor_plane(struct drm_plane *plane,
13671 struct drm_crtc *crtc)
13672 {
13673 intel_crtc_update_cursor(crtc, false);
13674 }
13675
13676 static void
13677 intel_commit_cursor_plane(struct drm_plane *plane,
13678 struct intel_plane_state *state)
13679 {
13680 struct drm_crtc *crtc = state->base.crtc;
13681 struct drm_device *dev = plane->dev;
13682 struct intel_crtc *intel_crtc;
13683 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13684 uint32_t addr;
13685
13686 crtc = crtc ? crtc : plane->crtc;
13687 intel_crtc = to_intel_crtc(crtc);
13688
13689 if (intel_crtc->cursor_bo == obj)
13690 goto update;
13691
13692 if (!obj)
13693 addr = 0;
13694 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13695 addr = i915_gem_obj_ggtt_offset(obj);
13696 else
13697 addr = obj->phys_handle->busaddr;
13698
13699 intel_crtc->cursor_addr = addr;
13700 intel_crtc->cursor_bo = obj;
13701
13702 update:
13703 intel_crtc_update_cursor(crtc, state->visible);
13704 }
13705
13706 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13707 int pipe)
13708 {
13709 struct intel_plane *cursor;
13710 struct intel_plane_state *state;
13711
13712 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13713 if (cursor == NULL)
13714 return NULL;
13715
13716 state = intel_create_plane_state(&cursor->base);
13717 if (!state) {
13718 kfree(cursor);
13719 return NULL;
13720 }
13721 cursor->base.state = &state->base;
13722
13723 cursor->can_scale = false;
13724 cursor->max_downscale = 1;
13725 cursor->pipe = pipe;
13726 cursor->plane = pipe;
13727 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13728 cursor->check_plane = intel_check_cursor_plane;
13729 cursor->commit_plane = intel_commit_cursor_plane;
13730 cursor->disable_plane = intel_disable_cursor_plane;
13731
13732 drm_universal_plane_init(dev, &cursor->base, 0,
13733 &intel_plane_funcs,
13734 intel_cursor_formats,
13735 ARRAY_SIZE(intel_cursor_formats),
13736 DRM_PLANE_TYPE_CURSOR);
13737
13738 if (INTEL_INFO(dev)->gen >= 4) {
13739 if (!dev->mode_config.rotation_property)
13740 dev->mode_config.rotation_property =
13741 drm_mode_create_rotation_property(dev,
13742 BIT(DRM_ROTATE_0) |
13743 BIT(DRM_ROTATE_180));
13744 if (dev->mode_config.rotation_property)
13745 drm_object_attach_property(&cursor->base.base,
13746 dev->mode_config.rotation_property,
13747 state->base.rotation);
13748 }
13749
13750 if (INTEL_INFO(dev)->gen >=9)
13751 state->scaler_id = -1;
13752
13753 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13754
13755 return &cursor->base;
13756 }
13757
13758 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13759 struct intel_crtc_state *crtc_state)
13760 {
13761 int i;
13762 struct intel_scaler *intel_scaler;
13763 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13764
13765 for (i = 0; i < intel_crtc->num_scalers; i++) {
13766 intel_scaler = &scaler_state->scalers[i];
13767 intel_scaler->in_use = 0;
13768 intel_scaler->mode = PS_SCALER_MODE_DYN;
13769 }
13770
13771 scaler_state->scaler_id = -1;
13772 }
13773
13774 static void intel_crtc_init(struct drm_device *dev, int pipe)
13775 {
13776 struct drm_i915_private *dev_priv = dev->dev_private;
13777 struct intel_crtc *intel_crtc;
13778 struct intel_crtc_state *crtc_state = NULL;
13779 struct drm_plane *primary = NULL;
13780 struct drm_plane *cursor = NULL;
13781 int i, ret;
13782
13783 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13784 if (intel_crtc == NULL)
13785 return;
13786
13787 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13788 if (!crtc_state)
13789 goto fail;
13790 intel_crtc->config = crtc_state;
13791 intel_crtc->base.state = &crtc_state->base;
13792 crtc_state->base.crtc = &intel_crtc->base;
13793
13794 /* initialize shared scalers */
13795 if (INTEL_INFO(dev)->gen >= 9) {
13796 if (pipe == PIPE_C)
13797 intel_crtc->num_scalers = 1;
13798 else
13799 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13800
13801 skl_init_scalers(dev, intel_crtc, crtc_state);
13802 }
13803
13804 primary = intel_primary_plane_create(dev, pipe);
13805 if (!primary)
13806 goto fail;
13807
13808 cursor = intel_cursor_plane_create(dev, pipe);
13809 if (!cursor)
13810 goto fail;
13811
13812 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13813 cursor, &intel_crtc_funcs);
13814 if (ret)
13815 goto fail;
13816
13817 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13818 for (i = 0; i < 256; i++) {
13819 intel_crtc->lut_r[i] = i;
13820 intel_crtc->lut_g[i] = i;
13821 intel_crtc->lut_b[i] = i;
13822 }
13823
13824 /*
13825 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13826 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13827 */
13828 intel_crtc->pipe = pipe;
13829 intel_crtc->plane = pipe;
13830 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13831 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13832 intel_crtc->plane = !pipe;
13833 }
13834
13835 intel_crtc->cursor_base = ~0;
13836 intel_crtc->cursor_cntl = ~0;
13837 intel_crtc->cursor_size = ~0;
13838
13839 intel_crtc->wm.cxsr_allowed = true;
13840
13841 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13842 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13843 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13844 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13845
13846 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13847
13848 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13849 return;
13850
13851 fail:
13852 if (primary)
13853 drm_plane_cleanup(primary);
13854 if (cursor)
13855 drm_plane_cleanup(cursor);
13856 kfree(crtc_state);
13857 kfree(intel_crtc);
13858 }
13859
13860 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13861 {
13862 struct drm_encoder *encoder = connector->base.encoder;
13863 struct drm_device *dev = connector->base.dev;
13864
13865 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13866
13867 if (!encoder || WARN_ON(!encoder->crtc))
13868 return INVALID_PIPE;
13869
13870 return to_intel_crtc(encoder->crtc)->pipe;
13871 }
13872
13873 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13874 struct drm_file *file)
13875 {
13876 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13877 struct drm_crtc *drmmode_crtc;
13878 struct intel_crtc *crtc;
13879
13880 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13881
13882 if (!drmmode_crtc) {
13883 DRM_ERROR("no such CRTC id\n");
13884 return -ENOENT;
13885 }
13886
13887 crtc = to_intel_crtc(drmmode_crtc);
13888 pipe_from_crtc_id->pipe = crtc->pipe;
13889
13890 return 0;
13891 }
13892
13893 static int intel_encoder_clones(struct intel_encoder *encoder)
13894 {
13895 struct drm_device *dev = encoder->base.dev;
13896 struct intel_encoder *source_encoder;
13897 int index_mask = 0;
13898 int entry = 0;
13899
13900 for_each_intel_encoder(dev, source_encoder) {
13901 if (encoders_cloneable(encoder, source_encoder))
13902 index_mask |= (1 << entry);
13903
13904 entry++;
13905 }
13906
13907 return index_mask;
13908 }
13909
13910 static bool has_edp_a(struct drm_device *dev)
13911 {
13912 struct drm_i915_private *dev_priv = dev->dev_private;
13913
13914 if (!IS_MOBILE(dev))
13915 return false;
13916
13917 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13918 return false;
13919
13920 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13921 return false;
13922
13923 return true;
13924 }
13925
13926 static bool intel_crt_present(struct drm_device *dev)
13927 {
13928 struct drm_i915_private *dev_priv = dev->dev_private;
13929
13930 if (INTEL_INFO(dev)->gen >= 9)
13931 return false;
13932
13933 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13934 return false;
13935
13936 if (IS_CHERRYVIEW(dev))
13937 return false;
13938
13939 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13940 return false;
13941
13942 return true;
13943 }
13944
13945 static void intel_setup_outputs(struct drm_device *dev)
13946 {
13947 struct drm_i915_private *dev_priv = dev->dev_private;
13948 struct intel_encoder *encoder;
13949 bool dpd_is_edp = false;
13950
13951 intel_lvds_init(dev);
13952
13953 if (intel_crt_present(dev))
13954 intel_crt_init(dev);
13955
13956 if (IS_BROXTON(dev)) {
13957 /*
13958 * FIXME: Broxton doesn't support port detection via the
13959 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13960 * detect the ports.
13961 */
13962 intel_ddi_init(dev, PORT_A);
13963 intel_ddi_init(dev, PORT_B);
13964 intel_ddi_init(dev, PORT_C);
13965 } else if (HAS_DDI(dev)) {
13966 int found;
13967
13968 /*
13969 * Haswell uses DDI functions to detect digital outputs.
13970 * On SKL pre-D0 the strap isn't connected, so we assume
13971 * it's there.
13972 */
13973 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13974 /* WaIgnoreDDIAStrap: skl */
13975 if (found || IS_SKYLAKE(dev))
13976 intel_ddi_init(dev, PORT_A);
13977
13978 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13979 * register */
13980 found = I915_READ(SFUSE_STRAP);
13981
13982 if (found & SFUSE_STRAP_DDIB_DETECTED)
13983 intel_ddi_init(dev, PORT_B);
13984 if (found & SFUSE_STRAP_DDIC_DETECTED)
13985 intel_ddi_init(dev, PORT_C);
13986 if (found & SFUSE_STRAP_DDID_DETECTED)
13987 intel_ddi_init(dev, PORT_D);
13988 /*
13989 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13990 */
13991 if (IS_SKYLAKE(dev) &&
13992 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13993 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13994 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13995 intel_ddi_init(dev, PORT_E);
13996
13997 } else if (HAS_PCH_SPLIT(dev)) {
13998 int found;
13999 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14000
14001 if (has_edp_a(dev))
14002 intel_dp_init(dev, DP_A, PORT_A);
14003
14004 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14005 /* PCH SDVOB multiplex with HDMIB */
14006 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14007 if (!found)
14008 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14009 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14010 intel_dp_init(dev, PCH_DP_B, PORT_B);
14011 }
14012
14013 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14014 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14015
14016 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14017 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14018
14019 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14020 intel_dp_init(dev, PCH_DP_C, PORT_C);
14021
14022 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14023 intel_dp_init(dev, PCH_DP_D, PORT_D);
14024 } else if (IS_VALLEYVIEW(dev)) {
14025 /*
14026 * The DP_DETECTED bit is the latched state of the DDC
14027 * SDA pin at boot. However since eDP doesn't require DDC
14028 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14029 * eDP ports may have been muxed to an alternate function.
14030 * Thus we can't rely on the DP_DETECTED bit alone to detect
14031 * eDP ports. Consult the VBT as well as DP_DETECTED to
14032 * detect eDP ports.
14033 */
14034 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14035 !intel_dp_is_edp(dev, PORT_B))
14036 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14037 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14038 intel_dp_is_edp(dev, PORT_B))
14039 intel_dp_init(dev, VLV_DP_B, PORT_B);
14040
14041 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14042 !intel_dp_is_edp(dev, PORT_C))
14043 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14044 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14045 intel_dp_is_edp(dev, PORT_C))
14046 intel_dp_init(dev, VLV_DP_C, PORT_C);
14047
14048 if (IS_CHERRYVIEW(dev)) {
14049 /* eDP not supported on port D, so don't check VBT */
14050 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14051 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14052 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14053 intel_dp_init(dev, CHV_DP_D, PORT_D);
14054 }
14055
14056 intel_dsi_init(dev);
14057 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14058 bool found = false;
14059
14060 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14061 DRM_DEBUG_KMS("probing SDVOB\n");
14062 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14063 if (!found && IS_G4X(dev)) {
14064 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14065 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14066 }
14067
14068 if (!found && IS_G4X(dev))
14069 intel_dp_init(dev, DP_B, PORT_B);
14070 }
14071
14072 /* Before G4X SDVOC doesn't have its own detect register */
14073
14074 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14075 DRM_DEBUG_KMS("probing SDVOC\n");
14076 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14077 }
14078
14079 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14080
14081 if (IS_G4X(dev)) {
14082 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14083 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14084 }
14085 if (IS_G4X(dev))
14086 intel_dp_init(dev, DP_C, PORT_C);
14087 }
14088
14089 if (IS_G4X(dev) &&
14090 (I915_READ(DP_D) & DP_DETECTED))
14091 intel_dp_init(dev, DP_D, PORT_D);
14092 } else if (IS_GEN2(dev))
14093 intel_dvo_init(dev);
14094
14095 if (SUPPORTS_TV(dev))
14096 intel_tv_init(dev);
14097
14098 intel_psr_init(dev);
14099
14100 for_each_intel_encoder(dev, encoder) {
14101 encoder->base.possible_crtcs = encoder->crtc_mask;
14102 encoder->base.possible_clones =
14103 intel_encoder_clones(encoder);
14104 }
14105
14106 intel_init_pch_refclk(dev);
14107
14108 drm_helper_move_panel_connectors_to_head(dev);
14109 }
14110
14111 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14112 {
14113 struct drm_device *dev = fb->dev;
14114 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14115
14116 drm_framebuffer_cleanup(fb);
14117 mutex_lock(&dev->struct_mutex);
14118 WARN_ON(!intel_fb->obj->framebuffer_references--);
14119 drm_gem_object_unreference(&intel_fb->obj->base);
14120 mutex_unlock(&dev->struct_mutex);
14121 kfree(intel_fb);
14122 }
14123
14124 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14125 struct drm_file *file,
14126 unsigned int *handle)
14127 {
14128 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14129 struct drm_i915_gem_object *obj = intel_fb->obj;
14130
14131 return drm_gem_handle_create(file, &obj->base, handle);
14132 }
14133
14134 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14135 struct drm_file *file,
14136 unsigned flags, unsigned color,
14137 struct drm_clip_rect *clips,
14138 unsigned num_clips)
14139 {
14140 struct drm_device *dev = fb->dev;
14141 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14142 struct drm_i915_gem_object *obj = intel_fb->obj;
14143
14144 mutex_lock(&dev->struct_mutex);
14145 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14146 mutex_unlock(&dev->struct_mutex);
14147
14148 return 0;
14149 }
14150
14151 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14152 .destroy = intel_user_framebuffer_destroy,
14153 .create_handle = intel_user_framebuffer_create_handle,
14154 .dirty = intel_user_framebuffer_dirty,
14155 };
14156
14157 static
14158 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14159 uint32_t pixel_format)
14160 {
14161 u32 gen = INTEL_INFO(dev)->gen;
14162
14163 if (gen >= 9) {
14164 /* "The stride in bytes must not exceed the of the size of 8K
14165 * pixels and 32K bytes."
14166 */
14167 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14168 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14169 return 32*1024;
14170 } else if (gen >= 4) {
14171 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14172 return 16*1024;
14173 else
14174 return 32*1024;
14175 } else if (gen >= 3) {
14176 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14177 return 8*1024;
14178 else
14179 return 16*1024;
14180 } else {
14181 /* XXX DSPC is limited to 4k tiled */
14182 return 8*1024;
14183 }
14184 }
14185
14186 static int intel_framebuffer_init(struct drm_device *dev,
14187 struct intel_framebuffer *intel_fb,
14188 struct drm_mode_fb_cmd2 *mode_cmd,
14189 struct drm_i915_gem_object *obj)
14190 {
14191 unsigned int aligned_height;
14192 int ret;
14193 u32 pitch_limit, stride_alignment;
14194
14195 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14196
14197 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14198 /* Enforce that fb modifier and tiling mode match, but only for
14199 * X-tiled. This is needed for FBC. */
14200 if (!!(obj->tiling_mode == I915_TILING_X) !=
14201 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14202 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14203 return -EINVAL;
14204 }
14205 } else {
14206 if (obj->tiling_mode == I915_TILING_X)
14207 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14208 else if (obj->tiling_mode == I915_TILING_Y) {
14209 DRM_DEBUG("No Y tiling for legacy addfb\n");
14210 return -EINVAL;
14211 }
14212 }
14213
14214 /* Passed in modifier sanity checking. */
14215 switch (mode_cmd->modifier[0]) {
14216 case I915_FORMAT_MOD_Y_TILED:
14217 case I915_FORMAT_MOD_Yf_TILED:
14218 if (INTEL_INFO(dev)->gen < 9) {
14219 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14220 mode_cmd->modifier[0]);
14221 return -EINVAL;
14222 }
14223 case DRM_FORMAT_MOD_NONE:
14224 case I915_FORMAT_MOD_X_TILED:
14225 break;
14226 default:
14227 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14228 mode_cmd->modifier[0]);
14229 return -EINVAL;
14230 }
14231
14232 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14233 mode_cmd->pixel_format);
14234 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14235 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14236 mode_cmd->pitches[0], stride_alignment);
14237 return -EINVAL;
14238 }
14239
14240 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14241 mode_cmd->pixel_format);
14242 if (mode_cmd->pitches[0] > pitch_limit) {
14243 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14244 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14245 "tiled" : "linear",
14246 mode_cmd->pitches[0], pitch_limit);
14247 return -EINVAL;
14248 }
14249
14250 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14251 mode_cmd->pitches[0] != obj->stride) {
14252 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14253 mode_cmd->pitches[0], obj->stride);
14254 return -EINVAL;
14255 }
14256
14257 /* Reject formats not supported by any plane early. */
14258 switch (mode_cmd->pixel_format) {
14259 case DRM_FORMAT_C8:
14260 case DRM_FORMAT_RGB565:
14261 case DRM_FORMAT_XRGB8888:
14262 case DRM_FORMAT_ARGB8888:
14263 break;
14264 case DRM_FORMAT_XRGB1555:
14265 if (INTEL_INFO(dev)->gen > 3) {
14266 DRM_DEBUG("unsupported pixel format: %s\n",
14267 drm_get_format_name(mode_cmd->pixel_format));
14268 return -EINVAL;
14269 }
14270 break;
14271 case DRM_FORMAT_ABGR8888:
14272 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14273 DRM_DEBUG("unsupported pixel format: %s\n",
14274 drm_get_format_name(mode_cmd->pixel_format));
14275 return -EINVAL;
14276 }
14277 break;
14278 case DRM_FORMAT_XBGR8888:
14279 case DRM_FORMAT_XRGB2101010:
14280 case DRM_FORMAT_XBGR2101010:
14281 if (INTEL_INFO(dev)->gen < 4) {
14282 DRM_DEBUG("unsupported pixel format: %s\n",
14283 drm_get_format_name(mode_cmd->pixel_format));
14284 return -EINVAL;
14285 }
14286 break;
14287 case DRM_FORMAT_ABGR2101010:
14288 if (!IS_VALLEYVIEW(dev)) {
14289 DRM_DEBUG("unsupported pixel format: %s\n",
14290 drm_get_format_name(mode_cmd->pixel_format));
14291 return -EINVAL;
14292 }
14293 break;
14294 case DRM_FORMAT_YUYV:
14295 case DRM_FORMAT_UYVY:
14296 case DRM_FORMAT_YVYU:
14297 case DRM_FORMAT_VYUY:
14298 if (INTEL_INFO(dev)->gen < 5) {
14299 DRM_DEBUG("unsupported pixel format: %s\n",
14300 drm_get_format_name(mode_cmd->pixel_format));
14301 return -EINVAL;
14302 }
14303 break;
14304 default:
14305 DRM_DEBUG("unsupported pixel format: %s\n",
14306 drm_get_format_name(mode_cmd->pixel_format));
14307 return -EINVAL;
14308 }
14309
14310 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14311 if (mode_cmd->offsets[0] != 0)
14312 return -EINVAL;
14313
14314 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14315 mode_cmd->pixel_format,
14316 mode_cmd->modifier[0]);
14317 /* FIXME drm helper for size checks (especially planar formats)? */
14318 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14319 return -EINVAL;
14320
14321 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14322 intel_fb->obj = obj;
14323 intel_fb->obj->framebuffer_references++;
14324
14325 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14326 if (ret) {
14327 DRM_ERROR("framebuffer init failed %d\n", ret);
14328 return ret;
14329 }
14330
14331 return 0;
14332 }
14333
14334 static struct drm_framebuffer *
14335 intel_user_framebuffer_create(struct drm_device *dev,
14336 struct drm_file *filp,
14337 struct drm_mode_fb_cmd2 *mode_cmd)
14338 {
14339 struct drm_i915_gem_object *obj;
14340
14341 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14342 mode_cmd->handles[0]));
14343 if (&obj->base == NULL)
14344 return ERR_PTR(-ENOENT);
14345
14346 return intel_framebuffer_create(dev, mode_cmd, obj);
14347 }
14348
14349 #ifndef CONFIG_DRM_FBDEV_EMULATION
14350 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14351 {
14352 }
14353 #endif
14354
14355 static const struct drm_mode_config_funcs intel_mode_funcs = {
14356 .fb_create = intel_user_framebuffer_create,
14357 .output_poll_changed = intel_fbdev_output_poll_changed,
14358 .atomic_check = intel_atomic_check,
14359 .atomic_commit = intel_atomic_commit,
14360 .atomic_state_alloc = intel_atomic_state_alloc,
14361 .atomic_state_clear = intel_atomic_state_clear,
14362 };
14363
14364 /* Set up chip specific display functions */
14365 static void intel_init_display(struct drm_device *dev)
14366 {
14367 struct drm_i915_private *dev_priv = dev->dev_private;
14368
14369 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14370 dev_priv->display.find_dpll = g4x_find_best_dpll;
14371 else if (IS_CHERRYVIEW(dev))
14372 dev_priv->display.find_dpll = chv_find_best_dpll;
14373 else if (IS_VALLEYVIEW(dev))
14374 dev_priv->display.find_dpll = vlv_find_best_dpll;
14375 else if (IS_PINEVIEW(dev))
14376 dev_priv->display.find_dpll = pnv_find_best_dpll;
14377 else
14378 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14379
14380 if (INTEL_INFO(dev)->gen >= 9) {
14381 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14382 dev_priv->display.get_initial_plane_config =
14383 skylake_get_initial_plane_config;
14384 dev_priv->display.crtc_compute_clock =
14385 haswell_crtc_compute_clock;
14386 dev_priv->display.crtc_enable = haswell_crtc_enable;
14387 dev_priv->display.crtc_disable = haswell_crtc_disable;
14388 dev_priv->display.update_primary_plane =
14389 skylake_update_primary_plane;
14390 } else if (HAS_DDI(dev)) {
14391 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14392 dev_priv->display.get_initial_plane_config =
14393 ironlake_get_initial_plane_config;
14394 dev_priv->display.crtc_compute_clock =
14395 haswell_crtc_compute_clock;
14396 dev_priv->display.crtc_enable = haswell_crtc_enable;
14397 dev_priv->display.crtc_disable = haswell_crtc_disable;
14398 dev_priv->display.update_primary_plane =
14399 ironlake_update_primary_plane;
14400 } else if (HAS_PCH_SPLIT(dev)) {
14401 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14402 dev_priv->display.get_initial_plane_config =
14403 ironlake_get_initial_plane_config;
14404 dev_priv->display.crtc_compute_clock =
14405 ironlake_crtc_compute_clock;
14406 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14407 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14408 dev_priv->display.update_primary_plane =
14409 ironlake_update_primary_plane;
14410 } else if (IS_VALLEYVIEW(dev)) {
14411 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14412 dev_priv->display.get_initial_plane_config =
14413 i9xx_get_initial_plane_config;
14414 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14415 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14416 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14417 dev_priv->display.update_primary_plane =
14418 i9xx_update_primary_plane;
14419 } else {
14420 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14421 dev_priv->display.get_initial_plane_config =
14422 i9xx_get_initial_plane_config;
14423 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14424 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14425 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14426 dev_priv->display.update_primary_plane =
14427 i9xx_update_primary_plane;
14428 }
14429
14430 /* Returns the core display clock speed */
14431 if (IS_SKYLAKE(dev))
14432 dev_priv->display.get_display_clock_speed =
14433 skylake_get_display_clock_speed;
14434 else if (IS_BROXTON(dev))
14435 dev_priv->display.get_display_clock_speed =
14436 broxton_get_display_clock_speed;
14437 else if (IS_BROADWELL(dev))
14438 dev_priv->display.get_display_clock_speed =
14439 broadwell_get_display_clock_speed;
14440 else if (IS_HASWELL(dev))
14441 dev_priv->display.get_display_clock_speed =
14442 haswell_get_display_clock_speed;
14443 else if (IS_VALLEYVIEW(dev))
14444 dev_priv->display.get_display_clock_speed =
14445 valleyview_get_display_clock_speed;
14446 else if (IS_GEN5(dev))
14447 dev_priv->display.get_display_clock_speed =
14448 ilk_get_display_clock_speed;
14449 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14450 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14451 dev_priv->display.get_display_clock_speed =
14452 i945_get_display_clock_speed;
14453 else if (IS_GM45(dev))
14454 dev_priv->display.get_display_clock_speed =
14455 gm45_get_display_clock_speed;
14456 else if (IS_CRESTLINE(dev))
14457 dev_priv->display.get_display_clock_speed =
14458 i965gm_get_display_clock_speed;
14459 else if (IS_PINEVIEW(dev))
14460 dev_priv->display.get_display_clock_speed =
14461 pnv_get_display_clock_speed;
14462 else if (IS_G33(dev) || IS_G4X(dev))
14463 dev_priv->display.get_display_clock_speed =
14464 g33_get_display_clock_speed;
14465 else if (IS_I915G(dev))
14466 dev_priv->display.get_display_clock_speed =
14467 i915_get_display_clock_speed;
14468 else if (IS_I945GM(dev) || IS_845G(dev))
14469 dev_priv->display.get_display_clock_speed =
14470 i9xx_misc_get_display_clock_speed;
14471 else if (IS_PINEVIEW(dev))
14472 dev_priv->display.get_display_clock_speed =
14473 pnv_get_display_clock_speed;
14474 else if (IS_I915GM(dev))
14475 dev_priv->display.get_display_clock_speed =
14476 i915gm_get_display_clock_speed;
14477 else if (IS_I865G(dev))
14478 dev_priv->display.get_display_clock_speed =
14479 i865_get_display_clock_speed;
14480 else if (IS_I85X(dev))
14481 dev_priv->display.get_display_clock_speed =
14482 i85x_get_display_clock_speed;
14483 else { /* 830 */
14484 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14485 dev_priv->display.get_display_clock_speed =
14486 i830_get_display_clock_speed;
14487 }
14488
14489 if (IS_GEN5(dev)) {
14490 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14491 } else if (IS_GEN6(dev)) {
14492 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14493 } else if (IS_IVYBRIDGE(dev)) {
14494 /* FIXME: detect B0+ stepping and use auto training */
14495 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14496 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14497 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14498 if (IS_BROADWELL(dev)) {
14499 dev_priv->display.modeset_commit_cdclk =
14500 broadwell_modeset_commit_cdclk;
14501 dev_priv->display.modeset_calc_cdclk =
14502 broadwell_modeset_calc_cdclk;
14503 }
14504 } else if (IS_VALLEYVIEW(dev)) {
14505 dev_priv->display.modeset_commit_cdclk =
14506 valleyview_modeset_commit_cdclk;
14507 dev_priv->display.modeset_calc_cdclk =
14508 valleyview_modeset_calc_cdclk;
14509 } else if (IS_BROXTON(dev)) {
14510 dev_priv->display.modeset_commit_cdclk =
14511 broxton_modeset_commit_cdclk;
14512 dev_priv->display.modeset_calc_cdclk =
14513 broxton_modeset_calc_cdclk;
14514 }
14515
14516 switch (INTEL_INFO(dev)->gen) {
14517 case 2:
14518 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14519 break;
14520
14521 case 3:
14522 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14523 break;
14524
14525 case 4:
14526 case 5:
14527 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14528 break;
14529
14530 case 6:
14531 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14532 break;
14533 case 7:
14534 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14535 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14536 break;
14537 case 9:
14538 /* Drop through - unsupported since execlist only. */
14539 default:
14540 /* Default just returns -ENODEV to indicate unsupported */
14541 dev_priv->display.queue_flip = intel_default_queue_flip;
14542 }
14543
14544 mutex_init(&dev_priv->pps_mutex);
14545 }
14546
14547 /*
14548 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14549 * resume, or other times. This quirk makes sure that's the case for
14550 * affected systems.
14551 */
14552 static void quirk_pipea_force(struct drm_device *dev)
14553 {
14554 struct drm_i915_private *dev_priv = dev->dev_private;
14555
14556 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14557 DRM_INFO("applying pipe a force quirk\n");
14558 }
14559
14560 static void quirk_pipeb_force(struct drm_device *dev)
14561 {
14562 struct drm_i915_private *dev_priv = dev->dev_private;
14563
14564 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14565 DRM_INFO("applying pipe b force quirk\n");
14566 }
14567
14568 /*
14569 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14570 */
14571 static void quirk_ssc_force_disable(struct drm_device *dev)
14572 {
14573 struct drm_i915_private *dev_priv = dev->dev_private;
14574 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14575 DRM_INFO("applying lvds SSC disable quirk\n");
14576 }
14577
14578 /*
14579 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14580 * brightness value
14581 */
14582 static void quirk_invert_brightness(struct drm_device *dev)
14583 {
14584 struct drm_i915_private *dev_priv = dev->dev_private;
14585 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14586 DRM_INFO("applying inverted panel brightness quirk\n");
14587 }
14588
14589 /* Some VBT's incorrectly indicate no backlight is present */
14590 static void quirk_backlight_present(struct drm_device *dev)
14591 {
14592 struct drm_i915_private *dev_priv = dev->dev_private;
14593 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14594 DRM_INFO("applying backlight present quirk\n");
14595 }
14596
14597 struct intel_quirk {
14598 int device;
14599 int subsystem_vendor;
14600 int subsystem_device;
14601 void (*hook)(struct drm_device *dev);
14602 };
14603
14604 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14605 struct intel_dmi_quirk {
14606 void (*hook)(struct drm_device *dev);
14607 const struct dmi_system_id (*dmi_id_list)[];
14608 };
14609
14610 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14611 {
14612 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14613 return 1;
14614 }
14615
14616 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14617 {
14618 .dmi_id_list = &(const struct dmi_system_id[]) {
14619 {
14620 .callback = intel_dmi_reverse_brightness,
14621 .ident = "NCR Corporation",
14622 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14623 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14624 },
14625 },
14626 { } /* terminating entry */
14627 },
14628 .hook = quirk_invert_brightness,
14629 },
14630 };
14631
14632 static struct intel_quirk intel_quirks[] = {
14633 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14634 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14635
14636 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14637 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14638
14639 /* 830 needs to leave pipe A & dpll A up */
14640 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14641
14642 /* 830 needs to leave pipe B & dpll B up */
14643 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14644
14645 /* Lenovo U160 cannot use SSC on LVDS */
14646 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14647
14648 /* Sony Vaio Y cannot use SSC on LVDS */
14649 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14650
14651 /* Acer Aspire 5734Z must invert backlight brightness */
14652 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14653
14654 /* Acer/eMachines G725 */
14655 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14656
14657 /* Acer/eMachines e725 */
14658 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14659
14660 /* Acer/Packard Bell NCL20 */
14661 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14662
14663 /* Acer Aspire 4736Z */
14664 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14665
14666 /* Acer Aspire 5336 */
14667 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14668
14669 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14670 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14671
14672 /* Acer C720 Chromebook (Core i3 4005U) */
14673 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14674
14675 /* Apple Macbook 2,1 (Core 2 T7400) */
14676 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14677
14678 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14679 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14680
14681 /* HP Chromebook 14 (Celeron 2955U) */
14682 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14683
14684 /* Dell Chromebook 11 */
14685 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14686 };
14687
14688 static void intel_init_quirks(struct drm_device *dev)
14689 {
14690 struct pci_dev *d = dev->pdev;
14691 int i;
14692
14693 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14694 struct intel_quirk *q = &intel_quirks[i];
14695
14696 if (d->device == q->device &&
14697 (d->subsystem_vendor == q->subsystem_vendor ||
14698 q->subsystem_vendor == PCI_ANY_ID) &&
14699 (d->subsystem_device == q->subsystem_device ||
14700 q->subsystem_device == PCI_ANY_ID))
14701 q->hook(dev);
14702 }
14703 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14704 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14705 intel_dmi_quirks[i].hook(dev);
14706 }
14707 }
14708
14709 /* Disable the VGA plane that we never use */
14710 static void i915_disable_vga(struct drm_device *dev)
14711 {
14712 struct drm_i915_private *dev_priv = dev->dev_private;
14713 u8 sr1;
14714 u32 vga_reg = i915_vgacntrl_reg(dev);
14715
14716 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14717 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14718 outb(SR01, VGA_SR_INDEX);
14719 sr1 = inb(VGA_SR_DATA);
14720 outb(sr1 | 1<<5, VGA_SR_DATA);
14721 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14722 udelay(300);
14723
14724 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14725 POSTING_READ(vga_reg);
14726 }
14727
14728 void intel_modeset_init_hw(struct drm_device *dev)
14729 {
14730 intel_update_cdclk(dev);
14731 intel_prepare_ddi(dev);
14732 intel_init_clock_gating(dev);
14733 intel_enable_gt_powersave(dev);
14734 }
14735
14736 void intel_modeset_init(struct drm_device *dev)
14737 {
14738 struct drm_i915_private *dev_priv = dev->dev_private;
14739 int sprite, ret;
14740 enum pipe pipe;
14741 struct intel_crtc *crtc;
14742
14743 drm_mode_config_init(dev);
14744
14745 dev->mode_config.min_width = 0;
14746 dev->mode_config.min_height = 0;
14747
14748 dev->mode_config.preferred_depth = 24;
14749 dev->mode_config.prefer_shadow = 1;
14750
14751 dev->mode_config.allow_fb_modifiers = true;
14752
14753 dev->mode_config.funcs = &intel_mode_funcs;
14754
14755 intel_init_quirks(dev);
14756
14757 intel_init_pm(dev);
14758
14759 if (INTEL_INFO(dev)->num_pipes == 0)
14760 return;
14761
14762 /*
14763 * There may be no VBT; and if the BIOS enabled SSC we can
14764 * just keep using it to avoid unnecessary flicker. Whereas if the
14765 * BIOS isn't using it, don't assume it will work even if the VBT
14766 * indicates as much.
14767 */
14768 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14769 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14770 DREF_SSC1_ENABLE);
14771
14772 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14773 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14774 bios_lvds_use_ssc ? "en" : "dis",
14775 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14776 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14777 }
14778 }
14779
14780 intel_init_display(dev);
14781 intel_init_audio(dev);
14782
14783 if (IS_GEN2(dev)) {
14784 dev->mode_config.max_width = 2048;
14785 dev->mode_config.max_height = 2048;
14786 } else if (IS_GEN3(dev)) {
14787 dev->mode_config.max_width = 4096;
14788 dev->mode_config.max_height = 4096;
14789 } else {
14790 dev->mode_config.max_width = 8192;
14791 dev->mode_config.max_height = 8192;
14792 }
14793
14794 if (IS_845G(dev) || IS_I865G(dev)) {
14795 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14796 dev->mode_config.cursor_height = 1023;
14797 } else if (IS_GEN2(dev)) {
14798 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14799 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14800 } else {
14801 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14802 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14803 }
14804
14805 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14806
14807 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14808 INTEL_INFO(dev)->num_pipes,
14809 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14810
14811 for_each_pipe(dev_priv, pipe) {
14812 intel_crtc_init(dev, pipe);
14813 for_each_sprite(dev_priv, pipe, sprite) {
14814 ret = intel_plane_init(dev, pipe, sprite);
14815 if (ret)
14816 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14817 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14818 }
14819 }
14820
14821 intel_update_czclk(dev_priv);
14822 intel_update_cdclk(dev);
14823
14824 intel_shared_dpll_init(dev);
14825
14826 /* Just disable it once at startup */
14827 i915_disable_vga(dev);
14828 intel_setup_outputs(dev);
14829
14830 /* Just in case the BIOS is doing something questionable. */
14831 intel_fbc_disable(dev_priv);
14832
14833 drm_modeset_lock_all(dev);
14834 intel_modeset_setup_hw_state(dev);
14835 drm_modeset_unlock_all(dev);
14836
14837 for_each_intel_crtc(dev, crtc) {
14838 struct intel_initial_plane_config plane_config = {};
14839
14840 if (!crtc->active)
14841 continue;
14842
14843 /*
14844 * Note that reserving the BIOS fb up front prevents us
14845 * from stuffing other stolen allocations like the ring
14846 * on top. This prevents some ugliness at boot time, and
14847 * can even allow for smooth boot transitions if the BIOS
14848 * fb is large enough for the active pipe configuration.
14849 */
14850 dev_priv->display.get_initial_plane_config(crtc,
14851 &plane_config);
14852
14853 /*
14854 * If the fb is shared between multiple heads, we'll
14855 * just get the first one.
14856 */
14857 intel_find_initial_plane_obj(crtc, &plane_config);
14858 }
14859 }
14860
14861 static void intel_enable_pipe_a(struct drm_device *dev)
14862 {
14863 struct intel_connector *connector;
14864 struct drm_connector *crt = NULL;
14865 struct intel_load_detect_pipe load_detect_temp;
14866 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14867
14868 /* We can't just switch on the pipe A, we need to set things up with a
14869 * proper mode and output configuration. As a gross hack, enable pipe A
14870 * by enabling the load detect pipe once. */
14871 for_each_intel_connector(dev, connector) {
14872 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14873 crt = &connector->base;
14874 break;
14875 }
14876 }
14877
14878 if (!crt)
14879 return;
14880
14881 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14882 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14883 }
14884
14885 static bool
14886 intel_check_plane_mapping(struct intel_crtc *crtc)
14887 {
14888 struct drm_device *dev = crtc->base.dev;
14889 struct drm_i915_private *dev_priv = dev->dev_private;
14890 u32 val;
14891
14892 if (INTEL_INFO(dev)->num_pipes == 1)
14893 return true;
14894
14895 val = I915_READ(DSPCNTR(!crtc->plane));
14896
14897 if ((val & DISPLAY_PLANE_ENABLE) &&
14898 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14899 return false;
14900
14901 return true;
14902 }
14903
14904 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14905 {
14906 struct drm_device *dev = crtc->base.dev;
14907 struct intel_encoder *encoder;
14908
14909 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14910 return true;
14911
14912 return false;
14913 }
14914
14915 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14916 {
14917 struct drm_device *dev = crtc->base.dev;
14918 struct drm_i915_private *dev_priv = dev->dev_private;
14919 u32 reg;
14920
14921 /* Clear any frame start delays used for debugging left by the BIOS */
14922 reg = PIPECONF(crtc->config->cpu_transcoder);
14923 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14924
14925 /* restore vblank interrupts to correct state */
14926 drm_crtc_vblank_reset(&crtc->base);
14927 if (crtc->active) {
14928 struct intel_plane *plane;
14929
14930 drm_crtc_vblank_on(&crtc->base);
14931
14932 /* Disable everything but the primary plane */
14933 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14934 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14935 continue;
14936
14937 plane->disable_plane(&plane->base, &crtc->base);
14938 }
14939 }
14940
14941 /* We need to sanitize the plane -> pipe mapping first because this will
14942 * disable the crtc (and hence change the state) if it is wrong. Note
14943 * that gen4+ has a fixed plane -> pipe mapping. */
14944 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14945 bool plane;
14946
14947 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14948 crtc->base.base.id);
14949
14950 /* Pipe has the wrong plane attached and the plane is active.
14951 * Temporarily change the plane mapping and disable everything
14952 * ... */
14953 plane = crtc->plane;
14954 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14955 crtc->plane = !plane;
14956 intel_crtc_disable_noatomic(&crtc->base);
14957 crtc->plane = plane;
14958 }
14959
14960 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14961 crtc->pipe == PIPE_A && !crtc->active) {
14962 /* BIOS forgot to enable pipe A, this mostly happens after
14963 * resume. Force-enable the pipe to fix this, the update_dpms
14964 * call below we restore the pipe to the right state, but leave
14965 * the required bits on. */
14966 intel_enable_pipe_a(dev);
14967 }
14968
14969 /* Adjust the state of the output pipe according to whether we
14970 * have active connectors/encoders. */
14971 if (!intel_crtc_has_encoders(crtc))
14972 intel_crtc_disable_noatomic(&crtc->base);
14973
14974 if (crtc->active != crtc->base.state->active) {
14975 struct intel_encoder *encoder;
14976
14977 /* This can happen either due to bugs in the get_hw_state
14978 * functions or because of calls to intel_crtc_disable_noatomic,
14979 * or because the pipe is force-enabled due to the
14980 * pipe A quirk. */
14981 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14982 crtc->base.base.id,
14983 crtc->base.state->enable ? "enabled" : "disabled",
14984 crtc->active ? "enabled" : "disabled");
14985
14986 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
14987 crtc->base.state->active = crtc->active;
14988 crtc->base.enabled = crtc->active;
14989
14990 /* Because we only establish the connector -> encoder ->
14991 * crtc links if something is active, this means the
14992 * crtc is now deactivated. Break the links. connector
14993 * -> encoder links are only establish when things are
14994 * actually up, hence no need to break them. */
14995 WARN_ON(crtc->active);
14996
14997 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14998 encoder->base.crtc = NULL;
14999 }
15000
15001 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15002 /*
15003 * We start out with underrun reporting disabled to avoid races.
15004 * For correct bookkeeping mark this on active crtcs.
15005 *
15006 * Also on gmch platforms we dont have any hardware bits to
15007 * disable the underrun reporting. Which means we need to start
15008 * out with underrun reporting disabled also on inactive pipes,
15009 * since otherwise we'll complain about the garbage we read when
15010 * e.g. coming up after runtime pm.
15011 *
15012 * No protection against concurrent access is required - at
15013 * worst a fifo underrun happens which also sets this to false.
15014 */
15015 crtc->cpu_fifo_underrun_disabled = true;
15016 crtc->pch_fifo_underrun_disabled = true;
15017 }
15018 }
15019
15020 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15021 {
15022 struct intel_connector *connector;
15023 struct drm_device *dev = encoder->base.dev;
15024 bool active = false;
15025
15026 /* We need to check both for a crtc link (meaning that the
15027 * encoder is active and trying to read from a pipe) and the
15028 * pipe itself being active. */
15029 bool has_active_crtc = encoder->base.crtc &&
15030 to_intel_crtc(encoder->base.crtc)->active;
15031
15032 for_each_intel_connector(dev, connector) {
15033 if (connector->base.encoder != &encoder->base)
15034 continue;
15035
15036 active = true;
15037 break;
15038 }
15039
15040 if (active && !has_active_crtc) {
15041 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15042 encoder->base.base.id,
15043 encoder->base.name);
15044
15045 /* Connector is active, but has no active pipe. This is
15046 * fallout from our resume register restoring. Disable
15047 * the encoder manually again. */
15048 if (encoder->base.crtc) {
15049 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15050 encoder->base.base.id,
15051 encoder->base.name);
15052 encoder->disable(encoder);
15053 if (encoder->post_disable)
15054 encoder->post_disable(encoder);
15055 }
15056 encoder->base.crtc = NULL;
15057
15058 /* Inconsistent output/port/pipe state happens presumably due to
15059 * a bug in one of the get_hw_state functions. Or someplace else
15060 * in our code, like the register restore mess on resume. Clamp
15061 * things to off as a safer default. */
15062 for_each_intel_connector(dev, connector) {
15063 if (connector->encoder != encoder)
15064 continue;
15065 connector->base.dpms = DRM_MODE_DPMS_OFF;
15066 connector->base.encoder = NULL;
15067 }
15068 }
15069 /* Enabled encoders without active connectors will be fixed in
15070 * the crtc fixup. */
15071 }
15072
15073 void i915_redisable_vga_power_on(struct drm_device *dev)
15074 {
15075 struct drm_i915_private *dev_priv = dev->dev_private;
15076 u32 vga_reg = i915_vgacntrl_reg(dev);
15077
15078 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15079 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15080 i915_disable_vga(dev);
15081 }
15082 }
15083
15084 void i915_redisable_vga(struct drm_device *dev)
15085 {
15086 struct drm_i915_private *dev_priv = dev->dev_private;
15087
15088 /* This function can be called both from intel_modeset_setup_hw_state or
15089 * at a very early point in our resume sequence, where the power well
15090 * structures are not yet restored. Since this function is at a very
15091 * paranoid "someone might have enabled VGA while we were not looking"
15092 * level, just check if the power well is enabled instead of trying to
15093 * follow the "don't touch the power well if we don't need it" policy
15094 * the rest of the driver uses. */
15095 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15096 return;
15097
15098 i915_redisable_vga_power_on(dev);
15099 }
15100
15101 static bool primary_get_hw_state(struct intel_plane *plane)
15102 {
15103 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15104
15105 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15106 }
15107
15108 /* FIXME read out full plane state for all planes */
15109 static void readout_plane_state(struct intel_crtc *crtc)
15110 {
15111 struct drm_plane *primary = crtc->base.primary;
15112 struct intel_plane_state *plane_state =
15113 to_intel_plane_state(primary->state);
15114
15115 plane_state->visible =
15116 primary_get_hw_state(to_intel_plane(primary));
15117
15118 if (plane_state->visible)
15119 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15120 }
15121
15122 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15123 {
15124 struct drm_i915_private *dev_priv = dev->dev_private;
15125 enum pipe pipe;
15126 struct intel_crtc *crtc;
15127 struct intel_encoder *encoder;
15128 struct intel_connector *connector;
15129 int i;
15130
15131 for_each_intel_crtc(dev, crtc) {
15132 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15133 memset(crtc->config, 0, sizeof(*crtc->config));
15134 crtc->config->base.crtc = &crtc->base;
15135
15136 crtc->active = dev_priv->display.get_pipe_config(crtc,
15137 crtc->config);
15138
15139 crtc->base.state->active = crtc->active;
15140 crtc->base.enabled = crtc->active;
15141
15142 readout_plane_state(crtc);
15143
15144 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15145 crtc->base.base.id,
15146 crtc->active ? "enabled" : "disabled");
15147 }
15148
15149 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15150 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15151
15152 pll->on = pll->get_hw_state(dev_priv, pll,
15153 &pll->config.hw_state);
15154 pll->active = 0;
15155 pll->config.crtc_mask = 0;
15156 for_each_intel_crtc(dev, crtc) {
15157 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15158 pll->active++;
15159 pll->config.crtc_mask |= 1 << crtc->pipe;
15160 }
15161 }
15162
15163 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15164 pll->name, pll->config.crtc_mask, pll->on);
15165
15166 if (pll->config.crtc_mask)
15167 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15168 }
15169
15170 for_each_intel_encoder(dev, encoder) {
15171 pipe = 0;
15172
15173 if (encoder->get_hw_state(encoder, &pipe)) {
15174 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15175 encoder->base.crtc = &crtc->base;
15176 encoder->get_config(encoder, crtc->config);
15177 } else {
15178 encoder->base.crtc = NULL;
15179 }
15180
15181 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15182 encoder->base.base.id,
15183 encoder->base.name,
15184 encoder->base.crtc ? "enabled" : "disabled",
15185 pipe_name(pipe));
15186 }
15187
15188 for_each_intel_connector(dev, connector) {
15189 if (connector->get_hw_state(connector)) {
15190 connector->base.dpms = DRM_MODE_DPMS_ON;
15191 connector->base.encoder = &connector->encoder->base;
15192 } else {
15193 connector->base.dpms = DRM_MODE_DPMS_OFF;
15194 connector->base.encoder = NULL;
15195 }
15196 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15197 connector->base.base.id,
15198 connector->base.name,
15199 connector->base.encoder ? "enabled" : "disabled");
15200 }
15201
15202 for_each_intel_crtc(dev, crtc) {
15203 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15204
15205 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15206 if (crtc->base.state->active) {
15207 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15208 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15209 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15210
15211 /*
15212 * The initial mode needs to be set in order to keep
15213 * the atomic core happy. It wants a valid mode if the
15214 * crtc's enabled, so we do the above call.
15215 *
15216 * At this point some state updated by the connectors
15217 * in their ->detect() callback has not run yet, so
15218 * no recalculation can be done yet.
15219 *
15220 * Even if we could do a recalculation and modeset
15221 * right now it would cause a double modeset if
15222 * fbdev or userspace chooses a different initial mode.
15223 *
15224 * If that happens, someone indicated they wanted a
15225 * mode change, which means it's safe to do a full
15226 * recalculation.
15227 */
15228 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15229
15230 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15231 update_scanline_offset(crtc);
15232 }
15233 }
15234 }
15235
15236 /* Scan out the current hw modeset state,
15237 * and sanitizes it to the current state
15238 */
15239 static void
15240 intel_modeset_setup_hw_state(struct drm_device *dev)
15241 {
15242 struct drm_i915_private *dev_priv = dev->dev_private;
15243 enum pipe pipe;
15244 struct intel_crtc *crtc;
15245 struct intel_encoder *encoder;
15246 int i;
15247
15248 intel_modeset_readout_hw_state(dev);
15249
15250 /* HW state is read out, now we need to sanitize this mess. */
15251 for_each_intel_encoder(dev, encoder) {
15252 intel_sanitize_encoder(encoder);
15253 }
15254
15255 for_each_pipe(dev_priv, pipe) {
15256 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15257 intel_sanitize_crtc(crtc);
15258 intel_dump_pipe_config(crtc, crtc->config,
15259 "[setup_hw_state]");
15260 }
15261
15262 intel_modeset_update_connector_atomic_state(dev);
15263
15264 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15265 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15266
15267 if (!pll->on || pll->active)
15268 continue;
15269
15270 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15271
15272 pll->disable(dev_priv, pll);
15273 pll->on = false;
15274 }
15275
15276 if (IS_VALLEYVIEW(dev))
15277 vlv_wm_get_hw_state(dev);
15278 else if (IS_GEN9(dev))
15279 skl_wm_get_hw_state(dev);
15280 else if (HAS_PCH_SPLIT(dev))
15281 ilk_wm_get_hw_state(dev);
15282
15283 for_each_intel_crtc(dev, crtc) {
15284 unsigned long put_domains;
15285
15286 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15287 if (WARN_ON(put_domains))
15288 modeset_put_power_domains(dev_priv, put_domains);
15289 }
15290 intel_display_set_init_power(dev_priv, false);
15291 }
15292
15293 void intel_display_resume(struct drm_device *dev)
15294 {
15295 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15296 struct intel_connector *conn;
15297 struct intel_plane *plane;
15298 struct drm_crtc *crtc;
15299 int ret;
15300
15301 if (!state)
15302 return;
15303
15304 state->acquire_ctx = dev->mode_config.acquire_ctx;
15305
15306 /* preserve complete old state, including dpll */
15307 intel_atomic_get_shared_dpll_state(state);
15308
15309 for_each_crtc(dev, crtc) {
15310 struct drm_crtc_state *crtc_state =
15311 drm_atomic_get_crtc_state(state, crtc);
15312
15313 ret = PTR_ERR_OR_ZERO(crtc_state);
15314 if (ret)
15315 goto err;
15316
15317 /* force a restore */
15318 crtc_state->mode_changed = true;
15319 }
15320
15321 for_each_intel_plane(dev, plane) {
15322 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15323 if (ret)
15324 goto err;
15325 }
15326
15327 for_each_intel_connector(dev, conn) {
15328 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15329 if (ret)
15330 goto err;
15331 }
15332
15333 intel_modeset_setup_hw_state(dev);
15334
15335 i915_redisable_vga(dev);
15336 ret = drm_atomic_commit(state);
15337 if (!ret)
15338 return;
15339
15340 err:
15341 DRM_ERROR("Restoring old state failed with %i\n", ret);
15342 drm_atomic_state_free(state);
15343 }
15344
15345 void intel_modeset_gem_init(struct drm_device *dev)
15346 {
15347 struct drm_crtc *c;
15348 struct drm_i915_gem_object *obj;
15349 int ret;
15350
15351 mutex_lock(&dev->struct_mutex);
15352 intel_init_gt_powersave(dev);
15353 mutex_unlock(&dev->struct_mutex);
15354
15355 intel_modeset_init_hw(dev);
15356
15357 intel_setup_overlay(dev);
15358
15359 /*
15360 * Make sure any fbs we allocated at startup are properly
15361 * pinned & fenced. When we do the allocation it's too early
15362 * for this.
15363 */
15364 for_each_crtc(dev, c) {
15365 obj = intel_fb_obj(c->primary->fb);
15366 if (obj == NULL)
15367 continue;
15368
15369 mutex_lock(&dev->struct_mutex);
15370 ret = intel_pin_and_fence_fb_obj(c->primary,
15371 c->primary->fb,
15372 c->primary->state,
15373 NULL, NULL);
15374 mutex_unlock(&dev->struct_mutex);
15375 if (ret) {
15376 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15377 to_intel_crtc(c)->pipe);
15378 drm_framebuffer_unreference(c->primary->fb);
15379 c->primary->fb = NULL;
15380 c->primary->crtc = c->primary->state->crtc = NULL;
15381 update_state_fb(c->primary);
15382 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15383 }
15384 }
15385
15386 intel_backlight_register(dev);
15387 }
15388
15389 void intel_connector_unregister(struct intel_connector *intel_connector)
15390 {
15391 struct drm_connector *connector = &intel_connector->base;
15392
15393 intel_panel_destroy_backlight(connector);
15394 drm_connector_unregister(connector);
15395 }
15396
15397 void intel_modeset_cleanup(struct drm_device *dev)
15398 {
15399 struct drm_i915_private *dev_priv = dev->dev_private;
15400 struct drm_connector *connector;
15401
15402 intel_disable_gt_powersave(dev);
15403
15404 intel_backlight_unregister(dev);
15405
15406 /*
15407 * Interrupts and polling as the first thing to avoid creating havoc.
15408 * Too much stuff here (turning of connectors, ...) would
15409 * experience fancy races otherwise.
15410 */
15411 intel_irq_uninstall(dev_priv);
15412
15413 /*
15414 * Due to the hpd irq storm handling the hotplug work can re-arm the
15415 * poll handlers. Hence disable polling after hpd handling is shut down.
15416 */
15417 drm_kms_helper_poll_fini(dev);
15418
15419 intel_unregister_dsm_handler();
15420
15421 intel_fbc_disable(dev_priv);
15422
15423 /* flush any delayed tasks or pending work */
15424 flush_scheduled_work();
15425
15426 /* destroy the backlight and sysfs files before encoders/connectors */
15427 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15428 struct intel_connector *intel_connector;
15429
15430 intel_connector = to_intel_connector(connector);
15431 intel_connector->unregister(intel_connector);
15432 }
15433
15434 drm_mode_config_cleanup(dev);
15435
15436 intel_cleanup_overlay(dev);
15437
15438 mutex_lock(&dev->struct_mutex);
15439 intel_cleanup_gt_powersave(dev);
15440 mutex_unlock(&dev->struct_mutex);
15441 }
15442
15443 /*
15444 * Return which encoder is currently attached for connector.
15445 */
15446 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15447 {
15448 return &intel_attached_encoder(connector)->base;
15449 }
15450
15451 void intel_connector_attach_encoder(struct intel_connector *connector,
15452 struct intel_encoder *encoder)
15453 {
15454 connector->encoder = encoder;
15455 drm_mode_connector_attach_encoder(&connector->base,
15456 &encoder->base);
15457 }
15458
15459 /*
15460 * set vga decode state - true == enable VGA decode
15461 */
15462 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15463 {
15464 struct drm_i915_private *dev_priv = dev->dev_private;
15465 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15466 u16 gmch_ctrl;
15467
15468 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15469 DRM_ERROR("failed to read control word\n");
15470 return -EIO;
15471 }
15472
15473 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15474 return 0;
15475
15476 if (state)
15477 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15478 else
15479 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15480
15481 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15482 DRM_ERROR("failed to write control word\n");
15483 return -EIO;
15484 }
15485
15486 return 0;
15487 }
15488
15489 struct intel_display_error_state {
15490
15491 u32 power_well_driver;
15492
15493 int num_transcoders;
15494
15495 struct intel_cursor_error_state {
15496 u32 control;
15497 u32 position;
15498 u32 base;
15499 u32 size;
15500 } cursor[I915_MAX_PIPES];
15501
15502 struct intel_pipe_error_state {
15503 bool power_domain_on;
15504 u32 source;
15505 u32 stat;
15506 } pipe[I915_MAX_PIPES];
15507
15508 struct intel_plane_error_state {
15509 u32 control;
15510 u32 stride;
15511 u32 size;
15512 u32 pos;
15513 u32 addr;
15514 u32 surface;
15515 u32 tile_offset;
15516 } plane[I915_MAX_PIPES];
15517
15518 struct intel_transcoder_error_state {
15519 bool power_domain_on;
15520 enum transcoder cpu_transcoder;
15521
15522 u32 conf;
15523
15524 u32 htotal;
15525 u32 hblank;
15526 u32 hsync;
15527 u32 vtotal;
15528 u32 vblank;
15529 u32 vsync;
15530 } transcoder[4];
15531 };
15532
15533 struct intel_display_error_state *
15534 intel_display_capture_error_state(struct drm_device *dev)
15535 {
15536 struct drm_i915_private *dev_priv = dev->dev_private;
15537 struct intel_display_error_state *error;
15538 int transcoders[] = {
15539 TRANSCODER_A,
15540 TRANSCODER_B,
15541 TRANSCODER_C,
15542 TRANSCODER_EDP,
15543 };
15544 int i;
15545
15546 if (INTEL_INFO(dev)->num_pipes == 0)
15547 return NULL;
15548
15549 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15550 if (error == NULL)
15551 return NULL;
15552
15553 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15554 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15555
15556 for_each_pipe(dev_priv, i) {
15557 error->pipe[i].power_domain_on =
15558 __intel_display_power_is_enabled(dev_priv,
15559 POWER_DOMAIN_PIPE(i));
15560 if (!error->pipe[i].power_domain_on)
15561 continue;
15562
15563 error->cursor[i].control = I915_READ(CURCNTR(i));
15564 error->cursor[i].position = I915_READ(CURPOS(i));
15565 error->cursor[i].base = I915_READ(CURBASE(i));
15566
15567 error->plane[i].control = I915_READ(DSPCNTR(i));
15568 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15569 if (INTEL_INFO(dev)->gen <= 3) {
15570 error->plane[i].size = I915_READ(DSPSIZE(i));
15571 error->plane[i].pos = I915_READ(DSPPOS(i));
15572 }
15573 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15574 error->plane[i].addr = I915_READ(DSPADDR(i));
15575 if (INTEL_INFO(dev)->gen >= 4) {
15576 error->plane[i].surface = I915_READ(DSPSURF(i));
15577 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15578 }
15579
15580 error->pipe[i].source = I915_READ(PIPESRC(i));
15581
15582 if (HAS_GMCH_DISPLAY(dev))
15583 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15584 }
15585
15586 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15587 if (HAS_DDI(dev_priv->dev))
15588 error->num_transcoders++; /* Account for eDP. */
15589
15590 for (i = 0; i < error->num_transcoders; i++) {
15591 enum transcoder cpu_transcoder = transcoders[i];
15592
15593 error->transcoder[i].power_domain_on =
15594 __intel_display_power_is_enabled(dev_priv,
15595 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15596 if (!error->transcoder[i].power_domain_on)
15597 continue;
15598
15599 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15600
15601 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15602 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15603 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15604 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15605 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15606 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15607 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15608 }
15609
15610 return error;
15611 }
15612
15613 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15614
15615 void
15616 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15617 struct drm_device *dev,
15618 struct intel_display_error_state *error)
15619 {
15620 struct drm_i915_private *dev_priv = dev->dev_private;
15621 int i;
15622
15623 if (!error)
15624 return;
15625
15626 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15627 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15628 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15629 error->power_well_driver);
15630 for_each_pipe(dev_priv, i) {
15631 err_printf(m, "Pipe [%d]:\n", i);
15632 err_printf(m, " Power: %s\n",
15633 error->pipe[i].power_domain_on ? "on" : "off");
15634 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15635 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15636
15637 err_printf(m, "Plane [%d]:\n", i);
15638 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15639 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15640 if (INTEL_INFO(dev)->gen <= 3) {
15641 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15642 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15643 }
15644 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15645 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15646 if (INTEL_INFO(dev)->gen >= 4) {
15647 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15648 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15649 }
15650
15651 err_printf(m, "Cursor [%d]:\n", i);
15652 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15653 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15654 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15655 }
15656
15657 for (i = 0; i < error->num_transcoders; i++) {
15658 err_printf(m, "CPU transcoder: %c\n",
15659 transcoder_name(error->transcoder[i].cpu_transcoder));
15660 err_printf(m, " Power: %s\n",
15661 error->transcoder[i].power_domain_on ? "on" : "off");
15662 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15663 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15664 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15665 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15666 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15667 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15668 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15669 }
15670 }
15671
15672 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15673 {
15674 struct intel_crtc *crtc;
15675
15676 for_each_intel_crtc(dev, crtc) {
15677 struct intel_unpin_work *work;
15678
15679 spin_lock_irq(&dev->event_lock);
15680
15681 work = crtc->unpin_work;
15682
15683 if (work && work->event &&
15684 work->event->base.file_priv == file) {
15685 kfree(work->event);
15686 work->event = NULL;
15687 }
15688
15689 spin_unlock_irq(&dev->event_lock);
15690 }
15691 }
Linux kernel - Deliverables
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