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drm/i915: Don't pass plane+plane_state to intel_pin_and_fence_fb_obj()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47 #include <linux/reservation.h>
48 #include <linux/dma-buf.h>
49
50 /* Primary plane formats for gen <= 3 */
51 static const uint32_t i8xx_primary_formats[] = {
52 DRM_FORMAT_C8,
53 DRM_FORMAT_RGB565,
54 DRM_FORMAT_XRGB1555,
55 DRM_FORMAT_XRGB8888,
56 };
57
58 /* Primary plane formats for gen >= 4 */
59 static const uint32_t i965_primary_formats[] = {
60 DRM_FORMAT_C8,
61 DRM_FORMAT_RGB565,
62 DRM_FORMAT_XRGB8888,
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_XRGB2101010,
65 DRM_FORMAT_XBGR2101010,
66 };
67
68 static const uint32_t skl_primary_formats[] = {
69 DRM_FORMAT_C8,
70 DRM_FORMAT_RGB565,
71 DRM_FORMAT_XRGB8888,
72 DRM_FORMAT_XBGR8888,
73 DRM_FORMAT_ARGB8888,
74 DRM_FORMAT_ABGR8888,
75 DRM_FORMAT_XRGB2101010,
76 DRM_FORMAT_XBGR2101010,
77 DRM_FORMAT_YUYV,
78 DRM_FORMAT_YVYU,
79 DRM_FORMAT_UYVY,
80 DRM_FORMAT_VYUY,
81 };
82
83 /* Cursor formats */
84 static const uint32_t intel_cursor_formats[] = {
85 DRM_FORMAT_ARGB8888,
86 };
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary(struct drm_crtc *crtc);
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138 {
139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv->sb_lock);
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144 CCK_FUSE_HPLL_FREQ_MASK;
145 mutex_unlock(&dev_priv->sb_lock);
146
147 return vco_freq[hpll_freq] * 1000;
148 }
149
150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg)
152 {
153 u32 val;
154 int divider;
155
156 if (dev_priv->hpll_freq == 0)
157 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
158
159 mutex_lock(&dev_priv->sb_lock);
160 val = vlv_cck_read(dev_priv, reg);
161 mutex_unlock(&dev_priv->sb_lock);
162
163 divider = val & CCK_FREQUENCY_VALUES;
164
165 WARN((val & CCK_FREQUENCY_STATUS) !=
166 (divider << CCK_FREQUENCY_STATUS_SHIFT),
167 "%s change in progress\n", name);
168
169 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
170 }
171
172 int
173 intel_pch_rawclk(struct drm_device *dev)
174 {
175 struct drm_i915_private *dev_priv = dev->dev_private;
176
177 WARN_ON(!HAS_PCH_SPLIT(dev));
178
179 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
180 }
181
182 /* hrawclock is 1/4 the FSB frequency */
183 int intel_hrawclk(struct drm_device *dev)
184 {
185 struct drm_i915_private *dev_priv = dev->dev_private;
186 uint32_t clkcfg;
187
188 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
189 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
190 return 200;
191
192 clkcfg = I915_READ(CLKCFG);
193 switch (clkcfg & CLKCFG_FSB_MASK) {
194 case CLKCFG_FSB_400:
195 return 100;
196 case CLKCFG_FSB_533:
197 return 133;
198 case CLKCFG_FSB_667:
199 return 166;
200 case CLKCFG_FSB_800:
201 return 200;
202 case CLKCFG_FSB_1067:
203 return 266;
204 case CLKCFG_FSB_1333:
205 return 333;
206 /* these two are just a guess; one of them might be right */
207 case CLKCFG_FSB_1600:
208 case CLKCFG_FSB_1600_ALT:
209 return 400;
210 default:
211 return 133;
212 }
213 }
214
215 static void intel_update_czclk(struct drm_i915_private *dev_priv)
216 {
217 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
218 return;
219
220 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
221 CCK_CZ_CLOCK_CONTROL);
222
223 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
224 }
225
226 static inline u32 /* units of 100MHz */
227 intel_fdi_link_freq(struct drm_device *dev)
228 {
229 if (IS_GEN5(dev)) {
230 struct drm_i915_private *dev_priv = dev->dev_private;
231 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
232 } else
233 return 27;
234 }
235
236 static const intel_limit_t intel_limits_i8xx_dac = {
237 .dot = { .min = 25000, .max = 350000 },
238 .vco = { .min = 908000, .max = 1512000 },
239 .n = { .min = 2, .max = 16 },
240 .m = { .min = 96, .max = 140 },
241 .m1 = { .min = 18, .max = 26 },
242 .m2 = { .min = 6, .max = 16 },
243 .p = { .min = 4, .max = 128 },
244 .p1 = { .min = 2, .max = 33 },
245 .p2 = { .dot_limit = 165000,
246 .p2_slow = 4, .p2_fast = 2 },
247 };
248
249 static const intel_limit_t intel_limits_i8xx_dvo = {
250 .dot = { .min = 25000, .max = 350000 },
251 .vco = { .min = 908000, .max = 1512000 },
252 .n = { .min = 2, .max = 16 },
253 .m = { .min = 96, .max = 140 },
254 .m1 = { .min = 18, .max = 26 },
255 .m2 = { .min = 6, .max = 16 },
256 .p = { .min = 4, .max = 128 },
257 .p1 = { .min = 2, .max = 33 },
258 .p2 = { .dot_limit = 165000,
259 .p2_slow = 4, .p2_fast = 4 },
260 };
261
262 static const intel_limit_t intel_limits_i8xx_lvds = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 908000, .max = 1512000 },
265 .n = { .min = 2, .max = 16 },
266 .m = { .min = 96, .max = 140 },
267 .m1 = { .min = 18, .max = 26 },
268 .m2 = { .min = 6, .max = 16 },
269 .p = { .min = 4, .max = 128 },
270 .p1 = { .min = 1, .max = 6 },
271 .p2 = { .dot_limit = 165000,
272 .p2_slow = 14, .p2_fast = 7 },
273 };
274
275 static const intel_limit_t intel_limits_i9xx_sdvo = {
276 .dot = { .min = 20000, .max = 400000 },
277 .vco = { .min = 1400000, .max = 2800000 },
278 .n = { .min = 1, .max = 6 },
279 .m = { .min = 70, .max = 120 },
280 .m1 = { .min = 8, .max = 18 },
281 .m2 = { .min = 3, .max = 7 },
282 .p = { .min = 5, .max = 80 },
283 .p1 = { .min = 1, .max = 8 },
284 .p2 = { .dot_limit = 200000,
285 .p2_slow = 10, .p2_fast = 5 },
286 };
287
288 static const intel_limit_t intel_limits_i9xx_lvds = {
289 .dot = { .min = 20000, .max = 400000 },
290 .vco = { .min = 1400000, .max = 2800000 },
291 .n = { .min = 1, .max = 6 },
292 .m = { .min = 70, .max = 120 },
293 .m1 = { .min = 8, .max = 18 },
294 .m2 = { .min = 3, .max = 7 },
295 .p = { .min = 7, .max = 98 },
296 .p1 = { .min = 1, .max = 8 },
297 .p2 = { .dot_limit = 112000,
298 .p2_slow = 14, .p2_fast = 7 },
299 };
300
301
302 static const intel_limit_t intel_limits_g4x_sdvo = {
303 .dot = { .min = 25000, .max = 270000 },
304 .vco = { .min = 1750000, .max = 3500000},
305 .n = { .min = 1, .max = 4 },
306 .m = { .min = 104, .max = 138 },
307 .m1 = { .min = 17, .max = 23 },
308 .m2 = { .min = 5, .max = 11 },
309 .p = { .min = 10, .max = 30 },
310 .p1 = { .min = 1, .max = 3},
311 .p2 = { .dot_limit = 270000,
312 .p2_slow = 10,
313 .p2_fast = 10
314 },
315 };
316
317 static const intel_limit_t intel_limits_g4x_hdmi = {
318 .dot = { .min = 22000, .max = 400000 },
319 .vco = { .min = 1750000, .max = 3500000},
320 .n = { .min = 1, .max = 4 },
321 .m = { .min = 104, .max = 138 },
322 .m1 = { .min = 16, .max = 23 },
323 .m2 = { .min = 5, .max = 11 },
324 .p = { .min = 5, .max = 80 },
325 .p1 = { .min = 1, .max = 8},
326 .p2 = { .dot_limit = 165000,
327 .p2_slow = 10, .p2_fast = 5 },
328 };
329
330 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
331 .dot = { .min = 20000, .max = 115000 },
332 .vco = { .min = 1750000, .max = 3500000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 104, .max = 138 },
335 .m1 = { .min = 17, .max = 23 },
336 .m2 = { .min = 5, .max = 11 },
337 .p = { .min = 28, .max = 112 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 0,
340 .p2_slow = 14, .p2_fast = 14
341 },
342 };
343
344 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
345 .dot = { .min = 80000, .max = 224000 },
346 .vco = { .min = 1750000, .max = 3500000 },
347 .n = { .min = 1, .max = 3 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 17, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 14, .max = 42 },
352 .p1 = { .min = 2, .max = 6 },
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 7, .p2_fast = 7
355 },
356 };
357
358 static const intel_limit_t intel_limits_pineview_sdvo = {
359 .dot = { .min = 20000, .max = 400000},
360 .vco = { .min = 1700000, .max = 3500000 },
361 /* Pineview's Ncounter is a ring counter */
362 .n = { .min = 3, .max = 6 },
363 .m = { .min = 2, .max = 256 },
364 /* Pineview only has one combined m divider, which we treat as m2. */
365 .m1 = { .min = 0, .max = 0 },
366 .m2 = { .min = 0, .max = 254 },
367 .p = { .min = 5, .max = 80 },
368 .p1 = { .min = 1, .max = 8 },
369 .p2 = { .dot_limit = 200000,
370 .p2_slow = 10, .p2_fast = 5 },
371 };
372
373 static const intel_limit_t intel_limits_pineview_lvds = {
374 .dot = { .min = 20000, .max = 400000 },
375 .vco = { .min = 1700000, .max = 3500000 },
376 .n = { .min = 3, .max = 6 },
377 .m = { .min = 2, .max = 256 },
378 .m1 = { .min = 0, .max = 0 },
379 .m2 = { .min = 0, .max = 254 },
380 .p = { .min = 7, .max = 112 },
381 .p1 = { .min = 1, .max = 8 },
382 .p2 = { .dot_limit = 112000,
383 .p2_slow = 14, .p2_fast = 14 },
384 };
385
386 /* Ironlake / Sandybridge
387 *
388 * We calculate clock using (register_value + 2) for N/M1/M2, so here
389 * the range value for them is (actual_value - 2).
390 */
391 static const intel_limit_t intel_limits_ironlake_dac = {
392 .dot = { .min = 25000, .max = 350000 },
393 .vco = { .min = 1760000, .max = 3510000 },
394 .n = { .min = 1, .max = 5 },
395 .m = { .min = 79, .max = 127 },
396 .m1 = { .min = 12, .max = 22 },
397 .m2 = { .min = 5, .max = 9 },
398 .p = { .min = 5, .max = 80 },
399 .p1 = { .min = 1, .max = 8 },
400 .p2 = { .dot_limit = 225000,
401 .p2_slow = 10, .p2_fast = 5 },
402 };
403
404 static const intel_limit_t intel_limits_ironlake_single_lvds = {
405 .dot = { .min = 25000, .max = 350000 },
406 .vco = { .min = 1760000, .max = 3510000 },
407 .n = { .min = 1, .max = 3 },
408 .m = { .min = 79, .max = 118 },
409 .m1 = { .min = 12, .max = 22 },
410 .m2 = { .min = 5, .max = 9 },
411 .p = { .min = 28, .max = 112 },
412 .p1 = { .min = 2, .max = 8 },
413 .p2 = { .dot_limit = 225000,
414 .p2_slow = 14, .p2_fast = 14 },
415 };
416
417 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
418 .dot = { .min = 25000, .max = 350000 },
419 .vco = { .min = 1760000, .max = 3510000 },
420 .n = { .min = 1, .max = 3 },
421 .m = { .min = 79, .max = 127 },
422 .m1 = { .min = 12, .max = 22 },
423 .m2 = { .min = 5, .max = 9 },
424 .p = { .min = 14, .max = 56 },
425 .p1 = { .min = 2, .max = 8 },
426 .p2 = { .dot_limit = 225000,
427 .p2_slow = 7, .p2_fast = 7 },
428 };
429
430 /* LVDS 100mhz refclk limits. */
431 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 2 },
435 .m = { .min = 79, .max = 126 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 126 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 42 },
452 .p1 = { .min = 2, .max = 6 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 static const intel_limit_t intel_limits_vlv = {
458 /*
459 * These are the data rate limits (measured in fast clocks)
460 * since those are the strictest limits we have. The fast
461 * clock and actual rate limits are more relaxed, so checking
462 * them would make no difference.
463 */
464 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
465 .vco = { .min = 4000000, .max = 6000000 },
466 .n = { .min = 1, .max = 7 },
467 .m1 = { .min = 2, .max = 3 },
468 .m2 = { .min = 11, .max = 156 },
469 .p1 = { .min = 2, .max = 3 },
470 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
471 };
472
473 static const intel_limit_t intel_limits_chv = {
474 /*
475 * These are the data rate limits (measured in fast clocks)
476 * since those are the strictest limits we have. The fast
477 * clock and actual rate limits are more relaxed, so checking
478 * them would make no difference.
479 */
480 .dot = { .min = 25000 * 5, .max = 540000 * 5},
481 .vco = { .min = 4800000, .max = 6480000 },
482 .n = { .min = 1, .max = 1 },
483 .m1 = { .min = 2, .max = 2 },
484 .m2 = { .min = 24 << 22, .max = 175 << 22 },
485 .p1 = { .min = 2, .max = 4 },
486 .p2 = { .p2_slow = 1, .p2_fast = 14 },
487 };
488
489 static const intel_limit_t intel_limits_bxt = {
490 /* FIXME: find real dot limits */
491 .dot = { .min = 0, .max = INT_MAX },
492 .vco = { .min = 4800000, .max = 6700000 },
493 .n = { .min = 1, .max = 1 },
494 .m1 = { .min = 2, .max = 2 },
495 /* FIXME: find real m2 limits */
496 .m2 = { .min = 2 << 22, .max = 255 << 22 },
497 .p1 = { .min = 2, .max = 4 },
498 .p2 = { .p2_slow = 1, .p2_fast = 20 },
499 };
500
501 static bool
502 needs_modeset(struct drm_crtc_state *state)
503 {
504 return drm_atomic_crtc_needs_modeset(state);
505 }
506
507 /**
508 * Returns whether any output on the specified pipe is of the specified type
509 */
510 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
511 {
512 struct drm_device *dev = crtc->base.dev;
513 struct intel_encoder *encoder;
514
515 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
516 if (encoder->type == type)
517 return true;
518
519 return false;
520 }
521
522 /**
523 * Returns whether any output on the specified pipe will have the specified
524 * type after a staged modeset is complete, i.e., the same as
525 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
526 * encoder->crtc.
527 */
528 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
529 int type)
530 {
531 struct drm_atomic_state *state = crtc_state->base.state;
532 struct drm_connector *connector;
533 struct drm_connector_state *connector_state;
534 struct intel_encoder *encoder;
535 int i, num_connectors = 0;
536
537 for_each_connector_in_state(state, connector, connector_state, i) {
538 if (connector_state->crtc != crtc_state->base.crtc)
539 continue;
540
541 num_connectors++;
542
543 encoder = to_intel_encoder(connector_state->best_encoder);
544 if (encoder->type == type)
545 return true;
546 }
547
548 WARN_ON(num_connectors == 0);
549
550 return false;
551 }
552
553 static const intel_limit_t *
554 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
555 {
556 struct drm_device *dev = crtc_state->base.crtc->dev;
557 const intel_limit_t *limit;
558
559 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
560 if (intel_is_dual_link_lvds(dev)) {
561 if (refclk == 100000)
562 limit = &intel_limits_ironlake_dual_lvds_100m;
563 else
564 limit = &intel_limits_ironlake_dual_lvds;
565 } else {
566 if (refclk == 100000)
567 limit = &intel_limits_ironlake_single_lvds_100m;
568 else
569 limit = &intel_limits_ironlake_single_lvds;
570 }
571 } else
572 limit = &intel_limits_ironlake_dac;
573
574 return limit;
575 }
576
577 static const intel_limit_t *
578 intel_g4x_limit(struct intel_crtc_state *crtc_state)
579 {
580 struct drm_device *dev = crtc_state->base.crtc->dev;
581 const intel_limit_t *limit;
582
583 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
584 if (intel_is_dual_link_lvds(dev))
585 limit = &intel_limits_g4x_dual_channel_lvds;
586 else
587 limit = &intel_limits_g4x_single_channel_lvds;
588 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
589 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
590 limit = &intel_limits_g4x_hdmi;
591 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
592 limit = &intel_limits_g4x_sdvo;
593 } else /* The option is for other outputs */
594 limit = &intel_limits_i9xx_sdvo;
595
596 return limit;
597 }
598
599 static const intel_limit_t *
600 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
601 {
602 struct drm_device *dev = crtc_state->base.crtc->dev;
603 const intel_limit_t *limit;
604
605 if (IS_BROXTON(dev))
606 limit = &intel_limits_bxt;
607 else if (HAS_PCH_SPLIT(dev))
608 limit = intel_ironlake_limit(crtc_state, refclk);
609 else if (IS_G4X(dev)) {
610 limit = intel_g4x_limit(crtc_state);
611 } else if (IS_PINEVIEW(dev)) {
612 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
613 limit = &intel_limits_pineview_lvds;
614 else
615 limit = &intel_limits_pineview_sdvo;
616 } else if (IS_CHERRYVIEW(dev)) {
617 limit = &intel_limits_chv;
618 } else if (IS_VALLEYVIEW(dev)) {
619 limit = &intel_limits_vlv;
620 } else if (!IS_GEN2(dev)) {
621 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
622 limit = &intel_limits_i9xx_lvds;
623 else
624 limit = &intel_limits_i9xx_sdvo;
625 } else {
626 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
627 limit = &intel_limits_i8xx_lvds;
628 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
629 limit = &intel_limits_i8xx_dvo;
630 else
631 limit = &intel_limits_i8xx_dac;
632 }
633 return limit;
634 }
635
636 /*
637 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
638 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
639 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
640 * The helpers' return value is the rate of the clock that is fed to the
641 * display engine's pipe which can be the above fast dot clock rate or a
642 * divided-down version of it.
643 */
644 /* m1 is reserved as 0 in Pineview, n is a ring counter */
645 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
646 {
647 clock->m = clock->m2 + 2;
648 clock->p = clock->p1 * clock->p2;
649 if (WARN_ON(clock->n == 0 || clock->p == 0))
650 return 0;
651 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
652 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
653
654 return clock->dot;
655 }
656
657 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
658 {
659 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
660 }
661
662 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
663 {
664 clock->m = i9xx_dpll_compute_m(clock);
665 clock->p = clock->p1 * clock->p2;
666 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
667 return 0;
668 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
669 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
670
671 return clock->dot;
672 }
673
674 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
675 {
676 clock->m = clock->m1 * clock->m2;
677 clock->p = clock->p1 * clock->p2;
678 if (WARN_ON(clock->n == 0 || clock->p == 0))
679 return 0;
680 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
681 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
682
683 return clock->dot / 5;
684 }
685
686 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
687 {
688 clock->m = clock->m1 * clock->m2;
689 clock->p = clock->p1 * clock->p2;
690 if (WARN_ON(clock->n == 0 || clock->p == 0))
691 return 0;
692 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
693 clock->n << 22);
694 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
695
696 return clock->dot / 5;
697 }
698
699 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
700 /**
701 * Returns whether the given set of divisors are valid for a given refclk with
702 * the given connectors.
703 */
704
705 static bool intel_PLL_is_valid(struct drm_device *dev,
706 const intel_limit_t *limit,
707 const intel_clock_t *clock)
708 {
709 if (clock->n < limit->n.min || limit->n.max < clock->n)
710 INTELPllInvalid("n out of range\n");
711 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
712 INTELPllInvalid("p1 out of range\n");
713 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
714 INTELPllInvalid("m2 out of range\n");
715 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
716 INTELPllInvalid("m1 out of range\n");
717
718 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
719 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
720 if (clock->m1 <= clock->m2)
721 INTELPllInvalid("m1 <= m2\n");
722
723 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
724 if (clock->p < limit->p.min || limit->p.max < clock->p)
725 INTELPllInvalid("p out of range\n");
726 if (clock->m < limit->m.min || limit->m.max < clock->m)
727 INTELPllInvalid("m out of range\n");
728 }
729
730 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
731 INTELPllInvalid("vco out of range\n");
732 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
733 * connector, etc., rather than just a single range.
734 */
735 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
736 INTELPllInvalid("dot out of range\n");
737
738 return true;
739 }
740
741 static int
742 i9xx_select_p2_div(const intel_limit_t *limit,
743 const struct intel_crtc_state *crtc_state,
744 int target)
745 {
746 struct drm_device *dev = crtc_state->base.crtc->dev;
747
748 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
749 /*
750 * For LVDS just rely on its current settings for dual-channel.
751 * We haven't figured out how to reliably set up different
752 * single/dual channel state, if we even can.
753 */
754 if (intel_is_dual_link_lvds(dev))
755 return limit->p2.p2_fast;
756 else
757 return limit->p2.p2_slow;
758 } else {
759 if (target < limit->p2.dot_limit)
760 return limit->p2.p2_slow;
761 else
762 return limit->p2.p2_fast;
763 }
764 }
765
766 static bool
767 i9xx_find_best_dpll(const intel_limit_t *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
771 {
772 struct drm_device *dev = crtc_state->base.crtc->dev;
773 intel_clock_t clock;
774 int err = target;
775
776 memset(best_clock, 0, sizeof(*best_clock));
777
778 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
779
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
781 clock.m1++) {
782 for (clock.m2 = limit->m2.min;
783 clock.m2 <= limit->m2.max; clock.m2++) {
784 if (clock.m2 >= clock.m1)
785 break;
786 for (clock.n = limit->n.min;
787 clock.n <= limit->n.max; clock.n++) {
788 for (clock.p1 = limit->p1.min;
789 clock.p1 <= limit->p1.max; clock.p1++) {
790 int this_err;
791
792 i9xx_calc_dpll_params(refclk, &clock);
793 if (!intel_PLL_is_valid(dev, limit,
794 &clock))
795 continue;
796 if (match_clock &&
797 clock.p != match_clock->p)
798 continue;
799
800 this_err = abs(clock.dot - target);
801 if (this_err < err) {
802 *best_clock = clock;
803 err = this_err;
804 }
805 }
806 }
807 }
808 }
809
810 return (err != target);
811 }
812
813 static bool
814 pnv_find_best_dpll(const intel_limit_t *limit,
815 struct intel_crtc_state *crtc_state,
816 int target, int refclk, intel_clock_t *match_clock,
817 intel_clock_t *best_clock)
818 {
819 struct drm_device *dev = crtc_state->base.crtc->dev;
820 intel_clock_t clock;
821 int err = target;
822
823 memset(best_clock, 0, sizeof(*best_clock));
824
825 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
826
827 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
828 clock.m1++) {
829 for (clock.m2 = limit->m2.min;
830 clock.m2 <= limit->m2.max; clock.m2++) {
831 for (clock.n = limit->n.min;
832 clock.n <= limit->n.max; clock.n++) {
833 for (clock.p1 = limit->p1.min;
834 clock.p1 <= limit->p1.max; clock.p1++) {
835 int this_err;
836
837 pnv_calc_dpll_params(refclk, &clock);
838 if (!intel_PLL_is_valid(dev, limit,
839 &clock))
840 continue;
841 if (match_clock &&
842 clock.p != match_clock->p)
843 continue;
844
845 this_err = abs(clock.dot - target);
846 if (this_err < err) {
847 *best_clock = clock;
848 err = this_err;
849 }
850 }
851 }
852 }
853 }
854
855 return (err != target);
856 }
857
858 static bool
859 g4x_find_best_dpll(const intel_limit_t *limit,
860 struct intel_crtc_state *crtc_state,
861 int target, int refclk, intel_clock_t *match_clock,
862 intel_clock_t *best_clock)
863 {
864 struct drm_device *dev = crtc_state->base.crtc->dev;
865 intel_clock_t clock;
866 int max_n;
867 bool found = false;
868 /* approximately equals target * 0.00585 */
869 int err_most = (target >> 8) + (target >> 9);
870
871 memset(best_clock, 0, sizeof(*best_clock));
872
873 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
874
875 max_n = limit->n.max;
876 /* based on hardware requirement, prefer smaller n to precision */
877 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
878 /* based on hardware requirement, prefere larger m1,m2 */
879 for (clock.m1 = limit->m1.max;
880 clock.m1 >= limit->m1.min; clock.m1--) {
881 for (clock.m2 = limit->m2.max;
882 clock.m2 >= limit->m2.min; clock.m2--) {
883 for (clock.p1 = limit->p1.max;
884 clock.p1 >= limit->p1.min; clock.p1--) {
885 int this_err;
886
887 i9xx_calc_dpll_params(refclk, &clock);
888 if (!intel_PLL_is_valid(dev, limit,
889 &clock))
890 continue;
891
892 this_err = abs(clock.dot - target);
893 if (this_err < err_most) {
894 *best_clock = clock;
895 err_most = this_err;
896 max_n = clock.n;
897 found = true;
898 }
899 }
900 }
901 }
902 }
903 return found;
904 }
905
906 /*
907 * Check if the calculated PLL configuration is more optimal compared to the
908 * best configuration and error found so far. Return the calculated error.
909 */
910 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
911 const intel_clock_t *calculated_clock,
912 const intel_clock_t *best_clock,
913 unsigned int best_error_ppm,
914 unsigned int *error_ppm)
915 {
916 /*
917 * For CHV ignore the error and consider only the P value.
918 * Prefer a bigger P value based on HW requirements.
919 */
920 if (IS_CHERRYVIEW(dev)) {
921 *error_ppm = 0;
922
923 return calculated_clock->p > best_clock->p;
924 }
925
926 if (WARN_ON_ONCE(!target_freq))
927 return false;
928
929 *error_ppm = div_u64(1000000ULL *
930 abs(target_freq - calculated_clock->dot),
931 target_freq);
932 /*
933 * Prefer a better P value over a better (smaller) error if the error
934 * is small. Ensure this preference for future configurations too by
935 * setting the error to 0.
936 */
937 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
938 *error_ppm = 0;
939
940 return true;
941 }
942
943 return *error_ppm + 10 < best_error_ppm;
944 }
945
946 static bool
947 vlv_find_best_dpll(const intel_limit_t *limit,
948 struct intel_crtc_state *crtc_state,
949 int target, int refclk, intel_clock_t *match_clock,
950 intel_clock_t *best_clock)
951 {
952 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
953 struct drm_device *dev = crtc->base.dev;
954 intel_clock_t clock;
955 unsigned int bestppm = 1000000;
956 /* min update 19.2 MHz */
957 int max_n = min(limit->n.max, refclk / 19200);
958 bool found = false;
959
960 target *= 5; /* fast clock */
961
962 memset(best_clock, 0, sizeof(*best_clock));
963
964 /* based on hardware requirement, prefer smaller n to precision */
965 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
966 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
967 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
968 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
969 clock.p = clock.p1 * clock.p2;
970 /* based on hardware requirement, prefer bigger m1,m2 values */
971 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
972 unsigned int ppm;
973
974 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
975 refclk * clock.m1);
976
977 vlv_calc_dpll_params(refclk, &clock);
978
979 if (!intel_PLL_is_valid(dev, limit,
980 &clock))
981 continue;
982
983 if (!vlv_PLL_is_optimal(dev, target,
984 &clock,
985 best_clock,
986 bestppm, &ppm))
987 continue;
988
989 *best_clock = clock;
990 bestppm = ppm;
991 found = true;
992 }
993 }
994 }
995 }
996
997 return found;
998 }
999
1000 static bool
1001 chv_find_best_dpll(const intel_limit_t *limit,
1002 struct intel_crtc_state *crtc_state,
1003 int target, int refclk, intel_clock_t *match_clock,
1004 intel_clock_t *best_clock)
1005 {
1006 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1007 struct drm_device *dev = crtc->base.dev;
1008 unsigned int best_error_ppm;
1009 intel_clock_t clock;
1010 uint64_t m2;
1011 int found = false;
1012
1013 memset(best_clock, 0, sizeof(*best_clock));
1014 best_error_ppm = 1000000;
1015
1016 /*
1017 * Based on hardware doc, the n always set to 1, and m1 always
1018 * set to 2. If requires to support 200Mhz refclk, we need to
1019 * revisit this because n may not 1 anymore.
1020 */
1021 clock.n = 1, clock.m1 = 2;
1022 target *= 5; /* fast clock */
1023
1024 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1025 for (clock.p2 = limit->p2.p2_fast;
1026 clock.p2 >= limit->p2.p2_slow;
1027 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1028 unsigned int error_ppm;
1029
1030 clock.p = clock.p1 * clock.p2;
1031
1032 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1033 clock.n) << 22, refclk * clock.m1);
1034
1035 if (m2 > INT_MAX/clock.m1)
1036 continue;
1037
1038 clock.m2 = m2;
1039
1040 chv_calc_dpll_params(refclk, &clock);
1041
1042 if (!intel_PLL_is_valid(dev, limit, &clock))
1043 continue;
1044
1045 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1046 best_error_ppm, &error_ppm))
1047 continue;
1048
1049 *best_clock = clock;
1050 best_error_ppm = error_ppm;
1051 found = true;
1052 }
1053 }
1054
1055 return found;
1056 }
1057
1058 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1059 intel_clock_t *best_clock)
1060 {
1061 int refclk = i9xx_get_refclk(crtc_state, 0);
1062
1063 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1064 target_clock, refclk, NULL, best_clock);
1065 }
1066
1067 bool intel_crtc_active(struct drm_crtc *crtc)
1068 {
1069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070
1071 /* Be paranoid as we can arrive here with only partial
1072 * state retrieved from the hardware during setup.
1073 *
1074 * We can ditch the adjusted_mode.crtc_clock check as soon
1075 * as Haswell has gained clock readout/fastboot support.
1076 *
1077 * We can ditch the crtc->primary->fb check as soon as we can
1078 * properly reconstruct framebuffers.
1079 *
1080 * FIXME: The intel_crtc->active here should be switched to
1081 * crtc->state->active once we have proper CRTC states wired up
1082 * for atomic.
1083 */
1084 return intel_crtc->active && crtc->primary->state->fb &&
1085 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 }
1087
1088 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089 enum pipe pipe)
1090 {
1091 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1093
1094 return intel_crtc->config->cpu_transcoder;
1095 }
1096
1097 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1098 {
1099 struct drm_i915_private *dev_priv = dev->dev_private;
1100 i915_reg_t reg = PIPEDSL(pipe);
1101 u32 line1, line2;
1102 u32 line_mask;
1103
1104 if (IS_GEN2(dev))
1105 line_mask = DSL_LINEMASK_GEN2;
1106 else
1107 line_mask = DSL_LINEMASK_GEN3;
1108
1109 line1 = I915_READ(reg) & line_mask;
1110 msleep(5);
1111 line2 = I915_READ(reg) & line_mask;
1112
1113 return line1 == line2;
1114 }
1115
1116 /*
1117 * intel_wait_for_pipe_off - wait for pipe to turn off
1118 * @crtc: crtc whose pipe to wait for
1119 *
1120 * After disabling a pipe, we can't wait for vblank in the usual way,
1121 * spinning on the vblank interrupt status bit, since we won't actually
1122 * see an interrupt when the pipe is disabled.
1123 *
1124 * On Gen4 and above:
1125 * wait for the pipe register state bit to turn off
1126 *
1127 * Otherwise:
1128 * wait for the display line value to settle (it usually
1129 * ends up stopping at the start of the next frame).
1130 *
1131 */
1132 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1133 {
1134 struct drm_device *dev = crtc->base.dev;
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1136 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1137 enum pipe pipe = crtc->pipe;
1138
1139 if (INTEL_INFO(dev)->gen >= 4) {
1140 i915_reg_t reg = PIPECONF(cpu_transcoder);
1141
1142 /* Wait for the Pipe State to go off */
1143 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1144 100))
1145 WARN(1, "pipe_off wait timed out\n");
1146 } else {
1147 /* Wait for the display line to settle */
1148 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1149 WARN(1, "pipe_off wait timed out\n");
1150 }
1151 }
1152
1153 /* Only for pre-ILK configs */
1154 void assert_pll(struct drm_i915_private *dev_priv,
1155 enum pipe pipe, bool state)
1156 {
1157 u32 val;
1158 bool cur_state;
1159
1160 val = I915_READ(DPLL(pipe));
1161 cur_state = !!(val & DPLL_VCO_ENABLE);
1162 I915_STATE_WARN(cur_state != state,
1163 "PLL state assertion failure (expected %s, current %s)\n",
1164 onoff(state), onoff(cur_state));
1165 }
1166
1167 /* XXX: the dsi pll is shared between MIPI DSI ports */
1168 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1169 {
1170 u32 val;
1171 bool cur_state;
1172
1173 mutex_lock(&dev_priv->sb_lock);
1174 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1175 mutex_unlock(&dev_priv->sb_lock);
1176
1177 cur_state = val & DSI_PLL_VCO_EN;
1178 I915_STATE_WARN(cur_state != state,
1179 "DSI PLL state assertion failure (expected %s, current %s)\n",
1180 onoff(state), onoff(cur_state));
1181 }
1182 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1183 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1184
1185 struct intel_shared_dpll *
1186 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1187 {
1188 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1189
1190 if (crtc->config->shared_dpll < 0)
1191 return NULL;
1192
1193 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1194 }
1195
1196 /* For ILK+ */
1197 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1198 struct intel_shared_dpll *pll,
1199 bool state)
1200 {
1201 bool cur_state;
1202 struct intel_dpll_hw_state hw_state;
1203
1204 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
1205 return;
1206
1207 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1208 I915_STATE_WARN(cur_state != state,
1209 "%s assertion failure (expected %s, current %s)\n",
1210 pll->name, onoff(state), onoff(cur_state));
1211 }
1212
1213 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1214 enum pipe pipe, bool state)
1215 {
1216 bool cur_state;
1217 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1218 pipe);
1219
1220 if (HAS_DDI(dev_priv->dev)) {
1221 /* DDI does not have a specific FDI_TX register */
1222 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1223 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1224 } else {
1225 u32 val = I915_READ(FDI_TX_CTL(pipe));
1226 cur_state = !!(val & FDI_TX_ENABLE);
1227 }
1228 I915_STATE_WARN(cur_state != state,
1229 "FDI TX state assertion failure (expected %s, current %s)\n",
1230 onoff(state), onoff(cur_state));
1231 }
1232 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1233 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1234
1235 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1236 enum pipe pipe, bool state)
1237 {
1238 u32 val;
1239 bool cur_state;
1240
1241 val = I915_READ(FDI_RX_CTL(pipe));
1242 cur_state = !!(val & FDI_RX_ENABLE);
1243 I915_STATE_WARN(cur_state != state,
1244 "FDI RX state assertion failure (expected %s, current %s)\n",
1245 onoff(state), onoff(cur_state));
1246 }
1247 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1248 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1249
1250 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1251 enum pipe pipe)
1252 {
1253 u32 val;
1254
1255 /* ILK FDI PLL is always enabled */
1256 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1257 return;
1258
1259 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1260 if (HAS_DDI(dev_priv->dev))
1261 return;
1262
1263 val = I915_READ(FDI_TX_CTL(pipe));
1264 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1265 }
1266
1267 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1268 enum pipe pipe, bool state)
1269 {
1270 u32 val;
1271 bool cur_state;
1272
1273 val = I915_READ(FDI_RX_CTL(pipe));
1274 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1275 I915_STATE_WARN(cur_state != state,
1276 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1277 onoff(state), onoff(cur_state));
1278 }
1279
1280 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1281 enum pipe pipe)
1282 {
1283 struct drm_device *dev = dev_priv->dev;
1284 i915_reg_t pp_reg;
1285 u32 val;
1286 enum pipe panel_pipe = PIPE_A;
1287 bool locked = true;
1288
1289 if (WARN_ON(HAS_DDI(dev)))
1290 return;
1291
1292 if (HAS_PCH_SPLIT(dev)) {
1293 u32 port_sel;
1294
1295 pp_reg = PCH_PP_CONTROL;
1296 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1297
1298 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1299 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1300 panel_pipe = PIPE_B;
1301 /* XXX: else fix for eDP */
1302 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1303 /* presumably write lock depends on pipe, not port select */
1304 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1305 panel_pipe = pipe;
1306 } else {
1307 pp_reg = PP_CONTROL;
1308 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1309 panel_pipe = PIPE_B;
1310 }
1311
1312 val = I915_READ(pp_reg);
1313 if (!(val & PANEL_POWER_ON) ||
1314 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1315 locked = false;
1316
1317 I915_STATE_WARN(panel_pipe == pipe && locked,
1318 "panel assertion failure, pipe %c regs locked\n",
1319 pipe_name(pipe));
1320 }
1321
1322 static void assert_cursor(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, bool state)
1324 {
1325 struct drm_device *dev = dev_priv->dev;
1326 bool cur_state;
1327
1328 if (IS_845G(dev) || IS_I865G(dev))
1329 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1330 else
1331 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1332
1333 I915_STATE_WARN(cur_state != state,
1334 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1335 pipe_name(pipe), onoff(state), onoff(cur_state));
1336 }
1337 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1338 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1339
1340 void assert_pipe(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, bool state)
1342 {
1343 bool cur_state;
1344 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1345 pipe);
1346 enum intel_display_power_domain power_domain;
1347
1348 /* if we need the pipe quirk it must be always on */
1349 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1350 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1351 state = true;
1352
1353 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1354 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1355 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1356 cur_state = !!(val & PIPECONF_ENABLE);
1357
1358 intel_display_power_put(dev_priv, power_domain);
1359 } else {
1360 cur_state = false;
1361 }
1362
1363 I915_STATE_WARN(cur_state != state,
1364 "pipe %c assertion failure (expected %s, current %s)\n",
1365 pipe_name(pipe), onoff(state), onoff(cur_state));
1366 }
1367
1368 static void assert_plane(struct drm_i915_private *dev_priv,
1369 enum plane plane, bool state)
1370 {
1371 u32 val;
1372 bool cur_state;
1373
1374 val = I915_READ(DSPCNTR(plane));
1375 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1376 I915_STATE_WARN(cur_state != state,
1377 "plane %c assertion failure (expected %s, current %s)\n",
1378 plane_name(plane), onoff(state), onoff(cur_state));
1379 }
1380
1381 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1382 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1383
1384 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe)
1386 {
1387 struct drm_device *dev = dev_priv->dev;
1388 int i;
1389
1390 /* Primary planes are fixed to pipes on gen4+ */
1391 if (INTEL_INFO(dev)->gen >= 4) {
1392 u32 val = I915_READ(DSPCNTR(pipe));
1393 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1394 "plane %c assertion failure, should be disabled but not\n",
1395 plane_name(pipe));
1396 return;
1397 }
1398
1399 /* Need to check both planes against the pipe */
1400 for_each_pipe(dev_priv, i) {
1401 u32 val = I915_READ(DSPCNTR(i));
1402 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1403 DISPPLANE_SEL_PIPE_SHIFT;
1404 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1405 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1406 plane_name(i), pipe_name(pipe));
1407 }
1408 }
1409
1410 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1411 enum pipe pipe)
1412 {
1413 struct drm_device *dev = dev_priv->dev;
1414 int sprite;
1415
1416 if (INTEL_INFO(dev)->gen >= 9) {
1417 for_each_sprite(dev_priv, pipe, sprite) {
1418 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1419 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1420 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1421 sprite, pipe_name(pipe));
1422 }
1423 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1424 for_each_sprite(dev_priv, pipe, sprite) {
1425 u32 val = I915_READ(SPCNTR(pipe, sprite));
1426 I915_STATE_WARN(val & SP_ENABLE,
1427 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1428 sprite_name(pipe, sprite), pipe_name(pipe));
1429 }
1430 } else if (INTEL_INFO(dev)->gen >= 7) {
1431 u32 val = I915_READ(SPRCTL(pipe));
1432 I915_STATE_WARN(val & SPRITE_ENABLE,
1433 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1434 plane_name(pipe), pipe_name(pipe));
1435 } else if (INTEL_INFO(dev)->gen >= 5) {
1436 u32 val = I915_READ(DVSCNTR(pipe));
1437 I915_STATE_WARN(val & DVS_ENABLE,
1438 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1439 plane_name(pipe), pipe_name(pipe));
1440 }
1441 }
1442
1443 static void assert_vblank_disabled(struct drm_crtc *crtc)
1444 {
1445 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1446 drm_crtc_vblank_put(crtc);
1447 }
1448
1449 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1450 {
1451 u32 val;
1452 bool enabled;
1453
1454 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1455
1456 val = I915_READ(PCH_DREF_CONTROL);
1457 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1458 DREF_SUPERSPREAD_SOURCE_MASK));
1459 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1460 }
1461
1462 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1463 enum pipe pipe)
1464 {
1465 u32 val;
1466 bool enabled;
1467
1468 val = I915_READ(PCH_TRANSCONF(pipe));
1469 enabled = !!(val & TRANS_ENABLE);
1470 I915_STATE_WARN(enabled,
1471 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1472 pipe_name(pipe));
1473 }
1474
1475 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1476 enum pipe pipe, u32 port_sel, u32 val)
1477 {
1478 if ((val & DP_PORT_EN) == 0)
1479 return false;
1480
1481 if (HAS_PCH_CPT(dev_priv->dev)) {
1482 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1483 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1484 return false;
1485 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1486 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1487 return false;
1488 } else {
1489 if ((val & DP_PIPE_MASK) != (pipe << 30))
1490 return false;
1491 }
1492 return true;
1493 }
1494
1495 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1496 enum pipe pipe, u32 val)
1497 {
1498 if ((val & SDVO_ENABLE) == 0)
1499 return false;
1500
1501 if (HAS_PCH_CPT(dev_priv->dev)) {
1502 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1503 return false;
1504 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1505 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1506 return false;
1507 } else {
1508 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1509 return false;
1510 }
1511 return true;
1512 }
1513
1514 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1515 enum pipe pipe, u32 val)
1516 {
1517 if ((val & LVDS_PORT_EN) == 0)
1518 return false;
1519
1520 if (HAS_PCH_CPT(dev_priv->dev)) {
1521 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1522 return false;
1523 } else {
1524 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1525 return false;
1526 }
1527 return true;
1528 }
1529
1530 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1531 enum pipe pipe, u32 val)
1532 {
1533 if ((val & ADPA_DAC_ENABLE) == 0)
1534 return false;
1535 if (HAS_PCH_CPT(dev_priv->dev)) {
1536 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1537 return false;
1538 } else {
1539 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1540 return false;
1541 }
1542 return true;
1543 }
1544
1545 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1546 enum pipe pipe, i915_reg_t reg,
1547 u32 port_sel)
1548 {
1549 u32 val = I915_READ(reg);
1550 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1551 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1552 i915_mmio_reg_offset(reg), pipe_name(pipe));
1553
1554 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1555 && (val & DP_PIPEB_SELECT),
1556 "IBX PCH dp port still using transcoder B\n");
1557 }
1558
1559 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1560 enum pipe pipe, i915_reg_t reg)
1561 {
1562 u32 val = I915_READ(reg);
1563 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1564 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1565 i915_mmio_reg_offset(reg), pipe_name(pipe));
1566
1567 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1568 && (val & SDVO_PIPE_B_SELECT),
1569 "IBX PCH hdmi port still using transcoder B\n");
1570 }
1571
1572 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1573 enum pipe pipe)
1574 {
1575 u32 val;
1576
1577 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1580
1581 val = I915_READ(PCH_ADPA);
1582 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1583 "PCH VGA enabled on transcoder %c, should be disabled\n",
1584 pipe_name(pipe));
1585
1586 val = I915_READ(PCH_LVDS);
1587 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1588 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1589 pipe_name(pipe));
1590
1591 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1594 }
1595
1596 static void vlv_enable_pll(struct intel_crtc *crtc,
1597 const struct intel_crtc_state *pipe_config)
1598 {
1599 struct drm_device *dev = crtc->base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 i915_reg_t reg = DPLL(crtc->pipe);
1602 u32 dpll = pipe_config->dpll_hw_state.dpll;
1603
1604 assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606 /* PLL is protected by panel, make sure we can write it */
1607 if (IS_MOBILE(dev_priv->dev))
1608 assert_panel_unlocked(dev_priv, crtc->pipe);
1609
1610 I915_WRITE(reg, dpll);
1611 POSTING_READ(reg);
1612 udelay(150);
1613
1614 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1615 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1616
1617 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1618 POSTING_READ(DPLL_MD(crtc->pipe));
1619
1620 /* We do this three times for luck */
1621 I915_WRITE(reg, dpll);
1622 POSTING_READ(reg);
1623 udelay(150); /* wait for warmup */
1624 I915_WRITE(reg, dpll);
1625 POSTING_READ(reg);
1626 udelay(150); /* wait for warmup */
1627 I915_WRITE(reg, dpll);
1628 POSTING_READ(reg);
1629 udelay(150); /* wait for warmup */
1630 }
1631
1632 static void chv_enable_pll(struct intel_crtc *crtc,
1633 const struct intel_crtc_state *pipe_config)
1634 {
1635 struct drm_device *dev = crtc->base.dev;
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637 int pipe = crtc->pipe;
1638 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1639 u32 tmp;
1640
1641 assert_pipe_disabled(dev_priv, crtc->pipe);
1642
1643 mutex_lock(&dev_priv->sb_lock);
1644
1645 /* Enable back the 10bit clock to display controller */
1646 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1647 tmp |= DPIO_DCLKP_EN;
1648 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1649
1650 mutex_unlock(&dev_priv->sb_lock);
1651
1652 /*
1653 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1654 */
1655 udelay(1);
1656
1657 /* Enable PLL */
1658 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1659
1660 /* Check PLL is locked */
1661 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1662 DRM_ERROR("PLL %d failed to lock\n", pipe);
1663
1664 /* not sure when this should be written */
1665 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1666 POSTING_READ(DPLL_MD(pipe));
1667 }
1668
1669 static int intel_num_dvo_pipes(struct drm_device *dev)
1670 {
1671 struct intel_crtc *crtc;
1672 int count = 0;
1673
1674 for_each_intel_crtc(dev, crtc)
1675 count += crtc->base.state->active &&
1676 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1677
1678 return count;
1679 }
1680
1681 static void i9xx_enable_pll(struct intel_crtc *crtc)
1682 {
1683 struct drm_device *dev = crtc->base.dev;
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685 i915_reg_t reg = DPLL(crtc->pipe);
1686 u32 dpll = crtc->config->dpll_hw_state.dpll;
1687
1688 assert_pipe_disabled(dev_priv, crtc->pipe);
1689
1690 /* No really, not for ILK+ */
1691 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1692
1693 /* PLL is protected by panel, make sure we can write it */
1694 if (IS_MOBILE(dev) && !IS_I830(dev))
1695 assert_panel_unlocked(dev_priv, crtc->pipe);
1696
1697 /* Enable DVO 2x clock on both PLLs if necessary */
1698 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1699 /*
1700 * It appears to be important that we don't enable this
1701 * for the current pipe before otherwise configuring the
1702 * PLL. No idea how this should be handled if multiple
1703 * DVO outputs are enabled simultaneosly.
1704 */
1705 dpll |= DPLL_DVO_2X_MODE;
1706 I915_WRITE(DPLL(!crtc->pipe),
1707 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1708 }
1709
1710 /*
1711 * Apparently we need to have VGA mode enabled prior to changing
1712 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1713 * dividers, even though the register value does change.
1714 */
1715 I915_WRITE(reg, 0);
1716
1717 I915_WRITE(reg, dpll);
1718
1719 /* Wait for the clocks to stabilize. */
1720 POSTING_READ(reg);
1721 udelay(150);
1722
1723 if (INTEL_INFO(dev)->gen >= 4) {
1724 I915_WRITE(DPLL_MD(crtc->pipe),
1725 crtc->config->dpll_hw_state.dpll_md);
1726 } else {
1727 /* The pixel multiplier can only be updated once the
1728 * DPLL is enabled and the clocks are stable.
1729 *
1730 * So write it again.
1731 */
1732 I915_WRITE(reg, dpll);
1733 }
1734
1735 /* We do this three times for luck */
1736 I915_WRITE(reg, dpll);
1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
1739 I915_WRITE(reg, dpll);
1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742 I915_WRITE(reg, dpll);
1743 POSTING_READ(reg);
1744 udelay(150); /* wait for warmup */
1745 }
1746
1747 /**
1748 * i9xx_disable_pll - disable a PLL
1749 * @dev_priv: i915 private structure
1750 * @pipe: pipe PLL to disable
1751 *
1752 * Disable the PLL for @pipe, making sure the pipe is off first.
1753 *
1754 * Note! This is for pre-ILK only.
1755 */
1756 static void i9xx_disable_pll(struct intel_crtc *crtc)
1757 {
1758 struct drm_device *dev = crtc->base.dev;
1759 struct drm_i915_private *dev_priv = dev->dev_private;
1760 enum pipe pipe = crtc->pipe;
1761
1762 /* Disable DVO 2x clock on both PLLs if necessary */
1763 if (IS_I830(dev) &&
1764 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1765 !intel_num_dvo_pipes(dev)) {
1766 I915_WRITE(DPLL(PIPE_B),
1767 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1768 I915_WRITE(DPLL(PIPE_A),
1769 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1770 }
1771
1772 /* Don't disable pipe or pipe PLLs if needed */
1773 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1774 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1775 return;
1776
1777 /* Make sure the pipe isn't still relying on us */
1778 assert_pipe_disabled(dev_priv, pipe);
1779
1780 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1781 POSTING_READ(DPLL(pipe));
1782 }
1783
1784 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1785 {
1786 u32 val;
1787
1788 /* Make sure the pipe isn't still relying on us */
1789 assert_pipe_disabled(dev_priv, pipe);
1790
1791 /*
1792 * Leave integrated clock source and reference clock enabled for pipe B.
1793 * The latter is needed for VGA hotplug / manual detection.
1794 */
1795 val = DPLL_VGA_MODE_DIS;
1796 if (pipe == PIPE_B)
1797 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1798 I915_WRITE(DPLL(pipe), val);
1799 POSTING_READ(DPLL(pipe));
1800
1801 }
1802
1803 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1804 {
1805 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1806 u32 val;
1807
1808 /* Make sure the pipe isn't still relying on us */
1809 assert_pipe_disabled(dev_priv, pipe);
1810
1811 /* Set PLL en = 0 */
1812 val = DPLL_SSC_REF_CLK_CHV |
1813 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1814 if (pipe != PIPE_A)
1815 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1816 I915_WRITE(DPLL(pipe), val);
1817 POSTING_READ(DPLL(pipe));
1818
1819 mutex_lock(&dev_priv->sb_lock);
1820
1821 /* Disable 10bit clock to display controller */
1822 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1823 val &= ~DPIO_DCLKP_EN;
1824 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1825
1826 mutex_unlock(&dev_priv->sb_lock);
1827 }
1828
1829 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1830 struct intel_digital_port *dport,
1831 unsigned int expected_mask)
1832 {
1833 u32 port_mask;
1834 i915_reg_t dpll_reg;
1835
1836 switch (dport->port) {
1837 case PORT_B:
1838 port_mask = DPLL_PORTB_READY_MASK;
1839 dpll_reg = DPLL(0);
1840 break;
1841 case PORT_C:
1842 port_mask = DPLL_PORTC_READY_MASK;
1843 dpll_reg = DPLL(0);
1844 expected_mask <<= 4;
1845 break;
1846 case PORT_D:
1847 port_mask = DPLL_PORTD_READY_MASK;
1848 dpll_reg = DPIO_PHY_STATUS;
1849 break;
1850 default:
1851 BUG();
1852 }
1853
1854 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1855 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1856 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1857 }
1858
1859 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1860 {
1861 struct drm_device *dev = crtc->base.dev;
1862 struct drm_i915_private *dev_priv = dev->dev_private;
1863 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1864
1865 if (WARN_ON(pll == NULL))
1866 return;
1867
1868 WARN_ON(!pll->config.crtc_mask);
1869 if (pll->active == 0) {
1870 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1871 WARN_ON(pll->on);
1872 assert_shared_dpll_disabled(dev_priv, pll);
1873
1874 pll->mode_set(dev_priv, pll);
1875 }
1876 }
1877
1878 /**
1879 * intel_enable_shared_dpll - enable PCH PLL
1880 * @dev_priv: i915 private structure
1881 * @pipe: pipe PLL to enable
1882 *
1883 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1884 * drives the transcoder clock.
1885 */
1886 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1887 {
1888 struct drm_device *dev = crtc->base.dev;
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1890 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1891
1892 if (WARN_ON(pll == NULL))
1893 return;
1894
1895 if (WARN_ON(pll->config.crtc_mask == 0))
1896 return;
1897
1898 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1899 pll->name, pll->active, pll->on,
1900 crtc->base.base.id);
1901
1902 if (pll->active++) {
1903 WARN_ON(!pll->on);
1904 assert_shared_dpll_enabled(dev_priv, pll);
1905 return;
1906 }
1907 WARN_ON(pll->on);
1908
1909 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1910
1911 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1912 pll->enable(dev_priv, pll);
1913 pll->on = true;
1914 }
1915
1916 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1917 {
1918 struct drm_device *dev = crtc->base.dev;
1919 struct drm_i915_private *dev_priv = dev->dev_private;
1920 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1921
1922 /* PCH only available on ILK+ */
1923 if (INTEL_INFO(dev)->gen < 5)
1924 return;
1925
1926 if (pll == NULL)
1927 return;
1928
1929 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1930 return;
1931
1932 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1933 pll->name, pll->active, pll->on,
1934 crtc->base.base.id);
1935
1936 if (WARN_ON(pll->active == 0)) {
1937 assert_shared_dpll_disabled(dev_priv, pll);
1938 return;
1939 }
1940
1941 assert_shared_dpll_enabled(dev_priv, pll);
1942 WARN_ON(!pll->on);
1943 if (--pll->active)
1944 return;
1945
1946 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1947 pll->disable(dev_priv, pll);
1948 pll->on = false;
1949
1950 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1951 }
1952
1953 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1954 enum pipe pipe)
1955 {
1956 struct drm_device *dev = dev_priv->dev;
1957 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1959 i915_reg_t reg;
1960 uint32_t val, pipeconf_val;
1961
1962 /* PCH only available on ILK+ */
1963 BUG_ON(!HAS_PCH_SPLIT(dev));
1964
1965 /* Make sure PCH DPLL is enabled */
1966 assert_shared_dpll_enabled(dev_priv,
1967 intel_crtc_to_shared_dpll(intel_crtc));
1968
1969 /* FDI must be feeding us bits for PCH ports */
1970 assert_fdi_tx_enabled(dev_priv, pipe);
1971 assert_fdi_rx_enabled(dev_priv, pipe);
1972
1973 if (HAS_PCH_CPT(dev)) {
1974 /* Workaround: Set the timing override bit before enabling the
1975 * pch transcoder. */
1976 reg = TRANS_CHICKEN2(pipe);
1977 val = I915_READ(reg);
1978 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1979 I915_WRITE(reg, val);
1980 }
1981
1982 reg = PCH_TRANSCONF(pipe);
1983 val = I915_READ(reg);
1984 pipeconf_val = I915_READ(PIPECONF(pipe));
1985
1986 if (HAS_PCH_IBX(dev_priv->dev)) {
1987 /*
1988 * Make the BPC in transcoder be consistent with
1989 * that in pipeconf reg. For HDMI we must use 8bpc
1990 * here for both 8bpc and 12bpc.
1991 */
1992 val &= ~PIPECONF_BPC_MASK;
1993 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1994 val |= PIPECONF_8BPC;
1995 else
1996 val |= pipeconf_val & PIPECONF_BPC_MASK;
1997 }
1998
1999 val &= ~TRANS_INTERLACE_MASK;
2000 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2001 if (HAS_PCH_IBX(dev_priv->dev) &&
2002 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2003 val |= TRANS_LEGACY_INTERLACED_ILK;
2004 else
2005 val |= TRANS_INTERLACED;
2006 else
2007 val |= TRANS_PROGRESSIVE;
2008
2009 I915_WRITE(reg, val | TRANS_ENABLE);
2010 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2011 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2012 }
2013
2014 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2015 enum transcoder cpu_transcoder)
2016 {
2017 u32 val, pipeconf_val;
2018
2019 /* PCH only available on ILK+ */
2020 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2021
2022 /* FDI must be feeding us bits for PCH ports */
2023 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2024 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2025
2026 /* Workaround: set timing override bit. */
2027 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2028 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2029 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2030
2031 val = TRANS_ENABLE;
2032 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2033
2034 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2035 PIPECONF_INTERLACED_ILK)
2036 val |= TRANS_INTERLACED;
2037 else
2038 val |= TRANS_PROGRESSIVE;
2039
2040 I915_WRITE(LPT_TRANSCONF, val);
2041 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2042 DRM_ERROR("Failed to enable PCH transcoder\n");
2043 }
2044
2045 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2046 enum pipe pipe)
2047 {
2048 struct drm_device *dev = dev_priv->dev;
2049 i915_reg_t reg;
2050 uint32_t val;
2051
2052 /* FDI relies on the transcoder */
2053 assert_fdi_tx_disabled(dev_priv, pipe);
2054 assert_fdi_rx_disabled(dev_priv, pipe);
2055
2056 /* Ports must be off as well */
2057 assert_pch_ports_disabled(dev_priv, pipe);
2058
2059 reg = PCH_TRANSCONF(pipe);
2060 val = I915_READ(reg);
2061 val &= ~TRANS_ENABLE;
2062 I915_WRITE(reg, val);
2063 /* wait for PCH transcoder off, transcoder state */
2064 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2065 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2066
2067 if (HAS_PCH_CPT(dev)) {
2068 /* Workaround: Clear the timing override chicken bit again. */
2069 reg = TRANS_CHICKEN2(pipe);
2070 val = I915_READ(reg);
2071 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2072 I915_WRITE(reg, val);
2073 }
2074 }
2075
2076 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2077 {
2078 u32 val;
2079
2080 val = I915_READ(LPT_TRANSCONF);
2081 val &= ~TRANS_ENABLE;
2082 I915_WRITE(LPT_TRANSCONF, val);
2083 /* wait for PCH transcoder off, transcoder state */
2084 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2085 DRM_ERROR("Failed to disable PCH transcoder\n");
2086
2087 /* Workaround: clear timing override bit. */
2088 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2089 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2090 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2091 }
2092
2093 /**
2094 * intel_enable_pipe - enable a pipe, asserting requirements
2095 * @crtc: crtc responsible for the pipe
2096 *
2097 * Enable @crtc's pipe, making sure that various hardware specific requirements
2098 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2099 */
2100 static void intel_enable_pipe(struct intel_crtc *crtc)
2101 {
2102 struct drm_device *dev = crtc->base.dev;
2103 struct drm_i915_private *dev_priv = dev->dev_private;
2104 enum pipe pipe = crtc->pipe;
2105 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2106 enum pipe pch_transcoder;
2107 i915_reg_t reg;
2108 u32 val;
2109
2110 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2111
2112 assert_planes_disabled(dev_priv, pipe);
2113 assert_cursor_disabled(dev_priv, pipe);
2114 assert_sprites_disabled(dev_priv, pipe);
2115
2116 if (HAS_PCH_LPT(dev_priv->dev))
2117 pch_transcoder = TRANSCODER_A;
2118 else
2119 pch_transcoder = pipe;
2120
2121 /*
2122 * A pipe without a PLL won't actually be able to drive bits from
2123 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2124 * need the check.
2125 */
2126 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2127 if (crtc->config->has_dsi_encoder)
2128 assert_dsi_pll_enabled(dev_priv);
2129 else
2130 assert_pll_enabled(dev_priv, pipe);
2131 else {
2132 if (crtc->config->has_pch_encoder) {
2133 /* if driving the PCH, we need FDI enabled */
2134 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2135 assert_fdi_tx_pll_enabled(dev_priv,
2136 (enum pipe) cpu_transcoder);
2137 }
2138 /* FIXME: assert CPU port conditions for SNB+ */
2139 }
2140
2141 reg = PIPECONF(cpu_transcoder);
2142 val = I915_READ(reg);
2143 if (val & PIPECONF_ENABLE) {
2144 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2145 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2146 return;
2147 }
2148
2149 I915_WRITE(reg, val | PIPECONF_ENABLE);
2150 POSTING_READ(reg);
2151
2152 /*
2153 * Until the pipe starts DSL will read as 0, which would cause
2154 * an apparent vblank timestamp jump, which messes up also the
2155 * frame count when it's derived from the timestamps. So let's
2156 * wait for the pipe to start properly before we call
2157 * drm_crtc_vblank_on()
2158 */
2159 if (dev->max_vblank_count == 0 &&
2160 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2161 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2162 }
2163
2164 /**
2165 * intel_disable_pipe - disable a pipe, asserting requirements
2166 * @crtc: crtc whose pipes is to be disabled
2167 *
2168 * Disable the pipe of @crtc, making sure that various hardware
2169 * specific requirements are met, if applicable, e.g. plane
2170 * disabled, panel fitter off, etc.
2171 *
2172 * Will wait until the pipe has shut down before returning.
2173 */
2174 static void intel_disable_pipe(struct intel_crtc *crtc)
2175 {
2176 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2177 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2178 enum pipe pipe = crtc->pipe;
2179 i915_reg_t reg;
2180 u32 val;
2181
2182 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2183
2184 /*
2185 * Make sure planes won't keep trying to pump pixels to us,
2186 * or we might hang the display.
2187 */
2188 assert_planes_disabled(dev_priv, pipe);
2189 assert_cursor_disabled(dev_priv, pipe);
2190 assert_sprites_disabled(dev_priv, pipe);
2191
2192 reg = PIPECONF(cpu_transcoder);
2193 val = I915_READ(reg);
2194 if ((val & PIPECONF_ENABLE) == 0)
2195 return;
2196
2197 /*
2198 * Double wide has implications for planes
2199 * so best keep it disabled when not needed.
2200 */
2201 if (crtc->config->double_wide)
2202 val &= ~PIPECONF_DOUBLE_WIDE;
2203
2204 /* Don't disable pipe or pipe PLLs if needed */
2205 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2206 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2207 val &= ~PIPECONF_ENABLE;
2208
2209 I915_WRITE(reg, val);
2210 if ((val & PIPECONF_ENABLE) == 0)
2211 intel_wait_for_pipe_off(crtc);
2212 }
2213
2214 static bool need_vtd_wa(struct drm_device *dev)
2215 {
2216 #ifdef CONFIG_INTEL_IOMMU
2217 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2218 return true;
2219 #endif
2220 return false;
2221 }
2222
2223 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2224 {
2225 return IS_GEN2(dev_priv) ? 2048 : 4096;
2226 }
2227
2228 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2229 uint64_t fb_modifier, unsigned int cpp)
2230 {
2231 switch (fb_modifier) {
2232 case DRM_FORMAT_MOD_NONE:
2233 return cpp;
2234 case I915_FORMAT_MOD_X_TILED:
2235 if (IS_GEN2(dev_priv))
2236 return 128;
2237 else
2238 return 512;
2239 case I915_FORMAT_MOD_Y_TILED:
2240 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2241 return 128;
2242 else
2243 return 512;
2244 case I915_FORMAT_MOD_Yf_TILED:
2245 switch (cpp) {
2246 case 1:
2247 return 64;
2248 case 2:
2249 case 4:
2250 return 128;
2251 case 8:
2252 case 16:
2253 return 256;
2254 default:
2255 MISSING_CASE(cpp);
2256 return cpp;
2257 }
2258 break;
2259 default:
2260 MISSING_CASE(fb_modifier);
2261 return cpp;
2262 }
2263 }
2264
2265 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2266 uint64_t fb_modifier, unsigned int cpp)
2267 {
2268 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2269 return 1;
2270 else
2271 return intel_tile_size(dev_priv) /
2272 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2273 }
2274
2275 /* Return the tile dimensions in pixel units */
2276 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2277 unsigned int *tile_width,
2278 unsigned int *tile_height,
2279 uint64_t fb_modifier,
2280 unsigned int cpp)
2281 {
2282 unsigned int tile_width_bytes =
2283 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2284
2285 *tile_width = tile_width_bytes / cpp;
2286 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2287 }
2288
2289 unsigned int
2290 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2291 uint32_t pixel_format, uint64_t fb_modifier)
2292 {
2293 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2294 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2295
2296 return ALIGN(height, tile_height);
2297 }
2298
2299 static void
2300 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2301 const struct drm_framebuffer *fb,
2302 unsigned int rotation)
2303 {
2304 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2305 struct intel_rotation_info *info = &view->params.rotated;
2306 unsigned int tile_size, tile_width, tile_height, cpp;
2307
2308 *view = i915_ggtt_view_normal;
2309
2310 if (!intel_rotation_90_or_270(rotation))
2311 return;
2312
2313 *view = i915_ggtt_view_rotated;
2314
2315 info->height = fb->height;
2316 info->pixel_format = fb->pixel_format;
2317 info->pitch = fb->pitches[0];
2318 info->uv_offset = fb->offsets[1];
2319 info->fb_modifier = fb->modifier[0];
2320
2321 tile_size = intel_tile_size(dev_priv);
2322
2323 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2324 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2325 fb->modifier[0], cpp);
2326
2327 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2328 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2329 info->size = info->width_pages * info->height_pages * tile_size;
2330
2331 if (info->pixel_format == DRM_FORMAT_NV12) {
2332 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2333 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2334 fb->modifier[1], cpp);
2335
2336 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2337 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
2338 info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
2339 }
2340 }
2341
2342 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2343 {
2344 if (INTEL_INFO(dev_priv)->gen >= 9)
2345 return 256 * 1024;
2346 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2347 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2348 return 128 * 1024;
2349 else if (INTEL_INFO(dev_priv)->gen >= 4)
2350 return 4 * 1024;
2351 else
2352 return 0;
2353 }
2354
2355 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2356 uint64_t fb_modifier)
2357 {
2358 switch (fb_modifier) {
2359 case DRM_FORMAT_MOD_NONE:
2360 return intel_linear_alignment(dev_priv);
2361 case I915_FORMAT_MOD_X_TILED:
2362 if (INTEL_INFO(dev_priv)->gen >= 9)
2363 return 256 * 1024;
2364 return 0;
2365 case I915_FORMAT_MOD_Y_TILED:
2366 case I915_FORMAT_MOD_Yf_TILED:
2367 return 1 * 1024 * 1024;
2368 default:
2369 MISSING_CASE(fb_modifier);
2370 return 0;
2371 }
2372 }
2373
2374 int
2375 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2376 unsigned int rotation)
2377 {
2378 struct drm_device *dev = fb->dev;
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2381 struct i915_ggtt_view view;
2382 u32 alignment;
2383 int ret;
2384
2385 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2386
2387 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2388
2389 intel_fill_fb_ggtt_view(&view, fb, rotation);
2390
2391 /* Note that the w/a also requires 64 PTE of padding following the
2392 * bo. We currently fill all unused PTE with the shadow page and so
2393 * we should always have valid PTE following the scanout preventing
2394 * the VT-d warning.
2395 */
2396 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2397 alignment = 256 * 1024;
2398
2399 /*
2400 * Global gtt pte registers are special registers which actually forward
2401 * writes to a chunk of system memory. Which means that there is no risk
2402 * that the register values disappear as soon as we call
2403 * intel_runtime_pm_put(), so it is correct to wrap only the
2404 * pin/unpin/fence and not more.
2405 */
2406 intel_runtime_pm_get(dev_priv);
2407
2408 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2409 &view);
2410 if (ret)
2411 goto err_pm;
2412
2413 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2414 * fence, whereas 965+ only requires a fence if using
2415 * framebuffer compression. For simplicity, we always install
2416 * a fence as the cost is not that onerous.
2417 */
2418 if (view.type == I915_GGTT_VIEW_NORMAL) {
2419 ret = i915_gem_object_get_fence(obj);
2420 if (ret == -EDEADLK) {
2421 /*
2422 * -EDEADLK means there are no free fences
2423 * no pending flips.
2424 *
2425 * This is propagated to atomic, but it uses
2426 * -EDEADLK to force a locking recovery, so
2427 * change the returned error to -EBUSY.
2428 */
2429 ret = -EBUSY;
2430 goto err_unpin;
2431 } else if (ret)
2432 goto err_unpin;
2433
2434 i915_gem_object_pin_fence(obj);
2435 }
2436
2437 intel_runtime_pm_put(dev_priv);
2438 return 0;
2439
2440 err_unpin:
2441 i915_gem_object_unpin_from_display_plane(obj, &view);
2442 err_pm:
2443 intel_runtime_pm_put(dev_priv);
2444 return ret;
2445 }
2446
2447 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2448 {
2449 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2450 struct i915_ggtt_view view;
2451
2452 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2453
2454 intel_fill_fb_ggtt_view(&view, fb, rotation);
2455
2456 if (view.type == I915_GGTT_VIEW_NORMAL)
2457 i915_gem_object_unpin_fence(obj);
2458
2459 i915_gem_object_unpin_from_display_plane(obj, &view);
2460 }
2461
2462 /*
2463 * Adjust the tile offset by moving the difference into
2464 * the x/y offsets.
2465 *
2466 * Input tile dimensions and pitch must already be
2467 * rotated to match x and y, and in pixel units.
2468 */
2469 static u32 intel_adjust_tile_offset(int *x, int *y,
2470 unsigned int tile_width,
2471 unsigned int tile_height,
2472 unsigned int tile_size,
2473 unsigned int pitch_tiles,
2474 u32 old_offset,
2475 u32 new_offset)
2476 {
2477 unsigned int tiles;
2478
2479 WARN_ON(old_offset & (tile_size - 1));
2480 WARN_ON(new_offset & (tile_size - 1));
2481 WARN_ON(new_offset > old_offset);
2482
2483 tiles = (old_offset - new_offset) / tile_size;
2484
2485 *y += tiles / pitch_tiles * tile_height;
2486 *x += tiles % pitch_tiles * tile_width;
2487
2488 return new_offset;
2489 }
2490
2491 /*
2492 * Computes the linear offset to the base tile and adjusts
2493 * x, y. bytes per pixel is assumed to be a power-of-two.
2494 *
2495 * In the 90/270 rotated case, x and y are assumed
2496 * to be already rotated to match the rotated GTT view, and
2497 * pitch is the tile_height aligned framebuffer height.
2498 */
2499 u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
2500 int *x, int *y,
2501 uint64_t fb_modifier,
2502 unsigned int cpp,
2503 unsigned int pitch,
2504 unsigned int rotation)
2505 {
2506 u32 offset, offset_aligned, alignment;
2507
2508 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2509 if (alignment)
2510 alignment--;
2511
2512 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2513 unsigned int tile_size, tile_width, tile_height;
2514 unsigned int tile_rows, tiles, pitch_tiles;
2515
2516 tile_size = intel_tile_size(dev_priv);
2517 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2518 fb_modifier, cpp);
2519
2520 if (intel_rotation_90_or_270(rotation)) {
2521 pitch_tiles = pitch / tile_height;
2522 swap(tile_width, tile_height);
2523 } else {
2524 pitch_tiles = pitch / (tile_width * cpp);
2525 }
2526
2527 tile_rows = *y / tile_height;
2528 *y %= tile_height;
2529
2530 tiles = *x / tile_width;
2531 *x %= tile_width;
2532
2533 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2534 offset_aligned = offset & ~alignment;
2535
2536 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2537 tile_size, pitch_tiles,
2538 offset, offset_aligned);
2539 } else {
2540 offset = *y * pitch + *x * cpp;
2541 offset_aligned = offset & ~alignment;
2542
2543 *y = (offset & alignment) / pitch;
2544 *x = ((offset & alignment) - *y * pitch) / cpp;
2545 }
2546
2547 return offset_aligned;
2548 }
2549
2550 static int i9xx_format_to_fourcc(int format)
2551 {
2552 switch (format) {
2553 case DISPPLANE_8BPP:
2554 return DRM_FORMAT_C8;
2555 case DISPPLANE_BGRX555:
2556 return DRM_FORMAT_XRGB1555;
2557 case DISPPLANE_BGRX565:
2558 return DRM_FORMAT_RGB565;
2559 default:
2560 case DISPPLANE_BGRX888:
2561 return DRM_FORMAT_XRGB8888;
2562 case DISPPLANE_RGBX888:
2563 return DRM_FORMAT_XBGR8888;
2564 case DISPPLANE_BGRX101010:
2565 return DRM_FORMAT_XRGB2101010;
2566 case DISPPLANE_RGBX101010:
2567 return DRM_FORMAT_XBGR2101010;
2568 }
2569 }
2570
2571 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2572 {
2573 switch (format) {
2574 case PLANE_CTL_FORMAT_RGB_565:
2575 return DRM_FORMAT_RGB565;
2576 default:
2577 case PLANE_CTL_FORMAT_XRGB_8888:
2578 if (rgb_order) {
2579 if (alpha)
2580 return DRM_FORMAT_ABGR8888;
2581 else
2582 return DRM_FORMAT_XBGR8888;
2583 } else {
2584 if (alpha)
2585 return DRM_FORMAT_ARGB8888;
2586 else
2587 return DRM_FORMAT_XRGB8888;
2588 }
2589 case PLANE_CTL_FORMAT_XRGB_2101010:
2590 if (rgb_order)
2591 return DRM_FORMAT_XBGR2101010;
2592 else
2593 return DRM_FORMAT_XRGB2101010;
2594 }
2595 }
2596
2597 static bool
2598 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2599 struct intel_initial_plane_config *plane_config)
2600 {
2601 struct drm_device *dev = crtc->base.dev;
2602 struct drm_i915_private *dev_priv = to_i915(dev);
2603 struct drm_i915_gem_object *obj = NULL;
2604 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2605 struct drm_framebuffer *fb = &plane_config->fb->base;
2606 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2607 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2608 PAGE_SIZE);
2609
2610 size_aligned -= base_aligned;
2611
2612 if (plane_config->size == 0)
2613 return false;
2614
2615 /* If the FB is too big, just don't use it since fbdev is not very
2616 * important and we should probably use that space with FBC or other
2617 * features. */
2618 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2619 return false;
2620
2621 mutex_lock(&dev->struct_mutex);
2622
2623 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2624 base_aligned,
2625 base_aligned,
2626 size_aligned);
2627 if (!obj) {
2628 mutex_unlock(&dev->struct_mutex);
2629 return false;
2630 }
2631
2632 obj->tiling_mode = plane_config->tiling;
2633 if (obj->tiling_mode == I915_TILING_X)
2634 obj->stride = fb->pitches[0];
2635
2636 mode_cmd.pixel_format = fb->pixel_format;
2637 mode_cmd.width = fb->width;
2638 mode_cmd.height = fb->height;
2639 mode_cmd.pitches[0] = fb->pitches[0];
2640 mode_cmd.modifier[0] = fb->modifier[0];
2641 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2642
2643 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2644 &mode_cmd, obj)) {
2645 DRM_DEBUG_KMS("intel fb init failed\n");
2646 goto out_unref_obj;
2647 }
2648
2649 mutex_unlock(&dev->struct_mutex);
2650
2651 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2652 return true;
2653
2654 out_unref_obj:
2655 drm_gem_object_unreference(&obj->base);
2656 mutex_unlock(&dev->struct_mutex);
2657 return false;
2658 }
2659
2660 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2661 static void
2662 update_state_fb(struct drm_plane *plane)
2663 {
2664 if (plane->fb == plane->state->fb)
2665 return;
2666
2667 if (plane->state->fb)
2668 drm_framebuffer_unreference(plane->state->fb);
2669 plane->state->fb = plane->fb;
2670 if (plane->state->fb)
2671 drm_framebuffer_reference(plane->state->fb);
2672 }
2673
2674 static void
2675 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2676 struct intel_initial_plane_config *plane_config)
2677 {
2678 struct drm_device *dev = intel_crtc->base.dev;
2679 struct drm_i915_private *dev_priv = dev->dev_private;
2680 struct drm_crtc *c;
2681 struct intel_crtc *i;
2682 struct drm_i915_gem_object *obj;
2683 struct drm_plane *primary = intel_crtc->base.primary;
2684 struct drm_plane_state *plane_state = primary->state;
2685 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2686 struct intel_plane *intel_plane = to_intel_plane(primary);
2687 struct intel_plane_state *intel_state =
2688 to_intel_plane_state(plane_state);
2689 struct drm_framebuffer *fb;
2690
2691 if (!plane_config->fb)
2692 return;
2693
2694 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2695 fb = &plane_config->fb->base;
2696 goto valid_fb;
2697 }
2698
2699 kfree(plane_config->fb);
2700
2701 /*
2702 * Failed to alloc the obj, check to see if we should share
2703 * an fb with another CRTC instead
2704 */
2705 for_each_crtc(dev, c) {
2706 i = to_intel_crtc(c);
2707
2708 if (c == &intel_crtc->base)
2709 continue;
2710
2711 if (!i->active)
2712 continue;
2713
2714 fb = c->primary->fb;
2715 if (!fb)
2716 continue;
2717
2718 obj = intel_fb_obj(fb);
2719 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2720 drm_framebuffer_reference(fb);
2721 goto valid_fb;
2722 }
2723 }
2724
2725 /*
2726 * We've failed to reconstruct the BIOS FB. Current display state
2727 * indicates that the primary plane is visible, but has a NULL FB,
2728 * which will lead to problems later if we don't fix it up. The
2729 * simplest solution is to just disable the primary plane now and
2730 * pretend the BIOS never had it enabled.
2731 */
2732 to_intel_plane_state(plane_state)->visible = false;
2733 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2734 intel_pre_disable_primary(&intel_crtc->base);
2735 intel_plane->disable_plane(primary, &intel_crtc->base);
2736
2737 return;
2738
2739 valid_fb:
2740 plane_state->src_x = 0;
2741 plane_state->src_y = 0;
2742 plane_state->src_w = fb->width << 16;
2743 plane_state->src_h = fb->height << 16;
2744
2745 plane_state->crtc_x = 0;
2746 plane_state->crtc_y = 0;
2747 plane_state->crtc_w = fb->width;
2748 plane_state->crtc_h = fb->height;
2749
2750 intel_state->src.x1 = plane_state->src_x;
2751 intel_state->src.y1 = plane_state->src_y;
2752 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2753 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2754 intel_state->dst.x1 = plane_state->crtc_x;
2755 intel_state->dst.y1 = plane_state->crtc_y;
2756 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2757 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2758
2759 obj = intel_fb_obj(fb);
2760 if (obj->tiling_mode != I915_TILING_NONE)
2761 dev_priv->preserve_bios_swizzle = true;
2762
2763 drm_framebuffer_reference(fb);
2764 primary->fb = primary->state->fb = fb;
2765 primary->crtc = primary->state->crtc = &intel_crtc->base;
2766 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2767 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2768 }
2769
2770 static void i9xx_update_primary_plane(struct drm_plane *primary,
2771 const struct intel_crtc_state *crtc_state,
2772 const struct intel_plane_state *plane_state)
2773 {
2774 struct drm_device *dev = primary->dev;
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2777 struct drm_framebuffer *fb = plane_state->base.fb;
2778 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2779 int plane = intel_crtc->plane;
2780 u32 linear_offset;
2781 u32 dspcntr;
2782 i915_reg_t reg = DSPCNTR(plane);
2783 unsigned int rotation = plane_state->base.rotation;
2784 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2785 int x = plane_state->src.x1 >> 16;
2786 int y = plane_state->src.y1 >> 16;
2787
2788 dspcntr = DISPPLANE_GAMMA_ENABLE;
2789
2790 dspcntr |= DISPLAY_PLANE_ENABLE;
2791
2792 if (INTEL_INFO(dev)->gen < 4) {
2793 if (intel_crtc->pipe == PIPE_B)
2794 dspcntr |= DISPPLANE_SEL_PIPE_B;
2795
2796 /* pipesrc and dspsize control the size that is scaled from,
2797 * which should always be the user's requested size.
2798 */
2799 I915_WRITE(DSPSIZE(plane),
2800 ((crtc_state->pipe_src_h - 1) << 16) |
2801 (crtc_state->pipe_src_w - 1));
2802 I915_WRITE(DSPPOS(plane), 0);
2803 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2804 I915_WRITE(PRIMSIZE(plane),
2805 ((crtc_state->pipe_src_h - 1) << 16) |
2806 (crtc_state->pipe_src_w - 1));
2807 I915_WRITE(PRIMPOS(plane), 0);
2808 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2809 }
2810
2811 switch (fb->pixel_format) {
2812 case DRM_FORMAT_C8:
2813 dspcntr |= DISPPLANE_8BPP;
2814 break;
2815 case DRM_FORMAT_XRGB1555:
2816 dspcntr |= DISPPLANE_BGRX555;
2817 break;
2818 case DRM_FORMAT_RGB565:
2819 dspcntr |= DISPPLANE_BGRX565;
2820 break;
2821 case DRM_FORMAT_XRGB8888:
2822 dspcntr |= DISPPLANE_BGRX888;
2823 break;
2824 case DRM_FORMAT_XBGR8888:
2825 dspcntr |= DISPPLANE_RGBX888;
2826 break;
2827 case DRM_FORMAT_XRGB2101010:
2828 dspcntr |= DISPPLANE_BGRX101010;
2829 break;
2830 case DRM_FORMAT_XBGR2101010:
2831 dspcntr |= DISPPLANE_RGBX101010;
2832 break;
2833 default:
2834 BUG();
2835 }
2836
2837 if (INTEL_INFO(dev)->gen >= 4 &&
2838 obj->tiling_mode != I915_TILING_NONE)
2839 dspcntr |= DISPPLANE_TILED;
2840
2841 if (IS_G4X(dev))
2842 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2843
2844 linear_offset = y * fb->pitches[0] + x * cpp;
2845
2846 if (INTEL_INFO(dev)->gen >= 4) {
2847 intel_crtc->dspaddr_offset =
2848 intel_compute_tile_offset(dev_priv, &x, &y,
2849 fb->modifier[0], cpp,
2850 fb->pitches[0], rotation);
2851 linear_offset -= intel_crtc->dspaddr_offset;
2852 } else {
2853 intel_crtc->dspaddr_offset = linear_offset;
2854 }
2855
2856 if (rotation == BIT(DRM_ROTATE_180)) {
2857 dspcntr |= DISPPLANE_ROTATE_180;
2858
2859 x += (crtc_state->pipe_src_w - 1);
2860 y += (crtc_state->pipe_src_h - 1);
2861
2862 /* Finding the last pixel of the last line of the display
2863 data and adding to linear_offset*/
2864 linear_offset +=
2865 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2866 (crtc_state->pipe_src_w - 1) * cpp;
2867 }
2868
2869 intel_crtc->adjusted_x = x;
2870 intel_crtc->adjusted_y = y;
2871
2872 I915_WRITE(reg, dspcntr);
2873
2874 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2875 if (INTEL_INFO(dev)->gen >= 4) {
2876 I915_WRITE(DSPSURF(plane),
2877 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2878 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2879 I915_WRITE(DSPLINOFF(plane), linear_offset);
2880 } else
2881 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2882 POSTING_READ(reg);
2883 }
2884
2885 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2886 struct drm_crtc *crtc)
2887 {
2888 struct drm_device *dev = crtc->dev;
2889 struct drm_i915_private *dev_priv = dev->dev_private;
2890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2891 int plane = intel_crtc->plane;
2892
2893 I915_WRITE(DSPCNTR(plane), 0);
2894 if (INTEL_INFO(dev_priv)->gen >= 4)
2895 I915_WRITE(DSPSURF(plane), 0);
2896 else
2897 I915_WRITE(DSPADDR(plane), 0);
2898 POSTING_READ(DSPCNTR(plane));
2899 }
2900
2901 static void ironlake_update_primary_plane(struct drm_plane *primary,
2902 const struct intel_crtc_state *crtc_state,
2903 const struct intel_plane_state *plane_state)
2904 {
2905 struct drm_device *dev = primary->dev;
2906 struct drm_i915_private *dev_priv = dev->dev_private;
2907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2908 struct drm_framebuffer *fb = plane_state->base.fb;
2909 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2910 int plane = intel_crtc->plane;
2911 u32 linear_offset;
2912 u32 dspcntr;
2913 i915_reg_t reg = DSPCNTR(plane);
2914 unsigned int rotation = plane_state->base.rotation;
2915 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2916 int x = plane_state->src.x1 >> 16;
2917 int y = plane_state->src.y1 >> 16;
2918
2919 dspcntr = DISPPLANE_GAMMA_ENABLE;
2920 dspcntr |= DISPLAY_PLANE_ENABLE;
2921
2922 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2923 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2924
2925 switch (fb->pixel_format) {
2926 case DRM_FORMAT_C8:
2927 dspcntr |= DISPPLANE_8BPP;
2928 break;
2929 case DRM_FORMAT_RGB565:
2930 dspcntr |= DISPPLANE_BGRX565;
2931 break;
2932 case DRM_FORMAT_XRGB8888:
2933 dspcntr |= DISPPLANE_BGRX888;
2934 break;
2935 case DRM_FORMAT_XBGR8888:
2936 dspcntr |= DISPPLANE_RGBX888;
2937 break;
2938 case DRM_FORMAT_XRGB2101010:
2939 dspcntr |= DISPPLANE_BGRX101010;
2940 break;
2941 case DRM_FORMAT_XBGR2101010:
2942 dspcntr |= DISPPLANE_RGBX101010;
2943 break;
2944 default:
2945 BUG();
2946 }
2947
2948 if (obj->tiling_mode != I915_TILING_NONE)
2949 dspcntr |= DISPPLANE_TILED;
2950
2951 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2952 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2953
2954 linear_offset = y * fb->pitches[0] + x * cpp;
2955 intel_crtc->dspaddr_offset =
2956 intel_compute_tile_offset(dev_priv, &x, &y,
2957 fb->modifier[0], cpp,
2958 fb->pitches[0], rotation);
2959 linear_offset -= intel_crtc->dspaddr_offset;
2960 if (rotation == BIT(DRM_ROTATE_180)) {
2961 dspcntr |= DISPPLANE_ROTATE_180;
2962
2963 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2964 x += (crtc_state->pipe_src_w - 1);
2965 y += (crtc_state->pipe_src_h - 1);
2966
2967 /* Finding the last pixel of the last line of the display
2968 data and adding to linear_offset*/
2969 linear_offset +=
2970 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2971 (crtc_state->pipe_src_w - 1) * cpp;
2972 }
2973 }
2974
2975 intel_crtc->adjusted_x = x;
2976 intel_crtc->adjusted_y = y;
2977
2978 I915_WRITE(reg, dspcntr);
2979
2980 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2981 I915_WRITE(DSPSURF(plane),
2982 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2983 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2984 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2985 } else {
2986 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2987 I915_WRITE(DSPLINOFF(plane), linear_offset);
2988 }
2989 POSTING_READ(reg);
2990 }
2991
2992 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2993 uint64_t fb_modifier, uint32_t pixel_format)
2994 {
2995 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2996 return 64;
2997 } else {
2998 int cpp = drm_format_plane_cpp(pixel_format, 0);
2999
3000 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3001 }
3002 }
3003
3004 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
3005 struct drm_i915_gem_object *obj,
3006 unsigned int plane)
3007 {
3008 struct i915_ggtt_view view;
3009 struct i915_vma *vma;
3010 u64 offset;
3011
3012 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
3013 intel_plane->base.state->rotation);
3014
3015 vma = i915_gem_obj_to_ggtt_view(obj, &view);
3016 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3017 view.type))
3018 return -1;
3019
3020 offset = vma->node.start;
3021
3022 if (plane == 1) {
3023 offset += vma->ggtt_view.params.rotated.uv_start_page *
3024 PAGE_SIZE;
3025 }
3026
3027 WARN_ON(upper_32_bits(offset));
3028
3029 return lower_32_bits(offset);
3030 }
3031
3032 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3033 {
3034 struct drm_device *dev = intel_crtc->base.dev;
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036
3037 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3038 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3039 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3040 }
3041
3042 /*
3043 * This function detaches (aka. unbinds) unused scalers in hardware
3044 */
3045 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3046 {
3047 struct intel_crtc_scaler_state *scaler_state;
3048 int i;
3049
3050 scaler_state = &intel_crtc->config->scaler_state;
3051
3052 /* loop through and disable scalers that aren't in use */
3053 for (i = 0; i < intel_crtc->num_scalers; i++) {
3054 if (!scaler_state->scalers[i].in_use)
3055 skl_detach_scaler(intel_crtc, i);
3056 }
3057 }
3058
3059 u32 skl_plane_ctl_format(uint32_t pixel_format)
3060 {
3061 switch (pixel_format) {
3062 case DRM_FORMAT_C8:
3063 return PLANE_CTL_FORMAT_INDEXED;
3064 case DRM_FORMAT_RGB565:
3065 return PLANE_CTL_FORMAT_RGB_565;
3066 case DRM_FORMAT_XBGR8888:
3067 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3068 case DRM_FORMAT_XRGB8888:
3069 return PLANE_CTL_FORMAT_XRGB_8888;
3070 /*
3071 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3072 * to be already pre-multiplied. We need to add a knob (or a different
3073 * DRM_FORMAT) for user-space to configure that.
3074 */
3075 case DRM_FORMAT_ABGR8888:
3076 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3077 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3078 case DRM_FORMAT_ARGB8888:
3079 return PLANE_CTL_FORMAT_XRGB_8888 |
3080 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3081 case DRM_FORMAT_XRGB2101010:
3082 return PLANE_CTL_FORMAT_XRGB_2101010;
3083 case DRM_FORMAT_XBGR2101010:
3084 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3085 case DRM_FORMAT_YUYV:
3086 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3087 case DRM_FORMAT_YVYU:
3088 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3089 case DRM_FORMAT_UYVY:
3090 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3091 case DRM_FORMAT_VYUY:
3092 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3093 default:
3094 MISSING_CASE(pixel_format);
3095 }
3096
3097 return 0;
3098 }
3099
3100 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3101 {
3102 switch (fb_modifier) {
3103 case DRM_FORMAT_MOD_NONE:
3104 break;
3105 case I915_FORMAT_MOD_X_TILED:
3106 return PLANE_CTL_TILED_X;
3107 case I915_FORMAT_MOD_Y_TILED:
3108 return PLANE_CTL_TILED_Y;
3109 case I915_FORMAT_MOD_Yf_TILED:
3110 return PLANE_CTL_TILED_YF;
3111 default:
3112 MISSING_CASE(fb_modifier);
3113 }
3114
3115 return 0;
3116 }
3117
3118 u32 skl_plane_ctl_rotation(unsigned int rotation)
3119 {
3120 switch (rotation) {
3121 case BIT(DRM_ROTATE_0):
3122 break;
3123 /*
3124 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3125 * while i915 HW rotation is clockwise, thats why this swapping.
3126 */
3127 case BIT(DRM_ROTATE_90):
3128 return PLANE_CTL_ROTATE_270;
3129 case BIT(DRM_ROTATE_180):
3130 return PLANE_CTL_ROTATE_180;
3131 case BIT(DRM_ROTATE_270):
3132 return PLANE_CTL_ROTATE_90;
3133 default:
3134 MISSING_CASE(rotation);
3135 }
3136
3137 return 0;
3138 }
3139
3140 static void skylake_update_primary_plane(struct drm_plane *plane,
3141 const struct intel_crtc_state *crtc_state,
3142 const struct intel_plane_state *plane_state)
3143 {
3144 struct drm_device *dev = plane->dev;
3145 struct drm_i915_private *dev_priv = dev->dev_private;
3146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3147 struct drm_framebuffer *fb = plane_state->base.fb;
3148 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3149 int pipe = intel_crtc->pipe;
3150 u32 plane_ctl, stride_div, stride;
3151 u32 tile_height, plane_offset, plane_size;
3152 unsigned int rotation = plane_state->base.rotation;
3153 int x_offset, y_offset;
3154 u32 surf_addr;
3155 int scaler_id = plane_state->scaler_id;
3156 int src_x = plane_state->src.x1 >> 16;
3157 int src_y = plane_state->src.y1 >> 16;
3158 int src_w = drm_rect_width(&plane_state->src) >> 16;
3159 int src_h = drm_rect_height(&plane_state->src) >> 16;
3160 int dst_x = plane_state->dst.x1;
3161 int dst_y = plane_state->dst.y1;
3162 int dst_w = drm_rect_width(&plane_state->dst);
3163 int dst_h = drm_rect_height(&plane_state->dst);
3164
3165 plane_ctl = PLANE_CTL_ENABLE |
3166 PLANE_CTL_PIPE_GAMMA_ENABLE |
3167 PLANE_CTL_PIPE_CSC_ENABLE;
3168
3169 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3170 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3171 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3172 plane_ctl |= skl_plane_ctl_rotation(rotation);
3173
3174 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3175 fb->pixel_format);
3176 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3177
3178 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3179
3180 if (intel_rotation_90_or_270(rotation)) {
3181 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3182
3183 /* stride = Surface height in tiles */
3184 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3185 stride = DIV_ROUND_UP(fb->height, tile_height);
3186 x_offset = stride * tile_height - src_y - src_h;
3187 y_offset = src_x;
3188 plane_size = (src_w - 1) << 16 | (src_h - 1);
3189 } else {
3190 stride = fb->pitches[0] / stride_div;
3191 x_offset = src_x;
3192 y_offset = src_y;
3193 plane_size = (src_h - 1) << 16 | (src_w - 1);
3194 }
3195 plane_offset = y_offset << 16 | x_offset;
3196
3197 intel_crtc->adjusted_x = x_offset;
3198 intel_crtc->adjusted_y = y_offset;
3199
3200 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3201 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3202 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3203 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3204
3205 if (scaler_id >= 0) {
3206 uint32_t ps_ctrl = 0;
3207
3208 WARN_ON(!dst_w || !dst_h);
3209 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3210 crtc_state->scaler_state.scalers[scaler_id].mode;
3211 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3212 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3213 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3214 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3215 I915_WRITE(PLANE_POS(pipe, 0), 0);
3216 } else {
3217 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3218 }
3219
3220 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3221
3222 POSTING_READ(PLANE_SURF(pipe, 0));
3223 }
3224
3225 static void skylake_disable_primary_plane(struct drm_plane *primary,
3226 struct drm_crtc *crtc)
3227 {
3228 struct drm_device *dev = crtc->dev;
3229 struct drm_i915_private *dev_priv = dev->dev_private;
3230 int pipe = to_intel_crtc(crtc)->pipe;
3231
3232 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3233 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3234 POSTING_READ(PLANE_SURF(pipe, 0));
3235 }
3236
3237 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3238 static int
3239 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3240 int x, int y, enum mode_set_atomic state)
3241 {
3242 /* Support for kgdboc is disabled, this needs a major rework. */
3243 DRM_ERROR("legacy panic handler not supported any more.\n");
3244
3245 return -ENODEV;
3246 }
3247
3248 static void intel_complete_page_flips(struct drm_device *dev)
3249 {
3250 struct drm_crtc *crtc;
3251
3252 for_each_crtc(dev, crtc) {
3253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3254 enum plane plane = intel_crtc->plane;
3255
3256 intel_prepare_page_flip(dev, plane);
3257 intel_finish_page_flip_plane(dev, plane);
3258 }
3259 }
3260
3261 static void intel_update_primary_planes(struct drm_device *dev)
3262 {
3263 struct drm_crtc *crtc;
3264
3265 for_each_crtc(dev, crtc) {
3266 struct intel_plane *plane = to_intel_plane(crtc->primary);
3267 struct intel_plane_state *plane_state;
3268
3269 drm_modeset_lock_crtc(crtc, &plane->base);
3270 plane_state = to_intel_plane_state(plane->base.state);
3271
3272 if (plane_state->visible)
3273 plane->update_plane(&plane->base,
3274 to_intel_crtc_state(crtc->state),
3275 plane_state);
3276
3277 drm_modeset_unlock_crtc(crtc);
3278 }
3279 }
3280
3281 void intel_prepare_reset(struct drm_device *dev)
3282 {
3283 /* no reset support for gen2 */
3284 if (IS_GEN2(dev))
3285 return;
3286
3287 /* reset doesn't touch the display */
3288 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3289 return;
3290
3291 drm_modeset_lock_all(dev);
3292 /*
3293 * Disabling the crtcs gracefully seems nicer. Also the
3294 * g33 docs say we should at least disable all the planes.
3295 */
3296 intel_display_suspend(dev);
3297 }
3298
3299 void intel_finish_reset(struct drm_device *dev)
3300 {
3301 struct drm_i915_private *dev_priv = to_i915(dev);
3302
3303 /*
3304 * Flips in the rings will be nuked by the reset,
3305 * so complete all pending flips so that user space
3306 * will get its events and not get stuck.
3307 */
3308 intel_complete_page_flips(dev);
3309
3310 /* no reset support for gen2 */
3311 if (IS_GEN2(dev))
3312 return;
3313
3314 /* reset doesn't touch the display */
3315 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3316 /*
3317 * Flips in the rings have been nuked by the reset,
3318 * so update the base address of all primary
3319 * planes to the the last fb to make sure we're
3320 * showing the correct fb after a reset.
3321 *
3322 * FIXME: Atomic will make this obsolete since we won't schedule
3323 * CS-based flips (which might get lost in gpu resets) any more.
3324 */
3325 intel_update_primary_planes(dev);
3326 return;
3327 }
3328
3329 /*
3330 * The display has been reset as well,
3331 * so need a full re-initialization.
3332 */
3333 intel_runtime_pm_disable_interrupts(dev_priv);
3334 intel_runtime_pm_enable_interrupts(dev_priv);
3335
3336 intel_modeset_init_hw(dev);
3337
3338 spin_lock_irq(&dev_priv->irq_lock);
3339 if (dev_priv->display.hpd_irq_setup)
3340 dev_priv->display.hpd_irq_setup(dev);
3341 spin_unlock_irq(&dev_priv->irq_lock);
3342
3343 intel_display_resume(dev);
3344
3345 intel_hpd_init(dev_priv);
3346
3347 drm_modeset_unlock_all(dev);
3348 }
3349
3350 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3351 {
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355 bool pending;
3356
3357 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3358 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3359 return false;
3360
3361 spin_lock_irq(&dev->event_lock);
3362 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3363 spin_unlock_irq(&dev->event_lock);
3364
3365 return pending;
3366 }
3367
3368 static void intel_update_pipe_config(struct intel_crtc *crtc,
3369 struct intel_crtc_state *old_crtc_state)
3370 {
3371 struct drm_device *dev = crtc->base.dev;
3372 struct drm_i915_private *dev_priv = dev->dev_private;
3373 struct intel_crtc_state *pipe_config =
3374 to_intel_crtc_state(crtc->base.state);
3375
3376 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3377 crtc->base.mode = crtc->base.state->mode;
3378
3379 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3380 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3381 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3382
3383 if (HAS_DDI(dev))
3384 intel_set_pipe_csc(&crtc->base);
3385
3386 /*
3387 * Update pipe size and adjust fitter if needed: the reason for this is
3388 * that in compute_mode_changes we check the native mode (not the pfit
3389 * mode) to see if we can flip rather than do a full mode set. In the
3390 * fastboot case, we'll flip, but if we don't update the pipesrc and
3391 * pfit state, we'll end up with a big fb scanned out into the wrong
3392 * sized surface.
3393 */
3394
3395 I915_WRITE(PIPESRC(crtc->pipe),
3396 ((pipe_config->pipe_src_w - 1) << 16) |
3397 (pipe_config->pipe_src_h - 1));
3398
3399 /* on skylake this is done by detaching scalers */
3400 if (INTEL_INFO(dev)->gen >= 9) {
3401 skl_detach_scalers(crtc);
3402
3403 if (pipe_config->pch_pfit.enabled)
3404 skylake_pfit_enable(crtc);
3405 } else if (HAS_PCH_SPLIT(dev)) {
3406 if (pipe_config->pch_pfit.enabled)
3407 ironlake_pfit_enable(crtc);
3408 else if (old_crtc_state->pch_pfit.enabled)
3409 ironlake_pfit_disable(crtc, true);
3410 }
3411 }
3412
3413 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3414 {
3415 struct drm_device *dev = crtc->dev;
3416 struct drm_i915_private *dev_priv = dev->dev_private;
3417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3418 int pipe = intel_crtc->pipe;
3419 i915_reg_t reg;
3420 u32 temp;
3421
3422 /* enable normal train */
3423 reg = FDI_TX_CTL(pipe);
3424 temp = I915_READ(reg);
3425 if (IS_IVYBRIDGE(dev)) {
3426 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3427 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3428 } else {
3429 temp &= ~FDI_LINK_TRAIN_NONE;
3430 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3431 }
3432 I915_WRITE(reg, temp);
3433
3434 reg = FDI_RX_CTL(pipe);
3435 temp = I915_READ(reg);
3436 if (HAS_PCH_CPT(dev)) {
3437 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3438 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3439 } else {
3440 temp &= ~FDI_LINK_TRAIN_NONE;
3441 temp |= FDI_LINK_TRAIN_NONE;
3442 }
3443 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3444
3445 /* wait one idle pattern time */
3446 POSTING_READ(reg);
3447 udelay(1000);
3448
3449 /* IVB wants error correction enabled */
3450 if (IS_IVYBRIDGE(dev))
3451 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3452 FDI_FE_ERRC_ENABLE);
3453 }
3454
3455 /* The FDI link training functions for ILK/Ibexpeak. */
3456 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3457 {
3458 struct drm_device *dev = crtc->dev;
3459 struct drm_i915_private *dev_priv = dev->dev_private;
3460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3461 int pipe = intel_crtc->pipe;
3462 i915_reg_t reg;
3463 u32 temp, tries;
3464
3465 /* FDI needs bits from pipe first */
3466 assert_pipe_enabled(dev_priv, pipe);
3467
3468 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3469 for train result */
3470 reg = FDI_RX_IMR(pipe);
3471 temp = I915_READ(reg);
3472 temp &= ~FDI_RX_SYMBOL_LOCK;
3473 temp &= ~FDI_RX_BIT_LOCK;
3474 I915_WRITE(reg, temp);
3475 I915_READ(reg);
3476 udelay(150);
3477
3478 /* enable CPU FDI TX and PCH FDI RX */
3479 reg = FDI_TX_CTL(pipe);
3480 temp = I915_READ(reg);
3481 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3482 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3483 temp &= ~FDI_LINK_TRAIN_NONE;
3484 temp |= FDI_LINK_TRAIN_PATTERN_1;
3485 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3486
3487 reg = FDI_RX_CTL(pipe);
3488 temp = I915_READ(reg);
3489 temp &= ~FDI_LINK_TRAIN_NONE;
3490 temp |= FDI_LINK_TRAIN_PATTERN_1;
3491 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3492
3493 POSTING_READ(reg);
3494 udelay(150);
3495
3496 /* Ironlake workaround, enable clock pointer after FDI enable*/
3497 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3498 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3499 FDI_RX_PHASE_SYNC_POINTER_EN);
3500
3501 reg = FDI_RX_IIR(pipe);
3502 for (tries = 0; tries < 5; tries++) {
3503 temp = I915_READ(reg);
3504 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3505
3506 if ((temp & FDI_RX_BIT_LOCK)) {
3507 DRM_DEBUG_KMS("FDI train 1 done.\n");
3508 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3509 break;
3510 }
3511 }
3512 if (tries == 5)
3513 DRM_ERROR("FDI train 1 fail!\n");
3514
3515 /* Train 2 */
3516 reg = FDI_TX_CTL(pipe);
3517 temp = I915_READ(reg);
3518 temp &= ~FDI_LINK_TRAIN_NONE;
3519 temp |= FDI_LINK_TRAIN_PATTERN_2;
3520 I915_WRITE(reg, temp);
3521
3522 reg = FDI_RX_CTL(pipe);
3523 temp = I915_READ(reg);
3524 temp &= ~FDI_LINK_TRAIN_NONE;
3525 temp |= FDI_LINK_TRAIN_PATTERN_2;
3526 I915_WRITE(reg, temp);
3527
3528 POSTING_READ(reg);
3529 udelay(150);
3530
3531 reg = FDI_RX_IIR(pipe);
3532 for (tries = 0; tries < 5; tries++) {
3533 temp = I915_READ(reg);
3534 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3535
3536 if (temp & FDI_RX_SYMBOL_LOCK) {
3537 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3538 DRM_DEBUG_KMS("FDI train 2 done.\n");
3539 break;
3540 }
3541 }
3542 if (tries == 5)
3543 DRM_ERROR("FDI train 2 fail!\n");
3544
3545 DRM_DEBUG_KMS("FDI train done\n");
3546
3547 }
3548
3549 static const int snb_b_fdi_train_param[] = {
3550 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3551 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3552 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3553 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3554 };
3555
3556 /* The FDI link training functions for SNB/Cougarpoint. */
3557 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3558 {
3559 struct drm_device *dev = crtc->dev;
3560 struct drm_i915_private *dev_priv = dev->dev_private;
3561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3562 int pipe = intel_crtc->pipe;
3563 i915_reg_t reg;
3564 u32 temp, i, retry;
3565
3566 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3567 for train result */
3568 reg = FDI_RX_IMR(pipe);
3569 temp = I915_READ(reg);
3570 temp &= ~FDI_RX_SYMBOL_LOCK;
3571 temp &= ~FDI_RX_BIT_LOCK;
3572 I915_WRITE(reg, temp);
3573
3574 POSTING_READ(reg);
3575 udelay(150);
3576
3577 /* enable CPU FDI TX and PCH FDI RX */
3578 reg = FDI_TX_CTL(pipe);
3579 temp = I915_READ(reg);
3580 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3581 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3582 temp &= ~FDI_LINK_TRAIN_NONE;
3583 temp |= FDI_LINK_TRAIN_PATTERN_1;
3584 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3585 /* SNB-B */
3586 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3587 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3588
3589 I915_WRITE(FDI_RX_MISC(pipe),
3590 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3591
3592 reg = FDI_RX_CTL(pipe);
3593 temp = I915_READ(reg);
3594 if (HAS_PCH_CPT(dev)) {
3595 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3596 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3597 } else {
3598 temp &= ~FDI_LINK_TRAIN_NONE;
3599 temp |= FDI_LINK_TRAIN_PATTERN_1;
3600 }
3601 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3602
3603 POSTING_READ(reg);
3604 udelay(150);
3605
3606 for (i = 0; i < 4; i++) {
3607 reg = FDI_TX_CTL(pipe);
3608 temp = I915_READ(reg);
3609 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3610 temp |= snb_b_fdi_train_param[i];
3611 I915_WRITE(reg, temp);
3612
3613 POSTING_READ(reg);
3614 udelay(500);
3615
3616 for (retry = 0; retry < 5; retry++) {
3617 reg = FDI_RX_IIR(pipe);
3618 temp = I915_READ(reg);
3619 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3620 if (temp & FDI_RX_BIT_LOCK) {
3621 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3622 DRM_DEBUG_KMS("FDI train 1 done.\n");
3623 break;
3624 }
3625 udelay(50);
3626 }
3627 if (retry < 5)
3628 break;
3629 }
3630 if (i == 4)
3631 DRM_ERROR("FDI train 1 fail!\n");
3632
3633 /* Train 2 */
3634 reg = FDI_TX_CTL(pipe);
3635 temp = I915_READ(reg);
3636 temp &= ~FDI_LINK_TRAIN_NONE;
3637 temp |= FDI_LINK_TRAIN_PATTERN_2;
3638 if (IS_GEN6(dev)) {
3639 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3640 /* SNB-B */
3641 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3642 }
3643 I915_WRITE(reg, temp);
3644
3645 reg = FDI_RX_CTL(pipe);
3646 temp = I915_READ(reg);
3647 if (HAS_PCH_CPT(dev)) {
3648 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3649 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3650 } else {
3651 temp &= ~FDI_LINK_TRAIN_NONE;
3652 temp |= FDI_LINK_TRAIN_PATTERN_2;
3653 }
3654 I915_WRITE(reg, temp);
3655
3656 POSTING_READ(reg);
3657 udelay(150);
3658
3659 for (i = 0; i < 4; i++) {
3660 reg = FDI_TX_CTL(pipe);
3661 temp = I915_READ(reg);
3662 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3663 temp |= snb_b_fdi_train_param[i];
3664 I915_WRITE(reg, temp);
3665
3666 POSTING_READ(reg);
3667 udelay(500);
3668
3669 for (retry = 0; retry < 5; retry++) {
3670 reg = FDI_RX_IIR(pipe);
3671 temp = I915_READ(reg);
3672 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3673 if (temp & FDI_RX_SYMBOL_LOCK) {
3674 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3675 DRM_DEBUG_KMS("FDI train 2 done.\n");
3676 break;
3677 }
3678 udelay(50);
3679 }
3680 if (retry < 5)
3681 break;
3682 }
3683 if (i == 4)
3684 DRM_ERROR("FDI train 2 fail!\n");
3685
3686 DRM_DEBUG_KMS("FDI train done.\n");
3687 }
3688
3689 /* Manual link training for Ivy Bridge A0 parts */
3690 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3691 {
3692 struct drm_device *dev = crtc->dev;
3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3695 int pipe = intel_crtc->pipe;
3696 i915_reg_t reg;
3697 u32 temp, i, j;
3698
3699 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3700 for train result */
3701 reg = FDI_RX_IMR(pipe);
3702 temp = I915_READ(reg);
3703 temp &= ~FDI_RX_SYMBOL_LOCK;
3704 temp &= ~FDI_RX_BIT_LOCK;
3705 I915_WRITE(reg, temp);
3706
3707 POSTING_READ(reg);
3708 udelay(150);
3709
3710 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3711 I915_READ(FDI_RX_IIR(pipe)));
3712
3713 /* Try each vswing and preemphasis setting twice before moving on */
3714 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3715 /* disable first in case we need to retry */
3716 reg = FDI_TX_CTL(pipe);
3717 temp = I915_READ(reg);
3718 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3719 temp &= ~FDI_TX_ENABLE;
3720 I915_WRITE(reg, temp);
3721
3722 reg = FDI_RX_CTL(pipe);
3723 temp = I915_READ(reg);
3724 temp &= ~FDI_LINK_TRAIN_AUTO;
3725 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3726 temp &= ~FDI_RX_ENABLE;
3727 I915_WRITE(reg, temp);
3728
3729 /* enable CPU FDI TX and PCH FDI RX */
3730 reg = FDI_TX_CTL(pipe);
3731 temp = I915_READ(reg);
3732 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3733 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3734 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3736 temp |= snb_b_fdi_train_param[j/2];
3737 temp |= FDI_COMPOSITE_SYNC;
3738 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3739
3740 I915_WRITE(FDI_RX_MISC(pipe),
3741 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3742
3743 reg = FDI_RX_CTL(pipe);
3744 temp = I915_READ(reg);
3745 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3746 temp |= FDI_COMPOSITE_SYNC;
3747 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3748
3749 POSTING_READ(reg);
3750 udelay(1); /* should be 0.5us */
3751
3752 for (i = 0; i < 4; i++) {
3753 reg = FDI_RX_IIR(pipe);
3754 temp = I915_READ(reg);
3755 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3756
3757 if (temp & FDI_RX_BIT_LOCK ||
3758 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3759 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3760 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3761 i);
3762 break;
3763 }
3764 udelay(1); /* should be 0.5us */
3765 }
3766 if (i == 4) {
3767 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3768 continue;
3769 }
3770
3771 /* Train 2 */
3772 reg = FDI_TX_CTL(pipe);
3773 temp = I915_READ(reg);
3774 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3775 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3776 I915_WRITE(reg, temp);
3777
3778 reg = FDI_RX_CTL(pipe);
3779 temp = I915_READ(reg);
3780 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3781 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3782 I915_WRITE(reg, temp);
3783
3784 POSTING_READ(reg);
3785 udelay(2); /* should be 1.5us */
3786
3787 for (i = 0; i < 4; i++) {
3788 reg = FDI_RX_IIR(pipe);
3789 temp = I915_READ(reg);
3790 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3791
3792 if (temp & FDI_RX_SYMBOL_LOCK ||
3793 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3794 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3795 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3796 i);
3797 goto train_done;
3798 }
3799 udelay(2); /* should be 1.5us */
3800 }
3801 if (i == 4)
3802 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3803 }
3804
3805 train_done:
3806 DRM_DEBUG_KMS("FDI train done.\n");
3807 }
3808
3809 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3810 {
3811 struct drm_device *dev = intel_crtc->base.dev;
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813 int pipe = intel_crtc->pipe;
3814 i915_reg_t reg;
3815 u32 temp;
3816
3817 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3818 reg = FDI_RX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3821 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3822 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3823 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3824
3825 POSTING_READ(reg);
3826 udelay(200);
3827
3828 /* Switch from Rawclk to PCDclk */
3829 temp = I915_READ(reg);
3830 I915_WRITE(reg, temp | FDI_PCDCLK);
3831
3832 POSTING_READ(reg);
3833 udelay(200);
3834
3835 /* Enable CPU FDI TX PLL, always on for Ironlake */
3836 reg = FDI_TX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3839 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3840
3841 POSTING_READ(reg);
3842 udelay(100);
3843 }
3844 }
3845
3846 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3847 {
3848 struct drm_device *dev = intel_crtc->base.dev;
3849 struct drm_i915_private *dev_priv = dev->dev_private;
3850 int pipe = intel_crtc->pipe;
3851 i915_reg_t reg;
3852 u32 temp;
3853
3854 /* Switch from PCDclk to Rawclk */
3855 reg = FDI_RX_CTL(pipe);
3856 temp = I915_READ(reg);
3857 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3858
3859 /* Disable CPU FDI TX PLL */
3860 reg = FDI_TX_CTL(pipe);
3861 temp = I915_READ(reg);
3862 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3863
3864 POSTING_READ(reg);
3865 udelay(100);
3866
3867 reg = FDI_RX_CTL(pipe);
3868 temp = I915_READ(reg);
3869 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3870
3871 /* Wait for the clocks to turn off. */
3872 POSTING_READ(reg);
3873 udelay(100);
3874 }
3875
3876 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3877 {
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3881 int pipe = intel_crtc->pipe;
3882 i915_reg_t reg;
3883 u32 temp;
3884
3885 /* disable CPU FDI tx and PCH FDI rx */
3886 reg = FDI_TX_CTL(pipe);
3887 temp = I915_READ(reg);
3888 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3889 POSTING_READ(reg);
3890
3891 reg = FDI_RX_CTL(pipe);
3892 temp = I915_READ(reg);
3893 temp &= ~(0x7 << 16);
3894 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3895 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3896
3897 POSTING_READ(reg);
3898 udelay(100);
3899
3900 /* Ironlake workaround, disable clock pointer after downing FDI */
3901 if (HAS_PCH_IBX(dev))
3902 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3903
3904 /* still set train pattern 1 */
3905 reg = FDI_TX_CTL(pipe);
3906 temp = I915_READ(reg);
3907 temp &= ~FDI_LINK_TRAIN_NONE;
3908 temp |= FDI_LINK_TRAIN_PATTERN_1;
3909 I915_WRITE(reg, temp);
3910
3911 reg = FDI_RX_CTL(pipe);
3912 temp = I915_READ(reg);
3913 if (HAS_PCH_CPT(dev)) {
3914 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3915 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3916 } else {
3917 temp &= ~FDI_LINK_TRAIN_NONE;
3918 temp |= FDI_LINK_TRAIN_PATTERN_1;
3919 }
3920 /* BPC in FDI rx is consistent with that in PIPECONF */
3921 temp &= ~(0x07 << 16);
3922 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3923 I915_WRITE(reg, temp);
3924
3925 POSTING_READ(reg);
3926 udelay(100);
3927 }
3928
3929 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3930 {
3931 struct intel_crtc *crtc;
3932
3933 /* Note that we don't need to be called with mode_config.lock here
3934 * as our list of CRTC objects is static for the lifetime of the
3935 * device and so cannot disappear as we iterate. Similarly, we can
3936 * happily treat the predicates as racy, atomic checks as userspace
3937 * cannot claim and pin a new fb without at least acquring the
3938 * struct_mutex and so serialising with us.
3939 */
3940 for_each_intel_crtc(dev, crtc) {
3941 if (atomic_read(&crtc->unpin_work_count) == 0)
3942 continue;
3943
3944 if (crtc->unpin_work)
3945 intel_wait_for_vblank(dev, crtc->pipe);
3946
3947 return true;
3948 }
3949
3950 return false;
3951 }
3952
3953 static void page_flip_completed(struct intel_crtc *intel_crtc)
3954 {
3955 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3956 struct intel_unpin_work *work = intel_crtc->unpin_work;
3957
3958 /* ensure that the unpin work is consistent wrt ->pending. */
3959 smp_rmb();
3960 intel_crtc->unpin_work = NULL;
3961
3962 if (work->event)
3963 drm_send_vblank_event(intel_crtc->base.dev,
3964 intel_crtc->pipe,
3965 work->event);
3966
3967 drm_crtc_vblank_put(&intel_crtc->base);
3968
3969 wake_up_all(&dev_priv->pending_flip_queue);
3970 queue_work(dev_priv->wq, &work->work);
3971
3972 trace_i915_flip_complete(intel_crtc->plane,
3973 work->pending_flip_obj);
3974 }
3975
3976 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3977 {
3978 struct drm_device *dev = crtc->dev;
3979 struct drm_i915_private *dev_priv = dev->dev_private;
3980 long ret;
3981
3982 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3983
3984 ret = wait_event_interruptible_timeout(
3985 dev_priv->pending_flip_queue,
3986 !intel_crtc_has_pending_flip(crtc),
3987 60*HZ);
3988
3989 if (ret < 0)
3990 return ret;
3991
3992 if (ret == 0) {
3993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3994
3995 spin_lock_irq(&dev->event_lock);
3996 if (intel_crtc->unpin_work) {
3997 WARN_ONCE(1, "Removing stuck page flip\n");
3998 page_flip_completed(intel_crtc);
3999 }
4000 spin_unlock_irq(&dev->event_lock);
4001 }
4002
4003 return 0;
4004 }
4005
4006 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4007 {
4008 u32 temp;
4009
4010 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4011
4012 mutex_lock(&dev_priv->sb_lock);
4013
4014 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4015 temp |= SBI_SSCCTL_DISABLE;
4016 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4017
4018 mutex_unlock(&dev_priv->sb_lock);
4019 }
4020
4021 /* Program iCLKIP clock to the desired frequency */
4022 static void lpt_program_iclkip(struct drm_crtc *crtc)
4023 {
4024 struct drm_device *dev = crtc->dev;
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4026 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4027 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4028 u32 temp;
4029
4030 lpt_disable_iclkip(dev_priv);
4031
4032 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
4033 if (clock == 20000) {
4034 auxdiv = 1;
4035 divsel = 0x41;
4036 phaseinc = 0x20;
4037 } else {
4038 /* The iCLK virtual clock root frequency is in MHz,
4039 * but the adjusted_mode->crtc_clock in in KHz. To get the
4040 * divisors, it is necessary to divide one by another, so we
4041 * convert the virtual clock precision to KHz here for higher
4042 * precision.
4043 */
4044 u32 iclk_virtual_root_freq = 172800 * 1000;
4045 u32 iclk_pi_range = 64;
4046 u32 desired_divisor, msb_divisor_value, pi_value;
4047
4048 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
4049 msb_divisor_value = desired_divisor / iclk_pi_range;
4050 pi_value = desired_divisor % iclk_pi_range;
4051
4052 auxdiv = 0;
4053 divsel = msb_divisor_value - 2;
4054 phaseinc = pi_value;
4055 }
4056
4057 /* This should not happen with any sane values */
4058 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4059 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4060 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4061 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4062
4063 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4064 clock,
4065 auxdiv,
4066 divsel,
4067 phasedir,
4068 phaseinc);
4069
4070 mutex_lock(&dev_priv->sb_lock);
4071
4072 /* Program SSCDIVINTPHASE6 */
4073 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4074 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4075 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4076 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4077 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4078 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4079 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4080 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4081
4082 /* Program SSCAUXDIV */
4083 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4084 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4085 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4086 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4087
4088 /* Enable modulator and associated divider */
4089 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4090 temp &= ~SBI_SSCCTL_DISABLE;
4091 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4092
4093 mutex_unlock(&dev_priv->sb_lock);
4094
4095 /* Wait for initialization time */
4096 udelay(24);
4097
4098 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4099 }
4100
4101 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4102 enum pipe pch_transcoder)
4103 {
4104 struct drm_device *dev = crtc->base.dev;
4105 struct drm_i915_private *dev_priv = dev->dev_private;
4106 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4107
4108 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4109 I915_READ(HTOTAL(cpu_transcoder)));
4110 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4111 I915_READ(HBLANK(cpu_transcoder)));
4112 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4113 I915_READ(HSYNC(cpu_transcoder)));
4114
4115 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4116 I915_READ(VTOTAL(cpu_transcoder)));
4117 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4118 I915_READ(VBLANK(cpu_transcoder)));
4119 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4120 I915_READ(VSYNC(cpu_transcoder)));
4121 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4122 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4123 }
4124
4125 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4126 {
4127 struct drm_i915_private *dev_priv = dev->dev_private;
4128 uint32_t temp;
4129
4130 temp = I915_READ(SOUTH_CHICKEN1);
4131 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4132 return;
4133
4134 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4135 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4136
4137 temp &= ~FDI_BC_BIFURCATION_SELECT;
4138 if (enable)
4139 temp |= FDI_BC_BIFURCATION_SELECT;
4140
4141 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4142 I915_WRITE(SOUTH_CHICKEN1, temp);
4143 POSTING_READ(SOUTH_CHICKEN1);
4144 }
4145
4146 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4147 {
4148 struct drm_device *dev = intel_crtc->base.dev;
4149
4150 switch (intel_crtc->pipe) {
4151 case PIPE_A:
4152 break;
4153 case PIPE_B:
4154 if (intel_crtc->config->fdi_lanes > 2)
4155 cpt_set_fdi_bc_bifurcation(dev, false);
4156 else
4157 cpt_set_fdi_bc_bifurcation(dev, true);
4158
4159 break;
4160 case PIPE_C:
4161 cpt_set_fdi_bc_bifurcation(dev, true);
4162
4163 break;
4164 default:
4165 BUG();
4166 }
4167 }
4168
4169 /* Return which DP Port should be selected for Transcoder DP control */
4170 static enum port
4171 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4172 {
4173 struct drm_device *dev = crtc->dev;
4174 struct intel_encoder *encoder;
4175
4176 for_each_encoder_on_crtc(dev, crtc, encoder) {
4177 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4178 encoder->type == INTEL_OUTPUT_EDP)
4179 return enc_to_dig_port(&encoder->base)->port;
4180 }
4181
4182 return -1;
4183 }
4184
4185 /*
4186 * Enable PCH resources required for PCH ports:
4187 * - PCH PLLs
4188 * - FDI training & RX/TX
4189 * - update transcoder timings
4190 * - DP transcoding bits
4191 * - transcoder
4192 */
4193 static void ironlake_pch_enable(struct drm_crtc *crtc)
4194 {
4195 struct drm_device *dev = crtc->dev;
4196 struct drm_i915_private *dev_priv = dev->dev_private;
4197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4198 int pipe = intel_crtc->pipe;
4199 u32 temp;
4200
4201 assert_pch_transcoder_disabled(dev_priv, pipe);
4202
4203 if (IS_IVYBRIDGE(dev))
4204 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4205
4206 /* Write the TU size bits before fdi link training, so that error
4207 * detection works. */
4208 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4209 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4210
4211 /*
4212 * Sometimes spurious CPU pipe underruns happen during FDI
4213 * training, at least with VGA+HDMI cloning. Suppress them.
4214 */
4215 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4216
4217 /* For PCH output, training FDI link */
4218 dev_priv->display.fdi_link_train(crtc);
4219
4220 /* We need to program the right clock selection before writing the pixel
4221 * mutliplier into the DPLL. */
4222 if (HAS_PCH_CPT(dev)) {
4223 u32 sel;
4224
4225 temp = I915_READ(PCH_DPLL_SEL);
4226 temp |= TRANS_DPLL_ENABLE(pipe);
4227 sel = TRANS_DPLLB_SEL(pipe);
4228 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4229 temp |= sel;
4230 else
4231 temp &= ~sel;
4232 I915_WRITE(PCH_DPLL_SEL, temp);
4233 }
4234
4235 /* XXX: pch pll's can be enabled any time before we enable the PCH
4236 * transcoder, and we actually should do this to not upset any PCH
4237 * transcoder that already use the clock when we share it.
4238 *
4239 * Note that enable_shared_dpll tries to do the right thing, but
4240 * get_shared_dpll unconditionally resets the pll - we need that to have
4241 * the right LVDS enable sequence. */
4242 intel_enable_shared_dpll(intel_crtc);
4243
4244 /* set transcoder timing, panel must allow it */
4245 assert_panel_unlocked(dev_priv, pipe);
4246 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4247
4248 intel_fdi_normal_train(crtc);
4249
4250 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4251
4252 /* For PCH DP, enable TRANS_DP_CTL */
4253 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4254 const struct drm_display_mode *adjusted_mode =
4255 &intel_crtc->config->base.adjusted_mode;
4256 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4257 i915_reg_t reg = TRANS_DP_CTL(pipe);
4258 temp = I915_READ(reg);
4259 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4260 TRANS_DP_SYNC_MASK |
4261 TRANS_DP_BPC_MASK);
4262 temp |= TRANS_DP_OUTPUT_ENABLE;
4263 temp |= bpc << 9; /* same format but at 11:9 */
4264
4265 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4266 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4267 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4268 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4269
4270 switch (intel_trans_dp_port_sel(crtc)) {
4271 case PORT_B:
4272 temp |= TRANS_DP_PORT_SEL_B;
4273 break;
4274 case PORT_C:
4275 temp |= TRANS_DP_PORT_SEL_C;
4276 break;
4277 case PORT_D:
4278 temp |= TRANS_DP_PORT_SEL_D;
4279 break;
4280 default:
4281 BUG();
4282 }
4283
4284 I915_WRITE(reg, temp);
4285 }
4286
4287 ironlake_enable_pch_transcoder(dev_priv, pipe);
4288 }
4289
4290 static void lpt_pch_enable(struct drm_crtc *crtc)
4291 {
4292 struct drm_device *dev = crtc->dev;
4293 struct drm_i915_private *dev_priv = dev->dev_private;
4294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4295 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4296
4297 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4298
4299 lpt_program_iclkip(crtc);
4300
4301 /* Set transcoder timing. */
4302 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4303
4304 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4305 }
4306
4307 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4308 struct intel_crtc_state *crtc_state)
4309 {
4310 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4311 struct intel_shared_dpll *pll;
4312 struct intel_shared_dpll_config *shared_dpll;
4313 enum intel_dpll_id i;
4314 int max = dev_priv->num_shared_dpll;
4315
4316 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4317
4318 if (HAS_PCH_IBX(dev_priv->dev)) {
4319 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4320 i = (enum intel_dpll_id) crtc->pipe;
4321 pll = &dev_priv->shared_dplls[i];
4322
4323 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4324 crtc->base.base.id, pll->name);
4325
4326 WARN_ON(shared_dpll[i].crtc_mask);
4327
4328 goto found;
4329 }
4330
4331 if (IS_BROXTON(dev_priv->dev)) {
4332 /* PLL is attached to port in bxt */
4333 struct intel_encoder *encoder;
4334 struct intel_digital_port *intel_dig_port;
4335
4336 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4337 if (WARN_ON(!encoder))
4338 return NULL;
4339
4340 intel_dig_port = enc_to_dig_port(&encoder->base);
4341 /* 1:1 mapping between ports and PLLs */
4342 i = (enum intel_dpll_id)intel_dig_port->port;
4343 pll = &dev_priv->shared_dplls[i];
4344 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4345 crtc->base.base.id, pll->name);
4346 WARN_ON(shared_dpll[i].crtc_mask);
4347
4348 goto found;
4349 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4350 /* Do not consider SPLL */
4351 max = 2;
4352
4353 for (i = 0; i < max; i++) {
4354 pll = &dev_priv->shared_dplls[i];
4355
4356 /* Only want to check enabled timings first */
4357 if (shared_dpll[i].crtc_mask == 0)
4358 continue;
4359
4360 if (memcmp(&crtc_state->dpll_hw_state,
4361 &shared_dpll[i].hw_state,
4362 sizeof(crtc_state->dpll_hw_state)) == 0) {
4363 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4364 crtc->base.base.id, pll->name,
4365 shared_dpll[i].crtc_mask,
4366 pll->active);
4367 goto found;
4368 }
4369 }
4370
4371 /* Ok no matching timings, maybe there's a free one? */
4372 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4373 pll = &dev_priv->shared_dplls[i];
4374 if (shared_dpll[i].crtc_mask == 0) {
4375 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4376 crtc->base.base.id, pll->name);
4377 goto found;
4378 }
4379 }
4380
4381 return NULL;
4382
4383 found:
4384 if (shared_dpll[i].crtc_mask == 0)
4385 shared_dpll[i].hw_state =
4386 crtc_state->dpll_hw_state;
4387
4388 crtc_state->shared_dpll = i;
4389 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4390 pipe_name(crtc->pipe));
4391
4392 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4393
4394 return pll;
4395 }
4396
4397 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4398 {
4399 struct drm_i915_private *dev_priv = to_i915(state->dev);
4400 struct intel_shared_dpll_config *shared_dpll;
4401 struct intel_shared_dpll *pll;
4402 enum intel_dpll_id i;
4403
4404 if (!to_intel_atomic_state(state)->dpll_set)
4405 return;
4406
4407 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4408 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4409 pll = &dev_priv->shared_dplls[i];
4410 pll->config = shared_dpll[i];
4411 }
4412 }
4413
4414 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4415 {
4416 struct drm_i915_private *dev_priv = dev->dev_private;
4417 i915_reg_t dslreg = PIPEDSL(pipe);
4418 u32 temp;
4419
4420 temp = I915_READ(dslreg);
4421 udelay(500);
4422 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4423 if (wait_for(I915_READ(dslreg) != temp, 5))
4424 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4425 }
4426 }
4427
4428 static int
4429 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4430 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4431 int src_w, int src_h, int dst_w, int dst_h)
4432 {
4433 struct intel_crtc_scaler_state *scaler_state =
4434 &crtc_state->scaler_state;
4435 struct intel_crtc *intel_crtc =
4436 to_intel_crtc(crtc_state->base.crtc);
4437 int need_scaling;
4438
4439 need_scaling = intel_rotation_90_or_270(rotation) ?
4440 (src_h != dst_w || src_w != dst_h):
4441 (src_w != dst_w || src_h != dst_h);
4442
4443 /*
4444 * if plane is being disabled or scaler is no more required or force detach
4445 * - free scaler binded to this plane/crtc
4446 * - in order to do this, update crtc->scaler_usage
4447 *
4448 * Here scaler state in crtc_state is set free so that
4449 * scaler can be assigned to other user. Actual register
4450 * update to free the scaler is done in plane/panel-fit programming.
4451 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4452 */
4453 if (force_detach || !need_scaling) {
4454 if (*scaler_id >= 0) {
4455 scaler_state->scaler_users &= ~(1 << scaler_user);
4456 scaler_state->scalers[*scaler_id].in_use = 0;
4457
4458 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4459 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4460 intel_crtc->pipe, scaler_user, *scaler_id,
4461 scaler_state->scaler_users);
4462 *scaler_id = -1;
4463 }
4464 return 0;
4465 }
4466
4467 /* range checks */
4468 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4469 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4470
4471 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4472 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4473 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4474 "size is out of scaler range\n",
4475 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4476 return -EINVAL;
4477 }
4478
4479 /* mark this plane as a scaler user in crtc_state */
4480 scaler_state->scaler_users |= (1 << scaler_user);
4481 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4482 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4483 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4484 scaler_state->scaler_users);
4485
4486 return 0;
4487 }
4488
4489 /**
4490 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4491 *
4492 * @state: crtc's scaler state
4493 *
4494 * Return
4495 * 0 - scaler_usage updated successfully
4496 * error - requested scaling cannot be supported or other error condition
4497 */
4498 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4499 {
4500 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4501 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4502
4503 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4504 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4505
4506 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4507 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4508 state->pipe_src_w, state->pipe_src_h,
4509 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4510 }
4511
4512 /**
4513 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4514 *
4515 * @state: crtc's scaler state
4516 * @plane_state: atomic plane state to update
4517 *
4518 * Return
4519 * 0 - scaler_usage updated successfully
4520 * error - requested scaling cannot be supported or other error condition
4521 */
4522 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4523 struct intel_plane_state *plane_state)
4524 {
4525
4526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4527 struct intel_plane *intel_plane =
4528 to_intel_plane(plane_state->base.plane);
4529 struct drm_framebuffer *fb = plane_state->base.fb;
4530 int ret;
4531
4532 bool force_detach = !fb || !plane_state->visible;
4533
4534 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4535 intel_plane->base.base.id, intel_crtc->pipe,
4536 drm_plane_index(&intel_plane->base));
4537
4538 ret = skl_update_scaler(crtc_state, force_detach,
4539 drm_plane_index(&intel_plane->base),
4540 &plane_state->scaler_id,
4541 plane_state->base.rotation,
4542 drm_rect_width(&plane_state->src) >> 16,
4543 drm_rect_height(&plane_state->src) >> 16,
4544 drm_rect_width(&plane_state->dst),
4545 drm_rect_height(&plane_state->dst));
4546
4547 if (ret || plane_state->scaler_id < 0)
4548 return ret;
4549
4550 /* check colorkey */
4551 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4552 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4553 intel_plane->base.base.id);
4554 return -EINVAL;
4555 }
4556
4557 /* Check src format */
4558 switch (fb->pixel_format) {
4559 case DRM_FORMAT_RGB565:
4560 case DRM_FORMAT_XBGR8888:
4561 case DRM_FORMAT_XRGB8888:
4562 case DRM_FORMAT_ABGR8888:
4563 case DRM_FORMAT_ARGB8888:
4564 case DRM_FORMAT_XRGB2101010:
4565 case DRM_FORMAT_XBGR2101010:
4566 case DRM_FORMAT_YUYV:
4567 case DRM_FORMAT_YVYU:
4568 case DRM_FORMAT_UYVY:
4569 case DRM_FORMAT_VYUY:
4570 break;
4571 default:
4572 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4573 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4574 return -EINVAL;
4575 }
4576
4577 return 0;
4578 }
4579
4580 static void skylake_scaler_disable(struct intel_crtc *crtc)
4581 {
4582 int i;
4583
4584 for (i = 0; i < crtc->num_scalers; i++)
4585 skl_detach_scaler(crtc, i);
4586 }
4587
4588 static void skylake_pfit_enable(struct intel_crtc *crtc)
4589 {
4590 struct drm_device *dev = crtc->base.dev;
4591 struct drm_i915_private *dev_priv = dev->dev_private;
4592 int pipe = crtc->pipe;
4593 struct intel_crtc_scaler_state *scaler_state =
4594 &crtc->config->scaler_state;
4595
4596 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4597
4598 if (crtc->config->pch_pfit.enabled) {
4599 int id;
4600
4601 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4602 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4603 return;
4604 }
4605
4606 id = scaler_state->scaler_id;
4607 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4608 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4609 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4610 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4611
4612 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4613 }
4614 }
4615
4616 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4617 {
4618 struct drm_device *dev = crtc->base.dev;
4619 struct drm_i915_private *dev_priv = dev->dev_private;
4620 int pipe = crtc->pipe;
4621
4622 if (crtc->config->pch_pfit.enabled) {
4623 /* Force use of hard-coded filter coefficients
4624 * as some pre-programmed values are broken,
4625 * e.g. x201.
4626 */
4627 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4628 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4629 PF_PIPE_SEL_IVB(pipe));
4630 else
4631 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4632 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4633 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4634 }
4635 }
4636
4637 void hsw_enable_ips(struct intel_crtc *crtc)
4638 {
4639 struct drm_device *dev = crtc->base.dev;
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4641
4642 if (!crtc->config->ips_enabled)
4643 return;
4644
4645 /* We can only enable IPS after we enable a plane and wait for a vblank */
4646 intel_wait_for_vblank(dev, crtc->pipe);
4647
4648 assert_plane_enabled(dev_priv, crtc->plane);
4649 if (IS_BROADWELL(dev)) {
4650 mutex_lock(&dev_priv->rps.hw_lock);
4651 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4652 mutex_unlock(&dev_priv->rps.hw_lock);
4653 /* Quoting Art Runyan: "its not safe to expect any particular
4654 * value in IPS_CTL bit 31 after enabling IPS through the
4655 * mailbox." Moreover, the mailbox may return a bogus state,
4656 * so we need to just enable it and continue on.
4657 */
4658 } else {
4659 I915_WRITE(IPS_CTL, IPS_ENABLE);
4660 /* The bit only becomes 1 in the next vblank, so this wait here
4661 * is essentially intel_wait_for_vblank. If we don't have this
4662 * and don't wait for vblanks until the end of crtc_enable, then
4663 * the HW state readout code will complain that the expected
4664 * IPS_CTL value is not the one we read. */
4665 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4666 DRM_ERROR("Timed out waiting for IPS enable\n");
4667 }
4668 }
4669
4670 void hsw_disable_ips(struct intel_crtc *crtc)
4671 {
4672 struct drm_device *dev = crtc->base.dev;
4673 struct drm_i915_private *dev_priv = dev->dev_private;
4674
4675 if (!crtc->config->ips_enabled)
4676 return;
4677
4678 assert_plane_enabled(dev_priv, crtc->plane);
4679 if (IS_BROADWELL(dev)) {
4680 mutex_lock(&dev_priv->rps.hw_lock);
4681 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4682 mutex_unlock(&dev_priv->rps.hw_lock);
4683 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4684 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4685 DRM_ERROR("Timed out waiting for IPS disable\n");
4686 } else {
4687 I915_WRITE(IPS_CTL, 0);
4688 POSTING_READ(IPS_CTL);
4689 }
4690
4691 /* We need to wait for a vblank before we can disable the plane. */
4692 intel_wait_for_vblank(dev, crtc->pipe);
4693 }
4694
4695 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4696 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4697 {
4698 struct drm_device *dev = crtc->dev;
4699 struct drm_i915_private *dev_priv = dev->dev_private;
4700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4701 enum pipe pipe = intel_crtc->pipe;
4702 int i;
4703 bool reenable_ips = false;
4704
4705 /* The clocks have to be on to load the palette. */
4706 if (!crtc->state->active)
4707 return;
4708
4709 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4710 if (intel_crtc->config->has_dsi_encoder)
4711 assert_dsi_pll_enabled(dev_priv);
4712 else
4713 assert_pll_enabled(dev_priv, pipe);
4714 }
4715
4716 /* Workaround : Do not read or write the pipe palette/gamma data while
4717 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4718 */
4719 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4720 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4721 GAMMA_MODE_MODE_SPLIT)) {
4722 hsw_disable_ips(intel_crtc);
4723 reenable_ips = true;
4724 }
4725
4726 for (i = 0; i < 256; i++) {
4727 i915_reg_t palreg;
4728
4729 if (HAS_GMCH_DISPLAY(dev))
4730 palreg = PALETTE(pipe, i);
4731 else
4732 palreg = LGC_PALETTE(pipe, i);
4733
4734 I915_WRITE(palreg,
4735 (intel_crtc->lut_r[i] << 16) |
4736 (intel_crtc->lut_g[i] << 8) |
4737 intel_crtc->lut_b[i]);
4738 }
4739
4740 if (reenable_ips)
4741 hsw_enable_ips(intel_crtc);
4742 }
4743
4744 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4745 {
4746 if (intel_crtc->overlay) {
4747 struct drm_device *dev = intel_crtc->base.dev;
4748 struct drm_i915_private *dev_priv = dev->dev_private;
4749
4750 mutex_lock(&dev->struct_mutex);
4751 dev_priv->mm.interruptible = false;
4752 (void) intel_overlay_switch_off(intel_crtc->overlay);
4753 dev_priv->mm.interruptible = true;
4754 mutex_unlock(&dev->struct_mutex);
4755 }
4756
4757 /* Let userspace switch the overlay on again. In most cases userspace
4758 * has to recompute where to put it anyway.
4759 */
4760 }
4761
4762 /**
4763 * intel_post_enable_primary - Perform operations after enabling primary plane
4764 * @crtc: the CRTC whose primary plane was just enabled
4765 *
4766 * Performs potentially sleeping operations that must be done after the primary
4767 * plane is enabled, such as updating FBC and IPS. Note that this may be
4768 * called due to an explicit primary plane update, or due to an implicit
4769 * re-enable that is caused when a sprite plane is updated to no longer
4770 * completely hide the primary plane.
4771 */
4772 static void
4773 intel_post_enable_primary(struct drm_crtc *crtc)
4774 {
4775 struct drm_device *dev = crtc->dev;
4776 struct drm_i915_private *dev_priv = dev->dev_private;
4777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4778 int pipe = intel_crtc->pipe;
4779
4780 /*
4781 * FIXME IPS should be fine as long as one plane is
4782 * enabled, but in practice it seems to have problems
4783 * when going from primary only to sprite only and vice
4784 * versa.
4785 */
4786 hsw_enable_ips(intel_crtc);
4787
4788 /*
4789 * Gen2 reports pipe underruns whenever all planes are disabled.
4790 * So don't enable underrun reporting before at least some planes
4791 * are enabled.
4792 * FIXME: Need to fix the logic to work when we turn off all planes
4793 * but leave the pipe running.
4794 */
4795 if (IS_GEN2(dev))
4796 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4797
4798 /* Underruns don't always raise interrupts, so check manually. */
4799 intel_check_cpu_fifo_underruns(dev_priv);
4800 intel_check_pch_fifo_underruns(dev_priv);
4801 }
4802
4803 /**
4804 * intel_pre_disable_primary - Perform operations before disabling primary plane
4805 * @crtc: the CRTC whose primary plane is to be disabled
4806 *
4807 * Performs potentially sleeping operations that must be done before the
4808 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4809 * be called due to an explicit primary plane update, or due to an implicit
4810 * disable that is caused when a sprite plane completely hides the primary
4811 * plane.
4812 */
4813 static void
4814 intel_pre_disable_primary(struct drm_crtc *crtc)
4815 {
4816 struct drm_device *dev = crtc->dev;
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4819 int pipe = intel_crtc->pipe;
4820
4821 /*
4822 * Gen2 reports pipe underruns whenever all planes are disabled.
4823 * So diasble underrun reporting before all the planes get disabled.
4824 * FIXME: Need to fix the logic to work when we turn off all planes
4825 * but leave the pipe running.
4826 */
4827 if (IS_GEN2(dev))
4828 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4829
4830 /*
4831 * Vblank time updates from the shadow to live plane control register
4832 * are blocked if the memory self-refresh mode is active at that
4833 * moment. So to make sure the plane gets truly disabled, disable
4834 * first the self-refresh mode. The self-refresh enable bit in turn
4835 * will be checked/applied by the HW only at the next frame start
4836 * event which is after the vblank start event, so we need to have a
4837 * wait-for-vblank between disabling the plane and the pipe.
4838 */
4839 if (HAS_GMCH_DISPLAY(dev)) {
4840 intel_set_memory_cxsr(dev_priv, false);
4841 dev_priv->wm.vlv.cxsr = false;
4842 intel_wait_for_vblank(dev, pipe);
4843 }
4844
4845 /*
4846 * FIXME IPS should be fine as long as one plane is
4847 * enabled, but in practice it seems to have problems
4848 * when going from primary only to sprite only and vice
4849 * versa.
4850 */
4851 hsw_disable_ips(intel_crtc);
4852 }
4853
4854 static void intel_post_plane_update(struct intel_crtc *crtc)
4855 {
4856 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4857 struct intel_crtc_state *pipe_config =
4858 to_intel_crtc_state(crtc->base.state);
4859 struct drm_device *dev = crtc->base.dev;
4860
4861 intel_frontbuffer_flip(dev, atomic->fb_bits);
4862
4863 crtc->wm.cxsr_allowed = true;
4864
4865 if (pipe_config->wm_changed && pipe_config->base.active)
4866 intel_update_watermarks(&crtc->base);
4867
4868 if (atomic->update_fbc)
4869 intel_fbc_post_update(crtc);
4870
4871 if (atomic->post_enable_primary)
4872 intel_post_enable_primary(&crtc->base);
4873
4874 memset(atomic, 0, sizeof(*atomic));
4875 }
4876
4877 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4878 {
4879 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4880 struct drm_device *dev = crtc->base.dev;
4881 struct drm_i915_private *dev_priv = dev->dev_private;
4882 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4883 struct intel_crtc_state *pipe_config =
4884 to_intel_crtc_state(crtc->base.state);
4885 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4886 struct drm_plane *primary = crtc->base.primary;
4887 struct drm_plane_state *old_pri_state =
4888 drm_atomic_get_existing_plane_state(old_state, primary);
4889 bool modeset = needs_modeset(&pipe_config->base);
4890
4891 if (atomic->update_fbc)
4892 intel_fbc_pre_update(crtc);
4893
4894 if (old_pri_state) {
4895 struct intel_plane_state *primary_state =
4896 to_intel_plane_state(primary->state);
4897 struct intel_plane_state *old_primary_state =
4898 to_intel_plane_state(old_pri_state);
4899
4900 if (old_primary_state->visible &&
4901 (modeset || !primary_state->visible))
4902 intel_pre_disable_primary(&crtc->base);
4903 }
4904
4905 if (pipe_config->disable_cxsr) {
4906 crtc->wm.cxsr_allowed = false;
4907
4908 if (old_crtc_state->base.active)
4909 intel_set_memory_cxsr(dev_priv, false);
4910 }
4911
4912 /*
4913 * IVB workaround: must disable low power watermarks for at least
4914 * one frame before enabling scaling. LP watermarks can be re-enabled
4915 * when scaling is disabled.
4916 *
4917 * WaCxSRDisabledForSpriteScaling:ivb
4918 */
4919 if (pipe_config->disable_lp_wm) {
4920 ilk_disable_lp_wm(dev);
4921 intel_wait_for_vblank(dev, crtc->pipe);
4922 }
4923
4924 /*
4925 * If we're doing a modeset, we're done. No need to do any pre-vblank
4926 * watermark programming here.
4927 */
4928 if (needs_modeset(&pipe_config->base))
4929 return;
4930
4931 /*
4932 * For platforms that support atomic watermarks, program the
4933 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4934 * will be the intermediate values that are safe for both pre- and
4935 * post- vblank; when vblank happens, the 'active' values will be set
4936 * to the final 'target' values and we'll do this again to get the
4937 * optimal watermarks. For gen9+ platforms, the values we program here
4938 * will be the final target values which will get automatically latched
4939 * at vblank time; no further programming will be necessary.
4940 *
4941 * If a platform hasn't been transitioned to atomic watermarks yet,
4942 * we'll continue to update watermarks the old way, if flags tell
4943 * us to.
4944 */
4945 if (dev_priv->display.initial_watermarks != NULL)
4946 dev_priv->display.initial_watermarks(pipe_config);
4947 else if (pipe_config->wm_changed)
4948 intel_update_watermarks(&crtc->base);
4949 }
4950
4951 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4952 {
4953 struct drm_device *dev = crtc->dev;
4954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4955 struct drm_plane *p;
4956 int pipe = intel_crtc->pipe;
4957
4958 intel_crtc_dpms_overlay_disable(intel_crtc);
4959
4960 drm_for_each_plane_mask(p, dev, plane_mask)
4961 to_intel_plane(p)->disable_plane(p, crtc);
4962
4963 /*
4964 * FIXME: Once we grow proper nuclear flip support out of this we need
4965 * to compute the mask of flip planes precisely. For the time being
4966 * consider this a flip to a NULL plane.
4967 */
4968 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4969 }
4970
4971 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4972 {
4973 struct drm_device *dev = crtc->dev;
4974 struct drm_i915_private *dev_priv = dev->dev_private;
4975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4976 struct intel_encoder *encoder;
4977 int pipe = intel_crtc->pipe;
4978
4979 if (WARN_ON(intel_crtc->active))
4980 return;
4981
4982 if (intel_crtc->config->has_pch_encoder)
4983 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4984
4985 if (intel_crtc->config->has_pch_encoder)
4986 intel_prepare_shared_dpll(intel_crtc);
4987
4988 if (intel_crtc->config->has_dp_encoder)
4989 intel_dp_set_m_n(intel_crtc, M1_N1);
4990
4991 intel_set_pipe_timings(intel_crtc);
4992
4993 if (intel_crtc->config->has_pch_encoder) {
4994 intel_cpu_transcoder_set_m_n(intel_crtc,
4995 &intel_crtc->config->fdi_m_n, NULL);
4996 }
4997
4998 ironlake_set_pipeconf(crtc);
4999
5000 intel_crtc->active = true;
5001
5002 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5003
5004 for_each_encoder_on_crtc(dev, crtc, encoder)
5005 if (encoder->pre_enable)
5006 encoder->pre_enable(encoder);
5007
5008 if (intel_crtc->config->has_pch_encoder) {
5009 /* Note: FDI PLL enabling _must_ be done before we enable the
5010 * cpu pipes, hence this is separate from all the other fdi/pch
5011 * enabling. */
5012 ironlake_fdi_pll_enable(intel_crtc);
5013 } else {
5014 assert_fdi_tx_disabled(dev_priv, pipe);
5015 assert_fdi_rx_disabled(dev_priv, pipe);
5016 }
5017
5018 ironlake_pfit_enable(intel_crtc);
5019
5020 /*
5021 * On ILK+ LUT must be loaded before the pipe is running but with
5022 * clocks enabled
5023 */
5024 intel_crtc_load_lut(crtc);
5025
5026 if (dev_priv->display.initial_watermarks != NULL)
5027 dev_priv->display.initial_watermarks(intel_crtc->config);
5028 intel_enable_pipe(intel_crtc);
5029
5030 if (intel_crtc->config->has_pch_encoder)
5031 ironlake_pch_enable(crtc);
5032
5033 assert_vblank_disabled(crtc);
5034 drm_crtc_vblank_on(crtc);
5035
5036 for_each_encoder_on_crtc(dev, crtc, encoder)
5037 encoder->enable(encoder);
5038
5039 if (HAS_PCH_CPT(dev))
5040 cpt_verify_modeset(dev, intel_crtc->pipe);
5041
5042 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5043 if (intel_crtc->config->has_pch_encoder)
5044 intel_wait_for_vblank(dev, pipe);
5045 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5046 }
5047
5048 /* IPS only exists on ULT machines and is tied to pipe A. */
5049 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5050 {
5051 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5052 }
5053
5054 static void haswell_crtc_enable(struct drm_crtc *crtc)
5055 {
5056 struct drm_device *dev = crtc->dev;
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5059 struct intel_encoder *encoder;
5060 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5061 struct intel_crtc_state *pipe_config =
5062 to_intel_crtc_state(crtc->state);
5063
5064 if (WARN_ON(intel_crtc->active))
5065 return;
5066
5067 if (intel_crtc->config->has_pch_encoder)
5068 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5069 false);
5070
5071 if (intel_crtc_to_shared_dpll(intel_crtc))
5072 intel_enable_shared_dpll(intel_crtc);
5073
5074 if (intel_crtc->config->has_dp_encoder)
5075 intel_dp_set_m_n(intel_crtc, M1_N1);
5076
5077 intel_set_pipe_timings(intel_crtc);
5078
5079 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5080 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5081 intel_crtc->config->pixel_multiplier - 1);
5082 }
5083
5084 if (intel_crtc->config->has_pch_encoder) {
5085 intel_cpu_transcoder_set_m_n(intel_crtc,
5086 &intel_crtc->config->fdi_m_n, NULL);
5087 }
5088
5089 haswell_set_pipeconf(crtc);
5090
5091 intel_set_pipe_csc(crtc);
5092
5093 intel_crtc->active = true;
5094
5095 if (intel_crtc->config->has_pch_encoder)
5096 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5097 else
5098 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5099
5100 for_each_encoder_on_crtc(dev, crtc, encoder) {
5101 if (encoder->pre_enable)
5102 encoder->pre_enable(encoder);
5103 }
5104
5105 if (intel_crtc->config->has_pch_encoder)
5106 dev_priv->display.fdi_link_train(crtc);
5107
5108 if (!intel_crtc->config->has_dsi_encoder)
5109 intel_ddi_enable_pipe_clock(intel_crtc);
5110
5111 if (INTEL_INFO(dev)->gen >= 9)
5112 skylake_pfit_enable(intel_crtc);
5113 else
5114 ironlake_pfit_enable(intel_crtc);
5115
5116 /*
5117 * On ILK+ LUT must be loaded before the pipe is running but with
5118 * clocks enabled
5119 */
5120 intel_crtc_load_lut(crtc);
5121
5122 intel_ddi_set_pipe_settings(crtc);
5123 if (!intel_crtc->config->has_dsi_encoder)
5124 intel_ddi_enable_transcoder_func(crtc);
5125
5126 if (dev_priv->display.initial_watermarks != NULL)
5127 dev_priv->display.initial_watermarks(pipe_config);
5128 else
5129 intel_update_watermarks(crtc);
5130 intel_enable_pipe(intel_crtc);
5131
5132 if (intel_crtc->config->has_pch_encoder)
5133 lpt_pch_enable(crtc);
5134
5135 if (intel_crtc->config->dp_encoder_is_mst)
5136 intel_ddi_set_vc_payload_alloc(crtc, true);
5137
5138 assert_vblank_disabled(crtc);
5139 drm_crtc_vblank_on(crtc);
5140
5141 for_each_encoder_on_crtc(dev, crtc, encoder) {
5142 encoder->enable(encoder);
5143 intel_opregion_notify_encoder(encoder, true);
5144 }
5145
5146 if (intel_crtc->config->has_pch_encoder) {
5147 intel_wait_for_vblank(dev, pipe);
5148 intel_wait_for_vblank(dev, pipe);
5149 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5150 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5151 true);
5152 }
5153
5154 /* If we change the relative order between pipe/planes enabling, we need
5155 * to change the workaround. */
5156 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5157 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5158 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5159 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5160 }
5161 }
5162
5163 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5164 {
5165 struct drm_device *dev = crtc->base.dev;
5166 struct drm_i915_private *dev_priv = dev->dev_private;
5167 int pipe = crtc->pipe;
5168
5169 /* To avoid upsetting the power well on haswell only disable the pfit if
5170 * it's in use. The hw state code will make sure we get this right. */
5171 if (force || crtc->config->pch_pfit.enabled) {
5172 I915_WRITE(PF_CTL(pipe), 0);
5173 I915_WRITE(PF_WIN_POS(pipe), 0);
5174 I915_WRITE(PF_WIN_SZ(pipe), 0);
5175 }
5176 }
5177
5178 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5179 {
5180 struct drm_device *dev = crtc->dev;
5181 struct drm_i915_private *dev_priv = dev->dev_private;
5182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5183 struct intel_encoder *encoder;
5184 int pipe = intel_crtc->pipe;
5185
5186 if (intel_crtc->config->has_pch_encoder)
5187 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5188
5189 for_each_encoder_on_crtc(dev, crtc, encoder)
5190 encoder->disable(encoder);
5191
5192 drm_crtc_vblank_off(crtc);
5193 assert_vblank_disabled(crtc);
5194
5195 /*
5196 * Sometimes spurious CPU pipe underruns happen when the
5197 * pipe is already disabled, but FDI RX/TX is still enabled.
5198 * Happens at least with VGA+HDMI cloning. Suppress them.
5199 */
5200 if (intel_crtc->config->has_pch_encoder)
5201 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5202
5203 intel_disable_pipe(intel_crtc);
5204
5205 ironlake_pfit_disable(intel_crtc, false);
5206
5207 if (intel_crtc->config->has_pch_encoder) {
5208 ironlake_fdi_disable(crtc);
5209 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5210 }
5211
5212 for_each_encoder_on_crtc(dev, crtc, encoder)
5213 if (encoder->post_disable)
5214 encoder->post_disable(encoder);
5215
5216 if (intel_crtc->config->has_pch_encoder) {
5217 ironlake_disable_pch_transcoder(dev_priv, pipe);
5218
5219 if (HAS_PCH_CPT(dev)) {
5220 i915_reg_t reg;
5221 u32 temp;
5222
5223 /* disable TRANS_DP_CTL */
5224 reg = TRANS_DP_CTL(pipe);
5225 temp = I915_READ(reg);
5226 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5227 TRANS_DP_PORT_SEL_MASK);
5228 temp |= TRANS_DP_PORT_SEL_NONE;
5229 I915_WRITE(reg, temp);
5230
5231 /* disable DPLL_SEL */
5232 temp = I915_READ(PCH_DPLL_SEL);
5233 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5234 I915_WRITE(PCH_DPLL_SEL, temp);
5235 }
5236
5237 ironlake_fdi_pll_disable(intel_crtc);
5238 }
5239
5240 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5241 }
5242
5243 static void haswell_crtc_disable(struct drm_crtc *crtc)
5244 {
5245 struct drm_device *dev = crtc->dev;
5246 struct drm_i915_private *dev_priv = dev->dev_private;
5247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5248 struct intel_encoder *encoder;
5249 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5250
5251 if (intel_crtc->config->has_pch_encoder)
5252 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5253 false);
5254
5255 for_each_encoder_on_crtc(dev, crtc, encoder) {
5256 intel_opregion_notify_encoder(encoder, false);
5257 encoder->disable(encoder);
5258 }
5259
5260 drm_crtc_vblank_off(crtc);
5261 assert_vblank_disabled(crtc);
5262
5263 intel_disable_pipe(intel_crtc);
5264
5265 if (intel_crtc->config->dp_encoder_is_mst)
5266 intel_ddi_set_vc_payload_alloc(crtc, false);
5267
5268 if (!intel_crtc->config->has_dsi_encoder)
5269 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5270
5271 if (INTEL_INFO(dev)->gen >= 9)
5272 skylake_scaler_disable(intel_crtc);
5273 else
5274 ironlake_pfit_disable(intel_crtc, false);
5275
5276 if (!intel_crtc->config->has_dsi_encoder)
5277 intel_ddi_disable_pipe_clock(intel_crtc);
5278
5279 for_each_encoder_on_crtc(dev, crtc, encoder)
5280 if (encoder->post_disable)
5281 encoder->post_disable(encoder);
5282
5283 if (intel_crtc->config->has_pch_encoder) {
5284 lpt_disable_pch_transcoder(dev_priv);
5285 lpt_disable_iclkip(dev_priv);
5286 intel_ddi_fdi_disable(crtc);
5287
5288 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5289 true);
5290 }
5291 }
5292
5293 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5294 {
5295 struct drm_device *dev = crtc->base.dev;
5296 struct drm_i915_private *dev_priv = dev->dev_private;
5297 struct intel_crtc_state *pipe_config = crtc->config;
5298
5299 if (!pipe_config->gmch_pfit.control)
5300 return;
5301
5302 /*
5303 * The panel fitter should only be adjusted whilst the pipe is disabled,
5304 * according to register description and PRM.
5305 */
5306 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5307 assert_pipe_disabled(dev_priv, crtc->pipe);
5308
5309 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5310 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5311
5312 /* Border color in case we don't scale up to the full screen. Black by
5313 * default, change to something else for debugging. */
5314 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5315 }
5316
5317 static enum intel_display_power_domain port_to_power_domain(enum port port)
5318 {
5319 switch (port) {
5320 case PORT_A:
5321 return POWER_DOMAIN_PORT_DDI_A_LANES;
5322 case PORT_B:
5323 return POWER_DOMAIN_PORT_DDI_B_LANES;
5324 case PORT_C:
5325 return POWER_DOMAIN_PORT_DDI_C_LANES;
5326 case PORT_D:
5327 return POWER_DOMAIN_PORT_DDI_D_LANES;
5328 case PORT_E:
5329 return POWER_DOMAIN_PORT_DDI_E_LANES;
5330 default:
5331 MISSING_CASE(port);
5332 return POWER_DOMAIN_PORT_OTHER;
5333 }
5334 }
5335
5336 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5337 {
5338 switch (port) {
5339 case PORT_A:
5340 return POWER_DOMAIN_AUX_A;
5341 case PORT_B:
5342 return POWER_DOMAIN_AUX_B;
5343 case PORT_C:
5344 return POWER_DOMAIN_AUX_C;
5345 case PORT_D:
5346 return POWER_DOMAIN_AUX_D;
5347 case PORT_E:
5348 /* FIXME: Check VBT for actual wiring of PORT E */
5349 return POWER_DOMAIN_AUX_D;
5350 default:
5351 MISSING_CASE(port);
5352 return POWER_DOMAIN_AUX_A;
5353 }
5354 }
5355
5356 enum intel_display_power_domain
5357 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5358 {
5359 struct drm_device *dev = intel_encoder->base.dev;
5360 struct intel_digital_port *intel_dig_port;
5361
5362 switch (intel_encoder->type) {
5363 case INTEL_OUTPUT_UNKNOWN:
5364 /* Only DDI platforms should ever use this output type */
5365 WARN_ON_ONCE(!HAS_DDI(dev));
5366 case INTEL_OUTPUT_DISPLAYPORT:
5367 case INTEL_OUTPUT_HDMI:
5368 case INTEL_OUTPUT_EDP:
5369 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5370 return port_to_power_domain(intel_dig_port->port);
5371 case INTEL_OUTPUT_DP_MST:
5372 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5373 return port_to_power_domain(intel_dig_port->port);
5374 case INTEL_OUTPUT_ANALOG:
5375 return POWER_DOMAIN_PORT_CRT;
5376 case INTEL_OUTPUT_DSI:
5377 return POWER_DOMAIN_PORT_DSI;
5378 default:
5379 return POWER_DOMAIN_PORT_OTHER;
5380 }
5381 }
5382
5383 enum intel_display_power_domain
5384 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5385 {
5386 struct drm_device *dev = intel_encoder->base.dev;
5387 struct intel_digital_port *intel_dig_port;
5388
5389 switch (intel_encoder->type) {
5390 case INTEL_OUTPUT_UNKNOWN:
5391 case INTEL_OUTPUT_HDMI:
5392 /*
5393 * Only DDI platforms should ever use these output types.
5394 * We can get here after the HDMI detect code has already set
5395 * the type of the shared encoder. Since we can't be sure
5396 * what's the status of the given connectors, play safe and
5397 * run the DP detection too.
5398 */
5399 WARN_ON_ONCE(!HAS_DDI(dev));
5400 case INTEL_OUTPUT_DISPLAYPORT:
5401 case INTEL_OUTPUT_EDP:
5402 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5403 return port_to_aux_power_domain(intel_dig_port->port);
5404 case INTEL_OUTPUT_DP_MST:
5405 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5406 return port_to_aux_power_domain(intel_dig_port->port);
5407 default:
5408 MISSING_CASE(intel_encoder->type);
5409 return POWER_DOMAIN_AUX_A;
5410 }
5411 }
5412
5413 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5414 struct intel_crtc_state *crtc_state)
5415 {
5416 struct drm_device *dev = crtc->dev;
5417 struct drm_encoder *encoder;
5418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5419 enum pipe pipe = intel_crtc->pipe;
5420 unsigned long mask;
5421 enum transcoder transcoder = crtc_state->cpu_transcoder;
5422
5423 if (!crtc_state->base.active)
5424 return 0;
5425
5426 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5427 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5428 if (crtc_state->pch_pfit.enabled ||
5429 crtc_state->pch_pfit.force_thru)
5430 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5431
5432 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5433 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5434
5435 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5436 }
5437
5438 return mask;
5439 }
5440
5441 static unsigned long
5442 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5443 struct intel_crtc_state *crtc_state)
5444 {
5445 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5447 enum intel_display_power_domain domain;
5448 unsigned long domains, new_domains, old_domains;
5449
5450 old_domains = intel_crtc->enabled_power_domains;
5451 intel_crtc->enabled_power_domains = new_domains =
5452 get_crtc_power_domains(crtc, crtc_state);
5453
5454 domains = new_domains & ~old_domains;
5455
5456 for_each_power_domain(domain, domains)
5457 intel_display_power_get(dev_priv, domain);
5458
5459 return old_domains & ~new_domains;
5460 }
5461
5462 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5463 unsigned long domains)
5464 {
5465 enum intel_display_power_domain domain;
5466
5467 for_each_power_domain(domain, domains)
5468 intel_display_power_put(dev_priv, domain);
5469 }
5470
5471 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5472 {
5473 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5474
5475 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5476 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5477 return max_cdclk_freq;
5478 else if (IS_CHERRYVIEW(dev_priv))
5479 return max_cdclk_freq*95/100;
5480 else if (INTEL_INFO(dev_priv)->gen < 4)
5481 return 2*max_cdclk_freq*90/100;
5482 else
5483 return max_cdclk_freq*90/100;
5484 }
5485
5486 static void intel_update_max_cdclk(struct drm_device *dev)
5487 {
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489
5490 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5491 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5492
5493 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5494 dev_priv->max_cdclk_freq = 675000;
5495 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5496 dev_priv->max_cdclk_freq = 540000;
5497 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5498 dev_priv->max_cdclk_freq = 450000;
5499 else
5500 dev_priv->max_cdclk_freq = 337500;
5501 } else if (IS_BROADWELL(dev)) {
5502 /*
5503 * FIXME with extra cooling we can allow
5504 * 540 MHz for ULX and 675 Mhz for ULT.
5505 * How can we know if extra cooling is
5506 * available? PCI ID, VTB, something else?
5507 */
5508 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5509 dev_priv->max_cdclk_freq = 450000;
5510 else if (IS_BDW_ULX(dev))
5511 dev_priv->max_cdclk_freq = 450000;
5512 else if (IS_BDW_ULT(dev))
5513 dev_priv->max_cdclk_freq = 540000;
5514 else
5515 dev_priv->max_cdclk_freq = 675000;
5516 } else if (IS_CHERRYVIEW(dev)) {
5517 dev_priv->max_cdclk_freq = 320000;
5518 } else if (IS_VALLEYVIEW(dev)) {
5519 dev_priv->max_cdclk_freq = 400000;
5520 } else {
5521 /* otherwise assume cdclk is fixed */
5522 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5523 }
5524
5525 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5526
5527 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5528 dev_priv->max_cdclk_freq);
5529
5530 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5531 dev_priv->max_dotclk_freq);
5532 }
5533
5534 static void intel_update_cdclk(struct drm_device *dev)
5535 {
5536 struct drm_i915_private *dev_priv = dev->dev_private;
5537
5538 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5539 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5540 dev_priv->cdclk_freq);
5541
5542 /*
5543 * Program the gmbus_freq based on the cdclk frequency.
5544 * BSpec erroneously claims we should aim for 4MHz, but
5545 * in fact 1MHz is the correct frequency.
5546 */
5547 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5548 /*
5549 * Program the gmbus_freq based on the cdclk frequency.
5550 * BSpec erroneously claims we should aim for 4MHz, but
5551 * in fact 1MHz is the correct frequency.
5552 */
5553 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5554 }
5555
5556 if (dev_priv->max_cdclk_freq == 0)
5557 intel_update_max_cdclk(dev);
5558 }
5559
5560 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5561 {
5562 struct drm_i915_private *dev_priv = dev->dev_private;
5563 uint32_t divider;
5564 uint32_t ratio;
5565 uint32_t current_freq;
5566 int ret;
5567
5568 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5569 switch (frequency) {
5570 case 144000:
5571 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5572 ratio = BXT_DE_PLL_RATIO(60);
5573 break;
5574 case 288000:
5575 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5576 ratio = BXT_DE_PLL_RATIO(60);
5577 break;
5578 case 384000:
5579 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5580 ratio = BXT_DE_PLL_RATIO(60);
5581 break;
5582 case 576000:
5583 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5584 ratio = BXT_DE_PLL_RATIO(60);
5585 break;
5586 case 624000:
5587 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5588 ratio = BXT_DE_PLL_RATIO(65);
5589 break;
5590 case 19200:
5591 /*
5592 * Bypass frequency with DE PLL disabled. Init ratio, divider
5593 * to suppress GCC warning.
5594 */
5595 ratio = 0;
5596 divider = 0;
5597 break;
5598 default:
5599 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5600
5601 return;
5602 }
5603
5604 mutex_lock(&dev_priv->rps.hw_lock);
5605 /* Inform power controller of upcoming frequency change */
5606 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5607 0x80000000);
5608 mutex_unlock(&dev_priv->rps.hw_lock);
5609
5610 if (ret) {
5611 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5612 ret, frequency);
5613 return;
5614 }
5615
5616 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5617 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5618 current_freq = current_freq * 500 + 1000;
5619
5620 /*
5621 * DE PLL has to be disabled when
5622 * - setting to 19.2MHz (bypass, PLL isn't used)
5623 * - before setting to 624MHz (PLL needs toggling)
5624 * - before setting to any frequency from 624MHz (PLL needs toggling)
5625 */
5626 if (frequency == 19200 || frequency == 624000 ||
5627 current_freq == 624000) {
5628 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5629 /* Timeout 200us */
5630 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5631 1))
5632 DRM_ERROR("timout waiting for DE PLL unlock\n");
5633 }
5634
5635 if (frequency != 19200) {
5636 uint32_t val;
5637
5638 val = I915_READ(BXT_DE_PLL_CTL);
5639 val &= ~BXT_DE_PLL_RATIO_MASK;
5640 val |= ratio;
5641 I915_WRITE(BXT_DE_PLL_CTL, val);
5642
5643 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5644 /* Timeout 200us */
5645 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5646 DRM_ERROR("timeout waiting for DE PLL lock\n");
5647
5648 val = I915_READ(CDCLK_CTL);
5649 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5650 val |= divider;
5651 /*
5652 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5653 * enable otherwise.
5654 */
5655 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5656 if (frequency >= 500000)
5657 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5658
5659 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5660 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5661 val |= (frequency - 1000) / 500;
5662 I915_WRITE(CDCLK_CTL, val);
5663 }
5664
5665 mutex_lock(&dev_priv->rps.hw_lock);
5666 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5667 DIV_ROUND_UP(frequency, 25000));
5668 mutex_unlock(&dev_priv->rps.hw_lock);
5669
5670 if (ret) {
5671 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5672 ret, frequency);
5673 return;
5674 }
5675
5676 intel_update_cdclk(dev);
5677 }
5678
5679 void broxton_init_cdclk(struct drm_device *dev)
5680 {
5681 struct drm_i915_private *dev_priv = dev->dev_private;
5682 uint32_t val;
5683
5684 /*
5685 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5686 * or else the reset will hang because there is no PCH to respond.
5687 * Move the handshake programming to initialization sequence.
5688 * Previously was left up to BIOS.
5689 */
5690 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5691 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5692 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5693
5694 /* Enable PG1 for cdclk */
5695 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5696
5697 /* check if cd clock is enabled */
5698 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5699 DRM_DEBUG_KMS("Display already initialized\n");
5700 return;
5701 }
5702
5703 /*
5704 * FIXME:
5705 * - The initial CDCLK needs to be read from VBT.
5706 * Need to make this change after VBT has changes for BXT.
5707 * - check if setting the max (or any) cdclk freq is really necessary
5708 * here, it belongs to modeset time
5709 */
5710 broxton_set_cdclk(dev, 624000);
5711
5712 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5713 POSTING_READ(DBUF_CTL);
5714
5715 udelay(10);
5716
5717 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5718 DRM_ERROR("DBuf power enable timeout!\n");
5719 }
5720
5721 void broxton_uninit_cdclk(struct drm_device *dev)
5722 {
5723 struct drm_i915_private *dev_priv = dev->dev_private;
5724
5725 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5726 POSTING_READ(DBUF_CTL);
5727
5728 udelay(10);
5729
5730 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5731 DRM_ERROR("DBuf power disable timeout!\n");
5732
5733 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5734 broxton_set_cdclk(dev, 19200);
5735
5736 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5737 }
5738
5739 static const struct skl_cdclk_entry {
5740 unsigned int freq;
5741 unsigned int vco;
5742 } skl_cdclk_frequencies[] = {
5743 { .freq = 308570, .vco = 8640 },
5744 { .freq = 337500, .vco = 8100 },
5745 { .freq = 432000, .vco = 8640 },
5746 { .freq = 450000, .vco = 8100 },
5747 { .freq = 540000, .vco = 8100 },
5748 { .freq = 617140, .vco = 8640 },
5749 { .freq = 675000, .vco = 8100 },
5750 };
5751
5752 static unsigned int skl_cdclk_decimal(unsigned int freq)
5753 {
5754 return (freq - 1000) / 500;
5755 }
5756
5757 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5758 {
5759 unsigned int i;
5760
5761 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5762 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5763
5764 if (e->freq == freq)
5765 return e->vco;
5766 }
5767
5768 return 8100;
5769 }
5770
5771 static void
5772 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5773 {
5774 unsigned int min_freq;
5775 u32 val;
5776
5777 /* select the minimum CDCLK before enabling DPLL 0 */
5778 val = I915_READ(CDCLK_CTL);
5779 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5780 val |= CDCLK_FREQ_337_308;
5781
5782 if (required_vco == 8640)
5783 min_freq = 308570;
5784 else
5785 min_freq = 337500;
5786
5787 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5788
5789 I915_WRITE(CDCLK_CTL, val);
5790 POSTING_READ(CDCLK_CTL);
5791
5792 /*
5793 * We always enable DPLL0 with the lowest link rate possible, but still
5794 * taking into account the VCO required to operate the eDP panel at the
5795 * desired frequency. The usual DP link rates operate with a VCO of
5796 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5797 * The modeset code is responsible for the selection of the exact link
5798 * rate later on, with the constraint of choosing a frequency that
5799 * works with required_vco.
5800 */
5801 val = I915_READ(DPLL_CTRL1);
5802
5803 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5804 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5805 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5806 if (required_vco == 8640)
5807 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5808 SKL_DPLL0);
5809 else
5810 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5811 SKL_DPLL0);
5812
5813 I915_WRITE(DPLL_CTRL1, val);
5814 POSTING_READ(DPLL_CTRL1);
5815
5816 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5817
5818 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5819 DRM_ERROR("DPLL0 not locked\n");
5820 }
5821
5822 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5823 {
5824 int ret;
5825 u32 val;
5826
5827 /* inform PCU we want to change CDCLK */
5828 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5829 mutex_lock(&dev_priv->rps.hw_lock);
5830 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5831 mutex_unlock(&dev_priv->rps.hw_lock);
5832
5833 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5834 }
5835
5836 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5837 {
5838 unsigned int i;
5839
5840 for (i = 0; i < 15; i++) {
5841 if (skl_cdclk_pcu_ready(dev_priv))
5842 return true;
5843 udelay(10);
5844 }
5845
5846 return false;
5847 }
5848
5849 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5850 {
5851 struct drm_device *dev = dev_priv->dev;
5852 u32 freq_select, pcu_ack;
5853
5854 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5855
5856 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5857 DRM_ERROR("failed to inform PCU about cdclk change\n");
5858 return;
5859 }
5860
5861 /* set CDCLK_CTL */
5862 switch(freq) {
5863 case 450000:
5864 case 432000:
5865 freq_select = CDCLK_FREQ_450_432;
5866 pcu_ack = 1;
5867 break;
5868 case 540000:
5869 freq_select = CDCLK_FREQ_540;
5870 pcu_ack = 2;
5871 break;
5872 case 308570:
5873 case 337500:
5874 default:
5875 freq_select = CDCLK_FREQ_337_308;
5876 pcu_ack = 0;
5877 break;
5878 case 617140:
5879 case 675000:
5880 freq_select = CDCLK_FREQ_675_617;
5881 pcu_ack = 3;
5882 break;
5883 }
5884
5885 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5886 POSTING_READ(CDCLK_CTL);
5887
5888 /* inform PCU of the change */
5889 mutex_lock(&dev_priv->rps.hw_lock);
5890 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5891 mutex_unlock(&dev_priv->rps.hw_lock);
5892
5893 intel_update_cdclk(dev);
5894 }
5895
5896 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5897 {
5898 /* disable DBUF power */
5899 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5900 POSTING_READ(DBUF_CTL);
5901
5902 udelay(10);
5903
5904 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5905 DRM_ERROR("DBuf power disable timeout\n");
5906
5907 /* disable DPLL0 */
5908 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5909 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5910 DRM_ERROR("Couldn't disable DPLL0\n");
5911 }
5912
5913 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5914 {
5915 unsigned int required_vco;
5916
5917 /* DPLL0 not enabled (happens on early BIOS versions) */
5918 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5919 /* enable DPLL0 */
5920 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5921 skl_dpll0_enable(dev_priv, required_vco);
5922 }
5923
5924 /* set CDCLK to the frequency the BIOS chose */
5925 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5926
5927 /* enable DBUF power */
5928 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5929 POSTING_READ(DBUF_CTL);
5930
5931 udelay(10);
5932
5933 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5934 DRM_ERROR("DBuf power enable timeout\n");
5935 }
5936
5937 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5938 {
5939 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5940 uint32_t cdctl = I915_READ(CDCLK_CTL);
5941 int freq = dev_priv->skl_boot_cdclk;
5942
5943 /*
5944 * check if the pre-os intialized the display
5945 * There is SWF18 scratchpad register defined which is set by the
5946 * pre-os which can be used by the OS drivers to check the status
5947 */
5948 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5949 goto sanitize;
5950
5951 /* Is PLL enabled and locked ? */
5952 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5953 goto sanitize;
5954
5955 /* DPLL okay; verify the cdclock
5956 *
5957 * Noticed in some instances that the freq selection is correct but
5958 * decimal part is programmed wrong from BIOS where pre-os does not
5959 * enable display. Verify the same as well.
5960 */
5961 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5962 /* All well; nothing to sanitize */
5963 return false;
5964 sanitize:
5965 /*
5966 * As of now initialize with max cdclk till
5967 * we get dynamic cdclk support
5968 * */
5969 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5970 skl_init_cdclk(dev_priv);
5971
5972 /* we did have to sanitize */
5973 return true;
5974 }
5975
5976 /* Adjust CDclk dividers to allow high res or save power if possible */
5977 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5978 {
5979 struct drm_i915_private *dev_priv = dev->dev_private;
5980 u32 val, cmd;
5981
5982 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5983 != dev_priv->cdclk_freq);
5984
5985 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5986 cmd = 2;
5987 else if (cdclk == 266667)
5988 cmd = 1;
5989 else
5990 cmd = 0;
5991
5992 mutex_lock(&dev_priv->rps.hw_lock);
5993 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5994 val &= ~DSPFREQGUAR_MASK;
5995 val |= (cmd << DSPFREQGUAR_SHIFT);
5996 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5997 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5998 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5999 50)) {
6000 DRM_ERROR("timed out waiting for CDclk change\n");
6001 }
6002 mutex_unlock(&dev_priv->rps.hw_lock);
6003
6004 mutex_lock(&dev_priv->sb_lock);
6005
6006 if (cdclk == 400000) {
6007 u32 divider;
6008
6009 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6010
6011 /* adjust cdclk divider */
6012 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6013 val &= ~CCK_FREQUENCY_VALUES;
6014 val |= divider;
6015 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6016
6017 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6018 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6019 50))
6020 DRM_ERROR("timed out waiting for CDclk change\n");
6021 }
6022
6023 /* adjust self-refresh exit latency value */
6024 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6025 val &= ~0x7f;
6026
6027 /*
6028 * For high bandwidth configs, we set a higher latency in the bunit
6029 * so that the core display fetch happens in time to avoid underruns.
6030 */
6031 if (cdclk == 400000)
6032 val |= 4500 / 250; /* 4.5 usec */
6033 else
6034 val |= 3000 / 250; /* 3.0 usec */
6035 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6036
6037 mutex_unlock(&dev_priv->sb_lock);
6038
6039 intel_update_cdclk(dev);
6040 }
6041
6042 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6043 {
6044 struct drm_i915_private *dev_priv = dev->dev_private;
6045 u32 val, cmd;
6046
6047 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6048 != dev_priv->cdclk_freq);
6049
6050 switch (cdclk) {
6051 case 333333:
6052 case 320000:
6053 case 266667:
6054 case 200000:
6055 break;
6056 default:
6057 MISSING_CASE(cdclk);
6058 return;
6059 }
6060
6061 /*
6062 * Specs are full of misinformation, but testing on actual
6063 * hardware has shown that we just need to write the desired
6064 * CCK divider into the Punit register.
6065 */
6066 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6067
6068 mutex_lock(&dev_priv->rps.hw_lock);
6069 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6070 val &= ~DSPFREQGUAR_MASK_CHV;
6071 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6072 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6073 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6074 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6075 50)) {
6076 DRM_ERROR("timed out waiting for CDclk change\n");
6077 }
6078 mutex_unlock(&dev_priv->rps.hw_lock);
6079
6080 intel_update_cdclk(dev);
6081 }
6082
6083 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6084 int max_pixclk)
6085 {
6086 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6087 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6088
6089 /*
6090 * Really only a few cases to deal with, as only 4 CDclks are supported:
6091 * 200MHz
6092 * 267MHz
6093 * 320/333MHz (depends on HPLL freq)
6094 * 400MHz (VLV only)
6095 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6096 * of the lower bin and adjust if needed.
6097 *
6098 * We seem to get an unstable or solid color picture at 200MHz.
6099 * Not sure what's wrong. For now use 200MHz only when all pipes
6100 * are off.
6101 */
6102 if (!IS_CHERRYVIEW(dev_priv) &&
6103 max_pixclk > freq_320*limit/100)
6104 return 400000;
6105 else if (max_pixclk > 266667*limit/100)
6106 return freq_320;
6107 else if (max_pixclk > 0)
6108 return 266667;
6109 else
6110 return 200000;
6111 }
6112
6113 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6114 int max_pixclk)
6115 {
6116 /*
6117 * FIXME:
6118 * - remove the guardband, it's not needed on BXT
6119 * - set 19.2MHz bypass frequency if there are no active pipes
6120 */
6121 if (max_pixclk > 576000*9/10)
6122 return 624000;
6123 else if (max_pixclk > 384000*9/10)
6124 return 576000;
6125 else if (max_pixclk > 288000*9/10)
6126 return 384000;
6127 else if (max_pixclk > 144000*9/10)
6128 return 288000;
6129 else
6130 return 144000;
6131 }
6132
6133 /* Compute the max pixel clock for new configuration. */
6134 static int intel_mode_max_pixclk(struct drm_device *dev,
6135 struct drm_atomic_state *state)
6136 {
6137 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6138 struct drm_i915_private *dev_priv = dev->dev_private;
6139 struct drm_crtc *crtc;
6140 struct drm_crtc_state *crtc_state;
6141 unsigned max_pixclk = 0, i;
6142 enum pipe pipe;
6143
6144 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6145 sizeof(intel_state->min_pixclk));
6146
6147 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6148 int pixclk = 0;
6149
6150 if (crtc_state->enable)
6151 pixclk = crtc_state->adjusted_mode.crtc_clock;
6152
6153 intel_state->min_pixclk[i] = pixclk;
6154 }
6155
6156 for_each_pipe(dev_priv, pipe)
6157 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6158
6159 return max_pixclk;
6160 }
6161
6162 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6163 {
6164 struct drm_device *dev = state->dev;
6165 struct drm_i915_private *dev_priv = dev->dev_private;
6166 int max_pixclk = intel_mode_max_pixclk(dev, state);
6167 struct intel_atomic_state *intel_state =
6168 to_intel_atomic_state(state);
6169
6170 if (max_pixclk < 0)
6171 return max_pixclk;
6172
6173 intel_state->cdclk = intel_state->dev_cdclk =
6174 valleyview_calc_cdclk(dev_priv, max_pixclk);
6175
6176 if (!intel_state->active_crtcs)
6177 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6178
6179 return 0;
6180 }
6181
6182 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6183 {
6184 struct drm_device *dev = state->dev;
6185 struct drm_i915_private *dev_priv = dev->dev_private;
6186 int max_pixclk = intel_mode_max_pixclk(dev, state);
6187 struct intel_atomic_state *intel_state =
6188 to_intel_atomic_state(state);
6189
6190 if (max_pixclk < 0)
6191 return max_pixclk;
6192
6193 intel_state->cdclk = intel_state->dev_cdclk =
6194 broxton_calc_cdclk(dev_priv, max_pixclk);
6195
6196 if (!intel_state->active_crtcs)
6197 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6198
6199 return 0;
6200 }
6201
6202 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6203 {
6204 unsigned int credits, default_credits;
6205
6206 if (IS_CHERRYVIEW(dev_priv))
6207 default_credits = PFI_CREDIT(12);
6208 else
6209 default_credits = PFI_CREDIT(8);
6210
6211 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6212 /* CHV suggested value is 31 or 63 */
6213 if (IS_CHERRYVIEW(dev_priv))
6214 credits = PFI_CREDIT_63;
6215 else
6216 credits = PFI_CREDIT(15);
6217 } else {
6218 credits = default_credits;
6219 }
6220
6221 /*
6222 * WA - write default credits before re-programming
6223 * FIXME: should we also set the resend bit here?
6224 */
6225 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6226 default_credits);
6227
6228 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6229 credits | PFI_CREDIT_RESEND);
6230
6231 /*
6232 * FIXME is this guaranteed to clear
6233 * immediately or should we poll for it?
6234 */
6235 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6236 }
6237
6238 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6239 {
6240 struct drm_device *dev = old_state->dev;
6241 struct drm_i915_private *dev_priv = dev->dev_private;
6242 struct intel_atomic_state *old_intel_state =
6243 to_intel_atomic_state(old_state);
6244 unsigned req_cdclk = old_intel_state->dev_cdclk;
6245
6246 /*
6247 * FIXME: We can end up here with all power domains off, yet
6248 * with a CDCLK frequency other than the minimum. To account
6249 * for this take the PIPE-A power domain, which covers the HW
6250 * blocks needed for the following programming. This can be
6251 * removed once it's guaranteed that we get here either with
6252 * the minimum CDCLK set, or the required power domains
6253 * enabled.
6254 */
6255 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6256
6257 if (IS_CHERRYVIEW(dev))
6258 cherryview_set_cdclk(dev, req_cdclk);
6259 else
6260 valleyview_set_cdclk(dev, req_cdclk);
6261
6262 vlv_program_pfi_credits(dev_priv);
6263
6264 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6265 }
6266
6267 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6268 {
6269 struct drm_device *dev = crtc->dev;
6270 struct drm_i915_private *dev_priv = to_i915(dev);
6271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6272 struct intel_encoder *encoder;
6273 int pipe = intel_crtc->pipe;
6274
6275 if (WARN_ON(intel_crtc->active))
6276 return;
6277
6278 if (intel_crtc->config->has_dp_encoder)
6279 intel_dp_set_m_n(intel_crtc, M1_N1);
6280
6281 intel_set_pipe_timings(intel_crtc);
6282
6283 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6284 struct drm_i915_private *dev_priv = dev->dev_private;
6285
6286 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6287 I915_WRITE(CHV_CANVAS(pipe), 0);
6288 }
6289
6290 i9xx_set_pipeconf(intel_crtc);
6291
6292 intel_crtc->active = true;
6293
6294 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6295
6296 for_each_encoder_on_crtc(dev, crtc, encoder)
6297 if (encoder->pre_pll_enable)
6298 encoder->pre_pll_enable(encoder);
6299
6300 if (!intel_crtc->config->has_dsi_encoder) {
6301 if (IS_CHERRYVIEW(dev)) {
6302 chv_prepare_pll(intel_crtc, intel_crtc->config);
6303 chv_enable_pll(intel_crtc, intel_crtc->config);
6304 } else {
6305 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6306 vlv_enable_pll(intel_crtc, intel_crtc->config);
6307 }
6308 }
6309
6310 for_each_encoder_on_crtc(dev, crtc, encoder)
6311 if (encoder->pre_enable)
6312 encoder->pre_enable(encoder);
6313
6314 i9xx_pfit_enable(intel_crtc);
6315
6316 intel_crtc_load_lut(crtc);
6317
6318 intel_enable_pipe(intel_crtc);
6319
6320 assert_vblank_disabled(crtc);
6321 drm_crtc_vblank_on(crtc);
6322
6323 for_each_encoder_on_crtc(dev, crtc, encoder)
6324 encoder->enable(encoder);
6325 }
6326
6327 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6328 {
6329 struct drm_device *dev = crtc->base.dev;
6330 struct drm_i915_private *dev_priv = dev->dev_private;
6331
6332 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6333 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6334 }
6335
6336 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6337 {
6338 struct drm_device *dev = crtc->dev;
6339 struct drm_i915_private *dev_priv = to_i915(dev);
6340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6341 struct intel_encoder *encoder;
6342 int pipe = intel_crtc->pipe;
6343
6344 if (WARN_ON(intel_crtc->active))
6345 return;
6346
6347 i9xx_set_pll_dividers(intel_crtc);
6348
6349 if (intel_crtc->config->has_dp_encoder)
6350 intel_dp_set_m_n(intel_crtc, M1_N1);
6351
6352 intel_set_pipe_timings(intel_crtc);
6353
6354 i9xx_set_pipeconf(intel_crtc);
6355
6356 intel_crtc->active = true;
6357
6358 if (!IS_GEN2(dev))
6359 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6360
6361 for_each_encoder_on_crtc(dev, crtc, encoder)
6362 if (encoder->pre_enable)
6363 encoder->pre_enable(encoder);
6364
6365 i9xx_enable_pll(intel_crtc);
6366
6367 i9xx_pfit_enable(intel_crtc);
6368
6369 intel_crtc_load_lut(crtc);
6370
6371 intel_update_watermarks(crtc);
6372 intel_enable_pipe(intel_crtc);
6373
6374 assert_vblank_disabled(crtc);
6375 drm_crtc_vblank_on(crtc);
6376
6377 for_each_encoder_on_crtc(dev, crtc, encoder)
6378 encoder->enable(encoder);
6379 }
6380
6381 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6382 {
6383 struct drm_device *dev = crtc->base.dev;
6384 struct drm_i915_private *dev_priv = dev->dev_private;
6385
6386 if (!crtc->config->gmch_pfit.control)
6387 return;
6388
6389 assert_pipe_disabled(dev_priv, crtc->pipe);
6390
6391 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6392 I915_READ(PFIT_CONTROL));
6393 I915_WRITE(PFIT_CONTROL, 0);
6394 }
6395
6396 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6397 {
6398 struct drm_device *dev = crtc->dev;
6399 struct drm_i915_private *dev_priv = dev->dev_private;
6400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6401 struct intel_encoder *encoder;
6402 int pipe = intel_crtc->pipe;
6403
6404 /*
6405 * On gen2 planes are double buffered but the pipe isn't, so we must
6406 * wait for planes to fully turn off before disabling the pipe.
6407 * We also need to wait on all gmch platforms because of the
6408 * self-refresh mode constraint explained above.
6409 */
6410 intel_wait_for_vblank(dev, pipe);
6411
6412 for_each_encoder_on_crtc(dev, crtc, encoder)
6413 encoder->disable(encoder);
6414
6415 drm_crtc_vblank_off(crtc);
6416 assert_vblank_disabled(crtc);
6417
6418 intel_disable_pipe(intel_crtc);
6419
6420 i9xx_pfit_disable(intel_crtc);
6421
6422 for_each_encoder_on_crtc(dev, crtc, encoder)
6423 if (encoder->post_disable)
6424 encoder->post_disable(encoder);
6425
6426 if (!intel_crtc->config->has_dsi_encoder) {
6427 if (IS_CHERRYVIEW(dev))
6428 chv_disable_pll(dev_priv, pipe);
6429 else if (IS_VALLEYVIEW(dev))
6430 vlv_disable_pll(dev_priv, pipe);
6431 else
6432 i9xx_disable_pll(intel_crtc);
6433 }
6434
6435 for_each_encoder_on_crtc(dev, crtc, encoder)
6436 if (encoder->post_pll_disable)
6437 encoder->post_pll_disable(encoder);
6438
6439 if (!IS_GEN2(dev))
6440 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6441 }
6442
6443 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6444 {
6445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6446 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6447 enum intel_display_power_domain domain;
6448 unsigned long domains;
6449
6450 if (!intel_crtc->active)
6451 return;
6452
6453 if (to_intel_plane_state(crtc->primary->state)->visible) {
6454 WARN_ON(intel_crtc->unpin_work);
6455
6456 intel_pre_disable_primary(crtc);
6457
6458 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6459 to_intel_plane_state(crtc->primary->state)->visible = false;
6460 }
6461
6462 dev_priv->display.crtc_disable(crtc);
6463 intel_crtc->active = false;
6464 intel_fbc_disable(intel_crtc);
6465 intel_update_watermarks(crtc);
6466 intel_disable_shared_dpll(intel_crtc);
6467
6468 domains = intel_crtc->enabled_power_domains;
6469 for_each_power_domain(domain, domains)
6470 intel_display_power_put(dev_priv, domain);
6471 intel_crtc->enabled_power_domains = 0;
6472
6473 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6474 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6475 }
6476
6477 /*
6478 * turn all crtc's off, but do not adjust state
6479 * This has to be paired with a call to intel_modeset_setup_hw_state.
6480 */
6481 int intel_display_suspend(struct drm_device *dev)
6482 {
6483 struct drm_i915_private *dev_priv = to_i915(dev);
6484 struct drm_atomic_state *state;
6485 int ret;
6486
6487 state = drm_atomic_helper_suspend(dev);
6488 ret = PTR_ERR_OR_ZERO(state);
6489 if (ret)
6490 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6491 else
6492 dev_priv->modeset_restore_state = state;
6493 return ret;
6494 }
6495
6496 void intel_encoder_destroy(struct drm_encoder *encoder)
6497 {
6498 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6499
6500 drm_encoder_cleanup(encoder);
6501 kfree(intel_encoder);
6502 }
6503
6504 /* Cross check the actual hw state with our own modeset state tracking (and it's
6505 * internal consistency). */
6506 static void intel_connector_check_state(struct intel_connector *connector)
6507 {
6508 struct drm_crtc *crtc = connector->base.state->crtc;
6509
6510 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6511 connector->base.base.id,
6512 connector->base.name);
6513
6514 if (connector->get_hw_state(connector)) {
6515 struct intel_encoder *encoder = connector->encoder;
6516 struct drm_connector_state *conn_state = connector->base.state;
6517
6518 I915_STATE_WARN(!crtc,
6519 "connector enabled without attached crtc\n");
6520
6521 if (!crtc)
6522 return;
6523
6524 I915_STATE_WARN(!crtc->state->active,
6525 "connector is active, but attached crtc isn't\n");
6526
6527 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6528 return;
6529
6530 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6531 "atomic encoder doesn't match attached encoder\n");
6532
6533 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6534 "attached encoder crtc differs from connector crtc\n");
6535 } else {
6536 I915_STATE_WARN(crtc && crtc->state->active,
6537 "attached crtc is active, but connector isn't\n");
6538 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6539 "best encoder set without crtc!\n");
6540 }
6541 }
6542
6543 int intel_connector_init(struct intel_connector *connector)
6544 {
6545 drm_atomic_helper_connector_reset(&connector->base);
6546
6547 if (!connector->base.state)
6548 return -ENOMEM;
6549
6550 return 0;
6551 }
6552
6553 struct intel_connector *intel_connector_alloc(void)
6554 {
6555 struct intel_connector *connector;
6556
6557 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6558 if (!connector)
6559 return NULL;
6560
6561 if (intel_connector_init(connector) < 0) {
6562 kfree(connector);
6563 return NULL;
6564 }
6565
6566 return connector;
6567 }
6568
6569 /* Simple connector->get_hw_state implementation for encoders that support only
6570 * one connector and no cloning and hence the encoder state determines the state
6571 * of the connector. */
6572 bool intel_connector_get_hw_state(struct intel_connector *connector)
6573 {
6574 enum pipe pipe = 0;
6575 struct intel_encoder *encoder = connector->encoder;
6576
6577 return encoder->get_hw_state(encoder, &pipe);
6578 }
6579
6580 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6581 {
6582 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6583 return crtc_state->fdi_lanes;
6584
6585 return 0;
6586 }
6587
6588 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6589 struct intel_crtc_state *pipe_config)
6590 {
6591 struct drm_atomic_state *state = pipe_config->base.state;
6592 struct intel_crtc *other_crtc;
6593 struct intel_crtc_state *other_crtc_state;
6594
6595 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6596 pipe_name(pipe), pipe_config->fdi_lanes);
6597 if (pipe_config->fdi_lanes > 4) {
6598 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6599 pipe_name(pipe), pipe_config->fdi_lanes);
6600 return -EINVAL;
6601 }
6602
6603 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6604 if (pipe_config->fdi_lanes > 2) {
6605 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6606 pipe_config->fdi_lanes);
6607 return -EINVAL;
6608 } else {
6609 return 0;
6610 }
6611 }
6612
6613 if (INTEL_INFO(dev)->num_pipes == 2)
6614 return 0;
6615
6616 /* Ivybridge 3 pipe is really complicated */
6617 switch (pipe) {
6618 case PIPE_A:
6619 return 0;
6620 case PIPE_B:
6621 if (pipe_config->fdi_lanes <= 2)
6622 return 0;
6623
6624 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6625 other_crtc_state =
6626 intel_atomic_get_crtc_state(state, other_crtc);
6627 if (IS_ERR(other_crtc_state))
6628 return PTR_ERR(other_crtc_state);
6629
6630 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6631 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6632 pipe_name(pipe), pipe_config->fdi_lanes);
6633 return -EINVAL;
6634 }
6635 return 0;
6636 case PIPE_C:
6637 if (pipe_config->fdi_lanes > 2) {
6638 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6639 pipe_name(pipe), pipe_config->fdi_lanes);
6640 return -EINVAL;
6641 }
6642
6643 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6644 other_crtc_state =
6645 intel_atomic_get_crtc_state(state, other_crtc);
6646 if (IS_ERR(other_crtc_state))
6647 return PTR_ERR(other_crtc_state);
6648
6649 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6650 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6651 return -EINVAL;
6652 }
6653 return 0;
6654 default:
6655 BUG();
6656 }
6657 }
6658
6659 #define RETRY 1
6660 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6661 struct intel_crtc_state *pipe_config)
6662 {
6663 struct drm_device *dev = intel_crtc->base.dev;
6664 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6665 int lane, link_bw, fdi_dotclock, ret;
6666 bool needs_recompute = false;
6667
6668 retry:
6669 /* FDI is a binary signal running at ~2.7GHz, encoding
6670 * each output octet as 10 bits. The actual frequency
6671 * is stored as a divider into a 100MHz clock, and the
6672 * mode pixel clock is stored in units of 1KHz.
6673 * Hence the bw of each lane in terms of the mode signal
6674 * is:
6675 */
6676 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6677
6678 fdi_dotclock = adjusted_mode->crtc_clock;
6679
6680 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6681 pipe_config->pipe_bpp);
6682
6683 pipe_config->fdi_lanes = lane;
6684
6685 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6686 link_bw, &pipe_config->fdi_m_n);
6687
6688 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6689 intel_crtc->pipe, pipe_config);
6690 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6691 pipe_config->pipe_bpp -= 2*3;
6692 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6693 pipe_config->pipe_bpp);
6694 needs_recompute = true;
6695 pipe_config->bw_constrained = true;
6696
6697 goto retry;
6698 }
6699
6700 if (needs_recompute)
6701 return RETRY;
6702
6703 return ret;
6704 }
6705
6706 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6707 struct intel_crtc_state *pipe_config)
6708 {
6709 if (pipe_config->pipe_bpp > 24)
6710 return false;
6711
6712 /* HSW can handle pixel rate up to cdclk? */
6713 if (IS_HASWELL(dev_priv->dev))
6714 return true;
6715
6716 /*
6717 * We compare against max which means we must take
6718 * the increased cdclk requirement into account when
6719 * calculating the new cdclk.
6720 *
6721 * Should measure whether using a lower cdclk w/o IPS
6722 */
6723 return ilk_pipe_pixel_rate(pipe_config) <=
6724 dev_priv->max_cdclk_freq * 95 / 100;
6725 }
6726
6727 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6728 struct intel_crtc_state *pipe_config)
6729 {
6730 struct drm_device *dev = crtc->base.dev;
6731 struct drm_i915_private *dev_priv = dev->dev_private;
6732
6733 pipe_config->ips_enabled = i915.enable_ips &&
6734 hsw_crtc_supports_ips(crtc) &&
6735 pipe_config_supports_ips(dev_priv, pipe_config);
6736 }
6737
6738 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6739 {
6740 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6741
6742 /* GDG double wide on either pipe, otherwise pipe A only */
6743 return INTEL_INFO(dev_priv)->gen < 4 &&
6744 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6745 }
6746
6747 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6748 struct intel_crtc_state *pipe_config)
6749 {
6750 struct drm_device *dev = crtc->base.dev;
6751 struct drm_i915_private *dev_priv = dev->dev_private;
6752 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6753
6754 /* FIXME should check pixel clock limits on all platforms */
6755 if (INTEL_INFO(dev)->gen < 4) {
6756 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6757
6758 /*
6759 * Enable double wide mode when the dot clock
6760 * is > 90% of the (display) core speed.
6761 */
6762 if (intel_crtc_supports_double_wide(crtc) &&
6763 adjusted_mode->crtc_clock > clock_limit) {
6764 clock_limit *= 2;
6765 pipe_config->double_wide = true;
6766 }
6767
6768 if (adjusted_mode->crtc_clock > clock_limit) {
6769 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6770 adjusted_mode->crtc_clock, clock_limit,
6771 yesno(pipe_config->double_wide));
6772 return -EINVAL;
6773 }
6774 }
6775
6776 /*
6777 * Pipe horizontal size must be even in:
6778 * - DVO ganged mode
6779 * - LVDS dual channel mode
6780 * - Double wide pipe
6781 */
6782 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6783 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6784 pipe_config->pipe_src_w &= ~1;
6785
6786 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6787 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6788 */
6789 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6790 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6791 return -EINVAL;
6792
6793 if (HAS_IPS(dev))
6794 hsw_compute_ips_config(crtc, pipe_config);
6795
6796 if (pipe_config->has_pch_encoder)
6797 return ironlake_fdi_compute_config(crtc, pipe_config);
6798
6799 return 0;
6800 }
6801
6802 static int skylake_get_display_clock_speed(struct drm_device *dev)
6803 {
6804 struct drm_i915_private *dev_priv = to_i915(dev);
6805 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6806 uint32_t cdctl = I915_READ(CDCLK_CTL);
6807 uint32_t linkrate;
6808
6809 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6810 return 24000; /* 24MHz is the cd freq with NSSC ref */
6811
6812 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6813 return 540000;
6814
6815 linkrate = (I915_READ(DPLL_CTRL1) &
6816 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6817
6818 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6819 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6820 /* vco 8640 */
6821 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6822 case CDCLK_FREQ_450_432:
6823 return 432000;
6824 case CDCLK_FREQ_337_308:
6825 return 308570;
6826 case CDCLK_FREQ_675_617:
6827 return 617140;
6828 default:
6829 WARN(1, "Unknown cd freq selection\n");
6830 }
6831 } else {
6832 /* vco 8100 */
6833 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6834 case CDCLK_FREQ_450_432:
6835 return 450000;
6836 case CDCLK_FREQ_337_308:
6837 return 337500;
6838 case CDCLK_FREQ_675_617:
6839 return 675000;
6840 default:
6841 WARN(1, "Unknown cd freq selection\n");
6842 }
6843 }
6844
6845 /* error case, do as if DPLL0 isn't enabled */
6846 return 24000;
6847 }
6848
6849 static int broxton_get_display_clock_speed(struct drm_device *dev)
6850 {
6851 struct drm_i915_private *dev_priv = to_i915(dev);
6852 uint32_t cdctl = I915_READ(CDCLK_CTL);
6853 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6854 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6855 int cdclk;
6856
6857 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6858 return 19200;
6859
6860 cdclk = 19200 * pll_ratio / 2;
6861
6862 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6863 case BXT_CDCLK_CD2X_DIV_SEL_1:
6864 return cdclk; /* 576MHz or 624MHz */
6865 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6866 return cdclk * 2 / 3; /* 384MHz */
6867 case BXT_CDCLK_CD2X_DIV_SEL_2:
6868 return cdclk / 2; /* 288MHz */
6869 case BXT_CDCLK_CD2X_DIV_SEL_4:
6870 return cdclk / 4; /* 144MHz */
6871 }
6872
6873 /* error case, do as if DE PLL isn't enabled */
6874 return 19200;
6875 }
6876
6877 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6878 {
6879 struct drm_i915_private *dev_priv = dev->dev_private;
6880 uint32_t lcpll = I915_READ(LCPLL_CTL);
6881 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6882
6883 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6884 return 800000;
6885 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6886 return 450000;
6887 else if (freq == LCPLL_CLK_FREQ_450)
6888 return 450000;
6889 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6890 return 540000;
6891 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6892 return 337500;
6893 else
6894 return 675000;
6895 }
6896
6897 static int haswell_get_display_clock_speed(struct drm_device *dev)
6898 {
6899 struct drm_i915_private *dev_priv = dev->dev_private;
6900 uint32_t lcpll = I915_READ(LCPLL_CTL);
6901 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6902
6903 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6904 return 800000;
6905 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6906 return 450000;
6907 else if (freq == LCPLL_CLK_FREQ_450)
6908 return 450000;
6909 else if (IS_HSW_ULT(dev))
6910 return 337500;
6911 else
6912 return 540000;
6913 }
6914
6915 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6916 {
6917 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6918 CCK_DISPLAY_CLOCK_CONTROL);
6919 }
6920
6921 static int ilk_get_display_clock_speed(struct drm_device *dev)
6922 {
6923 return 450000;
6924 }
6925
6926 static int i945_get_display_clock_speed(struct drm_device *dev)
6927 {
6928 return 400000;
6929 }
6930
6931 static int i915_get_display_clock_speed(struct drm_device *dev)
6932 {
6933 return 333333;
6934 }
6935
6936 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6937 {
6938 return 200000;
6939 }
6940
6941 static int pnv_get_display_clock_speed(struct drm_device *dev)
6942 {
6943 u16 gcfgc = 0;
6944
6945 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6946
6947 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6948 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6949 return 266667;
6950 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6951 return 333333;
6952 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6953 return 444444;
6954 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6955 return 200000;
6956 default:
6957 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6958 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6959 return 133333;
6960 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6961 return 166667;
6962 }
6963 }
6964
6965 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6966 {
6967 u16 gcfgc = 0;
6968
6969 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6970
6971 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6972 return 133333;
6973 else {
6974 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6975 case GC_DISPLAY_CLOCK_333_MHZ:
6976 return 333333;
6977 default:
6978 case GC_DISPLAY_CLOCK_190_200_MHZ:
6979 return 190000;
6980 }
6981 }
6982 }
6983
6984 static int i865_get_display_clock_speed(struct drm_device *dev)
6985 {
6986 return 266667;
6987 }
6988
6989 static int i85x_get_display_clock_speed(struct drm_device *dev)
6990 {
6991 u16 hpllcc = 0;
6992
6993 /*
6994 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6995 * encoding is different :(
6996 * FIXME is this the right way to detect 852GM/852GMV?
6997 */
6998 if (dev->pdev->revision == 0x1)
6999 return 133333;
7000
7001 pci_bus_read_config_word(dev->pdev->bus,
7002 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7003
7004 /* Assume that the hardware is in the high speed state. This
7005 * should be the default.
7006 */
7007 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7008 case GC_CLOCK_133_200:
7009 case GC_CLOCK_133_200_2:
7010 case GC_CLOCK_100_200:
7011 return 200000;
7012 case GC_CLOCK_166_250:
7013 return 250000;
7014 case GC_CLOCK_100_133:
7015 return 133333;
7016 case GC_CLOCK_133_266:
7017 case GC_CLOCK_133_266_2:
7018 case GC_CLOCK_166_266:
7019 return 266667;
7020 }
7021
7022 /* Shouldn't happen */
7023 return 0;
7024 }
7025
7026 static int i830_get_display_clock_speed(struct drm_device *dev)
7027 {
7028 return 133333;
7029 }
7030
7031 static unsigned int intel_hpll_vco(struct drm_device *dev)
7032 {
7033 struct drm_i915_private *dev_priv = dev->dev_private;
7034 static const unsigned int blb_vco[8] = {
7035 [0] = 3200000,
7036 [1] = 4000000,
7037 [2] = 5333333,
7038 [3] = 4800000,
7039 [4] = 6400000,
7040 };
7041 static const unsigned int pnv_vco[8] = {
7042 [0] = 3200000,
7043 [1] = 4000000,
7044 [2] = 5333333,
7045 [3] = 4800000,
7046 [4] = 2666667,
7047 };
7048 static const unsigned int cl_vco[8] = {
7049 [0] = 3200000,
7050 [1] = 4000000,
7051 [2] = 5333333,
7052 [3] = 6400000,
7053 [4] = 3333333,
7054 [5] = 3566667,
7055 [6] = 4266667,
7056 };
7057 static const unsigned int elk_vco[8] = {
7058 [0] = 3200000,
7059 [1] = 4000000,
7060 [2] = 5333333,
7061 [3] = 4800000,
7062 };
7063 static const unsigned int ctg_vco[8] = {
7064 [0] = 3200000,
7065 [1] = 4000000,
7066 [2] = 5333333,
7067 [3] = 6400000,
7068 [4] = 2666667,
7069 [5] = 4266667,
7070 };
7071 const unsigned int *vco_table;
7072 unsigned int vco;
7073 uint8_t tmp = 0;
7074
7075 /* FIXME other chipsets? */
7076 if (IS_GM45(dev))
7077 vco_table = ctg_vco;
7078 else if (IS_G4X(dev))
7079 vco_table = elk_vco;
7080 else if (IS_CRESTLINE(dev))
7081 vco_table = cl_vco;
7082 else if (IS_PINEVIEW(dev))
7083 vco_table = pnv_vco;
7084 else if (IS_G33(dev))
7085 vco_table = blb_vco;
7086 else
7087 return 0;
7088
7089 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7090
7091 vco = vco_table[tmp & 0x7];
7092 if (vco == 0)
7093 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7094 else
7095 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7096
7097 return vco;
7098 }
7099
7100 static int gm45_get_display_clock_speed(struct drm_device *dev)
7101 {
7102 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7103 uint16_t tmp = 0;
7104
7105 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7106
7107 cdclk_sel = (tmp >> 12) & 0x1;
7108
7109 switch (vco) {
7110 case 2666667:
7111 case 4000000:
7112 case 5333333:
7113 return cdclk_sel ? 333333 : 222222;
7114 case 3200000:
7115 return cdclk_sel ? 320000 : 228571;
7116 default:
7117 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7118 return 222222;
7119 }
7120 }
7121
7122 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7123 {
7124 static const uint8_t div_3200[] = { 16, 10, 8 };
7125 static const uint8_t div_4000[] = { 20, 12, 10 };
7126 static const uint8_t div_5333[] = { 24, 16, 14 };
7127 const uint8_t *div_table;
7128 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7129 uint16_t tmp = 0;
7130
7131 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7132
7133 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7134
7135 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7136 goto fail;
7137
7138 switch (vco) {
7139 case 3200000:
7140 div_table = div_3200;
7141 break;
7142 case 4000000:
7143 div_table = div_4000;
7144 break;
7145 case 5333333:
7146 div_table = div_5333;
7147 break;
7148 default:
7149 goto fail;
7150 }
7151
7152 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7153
7154 fail:
7155 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7156 return 200000;
7157 }
7158
7159 static int g33_get_display_clock_speed(struct drm_device *dev)
7160 {
7161 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7162 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7163 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7164 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7165 const uint8_t *div_table;
7166 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7167 uint16_t tmp = 0;
7168
7169 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7170
7171 cdclk_sel = (tmp >> 4) & 0x7;
7172
7173 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7174 goto fail;
7175
7176 switch (vco) {
7177 case 3200000:
7178 div_table = div_3200;
7179 break;
7180 case 4000000:
7181 div_table = div_4000;
7182 break;
7183 case 4800000:
7184 div_table = div_4800;
7185 break;
7186 case 5333333:
7187 div_table = div_5333;
7188 break;
7189 default:
7190 goto fail;
7191 }
7192
7193 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7194
7195 fail:
7196 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7197 return 190476;
7198 }
7199
7200 static void
7201 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7202 {
7203 while (*num > DATA_LINK_M_N_MASK ||
7204 *den > DATA_LINK_M_N_MASK) {
7205 *num >>= 1;
7206 *den >>= 1;
7207 }
7208 }
7209
7210 static void compute_m_n(unsigned int m, unsigned int n,
7211 uint32_t *ret_m, uint32_t *ret_n)
7212 {
7213 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7214 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7215 intel_reduce_m_n_ratio(ret_m, ret_n);
7216 }
7217
7218 void
7219 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7220 int pixel_clock, int link_clock,
7221 struct intel_link_m_n *m_n)
7222 {
7223 m_n->tu = 64;
7224
7225 compute_m_n(bits_per_pixel * pixel_clock,
7226 link_clock * nlanes * 8,
7227 &m_n->gmch_m, &m_n->gmch_n);
7228
7229 compute_m_n(pixel_clock, link_clock,
7230 &m_n->link_m, &m_n->link_n);
7231 }
7232
7233 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7234 {
7235 if (i915.panel_use_ssc >= 0)
7236 return i915.panel_use_ssc != 0;
7237 return dev_priv->vbt.lvds_use_ssc
7238 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7239 }
7240
7241 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7242 int num_connectors)
7243 {
7244 struct drm_device *dev = crtc_state->base.crtc->dev;
7245 struct drm_i915_private *dev_priv = dev->dev_private;
7246 int refclk;
7247
7248 WARN_ON(!crtc_state->base.state);
7249
7250 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7251 refclk = 100000;
7252 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7253 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7254 refclk = dev_priv->vbt.lvds_ssc_freq;
7255 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7256 } else if (!IS_GEN2(dev)) {
7257 refclk = 96000;
7258 } else {
7259 refclk = 48000;
7260 }
7261
7262 return refclk;
7263 }
7264
7265 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7266 {
7267 return (1 << dpll->n) << 16 | dpll->m2;
7268 }
7269
7270 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7271 {
7272 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7273 }
7274
7275 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7276 struct intel_crtc_state *crtc_state,
7277 intel_clock_t *reduced_clock)
7278 {
7279 struct drm_device *dev = crtc->base.dev;
7280 u32 fp, fp2 = 0;
7281
7282 if (IS_PINEVIEW(dev)) {
7283 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7284 if (reduced_clock)
7285 fp2 = pnv_dpll_compute_fp(reduced_clock);
7286 } else {
7287 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7288 if (reduced_clock)
7289 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7290 }
7291
7292 crtc_state->dpll_hw_state.fp0 = fp;
7293
7294 crtc->lowfreq_avail = false;
7295 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7296 reduced_clock) {
7297 crtc_state->dpll_hw_state.fp1 = fp2;
7298 crtc->lowfreq_avail = true;
7299 } else {
7300 crtc_state->dpll_hw_state.fp1 = fp;
7301 }
7302 }
7303
7304 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7305 pipe)
7306 {
7307 u32 reg_val;
7308
7309 /*
7310 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7311 * and set it to a reasonable value instead.
7312 */
7313 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7314 reg_val &= 0xffffff00;
7315 reg_val |= 0x00000030;
7316 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7317
7318 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7319 reg_val &= 0x8cffffff;
7320 reg_val = 0x8c000000;
7321 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7322
7323 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7324 reg_val &= 0xffffff00;
7325 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7326
7327 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7328 reg_val &= 0x00ffffff;
7329 reg_val |= 0xb0000000;
7330 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7331 }
7332
7333 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7334 struct intel_link_m_n *m_n)
7335 {
7336 struct drm_device *dev = crtc->base.dev;
7337 struct drm_i915_private *dev_priv = dev->dev_private;
7338 int pipe = crtc->pipe;
7339
7340 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7341 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7342 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7343 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7344 }
7345
7346 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7347 struct intel_link_m_n *m_n,
7348 struct intel_link_m_n *m2_n2)
7349 {
7350 struct drm_device *dev = crtc->base.dev;
7351 struct drm_i915_private *dev_priv = dev->dev_private;
7352 int pipe = crtc->pipe;
7353 enum transcoder transcoder = crtc->config->cpu_transcoder;
7354
7355 if (INTEL_INFO(dev)->gen >= 5) {
7356 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7357 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7358 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7359 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7360 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7361 * for gen < 8) and if DRRS is supported (to make sure the
7362 * registers are not unnecessarily accessed).
7363 */
7364 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7365 crtc->config->has_drrs) {
7366 I915_WRITE(PIPE_DATA_M2(transcoder),
7367 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7368 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7369 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7370 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7371 }
7372 } else {
7373 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7374 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7375 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7376 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7377 }
7378 }
7379
7380 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7381 {
7382 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7383
7384 if (m_n == M1_N1) {
7385 dp_m_n = &crtc->config->dp_m_n;
7386 dp_m2_n2 = &crtc->config->dp_m2_n2;
7387 } else if (m_n == M2_N2) {
7388
7389 /*
7390 * M2_N2 registers are not supported. Hence m2_n2 divider value
7391 * needs to be programmed into M1_N1.
7392 */
7393 dp_m_n = &crtc->config->dp_m2_n2;
7394 } else {
7395 DRM_ERROR("Unsupported divider value\n");
7396 return;
7397 }
7398
7399 if (crtc->config->has_pch_encoder)
7400 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7401 else
7402 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7403 }
7404
7405 static void vlv_compute_dpll(struct intel_crtc *crtc,
7406 struct intel_crtc_state *pipe_config)
7407 {
7408 u32 dpll, dpll_md;
7409
7410 /*
7411 * Enable DPIO clock input. We should never disable the reference
7412 * clock for pipe B, since VGA hotplug / manual detection depends
7413 * on it.
7414 */
7415 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7416 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7417 /* We should never disable this, set it here for state tracking */
7418 if (crtc->pipe == PIPE_B)
7419 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7420 dpll |= DPLL_VCO_ENABLE;
7421 pipe_config->dpll_hw_state.dpll = dpll;
7422
7423 dpll_md = (pipe_config->pixel_multiplier - 1)
7424 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7425 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7426 }
7427
7428 static void vlv_prepare_pll(struct intel_crtc *crtc,
7429 const struct intel_crtc_state *pipe_config)
7430 {
7431 struct drm_device *dev = crtc->base.dev;
7432 struct drm_i915_private *dev_priv = dev->dev_private;
7433 int pipe = crtc->pipe;
7434 u32 mdiv;
7435 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7436 u32 coreclk, reg_val;
7437
7438 mutex_lock(&dev_priv->sb_lock);
7439
7440 bestn = pipe_config->dpll.n;
7441 bestm1 = pipe_config->dpll.m1;
7442 bestm2 = pipe_config->dpll.m2;
7443 bestp1 = pipe_config->dpll.p1;
7444 bestp2 = pipe_config->dpll.p2;
7445
7446 /* See eDP HDMI DPIO driver vbios notes doc */
7447
7448 /* PLL B needs special handling */
7449 if (pipe == PIPE_B)
7450 vlv_pllb_recal_opamp(dev_priv, pipe);
7451
7452 /* Set up Tx target for periodic Rcomp update */
7453 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7454
7455 /* Disable target IRef on PLL */
7456 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7457 reg_val &= 0x00ffffff;
7458 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7459
7460 /* Disable fast lock */
7461 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7462
7463 /* Set idtafcrecal before PLL is enabled */
7464 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7465 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7466 mdiv |= ((bestn << DPIO_N_SHIFT));
7467 mdiv |= (1 << DPIO_K_SHIFT);
7468
7469 /*
7470 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7471 * but we don't support that).
7472 * Note: don't use the DAC post divider as it seems unstable.
7473 */
7474 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7475 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7476
7477 mdiv |= DPIO_ENABLE_CALIBRATION;
7478 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7479
7480 /* Set HBR and RBR LPF coefficients */
7481 if (pipe_config->port_clock == 162000 ||
7482 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7483 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7484 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7485 0x009f0003);
7486 else
7487 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7488 0x00d0000f);
7489
7490 if (pipe_config->has_dp_encoder) {
7491 /* Use SSC source */
7492 if (pipe == PIPE_A)
7493 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7494 0x0df40000);
7495 else
7496 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7497 0x0df70000);
7498 } else { /* HDMI or VGA */
7499 /* Use bend source */
7500 if (pipe == PIPE_A)
7501 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7502 0x0df70000);
7503 else
7504 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7505 0x0df40000);
7506 }
7507
7508 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7509 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7510 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7511 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7512 coreclk |= 0x01000000;
7513 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7514
7515 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7516 mutex_unlock(&dev_priv->sb_lock);
7517 }
7518
7519 static void chv_compute_dpll(struct intel_crtc *crtc,
7520 struct intel_crtc_state *pipe_config)
7521 {
7522 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7523 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7524 DPLL_VCO_ENABLE;
7525 if (crtc->pipe != PIPE_A)
7526 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7527
7528 pipe_config->dpll_hw_state.dpll_md =
7529 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7530 }
7531
7532 static void chv_prepare_pll(struct intel_crtc *crtc,
7533 const struct intel_crtc_state *pipe_config)
7534 {
7535 struct drm_device *dev = crtc->base.dev;
7536 struct drm_i915_private *dev_priv = dev->dev_private;
7537 int pipe = crtc->pipe;
7538 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7539 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7540 u32 loopfilter, tribuf_calcntr;
7541 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7542 u32 dpio_val;
7543 int vco;
7544
7545 bestn = pipe_config->dpll.n;
7546 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7547 bestm1 = pipe_config->dpll.m1;
7548 bestm2 = pipe_config->dpll.m2 >> 22;
7549 bestp1 = pipe_config->dpll.p1;
7550 bestp2 = pipe_config->dpll.p2;
7551 vco = pipe_config->dpll.vco;
7552 dpio_val = 0;
7553 loopfilter = 0;
7554
7555 /*
7556 * Enable Refclk and SSC
7557 */
7558 I915_WRITE(dpll_reg,
7559 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7560
7561 mutex_lock(&dev_priv->sb_lock);
7562
7563 /* p1 and p2 divider */
7564 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7565 5 << DPIO_CHV_S1_DIV_SHIFT |
7566 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7567 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7568 1 << DPIO_CHV_K_DIV_SHIFT);
7569
7570 /* Feedback post-divider - m2 */
7571 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7572
7573 /* Feedback refclk divider - n and m1 */
7574 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7575 DPIO_CHV_M1_DIV_BY_2 |
7576 1 << DPIO_CHV_N_DIV_SHIFT);
7577
7578 /* M2 fraction division */
7579 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7580
7581 /* M2 fraction division enable */
7582 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7583 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7584 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7585 if (bestm2_frac)
7586 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7587 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7588
7589 /* Program digital lock detect threshold */
7590 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7591 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7592 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7593 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7594 if (!bestm2_frac)
7595 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7596 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7597
7598 /* Loop filter */
7599 if (vco == 5400000) {
7600 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7601 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7602 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7603 tribuf_calcntr = 0x9;
7604 } else if (vco <= 6200000) {
7605 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7606 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7607 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7608 tribuf_calcntr = 0x9;
7609 } else if (vco <= 6480000) {
7610 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7611 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7612 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7613 tribuf_calcntr = 0x8;
7614 } else {
7615 /* Not supported. Apply the same limits as in the max case */
7616 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7617 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7618 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7619 tribuf_calcntr = 0;
7620 }
7621 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7622
7623 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7624 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7625 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7626 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7627
7628 /* AFC Recal */
7629 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7630 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7631 DPIO_AFC_RECAL);
7632
7633 mutex_unlock(&dev_priv->sb_lock);
7634 }
7635
7636 /**
7637 * vlv_force_pll_on - forcibly enable just the PLL
7638 * @dev_priv: i915 private structure
7639 * @pipe: pipe PLL to enable
7640 * @dpll: PLL configuration
7641 *
7642 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7643 * in cases where we need the PLL enabled even when @pipe is not going to
7644 * be enabled.
7645 */
7646 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7647 const struct dpll *dpll)
7648 {
7649 struct intel_crtc *crtc =
7650 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7651 struct intel_crtc_state *pipe_config;
7652
7653 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7654 if (!pipe_config)
7655 return -ENOMEM;
7656
7657 pipe_config->base.crtc = &crtc->base;
7658 pipe_config->pixel_multiplier = 1;
7659 pipe_config->dpll = *dpll;
7660
7661 if (IS_CHERRYVIEW(dev)) {
7662 chv_compute_dpll(crtc, pipe_config);
7663 chv_prepare_pll(crtc, pipe_config);
7664 chv_enable_pll(crtc, pipe_config);
7665 } else {
7666 vlv_compute_dpll(crtc, pipe_config);
7667 vlv_prepare_pll(crtc, pipe_config);
7668 vlv_enable_pll(crtc, pipe_config);
7669 }
7670
7671 kfree(pipe_config);
7672
7673 return 0;
7674 }
7675
7676 /**
7677 * vlv_force_pll_off - forcibly disable just the PLL
7678 * @dev_priv: i915 private structure
7679 * @pipe: pipe PLL to disable
7680 *
7681 * Disable the PLL for @pipe. To be used in cases where we need
7682 * the PLL enabled even when @pipe is not going to be enabled.
7683 */
7684 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7685 {
7686 if (IS_CHERRYVIEW(dev))
7687 chv_disable_pll(to_i915(dev), pipe);
7688 else
7689 vlv_disable_pll(to_i915(dev), pipe);
7690 }
7691
7692 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7693 struct intel_crtc_state *crtc_state,
7694 intel_clock_t *reduced_clock,
7695 int num_connectors)
7696 {
7697 struct drm_device *dev = crtc->base.dev;
7698 struct drm_i915_private *dev_priv = dev->dev_private;
7699 u32 dpll;
7700 bool is_sdvo;
7701 struct dpll *clock = &crtc_state->dpll;
7702
7703 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7704
7705 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7706 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7707
7708 dpll = DPLL_VGA_MODE_DIS;
7709
7710 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7711 dpll |= DPLLB_MODE_LVDS;
7712 else
7713 dpll |= DPLLB_MODE_DAC_SERIAL;
7714
7715 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7716 dpll |= (crtc_state->pixel_multiplier - 1)
7717 << SDVO_MULTIPLIER_SHIFT_HIRES;
7718 }
7719
7720 if (is_sdvo)
7721 dpll |= DPLL_SDVO_HIGH_SPEED;
7722
7723 if (crtc_state->has_dp_encoder)
7724 dpll |= DPLL_SDVO_HIGH_SPEED;
7725
7726 /* compute bitmask from p1 value */
7727 if (IS_PINEVIEW(dev))
7728 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7729 else {
7730 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7731 if (IS_G4X(dev) && reduced_clock)
7732 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7733 }
7734 switch (clock->p2) {
7735 case 5:
7736 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7737 break;
7738 case 7:
7739 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7740 break;
7741 case 10:
7742 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7743 break;
7744 case 14:
7745 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7746 break;
7747 }
7748 if (INTEL_INFO(dev)->gen >= 4)
7749 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7750
7751 if (crtc_state->sdvo_tv_clock)
7752 dpll |= PLL_REF_INPUT_TVCLKINBC;
7753 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7754 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7755 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7756 else
7757 dpll |= PLL_REF_INPUT_DREFCLK;
7758
7759 dpll |= DPLL_VCO_ENABLE;
7760 crtc_state->dpll_hw_state.dpll = dpll;
7761
7762 if (INTEL_INFO(dev)->gen >= 4) {
7763 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7764 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7765 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7766 }
7767 }
7768
7769 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7770 struct intel_crtc_state *crtc_state,
7771 intel_clock_t *reduced_clock,
7772 int num_connectors)
7773 {
7774 struct drm_device *dev = crtc->base.dev;
7775 struct drm_i915_private *dev_priv = dev->dev_private;
7776 u32 dpll;
7777 struct dpll *clock = &crtc_state->dpll;
7778
7779 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7780
7781 dpll = DPLL_VGA_MODE_DIS;
7782
7783 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7784 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7785 } else {
7786 if (clock->p1 == 2)
7787 dpll |= PLL_P1_DIVIDE_BY_TWO;
7788 else
7789 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7790 if (clock->p2 == 4)
7791 dpll |= PLL_P2_DIVIDE_BY_4;
7792 }
7793
7794 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7795 dpll |= DPLL_DVO_2X_MODE;
7796
7797 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7798 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7799 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7800 else
7801 dpll |= PLL_REF_INPUT_DREFCLK;
7802
7803 dpll |= DPLL_VCO_ENABLE;
7804 crtc_state->dpll_hw_state.dpll = dpll;
7805 }
7806
7807 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7808 {
7809 struct drm_device *dev = intel_crtc->base.dev;
7810 struct drm_i915_private *dev_priv = dev->dev_private;
7811 enum pipe pipe = intel_crtc->pipe;
7812 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7813 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7814 uint32_t crtc_vtotal, crtc_vblank_end;
7815 int vsyncshift = 0;
7816
7817 /* We need to be careful not to changed the adjusted mode, for otherwise
7818 * the hw state checker will get angry at the mismatch. */
7819 crtc_vtotal = adjusted_mode->crtc_vtotal;
7820 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7821
7822 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7823 /* the chip adds 2 halflines automatically */
7824 crtc_vtotal -= 1;
7825 crtc_vblank_end -= 1;
7826
7827 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7828 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7829 else
7830 vsyncshift = adjusted_mode->crtc_hsync_start -
7831 adjusted_mode->crtc_htotal / 2;
7832 if (vsyncshift < 0)
7833 vsyncshift += adjusted_mode->crtc_htotal;
7834 }
7835
7836 if (INTEL_INFO(dev)->gen > 3)
7837 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7838
7839 I915_WRITE(HTOTAL(cpu_transcoder),
7840 (adjusted_mode->crtc_hdisplay - 1) |
7841 ((adjusted_mode->crtc_htotal - 1) << 16));
7842 I915_WRITE(HBLANK(cpu_transcoder),
7843 (adjusted_mode->crtc_hblank_start - 1) |
7844 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7845 I915_WRITE(HSYNC(cpu_transcoder),
7846 (adjusted_mode->crtc_hsync_start - 1) |
7847 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7848
7849 I915_WRITE(VTOTAL(cpu_transcoder),
7850 (adjusted_mode->crtc_vdisplay - 1) |
7851 ((crtc_vtotal - 1) << 16));
7852 I915_WRITE(VBLANK(cpu_transcoder),
7853 (adjusted_mode->crtc_vblank_start - 1) |
7854 ((crtc_vblank_end - 1) << 16));
7855 I915_WRITE(VSYNC(cpu_transcoder),
7856 (adjusted_mode->crtc_vsync_start - 1) |
7857 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7858
7859 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7860 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7861 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7862 * bits. */
7863 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7864 (pipe == PIPE_B || pipe == PIPE_C))
7865 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7866
7867 /* pipesrc controls the size that is scaled from, which should
7868 * always be the user's requested size.
7869 */
7870 I915_WRITE(PIPESRC(pipe),
7871 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7872 (intel_crtc->config->pipe_src_h - 1));
7873 }
7874
7875 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7876 struct intel_crtc_state *pipe_config)
7877 {
7878 struct drm_device *dev = crtc->base.dev;
7879 struct drm_i915_private *dev_priv = dev->dev_private;
7880 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7881 uint32_t tmp;
7882
7883 tmp = I915_READ(HTOTAL(cpu_transcoder));
7884 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7885 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7886 tmp = I915_READ(HBLANK(cpu_transcoder));
7887 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7888 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7889 tmp = I915_READ(HSYNC(cpu_transcoder));
7890 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7891 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7892
7893 tmp = I915_READ(VTOTAL(cpu_transcoder));
7894 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7895 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7896 tmp = I915_READ(VBLANK(cpu_transcoder));
7897 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7898 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7899 tmp = I915_READ(VSYNC(cpu_transcoder));
7900 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7901 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7902
7903 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7904 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7905 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7906 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7907 }
7908
7909 tmp = I915_READ(PIPESRC(crtc->pipe));
7910 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7911 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7912
7913 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7914 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7915 }
7916
7917 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7918 struct intel_crtc_state *pipe_config)
7919 {
7920 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7921 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7922 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7923 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7924
7925 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7926 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7927 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7928 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7929
7930 mode->flags = pipe_config->base.adjusted_mode.flags;
7931 mode->type = DRM_MODE_TYPE_DRIVER;
7932
7933 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7934 mode->flags |= pipe_config->base.adjusted_mode.flags;
7935
7936 mode->hsync = drm_mode_hsync(mode);
7937 mode->vrefresh = drm_mode_vrefresh(mode);
7938 drm_mode_set_name(mode);
7939 }
7940
7941 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7942 {
7943 struct drm_device *dev = intel_crtc->base.dev;
7944 struct drm_i915_private *dev_priv = dev->dev_private;
7945 uint32_t pipeconf;
7946
7947 pipeconf = 0;
7948
7949 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7950 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7951 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7952
7953 if (intel_crtc->config->double_wide)
7954 pipeconf |= PIPECONF_DOUBLE_WIDE;
7955
7956 /* only g4x and later have fancy bpc/dither controls */
7957 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7958 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7959 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7960 pipeconf |= PIPECONF_DITHER_EN |
7961 PIPECONF_DITHER_TYPE_SP;
7962
7963 switch (intel_crtc->config->pipe_bpp) {
7964 case 18:
7965 pipeconf |= PIPECONF_6BPC;
7966 break;
7967 case 24:
7968 pipeconf |= PIPECONF_8BPC;
7969 break;
7970 case 30:
7971 pipeconf |= PIPECONF_10BPC;
7972 break;
7973 default:
7974 /* Case prevented by intel_choose_pipe_bpp_dither. */
7975 BUG();
7976 }
7977 }
7978
7979 if (HAS_PIPE_CXSR(dev)) {
7980 if (intel_crtc->lowfreq_avail) {
7981 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7982 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7983 } else {
7984 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7985 }
7986 }
7987
7988 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7989 if (INTEL_INFO(dev)->gen < 4 ||
7990 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7991 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7992 else
7993 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7994 } else
7995 pipeconf |= PIPECONF_PROGRESSIVE;
7996
7997 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7998 intel_crtc->config->limited_color_range)
7999 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8000
8001 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8002 POSTING_READ(PIPECONF(intel_crtc->pipe));
8003 }
8004
8005 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8006 struct intel_crtc_state *crtc_state)
8007 {
8008 struct drm_device *dev = crtc->base.dev;
8009 struct drm_i915_private *dev_priv = dev->dev_private;
8010 int refclk, num_connectors = 0;
8011 intel_clock_t clock;
8012 bool ok;
8013 const intel_limit_t *limit;
8014 struct drm_atomic_state *state = crtc_state->base.state;
8015 struct drm_connector *connector;
8016 struct drm_connector_state *connector_state;
8017 int i;
8018
8019 memset(&crtc_state->dpll_hw_state, 0,
8020 sizeof(crtc_state->dpll_hw_state));
8021
8022 if (crtc_state->has_dsi_encoder)
8023 return 0;
8024
8025 for_each_connector_in_state(state, connector, connector_state, i) {
8026 if (connector_state->crtc == &crtc->base)
8027 num_connectors++;
8028 }
8029
8030 if (!crtc_state->clock_set) {
8031 refclk = i9xx_get_refclk(crtc_state, num_connectors);
8032
8033 /*
8034 * Returns a set of divisors for the desired target clock with
8035 * the given refclk, or FALSE. The returned values represent
8036 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
8037 * 2) / p1 / p2.
8038 */
8039 limit = intel_limit(crtc_state, refclk);
8040 ok = dev_priv->display.find_dpll(limit, crtc_state,
8041 crtc_state->port_clock,
8042 refclk, NULL, &clock);
8043 if (!ok) {
8044 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8045 return -EINVAL;
8046 }
8047
8048 /* Compat-code for transition, will disappear. */
8049 crtc_state->dpll.n = clock.n;
8050 crtc_state->dpll.m1 = clock.m1;
8051 crtc_state->dpll.m2 = clock.m2;
8052 crtc_state->dpll.p1 = clock.p1;
8053 crtc_state->dpll.p2 = clock.p2;
8054 }
8055
8056 if (IS_GEN2(dev)) {
8057 i8xx_compute_dpll(crtc, crtc_state, NULL,
8058 num_connectors);
8059 } else if (IS_CHERRYVIEW(dev)) {
8060 chv_compute_dpll(crtc, crtc_state);
8061 } else if (IS_VALLEYVIEW(dev)) {
8062 vlv_compute_dpll(crtc, crtc_state);
8063 } else {
8064 i9xx_compute_dpll(crtc, crtc_state, NULL,
8065 num_connectors);
8066 }
8067
8068 return 0;
8069 }
8070
8071 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8072 struct intel_crtc_state *pipe_config)
8073 {
8074 struct drm_device *dev = crtc->base.dev;
8075 struct drm_i915_private *dev_priv = dev->dev_private;
8076 uint32_t tmp;
8077
8078 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8079 return;
8080
8081 tmp = I915_READ(PFIT_CONTROL);
8082 if (!(tmp & PFIT_ENABLE))
8083 return;
8084
8085 /* Check whether the pfit is attached to our pipe. */
8086 if (INTEL_INFO(dev)->gen < 4) {
8087 if (crtc->pipe != PIPE_B)
8088 return;
8089 } else {
8090 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8091 return;
8092 }
8093
8094 pipe_config->gmch_pfit.control = tmp;
8095 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8096 if (INTEL_INFO(dev)->gen < 5)
8097 pipe_config->gmch_pfit.lvds_border_bits =
8098 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8099 }
8100
8101 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8102 struct intel_crtc_state *pipe_config)
8103 {
8104 struct drm_device *dev = crtc->base.dev;
8105 struct drm_i915_private *dev_priv = dev->dev_private;
8106 int pipe = pipe_config->cpu_transcoder;
8107 intel_clock_t clock;
8108 u32 mdiv;
8109 int refclk = 100000;
8110
8111 /* In case of MIPI DPLL will not even be used */
8112 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8113 return;
8114
8115 mutex_lock(&dev_priv->sb_lock);
8116 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8117 mutex_unlock(&dev_priv->sb_lock);
8118
8119 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8120 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8121 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8122 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8123 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8124
8125 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8126 }
8127
8128 static void
8129 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8130 struct intel_initial_plane_config *plane_config)
8131 {
8132 struct drm_device *dev = crtc->base.dev;
8133 struct drm_i915_private *dev_priv = dev->dev_private;
8134 u32 val, base, offset;
8135 int pipe = crtc->pipe, plane = crtc->plane;
8136 int fourcc, pixel_format;
8137 unsigned int aligned_height;
8138 struct drm_framebuffer *fb;
8139 struct intel_framebuffer *intel_fb;
8140
8141 val = I915_READ(DSPCNTR(plane));
8142 if (!(val & DISPLAY_PLANE_ENABLE))
8143 return;
8144
8145 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8146 if (!intel_fb) {
8147 DRM_DEBUG_KMS("failed to alloc fb\n");
8148 return;
8149 }
8150
8151 fb = &intel_fb->base;
8152
8153 if (INTEL_INFO(dev)->gen >= 4) {
8154 if (val & DISPPLANE_TILED) {
8155 plane_config->tiling = I915_TILING_X;
8156 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8157 }
8158 }
8159
8160 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8161 fourcc = i9xx_format_to_fourcc(pixel_format);
8162 fb->pixel_format = fourcc;
8163 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8164
8165 if (INTEL_INFO(dev)->gen >= 4) {
8166 if (plane_config->tiling)
8167 offset = I915_READ(DSPTILEOFF(plane));
8168 else
8169 offset = I915_READ(DSPLINOFF(plane));
8170 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8171 } else {
8172 base = I915_READ(DSPADDR(plane));
8173 }
8174 plane_config->base = base;
8175
8176 val = I915_READ(PIPESRC(pipe));
8177 fb->width = ((val >> 16) & 0xfff) + 1;
8178 fb->height = ((val >> 0) & 0xfff) + 1;
8179
8180 val = I915_READ(DSPSTRIDE(pipe));
8181 fb->pitches[0] = val & 0xffffffc0;
8182
8183 aligned_height = intel_fb_align_height(dev, fb->height,
8184 fb->pixel_format,
8185 fb->modifier[0]);
8186
8187 plane_config->size = fb->pitches[0] * aligned_height;
8188
8189 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8190 pipe_name(pipe), plane, fb->width, fb->height,
8191 fb->bits_per_pixel, base, fb->pitches[0],
8192 plane_config->size);
8193
8194 plane_config->fb = intel_fb;
8195 }
8196
8197 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8198 struct intel_crtc_state *pipe_config)
8199 {
8200 struct drm_device *dev = crtc->base.dev;
8201 struct drm_i915_private *dev_priv = dev->dev_private;
8202 int pipe = pipe_config->cpu_transcoder;
8203 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8204 intel_clock_t clock;
8205 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8206 int refclk = 100000;
8207
8208 mutex_lock(&dev_priv->sb_lock);
8209 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8210 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8211 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8212 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8213 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8214 mutex_unlock(&dev_priv->sb_lock);
8215
8216 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8217 clock.m2 = (pll_dw0 & 0xff) << 22;
8218 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8219 clock.m2 |= pll_dw2 & 0x3fffff;
8220 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8221 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8222 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8223
8224 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8225 }
8226
8227 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8228 struct intel_crtc_state *pipe_config)
8229 {
8230 struct drm_device *dev = crtc->base.dev;
8231 struct drm_i915_private *dev_priv = dev->dev_private;
8232 enum intel_display_power_domain power_domain;
8233 uint32_t tmp;
8234 bool ret;
8235
8236 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8237 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8238 return false;
8239
8240 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8241 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8242
8243 ret = false;
8244
8245 tmp = I915_READ(PIPECONF(crtc->pipe));
8246 if (!(tmp & PIPECONF_ENABLE))
8247 goto out;
8248
8249 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8250 switch (tmp & PIPECONF_BPC_MASK) {
8251 case PIPECONF_6BPC:
8252 pipe_config->pipe_bpp = 18;
8253 break;
8254 case PIPECONF_8BPC:
8255 pipe_config->pipe_bpp = 24;
8256 break;
8257 case PIPECONF_10BPC:
8258 pipe_config->pipe_bpp = 30;
8259 break;
8260 default:
8261 break;
8262 }
8263 }
8264
8265 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8266 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8267 pipe_config->limited_color_range = true;
8268
8269 if (INTEL_INFO(dev)->gen < 4)
8270 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8271
8272 intel_get_pipe_timings(crtc, pipe_config);
8273
8274 i9xx_get_pfit_config(crtc, pipe_config);
8275
8276 if (INTEL_INFO(dev)->gen >= 4) {
8277 tmp = I915_READ(DPLL_MD(crtc->pipe));
8278 pipe_config->pixel_multiplier =
8279 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8280 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8281 pipe_config->dpll_hw_state.dpll_md = tmp;
8282 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8283 tmp = I915_READ(DPLL(crtc->pipe));
8284 pipe_config->pixel_multiplier =
8285 ((tmp & SDVO_MULTIPLIER_MASK)
8286 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8287 } else {
8288 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8289 * port and will be fixed up in the encoder->get_config
8290 * function. */
8291 pipe_config->pixel_multiplier = 1;
8292 }
8293 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8294 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8295 /*
8296 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8297 * on 830. Filter it out here so that we don't
8298 * report errors due to that.
8299 */
8300 if (IS_I830(dev))
8301 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8302
8303 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8304 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8305 } else {
8306 /* Mask out read-only status bits. */
8307 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8308 DPLL_PORTC_READY_MASK |
8309 DPLL_PORTB_READY_MASK);
8310 }
8311
8312 if (IS_CHERRYVIEW(dev))
8313 chv_crtc_clock_get(crtc, pipe_config);
8314 else if (IS_VALLEYVIEW(dev))
8315 vlv_crtc_clock_get(crtc, pipe_config);
8316 else
8317 i9xx_crtc_clock_get(crtc, pipe_config);
8318
8319 /*
8320 * Normally the dotclock is filled in by the encoder .get_config()
8321 * but in case the pipe is enabled w/o any ports we need a sane
8322 * default.
8323 */
8324 pipe_config->base.adjusted_mode.crtc_clock =
8325 pipe_config->port_clock / pipe_config->pixel_multiplier;
8326
8327 ret = true;
8328
8329 out:
8330 intel_display_power_put(dev_priv, power_domain);
8331
8332 return ret;
8333 }
8334
8335 static void ironlake_init_pch_refclk(struct drm_device *dev)
8336 {
8337 struct drm_i915_private *dev_priv = dev->dev_private;
8338 struct intel_encoder *encoder;
8339 u32 val, final;
8340 bool has_lvds = false;
8341 bool has_cpu_edp = false;
8342 bool has_panel = false;
8343 bool has_ck505 = false;
8344 bool can_ssc = false;
8345
8346 /* We need to take the global config into account */
8347 for_each_intel_encoder(dev, encoder) {
8348 switch (encoder->type) {
8349 case INTEL_OUTPUT_LVDS:
8350 has_panel = true;
8351 has_lvds = true;
8352 break;
8353 case INTEL_OUTPUT_EDP:
8354 has_panel = true;
8355 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8356 has_cpu_edp = true;
8357 break;
8358 default:
8359 break;
8360 }
8361 }
8362
8363 if (HAS_PCH_IBX(dev)) {
8364 has_ck505 = dev_priv->vbt.display_clock_mode;
8365 can_ssc = has_ck505;
8366 } else {
8367 has_ck505 = false;
8368 can_ssc = true;
8369 }
8370
8371 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8372 has_panel, has_lvds, has_ck505);
8373
8374 /* Ironlake: try to setup display ref clock before DPLL
8375 * enabling. This is only under driver's control after
8376 * PCH B stepping, previous chipset stepping should be
8377 * ignoring this setting.
8378 */
8379 val = I915_READ(PCH_DREF_CONTROL);
8380
8381 /* As we must carefully and slowly disable/enable each source in turn,
8382 * compute the final state we want first and check if we need to
8383 * make any changes at all.
8384 */
8385 final = val;
8386 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8387 if (has_ck505)
8388 final |= DREF_NONSPREAD_CK505_ENABLE;
8389 else
8390 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8391
8392 final &= ~DREF_SSC_SOURCE_MASK;
8393 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8394 final &= ~DREF_SSC1_ENABLE;
8395
8396 if (has_panel) {
8397 final |= DREF_SSC_SOURCE_ENABLE;
8398
8399 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8400 final |= DREF_SSC1_ENABLE;
8401
8402 if (has_cpu_edp) {
8403 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8404 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8405 else
8406 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8407 } else
8408 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8409 } else {
8410 final |= DREF_SSC_SOURCE_DISABLE;
8411 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8412 }
8413
8414 if (final == val)
8415 return;
8416
8417 /* Always enable nonspread source */
8418 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8419
8420 if (has_ck505)
8421 val |= DREF_NONSPREAD_CK505_ENABLE;
8422 else
8423 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8424
8425 if (has_panel) {
8426 val &= ~DREF_SSC_SOURCE_MASK;
8427 val |= DREF_SSC_SOURCE_ENABLE;
8428
8429 /* SSC must be turned on before enabling the CPU output */
8430 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8431 DRM_DEBUG_KMS("Using SSC on panel\n");
8432 val |= DREF_SSC1_ENABLE;
8433 } else
8434 val &= ~DREF_SSC1_ENABLE;
8435
8436 /* Get SSC going before enabling the outputs */
8437 I915_WRITE(PCH_DREF_CONTROL, val);
8438 POSTING_READ(PCH_DREF_CONTROL);
8439 udelay(200);
8440
8441 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8442
8443 /* Enable CPU source on CPU attached eDP */
8444 if (has_cpu_edp) {
8445 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8446 DRM_DEBUG_KMS("Using SSC on eDP\n");
8447 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8448 } else
8449 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8450 } else
8451 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8452
8453 I915_WRITE(PCH_DREF_CONTROL, val);
8454 POSTING_READ(PCH_DREF_CONTROL);
8455 udelay(200);
8456 } else {
8457 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8458
8459 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8460
8461 /* Turn off CPU output */
8462 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8463
8464 I915_WRITE(PCH_DREF_CONTROL, val);
8465 POSTING_READ(PCH_DREF_CONTROL);
8466 udelay(200);
8467
8468 /* Turn off the SSC source */
8469 val &= ~DREF_SSC_SOURCE_MASK;
8470 val |= DREF_SSC_SOURCE_DISABLE;
8471
8472 /* Turn off SSC1 */
8473 val &= ~DREF_SSC1_ENABLE;
8474
8475 I915_WRITE(PCH_DREF_CONTROL, val);
8476 POSTING_READ(PCH_DREF_CONTROL);
8477 udelay(200);
8478 }
8479
8480 BUG_ON(val != final);
8481 }
8482
8483 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8484 {
8485 uint32_t tmp;
8486
8487 tmp = I915_READ(SOUTH_CHICKEN2);
8488 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8489 I915_WRITE(SOUTH_CHICKEN2, tmp);
8490
8491 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8492 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8493 DRM_ERROR("FDI mPHY reset assert timeout\n");
8494
8495 tmp = I915_READ(SOUTH_CHICKEN2);
8496 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8497 I915_WRITE(SOUTH_CHICKEN2, tmp);
8498
8499 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8500 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8501 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8502 }
8503
8504 /* WaMPhyProgramming:hsw */
8505 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8506 {
8507 uint32_t tmp;
8508
8509 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8510 tmp &= ~(0xFF << 24);
8511 tmp |= (0x12 << 24);
8512 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8513
8514 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8515 tmp |= (1 << 11);
8516 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8517
8518 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8519 tmp |= (1 << 11);
8520 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8521
8522 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8523 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8524 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8525
8526 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8527 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8528 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8529
8530 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8531 tmp &= ~(7 << 13);
8532 tmp |= (5 << 13);
8533 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8534
8535 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8536 tmp &= ~(7 << 13);
8537 tmp |= (5 << 13);
8538 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8539
8540 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8541 tmp &= ~0xFF;
8542 tmp |= 0x1C;
8543 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8544
8545 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8546 tmp &= ~0xFF;
8547 tmp |= 0x1C;
8548 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8549
8550 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8551 tmp &= ~(0xFF << 16);
8552 tmp |= (0x1C << 16);
8553 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8554
8555 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8556 tmp &= ~(0xFF << 16);
8557 tmp |= (0x1C << 16);
8558 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8559
8560 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8561 tmp |= (1 << 27);
8562 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8563
8564 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8565 tmp |= (1 << 27);
8566 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8567
8568 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8569 tmp &= ~(0xF << 28);
8570 tmp |= (4 << 28);
8571 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8572
8573 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8574 tmp &= ~(0xF << 28);
8575 tmp |= (4 << 28);
8576 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8577 }
8578
8579 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8580 * Programming" based on the parameters passed:
8581 * - Sequence to enable CLKOUT_DP
8582 * - Sequence to enable CLKOUT_DP without spread
8583 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8584 */
8585 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8586 bool with_fdi)
8587 {
8588 struct drm_i915_private *dev_priv = dev->dev_private;
8589 uint32_t reg, tmp;
8590
8591 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8592 with_spread = true;
8593 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8594 with_fdi = false;
8595
8596 mutex_lock(&dev_priv->sb_lock);
8597
8598 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8599 tmp &= ~SBI_SSCCTL_DISABLE;
8600 tmp |= SBI_SSCCTL_PATHALT;
8601 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8602
8603 udelay(24);
8604
8605 if (with_spread) {
8606 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8607 tmp &= ~SBI_SSCCTL_PATHALT;
8608 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8609
8610 if (with_fdi) {
8611 lpt_reset_fdi_mphy(dev_priv);
8612 lpt_program_fdi_mphy(dev_priv);
8613 }
8614 }
8615
8616 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8617 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8618 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8619 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8620
8621 mutex_unlock(&dev_priv->sb_lock);
8622 }
8623
8624 /* Sequence to disable CLKOUT_DP */
8625 static void lpt_disable_clkout_dp(struct drm_device *dev)
8626 {
8627 struct drm_i915_private *dev_priv = dev->dev_private;
8628 uint32_t reg, tmp;
8629
8630 mutex_lock(&dev_priv->sb_lock);
8631
8632 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8633 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8634 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8635 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8636
8637 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8638 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8639 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8640 tmp |= SBI_SSCCTL_PATHALT;
8641 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8642 udelay(32);
8643 }
8644 tmp |= SBI_SSCCTL_DISABLE;
8645 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8646 }
8647
8648 mutex_unlock(&dev_priv->sb_lock);
8649 }
8650
8651 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8652
8653 static const uint16_t sscdivintphase[] = {
8654 [BEND_IDX( 50)] = 0x3B23,
8655 [BEND_IDX( 45)] = 0x3B23,
8656 [BEND_IDX( 40)] = 0x3C23,
8657 [BEND_IDX( 35)] = 0x3C23,
8658 [BEND_IDX( 30)] = 0x3D23,
8659 [BEND_IDX( 25)] = 0x3D23,
8660 [BEND_IDX( 20)] = 0x3E23,
8661 [BEND_IDX( 15)] = 0x3E23,
8662 [BEND_IDX( 10)] = 0x3F23,
8663 [BEND_IDX( 5)] = 0x3F23,
8664 [BEND_IDX( 0)] = 0x0025,
8665 [BEND_IDX( -5)] = 0x0025,
8666 [BEND_IDX(-10)] = 0x0125,
8667 [BEND_IDX(-15)] = 0x0125,
8668 [BEND_IDX(-20)] = 0x0225,
8669 [BEND_IDX(-25)] = 0x0225,
8670 [BEND_IDX(-30)] = 0x0325,
8671 [BEND_IDX(-35)] = 0x0325,
8672 [BEND_IDX(-40)] = 0x0425,
8673 [BEND_IDX(-45)] = 0x0425,
8674 [BEND_IDX(-50)] = 0x0525,
8675 };
8676
8677 /*
8678 * Bend CLKOUT_DP
8679 * steps -50 to 50 inclusive, in steps of 5
8680 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8681 * change in clock period = -(steps / 10) * 5.787 ps
8682 */
8683 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8684 {
8685 uint32_t tmp;
8686 int idx = BEND_IDX(steps);
8687
8688 if (WARN_ON(steps % 5 != 0))
8689 return;
8690
8691 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8692 return;
8693
8694 mutex_lock(&dev_priv->sb_lock);
8695
8696 if (steps % 10 != 0)
8697 tmp = 0xAAAAAAAB;
8698 else
8699 tmp = 0x00000000;
8700 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8701
8702 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8703 tmp &= 0xffff0000;
8704 tmp |= sscdivintphase[idx];
8705 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8706
8707 mutex_unlock(&dev_priv->sb_lock);
8708 }
8709
8710 #undef BEND_IDX
8711
8712 static void lpt_init_pch_refclk(struct drm_device *dev)
8713 {
8714 struct intel_encoder *encoder;
8715 bool has_vga = false;
8716
8717 for_each_intel_encoder(dev, encoder) {
8718 switch (encoder->type) {
8719 case INTEL_OUTPUT_ANALOG:
8720 has_vga = true;
8721 break;
8722 default:
8723 break;
8724 }
8725 }
8726
8727 if (has_vga) {
8728 lpt_bend_clkout_dp(to_i915(dev), 0);
8729 lpt_enable_clkout_dp(dev, true, true);
8730 } else {
8731 lpt_disable_clkout_dp(dev);
8732 }
8733 }
8734
8735 /*
8736 * Initialize reference clocks when the driver loads
8737 */
8738 void intel_init_pch_refclk(struct drm_device *dev)
8739 {
8740 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8741 ironlake_init_pch_refclk(dev);
8742 else if (HAS_PCH_LPT(dev))
8743 lpt_init_pch_refclk(dev);
8744 }
8745
8746 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8747 {
8748 struct drm_device *dev = crtc_state->base.crtc->dev;
8749 struct drm_i915_private *dev_priv = dev->dev_private;
8750 struct drm_atomic_state *state = crtc_state->base.state;
8751 struct drm_connector *connector;
8752 struct drm_connector_state *connector_state;
8753 struct intel_encoder *encoder;
8754 int num_connectors = 0, i;
8755 bool is_lvds = false;
8756
8757 for_each_connector_in_state(state, connector, connector_state, i) {
8758 if (connector_state->crtc != crtc_state->base.crtc)
8759 continue;
8760
8761 encoder = to_intel_encoder(connector_state->best_encoder);
8762
8763 switch (encoder->type) {
8764 case INTEL_OUTPUT_LVDS:
8765 is_lvds = true;
8766 break;
8767 default:
8768 break;
8769 }
8770 num_connectors++;
8771 }
8772
8773 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8774 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8775 dev_priv->vbt.lvds_ssc_freq);
8776 return dev_priv->vbt.lvds_ssc_freq;
8777 }
8778
8779 return 120000;
8780 }
8781
8782 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8783 {
8784 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8786 int pipe = intel_crtc->pipe;
8787 uint32_t val;
8788
8789 val = 0;
8790
8791 switch (intel_crtc->config->pipe_bpp) {
8792 case 18:
8793 val |= PIPECONF_6BPC;
8794 break;
8795 case 24:
8796 val |= PIPECONF_8BPC;
8797 break;
8798 case 30:
8799 val |= PIPECONF_10BPC;
8800 break;
8801 case 36:
8802 val |= PIPECONF_12BPC;
8803 break;
8804 default:
8805 /* Case prevented by intel_choose_pipe_bpp_dither. */
8806 BUG();
8807 }
8808
8809 if (intel_crtc->config->dither)
8810 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8811
8812 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8813 val |= PIPECONF_INTERLACED_ILK;
8814 else
8815 val |= PIPECONF_PROGRESSIVE;
8816
8817 if (intel_crtc->config->limited_color_range)
8818 val |= PIPECONF_COLOR_RANGE_SELECT;
8819
8820 I915_WRITE(PIPECONF(pipe), val);
8821 POSTING_READ(PIPECONF(pipe));
8822 }
8823
8824 /*
8825 * Set up the pipe CSC unit.
8826 *
8827 * Currently only full range RGB to limited range RGB conversion
8828 * is supported, but eventually this should handle various
8829 * RGB<->YCbCr scenarios as well.
8830 */
8831 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8832 {
8833 struct drm_device *dev = crtc->dev;
8834 struct drm_i915_private *dev_priv = dev->dev_private;
8835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8836 int pipe = intel_crtc->pipe;
8837 uint16_t coeff = 0x7800; /* 1.0 */
8838
8839 /*
8840 * TODO: Check what kind of values actually come out of the pipe
8841 * with these coeff/postoff values and adjust to get the best
8842 * accuracy. Perhaps we even need to take the bpc value into
8843 * consideration.
8844 */
8845
8846 if (intel_crtc->config->limited_color_range)
8847 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8848
8849 /*
8850 * GY/GU and RY/RU should be the other way around according
8851 * to BSpec, but reality doesn't agree. Just set them up in
8852 * a way that results in the correct picture.
8853 */
8854 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8855 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8856
8857 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8858 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8859
8860 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8861 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8862
8863 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8864 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8865 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8866
8867 if (INTEL_INFO(dev)->gen > 6) {
8868 uint16_t postoff = 0;
8869
8870 if (intel_crtc->config->limited_color_range)
8871 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8872
8873 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8874 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8875 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8876
8877 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8878 } else {
8879 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8880
8881 if (intel_crtc->config->limited_color_range)
8882 mode |= CSC_BLACK_SCREEN_OFFSET;
8883
8884 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8885 }
8886 }
8887
8888 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8889 {
8890 struct drm_device *dev = crtc->dev;
8891 struct drm_i915_private *dev_priv = dev->dev_private;
8892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8893 enum pipe pipe = intel_crtc->pipe;
8894 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8895 uint32_t val;
8896
8897 val = 0;
8898
8899 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8900 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8901
8902 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8903 val |= PIPECONF_INTERLACED_ILK;
8904 else
8905 val |= PIPECONF_PROGRESSIVE;
8906
8907 I915_WRITE(PIPECONF(cpu_transcoder), val);
8908 POSTING_READ(PIPECONF(cpu_transcoder));
8909
8910 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8911 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8912
8913 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8914 val = 0;
8915
8916 switch (intel_crtc->config->pipe_bpp) {
8917 case 18:
8918 val |= PIPEMISC_DITHER_6_BPC;
8919 break;
8920 case 24:
8921 val |= PIPEMISC_DITHER_8_BPC;
8922 break;
8923 case 30:
8924 val |= PIPEMISC_DITHER_10_BPC;
8925 break;
8926 case 36:
8927 val |= PIPEMISC_DITHER_12_BPC;
8928 break;
8929 default:
8930 /* Case prevented by pipe_config_set_bpp. */
8931 BUG();
8932 }
8933
8934 if (intel_crtc->config->dither)
8935 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8936
8937 I915_WRITE(PIPEMISC(pipe), val);
8938 }
8939 }
8940
8941 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8942 struct intel_crtc_state *crtc_state,
8943 intel_clock_t *clock,
8944 bool *has_reduced_clock,
8945 intel_clock_t *reduced_clock)
8946 {
8947 struct drm_device *dev = crtc->dev;
8948 struct drm_i915_private *dev_priv = dev->dev_private;
8949 int refclk;
8950 const intel_limit_t *limit;
8951 bool ret;
8952
8953 refclk = ironlake_get_refclk(crtc_state);
8954
8955 /*
8956 * Returns a set of divisors for the desired target clock with the given
8957 * refclk, or FALSE. The returned values represent the clock equation:
8958 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8959 */
8960 limit = intel_limit(crtc_state, refclk);
8961 ret = dev_priv->display.find_dpll(limit, crtc_state,
8962 crtc_state->port_clock,
8963 refclk, NULL, clock);
8964 if (!ret)
8965 return false;
8966
8967 return true;
8968 }
8969
8970 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8971 {
8972 /*
8973 * Account for spread spectrum to avoid
8974 * oversubscribing the link. Max center spread
8975 * is 2.5%; use 5% for safety's sake.
8976 */
8977 u32 bps = target_clock * bpp * 21 / 20;
8978 return DIV_ROUND_UP(bps, link_bw * 8);
8979 }
8980
8981 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8982 {
8983 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8984 }
8985
8986 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8987 struct intel_crtc_state *crtc_state,
8988 u32 *fp,
8989 intel_clock_t *reduced_clock, u32 *fp2)
8990 {
8991 struct drm_crtc *crtc = &intel_crtc->base;
8992 struct drm_device *dev = crtc->dev;
8993 struct drm_i915_private *dev_priv = dev->dev_private;
8994 struct drm_atomic_state *state = crtc_state->base.state;
8995 struct drm_connector *connector;
8996 struct drm_connector_state *connector_state;
8997 struct intel_encoder *encoder;
8998 uint32_t dpll;
8999 int factor, num_connectors = 0, i;
9000 bool is_lvds = false, is_sdvo = false;
9001
9002 for_each_connector_in_state(state, connector, connector_state, i) {
9003 if (connector_state->crtc != crtc_state->base.crtc)
9004 continue;
9005
9006 encoder = to_intel_encoder(connector_state->best_encoder);
9007
9008 switch (encoder->type) {
9009 case INTEL_OUTPUT_LVDS:
9010 is_lvds = true;
9011 break;
9012 case INTEL_OUTPUT_SDVO:
9013 case INTEL_OUTPUT_HDMI:
9014 is_sdvo = true;
9015 break;
9016 default:
9017 break;
9018 }
9019
9020 num_connectors++;
9021 }
9022
9023 /* Enable autotuning of the PLL clock (if permissible) */
9024 factor = 21;
9025 if (is_lvds) {
9026 if ((intel_panel_use_ssc(dev_priv) &&
9027 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9028 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9029 factor = 25;
9030 } else if (crtc_state->sdvo_tv_clock)
9031 factor = 20;
9032
9033 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9034 *fp |= FP_CB_TUNE;
9035
9036 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
9037 *fp2 |= FP_CB_TUNE;
9038
9039 dpll = 0;
9040
9041 if (is_lvds)
9042 dpll |= DPLLB_MODE_LVDS;
9043 else
9044 dpll |= DPLLB_MODE_DAC_SERIAL;
9045
9046 dpll |= (crtc_state->pixel_multiplier - 1)
9047 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9048
9049 if (is_sdvo)
9050 dpll |= DPLL_SDVO_HIGH_SPEED;
9051 if (crtc_state->has_dp_encoder)
9052 dpll |= DPLL_SDVO_HIGH_SPEED;
9053
9054 /* compute bitmask from p1 value */
9055 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9056 /* also FPA1 */
9057 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9058
9059 switch (crtc_state->dpll.p2) {
9060 case 5:
9061 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9062 break;
9063 case 7:
9064 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9065 break;
9066 case 10:
9067 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9068 break;
9069 case 14:
9070 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9071 break;
9072 }
9073
9074 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
9075 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9076 else
9077 dpll |= PLL_REF_INPUT_DREFCLK;
9078
9079 return dpll | DPLL_VCO_ENABLE;
9080 }
9081
9082 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9083 struct intel_crtc_state *crtc_state)
9084 {
9085 struct drm_device *dev = crtc->base.dev;
9086 intel_clock_t clock, reduced_clock;
9087 u32 dpll = 0, fp = 0, fp2 = 0;
9088 bool ok, has_reduced_clock = false;
9089 bool is_lvds = false;
9090 struct intel_shared_dpll *pll;
9091
9092 memset(&crtc_state->dpll_hw_state, 0,
9093 sizeof(crtc_state->dpll_hw_state));
9094
9095 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
9096
9097 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9098 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9099
9100 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
9101 &has_reduced_clock, &reduced_clock);
9102 if (!ok && !crtc_state->clock_set) {
9103 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9104 return -EINVAL;
9105 }
9106 /* Compat-code for transition, will disappear. */
9107 if (!crtc_state->clock_set) {
9108 crtc_state->dpll.n = clock.n;
9109 crtc_state->dpll.m1 = clock.m1;
9110 crtc_state->dpll.m2 = clock.m2;
9111 crtc_state->dpll.p1 = clock.p1;
9112 crtc_state->dpll.p2 = clock.p2;
9113 }
9114
9115 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9116 if (crtc_state->has_pch_encoder) {
9117 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9118 if (has_reduced_clock)
9119 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9120
9121 dpll = ironlake_compute_dpll(crtc, crtc_state,
9122 &fp, &reduced_clock,
9123 has_reduced_clock ? &fp2 : NULL);
9124
9125 crtc_state->dpll_hw_state.dpll = dpll;
9126 crtc_state->dpll_hw_state.fp0 = fp;
9127 if (has_reduced_clock)
9128 crtc_state->dpll_hw_state.fp1 = fp2;
9129 else
9130 crtc_state->dpll_hw_state.fp1 = fp;
9131
9132 pll = intel_get_shared_dpll(crtc, crtc_state);
9133 if (pll == NULL) {
9134 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9135 pipe_name(crtc->pipe));
9136 return -EINVAL;
9137 }
9138 }
9139
9140 if (is_lvds && has_reduced_clock)
9141 crtc->lowfreq_avail = true;
9142 else
9143 crtc->lowfreq_avail = false;
9144
9145 return 0;
9146 }
9147
9148 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9149 struct intel_link_m_n *m_n)
9150 {
9151 struct drm_device *dev = crtc->base.dev;
9152 struct drm_i915_private *dev_priv = dev->dev_private;
9153 enum pipe pipe = crtc->pipe;
9154
9155 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9156 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9157 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9158 & ~TU_SIZE_MASK;
9159 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9160 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9161 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9162 }
9163
9164 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9165 enum transcoder transcoder,
9166 struct intel_link_m_n *m_n,
9167 struct intel_link_m_n *m2_n2)
9168 {
9169 struct drm_device *dev = crtc->base.dev;
9170 struct drm_i915_private *dev_priv = dev->dev_private;
9171 enum pipe pipe = crtc->pipe;
9172
9173 if (INTEL_INFO(dev)->gen >= 5) {
9174 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9175 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9176 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9177 & ~TU_SIZE_MASK;
9178 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9179 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9180 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9181 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9182 * gen < 8) and if DRRS is supported (to make sure the
9183 * registers are not unnecessarily read).
9184 */
9185 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9186 crtc->config->has_drrs) {
9187 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9188 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9189 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9190 & ~TU_SIZE_MASK;
9191 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9192 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9193 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9194 }
9195 } else {
9196 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9197 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9198 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9199 & ~TU_SIZE_MASK;
9200 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9201 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9202 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9203 }
9204 }
9205
9206 void intel_dp_get_m_n(struct intel_crtc *crtc,
9207 struct intel_crtc_state *pipe_config)
9208 {
9209 if (pipe_config->has_pch_encoder)
9210 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9211 else
9212 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9213 &pipe_config->dp_m_n,
9214 &pipe_config->dp_m2_n2);
9215 }
9216
9217 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9218 struct intel_crtc_state *pipe_config)
9219 {
9220 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9221 &pipe_config->fdi_m_n, NULL);
9222 }
9223
9224 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9225 struct intel_crtc_state *pipe_config)
9226 {
9227 struct drm_device *dev = crtc->base.dev;
9228 struct drm_i915_private *dev_priv = dev->dev_private;
9229 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9230 uint32_t ps_ctrl = 0;
9231 int id = -1;
9232 int i;
9233
9234 /* find scaler attached to this pipe */
9235 for (i = 0; i < crtc->num_scalers; i++) {
9236 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9237 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9238 id = i;
9239 pipe_config->pch_pfit.enabled = true;
9240 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9241 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9242 break;
9243 }
9244 }
9245
9246 scaler_state->scaler_id = id;
9247 if (id >= 0) {
9248 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9249 } else {
9250 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9251 }
9252 }
9253
9254 static void
9255 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9256 struct intel_initial_plane_config *plane_config)
9257 {
9258 struct drm_device *dev = crtc->base.dev;
9259 struct drm_i915_private *dev_priv = dev->dev_private;
9260 u32 val, base, offset, stride_mult, tiling;
9261 int pipe = crtc->pipe;
9262 int fourcc, pixel_format;
9263 unsigned int aligned_height;
9264 struct drm_framebuffer *fb;
9265 struct intel_framebuffer *intel_fb;
9266
9267 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9268 if (!intel_fb) {
9269 DRM_DEBUG_KMS("failed to alloc fb\n");
9270 return;
9271 }
9272
9273 fb = &intel_fb->base;
9274
9275 val = I915_READ(PLANE_CTL(pipe, 0));
9276 if (!(val & PLANE_CTL_ENABLE))
9277 goto error;
9278
9279 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9280 fourcc = skl_format_to_fourcc(pixel_format,
9281 val & PLANE_CTL_ORDER_RGBX,
9282 val & PLANE_CTL_ALPHA_MASK);
9283 fb->pixel_format = fourcc;
9284 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9285
9286 tiling = val & PLANE_CTL_TILED_MASK;
9287 switch (tiling) {
9288 case PLANE_CTL_TILED_LINEAR:
9289 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9290 break;
9291 case PLANE_CTL_TILED_X:
9292 plane_config->tiling = I915_TILING_X;
9293 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9294 break;
9295 case PLANE_CTL_TILED_Y:
9296 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9297 break;
9298 case PLANE_CTL_TILED_YF:
9299 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9300 break;
9301 default:
9302 MISSING_CASE(tiling);
9303 goto error;
9304 }
9305
9306 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9307 plane_config->base = base;
9308
9309 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9310
9311 val = I915_READ(PLANE_SIZE(pipe, 0));
9312 fb->height = ((val >> 16) & 0xfff) + 1;
9313 fb->width = ((val >> 0) & 0x1fff) + 1;
9314
9315 val = I915_READ(PLANE_STRIDE(pipe, 0));
9316 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9317 fb->pixel_format);
9318 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9319
9320 aligned_height = intel_fb_align_height(dev, fb->height,
9321 fb->pixel_format,
9322 fb->modifier[0]);
9323
9324 plane_config->size = fb->pitches[0] * aligned_height;
9325
9326 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9327 pipe_name(pipe), fb->width, fb->height,
9328 fb->bits_per_pixel, base, fb->pitches[0],
9329 plane_config->size);
9330
9331 plane_config->fb = intel_fb;
9332 return;
9333
9334 error:
9335 kfree(fb);
9336 }
9337
9338 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9339 struct intel_crtc_state *pipe_config)
9340 {
9341 struct drm_device *dev = crtc->base.dev;
9342 struct drm_i915_private *dev_priv = dev->dev_private;
9343 uint32_t tmp;
9344
9345 tmp = I915_READ(PF_CTL(crtc->pipe));
9346
9347 if (tmp & PF_ENABLE) {
9348 pipe_config->pch_pfit.enabled = true;
9349 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9350 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9351
9352 /* We currently do not free assignements of panel fitters on
9353 * ivb/hsw (since we don't use the higher upscaling modes which
9354 * differentiates them) so just WARN about this case for now. */
9355 if (IS_GEN7(dev)) {
9356 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9357 PF_PIPE_SEL_IVB(crtc->pipe));
9358 }
9359 }
9360 }
9361
9362 static void
9363 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9364 struct intel_initial_plane_config *plane_config)
9365 {
9366 struct drm_device *dev = crtc->base.dev;
9367 struct drm_i915_private *dev_priv = dev->dev_private;
9368 u32 val, base, offset;
9369 int pipe = crtc->pipe;
9370 int fourcc, pixel_format;
9371 unsigned int aligned_height;
9372 struct drm_framebuffer *fb;
9373 struct intel_framebuffer *intel_fb;
9374
9375 val = I915_READ(DSPCNTR(pipe));
9376 if (!(val & DISPLAY_PLANE_ENABLE))
9377 return;
9378
9379 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9380 if (!intel_fb) {
9381 DRM_DEBUG_KMS("failed to alloc fb\n");
9382 return;
9383 }
9384
9385 fb = &intel_fb->base;
9386
9387 if (INTEL_INFO(dev)->gen >= 4) {
9388 if (val & DISPPLANE_TILED) {
9389 plane_config->tiling = I915_TILING_X;
9390 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9391 }
9392 }
9393
9394 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9395 fourcc = i9xx_format_to_fourcc(pixel_format);
9396 fb->pixel_format = fourcc;
9397 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9398
9399 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9400 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9401 offset = I915_READ(DSPOFFSET(pipe));
9402 } else {
9403 if (plane_config->tiling)
9404 offset = I915_READ(DSPTILEOFF(pipe));
9405 else
9406 offset = I915_READ(DSPLINOFF(pipe));
9407 }
9408 plane_config->base = base;
9409
9410 val = I915_READ(PIPESRC(pipe));
9411 fb->width = ((val >> 16) & 0xfff) + 1;
9412 fb->height = ((val >> 0) & 0xfff) + 1;
9413
9414 val = I915_READ(DSPSTRIDE(pipe));
9415 fb->pitches[0] = val & 0xffffffc0;
9416
9417 aligned_height = intel_fb_align_height(dev, fb->height,
9418 fb->pixel_format,
9419 fb->modifier[0]);
9420
9421 plane_config->size = fb->pitches[0] * aligned_height;
9422
9423 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9424 pipe_name(pipe), fb->width, fb->height,
9425 fb->bits_per_pixel, base, fb->pitches[0],
9426 plane_config->size);
9427
9428 plane_config->fb = intel_fb;
9429 }
9430
9431 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9432 struct intel_crtc_state *pipe_config)
9433 {
9434 struct drm_device *dev = crtc->base.dev;
9435 struct drm_i915_private *dev_priv = dev->dev_private;
9436 enum intel_display_power_domain power_domain;
9437 uint32_t tmp;
9438 bool ret;
9439
9440 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9441 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9442 return false;
9443
9444 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9445 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9446
9447 ret = false;
9448 tmp = I915_READ(PIPECONF(crtc->pipe));
9449 if (!(tmp & PIPECONF_ENABLE))
9450 goto out;
9451
9452 switch (tmp & PIPECONF_BPC_MASK) {
9453 case PIPECONF_6BPC:
9454 pipe_config->pipe_bpp = 18;
9455 break;
9456 case PIPECONF_8BPC:
9457 pipe_config->pipe_bpp = 24;
9458 break;
9459 case PIPECONF_10BPC:
9460 pipe_config->pipe_bpp = 30;
9461 break;
9462 case PIPECONF_12BPC:
9463 pipe_config->pipe_bpp = 36;
9464 break;
9465 default:
9466 break;
9467 }
9468
9469 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9470 pipe_config->limited_color_range = true;
9471
9472 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9473 struct intel_shared_dpll *pll;
9474
9475 pipe_config->has_pch_encoder = true;
9476
9477 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9478 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9479 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9480
9481 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9482
9483 if (HAS_PCH_IBX(dev_priv->dev)) {
9484 pipe_config->shared_dpll =
9485 (enum intel_dpll_id) crtc->pipe;
9486 } else {
9487 tmp = I915_READ(PCH_DPLL_SEL);
9488 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9489 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9490 else
9491 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9492 }
9493
9494 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9495
9496 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9497 &pipe_config->dpll_hw_state));
9498
9499 tmp = pipe_config->dpll_hw_state.dpll;
9500 pipe_config->pixel_multiplier =
9501 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9502 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9503
9504 ironlake_pch_clock_get(crtc, pipe_config);
9505 } else {
9506 pipe_config->pixel_multiplier = 1;
9507 }
9508
9509 intel_get_pipe_timings(crtc, pipe_config);
9510
9511 ironlake_get_pfit_config(crtc, pipe_config);
9512
9513 ret = true;
9514
9515 out:
9516 intel_display_power_put(dev_priv, power_domain);
9517
9518 return ret;
9519 }
9520
9521 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9522 {
9523 struct drm_device *dev = dev_priv->dev;
9524 struct intel_crtc *crtc;
9525
9526 for_each_intel_crtc(dev, crtc)
9527 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9528 pipe_name(crtc->pipe));
9529
9530 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9531 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9532 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9533 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9534 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9535 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9536 "CPU PWM1 enabled\n");
9537 if (IS_HASWELL(dev))
9538 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9539 "CPU PWM2 enabled\n");
9540 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9541 "PCH PWM1 enabled\n");
9542 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9543 "Utility pin enabled\n");
9544 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9545
9546 /*
9547 * In theory we can still leave IRQs enabled, as long as only the HPD
9548 * interrupts remain enabled. We used to check for that, but since it's
9549 * gen-specific and since we only disable LCPLL after we fully disable
9550 * the interrupts, the check below should be enough.
9551 */
9552 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9553 }
9554
9555 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9556 {
9557 struct drm_device *dev = dev_priv->dev;
9558
9559 if (IS_HASWELL(dev))
9560 return I915_READ(D_COMP_HSW);
9561 else
9562 return I915_READ(D_COMP_BDW);
9563 }
9564
9565 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9566 {
9567 struct drm_device *dev = dev_priv->dev;
9568
9569 if (IS_HASWELL(dev)) {
9570 mutex_lock(&dev_priv->rps.hw_lock);
9571 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9572 val))
9573 DRM_ERROR("Failed to write to D_COMP\n");
9574 mutex_unlock(&dev_priv->rps.hw_lock);
9575 } else {
9576 I915_WRITE(D_COMP_BDW, val);
9577 POSTING_READ(D_COMP_BDW);
9578 }
9579 }
9580
9581 /*
9582 * This function implements pieces of two sequences from BSpec:
9583 * - Sequence for display software to disable LCPLL
9584 * - Sequence for display software to allow package C8+
9585 * The steps implemented here are just the steps that actually touch the LCPLL
9586 * register. Callers should take care of disabling all the display engine
9587 * functions, doing the mode unset, fixing interrupts, etc.
9588 */
9589 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9590 bool switch_to_fclk, bool allow_power_down)
9591 {
9592 uint32_t val;
9593
9594 assert_can_disable_lcpll(dev_priv);
9595
9596 val = I915_READ(LCPLL_CTL);
9597
9598 if (switch_to_fclk) {
9599 val |= LCPLL_CD_SOURCE_FCLK;
9600 I915_WRITE(LCPLL_CTL, val);
9601
9602 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9603 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9604 DRM_ERROR("Switching to FCLK failed\n");
9605
9606 val = I915_READ(LCPLL_CTL);
9607 }
9608
9609 val |= LCPLL_PLL_DISABLE;
9610 I915_WRITE(LCPLL_CTL, val);
9611 POSTING_READ(LCPLL_CTL);
9612
9613 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9614 DRM_ERROR("LCPLL still locked\n");
9615
9616 val = hsw_read_dcomp(dev_priv);
9617 val |= D_COMP_COMP_DISABLE;
9618 hsw_write_dcomp(dev_priv, val);
9619 ndelay(100);
9620
9621 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9622 1))
9623 DRM_ERROR("D_COMP RCOMP still in progress\n");
9624
9625 if (allow_power_down) {
9626 val = I915_READ(LCPLL_CTL);
9627 val |= LCPLL_POWER_DOWN_ALLOW;
9628 I915_WRITE(LCPLL_CTL, val);
9629 POSTING_READ(LCPLL_CTL);
9630 }
9631 }
9632
9633 /*
9634 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9635 * source.
9636 */
9637 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9638 {
9639 uint32_t val;
9640
9641 val = I915_READ(LCPLL_CTL);
9642
9643 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9644 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9645 return;
9646
9647 /*
9648 * Make sure we're not on PC8 state before disabling PC8, otherwise
9649 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9650 */
9651 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9652
9653 if (val & LCPLL_POWER_DOWN_ALLOW) {
9654 val &= ~LCPLL_POWER_DOWN_ALLOW;
9655 I915_WRITE(LCPLL_CTL, val);
9656 POSTING_READ(LCPLL_CTL);
9657 }
9658
9659 val = hsw_read_dcomp(dev_priv);
9660 val |= D_COMP_COMP_FORCE;
9661 val &= ~D_COMP_COMP_DISABLE;
9662 hsw_write_dcomp(dev_priv, val);
9663
9664 val = I915_READ(LCPLL_CTL);
9665 val &= ~LCPLL_PLL_DISABLE;
9666 I915_WRITE(LCPLL_CTL, val);
9667
9668 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9669 DRM_ERROR("LCPLL not locked yet\n");
9670
9671 if (val & LCPLL_CD_SOURCE_FCLK) {
9672 val = I915_READ(LCPLL_CTL);
9673 val &= ~LCPLL_CD_SOURCE_FCLK;
9674 I915_WRITE(LCPLL_CTL, val);
9675
9676 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9677 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9678 DRM_ERROR("Switching back to LCPLL failed\n");
9679 }
9680
9681 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9682 intel_update_cdclk(dev_priv->dev);
9683 }
9684
9685 /*
9686 * Package states C8 and deeper are really deep PC states that can only be
9687 * reached when all the devices on the system allow it, so even if the graphics
9688 * device allows PC8+, it doesn't mean the system will actually get to these
9689 * states. Our driver only allows PC8+ when going into runtime PM.
9690 *
9691 * The requirements for PC8+ are that all the outputs are disabled, the power
9692 * well is disabled and most interrupts are disabled, and these are also
9693 * requirements for runtime PM. When these conditions are met, we manually do
9694 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9695 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9696 * hang the machine.
9697 *
9698 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9699 * the state of some registers, so when we come back from PC8+ we need to
9700 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9701 * need to take care of the registers kept by RC6. Notice that this happens even
9702 * if we don't put the device in PCI D3 state (which is what currently happens
9703 * because of the runtime PM support).
9704 *
9705 * For more, read "Display Sequences for Package C8" on the hardware
9706 * documentation.
9707 */
9708 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9709 {
9710 struct drm_device *dev = dev_priv->dev;
9711 uint32_t val;
9712
9713 DRM_DEBUG_KMS("Enabling package C8+\n");
9714
9715 if (HAS_PCH_LPT_LP(dev)) {
9716 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9717 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9718 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9719 }
9720
9721 lpt_disable_clkout_dp(dev);
9722 hsw_disable_lcpll(dev_priv, true, true);
9723 }
9724
9725 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9726 {
9727 struct drm_device *dev = dev_priv->dev;
9728 uint32_t val;
9729
9730 DRM_DEBUG_KMS("Disabling package C8+\n");
9731
9732 hsw_restore_lcpll(dev_priv);
9733 lpt_init_pch_refclk(dev);
9734
9735 if (HAS_PCH_LPT_LP(dev)) {
9736 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9737 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9738 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9739 }
9740 }
9741
9742 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9743 {
9744 struct drm_device *dev = old_state->dev;
9745 struct intel_atomic_state *old_intel_state =
9746 to_intel_atomic_state(old_state);
9747 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9748
9749 broxton_set_cdclk(dev, req_cdclk);
9750 }
9751
9752 /* compute the max rate for new configuration */
9753 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9754 {
9755 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9756 struct drm_i915_private *dev_priv = state->dev->dev_private;
9757 struct drm_crtc *crtc;
9758 struct drm_crtc_state *cstate;
9759 struct intel_crtc_state *crtc_state;
9760 unsigned max_pixel_rate = 0, i;
9761 enum pipe pipe;
9762
9763 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9764 sizeof(intel_state->min_pixclk));
9765
9766 for_each_crtc_in_state(state, crtc, cstate, i) {
9767 int pixel_rate;
9768
9769 crtc_state = to_intel_crtc_state(cstate);
9770 if (!crtc_state->base.enable) {
9771 intel_state->min_pixclk[i] = 0;
9772 continue;
9773 }
9774
9775 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9776
9777 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9778 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9779 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9780
9781 intel_state->min_pixclk[i] = pixel_rate;
9782 }
9783
9784 for_each_pipe(dev_priv, pipe)
9785 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9786
9787 return max_pixel_rate;
9788 }
9789
9790 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9791 {
9792 struct drm_i915_private *dev_priv = dev->dev_private;
9793 uint32_t val, data;
9794 int ret;
9795
9796 if (WARN((I915_READ(LCPLL_CTL) &
9797 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9798 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9799 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9800 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9801 "trying to change cdclk frequency with cdclk not enabled\n"))
9802 return;
9803
9804 mutex_lock(&dev_priv->rps.hw_lock);
9805 ret = sandybridge_pcode_write(dev_priv,
9806 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9807 mutex_unlock(&dev_priv->rps.hw_lock);
9808 if (ret) {
9809 DRM_ERROR("failed to inform pcode about cdclk change\n");
9810 return;
9811 }
9812
9813 val = I915_READ(LCPLL_CTL);
9814 val |= LCPLL_CD_SOURCE_FCLK;
9815 I915_WRITE(LCPLL_CTL, val);
9816
9817 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9818 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9819 DRM_ERROR("Switching to FCLK failed\n");
9820
9821 val = I915_READ(LCPLL_CTL);
9822 val &= ~LCPLL_CLK_FREQ_MASK;
9823
9824 switch (cdclk) {
9825 case 450000:
9826 val |= LCPLL_CLK_FREQ_450;
9827 data = 0;
9828 break;
9829 case 540000:
9830 val |= LCPLL_CLK_FREQ_54O_BDW;
9831 data = 1;
9832 break;
9833 case 337500:
9834 val |= LCPLL_CLK_FREQ_337_5_BDW;
9835 data = 2;
9836 break;
9837 case 675000:
9838 val |= LCPLL_CLK_FREQ_675_BDW;
9839 data = 3;
9840 break;
9841 default:
9842 WARN(1, "invalid cdclk frequency\n");
9843 return;
9844 }
9845
9846 I915_WRITE(LCPLL_CTL, val);
9847
9848 val = I915_READ(LCPLL_CTL);
9849 val &= ~LCPLL_CD_SOURCE_FCLK;
9850 I915_WRITE(LCPLL_CTL, val);
9851
9852 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9853 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9854 DRM_ERROR("Switching back to LCPLL failed\n");
9855
9856 mutex_lock(&dev_priv->rps.hw_lock);
9857 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9858 mutex_unlock(&dev_priv->rps.hw_lock);
9859
9860 intel_update_cdclk(dev);
9861
9862 WARN(cdclk != dev_priv->cdclk_freq,
9863 "cdclk requested %d kHz but got %d kHz\n",
9864 cdclk, dev_priv->cdclk_freq);
9865 }
9866
9867 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9868 {
9869 struct drm_i915_private *dev_priv = to_i915(state->dev);
9870 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9871 int max_pixclk = ilk_max_pixel_rate(state);
9872 int cdclk;
9873
9874 /*
9875 * FIXME should also account for plane ratio
9876 * once 64bpp pixel formats are supported.
9877 */
9878 if (max_pixclk > 540000)
9879 cdclk = 675000;
9880 else if (max_pixclk > 450000)
9881 cdclk = 540000;
9882 else if (max_pixclk > 337500)
9883 cdclk = 450000;
9884 else
9885 cdclk = 337500;
9886
9887 if (cdclk > dev_priv->max_cdclk_freq) {
9888 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9889 cdclk, dev_priv->max_cdclk_freq);
9890 return -EINVAL;
9891 }
9892
9893 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9894 if (!intel_state->active_crtcs)
9895 intel_state->dev_cdclk = 337500;
9896
9897 return 0;
9898 }
9899
9900 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9901 {
9902 struct drm_device *dev = old_state->dev;
9903 struct intel_atomic_state *old_intel_state =
9904 to_intel_atomic_state(old_state);
9905 unsigned req_cdclk = old_intel_state->dev_cdclk;
9906
9907 broadwell_set_cdclk(dev, req_cdclk);
9908 }
9909
9910 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9911 struct intel_crtc_state *crtc_state)
9912 {
9913 struct intel_encoder *intel_encoder =
9914 intel_ddi_get_crtc_new_encoder(crtc_state);
9915
9916 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9917 if (!intel_ddi_pll_select(crtc, crtc_state))
9918 return -EINVAL;
9919 }
9920
9921 crtc->lowfreq_avail = false;
9922
9923 return 0;
9924 }
9925
9926 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9927 enum port port,
9928 struct intel_crtc_state *pipe_config)
9929 {
9930 switch (port) {
9931 case PORT_A:
9932 pipe_config->ddi_pll_sel = SKL_DPLL0;
9933 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9934 break;
9935 case PORT_B:
9936 pipe_config->ddi_pll_sel = SKL_DPLL1;
9937 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9938 break;
9939 case PORT_C:
9940 pipe_config->ddi_pll_sel = SKL_DPLL2;
9941 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9942 break;
9943 default:
9944 DRM_ERROR("Incorrect port type\n");
9945 }
9946 }
9947
9948 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9949 enum port port,
9950 struct intel_crtc_state *pipe_config)
9951 {
9952 u32 temp, dpll_ctl1;
9953
9954 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9955 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9956
9957 switch (pipe_config->ddi_pll_sel) {
9958 case SKL_DPLL0:
9959 /*
9960 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9961 * of the shared DPLL framework and thus needs to be read out
9962 * separately
9963 */
9964 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9965 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9966 break;
9967 case SKL_DPLL1:
9968 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9969 break;
9970 case SKL_DPLL2:
9971 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9972 break;
9973 case SKL_DPLL3:
9974 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9975 break;
9976 }
9977 }
9978
9979 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9980 enum port port,
9981 struct intel_crtc_state *pipe_config)
9982 {
9983 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9984
9985 switch (pipe_config->ddi_pll_sel) {
9986 case PORT_CLK_SEL_WRPLL1:
9987 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9988 break;
9989 case PORT_CLK_SEL_WRPLL2:
9990 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9991 break;
9992 case PORT_CLK_SEL_SPLL:
9993 pipe_config->shared_dpll = DPLL_ID_SPLL;
9994 break;
9995 }
9996 }
9997
9998 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9999 struct intel_crtc_state *pipe_config)
10000 {
10001 struct drm_device *dev = crtc->base.dev;
10002 struct drm_i915_private *dev_priv = dev->dev_private;
10003 struct intel_shared_dpll *pll;
10004 enum port port;
10005 uint32_t tmp;
10006
10007 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10008
10009 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10010
10011 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10012 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10013 else if (IS_BROXTON(dev))
10014 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10015 else
10016 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10017
10018 if (pipe_config->shared_dpll >= 0) {
10019 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
10020
10021 WARN_ON(!pll->get_hw_state(dev_priv, pll,
10022 &pipe_config->dpll_hw_state));
10023 }
10024
10025 /*
10026 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10027 * DDI E. So just check whether this pipe is wired to DDI E and whether
10028 * the PCH transcoder is on.
10029 */
10030 if (INTEL_INFO(dev)->gen < 9 &&
10031 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10032 pipe_config->has_pch_encoder = true;
10033
10034 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10035 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10036 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10037
10038 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10039 }
10040 }
10041
10042 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10043 struct intel_crtc_state *pipe_config)
10044 {
10045 struct drm_device *dev = crtc->base.dev;
10046 struct drm_i915_private *dev_priv = dev->dev_private;
10047 enum intel_display_power_domain power_domain;
10048 unsigned long power_domain_mask;
10049 uint32_t tmp;
10050 bool ret;
10051
10052 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10053 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10054 return false;
10055 power_domain_mask = BIT(power_domain);
10056
10057 ret = false;
10058
10059 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10060 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10061
10062 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10063 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10064 enum pipe trans_edp_pipe;
10065 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10066 default:
10067 WARN(1, "unknown pipe linked to edp transcoder\n");
10068 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10069 case TRANS_DDI_EDP_INPUT_A_ON:
10070 trans_edp_pipe = PIPE_A;
10071 break;
10072 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10073 trans_edp_pipe = PIPE_B;
10074 break;
10075 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10076 trans_edp_pipe = PIPE_C;
10077 break;
10078 }
10079
10080 if (trans_edp_pipe == crtc->pipe)
10081 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10082 }
10083
10084 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10085 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10086 goto out;
10087 power_domain_mask |= BIT(power_domain);
10088
10089 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10090 if (!(tmp & PIPECONF_ENABLE))
10091 goto out;
10092
10093 haswell_get_ddi_port_state(crtc, pipe_config);
10094
10095 intel_get_pipe_timings(crtc, pipe_config);
10096
10097 if (INTEL_INFO(dev)->gen >= 9) {
10098 skl_init_scalers(dev, crtc, pipe_config);
10099 }
10100
10101 if (INTEL_INFO(dev)->gen >= 9) {
10102 pipe_config->scaler_state.scaler_id = -1;
10103 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10104 }
10105
10106 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10107 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10108 power_domain_mask |= BIT(power_domain);
10109 if (INTEL_INFO(dev)->gen >= 9)
10110 skylake_get_pfit_config(crtc, pipe_config);
10111 else
10112 ironlake_get_pfit_config(crtc, pipe_config);
10113 }
10114
10115 if (IS_HASWELL(dev))
10116 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10117 (I915_READ(IPS_CTL) & IPS_ENABLE);
10118
10119 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10120 pipe_config->pixel_multiplier =
10121 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10122 } else {
10123 pipe_config->pixel_multiplier = 1;
10124 }
10125
10126 ret = true;
10127
10128 out:
10129 for_each_power_domain(power_domain, power_domain_mask)
10130 intel_display_power_put(dev_priv, power_domain);
10131
10132 return ret;
10133 }
10134
10135 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10136 const struct intel_plane_state *plane_state)
10137 {
10138 struct drm_device *dev = crtc->dev;
10139 struct drm_i915_private *dev_priv = dev->dev_private;
10140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10141 uint32_t cntl = 0, size = 0;
10142
10143 if (plane_state && plane_state->visible) {
10144 unsigned int width = plane_state->base.crtc_w;
10145 unsigned int height = plane_state->base.crtc_h;
10146 unsigned int stride = roundup_pow_of_two(width) * 4;
10147
10148 switch (stride) {
10149 default:
10150 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10151 width, stride);
10152 stride = 256;
10153 /* fallthrough */
10154 case 256:
10155 case 512:
10156 case 1024:
10157 case 2048:
10158 break;
10159 }
10160
10161 cntl |= CURSOR_ENABLE |
10162 CURSOR_GAMMA_ENABLE |
10163 CURSOR_FORMAT_ARGB |
10164 CURSOR_STRIDE(stride);
10165
10166 size = (height << 12) | width;
10167 }
10168
10169 if (intel_crtc->cursor_cntl != 0 &&
10170 (intel_crtc->cursor_base != base ||
10171 intel_crtc->cursor_size != size ||
10172 intel_crtc->cursor_cntl != cntl)) {
10173 /* On these chipsets we can only modify the base/size/stride
10174 * whilst the cursor is disabled.
10175 */
10176 I915_WRITE(CURCNTR(PIPE_A), 0);
10177 POSTING_READ(CURCNTR(PIPE_A));
10178 intel_crtc->cursor_cntl = 0;
10179 }
10180
10181 if (intel_crtc->cursor_base != base) {
10182 I915_WRITE(CURBASE(PIPE_A), base);
10183 intel_crtc->cursor_base = base;
10184 }
10185
10186 if (intel_crtc->cursor_size != size) {
10187 I915_WRITE(CURSIZE, size);
10188 intel_crtc->cursor_size = size;
10189 }
10190
10191 if (intel_crtc->cursor_cntl != cntl) {
10192 I915_WRITE(CURCNTR(PIPE_A), cntl);
10193 POSTING_READ(CURCNTR(PIPE_A));
10194 intel_crtc->cursor_cntl = cntl;
10195 }
10196 }
10197
10198 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10199 const struct intel_plane_state *plane_state)
10200 {
10201 struct drm_device *dev = crtc->dev;
10202 struct drm_i915_private *dev_priv = dev->dev_private;
10203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10204 int pipe = intel_crtc->pipe;
10205 uint32_t cntl = 0;
10206
10207 if (plane_state && plane_state->visible) {
10208 cntl = MCURSOR_GAMMA_ENABLE;
10209 switch (plane_state->base.crtc_w) {
10210 case 64:
10211 cntl |= CURSOR_MODE_64_ARGB_AX;
10212 break;
10213 case 128:
10214 cntl |= CURSOR_MODE_128_ARGB_AX;
10215 break;
10216 case 256:
10217 cntl |= CURSOR_MODE_256_ARGB_AX;
10218 break;
10219 default:
10220 MISSING_CASE(plane_state->base.crtc_w);
10221 return;
10222 }
10223 cntl |= pipe << 28; /* Connect to correct pipe */
10224
10225 if (HAS_DDI(dev))
10226 cntl |= CURSOR_PIPE_CSC_ENABLE;
10227
10228 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10229 cntl |= CURSOR_ROTATE_180;
10230 }
10231
10232 if (intel_crtc->cursor_cntl != cntl) {
10233 I915_WRITE(CURCNTR(pipe), cntl);
10234 POSTING_READ(CURCNTR(pipe));
10235 intel_crtc->cursor_cntl = cntl;
10236 }
10237
10238 /* and commit changes on next vblank */
10239 I915_WRITE(CURBASE(pipe), base);
10240 POSTING_READ(CURBASE(pipe));
10241
10242 intel_crtc->cursor_base = base;
10243 }
10244
10245 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10246 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10247 const struct intel_plane_state *plane_state)
10248 {
10249 struct drm_device *dev = crtc->dev;
10250 struct drm_i915_private *dev_priv = dev->dev_private;
10251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10252 int pipe = intel_crtc->pipe;
10253 u32 base = intel_crtc->cursor_addr;
10254 u32 pos = 0;
10255
10256 if (plane_state) {
10257 int x = plane_state->base.crtc_x;
10258 int y = plane_state->base.crtc_y;
10259
10260 if (x < 0) {
10261 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10262 x = -x;
10263 }
10264 pos |= x << CURSOR_X_SHIFT;
10265
10266 if (y < 0) {
10267 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10268 y = -y;
10269 }
10270 pos |= y << CURSOR_Y_SHIFT;
10271
10272 /* ILK+ do this automagically */
10273 if (HAS_GMCH_DISPLAY(dev) &&
10274 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10275 base += (plane_state->base.crtc_h *
10276 plane_state->base.crtc_w - 1) * 4;
10277 }
10278 }
10279
10280 I915_WRITE(CURPOS(pipe), pos);
10281
10282 if (IS_845G(dev) || IS_I865G(dev))
10283 i845_update_cursor(crtc, base, plane_state);
10284 else
10285 i9xx_update_cursor(crtc, base, plane_state);
10286 }
10287
10288 static bool cursor_size_ok(struct drm_device *dev,
10289 uint32_t width, uint32_t height)
10290 {
10291 if (width == 0 || height == 0)
10292 return false;
10293
10294 /*
10295 * 845g/865g are special in that they are only limited by
10296 * the width of their cursors, the height is arbitrary up to
10297 * the precision of the register. Everything else requires
10298 * square cursors, limited to a few power-of-two sizes.
10299 */
10300 if (IS_845G(dev) || IS_I865G(dev)) {
10301 if ((width & 63) != 0)
10302 return false;
10303
10304 if (width > (IS_845G(dev) ? 64 : 512))
10305 return false;
10306
10307 if (height > 1023)
10308 return false;
10309 } else {
10310 switch (width | height) {
10311 case 256:
10312 case 128:
10313 if (IS_GEN2(dev))
10314 return false;
10315 case 64:
10316 break;
10317 default:
10318 return false;
10319 }
10320 }
10321
10322 return true;
10323 }
10324
10325 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10326 u16 *blue, uint32_t start, uint32_t size)
10327 {
10328 int end = (start + size > 256) ? 256 : start + size, i;
10329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10330
10331 for (i = start; i < end; i++) {
10332 intel_crtc->lut_r[i] = red[i] >> 8;
10333 intel_crtc->lut_g[i] = green[i] >> 8;
10334 intel_crtc->lut_b[i] = blue[i] >> 8;
10335 }
10336
10337 intel_crtc_load_lut(crtc);
10338 }
10339
10340 /* VESA 640x480x72Hz mode to set on the pipe */
10341 static struct drm_display_mode load_detect_mode = {
10342 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10343 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10344 };
10345
10346 struct drm_framebuffer *
10347 __intel_framebuffer_create(struct drm_device *dev,
10348 struct drm_mode_fb_cmd2 *mode_cmd,
10349 struct drm_i915_gem_object *obj)
10350 {
10351 struct intel_framebuffer *intel_fb;
10352 int ret;
10353
10354 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10355 if (!intel_fb)
10356 return ERR_PTR(-ENOMEM);
10357
10358 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10359 if (ret)
10360 goto err;
10361
10362 return &intel_fb->base;
10363
10364 err:
10365 kfree(intel_fb);
10366 return ERR_PTR(ret);
10367 }
10368
10369 static struct drm_framebuffer *
10370 intel_framebuffer_create(struct drm_device *dev,
10371 struct drm_mode_fb_cmd2 *mode_cmd,
10372 struct drm_i915_gem_object *obj)
10373 {
10374 struct drm_framebuffer *fb;
10375 int ret;
10376
10377 ret = i915_mutex_lock_interruptible(dev);
10378 if (ret)
10379 return ERR_PTR(ret);
10380 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10381 mutex_unlock(&dev->struct_mutex);
10382
10383 return fb;
10384 }
10385
10386 static u32
10387 intel_framebuffer_pitch_for_width(int width, int bpp)
10388 {
10389 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10390 return ALIGN(pitch, 64);
10391 }
10392
10393 static u32
10394 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10395 {
10396 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10397 return PAGE_ALIGN(pitch * mode->vdisplay);
10398 }
10399
10400 static struct drm_framebuffer *
10401 intel_framebuffer_create_for_mode(struct drm_device *dev,
10402 struct drm_display_mode *mode,
10403 int depth, int bpp)
10404 {
10405 struct drm_framebuffer *fb;
10406 struct drm_i915_gem_object *obj;
10407 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10408
10409 obj = i915_gem_alloc_object(dev,
10410 intel_framebuffer_size_for_mode(mode, bpp));
10411 if (obj == NULL)
10412 return ERR_PTR(-ENOMEM);
10413
10414 mode_cmd.width = mode->hdisplay;
10415 mode_cmd.height = mode->vdisplay;
10416 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10417 bpp);
10418 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10419
10420 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10421 if (IS_ERR(fb))
10422 drm_gem_object_unreference_unlocked(&obj->base);
10423
10424 return fb;
10425 }
10426
10427 static struct drm_framebuffer *
10428 mode_fits_in_fbdev(struct drm_device *dev,
10429 struct drm_display_mode *mode)
10430 {
10431 #ifdef CONFIG_DRM_FBDEV_EMULATION
10432 struct drm_i915_private *dev_priv = dev->dev_private;
10433 struct drm_i915_gem_object *obj;
10434 struct drm_framebuffer *fb;
10435
10436 if (!dev_priv->fbdev)
10437 return NULL;
10438
10439 if (!dev_priv->fbdev->fb)
10440 return NULL;
10441
10442 obj = dev_priv->fbdev->fb->obj;
10443 BUG_ON(!obj);
10444
10445 fb = &dev_priv->fbdev->fb->base;
10446 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10447 fb->bits_per_pixel))
10448 return NULL;
10449
10450 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10451 return NULL;
10452
10453 drm_framebuffer_reference(fb);
10454 return fb;
10455 #else
10456 return NULL;
10457 #endif
10458 }
10459
10460 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10461 struct drm_crtc *crtc,
10462 struct drm_display_mode *mode,
10463 struct drm_framebuffer *fb,
10464 int x, int y)
10465 {
10466 struct drm_plane_state *plane_state;
10467 int hdisplay, vdisplay;
10468 int ret;
10469
10470 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10471 if (IS_ERR(plane_state))
10472 return PTR_ERR(plane_state);
10473
10474 if (mode)
10475 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10476 else
10477 hdisplay = vdisplay = 0;
10478
10479 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10480 if (ret)
10481 return ret;
10482 drm_atomic_set_fb_for_plane(plane_state, fb);
10483 plane_state->crtc_x = 0;
10484 plane_state->crtc_y = 0;
10485 plane_state->crtc_w = hdisplay;
10486 plane_state->crtc_h = vdisplay;
10487 plane_state->src_x = x << 16;
10488 plane_state->src_y = y << 16;
10489 plane_state->src_w = hdisplay << 16;
10490 plane_state->src_h = vdisplay << 16;
10491
10492 return 0;
10493 }
10494
10495 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10496 struct drm_display_mode *mode,
10497 struct intel_load_detect_pipe *old,
10498 struct drm_modeset_acquire_ctx *ctx)
10499 {
10500 struct intel_crtc *intel_crtc;
10501 struct intel_encoder *intel_encoder =
10502 intel_attached_encoder(connector);
10503 struct drm_crtc *possible_crtc;
10504 struct drm_encoder *encoder = &intel_encoder->base;
10505 struct drm_crtc *crtc = NULL;
10506 struct drm_device *dev = encoder->dev;
10507 struct drm_framebuffer *fb;
10508 struct drm_mode_config *config = &dev->mode_config;
10509 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10510 struct drm_connector_state *connector_state;
10511 struct intel_crtc_state *crtc_state;
10512 int ret, i = -1;
10513
10514 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10515 connector->base.id, connector->name,
10516 encoder->base.id, encoder->name);
10517
10518 old->restore_state = NULL;
10519
10520 retry:
10521 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10522 if (ret)
10523 goto fail;
10524
10525 /*
10526 * Algorithm gets a little messy:
10527 *
10528 * - if the connector already has an assigned crtc, use it (but make
10529 * sure it's on first)
10530 *
10531 * - try to find the first unused crtc that can drive this connector,
10532 * and use that if we find one
10533 */
10534
10535 /* See if we already have a CRTC for this connector */
10536 if (connector->state->crtc) {
10537 crtc = connector->state->crtc;
10538
10539 ret = drm_modeset_lock(&crtc->mutex, ctx);
10540 if (ret)
10541 goto fail;
10542
10543 /* Make sure the crtc and connector are running */
10544 goto found;
10545 }
10546
10547 /* Find an unused one (if possible) */
10548 for_each_crtc(dev, possible_crtc) {
10549 i++;
10550 if (!(encoder->possible_crtcs & (1 << i)))
10551 continue;
10552
10553 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10554 if (ret)
10555 goto fail;
10556
10557 if (possible_crtc->state->enable) {
10558 drm_modeset_unlock(&possible_crtc->mutex);
10559 continue;
10560 }
10561
10562 crtc = possible_crtc;
10563 break;
10564 }
10565
10566 /*
10567 * If we didn't find an unused CRTC, don't use any.
10568 */
10569 if (!crtc) {
10570 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10571 goto fail;
10572 }
10573
10574 found:
10575 intel_crtc = to_intel_crtc(crtc);
10576
10577 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10578 if (ret)
10579 goto fail;
10580
10581 state = drm_atomic_state_alloc(dev);
10582 restore_state = drm_atomic_state_alloc(dev);
10583 if (!state || !restore_state) {
10584 ret = -ENOMEM;
10585 goto fail;
10586 }
10587
10588 state->acquire_ctx = ctx;
10589 restore_state->acquire_ctx = ctx;
10590
10591 connector_state = drm_atomic_get_connector_state(state, connector);
10592 if (IS_ERR(connector_state)) {
10593 ret = PTR_ERR(connector_state);
10594 goto fail;
10595 }
10596
10597 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10598 if (ret)
10599 goto fail;
10600
10601 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10602 if (IS_ERR(crtc_state)) {
10603 ret = PTR_ERR(crtc_state);
10604 goto fail;
10605 }
10606
10607 crtc_state->base.active = crtc_state->base.enable = true;
10608
10609 if (!mode)
10610 mode = &load_detect_mode;
10611
10612 /* We need a framebuffer large enough to accommodate all accesses
10613 * that the plane may generate whilst we perform load detection.
10614 * We can not rely on the fbcon either being present (we get called
10615 * during its initialisation to detect all boot displays, or it may
10616 * not even exist) or that it is large enough to satisfy the
10617 * requested mode.
10618 */
10619 fb = mode_fits_in_fbdev(dev, mode);
10620 if (fb == NULL) {
10621 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10622 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10623 } else
10624 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10625 if (IS_ERR(fb)) {
10626 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10627 goto fail;
10628 }
10629
10630 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10631 if (ret)
10632 goto fail;
10633
10634 drm_framebuffer_unreference(fb);
10635
10636 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10637 if (ret)
10638 goto fail;
10639
10640 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10641 if (!ret)
10642 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10643 if (!ret)
10644 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10645 if (ret) {
10646 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10647 goto fail;
10648 }
10649
10650 ret = drm_atomic_commit(state);
10651 if (ret) {
10652 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10653 goto fail;
10654 }
10655
10656 old->restore_state = restore_state;
10657
10658 /* let the connector get through one full cycle before testing */
10659 intel_wait_for_vblank(dev, intel_crtc->pipe);
10660 return true;
10661
10662 fail:
10663 drm_atomic_state_free(state);
10664 drm_atomic_state_free(restore_state);
10665 restore_state = state = NULL;
10666
10667 if (ret == -EDEADLK) {
10668 drm_modeset_backoff(ctx);
10669 goto retry;
10670 }
10671
10672 return false;
10673 }
10674
10675 void intel_release_load_detect_pipe(struct drm_connector *connector,
10676 struct intel_load_detect_pipe *old,
10677 struct drm_modeset_acquire_ctx *ctx)
10678 {
10679 struct intel_encoder *intel_encoder =
10680 intel_attached_encoder(connector);
10681 struct drm_encoder *encoder = &intel_encoder->base;
10682 struct drm_atomic_state *state = old->restore_state;
10683 int ret;
10684
10685 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10686 connector->base.id, connector->name,
10687 encoder->base.id, encoder->name);
10688
10689 if (!state)
10690 return;
10691
10692 ret = drm_atomic_commit(state);
10693 if (ret) {
10694 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10695 drm_atomic_state_free(state);
10696 }
10697 }
10698
10699 static int i9xx_pll_refclk(struct drm_device *dev,
10700 const struct intel_crtc_state *pipe_config)
10701 {
10702 struct drm_i915_private *dev_priv = dev->dev_private;
10703 u32 dpll = pipe_config->dpll_hw_state.dpll;
10704
10705 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10706 return dev_priv->vbt.lvds_ssc_freq;
10707 else if (HAS_PCH_SPLIT(dev))
10708 return 120000;
10709 else if (!IS_GEN2(dev))
10710 return 96000;
10711 else
10712 return 48000;
10713 }
10714
10715 /* Returns the clock of the currently programmed mode of the given pipe. */
10716 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10717 struct intel_crtc_state *pipe_config)
10718 {
10719 struct drm_device *dev = crtc->base.dev;
10720 struct drm_i915_private *dev_priv = dev->dev_private;
10721 int pipe = pipe_config->cpu_transcoder;
10722 u32 dpll = pipe_config->dpll_hw_state.dpll;
10723 u32 fp;
10724 intel_clock_t clock;
10725 int port_clock;
10726 int refclk = i9xx_pll_refclk(dev, pipe_config);
10727
10728 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10729 fp = pipe_config->dpll_hw_state.fp0;
10730 else
10731 fp = pipe_config->dpll_hw_state.fp1;
10732
10733 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10734 if (IS_PINEVIEW(dev)) {
10735 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10736 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10737 } else {
10738 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10739 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10740 }
10741
10742 if (!IS_GEN2(dev)) {
10743 if (IS_PINEVIEW(dev))
10744 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10745 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10746 else
10747 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10748 DPLL_FPA01_P1_POST_DIV_SHIFT);
10749
10750 switch (dpll & DPLL_MODE_MASK) {
10751 case DPLLB_MODE_DAC_SERIAL:
10752 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10753 5 : 10;
10754 break;
10755 case DPLLB_MODE_LVDS:
10756 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10757 7 : 14;
10758 break;
10759 default:
10760 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10761 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10762 return;
10763 }
10764
10765 if (IS_PINEVIEW(dev))
10766 port_clock = pnv_calc_dpll_params(refclk, &clock);
10767 else
10768 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10769 } else {
10770 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10771 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10772
10773 if (is_lvds) {
10774 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10775 DPLL_FPA01_P1_POST_DIV_SHIFT);
10776
10777 if (lvds & LVDS_CLKB_POWER_UP)
10778 clock.p2 = 7;
10779 else
10780 clock.p2 = 14;
10781 } else {
10782 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10783 clock.p1 = 2;
10784 else {
10785 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10786 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10787 }
10788 if (dpll & PLL_P2_DIVIDE_BY_4)
10789 clock.p2 = 4;
10790 else
10791 clock.p2 = 2;
10792 }
10793
10794 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10795 }
10796
10797 /*
10798 * This value includes pixel_multiplier. We will use
10799 * port_clock to compute adjusted_mode.crtc_clock in the
10800 * encoder's get_config() function.
10801 */
10802 pipe_config->port_clock = port_clock;
10803 }
10804
10805 int intel_dotclock_calculate(int link_freq,
10806 const struct intel_link_m_n *m_n)
10807 {
10808 /*
10809 * The calculation for the data clock is:
10810 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10811 * But we want to avoid losing precison if possible, so:
10812 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10813 *
10814 * and the link clock is simpler:
10815 * link_clock = (m * link_clock) / n
10816 */
10817
10818 if (!m_n->link_n)
10819 return 0;
10820
10821 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10822 }
10823
10824 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10825 struct intel_crtc_state *pipe_config)
10826 {
10827 struct drm_device *dev = crtc->base.dev;
10828
10829 /* read out port_clock from the DPLL */
10830 i9xx_crtc_clock_get(crtc, pipe_config);
10831
10832 /*
10833 * This value does not include pixel_multiplier.
10834 * We will check that port_clock and adjusted_mode.crtc_clock
10835 * agree once we know their relationship in the encoder's
10836 * get_config() function.
10837 */
10838 pipe_config->base.adjusted_mode.crtc_clock =
10839 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10840 &pipe_config->fdi_m_n);
10841 }
10842
10843 /** Returns the currently programmed mode of the given pipe. */
10844 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10845 struct drm_crtc *crtc)
10846 {
10847 struct drm_i915_private *dev_priv = dev->dev_private;
10848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10849 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10850 struct drm_display_mode *mode;
10851 struct intel_crtc_state *pipe_config;
10852 int htot = I915_READ(HTOTAL(cpu_transcoder));
10853 int hsync = I915_READ(HSYNC(cpu_transcoder));
10854 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10855 int vsync = I915_READ(VSYNC(cpu_transcoder));
10856 enum pipe pipe = intel_crtc->pipe;
10857
10858 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10859 if (!mode)
10860 return NULL;
10861
10862 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10863 if (!pipe_config) {
10864 kfree(mode);
10865 return NULL;
10866 }
10867
10868 /*
10869 * Construct a pipe_config sufficient for getting the clock info
10870 * back out of crtc_clock_get.
10871 *
10872 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10873 * to use a real value here instead.
10874 */
10875 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10876 pipe_config->pixel_multiplier = 1;
10877 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10878 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10879 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10880 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10881
10882 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10883 mode->hdisplay = (htot & 0xffff) + 1;
10884 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10885 mode->hsync_start = (hsync & 0xffff) + 1;
10886 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10887 mode->vdisplay = (vtot & 0xffff) + 1;
10888 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10889 mode->vsync_start = (vsync & 0xffff) + 1;
10890 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10891
10892 drm_mode_set_name(mode);
10893
10894 kfree(pipe_config);
10895
10896 return mode;
10897 }
10898
10899 void intel_mark_busy(struct drm_device *dev)
10900 {
10901 struct drm_i915_private *dev_priv = dev->dev_private;
10902
10903 if (dev_priv->mm.busy)
10904 return;
10905
10906 intel_runtime_pm_get(dev_priv);
10907 i915_update_gfx_val(dev_priv);
10908 if (INTEL_INFO(dev)->gen >= 6)
10909 gen6_rps_busy(dev_priv);
10910 dev_priv->mm.busy = true;
10911 }
10912
10913 void intel_mark_idle(struct drm_device *dev)
10914 {
10915 struct drm_i915_private *dev_priv = dev->dev_private;
10916
10917 if (!dev_priv->mm.busy)
10918 return;
10919
10920 dev_priv->mm.busy = false;
10921
10922 if (INTEL_INFO(dev)->gen >= 6)
10923 gen6_rps_idle(dev->dev_private);
10924
10925 intel_runtime_pm_put(dev_priv);
10926 }
10927
10928 static void intel_crtc_destroy(struct drm_crtc *crtc)
10929 {
10930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10931 struct drm_device *dev = crtc->dev;
10932 struct intel_unpin_work *work;
10933
10934 spin_lock_irq(&dev->event_lock);
10935 work = intel_crtc->unpin_work;
10936 intel_crtc->unpin_work = NULL;
10937 spin_unlock_irq(&dev->event_lock);
10938
10939 if (work) {
10940 cancel_work_sync(&work->work);
10941 kfree(work);
10942 }
10943
10944 drm_crtc_cleanup(crtc);
10945
10946 kfree(intel_crtc);
10947 }
10948
10949 static void intel_unpin_work_fn(struct work_struct *__work)
10950 {
10951 struct intel_unpin_work *work =
10952 container_of(__work, struct intel_unpin_work, work);
10953 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10954 struct drm_device *dev = crtc->base.dev;
10955 struct drm_plane *primary = crtc->base.primary;
10956
10957 mutex_lock(&dev->struct_mutex);
10958 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10959 drm_gem_object_unreference(&work->pending_flip_obj->base);
10960
10961 if (work->flip_queued_req)
10962 i915_gem_request_assign(&work->flip_queued_req, NULL);
10963 mutex_unlock(&dev->struct_mutex);
10964
10965 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10966 intel_fbc_post_update(crtc);
10967 drm_framebuffer_unreference(work->old_fb);
10968
10969 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10970 atomic_dec(&crtc->unpin_work_count);
10971
10972 kfree(work);
10973 }
10974
10975 static void do_intel_finish_page_flip(struct drm_device *dev,
10976 struct drm_crtc *crtc)
10977 {
10978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10979 struct intel_unpin_work *work;
10980 unsigned long flags;
10981
10982 /* Ignore early vblank irqs */
10983 if (intel_crtc == NULL)
10984 return;
10985
10986 /*
10987 * This is called both by irq handlers and the reset code (to complete
10988 * lost pageflips) so needs the full irqsave spinlocks.
10989 */
10990 spin_lock_irqsave(&dev->event_lock, flags);
10991 work = intel_crtc->unpin_work;
10992
10993 /* Ensure we don't miss a work->pending update ... */
10994 smp_rmb();
10995
10996 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10997 spin_unlock_irqrestore(&dev->event_lock, flags);
10998 return;
10999 }
11000
11001 page_flip_completed(intel_crtc);
11002
11003 spin_unlock_irqrestore(&dev->event_lock, flags);
11004 }
11005
11006 void intel_finish_page_flip(struct drm_device *dev, int pipe)
11007 {
11008 struct drm_i915_private *dev_priv = dev->dev_private;
11009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11010
11011 do_intel_finish_page_flip(dev, crtc);
11012 }
11013
11014 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
11015 {
11016 struct drm_i915_private *dev_priv = dev->dev_private;
11017 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
11018
11019 do_intel_finish_page_flip(dev, crtc);
11020 }
11021
11022 /* Is 'a' after or equal to 'b'? */
11023 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11024 {
11025 return !((a - b) & 0x80000000);
11026 }
11027
11028 static bool page_flip_finished(struct intel_crtc *crtc)
11029 {
11030 struct drm_device *dev = crtc->base.dev;
11031 struct drm_i915_private *dev_priv = dev->dev_private;
11032
11033 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
11034 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
11035 return true;
11036
11037 /*
11038 * The relevant registers doen't exist on pre-ctg.
11039 * As the flip done interrupt doesn't trigger for mmio
11040 * flips on gmch platforms, a flip count check isn't
11041 * really needed there. But since ctg has the registers,
11042 * include it in the check anyway.
11043 */
11044 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11045 return true;
11046
11047 /*
11048 * BDW signals flip done immediately if the plane
11049 * is disabled, even if the plane enable is already
11050 * armed to occur at the next vblank :(
11051 */
11052
11053 /*
11054 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11055 * used the same base address. In that case the mmio flip might
11056 * have completed, but the CS hasn't even executed the flip yet.
11057 *
11058 * A flip count check isn't enough as the CS might have updated
11059 * the base address just after start of vblank, but before we
11060 * managed to process the interrupt. This means we'd complete the
11061 * CS flip too soon.
11062 *
11063 * Combining both checks should get us a good enough result. It may
11064 * still happen that the CS flip has been executed, but has not
11065 * yet actually completed. But in case the base address is the same
11066 * anyway, we don't really care.
11067 */
11068 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11069 crtc->unpin_work->gtt_offset &&
11070 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11071 crtc->unpin_work->flip_count);
11072 }
11073
11074 void intel_prepare_page_flip(struct drm_device *dev, int plane)
11075 {
11076 struct drm_i915_private *dev_priv = dev->dev_private;
11077 struct intel_crtc *intel_crtc =
11078 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11079 unsigned long flags;
11080
11081
11082 /*
11083 * This is called both by irq handlers and the reset code (to complete
11084 * lost pageflips) so needs the full irqsave spinlocks.
11085 *
11086 * NB: An MMIO update of the plane base pointer will also
11087 * generate a page-flip completion irq, i.e. every modeset
11088 * is also accompanied by a spurious intel_prepare_page_flip().
11089 */
11090 spin_lock_irqsave(&dev->event_lock, flags);
11091 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11092 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11093 spin_unlock_irqrestore(&dev->event_lock, flags);
11094 }
11095
11096 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11097 {
11098 /* Ensure that the work item is consistent when activating it ... */
11099 smp_wmb();
11100 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11101 /* and that it is marked active as soon as the irq could fire. */
11102 smp_wmb();
11103 }
11104
11105 static int intel_gen2_queue_flip(struct drm_device *dev,
11106 struct drm_crtc *crtc,
11107 struct drm_framebuffer *fb,
11108 struct drm_i915_gem_object *obj,
11109 struct drm_i915_gem_request *req,
11110 uint32_t flags)
11111 {
11112 struct intel_engine_cs *ring = req->ring;
11113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11114 u32 flip_mask;
11115 int ret;
11116
11117 ret = intel_ring_begin(req, 6);
11118 if (ret)
11119 return ret;
11120
11121 /* Can't queue multiple flips, so wait for the previous
11122 * one to finish before executing the next.
11123 */
11124 if (intel_crtc->plane)
11125 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11126 else
11127 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11128 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11129 intel_ring_emit(ring, MI_NOOP);
11130 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11131 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11132 intel_ring_emit(ring, fb->pitches[0]);
11133 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11134 intel_ring_emit(ring, 0); /* aux display base address, unused */
11135
11136 intel_mark_page_flip_active(intel_crtc->unpin_work);
11137 return 0;
11138 }
11139
11140 static int intel_gen3_queue_flip(struct drm_device *dev,
11141 struct drm_crtc *crtc,
11142 struct drm_framebuffer *fb,
11143 struct drm_i915_gem_object *obj,
11144 struct drm_i915_gem_request *req,
11145 uint32_t flags)
11146 {
11147 struct intel_engine_cs *ring = req->ring;
11148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11149 u32 flip_mask;
11150 int ret;
11151
11152 ret = intel_ring_begin(req, 6);
11153 if (ret)
11154 return ret;
11155
11156 if (intel_crtc->plane)
11157 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11158 else
11159 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11160 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11161 intel_ring_emit(ring, MI_NOOP);
11162 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11163 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11164 intel_ring_emit(ring, fb->pitches[0]);
11165 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11166 intel_ring_emit(ring, MI_NOOP);
11167
11168 intel_mark_page_flip_active(intel_crtc->unpin_work);
11169 return 0;
11170 }
11171
11172 static int intel_gen4_queue_flip(struct drm_device *dev,
11173 struct drm_crtc *crtc,
11174 struct drm_framebuffer *fb,
11175 struct drm_i915_gem_object *obj,
11176 struct drm_i915_gem_request *req,
11177 uint32_t flags)
11178 {
11179 struct intel_engine_cs *ring = req->ring;
11180 struct drm_i915_private *dev_priv = dev->dev_private;
11181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11182 uint32_t pf, pipesrc;
11183 int ret;
11184
11185 ret = intel_ring_begin(req, 4);
11186 if (ret)
11187 return ret;
11188
11189 /* i965+ uses the linear or tiled offsets from the
11190 * Display Registers (which do not change across a page-flip)
11191 * so we need only reprogram the base address.
11192 */
11193 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11194 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11195 intel_ring_emit(ring, fb->pitches[0]);
11196 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11197 obj->tiling_mode);
11198
11199 /* XXX Enabling the panel-fitter across page-flip is so far
11200 * untested on non-native modes, so ignore it for now.
11201 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11202 */
11203 pf = 0;
11204 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11205 intel_ring_emit(ring, pf | pipesrc);
11206
11207 intel_mark_page_flip_active(intel_crtc->unpin_work);
11208 return 0;
11209 }
11210
11211 static int intel_gen6_queue_flip(struct drm_device *dev,
11212 struct drm_crtc *crtc,
11213 struct drm_framebuffer *fb,
11214 struct drm_i915_gem_object *obj,
11215 struct drm_i915_gem_request *req,
11216 uint32_t flags)
11217 {
11218 struct intel_engine_cs *ring = req->ring;
11219 struct drm_i915_private *dev_priv = dev->dev_private;
11220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11221 uint32_t pf, pipesrc;
11222 int ret;
11223
11224 ret = intel_ring_begin(req, 4);
11225 if (ret)
11226 return ret;
11227
11228 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11229 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11230 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11231 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11232
11233 /* Contrary to the suggestions in the documentation,
11234 * "Enable Panel Fitter" does not seem to be required when page
11235 * flipping with a non-native mode, and worse causes a normal
11236 * modeset to fail.
11237 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11238 */
11239 pf = 0;
11240 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11241 intel_ring_emit(ring, pf | pipesrc);
11242
11243 intel_mark_page_flip_active(intel_crtc->unpin_work);
11244 return 0;
11245 }
11246
11247 static int intel_gen7_queue_flip(struct drm_device *dev,
11248 struct drm_crtc *crtc,
11249 struct drm_framebuffer *fb,
11250 struct drm_i915_gem_object *obj,
11251 struct drm_i915_gem_request *req,
11252 uint32_t flags)
11253 {
11254 struct intel_engine_cs *ring = req->ring;
11255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11256 uint32_t plane_bit = 0;
11257 int len, ret;
11258
11259 switch (intel_crtc->plane) {
11260 case PLANE_A:
11261 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11262 break;
11263 case PLANE_B:
11264 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11265 break;
11266 case PLANE_C:
11267 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11268 break;
11269 default:
11270 WARN_ONCE(1, "unknown plane in flip command\n");
11271 return -ENODEV;
11272 }
11273
11274 len = 4;
11275 if (ring->id == RCS) {
11276 len += 6;
11277 /*
11278 * On Gen 8, SRM is now taking an extra dword to accommodate
11279 * 48bits addresses, and we need a NOOP for the batch size to
11280 * stay even.
11281 */
11282 if (IS_GEN8(dev))
11283 len += 2;
11284 }
11285
11286 /*
11287 * BSpec MI_DISPLAY_FLIP for IVB:
11288 * "The full packet must be contained within the same cache line."
11289 *
11290 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11291 * cacheline, if we ever start emitting more commands before
11292 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11293 * then do the cacheline alignment, and finally emit the
11294 * MI_DISPLAY_FLIP.
11295 */
11296 ret = intel_ring_cacheline_align(req);
11297 if (ret)
11298 return ret;
11299
11300 ret = intel_ring_begin(req, len);
11301 if (ret)
11302 return ret;
11303
11304 /* Unmask the flip-done completion message. Note that the bspec says that
11305 * we should do this for both the BCS and RCS, and that we must not unmask
11306 * more than one flip event at any time (or ensure that one flip message
11307 * can be sent by waiting for flip-done prior to queueing new flips).
11308 * Experimentation says that BCS works despite DERRMR masking all
11309 * flip-done completion events and that unmasking all planes at once
11310 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11311 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11312 */
11313 if (ring->id == RCS) {
11314 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11315 intel_ring_emit_reg(ring, DERRMR);
11316 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11317 DERRMR_PIPEB_PRI_FLIP_DONE |
11318 DERRMR_PIPEC_PRI_FLIP_DONE));
11319 if (IS_GEN8(dev))
11320 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11321 MI_SRM_LRM_GLOBAL_GTT);
11322 else
11323 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11324 MI_SRM_LRM_GLOBAL_GTT);
11325 intel_ring_emit_reg(ring, DERRMR);
11326 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11327 if (IS_GEN8(dev)) {
11328 intel_ring_emit(ring, 0);
11329 intel_ring_emit(ring, MI_NOOP);
11330 }
11331 }
11332
11333 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11334 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11335 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11336 intel_ring_emit(ring, (MI_NOOP));
11337
11338 intel_mark_page_flip_active(intel_crtc->unpin_work);
11339 return 0;
11340 }
11341
11342 static bool use_mmio_flip(struct intel_engine_cs *ring,
11343 struct drm_i915_gem_object *obj)
11344 {
11345 /*
11346 * This is not being used for older platforms, because
11347 * non-availability of flip done interrupt forces us to use
11348 * CS flips. Older platforms derive flip done using some clever
11349 * tricks involving the flip_pending status bits and vblank irqs.
11350 * So using MMIO flips there would disrupt this mechanism.
11351 */
11352
11353 if (ring == NULL)
11354 return true;
11355
11356 if (INTEL_INFO(ring->dev)->gen < 5)
11357 return false;
11358
11359 if (i915.use_mmio_flip < 0)
11360 return false;
11361 else if (i915.use_mmio_flip > 0)
11362 return true;
11363 else if (i915.enable_execlists)
11364 return true;
11365 else if (obj->base.dma_buf &&
11366 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11367 false))
11368 return true;
11369 else
11370 return ring != i915_gem_request_get_ring(obj->last_write_req);
11371 }
11372
11373 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11374 unsigned int rotation,
11375 struct intel_unpin_work *work)
11376 {
11377 struct drm_device *dev = intel_crtc->base.dev;
11378 struct drm_i915_private *dev_priv = dev->dev_private;
11379 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11380 const enum pipe pipe = intel_crtc->pipe;
11381 u32 ctl, stride, tile_height;
11382
11383 ctl = I915_READ(PLANE_CTL(pipe, 0));
11384 ctl &= ~PLANE_CTL_TILED_MASK;
11385 switch (fb->modifier[0]) {
11386 case DRM_FORMAT_MOD_NONE:
11387 break;
11388 case I915_FORMAT_MOD_X_TILED:
11389 ctl |= PLANE_CTL_TILED_X;
11390 break;
11391 case I915_FORMAT_MOD_Y_TILED:
11392 ctl |= PLANE_CTL_TILED_Y;
11393 break;
11394 case I915_FORMAT_MOD_Yf_TILED:
11395 ctl |= PLANE_CTL_TILED_YF;
11396 break;
11397 default:
11398 MISSING_CASE(fb->modifier[0]);
11399 }
11400
11401 /*
11402 * The stride is either expressed as a multiple of 64 bytes chunks for
11403 * linear buffers or in number of tiles for tiled buffers.
11404 */
11405 if (intel_rotation_90_or_270(rotation)) {
11406 /* stride = Surface height in tiles */
11407 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11408 stride = DIV_ROUND_UP(fb->height, tile_height);
11409 } else {
11410 stride = fb->pitches[0] /
11411 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11412 fb->pixel_format);
11413 }
11414
11415 /*
11416 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11417 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11418 */
11419 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11420 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11421
11422 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11423 POSTING_READ(PLANE_SURF(pipe, 0));
11424 }
11425
11426 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11427 struct intel_unpin_work *work)
11428 {
11429 struct drm_device *dev = intel_crtc->base.dev;
11430 struct drm_i915_private *dev_priv = dev->dev_private;
11431 struct intel_framebuffer *intel_fb =
11432 to_intel_framebuffer(intel_crtc->base.primary->fb);
11433 struct drm_i915_gem_object *obj = intel_fb->obj;
11434 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11435 u32 dspcntr;
11436
11437 dspcntr = I915_READ(reg);
11438
11439 if (obj->tiling_mode != I915_TILING_NONE)
11440 dspcntr |= DISPPLANE_TILED;
11441 else
11442 dspcntr &= ~DISPPLANE_TILED;
11443
11444 I915_WRITE(reg, dspcntr);
11445
11446 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11447 POSTING_READ(DSPSURF(intel_crtc->plane));
11448 }
11449
11450 /*
11451 * XXX: This is the temporary way to update the plane registers until we get
11452 * around to using the usual plane update functions for MMIO flips
11453 */
11454 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11455 {
11456 struct intel_crtc *crtc = mmio_flip->crtc;
11457 struct intel_unpin_work *work;
11458
11459 spin_lock_irq(&crtc->base.dev->event_lock);
11460 work = crtc->unpin_work;
11461 spin_unlock_irq(&crtc->base.dev->event_lock);
11462 if (work == NULL)
11463 return;
11464
11465 intel_mark_page_flip_active(work);
11466
11467 intel_pipe_update_start(crtc);
11468
11469 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11470 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11471 else
11472 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11473 ilk_do_mmio_flip(crtc, work);
11474
11475 intel_pipe_update_end(crtc);
11476 }
11477
11478 static void intel_mmio_flip_work_func(struct work_struct *work)
11479 {
11480 struct intel_mmio_flip *mmio_flip =
11481 container_of(work, struct intel_mmio_flip, work);
11482 struct intel_framebuffer *intel_fb =
11483 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11484 struct drm_i915_gem_object *obj = intel_fb->obj;
11485
11486 if (mmio_flip->req) {
11487 WARN_ON(__i915_wait_request(mmio_flip->req,
11488 mmio_flip->crtc->reset_counter,
11489 false, NULL,
11490 &mmio_flip->i915->rps.mmioflips));
11491 i915_gem_request_unreference__unlocked(mmio_flip->req);
11492 }
11493
11494 /* For framebuffer backed by dmabuf, wait for fence */
11495 if (obj->base.dma_buf)
11496 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11497 false, false,
11498 MAX_SCHEDULE_TIMEOUT) < 0);
11499
11500 intel_do_mmio_flip(mmio_flip);
11501 kfree(mmio_flip);
11502 }
11503
11504 static int intel_queue_mmio_flip(struct drm_device *dev,
11505 struct drm_crtc *crtc,
11506 struct drm_i915_gem_object *obj)
11507 {
11508 struct intel_mmio_flip *mmio_flip;
11509
11510 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11511 if (mmio_flip == NULL)
11512 return -ENOMEM;
11513
11514 mmio_flip->i915 = to_i915(dev);
11515 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11516 mmio_flip->crtc = to_intel_crtc(crtc);
11517 mmio_flip->rotation = crtc->primary->state->rotation;
11518
11519 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11520 schedule_work(&mmio_flip->work);
11521
11522 return 0;
11523 }
11524
11525 static int intel_default_queue_flip(struct drm_device *dev,
11526 struct drm_crtc *crtc,
11527 struct drm_framebuffer *fb,
11528 struct drm_i915_gem_object *obj,
11529 struct drm_i915_gem_request *req,
11530 uint32_t flags)
11531 {
11532 return -ENODEV;
11533 }
11534
11535 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11536 struct drm_crtc *crtc)
11537 {
11538 struct drm_i915_private *dev_priv = dev->dev_private;
11539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11540 struct intel_unpin_work *work = intel_crtc->unpin_work;
11541 u32 addr;
11542
11543 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11544 return true;
11545
11546 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11547 return false;
11548
11549 if (!work->enable_stall_check)
11550 return false;
11551
11552 if (work->flip_ready_vblank == 0) {
11553 if (work->flip_queued_req &&
11554 !i915_gem_request_completed(work->flip_queued_req, true))
11555 return false;
11556
11557 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11558 }
11559
11560 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11561 return false;
11562
11563 /* Potential stall - if we see that the flip has happened,
11564 * assume a missed interrupt. */
11565 if (INTEL_INFO(dev)->gen >= 4)
11566 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11567 else
11568 addr = I915_READ(DSPADDR(intel_crtc->plane));
11569
11570 /* There is a potential issue here with a false positive after a flip
11571 * to the same address. We could address this by checking for a
11572 * non-incrementing frame counter.
11573 */
11574 return addr == work->gtt_offset;
11575 }
11576
11577 void intel_check_page_flip(struct drm_device *dev, int pipe)
11578 {
11579 struct drm_i915_private *dev_priv = dev->dev_private;
11580 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11582 struct intel_unpin_work *work;
11583
11584 WARN_ON(!in_interrupt());
11585
11586 if (crtc == NULL)
11587 return;
11588
11589 spin_lock(&dev->event_lock);
11590 work = intel_crtc->unpin_work;
11591 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11592 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11593 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11594 page_flip_completed(intel_crtc);
11595 work = NULL;
11596 }
11597 if (work != NULL &&
11598 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11599 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11600 spin_unlock(&dev->event_lock);
11601 }
11602
11603 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11604 struct drm_framebuffer *fb,
11605 struct drm_pending_vblank_event *event,
11606 uint32_t page_flip_flags)
11607 {
11608 struct drm_device *dev = crtc->dev;
11609 struct drm_i915_private *dev_priv = dev->dev_private;
11610 struct drm_framebuffer *old_fb = crtc->primary->fb;
11611 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11613 struct drm_plane *primary = crtc->primary;
11614 enum pipe pipe = intel_crtc->pipe;
11615 struct intel_unpin_work *work;
11616 struct intel_engine_cs *ring;
11617 bool mmio_flip;
11618 struct drm_i915_gem_request *request = NULL;
11619 int ret;
11620
11621 /*
11622 * drm_mode_page_flip_ioctl() should already catch this, but double
11623 * check to be safe. In the future we may enable pageflipping from
11624 * a disabled primary plane.
11625 */
11626 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11627 return -EBUSY;
11628
11629 /* Can't change pixel format via MI display flips. */
11630 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11631 return -EINVAL;
11632
11633 /*
11634 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11635 * Note that pitch changes could also affect these register.
11636 */
11637 if (INTEL_INFO(dev)->gen > 3 &&
11638 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11639 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11640 return -EINVAL;
11641
11642 if (i915_terminally_wedged(&dev_priv->gpu_error))
11643 goto out_hang;
11644
11645 work = kzalloc(sizeof(*work), GFP_KERNEL);
11646 if (work == NULL)
11647 return -ENOMEM;
11648
11649 work->event = event;
11650 work->crtc = crtc;
11651 work->old_fb = old_fb;
11652 INIT_WORK(&work->work, intel_unpin_work_fn);
11653
11654 ret = drm_crtc_vblank_get(crtc);
11655 if (ret)
11656 goto free_work;
11657
11658 /* We borrow the event spin lock for protecting unpin_work */
11659 spin_lock_irq(&dev->event_lock);
11660 if (intel_crtc->unpin_work) {
11661 /* Before declaring the flip queue wedged, check if
11662 * the hardware completed the operation behind our backs.
11663 */
11664 if (__intel_pageflip_stall_check(dev, crtc)) {
11665 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11666 page_flip_completed(intel_crtc);
11667 } else {
11668 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11669 spin_unlock_irq(&dev->event_lock);
11670
11671 drm_crtc_vblank_put(crtc);
11672 kfree(work);
11673 return -EBUSY;
11674 }
11675 }
11676 intel_crtc->unpin_work = work;
11677 spin_unlock_irq(&dev->event_lock);
11678
11679 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11680 flush_workqueue(dev_priv->wq);
11681
11682 /* Reference the objects for the scheduled work. */
11683 drm_framebuffer_reference(work->old_fb);
11684 drm_gem_object_reference(&obj->base);
11685
11686 crtc->primary->fb = fb;
11687 update_state_fb(crtc->primary);
11688 intel_fbc_pre_update(intel_crtc);
11689
11690 work->pending_flip_obj = obj;
11691
11692 ret = i915_mutex_lock_interruptible(dev);
11693 if (ret)
11694 goto cleanup;
11695
11696 atomic_inc(&intel_crtc->unpin_work_count);
11697 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11698
11699 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11700 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11701
11702 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11703 ring = &dev_priv->ring[BCS];
11704 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11705 /* vlv: DISPLAY_FLIP fails to change tiling */
11706 ring = NULL;
11707 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11708 ring = &dev_priv->ring[BCS];
11709 } else if (INTEL_INFO(dev)->gen >= 7) {
11710 ring = i915_gem_request_get_ring(obj->last_write_req);
11711 if (ring == NULL || ring->id != RCS)
11712 ring = &dev_priv->ring[BCS];
11713 } else {
11714 ring = &dev_priv->ring[RCS];
11715 }
11716
11717 mmio_flip = use_mmio_flip(ring, obj);
11718
11719 /* When using CS flips, we want to emit semaphores between rings.
11720 * However, when using mmio flips we will create a task to do the
11721 * synchronisation, so all we want here is to pin the framebuffer
11722 * into the display plane and skip any waits.
11723 */
11724 if (!mmio_flip) {
11725 ret = i915_gem_object_sync(obj, ring, &request);
11726 if (ret)
11727 goto cleanup_pending;
11728 }
11729
11730 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11731 if (ret)
11732 goto cleanup_pending;
11733
11734 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11735 obj, 0);
11736 work->gtt_offset += intel_crtc->dspaddr_offset;
11737
11738 if (mmio_flip) {
11739 ret = intel_queue_mmio_flip(dev, crtc, obj);
11740 if (ret)
11741 goto cleanup_unpin;
11742
11743 i915_gem_request_assign(&work->flip_queued_req,
11744 obj->last_write_req);
11745 } else {
11746 if (!request) {
11747 request = i915_gem_request_alloc(ring, NULL);
11748 if (IS_ERR(request)) {
11749 ret = PTR_ERR(request);
11750 goto cleanup_unpin;
11751 }
11752 }
11753
11754 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11755 page_flip_flags);
11756 if (ret)
11757 goto cleanup_unpin;
11758
11759 i915_gem_request_assign(&work->flip_queued_req, request);
11760 }
11761
11762 if (request)
11763 i915_add_request_no_flush(request);
11764
11765 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11766 work->enable_stall_check = true;
11767
11768 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11769 to_intel_plane(primary)->frontbuffer_bit);
11770 mutex_unlock(&dev->struct_mutex);
11771
11772 intel_frontbuffer_flip_prepare(dev,
11773 to_intel_plane(primary)->frontbuffer_bit);
11774
11775 trace_i915_flip_request(intel_crtc->plane, obj);
11776
11777 return 0;
11778
11779 cleanup_unpin:
11780 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11781 cleanup_pending:
11782 if (!IS_ERR_OR_NULL(request))
11783 i915_gem_request_cancel(request);
11784 atomic_dec(&intel_crtc->unpin_work_count);
11785 mutex_unlock(&dev->struct_mutex);
11786 cleanup:
11787 crtc->primary->fb = old_fb;
11788 update_state_fb(crtc->primary);
11789
11790 drm_gem_object_unreference_unlocked(&obj->base);
11791 drm_framebuffer_unreference(work->old_fb);
11792
11793 spin_lock_irq(&dev->event_lock);
11794 intel_crtc->unpin_work = NULL;
11795 spin_unlock_irq(&dev->event_lock);
11796
11797 drm_crtc_vblank_put(crtc);
11798 free_work:
11799 kfree(work);
11800
11801 if (ret == -EIO) {
11802 struct drm_atomic_state *state;
11803 struct drm_plane_state *plane_state;
11804
11805 out_hang:
11806 state = drm_atomic_state_alloc(dev);
11807 if (!state)
11808 return -ENOMEM;
11809 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11810
11811 retry:
11812 plane_state = drm_atomic_get_plane_state(state, primary);
11813 ret = PTR_ERR_OR_ZERO(plane_state);
11814 if (!ret) {
11815 drm_atomic_set_fb_for_plane(plane_state, fb);
11816
11817 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11818 if (!ret)
11819 ret = drm_atomic_commit(state);
11820 }
11821
11822 if (ret == -EDEADLK) {
11823 drm_modeset_backoff(state->acquire_ctx);
11824 drm_atomic_state_clear(state);
11825 goto retry;
11826 }
11827
11828 if (ret)
11829 drm_atomic_state_free(state);
11830
11831 if (ret == 0 && event) {
11832 spin_lock_irq(&dev->event_lock);
11833 drm_send_vblank_event(dev, pipe, event);
11834 spin_unlock_irq(&dev->event_lock);
11835 }
11836 }
11837 return ret;
11838 }
11839
11840
11841 /**
11842 * intel_wm_need_update - Check whether watermarks need updating
11843 * @plane: drm plane
11844 * @state: new plane state
11845 *
11846 * Check current plane state versus the new one to determine whether
11847 * watermarks need to be recalculated.
11848 *
11849 * Returns true or false.
11850 */
11851 static bool intel_wm_need_update(struct drm_plane *plane,
11852 struct drm_plane_state *state)
11853 {
11854 struct intel_plane_state *new = to_intel_plane_state(state);
11855 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11856
11857 /* Update watermarks on tiling or size changes. */
11858 if (new->visible != cur->visible)
11859 return true;
11860
11861 if (!cur->base.fb || !new->base.fb)
11862 return false;
11863
11864 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11865 cur->base.rotation != new->base.rotation ||
11866 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11867 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11868 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11869 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11870 return true;
11871
11872 return false;
11873 }
11874
11875 static bool needs_scaling(struct intel_plane_state *state)
11876 {
11877 int src_w = drm_rect_width(&state->src) >> 16;
11878 int src_h = drm_rect_height(&state->src) >> 16;
11879 int dst_w = drm_rect_width(&state->dst);
11880 int dst_h = drm_rect_height(&state->dst);
11881
11882 return (src_w != dst_w || src_h != dst_h);
11883 }
11884
11885 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11886 struct drm_plane_state *plane_state)
11887 {
11888 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11889 struct drm_crtc *crtc = crtc_state->crtc;
11890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11891 struct drm_plane *plane = plane_state->plane;
11892 struct drm_device *dev = crtc->dev;
11893 struct drm_i915_private *dev_priv = to_i915(dev);
11894 struct intel_plane_state *old_plane_state =
11895 to_intel_plane_state(plane->state);
11896 int idx = intel_crtc->base.base.id, ret;
11897 bool mode_changed = needs_modeset(crtc_state);
11898 bool was_crtc_enabled = crtc->state->active;
11899 bool is_crtc_enabled = crtc_state->active;
11900 bool turn_off, turn_on, visible, was_visible;
11901 struct drm_framebuffer *fb = plane_state->fb;
11902
11903 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11904 plane->type != DRM_PLANE_TYPE_CURSOR) {
11905 ret = skl_update_scaler_plane(
11906 to_intel_crtc_state(crtc_state),
11907 to_intel_plane_state(plane_state));
11908 if (ret)
11909 return ret;
11910 }
11911
11912 was_visible = old_plane_state->visible;
11913 visible = to_intel_plane_state(plane_state)->visible;
11914
11915 if (!was_crtc_enabled && WARN_ON(was_visible))
11916 was_visible = false;
11917
11918 /*
11919 * Visibility is calculated as if the crtc was on, but
11920 * after scaler setup everything depends on it being off
11921 * when the crtc isn't active.
11922 */
11923 if (!is_crtc_enabled)
11924 to_intel_plane_state(plane_state)->visible = visible = false;
11925
11926 if (!was_visible && !visible)
11927 return 0;
11928
11929 if (fb != old_plane_state->base.fb)
11930 pipe_config->fb_changed = true;
11931
11932 turn_off = was_visible && (!visible || mode_changed);
11933 turn_on = visible && (!was_visible || mode_changed);
11934
11935 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11936 plane->base.id, fb ? fb->base.id : -1);
11937
11938 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11939 plane->base.id, was_visible, visible,
11940 turn_off, turn_on, mode_changed);
11941
11942 if (turn_on || turn_off) {
11943 pipe_config->wm_changed = true;
11944
11945 /* must disable cxsr around plane enable/disable */
11946 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11947 pipe_config->disable_cxsr = true;
11948 } else if (intel_wm_need_update(plane, plane_state)) {
11949 pipe_config->wm_changed = true;
11950 }
11951
11952 /* Pre-gen9 platforms need two-step watermark updates */
11953 if (pipe_config->wm_changed && INTEL_INFO(dev)->gen < 9 &&
11954 dev_priv->display.optimize_watermarks)
11955 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11956
11957 if (visible || was_visible)
11958 intel_crtc->atomic.fb_bits |=
11959 to_intel_plane(plane)->frontbuffer_bit;
11960
11961 switch (plane->type) {
11962 case DRM_PLANE_TYPE_PRIMARY:
11963 intel_crtc->atomic.post_enable_primary = turn_on;
11964 intel_crtc->atomic.update_fbc = true;
11965
11966 break;
11967 case DRM_PLANE_TYPE_CURSOR:
11968 break;
11969 case DRM_PLANE_TYPE_OVERLAY:
11970 /*
11971 * WaCxSRDisabledForSpriteScaling:ivb
11972 *
11973 * cstate->update_wm was already set above, so this flag will
11974 * take effect when we commit and program watermarks.
11975 */
11976 if (IS_IVYBRIDGE(dev) &&
11977 needs_scaling(to_intel_plane_state(plane_state)) &&
11978 !needs_scaling(old_plane_state))
11979 pipe_config->disable_lp_wm = true;
11980
11981 break;
11982 }
11983 return 0;
11984 }
11985
11986 static bool encoders_cloneable(const struct intel_encoder *a,
11987 const struct intel_encoder *b)
11988 {
11989 /* masks could be asymmetric, so check both ways */
11990 return a == b || (a->cloneable & (1 << b->type) &&
11991 b->cloneable & (1 << a->type));
11992 }
11993
11994 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11995 struct intel_crtc *crtc,
11996 struct intel_encoder *encoder)
11997 {
11998 struct intel_encoder *source_encoder;
11999 struct drm_connector *connector;
12000 struct drm_connector_state *connector_state;
12001 int i;
12002
12003 for_each_connector_in_state(state, connector, connector_state, i) {
12004 if (connector_state->crtc != &crtc->base)
12005 continue;
12006
12007 source_encoder =
12008 to_intel_encoder(connector_state->best_encoder);
12009 if (!encoders_cloneable(encoder, source_encoder))
12010 return false;
12011 }
12012
12013 return true;
12014 }
12015
12016 static bool check_encoder_cloning(struct drm_atomic_state *state,
12017 struct intel_crtc *crtc)
12018 {
12019 struct intel_encoder *encoder;
12020 struct drm_connector *connector;
12021 struct drm_connector_state *connector_state;
12022 int i;
12023
12024 for_each_connector_in_state(state, connector, connector_state, i) {
12025 if (connector_state->crtc != &crtc->base)
12026 continue;
12027
12028 encoder = to_intel_encoder(connector_state->best_encoder);
12029 if (!check_single_encoder_cloning(state, crtc, encoder))
12030 return false;
12031 }
12032
12033 return true;
12034 }
12035
12036 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12037 struct drm_crtc_state *crtc_state)
12038 {
12039 struct drm_device *dev = crtc->dev;
12040 struct drm_i915_private *dev_priv = dev->dev_private;
12041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12042 struct intel_crtc_state *pipe_config =
12043 to_intel_crtc_state(crtc_state);
12044 struct drm_atomic_state *state = crtc_state->state;
12045 int ret;
12046 bool mode_changed = needs_modeset(crtc_state);
12047
12048 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12049 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12050 return -EINVAL;
12051 }
12052
12053 if (mode_changed && !crtc_state->active)
12054 pipe_config->wm_changed = true;
12055
12056 if (mode_changed && crtc_state->enable &&
12057 dev_priv->display.crtc_compute_clock &&
12058 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
12059 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12060 pipe_config);
12061 if (ret)
12062 return ret;
12063 }
12064
12065 ret = 0;
12066 if (dev_priv->display.compute_pipe_wm) {
12067 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
12068 if (ret) {
12069 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12070 return ret;
12071 }
12072 }
12073
12074 if (dev_priv->display.compute_intermediate_wm &&
12075 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12076 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12077 return 0;
12078
12079 /*
12080 * Calculate 'intermediate' watermarks that satisfy both the
12081 * old state and the new state. We can program these
12082 * immediately.
12083 */
12084 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12085 intel_crtc,
12086 pipe_config);
12087 if (ret) {
12088 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12089 return ret;
12090 }
12091 }
12092
12093 if (INTEL_INFO(dev)->gen >= 9) {
12094 if (mode_changed)
12095 ret = skl_update_scaler_crtc(pipe_config);
12096
12097 if (!ret)
12098 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12099 pipe_config);
12100 }
12101
12102 return ret;
12103 }
12104
12105 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12106 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12107 .load_lut = intel_crtc_load_lut,
12108 .atomic_begin = intel_begin_crtc_commit,
12109 .atomic_flush = intel_finish_crtc_commit,
12110 .atomic_check = intel_crtc_atomic_check,
12111 };
12112
12113 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12114 {
12115 struct intel_connector *connector;
12116
12117 for_each_intel_connector(dev, connector) {
12118 if (connector->base.encoder) {
12119 connector->base.state->best_encoder =
12120 connector->base.encoder;
12121 connector->base.state->crtc =
12122 connector->base.encoder->crtc;
12123 } else {
12124 connector->base.state->best_encoder = NULL;
12125 connector->base.state->crtc = NULL;
12126 }
12127 }
12128 }
12129
12130 static void
12131 connected_sink_compute_bpp(struct intel_connector *connector,
12132 struct intel_crtc_state *pipe_config)
12133 {
12134 int bpp = pipe_config->pipe_bpp;
12135
12136 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12137 connector->base.base.id,
12138 connector->base.name);
12139
12140 /* Don't use an invalid EDID bpc value */
12141 if (connector->base.display_info.bpc &&
12142 connector->base.display_info.bpc * 3 < bpp) {
12143 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12144 bpp, connector->base.display_info.bpc*3);
12145 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12146 }
12147
12148 /* Clamp bpp to default limit on screens without EDID 1.4 */
12149 if (connector->base.display_info.bpc == 0) {
12150 int type = connector->base.connector_type;
12151 int clamp_bpp = 24;
12152
12153 /* Fall back to 18 bpp when DP sink capability is unknown. */
12154 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12155 type == DRM_MODE_CONNECTOR_eDP)
12156 clamp_bpp = 18;
12157
12158 if (bpp > clamp_bpp) {
12159 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12160 bpp, clamp_bpp);
12161 pipe_config->pipe_bpp = clamp_bpp;
12162 }
12163 }
12164 }
12165
12166 static int
12167 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12168 struct intel_crtc_state *pipe_config)
12169 {
12170 struct drm_device *dev = crtc->base.dev;
12171 struct drm_atomic_state *state;
12172 struct drm_connector *connector;
12173 struct drm_connector_state *connector_state;
12174 int bpp, i;
12175
12176 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12177 bpp = 10*3;
12178 else if (INTEL_INFO(dev)->gen >= 5)
12179 bpp = 12*3;
12180 else
12181 bpp = 8*3;
12182
12183
12184 pipe_config->pipe_bpp = bpp;
12185
12186 state = pipe_config->base.state;
12187
12188 /* Clamp display bpp to EDID value */
12189 for_each_connector_in_state(state, connector, connector_state, i) {
12190 if (connector_state->crtc != &crtc->base)
12191 continue;
12192
12193 connected_sink_compute_bpp(to_intel_connector(connector),
12194 pipe_config);
12195 }
12196
12197 return bpp;
12198 }
12199
12200 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12201 {
12202 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12203 "type: 0x%x flags: 0x%x\n",
12204 mode->crtc_clock,
12205 mode->crtc_hdisplay, mode->crtc_hsync_start,
12206 mode->crtc_hsync_end, mode->crtc_htotal,
12207 mode->crtc_vdisplay, mode->crtc_vsync_start,
12208 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12209 }
12210
12211 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12212 struct intel_crtc_state *pipe_config,
12213 const char *context)
12214 {
12215 struct drm_device *dev = crtc->base.dev;
12216 struct drm_plane *plane;
12217 struct intel_plane *intel_plane;
12218 struct intel_plane_state *state;
12219 struct drm_framebuffer *fb;
12220
12221 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12222 context, pipe_config, pipe_name(crtc->pipe));
12223
12224 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12225 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12226 pipe_config->pipe_bpp, pipe_config->dither);
12227 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12228 pipe_config->has_pch_encoder,
12229 pipe_config->fdi_lanes,
12230 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12231 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12232 pipe_config->fdi_m_n.tu);
12233 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12234 pipe_config->has_dp_encoder,
12235 pipe_config->lane_count,
12236 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12237 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12238 pipe_config->dp_m_n.tu);
12239
12240 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12241 pipe_config->has_dp_encoder,
12242 pipe_config->lane_count,
12243 pipe_config->dp_m2_n2.gmch_m,
12244 pipe_config->dp_m2_n2.gmch_n,
12245 pipe_config->dp_m2_n2.link_m,
12246 pipe_config->dp_m2_n2.link_n,
12247 pipe_config->dp_m2_n2.tu);
12248
12249 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12250 pipe_config->has_audio,
12251 pipe_config->has_infoframe);
12252
12253 DRM_DEBUG_KMS("requested mode:\n");
12254 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12255 DRM_DEBUG_KMS("adjusted mode:\n");
12256 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12257 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12258 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12259 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12260 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12261 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12262 crtc->num_scalers,
12263 pipe_config->scaler_state.scaler_users,
12264 pipe_config->scaler_state.scaler_id);
12265 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12266 pipe_config->gmch_pfit.control,
12267 pipe_config->gmch_pfit.pgm_ratios,
12268 pipe_config->gmch_pfit.lvds_border_bits);
12269 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12270 pipe_config->pch_pfit.pos,
12271 pipe_config->pch_pfit.size,
12272 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12273 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12274 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12275
12276 if (IS_BROXTON(dev)) {
12277 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12278 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12279 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12280 pipe_config->ddi_pll_sel,
12281 pipe_config->dpll_hw_state.ebb0,
12282 pipe_config->dpll_hw_state.ebb4,
12283 pipe_config->dpll_hw_state.pll0,
12284 pipe_config->dpll_hw_state.pll1,
12285 pipe_config->dpll_hw_state.pll2,
12286 pipe_config->dpll_hw_state.pll3,
12287 pipe_config->dpll_hw_state.pll6,
12288 pipe_config->dpll_hw_state.pll8,
12289 pipe_config->dpll_hw_state.pll9,
12290 pipe_config->dpll_hw_state.pll10,
12291 pipe_config->dpll_hw_state.pcsdw12);
12292 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12293 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12294 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12295 pipe_config->ddi_pll_sel,
12296 pipe_config->dpll_hw_state.ctrl1,
12297 pipe_config->dpll_hw_state.cfgcr1,
12298 pipe_config->dpll_hw_state.cfgcr2);
12299 } else if (HAS_DDI(dev)) {
12300 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12301 pipe_config->ddi_pll_sel,
12302 pipe_config->dpll_hw_state.wrpll,
12303 pipe_config->dpll_hw_state.spll);
12304 } else {
12305 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12306 "fp0: 0x%x, fp1: 0x%x\n",
12307 pipe_config->dpll_hw_state.dpll,
12308 pipe_config->dpll_hw_state.dpll_md,
12309 pipe_config->dpll_hw_state.fp0,
12310 pipe_config->dpll_hw_state.fp1);
12311 }
12312
12313 DRM_DEBUG_KMS("planes on this crtc\n");
12314 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12315 intel_plane = to_intel_plane(plane);
12316 if (intel_plane->pipe != crtc->pipe)
12317 continue;
12318
12319 state = to_intel_plane_state(plane->state);
12320 fb = state->base.fb;
12321 if (!fb) {
12322 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12323 "disabled, scaler_id = %d\n",
12324 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12325 plane->base.id, intel_plane->pipe,
12326 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12327 drm_plane_index(plane), state->scaler_id);
12328 continue;
12329 }
12330
12331 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12332 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12333 plane->base.id, intel_plane->pipe,
12334 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12335 drm_plane_index(plane));
12336 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12337 fb->base.id, fb->width, fb->height, fb->pixel_format);
12338 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12339 state->scaler_id,
12340 state->src.x1 >> 16, state->src.y1 >> 16,
12341 drm_rect_width(&state->src) >> 16,
12342 drm_rect_height(&state->src) >> 16,
12343 state->dst.x1, state->dst.y1,
12344 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12345 }
12346 }
12347
12348 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12349 {
12350 struct drm_device *dev = state->dev;
12351 struct drm_connector *connector;
12352 unsigned int used_ports = 0;
12353
12354 /*
12355 * Walk the connector list instead of the encoder
12356 * list to detect the problem on ddi platforms
12357 * where there's just one encoder per digital port.
12358 */
12359 drm_for_each_connector(connector, dev) {
12360 struct drm_connector_state *connector_state;
12361 struct intel_encoder *encoder;
12362
12363 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12364 if (!connector_state)
12365 connector_state = connector->state;
12366
12367 if (!connector_state->best_encoder)
12368 continue;
12369
12370 encoder = to_intel_encoder(connector_state->best_encoder);
12371
12372 WARN_ON(!connector_state->crtc);
12373
12374 switch (encoder->type) {
12375 unsigned int port_mask;
12376 case INTEL_OUTPUT_UNKNOWN:
12377 if (WARN_ON(!HAS_DDI(dev)))
12378 break;
12379 case INTEL_OUTPUT_DISPLAYPORT:
12380 case INTEL_OUTPUT_HDMI:
12381 case INTEL_OUTPUT_EDP:
12382 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12383
12384 /* the same port mustn't appear more than once */
12385 if (used_ports & port_mask)
12386 return false;
12387
12388 used_ports |= port_mask;
12389 default:
12390 break;
12391 }
12392 }
12393
12394 return true;
12395 }
12396
12397 static void
12398 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12399 {
12400 struct drm_crtc_state tmp_state;
12401 struct intel_crtc_scaler_state scaler_state;
12402 struct intel_dpll_hw_state dpll_hw_state;
12403 enum intel_dpll_id shared_dpll;
12404 uint32_t ddi_pll_sel;
12405 bool force_thru;
12406
12407 /* FIXME: before the switch to atomic started, a new pipe_config was
12408 * kzalloc'd. Code that depends on any field being zero should be
12409 * fixed, so that the crtc_state can be safely duplicated. For now,
12410 * only fields that are know to not cause problems are preserved. */
12411
12412 tmp_state = crtc_state->base;
12413 scaler_state = crtc_state->scaler_state;
12414 shared_dpll = crtc_state->shared_dpll;
12415 dpll_hw_state = crtc_state->dpll_hw_state;
12416 ddi_pll_sel = crtc_state->ddi_pll_sel;
12417 force_thru = crtc_state->pch_pfit.force_thru;
12418
12419 memset(crtc_state, 0, sizeof *crtc_state);
12420
12421 crtc_state->base = tmp_state;
12422 crtc_state->scaler_state = scaler_state;
12423 crtc_state->shared_dpll = shared_dpll;
12424 crtc_state->dpll_hw_state = dpll_hw_state;
12425 crtc_state->ddi_pll_sel = ddi_pll_sel;
12426 crtc_state->pch_pfit.force_thru = force_thru;
12427 }
12428
12429 static int
12430 intel_modeset_pipe_config(struct drm_crtc *crtc,
12431 struct intel_crtc_state *pipe_config)
12432 {
12433 struct drm_atomic_state *state = pipe_config->base.state;
12434 struct intel_encoder *encoder;
12435 struct drm_connector *connector;
12436 struct drm_connector_state *connector_state;
12437 int base_bpp, ret = -EINVAL;
12438 int i;
12439 bool retry = true;
12440
12441 clear_intel_crtc_state(pipe_config);
12442
12443 pipe_config->cpu_transcoder =
12444 (enum transcoder) to_intel_crtc(crtc)->pipe;
12445
12446 /*
12447 * Sanitize sync polarity flags based on requested ones. If neither
12448 * positive or negative polarity is requested, treat this as meaning
12449 * negative polarity.
12450 */
12451 if (!(pipe_config->base.adjusted_mode.flags &
12452 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12453 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12454
12455 if (!(pipe_config->base.adjusted_mode.flags &
12456 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12457 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12458
12459 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12460 pipe_config);
12461 if (base_bpp < 0)
12462 goto fail;
12463
12464 /*
12465 * Determine the real pipe dimensions. Note that stereo modes can
12466 * increase the actual pipe size due to the frame doubling and
12467 * insertion of additional space for blanks between the frame. This
12468 * is stored in the crtc timings. We use the requested mode to do this
12469 * computation to clearly distinguish it from the adjusted mode, which
12470 * can be changed by the connectors in the below retry loop.
12471 */
12472 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12473 &pipe_config->pipe_src_w,
12474 &pipe_config->pipe_src_h);
12475
12476 encoder_retry:
12477 /* Ensure the port clock defaults are reset when retrying. */
12478 pipe_config->port_clock = 0;
12479 pipe_config->pixel_multiplier = 1;
12480
12481 /* Fill in default crtc timings, allow encoders to overwrite them. */
12482 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12483 CRTC_STEREO_DOUBLE);
12484
12485 /* Pass our mode to the connectors and the CRTC to give them a chance to
12486 * adjust it according to limitations or connector properties, and also
12487 * a chance to reject the mode entirely.
12488 */
12489 for_each_connector_in_state(state, connector, connector_state, i) {
12490 if (connector_state->crtc != crtc)
12491 continue;
12492
12493 encoder = to_intel_encoder(connector_state->best_encoder);
12494
12495 if (!(encoder->compute_config(encoder, pipe_config))) {
12496 DRM_DEBUG_KMS("Encoder config failure\n");
12497 goto fail;
12498 }
12499 }
12500
12501 /* Set default port clock if not overwritten by the encoder. Needs to be
12502 * done afterwards in case the encoder adjusts the mode. */
12503 if (!pipe_config->port_clock)
12504 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12505 * pipe_config->pixel_multiplier;
12506
12507 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12508 if (ret < 0) {
12509 DRM_DEBUG_KMS("CRTC fixup failed\n");
12510 goto fail;
12511 }
12512
12513 if (ret == RETRY) {
12514 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12515 ret = -EINVAL;
12516 goto fail;
12517 }
12518
12519 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12520 retry = false;
12521 goto encoder_retry;
12522 }
12523
12524 /* Dithering seems to not pass-through bits correctly when it should, so
12525 * only enable it on 6bpc panels. */
12526 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12527 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12528 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12529
12530 fail:
12531 return ret;
12532 }
12533
12534 static void
12535 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12536 {
12537 struct drm_crtc *crtc;
12538 struct drm_crtc_state *crtc_state;
12539 int i;
12540
12541 /* Double check state. */
12542 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12543 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12544
12545 /* Update hwmode for vblank functions */
12546 if (crtc->state->active)
12547 crtc->hwmode = crtc->state->adjusted_mode;
12548 else
12549 crtc->hwmode.crtc_clock = 0;
12550
12551 /*
12552 * Update legacy state to satisfy fbc code. This can
12553 * be removed when fbc uses the atomic state.
12554 */
12555 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12556 struct drm_plane_state *plane_state = crtc->primary->state;
12557
12558 crtc->primary->fb = plane_state->fb;
12559 crtc->x = plane_state->src_x >> 16;
12560 crtc->y = plane_state->src_y >> 16;
12561 }
12562 }
12563 }
12564
12565 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12566 {
12567 int diff;
12568
12569 if (clock1 == clock2)
12570 return true;
12571
12572 if (!clock1 || !clock2)
12573 return false;
12574
12575 diff = abs(clock1 - clock2);
12576
12577 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12578 return true;
12579
12580 return false;
12581 }
12582
12583 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12584 list_for_each_entry((intel_crtc), \
12585 &(dev)->mode_config.crtc_list, \
12586 base.head) \
12587 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12588
12589 static bool
12590 intel_compare_m_n(unsigned int m, unsigned int n,
12591 unsigned int m2, unsigned int n2,
12592 bool exact)
12593 {
12594 if (m == m2 && n == n2)
12595 return true;
12596
12597 if (exact || !m || !n || !m2 || !n2)
12598 return false;
12599
12600 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12601
12602 if (n > n2) {
12603 while (n > n2) {
12604 m2 <<= 1;
12605 n2 <<= 1;
12606 }
12607 } else if (n < n2) {
12608 while (n < n2) {
12609 m <<= 1;
12610 n <<= 1;
12611 }
12612 }
12613
12614 if (n != n2)
12615 return false;
12616
12617 return intel_fuzzy_clock_check(m, m2);
12618 }
12619
12620 static bool
12621 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12622 struct intel_link_m_n *m2_n2,
12623 bool adjust)
12624 {
12625 if (m_n->tu == m2_n2->tu &&
12626 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12627 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12628 intel_compare_m_n(m_n->link_m, m_n->link_n,
12629 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12630 if (adjust)
12631 *m2_n2 = *m_n;
12632
12633 return true;
12634 }
12635
12636 return false;
12637 }
12638
12639 static bool
12640 intel_pipe_config_compare(struct drm_device *dev,
12641 struct intel_crtc_state *current_config,
12642 struct intel_crtc_state *pipe_config,
12643 bool adjust)
12644 {
12645 bool ret = true;
12646
12647 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12648 do { \
12649 if (!adjust) \
12650 DRM_ERROR(fmt, ##__VA_ARGS__); \
12651 else \
12652 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12653 } while (0)
12654
12655 #define PIPE_CONF_CHECK_X(name) \
12656 if (current_config->name != pipe_config->name) { \
12657 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12658 "(expected 0x%08x, found 0x%08x)\n", \
12659 current_config->name, \
12660 pipe_config->name); \
12661 ret = false; \
12662 }
12663
12664 #define PIPE_CONF_CHECK_I(name) \
12665 if (current_config->name != pipe_config->name) { \
12666 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12667 "(expected %i, found %i)\n", \
12668 current_config->name, \
12669 pipe_config->name); \
12670 ret = false; \
12671 }
12672
12673 #define PIPE_CONF_CHECK_M_N(name) \
12674 if (!intel_compare_link_m_n(&current_config->name, \
12675 &pipe_config->name,\
12676 adjust)) { \
12677 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12678 "(expected tu %i gmch %i/%i link %i/%i, " \
12679 "found tu %i, gmch %i/%i link %i/%i)\n", \
12680 current_config->name.tu, \
12681 current_config->name.gmch_m, \
12682 current_config->name.gmch_n, \
12683 current_config->name.link_m, \
12684 current_config->name.link_n, \
12685 pipe_config->name.tu, \
12686 pipe_config->name.gmch_m, \
12687 pipe_config->name.gmch_n, \
12688 pipe_config->name.link_m, \
12689 pipe_config->name.link_n); \
12690 ret = false; \
12691 }
12692
12693 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12694 if (!intel_compare_link_m_n(&current_config->name, \
12695 &pipe_config->name, adjust) && \
12696 !intel_compare_link_m_n(&current_config->alt_name, \
12697 &pipe_config->name, adjust)) { \
12698 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12699 "(expected tu %i gmch %i/%i link %i/%i, " \
12700 "or tu %i gmch %i/%i link %i/%i, " \
12701 "found tu %i, gmch %i/%i link %i/%i)\n", \
12702 current_config->name.tu, \
12703 current_config->name.gmch_m, \
12704 current_config->name.gmch_n, \
12705 current_config->name.link_m, \
12706 current_config->name.link_n, \
12707 current_config->alt_name.tu, \
12708 current_config->alt_name.gmch_m, \
12709 current_config->alt_name.gmch_n, \
12710 current_config->alt_name.link_m, \
12711 current_config->alt_name.link_n, \
12712 pipe_config->name.tu, \
12713 pipe_config->name.gmch_m, \
12714 pipe_config->name.gmch_n, \
12715 pipe_config->name.link_m, \
12716 pipe_config->name.link_n); \
12717 ret = false; \
12718 }
12719
12720 /* This is required for BDW+ where there is only one set of registers for
12721 * switching between high and low RR.
12722 * This macro can be used whenever a comparison has to be made between one
12723 * hw state and multiple sw state variables.
12724 */
12725 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12726 if ((current_config->name != pipe_config->name) && \
12727 (current_config->alt_name != pipe_config->name)) { \
12728 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12729 "(expected %i or %i, found %i)\n", \
12730 current_config->name, \
12731 current_config->alt_name, \
12732 pipe_config->name); \
12733 ret = false; \
12734 }
12735
12736 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12737 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12738 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12739 "(expected %i, found %i)\n", \
12740 current_config->name & (mask), \
12741 pipe_config->name & (mask)); \
12742 ret = false; \
12743 }
12744
12745 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12746 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12747 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12748 "(expected %i, found %i)\n", \
12749 current_config->name, \
12750 pipe_config->name); \
12751 ret = false; \
12752 }
12753
12754 #define PIPE_CONF_QUIRK(quirk) \
12755 ((current_config->quirks | pipe_config->quirks) & (quirk))
12756
12757 PIPE_CONF_CHECK_I(cpu_transcoder);
12758
12759 PIPE_CONF_CHECK_I(has_pch_encoder);
12760 PIPE_CONF_CHECK_I(fdi_lanes);
12761 PIPE_CONF_CHECK_M_N(fdi_m_n);
12762
12763 PIPE_CONF_CHECK_I(has_dp_encoder);
12764 PIPE_CONF_CHECK_I(lane_count);
12765
12766 if (INTEL_INFO(dev)->gen < 8) {
12767 PIPE_CONF_CHECK_M_N(dp_m_n);
12768
12769 if (current_config->has_drrs)
12770 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12771 } else
12772 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12773
12774 PIPE_CONF_CHECK_I(has_dsi_encoder);
12775
12776 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12777 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12778 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12779 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12780 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12781 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12782
12783 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12784 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12785 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12786 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12787 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12788 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12789
12790 PIPE_CONF_CHECK_I(pixel_multiplier);
12791 PIPE_CONF_CHECK_I(has_hdmi_sink);
12792 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12793 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12794 PIPE_CONF_CHECK_I(limited_color_range);
12795 PIPE_CONF_CHECK_I(has_infoframe);
12796
12797 PIPE_CONF_CHECK_I(has_audio);
12798
12799 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12800 DRM_MODE_FLAG_INTERLACE);
12801
12802 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12803 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12804 DRM_MODE_FLAG_PHSYNC);
12805 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12806 DRM_MODE_FLAG_NHSYNC);
12807 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12808 DRM_MODE_FLAG_PVSYNC);
12809 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12810 DRM_MODE_FLAG_NVSYNC);
12811 }
12812
12813 PIPE_CONF_CHECK_X(gmch_pfit.control);
12814 /* pfit ratios are autocomputed by the hw on gen4+ */
12815 if (INTEL_INFO(dev)->gen < 4)
12816 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12817 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12818
12819 if (!adjust) {
12820 PIPE_CONF_CHECK_I(pipe_src_w);
12821 PIPE_CONF_CHECK_I(pipe_src_h);
12822
12823 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12824 if (current_config->pch_pfit.enabled) {
12825 PIPE_CONF_CHECK_X(pch_pfit.pos);
12826 PIPE_CONF_CHECK_X(pch_pfit.size);
12827 }
12828
12829 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12830 }
12831
12832 /* BDW+ don't expose a synchronous way to read the state */
12833 if (IS_HASWELL(dev))
12834 PIPE_CONF_CHECK_I(ips_enabled);
12835
12836 PIPE_CONF_CHECK_I(double_wide);
12837
12838 PIPE_CONF_CHECK_X(ddi_pll_sel);
12839
12840 PIPE_CONF_CHECK_I(shared_dpll);
12841 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12842 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12843 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12844 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12845 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12846 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12847 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12848 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12849 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12850
12851 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12852 PIPE_CONF_CHECK_I(pipe_bpp);
12853
12854 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12855 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12856
12857 #undef PIPE_CONF_CHECK_X
12858 #undef PIPE_CONF_CHECK_I
12859 #undef PIPE_CONF_CHECK_I_ALT
12860 #undef PIPE_CONF_CHECK_FLAGS
12861 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12862 #undef PIPE_CONF_QUIRK
12863 #undef INTEL_ERR_OR_DBG_KMS
12864
12865 return ret;
12866 }
12867
12868 static void check_wm_state(struct drm_device *dev)
12869 {
12870 struct drm_i915_private *dev_priv = dev->dev_private;
12871 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12872 struct intel_crtc *intel_crtc;
12873 int plane;
12874
12875 if (INTEL_INFO(dev)->gen < 9)
12876 return;
12877
12878 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12879 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12880
12881 for_each_intel_crtc(dev, intel_crtc) {
12882 struct skl_ddb_entry *hw_entry, *sw_entry;
12883 const enum pipe pipe = intel_crtc->pipe;
12884
12885 if (!intel_crtc->active)
12886 continue;
12887
12888 /* planes */
12889 for_each_plane(dev_priv, pipe, plane) {
12890 hw_entry = &hw_ddb.plane[pipe][plane];
12891 sw_entry = &sw_ddb->plane[pipe][plane];
12892
12893 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12894 continue;
12895
12896 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12897 "(expected (%u,%u), found (%u,%u))\n",
12898 pipe_name(pipe), plane + 1,
12899 sw_entry->start, sw_entry->end,
12900 hw_entry->start, hw_entry->end);
12901 }
12902
12903 /* cursor */
12904 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12905 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12906
12907 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12908 continue;
12909
12910 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12911 "(expected (%u,%u), found (%u,%u))\n",
12912 pipe_name(pipe),
12913 sw_entry->start, sw_entry->end,
12914 hw_entry->start, hw_entry->end);
12915 }
12916 }
12917
12918 static void
12919 check_connector_state(struct drm_device *dev,
12920 struct drm_atomic_state *old_state)
12921 {
12922 struct drm_connector_state *old_conn_state;
12923 struct drm_connector *connector;
12924 int i;
12925
12926 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12927 struct drm_encoder *encoder = connector->encoder;
12928 struct drm_connector_state *state = connector->state;
12929
12930 /* This also checks the encoder/connector hw state with the
12931 * ->get_hw_state callbacks. */
12932 intel_connector_check_state(to_intel_connector(connector));
12933
12934 I915_STATE_WARN(state->best_encoder != encoder,
12935 "connector's atomic encoder doesn't match legacy encoder\n");
12936 }
12937 }
12938
12939 static void
12940 check_encoder_state(struct drm_device *dev)
12941 {
12942 struct intel_encoder *encoder;
12943 struct intel_connector *connector;
12944
12945 for_each_intel_encoder(dev, encoder) {
12946 bool enabled = false;
12947 enum pipe pipe;
12948
12949 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12950 encoder->base.base.id,
12951 encoder->base.name);
12952
12953 for_each_intel_connector(dev, connector) {
12954 if (connector->base.state->best_encoder != &encoder->base)
12955 continue;
12956 enabled = true;
12957
12958 I915_STATE_WARN(connector->base.state->crtc !=
12959 encoder->base.crtc,
12960 "connector's crtc doesn't match encoder crtc\n");
12961 }
12962
12963 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12964 "encoder's enabled state mismatch "
12965 "(expected %i, found %i)\n",
12966 !!encoder->base.crtc, enabled);
12967
12968 if (!encoder->base.crtc) {
12969 bool active;
12970
12971 active = encoder->get_hw_state(encoder, &pipe);
12972 I915_STATE_WARN(active,
12973 "encoder detached but still enabled on pipe %c.\n",
12974 pipe_name(pipe));
12975 }
12976 }
12977 }
12978
12979 static void
12980 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12981 {
12982 struct drm_i915_private *dev_priv = dev->dev_private;
12983 struct intel_encoder *encoder;
12984 struct drm_crtc_state *old_crtc_state;
12985 struct drm_crtc *crtc;
12986 int i;
12987
12988 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12990 struct intel_crtc_state *pipe_config, *sw_config;
12991 bool active;
12992
12993 if (!needs_modeset(crtc->state) &&
12994 !to_intel_crtc_state(crtc->state)->update_pipe)
12995 continue;
12996
12997 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12998 pipe_config = to_intel_crtc_state(old_crtc_state);
12999 memset(pipe_config, 0, sizeof(*pipe_config));
13000 pipe_config->base.crtc = crtc;
13001 pipe_config->base.state = old_state;
13002
13003 DRM_DEBUG_KMS("[CRTC:%d]\n",
13004 crtc->base.id);
13005
13006 active = dev_priv->display.get_pipe_config(intel_crtc,
13007 pipe_config);
13008
13009 /* hw state is inconsistent with the pipe quirk */
13010 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13011 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13012 active = crtc->state->active;
13013
13014 I915_STATE_WARN(crtc->state->active != active,
13015 "crtc active state doesn't match with hw state "
13016 "(expected %i, found %i)\n", crtc->state->active, active);
13017
13018 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
13019 "transitional active state does not match atomic hw state "
13020 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
13021
13022 for_each_encoder_on_crtc(dev, crtc, encoder) {
13023 enum pipe pipe;
13024
13025 active = encoder->get_hw_state(encoder, &pipe);
13026 I915_STATE_WARN(active != crtc->state->active,
13027 "[ENCODER:%i] active %i with crtc active %i\n",
13028 encoder->base.base.id, active, crtc->state->active);
13029
13030 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13031 "Encoder connected to wrong pipe %c\n",
13032 pipe_name(pipe));
13033
13034 if (active)
13035 encoder->get_config(encoder, pipe_config);
13036 }
13037
13038 if (!crtc->state->active)
13039 continue;
13040
13041 sw_config = to_intel_crtc_state(crtc->state);
13042 if (!intel_pipe_config_compare(dev, sw_config,
13043 pipe_config, false)) {
13044 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13045 intel_dump_pipe_config(intel_crtc, pipe_config,
13046 "[hw state]");
13047 intel_dump_pipe_config(intel_crtc, sw_config,
13048 "[sw state]");
13049 }
13050 }
13051 }
13052
13053 static void
13054 check_shared_dpll_state(struct drm_device *dev)
13055 {
13056 struct drm_i915_private *dev_priv = dev->dev_private;
13057 struct intel_crtc *crtc;
13058 struct intel_dpll_hw_state dpll_hw_state;
13059 int i;
13060
13061 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13062 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13063 int enabled_crtcs = 0, active_crtcs = 0;
13064 bool active;
13065
13066 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13067
13068 DRM_DEBUG_KMS("%s\n", pll->name);
13069
13070 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
13071
13072 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
13073 "more active pll users than references: %i vs %i\n",
13074 pll->active, hweight32(pll->config.crtc_mask));
13075 I915_STATE_WARN(pll->active && !pll->on,
13076 "pll in active use but not on in sw tracking\n");
13077 I915_STATE_WARN(pll->on && !pll->active,
13078 "pll in on but not on in use in sw tracking\n");
13079 I915_STATE_WARN(pll->on != active,
13080 "pll on state mismatch (expected %i, found %i)\n",
13081 pll->on, active);
13082
13083 for_each_intel_crtc(dev, crtc) {
13084 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
13085 enabled_crtcs++;
13086 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13087 active_crtcs++;
13088 }
13089 I915_STATE_WARN(pll->active != active_crtcs,
13090 "pll active crtcs mismatch (expected %i, found %i)\n",
13091 pll->active, active_crtcs);
13092 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
13093 "pll enabled crtcs mismatch (expected %i, found %i)\n",
13094 hweight32(pll->config.crtc_mask), enabled_crtcs);
13095
13096 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
13097 sizeof(dpll_hw_state)),
13098 "pll hw state mismatch\n");
13099 }
13100 }
13101
13102 static void
13103 intel_modeset_check_state(struct drm_device *dev,
13104 struct drm_atomic_state *old_state)
13105 {
13106 check_wm_state(dev);
13107 check_connector_state(dev, old_state);
13108 check_encoder_state(dev);
13109 check_crtc_state(dev, old_state);
13110 check_shared_dpll_state(dev);
13111 }
13112
13113 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
13114 int dotclock)
13115 {
13116 /*
13117 * FDI already provided one idea for the dotclock.
13118 * Yell if the encoder disagrees.
13119 */
13120 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
13121 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13122 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
13123 }
13124
13125 static void update_scanline_offset(struct intel_crtc *crtc)
13126 {
13127 struct drm_device *dev = crtc->base.dev;
13128
13129 /*
13130 * The scanline counter increments at the leading edge of hsync.
13131 *
13132 * On most platforms it starts counting from vtotal-1 on the
13133 * first active line. That means the scanline counter value is
13134 * always one less than what we would expect. Ie. just after
13135 * start of vblank, which also occurs at start of hsync (on the
13136 * last active line), the scanline counter will read vblank_start-1.
13137 *
13138 * On gen2 the scanline counter starts counting from 1 instead
13139 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13140 * to keep the value positive), instead of adding one.
13141 *
13142 * On HSW+ the behaviour of the scanline counter depends on the output
13143 * type. For DP ports it behaves like most other platforms, but on HDMI
13144 * there's an extra 1 line difference. So we need to add two instead of
13145 * one to the value.
13146 */
13147 if (IS_GEN2(dev)) {
13148 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13149 int vtotal;
13150
13151 vtotal = adjusted_mode->crtc_vtotal;
13152 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13153 vtotal /= 2;
13154
13155 crtc->scanline_offset = vtotal - 1;
13156 } else if (HAS_DDI(dev) &&
13157 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13158 crtc->scanline_offset = 2;
13159 } else
13160 crtc->scanline_offset = 1;
13161 }
13162
13163 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13164 {
13165 struct drm_device *dev = state->dev;
13166 struct drm_i915_private *dev_priv = to_i915(dev);
13167 struct intel_shared_dpll_config *shared_dpll = NULL;
13168 struct drm_crtc *crtc;
13169 struct drm_crtc_state *crtc_state;
13170 int i;
13171
13172 if (!dev_priv->display.crtc_compute_clock)
13173 return;
13174
13175 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13177 int old_dpll = to_intel_crtc_state(crtc->state)->shared_dpll;
13178
13179 if (!needs_modeset(crtc_state))
13180 continue;
13181
13182 to_intel_crtc_state(crtc_state)->shared_dpll = DPLL_ID_PRIVATE;
13183
13184 if (old_dpll == DPLL_ID_PRIVATE)
13185 continue;
13186
13187 if (!shared_dpll)
13188 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13189
13190 shared_dpll[old_dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13191 }
13192 }
13193
13194 /*
13195 * This implements the workaround described in the "notes" section of the mode
13196 * set sequence documentation. When going from no pipes or single pipe to
13197 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13198 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13199 */
13200 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13201 {
13202 struct drm_crtc_state *crtc_state;
13203 struct intel_crtc *intel_crtc;
13204 struct drm_crtc *crtc;
13205 struct intel_crtc_state *first_crtc_state = NULL;
13206 struct intel_crtc_state *other_crtc_state = NULL;
13207 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13208 int i;
13209
13210 /* look at all crtc's that are going to be enabled in during modeset */
13211 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13212 intel_crtc = to_intel_crtc(crtc);
13213
13214 if (!crtc_state->active || !needs_modeset(crtc_state))
13215 continue;
13216
13217 if (first_crtc_state) {
13218 other_crtc_state = to_intel_crtc_state(crtc_state);
13219 break;
13220 } else {
13221 first_crtc_state = to_intel_crtc_state(crtc_state);
13222 first_pipe = intel_crtc->pipe;
13223 }
13224 }
13225
13226 /* No workaround needed? */
13227 if (!first_crtc_state)
13228 return 0;
13229
13230 /* w/a possibly needed, check how many crtc's are already enabled. */
13231 for_each_intel_crtc(state->dev, intel_crtc) {
13232 struct intel_crtc_state *pipe_config;
13233
13234 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13235 if (IS_ERR(pipe_config))
13236 return PTR_ERR(pipe_config);
13237
13238 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13239
13240 if (!pipe_config->base.active ||
13241 needs_modeset(&pipe_config->base))
13242 continue;
13243
13244 /* 2 or more enabled crtcs means no need for w/a */
13245 if (enabled_pipe != INVALID_PIPE)
13246 return 0;
13247
13248 enabled_pipe = intel_crtc->pipe;
13249 }
13250
13251 if (enabled_pipe != INVALID_PIPE)
13252 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13253 else if (other_crtc_state)
13254 other_crtc_state->hsw_workaround_pipe = first_pipe;
13255
13256 return 0;
13257 }
13258
13259 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13260 {
13261 struct drm_crtc *crtc;
13262 struct drm_crtc_state *crtc_state;
13263 int ret = 0;
13264
13265 /* add all active pipes to the state */
13266 for_each_crtc(state->dev, crtc) {
13267 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13268 if (IS_ERR(crtc_state))
13269 return PTR_ERR(crtc_state);
13270
13271 if (!crtc_state->active || needs_modeset(crtc_state))
13272 continue;
13273
13274 crtc_state->mode_changed = true;
13275
13276 ret = drm_atomic_add_affected_connectors(state, crtc);
13277 if (ret)
13278 break;
13279
13280 ret = drm_atomic_add_affected_planes(state, crtc);
13281 if (ret)
13282 break;
13283 }
13284
13285 return ret;
13286 }
13287
13288 static int intel_modeset_checks(struct drm_atomic_state *state)
13289 {
13290 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13291 struct drm_i915_private *dev_priv = state->dev->dev_private;
13292 struct drm_crtc *crtc;
13293 struct drm_crtc_state *crtc_state;
13294 int ret = 0, i;
13295
13296 if (!check_digital_port_conflicts(state)) {
13297 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13298 return -EINVAL;
13299 }
13300
13301 intel_state->modeset = true;
13302 intel_state->active_crtcs = dev_priv->active_crtcs;
13303
13304 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13305 if (crtc_state->active)
13306 intel_state->active_crtcs |= 1 << i;
13307 else
13308 intel_state->active_crtcs &= ~(1 << i);
13309 }
13310
13311 /*
13312 * See if the config requires any additional preparation, e.g.
13313 * to adjust global state with pipes off. We need to do this
13314 * here so we can get the modeset_pipe updated config for the new
13315 * mode set on this crtc. For other crtcs we need to use the
13316 * adjusted_mode bits in the crtc directly.
13317 */
13318 if (dev_priv->display.modeset_calc_cdclk) {
13319 ret = dev_priv->display.modeset_calc_cdclk(state);
13320
13321 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13322 ret = intel_modeset_all_pipes(state);
13323
13324 if (ret < 0)
13325 return ret;
13326
13327 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13328 intel_state->cdclk, intel_state->dev_cdclk);
13329 } else
13330 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13331
13332 intel_modeset_clear_plls(state);
13333
13334 if (IS_HASWELL(dev_priv))
13335 return haswell_mode_set_planes_workaround(state);
13336
13337 return 0;
13338 }
13339
13340 /*
13341 * Handle calculation of various watermark data at the end of the atomic check
13342 * phase. The code here should be run after the per-crtc and per-plane 'check'
13343 * handlers to ensure that all derived state has been updated.
13344 */
13345 static void calc_watermark_data(struct drm_atomic_state *state)
13346 {
13347 struct drm_device *dev = state->dev;
13348 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13349 struct drm_crtc *crtc;
13350 struct drm_crtc_state *cstate;
13351 struct drm_plane *plane;
13352 struct drm_plane_state *pstate;
13353
13354 /*
13355 * Calculate watermark configuration details now that derived
13356 * plane/crtc state is all properly updated.
13357 */
13358 drm_for_each_crtc(crtc, dev) {
13359 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13360 crtc->state;
13361
13362 if (cstate->active)
13363 intel_state->wm_config.num_pipes_active++;
13364 }
13365 drm_for_each_legacy_plane(plane, dev) {
13366 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13367 plane->state;
13368
13369 if (!to_intel_plane_state(pstate)->visible)
13370 continue;
13371
13372 intel_state->wm_config.sprites_enabled = true;
13373 if (pstate->crtc_w != pstate->src_w >> 16 ||
13374 pstate->crtc_h != pstate->src_h >> 16)
13375 intel_state->wm_config.sprites_scaled = true;
13376 }
13377 }
13378
13379 /**
13380 * intel_atomic_check - validate state object
13381 * @dev: drm device
13382 * @state: state to validate
13383 */
13384 static int intel_atomic_check(struct drm_device *dev,
13385 struct drm_atomic_state *state)
13386 {
13387 struct drm_i915_private *dev_priv = to_i915(dev);
13388 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13389 struct drm_crtc *crtc;
13390 struct drm_crtc_state *crtc_state;
13391 int ret, i;
13392 bool any_ms = false;
13393
13394 ret = drm_atomic_helper_check_modeset(dev, state);
13395 if (ret)
13396 return ret;
13397
13398 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13399 struct intel_crtc_state *pipe_config =
13400 to_intel_crtc_state(crtc_state);
13401
13402 memset(&to_intel_crtc(crtc)->atomic, 0,
13403 sizeof(struct intel_crtc_atomic_commit));
13404
13405 /* Catch I915_MODE_FLAG_INHERITED */
13406 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13407 crtc_state->mode_changed = true;
13408
13409 if (!crtc_state->enable) {
13410 if (needs_modeset(crtc_state))
13411 any_ms = true;
13412 continue;
13413 }
13414
13415 if (!needs_modeset(crtc_state))
13416 continue;
13417
13418 /* FIXME: For only active_changed we shouldn't need to do any
13419 * state recomputation at all. */
13420
13421 ret = drm_atomic_add_affected_connectors(state, crtc);
13422 if (ret)
13423 return ret;
13424
13425 ret = intel_modeset_pipe_config(crtc, pipe_config);
13426 if (ret)
13427 return ret;
13428
13429 if (i915.fastboot &&
13430 intel_pipe_config_compare(dev,
13431 to_intel_crtc_state(crtc->state),
13432 pipe_config, true)) {
13433 crtc_state->mode_changed = false;
13434 to_intel_crtc_state(crtc_state)->update_pipe = true;
13435 }
13436
13437 if (needs_modeset(crtc_state)) {
13438 any_ms = true;
13439
13440 ret = drm_atomic_add_affected_planes(state, crtc);
13441 if (ret)
13442 return ret;
13443 }
13444
13445 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13446 needs_modeset(crtc_state) ?
13447 "[modeset]" : "[fastset]");
13448 }
13449
13450 if (any_ms) {
13451 ret = intel_modeset_checks(state);
13452
13453 if (ret)
13454 return ret;
13455 } else
13456 intel_state->cdclk = dev_priv->cdclk_freq;
13457
13458 ret = drm_atomic_helper_check_planes(dev, state);
13459 if (ret)
13460 return ret;
13461
13462 intel_fbc_choose_crtc(dev_priv, state);
13463 calc_watermark_data(state);
13464
13465 return 0;
13466 }
13467
13468 static int intel_atomic_prepare_commit(struct drm_device *dev,
13469 struct drm_atomic_state *state,
13470 bool async)
13471 {
13472 struct drm_i915_private *dev_priv = dev->dev_private;
13473 struct drm_plane_state *plane_state;
13474 struct drm_crtc_state *crtc_state;
13475 struct drm_plane *plane;
13476 struct drm_crtc *crtc;
13477 int i, ret;
13478
13479 if (async) {
13480 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13481 return -EINVAL;
13482 }
13483
13484 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13485 ret = intel_crtc_wait_for_pending_flips(crtc);
13486 if (ret)
13487 return ret;
13488
13489 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13490 flush_workqueue(dev_priv->wq);
13491 }
13492
13493 ret = mutex_lock_interruptible(&dev->struct_mutex);
13494 if (ret)
13495 return ret;
13496
13497 ret = drm_atomic_helper_prepare_planes(dev, state);
13498 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13499 u32 reset_counter;
13500
13501 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13502 mutex_unlock(&dev->struct_mutex);
13503
13504 for_each_plane_in_state(state, plane, plane_state, i) {
13505 struct intel_plane_state *intel_plane_state =
13506 to_intel_plane_state(plane_state);
13507
13508 if (!intel_plane_state->wait_req)
13509 continue;
13510
13511 ret = __i915_wait_request(intel_plane_state->wait_req,
13512 reset_counter, true,
13513 NULL, NULL);
13514
13515 /* Swallow -EIO errors to allow updates during hw lockup. */
13516 if (ret == -EIO)
13517 ret = 0;
13518
13519 if (ret)
13520 break;
13521 }
13522
13523 if (!ret)
13524 return 0;
13525
13526 mutex_lock(&dev->struct_mutex);
13527 drm_atomic_helper_cleanup_planes(dev, state);
13528 }
13529
13530 mutex_unlock(&dev->struct_mutex);
13531 return ret;
13532 }
13533
13534 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13535 struct drm_i915_private *dev_priv,
13536 unsigned crtc_mask)
13537 {
13538 unsigned last_vblank_count[I915_MAX_PIPES];
13539 enum pipe pipe;
13540 int ret;
13541
13542 if (!crtc_mask)
13543 return;
13544
13545 for_each_pipe(dev_priv, pipe) {
13546 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13547
13548 if (!((1 << pipe) & crtc_mask))
13549 continue;
13550
13551 ret = drm_crtc_vblank_get(crtc);
13552 if (WARN_ON(ret != 0)) {
13553 crtc_mask &= ~(1 << pipe);
13554 continue;
13555 }
13556
13557 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13558 }
13559
13560 for_each_pipe(dev_priv, pipe) {
13561 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13562 long lret;
13563
13564 if (!((1 << pipe) & crtc_mask))
13565 continue;
13566
13567 lret = wait_event_timeout(dev->vblank[pipe].queue,
13568 last_vblank_count[pipe] !=
13569 drm_crtc_vblank_count(crtc),
13570 msecs_to_jiffies(50));
13571
13572 WARN_ON(!lret);
13573
13574 drm_crtc_vblank_put(crtc);
13575 }
13576 }
13577
13578 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13579 {
13580 /* fb updated, need to unpin old fb */
13581 if (crtc_state->fb_changed)
13582 return true;
13583
13584 /* wm changes, need vblank before final wm's */
13585 if (crtc_state->wm_changed)
13586 return true;
13587
13588 /*
13589 * cxsr is re-enabled after vblank.
13590 * This is already handled by crtc_state->wm_changed,
13591 * but added for clarity.
13592 */
13593 if (crtc_state->disable_cxsr)
13594 return true;
13595
13596 return false;
13597 }
13598
13599 /**
13600 * intel_atomic_commit - commit validated state object
13601 * @dev: DRM device
13602 * @state: the top-level driver state object
13603 * @async: asynchronous commit
13604 *
13605 * This function commits a top-level state object that has been validated
13606 * with drm_atomic_helper_check().
13607 *
13608 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13609 * we can only handle plane-related operations and do not yet support
13610 * asynchronous commit.
13611 *
13612 * RETURNS
13613 * Zero for success or -errno.
13614 */
13615 static int intel_atomic_commit(struct drm_device *dev,
13616 struct drm_atomic_state *state,
13617 bool async)
13618 {
13619 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13620 struct drm_i915_private *dev_priv = dev->dev_private;
13621 struct drm_crtc_state *crtc_state;
13622 struct drm_crtc *crtc;
13623 struct intel_crtc_state *intel_cstate;
13624 int ret = 0, i;
13625 bool hw_check = intel_state->modeset;
13626 unsigned long put_domains[I915_MAX_PIPES] = {};
13627 unsigned crtc_vblank_mask = 0;
13628
13629 ret = intel_atomic_prepare_commit(dev, state, async);
13630 if (ret) {
13631 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13632 return ret;
13633 }
13634
13635 drm_atomic_helper_swap_state(dev, state);
13636 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13637
13638 if (intel_state->modeset) {
13639 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13640 sizeof(intel_state->min_pixclk));
13641 dev_priv->active_crtcs = intel_state->active_crtcs;
13642 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13643
13644 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13645 }
13646
13647 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13649
13650 if (needs_modeset(crtc->state) ||
13651 to_intel_crtc_state(crtc->state)->update_pipe) {
13652 hw_check = true;
13653
13654 put_domains[to_intel_crtc(crtc)->pipe] =
13655 modeset_get_crtc_power_domains(crtc,
13656 to_intel_crtc_state(crtc->state));
13657 }
13658
13659 if (!needs_modeset(crtc->state))
13660 continue;
13661
13662 intel_pre_plane_update(to_intel_crtc_state(crtc_state));
13663
13664 if (crtc_state->active) {
13665 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13666 dev_priv->display.crtc_disable(crtc);
13667 intel_crtc->active = false;
13668 intel_fbc_disable(intel_crtc);
13669 intel_disable_shared_dpll(intel_crtc);
13670
13671 /*
13672 * Underruns don't always raise
13673 * interrupts, so check manually.
13674 */
13675 intel_check_cpu_fifo_underruns(dev_priv);
13676 intel_check_pch_fifo_underruns(dev_priv);
13677
13678 if (!crtc->state->active)
13679 intel_update_watermarks(crtc);
13680 }
13681 }
13682
13683 /* Only after disabling all output pipelines that will be changed can we
13684 * update the the output configuration. */
13685 intel_modeset_update_crtc_state(state);
13686
13687 if (intel_state->modeset) {
13688 intel_shared_dpll_commit(state);
13689
13690 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13691
13692 if (dev_priv->display.modeset_commit_cdclk &&
13693 intel_state->dev_cdclk != dev_priv->cdclk_freq)
13694 dev_priv->display.modeset_commit_cdclk(state);
13695 }
13696
13697 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13698 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13700 bool modeset = needs_modeset(crtc->state);
13701 struct intel_crtc_state *pipe_config =
13702 to_intel_crtc_state(crtc->state);
13703 bool update_pipe = !modeset && pipe_config->update_pipe;
13704
13705 if (modeset && crtc->state->active) {
13706 update_scanline_offset(to_intel_crtc(crtc));
13707 dev_priv->display.crtc_enable(crtc);
13708 }
13709
13710 if (!modeset)
13711 intel_pre_plane_update(to_intel_crtc_state(crtc_state));
13712
13713 if (crtc->state->active && intel_crtc->atomic.update_fbc)
13714 intel_fbc_enable(intel_crtc);
13715
13716 if (crtc->state->active &&
13717 (crtc->state->planes_changed || update_pipe))
13718 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13719
13720 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13721 crtc_vblank_mask |= 1 << i;
13722 }
13723
13724 /* FIXME: add subpixel order */
13725
13726 if (!state->legacy_cursor_update)
13727 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13728
13729 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13730 intel_post_plane_update(to_intel_crtc(crtc));
13731
13732 if (put_domains[i])
13733 modeset_put_power_domains(dev_priv, put_domains[i]);
13734 }
13735
13736 if (intel_state->modeset)
13737 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13738
13739 /*
13740 * Now that the vblank has passed, we can go ahead and program the
13741 * optimal watermarks on platforms that need two-step watermark
13742 * programming.
13743 *
13744 * TODO: Move this (and other cleanup) to an async worker eventually.
13745 */
13746 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13747 intel_cstate = to_intel_crtc_state(crtc->state);
13748
13749 if (dev_priv->display.optimize_watermarks)
13750 dev_priv->display.optimize_watermarks(intel_cstate);
13751 }
13752
13753 mutex_lock(&dev->struct_mutex);
13754 drm_atomic_helper_cleanup_planes(dev, state);
13755 mutex_unlock(&dev->struct_mutex);
13756
13757 if (hw_check)
13758 intel_modeset_check_state(dev, state);
13759
13760 drm_atomic_state_free(state);
13761
13762 /* As one of the primary mmio accessors, KMS has a high likelihood
13763 * of triggering bugs in unclaimed access. After we finish
13764 * modesetting, see if an error has been flagged, and if so
13765 * enable debugging for the next modeset - and hope we catch
13766 * the culprit.
13767 *
13768 * XXX note that we assume display power is on at this point.
13769 * This might hold true now but we need to add pm helper to check
13770 * unclaimed only when the hardware is on, as atomic commits
13771 * can happen also when the device is completely off.
13772 */
13773 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13774
13775 return 0;
13776 }
13777
13778 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13779 {
13780 struct drm_device *dev = crtc->dev;
13781 struct drm_atomic_state *state;
13782 struct drm_crtc_state *crtc_state;
13783 int ret;
13784
13785 state = drm_atomic_state_alloc(dev);
13786 if (!state) {
13787 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13788 crtc->base.id);
13789 return;
13790 }
13791
13792 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13793
13794 retry:
13795 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13796 ret = PTR_ERR_OR_ZERO(crtc_state);
13797 if (!ret) {
13798 if (!crtc_state->active)
13799 goto out;
13800
13801 crtc_state->mode_changed = true;
13802 ret = drm_atomic_commit(state);
13803 }
13804
13805 if (ret == -EDEADLK) {
13806 drm_atomic_state_clear(state);
13807 drm_modeset_backoff(state->acquire_ctx);
13808 goto retry;
13809 }
13810
13811 if (ret)
13812 out:
13813 drm_atomic_state_free(state);
13814 }
13815
13816 #undef for_each_intel_crtc_masked
13817
13818 static const struct drm_crtc_funcs intel_crtc_funcs = {
13819 .gamma_set = intel_crtc_gamma_set,
13820 .set_config = drm_atomic_helper_set_config,
13821 .destroy = intel_crtc_destroy,
13822 .page_flip = intel_crtc_page_flip,
13823 .atomic_duplicate_state = intel_crtc_duplicate_state,
13824 .atomic_destroy_state = intel_crtc_destroy_state,
13825 };
13826
13827 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13828 struct intel_shared_dpll *pll,
13829 struct intel_dpll_hw_state *hw_state)
13830 {
13831 uint32_t val;
13832
13833 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
13834 return false;
13835
13836 val = I915_READ(PCH_DPLL(pll->id));
13837 hw_state->dpll = val;
13838 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13839 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13840
13841 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
13842
13843 return val & DPLL_VCO_ENABLE;
13844 }
13845
13846 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13847 struct intel_shared_dpll *pll)
13848 {
13849 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13850 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13851 }
13852
13853 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13854 struct intel_shared_dpll *pll)
13855 {
13856 /* PCH refclock must be enabled first */
13857 ibx_assert_pch_refclk_enabled(dev_priv);
13858
13859 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13860
13861 /* Wait for the clocks to stabilize. */
13862 POSTING_READ(PCH_DPLL(pll->id));
13863 udelay(150);
13864
13865 /* The pixel multiplier can only be updated once the
13866 * DPLL is enabled and the clocks are stable.
13867 *
13868 * So write it again.
13869 */
13870 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13871 POSTING_READ(PCH_DPLL(pll->id));
13872 udelay(200);
13873 }
13874
13875 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13876 struct intel_shared_dpll *pll)
13877 {
13878 struct drm_device *dev = dev_priv->dev;
13879 struct intel_crtc *crtc;
13880
13881 /* Make sure no transcoder isn't still depending on us. */
13882 for_each_intel_crtc(dev, crtc) {
13883 if (intel_crtc_to_shared_dpll(crtc) == pll)
13884 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13885 }
13886
13887 I915_WRITE(PCH_DPLL(pll->id), 0);
13888 POSTING_READ(PCH_DPLL(pll->id));
13889 udelay(200);
13890 }
13891
13892 static char *ibx_pch_dpll_names[] = {
13893 "PCH DPLL A",
13894 "PCH DPLL B",
13895 };
13896
13897 static void ibx_pch_dpll_init(struct drm_device *dev)
13898 {
13899 struct drm_i915_private *dev_priv = dev->dev_private;
13900 int i;
13901
13902 dev_priv->num_shared_dpll = 2;
13903
13904 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13905 dev_priv->shared_dplls[i].id = i;
13906 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13907 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13908 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13909 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13910 dev_priv->shared_dplls[i].get_hw_state =
13911 ibx_pch_dpll_get_hw_state;
13912 }
13913 }
13914
13915 static void intel_shared_dpll_init(struct drm_device *dev)
13916 {
13917 struct drm_i915_private *dev_priv = dev->dev_private;
13918
13919 if (HAS_DDI(dev))
13920 intel_ddi_pll_init(dev);
13921 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13922 ibx_pch_dpll_init(dev);
13923 else
13924 dev_priv->num_shared_dpll = 0;
13925
13926 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13927 }
13928
13929 /**
13930 * intel_prepare_plane_fb - Prepare fb for usage on plane
13931 * @plane: drm plane to prepare for
13932 * @fb: framebuffer to prepare for presentation
13933 *
13934 * Prepares a framebuffer for usage on a display plane. Generally this
13935 * involves pinning the underlying object and updating the frontbuffer tracking
13936 * bits. Some older platforms need special physical address handling for
13937 * cursor planes.
13938 *
13939 * Must be called with struct_mutex held.
13940 *
13941 * Returns 0 on success, negative error code on failure.
13942 */
13943 int
13944 intel_prepare_plane_fb(struct drm_plane *plane,
13945 const struct drm_plane_state *new_state)
13946 {
13947 struct drm_device *dev = plane->dev;
13948 struct drm_framebuffer *fb = new_state->fb;
13949 struct intel_plane *intel_plane = to_intel_plane(plane);
13950 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13951 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13952 int ret = 0;
13953
13954 if (!obj && !old_obj)
13955 return 0;
13956
13957 if (old_obj) {
13958 struct drm_crtc_state *crtc_state =
13959 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13960
13961 /* Big Hammer, we also need to ensure that any pending
13962 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13963 * current scanout is retired before unpinning the old
13964 * framebuffer. Note that we rely on userspace rendering
13965 * into the buffer attached to the pipe they are waiting
13966 * on. If not, userspace generates a GPU hang with IPEHR
13967 * point to the MI_WAIT_FOR_EVENT.
13968 *
13969 * This should only fail upon a hung GPU, in which case we
13970 * can safely continue.
13971 */
13972 if (needs_modeset(crtc_state))
13973 ret = i915_gem_object_wait_rendering(old_obj, true);
13974
13975 /* Swallow -EIO errors to allow updates during hw lockup. */
13976 if (ret && ret != -EIO)
13977 return ret;
13978 }
13979
13980 /* For framebuffer backed by dmabuf, wait for fence */
13981 if (obj && obj->base.dma_buf) {
13982 long lret;
13983
13984 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13985 false, true,
13986 MAX_SCHEDULE_TIMEOUT);
13987 if (lret == -ERESTARTSYS)
13988 return lret;
13989
13990 WARN(lret < 0, "waiting returns %li\n", lret);
13991 }
13992
13993 if (!obj) {
13994 ret = 0;
13995 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13996 INTEL_INFO(dev)->cursor_needs_physical) {
13997 int align = IS_I830(dev) ? 16 * 1024 : 256;
13998 ret = i915_gem_object_attach_phys(obj, align);
13999 if (ret)
14000 DRM_DEBUG_KMS("failed to attach phys object\n");
14001 } else {
14002 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14003 }
14004
14005 if (ret == 0) {
14006 if (obj) {
14007 struct intel_plane_state *plane_state =
14008 to_intel_plane_state(new_state);
14009
14010 i915_gem_request_assign(&plane_state->wait_req,
14011 obj->last_write_req);
14012 }
14013
14014 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
14015 }
14016
14017 return ret;
14018 }
14019
14020 /**
14021 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14022 * @plane: drm plane to clean up for
14023 * @fb: old framebuffer that was on plane
14024 *
14025 * Cleans up a framebuffer that has just been removed from a plane.
14026 *
14027 * Must be called with struct_mutex held.
14028 */
14029 void
14030 intel_cleanup_plane_fb(struct drm_plane *plane,
14031 const struct drm_plane_state *old_state)
14032 {
14033 struct drm_device *dev = plane->dev;
14034 struct intel_plane *intel_plane = to_intel_plane(plane);
14035 struct intel_plane_state *old_intel_state;
14036 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14037 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14038
14039 old_intel_state = to_intel_plane_state(old_state);
14040
14041 if (!obj && !old_obj)
14042 return;
14043
14044 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14045 !INTEL_INFO(dev)->cursor_needs_physical))
14046 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14047
14048 /* prepare_fb aborted? */
14049 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
14050 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
14051 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
14052
14053 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14054 }
14055
14056 int
14057 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14058 {
14059 int max_scale;
14060 struct drm_device *dev;
14061 struct drm_i915_private *dev_priv;
14062 int crtc_clock, cdclk;
14063
14064 if (!intel_crtc || !crtc_state->base.enable)
14065 return DRM_PLANE_HELPER_NO_SCALING;
14066
14067 dev = intel_crtc->base.dev;
14068 dev_priv = dev->dev_private;
14069 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14070 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14071
14072 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14073 return DRM_PLANE_HELPER_NO_SCALING;
14074
14075 /*
14076 * skl max scale is lower of:
14077 * close to 3 but not 3, -1 is for that purpose
14078 * or
14079 * cdclk/crtc_clock
14080 */
14081 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14082
14083 return max_scale;
14084 }
14085
14086 static int
14087 intel_check_primary_plane(struct drm_plane *plane,
14088 struct intel_crtc_state *crtc_state,
14089 struct intel_plane_state *state)
14090 {
14091 struct drm_crtc *crtc = state->base.crtc;
14092 struct drm_framebuffer *fb = state->base.fb;
14093 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14094 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14095 bool can_position = false;
14096
14097 if (INTEL_INFO(plane->dev)->gen >= 9) {
14098 /* use scaler when colorkey is not required */
14099 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14100 min_scale = 1;
14101 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14102 }
14103 can_position = true;
14104 }
14105
14106 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14107 &state->dst, &state->clip,
14108 min_scale, max_scale,
14109 can_position, true,
14110 &state->visible);
14111 }
14112
14113 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14114 struct drm_crtc_state *old_crtc_state)
14115 {
14116 struct drm_device *dev = crtc->dev;
14117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14118 struct intel_crtc_state *old_intel_state =
14119 to_intel_crtc_state(old_crtc_state);
14120 bool modeset = needs_modeset(crtc->state);
14121
14122 /* Perform vblank evasion around commit operation */
14123 intel_pipe_update_start(intel_crtc);
14124
14125 if (modeset)
14126 return;
14127
14128 if (to_intel_crtc_state(crtc->state)->update_pipe)
14129 intel_update_pipe_config(intel_crtc, old_intel_state);
14130 else if (INTEL_INFO(dev)->gen >= 9)
14131 skl_detach_scalers(intel_crtc);
14132 }
14133
14134 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14135 struct drm_crtc_state *old_crtc_state)
14136 {
14137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14138
14139 intel_pipe_update_end(intel_crtc);
14140 }
14141
14142 /**
14143 * intel_plane_destroy - destroy a plane
14144 * @plane: plane to destroy
14145 *
14146 * Common destruction function for all types of planes (primary, cursor,
14147 * sprite).
14148 */
14149 void intel_plane_destroy(struct drm_plane *plane)
14150 {
14151 struct intel_plane *intel_plane = to_intel_plane(plane);
14152 drm_plane_cleanup(plane);
14153 kfree(intel_plane);
14154 }
14155
14156 const struct drm_plane_funcs intel_plane_funcs = {
14157 .update_plane = drm_atomic_helper_update_plane,
14158 .disable_plane = drm_atomic_helper_disable_plane,
14159 .destroy = intel_plane_destroy,
14160 .set_property = drm_atomic_helper_plane_set_property,
14161 .atomic_get_property = intel_plane_atomic_get_property,
14162 .atomic_set_property = intel_plane_atomic_set_property,
14163 .atomic_duplicate_state = intel_plane_duplicate_state,
14164 .atomic_destroy_state = intel_plane_destroy_state,
14165
14166 };
14167
14168 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14169 int pipe)
14170 {
14171 struct intel_plane *primary;
14172 struct intel_plane_state *state;
14173 const uint32_t *intel_primary_formats;
14174 unsigned int num_formats;
14175
14176 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14177 if (primary == NULL)
14178 return NULL;
14179
14180 state = intel_create_plane_state(&primary->base);
14181 if (!state) {
14182 kfree(primary);
14183 return NULL;
14184 }
14185 primary->base.state = &state->base;
14186
14187 primary->can_scale = false;
14188 primary->max_downscale = 1;
14189 if (INTEL_INFO(dev)->gen >= 9) {
14190 primary->can_scale = true;
14191 state->scaler_id = -1;
14192 }
14193 primary->pipe = pipe;
14194 primary->plane = pipe;
14195 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14196 primary->check_plane = intel_check_primary_plane;
14197 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14198 primary->plane = !pipe;
14199
14200 if (INTEL_INFO(dev)->gen >= 9) {
14201 intel_primary_formats = skl_primary_formats;
14202 num_formats = ARRAY_SIZE(skl_primary_formats);
14203
14204 primary->update_plane = skylake_update_primary_plane;
14205 primary->disable_plane = skylake_disable_primary_plane;
14206 } else if (HAS_PCH_SPLIT(dev)) {
14207 intel_primary_formats = i965_primary_formats;
14208 num_formats = ARRAY_SIZE(i965_primary_formats);
14209
14210 primary->update_plane = ironlake_update_primary_plane;
14211 primary->disable_plane = i9xx_disable_primary_plane;
14212 } else if (INTEL_INFO(dev)->gen >= 4) {
14213 intel_primary_formats = i965_primary_formats;
14214 num_formats = ARRAY_SIZE(i965_primary_formats);
14215
14216 primary->update_plane = i9xx_update_primary_plane;
14217 primary->disable_plane = i9xx_disable_primary_plane;
14218 } else {
14219 intel_primary_formats = i8xx_primary_formats;
14220 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14221
14222 primary->update_plane = i9xx_update_primary_plane;
14223 primary->disable_plane = i9xx_disable_primary_plane;
14224 }
14225
14226 drm_universal_plane_init(dev, &primary->base, 0,
14227 &intel_plane_funcs,
14228 intel_primary_formats, num_formats,
14229 DRM_PLANE_TYPE_PRIMARY, NULL);
14230
14231 if (INTEL_INFO(dev)->gen >= 4)
14232 intel_create_rotation_property(dev, primary);
14233
14234 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14235
14236 return &primary->base;
14237 }
14238
14239 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14240 {
14241 if (!dev->mode_config.rotation_property) {
14242 unsigned long flags = BIT(DRM_ROTATE_0) |
14243 BIT(DRM_ROTATE_180);
14244
14245 if (INTEL_INFO(dev)->gen >= 9)
14246 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14247
14248 dev->mode_config.rotation_property =
14249 drm_mode_create_rotation_property(dev, flags);
14250 }
14251 if (dev->mode_config.rotation_property)
14252 drm_object_attach_property(&plane->base.base,
14253 dev->mode_config.rotation_property,
14254 plane->base.state->rotation);
14255 }
14256
14257 static int
14258 intel_check_cursor_plane(struct drm_plane *plane,
14259 struct intel_crtc_state *crtc_state,
14260 struct intel_plane_state *state)
14261 {
14262 struct drm_crtc *crtc = crtc_state->base.crtc;
14263 struct drm_framebuffer *fb = state->base.fb;
14264 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14265 enum pipe pipe = to_intel_plane(plane)->pipe;
14266 unsigned stride;
14267 int ret;
14268
14269 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14270 &state->dst, &state->clip,
14271 DRM_PLANE_HELPER_NO_SCALING,
14272 DRM_PLANE_HELPER_NO_SCALING,
14273 true, true, &state->visible);
14274 if (ret)
14275 return ret;
14276
14277 /* if we want to turn off the cursor ignore width and height */
14278 if (!obj)
14279 return 0;
14280
14281 /* Check for which cursor types we support */
14282 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14283 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14284 state->base.crtc_w, state->base.crtc_h);
14285 return -EINVAL;
14286 }
14287
14288 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14289 if (obj->base.size < stride * state->base.crtc_h) {
14290 DRM_DEBUG_KMS("buffer is too small\n");
14291 return -ENOMEM;
14292 }
14293
14294 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14295 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14296 return -EINVAL;
14297 }
14298
14299 /*
14300 * There's something wrong with the cursor on CHV pipe C.
14301 * If it straddles the left edge of the screen then
14302 * moving it away from the edge or disabling it often
14303 * results in a pipe underrun, and often that can lead to
14304 * dead pipe (constant underrun reported, and it scans
14305 * out just a solid color). To recover from that, the
14306 * display power well must be turned off and on again.
14307 * Refuse the put the cursor into that compromised position.
14308 */
14309 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14310 state->visible && state->base.crtc_x < 0) {
14311 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14312 return -EINVAL;
14313 }
14314
14315 return 0;
14316 }
14317
14318 static void
14319 intel_disable_cursor_plane(struct drm_plane *plane,
14320 struct drm_crtc *crtc)
14321 {
14322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14323
14324 intel_crtc->cursor_addr = 0;
14325 intel_crtc_update_cursor(crtc, NULL);
14326 }
14327
14328 static void
14329 intel_update_cursor_plane(struct drm_plane *plane,
14330 const struct intel_crtc_state *crtc_state,
14331 const struct intel_plane_state *state)
14332 {
14333 struct drm_crtc *crtc = crtc_state->base.crtc;
14334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14335 struct drm_device *dev = plane->dev;
14336 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14337 uint32_t addr;
14338
14339 if (!obj)
14340 addr = 0;
14341 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14342 addr = i915_gem_obj_ggtt_offset(obj);
14343 else
14344 addr = obj->phys_handle->busaddr;
14345
14346 intel_crtc->cursor_addr = addr;
14347 intel_crtc_update_cursor(crtc, state);
14348 }
14349
14350 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14351 int pipe)
14352 {
14353 struct intel_plane *cursor;
14354 struct intel_plane_state *state;
14355
14356 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14357 if (cursor == NULL)
14358 return NULL;
14359
14360 state = intel_create_plane_state(&cursor->base);
14361 if (!state) {
14362 kfree(cursor);
14363 return NULL;
14364 }
14365 cursor->base.state = &state->base;
14366
14367 cursor->can_scale = false;
14368 cursor->max_downscale = 1;
14369 cursor->pipe = pipe;
14370 cursor->plane = pipe;
14371 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14372 cursor->check_plane = intel_check_cursor_plane;
14373 cursor->update_plane = intel_update_cursor_plane;
14374 cursor->disable_plane = intel_disable_cursor_plane;
14375
14376 drm_universal_plane_init(dev, &cursor->base, 0,
14377 &intel_plane_funcs,
14378 intel_cursor_formats,
14379 ARRAY_SIZE(intel_cursor_formats),
14380 DRM_PLANE_TYPE_CURSOR, NULL);
14381
14382 if (INTEL_INFO(dev)->gen >= 4) {
14383 if (!dev->mode_config.rotation_property)
14384 dev->mode_config.rotation_property =
14385 drm_mode_create_rotation_property(dev,
14386 BIT(DRM_ROTATE_0) |
14387 BIT(DRM_ROTATE_180));
14388 if (dev->mode_config.rotation_property)
14389 drm_object_attach_property(&cursor->base.base,
14390 dev->mode_config.rotation_property,
14391 state->base.rotation);
14392 }
14393
14394 if (INTEL_INFO(dev)->gen >=9)
14395 state->scaler_id = -1;
14396
14397 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14398
14399 return &cursor->base;
14400 }
14401
14402 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14403 struct intel_crtc_state *crtc_state)
14404 {
14405 int i;
14406 struct intel_scaler *intel_scaler;
14407 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14408
14409 for (i = 0; i < intel_crtc->num_scalers; i++) {
14410 intel_scaler = &scaler_state->scalers[i];
14411 intel_scaler->in_use = 0;
14412 intel_scaler->mode = PS_SCALER_MODE_DYN;
14413 }
14414
14415 scaler_state->scaler_id = -1;
14416 }
14417
14418 static void intel_crtc_init(struct drm_device *dev, int pipe)
14419 {
14420 struct drm_i915_private *dev_priv = dev->dev_private;
14421 struct intel_crtc *intel_crtc;
14422 struct intel_crtc_state *crtc_state = NULL;
14423 struct drm_plane *primary = NULL;
14424 struct drm_plane *cursor = NULL;
14425 int i, ret;
14426
14427 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14428 if (intel_crtc == NULL)
14429 return;
14430
14431 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14432 if (!crtc_state)
14433 goto fail;
14434 intel_crtc->config = crtc_state;
14435 intel_crtc->base.state = &crtc_state->base;
14436 crtc_state->base.crtc = &intel_crtc->base;
14437
14438 /* initialize shared scalers */
14439 if (INTEL_INFO(dev)->gen >= 9) {
14440 if (pipe == PIPE_C)
14441 intel_crtc->num_scalers = 1;
14442 else
14443 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14444
14445 skl_init_scalers(dev, intel_crtc, crtc_state);
14446 }
14447
14448 primary = intel_primary_plane_create(dev, pipe);
14449 if (!primary)
14450 goto fail;
14451
14452 cursor = intel_cursor_plane_create(dev, pipe);
14453 if (!cursor)
14454 goto fail;
14455
14456 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14457 cursor, &intel_crtc_funcs, NULL);
14458 if (ret)
14459 goto fail;
14460
14461 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14462 for (i = 0; i < 256; i++) {
14463 intel_crtc->lut_r[i] = i;
14464 intel_crtc->lut_g[i] = i;
14465 intel_crtc->lut_b[i] = i;
14466 }
14467
14468 /*
14469 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14470 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14471 */
14472 intel_crtc->pipe = pipe;
14473 intel_crtc->plane = pipe;
14474 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14475 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14476 intel_crtc->plane = !pipe;
14477 }
14478
14479 intel_crtc->cursor_base = ~0;
14480 intel_crtc->cursor_cntl = ~0;
14481 intel_crtc->cursor_size = ~0;
14482
14483 intel_crtc->wm.cxsr_allowed = true;
14484
14485 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14486 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14487 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14488 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14489
14490 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14491
14492 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14493 return;
14494
14495 fail:
14496 if (primary)
14497 drm_plane_cleanup(primary);
14498 if (cursor)
14499 drm_plane_cleanup(cursor);
14500 kfree(crtc_state);
14501 kfree(intel_crtc);
14502 }
14503
14504 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14505 {
14506 struct drm_encoder *encoder = connector->base.encoder;
14507 struct drm_device *dev = connector->base.dev;
14508
14509 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14510
14511 if (!encoder || WARN_ON(!encoder->crtc))
14512 return INVALID_PIPE;
14513
14514 return to_intel_crtc(encoder->crtc)->pipe;
14515 }
14516
14517 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14518 struct drm_file *file)
14519 {
14520 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14521 struct drm_crtc *drmmode_crtc;
14522 struct intel_crtc *crtc;
14523
14524 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14525
14526 if (!drmmode_crtc) {
14527 DRM_ERROR("no such CRTC id\n");
14528 return -ENOENT;
14529 }
14530
14531 crtc = to_intel_crtc(drmmode_crtc);
14532 pipe_from_crtc_id->pipe = crtc->pipe;
14533
14534 return 0;
14535 }
14536
14537 static int intel_encoder_clones(struct intel_encoder *encoder)
14538 {
14539 struct drm_device *dev = encoder->base.dev;
14540 struct intel_encoder *source_encoder;
14541 int index_mask = 0;
14542 int entry = 0;
14543
14544 for_each_intel_encoder(dev, source_encoder) {
14545 if (encoders_cloneable(encoder, source_encoder))
14546 index_mask |= (1 << entry);
14547
14548 entry++;
14549 }
14550
14551 return index_mask;
14552 }
14553
14554 static bool has_edp_a(struct drm_device *dev)
14555 {
14556 struct drm_i915_private *dev_priv = dev->dev_private;
14557
14558 if (!IS_MOBILE(dev))
14559 return false;
14560
14561 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14562 return false;
14563
14564 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14565 return false;
14566
14567 return true;
14568 }
14569
14570 static bool intel_crt_present(struct drm_device *dev)
14571 {
14572 struct drm_i915_private *dev_priv = dev->dev_private;
14573
14574 if (INTEL_INFO(dev)->gen >= 9)
14575 return false;
14576
14577 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14578 return false;
14579
14580 if (IS_CHERRYVIEW(dev))
14581 return false;
14582
14583 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14584 return false;
14585
14586 /* DDI E can't be used if DDI A requires 4 lanes */
14587 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14588 return false;
14589
14590 if (!dev_priv->vbt.int_crt_support)
14591 return false;
14592
14593 return true;
14594 }
14595
14596 static void intel_setup_outputs(struct drm_device *dev)
14597 {
14598 struct drm_i915_private *dev_priv = dev->dev_private;
14599 struct intel_encoder *encoder;
14600 bool dpd_is_edp = false;
14601
14602 intel_lvds_init(dev);
14603
14604 if (intel_crt_present(dev))
14605 intel_crt_init(dev);
14606
14607 if (IS_BROXTON(dev)) {
14608 /*
14609 * FIXME: Broxton doesn't support port detection via the
14610 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14611 * detect the ports.
14612 */
14613 intel_ddi_init(dev, PORT_A);
14614 intel_ddi_init(dev, PORT_B);
14615 intel_ddi_init(dev, PORT_C);
14616 } else if (HAS_DDI(dev)) {
14617 int found;
14618
14619 /*
14620 * Haswell uses DDI functions to detect digital outputs.
14621 * On SKL pre-D0 the strap isn't connected, so we assume
14622 * it's there.
14623 */
14624 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14625 /* WaIgnoreDDIAStrap: skl */
14626 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14627 intel_ddi_init(dev, PORT_A);
14628
14629 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14630 * register */
14631 found = I915_READ(SFUSE_STRAP);
14632
14633 if (found & SFUSE_STRAP_DDIB_DETECTED)
14634 intel_ddi_init(dev, PORT_B);
14635 if (found & SFUSE_STRAP_DDIC_DETECTED)
14636 intel_ddi_init(dev, PORT_C);
14637 if (found & SFUSE_STRAP_DDID_DETECTED)
14638 intel_ddi_init(dev, PORT_D);
14639 /*
14640 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14641 */
14642 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14643 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14644 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14645 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14646 intel_ddi_init(dev, PORT_E);
14647
14648 } else if (HAS_PCH_SPLIT(dev)) {
14649 int found;
14650 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14651
14652 if (has_edp_a(dev))
14653 intel_dp_init(dev, DP_A, PORT_A);
14654
14655 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14656 /* PCH SDVOB multiplex with HDMIB */
14657 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14658 if (!found)
14659 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14660 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14661 intel_dp_init(dev, PCH_DP_B, PORT_B);
14662 }
14663
14664 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14665 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14666
14667 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14668 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14669
14670 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14671 intel_dp_init(dev, PCH_DP_C, PORT_C);
14672
14673 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14674 intel_dp_init(dev, PCH_DP_D, PORT_D);
14675 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14676 /*
14677 * The DP_DETECTED bit is the latched state of the DDC
14678 * SDA pin at boot. However since eDP doesn't require DDC
14679 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14680 * eDP ports may have been muxed to an alternate function.
14681 * Thus we can't rely on the DP_DETECTED bit alone to detect
14682 * eDP ports. Consult the VBT as well as DP_DETECTED to
14683 * detect eDP ports.
14684 */
14685 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14686 !intel_dp_is_edp(dev, PORT_B))
14687 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14688 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14689 intel_dp_is_edp(dev, PORT_B))
14690 intel_dp_init(dev, VLV_DP_B, PORT_B);
14691
14692 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14693 !intel_dp_is_edp(dev, PORT_C))
14694 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14695 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14696 intel_dp_is_edp(dev, PORT_C))
14697 intel_dp_init(dev, VLV_DP_C, PORT_C);
14698
14699 if (IS_CHERRYVIEW(dev)) {
14700 /* eDP not supported on port D, so don't check VBT */
14701 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14702 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14703 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14704 intel_dp_init(dev, CHV_DP_D, PORT_D);
14705 }
14706
14707 intel_dsi_init(dev);
14708 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14709 bool found = false;
14710
14711 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14712 DRM_DEBUG_KMS("probing SDVOB\n");
14713 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14714 if (!found && IS_G4X(dev)) {
14715 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14716 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14717 }
14718
14719 if (!found && IS_G4X(dev))
14720 intel_dp_init(dev, DP_B, PORT_B);
14721 }
14722
14723 /* Before G4X SDVOC doesn't have its own detect register */
14724
14725 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14726 DRM_DEBUG_KMS("probing SDVOC\n");
14727 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14728 }
14729
14730 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14731
14732 if (IS_G4X(dev)) {
14733 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14734 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14735 }
14736 if (IS_G4X(dev))
14737 intel_dp_init(dev, DP_C, PORT_C);
14738 }
14739
14740 if (IS_G4X(dev) &&
14741 (I915_READ(DP_D) & DP_DETECTED))
14742 intel_dp_init(dev, DP_D, PORT_D);
14743 } else if (IS_GEN2(dev))
14744 intel_dvo_init(dev);
14745
14746 if (SUPPORTS_TV(dev))
14747 intel_tv_init(dev);
14748
14749 intel_psr_init(dev);
14750
14751 for_each_intel_encoder(dev, encoder) {
14752 encoder->base.possible_crtcs = encoder->crtc_mask;
14753 encoder->base.possible_clones =
14754 intel_encoder_clones(encoder);
14755 }
14756
14757 intel_init_pch_refclk(dev);
14758
14759 drm_helper_move_panel_connectors_to_head(dev);
14760 }
14761
14762 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14763 {
14764 struct drm_device *dev = fb->dev;
14765 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14766
14767 drm_framebuffer_cleanup(fb);
14768 mutex_lock(&dev->struct_mutex);
14769 WARN_ON(!intel_fb->obj->framebuffer_references--);
14770 drm_gem_object_unreference(&intel_fb->obj->base);
14771 mutex_unlock(&dev->struct_mutex);
14772 kfree(intel_fb);
14773 }
14774
14775 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14776 struct drm_file *file,
14777 unsigned int *handle)
14778 {
14779 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14780 struct drm_i915_gem_object *obj = intel_fb->obj;
14781
14782 if (obj->userptr.mm) {
14783 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14784 return -EINVAL;
14785 }
14786
14787 return drm_gem_handle_create(file, &obj->base, handle);
14788 }
14789
14790 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14791 struct drm_file *file,
14792 unsigned flags, unsigned color,
14793 struct drm_clip_rect *clips,
14794 unsigned num_clips)
14795 {
14796 struct drm_device *dev = fb->dev;
14797 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14798 struct drm_i915_gem_object *obj = intel_fb->obj;
14799
14800 mutex_lock(&dev->struct_mutex);
14801 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14802 mutex_unlock(&dev->struct_mutex);
14803
14804 return 0;
14805 }
14806
14807 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14808 .destroy = intel_user_framebuffer_destroy,
14809 .create_handle = intel_user_framebuffer_create_handle,
14810 .dirty = intel_user_framebuffer_dirty,
14811 };
14812
14813 static
14814 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14815 uint32_t pixel_format)
14816 {
14817 u32 gen = INTEL_INFO(dev)->gen;
14818
14819 if (gen >= 9) {
14820 int cpp = drm_format_plane_cpp(pixel_format, 0);
14821
14822 /* "The stride in bytes must not exceed the of the size of 8K
14823 * pixels and 32K bytes."
14824 */
14825 return min(8192 * cpp, 32768);
14826 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14827 return 32*1024;
14828 } else if (gen >= 4) {
14829 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14830 return 16*1024;
14831 else
14832 return 32*1024;
14833 } else if (gen >= 3) {
14834 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14835 return 8*1024;
14836 else
14837 return 16*1024;
14838 } else {
14839 /* XXX DSPC is limited to 4k tiled */
14840 return 8*1024;
14841 }
14842 }
14843
14844 static int intel_framebuffer_init(struct drm_device *dev,
14845 struct intel_framebuffer *intel_fb,
14846 struct drm_mode_fb_cmd2 *mode_cmd,
14847 struct drm_i915_gem_object *obj)
14848 {
14849 struct drm_i915_private *dev_priv = to_i915(dev);
14850 unsigned int aligned_height;
14851 int ret;
14852 u32 pitch_limit, stride_alignment;
14853
14854 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14855
14856 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14857 /* Enforce that fb modifier and tiling mode match, but only for
14858 * X-tiled. This is needed for FBC. */
14859 if (!!(obj->tiling_mode == I915_TILING_X) !=
14860 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14861 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14862 return -EINVAL;
14863 }
14864 } else {
14865 if (obj->tiling_mode == I915_TILING_X)
14866 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14867 else if (obj->tiling_mode == I915_TILING_Y) {
14868 DRM_DEBUG("No Y tiling for legacy addfb\n");
14869 return -EINVAL;
14870 }
14871 }
14872
14873 /* Passed in modifier sanity checking. */
14874 switch (mode_cmd->modifier[0]) {
14875 case I915_FORMAT_MOD_Y_TILED:
14876 case I915_FORMAT_MOD_Yf_TILED:
14877 if (INTEL_INFO(dev)->gen < 9) {
14878 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14879 mode_cmd->modifier[0]);
14880 return -EINVAL;
14881 }
14882 case DRM_FORMAT_MOD_NONE:
14883 case I915_FORMAT_MOD_X_TILED:
14884 break;
14885 default:
14886 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14887 mode_cmd->modifier[0]);
14888 return -EINVAL;
14889 }
14890
14891 stride_alignment = intel_fb_stride_alignment(dev_priv,
14892 mode_cmd->modifier[0],
14893 mode_cmd->pixel_format);
14894 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14895 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14896 mode_cmd->pitches[0], stride_alignment);
14897 return -EINVAL;
14898 }
14899
14900 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14901 mode_cmd->pixel_format);
14902 if (mode_cmd->pitches[0] > pitch_limit) {
14903 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14904 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14905 "tiled" : "linear",
14906 mode_cmd->pitches[0], pitch_limit);
14907 return -EINVAL;
14908 }
14909
14910 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14911 mode_cmd->pitches[0] != obj->stride) {
14912 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14913 mode_cmd->pitches[0], obj->stride);
14914 return -EINVAL;
14915 }
14916
14917 /* Reject formats not supported by any plane early. */
14918 switch (mode_cmd->pixel_format) {
14919 case DRM_FORMAT_C8:
14920 case DRM_FORMAT_RGB565:
14921 case DRM_FORMAT_XRGB8888:
14922 case DRM_FORMAT_ARGB8888:
14923 break;
14924 case DRM_FORMAT_XRGB1555:
14925 if (INTEL_INFO(dev)->gen > 3) {
14926 DRM_DEBUG("unsupported pixel format: %s\n",
14927 drm_get_format_name(mode_cmd->pixel_format));
14928 return -EINVAL;
14929 }
14930 break;
14931 case DRM_FORMAT_ABGR8888:
14932 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14933 INTEL_INFO(dev)->gen < 9) {
14934 DRM_DEBUG("unsupported pixel format: %s\n",
14935 drm_get_format_name(mode_cmd->pixel_format));
14936 return -EINVAL;
14937 }
14938 break;
14939 case DRM_FORMAT_XBGR8888:
14940 case DRM_FORMAT_XRGB2101010:
14941 case DRM_FORMAT_XBGR2101010:
14942 if (INTEL_INFO(dev)->gen < 4) {
14943 DRM_DEBUG("unsupported pixel format: %s\n",
14944 drm_get_format_name(mode_cmd->pixel_format));
14945 return -EINVAL;
14946 }
14947 break;
14948 case DRM_FORMAT_ABGR2101010:
14949 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14950 DRM_DEBUG("unsupported pixel format: %s\n",
14951 drm_get_format_name(mode_cmd->pixel_format));
14952 return -EINVAL;
14953 }
14954 break;
14955 case DRM_FORMAT_YUYV:
14956 case DRM_FORMAT_UYVY:
14957 case DRM_FORMAT_YVYU:
14958 case DRM_FORMAT_VYUY:
14959 if (INTEL_INFO(dev)->gen < 5) {
14960 DRM_DEBUG("unsupported pixel format: %s\n",
14961 drm_get_format_name(mode_cmd->pixel_format));
14962 return -EINVAL;
14963 }
14964 break;
14965 default:
14966 DRM_DEBUG("unsupported pixel format: %s\n",
14967 drm_get_format_name(mode_cmd->pixel_format));
14968 return -EINVAL;
14969 }
14970
14971 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14972 if (mode_cmd->offsets[0] != 0)
14973 return -EINVAL;
14974
14975 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14976 mode_cmd->pixel_format,
14977 mode_cmd->modifier[0]);
14978 /* FIXME drm helper for size checks (especially planar formats)? */
14979 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14980 return -EINVAL;
14981
14982 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14983 intel_fb->obj = obj;
14984
14985 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14986 if (ret) {
14987 DRM_ERROR("framebuffer init failed %d\n", ret);
14988 return ret;
14989 }
14990
14991 intel_fb->obj->framebuffer_references++;
14992
14993 return 0;
14994 }
14995
14996 static struct drm_framebuffer *
14997 intel_user_framebuffer_create(struct drm_device *dev,
14998 struct drm_file *filp,
14999 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15000 {
15001 struct drm_framebuffer *fb;
15002 struct drm_i915_gem_object *obj;
15003 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15004
15005 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
15006 mode_cmd.handles[0]));
15007 if (&obj->base == NULL)
15008 return ERR_PTR(-ENOENT);
15009
15010 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15011 if (IS_ERR(fb))
15012 drm_gem_object_unreference_unlocked(&obj->base);
15013
15014 return fb;
15015 }
15016
15017 #ifndef CONFIG_DRM_FBDEV_EMULATION
15018 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15019 {
15020 }
15021 #endif
15022
15023 static const struct drm_mode_config_funcs intel_mode_funcs = {
15024 .fb_create = intel_user_framebuffer_create,
15025 .output_poll_changed = intel_fbdev_output_poll_changed,
15026 .atomic_check = intel_atomic_check,
15027 .atomic_commit = intel_atomic_commit,
15028 .atomic_state_alloc = intel_atomic_state_alloc,
15029 .atomic_state_clear = intel_atomic_state_clear,
15030 };
15031
15032 /* Set up chip specific display functions */
15033 static void intel_init_display(struct drm_device *dev)
15034 {
15035 struct drm_i915_private *dev_priv = dev->dev_private;
15036
15037 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
15038 dev_priv->display.find_dpll = g4x_find_best_dpll;
15039 else if (IS_CHERRYVIEW(dev))
15040 dev_priv->display.find_dpll = chv_find_best_dpll;
15041 else if (IS_VALLEYVIEW(dev))
15042 dev_priv->display.find_dpll = vlv_find_best_dpll;
15043 else if (IS_PINEVIEW(dev))
15044 dev_priv->display.find_dpll = pnv_find_best_dpll;
15045 else
15046 dev_priv->display.find_dpll = i9xx_find_best_dpll;
15047
15048 if (INTEL_INFO(dev)->gen >= 9) {
15049 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15050 dev_priv->display.get_initial_plane_config =
15051 skylake_get_initial_plane_config;
15052 dev_priv->display.crtc_compute_clock =
15053 haswell_crtc_compute_clock;
15054 dev_priv->display.crtc_enable = haswell_crtc_enable;
15055 dev_priv->display.crtc_disable = haswell_crtc_disable;
15056 } else if (HAS_DDI(dev)) {
15057 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15058 dev_priv->display.get_initial_plane_config =
15059 ironlake_get_initial_plane_config;
15060 dev_priv->display.crtc_compute_clock =
15061 haswell_crtc_compute_clock;
15062 dev_priv->display.crtc_enable = haswell_crtc_enable;
15063 dev_priv->display.crtc_disable = haswell_crtc_disable;
15064 } else if (HAS_PCH_SPLIT(dev)) {
15065 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15066 dev_priv->display.get_initial_plane_config =
15067 ironlake_get_initial_plane_config;
15068 dev_priv->display.crtc_compute_clock =
15069 ironlake_crtc_compute_clock;
15070 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15071 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15072 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15073 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15074 dev_priv->display.get_initial_plane_config =
15075 i9xx_get_initial_plane_config;
15076 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15077 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15078 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15079 } else {
15080 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15081 dev_priv->display.get_initial_plane_config =
15082 i9xx_get_initial_plane_config;
15083 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15084 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15085 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15086 }
15087
15088 /* Returns the core display clock speed */
15089 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15090 dev_priv->display.get_display_clock_speed =
15091 skylake_get_display_clock_speed;
15092 else if (IS_BROXTON(dev))
15093 dev_priv->display.get_display_clock_speed =
15094 broxton_get_display_clock_speed;
15095 else if (IS_BROADWELL(dev))
15096 dev_priv->display.get_display_clock_speed =
15097 broadwell_get_display_clock_speed;
15098 else if (IS_HASWELL(dev))
15099 dev_priv->display.get_display_clock_speed =
15100 haswell_get_display_clock_speed;
15101 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15102 dev_priv->display.get_display_clock_speed =
15103 valleyview_get_display_clock_speed;
15104 else if (IS_GEN5(dev))
15105 dev_priv->display.get_display_clock_speed =
15106 ilk_get_display_clock_speed;
15107 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
15108 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
15109 dev_priv->display.get_display_clock_speed =
15110 i945_get_display_clock_speed;
15111 else if (IS_GM45(dev))
15112 dev_priv->display.get_display_clock_speed =
15113 gm45_get_display_clock_speed;
15114 else if (IS_CRESTLINE(dev))
15115 dev_priv->display.get_display_clock_speed =
15116 i965gm_get_display_clock_speed;
15117 else if (IS_PINEVIEW(dev))
15118 dev_priv->display.get_display_clock_speed =
15119 pnv_get_display_clock_speed;
15120 else if (IS_G33(dev) || IS_G4X(dev))
15121 dev_priv->display.get_display_clock_speed =
15122 g33_get_display_clock_speed;
15123 else if (IS_I915G(dev))
15124 dev_priv->display.get_display_clock_speed =
15125 i915_get_display_clock_speed;
15126 else if (IS_I945GM(dev) || IS_845G(dev))
15127 dev_priv->display.get_display_clock_speed =
15128 i9xx_misc_get_display_clock_speed;
15129 else if (IS_I915GM(dev))
15130 dev_priv->display.get_display_clock_speed =
15131 i915gm_get_display_clock_speed;
15132 else if (IS_I865G(dev))
15133 dev_priv->display.get_display_clock_speed =
15134 i865_get_display_clock_speed;
15135 else if (IS_I85X(dev))
15136 dev_priv->display.get_display_clock_speed =
15137 i85x_get_display_clock_speed;
15138 else { /* 830 */
15139 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
15140 dev_priv->display.get_display_clock_speed =
15141 i830_get_display_clock_speed;
15142 }
15143
15144 if (IS_GEN5(dev)) {
15145 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15146 } else if (IS_GEN6(dev)) {
15147 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15148 } else if (IS_IVYBRIDGE(dev)) {
15149 /* FIXME: detect B0+ stepping and use auto training */
15150 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15151 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
15152 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15153 if (IS_BROADWELL(dev)) {
15154 dev_priv->display.modeset_commit_cdclk =
15155 broadwell_modeset_commit_cdclk;
15156 dev_priv->display.modeset_calc_cdclk =
15157 broadwell_modeset_calc_cdclk;
15158 }
15159 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15160 dev_priv->display.modeset_commit_cdclk =
15161 valleyview_modeset_commit_cdclk;
15162 dev_priv->display.modeset_calc_cdclk =
15163 valleyview_modeset_calc_cdclk;
15164 } else if (IS_BROXTON(dev)) {
15165 dev_priv->display.modeset_commit_cdclk =
15166 broxton_modeset_commit_cdclk;
15167 dev_priv->display.modeset_calc_cdclk =
15168 broxton_modeset_calc_cdclk;
15169 }
15170
15171 switch (INTEL_INFO(dev)->gen) {
15172 case 2:
15173 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15174 break;
15175
15176 case 3:
15177 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15178 break;
15179
15180 case 4:
15181 case 5:
15182 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15183 break;
15184
15185 case 6:
15186 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15187 break;
15188 case 7:
15189 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15190 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15191 break;
15192 case 9:
15193 /* Drop through - unsupported since execlist only. */
15194 default:
15195 /* Default just returns -ENODEV to indicate unsupported */
15196 dev_priv->display.queue_flip = intel_default_queue_flip;
15197 }
15198
15199 mutex_init(&dev_priv->pps_mutex);
15200 }
15201
15202 /*
15203 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15204 * resume, or other times. This quirk makes sure that's the case for
15205 * affected systems.
15206 */
15207 static void quirk_pipea_force(struct drm_device *dev)
15208 {
15209 struct drm_i915_private *dev_priv = dev->dev_private;
15210
15211 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15212 DRM_INFO("applying pipe a force quirk\n");
15213 }
15214
15215 static void quirk_pipeb_force(struct drm_device *dev)
15216 {
15217 struct drm_i915_private *dev_priv = dev->dev_private;
15218
15219 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15220 DRM_INFO("applying pipe b force quirk\n");
15221 }
15222
15223 /*
15224 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15225 */
15226 static void quirk_ssc_force_disable(struct drm_device *dev)
15227 {
15228 struct drm_i915_private *dev_priv = dev->dev_private;
15229 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15230 DRM_INFO("applying lvds SSC disable quirk\n");
15231 }
15232
15233 /*
15234 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15235 * brightness value
15236 */
15237 static void quirk_invert_brightness(struct drm_device *dev)
15238 {
15239 struct drm_i915_private *dev_priv = dev->dev_private;
15240 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15241 DRM_INFO("applying inverted panel brightness quirk\n");
15242 }
15243
15244 /* Some VBT's incorrectly indicate no backlight is present */
15245 static void quirk_backlight_present(struct drm_device *dev)
15246 {
15247 struct drm_i915_private *dev_priv = dev->dev_private;
15248 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15249 DRM_INFO("applying backlight present quirk\n");
15250 }
15251
15252 struct intel_quirk {
15253 int device;
15254 int subsystem_vendor;
15255 int subsystem_device;
15256 void (*hook)(struct drm_device *dev);
15257 };
15258
15259 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15260 struct intel_dmi_quirk {
15261 void (*hook)(struct drm_device *dev);
15262 const struct dmi_system_id (*dmi_id_list)[];
15263 };
15264
15265 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15266 {
15267 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15268 return 1;
15269 }
15270
15271 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15272 {
15273 .dmi_id_list = &(const struct dmi_system_id[]) {
15274 {
15275 .callback = intel_dmi_reverse_brightness,
15276 .ident = "NCR Corporation",
15277 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15278 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15279 },
15280 },
15281 { } /* terminating entry */
15282 },
15283 .hook = quirk_invert_brightness,
15284 },
15285 };
15286
15287 static struct intel_quirk intel_quirks[] = {
15288 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15289 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15290
15291 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15292 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15293
15294 /* 830 needs to leave pipe A & dpll A up */
15295 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15296
15297 /* 830 needs to leave pipe B & dpll B up */
15298 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15299
15300 /* Lenovo U160 cannot use SSC on LVDS */
15301 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15302
15303 /* Sony Vaio Y cannot use SSC on LVDS */
15304 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15305
15306 /* Acer Aspire 5734Z must invert backlight brightness */
15307 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15308
15309 /* Acer/eMachines G725 */
15310 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15311
15312 /* Acer/eMachines e725 */
15313 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15314
15315 /* Acer/Packard Bell NCL20 */
15316 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15317
15318 /* Acer Aspire 4736Z */
15319 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15320
15321 /* Acer Aspire 5336 */
15322 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15323
15324 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15325 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15326
15327 /* Acer C720 Chromebook (Core i3 4005U) */
15328 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15329
15330 /* Apple Macbook 2,1 (Core 2 T7400) */
15331 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15332
15333 /* Apple Macbook 4,1 */
15334 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15335
15336 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15337 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15338
15339 /* HP Chromebook 14 (Celeron 2955U) */
15340 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15341
15342 /* Dell Chromebook 11 */
15343 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15344
15345 /* Dell Chromebook 11 (2015 version) */
15346 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15347 };
15348
15349 static void intel_init_quirks(struct drm_device *dev)
15350 {
15351 struct pci_dev *d = dev->pdev;
15352 int i;
15353
15354 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15355 struct intel_quirk *q = &intel_quirks[i];
15356
15357 if (d->device == q->device &&
15358 (d->subsystem_vendor == q->subsystem_vendor ||
15359 q->subsystem_vendor == PCI_ANY_ID) &&
15360 (d->subsystem_device == q->subsystem_device ||
15361 q->subsystem_device == PCI_ANY_ID))
15362 q->hook(dev);
15363 }
15364 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15365 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15366 intel_dmi_quirks[i].hook(dev);
15367 }
15368 }
15369
15370 /* Disable the VGA plane that we never use */
15371 static void i915_disable_vga(struct drm_device *dev)
15372 {
15373 struct drm_i915_private *dev_priv = dev->dev_private;
15374 u8 sr1;
15375 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15376
15377 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15378 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15379 outb(SR01, VGA_SR_INDEX);
15380 sr1 = inb(VGA_SR_DATA);
15381 outb(sr1 | 1<<5, VGA_SR_DATA);
15382 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15383 udelay(300);
15384
15385 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15386 POSTING_READ(vga_reg);
15387 }
15388
15389 void intel_modeset_init_hw(struct drm_device *dev)
15390 {
15391 struct drm_i915_private *dev_priv = dev->dev_private;
15392
15393 intel_update_cdclk(dev);
15394
15395 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15396
15397 intel_init_clock_gating(dev);
15398 intel_enable_gt_powersave(dev);
15399 }
15400
15401 /*
15402 * Calculate what we think the watermarks should be for the state we've read
15403 * out of the hardware and then immediately program those watermarks so that
15404 * we ensure the hardware settings match our internal state.
15405 *
15406 * We can calculate what we think WM's should be by creating a duplicate of the
15407 * current state (which was constructed during hardware readout) and running it
15408 * through the atomic check code to calculate new watermark values in the
15409 * state object.
15410 */
15411 static void sanitize_watermarks(struct drm_device *dev)
15412 {
15413 struct drm_i915_private *dev_priv = to_i915(dev);
15414 struct drm_atomic_state *state;
15415 struct drm_crtc *crtc;
15416 struct drm_crtc_state *cstate;
15417 struct drm_modeset_acquire_ctx ctx;
15418 int ret;
15419 int i;
15420
15421 /* Only supported on platforms that use atomic watermark design */
15422 if (!dev_priv->display.optimize_watermarks)
15423 return;
15424
15425 /*
15426 * We need to hold connection_mutex before calling duplicate_state so
15427 * that the connector loop is protected.
15428 */
15429 drm_modeset_acquire_init(&ctx, 0);
15430 retry:
15431 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15432 if (ret == -EDEADLK) {
15433 drm_modeset_backoff(&ctx);
15434 goto retry;
15435 } else if (WARN_ON(ret)) {
15436 goto fail;
15437 }
15438
15439 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15440 if (WARN_ON(IS_ERR(state)))
15441 goto fail;
15442
15443 /*
15444 * Hardware readout is the only time we don't want to calculate
15445 * intermediate watermarks (since we don't trust the current
15446 * watermarks).
15447 */
15448 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15449
15450 ret = intel_atomic_check(dev, state);
15451 if (ret) {
15452 /*
15453 * If we fail here, it means that the hardware appears to be
15454 * programmed in a way that shouldn't be possible, given our
15455 * understanding of watermark requirements. This might mean a
15456 * mistake in the hardware readout code or a mistake in the
15457 * watermark calculations for a given platform. Raise a WARN
15458 * so that this is noticeable.
15459 *
15460 * If this actually happens, we'll have to just leave the
15461 * BIOS-programmed watermarks untouched and hope for the best.
15462 */
15463 WARN(true, "Could not determine valid watermarks for inherited state\n");
15464 goto fail;
15465 }
15466
15467 /* Write calculated watermark values back */
15468 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15469 for_each_crtc_in_state(state, crtc, cstate, i) {
15470 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15471
15472 cs->wm.need_postvbl_update = true;
15473 dev_priv->display.optimize_watermarks(cs);
15474 }
15475
15476 drm_atomic_state_free(state);
15477 fail:
15478 drm_modeset_drop_locks(&ctx);
15479 drm_modeset_acquire_fini(&ctx);
15480 }
15481
15482 void intel_modeset_init(struct drm_device *dev)
15483 {
15484 struct drm_i915_private *dev_priv = dev->dev_private;
15485 int sprite, ret;
15486 enum pipe pipe;
15487 struct intel_crtc *crtc;
15488
15489 drm_mode_config_init(dev);
15490
15491 dev->mode_config.min_width = 0;
15492 dev->mode_config.min_height = 0;
15493
15494 dev->mode_config.preferred_depth = 24;
15495 dev->mode_config.prefer_shadow = 1;
15496
15497 dev->mode_config.allow_fb_modifiers = true;
15498
15499 dev->mode_config.funcs = &intel_mode_funcs;
15500
15501 intel_init_quirks(dev);
15502
15503 intel_init_pm(dev);
15504
15505 if (INTEL_INFO(dev)->num_pipes == 0)
15506 return;
15507
15508 /*
15509 * There may be no VBT; and if the BIOS enabled SSC we can
15510 * just keep using it to avoid unnecessary flicker. Whereas if the
15511 * BIOS isn't using it, don't assume it will work even if the VBT
15512 * indicates as much.
15513 */
15514 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15515 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15516 DREF_SSC1_ENABLE);
15517
15518 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15519 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15520 bios_lvds_use_ssc ? "en" : "dis",
15521 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15522 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15523 }
15524 }
15525
15526 intel_init_display(dev);
15527 intel_init_audio(dev);
15528
15529 if (IS_GEN2(dev)) {
15530 dev->mode_config.max_width = 2048;
15531 dev->mode_config.max_height = 2048;
15532 } else if (IS_GEN3(dev)) {
15533 dev->mode_config.max_width = 4096;
15534 dev->mode_config.max_height = 4096;
15535 } else {
15536 dev->mode_config.max_width = 8192;
15537 dev->mode_config.max_height = 8192;
15538 }
15539
15540 if (IS_845G(dev) || IS_I865G(dev)) {
15541 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15542 dev->mode_config.cursor_height = 1023;
15543 } else if (IS_GEN2(dev)) {
15544 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15545 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15546 } else {
15547 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15548 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15549 }
15550
15551 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15552
15553 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15554 INTEL_INFO(dev)->num_pipes,
15555 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15556
15557 for_each_pipe(dev_priv, pipe) {
15558 intel_crtc_init(dev, pipe);
15559 for_each_sprite(dev_priv, pipe, sprite) {
15560 ret = intel_plane_init(dev, pipe, sprite);
15561 if (ret)
15562 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15563 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15564 }
15565 }
15566
15567 intel_update_czclk(dev_priv);
15568 intel_update_cdclk(dev);
15569
15570 intel_shared_dpll_init(dev);
15571
15572 /* Just disable it once at startup */
15573 i915_disable_vga(dev);
15574 intel_setup_outputs(dev);
15575
15576 drm_modeset_lock_all(dev);
15577 intel_modeset_setup_hw_state(dev);
15578 drm_modeset_unlock_all(dev);
15579
15580 for_each_intel_crtc(dev, crtc) {
15581 struct intel_initial_plane_config plane_config = {};
15582
15583 if (!crtc->active)
15584 continue;
15585
15586 /*
15587 * Note that reserving the BIOS fb up front prevents us
15588 * from stuffing other stolen allocations like the ring
15589 * on top. This prevents some ugliness at boot time, and
15590 * can even allow for smooth boot transitions if the BIOS
15591 * fb is large enough for the active pipe configuration.
15592 */
15593 dev_priv->display.get_initial_plane_config(crtc,
15594 &plane_config);
15595
15596 /*
15597 * If the fb is shared between multiple heads, we'll
15598 * just get the first one.
15599 */
15600 intel_find_initial_plane_obj(crtc, &plane_config);
15601 }
15602
15603 /*
15604 * Make sure hardware watermarks really match the state we read out.
15605 * Note that we need to do this after reconstructing the BIOS fb's
15606 * since the watermark calculation done here will use pstate->fb.
15607 */
15608 sanitize_watermarks(dev);
15609 }
15610
15611 static void intel_enable_pipe_a(struct drm_device *dev)
15612 {
15613 struct intel_connector *connector;
15614 struct drm_connector *crt = NULL;
15615 struct intel_load_detect_pipe load_detect_temp;
15616 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15617
15618 /* We can't just switch on the pipe A, we need to set things up with a
15619 * proper mode and output configuration. As a gross hack, enable pipe A
15620 * by enabling the load detect pipe once. */
15621 for_each_intel_connector(dev, connector) {
15622 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15623 crt = &connector->base;
15624 break;
15625 }
15626 }
15627
15628 if (!crt)
15629 return;
15630
15631 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15632 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15633 }
15634
15635 static bool
15636 intel_check_plane_mapping(struct intel_crtc *crtc)
15637 {
15638 struct drm_device *dev = crtc->base.dev;
15639 struct drm_i915_private *dev_priv = dev->dev_private;
15640 u32 val;
15641
15642 if (INTEL_INFO(dev)->num_pipes == 1)
15643 return true;
15644
15645 val = I915_READ(DSPCNTR(!crtc->plane));
15646
15647 if ((val & DISPLAY_PLANE_ENABLE) &&
15648 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15649 return false;
15650
15651 return true;
15652 }
15653
15654 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15655 {
15656 struct drm_device *dev = crtc->base.dev;
15657 struct intel_encoder *encoder;
15658
15659 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15660 return true;
15661
15662 return false;
15663 }
15664
15665 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15666 {
15667 struct drm_device *dev = encoder->base.dev;
15668 struct intel_connector *connector;
15669
15670 for_each_connector_on_encoder(dev, &encoder->base, connector)
15671 return true;
15672
15673 return false;
15674 }
15675
15676 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15677 {
15678 struct drm_device *dev = crtc->base.dev;
15679 struct drm_i915_private *dev_priv = dev->dev_private;
15680 i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15681
15682 /* Clear any frame start delays used for debugging left by the BIOS */
15683 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15684
15685 /* restore vblank interrupts to correct state */
15686 drm_crtc_vblank_reset(&crtc->base);
15687 if (crtc->active) {
15688 struct intel_plane *plane;
15689
15690 drm_crtc_vblank_on(&crtc->base);
15691
15692 /* Disable everything but the primary plane */
15693 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15694 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15695 continue;
15696
15697 plane->disable_plane(&plane->base, &crtc->base);
15698 }
15699 }
15700
15701 /* We need to sanitize the plane -> pipe mapping first because this will
15702 * disable the crtc (and hence change the state) if it is wrong. Note
15703 * that gen4+ has a fixed plane -> pipe mapping. */
15704 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15705 bool plane;
15706
15707 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15708 crtc->base.base.id);
15709
15710 /* Pipe has the wrong plane attached and the plane is active.
15711 * Temporarily change the plane mapping and disable everything
15712 * ... */
15713 plane = crtc->plane;
15714 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15715 crtc->plane = !plane;
15716 intel_crtc_disable_noatomic(&crtc->base);
15717 crtc->plane = plane;
15718 }
15719
15720 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15721 crtc->pipe == PIPE_A && !crtc->active) {
15722 /* BIOS forgot to enable pipe A, this mostly happens after
15723 * resume. Force-enable the pipe to fix this, the update_dpms
15724 * call below we restore the pipe to the right state, but leave
15725 * the required bits on. */
15726 intel_enable_pipe_a(dev);
15727 }
15728
15729 /* Adjust the state of the output pipe according to whether we
15730 * have active connectors/encoders. */
15731 if (!intel_crtc_has_encoders(crtc))
15732 intel_crtc_disable_noatomic(&crtc->base);
15733
15734 if (crtc->active != crtc->base.state->active) {
15735 struct intel_encoder *encoder;
15736
15737 /* This can happen either due to bugs in the get_hw_state
15738 * functions or because of calls to intel_crtc_disable_noatomic,
15739 * or because the pipe is force-enabled due to the
15740 * pipe A quirk. */
15741 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15742 crtc->base.base.id,
15743 crtc->base.state->enable ? "enabled" : "disabled",
15744 crtc->active ? "enabled" : "disabled");
15745
15746 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15747 crtc->base.state->active = crtc->active;
15748 crtc->base.enabled = crtc->active;
15749 crtc->base.state->connector_mask = 0;
15750 crtc->base.state->encoder_mask = 0;
15751
15752 /* Because we only establish the connector -> encoder ->
15753 * crtc links if something is active, this means the
15754 * crtc is now deactivated. Break the links. connector
15755 * -> encoder links are only establish when things are
15756 * actually up, hence no need to break them. */
15757 WARN_ON(crtc->active);
15758
15759 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15760 encoder->base.crtc = NULL;
15761 }
15762
15763 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15764 /*
15765 * We start out with underrun reporting disabled to avoid races.
15766 * For correct bookkeeping mark this on active crtcs.
15767 *
15768 * Also on gmch platforms we dont have any hardware bits to
15769 * disable the underrun reporting. Which means we need to start
15770 * out with underrun reporting disabled also on inactive pipes,
15771 * since otherwise we'll complain about the garbage we read when
15772 * e.g. coming up after runtime pm.
15773 *
15774 * No protection against concurrent access is required - at
15775 * worst a fifo underrun happens which also sets this to false.
15776 */
15777 crtc->cpu_fifo_underrun_disabled = true;
15778 crtc->pch_fifo_underrun_disabled = true;
15779 }
15780 }
15781
15782 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15783 {
15784 struct intel_connector *connector;
15785 struct drm_device *dev = encoder->base.dev;
15786
15787 /* We need to check both for a crtc link (meaning that the
15788 * encoder is active and trying to read from a pipe) and the
15789 * pipe itself being active. */
15790 bool has_active_crtc = encoder->base.crtc &&
15791 to_intel_crtc(encoder->base.crtc)->active;
15792
15793 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15794 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15795 encoder->base.base.id,
15796 encoder->base.name);
15797
15798 /* Connector is active, but has no active pipe. This is
15799 * fallout from our resume register restoring. Disable
15800 * the encoder manually again. */
15801 if (encoder->base.crtc) {
15802 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15803 encoder->base.base.id,
15804 encoder->base.name);
15805 encoder->disable(encoder);
15806 if (encoder->post_disable)
15807 encoder->post_disable(encoder);
15808 }
15809 encoder->base.crtc = NULL;
15810
15811 /* Inconsistent output/port/pipe state happens presumably due to
15812 * a bug in one of the get_hw_state functions. Or someplace else
15813 * in our code, like the register restore mess on resume. Clamp
15814 * things to off as a safer default. */
15815 for_each_intel_connector(dev, connector) {
15816 if (connector->encoder != encoder)
15817 continue;
15818 connector->base.dpms = DRM_MODE_DPMS_OFF;
15819 connector->base.encoder = NULL;
15820 }
15821 }
15822 /* Enabled encoders without active connectors will be fixed in
15823 * the crtc fixup. */
15824 }
15825
15826 void i915_redisable_vga_power_on(struct drm_device *dev)
15827 {
15828 struct drm_i915_private *dev_priv = dev->dev_private;
15829 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15830
15831 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15832 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15833 i915_disable_vga(dev);
15834 }
15835 }
15836
15837 void i915_redisable_vga(struct drm_device *dev)
15838 {
15839 struct drm_i915_private *dev_priv = dev->dev_private;
15840
15841 /* This function can be called both from intel_modeset_setup_hw_state or
15842 * at a very early point in our resume sequence, where the power well
15843 * structures are not yet restored. Since this function is at a very
15844 * paranoid "someone might have enabled VGA while we were not looking"
15845 * level, just check if the power well is enabled instead of trying to
15846 * follow the "don't touch the power well if we don't need it" policy
15847 * the rest of the driver uses. */
15848 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15849 return;
15850
15851 i915_redisable_vga_power_on(dev);
15852
15853 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15854 }
15855
15856 static bool primary_get_hw_state(struct intel_plane *plane)
15857 {
15858 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15859
15860 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15861 }
15862
15863 /* FIXME read out full plane state for all planes */
15864 static void readout_plane_state(struct intel_crtc *crtc)
15865 {
15866 struct drm_plane *primary = crtc->base.primary;
15867 struct intel_plane_state *plane_state =
15868 to_intel_plane_state(primary->state);
15869
15870 plane_state->visible = crtc->active &&
15871 primary_get_hw_state(to_intel_plane(primary));
15872
15873 if (plane_state->visible)
15874 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15875 }
15876
15877 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15878 {
15879 struct drm_i915_private *dev_priv = dev->dev_private;
15880 enum pipe pipe;
15881 struct intel_crtc *crtc;
15882 struct intel_encoder *encoder;
15883 struct intel_connector *connector;
15884 int i;
15885
15886 dev_priv->active_crtcs = 0;
15887
15888 for_each_intel_crtc(dev, crtc) {
15889 struct intel_crtc_state *crtc_state = crtc->config;
15890 int pixclk = 0;
15891
15892 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15893 memset(crtc_state, 0, sizeof(*crtc_state));
15894 crtc_state->base.crtc = &crtc->base;
15895
15896 crtc_state->base.active = crtc_state->base.enable =
15897 dev_priv->display.get_pipe_config(crtc, crtc_state);
15898
15899 crtc->base.enabled = crtc_state->base.enable;
15900 crtc->active = crtc_state->base.active;
15901
15902 if (crtc_state->base.active) {
15903 dev_priv->active_crtcs |= 1 << crtc->pipe;
15904
15905 if (IS_BROADWELL(dev_priv)) {
15906 pixclk = ilk_pipe_pixel_rate(crtc_state);
15907
15908 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15909 if (crtc_state->ips_enabled)
15910 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15911 } else if (IS_VALLEYVIEW(dev_priv) ||
15912 IS_CHERRYVIEW(dev_priv) ||
15913 IS_BROXTON(dev_priv))
15914 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15915 else
15916 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15917 }
15918
15919 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15920
15921 readout_plane_state(crtc);
15922
15923 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15924 crtc->base.base.id,
15925 crtc->active ? "enabled" : "disabled");
15926 }
15927
15928 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15929 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15930
15931 pll->on = pll->get_hw_state(dev_priv, pll,
15932 &pll->config.hw_state);
15933 pll->active = 0;
15934 pll->config.crtc_mask = 0;
15935 for_each_intel_crtc(dev, crtc) {
15936 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15937 pll->active++;
15938 pll->config.crtc_mask |= 1 << crtc->pipe;
15939 }
15940 }
15941
15942 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15943 pll->name, pll->config.crtc_mask, pll->on);
15944
15945 if (pll->config.crtc_mask)
15946 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15947 }
15948
15949 for_each_intel_encoder(dev, encoder) {
15950 pipe = 0;
15951
15952 if (encoder->get_hw_state(encoder, &pipe)) {
15953 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15954 encoder->base.crtc = &crtc->base;
15955 encoder->get_config(encoder, crtc->config);
15956 } else {
15957 encoder->base.crtc = NULL;
15958 }
15959
15960 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15961 encoder->base.base.id,
15962 encoder->base.name,
15963 encoder->base.crtc ? "enabled" : "disabled",
15964 pipe_name(pipe));
15965 }
15966
15967 for_each_intel_connector(dev, connector) {
15968 if (connector->get_hw_state(connector)) {
15969 connector->base.dpms = DRM_MODE_DPMS_ON;
15970
15971 encoder = connector->encoder;
15972 connector->base.encoder = &encoder->base;
15973
15974 if (encoder->base.crtc &&
15975 encoder->base.crtc->state->active) {
15976 /*
15977 * This has to be done during hardware readout
15978 * because anything calling .crtc_disable may
15979 * rely on the connector_mask being accurate.
15980 */
15981 encoder->base.crtc->state->connector_mask |=
15982 1 << drm_connector_index(&connector->base);
15983 encoder->base.crtc->state->encoder_mask |=
15984 1 << drm_encoder_index(&encoder->base);
15985 }
15986
15987 } else {
15988 connector->base.dpms = DRM_MODE_DPMS_OFF;
15989 connector->base.encoder = NULL;
15990 }
15991 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15992 connector->base.base.id,
15993 connector->base.name,
15994 connector->base.encoder ? "enabled" : "disabled");
15995 }
15996
15997 for_each_intel_crtc(dev, crtc) {
15998 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15999
16000 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16001 if (crtc->base.state->active) {
16002 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16003 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16004 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16005
16006 /*
16007 * The initial mode needs to be set in order to keep
16008 * the atomic core happy. It wants a valid mode if the
16009 * crtc's enabled, so we do the above call.
16010 *
16011 * At this point some state updated by the connectors
16012 * in their ->detect() callback has not run yet, so
16013 * no recalculation can be done yet.
16014 *
16015 * Even if we could do a recalculation and modeset
16016 * right now it would cause a double modeset if
16017 * fbdev or userspace chooses a different initial mode.
16018 *
16019 * If that happens, someone indicated they wanted a
16020 * mode change, which means it's safe to do a full
16021 * recalculation.
16022 */
16023 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16024
16025 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16026 update_scanline_offset(crtc);
16027 }
16028 }
16029 }
16030
16031 /* Scan out the current hw modeset state,
16032 * and sanitizes it to the current state
16033 */
16034 static void
16035 intel_modeset_setup_hw_state(struct drm_device *dev)
16036 {
16037 struct drm_i915_private *dev_priv = dev->dev_private;
16038 enum pipe pipe;
16039 struct intel_crtc *crtc;
16040 struct intel_encoder *encoder;
16041 int i;
16042
16043 intel_modeset_readout_hw_state(dev);
16044
16045 /* HW state is read out, now we need to sanitize this mess. */
16046 for_each_intel_encoder(dev, encoder) {
16047 intel_sanitize_encoder(encoder);
16048 }
16049
16050 for_each_pipe(dev_priv, pipe) {
16051 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16052 intel_sanitize_crtc(crtc);
16053 intel_dump_pipe_config(crtc, crtc->config,
16054 "[setup_hw_state]");
16055 }
16056
16057 intel_modeset_update_connector_atomic_state(dev);
16058
16059 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16060 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16061
16062 if (!pll->on || pll->active)
16063 continue;
16064
16065 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16066
16067 pll->disable(dev_priv, pll);
16068 pll->on = false;
16069 }
16070
16071 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16072 vlv_wm_get_hw_state(dev);
16073 else if (IS_GEN9(dev))
16074 skl_wm_get_hw_state(dev);
16075 else if (HAS_PCH_SPLIT(dev))
16076 ilk_wm_get_hw_state(dev);
16077
16078 for_each_intel_crtc(dev, crtc) {
16079 unsigned long put_domains;
16080
16081 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16082 if (WARN_ON(put_domains))
16083 modeset_put_power_domains(dev_priv, put_domains);
16084 }
16085 intel_display_set_init_power(dev_priv, false);
16086
16087 intel_fbc_init_pipe_state(dev_priv);
16088 }
16089
16090 void intel_display_resume(struct drm_device *dev)
16091 {
16092 struct drm_i915_private *dev_priv = to_i915(dev);
16093 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16094 struct drm_modeset_acquire_ctx ctx;
16095 int ret;
16096 bool setup = false;
16097
16098 dev_priv->modeset_restore_state = NULL;
16099
16100 /*
16101 * This is a cludge because with real atomic modeset mode_config.mutex
16102 * won't be taken. Unfortunately some probed state like
16103 * audio_codec_enable is still protected by mode_config.mutex, so lock
16104 * it here for now.
16105 */
16106 mutex_lock(&dev->mode_config.mutex);
16107 drm_modeset_acquire_init(&ctx, 0);
16108
16109 retry:
16110 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16111
16112 if (ret == 0 && !setup) {
16113 setup = true;
16114
16115 intel_modeset_setup_hw_state(dev);
16116 i915_redisable_vga(dev);
16117 }
16118
16119 if (ret == 0 && state) {
16120 struct drm_crtc_state *crtc_state;
16121 struct drm_crtc *crtc;
16122 int i;
16123
16124 state->acquire_ctx = &ctx;
16125
16126 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16127 /*
16128 * Force recalculation even if we restore
16129 * current state. With fast modeset this may not result
16130 * in a modeset when the state is compatible.
16131 */
16132 crtc_state->mode_changed = true;
16133 }
16134
16135 ret = drm_atomic_commit(state);
16136 }
16137
16138 if (ret == -EDEADLK) {
16139 drm_modeset_backoff(&ctx);
16140 goto retry;
16141 }
16142
16143 drm_modeset_drop_locks(&ctx);
16144 drm_modeset_acquire_fini(&ctx);
16145 mutex_unlock(&dev->mode_config.mutex);
16146
16147 if (ret) {
16148 DRM_ERROR("Restoring old state failed with %i\n", ret);
16149 drm_atomic_state_free(state);
16150 }
16151 }
16152
16153 void intel_modeset_gem_init(struct drm_device *dev)
16154 {
16155 struct drm_crtc *c;
16156 struct drm_i915_gem_object *obj;
16157 int ret;
16158
16159 intel_init_gt_powersave(dev);
16160
16161 intel_modeset_init_hw(dev);
16162
16163 intel_setup_overlay(dev);
16164
16165 /*
16166 * Make sure any fbs we allocated at startup are properly
16167 * pinned & fenced. When we do the allocation it's too early
16168 * for this.
16169 */
16170 for_each_crtc(dev, c) {
16171 obj = intel_fb_obj(c->primary->fb);
16172 if (obj == NULL)
16173 continue;
16174
16175 mutex_lock(&dev->struct_mutex);
16176 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16177 c->primary->state->rotation);
16178 mutex_unlock(&dev->struct_mutex);
16179 if (ret) {
16180 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16181 to_intel_crtc(c)->pipe);
16182 drm_framebuffer_unreference(c->primary->fb);
16183 c->primary->fb = NULL;
16184 c->primary->crtc = c->primary->state->crtc = NULL;
16185 update_state_fb(c->primary);
16186 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16187 }
16188 }
16189
16190 intel_backlight_register(dev);
16191 }
16192
16193 void intel_connector_unregister(struct intel_connector *intel_connector)
16194 {
16195 struct drm_connector *connector = &intel_connector->base;
16196
16197 intel_panel_destroy_backlight(connector);
16198 drm_connector_unregister(connector);
16199 }
16200
16201 void intel_modeset_cleanup(struct drm_device *dev)
16202 {
16203 struct drm_i915_private *dev_priv = dev->dev_private;
16204 struct intel_connector *connector;
16205
16206 intel_disable_gt_powersave(dev);
16207
16208 intel_backlight_unregister(dev);
16209
16210 /*
16211 * Interrupts and polling as the first thing to avoid creating havoc.
16212 * Too much stuff here (turning of connectors, ...) would
16213 * experience fancy races otherwise.
16214 */
16215 intel_irq_uninstall(dev_priv);
16216
16217 /*
16218 * Due to the hpd irq storm handling the hotplug work can re-arm the
16219 * poll handlers. Hence disable polling after hpd handling is shut down.
16220 */
16221 drm_kms_helper_poll_fini(dev);
16222
16223 intel_unregister_dsm_handler();
16224
16225 intel_fbc_global_disable(dev_priv);
16226
16227 /* flush any delayed tasks or pending work */
16228 flush_scheduled_work();
16229
16230 /* destroy the backlight and sysfs files before encoders/connectors */
16231 for_each_intel_connector(dev, connector)
16232 connector->unregister(connector);
16233
16234 drm_mode_config_cleanup(dev);
16235
16236 intel_cleanup_overlay(dev);
16237
16238 intel_cleanup_gt_powersave(dev);
16239
16240 intel_teardown_gmbus(dev);
16241 }
16242
16243 /*
16244 * Return which encoder is currently attached for connector.
16245 */
16246 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16247 {
16248 return &intel_attached_encoder(connector)->base;
16249 }
16250
16251 void intel_connector_attach_encoder(struct intel_connector *connector,
16252 struct intel_encoder *encoder)
16253 {
16254 connector->encoder = encoder;
16255 drm_mode_connector_attach_encoder(&connector->base,
16256 &encoder->base);
16257 }
16258
16259 /*
16260 * set vga decode state - true == enable VGA decode
16261 */
16262 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16263 {
16264 struct drm_i915_private *dev_priv = dev->dev_private;
16265 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16266 u16 gmch_ctrl;
16267
16268 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16269 DRM_ERROR("failed to read control word\n");
16270 return -EIO;
16271 }
16272
16273 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16274 return 0;
16275
16276 if (state)
16277 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16278 else
16279 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16280
16281 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16282 DRM_ERROR("failed to write control word\n");
16283 return -EIO;
16284 }
16285
16286 return 0;
16287 }
16288
16289 struct intel_display_error_state {
16290
16291 u32 power_well_driver;
16292
16293 int num_transcoders;
16294
16295 struct intel_cursor_error_state {
16296 u32 control;
16297 u32 position;
16298 u32 base;
16299 u32 size;
16300 } cursor[I915_MAX_PIPES];
16301
16302 struct intel_pipe_error_state {
16303 bool power_domain_on;
16304 u32 source;
16305 u32 stat;
16306 } pipe[I915_MAX_PIPES];
16307
16308 struct intel_plane_error_state {
16309 u32 control;
16310 u32 stride;
16311 u32 size;
16312 u32 pos;
16313 u32 addr;
16314 u32 surface;
16315 u32 tile_offset;
16316 } plane[I915_MAX_PIPES];
16317
16318 struct intel_transcoder_error_state {
16319 bool power_domain_on;
16320 enum transcoder cpu_transcoder;
16321
16322 u32 conf;
16323
16324 u32 htotal;
16325 u32 hblank;
16326 u32 hsync;
16327 u32 vtotal;
16328 u32 vblank;
16329 u32 vsync;
16330 } transcoder[4];
16331 };
16332
16333 struct intel_display_error_state *
16334 intel_display_capture_error_state(struct drm_device *dev)
16335 {
16336 struct drm_i915_private *dev_priv = dev->dev_private;
16337 struct intel_display_error_state *error;
16338 int transcoders[] = {
16339 TRANSCODER_A,
16340 TRANSCODER_B,
16341 TRANSCODER_C,
16342 TRANSCODER_EDP,
16343 };
16344 int i;
16345
16346 if (INTEL_INFO(dev)->num_pipes == 0)
16347 return NULL;
16348
16349 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16350 if (error == NULL)
16351 return NULL;
16352
16353 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16354 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16355
16356 for_each_pipe(dev_priv, i) {
16357 error->pipe[i].power_domain_on =
16358 __intel_display_power_is_enabled(dev_priv,
16359 POWER_DOMAIN_PIPE(i));
16360 if (!error->pipe[i].power_domain_on)
16361 continue;
16362
16363 error->cursor[i].control = I915_READ(CURCNTR(i));
16364 error->cursor[i].position = I915_READ(CURPOS(i));
16365 error->cursor[i].base = I915_READ(CURBASE(i));
16366
16367 error->plane[i].control = I915_READ(DSPCNTR(i));
16368 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16369 if (INTEL_INFO(dev)->gen <= 3) {
16370 error->plane[i].size = I915_READ(DSPSIZE(i));
16371 error->plane[i].pos = I915_READ(DSPPOS(i));
16372 }
16373 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16374 error->plane[i].addr = I915_READ(DSPADDR(i));
16375 if (INTEL_INFO(dev)->gen >= 4) {
16376 error->plane[i].surface = I915_READ(DSPSURF(i));
16377 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16378 }
16379
16380 error->pipe[i].source = I915_READ(PIPESRC(i));
16381
16382 if (HAS_GMCH_DISPLAY(dev))
16383 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16384 }
16385
16386 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16387 if (HAS_DDI(dev_priv->dev))
16388 error->num_transcoders++; /* Account for eDP. */
16389
16390 for (i = 0; i < error->num_transcoders; i++) {
16391 enum transcoder cpu_transcoder = transcoders[i];
16392
16393 error->transcoder[i].power_domain_on =
16394 __intel_display_power_is_enabled(dev_priv,
16395 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16396 if (!error->transcoder[i].power_domain_on)
16397 continue;
16398
16399 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16400
16401 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16402 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16403 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16404 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16405 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16406 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16407 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16408 }
16409
16410 return error;
16411 }
16412
16413 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16414
16415 void
16416 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16417 struct drm_device *dev,
16418 struct intel_display_error_state *error)
16419 {
16420 struct drm_i915_private *dev_priv = dev->dev_private;
16421 int i;
16422
16423 if (!error)
16424 return;
16425
16426 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16427 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16428 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16429 error->power_well_driver);
16430 for_each_pipe(dev_priv, i) {
16431 err_printf(m, "Pipe [%d]:\n", i);
16432 err_printf(m, " Power: %s\n",
16433 onoff(error->pipe[i].power_domain_on));
16434 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16435 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16436
16437 err_printf(m, "Plane [%d]:\n", i);
16438 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16439 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16440 if (INTEL_INFO(dev)->gen <= 3) {
16441 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16442 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16443 }
16444 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16445 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16446 if (INTEL_INFO(dev)->gen >= 4) {
16447 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16448 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16449 }
16450
16451 err_printf(m, "Cursor [%d]:\n", i);
16452 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16453 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16454 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16455 }
16456
16457 for (i = 0; i < error->num_transcoders; i++) {
16458 err_printf(m, "CPU transcoder: %c\n",
16459 transcoder_name(error->transcoder[i].cpu_transcoder));
16460 err_printf(m, " Power: %s\n",
16461 onoff(error->transcoder[i].power_domain_on));
16462 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16463 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16464 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16465 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16466 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16467 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16468 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16469 }
16470 }
Linux kernel - Deliverables
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