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drm/i915: Use ilk_max_pixel_rate() for BXT cdclk calculation
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
50
51 /* Primary plane formats for gen <= 3 */
52 static const uint32_t i8xx_primary_formats[] = {
53 DRM_FORMAT_C8,
54 DRM_FORMAT_RGB565,
55 DRM_FORMAT_XRGB1555,
56 DRM_FORMAT_XRGB8888,
57 };
58
59 /* Primary plane formats for gen >= 4 */
60 static const uint32_t i965_primary_formats[] = {
61 DRM_FORMAT_C8,
62 DRM_FORMAT_RGB565,
63 DRM_FORMAT_XRGB8888,
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_XBGR2101010,
67 };
68
69 static const uint32_t skl_primary_formats[] = {
70 DRM_FORMAT_C8,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_XRGB8888,
73 DRM_FORMAT_XBGR8888,
74 DRM_FORMAT_ARGB8888,
75 DRM_FORMAT_ABGR8888,
76 DRM_FORMAT_XRGB2101010,
77 DRM_FORMAT_XBGR2101010,
78 DRM_FORMAT_YUYV,
79 DRM_FORMAT_YVYU,
80 DRM_FORMAT_UYVY,
81 DRM_FORMAT_VYUY,
82 };
83
84 /* Cursor formats */
85 static const uint32_t intel_cursor_formats[] = {
86 DRM_FORMAT_ARGB8888,
87 };
88
89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 struct intel_crtc_state *pipe_config);
91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
92 struct intel_crtc_state *pipe_config);
93
94 static int intel_framebuffer_init(struct drm_device *dev,
95 struct intel_framebuffer *ifb,
96 struct drm_mode_fb_cmd2 *mode_cmd,
97 struct drm_i915_gem_object *obj);
98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114 struct intel_crtc_state *crtc_state);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
120 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
121
122 struct intel_limit {
123 struct {
124 int min, max;
125 } dot, vco, n, m, m1, m2, p, p1;
126
127 struct {
128 int dot_limit;
129 int p2_slow, p2_fast;
130 } p2;
131 };
132
133 /* returns HPLL frequency in kHz */
134 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
135 {
136 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
137
138 /* Obtain SKU information */
139 mutex_lock(&dev_priv->sb_lock);
140 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
141 CCK_FUSE_HPLL_FREQ_MASK;
142 mutex_unlock(&dev_priv->sb_lock);
143
144 return vco_freq[hpll_freq] * 1000;
145 }
146
147 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
148 const char *name, u32 reg, int ref_freq)
149 {
150 u32 val;
151 int divider;
152
153 mutex_lock(&dev_priv->sb_lock);
154 val = vlv_cck_read(dev_priv, reg);
155 mutex_unlock(&dev_priv->sb_lock);
156
157 divider = val & CCK_FREQUENCY_VALUES;
158
159 WARN((val & CCK_FREQUENCY_STATUS) !=
160 (divider << CCK_FREQUENCY_STATUS_SHIFT),
161 "%s change in progress\n", name);
162
163 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
164 }
165
166 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
167 const char *name, u32 reg)
168 {
169 if (dev_priv->hpll_freq == 0)
170 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
171
172 return vlv_get_cck_clock(dev_priv, name, reg,
173 dev_priv->hpll_freq);
174 }
175
176 static int
177 intel_pch_rawclk(struct drm_i915_private *dev_priv)
178 {
179 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
180 }
181
182 static int
183 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
184 {
185 /* RAWCLK_FREQ_VLV register updated from power well code */
186 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
187 CCK_DISPLAY_REF_CLOCK_CONTROL);
188 }
189
190 static int
191 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
192 {
193 uint32_t clkcfg;
194
195 /* hrawclock is 1/4 the FSB frequency */
196 clkcfg = I915_READ(CLKCFG);
197 switch (clkcfg & CLKCFG_FSB_MASK) {
198 case CLKCFG_FSB_400:
199 return 100000;
200 case CLKCFG_FSB_533:
201 return 133333;
202 case CLKCFG_FSB_667:
203 return 166667;
204 case CLKCFG_FSB_800:
205 return 200000;
206 case CLKCFG_FSB_1067:
207 return 266667;
208 case CLKCFG_FSB_1333:
209 return 333333;
210 /* these two are just a guess; one of them might be right */
211 case CLKCFG_FSB_1600:
212 case CLKCFG_FSB_1600_ALT:
213 return 400000;
214 default:
215 return 133333;
216 }
217 }
218
219 void intel_update_rawclk(struct drm_i915_private *dev_priv)
220 {
221 if (HAS_PCH_SPLIT(dev_priv))
222 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
223 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
224 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
225 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
226 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
227 else
228 return; /* no rawclk on other platforms, or no need to know it */
229
230 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
231 }
232
233 static void intel_update_czclk(struct drm_i915_private *dev_priv)
234 {
235 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
236 return;
237
238 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
239 CCK_CZ_CLOCK_CONTROL);
240
241 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
242 }
243
244 static inline u32 /* units of 100MHz */
245 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
246 const struct intel_crtc_state *pipe_config)
247 {
248 if (HAS_DDI(dev_priv))
249 return pipe_config->port_clock; /* SPLL */
250 else if (IS_GEN5(dev_priv))
251 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
252 else
253 return 270000;
254 }
255
256 static const struct intel_limit intel_limits_i8xx_dac = {
257 .dot = { .min = 25000, .max = 350000 },
258 .vco = { .min = 908000, .max = 1512000 },
259 .n = { .min = 2, .max = 16 },
260 .m = { .min = 96, .max = 140 },
261 .m1 = { .min = 18, .max = 26 },
262 .m2 = { .min = 6, .max = 16 },
263 .p = { .min = 4, .max = 128 },
264 .p1 = { .min = 2, .max = 33 },
265 .p2 = { .dot_limit = 165000,
266 .p2_slow = 4, .p2_fast = 2 },
267 };
268
269 static const struct intel_limit intel_limits_i8xx_dvo = {
270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 908000, .max = 1512000 },
272 .n = { .min = 2, .max = 16 },
273 .m = { .min = 96, .max = 140 },
274 .m1 = { .min = 18, .max = 26 },
275 .m2 = { .min = 6, .max = 16 },
276 .p = { .min = 4, .max = 128 },
277 .p1 = { .min = 2, .max = 33 },
278 .p2 = { .dot_limit = 165000,
279 .p2_slow = 4, .p2_fast = 4 },
280 };
281
282 static const struct intel_limit intel_limits_i8xx_lvds = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 908000, .max = 1512000 },
285 .n = { .min = 2, .max = 16 },
286 .m = { .min = 96, .max = 140 },
287 .m1 = { .min = 18, .max = 26 },
288 .m2 = { .min = 6, .max = 16 },
289 .p = { .min = 4, .max = 128 },
290 .p1 = { .min = 1, .max = 6 },
291 .p2 = { .dot_limit = 165000,
292 .p2_slow = 14, .p2_fast = 7 },
293 };
294
295 static const struct intel_limit intel_limits_i9xx_sdvo = {
296 .dot = { .min = 20000, .max = 400000 },
297 .vco = { .min = 1400000, .max = 2800000 },
298 .n = { .min = 1, .max = 6 },
299 .m = { .min = 70, .max = 120 },
300 .m1 = { .min = 8, .max = 18 },
301 .m2 = { .min = 3, .max = 7 },
302 .p = { .min = 5, .max = 80 },
303 .p1 = { .min = 1, .max = 8 },
304 .p2 = { .dot_limit = 200000,
305 .p2_slow = 10, .p2_fast = 5 },
306 };
307
308 static const struct intel_limit intel_limits_i9xx_lvds = {
309 .dot = { .min = 20000, .max = 400000 },
310 .vco = { .min = 1400000, .max = 2800000 },
311 .n = { .min = 1, .max = 6 },
312 .m = { .min = 70, .max = 120 },
313 .m1 = { .min = 8, .max = 18 },
314 .m2 = { .min = 3, .max = 7 },
315 .p = { .min = 7, .max = 98 },
316 .p1 = { .min = 1, .max = 8 },
317 .p2 = { .dot_limit = 112000,
318 .p2_slow = 14, .p2_fast = 7 },
319 };
320
321
322 static const struct intel_limit intel_limits_g4x_sdvo = {
323 .dot = { .min = 25000, .max = 270000 },
324 .vco = { .min = 1750000, .max = 3500000},
325 .n = { .min = 1, .max = 4 },
326 .m = { .min = 104, .max = 138 },
327 .m1 = { .min = 17, .max = 23 },
328 .m2 = { .min = 5, .max = 11 },
329 .p = { .min = 10, .max = 30 },
330 .p1 = { .min = 1, .max = 3},
331 .p2 = { .dot_limit = 270000,
332 .p2_slow = 10,
333 .p2_fast = 10
334 },
335 };
336
337 static const struct intel_limit intel_limits_g4x_hdmi = {
338 .dot = { .min = 22000, .max = 400000 },
339 .vco = { .min = 1750000, .max = 3500000},
340 .n = { .min = 1, .max = 4 },
341 .m = { .min = 104, .max = 138 },
342 .m1 = { .min = 16, .max = 23 },
343 .m2 = { .min = 5, .max = 11 },
344 .p = { .min = 5, .max = 80 },
345 .p1 = { .min = 1, .max = 8},
346 .p2 = { .dot_limit = 165000,
347 .p2_slow = 10, .p2_fast = 5 },
348 };
349
350 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
351 .dot = { .min = 20000, .max = 115000 },
352 .vco = { .min = 1750000, .max = 3500000 },
353 .n = { .min = 1, .max = 3 },
354 .m = { .min = 104, .max = 138 },
355 .m1 = { .min = 17, .max = 23 },
356 .m2 = { .min = 5, .max = 11 },
357 .p = { .min = 28, .max = 112 },
358 .p1 = { .min = 2, .max = 8 },
359 .p2 = { .dot_limit = 0,
360 .p2_slow = 14, .p2_fast = 14
361 },
362 };
363
364 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
365 .dot = { .min = 80000, .max = 224000 },
366 .vco = { .min = 1750000, .max = 3500000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 104, .max = 138 },
369 .m1 = { .min = 17, .max = 23 },
370 .m2 = { .min = 5, .max = 11 },
371 .p = { .min = 14, .max = 42 },
372 .p1 = { .min = 2, .max = 6 },
373 .p2 = { .dot_limit = 0,
374 .p2_slow = 7, .p2_fast = 7
375 },
376 };
377
378 static const struct intel_limit intel_limits_pineview_sdvo = {
379 .dot = { .min = 20000, .max = 400000},
380 .vco = { .min = 1700000, .max = 3500000 },
381 /* Pineview's Ncounter is a ring counter */
382 .n = { .min = 3, .max = 6 },
383 .m = { .min = 2, .max = 256 },
384 /* Pineview only has one combined m divider, which we treat as m2. */
385 .m1 = { .min = 0, .max = 0 },
386 .m2 = { .min = 0, .max = 254 },
387 .p = { .min = 5, .max = 80 },
388 .p1 = { .min = 1, .max = 8 },
389 .p2 = { .dot_limit = 200000,
390 .p2_slow = 10, .p2_fast = 5 },
391 };
392
393 static const struct intel_limit intel_limits_pineview_lvds = {
394 .dot = { .min = 20000, .max = 400000 },
395 .vco = { .min = 1700000, .max = 3500000 },
396 .n = { .min = 3, .max = 6 },
397 .m = { .min = 2, .max = 256 },
398 .m1 = { .min = 0, .max = 0 },
399 .m2 = { .min = 0, .max = 254 },
400 .p = { .min = 7, .max = 112 },
401 .p1 = { .min = 1, .max = 8 },
402 .p2 = { .dot_limit = 112000,
403 .p2_slow = 14, .p2_fast = 14 },
404 };
405
406 /* Ironlake / Sandybridge
407 *
408 * We calculate clock using (register_value + 2) for N/M1/M2, so here
409 * the range value for them is (actual_value - 2).
410 */
411 static const struct intel_limit intel_limits_ironlake_dac = {
412 .dot = { .min = 25000, .max = 350000 },
413 .vco = { .min = 1760000, .max = 3510000 },
414 .n = { .min = 1, .max = 5 },
415 .m = { .min = 79, .max = 127 },
416 .m1 = { .min = 12, .max = 22 },
417 .m2 = { .min = 5, .max = 9 },
418 .p = { .min = 5, .max = 80 },
419 .p1 = { .min = 1, .max = 8 },
420 .p2 = { .dot_limit = 225000,
421 .p2_slow = 10, .p2_fast = 5 },
422 };
423
424 static const struct intel_limit intel_limits_ironlake_single_lvds = {
425 .dot = { .min = 25000, .max = 350000 },
426 .vco = { .min = 1760000, .max = 3510000 },
427 .n = { .min = 1, .max = 3 },
428 .m = { .min = 79, .max = 118 },
429 .m1 = { .min = 12, .max = 22 },
430 .m2 = { .min = 5, .max = 9 },
431 .p = { .min = 28, .max = 112 },
432 .p1 = { .min = 2, .max = 8 },
433 .p2 = { .dot_limit = 225000,
434 .p2_slow = 14, .p2_fast = 14 },
435 };
436
437 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
438 .dot = { .min = 25000, .max = 350000 },
439 .vco = { .min = 1760000, .max = 3510000 },
440 .n = { .min = 1, .max = 3 },
441 .m = { .min = 79, .max = 127 },
442 .m1 = { .min = 12, .max = 22 },
443 .m2 = { .min = 5, .max = 9 },
444 .p = { .min = 14, .max = 56 },
445 .p1 = { .min = 2, .max = 8 },
446 .p2 = { .dot_limit = 225000,
447 .p2_slow = 7, .p2_fast = 7 },
448 };
449
450 /* LVDS 100mhz refclk limits. */
451 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
452 .dot = { .min = 25000, .max = 350000 },
453 .vco = { .min = 1760000, .max = 3510000 },
454 .n = { .min = 1, .max = 2 },
455 .m = { .min = 79, .max = 126 },
456 .m1 = { .min = 12, .max = 22 },
457 .m2 = { .min = 5, .max = 9 },
458 .p = { .min = 28, .max = 112 },
459 .p1 = { .min = 2, .max = 8 },
460 .p2 = { .dot_limit = 225000,
461 .p2_slow = 14, .p2_fast = 14 },
462 };
463
464 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
465 .dot = { .min = 25000, .max = 350000 },
466 .vco = { .min = 1760000, .max = 3510000 },
467 .n = { .min = 1, .max = 3 },
468 .m = { .min = 79, .max = 126 },
469 .m1 = { .min = 12, .max = 22 },
470 .m2 = { .min = 5, .max = 9 },
471 .p = { .min = 14, .max = 42 },
472 .p1 = { .min = 2, .max = 6 },
473 .p2 = { .dot_limit = 225000,
474 .p2_slow = 7, .p2_fast = 7 },
475 };
476
477 static const struct intel_limit intel_limits_vlv = {
478 /*
479 * These are the data rate limits (measured in fast clocks)
480 * since those are the strictest limits we have. The fast
481 * clock and actual rate limits are more relaxed, so checking
482 * them would make no difference.
483 */
484 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
485 .vco = { .min = 4000000, .max = 6000000 },
486 .n = { .min = 1, .max = 7 },
487 .m1 = { .min = 2, .max = 3 },
488 .m2 = { .min = 11, .max = 156 },
489 .p1 = { .min = 2, .max = 3 },
490 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
491 };
492
493 static const struct intel_limit intel_limits_chv = {
494 /*
495 * These are the data rate limits (measured in fast clocks)
496 * since those are the strictest limits we have. The fast
497 * clock and actual rate limits are more relaxed, so checking
498 * them would make no difference.
499 */
500 .dot = { .min = 25000 * 5, .max = 540000 * 5},
501 .vco = { .min = 4800000, .max = 6480000 },
502 .n = { .min = 1, .max = 1 },
503 .m1 = { .min = 2, .max = 2 },
504 .m2 = { .min = 24 << 22, .max = 175 << 22 },
505 .p1 = { .min = 2, .max = 4 },
506 .p2 = { .p2_slow = 1, .p2_fast = 14 },
507 };
508
509 static const struct intel_limit intel_limits_bxt = {
510 /* FIXME: find real dot limits */
511 .dot = { .min = 0, .max = INT_MAX },
512 .vco = { .min = 4800000, .max = 6700000 },
513 .n = { .min = 1, .max = 1 },
514 .m1 = { .min = 2, .max = 2 },
515 /* FIXME: find real m2 limits */
516 .m2 = { .min = 2 << 22, .max = 255 << 22 },
517 .p1 = { .min = 2, .max = 4 },
518 .p2 = { .p2_slow = 1, .p2_fast = 20 },
519 };
520
521 static bool
522 needs_modeset(struct drm_crtc_state *state)
523 {
524 return drm_atomic_crtc_needs_modeset(state);
525 }
526
527 /**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
530 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
531 {
532 struct drm_device *dev = crtc->base.dev;
533 struct intel_encoder *encoder;
534
535 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
536 if (encoder->type == type)
537 return true;
538
539 return false;
540 }
541
542 /**
543 * Returns whether any output on the specified pipe will have the specified
544 * type after a staged modeset is complete, i.e., the same as
545 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
546 * encoder->crtc.
547 */
548 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
549 int type)
550 {
551 struct drm_atomic_state *state = crtc_state->base.state;
552 struct drm_connector *connector;
553 struct drm_connector_state *connector_state;
554 struct intel_encoder *encoder;
555 int i, num_connectors = 0;
556
557 for_each_connector_in_state(state, connector, connector_state, i) {
558 if (connector_state->crtc != crtc_state->base.crtc)
559 continue;
560
561 num_connectors++;
562
563 encoder = to_intel_encoder(connector_state->best_encoder);
564 if (encoder->type == type)
565 return true;
566 }
567
568 WARN_ON(num_connectors == 0);
569
570 return false;
571 }
572
573 /*
574 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
575 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
576 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
577 * The helpers' return value is the rate of the clock that is fed to the
578 * display engine's pipe which can be the above fast dot clock rate or a
579 * divided-down version of it.
580 */
581 /* m1 is reserved as 0 in Pineview, n is a ring counter */
582 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
583 {
584 clock->m = clock->m2 + 2;
585 clock->p = clock->p1 * clock->p2;
586 if (WARN_ON(clock->n == 0 || clock->p == 0))
587 return 0;
588 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
589 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
590
591 return clock->dot;
592 }
593
594 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
595 {
596 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
597 }
598
599 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
600 {
601 clock->m = i9xx_dpll_compute_m(clock);
602 clock->p = clock->p1 * clock->p2;
603 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
604 return 0;
605 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
606 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
607
608 return clock->dot;
609 }
610
611 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
612 {
613 clock->m = clock->m1 * clock->m2;
614 clock->p = clock->p1 * clock->p2;
615 if (WARN_ON(clock->n == 0 || clock->p == 0))
616 return 0;
617 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
618 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
619
620 return clock->dot / 5;
621 }
622
623 int chv_calc_dpll_params(int refclk, struct dpll *clock)
624 {
625 clock->m = clock->m1 * clock->m2;
626 clock->p = clock->p1 * clock->p2;
627 if (WARN_ON(clock->n == 0 || clock->p == 0))
628 return 0;
629 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
630 clock->n << 22);
631 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
632
633 return clock->dot / 5;
634 }
635
636 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
637 /**
638 * Returns whether the given set of divisors are valid for a given refclk with
639 * the given connectors.
640 */
641
642 static bool intel_PLL_is_valid(struct drm_device *dev,
643 const struct intel_limit *limit,
644 const struct dpll *clock)
645 {
646 if (clock->n < limit->n.min || limit->n.max < clock->n)
647 INTELPllInvalid("n out of range\n");
648 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
649 INTELPllInvalid("p1 out of range\n");
650 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
651 INTELPllInvalid("m2 out of range\n");
652 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
653 INTELPllInvalid("m1 out of range\n");
654
655 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
656 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
657 if (clock->m1 <= clock->m2)
658 INTELPllInvalid("m1 <= m2\n");
659
660 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
661 if (clock->p < limit->p.min || limit->p.max < clock->p)
662 INTELPllInvalid("p out of range\n");
663 if (clock->m < limit->m.min || limit->m.max < clock->m)
664 INTELPllInvalid("m out of range\n");
665 }
666
667 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
668 INTELPllInvalid("vco out of range\n");
669 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
670 * connector, etc., rather than just a single range.
671 */
672 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
673 INTELPllInvalid("dot out of range\n");
674
675 return true;
676 }
677
678 static int
679 i9xx_select_p2_div(const struct intel_limit *limit,
680 const struct intel_crtc_state *crtc_state,
681 int target)
682 {
683 struct drm_device *dev = crtc_state->base.crtc->dev;
684
685 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
686 /*
687 * For LVDS just rely on its current settings for dual-channel.
688 * We haven't figured out how to reliably set up different
689 * single/dual channel state, if we even can.
690 */
691 if (intel_is_dual_link_lvds(dev))
692 return limit->p2.p2_fast;
693 else
694 return limit->p2.p2_slow;
695 } else {
696 if (target < limit->p2.dot_limit)
697 return limit->p2.p2_slow;
698 else
699 return limit->p2.p2_fast;
700 }
701 }
702
703 /*
704 * Returns a set of divisors for the desired target clock with the given
705 * refclk, or FALSE. The returned values represent the clock equation:
706 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
707 *
708 * Target and reference clocks are specified in kHz.
709 *
710 * If match_clock is provided, then best_clock P divider must match the P
711 * divider from @match_clock used for LVDS downclocking.
712 */
713 static bool
714 i9xx_find_best_dpll(const struct intel_limit *limit,
715 struct intel_crtc_state *crtc_state,
716 int target, int refclk, struct dpll *match_clock,
717 struct dpll *best_clock)
718 {
719 struct drm_device *dev = crtc_state->base.crtc->dev;
720 struct dpll clock;
721 int err = target;
722
723 memset(best_clock, 0, sizeof(*best_clock));
724
725 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
726
727 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
728 clock.m1++) {
729 for (clock.m2 = limit->m2.min;
730 clock.m2 <= limit->m2.max; clock.m2++) {
731 if (clock.m2 >= clock.m1)
732 break;
733 for (clock.n = limit->n.min;
734 clock.n <= limit->n.max; clock.n++) {
735 for (clock.p1 = limit->p1.min;
736 clock.p1 <= limit->p1.max; clock.p1++) {
737 int this_err;
738
739 i9xx_calc_dpll_params(refclk, &clock);
740 if (!intel_PLL_is_valid(dev, limit,
741 &clock))
742 continue;
743 if (match_clock &&
744 clock.p != match_clock->p)
745 continue;
746
747 this_err = abs(clock.dot - target);
748 if (this_err < err) {
749 *best_clock = clock;
750 err = this_err;
751 }
752 }
753 }
754 }
755 }
756
757 return (err != target);
758 }
759
760 /*
761 * Returns a set of divisors for the desired target clock with the given
762 * refclk, or FALSE. The returned values represent the clock equation:
763 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
764 *
765 * Target and reference clocks are specified in kHz.
766 *
767 * If match_clock is provided, then best_clock P divider must match the P
768 * divider from @match_clock used for LVDS downclocking.
769 */
770 static bool
771 pnv_find_best_dpll(const struct intel_limit *limit,
772 struct intel_crtc_state *crtc_state,
773 int target, int refclk, struct dpll *match_clock,
774 struct dpll *best_clock)
775 {
776 struct drm_device *dev = crtc_state->base.crtc->dev;
777 struct dpll clock;
778 int err = target;
779
780 memset(best_clock, 0, sizeof(*best_clock));
781
782 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
783
784 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
785 clock.m1++) {
786 for (clock.m2 = limit->m2.min;
787 clock.m2 <= limit->m2.max; clock.m2++) {
788 for (clock.n = limit->n.min;
789 clock.n <= limit->n.max; clock.n++) {
790 for (clock.p1 = limit->p1.min;
791 clock.p1 <= limit->p1.max; clock.p1++) {
792 int this_err;
793
794 pnv_calc_dpll_params(refclk, &clock);
795 if (!intel_PLL_is_valid(dev, limit,
796 &clock))
797 continue;
798 if (match_clock &&
799 clock.p != match_clock->p)
800 continue;
801
802 this_err = abs(clock.dot - target);
803 if (this_err < err) {
804 *best_clock = clock;
805 err = this_err;
806 }
807 }
808 }
809 }
810 }
811
812 return (err != target);
813 }
814
815 /*
816 * Returns a set of divisors for the desired target clock with the given
817 * refclk, or FALSE. The returned values represent the clock equation:
818 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
819 *
820 * Target and reference clocks are specified in kHz.
821 *
822 * If match_clock is provided, then best_clock P divider must match the P
823 * divider from @match_clock used for LVDS downclocking.
824 */
825 static bool
826 g4x_find_best_dpll(const struct intel_limit *limit,
827 struct intel_crtc_state *crtc_state,
828 int target, int refclk, struct dpll *match_clock,
829 struct dpll *best_clock)
830 {
831 struct drm_device *dev = crtc_state->base.crtc->dev;
832 struct dpll clock;
833 int max_n;
834 bool found = false;
835 /* approximately equals target * 0.00585 */
836 int err_most = (target >> 8) + (target >> 9);
837
838 memset(best_clock, 0, sizeof(*best_clock));
839
840 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
841
842 max_n = limit->n.max;
843 /* based on hardware requirement, prefer smaller n to precision */
844 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
845 /* based on hardware requirement, prefere larger m1,m2 */
846 for (clock.m1 = limit->m1.max;
847 clock.m1 >= limit->m1.min; clock.m1--) {
848 for (clock.m2 = limit->m2.max;
849 clock.m2 >= limit->m2.min; clock.m2--) {
850 for (clock.p1 = limit->p1.max;
851 clock.p1 >= limit->p1.min; clock.p1--) {
852 int this_err;
853
854 i9xx_calc_dpll_params(refclk, &clock);
855 if (!intel_PLL_is_valid(dev, limit,
856 &clock))
857 continue;
858
859 this_err = abs(clock.dot - target);
860 if (this_err < err_most) {
861 *best_clock = clock;
862 err_most = this_err;
863 max_n = clock.n;
864 found = true;
865 }
866 }
867 }
868 }
869 }
870 return found;
871 }
872
873 /*
874 * Check if the calculated PLL configuration is more optimal compared to the
875 * best configuration and error found so far. Return the calculated error.
876 */
877 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
878 const struct dpll *calculated_clock,
879 const struct dpll *best_clock,
880 unsigned int best_error_ppm,
881 unsigned int *error_ppm)
882 {
883 /*
884 * For CHV ignore the error and consider only the P value.
885 * Prefer a bigger P value based on HW requirements.
886 */
887 if (IS_CHERRYVIEW(dev)) {
888 *error_ppm = 0;
889
890 return calculated_clock->p > best_clock->p;
891 }
892
893 if (WARN_ON_ONCE(!target_freq))
894 return false;
895
896 *error_ppm = div_u64(1000000ULL *
897 abs(target_freq - calculated_clock->dot),
898 target_freq);
899 /*
900 * Prefer a better P value over a better (smaller) error if the error
901 * is small. Ensure this preference for future configurations too by
902 * setting the error to 0.
903 */
904 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
905 *error_ppm = 0;
906
907 return true;
908 }
909
910 return *error_ppm + 10 < best_error_ppm;
911 }
912
913 /*
914 * Returns a set of divisors for the desired target clock with the given
915 * refclk, or FALSE. The returned values represent the clock equation:
916 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
917 */
918 static bool
919 vlv_find_best_dpll(const struct intel_limit *limit,
920 struct intel_crtc_state *crtc_state,
921 int target, int refclk, struct dpll *match_clock,
922 struct dpll *best_clock)
923 {
924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
925 struct drm_device *dev = crtc->base.dev;
926 struct dpll clock;
927 unsigned int bestppm = 1000000;
928 /* min update 19.2 MHz */
929 int max_n = min(limit->n.max, refclk / 19200);
930 bool found = false;
931
932 target *= 5; /* fast clock */
933
934 memset(best_clock, 0, sizeof(*best_clock));
935
936 /* based on hardware requirement, prefer smaller n to precision */
937 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
938 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
939 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
940 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
941 clock.p = clock.p1 * clock.p2;
942 /* based on hardware requirement, prefer bigger m1,m2 values */
943 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
944 unsigned int ppm;
945
946 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
947 refclk * clock.m1);
948
949 vlv_calc_dpll_params(refclk, &clock);
950
951 if (!intel_PLL_is_valid(dev, limit,
952 &clock))
953 continue;
954
955 if (!vlv_PLL_is_optimal(dev, target,
956 &clock,
957 best_clock,
958 bestppm, &ppm))
959 continue;
960
961 *best_clock = clock;
962 bestppm = ppm;
963 found = true;
964 }
965 }
966 }
967 }
968
969 return found;
970 }
971
972 /*
973 * Returns a set of divisors for the desired target clock with the given
974 * refclk, or FALSE. The returned values represent the clock equation:
975 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
976 */
977 static bool
978 chv_find_best_dpll(const struct intel_limit *limit,
979 struct intel_crtc_state *crtc_state,
980 int target, int refclk, struct dpll *match_clock,
981 struct dpll *best_clock)
982 {
983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
984 struct drm_device *dev = crtc->base.dev;
985 unsigned int best_error_ppm;
986 struct dpll clock;
987 uint64_t m2;
988 int found = false;
989
990 memset(best_clock, 0, sizeof(*best_clock));
991 best_error_ppm = 1000000;
992
993 /*
994 * Based on hardware doc, the n always set to 1, and m1 always
995 * set to 2. If requires to support 200Mhz refclk, we need to
996 * revisit this because n may not 1 anymore.
997 */
998 clock.n = 1, clock.m1 = 2;
999 target *= 5; /* fast clock */
1000
1001 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1002 for (clock.p2 = limit->p2.p2_fast;
1003 clock.p2 >= limit->p2.p2_slow;
1004 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1005 unsigned int error_ppm;
1006
1007 clock.p = clock.p1 * clock.p2;
1008
1009 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1010 clock.n) << 22, refclk * clock.m1);
1011
1012 if (m2 > INT_MAX/clock.m1)
1013 continue;
1014
1015 clock.m2 = m2;
1016
1017 chv_calc_dpll_params(refclk, &clock);
1018
1019 if (!intel_PLL_is_valid(dev, limit, &clock))
1020 continue;
1021
1022 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1023 best_error_ppm, &error_ppm))
1024 continue;
1025
1026 *best_clock = clock;
1027 best_error_ppm = error_ppm;
1028 found = true;
1029 }
1030 }
1031
1032 return found;
1033 }
1034
1035 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1036 struct dpll *best_clock)
1037 {
1038 int refclk = 100000;
1039 const struct intel_limit *limit = &intel_limits_bxt;
1040
1041 return chv_find_best_dpll(limit, crtc_state,
1042 target_clock, refclk, NULL, best_clock);
1043 }
1044
1045 bool intel_crtc_active(struct drm_crtc *crtc)
1046 {
1047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1048
1049 /* Be paranoid as we can arrive here with only partial
1050 * state retrieved from the hardware during setup.
1051 *
1052 * We can ditch the adjusted_mode.crtc_clock check as soon
1053 * as Haswell has gained clock readout/fastboot support.
1054 *
1055 * We can ditch the crtc->primary->fb check as soon as we can
1056 * properly reconstruct framebuffers.
1057 *
1058 * FIXME: The intel_crtc->active here should be switched to
1059 * crtc->state->active once we have proper CRTC states wired up
1060 * for atomic.
1061 */
1062 return intel_crtc->active && crtc->primary->state->fb &&
1063 intel_crtc->config->base.adjusted_mode.crtc_clock;
1064 }
1065
1066 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1067 enum pipe pipe)
1068 {
1069 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071
1072 return intel_crtc->config->cpu_transcoder;
1073 }
1074
1075 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1076 {
1077 struct drm_i915_private *dev_priv = dev->dev_private;
1078 i915_reg_t reg = PIPEDSL(pipe);
1079 u32 line1, line2;
1080 u32 line_mask;
1081
1082 if (IS_GEN2(dev))
1083 line_mask = DSL_LINEMASK_GEN2;
1084 else
1085 line_mask = DSL_LINEMASK_GEN3;
1086
1087 line1 = I915_READ(reg) & line_mask;
1088 msleep(5);
1089 line2 = I915_READ(reg) & line_mask;
1090
1091 return line1 == line2;
1092 }
1093
1094 /*
1095 * intel_wait_for_pipe_off - wait for pipe to turn off
1096 * @crtc: crtc whose pipe to wait for
1097 *
1098 * After disabling a pipe, we can't wait for vblank in the usual way,
1099 * spinning on the vblank interrupt status bit, since we won't actually
1100 * see an interrupt when the pipe is disabled.
1101 *
1102 * On Gen4 and above:
1103 * wait for the pipe register state bit to turn off
1104 *
1105 * Otherwise:
1106 * wait for the display line value to settle (it usually
1107 * ends up stopping at the start of the next frame).
1108 *
1109 */
1110 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1111 {
1112 struct drm_device *dev = crtc->base.dev;
1113 struct drm_i915_private *dev_priv = dev->dev_private;
1114 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1115 enum pipe pipe = crtc->pipe;
1116
1117 if (INTEL_INFO(dev)->gen >= 4) {
1118 i915_reg_t reg = PIPECONF(cpu_transcoder);
1119
1120 /* Wait for the Pipe State to go off */
1121 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1122 100))
1123 WARN(1, "pipe_off wait timed out\n");
1124 } else {
1125 /* Wait for the display line to settle */
1126 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1127 WARN(1, "pipe_off wait timed out\n");
1128 }
1129 }
1130
1131 /* Only for pre-ILK configs */
1132 void assert_pll(struct drm_i915_private *dev_priv,
1133 enum pipe pipe, bool state)
1134 {
1135 u32 val;
1136 bool cur_state;
1137
1138 val = I915_READ(DPLL(pipe));
1139 cur_state = !!(val & DPLL_VCO_ENABLE);
1140 I915_STATE_WARN(cur_state != state,
1141 "PLL state assertion failure (expected %s, current %s)\n",
1142 onoff(state), onoff(cur_state));
1143 }
1144
1145 /* XXX: the dsi pll is shared between MIPI DSI ports */
1146 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1147 {
1148 u32 val;
1149 bool cur_state;
1150
1151 mutex_lock(&dev_priv->sb_lock);
1152 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1153 mutex_unlock(&dev_priv->sb_lock);
1154
1155 cur_state = val & DSI_PLL_VCO_EN;
1156 I915_STATE_WARN(cur_state != state,
1157 "DSI PLL state assertion failure (expected %s, current %s)\n",
1158 onoff(state), onoff(cur_state));
1159 }
1160
1161 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1162 enum pipe pipe, bool state)
1163 {
1164 bool cur_state;
1165 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1166 pipe);
1167
1168 if (HAS_DDI(dev_priv)) {
1169 /* DDI does not have a specific FDI_TX register */
1170 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1171 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1172 } else {
1173 u32 val = I915_READ(FDI_TX_CTL(pipe));
1174 cur_state = !!(val & FDI_TX_ENABLE);
1175 }
1176 I915_STATE_WARN(cur_state != state,
1177 "FDI TX state assertion failure (expected %s, current %s)\n",
1178 onoff(state), onoff(cur_state));
1179 }
1180 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1181 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1182
1183 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1184 enum pipe pipe, bool state)
1185 {
1186 u32 val;
1187 bool cur_state;
1188
1189 val = I915_READ(FDI_RX_CTL(pipe));
1190 cur_state = !!(val & FDI_RX_ENABLE);
1191 I915_STATE_WARN(cur_state != state,
1192 "FDI RX state assertion failure (expected %s, current %s)\n",
1193 onoff(state), onoff(cur_state));
1194 }
1195 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1196 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1197
1198 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1199 enum pipe pipe)
1200 {
1201 u32 val;
1202
1203 /* ILK FDI PLL is always enabled */
1204 if (IS_GEN5(dev_priv))
1205 return;
1206
1207 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1208 if (HAS_DDI(dev_priv))
1209 return;
1210
1211 val = I915_READ(FDI_TX_CTL(pipe));
1212 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1213 }
1214
1215 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1216 enum pipe pipe, bool state)
1217 {
1218 u32 val;
1219 bool cur_state;
1220
1221 val = I915_READ(FDI_RX_CTL(pipe));
1222 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1223 I915_STATE_WARN(cur_state != state,
1224 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1225 onoff(state), onoff(cur_state));
1226 }
1227
1228 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230 {
1231 struct drm_device *dev = dev_priv->dev;
1232 i915_reg_t pp_reg;
1233 u32 val;
1234 enum pipe panel_pipe = PIPE_A;
1235 bool locked = true;
1236
1237 if (WARN_ON(HAS_DDI(dev)))
1238 return;
1239
1240 if (HAS_PCH_SPLIT(dev)) {
1241 u32 port_sel;
1242
1243 pp_reg = PCH_PP_CONTROL;
1244 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1245
1246 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1247 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1248 panel_pipe = PIPE_B;
1249 /* XXX: else fix for eDP */
1250 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1251 /* presumably write lock depends on pipe, not port select */
1252 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1253 panel_pipe = pipe;
1254 } else {
1255 pp_reg = PP_CONTROL;
1256 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1257 panel_pipe = PIPE_B;
1258 }
1259
1260 val = I915_READ(pp_reg);
1261 if (!(val & PANEL_POWER_ON) ||
1262 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1263 locked = false;
1264
1265 I915_STATE_WARN(panel_pipe == pipe && locked,
1266 "panel assertion failure, pipe %c regs locked\n",
1267 pipe_name(pipe));
1268 }
1269
1270 static void assert_cursor(struct drm_i915_private *dev_priv,
1271 enum pipe pipe, bool state)
1272 {
1273 struct drm_device *dev = dev_priv->dev;
1274 bool cur_state;
1275
1276 if (IS_845G(dev) || IS_I865G(dev))
1277 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1278 else
1279 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1280
1281 I915_STATE_WARN(cur_state != state,
1282 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1283 pipe_name(pipe), onoff(state), onoff(cur_state));
1284 }
1285 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1286 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1287
1288 void assert_pipe(struct drm_i915_private *dev_priv,
1289 enum pipe pipe, bool state)
1290 {
1291 bool cur_state;
1292 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1293 pipe);
1294 enum intel_display_power_domain power_domain;
1295
1296 /* if we need the pipe quirk it must be always on */
1297 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1298 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1299 state = true;
1300
1301 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1302 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1303 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1304 cur_state = !!(val & PIPECONF_ENABLE);
1305
1306 intel_display_power_put(dev_priv, power_domain);
1307 } else {
1308 cur_state = false;
1309 }
1310
1311 I915_STATE_WARN(cur_state != state,
1312 "pipe %c assertion failure (expected %s, current %s)\n",
1313 pipe_name(pipe), onoff(state), onoff(cur_state));
1314 }
1315
1316 static void assert_plane(struct drm_i915_private *dev_priv,
1317 enum plane plane, bool state)
1318 {
1319 u32 val;
1320 bool cur_state;
1321
1322 val = I915_READ(DSPCNTR(plane));
1323 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1324 I915_STATE_WARN(cur_state != state,
1325 "plane %c assertion failure (expected %s, current %s)\n",
1326 plane_name(plane), onoff(state), onoff(cur_state));
1327 }
1328
1329 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1330 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1331
1332 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1333 enum pipe pipe)
1334 {
1335 struct drm_device *dev = dev_priv->dev;
1336 int i;
1337
1338 /* Primary planes are fixed to pipes on gen4+ */
1339 if (INTEL_INFO(dev)->gen >= 4) {
1340 u32 val = I915_READ(DSPCNTR(pipe));
1341 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1342 "plane %c assertion failure, should be disabled but not\n",
1343 plane_name(pipe));
1344 return;
1345 }
1346
1347 /* Need to check both planes against the pipe */
1348 for_each_pipe(dev_priv, i) {
1349 u32 val = I915_READ(DSPCNTR(i));
1350 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1351 DISPPLANE_SEL_PIPE_SHIFT;
1352 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1353 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1354 plane_name(i), pipe_name(pipe));
1355 }
1356 }
1357
1358 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1359 enum pipe pipe)
1360 {
1361 struct drm_device *dev = dev_priv->dev;
1362 int sprite;
1363
1364 if (INTEL_INFO(dev)->gen >= 9) {
1365 for_each_sprite(dev_priv, pipe, sprite) {
1366 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1367 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1368 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1369 sprite, pipe_name(pipe));
1370 }
1371 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1372 for_each_sprite(dev_priv, pipe, sprite) {
1373 u32 val = I915_READ(SPCNTR(pipe, sprite));
1374 I915_STATE_WARN(val & SP_ENABLE,
1375 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1376 sprite_name(pipe, sprite), pipe_name(pipe));
1377 }
1378 } else if (INTEL_INFO(dev)->gen >= 7) {
1379 u32 val = I915_READ(SPRCTL(pipe));
1380 I915_STATE_WARN(val & SPRITE_ENABLE,
1381 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1382 plane_name(pipe), pipe_name(pipe));
1383 } else if (INTEL_INFO(dev)->gen >= 5) {
1384 u32 val = I915_READ(DVSCNTR(pipe));
1385 I915_STATE_WARN(val & DVS_ENABLE,
1386 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1387 plane_name(pipe), pipe_name(pipe));
1388 }
1389 }
1390
1391 static void assert_vblank_disabled(struct drm_crtc *crtc)
1392 {
1393 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1394 drm_crtc_vblank_put(crtc);
1395 }
1396
1397 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399 {
1400 u32 val;
1401 bool enabled;
1402
1403 val = I915_READ(PCH_TRANSCONF(pipe));
1404 enabled = !!(val & TRANS_ENABLE);
1405 I915_STATE_WARN(enabled,
1406 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1407 pipe_name(pipe));
1408 }
1409
1410 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1411 enum pipe pipe, u32 port_sel, u32 val)
1412 {
1413 if ((val & DP_PORT_EN) == 0)
1414 return false;
1415
1416 if (HAS_PCH_CPT(dev_priv)) {
1417 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1418 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1419 return false;
1420 } else if (IS_CHERRYVIEW(dev_priv)) {
1421 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1422 return false;
1423 } else {
1424 if ((val & DP_PIPE_MASK) != (pipe << 30))
1425 return false;
1426 }
1427 return true;
1428 }
1429
1430 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1431 enum pipe pipe, u32 val)
1432 {
1433 if ((val & SDVO_ENABLE) == 0)
1434 return false;
1435
1436 if (HAS_PCH_CPT(dev_priv)) {
1437 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1438 return false;
1439 } else if (IS_CHERRYVIEW(dev_priv)) {
1440 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1441 return false;
1442 } else {
1443 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1444 return false;
1445 }
1446 return true;
1447 }
1448
1449 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe, u32 val)
1451 {
1452 if ((val & LVDS_PORT_EN) == 0)
1453 return false;
1454
1455 if (HAS_PCH_CPT(dev_priv)) {
1456 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1457 return false;
1458 } else {
1459 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1460 return false;
1461 }
1462 return true;
1463 }
1464
1465 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1466 enum pipe pipe, u32 val)
1467 {
1468 if ((val & ADPA_DAC_ENABLE) == 0)
1469 return false;
1470 if (HAS_PCH_CPT(dev_priv)) {
1471 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1472 return false;
1473 } else {
1474 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1475 return false;
1476 }
1477 return true;
1478 }
1479
1480 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1481 enum pipe pipe, i915_reg_t reg,
1482 u32 port_sel)
1483 {
1484 u32 val = I915_READ(reg);
1485 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1486 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1487 i915_mmio_reg_offset(reg), pipe_name(pipe));
1488
1489 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1490 && (val & DP_PIPEB_SELECT),
1491 "IBX PCH dp port still using transcoder B\n");
1492 }
1493
1494 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, i915_reg_t reg)
1496 {
1497 u32 val = I915_READ(reg);
1498 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1499 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1500 i915_mmio_reg_offset(reg), pipe_name(pipe));
1501
1502 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1503 && (val & SDVO_PIPE_B_SELECT),
1504 "IBX PCH hdmi port still using transcoder B\n");
1505 }
1506
1507 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1508 enum pipe pipe)
1509 {
1510 u32 val;
1511
1512 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1513 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1515
1516 val = I915_READ(PCH_ADPA);
1517 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1518 "PCH VGA enabled on transcoder %c, should be disabled\n",
1519 pipe_name(pipe));
1520
1521 val = I915_READ(PCH_LVDS);
1522 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1523 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1524 pipe_name(pipe));
1525
1526 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1527 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1528 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1529 }
1530
1531 static void _vlv_enable_pll(struct intel_crtc *crtc,
1532 const struct intel_crtc_state *pipe_config)
1533 {
1534 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1535 enum pipe pipe = crtc->pipe;
1536
1537 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1538 POSTING_READ(DPLL(pipe));
1539 udelay(150);
1540
1541 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1542 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1543 }
1544
1545 static void vlv_enable_pll(struct intel_crtc *crtc,
1546 const struct intel_crtc_state *pipe_config)
1547 {
1548 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1549 enum pipe pipe = crtc->pipe;
1550
1551 assert_pipe_disabled(dev_priv, pipe);
1552
1553 /* PLL is protected by panel, make sure we can write it */
1554 assert_panel_unlocked(dev_priv, pipe);
1555
1556 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1557 _vlv_enable_pll(crtc, pipe_config);
1558
1559 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1560 POSTING_READ(DPLL_MD(pipe));
1561 }
1562
1563
1564 static void _chv_enable_pll(struct intel_crtc *crtc,
1565 const struct intel_crtc_state *pipe_config)
1566 {
1567 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1568 enum pipe pipe = crtc->pipe;
1569 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1570 u32 tmp;
1571
1572 mutex_lock(&dev_priv->sb_lock);
1573
1574 /* Enable back the 10bit clock to display controller */
1575 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1576 tmp |= DPIO_DCLKP_EN;
1577 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1578
1579 mutex_unlock(&dev_priv->sb_lock);
1580
1581 /*
1582 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1583 */
1584 udelay(1);
1585
1586 /* Enable PLL */
1587 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1588
1589 /* Check PLL is locked */
1590 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1591 DRM_ERROR("PLL %d failed to lock\n", pipe);
1592 }
1593
1594 static void chv_enable_pll(struct intel_crtc *crtc,
1595 const struct intel_crtc_state *pipe_config)
1596 {
1597 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1598 enum pipe pipe = crtc->pipe;
1599
1600 assert_pipe_disabled(dev_priv, pipe);
1601
1602 /* PLL is protected by panel, make sure we can write it */
1603 assert_panel_unlocked(dev_priv, pipe);
1604
1605 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1606 _chv_enable_pll(crtc, pipe_config);
1607
1608 if (pipe != PIPE_A) {
1609 /*
1610 * WaPixelRepeatModeFixForC0:chv
1611 *
1612 * DPLLCMD is AWOL. Use chicken bits to propagate
1613 * the value from DPLLBMD to either pipe B or C.
1614 */
1615 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1616 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1617 I915_WRITE(CBR4_VLV, 0);
1618 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1619
1620 /*
1621 * DPLLB VGA mode also seems to cause problems.
1622 * We should always have it disabled.
1623 */
1624 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1625 } else {
1626 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1627 POSTING_READ(DPLL_MD(pipe));
1628 }
1629 }
1630
1631 static int intel_num_dvo_pipes(struct drm_device *dev)
1632 {
1633 struct intel_crtc *crtc;
1634 int count = 0;
1635
1636 for_each_intel_crtc(dev, crtc)
1637 count += crtc->base.state->active &&
1638 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1639
1640 return count;
1641 }
1642
1643 static void i9xx_enable_pll(struct intel_crtc *crtc)
1644 {
1645 struct drm_device *dev = crtc->base.dev;
1646 struct drm_i915_private *dev_priv = dev->dev_private;
1647 i915_reg_t reg = DPLL(crtc->pipe);
1648 u32 dpll = crtc->config->dpll_hw_state.dpll;
1649
1650 assert_pipe_disabled(dev_priv, crtc->pipe);
1651
1652 /* PLL is protected by panel, make sure we can write it */
1653 if (IS_MOBILE(dev) && !IS_I830(dev))
1654 assert_panel_unlocked(dev_priv, crtc->pipe);
1655
1656 /* Enable DVO 2x clock on both PLLs if necessary */
1657 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1658 /*
1659 * It appears to be important that we don't enable this
1660 * for the current pipe before otherwise configuring the
1661 * PLL. No idea how this should be handled if multiple
1662 * DVO outputs are enabled simultaneosly.
1663 */
1664 dpll |= DPLL_DVO_2X_MODE;
1665 I915_WRITE(DPLL(!crtc->pipe),
1666 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1667 }
1668
1669 /*
1670 * Apparently we need to have VGA mode enabled prior to changing
1671 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1672 * dividers, even though the register value does change.
1673 */
1674 I915_WRITE(reg, 0);
1675
1676 I915_WRITE(reg, dpll);
1677
1678 /* Wait for the clocks to stabilize. */
1679 POSTING_READ(reg);
1680 udelay(150);
1681
1682 if (INTEL_INFO(dev)->gen >= 4) {
1683 I915_WRITE(DPLL_MD(crtc->pipe),
1684 crtc->config->dpll_hw_state.dpll_md);
1685 } else {
1686 /* The pixel multiplier can only be updated once the
1687 * DPLL is enabled and the clocks are stable.
1688 *
1689 * So write it again.
1690 */
1691 I915_WRITE(reg, dpll);
1692 }
1693
1694 /* We do this three times for luck */
1695 I915_WRITE(reg, dpll);
1696 POSTING_READ(reg);
1697 udelay(150); /* wait for warmup */
1698 I915_WRITE(reg, dpll);
1699 POSTING_READ(reg);
1700 udelay(150); /* wait for warmup */
1701 I915_WRITE(reg, dpll);
1702 POSTING_READ(reg);
1703 udelay(150); /* wait for warmup */
1704 }
1705
1706 /**
1707 * i9xx_disable_pll - disable a PLL
1708 * @dev_priv: i915 private structure
1709 * @pipe: pipe PLL to disable
1710 *
1711 * Disable the PLL for @pipe, making sure the pipe is off first.
1712 *
1713 * Note! This is for pre-ILK only.
1714 */
1715 static void i9xx_disable_pll(struct intel_crtc *crtc)
1716 {
1717 struct drm_device *dev = crtc->base.dev;
1718 struct drm_i915_private *dev_priv = dev->dev_private;
1719 enum pipe pipe = crtc->pipe;
1720
1721 /* Disable DVO 2x clock on both PLLs if necessary */
1722 if (IS_I830(dev) &&
1723 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1724 !intel_num_dvo_pipes(dev)) {
1725 I915_WRITE(DPLL(PIPE_B),
1726 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1727 I915_WRITE(DPLL(PIPE_A),
1728 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1729 }
1730
1731 /* Don't disable pipe or pipe PLLs if needed */
1732 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1733 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1734 return;
1735
1736 /* Make sure the pipe isn't still relying on us */
1737 assert_pipe_disabled(dev_priv, pipe);
1738
1739 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1740 POSTING_READ(DPLL(pipe));
1741 }
1742
1743 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1744 {
1745 u32 val;
1746
1747 /* Make sure the pipe isn't still relying on us */
1748 assert_pipe_disabled(dev_priv, pipe);
1749
1750 val = DPLL_INTEGRATED_REF_CLK_VLV |
1751 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1752 if (pipe != PIPE_A)
1753 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1754
1755 I915_WRITE(DPLL(pipe), val);
1756 POSTING_READ(DPLL(pipe));
1757 }
1758
1759 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1760 {
1761 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1762 u32 val;
1763
1764 /* Make sure the pipe isn't still relying on us */
1765 assert_pipe_disabled(dev_priv, pipe);
1766
1767 val = DPLL_SSC_REF_CLK_CHV |
1768 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1769 if (pipe != PIPE_A)
1770 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1771
1772 I915_WRITE(DPLL(pipe), val);
1773 POSTING_READ(DPLL(pipe));
1774
1775 mutex_lock(&dev_priv->sb_lock);
1776
1777 /* Disable 10bit clock to display controller */
1778 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1779 val &= ~DPIO_DCLKP_EN;
1780 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1781
1782 mutex_unlock(&dev_priv->sb_lock);
1783 }
1784
1785 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1786 struct intel_digital_port *dport,
1787 unsigned int expected_mask)
1788 {
1789 u32 port_mask;
1790 i915_reg_t dpll_reg;
1791
1792 switch (dport->port) {
1793 case PORT_B:
1794 port_mask = DPLL_PORTB_READY_MASK;
1795 dpll_reg = DPLL(0);
1796 break;
1797 case PORT_C:
1798 port_mask = DPLL_PORTC_READY_MASK;
1799 dpll_reg = DPLL(0);
1800 expected_mask <<= 4;
1801 break;
1802 case PORT_D:
1803 port_mask = DPLL_PORTD_READY_MASK;
1804 dpll_reg = DPIO_PHY_STATUS;
1805 break;
1806 default:
1807 BUG();
1808 }
1809
1810 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1811 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1812 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1813 }
1814
1815 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1816 enum pipe pipe)
1817 {
1818 struct drm_device *dev = dev_priv->dev;
1819 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1821 i915_reg_t reg;
1822 uint32_t val, pipeconf_val;
1823
1824 /* Make sure PCH DPLL is enabled */
1825 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1826
1827 /* FDI must be feeding us bits for PCH ports */
1828 assert_fdi_tx_enabled(dev_priv, pipe);
1829 assert_fdi_rx_enabled(dev_priv, pipe);
1830
1831 if (HAS_PCH_CPT(dev)) {
1832 /* Workaround: Set the timing override bit before enabling the
1833 * pch transcoder. */
1834 reg = TRANS_CHICKEN2(pipe);
1835 val = I915_READ(reg);
1836 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1837 I915_WRITE(reg, val);
1838 }
1839
1840 reg = PCH_TRANSCONF(pipe);
1841 val = I915_READ(reg);
1842 pipeconf_val = I915_READ(PIPECONF(pipe));
1843
1844 if (HAS_PCH_IBX(dev_priv)) {
1845 /*
1846 * Make the BPC in transcoder be consistent with
1847 * that in pipeconf reg. For HDMI we must use 8bpc
1848 * here for both 8bpc and 12bpc.
1849 */
1850 val &= ~PIPECONF_BPC_MASK;
1851 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1852 val |= PIPECONF_8BPC;
1853 else
1854 val |= pipeconf_val & PIPECONF_BPC_MASK;
1855 }
1856
1857 val &= ~TRANS_INTERLACE_MASK;
1858 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1859 if (HAS_PCH_IBX(dev_priv) &&
1860 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1861 val |= TRANS_LEGACY_INTERLACED_ILK;
1862 else
1863 val |= TRANS_INTERLACED;
1864 else
1865 val |= TRANS_PROGRESSIVE;
1866
1867 I915_WRITE(reg, val | TRANS_ENABLE);
1868 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1869 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1870 }
1871
1872 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1873 enum transcoder cpu_transcoder)
1874 {
1875 u32 val, pipeconf_val;
1876
1877 /* FDI must be feeding us bits for PCH ports */
1878 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1879 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1880
1881 /* Workaround: set timing override bit. */
1882 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1883 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1884 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1885
1886 val = TRANS_ENABLE;
1887 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1888
1889 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1890 PIPECONF_INTERLACED_ILK)
1891 val |= TRANS_INTERLACED;
1892 else
1893 val |= TRANS_PROGRESSIVE;
1894
1895 I915_WRITE(LPT_TRANSCONF, val);
1896 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1897 DRM_ERROR("Failed to enable PCH transcoder\n");
1898 }
1899
1900 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1901 enum pipe pipe)
1902 {
1903 struct drm_device *dev = dev_priv->dev;
1904 i915_reg_t reg;
1905 uint32_t val;
1906
1907 /* FDI relies on the transcoder */
1908 assert_fdi_tx_disabled(dev_priv, pipe);
1909 assert_fdi_rx_disabled(dev_priv, pipe);
1910
1911 /* Ports must be off as well */
1912 assert_pch_ports_disabled(dev_priv, pipe);
1913
1914 reg = PCH_TRANSCONF(pipe);
1915 val = I915_READ(reg);
1916 val &= ~TRANS_ENABLE;
1917 I915_WRITE(reg, val);
1918 /* wait for PCH transcoder off, transcoder state */
1919 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1920 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1921
1922 if (HAS_PCH_CPT(dev)) {
1923 /* Workaround: Clear the timing override chicken bit again. */
1924 reg = TRANS_CHICKEN2(pipe);
1925 val = I915_READ(reg);
1926 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1927 I915_WRITE(reg, val);
1928 }
1929 }
1930
1931 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1932 {
1933 u32 val;
1934
1935 val = I915_READ(LPT_TRANSCONF);
1936 val &= ~TRANS_ENABLE;
1937 I915_WRITE(LPT_TRANSCONF, val);
1938 /* wait for PCH transcoder off, transcoder state */
1939 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1940 DRM_ERROR("Failed to disable PCH transcoder\n");
1941
1942 /* Workaround: clear timing override bit. */
1943 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1944 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1945 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1946 }
1947
1948 /**
1949 * intel_enable_pipe - enable a pipe, asserting requirements
1950 * @crtc: crtc responsible for the pipe
1951 *
1952 * Enable @crtc's pipe, making sure that various hardware specific requirements
1953 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1954 */
1955 static void intel_enable_pipe(struct intel_crtc *crtc)
1956 {
1957 struct drm_device *dev = crtc->base.dev;
1958 struct drm_i915_private *dev_priv = dev->dev_private;
1959 enum pipe pipe = crtc->pipe;
1960 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1961 enum pipe pch_transcoder;
1962 i915_reg_t reg;
1963 u32 val;
1964
1965 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1966
1967 assert_planes_disabled(dev_priv, pipe);
1968 assert_cursor_disabled(dev_priv, pipe);
1969 assert_sprites_disabled(dev_priv, pipe);
1970
1971 if (HAS_PCH_LPT(dev_priv))
1972 pch_transcoder = TRANSCODER_A;
1973 else
1974 pch_transcoder = pipe;
1975
1976 /*
1977 * A pipe without a PLL won't actually be able to drive bits from
1978 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1979 * need the check.
1980 */
1981 if (HAS_GMCH_DISPLAY(dev_priv))
1982 if (crtc->config->has_dsi_encoder)
1983 assert_dsi_pll_enabled(dev_priv);
1984 else
1985 assert_pll_enabled(dev_priv, pipe);
1986 else {
1987 if (crtc->config->has_pch_encoder) {
1988 /* if driving the PCH, we need FDI enabled */
1989 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1990 assert_fdi_tx_pll_enabled(dev_priv,
1991 (enum pipe) cpu_transcoder);
1992 }
1993 /* FIXME: assert CPU port conditions for SNB+ */
1994 }
1995
1996 reg = PIPECONF(cpu_transcoder);
1997 val = I915_READ(reg);
1998 if (val & PIPECONF_ENABLE) {
1999 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2000 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2001 return;
2002 }
2003
2004 I915_WRITE(reg, val | PIPECONF_ENABLE);
2005 POSTING_READ(reg);
2006
2007 /*
2008 * Until the pipe starts DSL will read as 0, which would cause
2009 * an apparent vblank timestamp jump, which messes up also the
2010 * frame count when it's derived from the timestamps. So let's
2011 * wait for the pipe to start properly before we call
2012 * drm_crtc_vblank_on()
2013 */
2014 if (dev->max_vblank_count == 0 &&
2015 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2016 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2017 }
2018
2019 /**
2020 * intel_disable_pipe - disable a pipe, asserting requirements
2021 * @crtc: crtc whose pipes is to be disabled
2022 *
2023 * Disable the pipe of @crtc, making sure that various hardware
2024 * specific requirements are met, if applicable, e.g. plane
2025 * disabled, panel fitter off, etc.
2026 *
2027 * Will wait until the pipe has shut down before returning.
2028 */
2029 static void intel_disable_pipe(struct intel_crtc *crtc)
2030 {
2031 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2032 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2033 enum pipe pipe = crtc->pipe;
2034 i915_reg_t reg;
2035 u32 val;
2036
2037 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2038
2039 /*
2040 * Make sure planes won't keep trying to pump pixels to us,
2041 * or we might hang the display.
2042 */
2043 assert_planes_disabled(dev_priv, pipe);
2044 assert_cursor_disabled(dev_priv, pipe);
2045 assert_sprites_disabled(dev_priv, pipe);
2046
2047 reg = PIPECONF(cpu_transcoder);
2048 val = I915_READ(reg);
2049 if ((val & PIPECONF_ENABLE) == 0)
2050 return;
2051
2052 /*
2053 * Double wide has implications for planes
2054 * so best keep it disabled when not needed.
2055 */
2056 if (crtc->config->double_wide)
2057 val &= ~PIPECONF_DOUBLE_WIDE;
2058
2059 /* Don't disable pipe or pipe PLLs if needed */
2060 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2061 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2062 val &= ~PIPECONF_ENABLE;
2063
2064 I915_WRITE(reg, val);
2065 if ((val & PIPECONF_ENABLE) == 0)
2066 intel_wait_for_pipe_off(crtc);
2067 }
2068
2069 static bool need_vtd_wa(struct drm_device *dev)
2070 {
2071 #ifdef CONFIG_INTEL_IOMMU
2072 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2073 return true;
2074 #endif
2075 return false;
2076 }
2077
2078 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2079 {
2080 return IS_GEN2(dev_priv) ? 2048 : 4096;
2081 }
2082
2083 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2084 uint64_t fb_modifier, unsigned int cpp)
2085 {
2086 switch (fb_modifier) {
2087 case DRM_FORMAT_MOD_NONE:
2088 return cpp;
2089 case I915_FORMAT_MOD_X_TILED:
2090 if (IS_GEN2(dev_priv))
2091 return 128;
2092 else
2093 return 512;
2094 case I915_FORMAT_MOD_Y_TILED:
2095 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2096 return 128;
2097 else
2098 return 512;
2099 case I915_FORMAT_MOD_Yf_TILED:
2100 switch (cpp) {
2101 case 1:
2102 return 64;
2103 case 2:
2104 case 4:
2105 return 128;
2106 case 8:
2107 case 16:
2108 return 256;
2109 default:
2110 MISSING_CASE(cpp);
2111 return cpp;
2112 }
2113 break;
2114 default:
2115 MISSING_CASE(fb_modifier);
2116 return cpp;
2117 }
2118 }
2119
2120 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2121 uint64_t fb_modifier, unsigned int cpp)
2122 {
2123 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2124 return 1;
2125 else
2126 return intel_tile_size(dev_priv) /
2127 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2128 }
2129
2130 /* Return the tile dimensions in pixel units */
2131 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2132 unsigned int *tile_width,
2133 unsigned int *tile_height,
2134 uint64_t fb_modifier,
2135 unsigned int cpp)
2136 {
2137 unsigned int tile_width_bytes =
2138 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2139
2140 *tile_width = tile_width_bytes / cpp;
2141 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2142 }
2143
2144 unsigned int
2145 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2146 uint32_t pixel_format, uint64_t fb_modifier)
2147 {
2148 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2149 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2150
2151 return ALIGN(height, tile_height);
2152 }
2153
2154 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2155 {
2156 unsigned int size = 0;
2157 int i;
2158
2159 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2160 size += rot_info->plane[i].width * rot_info->plane[i].height;
2161
2162 return size;
2163 }
2164
2165 static void
2166 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2167 const struct drm_framebuffer *fb,
2168 unsigned int rotation)
2169 {
2170 if (intel_rotation_90_or_270(rotation)) {
2171 *view = i915_ggtt_view_rotated;
2172 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2173 } else {
2174 *view = i915_ggtt_view_normal;
2175 }
2176 }
2177
2178 static void
2179 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2180 struct drm_framebuffer *fb)
2181 {
2182 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2183 unsigned int tile_size, tile_width, tile_height, cpp;
2184
2185 tile_size = intel_tile_size(dev_priv);
2186
2187 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2188 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2189 fb->modifier[0], cpp);
2190
2191 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2192 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2193
2194 if (info->pixel_format == DRM_FORMAT_NV12) {
2195 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2196 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2197 fb->modifier[1], cpp);
2198
2199 info->uv_offset = fb->offsets[1];
2200 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2201 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2202 }
2203 }
2204
2205 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2206 {
2207 if (INTEL_INFO(dev_priv)->gen >= 9)
2208 return 256 * 1024;
2209 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2210 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2211 return 128 * 1024;
2212 else if (INTEL_INFO(dev_priv)->gen >= 4)
2213 return 4 * 1024;
2214 else
2215 return 0;
2216 }
2217
2218 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2219 uint64_t fb_modifier)
2220 {
2221 switch (fb_modifier) {
2222 case DRM_FORMAT_MOD_NONE:
2223 return intel_linear_alignment(dev_priv);
2224 case I915_FORMAT_MOD_X_TILED:
2225 if (INTEL_INFO(dev_priv)->gen >= 9)
2226 return 256 * 1024;
2227 return 0;
2228 case I915_FORMAT_MOD_Y_TILED:
2229 case I915_FORMAT_MOD_Yf_TILED:
2230 return 1 * 1024 * 1024;
2231 default:
2232 MISSING_CASE(fb_modifier);
2233 return 0;
2234 }
2235 }
2236
2237 int
2238 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2239 unsigned int rotation)
2240 {
2241 struct drm_device *dev = fb->dev;
2242 struct drm_i915_private *dev_priv = dev->dev_private;
2243 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2244 struct i915_ggtt_view view;
2245 u32 alignment;
2246 int ret;
2247
2248 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2249
2250 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2251
2252 intel_fill_fb_ggtt_view(&view, fb, rotation);
2253
2254 /* Note that the w/a also requires 64 PTE of padding following the
2255 * bo. We currently fill all unused PTE with the shadow page and so
2256 * we should always have valid PTE following the scanout preventing
2257 * the VT-d warning.
2258 */
2259 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2260 alignment = 256 * 1024;
2261
2262 /*
2263 * Global gtt pte registers are special registers which actually forward
2264 * writes to a chunk of system memory. Which means that there is no risk
2265 * that the register values disappear as soon as we call
2266 * intel_runtime_pm_put(), so it is correct to wrap only the
2267 * pin/unpin/fence and not more.
2268 */
2269 intel_runtime_pm_get(dev_priv);
2270
2271 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2272 &view);
2273 if (ret)
2274 goto err_pm;
2275
2276 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2277 * fence, whereas 965+ only requires a fence if using
2278 * framebuffer compression. For simplicity, we always install
2279 * a fence as the cost is not that onerous.
2280 */
2281 if (view.type == I915_GGTT_VIEW_NORMAL) {
2282 ret = i915_gem_object_get_fence(obj);
2283 if (ret == -EDEADLK) {
2284 /*
2285 * -EDEADLK means there are no free fences
2286 * no pending flips.
2287 *
2288 * This is propagated to atomic, but it uses
2289 * -EDEADLK to force a locking recovery, so
2290 * change the returned error to -EBUSY.
2291 */
2292 ret = -EBUSY;
2293 goto err_unpin;
2294 } else if (ret)
2295 goto err_unpin;
2296
2297 i915_gem_object_pin_fence(obj);
2298 }
2299
2300 intel_runtime_pm_put(dev_priv);
2301 return 0;
2302
2303 err_unpin:
2304 i915_gem_object_unpin_from_display_plane(obj, &view);
2305 err_pm:
2306 intel_runtime_pm_put(dev_priv);
2307 return ret;
2308 }
2309
2310 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2311 {
2312 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2313 struct i915_ggtt_view view;
2314
2315 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2316
2317 intel_fill_fb_ggtt_view(&view, fb, rotation);
2318
2319 if (view.type == I915_GGTT_VIEW_NORMAL)
2320 i915_gem_object_unpin_fence(obj);
2321
2322 i915_gem_object_unpin_from_display_plane(obj, &view);
2323 }
2324
2325 /*
2326 * Adjust the tile offset by moving the difference into
2327 * the x/y offsets.
2328 *
2329 * Input tile dimensions and pitch must already be
2330 * rotated to match x and y, and in pixel units.
2331 */
2332 static u32 intel_adjust_tile_offset(int *x, int *y,
2333 unsigned int tile_width,
2334 unsigned int tile_height,
2335 unsigned int tile_size,
2336 unsigned int pitch_tiles,
2337 u32 old_offset,
2338 u32 new_offset)
2339 {
2340 unsigned int tiles;
2341
2342 WARN_ON(old_offset & (tile_size - 1));
2343 WARN_ON(new_offset & (tile_size - 1));
2344 WARN_ON(new_offset > old_offset);
2345
2346 tiles = (old_offset - new_offset) / tile_size;
2347
2348 *y += tiles / pitch_tiles * tile_height;
2349 *x += tiles % pitch_tiles * tile_width;
2350
2351 return new_offset;
2352 }
2353
2354 /*
2355 * Computes the linear offset to the base tile and adjusts
2356 * x, y. bytes per pixel is assumed to be a power-of-two.
2357 *
2358 * In the 90/270 rotated case, x and y are assumed
2359 * to be already rotated to match the rotated GTT view, and
2360 * pitch is the tile_height aligned framebuffer height.
2361 */
2362 u32 intel_compute_tile_offset(int *x, int *y,
2363 const struct drm_framebuffer *fb, int plane,
2364 unsigned int pitch,
2365 unsigned int rotation)
2366 {
2367 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2368 uint64_t fb_modifier = fb->modifier[plane];
2369 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2370 u32 offset, offset_aligned, alignment;
2371
2372 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2373 if (alignment)
2374 alignment--;
2375
2376 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2377 unsigned int tile_size, tile_width, tile_height;
2378 unsigned int tile_rows, tiles, pitch_tiles;
2379
2380 tile_size = intel_tile_size(dev_priv);
2381 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2382 fb_modifier, cpp);
2383
2384 if (intel_rotation_90_or_270(rotation)) {
2385 pitch_tiles = pitch / tile_height;
2386 swap(tile_width, tile_height);
2387 } else {
2388 pitch_tiles = pitch / (tile_width * cpp);
2389 }
2390
2391 tile_rows = *y / tile_height;
2392 *y %= tile_height;
2393
2394 tiles = *x / tile_width;
2395 *x %= tile_width;
2396
2397 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2398 offset_aligned = offset & ~alignment;
2399
2400 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2401 tile_size, pitch_tiles,
2402 offset, offset_aligned);
2403 } else {
2404 offset = *y * pitch + *x * cpp;
2405 offset_aligned = offset & ~alignment;
2406
2407 *y = (offset & alignment) / pitch;
2408 *x = ((offset & alignment) - *y * pitch) / cpp;
2409 }
2410
2411 return offset_aligned;
2412 }
2413
2414 static int i9xx_format_to_fourcc(int format)
2415 {
2416 switch (format) {
2417 case DISPPLANE_8BPP:
2418 return DRM_FORMAT_C8;
2419 case DISPPLANE_BGRX555:
2420 return DRM_FORMAT_XRGB1555;
2421 case DISPPLANE_BGRX565:
2422 return DRM_FORMAT_RGB565;
2423 default:
2424 case DISPPLANE_BGRX888:
2425 return DRM_FORMAT_XRGB8888;
2426 case DISPPLANE_RGBX888:
2427 return DRM_FORMAT_XBGR8888;
2428 case DISPPLANE_BGRX101010:
2429 return DRM_FORMAT_XRGB2101010;
2430 case DISPPLANE_RGBX101010:
2431 return DRM_FORMAT_XBGR2101010;
2432 }
2433 }
2434
2435 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2436 {
2437 switch (format) {
2438 case PLANE_CTL_FORMAT_RGB_565:
2439 return DRM_FORMAT_RGB565;
2440 default:
2441 case PLANE_CTL_FORMAT_XRGB_8888:
2442 if (rgb_order) {
2443 if (alpha)
2444 return DRM_FORMAT_ABGR8888;
2445 else
2446 return DRM_FORMAT_XBGR8888;
2447 } else {
2448 if (alpha)
2449 return DRM_FORMAT_ARGB8888;
2450 else
2451 return DRM_FORMAT_XRGB8888;
2452 }
2453 case PLANE_CTL_FORMAT_XRGB_2101010:
2454 if (rgb_order)
2455 return DRM_FORMAT_XBGR2101010;
2456 else
2457 return DRM_FORMAT_XRGB2101010;
2458 }
2459 }
2460
2461 static bool
2462 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2463 struct intel_initial_plane_config *plane_config)
2464 {
2465 struct drm_device *dev = crtc->base.dev;
2466 struct drm_i915_private *dev_priv = to_i915(dev);
2467 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2468 struct drm_i915_gem_object *obj = NULL;
2469 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2470 struct drm_framebuffer *fb = &plane_config->fb->base;
2471 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2472 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2473 PAGE_SIZE);
2474
2475 size_aligned -= base_aligned;
2476
2477 if (plane_config->size == 0)
2478 return false;
2479
2480 /* If the FB is too big, just don't use it since fbdev is not very
2481 * important and we should probably use that space with FBC or other
2482 * features. */
2483 if (size_aligned * 2 > ggtt->stolen_usable_size)
2484 return false;
2485
2486 mutex_lock(&dev->struct_mutex);
2487
2488 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2489 base_aligned,
2490 base_aligned,
2491 size_aligned);
2492 if (!obj) {
2493 mutex_unlock(&dev->struct_mutex);
2494 return false;
2495 }
2496
2497 obj->tiling_mode = plane_config->tiling;
2498 if (obj->tiling_mode == I915_TILING_X)
2499 obj->stride = fb->pitches[0];
2500
2501 mode_cmd.pixel_format = fb->pixel_format;
2502 mode_cmd.width = fb->width;
2503 mode_cmd.height = fb->height;
2504 mode_cmd.pitches[0] = fb->pitches[0];
2505 mode_cmd.modifier[0] = fb->modifier[0];
2506 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2507
2508 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2509 &mode_cmd, obj)) {
2510 DRM_DEBUG_KMS("intel fb init failed\n");
2511 goto out_unref_obj;
2512 }
2513
2514 mutex_unlock(&dev->struct_mutex);
2515
2516 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2517 return true;
2518
2519 out_unref_obj:
2520 drm_gem_object_unreference(&obj->base);
2521 mutex_unlock(&dev->struct_mutex);
2522 return false;
2523 }
2524
2525 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2526 static void
2527 update_state_fb(struct drm_plane *plane)
2528 {
2529 if (plane->fb == plane->state->fb)
2530 return;
2531
2532 if (plane->state->fb)
2533 drm_framebuffer_unreference(plane->state->fb);
2534 plane->state->fb = plane->fb;
2535 if (plane->state->fb)
2536 drm_framebuffer_reference(plane->state->fb);
2537 }
2538
2539 static void
2540 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2541 struct intel_initial_plane_config *plane_config)
2542 {
2543 struct drm_device *dev = intel_crtc->base.dev;
2544 struct drm_i915_private *dev_priv = dev->dev_private;
2545 struct drm_crtc *c;
2546 struct intel_crtc *i;
2547 struct drm_i915_gem_object *obj;
2548 struct drm_plane *primary = intel_crtc->base.primary;
2549 struct drm_plane_state *plane_state = primary->state;
2550 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2551 struct intel_plane *intel_plane = to_intel_plane(primary);
2552 struct intel_plane_state *intel_state =
2553 to_intel_plane_state(plane_state);
2554 struct drm_framebuffer *fb;
2555
2556 if (!plane_config->fb)
2557 return;
2558
2559 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2560 fb = &plane_config->fb->base;
2561 goto valid_fb;
2562 }
2563
2564 kfree(plane_config->fb);
2565
2566 /*
2567 * Failed to alloc the obj, check to see if we should share
2568 * an fb with another CRTC instead
2569 */
2570 for_each_crtc(dev, c) {
2571 i = to_intel_crtc(c);
2572
2573 if (c == &intel_crtc->base)
2574 continue;
2575
2576 if (!i->active)
2577 continue;
2578
2579 fb = c->primary->fb;
2580 if (!fb)
2581 continue;
2582
2583 obj = intel_fb_obj(fb);
2584 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2585 drm_framebuffer_reference(fb);
2586 goto valid_fb;
2587 }
2588 }
2589
2590 /*
2591 * We've failed to reconstruct the BIOS FB. Current display state
2592 * indicates that the primary plane is visible, but has a NULL FB,
2593 * which will lead to problems later if we don't fix it up. The
2594 * simplest solution is to just disable the primary plane now and
2595 * pretend the BIOS never had it enabled.
2596 */
2597 to_intel_plane_state(plane_state)->visible = false;
2598 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2599 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2600 intel_plane->disable_plane(primary, &intel_crtc->base);
2601
2602 return;
2603
2604 valid_fb:
2605 plane_state->src_x = 0;
2606 plane_state->src_y = 0;
2607 plane_state->src_w = fb->width << 16;
2608 plane_state->src_h = fb->height << 16;
2609
2610 plane_state->crtc_x = 0;
2611 plane_state->crtc_y = 0;
2612 plane_state->crtc_w = fb->width;
2613 plane_state->crtc_h = fb->height;
2614
2615 intel_state->src.x1 = plane_state->src_x;
2616 intel_state->src.y1 = plane_state->src_y;
2617 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2618 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2619 intel_state->dst.x1 = plane_state->crtc_x;
2620 intel_state->dst.y1 = plane_state->crtc_y;
2621 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2622 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2623
2624 obj = intel_fb_obj(fb);
2625 if (obj->tiling_mode != I915_TILING_NONE)
2626 dev_priv->preserve_bios_swizzle = true;
2627
2628 drm_framebuffer_reference(fb);
2629 primary->fb = primary->state->fb = fb;
2630 primary->crtc = primary->state->crtc = &intel_crtc->base;
2631 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2632 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2633 }
2634
2635 static void i9xx_update_primary_plane(struct drm_plane *primary,
2636 const struct intel_crtc_state *crtc_state,
2637 const struct intel_plane_state *plane_state)
2638 {
2639 struct drm_device *dev = primary->dev;
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2642 struct drm_framebuffer *fb = plane_state->base.fb;
2643 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2644 int plane = intel_crtc->plane;
2645 u32 linear_offset;
2646 u32 dspcntr;
2647 i915_reg_t reg = DSPCNTR(plane);
2648 unsigned int rotation = plane_state->base.rotation;
2649 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2650 int x = plane_state->src.x1 >> 16;
2651 int y = plane_state->src.y1 >> 16;
2652
2653 dspcntr = DISPPLANE_GAMMA_ENABLE;
2654
2655 dspcntr |= DISPLAY_PLANE_ENABLE;
2656
2657 if (INTEL_INFO(dev)->gen < 4) {
2658 if (intel_crtc->pipe == PIPE_B)
2659 dspcntr |= DISPPLANE_SEL_PIPE_B;
2660
2661 /* pipesrc and dspsize control the size that is scaled from,
2662 * which should always be the user's requested size.
2663 */
2664 I915_WRITE(DSPSIZE(plane),
2665 ((crtc_state->pipe_src_h - 1) << 16) |
2666 (crtc_state->pipe_src_w - 1));
2667 I915_WRITE(DSPPOS(plane), 0);
2668 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2669 I915_WRITE(PRIMSIZE(plane),
2670 ((crtc_state->pipe_src_h - 1) << 16) |
2671 (crtc_state->pipe_src_w - 1));
2672 I915_WRITE(PRIMPOS(plane), 0);
2673 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2674 }
2675
2676 switch (fb->pixel_format) {
2677 case DRM_FORMAT_C8:
2678 dspcntr |= DISPPLANE_8BPP;
2679 break;
2680 case DRM_FORMAT_XRGB1555:
2681 dspcntr |= DISPPLANE_BGRX555;
2682 break;
2683 case DRM_FORMAT_RGB565:
2684 dspcntr |= DISPPLANE_BGRX565;
2685 break;
2686 case DRM_FORMAT_XRGB8888:
2687 dspcntr |= DISPPLANE_BGRX888;
2688 break;
2689 case DRM_FORMAT_XBGR8888:
2690 dspcntr |= DISPPLANE_RGBX888;
2691 break;
2692 case DRM_FORMAT_XRGB2101010:
2693 dspcntr |= DISPPLANE_BGRX101010;
2694 break;
2695 case DRM_FORMAT_XBGR2101010:
2696 dspcntr |= DISPPLANE_RGBX101010;
2697 break;
2698 default:
2699 BUG();
2700 }
2701
2702 if (INTEL_INFO(dev)->gen >= 4 &&
2703 obj->tiling_mode != I915_TILING_NONE)
2704 dspcntr |= DISPPLANE_TILED;
2705
2706 if (IS_G4X(dev))
2707 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2708
2709 linear_offset = y * fb->pitches[0] + x * cpp;
2710
2711 if (INTEL_INFO(dev)->gen >= 4) {
2712 intel_crtc->dspaddr_offset =
2713 intel_compute_tile_offset(&x, &y, fb, 0,
2714 fb->pitches[0], rotation);
2715 linear_offset -= intel_crtc->dspaddr_offset;
2716 } else {
2717 intel_crtc->dspaddr_offset = linear_offset;
2718 }
2719
2720 if (rotation == BIT(DRM_ROTATE_180)) {
2721 dspcntr |= DISPPLANE_ROTATE_180;
2722
2723 x += (crtc_state->pipe_src_w - 1);
2724 y += (crtc_state->pipe_src_h - 1);
2725
2726 /* Finding the last pixel of the last line of the display
2727 data and adding to linear_offset*/
2728 linear_offset +=
2729 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2730 (crtc_state->pipe_src_w - 1) * cpp;
2731 }
2732
2733 intel_crtc->adjusted_x = x;
2734 intel_crtc->adjusted_y = y;
2735
2736 I915_WRITE(reg, dspcntr);
2737
2738 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2739 if (INTEL_INFO(dev)->gen >= 4) {
2740 I915_WRITE(DSPSURF(plane),
2741 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2742 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2743 I915_WRITE(DSPLINOFF(plane), linear_offset);
2744 } else
2745 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2746 POSTING_READ(reg);
2747 }
2748
2749 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2750 struct drm_crtc *crtc)
2751 {
2752 struct drm_device *dev = crtc->dev;
2753 struct drm_i915_private *dev_priv = dev->dev_private;
2754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2755 int plane = intel_crtc->plane;
2756
2757 I915_WRITE(DSPCNTR(plane), 0);
2758 if (INTEL_INFO(dev_priv)->gen >= 4)
2759 I915_WRITE(DSPSURF(plane), 0);
2760 else
2761 I915_WRITE(DSPADDR(plane), 0);
2762 POSTING_READ(DSPCNTR(plane));
2763 }
2764
2765 static void ironlake_update_primary_plane(struct drm_plane *primary,
2766 const struct intel_crtc_state *crtc_state,
2767 const struct intel_plane_state *plane_state)
2768 {
2769 struct drm_device *dev = primary->dev;
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2772 struct drm_framebuffer *fb = plane_state->base.fb;
2773 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2774 int plane = intel_crtc->plane;
2775 u32 linear_offset;
2776 u32 dspcntr;
2777 i915_reg_t reg = DSPCNTR(plane);
2778 unsigned int rotation = plane_state->base.rotation;
2779 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2780 int x = plane_state->src.x1 >> 16;
2781 int y = plane_state->src.y1 >> 16;
2782
2783 dspcntr = DISPPLANE_GAMMA_ENABLE;
2784 dspcntr |= DISPLAY_PLANE_ENABLE;
2785
2786 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2787 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2788
2789 switch (fb->pixel_format) {
2790 case DRM_FORMAT_C8:
2791 dspcntr |= DISPPLANE_8BPP;
2792 break;
2793 case DRM_FORMAT_RGB565:
2794 dspcntr |= DISPPLANE_BGRX565;
2795 break;
2796 case DRM_FORMAT_XRGB8888:
2797 dspcntr |= DISPPLANE_BGRX888;
2798 break;
2799 case DRM_FORMAT_XBGR8888:
2800 dspcntr |= DISPPLANE_RGBX888;
2801 break;
2802 case DRM_FORMAT_XRGB2101010:
2803 dspcntr |= DISPPLANE_BGRX101010;
2804 break;
2805 case DRM_FORMAT_XBGR2101010:
2806 dspcntr |= DISPPLANE_RGBX101010;
2807 break;
2808 default:
2809 BUG();
2810 }
2811
2812 if (obj->tiling_mode != I915_TILING_NONE)
2813 dspcntr |= DISPPLANE_TILED;
2814
2815 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2816 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2817
2818 linear_offset = y * fb->pitches[0] + x * cpp;
2819 intel_crtc->dspaddr_offset =
2820 intel_compute_tile_offset(&x, &y, fb, 0,
2821 fb->pitches[0], rotation);
2822 linear_offset -= intel_crtc->dspaddr_offset;
2823 if (rotation == BIT(DRM_ROTATE_180)) {
2824 dspcntr |= DISPPLANE_ROTATE_180;
2825
2826 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2827 x += (crtc_state->pipe_src_w - 1);
2828 y += (crtc_state->pipe_src_h - 1);
2829
2830 /* Finding the last pixel of the last line of the display
2831 data and adding to linear_offset*/
2832 linear_offset +=
2833 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2834 (crtc_state->pipe_src_w - 1) * cpp;
2835 }
2836 }
2837
2838 intel_crtc->adjusted_x = x;
2839 intel_crtc->adjusted_y = y;
2840
2841 I915_WRITE(reg, dspcntr);
2842
2843 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2844 I915_WRITE(DSPSURF(plane),
2845 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2846 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2847 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2848 } else {
2849 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2850 I915_WRITE(DSPLINOFF(plane), linear_offset);
2851 }
2852 POSTING_READ(reg);
2853 }
2854
2855 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2856 uint64_t fb_modifier, uint32_t pixel_format)
2857 {
2858 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2859 return 64;
2860 } else {
2861 int cpp = drm_format_plane_cpp(pixel_format, 0);
2862
2863 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2864 }
2865 }
2866
2867 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2868 struct drm_i915_gem_object *obj,
2869 unsigned int plane)
2870 {
2871 struct i915_ggtt_view view;
2872 struct i915_vma *vma;
2873 u64 offset;
2874
2875 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2876 intel_plane->base.state->rotation);
2877
2878 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2879 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2880 view.type))
2881 return -1;
2882
2883 offset = vma->node.start;
2884
2885 if (plane == 1) {
2886 offset += vma->ggtt_view.params.rotated.uv_start_page *
2887 PAGE_SIZE;
2888 }
2889
2890 WARN_ON(upper_32_bits(offset));
2891
2892 return lower_32_bits(offset);
2893 }
2894
2895 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2896 {
2897 struct drm_device *dev = intel_crtc->base.dev;
2898 struct drm_i915_private *dev_priv = dev->dev_private;
2899
2900 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2901 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2902 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2903 }
2904
2905 /*
2906 * This function detaches (aka. unbinds) unused scalers in hardware
2907 */
2908 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2909 {
2910 struct intel_crtc_scaler_state *scaler_state;
2911 int i;
2912
2913 scaler_state = &intel_crtc->config->scaler_state;
2914
2915 /* loop through and disable scalers that aren't in use */
2916 for (i = 0; i < intel_crtc->num_scalers; i++) {
2917 if (!scaler_state->scalers[i].in_use)
2918 skl_detach_scaler(intel_crtc, i);
2919 }
2920 }
2921
2922 u32 skl_plane_ctl_format(uint32_t pixel_format)
2923 {
2924 switch (pixel_format) {
2925 case DRM_FORMAT_C8:
2926 return PLANE_CTL_FORMAT_INDEXED;
2927 case DRM_FORMAT_RGB565:
2928 return PLANE_CTL_FORMAT_RGB_565;
2929 case DRM_FORMAT_XBGR8888:
2930 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2931 case DRM_FORMAT_XRGB8888:
2932 return PLANE_CTL_FORMAT_XRGB_8888;
2933 /*
2934 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2935 * to be already pre-multiplied. We need to add a knob (or a different
2936 * DRM_FORMAT) for user-space to configure that.
2937 */
2938 case DRM_FORMAT_ABGR8888:
2939 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2940 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2941 case DRM_FORMAT_ARGB8888:
2942 return PLANE_CTL_FORMAT_XRGB_8888 |
2943 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2944 case DRM_FORMAT_XRGB2101010:
2945 return PLANE_CTL_FORMAT_XRGB_2101010;
2946 case DRM_FORMAT_XBGR2101010:
2947 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2948 case DRM_FORMAT_YUYV:
2949 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2950 case DRM_FORMAT_YVYU:
2951 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2952 case DRM_FORMAT_UYVY:
2953 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2954 case DRM_FORMAT_VYUY:
2955 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2956 default:
2957 MISSING_CASE(pixel_format);
2958 }
2959
2960 return 0;
2961 }
2962
2963 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2964 {
2965 switch (fb_modifier) {
2966 case DRM_FORMAT_MOD_NONE:
2967 break;
2968 case I915_FORMAT_MOD_X_TILED:
2969 return PLANE_CTL_TILED_X;
2970 case I915_FORMAT_MOD_Y_TILED:
2971 return PLANE_CTL_TILED_Y;
2972 case I915_FORMAT_MOD_Yf_TILED:
2973 return PLANE_CTL_TILED_YF;
2974 default:
2975 MISSING_CASE(fb_modifier);
2976 }
2977
2978 return 0;
2979 }
2980
2981 u32 skl_plane_ctl_rotation(unsigned int rotation)
2982 {
2983 switch (rotation) {
2984 case BIT(DRM_ROTATE_0):
2985 break;
2986 /*
2987 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2988 * while i915 HW rotation is clockwise, thats why this swapping.
2989 */
2990 case BIT(DRM_ROTATE_90):
2991 return PLANE_CTL_ROTATE_270;
2992 case BIT(DRM_ROTATE_180):
2993 return PLANE_CTL_ROTATE_180;
2994 case BIT(DRM_ROTATE_270):
2995 return PLANE_CTL_ROTATE_90;
2996 default:
2997 MISSING_CASE(rotation);
2998 }
2999
3000 return 0;
3001 }
3002
3003 static void skylake_update_primary_plane(struct drm_plane *plane,
3004 const struct intel_crtc_state *crtc_state,
3005 const struct intel_plane_state *plane_state)
3006 {
3007 struct drm_device *dev = plane->dev;
3008 struct drm_i915_private *dev_priv = dev->dev_private;
3009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3010 struct drm_framebuffer *fb = plane_state->base.fb;
3011 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3012 int pipe = intel_crtc->pipe;
3013 u32 plane_ctl, stride_div, stride;
3014 u32 tile_height, plane_offset, plane_size;
3015 unsigned int rotation = plane_state->base.rotation;
3016 int x_offset, y_offset;
3017 u32 surf_addr;
3018 int scaler_id = plane_state->scaler_id;
3019 int src_x = plane_state->src.x1 >> 16;
3020 int src_y = plane_state->src.y1 >> 16;
3021 int src_w = drm_rect_width(&plane_state->src) >> 16;
3022 int src_h = drm_rect_height(&plane_state->src) >> 16;
3023 int dst_x = plane_state->dst.x1;
3024 int dst_y = plane_state->dst.y1;
3025 int dst_w = drm_rect_width(&plane_state->dst);
3026 int dst_h = drm_rect_height(&plane_state->dst);
3027
3028 plane_ctl = PLANE_CTL_ENABLE |
3029 PLANE_CTL_PIPE_GAMMA_ENABLE |
3030 PLANE_CTL_PIPE_CSC_ENABLE;
3031
3032 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3033 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3034 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3035 plane_ctl |= skl_plane_ctl_rotation(rotation);
3036
3037 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3038 fb->pixel_format);
3039 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3040
3041 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3042
3043 if (intel_rotation_90_or_270(rotation)) {
3044 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3045
3046 /* stride = Surface height in tiles */
3047 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3048 stride = DIV_ROUND_UP(fb->height, tile_height);
3049 x_offset = stride * tile_height - src_y - src_h;
3050 y_offset = src_x;
3051 plane_size = (src_w - 1) << 16 | (src_h - 1);
3052 } else {
3053 stride = fb->pitches[0] / stride_div;
3054 x_offset = src_x;
3055 y_offset = src_y;
3056 plane_size = (src_h - 1) << 16 | (src_w - 1);
3057 }
3058 plane_offset = y_offset << 16 | x_offset;
3059
3060 intel_crtc->adjusted_x = x_offset;
3061 intel_crtc->adjusted_y = y_offset;
3062
3063 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3064 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3065 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3066 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3067
3068 if (scaler_id >= 0) {
3069 uint32_t ps_ctrl = 0;
3070
3071 WARN_ON(!dst_w || !dst_h);
3072 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3073 crtc_state->scaler_state.scalers[scaler_id].mode;
3074 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3075 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3076 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3077 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3078 I915_WRITE(PLANE_POS(pipe, 0), 0);
3079 } else {
3080 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3081 }
3082
3083 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3084
3085 POSTING_READ(PLANE_SURF(pipe, 0));
3086 }
3087
3088 static void skylake_disable_primary_plane(struct drm_plane *primary,
3089 struct drm_crtc *crtc)
3090 {
3091 struct drm_device *dev = crtc->dev;
3092 struct drm_i915_private *dev_priv = dev->dev_private;
3093 int pipe = to_intel_crtc(crtc)->pipe;
3094
3095 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3096 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3097 POSTING_READ(PLANE_SURF(pipe, 0));
3098 }
3099
3100 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3101 static int
3102 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3103 int x, int y, enum mode_set_atomic state)
3104 {
3105 /* Support for kgdboc is disabled, this needs a major rework. */
3106 DRM_ERROR("legacy panic handler not supported any more.\n");
3107
3108 return -ENODEV;
3109 }
3110
3111 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3112 {
3113 struct drm_crtc *crtc;
3114
3115 for_each_crtc(dev_priv->dev, crtc) {
3116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3117 enum plane plane = intel_crtc->plane;
3118
3119 intel_prepare_page_flip(dev_priv, plane);
3120 intel_finish_page_flip_plane(dev_priv, plane);
3121 }
3122 }
3123
3124 static void intel_update_primary_planes(struct drm_device *dev)
3125 {
3126 struct drm_crtc *crtc;
3127
3128 for_each_crtc(dev, crtc) {
3129 struct intel_plane *plane = to_intel_plane(crtc->primary);
3130 struct intel_plane_state *plane_state;
3131
3132 drm_modeset_lock_crtc(crtc, &plane->base);
3133 plane_state = to_intel_plane_state(plane->base.state);
3134
3135 if (plane_state->visible)
3136 plane->update_plane(&plane->base,
3137 to_intel_crtc_state(crtc->state),
3138 plane_state);
3139
3140 drm_modeset_unlock_crtc(crtc);
3141 }
3142 }
3143
3144 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3145 {
3146 /* no reset support for gen2 */
3147 if (IS_GEN2(dev_priv))
3148 return;
3149
3150 /* reset doesn't touch the display */
3151 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3152 return;
3153
3154 drm_modeset_lock_all(dev_priv->dev);
3155 /*
3156 * Disabling the crtcs gracefully seems nicer. Also the
3157 * g33 docs say we should at least disable all the planes.
3158 */
3159 intel_display_suspend(dev_priv->dev);
3160 }
3161
3162 void intel_finish_reset(struct drm_i915_private *dev_priv)
3163 {
3164 /*
3165 * Flips in the rings will be nuked by the reset,
3166 * so complete all pending flips so that user space
3167 * will get its events and not get stuck.
3168 */
3169 intel_complete_page_flips(dev_priv);
3170
3171 /* no reset support for gen2 */
3172 if (IS_GEN2(dev_priv))
3173 return;
3174
3175 /* reset doesn't touch the display */
3176 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3177 /*
3178 * Flips in the rings have been nuked by the reset,
3179 * so update the base address of all primary
3180 * planes to the the last fb to make sure we're
3181 * showing the correct fb after a reset.
3182 *
3183 * FIXME: Atomic will make this obsolete since we won't schedule
3184 * CS-based flips (which might get lost in gpu resets) any more.
3185 */
3186 intel_update_primary_planes(dev_priv->dev);
3187 return;
3188 }
3189
3190 /*
3191 * The display has been reset as well,
3192 * so need a full re-initialization.
3193 */
3194 intel_runtime_pm_disable_interrupts(dev_priv);
3195 intel_runtime_pm_enable_interrupts(dev_priv);
3196
3197 intel_modeset_init_hw(dev_priv->dev);
3198
3199 spin_lock_irq(&dev_priv->irq_lock);
3200 if (dev_priv->display.hpd_irq_setup)
3201 dev_priv->display.hpd_irq_setup(dev_priv);
3202 spin_unlock_irq(&dev_priv->irq_lock);
3203
3204 intel_display_resume(dev_priv->dev);
3205
3206 intel_hpd_init(dev_priv);
3207
3208 drm_modeset_unlock_all(dev_priv->dev);
3209 }
3210
3211 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3212 {
3213 struct drm_device *dev = crtc->dev;
3214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3215 unsigned reset_counter;
3216 bool pending;
3217
3218 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3219 if (intel_crtc->reset_counter != reset_counter)
3220 return false;
3221
3222 spin_lock_irq(&dev->event_lock);
3223 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3224 spin_unlock_irq(&dev->event_lock);
3225
3226 return pending;
3227 }
3228
3229 static void intel_update_pipe_config(struct intel_crtc *crtc,
3230 struct intel_crtc_state *old_crtc_state)
3231 {
3232 struct drm_device *dev = crtc->base.dev;
3233 struct drm_i915_private *dev_priv = dev->dev_private;
3234 struct intel_crtc_state *pipe_config =
3235 to_intel_crtc_state(crtc->base.state);
3236
3237 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3238 crtc->base.mode = crtc->base.state->mode;
3239
3240 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3241 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3242 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3243
3244 /*
3245 * Update pipe size and adjust fitter if needed: the reason for this is
3246 * that in compute_mode_changes we check the native mode (not the pfit
3247 * mode) to see if we can flip rather than do a full mode set. In the
3248 * fastboot case, we'll flip, but if we don't update the pipesrc and
3249 * pfit state, we'll end up with a big fb scanned out into the wrong
3250 * sized surface.
3251 */
3252
3253 I915_WRITE(PIPESRC(crtc->pipe),
3254 ((pipe_config->pipe_src_w - 1) << 16) |
3255 (pipe_config->pipe_src_h - 1));
3256
3257 /* on skylake this is done by detaching scalers */
3258 if (INTEL_INFO(dev)->gen >= 9) {
3259 skl_detach_scalers(crtc);
3260
3261 if (pipe_config->pch_pfit.enabled)
3262 skylake_pfit_enable(crtc);
3263 } else if (HAS_PCH_SPLIT(dev)) {
3264 if (pipe_config->pch_pfit.enabled)
3265 ironlake_pfit_enable(crtc);
3266 else if (old_crtc_state->pch_pfit.enabled)
3267 ironlake_pfit_disable(crtc, true);
3268 }
3269 }
3270
3271 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3272 {
3273 struct drm_device *dev = crtc->dev;
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3276 int pipe = intel_crtc->pipe;
3277 i915_reg_t reg;
3278 u32 temp;
3279
3280 /* enable normal train */
3281 reg = FDI_TX_CTL(pipe);
3282 temp = I915_READ(reg);
3283 if (IS_IVYBRIDGE(dev)) {
3284 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3285 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3286 } else {
3287 temp &= ~FDI_LINK_TRAIN_NONE;
3288 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3289 }
3290 I915_WRITE(reg, temp);
3291
3292 reg = FDI_RX_CTL(pipe);
3293 temp = I915_READ(reg);
3294 if (HAS_PCH_CPT(dev)) {
3295 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3296 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3297 } else {
3298 temp &= ~FDI_LINK_TRAIN_NONE;
3299 temp |= FDI_LINK_TRAIN_NONE;
3300 }
3301 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3302
3303 /* wait one idle pattern time */
3304 POSTING_READ(reg);
3305 udelay(1000);
3306
3307 /* IVB wants error correction enabled */
3308 if (IS_IVYBRIDGE(dev))
3309 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3310 FDI_FE_ERRC_ENABLE);
3311 }
3312
3313 /* The FDI link training functions for ILK/Ibexpeak. */
3314 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3315 {
3316 struct drm_device *dev = crtc->dev;
3317 struct drm_i915_private *dev_priv = dev->dev_private;
3318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3319 int pipe = intel_crtc->pipe;
3320 i915_reg_t reg;
3321 u32 temp, tries;
3322
3323 /* FDI needs bits from pipe first */
3324 assert_pipe_enabled(dev_priv, pipe);
3325
3326 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3327 for train result */
3328 reg = FDI_RX_IMR(pipe);
3329 temp = I915_READ(reg);
3330 temp &= ~FDI_RX_SYMBOL_LOCK;
3331 temp &= ~FDI_RX_BIT_LOCK;
3332 I915_WRITE(reg, temp);
3333 I915_READ(reg);
3334 udelay(150);
3335
3336 /* enable CPU FDI TX and PCH FDI RX */
3337 reg = FDI_TX_CTL(pipe);
3338 temp = I915_READ(reg);
3339 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3340 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3341 temp &= ~FDI_LINK_TRAIN_NONE;
3342 temp |= FDI_LINK_TRAIN_PATTERN_1;
3343 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3344
3345 reg = FDI_RX_CTL(pipe);
3346 temp = I915_READ(reg);
3347 temp &= ~FDI_LINK_TRAIN_NONE;
3348 temp |= FDI_LINK_TRAIN_PATTERN_1;
3349 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3350
3351 POSTING_READ(reg);
3352 udelay(150);
3353
3354 /* Ironlake workaround, enable clock pointer after FDI enable*/
3355 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3356 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3357 FDI_RX_PHASE_SYNC_POINTER_EN);
3358
3359 reg = FDI_RX_IIR(pipe);
3360 for (tries = 0; tries < 5; tries++) {
3361 temp = I915_READ(reg);
3362 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3363
3364 if ((temp & FDI_RX_BIT_LOCK)) {
3365 DRM_DEBUG_KMS("FDI train 1 done.\n");
3366 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3367 break;
3368 }
3369 }
3370 if (tries == 5)
3371 DRM_ERROR("FDI train 1 fail!\n");
3372
3373 /* Train 2 */
3374 reg = FDI_TX_CTL(pipe);
3375 temp = I915_READ(reg);
3376 temp &= ~FDI_LINK_TRAIN_NONE;
3377 temp |= FDI_LINK_TRAIN_PATTERN_2;
3378 I915_WRITE(reg, temp);
3379
3380 reg = FDI_RX_CTL(pipe);
3381 temp = I915_READ(reg);
3382 temp &= ~FDI_LINK_TRAIN_NONE;
3383 temp |= FDI_LINK_TRAIN_PATTERN_2;
3384 I915_WRITE(reg, temp);
3385
3386 POSTING_READ(reg);
3387 udelay(150);
3388
3389 reg = FDI_RX_IIR(pipe);
3390 for (tries = 0; tries < 5; tries++) {
3391 temp = I915_READ(reg);
3392 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3393
3394 if (temp & FDI_RX_SYMBOL_LOCK) {
3395 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3396 DRM_DEBUG_KMS("FDI train 2 done.\n");
3397 break;
3398 }
3399 }
3400 if (tries == 5)
3401 DRM_ERROR("FDI train 2 fail!\n");
3402
3403 DRM_DEBUG_KMS("FDI train done\n");
3404
3405 }
3406
3407 static const int snb_b_fdi_train_param[] = {
3408 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3409 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3410 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3411 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3412 };
3413
3414 /* The FDI link training functions for SNB/Cougarpoint. */
3415 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3416 {
3417 struct drm_device *dev = crtc->dev;
3418 struct drm_i915_private *dev_priv = dev->dev_private;
3419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3420 int pipe = intel_crtc->pipe;
3421 i915_reg_t reg;
3422 u32 temp, i, retry;
3423
3424 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3425 for train result */
3426 reg = FDI_RX_IMR(pipe);
3427 temp = I915_READ(reg);
3428 temp &= ~FDI_RX_SYMBOL_LOCK;
3429 temp &= ~FDI_RX_BIT_LOCK;
3430 I915_WRITE(reg, temp);
3431
3432 POSTING_READ(reg);
3433 udelay(150);
3434
3435 /* enable CPU FDI TX and PCH FDI RX */
3436 reg = FDI_TX_CTL(pipe);
3437 temp = I915_READ(reg);
3438 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3439 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3440 temp &= ~FDI_LINK_TRAIN_NONE;
3441 temp |= FDI_LINK_TRAIN_PATTERN_1;
3442 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3443 /* SNB-B */
3444 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3445 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3446
3447 I915_WRITE(FDI_RX_MISC(pipe),
3448 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3449
3450 reg = FDI_RX_CTL(pipe);
3451 temp = I915_READ(reg);
3452 if (HAS_PCH_CPT(dev)) {
3453 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3454 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3455 } else {
3456 temp &= ~FDI_LINK_TRAIN_NONE;
3457 temp |= FDI_LINK_TRAIN_PATTERN_1;
3458 }
3459 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3460
3461 POSTING_READ(reg);
3462 udelay(150);
3463
3464 for (i = 0; i < 4; i++) {
3465 reg = FDI_TX_CTL(pipe);
3466 temp = I915_READ(reg);
3467 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3468 temp |= snb_b_fdi_train_param[i];
3469 I915_WRITE(reg, temp);
3470
3471 POSTING_READ(reg);
3472 udelay(500);
3473
3474 for (retry = 0; retry < 5; retry++) {
3475 reg = FDI_RX_IIR(pipe);
3476 temp = I915_READ(reg);
3477 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3478 if (temp & FDI_RX_BIT_LOCK) {
3479 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3480 DRM_DEBUG_KMS("FDI train 1 done.\n");
3481 break;
3482 }
3483 udelay(50);
3484 }
3485 if (retry < 5)
3486 break;
3487 }
3488 if (i == 4)
3489 DRM_ERROR("FDI train 1 fail!\n");
3490
3491 /* Train 2 */
3492 reg = FDI_TX_CTL(pipe);
3493 temp = I915_READ(reg);
3494 temp &= ~FDI_LINK_TRAIN_NONE;
3495 temp |= FDI_LINK_TRAIN_PATTERN_2;
3496 if (IS_GEN6(dev)) {
3497 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3498 /* SNB-B */
3499 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3500 }
3501 I915_WRITE(reg, temp);
3502
3503 reg = FDI_RX_CTL(pipe);
3504 temp = I915_READ(reg);
3505 if (HAS_PCH_CPT(dev)) {
3506 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3507 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3508 } else {
3509 temp &= ~FDI_LINK_TRAIN_NONE;
3510 temp |= FDI_LINK_TRAIN_PATTERN_2;
3511 }
3512 I915_WRITE(reg, temp);
3513
3514 POSTING_READ(reg);
3515 udelay(150);
3516
3517 for (i = 0; i < 4; i++) {
3518 reg = FDI_TX_CTL(pipe);
3519 temp = I915_READ(reg);
3520 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3521 temp |= snb_b_fdi_train_param[i];
3522 I915_WRITE(reg, temp);
3523
3524 POSTING_READ(reg);
3525 udelay(500);
3526
3527 for (retry = 0; retry < 5; retry++) {
3528 reg = FDI_RX_IIR(pipe);
3529 temp = I915_READ(reg);
3530 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3531 if (temp & FDI_RX_SYMBOL_LOCK) {
3532 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3533 DRM_DEBUG_KMS("FDI train 2 done.\n");
3534 break;
3535 }
3536 udelay(50);
3537 }
3538 if (retry < 5)
3539 break;
3540 }
3541 if (i == 4)
3542 DRM_ERROR("FDI train 2 fail!\n");
3543
3544 DRM_DEBUG_KMS("FDI train done.\n");
3545 }
3546
3547 /* Manual link training for Ivy Bridge A0 parts */
3548 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3549 {
3550 struct drm_device *dev = crtc->dev;
3551 struct drm_i915_private *dev_priv = dev->dev_private;
3552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553 int pipe = intel_crtc->pipe;
3554 i915_reg_t reg;
3555 u32 temp, i, j;
3556
3557 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3558 for train result */
3559 reg = FDI_RX_IMR(pipe);
3560 temp = I915_READ(reg);
3561 temp &= ~FDI_RX_SYMBOL_LOCK;
3562 temp &= ~FDI_RX_BIT_LOCK;
3563 I915_WRITE(reg, temp);
3564
3565 POSTING_READ(reg);
3566 udelay(150);
3567
3568 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3569 I915_READ(FDI_RX_IIR(pipe)));
3570
3571 /* Try each vswing and preemphasis setting twice before moving on */
3572 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3573 /* disable first in case we need to retry */
3574 reg = FDI_TX_CTL(pipe);
3575 temp = I915_READ(reg);
3576 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3577 temp &= ~FDI_TX_ENABLE;
3578 I915_WRITE(reg, temp);
3579
3580 reg = FDI_RX_CTL(pipe);
3581 temp = I915_READ(reg);
3582 temp &= ~FDI_LINK_TRAIN_AUTO;
3583 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3584 temp &= ~FDI_RX_ENABLE;
3585 I915_WRITE(reg, temp);
3586
3587 /* enable CPU FDI TX and PCH FDI RX */
3588 reg = FDI_TX_CTL(pipe);
3589 temp = I915_READ(reg);
3590 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3591 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3592 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3593 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3594 temp |= snb_b_fdi_train_param[j/2];
3595 temp |= FDI_COMPOSITE_SYNC;
3596 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3597
3598 I915_WRITE(FDI_RX_MISC(pipe),
3599 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3600
3601 reg = FDI_RX_CTL(pipe);
3602 temp = I915_READ(reg);
3603 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3604 temp |= FDI_COMPOSITE_SYNC;
3605 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3606
3607 POSTING_READ(reg);
3608 udelay(1); /* should be 0.5us */
3609
3610 for (i = 0; i < 4; i++) {
3611 reg = FDI_RX_IIR(pipe);
3612 temp = I915_READ(reg);
3613 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3614
3615 if (temp & FDI_RX_BIT_LOCK ||
3616 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3617 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3618 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3619 i);
3620 break;
3621 }
3622 udelay(1); /* should be 0.5us */
3623 }
3624 if (i == 4) {
3625 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3626 continue;
3627 }
3628
3629 /* Train 2 */
3630 reg = FDI_TX_CTL(pipe);
3631 temp = I915_READ(reg);
3632 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3633 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3634 I915_WRITE(reg, temp);
3635
3636 reg = FDI_RX_CTL(pipe);
3637 temp = I915_READ(reg);
3638 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3639 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3640 I915_WRITE(reg, temp);
3641
3642 POSTING_READ(reg);
3643 udelay(2); /* should be 1.5us */
3644
3645 for (i = 0; i < 4; i++) {
3646 reg = FDI_RX_IIR(pipe);
3647 temp = I915_READ(reg);
3648 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3649
3650 if (temp & FDI_RX_SYMBOL_LOCK ||
3651 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3652 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3653 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3654 i);
3655 goto train_done;
3656 }
3657 udelay(2); /* should be 1.5us */
3658 }
3659 if (i == 4)
3660 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3661 }
3662
3663 train_done:
3664 DRM_DEBUG_KMS("FDI train done.\n");
3665 }
3666
3667 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3668 {
3669 struct drm_device *dev = intel_crtc->base.dev;
3670 struct drm_i915_private *dev_priv = dev->dev_private;
3671 int pipe = intel_crtc->pipe;
3672 i915_reg_t reg;
3673 u32 temp;
3674
3675 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3676 reg = FDI_RX_CTL(pipe);
3677 temp = I915_READ(reg);
3678 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3679 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3680 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3681 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3682
3683 POSTING_READ(reg);
3684 udelay(200);
3685
3686 /* Switch from Rawclk to PCDclk */
3687 temp = I915_READ(reg);
3688 I915_WRITE(reg, temp | FDI_PCDCLK);
3689
3690 POSTING_READ(reg);
3691 udelay(200);
3692
3693 /* Enable CPU FDI TX PLL, always on for Ironlake */
3694 reg = FDI_TX_CTL(pipe);
3695 temp = I915_READ(reg);
3696 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3697 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3698
3699 POSTING_READ(reg);
3700 udelay(100);
3701 }
3702 }
3703
3704 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3705 {
3706 struct drm_device *dev = intel_crtc->base.dev;
3707 struct drm_i915_private *dev_priv = dev->dev_private;
3708 int pipe = intel_crtc->pipe;
3709 i915_reg_t reg;
3710 u32 temp;
3711
3712 /* Switch from PCDclk to Rawclk */
3713 reg = FDI_RX_CTL(pipe);
3714 temp = I915_READ(reg);
3715 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3716
3717 /* Disable CPU FDI TX PLL */
3718 reg = FDI_TX_CTL(pipe);
3719 temp = I915_READ(reg);
3720 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3721
3722 POSTING_READ(reg);
3723 udelay(100);
3724
3725 reg = FDI_RX_CTL(pipe);
3726 temp = I915_READ(reg);
3727 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3728
3729 /* Wait for the clocks to turn off. */
3730 POSTING_READ(reg);
3731 udelay(100);
3732 }
3733
3734 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3735 {
3736 struct drm_device *dev = crtc->dev;
3737 struct drm_i915_private *dev_priv = dev->dev_private;
3738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3739 int pipe = intel_crtc->pipe;
3740 i915_reg_t reg;
3741 u32 temp;
3742
3743 /* disable CPU FDI tx and PCH FDI rx */
3744 reg = FDI_TX_CTL(pipe);
3745 temp = I915_READ(reg);
3746 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3747 POSTING_READ(reg);
3748
3749 reg = FDI_RX_CTL(pipe);
3750 temp = I915_READ(reg);
3751 temp &= ~(0x7 << 16);
3752 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3753 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3754
3755 POSTING_READ(reg);
3756 udelay(100);
3757
3758 /* Ironlake workaround, disable clock pointer after downing FDI */
3759 if (HAS_PCH_IBX(dev))
3760 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3761
3762 /* still set train pattern 1 */
3763 reg = FDI_TX_CTL(pipe);
3764 temp = I915_READ(reg);
3765 temp &= ~FDI_LINK_TRAIN_NONE;
3766 temp |= FDI_LINK_TRAIN_PATTERN_1;
3767 I915_WRITE(reg, temp);
3768
3769 reg = FDI_RX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 if (HAS_PCH_CPT(dev)) {
3772 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3773 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3774 } else {
3775 temp &= ~FDI_LINK_TRAIN_NONE;
3776 temp |= FDI_LINK_TRAIN_PATTERN_1;
3777 }
3778 /* BPC in FDI rx is consistent with that in PIPECONF */
3779 temp &= ~(0x07 << 16);
3780 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3781 I915_WRITE(reg, temp);
3782
3783 POSTING_READ(reg);
3784 udelay(100);
3785 }
3786
3787 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3788 {
3789 struct intel_crtc *crtc;
3790
3791 /* Note that we don't need to be called with mode_config.lock here
3792 * as our list of CRTC objects is static for the lifetime of the
3793 * device and so cannot disappear as we iterate. Similarly, we can
3794 * happily treat the predicates as racy, atomic checks as userspace
3795 * cannot claim and pin a new fb without at least acquring the
3796 * struct_mutex and so serialising with us.
3797 */
3798 for_each_intel_crtc(dev, crtc) {
3799 if (atomic_read(&crtc->unpin_work_count) == 0)
3800 continue;
3801
3802 if (crtc->unpin_work)
3803 intel_wait_for_vblank(dev, crtc->pipe);
3804
3805 return true;
3806 }
3807
3808 return false;
3809 }
3810
3811 static void page_flip_completed(struct intel_crtc *intel_crtc)
3812 {
3813 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3814 struct intel_unpin_work *work = intel_crtc->unpin_work;
3815
3816 /* ensure that the unpin work is consistent wrt ->pending. */
3817 smp_rmb();
3818 intel_crtc->unpin_work = NULL;
3819
3820 if (work->event)
3821 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3822
3823 drm_crtc_vblank_put(&intel_crtc->base);
3824
3825 wake_up_all(&dev_priv->pending_flip_queue);
3826 queue_work(dev_priv->wq, &work->work);
3827
3828 trace_i915_flip_complete(intel_crtc->plane,
3829 work->pending_flip_obj);
3830 }
3831
3832 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3833 {
3834 struct drm_device *dev = crtc->dev;
3835 struct drm_i915_private *dev_priv = dev->dev_private;
3836 long ret;
3837
3838 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3839
3840 ret = wait_event_interruptible_timeout(
3841 dev_priv->pending_flip_queue,
3842 !intel_crtc_has_pending_flip(crtc),
3843 60*HZ);
3844
3845 if (ret < 0)
3846 return ret;
3847
3848 if (ret == 0) {
3849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3850
3851 spin_lock_irq(&dev->event_lock);
3852 if (intel_crtc->unpin_work) {
3853 WARN_ONCE(1, "Removing stuck page flip\n");
3854 page_flip_completed(intel_crtc);
3855 }
3856 spin_unlock_irq(&dev->event_lock);
3857 }
3858
3859 return 0;
3860 }
3861
3862 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3863 {
3864 u32 temp;
3865
3866 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3867
3868 mutex_lock(&dev_priv->sb_lock);
3869
3870 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3871 temp |= SBI_SSCCTL_DISABLE;
3872 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3873
3874 mutex_unlock(&dev_priv->sb_lock);
3875 }
3876
3877 /* Program iCLKIP clock to the desired frequency */
3878 static void lpt_program_iclkip(struct drm_crtc *crtc)
3879 {
3880 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3881 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3882 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3883 u32 temp;
3884
3885 lpt_disable_iclkip(dev_priv);
3886
3887 /* The iCLK virtual clock root frequency is in MHz,
3888 * but the adjusted_mode->crtc_clock in in KHz. To get the
3889 * divisors, it is necessary to divide one by another, so we
3890 * convert the virtual clock precision to KHz here for higher
3891 * precision.
3892 */
3893 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3894 u32 iclk_virtual_root_freq = 172800 * 1000;
3895 u32 iclk_pi_range = 64;
3896 u32 desired_divisor;
3897
3898 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3899 clock << auxdiv);
3900 divsel = (desired_divisor / iclk_pi_range) - 2;
3901 phaseinc = desired_divisor % iclk_pi_range;
3902
3903 /*
3904 * Near 20MHz is a corner case which is
3905 * out of range for the 7-bit divisor
3906 */
3907 if (divsel <= 0x7f)
3908 break;
3909 }
3910
3911 /* This should not happen with any sane values */
3912 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3913 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3914 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3915 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3916
3917 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3918 clock,
3919 auxdiv,
3920 divsel,
3921 phasedir,
3922 phaseinc);
3923
3924 mutex_lock(&dev_priv->sb_lock);
3925
3926 /* Program SSCDIVINTPHASE6 */
3927 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3928 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3929 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3930 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3931 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3932 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3933 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3934 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3935
3936 /* Program SSCAUXDIV */
3937 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3938 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3939 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3940 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3941
3942 /* Enable modulator and associated divider */
3943 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3944 temp &= ~SBI_SSCCTL_DISABLE;
3945 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3946
3947 mutex_unlock(&dev_priv->sb_lock);
3948
3949 /* Wait for initialization time */
3950 udelay(24);
3951
3952 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3953 }
3954
3955 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3956 {
3957 u32 divsel, phaseinc, auxdiv;
3958 u32 iclk_virtual_root_freq = 172800 * 1000;
3959 u32 iclk_pi_range = 64;
3960 u32 desired_divisor;
3961 u32 temp;
3962
3963 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3964 return 0;
3965
3966 mutex_lock(&dev_priv->sb_lock);
3967
3968 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3969 if (temp & SBI_SSCCTL_DISABLE) {
3970 mutex_unlock(&dev_priv->sb_lock);
3971 return 0;
3972 }
3973
3974 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3975 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3976 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3977 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3978 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3979
3980 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3981 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3982 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3983
3984 mutex_unlock(&dev_priv->sb_lock);
3985
3986 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3987
3988 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3989 desired_divisor << auxdiv);
3990 }
3991
3992 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3993 enum pipe pch_transcoder)
3994 {
3995 struct drm_device *dev = crtc->base.dev;
3996 struct drm_i915_private *dev_priv = dev->dev_private;
3997 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3998
3999 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4000 I915_READ(HTOTAL(cpu_transcoder)));
4001 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4002 I915_READ(HBLANK(cpu_transcoder)));
4003 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4004 I915_READ(HSYNC(cpu_transcoder)));
4005
4006 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4007 I915_READ(VTOTAL(cpu_transcoder)));
4008 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4009 I915_READ(VBLANK(cpu_transcoder)));
4010 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4011 I915_READ(VSYNC(cpu_transcoder)));
4012 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4013 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4014 }
4015
4016 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4017 {
4018 struct drm_i915_private *dev_priv = dev->dev_private;
4019 uint32_t temp;
4020
4021 temp = I915_READ(SOUTH_CHICKEN1);
4022 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4023 return;
4024
4025 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4026 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4027
4028 temp &= ~FDI_BC_BIFURCATION_SELECT;
4029 if (enable)
4030 temp |= FDI_BC_BIFURCATION_SELECT;
4031
4032 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4033 I915_WRITE(SOUTH_CHICKEN1, temp);
4034 POSTING_READ(SOUTH_CHICKEN1);
4035 }
4036
4037 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4038 {
4039 struct drm_device *dev = intel_crtc->base.dev;
4040
4041 switch (intel_crtc->pipe) {
4042 case PIPE_A:
4043 break;
4044 case PIPE_B:
4045 if (intel_crtc->config->fdi_lanes > 2)
4046 cpt_set_fdi_bc_bifurcation(dev, false);
4047 else
4048 cpt_set_fdi_bc_bifurcation(dev, true);
4049
4050 break;
4051 case PIPE_C:
4052 cpt_set_fdi_bc_bifurcation(dev, true);
4053
4054 break;
4055 default:
4056 BUG();
4057 }
4058 }
4059
4060 /* Return which DP Port should be selected for Transcoder DP control */
4061 static enum port
4062 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4063 {
4064 struct drm_device *dev = crtc->dev;
4065 struct intel_encoder *encoder;
4066
4067 for_each_encoder_on_crtc(dev, crtc, encoder) {
4068 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4069 encoder->type == INTEL_OUTPUT_EDP)
4070 return enc_to_dig_port(&encoder->base)->port;
4071 }
4072
4073 return -1;
4074 }
4075
4076 /*
4077 * Enable PCH resources required for PCH ports:
4078 * - PCH PLLs
4079 * - FDI training & RX/TX
4080 * - update transcoder timings
4081 * - DP transcoding bits
4082 * - transcoder
4083 */
4084 static void ironlake_pch_enable(struct drm_crtc *crtc)
4085 {
4086 struct drm_device *dev = crtc->dev;
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4089 int pipe = intel_crtc->pipe;
4090 u32 temp;
4091
4092 assert_pch_transcoder_disabled(dev_priv, pipe);
4093
4094 if (IS_IVYBRIDGE(dev))
4095 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4096
4097 /* Write the TU size bits before fdi link training, so that error
4098 * detection works. */
4099 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4100 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4101
4102 /* For PCH output, training FDI link */
4103 dev_priv->display.fdi_link_train(crtc);
4104
4105 /* We need to program the right clock selection before writing the pixel
4106 * mutliplier into the DPLL. */
4107 if (HAS_PCH_CPT(dev)) {
4108 u32 sel;
4109
4110 temp = I915_READ(PCH_DPLL_SEL);
4111 temp |= TRANS_DPLL_ENABLE(pipe);
4112 sel = TRANS_DPLLB_SEL(pipe);
4113 if (intel_crtc->config->shared_dpll ==
4114 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4115 temp |= sel;
4116 else
4117 temp &= ~sel;
4118 I915_WRITE(PCH_DPLL_SEL, temp);
4119 }
4120
4121 /* XXX: pch pll's can be enabled any time before we enable the PCH
4122 * transcoder, and we actually should do this to not upset any PCH
4123 * transcoder that already use the clock when we share it.
4124 *
4125 * Note that enable_shared_dpll tries to do the right thing, but
4126 * get_shared_dpll unconditionally resets the pll - we need that to have
4127 * the right LVDS enable sequence. */
4128 intel_enable_shared_dpll(intel_crtc);
4129
4130 /* set transcoder timing, panel must allow it */
4131 assert_panel_unlocked(dev_priv, pipe);
4132 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4133
4134 intel_fdi_normal_train(crtc);
4135
4136 /* For PCH DP, enable TRANS_DP_CTL */
4137 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4138 const struct drm_display_mode *adjusted_mode =
4139 &intel_crtc->config->base.adjusted_mode;
4140 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4141 i915_reg_t reg = TRANS_DP_CTL(pipe);
4142 temp = I915_READ(reg);
4143 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4144 TRANS_DP_SYNC_MASK |
4145 TRANS_DP_BPC_MASK);
4146 temp |= TRANS_DP_OUTPUT_ENABLE;
4147 temp |= bpc << 9; /* same format but at 11:9 */
4148
4149 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4150 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4151 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4152 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4153
4154 switch (intel_trans_dp_port_sel(crtc)) {
4155 case PORT_B:
4156 temp |= TRANS_DP_PORT_SEL_B;
4157 break;
4158 case PORT_C:
4159 temp |= TRANS_DP_PORT_SEL_C;
4160 break;
4161 case PORT_D:
4162 temp |= TRANS_DP_PORT_SEL_D;
4163 break;
4164 default:
4165 BUG();
4166 }
4167
4168 I915_WRITE(reg, temp);
4169 }
4170
4171 ironlake_enable_pch_transcoder(dev_priv, pipe);
4172 }
4173
4174 static void lpt_pch_enable(struct drm_crtc *crtc)
4175 {
4176 struct drm_device *dev = crtc->dev;
4177 struct drm_i915_private *dev_priv = dev->dev_private;
4178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4179 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4180
4181 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4182
4183 lpt_program_iclkip(crtc);
4184
4185 /* Set transcoder timing. */
4186 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4187
4188 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4189 }
4190
4191 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4192 {
4193 struct drm_i915_private *dev_priv = dev->dev_private;
4194 i915_reg_t dslreg = PIPEDSL(pipe);
4195 u32 temp;
4196
4197 temp = I915_READ(dslreg);
4198 udelay(500);
4199 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4200 if (wait_for(I915_READ(dslreg) != temp, 5))
4201 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4202 }
4203 }
4204
4205 static int
4206 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4207 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4208 int src_w, int src_h, int dst_w, int dst_h)
4209 {
4210 struct intel_crtc_scaler_state *scaler_state =
4211 &crtc_state->scaler_state;
4212 struct intel_crtc *intel_crtc =
4213 to_intel_crtc(crtc_state->base.crtc);
4214 int need_scaling;
4215
4216 need_scaling = intel_rotation_90_or_270(rotation) ?
4217 (src_h != dst_w || src_w != dst_h):
4218 (src_w != dst_w || src_h != dst_h);
4219
4220 /*
4221 * if plane is being disabled or scaler is no more required or force detach
4222 * - free scaler binded to this plane/crtc
4223 * - in order to do this, update crtc->scaler_usage
4224 *
4225 * Here scaler state in crtc_state is set free so that
4226 * scaler can be assigned to other user. Actual register
4227 * update to free the scaler is done in plane/panel-fit programming.
4228 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4229 */
4230 if (force_detach || !need_scaling) {
4231 if (*scaler_id >= 0) {
4232 scaler_state->scaler_users &= ~(1 << scaler_user);
4233 scaler_state->scalers[*scaler_id].in_use = 0;
4234
4235 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4236 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4237 intel_crtc->pipe, scaler_user, *scaler_id,
4238 scaler_state->scaler_users);
4239 *scaler_id = -1;
4240 }
4241 return 0;
4242 }
4243
4244 /* range checks */
4245 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4246 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4247
4248 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4249 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4250 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4251 "size is out of scaler range\n",
4252 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4253 return -EINVAL;
4254 }
4255
4256 /* mark this plane as a scaler user in crtc_state */
4257 scaler_state->scaler_users |= (1 << scaler_user);
4258 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4259 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4260 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4261 scaler_state->scaler_users);
4262
4263 return 0;
4264 }
4265
4266 /**
4267 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4268 *
4269 * @state: crtc's scaler state
4270 *
4271 * Return
4272 * 0 - scaler_usage updated successfully
4273 * error - requested scaling cannot be supported or other error condition
4274 */
4275 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4276 {
4277 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4278 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4279
4280 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4281 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4282
4283 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4284 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4285 state->pipe_src_w, state->pipe_src_h,
4286 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4287 }
4288
4289 /**
4290 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4291 *
4292 * @state: crtc's scaler state
4293 * @plane_state: atomic plane state to update
4294 *
4295 * Return
4296 * 0 - scaler_usage updated successfully
4297 * error - requested scaling cannot be supported or other error condition
4298 */
4299 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4300 struct intel_plane_state *plane_state)
4301 {
4302
4303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4304 struct intel_plane *intel_plane =
4305 to_intel_plane(plane_state->base.plane);
4306 struct drm_framebuffer *fb = plane_state->base.fb;
4307 int ret;
4308
4309 bool force_detach = !fb || !plane_state->visible;
4310
4311 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4312 intel_plane->base.base.id, intel_crtc->pipe,
4313 drm_plane_index(&intel_plane->base));
4314
4315 ret = skl_update_scaler(crtc_state, force_detach,
4316 drm_plane_index(&intel_plane->base),
4317 &plane_state->scaler_id,
4318 plane_state->base.rotation,
4319 drm_rect_width(&plane_state->src) >> 16,
4320 drm_rect_height(&plane_state->src) >> 16,
4321 drm_rect_width(&plane_state->dst),
4322 drm_rect_height(&plane_state->dst));
4323
4324 if (ret || plane_state->scaler_id < 0)
4325 return ret;
4326
4327 /* check colorkey */
4328 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4329 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4330 intel_plane->base.base.id);
4331 return -EINVAL;
4332 }
4333
4334 /* Check src format */
4335 switch (fb->pixel_format) {
4336 case DRM_FORMAT_RGB565:
4337 case DRM_FORMAT_XBGR8888:
4338 case DRM_FORMAT_XRGB8888:
4339 case DRM_FORMAT_ABGR8888:
4340 case DRM_FORMAT_ARGB8888:
4341 case DRM_FORMAT_XRGB2101010:
4342 case DRM_FORMAT_XBGR2101010:
4343 case DRM_FORMAT_YUYV:
4344 case DRM_FORMAT_YVYU:
4345 case DRM_FORMAT_UYVY:
4346 case DRM_FORMAT_VYUY:
4347 break;
4348 default:
4349 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4350 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4351 return -EINVAL;
4352 }
4353
4354 return 0;
4355 }
4356
4357 static void skylake_scaler_disable(struct intel_crtc *crtc)
4358 {
4359 int i;
4360
4361 for (i = 0; i < crtc->num_scalers; i++)
4362 skl_detach_scaler(crtc, i);
4363 }
4364
4365 static void skylake_pfit_enable(struct intel_crtc *crtc)
4366 {
4367 struct drm_device *dev = crtc->base.dev;
4368 struct drm_i915_private *dev_priv = dev->dev_private;
4369 int pipe = crtc->pipe;
4370 struct intel_crtc_scaler_state *scaler_state =
4371 &crtc->config->scaler_state;
4372
4373 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4374
4375 if (crtc->config->pch_pfit.enabled) {
4376 int id;
4377
4378 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4379 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4380 return;
4381 }
4382
4383 id = scaler_state->scaler_id;
4384 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4385 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4386 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4387 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4388
4389 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4390 }
4391 }
4392
4393 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4394 {
4395 struct drm_device *dev = crtc->base.dev;
4396 struct drm_i915_private *dev_priv = dev->dev_private;
4397 int pipe = crtc->pipe;
4398
4399 if (crtc->config->pch_pfit.enabled) {
4400 /* Force use of hard-coded filter coefficients
4401 * as some pre-programmed values are broken,
4402 * e.g. x201.
4403 */
4404 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4405 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4406 PF_PIPE_SEL_IVB(pipe));
4407 else
4408 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4409 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4410 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4411 }
4412 }
4413
4414 void hsw_enable_ips(struct intel_crtc *crtc)
4415 {
4416 struct drm_device *dev = crtc->base.dev;
4417 struct drm_i915_private *dev_priv = dev->dev_private;
4418
4419 if (!crtc->config->ips_enabled)
4420 return;
4421
4422 /*
4423 * We can only enable IPS after we enable a plane and wait for a vblank
4424 * This function is called from post_plane_update, which is run after
4425 * a vblank wait.
4426 */
4427
4428 assert_plane_enabled(dev_priv, crtc->plane);
4429 if (IS_BROADWELL(dev)) {
4430 mutex_lock(&dev_priv->rps.hw_lock);
4431 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4432 mutex_unlock(&dev_priv->rps.hw_lock);
4433 /* Quoting Art Runyan: "its not safe to expect any particular
4434 * value in IPS_CTL bit 31 after enabling IPS through the
4435 * mailbox." Moreover, the mailbox may return a bogus state,
4436 * so we need to just enable it and continue on.
4437 */
4438 } else {
4439 I915_WRITE(IPS_CTL, IPS_ENABLE);
4440 /* The bit only becomes 1 in the next vblank, so this wait here
4441 * is essentially intel_wait_for_vblank. If we don't have this
4442 * and don't wait for vblanks until the end of crtc_enable, then
4443 * the HW state readout code will complain that the expected
4444 * IPS_CTL value is not the one we read. */
4445 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4446 DRM_ERROR("Timed out waiting for IPS enable\n");
4447 }
4448 }
4449
4450 void hsw_disable_ips(struct intel_crtc *crtc)
4451 {
4452 struct drm_device *dev = crtc->base.dev;
4453 struct drm_i915_private *dev_priv = dev->dev_private;
4454
4455 if (!crtc->config->ips_enabled)
4456 return;
4457
4458 assert_plane_enabled(dev_priv, crtc->plane);
4459 if (IS_BROADWELL(dev)) {
4460 mutex_lock(&dev_priv->rps.hw_lock);
4461 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4462 mutex_unlock(&dev_priv->rps.hw_lock);
4463 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4464 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4465 DRM_ERROR("Timed out waiting for IPS disable\n");
4466 } else {
4467 I915_WRITE(IPS_CTL, 0);
4468 POSTING_READ(IPS_CTL);
4469 }
4470
4471 /* We need to wait for a vblank before we can disable the plane. */
4472 intel_wait_for_vblank(dev, crtc->pipe);
4473 }
4474
4475 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4476 {
4477 if (intel_crtc->overlay) {
4478 struct drm_device *dev = intel_crtc->base.dev;
4479 struct drm_i915_private *dev_priv = dev->dev_private;
4480
4481 mutex_lock(&dev->struct_mutex);
4482 dev_priv->mm.interruptible = false;
4483 (void) intel_overlay_switch_off(intel_crtc->overlay);
4484 dev_priv->mm.interruptible = true;
4485 mutex_unlock(&dev->struct_mutex);
4486 }
4487
4488 /* Let userspace switch the overlay on again. In most cases userspace
4489 * has to recompute where to put it anyway.
4490 */
4491 }
4492
4493 /**
4494 * intel_post_enable_primary - Perform operations after enabling primary plane
4495 * @crtc: the CRTC whose primary plane was just enabled
4496 *
4497 * Performs potentially sleeping operations that must be done after the primary
4498 * plane is enabled, such as updating FBC and IPS. Note that this may be
4499 * called due to an explicit primary plane update, or due to an implicit
4500 * re-enable that is caused when a sprite plane is updated to no longer
4501 * completely hide the primary plane.
4502 */
4503 static void
4504 intel_post_enable_primary(struct drm_crtc *crtc)
4505 {
4506 struct drm_device *dev = crtc->dev;
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4509 int pipe = intel_crtc->pipe;
4510
4511 /*
4512 * FIXME IPS should be fine as long as one plane is
4513 * enabled, but in practice it seems to have problems
4514 * when going from primary only to sprite only and vice
4515 * versa.
4516 */
4517 hsw_enable_ips(intel_crtc);
4518
4519 /*
4520 * Gen2 reports pipe underruns whenever all planes are disabled.
4521 * So don't enable underrun reporting before at least some planes
4522 * are enabled.
4523 * FIXME: Need to fix the logic to work when we turn off all planes
4524 * but leave the pipe running.
4525 */
4526 if (IS_GEN2(dev))
4527 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4528
4529 /* Underruns don't always raise interrupts, so check manually. */
4530 intel_check_cpu_fifo_underruns(dev_priv);
4531 intel_check_pch_fifo_underruns(dev_priv);
4532 }
4533
4534 /* FIXME move all this to pre_plane_update() with proper state tracking */
4535 static void
4536 intel_pre_disable_primary(struct drm_crtc *crtc)
4537 {
4538 struct drm_device *dev = crtc->dev;
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4541 int pipe = intel_crtc->pipe;
4542
4543 /*
4544 * Gen2 reports pipe underruns whenever all planes are disabled.
4545 * So diasble underrun reporting before all the planes get disabled.
4546 * FIXME: Need to fix the logic to work when we turn off all planes
4547 * but leave the pipe running.
4548 */
4549 if (IS_GEN2(dev))
4550 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4551
4552 /*
4553 * FIXME IPS should be fine as long as one plane is
4554 * enabled, but in practice it seems to have problems
4555 * when going from primary only to sprite only and vice
4556 * versa.
4557 */
4558 hsw_disable_ips(intel_crtc);
4559 }
4560
4561 /* FIXME get rid of this and use pre_plane_update */
4562 static void
4563 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4564 {
4565 struct drm_device *dev = crtc->dev;
4566 struct drm_i915_private *dev_priv = dev->dev_private;
4567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4568 int pipe = intel_crtc->pipe;
4569
4570 intel_pre_disable_primary(crtc);
4571
4572 /*
4573 * Vblank time updates from the shadow to live plane control register
4574 * are blocked if the memory self-refresh mode is active at that
4575 * moment. So to make sure the plane gets truly disabled, disable
4576 * first the self-refresh mode. The self-refresh enable bit in turn
4577 * will be checked/applied by the HW only at the next frame start
4578 * event which is after the vblank start event, so we need to have a
4579 * wait-for-vblank between disabling the plane and the pipe.
4580 */
4581 if (HAS_GMCH_DISPLAY(dev)) {
4582 intel_set_memory_cxsr(dev_priv, false);
4583 dev_priv->wm.vlv.cxsr = false;
4584 intel_wait_for_vblank(dev, pipe);
4585 }
4586 }
4587
4588 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4589 {
4590 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4591 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4592 struct intel_crtc_state *pipe_config =
4593 to_intel_crtc_state(crtc->base.state);
4594 struct drm_device *dev = crtc->base.dev;
4595 struct drm_plane *primary = crtc->base.primary;
4596 struct drm_plane_state *old_pri_state =
4597 drm_atomic_get_existing_plane_state(old_state, primary);
4598
4599 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4600
4601 crtc->wm.cxsr_allowed = true;
4602
4603 if (pipe_config->update_wm_post && pipe_config->base.active)
4604 intel_update_watermarks(&crtc->base);
4605
4606 if (old_pri_state) {
4607 struct intel_plane_state *primary_state =
4608 to_intel_plane_state(primary->state);
4609 struct intel_plane_state *old_primary_state =
4610 to_intel_plane_state(old_pri_state);
4611
4612 intel_fbc_post_update(crtc);
4613
4614 if (primary_state->visible &&
4615 (needs_modeset(&pipe_config->base) ||
4616 !old_primary_state->visible))
4617 intel_post_enable_primary(&crtc->base);
4618 }
4619 }
4620
4621 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4622 {
4623 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4624 struct drm_device *dev = crtc->base.dev;
4625 struct drm_i915_private *dev_priv = dev->dev_private;
4626 struct intel_crtc_state *pipe_config =
4627 to_intel_crtc_state(crtc->base.state);
4628 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4629 struct drm_plane *primary = crtc->base.primary;
4630 struct drm_plane_state *old_pri_state =
4631 drm_atomic_get_existing_plane_state(old_state, primary);
4632 bool modeset = needs_modeset(&pipe_config->base);
4633
4634 if (old_pri_state) {
4635 struct intel_plane_state *primary_state =
4636 to_intel_plane_state(primary->state);
4637 struct intel_plane_state *old_primary_state =
4638 to_intel_plane_state(old_pri_state);
4639
4640 intel_fbc_pre_update(crtc);
4641
4642 if (old_primary_state->visible &&
4643 (modeset || !primary_state->visible))
4644 intel_pre_disable_primary(&crtc->base);
4645 }
4646
4647 if (pipe_config->disable_cxsr) {
4648 crtc->wm.cxsr_allowed = false;
4649
4650 /*
4651 * Vblank time updates from the shadow to live plane control register
4652 * are blocked if the memory self-refresh mode is active at that
4653 * moment. So to make sure the plane gets truly disabled, disable
4654 * first the self-refresh mode. The self-refresh enable bit in turn
4655 * will be checked/applied by the HW only at the next frame start
4656 * event which is after the vblank start event, so we need to have a
4657 * wait-for-vblank between disabling the plane and the pipe.
4658 */
4659 if (old_crtc_state->base.active) {
4660 intel_set_memory_cxsr(dev_priv, false);
4661 dev_priv->wm.vlv.cxsr = false;
4662 intel_wait_for_vblank(dev, crtc->pipe);
4663 }
4664 }
4665
4666 /*
4667 * IVB workaround: must disable low power watermarks for at least
4668 * one frame before enabling scaling. LP watermarks can be re-enabled
4669 * when scaling is disabled.
4670 *
4671 * WaCxSRDisabledForSpriteScaling:ivb
4672 */
4673 if (pipe_config->disable_lp_wm) {
4674 ilk_disable_lp_wm(dev);
4675 intel_wait_for_vblank(dev, crtc->pipe);
4676 }
4677
4678 /*
4679 * If we're doing a modeset, we're done. No need to do any pre-vblank
4680 * watermark programming here.
4681 */
4682 if (needs_modeset(&pipe_config->base))
4683 return;
4684
4685 /*
4686 * For platforms that support atomic watermarks, program the
4687 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4688 * will be the intermediate values that are safe for both pre- and
4689 * post- vblank; when vblank happens, the 'active' values will be set
4690 * to the final 'target' values and we'll do this again to get the
4691 * optimal watermarks. For gen9+ platforms, the values we program here
4692 * will be the final target values which will get automatically latched
4693 * at vblank time; no further programming will be necessary.
4694 *
4695 * If a platform hasn't been transitioned to atomic watermarks yet,
4696 * we'll continue to update watermarks the old way, if flags tell
4697 * us to.
4698 */
4699 if (dev_priv->display.initial_watermarks != NULL)
4700 dev_priv->display.initial_watermarks(pipe_config);
4701 else if (pipe_config->update_wm_pre)
4702 intel_update_watermarks(&crtc->base);
4703 }
4704
4705 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4706 {
4707 struct drm_device *dev = crtc->dev;
4708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709 struct drm_plane *p;
4710 int pipe = intel_crtc->pipe;
4711
4712 intel_crtc_dpms_overlay_disable(intel_crtc);
4713
4714 drm_for_each_plane_mask(p, dev, plane_mask)
4715 to_intel_plane(p)->disable_plane(p, crtc);
4716
4717 /*
4718 * FIXME: Once we grow proper nuclear flip support out of this we need
4719 * to compute the mask of flip planes precisely. For the time being
4720 * consider this a flip to a NULL plane.
4721 */
4722 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4723 }
4724
4725 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4726 {
4727 struct drm_device *dev = crtc->dev;
4728 struct drm_i915_private *dev_priv = dev->dev_private;
4729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4730 struct intel_encoder *encoder;
4731 int pipe = intel_crtc->pipe;
4732 struct intel_crtc_state *pipe_config =
4733 to_intel_crtc_state(crtc->state);
4734
4735 if (WARN_ON(intel_crtc->active))
4736 return;
4737
4738 /*
4739 * Sometimes spurious CPU pipe underruns happen during FDI
4740 * training, at least with VGA+HDMI cloning. Suppress them.
4741 *
4742 * On ILK we get an occasional spurious CPU pipe underruns
4743 * between eDP port A enable and vdd enable. Also PCH port
4744 * enable seems to result in the occasional CPU pipe underrun.
4745 *
4746 * Spurious PCH underruns also occur during PCH enabling.
4747 */
4748 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4749 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4750 if (intel_crtc->config->has_pch_encoder)
4751 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4752
4753 if (intel_crtc->config->has_pch_encoder)
4754 intel_prepare_shared_dpll(intel_crtc);
4755
4756 if (intel_crtc->config->has_dp_encoder)
4757 intel_dp_set_m_n(intel_crtc, M1_N1);
4758
4759 intel_set_pipe_timings(intel_crtc);
4760 intel_set_pipe_src_size(intel_crtc);
4761
4762 if (intel_crtc->config->has_pch_encoder) {
4763 intel_cpu_transcoder_set_m_n(intel_crtc,
4764 &intel_crtc->config->fdi_m_n, NULL);
4765 }
4766
4767 ironlake_set_pipeconf(crtc);
4768
4769 intel_crtc->active = true;
4770
4771 for_each_encoder_on_crtc(dev, crtc, encoder)
4772 if (encoder->pre_enable)
4773 encoder->pre_enable(encoder);
4774
4775 if (intel_crtc->config->has_pch_encoder) {
4776 /* Note: FDI PLL enabling _must_ be done before we enable the
4777 * cpu pipes, hence this is separate from all the other fdi/pch
4778 * enabling. */
4779 ironlake_fdi_pll_enable(intel_crtc);
4780 } else {
4781 assert_fdi_tx_disabled(dev_priv, pipe);
4782 assert_fdi_rx_disabled(dev_priv, pipe);
4783 }
4784
4785 ironlake_pfit_enable(intel_crtc);
4786
4787 /*
4788 * On ILK+ LUT must be loaded before the pipe is running but with
4789 * clocks enabled
4790 */
4791 intel_color_load_luts(&pipe_config->base);
4792
4793 if (dev_priv->display.initial_watermarks != NULL)
4794 dev_priv->display.initial_watermarks(intel_crtc->config);
4795 intel_enable_pipe(intel_crtc);
4796
4797 if (intel_crtc->config->has_pch_encoder)
4798 ironlake_pch_enable(crtc);
4799
4800 assert_vblank_disabled(crtc);
4801 drm_crtc_vblank_on(crtc);
4802
4803 for_each_encoder_on_crtc(dev, crtc, encoder)
4804 encoder->enable(encoder);
4805
4806 if (HAS_PCH_CPT(dev))
4807 cpt_verify_modeset(dev, intel_crtc->pipe);
4808
4809 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4810 if (intel_crtc->config->has_pch_encoder)
4811 intel_wait_for_vblank(dev, pipe);
4812 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4813 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4814 }
4815
4816 /* IPS only exists on ULT machines and is tied to pipe A. */
4817 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4818 {
4819 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4820 }
4821
4822 static void haswell_crtc_enable(struct drm_crtc *crtc)
4823 {
4824 struct drm_device *dev = crtc->dev;
4825 struct drm_i915_private *dev_priv = dev->dev_private;
4826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4827 struct intel_encoder *encoder;
4828 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4829 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4830 struct intel_crtc_state *pipe_config =
4831 to_intel_crtc_state(crtc->state);
4832
4833 if (WARN_ON(intel_crtc->active))
4834 return;
4835
4836 if (intel_crtc->config->has_pch_encoder)
4837 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4838 false);
4839
4840 if (intel_crtc->config->shared_dpll)
4841 intel_enable_shared_dpll(intel_crtc);
4842
4843 if (intel_crtc->config->has_dp_encoder)
4844 intel_dp_set_m_n(intel_crtc, M1_N1);
4845
4846 if (!intel_crtc->config->has_dsi_encoder)
4847 intel_set_pipe_timings(intel_crtc);
4848
4849 intel_set_pipe_src_size(intel_crtc);
4850
4851 if (cpu_transcoder != TRANSCODER_EDP &&
4852 !transcoder_is_dsi(cpu_transcoder)) {
4853 I915_WRITE(PIPE_MULT(cpu_transcoder),
4854 intel_crtc->config->pixel_multiplier - 1);
4855 }
4856
4857 if (intel_crtc->config->has_pch_encoder) {
4858 intel_cpu_transcoder_set_m_n(intel_crtc,
4859 &intel_crtc->config->fdi_m_n, NULL);
4860 }
4861
4862 if (!intel_crtc->config->has_dsi_encoder)
4863 haswell_set_pipeconf(crtc);
4864
4865 haswell_set_pipemisc(crtc);
4866
4867 intel_color_set_csc(&pipe_config->base);
4868
4869 intel_crtc->active = true;
4870
4871 if (intel_crtc->config->has_pch_encoder)
4872 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4873 else
4874 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4875
4876 for_each_encoder_on_crtc(dev, crtc, encoder) {
4877 if (encoder->pre_enable)
4878 encoder->pre_enable(encoder);
4879 }
4880
4881 if (intel_crtc->config->has_pch_encoder)
4882 dev_priv->display.fdi_link_train(crtc);
4883
4884 if (!intel_crtc->config->has_dsi_encoder)
4885 intel_ddi_enable_pipe_clock(intel_crtc);
4886
4887 if (INTEL_INFO(dev)->gen >= 9)
4888 skylake_pfit_enable(intel_crtc);
4889 else
4890 ironlake_pfit_enable(intel_crtc);
4891
4892 /*
4893 * On ILK+ LUT must be loaded before the pipe is running but with
4894 * clocks enabled
4895 */
4896 intel_color_load_luts(&pipe_config->base);
4897
4898 intel_ddi_set_pipe_settings(crtc);
4899 if (!intel_crtc->config->has_dsi_encoder)
4900 intel_ddi_enable_transcoder_func(crtc);
4901
4902 if (dev_priv->display.initial_watermarks != NULL)
4903 dev_priv->display.initial_watermarks(pipe_config);
4904 else
4905 intel_update_watermarks(crtc);
4906
4907 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4908 if (!intel_crtc->config->has_dsi_encoder)
4909 intel_enable_pipe(intel_crtc);
4910
4911 if (intel_crtc->config->has_pch_encoder)
4912 lpt_pch_enable(crtc);
4913
4914 if (intel_crtc->config->dp_encoder_is_mst)
4915 intel_ddi_set_vc_payload_alloc(crtc, true);
4916
4917 assert_vblank_disabled(crtc);
4918 drm_crtc_vblank_on(crtc);
4919
4920 for_each_encoder_on_crtc(dev, crtc, encoder) {
4921 encoder->enable(encoder);
4922 intel_opregion_notify_encoder(encoder, true);
4923 }
4924
4925 if (intel_crtc->config->has_pch_encoder) {
4926 intel_wait_for_vblank(dev, pipe);
4927 intel_wait_for_vblank(dev, pipe);
4928 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4929 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4930 true);
4931 }
4932
4933 /* If we change the relative order between pipe/planes enabling, we need
4934 * to change the workaround. */
4935 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4936 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4937 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4938 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4939 }
4940 }
4941
4942 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4943 {
4944 struct drm_device *dev = crtc->base.dev;
4945 struct drm_i915_private *dev_priv = dev->dev_private;
4946 int pipe = crtc->pipe;
4947
4948 /* To avoid upsetting the power well on haswell only disable the pfit if
4949 * it's in use. The hw state code will make sure we get this right. */
4950 if (force || crtc->config->pch_pfit.enabled) {
4951 I915_WRITE(PF_CTL(pipe), 0);
4952 I915_WRITE(PF_WIN_POS(pipe), 0);
4953 I915_WRITE(PF_WIN_SZ(pipe), 0);
4954 }
4955 }
4956
4957 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4958 {
4959 struct drm_device *dev = crtc->dev;
4960 struct drm_i915_private *dev_priv = dev->dev_private;
4961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4962 struct intel_encoder *encoder;
4963 int pipe = intel_crtc->pipe;
4964
4965 /*
4966 * Sometimes spurious CPU pipe underruns happen when the
4967 * pipe is already disabled, but FDI RX/TX is still enabled.
4968 * Happens at least with VGA+HDMI cloning. Suppress them.
4969 */
4970 if (intel_crtc->config->has_pch_encoder) {
4971 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4972 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4973 }
4974
4975 for_each_encoder_on_crtc(dev, crtc, encoder)
4976 encoder->disable(encoder);
4977
4978 drm_crtc_vblank_off(crtc);
4979 assert_vblank_disabled(crtc);
4980
4981 intel_disable_pipe(intel_crtc);
4982
4983 ironlake_pfit_disable(intel_crtc, false);
4984
4985 if (intel_crtc->config->has_pch_encoder)
4986 ironlake_fdi_disable(crtc);
4987
4988 for_each_encoder_on_crtc(dev, crtc, encoder)
4989 if (encoder->post_disable)
4990 encoder->post_disable(encoder);
4991
4992 if (intel_crtc->config->has_pch_encoder) {
4993 ironlake_disable_pch_transcoder(dev_priv, pipe);
4994
4995 if (HAS_PCH_CPT(dev)) {
4996 i915_reg_t reg;
4997 u32 temp;
4998
4999 /* disable TRANS_DP_CTL */
5000 reg = TRANS_DP_CTL(pipe);
5001 temp = I915_READ(reg);
5002 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5003 TRANS_DP_PORT_SEL_MASK);
5004 temp |= TRANS_DP_PORT_SEL_NONE;
5005 I915_WRITE(reg, temp);
5006
5007 /* disable DPLL_SEL */
5008 temp = I915_READ(PCH_DPLL_SEL);
5009 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5010 I915_WRITE(PCH_DPLL_SEL, temp);
5011 }
5012
5013 ironlake_fdi_pll_disable(intel_crtc);
5014 }
5015
5016 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5017 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5018 }
5019
5020 static void haswell_crtc_disable(struct drm_crtc *crtc)
5021 {
5022 struct drm_device *dev = crtc->dev;
5023 struct drm_i915_private *dev_priv = dev->dev_private;
5024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5025 struct intel_encoder *encoder;
5026 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5027
5028 if (intel_crtc->config->has_pch_encoder)
5029 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5030 false);
5031
5032 for_each_encoder_on_crtc(dev, crtc, encoder) {
5033 intel_opregion_notify_encoder(encoder, false);
5034 encoder->disable(encoder);
5035 }
5036
5037 drm_crtc_vblank_off(crtc);
5038 assert_vblank_disabled(crtc);
5039
5040 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5041 if (!intel_crtc->config->has_dsi_encoder)
5042 intel_disable_pipe(intel_crtc);
5043
5044 if (intel_crtc->config->dp_encoder_is_mst)
5045 intel_ddi_set_vc_payload_alloc(crtc, false);
5046
5047 if (!intel_crtc->config->has_dsi_encoder)
5048 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5049
5050 if (INTEL_INFO(dev)->gen >= 9)
5051 skylake_scaler_disable(intel_crtc);
5052 else
5053 ironlake_pfit_disable(intel_crtc, false);
5054
5055 if (!intel_crtc->config->has_dsi_encoder)
5056 intel_ddi_disable_pipe_clock(intel_crtc);
5057
5058 for_each_encoder_on_crtc(dev, crtc, encoder)
5059 if (encoder->post_disable)
5060 encoder->post_disable(encoder);
5061
5062 if (intel_crtc->config->has_pch_encoder) {
5063 lpt_disable_pch_transcoder(dev_priv);
5064 lpt_disable_iclkip(dev_priv);
5065 intel_ddi_fdi_disable(crtc);
5066
5067 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5068 true);
5069 }
5070 }
5071
5072 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5073 {
5074 struct drm_device *dev = crtc->base.dev;
5075 struct drm_i915_private *dev_priv = dev->dev_private;
5076 struct intel_crtc_state *pipe_config = crtc->config;
5077
5078 if (!pipe_config->gmch_pfit.control)
5079 return;
5080
5081 /*
5082 * The panel fitter should only be adjusted whilst the pipe is disabled,
5083 * according to register description and PRM.
5084 */
5085 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5086 assert_pipe_disabled(dev_priv, crtc->pipe);
5087
5088 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5089 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5090
5091 /* Border color in case we don't scale up to the full screen. Black by
5092 * default, change to something else for debugging. */
5093 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5094 }
5095
5096 static enum intel_display_power_domain port_to_power_domain(enum port port)
5097 {
5098 switch (port) {
5099 case PORT_A:
5100 return POWER_DOMAIN_PORT_DDI_A_LANES;
5101 case PORT_B:
5102 return POWER_DOMAIN_PORT_DDI_B_LANES;
5103 case PORT_C:
5104 return POWER_DOMAIN_PORT_DDI_C_LANES;
5105 case PORT_D:
5106 return POWER_DOMAIN_PORT_DDI_D_LANES;
5107 case PORT_E:
5108 return POWER_DOMAIN_PORT_DDI_E_LANES;
5109 default:
5110 MISSING_CASE(port);
5111 return POWER_DOMAIN_PORT_OTHER;
5112 }
5113 }
5114
5115 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5116 {
5117 switch (port) {
5118 case PORT_A:
5119 return POWER_DOMAIN_AUX_A;
5120 case PORT_B:
5121 return POWER_DOMAIN_AUX_B;
5122 case PORT_C:
5123 return POWER_DOMAIN_AUX_C;
5124 case PORT_D:
5125 return POWER_DOMAIN_AUX_D;
5126 case PORT_E:
5127 /* FIXME: Check VBT for actual wiring of PORT E */
5128 return POWER_DOMAIN_AUX_D;
5129 default:
5130 MISSING_CASE(port);
5131 return POWER_DOMAIN_AUX_A;
5132 }
5133 }
5134
5135 enum intel_display_power_domain
5136 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5137 {
5138 struct drm_device *dev = intel_encoder->base.dev;
5139 struct intel_digital_port *intel_dig_port;
5140
5141 switch (intel_encoder->type) {
5142 case INTEL_OUTPUT_UNKNOWN:
5143 /* Only DDI platforms should ever use this output type */
5144 WARN_ON_ONCE(!HAS_DDI(dev));
5145 case INTEL_OUTPUT_DISPLAYPORT:
5146 case INTEL_OUTPUT_HDMI:
5147 case INTEL_OUTPUT_EDP:
5148 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5149 return port_to_power_domain(intel_dig_port->port);
5150 case INTEL_OUTPUT_DP_MST:
5151 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5152 return port_to_power_domain(intel_dig_port->port);
5153 case INTEL_OUTPUT_ANALOG:
5154 return POWER_DOMAIN_PORT_CRT;
5155 case INTEL_OUTPUT_DSI:
5156 return POWER_DOMAIN_PORT_DSI;
5157 default:
5158 return POWER_DOMAIN_PORT_OTHER;
5159 }
5160 }
5161
5162 enum intel_display_power_domain
5163 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5164 {
5165 struct drm_device *dev = intel_encoder->base.dev;
5166 struct intel_digital_port *intel_dig_port;
5167
5168 switch (intel_encoder->type) {
5169 case INTEL_OUTPUT_UNKNOWN:
5170 case INTEL_OUTPUT_HDMI:
5171 /*
5172 * Only DDI platforms should ever use these output types.
5173 * We can get here after the HDMI detect code has already set
5174 * the type of the shared encoder. Since we can't be sure
5175 * what's the status of the given connectors, play safe and
5176 * run the DP detection too.
5177 */
5178 WARN_ON_ONCE(!HAS_DDI(dev));
5179 case INTEL_OUTPUT_DISPLAYPORT:
5180 case INTEL_OUTPUT_EDP:
5181 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5182 return port_to_aux_power_domain(intel_dig_port->port);
5183 case INTEL_OUTPUT_DP_MST:
5184 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5185 return port_to_aux_power_domain(intel_dig_port->port);
5186 default:
5187 MISSING_CASE(intel_encoder->type);
5188 return POWER_DOMAIN_AUX_A;
5189 }
5190 }
5191
5192 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5193 struct intel_crtc_state *crtc_state)
5194 {
5195 struct drm_device *dev = crtc->dev;
5196 struct drm_encoder *encoder;
5197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5198 enum pipe pipe = intel_crtc->pipe;
5199 unsigned long mask;
5200 enum transcoder transcoder = crtc_state->cpu_transcoder;
5201
5202 if (!crtc_state->base.active)
5203 return 0;
5204
5205 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5206 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5207 if (crtc_state->pch_pfit.enabled ||
5208 crtc_state->pch_pfit.force_thru)
5209 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5210
5211 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5212 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5213
5214 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5215 }
5216
5217 if (crtc_state->shared_dpll)
5218 mask |= BIT(POWER_DOMAIN_PLLS);
5219
5220 return mask;
5221 }
5222
5223 static unsigned long
5224 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5225 struct intel_crtc_state *crtc_state)
5226 {
5227 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5229 enum intel_display_power_domain domain;
5230 unsigned long domains, new_domains, old_domains;
5231
5232 old_domains = intel_crtc->enabled_power_domains;
5233 intel_crtc->enabled_power_domains = new_domains =
5234 get_crtc_power_domains(crtc, crtc_state);
5235
5236 domains = new_domains & ~old_domains;
5237
5238 for_each_power_domain(domain, domains)
5239 intel_display_power_get(dev_priv, domain);
5240
5241 return old_domains & ~new_domains;
5242 }
5243
5244 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5245 unsigned long domains)
5246 {
5247 enum intel_display_power_domain domain;
5248
5249 for_each_power_domain(domain, domains)
5250 intel_display_power_put(dev_priv, domain);
5251 }
5252
5253 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5254 {
5255 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5256
5257 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5258 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5259 return max_cdclk_freq;
5260 else if (IS_CHERRYVIEW(dev_priv))
5261 return max_cdclk_freq*95/100;
5262 else if (INTEL_INFO(dev_priv)->gen < 4)
5263 return 2*max_cdclk_freq*90/100;
5264 else
5265 return max_cdclk_freq*90/100;
5266 }
5267
5268 static void intel_update_max_cdclk(struct drm_device *dev)
5269 {
5270 struct drm_i915_private *dev_priv = dev->dev_private;
5271
5272 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5273 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5274
5275 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5276 dev_priv->max_cdclk_freq = 675000;
5277 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5278 dev_priv->max_cdclk_freq = 540000;
5279 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5280 dev_priv->max_cdclk_freq = 450000;
5281 else
5282 dev_priv->max_cdclk_freq = 337500;
5283 } else if (IS_BROXTON(dev)) {
5284 dev_priv->max_cdclk_freq = 624000;
5285 } else if (IS_BROADWELL(dev)) {
5286 /*
5287 * FIXME with extra cooling we can allow
5288 * 540 MHz for ULX and 675 Mhz for ULT.
5289 * How can we know if extra cooling is
5290 * available? PCI ID, VTB, something else?
5291 */
5292 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5293 dev_priv->max_cdclk_freq = 450000;
5294 else if (IS_BDW_ULX(dev))
5295 dev_priv->max_cdclk_freq = 450000;
5296 else if (IS_BDW_ULT(dev))
5297 dev_priv->max_cdclk_freq = 540000;
5298 else
5299 dev_priv->max_cdclk_freq = 675000;
5300 } else if (IS_CHERRYVIEW(dev)) {
5301 dev_priv->max_cdclk_freq = 320000;
5302 } else if (IS_VALLEYVIEW(dev)) {
5303 dev_priv->max_cdclk_freq = 400000;
5304 } else {
5305 /* otherwise assume cdclk is fixed */
5306 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5307 }
5308
5309 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5310
5311 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5312 dev_priv->max_cdclk_freq);
5313
5314 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5315 dev_priv->max_dotclk_freq);
5316 }
5317
5318 static void intel_update_cdclk(struct drm_device *dev)
5319 {
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5321
5322 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5323 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5324 dev_priv->cdclk_freq);
5325
5326 /*
5327 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5328 * Programmng [sic] note: bit[9:2] should be programmed to the number
5329 * of cdclk that generates 4MHz reference clock freq which is used to
5330 * generate GMBus clock. This will vary with the cdclk freq.
5331 */
5332 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5333 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5334
5335 if (dev_priv->max_cdclk_freq == 0)
5336 intel_update_max_cdclk(dev);
5337 }
5338
5339 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
5340 {
5341 uint32_t divider;
5342 uint32_t ratio;
5343 uint32_t current_freq;
5344 int ret;
5345
5346 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5347 switch (frequency) {
5348 case 144000:
5349 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5350 ratio = BXT_DE_PLL_RATIO(60);
5351 break;
5352 case 288000:
5353 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5354 ratio = BXT_DE_PLL_RATIO(60);
5355 break;
5356 case 384000:
5357 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5358 ratio = BXT_DE_PLL_RATIO(60);
5359 break;
5360 case 576000:
5361 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5362 ratio = BXT_DE_PLL_RATIO(60);
5363 break;
5364 case 624000:
5365 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5366 ratio = BXT_DE_PLL_RATIO(65);
5367 break;
5368 case 19200:
5369 /*
5370 * Bypass frequency with DE PLL disabled. Init ratio, divider
5371 * to suppress GCC warning.
5372 */
5373 ratio = 0;
5374 divider = 0;
5375 break;
5376 default:
5377 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5378
5379 return;
5380 }
5381
5382 mutex_lock(&dev_priv->rps.hw_lock);
5383 /* Inform power controller of upcoming frequency change */
5384 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5385 0x80000000);
5386 mutex_unlock(&dev_priv->rps.hw_lock);
5387
5388 if (ret) {
5389 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5390 ret, frequency);
5391 return;
5392 }
5393
5394 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5395 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5396 current_freq = current_freq * 500 + 1000;
5397
5398 /*
5399 * DE PLL has to be disabled when
5400 * - setting to 19.2MHz (bypass, PLL isn't used)
5401 * - before setting to 624MHz (PLL needs toggling)
5402 * - before setting to any frequency from 624MHz (PLL needs toggling)
5403 */
5404 if (frequency == 19200 || frequency == 624000 ||
5405 current_freq == 624000) {
5406 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5407 /* Timeout 200us */
5408 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5409 1))
5410 DRM_ERROR("timout waiting for DE PLL unlock\n");
5411 }
5412
5413 if (frequency != 19200) {
5414 uint32_t val;
5415
5416 val = I915_READ(BXT_DE_PLL_CTL);
5417 val &= ~BXT_DE_PLL_RATIO_MASK;
5418 val |= ratio;
5419 I915_WRITE(BXT_DE_PLL_CTL, val);
5420
5421 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5422 /* Timeout 200us */
5423 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5424 DRM_ERROR("timeout waiting for DE PLL lock\n");
5425
5426 val = I915_READ(CDCLK_CTL);
5427 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5428 val |= divider;
5429 /*
5430 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5431 * enable otherwise.
5432 */
5433 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5434 if (frequency >= 500000)
5435 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5436
5437 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5438 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5439 val |= (frequency - 1000) / 500;
5440 I915_WRITE(CDCLK_CTL, val);
5441 }
5442
5443 mutex_lock(&dev_priv->rps.hw_lock);
5444 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5445 DIV_ROUND_UP(frequency, 25000));
5446 mutex_unlock(&dev_priv->rps.hw_lock);
5447
5448 if (ret) {
5449 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5450 ret, frequency);
5451 return;
5452 }
5453
5454 intel_update_cdclk(dev_priv->dev);
5455 }
5456
5457 static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
5458 {
5459 if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
5460 return false;
5461
5462 /* TODO: Check for a valid CDCLK rate */
5463
5464 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
5465 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
5466
5467 return false;
5468 }
5469
5470 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
5471 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
5472
5473 return false;
5474 }
5475
5476 return true;
5477 }
5478
5479 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
5480 {
5481 return broxton_cdclk_is_enabled(dev_priv);
5482 }
5483
5484 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5485 {
5486 /* check if cd clock is enabled */
5487 if (broxton_cdclk_is_enabled(dev_priv)) {
5488 DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
5489 return;
5490 }
5491
5492 DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
5493
5494 /*
5495 * FIXME:
5496 * - The initial CDCLK needs to be read from VBT.
5497 * Need to make this change after VBT has changes for BXT.
5498 * - check if setting the max (or any) cdclk freq is really necessary
5499 * here, it belongs to modeset time
5500 */
5501 broxton_set_cdclk(dev_priv, 624000);
5502
5503 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5504 POSTING_READ(DBUF_CTL);
5505
5506 udelay(10);
5507
5508 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5509 DRM_ERROR("DBuf power enable timeout!\n");
5510 }
5511
5512 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5513 {
5514 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5515 POSTING_READ(DBUF_CTL);
5516
5517 udelay(10);
5518
5519 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5520 DRM_ERROR("DBuf power disable timeout!\n");
5521
5522 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5523 broxton_set_cdclk(dev_priv, 19200);
5524 }
5525
5526 static const struct skl_cdclk_entry {
5527 unsigned int freq;
5528 unsigned int vco;
5529 } skl_cdclk_frequencies[] = {
5530 { .freq = 308570, .vco = 8640 },
5531 { .freq = 337500, .vco = 8100 },
5532 { .freq = 432000, .vco = 8640 },
5533 { .freq = 450000, .vco = 8100 },
5534 { .freq = 540000, .vco = 8100 },
5535 { .freq = 617140, .vco = 8640 },
5536 { .freq = 675000, .vco = 8100 },
5537 };
5538
5539 static unsigned int skl_cdclk_decimal(unsigned int freq)
5540 {
5541 return (freq - 1000) / 500;
5542 }
5543
5544 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5545 {
5546 unsigned int i;
5547
5548 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5549 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5550
5551 if (e->freq == freq)
5552 return e->vco;
5553 }
5554
5555 return 8100;
5556 }
5557
5558 static void
5559 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5560 {
5561 unsigned int min_freq;
5562 u32 val;
5563
5564 /* select the minimum CDCLK before enabling DPLL 0 */
5565 val = I915_READ(CDCLK_CTL);
5566 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5567 val |= CDCLK_FREQ_337_308;
5568
5569 if (required_vco == 8640)
5570 min_freq = 308570;
5571 else
5572 min_freq = 337500;
5573
5574 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5575
5576 I915_WRITE(CDCLK_CTL, val);
5577 POSTING_READ(CDCLK_CTL);
5578
5579 /*
5580 * We always enable DPLL0 with the lowest link rate possible, but still
5581 * taking into account the VCO required to operate the eDP panel at the
5582 * desired frequency. The usual DP link rates operate with a VCO of
5583 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5584 * The modeset code is responsible for the selection of the exact link
5585 * rate later on, with the constraint of choosing a frequency that
5586 * works with required_vco.
5587 */
5588 val = I915_READ(DPLL_CTRL1);
5589
5590 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5591 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5592 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5593 if (required_vco == 8640)
5594 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5595 SKL_DPLL0);
5596 else
5597 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5598 SKL_DPLL0);
5599
5600 I915_WRITE(DPLL_CTRL1, val);
5601 POSTING_READ(DPLL_CTRL1);
5602
5603 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5604
5605 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5606 DRM_ERROR("DPLL0 not locked\n");
5607 }
5608
5609 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5610 {
5611 int ret;
5612 u32 val;
5613
5614 /* inform PCU we want to change CDCLK */
5615 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5616 mutex_lock(&dev_priv->rps.hw_lock);
5617 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5618 mutex_unlock(&dev_priv->rps.hw_lock);
5619
5620 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5621 }
5622
5623 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5624 {
5625 unsigned int i;
5626
5627 for (i = 0; i < 15; i++) {
5628 if (skl_cdclk_pcu_ready(dev_priv))
5629 return true;
5630 udelay(10);
5631 }
5632
5633 return false;
5634 }
5635
5636 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5637 {
5638 struct drm_device *dev = dev_priv->dev;
5639 u32 freq_select, pcu_ack;
5640
5641 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5642
5643 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5644 DRM_ERROR("failed to inform PCU about cdclk change\n");
5645 return;
5646 }
5647
5648 /* set CDCLK_CTL */
5649 switch(freq) {
5650 case 450000:
5651 case 432000:
5652 freq_select = CDCLK_FREQ_450_432;
5653 pcu_ack = 1;
5654 break;
5655 case 540000:
5656 freq_select = CDCLK_FREQ_540;
5657 pcu_ack = 2;
5658 break;
5659 case 308570:
5660 case 337500:
5661 default:
5662 freq_select = CDCLK_FREQ_337_308;
5663 pcu_ack = 0;
5664 break;
5665 case 617140:
5666 case 675000:
5667 freq_select = CDCLK_FREQ_675_617;
5668 pcu_ack = 3;
5669 break;
5670 }
5671
5672 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5673 POSTING_READ(CDCLK_CTL);
5674
5675 /* inform PCU of the change */
5676 mutex_lock(&dev_priv->rps.hw_lock);
5677 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5678 mutex_unlock(&dev_priv->rps.hw_lock);
5679
5680 intel_update_cdclk(dev);
5681 }
5682
5683 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5684 {
5685 /* disable DBUF power */
5686 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5687 POSTING_READ(DBUF_CTL);
5688
5689 udelay(10);
5690
5691 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5692 DRM_ERROR("DBuf power disable timeout\n");
5693
5694 /* disable DPLL0 */
5695 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5696 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5697 DRM_ERROR("Couldn't disable DPLL0\n");
5698 }
5699
5700 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5701 {
5702 unsigned int required_vco;
5703
5704 /* DPLL0 not enabled (happens on early BIOS versions) */
5705 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5706 /* enable DPLL0 */
5707 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5708 skl_dpll0_enable(dev_priv, required_vco);
5709 }
5710
5711 /* set CDCLK to the frequency the BIOS chose */
5712 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5713
5714 /* enable DBUF power */
5715 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5716 POSTING_READ(DBUF_CTL);
5717
5718 udelay(10);
5719
5720 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5721 DRM_ERROR("DBuf power enable timeout\n");
5722 }
5723
5724 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5725 {
5726 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5727 uint32_t cdctl = I915_READ(CDCLK_CTL);
5728 int freq = dev_priv->skl_boot_cdclk;
5729
5730 /*
5731 * check if the pre-os intialized the display
5732 * There is SWF18 scratchpad register defined which is set by the
5733 * pre-os which can be used by the OS drivers to check the status
5734 */
5735 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5736 goto sanitize;
5737
5738 /* Is PLL enabled and locked ? */
5739 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5740 goto sanitize;
5741
5742 /* DPLL okay; verify the cdclock
5743 *
5744 * Noticed in some instances that the freq selection is correct but
5745 * decimal part is programmed wrong from BIOS where pre-os does not
5746 * enable display. Verify the same as well.
5747 */
5748 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5749 /* All well; nothing to sanitize */
5750 return false;
5751 sanitize:
5752 /*
5753 * As of now initialize with max cdclk till
5754 * we get dynamic cdclk support
5755 * */
5756 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5757 skl_init_cdclk(dev_priv);
5758
5759 /* we did have to sanitize */
5760 return true;
5761 }
5762
5763 /* Adjust CDclk dividers to allow high res or save power if possible */
5764 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5765 {
5766 struct drm_i915_private *dev_priv = dev->dev_private;
5767 u32 val, cmd;
5768
5769 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5770 != dev_priv->cdclk_freq);
5771
5772 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5773 cmd = 2;
5774 else if (cdclk == 266667)
5775 cmd = 1;
5776 else
5777 cmd = 0;
5778
5779 mutex_lock(&dev_priv->rps.hw_lock);
5780 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5781 val &= ~DSPFREQGUAR_MASK;
5782 val |= (cmd << DSPFREQGUAR_SHIFT);
5783 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5784 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5785 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5786 50)) {
5787 DRM_ERROR("timed out waiting for CDclk change\n");
5788 }
5789 mutex_unlock(&dev_priv->rps.hw_lock);
5790
5791 mutex_lock(&dev_priv->sb_lock);
5792
5793 if (cdclk == 400000) {
5794 u32 divider;
5795
5796 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5797
5798 /* adjust cdclk divider */
5799 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5800 val &= ~CCK_FREQUENCY_VALUES;
5801 val |= divider;
5802 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5803
5804 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5805 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5806 50))
5807 DRM_ERROR("timed out waiting for CDclk change\n");
5808 }
5809
5810 /* adjust self-refresh exit latency value */
5811 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5812 val &= ~0x7f;
5813
5814 /*
5815 * For high bandwidth configs, we set a higher latency in the bunit
5816 * so that the core display fetch happens in time to avoid underruns.
5817 */
5818 if (cdclk == 400000)
5819 val |= 4500 / 250; /* 4.5 usec */
5820 else
5821 val |= 3000 / 250; /* 3.0 usec */
5822 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5823
5824 mutex_unlock(&dev_priv->sb_lock);
5825
5826 intel_update_cdclk(dev);
5827 }
5828
5829 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5830 {
5831 struct drm_i915_private *dev_priv = dev->dev_private;
5832 u32 val, cmd;
5833
5834 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5835 != dev_priv->cdclk_freq);
5836
5837 switch (cdclk) {
5838 case 333333:
5839 case 320000:
5840 case 266667:
5841 case 200000:
5842 break;
5843 default:
5844 MISSING_CASE(cdclk);
5845 return;
5846 }
5847
5848 /*
5849 * Specs are full of misinformation, but testing on actual
5850 * hardware has shown that we just need to write the desired
5851 * CCK divider into the Punit register.
5852 */
5853 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5854
5855 mutex_lock(&dev_priv->rps.hw_lock);
5856 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5857 val &= ~DSPFREQGUAR_MASK_CHV;
5858 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5859 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5860 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5861 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5862 50)) {
5863 DRM_ERROR("timed out waiting for CDclk change\n");
5864 }
5865 mutex_unlock(&dev_priv->rps.hw_lock);
5866
5867 intel_update_cdclk(dev);
5868 }
5869
5870 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5871 int max_pixclk)
5872 {
5873 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5874 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5875
5876 /*
5877 * Really only a few cases to deal with, as only 4 CDclks are supported:
5878 * 200MHz
5879 * 267MHz
5880 * 320/333MHz (depends on HPLL freq)
5881 * 400MHz (VLV only)
5882 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5883 * of the lower bin and adjust if needed.
5884 *
5885 * We seem to get an unstable or solid color picture at 200MHz.
5886 * Not sure what's wrong. For now use 200MHz only when all pipes
5887 * are off.
5888 */
5889 if (!IS_CHERRYVIEW(dev_priv) &&
5890 max_pixclk > freq_320*limit/100)
5891 return 400000;
5892 else if (max_pixclk > 266667*limit/100)
5893 return freq_320;
5894 else if (max_pixclk > 0)
5895 return 266667;
5896 else
5897 return 200000;
5898 }
5899
5900 static int broxton_calc_cdclk(int max_pixclk)
5901 {
5902 /*
5903 * FIXME:
5904 * - remove the guardband, it's not needed on BXT
5905 * - set 19.2MHz bypass frequency if there are no active pipes
5906 */
5907 if (max_pixclk > 576000*9/10)
5908 return 624000;
5909 else if (max_pixclk > 384000*9/10)
5910 return 576000;
5911 else if (max_pixclk > 288000*9/10)
5912 return 384000;
5913 else if (max_pixclk > 144000*9/10)
5914 return 288000;
5915 else
5916 return 144000;
5917 }
5918
5919 /* Compute the max pixel clock for new configuration. */
5920 static int intel_mode_max_pixclk(struct drm_device *dev,
5921 struct drm_atomic_state *state)
5922 {
5923 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5924 struct drm_i915_private *dev_priv = dev->dev_private;
5925 struct drm_crtc *crtc;
5926 struct drm_crtc_state *crtc_state;
5927 unsigned max_pixclk = 0, i;
5928 enum pipe pipe;
5929
5930 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5931 sizeof(intel_state->min_pixclk));
5932
5933 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5934 int pixclk = 0;
5935
5936 if (crtc_state->enable)
5937 pixclk = crtc_state->adjusted_mode.crtc_clock;
5938
5939 intel_state->min_pixclk[i] = pixclk;
5940 }
5941
5942 for_each_pipe(dev_priv, pipe)
5943 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5944
5945 return max_pixclk;
5946 }
5947
5948 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5949 {
5950 struct drm_device *dev = state->dev;
5951 struct drm_i915_private *dev_priv = dev->dev_private;
5952 int max_pixclk = intel_mode_max_pixclk(dev, state);
5953 struct intel_atomic_state *intel_state =
5954 to_intel_atomic_state(state);
5955
5956 intel_state->cdclk = intel_state->dev_cdclk =
5957 valleyview_calc_cdclk(dev_priv, max_pixclk);
5958
5959 if (!intel_state->active_crtcs)
5960 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5961
5962 return 0;
5963 }
5964
5965 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5966 {
5967 int max_pixclk = ilk_max_pixel_rate(state);
5968 struct intel_atomic_state *intel_state =
5969 to_intel_atomic_state(state);
5970
5971 intel_state->cdclk = intel_state->dev_cdclk =
5972 broxton_calc_cdclk(max_pixclk);
5973
5974 if (!intel_state->active_crtcs)
5975 intel_state->dev_cdclk = broxton_calc_cdclk(0);
5976
5977 return 0;
5978 }
5979
5980 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5981 {
5982 unsigned int credits, default_credits;
5983
5984 if (IS_CHERRYVIEW(dev_priv))
5985 default_credits = PFI_CREDIT(12);
5986 else
5987 default_credits = PFI_CREDIT(8);
5988
5989 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5990 /* CHV suggested value is 31 or 63 */
5991 if (IS_CHERRYVIEW(dev_priv))
5992 credits = PFI_CREDIT_63;
5993 else
5994 credits = PFI_CREDIT(15);
5995 } else {
5996 credits = default_credits;
5997 }
5998
5999 /*
6000 * WA - write default credits before re-programming
6001 * FIXME: should we also set the resend bit here?
6002 */
6003 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6004 default_credits);
6005
6006 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6007 credits | PFI_CREDIT_RESEND);
6008
6009 /*
6010 * FIXME is this guaranteed to clear
6011 * immediately or should we poll for it?
6012 */
6013 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6014 }
6015
6016 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6017 {
6018 struct drm_device *dev = old_state->dev;
6019 struct drm_i915_private *dev_priv = dev->dev_private;
6020 struct intel_atomic_state *old_intel_state =
6021 to_intel_atomic_state(old_state);
6022 unsigned req_cdclk = old_intel_state->dev_cdclk;
6023
6024 /*
6025 * FIXME: We can end up here with all power domains off, yet
6026 * with a CDCLK frequency other than the minimum. To account
6027 * for this take the PIPE-A power domain, which covers the HW
6028 * blocks needed for the following programming. This can be
6029 * removed once it's guaranteed that we get here either with
6030 * the minimum CDCLK set, or the required power domains
6031 * enabled.
6032 */
6033 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6034
6035 if (IS_CHERRYVIEW(dev))
6036 cherryview_set_cdclk(dev, req_cdclk);
6037 else
6038 valleyview_set_cdclk(dev, req_cdclk);
6039
6040 vlv_program_pfi_credits(dev_priv);
6041
6042 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6043 }
6044
6045 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6046 {
6047 struct drm_device *dev = crtc->dev;
6048 struct drm_i915_private *dev_priv = to_i915(dev);
6049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6050 struct intel_encoder *encoder;
6051 struct intel_crtc_state *pipe_config =
6052 to_intel_crtc_state(crtc->state);
6053 int pipe = intel_crtc->pipe;
6054
6055 if (WARN_ON(intel_crtc->active))
6056 return;
6057
6058 if (intel_crtc->config->has_dp_encoder)
6059 intel_dp_set_m_n(intel_crtc, M1_N1);
6060
6061 intel_set_pipe_timings(intel_crtc);
6062 intel_set_pipe_src_size(intel_crtc);
6063
6064 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6065 struct drm_i915_private *dev_priv = dev->dev_private;
6066
6067 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6068 I915_WRITE(CHV_CANVAS(pipe), 0);
6069 }
6070
6071 i9xx_set_pipeconf(intel_crtc);
6072
6073 intel_crtc->active = true;
6074
6075 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6076
6077 for_each_encoder_on_crtc(dev, crtc, encoder)
6078 if (encoder->pre_pll_enable)
6079 encoder->pre_pll_enable(encoder);
6080
6081 if (IS_CHERRYVIEW(dev)) {
6082 chv_prepare_pll(intel_crtc, intel_crtc->config);
6083 chv_enable_pll(intel_crtc, intel_crtc->config);
6084 } else {
6085 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6086 vlv_enable_pll(intel_crtc, intel_crtc->config);
6087 }
6088
6089 for_each_encoder_on_crtc(dev, crtc, encoder)
6090 if (encoder->pre_enable)
6091 encoder->pre_enable(encoder);
6092
6093 i9xx_pfit_enable(intel_crtc);
6094
6095 intel_color_load_luts(&pipe_config->base);
6096
6097 intel_update_watermarks(crtc);
6098 intel_enable_pipe(intel_crtc);
6099
6100 assert_vblank_disabled(crtc);
6101 drm_crtc_vblank_on(crtc);
6102
6103 for_each_encoder_on_crtc(dev, crtc, encoder)
6104 encoder->enable(encoder);
6105 }
6106
6107 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6108 {
6109 struct drm_device *dev = crtc->base.dev;
6110 struct drm_i915_private *dev_priv = dev->dev_private;
6111
6112 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6113 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6114 }
6115
6116 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6117 {
6118 struct drm_device *dev = crtc->dev;
6119 struct drm_i915_private *dev_priv = to_i915(dev);
6120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6121 struct intel_encoder *encoder;
6122 struct intel_crtc_state *pipe_config =
6123 to_intel_crtc_state(crtc->state);
6124 enum pipe pipe = intel_crtc->pipe;
6125
6126 if (WARN_ON(intel_crtc->active))
6127 return;
6128
6129 i9xx_set_pll_dividers(intel_crtc);
6130
6131 if (intel_crtc->config->has_dp_encoder)
6132 intel_dp_set_m_n(intel_crtc, M1_N1);
6133
6134 intel_set_pipe_timings(intel_crtc);
6135 intel_set_pipe_src_size(intel_crtc);
6136
6137 i9xx_set_pipeconf(intel_crtc);
6138
6139 intel_crtc->active = true;
6140
6141 if (!IS_GEN2(dev))
6142 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6143
6144 for_each_encoder_on_crtc(dev, crtc, encoder)
6145 if (encoder->pre_enable)
6146 encoder->pre_enable(encoder);
6147
6148 i9xx_enable_pll(intel_crtc);
6149
6150 i9xx_pfit_enable(intel_crtc);
6151
6152 intel_color_load_luts(&pipe_config->base);
6153
6154 intel_update_watermarks(crtc);
6155 intel_enable_pipe(intel_crtc);
6156
6157 assert_vblank_disabled(crtc);
6158 drm_crtc_vblank_on(crtc);
6159
6160 for_each_encoder_on_crtc(dev, crtc, encoder)
6161 encoder->enable(encoder);
6162 }
6163
6164 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6165 {
6166 struct drm_device *dev = crtc->base.dev;
6167 struct drm_i915_private *dev_priv = dev->dev_private;
6168
6169 if (!crtc->config->gmch_pfit.control)
6170 return;
6171
6172 assert_pipe_disabled(dev_priv, crtc->pipe);
6173
6174 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6175 I915_READ(PFIT_CONTROL));
6176 I915_WRITE(PFIT_CONTROL, 0);
6177 }
6178
6179 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6180 {
6181 struct drm_device *dev = crtc->dev;
6182 struct drm_i915_private *dev_priv = dev->dev_private;
6183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6184 struct intel_encoder *encoder;
6185 int pipe = intel_crtc->pipe;
6186
6187 /*
6188 * On gen2 planes are double buffered but the pipe isn't, so we must
6189 * wait for planes to fully turn off before disabling the pipe.
6190 */
6191 if (IS_GEN2(dev))
6192 intel_wait_for_vblank(dev, pipe);
6193
6194 for_each_encoder_on_crtc(dev, crtc, encoder)
6195 encoder->disable(encoder);
6196
6197 drm_crtc_vblank_off(crtc);
6198 assert_vblank_disabled(crtc);
6199
6200 intel_disable_pipe(intel_crtc);
6201
6202 i9xx_pfit_disable(intel_crtc);
6203
6204 for_each_encoder_on_crtc(dev, crtc, encoder)
6205 if (encoder->post_disable)
6206 encoder->post_disable(encoder);
6207
6208 if (!intel_crtc->config->has_dsi_encoder) {
6209 if (IS_CHERRYVIEW(dev))
6210 chv_disable_pll(dev_priv, pipe);
6211 else if (IS_VALLEYVIEW(dev))
6212 vlv_disable_pll(dev_priv, pipe);
6213 else
6214 i9xx_disable_pll(intel_crtc);
6215 }
6216
6217 for_each_encoder_on_crtc(dev, crtc, encoder)
6218 if (encoder->post_pll_disable)
6219 encoder->post_pll_disable(encoder);
6220
6221 if (!IS_GEN2(dev))
6222 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6223 }
6224
6225 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6226 {
6227 struct intel_encoder *encoder;
6228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6229 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6230 enum intel_display_power_domain domain;
6231 unsigned long domains;
6232
6233 if (!intel_crtc->active)
6234 return;
6235
6236 if (to_intel_plane_state(crtc->primary->state)->visible) {
6237 WARN_ON(intel_crtc->unpin_work);
6238
6239 intel_pre_disable_primary_noatomic(crtc);
6240
6241 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6242 to_intel_plane_state(crtc->primary->state)->visible = false;
6243 }
6244
6245 dev_priv->display.crtc_disable(crtc);
6246
6247 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6248 crtc->base.id);
6249
6250 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6251 crtc->state->active = false;
6252 intel_crtc->active = false;
6253 crtc->enabled = false;
6254 crtc->state->connector_mask = 0;
6255 crtc->state->encoder_mask = 0;
6256
6257 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6258 encoder->base.crtc = NULL;
6259
6260 intel_fbc_disable(intel_crtc);
6261 intel_update_watermarks(crtc);
6262 intel_disable_shared_dpll(intel_crtc);
6263
6264 domains = intel_crtc->enabled_power_domains;
6265 for_each_power_domain(domain, domains)
6266 intel_display_power_put(dev_priv, domain);
6267 intel_crtc->enabled_power_domains = 0;
6268
6269 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6270 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6271 }
6272
6273 /*
6274 * turn all crtc's off, but do not adjust state
6275 * This has to be paired with a call to intel_modeset_setup_hw_state.
6276 */
6277 int intel_display_suspend(struct drm_device *dev)
6278 {
6279 struct drm_i915_private *dev_priv = to_i915(dev);
6280 struct drm_atomic_state *state;
6281 int ret;
6282
6283 state = drm_atomic_helper_suspend(dev);
6284 ret = PTR_ERR_OR_ZERO(state);
6285 if (ret)
6286 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6287 else
6288 dev_priv->modeset_restore_state = state;
6289 return ret;
6290 }
6291
6292 void intel_encoder_destroy(struct drm_encoder *encoder)
6293 {
6294 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6295
6296 drm_encoder_cleanup(encoder);
6297 kfree(intel_encoder);
6298 }
6299
6300 /* Cross check the actual hw state with our own modeset state tracking (and it's
6301 * internal consistency). */
6302 static void intel_connector_verify_state(struct intel_connector *connector)
6303 {
6304 struct drm_crtc *crtc = connector->base.state->crtc;
6305
6306 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6307 connector->base.base.id,
6308 connector->base.name);
6309
6310 if (connector->get_hw_state(connector)) {
6311 struct intel_encoder *encoder = connector->encoder;
6312 struct drm_connector_state *conn_state = connector->base.state;
6313
6314 I915_STATE_WARN(!crtc,
6315 "connector enabled without attached crtc\n");
6316
6317 if (!crtc)
6318 return;
6319
6320 I915_STATE_WARN(!crtc->state->active,
6321 "connector is active, but attached crtc isn't\n");
6322
6323 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6324 return;
6325
6326 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6327 "atomic encoder doesn't match attached encoder\n");
6328
6329 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6330 "attached encoder crtc differs from connector crtc\n");
6331 } else {
6332 I915_STATE_WARN(crtc && crtc->state->active,
6333 "attached crtc is active, but connector isn't\n");
6334 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6335 "best encoder set without crtc!\n");
6336 }
6337 }
6338
6339 int intel_connector_init(struct intel_connector *connector)
6340 {
6341 drm_atomic_helper_connector_reset(&connector->base);
6342
6343 if (!connector->base.state)
6344 return -ENOMEM;
6345
6346 return 0;
6347 }
6348
6349 struct intel_connector *intel_connector_alloc(void)
6350 {
6351 struct intel_connector *connector;
6352
6353 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6354 if (!connector)
6355 return NULL;
6356
6357 if (intel_connector_init(connector) < 0) {
6358 kfree(connector);
6359 return NULL;
6360 }
6361
6362 return connector;
6363 }
6364
6365 /* Simple connector->get_hw_state implementation for encoders that support only
6366 * one connector and no cloning and hence the encoder state determines the state
6367 * of the connector. */
6368 bool intel_connector_get_hw_state(struct intel_connector *connector)
6369 {
6370 enum pipe pipe = 0;
6371 struct intel_encoder *encoder = connector->encoder;
6372
6373 return encoder->get_hw_state(encoder, &pipe);
6374 }
6375
6376 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6377 {
6378 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6379 return crtc_state->fdi_lanes;
6380
6381 return 0;
6382 }
6383
6384 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6385 struct intel_crtc_state *pipe_config)
6386 {
6387 struct drm_atomic_state *state = pipe_config->base.state;
6388 struct intel_crtc *other_crtc;
6389 struct intel_crtc_state *other_crtc_state;
6390
6391 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6392 pipe_name(pipe), pipe_config->fdi_lanes);
6393 if (pipe_config->fdi_lanes > 4) {
6394 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6395 pipe_name(pipe), pipe_config->fdi_lanes);
6396 return -EINVAL;
6397 }
6398
6399 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6400 if (pipe_config->fdi_lanes > 2) {
6401 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6402 pipe_config->fdi_lanes);
6403 return -EINVAL;
6404 } else {
6405 return 0;
6406 }
6407 }
6408
6409 if (INTEL_INFO(dev)->num_pipes == 2)
6410 return 0;
6411
6412 /* Ivybridge 3 pipe is really complicated */
6413 switch (pipe) {
6414 case PIPE_A:
6415 return 0;
6416 case PIPE_B:
6417 if (pipe_config->fdi_lanes <= 2)
6418 return 0;
6419
6420 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6421 other_crtc_state =
6422 intel_atomic_get_crtc_state(state, other_crtc);
6423 if (IS_ERR(other_crtc_state))
6424 return PTR_ERR(other_crtc_state);
6425
6426 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6427 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6428 pipe_name(pipe), pipe_config->fdi_lanes);
6429 return -EINVAL;
6430 }
6431 return 0;
6432 case PIPE_C:
6433 if (pipe_config->fdi_lanes > 2) {
6434 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6435 pipe_name(pipe), pipe_config->fdi_lanes);
6436 return -EINVAL;
6437 }
6438
6439 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6440 other_crtc_state =
6441 intel_atomic_get_crtc_state(state, other_crtc);
6442 if (IS_ERR(other_crtc_state))
6443 return PTR_ERR(other_crtc_state);
6444
6445 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6446 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6447 return -EINVAL;
6448 }
6449 return 0;
6450 default:
6451 BUG();
6452 }
6453 }
6454
6455 #define RETRY 1
6456 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6457 struct intel_crtc_state *pipe_config)
6458 {
6459 struct drm_device *dev = intel_crtc->base.dev;
6460 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6461 int lane, link_bw, fdi_dotclock, ret;
6462 bool needs_recompute = false;
6463
6464 retry:
6465 /* FDI is a binary signal running at ~2.7GHz, encoding
6466 * each output octet as 10 bits. The actual frequency
6467 * is stored as a divider into a 100MHz clock, and the
6468 * mode pixel clock is stored in units of 1KHz.
6469 * Hence the bw of each lane in terms of the mode signal
6470 * is:
6471 */
6472 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6473
6474 fdi_dotclock = adjusted_mode->crtc_clock;
6475
6476 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6477 pipe_config->pipe_bpp);
6478
6479 pipe_config->fdi_lanes = lane;
6480
6481 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6482 link_bw, &pipe_config->fdi_m_n);
6483
6484 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6485 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6486 pipe_config->pipe_bpp -= 2*3;
6487 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6488 pipe_config->pipe_bpp);
6489 needs_recompute = true;
6490 pipe_config->bw_constrained = true;
6491
6492 goto retry;
6493 }
6494
6495 if (needs_recompute)
6496 return RETRY;
6497
6498 return ret;
6499 }
6500
6501 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6502 struct intel_crtc_state *pipe_config)
6503 {
6504 if (pipe_config->pipe_bpp > 24)
6505 return false;
6506
6507 /* HSW can handle pixel rate up to cdclk? */
6508 if (IS_HASWELL(dev_priv))
6509 return true;
6510
6511 /*
6512 * We compare against max which means we must take
6513 * the increased cdclk requirement into account when
6514 * calculating the new cdclk.
6515 *
6516 * Should measure whether using a lower cdclk w/o IPS
6517 */
6518 return ilk_pipe_pixel_rate(pipe_config) <=
6519 dev_priv->max_cdclk_freq * 95 / 100;
6520 }
6521
6522 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6523 struct intel_crtc_state *pipe_config)
6524 {
6525 struct drm_device *dev = crtc->base.dev;
6526 struct drm_i915_private *dev_priv = dev->dev_private;
6527
6528 pipe_config->ips_enabled = i915.enable_ips &&
6529 hsw_crtc_supports_ips(crtc) &&
6530 pipe_config_supports_ips(dev_priv, pipe_config);
6531 }
6532
6533 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6534 {
6535 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6536
6537 /* GDG double wide on either pipe, otherwise pipe A only */
6538 return INTEL_INFO(dev_priv)->gen < 4 &&
6539 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6540 }
6541
6542 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6543 struct intel_crtc_state *pipe_config)
6544 {
6545 struct drm_device *dev = crtc->base.dev;
6546 struct drm_i915_private *dev_priv = dev->dev_private;
6547 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6548
6549 /* FIXME should check pixel clock limits on all platforms */
6550 if (INTEL_INFO(dev)->gen < 4) {
6551 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6552
6553 /*
6554 * Enable double wide mode when the dot clock
6555 * is > 90% of the (display) core speed.
6556 */
6557 if (intel_crtc_supports_double_wide(crtc) &&
6558 adjusted_mode->crtc_clock > clock_limit) {
6559 clock_limit *= 2;
6560 pipe_config->double_wide = true;
6561 }
6562
6563 if (adjusted_mode->crtc_clock > clock_limit) {
6564 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6565 adjusted_mode->crtc_clock, clock_limit,
6566 yesno(pipe_config->double_wide));
6567 return -EINVAL;
6568 }
6569 }
6570
6571 /*
6572 * Pipe horizontal size must be even in:
6573 * - DVO ganged mode
6574 * - LVDS dual channel mode
6575 * - Double wide pipe
6576 */
6577 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6578 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6579 pipe_config->pipe_src_w &= ~1;
6580
6581 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6582 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6583 */
6584 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6585 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6586 return -EINVAL;
6587
6588 if (HAS_IPS(dev))
6589 hsw_compute_ips_config(crtc, pipe_config);
6590
6591 if (pipe_config->has_pch_encoder)
6592 return ironlake_fdi_compute_config(crtc, pipe_config);
6593
6594 return 0;
6595 }
6596
6597 static int skylake_get_display_clock_speed(struct drm_device *dev)
6598 {
6599 struct drm_i915_private *dev_priv = to_i915(dev);
6600 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6601 uint32_t cdctl = I915_READ(CDCLK_CTL);
6602 uint32_t linkrate;
6603
6604 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6605 return 24000; /* 24MHz is the cd freq with NSSC ref */
6606
6607 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6608 return 540000;
6609
6610 linkrate = (I915_READ(DPLL_CTRL1) &
6611 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6612
6613 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6614 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6615 /* vco 8640 */
6616 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6617 case CDCLK_FREQ_450_432:
6618 return 432000;
6619 case CDCLK_FREQ_337_308:
6620 return 308570;
6621 case CDCLK_FREQ_675_617:
6622 return 617140;
6623 default:
6624 WARN(1, "Unknown cd freq selection\n");
6625 }
6626 } else {
6627 /* vco 8100 */
6628 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6629 case CDCLK_FREQ_450_432:
6630 return 450000;
6631 case CDCLK_FREQ_337_308:
6632 return 337500;
6633 case CDCLK_FREQ_675_617:
6634 return 675000;
6635 default:
6636 WARN(1, "Unknown cd freq selection\n");
6637 }
6638 }
6639
6640 /* error case, do as if DPLL0 isn't enabled */
6641 return 24000;
6642 }
6643
6644 static int broxton_get_display_clock_speed(struct drm_device *dev)
6645 {
6646 struct drm_i915_private *dev_priv = to_i915(dev);
6647 uint32_t cdctl = I915_READ(CDCLK_CTL);
6648 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6649 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6650 int cdclk;
6651
6652 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6653 return 19200;
6654
6655 cdclk = 19200 * pll_ratio / 2;
6656
6657 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6658 case BXT_CDCLK_CD2X_DIV_SEL_1:
6659 return cdclk; /* 576MHz or 624MHz */
6660 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6661 return cdclk * 2 / 3; /* 384MHz */
6662 case BXT_CDCLK_CD2X_DIV_SEL_2:
6663 return cdclk / 2; /* 288MHz */
6664 case BXT_CDCLK_CD2X_DIV_SEL_4:
6665 return cdclk / 4; /* 144MHz */
6666 }
6667
6668 /* error case, do as if DE PLL isn't enabled */
6669 return 19200;
6670 }
6671
6672 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6673 {
6674 struct drm_i915_private *dev_priv = dev->dev_private;
6675 uint32_t lcpll = I915_READ(LCPLL_CTL);
6676 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6677
6678 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6679 return 800000;
6680 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6681 return 450000;
6682 else if (freq == LCPLL_CLK_FREQ_450)
6683 return 450000;
6684 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6685 return 540000;
6686 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6687 return 337500;
6688 else
6689 return 675000;
6690 }
6691
6692 static int haswell_get_display_clock_speed(struct drm_device *dev)
6693 {
6694 struct drm_i915_private *dev_priv = dev->dev_private;
6695 uint32_t lcpll = I915_READ(LCPLL_CTL);
6696 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6697
6698 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6699 return 800000;
6700 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6701 return 450000;
6702 else if (freq == LCPLL_CLK_FREQ_450)
6703 return 450000;
6704 else if (IS_HSW_ULT(dev))
6705 return 337500;
6706 else
6707 return 540000;
6708 }
6709
6710 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6711 {
6712 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6713 CCK_DISPLAY_CLOCK_CONTROL);
6714 }
6715
6716 static int ilk_get_display_clock_speed(struct drm_device *dev)
6717 {
6718 return 450000;
6719 }
6720
6721 static int i945_get_display_clock_speed(struct drm_device *dev)
6722 {
6723 return 400000;
6724 }
6725
6726 static int i915_get_display_clock_speed(struct drm_device *dev)
6727 {
6728 return 333333;
6729 }
6730
6731 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6732 {
6733 return 200000;
6734 }
6735
6736 static int pnv_get_display_clock_speed(struct drm_device *dev)
6737 {
6738 u16 gcfgc = 0;
6739
6740 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6741
6742 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6743 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6744 return 266667;
6745 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6746 return 333333;
6747 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6748 return 444444;
6749 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6750 return 200000;
6751 default:
6752 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6753 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6754 return 133333;
6755 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6756 return 166667;
6757 }
6758 }
6759
6760 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6761 {
6762 u16 gcfgc = 0;
6763
6764 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6765
6766 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6767 return 133333;
6768 else {
6769 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6770 case GC_DISPLAY_CLOCK_333_MHZ:
6771 return 333333;
6772 default:
6773 case GC_DISPLAY_CLOCK_190_200_MHZ:
6774 return 190000;
6775 }
6776 }
6777 }
6778
6779 static int i865_get_display_clock_speed(struct drm_device *dev)
6780 {
6781 return 266667;
6782 }
6783
6784 static int i85x_get_display_clock_speed(struct drm_device *dev)
6785 {
6786 u16 hpllcc = 0;
6787
6788 /*
6789 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6790 * encoding is different :(
6791 * FIXME is this the right way to detect 852GM/852GMV?
6792 */
6793 if (dev->pdev->revision == 0x1)
6794 return 133333;
6795
6796 pci_bus_read_config_word(dev->pdev->bus,
6797 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6798
6799 /* Assume that the hardware is in the high speed state. This
6800 * should be the default.
6801 */
6802 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6803 case GC_CLOCK_133_200:
6804 case GC_CLOCK_133_200_2:
6805 case GC_CLOCK_100_200:
6806 return 200000;
6807 case GC_CLOCK_166_250:
6808 return 250000;
6809 case GC_CLOCK_100_133:
6810 return 133333;
6811 case GC_CLOCK_133_266:
6812 case GC_CLOCK_133_266_2:
6813 case GC_CLOCK_166_266:
6814 return 266667;
6815 }
6816
6817 /* Shouldn't happen */
6818 return 0;
6819 }
6820
6821 static int i830_get_display_clock_speed(struct drm_device *dev)
6822 {
6823 return 133333;
6824 }
6825
6826 static unsigned int intel_hpll_vco(struct drm_device *dev)
6827 {
6828 struct drm_i915_private *dev_priv = dev->dev_private;
6829 static const unsigned int blb_vco[8] = {
6830 [0] = 3200000,
6831 [1] = 4000000,
6832 [2] = 5333333,
6833 [3] = 4800000,
6834 [4] = 6400000,
6835 };
6836 static const unsigned int pnv_vco[8] = {
6837 [0] = 3200000,
6838 [1] = 4000000,
6839 [2] = 5333333,
6840 [3] = 4800000,
6841 [4] = 2666667,
6842 };
6843 static const unsigned int cl_vco[8] = {
6844 [0] = 3200000,
6845 [1] = 4000000,
6846 [2] = 5333333,
6847 [3] = 6400000,
6848 [4] = 3333333,
6849 [5] = 3566667,
6850 [6] = 4266667,
6851 };
6852 static const unsigned int elk_vco[8] = {
6853 [0] = 3200000,
6854 [1] = 4000000,
6855 [2] = 5333333,
6856 [3] = 4800000,
6857 };
6858 static const unsigned int ctg_vco[8] = {
6859 [0] = 3200000,
6860 [1] = 4000000,
6861 [2] = 5333333,
6862 [3] = 6400000,
6863 [4] = 2666667,
6864 [5] = 4266667,
6865 };
6866 const unsigned int *vco_table;
6867 unsigned int vco;
6868 uint8_t tmp = 0;
6869
6870 /* FIXME other chipsets? */
6871 if (IS_GM45(dev))
6872 vco_table = ctg_vco;
6873 else if (IS_G4X(dev))
6874 vco_table = elk_vco;
6875 else if (IS_CRESTLINE(dev))
6876 vco_table = cl_vco;
6877 else if (IS_PINEVIEW(dev))
6878 vco_table = pnv_vco;
6879 else if (IS_G33(dev))
6880 vco_table = blb_vco;
6881 else
6882 return 0;
6883
6884 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6885
6886 vco = vco_table[tmp & 0x7];
6887 if (vco == 0)
6888 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6889 else
6890 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6891
6892 return vco;
6893 }
6894
6895 static int gm45_get_display_clock_speed(struct drm_device *dev)
6896 {
6897 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6898 uint16_t tmp = 0;
6899
6900 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6901
6902 cdclk_sel = (tmp >> 12) & 0x1;
6903
6904 switch (vco) {
6905 case 2666667:
6906 case 4000000:
6907 case 5333333:
6908 return cdclk_sel ? 333333 : 222222;
6909 case 3200000:
6910 return cdclk_sel ? 320000 : 228571;
6911 default:
6912 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6913 return 222222;
6914 }
6915 }
6916
6917 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6918 {
6919 static const uint8_t div_3200[] = { 16, 10, 8 };
6920 static const uint8_t div_4000[] = { 20, 12, 10 };
6921 static const uint8_t div_5333[] = { 24, 16, 14 };
6922 const uint8_t *div_table;
6923 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6924 uint16_t tmp = 0;
6925
6926 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6927
6928 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6929
6930 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6931 goto fail;
6932
6933 switch (vco) {
6934 case 3200000:
6935 div_table = div_3200;
6936 break;
6937 case 4000000:
6938 div_table = div_4000;
6939 break;
6940 case 5333333:
6941 div_table = div_5333;
6942 break;
6943 default:
6944 goto fail;
6945 }
6946
6947 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6948
6949 fail:
6950 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6951 return 200000;
6952 }
6953
6954 static int g33_get_display_clock_speed(struct drm_device *dev)
6955 {
6956 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6957 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6958 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6959 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6960 const uint8_t *div_table;
6961 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6962 uint16_t tmp = 0;
6963
6964 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6965
6966 cdclk_sel = (tmp >> 4) & 0x7;
6967
6968 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6969 goto fail;
6970
6971 switch (vco) {
6972 case 3200000:
6973 div_table = div_3200;
6974 break;
6975 case 4000000:
6976 div_table = div_4000;
6977 break;
6978 case 4800000:
6979 div_table = div_4800;
6980 break;
6981 case 5333333:
6982 div_table = div_5333;
6983 break;
6984 default:
6985 goto fail;
6986 }
6987
6988 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6989
6990 fail:
6991 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6992 return 190476;
6993 }
6994
6995 static void
6996 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6997 {
6998 while (*num > DATA_LINK_M_N_MASK ||
6999 *den > DATA_LINK_M_N_MASK) {
7000 *num >>= 1;
7001 *den >>= 1;
7002 }
7003 }
7004
7005 static void compute_m_n(unsigned int m, unsigned int n,
7006 uint32_t *ret_m, uint32_t *ret_n)
7007 {
7008 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7009 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7010 intel_reduce_m_n_ratio(ret_m, ret_n);
7011 }
7012
7013 void
7014 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7015 int pixel_clock, int link_clock,
7016 struct intel_link_m_n *m_n)
7017 {
7018 m_n->tu = 64;
7019
7020 compute_m_n(bits_per_pixel * pixel_clock,
7021 link_clock * nlanes * 8,
7022 &m_n->gmch_m, &m_n->gmch_n);
7023
7024 compute_m_n(pixel_clock, link_clock,
7025 &m_n->link_m, &m_n->link_n);
7026 }
7027
7028 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7029 {
7030 if (i915.panel_use_ssc >= 0)
7031 return i915.panel_use_ssc != 0;
7032 return dev_priv->vbt.lvds_use_ssc
7033 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7034 }
7035
7036 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7037 {
7038 return (1 << dpll->n) << 16 | dpll->m2;
7039 }
7040
7041 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7042 {
7043 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7044 }
7045
7046 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7047 struct intel_crtc_state *crtc_state,
7048 struct dpll *reduced_clock)
7049 {
7050 struct drm_device *dev = crtc->base.dev;
7051 u32 fp, fp2 = 0;
7052
7053 if (IS_PINEVIEW(dev)) {
7054 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7055 if (reduced_clock)
7056 fp2 = pnv_dpll_compute_fp(reduced_clock);
7057 } else {
7058 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7059 if (reduced_clock)
7060 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7061 }
7062
7063 crtc_state->dpll_hw_state.fp0 = fp;
7064
7065 crtc->lowfreq_avail = false;
7066 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7067 reduced_clock) {
7068 crtc_state->dpll_hw_state.fp1 = fp2;
7069 crtc->lowfreq_avail = true;
7070 } else {
7071 crtc_state->dpll_hw_state.fp1 = fp;
7072 }
7073 }
7074
7075 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7076 pipe)
7077 {
7078 u32 reg_val;
7079
7080 /*
7081 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7082 * and set it to a reasonable value instead.
7083 */
7084 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7085 reg_val &= 0xffffff00;
7086 reg_val |= 0x00000030;
7087 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7088
7089 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7090 reg_val &= 0x8cffffff;
7091 reg_val = 0x8c000000;
7092 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7093
7094 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7095 reg_val &= 0xffffff00;
7096 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7097
7098 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7099 reg_val &= 0x00ffffff;
7100 reg_val |= 0xb0000000;
7101 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7102 }
7103
7104 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7105 struct intel_link_m_n *m_n)
7106 {
7107 struct drm_device *dev = crtc->base.dev;
7108 struct drm_i915_private *dev_priv = dev->dev_private;
7109 int pipe = crtc->pipe;
7110
7111 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7112 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7113 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7114 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7115 }
7116
7117 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7118 struct intel_link_m_n *m_n,
7119 struct intel_link_m_n *m2_n2)
7120 {
7121 struct drm_device *dev = crtc->base.dev;
7122 struct drm_i915_private *dev_priv = dev->dev_private;
7123 int pipe = crtc->pipe;
7124 enum transcoder transcoder = crtc->config->cpu_transcoder;
7125
7126 if (INTEL_INFO(dev)->gen >= 5) {
7127 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7128 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7129 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7130 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7131 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7132 * for gen < 8) and if DRRS is supported (to make sure the
7133 * registers are not unnecessarily accessed).
7134 */
7135 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7136 crtc->config->has_drrs) {
7137 I915_WRITE(PIPE_DATA_M2(transcoder),
7138 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7139 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7140 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7141 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7142 }
7143 } else {
7144 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7145 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7146 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7147 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7148 }
7149 }
7150
7151 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7152 {
7153 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7154
7155 if (m_n == M1_N1) {
7156 dp_m_n = &crtc->config->dp_m_n;
7157 dp_m2_n2 = &crtc->config->dp_m2_n2;
7158 } else if (m_n == M2_N2) {
7159
7160 /*
7161 * M2_N2 registers are not supported. Hence m2_n2 divider value
7162 * needs to be programmed into M1_N1.
7163 */
7164 dp_m_n = &crtc->config->dp_m2_n2;
7165 } else {
7166 DRM_ERROR("Unsupported divider value\n");
7167 return;
7168 }
7169
7170 if (crtc->config->has_pch_encoder)
7171 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7172 else
7173 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7174 }
7175
7176 static void vlv_compute_dpll(struct intel_crtc *crtc,
7177 struct intel_crtc_state *pipe_config)
7178 {
7179 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7180 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7181 if (crtc->pipe != PIPE_A)
7182 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7183
7184 /* DPLL not used with DSI, but still need the rest set up */
7185 if (!pipe_config->has_dsi_encoder)
7186 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7187 DPLL_EXT_BUFFER_ENABLE_VLV;
7188
7189 pipe_config->dpll_hw_state.dpll_md =
7190 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7191 }
7192
7193 static void chv_compute_dpll(struct intel_crtc *crtc,
7194 struct intel_crtc_state *pipe_config)
7195 {
7196 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7197 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7198 if (crtc->pipe != PIPE_A)
7199 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7200
7201 /* DPLL not used with DSI, but still need the rest set up */
7202 if (!pipe_config->has_dsi_encoder)
7203 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7204
7205 pipe_config->dpll_hw_state.dpll_md =
7206 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7207 }
7208
7209 static void vlv_prepare_pll(struct intel_crtc *crtc,
7210 const struct intel_crtc_state *pipe_config)
7211 {
7212 struct drm_device *dev = crtc->base.dev;
7213 struct drm_i915_private *dev_priv = dev->dev_private;
7214 enum pipe pipe = crtc->pipe;
7215 u32 mdiv;
7216 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7217 u32 coreclk, reg_val;
7218
7219 /* Enable Refclk */
7220 I915_WRITE(DPLL(pipe),
7221 pipe_config->dpll_hw_state.dpll &
7222 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7223
7224 /* No need to actually set up the DPLL with DSI */
7225 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7226 return;
7227
7228 mutex_lock(&dev_priv->sb_lock);
7229
7230 bestn = pipe_config->dpll.n;
7231 bestm1 = pipe_config->dpll.m1;
7232 bestm2 = pipe_config->dpll.m2;
7233 bestp1 = pipe_config->dpll.p1;
7234 bestp2 = pipe_config->dpll.p2;
7235
7236 /* See eDP HDMI DPIO driver vbios notes doc */
7237
7238 /* PLL B needs special handling */
7239 if (pipe == PIPE_B)
7240 vlv_pllb_recal_opamp(dev_priv, pipe);
7241
7242 /* Set up Tx target for periodic Rcomp update */
7243 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7244
7245 /* Disable target IRef on PLL */
7246 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7247 reg_val &= 0x00ffffff;
7248 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7249
7250 /* Disable fast lock */
7251 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7252
7253 /* Set idtafcrecal before PLL is enabled */
7254 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7255 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7256 mdiv |= ((bestn << DPIO_N_SHIFT));
7257 mdiv |= (1 << DPIO_K_SHIFT);
7258
7259 /*
7260 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7261 * but we don't support that).
7262 * Note: don't use the DAC post divider as it seems unstable.
7263 */
7264 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7265 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7266
7267 mdiv |= DPIO_ENABLE_CALIBRATION;
7268 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7269
7270 /* Set HBR and RBR LPF coefficients */
7271 if (pipe_config->port_clock == 162000 ||
7272 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7273 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7274 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7275 0x009f0003);
7276 else
7277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7278 0x00d0000f);
7279
7280 if (pipe_config->has_dp_encoder) {
7281 /* Use SSC source */
7282 if (pipe == PIPE_A)
7283 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7284 0x0df40000);
7285 else
7286 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7287 0x0df70000);
7288 } else { /* HDMI or VGA */
7289 /* Use bend source */
7290 if (pipe == PIPE_A)
7291 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7292 0x0df70000);
7293 else
7294 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7295 0x0df40000);
7296 }
7297
7298 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7299 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7300 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7301 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7302 coreclk |= 0x01000000;
7303 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7304
7305 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7306 mutex_unlock(&dev_priv->sb_lock);
7307 }
7308
7309 static void chv_prepare_pll(struct intel_crtc *crtc,
7310 const struct intel_crtc_state *pipe_config)
7311 {
7312 struct drm_device *dev = crtc->base.dev;
7313 struct drm_i915_private *dev_priv = dev->dev_private;
7314 enum pipe pipe = crtc->pipe;
7315 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7316 u32 loopfilter, tribuf_calcntr;
7317 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7318 u32 dpio_val;
7319 int vco;
7320
7321 /* Enable Refclk and SSC */
7322 I915_WRITE(DPLL(pipe),
7323 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7324
7325 /* No need to actually set up the DPLL with DSI */
7326 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7327 return;
7328
7329 bestn = pipe_config->dpll.n;
7330 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7331 bestm1 = pipe_config->dpll.m1;
7332 bestm2 = pipe_config->dpll.m2 >> 22;
7333 bestp1 = pipe_config->dpll.p1;
7334 bestp2 = pipe_config->dpll.p2;
7335 vco = pipe_config->dpll.vco;
7336 dpio_val = 0;
7337 loopfilter = 0;
7338
7339 mutex_lock(&dev_priv->sb_lock);
7340
7341 /* p1 and p2 divider */
7342 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7343 5 << DPIO_CHV_S1_DIV_SHIFT |
7344 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7345 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7346 1 << DPIO_CHV_K_DIV_SHIFT);
7347
7348 /* Feedback post-divider - m2 */
7349 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7350
7351 /* Feedback refclk divider - n and m1 */
7352 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7353 DPIO_CHV_M1_DIV_BY_2 |
7354 1 << DPIO_CHV_N_DIV_SHIFT);
7355
7356 /* M2 fraction division */
7357 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7358
7359 /* M2 fraction division enable */
7360 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7361 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7362 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7363 if (bestm2_frac)
7364 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7365 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7366
7367 /* Program digital lock detect threshold */
7368 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7369 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7370 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7371 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7372 if (!bestm2_frac)
7373 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7374 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7375
7376 /* Loop filter */
7377 if (vco == 5400000) {
7378 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7379 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7380 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7381 tribuf_calcntr = 0x9;
7382 } else if (vco <= 6200000) {
7383 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7384 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7385 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7386 tribuf_calcntr = 0x9;
7387 } else if (vco <= 6480000) {
7388 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7389 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7390 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7391 tribuf_calcntr = 0x8;
7392 } else {
7393 /* Not supported. Apply the same limits as in the max case */
7394 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7395 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7396 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7397 tribuf_calcntr = 0;
7398 }
7399 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7400
7401 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7402 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7403 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7404 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7405
7406 /* AFC Recal */
7407 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7408 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7409 DPIO_AFC_RECAL);
7410
7411 mutex_unlock(&dev_priv->sb_lock);
7412 }
7413
7414 /**
7415 * vlv_force_pll_on - forcibly enable just the PLL
7416 * @dev_priv: i915 private structure
7417 * @pipe: pipe PLL to enable
7418 * @dpll: PLL configuration
7419 *
7420 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7421 * in cases where we need the PLL enabled even when @pipe is not going to
7422 * be enabled.
7423 */
7424 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7425 const struct dpll *dpll)
7426 {
7427 struct intel_crtc *crtc =
7428 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7429 struct intel_crtc_state *pipe_config;
7430
7431 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7432 if (!pipe_config)
7433 return -ENOMEM;
7434
7435 pipe_config->base.crtc = &crtc->base;
7436 pipe_config->pixel_multiplier = 1;
7437 pipe_config->dpll = *dpll;
7438
7439 if (IS_CHERRYVIEW(dev)) {
7440 chv_compute_dpll(crtc, pipe_config);
7441 chv_prepare_pll(crtc, pipe_config);
7442 chv_enable_pll(crtc, pipe_config);
7443 } else {
7444 vlv_compute_dpll(crtc, pipe_config);
7445 vlv_prepare_pll(crtc, pipe_config);
7446 vlv_enable_pll(crtc, pipe_config);
7447 }
7448
7449 kfree(pipe_config);
7450
7451 return 0;
7452 }
7453
7454 /**
7455 * vlv_force_pll_off - forcibly disable just the PLL
7456 * @dev_priv: i915 private structure
7457 * @pipe: pipe PLL to disable
7458 *
7459 * Disable the PLL for @pipe. To be used in cases where we need
7460 * the PLL enabled even when @pipe is not going to be enabled.
7461 */
7462 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7463 {
7464 if (IS_CHERRYVIEW(dev))
7465 chv_disable_pll(to_i915(dev), pipe);
7466 else
7467 vlv_disable_pll(to_i915(dev), pipe);
7468 }
7469
7470 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7471 struct intel_crtc_state *crtc_state,
7472 struct dpll *reduced_clock)
7473 {
7474 struct drm_device *dev = crtc->base.dev;
7475 struct drm_i915_private *dev_priv = dev->dev_private;
7476 u32 dpll;
7477 bool is_sdvo;
7478 struct dpll *clock = &crtc_state->dpll;
7479
7480 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7481
7482 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7483 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7484
7485 dpll = DPLL_VGA_MODE_DIS;
7486
7487 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7488 dpll |= DPLLB_MODE_LVDS;
7489 else
7490 dpll |= DPLLB_MODE_DAC_SERIAL;
7491
7492 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7493 dpll |= (crtc_state->pixel_multiplier - 1)
7494 << SDVO_MULTIPLIER_SHIFT_HIRES;
7495 }
7496
7497 if (is_sdvo)
7498 dpll |= DPLL_SDVO_HIGH_SPEED;
7499
7500 if (crtc_state->has_dp_encoder)
7501 dpll |= DPLL_SDVO_HIGH_SPEED;
7502
7503 /* compute bitmask from p1 value */
7504 if (IS_PINEVIEW(dev))
7505 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7506 else {
7507 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7508 if (IS_G4X(dev) && reduced_clock)
7509 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7510 }
7511 switch (clock->p2) {
7512 case 5:
7513 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7514 break;
7515 case 7:
7516 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7517 break;
7518 case 10:
7519 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7520 break;
7521 case 14:
7522 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7523 break;
7524 }
7525 if (INTEL_INFO(dev)->gen >= 4)
7526 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7527
7528 if (crtc_state->sdvo_tv_clock)
7529 dpll |= PLL_REF_INPUT_TVCLKINBC;
7530 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7531 intel_panel_use_ssc(dev_priv))
7532 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7533 else
7534 dpll |= PLL_REF_INPUT_DREFCLK;
7535
7536 dpll |= DPLL_VCO_ENABLE;
7537 crtc_state->dpll_hw_state.dpll = dpll;
7538
7539 if (INTEL_INFO(dev)->gen >= 4) {
7540 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7541 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7542 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7543 }
7544 }
7545
7546 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7547 struct intel_crtc_state *crtc_state,
7548 struct dpll *reduced_clock)
7549 {
7550 struct drm_device *dev = crtc->base.dev;
7551 struct drm_i915_private *dev_priv = dev->dev_private;
7552 u32 dpll;
7553 struct dpll *clock = &crtc_state->dpll;
7554
7555 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7556
7557 dpll = DPLL_VGA_MODE_DIS;
7558
7559 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7560 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7561 } else {
7562 if (clock->p1 == 2)
7563 dpll |= PLL_P1_DIVIDE_BY_TWO;
7564 else
7565 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7566 if (clock->p2 == 4)
7567 dpll |= PLL_P2_DIVIDE_BY_4;
7568 }
7569
7570 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7571 dpll |= DPLL_DVO_2X_MODE;
7572
7573 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7574 intel_panel_use_ssc(dev_priv))
7575 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7576 else
7577 dpll |= PLL_REF_INPUT_DREFCLK;
7578
7579 dpll |= DPLL_VCO_ENABLE;
7580 crtc_state->dpll_hw_state.dpll = dpll;
7581 }
7582
7583 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7584 {
7585 struct drm_device *dev = intel_crtc->base.dev;
7586 struct drm_i915_private *dev_priv = dev->dev_private;
7587 enum pipe pipe = intel_crtc->pipe;
7588 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7589 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7590 uint32_t crtc_vtotal, crtc_vblank_end;
7591 int vsyncshift = 0;
7592
7593 /* We need to be careful not to changed the adjusted mode, for otherwise
7594 * the hw state checker will get angry at the mismatch. */
7595 crtc_vtotal = adjusted_mode->crtc_vtotal;
7596 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7597
7598 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7599 /* the chip adds 2 halflines automatically */
7600 crtc_vtotal -= 1;
7601 crtc_vblank_end -= 1;
7602
7603 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7604 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7605 else
7606 vsyncshift = adjusted_mode->crtc_hsync_start -
7607 adjusted_mode->crtc_htotal / 2;
7608 if (vsyncshift < 0)
7609 vsyncshift += adjusted_mode->crtc_htotal;
7610 }
7611
7612 if (INTEL_INFO(dev)->gen > 3)
7613 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7614
7615 I915_WRITE(HTOTAL(cpu_transcoder),
7616 (adjusted_mode->crtc_hdisplay - 1) |
7617 ((adjusted_mode->crtc_htotal - 1) << 16));
7618 I915_WRITE(HBLANK(cpu_transcoder),
7619 (adjusted_mode->crtc_hblank_start - 1) |
7620 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7621 I915_WRITE(HSYNC(cpu_transcoder),
7622 (adjusted_mode->crtc_hsync_start - 1) |
7623 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7624
7625 I915_WRITE(VTOTAL(cpu_transcoder),
7626 (adjusted_mode->crtc_vdisplay - 1) |
7627 ((crtc_vtotal - 1) << 16));
7628 I915_WRITE(VBLANK(cpu_transcoder),
7629 (adjusted_mode->crtc_vblank_start - 1) |
7630 ((crtc_vblank_end - 1) << 16));
7631 I915_WRITE(VSYNC(cpu_transcoder),
7632 (adjusted_mode->crtc_vsync_start - 1) |
7633 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7634
7635 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7636 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7637 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7638 * bits. */
7639 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7640 (pipe == PIPE_B || pipe == PIPE_C))
7641 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7642
7643 }
7644
7645 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7646 {
7647 struct drm_device *dev = intel_crtc->base.dev;
7648 struct drm_i915_private *dev_priv = dev->dev_private;
7649 enum pipe pipe = intel_crtc->pipe;
7650
7651 /* pipesrc controls the size that is scaled from, which should
7652 * always be the user's requested size.
7653 */
7654 I915_WRITE(PIPESRC(pipe),
7655 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7656 (intel_crtc->config->pipe_src_h - 1));
7657 }
7658
7659 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7660 struct intel_crtc_state *pipe_config)
7661 {
7662 struct drm_device *dev = crtc->base.dev;
7663 struct drm_i915_private *dev_priv = dev->dev_private;
7664 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7665 uint32_t tmp;
7666
7667 tmp = I915_READ(HTOTAL(cpu_transcoder));
7668 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7669 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7670 tmp = I915_READ(HBLANK(cpu_transcoder));
7671 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7672 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7673 tmp = I915_READ(HSYNC(cpu_transcoder));
7674 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7675 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7676
7677 tmp = I915_READ(VTOTAL(cpu_transcoder));
7678 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7679 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7680 tmp = I915_READ(VBLANK(cpu_transcoder));
7681 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7682 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7683 tmp = I915_READ(VSYNC(cpu_transcoder));
7684 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7685 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7686
7687 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7688 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7689 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7690 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7691 }
7692 }
7693
7694 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7695 struct intel_crtc_state *pipe_config)
7696 {
7697 struct drm_device *dev = crtc->base.dev;
7698 struct drm_i915_private *dev_priv = dev->dev_private;
7699 u32 tmp;
7700
7701 tmp = I915_READ(PIPESRC(crtc->pipe));
7702 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7703 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7704
7705 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7706 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7707 }
7708
7709 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7710 struct intel_crtc_state *pipe_config)
7711 {
7712 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7713 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7714 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7715 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7716
7717 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7718 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7719 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7720 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7721
7722 mode->flags = pipe_config->base.adjusted_mode.flags;
7723 mode->type = DRM_MODE_TYPE_DRIVER;
7724
7725 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7726 mode->flags |= pipe_config->base.adjusted_mode.flags;
7727
7728 mode->hsync = drm_mode_hsync(mode);
7729 mode->vrefresh = drm_mode_vrefresh(mode);
7730 drm_mode_set_name(mode);
7731 }
7732
7733 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7734 {
7735 struct drm_device *dev = intel_crtc->base.dev;
7736 struct drm_i915_private *dev_priv = dev->dev_private;
7737 uint32_t pipeconf;
7738
7739 pipeconf = 0;
7740
7741 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7742 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7743 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7744
7745 if (intel_crtc->config->double_wide)
7746 pipeconf |= PIPECONF_DOUBLE_WIDE;
7747
7748 /* only g4x and later have fancy bpc/dither controls */
7749 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7750 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7751 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7752 pipeconf |= PIPECONF_DITHER_EN |
7753 PIPECONF_DITHER_TYPE_SP;
7754
7755 switch (intel_crtc->config->pipe_bpp) {
7756 case 18:
7757 pipeconf |= PIPECONF_6BPC;
7758 break;
7759 case 24:
7760 pipeconf |= PIPECONF_8BPC;
7761 break;
7762 case 30:
7763 pipeconf |= PIPECONF_10BPC;
7764 break;
7765 default:
7766 /* Case prevented by intel_choose_pipe_bpp_dither. */
7767 BUG();
7768 }
7769 }
7770
7771 if (HAS_PIPE_CXSR(dev)) {
7772 if (intel_crtc->lowfreq_avail) {
7773 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7774 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7775 } else {
7776 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7777 }
7778 }
7779
7780 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7781 if (INTEL_INFO(dev)->gen < 4 ||
7782 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7783 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7784 else
7785 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7786 } else
7787 pipeconf |= PIPECONF_PROGRESSIVE;
7788
7789 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7790 intel_crtc->config->limited_color_range)
7791 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7792
7793 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7794 POSTING_READ(PIPECONF(intel_crtc->pipe));
7795 }
7796
7797 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7798 struct intel_crtc_state *crtc_state)
7799 {
7800 struct drm_device *dev = crtc->base.dev;
7801 struct drm_i915_private *dev_priv = dev->dev_private;
7802 const struct intel_limit *limit;
7803 int refclk = 48000;
7804
7805 memset(&crtc_state->dpll_hw_state, 0,
7806 sizeof(crtc_state->dpll_hw_state));
7807
7808 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7809 if (intel_panel_use_ssc(dev_priv)) {
7810 refclk = dev_priv->vbt.lvds_ssc_freq;
7811 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7812 }
7813
7814 limit = &intel_limits_i8xx_lvds;
7815 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7816 limit = &intel_limits_i8xx_dvo;
7817 } else {
7818 limit = &intel_limits_i8xx_dac;
7819 }
7820
7821 if (!crtc_state->clock_set &&
7822 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7823 refclk, NULL, &crtc_state->dpll)) {
7824 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7825 return -EINVAL;
7826 }
7827
7828 i8xx_compute_dpll(crtc, crtc_state, NULL);
7829
7830 return 0;
7831 }
7832
7833 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7834 struct intel_crtc_state *crtc_state)
7835 {
7836 struct drm_device *dev = crtc->base.dev;
7837 struct drm_i915_private *dev_priv = dev->dev_private;
7838 const struct intel_limit *limit;
7839 int refclk = 96000;
7840
7841 memset(&crtc_state->dpll_hw_state, 0,
7842 sizeof(crtc_state->dpll_hw_state));
7843
7844 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7845 if (intel_panel_use_ssc(dev_priv)) {
7846 refclk = dev_priv->vbt.lvds_ssc_freq;
7847 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7848 }
7849
7850 if (intel_is_dual_link_lvds(dev))
7851 limit = &intel_limits_g4x_dual_channel_lvds;
7852 else
7853 limit = &intel_limits_g4x_single_channel_lvds;
7854 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7855 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7856 limit = &intel_limits_g4x_hdmi;
7857 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7858 limit = &intel_limits_g4x_sdvo;
7859 } else {
7860 /* The option is for other outputs */
7861 limit = &intel_limits_i9xx_sdvo;
7862 }
7863
7864 if (!crtc_state->clock_set &&
7865 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7866 refclk, NULL, &crtc_state->dpll)) {
7867 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7868 return -EINVAL;
7869 }
7870
7871 i9xx_compute_dpll(crtc, crtc_state, NULL);
7872
7873 return 0;
7874 }
7875
7876 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7877 struct intel_crtc_state *crtc_state)
7878 {
7879 struct drm_device *dev = crtc->base.dev;
7880 struct drm_i915_private *dev_priv = dev->dev_private;
7881 const struct intel_limit *limit;
7882 int refclk = 96000;
7883
7884 memset(&crtc_state->dpll_hw_state, 0,
7885 sizeof(crtc_state->dpll_hw_state));
7886
7887 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7888 if (intel_panel_use_ssc(dev_priv)) {
7889 refclk = dev_priv->vbt.lvds_ssc_freq;
7890 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7891 }
7892
7893 limit = &intel_limits_pineview_lvds;
7894 } else {
7895 limit = &intel_limits_pineview_sdvo;
7896 }
7897
7898 if (!crtc_state->clock_set &&
7899 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7900 refclk, NULL, &crtc_state->dpll)) {
7901 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7902 return -EINVAL;
7903 }
7904
7905 i9xx_compute_dpll(crtc, crtc_state, NULL);
7906
7907 return 0;
7908 }
7909
7910 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7911 struct intel_crtc_state *crtc_state)
7912 {
7913 struct drm_device *dev = crtc->base.dev;
7914 struct drm_i915_private *dev_priv = dev->dev_private;
7915 const struct intel_limit *limit;
7916 int refclk = 96000;
7917
7918 memset(&crtc_state->dpll_hw_state, 0,
7919 sizeof(crtc_state->dpll_hw_state));
7920
7921 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7922 if (intel_panel_use_ssc(dev_priv)) {
7923 refclk = dev_priv->vbt.lvds_ssc_freq;
7924 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7925 }
7926
7927 limit = &intel_limits_i9xx_lvds;
7928 } else {
7929 limit = &intel_limits_i9xx_sdvo;
7930 }
7931
7932 if (!crtc_state->clock_set &&
7933 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7934 refclk, NULL, &crtc_state->dpll)) {
7935 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7936 return -EINVAL;
7937 }
7938
7939 i9xx_compute_dpll(crtc, crtc_state, NULL);
7940
7941 return 0;
7942 }
7943
7944 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7945 struct intel_crtc_state *crtc_state)
7946 {
7947 int refclk = 100000;
7948 const struct intel_limit *limit = &intel_limits_chv;
7949
7950 memset(&crtc_state->dpll_hw_state, 0,
7951 sizeof(crtc_state->dpll_hw_state));
7952
7953 if (!crtc_state->clock_set &&
7954 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7955 refclk, NULL, &crtc_state->dpll)) {
7956 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7957 return -EINVAL;
7958 }
7959
7960 chv_compute_dpll(crtc, crtc_state);
7961
7962 return 0;
7963 }
7964
7965 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7966 struct intel_crtc_state *crtc_state)
7967 {
7968 int refclk = 100000;
7969 const struct intel_limit *limit = &intel_limits_vlv;
7970
7971 memset(&crtc_state->dpll_hw_state, 0,
7972 sizeof(crtc_state->dpll_hw_state));
7973
7974 if (!crtc_state->clock_set &&
7975 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7976 refclk, NULL, &crtc_state->dpll)) {
7977 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7978 return -EINVAL;
7979 }
7980
7981 vlv_compute_dpll(crtc, crtc_state);
7982
7983 return 0;
7984 }
7985
7986 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7987 struct intel_crtc_state *pipe_config)
7988 {
7989 struct drm_device *dev = crtc->base.dev;
7990 struct drm_i915_private *dev_priv = dev->dev_private;
7991 uint32_t tmp;
7992
7993 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7994 return;
7995
7996 tmp = I915_READ(PFIT_CONTROL);
7997 if (!(tmp & PFIT_ENABLE))
7998 return;
7999
8000 /* Check whether the pfit is attached to our pipe. */
8001 if (INTEL_INFO(dev)->gen < 4) {
8002 if (crtc->pipe != PIPE_B)
8003 return;
8004 } else {
8005 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8006 return;
8007 }
8008
8009 pipe_config->gmch_pfit.control = tmp;
8010 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8011 }
8012
8013 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8014 struct intel_crtc_state *pipe_config)
8015 {
8016 struct drm_device *dev = crtc->base.dev;
8017 struct drm_i915_private *dev_priv = dev->dev_private;
8018 int pipe = pipe_config->cpu_transcoder;
8019 struct dpll clock;
8020 u32 mdiv;
8021 int refclk = 100000;
8022
8023 /* In case of DSI, DPLL will not be used */
8024 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8025 return;
8026
8027 mutex_lock(&dev_priv->sb_lock);
8028 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8029 mutex_unlock(&dev_priv->sb_lock);
8030
8031 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8032 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8033 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8034 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8035 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8036
8037 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8038 }
8039
8040 static void
8041 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8042 struct intel_initial_plane_config *plane_config)
8043 {
8044 struct drm_device *dev = crtc->base.dev;
8045 struct drm_i915_private *dev_priv = dev->dev_private;
8046 u32 val, base, offset;
8047 int pipe = crtc->pipe, plane = crtc->plane;
8048 int fourcc, pixel_format;
8049 unsigned int aligned_height;
8050 struct drm_framebuffer *fb;
8051 struct intel_framebuffer *intel_fb;
8052
8053 val = I915_READ(DSPCNTR(plane));
8054 if (!(val & DISPLAY_PLANE_ENABLE))
8055 return;
8056
8057 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8058 if (!intel_fb) {
8059 DRM_DEBUG_KMS("failed to alloc fb\n");
8060 return;
8061 }
8062
8063 fb = &intel_fb->base;
8064
8065 if (INTEL_INFO(dev)->gen >= 4) {
8066 if (val & DISPPLANE_TILED) {
8067 plane_config->tiling = I915_TILING_X;
8068 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8069 }
8070 }
8071
8072 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8073 fourcc = i9xx_format_to_fourcc(pixel_format);
8074 fb->pixel_format = fourcc;
8075 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8076
8077 if (INTEL_INFO(dev)->gen >= 4) {
8078 if (plane_config->tiling)
8079 offset = I915_READ(DSPTILEOFF(plane));
8080 else
8081 offset = I915_READ(DSPLINOFF(plane));
8082 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8083 } else {
8084 base = I915_READ(DSPADDR(plane));
8085 }
8086 plane_config->base = base;
8087
8088 val = I915_READ(PIPESRC(pipe));
8089 fb->width = ((val >> 16) & 0xfff) + 1;
8090 fb->height = ((val >> 0) & 0xfff) + 1;
8091
8092 val = I915_READ(DSPSTRIDE(pipe));
8093 fb->pitches[0] = val & 0xffffffc0;
8094
8095 aligned_height = intel_fb_align_height(dev, fb->height,
8096 fb->pixel_format,
8097 fb->modifier[0]);
8098
8099 plane_config->size = fb->pitches[0] * aligned_height;
8100
8101 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8102 pipe_name(pipe), plane, fb->width, fb->height,
8103 fb->bits_per_pixel, base, fb->pitches[0],
8104 plane_config->size);
8105
8106 plane_config->fb = intel_fb;
8107 }
8108
8109 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8110 struct intel_crtc_state *pipe_config)
8111 {
8112 struct drm_device *dev = crtc->base.dev;
8113 struct drm_i915_private *dev_priv = dev->dev_private;
8114 int pipe = pipe_config->cpu_transcoder;
8115 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8116 struct dpll clock;
8117 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8118 int refclk = 100000;
8119
8120 /* In case of DSI, DPLL will not be used */
8121 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8122 return;
8123
8124 mutex_lock(&dev_priv->sb_lock);
8125 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8126 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8127 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8128 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8129 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8130 mutex_unlock(&dev_priv->sb_lock);
8131
8132 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8133 clock.m2 = (pll_dw0 & 0xff) << 22;
8134 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8135 clock.m2 |= pll_dw2 & 0x3fffff;
8136 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8137 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8138 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8139
8140 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8141 }
8142
8143 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8144 struct intel_crtc_state *pipe_config)
8145 {
8146 struct drm_device *dev = crtc->base.dev;
8147 struct drm_i915_private *dev_priv = dev->dev_private;
8148 enum intel_display_power_domain power_domain;
8149 uint32_t tmp;
8150 bool ret;
8151
8152 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8153 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8154 return false;
8155
8156 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8157 pipe_config->shared_dpll = NULL;
8158
8159 ret = false;
8160
8161 tmp = I915_READ(PIPECONF(crtc->pipe));
8162 if (!(tmp & PIPECONF_ENABLE))
8163 goto out;
8164
8165 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8166 switch (tmp & PIPECONF_BPC_MASK) {
8167 case PIPECONF_6BPC:
8168 pipe_config->pipe_bpp = 18;
8169 break;
8170 case PIPECONF_8BPC:
8171 pipe_config->pipe_bpp = 24;
8172 break;
8173 case PIPECONF_10BPC:
8174 pipe_config->pipe_bpp = 30;
8175 break;
8176 default:
8177 break;
8178 }
8179 }
8180
8181 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8182 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8183 pipe_config->limited_color_range = true;
8184
8185 if (INTEL_INFO(dev)->gen < 4)
8186 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8187
8188 intel_get_pipe_timings(crtc, pipe_config);
8189 intel_get_pipe_src_size(crtc, pipe_config);
8190
8191 i9xx_get_pfit_config(crtc, pipe_config);
8192
8193 if (INTEL_INFO(dev)->gen >= 4) {
8194 /* No way to read it out on pipes B and C */
8195 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8196 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8197 else
8198 tmp = I915_READ(DPLL_MD(crtc->pipe));
8199 pipe_config->pixel_multiplier =
8200 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8201 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8202 pipe_config->dpll_hw_state.dpll_md = tmp;
8203 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8204 tmp = I915_READ(DPLL(crtc->pipe));
8205 pipe_config->pixel_multiplier =
8206 ((tmp & SDVO_MULTIPLIER_MASK)
8207 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8208 } else {
8209 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8210 * port and will be fixed up in the encoder->get_config
8211 * function. */
8212 pipe_config->pixel_multiplier = 1;
8213 }
8214 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8215 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8216 /*
8217 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8218 * on 830. Filter it out here so that we don't
8219 * report errors due to that.
8220 */
8221 if (IS_I830(dev))
8222 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8223
8224 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8225 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8226 } else {
8227 /* Mask out read-only status bits. */
8228 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8229 DPLL_PORTC_READY_MASK |
8230 DPLL_PORTB_READY_MASK);
8231 }
8232
8233 if (IS_CHERRYVIEW(dev))
8234 chv_crtc_clock_get(crtc, pipe_config);
8235 else if (IS_VALLEYVIEW(dev))
8236 vlv_crtc_clock_get(crtc, pipe_config);
8237 else
8238 i9xx_crtc_clock_get(crtc, pipe_config);
8239
8240 /*
8241 * Normally the dotclock is filled in by the encoder .get_config()
8242 * but in case the pipe is enabled w/o any ports we need a sane
8243 * default.
8244 */
8245 pipe_config->base.adjusted_mode.crtc_clock =
8246 pipe_config->port_clock / pipe_config->pixel_multiplier;
8247
8248 ret = true;
8249
8250 out:
8251 intel_display_power_put(dev_priv, power_domain);
8252
8253 return ret;
8254 }
8255
8256 static void ironlake_init_pch_refclk(struct drm_device *dev)
8257 {
8258 struct drm_i915_private *dev_priv = dev->dev_private;
8259 struct intel_encoder *encoder;
8260 u32 val, final;
8261 bool has_lvds = false;
8262 bool has_cpu_edp = false;
8263 bool has_panel = false;
8264 bool has_ck505 = false;
8265 bool can_ssc = false;
8266
8267 /* We need to take the global config into account */
8268 for_each_intel_encoder(dev, encoder) {
8269 switch (encoder->type) {
8270 case INTEL_OUTPUT_LVDS:
8271 has_panel = true;
8272 has_lvds = true;
8273 break;
8274 case INTEL_OUTPUT_EDP:
8275 has_panel = true;
8276 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8277 has_cpu_edp = true;
8278 break;
8279 default:
8280 break;
8281 }
8282 }
8283
8284 if (HAS_PCH_IBX(dev)) {
8285 has_ck505 = dev_priv->vbt.display_clock_mode;
8286 can_ssc = has_ck505;
8287 } else {
8288 has_ck505 = false;
8289 can_ssc = true;
8290 }
8291
8292 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8293 has_panel, has_lvds, has_ck505);
8294
8295 /* Ironlake: try to setup display ref clock before DPLL
8296 * enabling. This is only under driver's control after
8297 * PCH B stepping, previous chipset stepping should be
8298 * ignoring this setting.
8299 */
8300 val = I915_READ(PCH_DREF_CONTROL);
8301
8302 /* As we must carefully and slowly disable/enable each source in turn,
8303 * compute the final state we want first and check if we need to
8304 * make any changes at all.
8305 */
8306 final = val;
8307 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8308 if (has_ck505)
8309 final |= DREF_NONSPREAD_CK505_ENABLE;
8310 else
8311 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8312
8313 final &= ~DREF_SSC_SOURCE_MASK;
8314 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8315 final &= ~DREF_SSC1_ENABLE;
8316
8317 if (has_panel) {
8318 final |= DREF_SSC_SOURCE_ENABLE;
8319
8320 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8321 final |= DREF_SSC1_ENABLE;
8322
8323 if (has_cpu_edp) {
8324 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8325 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8326 else
8327 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8328 } else
8329 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8330 } else {
8331 final |= DREF_SSC_SOURCE_DISABLE;
8332 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8333 }
8334
8335 if (final == val)
8336 return;
8337
8338 /* Always enable nonspread source */
8339 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8340
8341 if (has_ck505)
8342 val |= DREF_NONSPREAD_CK505_ENABLE;
8343 else
8344 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8345
8346 if (has_panel) {
8347 val &= ~DREF_SSC_SOURCE_MASK;
8348 val |= DREF_SSC_SOURCE_ENABLE;
8349
8350 /* SSC must be turned on before enabling the CPU output */
8351 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8352 DRM_DEBUG_KMS("Using SSC on panel\n");
8353 val |= DREF_SSC1_ENABLE;
8354 } else
8355 val &= ~DREF_SSC1_ENABLE;
8356
8357 /* Get SSC going before enabling the outputs */
8358 I915_WRITE(PCH_DREF_CONTROL, val);
8359 POSTING_READ(PCH_DREF_CONTROL);
8360 udelay(200);
8361
8362 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8363
8364 /* Enable CPU source on CPU attached eDP */
8365 if (has_cpu_edp) {
8366 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8367 DRM_DEBUG_KMS("Using SSC on eDP\n");
8368 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8369 } else
8370 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8371 } else
8372 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8373
8374 I915_WRITE(PCH_DREF_CONTROL, val);
8375 POSTING_READ(PCH_DREF_CONTROL);
8376 udelay(200);
8377 } else {
8378 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8379
8380 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8381
8382 /* Turn off CPU output */
8383 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8384
8385 I915_WRITE(PCH_DREF_CONTROL, val);
8386 POSTING_READ(PCH_DREF_CONTROL);
8387 udelay(200);
8388
8389 /* Turn off the SSC source */
8390 val &= ~DREF_SSC_SOURCE_MASK;
8391 val |= DREF_SSC_SOURCE_DISABLE;
8392
8393 /* Turn off SSC1 */
8394 val &= ~DREF_SSC1_ENABLE;
8395
8396 I915_WRITE(PCH_DREF_CONTROL, val);
8397 POSTING_READ(PCH_DREF_CONTROL);
8398 udelay(200);
8399 }
8400
8401 BUG_ON(val != final);
8402 }
8403
8404 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8405 {
8406 uint32_t tmp;
8407
8408 tmp = I915_READ(SOUTH_CHICKEN2);
8409 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8410 I915_WRITE(SOUTH_CHICKEN2, tmp);
8411
8412 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8413 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8414 DRM_ERROR("FDI mPHY reset assert timeout\n");
8415
8416 tmp = I915_READ(SOUTH_CHICKEN2);
8417 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8418 I915_WRITE(SOUTH_CHICKEN2, tmp);
8419
8420 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8421 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8422 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8423 }
8424
8425 /* WaMPhyProgramming:hsw */
8426 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8427 {
8428 uint32_t tmp;
8429
8430 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8431 tmp &= ~(0xFF << 24);
8432 tmp |= (0x12 << 24);
8433 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8434
8435 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8436 tmp |= (1 << 11);
8437 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8438
8439 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8440 tmp |= (1 << 11);
8441 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8442
8443 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8444 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8445 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8446
8447 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8448 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8449 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8450
8451 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8452 tmp &= ~(7 << 13);
8453 tmp |= (5 << 13);
8454 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8455
8456 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8457 tmp &= ~(7 << 13);
8458 tmp |= (5 << 13);
8459 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8460
8461 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8462 tmp &= ~0xFF;
8463 tmp |= 0x1C;
8464 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8465
8466 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8467 tmp &= ~0xFF;
8468 tmp |= 0x1C;
8469 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8470
8471 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8472 tmp &= ~(0xFF << 16);
8473 tmp |= (0x1C << 16);
8474 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8475
8476 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8477 tmp &= ~(0xFF << 16);
8478 tmp |= (0x1C << 16);
8479 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8480
8481 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8482 tmp |= (1 << 27);
8483 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8484
8485 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8486 tmp |= (1 << 27);
8487 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8488
8489 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8490 tmp &= ~(0xF << 28);
8491 tmp |= (4 << 28);
8492 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8493
8494 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8495 tmp &= ~(0xF << 28);
8496 tmp |= (4 << 28);
8497 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8498 }
8499
8500 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8501 * Programming" based on the parameters passed:
8502 * - Sequence to enable CLKOUT_DP
8503 * - Sequence to enable CLKOUT_DP without spread
8504 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8505 */
8506 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8507 bool with_fdi)
8508 {
8509 struct drm_i915_private *dev_priv = dev->dev_private;
8510 uint32_t reg, tmp;
8511
8512 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8513 with_spread = true;
8514 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8515 with_fdi = false;
8516
8517 mutex_lock(&dev_priv->sb_lock);
8518
8519 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8520 tmp &= ~SBI_SSCCTL_DISABLE;
8521 tmp |= SBI_SSCCTL_PATHALT;
8522 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8523
8524 udelay(24);
8525
8526 if (with_spread) {
8527 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8528 tmp &= ~SBI_SSCCTL_PATHALT;
8529 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8530
8531 if (with_fdi) {
8532 lpt_reset_fdi_mphy(dev_priv);
8533 lpt_program_fdi_mphy(dev_priv);
8534 }
8535 }
8536
8537 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8538 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8539 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8540 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8541
8542 mutex_unlock(&dev_priv->sb_lock);
8543 }
8544
8545 /* Sequence to disable CLKOUT_DP */
8546 static void lpt_disable_clkout_dp(struct drm_device *dev)
8547 {
8548 struct drm_i915_private *dev_priv = dev->dev_private;
8549 uint32_t reg, tmp;
8550
8551 mutex_lock(&dev_priv->sb_lock);
8552
8553 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8554 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8555 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8556 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8557
8558 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8559 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8560 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8561 tmp |= SBI_SSCCTL_PATHALT;
8562 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8563 udelay(32);
8564 }
8565 tmp |= SBI_SSCCTL_DISABLE;
8566 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8567 }
8568
8569 mutex_unlock(&dev_priv->sb_lock);
8570 }
8571
8572 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8573
8574 static const uint16_t sscdivintphase[] = {
8575 [BEND_IDX( 50)] = 0x3B23,
8576 [BEND_IDX( 45)] = 0x3B23,
8577 [BEND_IDX( 40)] = 0x3C23,
8578 [BEND_IDX( 35)] = 0x3C23,
8579 [BEND_IDX( 30)] = 0x3D23,
8580 [BEND_IDX( 25)] = 0x3D23,
8581 [BEND_IDX( 20)] = 0x3E23,
8582 [BEND_IDX( 15)] = 0x3E23,
8583 [BEND_IDX( 10)] = 0x3F23,
8584 [BEND_IDX( 5)] = 0x3F23,
8585 [BEND_IDX( 0)] = 0x0025,
8586 [BEND_IDX( -5)] = 0x0025,
8587 [BEND_IDX(-10)] = 0x0125,
8588 [BEND_IDX(-15)] = 0x0125,
8589 [BEND_IDX(-20)] = 0x0225,
8590 [BEND_IDX(-25)] = 0x0225,
8591 [BEND_IDX(-30)] = 0x0325,
8592 [BEND_IDX(-35)] = 0x0325,
8593 [BEND_IDX(-40)] = 0x0425,
8594 [BEND_IDX(-45)] = 0x0425,
8595 [BEND_IDX(-50)] = 0x0525,
8596 };
8597
8598 /*
8599 * Bend CLKOUT_DP
8600 * steps -50 to 50 inclusive, in steps of 5
8601 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8602 * change in clock period = -(steps / 10) * 5.787 ps
8603 */
8604 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8605 {
8606 uint32_t tmp;
8607 int idx = BEND_IDX(steps);
8608
8609 if (WARN_ON(steps % 5 != 0))
8610 return;
8611
8612 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8613 return;
8614
8615 mutex_lock(&dev_priv->sb_lock);
8616
8617 if (steps % 10 != 0)
8618 tmp = 0xAAAAAAAB;
8619 else
8620 tmp = 0x00000000;
8621 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8622
8623 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8624 tmp &= 0xffff0000;
8625 tmp |= sscdivintphase[idx];
8626 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8627
8628 mutex_unlock(&dev_priv->sb_lock);
8629 }
8630
8631 #undef BEND_IDX
8632
8633 static void lpt_init_pch_refclk(struct drm_device *dev)
8634 {
8635 struct intel_encoder *encoder;
8636 bool has_vga = false;
8637
8638 for_each_intel_encoder(dev, encoder) {
8639 switch (encoder->type) {
8640 case INTEL_OUTPUT_ANALOG:
8641 has_vga = true;
8642 break;
8643 default:
8644 break;
8645 }
8646 }
8647
8648 if (has_vga) {
8649 lpt_bend_clkout_dp(to_i915(dev), 0);
8650 lpt_enable_clkout_dp(dev, true, true);
8651 } else {
8652 lpt_disable_clkout_dp(dev);
8653 }
8654 }
8655
8656 /*
8657 * Initialize reference clocks when the driver loads
8658 */
8659 void intel_init_pch_refclk(struct drm_device *dev)
8660 {
8661 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8662 ironlake_init_pch_refclk(dev);
8663 else if (HAS_PCH_LPT(dev))
8664 lpt_init_pch_refclk(dev);
8665 }
8666
8667 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8668 {
8669 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8671 int pipe = intel_crtc->pipe;
8672 uint32_t val;
8673
8674 val = 0;
8675
8676 switch (intel_crtc->config->pipe_bpp) {
8677 case 18:
8678 val |= PIPECONF_6BPC;
8679 break;
8680 case 24:
8681 val |= PIPECONF_8BPC;
8682 break;
8683 case 30:
8684 val |= PIPECONF_10BPC;
8685 break;
8686 case 36:
8687 val |= PIPECONF_12BPC;
8688 break;
8689 default:
8690 /* Case prevented by intel_choose_pipe_bpp_dither. */
8691 BUG();
8692 }
8693
8694 if (intel_crtc->config->dither)
8695 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8696
8697 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8698 val |= PIPECONF_INTERLACED_ILK;
8699 else
8700 val |= PIPECONF_PROGRESSIVE;
8701
8702 if (intel_crtc->config->limited_color_range)
8703 val |= PIPECONF_COLOR_RANGE_SELECT;
8704
8705 I915_WRITE(PIPECONF(pipe), val);
8706 POSTING_READ(PIPECONF(pipe));
8707 }
8708
8709 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8710 {
8711 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8713 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8714 u32 val = 0;
8715
8716 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8717 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8718
8719 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8720 val |= PIPECONF_INTERLACED_ILK;
8721 else
8722 val |= PIPECONF_PROGRESSIVE;
8723
8724 I915_WRITE(PIPECONF(cpu_transcoder), val);
8725 POSTING_READ(PIPECONF(cpu_transcoder));
8726 }
8727
8728 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8729 {
8730 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8732
8733 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8734 u32 val = 0;
8735
8736 switch (intel_crtc->config->pipe_bpp) {
8737 case 18:
8738 val |= PIPEMISC_DITHER_6_BPC;
8739 break;
8740 case 24:
8741 val |= PIPEMISC_DITHER_8_BPC;
8742 break;
8743 case 30:
8744 val |= PIPEMISC_DITHER_10_BPC;
8745 break;
8746 case 36:
8747 val |= PIPEMISC_DITHER_12_BPC;
8748 break;
8749 default:
8750 /* Case prevented by pipe_config_set_bpp. */
8751 BUG();
8752 }
8753
8754 if (intel_crtc->config->dither)
8755 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8756
8757 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8758 }
8759 }
8760
8761 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8762 {
8763 /*
8764 * Account for spread spectrum to avoid
8765 * oversubscribing the link. Max center spread
8766 * is 2.5%; use 5% for safety's sake.
8767 */
8768 u32 bps = target_clock * bpp * 21 / 20;
8769 return DIV_ROUND_UP(bps, link_bw * 8);
8770 }
8771
8772 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8773 {
8774 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8775 }
8776
8777 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8778 struct intel_crtc_state *crtc_state,
8779 struct dpll *reduced_clock)
8780 {
8781 struct drm_crtc *crtc = &intel_crtc->base;
8782 struct drm_device *dev = crtc->dev;
8783 struct drm_i915_private *dev_priv = dev->dev_private;
8784 struct drm_atomic_state *state = crtc_state->base.state;
8785 struct drm_connector *connector;
8786 struct drm_connector_state *connector_state;
8787 struct intel_encoder *encoder;
8788 u32 dpll, fp, fp2;
8789 int factor, i;
8790 bool is_lvds = false, is_sdvo = false;
8791
8792 for_each_connector_in_state(state, connector, connector_state, i) {
8793 if (connector_state->crtc != crtc_state->base.crtc)
8794 continue;
8795
8796 encoder = to_intel_encoder(connector_state->best_encoder);
8797
8798 switch (encoder->type) {
8799 case INTEL_OUTPUT_LVDS:
8800 is_lvds = true;
8801 break;
8802 case INTEL_OUTPUT_SDVO:
8803 case INTEL_OUTPUT_HDMI:
8804 is_sdvo = true;
8805 break;
8806 default:
8807 break;
8808 }
8809 }
8810
8811 /* Enable autotuning of the PLL clock (if permissible) */
8812 factor = 21;
8813 if (is_lvds) {
8814 if ((intel_panel_use_ssc(dev_priv) &&
8815 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8816 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8817 factor = 25;
8818 } else if (crtc_state->sdvo_tv_clock)
8819 factor = 20;
8820
8821 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8822
8823 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8824 fp |= FP_CB_TUNE;
8825
8826 if (reduced_clock) {
8827 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8828
8829 if (reduced_clock->m < factor * reduced_clock->n)
8830 fp2 |= FP_CB_TUNE;
8831 } else {
8832 fp2 = fp;
8833 }
8834
8835 dpll = 0;
8836
8837 if (is_lvds)
8838 dpll |= DPLLB_MODE_LVDS;
8839 else
8840 dpll |= DPLLB_MODE_DAC_SERIAL;
8841
8842 dpll |= (crtc_state->pixel_multiplier - 1)
8843 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8844
8845 if (is_sdvo)
8846 dpll |= DPLL_SDVO_HIGH_SPEED;
8847 if (crtc_state->has_dp_encoder)
8848 dpll |= DPLL_SDVO_HIGH_SPEED;
8849
8850 /* compute bitmask from p1 value */
8851 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8852 /* also FPA1 */
8853 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8854
8855 switch (crtc_state->dpll.p2) {
8856 case 5:
8857 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8858 break;
8859 case 7:
8860 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8861 break;
8862 case 10:
8863 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8864 break;
8865 case 14:
8866 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8867 break;
8868 }
8869
8870 if (is_lvds && intel_panel_use_ssc(dev_priv))
8871 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8872 else
8873 dpll |= PLL_REF_INPUT_DREFCLK;
8874
8875 dpll |= DPLL_VCO_ENABLE;
8876
8877 crtc_state->dpll_hw_state.dpll = dpll;
8878 crtc_state->dpll_hw_state.fp0 = fp;
8879 crtc_state->dpll_hw_state.fp1 = fp2;
8880 }
8881
8882 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8883 struct intel_crtc_state *crtc_state)
8884 {
8885 struct drm_device *dev = crtc->base.dev;
8886 struct drm_i915_private *dev_priv = dev->dev_private;
8887 struct dpll reduced_clock;
8888 bool has_reduced_clock = false;
8889 struct intel_shared_dpll *pll;
8890 const struct intel_limit *limit;
8891 int refclk = 120000;
8892
8893 memset(&crtc_state->dpll_hw_state, 0,
8894 sizeof(crtc_state->dpll_hw_state));
8895
8896 crtc->lowfreq_avail = false;
8897
8898 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8899 if (!crtc_state->has_pch_encoder)
8900 return 0;
8901
8902 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8903 if (intel_panel_use_ssc(dev_priv)) {
8904 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8905 dev_priv->vbt.lvds_ssc_freq);
8906 refclk = dev_priv->vbt.lvds_ssc_freq;
8907 }
8908
8909 if (intel_is_dual_link_lvds(dev)) {
8910 if (refclk == 100000)
8911 limit = &intel_limits_ironlake_dual_lvds_100m;
8912 else
8913 limit = &intel_limits_ironlake_dual_lvds;
8914 } else {
8915 if (refclk == 100000)
8916 limit = &intel_limits_ironlake_single_lvds_100m;
8917 else
8918 limit = &intel_limits_ironlake_single_lvds;
8919 }
8920 } else {
8921 limit = &intel_limits_ironlake_dac;
8922 }
8923
8924 if (!crtc_state->clock_set &&
8925 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8926 refclk, NULL, &crtc_state->dpll)) {
8927 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8928 return -EINVAL;
8929 }
8930
8931 ironlake_compute_dpll(crtc, crtc_state,
8932 has_reduced_clock ? &reduced_clock : NULL);
8933
8934 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8935 if (pll == NULL) {
8936 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8937 pipe_name(crtc->pipe));
8938 return -EINVAL;
8939 }
8940
8941 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8942 has_reduced_clock)
8943 crtc->lowfreq_avail = true;
8944
8945 return 0;
8946 }
8947
8948 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8949 struct intel_link_m_n *m_n)
8950 {
8951 struct drm_device *dev = crtc->base.dev;
8952 struct drm_i915_private *dev_priv = dev->dev_private;
8953 enum pipe pipe = crtc->pipe;
8954
8955 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8956 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8957 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8958 & ~TU_SIZE_MASK;
8959 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8960 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8961 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8962 }
8963
8964 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8965 enum transcoder transcoder,
8966 struct intel_link_m_n *m_n,
8967 struct intel_link_m_n *m2_n2)
8968 {
8969 struct drm_device *dev = crtc->base.dev;
8970 struct drm_i915_private *dev_priv = dev->dev_private;
8971 enum pipe pipe = crtc->pipe;
8972
8973 if (INTEL_INFO(dev)->gen >= 5) {
8974 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8975 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8976 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8977 & ~TU_SIZE_MASK;
8978 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8979 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8980 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8981 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8982 * gen < 8) and if DRRS is supported (to make sure the
8983 * registers are not unnecessarily read).
8984 */
8985 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8986 crtc->config->has_drrs) {
8987 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8988 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8989 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8990 & ~TU_SIZE_MASK;
8991 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8992 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8993 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8994 }
8995 } else {
8996 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8997 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8998 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8999 & ~TU_SIZE_MASK;
9000 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9001 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9002 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9003 }
9004 }
9005
9006 void intel_dp_get_m_n(struct intel_crtc *crtc,
9007 struct intel_crtc_state *pipe_config)
9008 {
9009 if (pipe_config->has_pch_encoder)
9010 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9011 else
9012 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9013 &pipe_config->dp_m_n,
9014 &pipe_config->dp_m2_n2);
9015 }
9016
9017 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9018 struct intel_crtc_state *pipe_config)
9019 {
9020 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9021 &pipe_config->fdi_m_n, NULL);
9022 }
9023
9024 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9025 struct intel_crtc_state *pipe_config)
9026 {
9027 struct drm_device *dev = crtc->base.dev;
9028 struct drm_i915_private *dev_priv = dev->dev_private;
9029 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9030 uint32_t ps_ctrl = 0;
9031 int id = -1;
9032 int i;
9033
9034 /* find scaler attached to this pipe */
9035 for (i = 0; i < crtc->num_scalers; i++) {
9036 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9037 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9038 id = i;
9039 pipe_config->pch_pfit.enabled = true;
9040 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9041 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9042 break;
9043 }
9044 }
9045
9046 scaler_state->scaler_id = id;
9047 if (id >= 0) {
9048 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9049 } else {
9050 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9051 }
9052 }
9053
9054 static void
9055 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9056 struct intel_initial_plane_config *plane_config)
9057 {
9058 struct drm_device *dev = crtc->base.dev;
9059 struct drm_i915_private *dev_priv = dev->dev_private;
9060 u32 val, base, offset, stride_mult, tiling;
9061 int pipe = crtc->pipe;
9062 int fourcc, pixel_format;
9063 unsigned int aligned_height;
9064 struct drm_framebuffer *fb;
9065 struct intel_framebuffer *intel_fb;
9066
9067 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9068 if (!intel_fb) {
9069 DRM_DEBUG_KMS("failed to alloc fb\n");
9070 return;
9071 }
9072
9073 fb = &intel_fb->base;
9074
9075 val = I915_READ(PLANE_CTL(pipe, 0));
9076 if (!(val & PLANE_CTL_ENABLE))
9077 goto error;
9078
9079 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9080 fourcc = skl_format_to_fourcc(pixel_format,
9081 val & PLANE_CTL_ORDER_RGBX,
9082 val & PLANE_CTL_ALPHA_MASK);
9083 fb->pixel_format = fourcc;
9084 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9085
9086 tiling = val & PLANE_CTL_TILED_MASK;
9087 switch (tiling) {
9088 case PLANE_CTL_TILED_LINEAR:
9089 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9090 break;
9091 case PLANE_CTL_TILED_X:
9092 plane_config->tiling = I915_TILING_X;
9093 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9094 break;
9095 case PLANE_CTL_TILED_Y:
9096 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9097 break;
9098 case PLANE_CTL_TILED_YF:
9099 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9100 break;
9101 default:
9102 MISSING_CASE(tiling);
9103 goto error;
9104 }
9105
9106 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9107 plane_config->base = base;
9108
9109 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9110
9111 val = I915_READ(PLANE_SIZE(pipe, 0));
9112 fb->height = ((val >> 16) & 0xfff) + 1;
9113 fb->width = ((val >> 0) & 0x1fff) + 1;
9114
9115 val = I915_READ(PLANE_STRIDE(pipe, 0));
9116 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9117 fb->pixel_format);
9118 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9119
9120 aligned_height = intel_fb_align_height(dev, fb->height,
9121 fb->pixel_format,
9122 fb->modifier[0]);
9123
9124 plane_config->size = fb->pitches[0] * aligned_height;
9125
9126 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9127 pipe_name(pipe), fb->width, fb->height,
9128 fb->bits_per_pixel, base, fb->pitches[0],
9129 plane_config->size);
9130
9131 plane_config->fb = intel_fb;
9132 return;
9133
9134 error:
9135 kfree(fb);
9136 }
9137
9138 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9139 struct intel_crtc_state *pipe_config)
9140 {
9141 struct drm_device *dev = crtc->base.dev;
9142 struct drm_i915_private *dev_priv = dev->dev_private;
9143 uint32_t tmp;
9144
9145 tmp = I915_READ(PF_CTL(crtc->pipe));
9146
9147 if (tmp & PF_ENABLE) {
9148 pipe_config->pch_pfit.enabled = true;
9149 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9150 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9151
9152 /* We currently do not free assignements of panel fitters on
9153 * ivb/hsw (since we don't use the higher upscaling modes which
9154 * differentiates them) so just WARN about this case for now. */
9155 if (IS_GEN7(dev)) {
9156 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9157 PF_PIPE_SEL_IVB(crtc->pipe));
9158 }
9159 }
9160 }
9161
9162 static void
9163 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9164 struct intel_initial_plane_config *plane_config)
9165 {
9166 struct drm_device *dev = crtc->base.dev;
9167 struct drm_i915_private *dev_priv = dev->dev_private;
9168 u32 val, base, offset;
9169 int pipe = crtc->pipe;
9170 int fourcc, pixel_format;
9171 unsigned int aligned_height;
9172 struct drm_framebuffer *fb;
9173 struct intel_framebuffer *intel_fb;
9174
9175 val = I915_READ(DSPCNTR(pipe));
9176 if (!(val & DISPLAY_PLANE_ENABLE))
9177 return;
9178
9179 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9180 if (!intel_fb) {
9181 DRM_DEBUG_KMS("failed to alloc fb\n");
9182 return;
9183 }
9184
9185 fb = &intel_fb->base;
9186
9187 if (INTEL_INFO(dev)->gen >= 4) {
9188 if (val & DISPPLANE_TILED) {
9189 plane_config->tiling = I915_TILING_X;
9190 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9191 }
9192 }
9193
9194 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9195 fourcc = i9xx_format_to_fourcc(pixel_format);
9196 fb->pixel_format = fourcc;
9197 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9198
9199 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9200 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9201 offset = I915_READ(DSPOFFSET(pipe));
9202 } else {
9203 if (plane_config->tiling)
9204 offset = I915_READ(DSPTILEOFF(pipe));
9205 else
9206 offset = I915_READ(DSPLINOFF(pipe));
9207 }
9208 plane_config->base = base;
9209
9210 val = I915_READ(PIPESRC(pipe));
9211 fb->width = ((val >> 16) & 0xfff) + 1;
9212 fb->height = ((val >> 0) & 0xfff) + 1;
9213
9214 val = I915_READ(DSPSTRIDE(pipe));
9215 fb->pitches[0] = val & 0xffffffc0;
9216
9217 aligned_height = intel_fb_align_height(dev, fb->height,
9218 fb->pixel_format,
9219 fb->modifier[0]);
9220
9221 plane_config->size = fb->pitches[0] * aligned_height;
9222
9223 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9224 pipe_name(pipe), fb->width, fb->height,
9225 fb->bits_per_pixel, base, fb->pitches[0],
9226 plane_config->size);
9227
9228 plane_config->fb = intel_fb;
9229 }
9230
9231 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9232 struct intel_crtc_state *pipe_config)
9233 {
9234 struct drm_device *dev = crtc->base.dev;
9235 struct drm_i915_private *dev_priv = dev->dev_private;
9236 enum intel_display_power_domain power_domain;
9237 uint32_t tmp;
9238 bool ret;
9239
9240 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9241 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9242 return false;
9243
9244 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9245 pipe_config->shared_dpll = NULL;
9246
9247 ret = false;
9248 tmp = I915_READ(PIPECONF(crtc->pipe));
9249 if (!(tmp & PIPECONF_ENABLE))
9250 goto out;
9251
9252 switch (tmp & PIPECONF_BPC_MASK) {
9253 case PIPECONF_6BPC:
9254 pipe_config->pipe_bpp = 18;
9255 break;
9256 case PIPECONF_8BPC:
9257 pipe_config->pipe_bpp = 24;
9258 break;
9259 case PIPECONF_10BPC:
9260 pipe_config->pipe_bpp = 30;
9261 break;
9262 case PIPECONF_12BPC:
9263 pipe_config->pipe_bpp = 36;
9264 break;
9265 default:
9266 break;
9267 }
9268
9269 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9270 pipe_config->limited_color_range = true;
9271
9272 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9273 struct intel_shared_dpll *pll;
9274 enum intel_dpll_id pll_id;
9275
9276 pipe_config->has_pch_encoder = true;
9277
9278 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9279 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9280 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9281
9282 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9283
9284 if (HAS_PCH_IBX(dev_priv)) {
9285 /*
9286 * The pipe->pch transcoder and pch transcoder->pll
9287 * mapping is fixed.
9288 */
9289 pll_id = (enum intel_dpll_id) crtc->pipe;
9290 } else {
9291 tmp = I915_READ(PCH_DPLL_SEL);
9292 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9293 pll_id = DPLL_ID_PCH_PLL_B;
9294 else
9295 pll_id= DPLL_ID_PCH_PLL_A;
9296 }
9297
9298 pipe_config->shared_dpll =
9299 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9300 pll = pipe_config->shared_dpll;
9301
9302 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9303 &pipe_config->dpll_hw_state));
9304
9305 tmp = pipe_config->dpll_hw_state.dpll;
9306 pipe_config->pixel_multiplier =
9307 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9308 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9309
9310 ironlake_pch_clock_get(crtc, pipe_config);
9311 } else {
9312 pipe_config->pixel_multiplier = 1;
9313 }
9314
9315 intel_get_pipe_timings(crtc, pipe_config);
9316 intel_get_pipe_src_size(crtc, pipe_config);
9317
9318 ironlake_get_pfit_config(crtc, pipe_config);
9319
9320 ret = true;
9321
9322 out:
9323 intel_display_power_put(dev_priv, power_domain);
9324
9325 return ret;
9326 }
9327
9328 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9329 {
9330 struct drm_device *dev = dev_priv->dev;
9331 struct intel_crtc *crtc;
9332
9333 for_each_intel_crtc(dev, crtc)
9334 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9335 pipe_name(crtc->pipe));
9336
9337 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9338 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9339 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9340 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9341 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9342 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9343 "CPU PWM1 enabled\n");
9344 if (IS_HASWELL(dev))
9345 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9346 "CPU PWM2 enabled\n");
9347 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9348 "PCH PWM1 enabled\n");
9349 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9350 "Utility pin enabled\n");
9351 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9352
9353 /*
9354 * In theory we can still leave IRQs enabled, as long as only the HPD
9355 * interrupts remain enabled. We used to check for that, but since it's
9356 * gen-specific and since we only disable LCPLL after we fully disable
9357 * the interrupts, the check below should be enough.
9358 */
9359 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9360 }
9361
9362 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9363 {
9364 struct drm_device *dev = dev_priv->dev;
9365
9366 if (IS_HASWELL(dev))
9367 return I915_READ(D_COMP_HSW);
9368 else
9369 return I915_READ(D_COMP_BDW);
9370 }
9371
9372 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9373 {
9374 struct drm_device *dev = dev_priv->dev;
9375
9376 if (IS_HASWELL(dev)) {
9377 mutex_lock(&dev_priv->rps.hw_lock);
9378 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9379 val))
9380 DRM_ERROR("Failed to write to D_COMP\n");
9381 mutex_unlock(&dev_priv->rps.hw_lock);
9382 } else {
9383 I915_WRITE(D_COMP_BDW, val);
9384 POSTING_READ(D_COMP_BDW);
9385 }
9386 }
9387
9388 /*
9389 * This function implements pieces of two sequences from BSpec:
9390 * - Sequence for display software to disable LCPLL
9391 * - Sequence for display software to allow package C8+
9392 * The steps implemented here are just the steps that actually touch the LCPLL
9393 * register. Callers should take care of disabling all the display engine
9394 * functions, doing the mode unset, fixing interrupts, etc.
9395 */
9396 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9397 bool switch_to_fclk, bool allow_power_down)
9398 {
9399 uint32_t val;
9400
9401 assert_can_disable_lcpll(dev_priv);
9402
9403 val = I915_READ(LCPLL_CTL);
9404
9405 if (switch_to_fclk) {
9406 val |= LCPLL_CD_SOURCE_FCLK;
9407 I915_WRITE(LCPLL_CTL, val);
9408
9409 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9410 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9411 DRM_ERROR("Switching to FCLK failed\n");
9412
9413 val = I915_READ(LCPLL_CTL);
9414 }
9415
9416 val |= LCPLL_PLL_DISABLE;
9417 I915_WRITE(LCPLL_CTL, val);
9418 POSTING_READ(LCPLL_CTL);
9419
9420 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9421 DRM_ERROR("LCPLL still locked\n");
9422
9423 val = hsw_read_dcomp(dev_priv);
9424 val |= D_COMP_COMP_DISABLE;
9425 hsw_write_dcomp(dev_priv, val);
9426 ndelay(100);
9427
9428 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9429 1))
9430 DRM_ERROR("D_COMP RCOMP still in progress\n");
9431
9432 if (allow_power_down) {
9433 val = I915_READ(LCPLL_CTL);
9434 val |= LCPLL_POWER_DOWN_ALLOW;
9435 I915_WRITE(LCPLL_CTL, val);
9436 POSTING_READ(LCPLL_CTL);
9437 }
9438 }
9439
9440 /*
9441 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9442 * source.
9443 */
9444 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9445 {
9446 uint32_t val;
9447
9448 val = I915_READ(LCPLL_CTL);
9449
9450 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9451 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9452 return;
9453
9454 /*
9455 * Make sure we're not on PC8 state before disabling PC8, otherwise
9456 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9457 */
9458 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9459
9460 if (val & LCPLL_POWER_DOWN_ALLOW) {
9461 val &= ~LCPLL_POWER_DOWN_ALLOW;
9462 I915_WRITE(LCPLL_CTL, val);
9463 POSTING_READ(LCPLL_CTL);
9464 }
9465
9466 val = hsw_read_dcomp(dev_priv);
9467 val |= D_COMP_COMP_FORCE;
9468 val &= ~D_COMP_COMP_DISABLE;
9469 hsw_write_dcomp(dev_priv, val);
9470
9471 val = I915_READ(LCPLL_CTL);
9472 val &= ~LCPLL_PLL_DISABLE;
9473 I915_WRITE(LCPLL_CTL, val);
9474
9475 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9476 DRM_ERROR("LCPLL not locked yet\n");
9477
9478 if (val & LCPLL_CD_SOURCE_FCLK) {
9479 val = I915_READ(LCPLL_CTL);
9480 val &= ~LCPLL_CD_SOURCE_FCLK;
9481 I915_WRITE(LCPLL_CTL, val);
9482
9483 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9484 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9485 DRM_ERROR("Switching back to LCPLL failed\n");
9486 }
9487
9488 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9489 intel_update_cdclk(dev_priv->dev);
9490 }
9491
9492 /*
9493 * Package states C8 and deeper are really deep PC states that can only be
9494 * reached when all the devices on the system allow it, so even if the graphics
9495 * device allows PC8+, it doesn't mean the system will actually get to these
9496 * states. Our driver only allows PC8+ when going into runtime PM.
9497 *
9498 * The requirements for PC8+ are that all the outputs are disabled, the power
9499 * well is disabled and most interrupts are disabled, and these are also
9500 * requirements for runtime PM. When these conditions are met, we manually do
9501 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9502 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9503 * hang the machine.
9504 *
9505 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9506 * the state of some registers, so when we come back from PC8+ we need to
9507 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9508 * need to take care of the registers kept by RC6. Notice that this happens even
9509 * if we don't put the device in PCI D3 state (which is what currently happens
9510 * because of the runtime PM support).
9511 *
9512 * For more, read "Display Sequences for Package C8" on the hardware
9513 * documentation.
9514 */
9515 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9516 {
9517 struct drm_device *dev = dev_priv->dev;
9518 uint32_t val;
9519
9520 DRM_DEBUG_KMS("Enabling package C8+\n");
9521
9522 if (HAS_PCH_LPT_LP(dev)) {
9523 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9524 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9525 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9526 }
9527
9528 lpt_disable_clkout_dp(dev);
9529 hsw_disable_lcpll(dev_priv, true, true);
9530 }
9531
9532 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9533 {
9534 struct drm_device *dev = dev_priv->dev;
9535 uint32_t val;
9536
9537 DRM_DEBUG_KMS("Disabling package C8+\n");
9538
9539 hsw_restore_lcpll(dev_priv);
9540 lpt_init_pch_refclk(dev);
9541
9542 if (HAS_PCH_LPT_LP(dev)) {
9543 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9544 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9545 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9546 }
9547 }
9548
9549 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9550 {
9551 struct drm_device *dev = old_state->dev;
9552 struct intel_atomic_state *old_intel_state =
9553 to_intel_atomic_state(old_state);
9554 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9555
9556 broxton_set_cdclk(to_i915(dev), req_cdclk);
9557 }
9558
9559 /* compute the max rate for new configuration */
9560 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9561 {
9562 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9563 struct drm_i915_private *dev_priv = state->dev->dev_private;
9564 struct drm_crtc *crtc;
9565 struct drm_crtc_state *cstate;
9566 struct intel_crtc_state *crtc_state;
9567 unsigned max_pixel_rate = 0, i;
9568 enum pipe pipe;
9569
9570 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9571 sizeof(intel_state->min_pixclk));
9572
9573 for_each_crtc_in_state(state, crtc, cstate, i) {
9574 int pixel_rate;
9575
9576 crtc_state = to_intel_crtc_state(cstate);
9577 if (!crtc_state->base.enable) {
9578 intel_state->min_pixclk[i] = 0;
9579 continue;
9580 }
9581
9582 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9583
9584 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9585 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9586 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9587
9588 intel_state->min_pixclk[i] = pixel_rate;
9589 }
9590
9591 for_each_pipe(dev_priv, pipe)
9592 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9593
9594 return max_pixel_rate;
9595 }
9596
9597 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9598 {
9599 struct drm_i915_private *dev_priv = dev->dev_private;
9600 uint32_t val, data;
9601 int ret;
9602
9603 if (WARN((I915_READ(LCPLL_CTL) &
9604 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9605 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9606 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9607 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9608 "trying to change cdclk frequency with cdclk not enabled\n"))
9609 return;
9610
9611 mutex_lock(&dev_priv->rps.hw_lock);
9612 ret = sandybridge_pcode_write(dev_priv,
9613 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9614 mutex_unlock(&dev_priv->rps.hw_lock);
9615 if (ret) {
9616 DRM_ERROR("failed to inform pcode about cdclk change\n");
9617 return;
9618 }
9619
9620 val = I915_READ(LCPLL_CTL);
9621 val |= LCPLL_CD_SOURCE_FCLK;
9622 I915_WRITE(LCPLL_CTL, val);
9623
9624 if (wait_for_us(I915_READ(LCPLL_CTL) &
9625 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9626 DRM_ERROR("Switching to FCLK failed\n");
9627
9628 val = I915_READ(LCPLL_CTL);
9629 val &= ~LCPLL_CLK_FREQ_MASK;
9630
9631 switch (cdclk) {
9632 case 450000:
9633 val |= LCPLL_CLK_FREQ_450;
9634 data = 0;
9635 break;
9636 case 540000:
9637 val |= LCPLL_CLK_FREQ_54O_BDW;
9638 data = 1;
9639 break;
9640 case 337500:
9641 val |= LCPLL_CLK_FREQ_337_5_BDW;
9642 data = 2;
9643 break;
9644 case 675000:
9645 val |= LCPLL_CLK_FREQ_675_BDW;
9646 data = 3;
9647 break;
9648 default:
9649 WARN(1, "invalid cdclk frequency\n");
9650 return;
9651 }
9652
9653 I915_WRITE(LCPLL_CTL, val);
9654
9655 val = I915_READ(LCPLL_CTL);
9656 val &= ~LCPLL_CD_SOURCE_FCLK;
9657 I915_WRITE(LCPLL_CTL, val);
9658
9659 if (wait_for_us((I915_READ(LCPLL_CTL) &
9660 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9661 DRM_ERROR("Switching back to LCPLL failed\n");
9662
9663 mutex_lock(&dev_priv->rps.hw_lock);
9664 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9665 mutex_unlock(&dev_priv->rps.hw_lock);
9666
9667 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9668
9669 intel_update_cdclk(dev);
9670
9671 WARN(cdclk != dev_priv->cdclk_freq,
9672 "cdclk requested %d kHz but got %d kHz\n",
9673 cdclk, dev_priv->cdclk_freq);
9674 }
9675
9676 static int broadwell_calc_cdclk(int max_pixclk)
9677 {
9678 if (max_pixclk > 540000)
9679 return 675000;
9680 else if (max_pixclk > 450000)
9681 return 540000;
9682 else if (max_pixclk > 337500)
9683 return 450000;
9684 else
9685 return 337500;
9686 }
9687
9688 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9689 {
9690 struct drm_i915_private *dev_priv = to_i915(state->dev);
9691 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9692 int max_pixclk = ilk_max_pixel_rate(state);
9693 int cdclk;
9694
9695 /*
9696 * FIXME should also account for plane ratio
9697 * once 64bpp pixel formats are supported.
9698 */
9699 cdclk = broadwell_calc_cdclk(max_pixclk);
9700
9701 if (cdclk > dev_priv->max_cdclk_freq) {
9702 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9703 cdclk, dev_priv->max_cdclk_freq);
9704 return -EINVAL;
9705 }
9706
9707 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9708 if (!intel_state->active_crtcs)
9709 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9710
9711 return 0;
9712 }
9713
9714 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9715 {
9716 struct drm_device *dev = old_state->dev;
9717 struct intel_atomic_state *old_intel_state =
9718 to_intel_atomic_state(old_state);
9719 unsigned req_cdclk = old_intel_state->dev_cdclk;
9720
9721 broadwell_set_cdclk(dev, req_cdclk);
9722 }
9723
9724 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9725 struct intel_crtc_state *crtc_state)
9726 {
9727 struct intel_encoder *intel_encoder =
9728 intel_ddi_get_crtc_new_encoder(crtc_state);
9729
9730 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9731 if (!intel_ddi_pll_select(crtc, crtc_state))
9732 return -EINVAL;
9733 }
9734
9735 crtc->lowfreq_avail = false;
9736
9737 return 0;
9738 }
9739
9740 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9741 enum port port,
9742 struct intel_crtc_state *pipe_config)
9743 {
9744 enum intel_dpll_id id;
9745
9746 switch (port) {
9747 case PORT_A:
9748 pipe_config->ddi_pll_sel = SKL_DPLL0;
9749 id = DPLL_ID_SKL_DPLL0;
9750 break;
9751 case PORT_B:
9752 pipe_config->ddi_pll_sel = SKL_DPLL1;
9753 id = DPLL_ID_SKL_DPLL1;
9754 break;
9755 case PORT_C:
9756 pipe_config->ddi_pll_sel = SKL_DPLL2;
9757 id = DPLL_ID_SKL_DPLL2;
9758 break;
9759 default:
9760 DRM_ERROR("Incorrect port type\n");
9761 return;
9762 }
9763
9764 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9765 }
9766
9767 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9768 enum port port,
9769 struct intel_crtc_state *pipe_config)
9770 {
9771 enum intel_dpll_id id;
9772 u32 temp;
9773
9774 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9775 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9776
9777 switch (pipe_config->ddi_pll_sel) {
9778 case SKL_DPLL0:
9779 id = DPLL_ID_SKL_DPLL0;
9780 break;
9781 case SKL_DPLL1:
9782 id = DPLL_ID_SKL_DPLL1;
9783 break;
9784 case SKL_DPLL2:
9785 id = DPLL_ID_SKL_DPLL2;
9786 break;
9787 case SKL_DPLL3:
9788 id = DPLL_ID_SKL_DPLL3;
9789 break;
9790 default:
9791 MISSING_CASE(pipe_config->ddi_pll_sel);
9792 return;
9793 }
9794
9795 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9796 }
9797
9798 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9799 enum port port,
9800 struct intel_crtc_state *pipe_config)
9801 {
9802 enum intel_dpll_id id;
9803
9804 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9805
9806 switch (pipe_config->ddi_pll_sel) {
9807 case PORT_CLK_SEL_WRPLL1:
9808 id = DPLL_ID_WRPLL1;
9809 break;
9810 case PORT_CLK_SEL_WRPLL2:
9811 id = DPLL_ID_WRPLL2;
9812 break;
9813 case PORT_CLK_SEL_SPLL:
9814 id = DPLL_ID_SPLL;
9815 break;
9816 case PORT_CLK_SEL_LCPLL_810:
9817 id = DPLL_ID_LCPLL_810;
9818 break;
9819 case PORT_CLK_SEL_LCPLL_1350:
9820 id = DPLL_ID_LCPLL_1350;
9821 break;
9822 case PORT_CLK_SEL_LCPLL_2700:
9823 id = DPLL_ID_LCPLL_2700;
9824 break;
9825 default:
9826 MISSING_CASE(pipe_config->ddi_pll_sel);
9827 /* fall through */
9828 case PORT_CLK_SEL_NONE:
9829 return;
9830 }
9831
9832 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9833 }
9834
9835 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9836 struct intel_crtc_state *pipe_config,
9837 unsigned long *power_domain_mask)
9838 {
9839 struct drm_device *dev = crtc->base.dev;
9840 struct drm_i915_private *dev_priv = dev->dev_private;
9841 enum intel_display_power_domain power_domain;
9842 u32 tmp;
9843
9844 /*
9845 * The pipe->transcoder mapping is fixed with the exception of the eDP
9846 * transcoder handled below.
9847 */
9848 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9849
9850 /*
9851 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9852 * consistency and less surprising code; it's in always on power).
9853 */
9854 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9855 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9856 enum pipe trans_edp_pipe;
9857 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9858 default:
9859 WARN(1, "unknown pipe linked to edp transcoder\n");
9860 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9861 case TRANS_DDI_EDP_INPUT_A_ON:
9862 trans_edp_pipe = PIPE_A;
9863 break;
9864 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9865 trans_edp_pipe = PIPE_B;
9866 break;
9867 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9868 trans_edp_pipe = PIPE_C;
9869 break;
9870 }
9871
9872 if (trans_edp_pipe == crtc->pipe)
9873 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9874 }
9875
9876 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9877 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9878 return false;
9879 *power_domain_mask |= BIT(power_domain);
9880
9881 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9882
9883 return tmp & PIPECONF_ENABLE;
9884 }
9885
9886 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9887 struct intel_crtc_state *pipe_config,
9888 unsigned long *power_domain_mask)
9889 {
9890 struct drm_device *dev = crtc->base.dev;
9891 struct drm_i915_private *dev_priv = dev->dev_private;
9892 enum intel_display_power_domain power_domain;
9893 enum port port;
9894 enum transcoder cpu_transcoder;
9895 u32 tmp;
9896
9897 pipe_config->has_dsi_encoder = false;
9898
9899 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9900 if (port == PORT_A)
9901 cpu_transcoder = TRANSCODER_DSI_A;
9902 else
9903 cpu_transcoder = TRANSCODER_DSI_C;
9904
9905 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9906 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9907 continue;
9908 *power_domain_mask |= BIT(power_domain);
9909
9910 /*
9911 * The PLL needs to be enabled with a valid divider
9912 * configuration, otherwise accessing DSI registers will hang
9913 * the machine. See BSpec North Display Engine
9914 * registers/MIPI[BXT]. We can break out here early, since we
9915 * need the same DSI PLL to be enabled for both DSI ports.
9916 */
9917 if (!intel_dsi_pll_is_enabled(dev_priv))
9918 break;
9919
9920 /* XXX: this works for video mode only */
9921 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9922 if (!(tmp & DPI_ENABLE))
9923 continue;
9924
9925 tmp = I915_READ(MIPI_CTRL(port));
9926 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9927 continue;
9928
9929 pipe_config->cpu_transcoder = cpu_transcoder;
9930 pipe_config->has_dsi_encoder = true;
9931 break;
9932 }
9933
9934 return pipe_config->has_dsi_encoder;
9935 }
9936
9937 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9938 struct intel_crtc_state *pipe_config)
9939 {
9940 struct drm_device *dev = crtc->base.dev;
9941 struct drm_i915_private *dev_priv = dev->dev_private;
9942 struct intel_shared_dpll *pll;
9943 enum port port;
9944 uint32_t tmp;
9945
9946 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9947
9948 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9949
9950 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9951 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9952 else if (IS_BROXTON(dev))
9953 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9954 else
9955 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9956
9957 pll = pipe_config->shared_dpll;
9958 if (pll) {
9959 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9960 &pipe_config->dpll_hw_state));
9961 }
9962
9963 /*
9964 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9965 * DDI E. So just check whether this pipe is wired to DDI E and whether
9966 * the PCH transcoder is on.
9967 */
9968 if (INTEL_INFO(dev)->gen < 9 &&
9969 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9970 pipe_config->has_pch_encoder = true;
9971
9972 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9973 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9974 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9975
9976 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9977 }
9978 }
9979
9980 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9981 struct intel_crtc_state *pipe_config)
9982 {
9983 struct drm_device *dev = crtc->base.dev;
9984 struct drm_i915_private *dev_priv = dev->dev_private;
9985 enum intel_display_power_domain power_domain;
9986 unsigned long power_domain_mask;
9987 bool active;
9988
9989 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9990 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9991 return false;
9992 power_domain_mask = BIT(power_domain);
9993
9994 pipe_config->shared_dpll = NULL;
9995
9996 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9997
9998 if (IS_BROXTON(dev_priv)) {
9999 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10000 &power_domain_mask);
10001 WARN_ON(active && pipe_config->has_dsi_encoder);
10002 if (pipe_config->has_dsi_encoder)
10003 active = true;
10004 }
10005
10006 if (!active)
10007 goto out;
10008
10009 if (!pipe_config->has_dsi_encoder) {
10010 haswell_get_ddi_port_state(crtc, pipe_config);
10011 intel_get_pipe_timings(crtc, pipe_config);
10012 }
10013
10014 intel_get_pipe_src_size(crtc, pipe_config);
10015
10016 pipe_config->gamma_mode =
10017 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10018
10019 if (INTEL_INFO(dev)->gen >= 9) {
10020 skl_init_scalers(dev, crtc, pipe_config);
10021 }
10022
10023 if (INTEL_INFO(dev)->gen >= 9) {
10024 pipe_config->scaler_state.scaler_id = -1;
10025 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10026 }
10027
10028 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10029 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10030 power_domain_mask |= BIT(power_domain);
10031 if (INTEL_INFO(dev)->gen >= 9)
10032 skylake_get_pfit_config(crtc, pipe_config);
10033 else
10034 ironlake_get_pfit_config(crtc, pipe_config);
10035 }
10036
10037 if (IS_HASWELL(dev))
10038 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10039 (I915_READ(IPS_CTL) & IPS_ENABLE);
10040
10041 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10042 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10043 pipe_config->pixel_multiplier =
10044 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10045 } else {
10046 pipe_config->pixel_multiplier = 1;
10047 }
10048
10049 out:
10050 for_each_power_domain(power_domain, power_domain_mask)
10051 intel_display_power_put(dev_priv, power_domain);
10052
10053 return active;
10054 }
10055
10056 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10057 const struct intel_plane_state *plane_state)
10058 {
10059 struct drm_device *dev = crtc->dev;
10060 struct drm_i915_private *dev_priv = dev->dev_private;
10061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10062 uint32_t cntl = 0, size = 0;
10063
10064 if (plane_state && plane_state->visible) {
10065 unsigned int width = plane_state->base.crtc_w;
10066 unsigned int height = plane_state->base.crtc_h;
10067 unsigned int stride = roundup_pow_of_two(width) * 4;
10068
10069 switch (stride) {
10070 default:
10071 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10072 width, stride);
10073 stride = 256;
10074 /* fallthrough */
10075 case 256:
10076 case 512:
10077 case 1024:
10078 case 2048:
10079 break;
10080 }
10081
10082 cntl |= CURSOR_ENABLE |
10083 CURSOR_GAMMA_ENABLE |
10084 CURSOR_FORMAT_ARGB |
10085 CURSOR_STRIDE(stride);
10086
10087 size = (height << 12) | width;
10088 }
10089
10090 if (intel_crtc->cursor_cntl != 0 &&
10091 (intel_crtc->cursor_base != base ||
10092 intel_crtc->cursor_size != size ||
10093 intel_crtc->cursor_cntl != cntl)) {
10094 /* On these chipsets we can only modify the base/size/stride
10095 * whilst the cursor is disabled.
10096 */
10097 I915_WRITE(CURCNTR(PIPE_A), 0);
10098 POSTING_READ(CURCNTR(PIPE_A));
10099 intel_crtc->cursor_cntl = 0;
10100 }
10101
10102 if (intel_crtc->cursor_base != base) {
10103 I915_WRITE(CURBASE(PIPE_A), base);
10104 intel_crtc->cursor_base = base;
10105 }
10106
10107 if (intel_crtc->cursor_size != size) {
10108 I915_WRITE(CURSIZE, size);
10109 intel_crtc->cursor_size = size;
10110 }
10111
10112 if (intel_crtc->cursor_cntl != cntl) {
10113 I915_WRITE(CURCNTR(PIPE_A), cntl);
10114 POSTING_READ(CURCNTR(PIPE_A));
10115 intel_crtc->cursor_cntl = cntl;
10116 }
10117 }
10118
10119 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10120 const struct intel_plane_state *plane_state)
10121 {
10122 struct drm_device *dev = crtc->dev;
10123 struct drm_i915_private *dev_priv = dev->dev_private;
10124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10125 int pipe = intel_crtc->pipe;
10126 uint32_t cntl = 0;
10127
10128 if (plane_state && plane_state->visible) {
10129 cntl = MCURSOR_GAMMA_ENABLE;
10130 switch (plane_state->base.crtc_w) {
10131 case 64:
10132 cntl |= CURSOR_MODE_64_ARGB_AX;
10133 break;
10134 case 128:
10135 cntl |= CURSOR_MODE_128_ARGB_AX;
10136 break;
10137 case 256:
10138 cntl |= CURSOR_MODE_256_ARGB_AX;
10139 break;
10140 default:
10141 MISSING_CASE(plane_state->base.crtc_w);
10142 return;
10143 }
10144 cntl |= pipe << 28; /* Connect to correct pipe */
10145
10146 if (HAS_DDI(dev))
10147 cntl |= CURSOR_PIPE_CSC_ENABLE;
10148
10149 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10150 cntl |= CURSOR_ROTATE_180;
10151 }
10152
10153 if (intel_crtc->cursor_cntl != cntl) {
10154 I915_WRITE(CURCNTR(pipe), cntl);
10155 POSTING_READ(CURCNTR(pipe));
10156 intel_crtc->cursor_cntl = cntl;
10157 }
10158
10159 /* and commit changes on next vblank */
10160 I915_WRITE(CURBASE(pipe), base);
10161 POSTING_READ(CURBASE(pipe));
10162
10163 intel_crtc->cursor_base = base;
10164 }
10165
10166 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10167 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10168 const struct intel_plane_state *plane_state)
10169 {
10170 struct drm_device *dev = crtc->dev;
10171 struct drm_i915_private *dev_priv = dev->dev_private;
10172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10173 int pipe = intel_crtc->pipe;
10174 u32 base = intel_crtc->cursor_addr;
10175 u32 pos = 0;
10176
10177 if (plane_state) {
10178 int x = plane_state->base.crtc_x;
10179 int y = plane_state->base.crtc_y;
10180
10181 if (x < 0) {
10182 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10183 x = -x;
10184 }
10185 pos |= x << CURSOR_X_SHIFT;
10186
10187 if (y < 0) {
10188 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10189 y = -y;
10190 }
10191 pos |= y << CURSOR_Y_SHIFT;
10192
10193 /* ILK+ do this automagically */
10194 if (HAS_GMCH_DISPLAY(dev) &&
10195 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10196 base += (plane_state->base.crtc_h *
10197 plane_state->base.crtc_w - 1) * 4;
10198 }
10199 }
10200
10201 I915_WRITE(CURPOS(pipe), pos);
10202
10203 if (IS_845G(dev) || IS_I865G(dev))
10204 i845_update_cursor(crtc, base, plane_state);
10205 else
10206 i9xx_update_cursor(crtc, base, plane_state);
10207 }
10208
10209 static bool cursor_size_ok(struct drm_device *dev,
10210 uint32_t width, uint32_t height)
10211 {
10212 if (width == 0 || height == 0)
10213 return false;
10214
10215 /*
10216 * 845g/865g are special in that they are only limited by
10217 * the width of their cursors, the height is arbitrary up to
10218 * the precision of the register. Everything else requires
10219 * square cursors, limited to a few power-of-two sizes.
10220 */
10221 if (IS_845G(dev) || IS_I865G(dev)) {
10222 if ((width & 63) != 0)
10223 return false;
10224
10225 if (width > (IS_845G(dev) ? 64 : 512))
10226 return false;
10227
10228 if (height > 1023)
10229 return false;
10230 } else {
10231 switch (width | height) {
10232 case 256:
10233 case 128:
10234 if (IS_GEN2(dev))
10235 return false;
10236 case 64:
10237 break;
10238 default:
10239 return false;
10240 }
10241 }
10242
10243 return true;
10244 }
10245
10246 /* VESA 640x480x72Hz mode to set on the pipe */
10247 static struct drm_display_mode load_detect_mode = {
10248 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10249 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10250 };
10251
10252 struct drm_framebuffer *
10253 __intel_framebuffer_create(struct drm_device *dev,
10254 struct drm_mode_fb_cmd2 *mode_cmd,
10255 struct drm_i915_gem_object *obj)
10256 {
10257 struct intel_framebuffer *intel_fb;
10258 int ret;
10259
10260 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10261 if (!intel_fb)
10262 return ERR_PTR(-ENOMEM);
10263
10264 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10265 if (ret)
10266 goto err;
10267
10268 return &intel_fb->base;
10269
10270 err:
10271 kfree(intel_fb);
10272 return ERR_PTR(ret);
10273 }
10274
10275 static struct drm_framebuffer *
10276 intel_framebuffer_create(struct drm_device *dev,
10277 struct drm_mode_fb_cmd2 *mode_cmd,
10278 struct drm_i915_gem_object *obj)
10279 {
10280 struct drm_framebuffer *fb;
10281 int ret;
10282
10283 ret = i915_mutex_lock_interruptible(dev);
10284 if (ret)
10285 return ERR_PTR(ret);
10286 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10287 mutex_unlock(&dev->struct_mutex);
10288
10289 return fb;
10290 }
10291
10292 static u32
10293 intel_framebuffer_pitch_for_width(int width, int bpp)
10294 {
10295 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10296 return ALIGN(pitch, 64);
10297 }
10298
10299 static u32
10300 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10301 {
10302 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10303 return PAGE_ALIGN(pitch * mode->vdisplay);
10304 }
10305
10306 static struct drm_framebuffer *
10307 intel_framebuffer_create_for_mode(struct drm_device *dev,
10308 struct drm_display_mode *mode,
10309 int depth, int bpp)
10310 {
10311 struct drm_framebuffer *fb;
10312 struct drm_i915_gem_object *obj;
10313 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10314
10315 obj = i915_gem_object_create(dev,
10316 intel_framebuffer_size_for_mode(mode, bpp));
10317 if (IS_ERR(obj))
10318 return ERR_CAST(obj);
10319
10320 mode_cmd.width = mode->hdisplay;
10321 mode_cmd.height = mode->vdisplay;
10322 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10323 bpp);
10324 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10325
10326 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10327 if (IS_ERR(fb))
10328 drm_gem_object_unreference_unlocked(&obj->base);
10329
10330 return fb;
10331 }
10332
10333 static struct drm_framebuffer *
10334 mode_fits_in_fbdev(struct drm_device *dev,
10335 struct drm_display_mode *mode)
10336 {
10337 #ifdef CONFIG_DRM_FBDEV_EMULATION
10338 struct drm_i915_private *dev_priv = dev->dev_private;
10339 struct drm_i915_gem_object *obj;
10340 struct drm_framebuffer *fb;
10341
10342 if (!dev_priv->fbdev)
10343 return NULL;
10344
10345 if (!dev_priv->fbdev->fb)
10346 return NULL;
10347
10348 obj = dev_priv->fbdev->fb->obj;
10349 BUG_ON(!obj);
10350
10351 fb = &dev_priv->fbdev->fb->base;
10352 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10353 fb->bits_per_pixel))
10354 return NULL;
10355
10356 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10357 return NULL;
10358
10359 drm_framebuffer_reference(fb);
10360 return fb;
10361 #else
10362 return NULL;
10363 #endif
10364 }
10365
10366 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10367 struct drm_crtc *crtc,
10368 struct drm_display_mode *mode,
10369 struct drm_framebuffer *fb,
10370 int x, int y)
10371 {
10372 struct drm_plane_state *plane_state;
10373 int hdisplay, vdisplay;
10374 int ret;
10375
10376 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10377 if (IS_ERR(plane_state))
10378 return PTR_ERR(plane_state);
10379
10380 if (mode)
10381 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10382 else
10383 hdisplay = vdisplay = 0;
10384
10385 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10386 if (ret)
10387 return ret;
10388 drm_atomic_set_fb_for_plane(plane_state, fb);
10389 plane_state->crtc_x = 0;
10390 plane_state->crtc_y = 0;
10391 plane_state->crtc_w = hdisplay;
10392 plane_state->crtc_h = vdisplay;
10393 plane_state->src_x = x << 16;
10394 plane_state->src_y = y << 16;
10395 plane_state->src_w = hdisplay << 16;
10396 plane_state->src_h = vdisplay << 16;
10397
10398 return 0;
10399 }
10400
10401 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10402 struct drm_display_mode *mode,
10403 struct intel_load_detect_pipe *old,
10404 struct drm_modeset_acquire_ctx *ctx)
10405 {
10406 struct intel_crtc *intel_crtc;
10407 struct intel_encoder *intel_encoder =
10408 intel_attached_encoder(connector);
10409 struct drm_crtc *possible_crtc;
10410 struct drm_encoder *encoder = &intel_encoder->base;
10411 struct drm_crtc *crtc = NULL;
10412 struct drm_device *dev = encoder->dev;
10413 struct drm_framebuffer *fb;
10414 struct drm_mode_config *config = &dev->mode_config;
10415 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10416 struct drm_connector_state *connector_state;
10417 struct intel_crtc_state *crtc_state;
10418 int ret, i = -1;
10419
10420 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10421 connector->base.id, connector->name,
10422 encoder->base.id, encoder->name);
10423
10424 old->restore_state = NULL;
10425
10426 retry:
10427 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10428 if (ret)
10429 goto fail;
10430
10431 /*
10432 * Algorithm gets a little messy:
10433 *
10434 * - if the connector already has an assigned crtc, use it (but make
10435 * sure it's on first)
10436 *
10437 * - try to find the first unused crtc that can drive this connector,
10438 * and use that if we find one
10439 */
10440
10441 /* See if we already have a CRTC for this connector */
10442 if (connector->state->crtc) {
10443 crtc = connector->state->crtc;
10444
10445 ret = drm_modeset_lock(&crtc->mutex, ctx);
10446 if (ret)
10447 goto fail;
10448
10449 /* Make sure the crtc and connector are running */
10450 goto found;
10451 }
10452
10453 /* Find an unused one (if possible) */
10454 for_each_crtc(dev, possible_crtc) {
10455 i++;
10456 if (!(encoder->possible_crtcs & (1 << i)))
10457 continue;
10458
10459 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10460 if (ret)
10461 goto fail;
10462
10463 if (possible_crtc->state->enable) {
10464 drm_modeset_unlock(&possible_crtc->mutex);
10465 continue;
10466 }
10467
10468 crtc = possible_crtc;
10469 break;
10470 }
10471
10472 /*
10473 * If we didn't find an unused CRTC, don't use any.
10474 */
10475 if (!crtc) {
10476 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10477 goto fail;
10478 }
10479
10480 found:
10481 intel_crtc = to_intel_crtc(crtc);
10482
10483 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10484 if (ret)
10485 goto fail;
10486
10487 state = drm_atomic_state_alloc(dev);
10488 restore_state = drm_atomic_state_alloc(dev);
10489 if (!state || !restore_state) {
10490 ret = -ENOMEM;
10491 goto fail;
10492 }
10493
10494 state->acquire_ctx = ctx;
10495 restore_state->acquire_ctx = ctx;
10496
10497 connector_state = drm_atomic_get_connector_state(state, connector);
10498 if (IS_ERR(connector_state)) {
10499 ret = PTR_ERR(connector_state);
10500 goto fail;
10501 }
10502
10503 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10504 if (ret)
10505 goto fail;
10506
10507 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10508 if (IS_ERR(crtc_state)) {
10509 ret = PTR_ERR(crtc_state);
10510 goto fail;
10511 }
10512
10513 crtc_state->base.active = crtc_state->base.enable = true;
10514
10515 if (!mode)
10516 mode = &load_detect_mode;
10517
10518 /* We need a framebuffer large enough to accommodate all accesses
10519 * that the plane may generate whilst we perform load detection.
10520 * We can not rely on the fbcon either being present (we get called
10521 * during its initialisation to detect all boot displays, or it may
10522 * not even exist) or that it is large enough to satisfy the
10523 * requested mode.
10524 */
10525 fb = mode_fits_in_fbdev(dev, mode);
10526 if (fb == NULL) {
10527 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10528 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10529 } else
10530 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10531 if (IS_ERR(fb)) {
10532 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10533 goto fail;
10534 }
10535
10536 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10537 if (ret)
10538 goto fail;
10539
10540 drm_framebuffer_unreference(fb);
10541
10542 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10543 if (ret)
10544 goto fail;
10545
10546 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10547 if (!ret)
10548 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10549 if (!ret)
10550 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10551 if (ret) {
10552 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10553 goto fail;
10554 }
10555
10556 ret = drm_atomic_commit(state);
10557 if (ret) {
10558 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10559 goto fail;
10560 }
10561
10562 old->restore_state = restore_state;
10563
10564 /* let the connector get through one full cycle before testing */
10565 intel_wait_for_vblank(dev, intel_crtc->pipe);
10566 return true;
10567
10568 fail:
10569 drm_atomic_state_free(state);
10570 drm_atomic_state_free(restore_state);
10571 restore_state = state = NULL;
10572
10573 if (ret == -EDEADLK) {
10574 drm_modeset_backoff(ctx);
10575 goto retry;
10576 }
10577
10578 return false;
10579 }
10580
10581 void intel_release_load_detect_pipe(struct drm_connector *connector,
10582 struct intel_load_detect_pipe *old,
10583 struct drm_modeset_acquire_ctx *ctx)
10584 {
10585 struct intel_encoder *intel_encoder =
10586 intel_attached_encoder(connector);
10587 struct drm_encoder *encoder = &intel_encoder->base;
10588 struct drm_atomic_state *state = old->restore_state;
10589 int ret;
10590
10591 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10592 connector->base.id, connector->name,
10593 encoder->base.id, encoder->name);
10594
10595 if (!state)
10596 return;
10597
10598 ret = drm_atomic_commit(state);
10599 if (ret) {
10600 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10601 drm_atomic_state_free(state);
10602 }
10603 }
10604
10605 static int i9xx_pll_refclk(struct drm_device *dev,
10606 const struct intel_crtc_state *pipe_config)
10607 {
10608 struct drm_i915_private *dev_priv = dev->dev_private;
10609 u32 dpll = pipe_config->dpll_hw_state.dpll;
10610
10611 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10612 return dev_priv->vbt.lvds_ssc_freq;
10613 else if (HAS_PCH_SPLIT(dev))
10614 return 120000;
10615 else if (!IS_GEN2(dev))
10616 return 96000;
10617 else
10618 return 48000;
10619 }
10620
10621 /* Returns the clock of the currently programmed mode of the given pipe. */
10622 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10623 struct intel_crtc_state *pipe_config)
10624 {
10625 struct drm_device *dev = crtc->base.dev;
10626 struct drm_i915_private *dev_priv = dev->dev_private;
10627 int pipe = pipe_config->cpu_transcoder;
10628 u32 dpll = pipe_config->dpll_hw_state.dpll;
10629 u32 fp;
10630 struct dpll clock;
10631 int port_clock;
10632 int refclk = i9xx_pll_refclk(dev, pipe_config);
10633
10634 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10635 fp = pipe_config->dpll_hw_state.fp0;
10636 else
10637 fp = pipe_config->dpll_hw_state.fp1;
10638
10639 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10640 if (IS_PINEVIEW(dev)) {
10641 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10642 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10643 } else {
10644 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10645 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10646 }
10647
10648 if (!IS_GEN2(dev)) {
10649 if (IS_PINEVIEW(dev))
10650 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10651 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10652 else
10653 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10654 DPLL_FPA01_P1_POST_DIV_SHIFT);
10655
10656 switch (dpll & DPLL_MODE_MASK) {
10657 case DPLLB_MODE_DAC_SERIAL:
10658 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10659 5 : 10;
10660 break;
10661 case DPLLB_MODE_LVDS:
10662 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10663 7 : 14;
10664 break;
10665 default:
10666 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10667 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10668 return;
10669 }
10670
10671 if (IS_PINEVIEW(dev))
10672 port_clock = pnv_calc_dpll_params(refclk, &clock);
10673 else
10674 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10675 } else {
10676 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10677 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10678
10679 if (is_lvds) {
10680 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10681 DPLL_FPA01_P1_POST_DIV_SHIFT);
10682
10683 if (lvds & LVDS_CLKB_POWER_UP)
10684 clock.p2 = 7;
10685 else
10686 clock.p2 = 14;
10687 } else {
10688 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10689 clock.p1 = 2;
10690 else {
10691 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10692 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10693 }
10694 if (dpll & PLL_P2_DIVIDE_BY_4)
10695 clock.p2 = 4;
10696 else
10697 clock.p2 = 2;
10698 }
10699
10700 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10701 }
10702
10703 /*
10704 * This value includes pixel_multiplier. We will use
10705 * port_clock to compute adjusted_mode.crtc_clock in the
10706 * encoder's get_config() function.
10707 */
10708 pipe_config->port_clock = port_clock;
10709 }
10710
10711 int intel_dotclock_calculate(int link_freq,
10712 const struct intel_link_m_n *m_n)
10713 {
10714 /*
10715 * The calculation for the data clock is:
10716 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10717 * But we want to avoid losing precison if possible, so:
10718 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10719 *
10720 * and the link clock is simpler:
10721 * link_clock = (m * link_clock) / n
10722 */
10723
10724 if (!m_n->link_n)
10725 return 0;
10726
10727 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10728 }
10729
10730 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10731 struct intel_crtc_state *pipe_config)
10732 {
10733 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10734
10735 /* read out port_clock from the DPLL */
10736 i9xx_crtc_clock_get(crtc, pipe_config);
10737
10738 /*
10739 * In case there is an active pipe without active ports,
10740 * we may need some idea for the dotclock anyway.
10741 * Calculate one based on the FDI configuration.
10742 */
10743 pipe_config->base.adjusted_mode.crtc_clock =
10744 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10745 &pipe_config->fdi_m_n);
10746 }
10747
10748 /** Returns the currently programmed mode of the given pipe. */
10749 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10750 struct drm_crtc *crtc)
10751 {
10752 struct drm_i915_private *dev_priv = dev->dev_private;
10753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10754 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10755 struct drm_display_mode *mode;
10756 struct intel_crtc_state *pipe_config;
10757 int htot = I915_READ(HTOTAL(cpu_transcoder));
10758 int hsync = I915_READ(HSYNC(cpu_transcoder));
10759 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10760 int vsync = I915_READ(VSYNC(cpu_transcoder));
10761 enum pipe pipe = intel_crtc->pipe;
10762
10763 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10764 if (!mode)
10765 return NULL;
10766
10767 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10768 if (!pipe_config) {
10769 kfree(mode);
10770 return NULL;
10771 }
10772
10773 /*
10774 * Construct a pipe_config sufficient for getting the clock info
10775 * back out of crtc_clock_get.
10776 *
10777 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10778 * to use a real value here instead.
10779 */
10780 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10781 pipe_config->pixel_multiplier = 1;
10782 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10783 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10784 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10785 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10786
10787 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10788 mode->hdisplay = (htot & 0xffff) + 1;
10789 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10790 mode->hsync_start = (hsync & 0xffff) + 1;
10791 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10792 mode->vdisplay = (vtot & 0xffff) + 1;
10793 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10794 mode->vsync_start = (vsync & 0xffff) + 1;
10795 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10796
10797 drm_mode_set_name(mode);
10798
10799 kfree(pipe_config);
10800
10801 return mode;
10802 }
10803
10804 void intel_mark_busy(struct drm_i915_private *dev_priv)
10805 {
10806 if (dev_priv->mm.busy)
10807 return;
10808
10809 intel_runtime_pm_get(dev_priv);
10810 i915_update_gfx_val(dev_priv);
10811 if (INTEL_GEN(dev_priv) >= 6)
10812 gen6_rps_busy(dev_priv);
10813 dev_priv->mm.busy = true;
10814 }
10815
10816 void intel_mark_idle(struct drm_i915_private *dev_priv)
10817 {
10818 if (!dev_priv->mm.busy)
10819 return;
10820
10821 dev_priv->mm.busy = false;
10822
10823 if (INTEL_GEN(dev_priv) >= 6)
10824 gen6_rps_idle(dev_priv);
10825
10826 intel_runtime_pm_put(dev_priv);
10827 }
10828
10829 static void intel_crtc_destroy(struct drm_crtc *crtc)
10830 {
10831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10832 struct drm_device *dev = crtc->dev;
10833 struct intel_unpin_work *work;
10834
10835 spin_lock_irq(&dev->event_lock);
10836 work = intel_crtc->unpin_work;
10837 intel_crtc->unpin_work = NULL;
10838 spin_unlock_irq(&dev->event_lock);
10839
10840 if (work) {
10841 cancel_work_sync(&work->work);
10842 kfree(work);
10843 }
10844
10845 drm_crtc_cleanup(crtc);
10846
10847 kfree(intel_crtc);
10848 }
10849
10850 static void intel_unpin_work_fn(struct work_struct *__work)
10851 {
10852 struct intel_unpin_work *work =
10853 container_of(__work, struct intel_unpin_work, work);
10854 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10855 struct drm_device *dev = crtc->base.dev;
10856 struct drm_plane *primary = crtc->base.primary;
10857
10858 mutex_lock(&dev->struct_mutex);
10859 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10860 drm_gem_object_unreference(&work->pending_flip_obj->base);
10861
10862 if (work->flip_queued_req)
10863 i915_gem_request_assign(&work->flip_queued_req, NULL);
10864 mutex_unlock(&dev->struct_mutex);
10865
10866 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10867 intel_fbc_post_update(crtc);
10868 drm_framebuffer_unreference(work->old_fb);
10869
10870 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10871 atomic_dec(&crtc->unpin_work_count);
10872
10873 kfree(work);
10874 }
10875
10876 static void do_intel_finish_page_flip(struct drm_i915_private *dev_priv,
10877 struct drm_crtc *crtc)
10878 {
10879 struct drm_device *dev = dev_priv->dev;
10880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10881 struct intel_unpin_work *work;
10882 unsigned long flags;
10883
10884 /* Ignore early vblank irqs */
10885 if (intel_crtc == NULL)
10886 return;
10887
10888 /*
10889 * This is called both by irq handlers and the reset code (to complete
10890 * lost pageflips) so needs the full irqsave spinlocks.
10891 */
10892 spin_lock_irqsave(&dev->event_lock, flags);
10893 work = intel_crtc->unpin_work;
10894
10895 /* Ensure we don't miss a work->pending update ... */
10896 smp_rmb();
10897
10898 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10899 spin_unlock_irqrestore(&dev->event_lock, flags);
10900 return;
10901 }
10902
10903 page_flip_completed(intel_crtc);
10904
10905 spin_unlock_irqrestore(&dev->event_lock, flags);
10906 }
10907
10908 void intel_finish_page_flip(struct drm_i915_private *dev_priv, int pipe)
10909 {
10910 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10911
10912 do_intel_finish_page_flip(dev_priv, crtc);
10913 }
10914
10915 void intel_finish_page_flip_plane(struct drm_i915_private *dev_priv, int plane)
10916 {
10917 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10918
10919 do_intel_finish_page_flip(dev_priv, crtc);
10920 }
10921
10922 /* Is 'a' after or equal to 'b'? */
10923 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10924 {
10925 return !((a - b) & 0x80000000);
10926 }
10927
10928 static bool page_flip_finished(struct intel_crtc *crtc)
10929 {
10930 struct drm_device *dev = crtc->base.dev;
10931 struct drm_i915_private *dev_priv = dev->dev_private;
10932 unsigned reset_counter;
10933
10934 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
10935 if (crtc->reset_counter != reset_counter)
10936 return true;
10937
10938 /*
10939 * The relevant registers doen't exist on pre-ctg.
10940 * As the flip done interrupt doesn't trigger for mmio
10941 * flips on gmch platforms, a flip count check isn't
10942 * really needed there. But since ctg has the registers,
10943 * include it in the check anyway.
10944 */
10945 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10946 return true;
10947
10948 /*
10949 * BDW signals flip done immediately if the plane
10950 * is disabled, even if the plane enable is already
10951 * armed to occur at the next vblank :(
10952 */
10953
10954 /*
10955 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10956 * used the same base address. In that case the mmio flip might
10957 * have completed, but the CS hasn't even executed the flip yet.
10958 *
10959 * A flip count check isn't enough as the CS might have updated
10960 * the base address just after start of vblank, but before we
10961 * managed to process the interrupt. This means we'd complete the
10962 * CS flip too soon.
10963 *
10964 * Combining both checks should get us a good enough result. It may
10965 * still happen that the CS flip has been executed, but has not
10966 * yet actually completed. But in case the base address is the same
10967 * anyway, we don't really care.
10968 */
10969 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10970 crtc->unpin_work->gtt_offset &&
10971 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10972 crtc->unpin_work->flip_count);
10973 }
10974
10975 void intel_prepare_page_flip(struct drm_i915_private *dev_priv, int plane)
10976 {
10977 struct drm_device *dev = dev_priv->dev;
10978 struct intel_crtc *intel_crtc =
10979 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10980 unsigned long flags;
10981
10982
10983 /*
10984 * This is called both by irq handlers and the reset code (to complete
10985 * lost pageflips) so needs the full irqsave spinlocks.
10986 *
10987 * NB: An MMIO update of the plane base pointer will also
10988 * generate a page-flip completion irq, i.e. every modeset
10989 * is also accompanied by a spurious intel_prepare_page_flip().
10990 */
10991 spin_lock_irqsave(&dev->event_lock, flags);
10992 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10993 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10994 spin_unlock_irqrestore(&dev->event_lock, flags);
10995 }
10996
10997 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10998 {
10999 /* Ensure that the work item is consistent when activating it ... */
11000 smp_wmb();
11001 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11002 /* and that it is marked active as soon as the irq could fire. */
11003 smp_wmb();
11004 }
11005
11006 static int intel_gen2_queue_flip(struct drm_device *dev,
11007 struct drm_crtc *crtc,
11008 struct drm_framebuffer *fb,
11009 struct drm_i915_gem_object *obj,
11010 struct drm_i915_gem_request *req,
11011 uint32_t flags)
11012 {
11013 struct intel_engine_cs *engine = req->engine;
11014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11015 u32 flip_mask;
11016 int ret;
11017
11018 ret = intel_ring_begin(req, 6);
11019 if (ret)
11020 return ret;
11021
11022 /* Can't queue multiple flips, so wait for the previous
11023 * one to finish before executing the next.
11024 */
11025 if (intel_crtc->plane)
11026 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11027 else
11028 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11029 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11030 intel_ring_emit(engine, MI_NOOP);
11031 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11032 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11033 intel_ring_emit(engine, fb->pitches[0]);
11034 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11035 intel_ring_emit(engine, 0); /* aux display base address, unused */
11036
11037 intel_mark_page_flip_active(intel_crtc->unpin_work);
11038 return 0;
11039 }
11040
11041 static int intel_gen3_queue_flip(struct drm_device *dev,
11042 struct drm_crtc *crtc,
11043 struct drm_framebuffer *fb,
11044 struct drm_i915_gem_object *obj,
11045 struct drm_i915_gem_request *req,
11046 uint32_t flags)
11047 {
11048 struct intel_engine_cs *engine = req->engine;
11049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11050 u32 flip_mask;
11051 int ret;
11052
11053 ret = intel_ring_begin(req, 6);
11054 if (ret)
11055 return ret;
11056
11057 if (intel_crtc->plane)
11058 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11059 else
11060 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11061 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11062 intel_ring_emit(engine, MI_NOOP);
11063 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11064 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11065 intel_ring_emit(engine, fb->pitches[0]);
11066 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11067 intel_ring_emit(engine, MI_NOOP);
11068
11069 intel_mark_page_flip_active(intel_crtc->unpin_work);
11070 return 0;
11071 }
11072
11073 static int intel_gen4_queue_flip(struct drm_device *dev,
11074 struct drm_crtc *crtc,
11075 struct drm_framebuffer *fb,
11076 struct drm_i915_gem_object *obj,
11077 struct drm_i915_gem_request *req,
11078 uint32_t flags)
11079 {
11080 struct intel_engine_cs *engine = req->engine;
11081 struct drm_i915_private *dev_priv = dev->dev_private;
11082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11083 uint32_t pf, pipesrc;
11084 int ret;
11085
11086 ret = intel_ring_begin(req, 4);
11087 if (ret)
11088 return ret;
11089
11090 /* i965+ uses the linear or tiled offsets from the
11091 * Display Registers (which do not change across a page-flip)
11092 * so we need only reprogram the base address.
11093 */
11094 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11095 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11096 intel_ring_emit(engine, fb->pitches[0]);
11097 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11098 obj->tiling_mode);
11099
11100 /* XXX Enabling the panel-fitter across page-flip is so far
11101 * untested on non-native modes, so ignore it for now.
11102 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11103 */
11104 pf = 0;
11105 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11106 intel_ring_emit(engine, pf | pipesrc);
11107
11108 intel_mark_page_flip_active(intel_crtc->unpin_work);
11109 return 0;
11110 }
11111
11112 static int intel_gen6_queue_flip(struct drm_device *dev,
11113 struct drm_crtc *crtc,
11114 struct drm_framebuffer *fb,
11115 struct drm_i915_gem_object *obj,
11116 struct drm_i915_gem_request *req,
11117 uint32_t flags)
11118 {
11119 struct intel_engine_cs *engine = req->engine;
11120 struct drm_i915_private *dev_priv = dev->dev_private;
11121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11122 uint32_t pf, pipesrc;
11123 int ret;
11124
11125 ret = intel_ring_begin(req, 4);
11126 if (ret)
11127 return ret;
11128
11129 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11130 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11131 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11132 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11133
11134 /* Contrary to the suggestions in the documentation,
11135 * "Enable Panel Fitter" does not seem to be required when page
11136 * flipping with a non-native mode, and worse causes a normal
11137 * modeset to fail.
11138 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11139 */
11140 pf = 0;
11141 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11142 intel_ring_emit(engine, pf | pipesrc);
11143
11144 intel_mark_page_flip_active(intel_crtc->unpin_work);
11145 return 0;
11146 }
11147
11148 static int intel_gen7_queue_flip(struct drm_device *dev,
11149 struct drm_crtc *crtc,
11150 struct drm_framebuffer *fb,
11151 struct drm_i915_gem_object *obj,
11152 struct drm_i915_gem_request *req,
11153 uint32_t flags)
11154 {
11155 struct intel_engine_cs *engine = req->engine;
11156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11157 uint32_t plane_bit = 0;
11158 int len, ret;
11159
11160 switch (intel_crtc->plane) {
11161 case PLANE_A:
11162 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11163 break;
11164 case PLANE_B:
11165 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11166 break;
11167 case PLANE_C:
11168 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11169 break;
11170 default:
11171 WARN_ONCE(1, "unknown plane in flip command\n");
11172 return -ENODEV;
11173 }
11174
11175 len = 4;
11176 if (engine->id == RCS) {
11177 len += 6;
11178 /*
11179 * On Gen 8, SRM is now taking an extra dword to accommodate
11180 * 48bits addresses, and we need a NOOP for the batch size to
11181 * stay even.
11182 */
11183 if (IS_GEN8(dev))
11184 len += 2;
11185 }
11186
11187 /*
11188 * BSpec MI_DISPLAY_FLIP for IVB:
11189 * "The full packet must be contained within the same cache line."
11190 *
11191 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11192 * cacheline, if we ever start emitting more commands before
11193 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11194 * then do the cacheline alignment, and finally emit the
11195 * MI_DISPLAY_FLIP.
11196 */
11197 ret = intel_ring_cacheline_align(req);
11198 if (ret)
11199 return ret;
11200
11201 ret = intel_ring_begin(req, len);
11202 if (ret)
11203 return ret;
11204
11205 /* Unmask the flip-done completion message. Note that the bspec says that
11206 * we should do this for both the BCS and RCS, and that we must not unmask
11207 * more than one flip event at any time (or ensure that one flip message
11208 * can be sent by waiting for flip-done prior to queueing new flips).
11209 * Experimentation says that BCS works despite DERRMR masking all
11210 * flip-done completion events and that unmasking all planes at once
11211 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11212 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11213 */
11214 if (engine->id == RCS) {
11215 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11216 intel_ring_emit_reg(engine, DERRMR);
11217 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11218 DERRMR_PIPEB_PRI_FLIP_DONE |
11219 DERRMR_PIPEC_PRI_FLIP_DONE));
11220 if (IS_GEN8(dev))
11221 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11222 MI_SRM_LRM_GLOBAL_GTT);
11223 else
11224 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11225 MI_SRM_LRM_GLOBAL_GTT);
11226 intel_ring_emit_reg(engine, DERRMR);
11227 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11228 if (IS_GEN8(dev)) {
11229 intel_ring_emit(engine, 0);
11230 intel_ring_emit(engine, MI_NOOP);
11231 }
11232 }
11233
11234 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11235 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11236 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11237 intel_ring_emit(engine, (MI_NOOP));
11238
11239 intel_mark_page_flip_active(intel_crtc->unpin_work);
11240 return 0;
11241 }
11242
11243 static bool use_mmio_flip(struct intel_engine_cs *engine,
11244 struct drm_i915_gem_object *obj)
11245 {
11246 /*
11247 * This is not being used for older platforms, because
11248 * non-availability of flip done interrupt forces us to use
11249 * CS flips. Older platforms derive flip done using some clever
11250 * tricks involving the flip_pending status bits and vblank irqs.
11251 * So using MMIO flips there would disrupt this mechanism.
11252 */
11253
11254 if (engine == NULL)
11255 return true;
11256
11257 if (INTEL_GEN(engine->i915) < 5)
11258 return false;
11259
11260 if (i915.use_mmio_flip < 0)
11261 return false;
11262 else if (i915.use_mmio_flip > 0)
11263 return true;
11264 else if (i915.enable_execlists)
11265 return true;
11266 else if (obj->base.dma_buf &&
11267 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11268 false))
11269 return true;
11270 else
11271 return engine != i915_gem_request_get_engine(obj->last_write_req);
11272 }
11273
11274 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11275 unsigned int rotation,
11276 struct intel_unpin_work *work)
11277 {
11278 struct drm_device *dev = intel_crtc->base.dev;
11279 struct drm_i915_private *dev_priv = dev->dev_private;
11280 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11281 const enum pipe pipe = intel_crtc->pipe;
11282 u32 ctl, stride, tile_height;
11283
11284 ctl = I915_READ(PLANE_CTL(pipe, 0));
11285 ctl &= ~PLANE_CTL_TILED_MASK;
11286 switch (fb->modifier[0]) {
11287 case DRM_FORMAT_MOD_NONE:
11288 break;
11289 case I915_FORMAT_MOD_X_TILED:
11290 ctl |= PLANE_CTL_TILED_X;
11291 break;
11292 case I915_FORMAT_MOD_Y_TILED:
11293 ctl |= PLANE_CTL_TILED_Y;
11294 break;
11295 case I915_FORMAT_MOD_Yf_TILED:
11296 ctl |= PLANE_CTL_TILED_YF;
11297 break;
11298 default:
11299 MISSING_CASE(fb->modifier[0]);
11300 }
11301
11302 /*
11303 * The stride is either expressed as a multiple of 64 bytes chunks for
11304 * linear buffers or in number of tiles for tiled buffers.
11305 */
11306 if (intel_rotation_90_or_270(rotation)) {
11307 /* stride = Surface height in tiles */
11308 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11309 stride = DIV_ROUND_UP(fb->height, tile_height);
11310 } else {
11311 stride = fb->pitches[0] /
11312 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11313 fb->pixel_format);
11314 }
11315
11316 /*
11317 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11318 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11319 */
11320 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11321 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11322
11323 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11324 POSTING_READ(PLANE_SURF(pipe, 0));
11325 }
11326
11327 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11328 struct intel_unpin_work *work)
11329 {
11330 struct drm_device *dev = intel_crtc->base.dev;
11331 struct drm_i915_private *dev_priv = dev->dev_private;
11332 struct intel_framebuffer *intel_fb =
11333 to_intel_framebuffer(intel_crtc->base.primary->fb);
11334 struct drm_i915_gem_object *obj = intel_fb->obj;
11335 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11336 u32 dspcntr;
11337
11338 dspcntr = I915_READ(reg);
11339
11340 if (obj->tiling_mode != I915_TILING_NONE)
11341 dspcntr |= DISPPLANE_TILED;
11342 else
11343 dspcntr &= ~DISPPLANE_TILED;
11344
11345 I915_WRITE(reg, dspcntr);
11346
11347 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11348 POSTING_READ(DSPSURF(intel_crtc->plane));
11349 }
11350
11351 /*
11352 * XXX: This is the temporary way to update the plane registers until we get
11353 * around to using the usual plane update functions for MMIO flips
11354 */
11355 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11356 {
11357 struct intel_crtc *crtc = mmio_flip->crtc;
11358 struct intel_unpin_work *work;
11359
11360 spin_lock_irq(&crtc->base.dev->event_lock);
11361 work = crtc->unpin_work;
11362 spin_unlock_irq(&crtc->base.dev->event_lock);
11363 if (work == NULL)
11364 return;
11365
11366 intel_mark_page_flip_active(work);
11367
11368 intel_pipe_update_start(crtc);
11369
11370 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11371 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11372 else
11373 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11374 ilk_do_mmio_flip(crtc, work);
11375
11376 intel_pipe_update_end(crtc);
11377 }
11378
11379 static void intel_mmio_flip_work_func(struct work_struct *work)
11380 {
11381 struct intel_mmio_flip *mmio_flip =
11382 container_of(work, struct intel_mmio_flip, work);
11383 struct intel_framebuffer *intel_fb =
11384 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11385 struct drm_i915_gem_object *obj = intel_fb->obj;
11386
11387 if (mmio_flip->req) {
11388 WARN_ON(__i915_wait_request(mmio_flip->req,
11389 false, NULL,
11390 &mmio_flip->i915->rps.mmioflips));
11391 i915_gem_request_unreference(mmio_flip->req);
11392 }
11393
11394 /* For framebuffer backed by dmabuf, wait for fence */
11395 if (obj->base.dma_buf)
11396 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11397 false, false,
11398 MAX_SCHEDULE_TIMEOUT) < 0);
11399
11400 intel_do_mmio_flip(mmio_flip);
11401 kfree(mmio_flip);
11402 }
11403
11404 static int intel_queue_mmio_flip(struct drm_device *dev,
11405 struct drm_crtc *crtc,
11406 struct drm_i915_gem_object *obj)
11407 {
11408 struct intel_mmio_flip *mmio_flip;
11409
11410 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11411 if (mmio_flip == NULL)
11412 return -ENOMEM;
11413
11414 mmio_flip->i915 = to_i915(dev);
11415 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11416 mmio_flip->crtc = to_intel_crtc(crtc);
11417 mmio_flip->rotation = crtc->primary->state->rotation;
11418
11419 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11420 schedule_work(&mmio_flip->work);
11421
11422 return 0;
11423 }
11424
11425 static int intel_default_queue_flip(struct drm_device *dev,
11426 struct drm_crtc *crtc,
11427 struct drm_framebuffer *fb,
11428 struct drm_i915_gem_object *obj,
11429 struct drm_i915_gem_request *req,
11430 uint32_t flags)
11431 {
11432 return -ENODEV;
11433 }
11434
11435 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11436 struct drm_crtc *crtc)
11437 {
11438 struct drm_i915_private *dev_priv = dev->dev_private;
11439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11440 struct intel_unpin_work *work = intel_crtc->unpin_work;
11441 u32 addr;
11442
11443 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11444 return true;
11445
11446 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11447 return false;
11448
11449 if (!work->enable_stall_check)
11450 return false;
11451
11452 if (work->flip_ready_vblank == 0) {
11453 if (work->flip_queued_req &&
11454 !i915_gem_request_completed(work->flip_queued_req, true))
11455 return false;
11456
11457 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11458 }
11459
11460 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11461 return false;
11462
11463 /* Potential stall - if we see that the flip has happened,
11464 * assume a missed interrupt. */
11465 if (INTEL_INFO(dev)->gen >= 4)
11466 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11467 else
11468 addr = I915_READ(DSPADDR(intel_crtc->plane));
11469
11470 /* There is a potential issue here with a false positive after a flip
11471 * to the same address. We could address this by checking for a
11472 * non-incrementing frame counter.
11473 */
11474 return addr == work->gtt_offset;
11475 }
11476
11477 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11478 {
11479 struct drm_device *dev = dev_priv->dev;
11480 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11482 struct intel_unpin_work *work;
11483
11484 WARN_ON(!in_interrupt());
11485
11486 if (crtc == NULL)
11487 return;
11488
11489 spin_lock(&dev->event_lock);
11490 work = intel_crtc->unpin_work;
11491 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11492 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11493 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11494 page_flip_completed(intel_crtc);
11495 work = NULL;
11496 }
11497 if (work != NULL &&
11498 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11499 intel_queue_rps_boost_for_request(work->flip_queued_req);
11500 spin_unlock(&dev->event_lock);
11501 }
11502
11503 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11504 struct drm_framebuffer *fb,
11505 struct drm_pending_vblank_event *event,
11506 uint32_t page_flip_flags)
11507 {
11508 struct drm_device *dev = crtc->dev;
11509 struct drm_i915_private *dev_priv = dev->dev_private;
11510 struct drm_framebuffer *old_fb = crtc->primary->fb;
11511 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11513 struct drm_plane *primary = crtc->primary;
11514 enum pipe pipe = intel_crtc->pipe;
11515 struct intel_unpin_work *work;
11516 struct intel_engine_cs *engine;
11517 bool mmio_flip;
11518 struct drm_i915_gem_request *request = NULL;
11519 int ret;
11520
11521 /*
11522 * drm_mode_page_flip_ioctl() should already catch this, but double
11523 * check to be safe. In the future we may enable pageflipping from
11524 * a disabled primary plane.
11525 */
11526 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11527 return -EBUSY;
11528
11529 /* Can't change pixel format via MI display flips. */
11530 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11531 return -EINVAL;
11532
11533 /*
11534 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11535 * Note that pitch changes could also affect these register.
11536 */
11537 if (INTEL_INFO(dev)->gen > 3 &&
11538 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11539 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11540 return -EINVAL;
11541
11542 if (i915_terminally_wedged(&dev_priv->gpu_error))
11543 goto out_hang;
11544
11545 work = kzalloc(sizeof(*work), GFP_KERNEL);
11546 if (work == NULL)
11547 return -ENOMEM;
11548
11549 work->event = event;
11550 work->crtc = crtc;
11551 work->old_fb = old_fb;
11552 INIT_WORK(&work->work, intel_unpin_work_fn);
11553
11554 ret = drm_crtc_vblank_get(crtc);
11555 if (ret)
11556 goto free_work;
11557
11558 /* We borrow the event spin lock for protecting unpin_work */
11559 spin_lock_irq(&dev->event_lock);
11560 if (intel_crtc->unpin_work) {
11561 /* Before declaring the flip queue wedged, check if
11562 * the hardware completed the operation behind our backs.
11563 */
11564 if (__intel_pageflip_stall_check(dev, crtc)) {
11565 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11566 page_flip_completed(intel_crtc);
11567 } else {
11568 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11569 spin_unlock_irq(&dev->event_lock);
11570
11571 drm_crtc_vblank_put(crtc);
11572 kfree(work);
11573 return -EBUSY;
11574 }
11575 }
11576 intel_crtc->unpin_work = work;
11577 spin_unlock_irq(&dev->event_lock);
11578
11579 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11580 flush_workqueue(dev_priv->wq);
11581
11582 /* Reference the objects for the scheduled work. */
11583 drm_framebuffer_reference(work->old_fb);
11584 drm_gem_object_reference(&obj->base);
11585
11586 crtc->primary->fb = fb;
11587 update_state_fb(crtc->primary);
11588 intel_fbc_pre_update(intel_crtc);
11589
11590 work->pending_flip_obj = obj;
11591
11592 ret = i915_mutex_lock_interruptible(dev);
11593 if (ret)
11594 goto cleanup;
11595
11596 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11597 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11598 ret = -EIO;
11599 goto cleanup;
11600 }
11601
11602 atomic_inc(&intel_crtc->unpin_work_count);
11603
11604 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11605 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11606
11607 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11608 engine = &dev_priv->engine[BCS];
11609 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11610 /* vlv: DISPLAY_FLIP fails to change tiling */
11611 engine = NULL;
11612 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11613 engine = &dev_priv->engine[BCS];
11614 } else if (INTEL_INFO(dev)->gen >= 7) {
11615 engine = i915_gem_request_get_engine(obj->last_write_req);
11616 if (engine == NULL || engine->id != RCS)
11617 engine = &dev_priv->engine[BCS];
11618 } else {
11619 engine = &dev_priv->engine[RCS];
11620 }
11621
11622 mmio_flip = use_mmio_flip(engine, obj);
11623
11624 /* When using CS flips, we want to emit semaphores between rings.
11625 * However, when using mmio flips we will create a task to do the
11626 * synchronisation, so all we want here is to pin the framebuffer
11627 * into the display plane and skip any waits.
11628 */
11629 if (!mmio_flip) {
11630 ret = i915_gem_object_sync(obj, engine, &request);
11631 if (ret)
11632 goto cleanup_pending;
11633 }
11634
11635 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11636 if (ret)
11637 goto cleanup_pending;
11638
11639 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11640 obj, 0);
11641 work->gtt_offset += intel_crtc->dspaddr_offset;
11642
11643 if (mmio_flip) {
11644 ret = intel_queue_mmio_flip(dev, crtc, obj);
11645 if (ret)
11646 goto cleanup_unpin;
11647
11648 i915_gem_request_assign(&work->flip_queued_req,
11649 obj->last_write_req);
11650 } else {
11651 if (!request) {
11652 request = i915_gem_request_alloc(engine, NULL);
11653 if (IS_ERR(request)) {
11654 ret = PTR_ERR(request);
11655 goto cleanup_unpin;
11656 }
11657 }
11658
11659 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11660 page_flip_flags);
11661 if (ret)
11662 goto cleanup_unpin;
11663
11664 i915_gem_request_assign(&work->flip_queued_req, request);
11665 }
11666
11667 if (request)
11668 i915_add_request_no_flush(request);
11669
11670 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11671 work->enable_stall_check = true;
11672
11673 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11674 to_intel_plane(primary)->frontbuffer_bit);
11675 mutex_unlock(&dev->struct_mutex);
11676
11677 intel_frontbuffer_flip_prepare(dev,
11678 to_intel_plane(primary)->frontbuffer_bit);
11679
11680 trace_i915_flip_request(intel_crtc->plane, obj);
11681
11682 return 0;
11683
11684 cleanup_unpin:
11685 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11686 cleanup_pending:
11687 if (!IS_ERR_OR_NULL(request))
11688 i915_add_request_no_flush(request);
11689 atomic_dec(&intel_crtc->unpin_work_count);
11690 mutex_unlock(&dev->struct_mutex);
11691 cleanup:
11692 crtc->primary->fb = old_fb;
11693 update_state_fb(crtc->primary);
11694
11695 drm_gem_object_unreference_unlocked(&obj->base);
11696 drm_framebuffer_unreference(work->old_fb);
11697
11698 spin_lock_irq(&dev->event_lock);
11699 intel_crtc->unpin_work = NULL;
11700 spin_unlock_irq(&dev->event_lock);
11701
11702 drm_crtc_vblank_put(crtc);
11703 free_work:
11704 kfree(work);
11705
11706 if (ret == -EIO) {
11707 struct drm_atomic_state *state;
11708 struct drm_plane_state *plane_state;
11709
11710 out_hang:
11711 state = drm_atomic_state_alloc(dev);
11712 if (!state)
11713 return -ENOMEM;
11714 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11715
11716 retry:
11717 plane_state = drm_atomic_get_plane_state(state, primary);
11718 ret = PTR_ERR_OR_ZERO(plane_state);
11719 if (!ret) {
11720 drm_atomic_set_fb_for_plane(plane_state, fb);
11721
11722 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11723 if (!ret)
11724 ret = drm_atomic_commit(state);
11725 }
11726
11727 if (ret == -EDEADLK) {
11728 drm_modeset_backoff(state->acquire_ctx);
11729 drm_atomic_state_clear(state);
11730 goto retry;
11731 }
11732
11733 if (ret)
11734 drm_atomic_state_free(state);
11735
11736 if (ret == 0 && event) {
11737 spin_lock_irq(&dev->event_lock);
11738 drm_crtc_send_vblank_event(crtc, event);
11739 spin_unlock_irq(&dev->event_lock);
11740 }
11741 }
11742 return ret;
11743 }
11744
11745
11746 /**
11747 * intel_wm_need_update - Check whether watermarks need updating
11748 * @plane: drm plane
11749 * @state: new plane state
11750 *
11751 * Check current plane state versus the new one to determine whether
11752 * watermarks need to be recalculated.
11753 *
11754 * Returns true or false.
11755 */
11756 static bool intel_wm_need_update(struct drm_plane *plane,
11757 struct drm_plane_state *state)
11758 {
11759 struct intel_plane_state *new = to_intel_plane_state(state);
11760 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11761
11762 /* Update watermarks on tiling or size changes. */
11763 if (new->visible != cur->visible)
11764 return true;
11765
11766 if (!cur->base.fb || !new->base.fb)
11767 return false;
11768
11769 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11770 cur->base.rotation != new->base.rotation ||
11771 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11772 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11773 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11774 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11775 return true;
11776
11777 return false;
11778 }
11779
11780 static bool needs_scaling(struct intel_plane_state *state)
11781 {
11782 int src_w = drm_rect_width(&state->src) >> 16;
11783 int src_h = drm_rect_height(&state->src) >> 16;
11784 int dst_w = drm_rect_width(&state->dst);
11785 int dst_h = drm_rect_height(&state->dst);
11786
11787 return (src_w != dst_w || src_h != dst_h);
11788 }
11789
11790 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11791 struct drm_plane_state *plane_state)
11792 {
11793 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11794 struct drm_crtc *crtc = crtc_state->crtc;
11795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11796 struct drm_plane *plane = plane_state->plane;
11797 struct drm_device *dev = crtc->dev;
11798 struct drm_i915_private *dev_priv = to_i915(dev);
11799 struct intel_plane_state *old_plane_state =
11800 to_intel_plane_state(plane->state);
11801 int idx = intel_crtc->base.base.id, ret;
11802 bool mode_changed = needs_modeset(crtc_state);
11803 bool was_crtc_enabled = crtc->state->active;
11804 bool is_crtc_enabled = crtc_state->active;
11805 bool turn_off, turn_on, visible, was_visible;
11806 struct drm_framebuffer *fb = plane_state->fb;
11807
11808 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11809 plane->type != DRM_PLANE_TYPE_CURSOR) {
11810 ret = skl_update_scaler_plane(
11811 to_intel_crtc_state(crtc_state),
11812 to_intel_plane_state(plane_state));
11813 if (ret)
11814 return ret;
11815 }
11816
11817 was_visible = old_plane_state->visible;
11818 visible = to_intel_plane_state(plane_state)->visible;
11819
11820 if (!was_crtc_enabled && WARN_ON(was_visible))
11821 was_visible = false;
11822
11823 /*
11824 * Visibility is calculated as if the crtc was on, but
11825 * after scaler setup everything depends on it being off
11826 * when the crtc isn't active.
11827 *
11828 * FIXME this is wrong for watermarks. Watermarks should also
11829 * be computed as if the pipe would be active. Perhaps move
11830 * per-plane wm computation to the .check_plane() hook, and
11831 * only combine the results from all planes in the current place?
11832 */
11833 if (!is_crtc_enabled)
11834 to_intel_plane_state(plane_state)->visible = visible = false;
11835
11836 if (!was_visible && !visible)
11837 return 0;
11838
11839 if (fb != old_plane_state->base.fb)
11840 pipe_config->fb_changed = true;
11841
11842 turn_off = was_visible && (!visible || mode_changed);
11843 turn_on = visible && (!was_visible || mode_changed);
11844
11845 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11846 plane->base.id, fb ? fb->base.id : -1);
11847
11848 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11849 plane->base.id, was_visible, visible,
11850 turn_off, turn_on, mode_changed);
11851
11852 if (turn_on) {
11853 pipe_config->update_wm_pre = true;
11854
11855 /* must disable cxsr around plane enable/disable */
11856 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11857 pipe_config->disable_cxsr = true;
11858 } else if (turn_off) {
11859 pipe_config->update_wm_post = true;
11860
11861 /* must disable cxsr around plane enable/disable */
11862 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11863 pipe_config->disable_cxsr = true;
11864 } else if (intel_wm_need_update(plane, plane_state)) {
11865 /* FIXME bollocks */
11866 pipe_config->update_wm_pre = true;
11867 pipe_config->update_wm_post = true;
11868 }
11869
11870 /* Pre-gen9 platforms need two-step watermark updates */
11871 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11872 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11873 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11874
11875 if (visible || was_visible)
11876 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11877
11878 /*
11879 * WaCxSRDisabledForSpriteScaling:ivb
11880 *
11881 * cstate->update_wm was already set above, so this flag will
11882 * take effect when we commit and program watermarks.
11883 */
11884 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11885 needs_scaling(to_intel_plane_state(plane_state)) &&
11886 !needs_scaling(old_plane_state))
11887 pipe_config->disable_lp_wm = true;
11888
11889 return 0;
11890 }
11891
11892 static bool encoders_cloneable(const struct intel_encoder *a,
11893 const struct intel_encoder *b)
11894 {
11895 /* masks could be asymmetric, so check both ways */
11896 return a == b || (a->cloneable & (1 << b->type) &&
11897 b->cloneable & (1 << a->type));
11898 }
11899
11900 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11901 struct intel_crtc *crtc,
11902 struct intel_encoder *encoder)
11903 {
11904 struct intel_encoder *source_encoder;
11905 struct drm_connector *connector;
11906 struct drm_connector_state *connector_state;
11907 int i;
11908
11909 for_each_connector_in_state(state, connector, connector_state, i) {
11910 if (connector_state->crtc != &crtc->base)
11911 continue;
11912
11913 source_encoder =
11914 to_intel_encoder(connector_state->best_encoder);
11915 if (!encoders_cloneable(encoder, source_encoder))
11916 return false;
11917 }
11918
11919 return true;
11920 }
11921
11922 static bool check_encoder_cloning(struct drm_atomic_state *state,
11923 struct intel_crtc *crtc)
11924 {
11925 struct intel_encoder *encoder;
11926 struct drm_connector *connector;
11927 struct drm_connector_state *connector_state;
11928 int i;
11929
11930 for_each_connector_in_state(state, connector, connector_state, i) {
11931 if (connector_state->crtc != &crtc->base)
11932 continue;
11933
11934 encoder = to_intel_encoder(connector_state->best_encoder);
11935 if (!check_single_encoder_cloning(state, crtc, encoder))
11936 return false;
11937 }
11938
11939 return true;
11940 }
11941
11942 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11943 struct drm_crtc_state *crtc_state)
11944 {
11945 struct drm_device *dev = crtc->dev;
11946 struct drm_i915_private *dev_priv = dev->dev_private;
11947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11948 struct intel_crtc_state *pipe_config =
11949 to_intel_crtc_state(crtc_state);
11950 struct drm_atomic_state *state = crtc_state->state;
11951 int ret;
11952 bool mode_changed = needs_modeset(crtc_state);
11953
11954 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11955 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11956 return -EINVAL;
11957 }
11958
11959 if (mode_changed && !crtc_state->active)
11960 pipe_config->update_wm_post = true;
11961
11962 if (mode_changed && crtc_state->enable &&
11963 dev_priv->display.crtc_compute_clock &&
11964 !WARN_ON(pipe_config->shared_dpll)) {
11965 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11966 pipe_config);
11967 if (ret)
11968 return ret;
11969 }
11970
11971 if (crtc_state->color_mgmt_changed) {
11972 ret = intel_color_check(crtc, crtc_state);
11973 if (ret)
11974 return ret;
11975 }
11976
11977 ret = 0;
11978 if (dev_priv->display.compute_pipe_wm) {
11979 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11980 if (ret) {
11981 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11982 return ret;
11983 }
11984 }
11985
11986 if (dev_priv->display.compute_intermediate_wm &&
11987 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11988 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11989 return 0;
11990
11991 /*
11992 * Calculate 'intermediate' watermarks that satisfy both the
11993 * old state and the new state. We can program these
11994 * immediately.
11995 */
11996 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11997 intel_crtc,
11998 pipe_config);
11999 if (ret) {
12000 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12001 return ret;
12002 }
12003 }
12004
12005 if (INTEL_INFO(dev)->gen >= 9) {
12006 if (mode_changed)
12007 ret = skl_update_scaler_crtc(pipe_config);
12008
12009 if (!ret)
12010 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12011 pipe_config);
12012 }
12013
12014 return ret;
12015 }
12016
12017 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12018 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12019 .atomic_begin = intel_begin_crtc_commit,
12020 .atomic_flush = intel_finish_crtc_commit,
12021 .atomic_check = intel_crtc_atomic_check,
12022 };
12023
12024 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12025 {
12026 struct intel_connector *connector;
12027
12028 for_each_intel_connector(dev, connector) {
12029 if (connector->base.encoder) {
12030 connector->base.state->best_encoder =
12031 connector->base.encoder;
12032 connector->base.state->crtc =
12033 connector->base.encoder->crtc;
12034 } else {
12035 connector->base.state->best_encoder = NULL;
12036 connector->base.state->crtc = NULL;
12037 }
12038 }
12039 }
12040
12041 static void
12042 connected_sink_compute_bpp(struct intel_connector *connector,
12043 struct intel_crtc_state *pipe_config)
12044 {
12045 int bpp = pipe_config->pipe_bpp;
12046
12047 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12048 connector->base.base.id,
12049 connector->base.name);
12050
12051 /* Don't use an invalid EDID bpc value */
12052 if (connector->base.display_info.bpc &&
12053 connector->base.display_info.bpc * 3 < bpp) {
12054 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12055 bpp, connector->base.display_info.bpc*3);
12056 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12057 }
12058
12059 /* Clamp bpp to default limit on screens without EDID 1.4 */
12060 if (connector->base.display_info.bpc == 0) {
12061 int type = connector->base.connector_type;
12062 int clamp_bpp = 24;
12063
12064 /* Fall back to 18 bpp when DP sink capability is unknown. */
12065 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12066 type == DRM_MODE_CONNECTOR_eDP)
12067 clamp_bpp = 18;
12068
12069 if (bpp > clamp_bpp) {
12070 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12071 bpp, clamp_bpp);
12072 pipe_config->pipe_bpp = clamp_bpp;
12073 }
12074 }
12075 }
12076
12077 static int
12078 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12079 struct intel_crtc_state *pipe_config)
12080 {
12081 struct drm_device *dev = crtc->base.dev;
12082 struct drm_atomic_state *state;
12083 struct drm_connector *connector;
12084 struct drm_connector_state *connector_state;
12085 int bpp, i;
12086
12087 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12088 bpp = 10*3;
12089 else if (INTEL_INFO(dev)->gen >= 5)
12090 bpp = 12*3;
12091 else
12092 bpp = 8*3;
12093
12094
12095 pipe_config->pipe_bpp = bpp;
12096
12097 state = pipe_config->base.state;
12098
12099 /* Clamp display bpp to EDID value */
12100 for_each_connector_in_state(state, connector, connector_state, i) {
12101 if (connector_state->crtc != &crtc->base)
12102 continue;
12103
12104 connected_sink_compute_bpp(to_intel_connector(connector),
12105 pipe_config);
12106 }
12107
12108 return bpp;
12109 }
12110
12111 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12112 {
12113 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12114 "type: 0x%x flags: 0x%x\n",
12115 mode->crtc_clock,
12116 mode->crtc_hdisplay, mode->crtc_hsync_start,
12117 mode->crtc_hsync_end, mode->crtc_htotal,
12118 mode->crtc_vdisplay, mode->crtc_vsync_start,
12119 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12120 }
12121
12122 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12123 struct intel_crtc_state *pipe_config,
12124 const char *context)
12125 {
12126 struct drm_device *dev = crtc->base.dev;
12127 struct drm_plane *plane;
12128 struct intel_plane *intel_plane;
12129 struct intel_plane_state *state;
12130 struct drm_framebuffer *fb;
12131
12132 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12133 context, pipe_config, pipe_name(crtc->pipe));
12134
12135 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12136 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12137 pipe_config->pipe_bpp, pipe_config->dither);
12138 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12139 pipe_config->has_pch_encoder,
12140 pipe_config->fdi_lanes,
12141 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12142 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12143 pipe_config->fdi_m_n.tu);
12144 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12145 pipe_config->has_dp_encoder,
12146 pipe_config->lane_count,
12147 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12148 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12149 pipe_config->dp_m_n.tu);
12150
12151 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12152 pipe_config->has_dp_encoder,
12153 pipe_config->lane_count,
12154 pipe_config->dp_m2_n2.gmch_m,
12155 pipe_config->dp_m2_n2.gmch_n,
12156 pipe_config->dp_m2_n2.link_m,
12157 pipe_config->dp_m2_n2.link_n,
12158 pipe_config->dp_m2_n2.tu);
12159
12160 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12161 pipe_config->has_audio,
12162 pipe_config->has_infoframe);
12163
12164 DRM_DEBUG_KMS("requested mode:\n");
12165 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12166 DRM_DEBUG_KMS("adjusted mode:\n");
12167 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12168 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12169 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12170 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12171 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12172 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12173 crtc->num_scalers,
12174 pipe_config->scaler_state.scaler_users,
12175 pipe_config->scaler_state.scaler_id);
12176 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12177 pipe_config->gmch_pfit.control,
12178 pipe_config->gmch_pfit.pgm_ratios,
12179 pipe_config->gmch_pfit.lvds_border_bits);
12180 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12181 pipe_config->pch_pfit.pos,
12182 pipe_config->pch_pfit.size,
12183 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12184 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12185 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12186
12187 if (IS_BROXTON(dev)) {
12188 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12189 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12190 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12191 pipe_config->ddi_pll_sel,
12192 pipe_config->dpll_hw_state.ebb0,
12193 pipe_config->dpll_hw_state.ebb4,
12194 pipe_config->dpll_hw_state.pll0,
12195 pipe_config->dpll_hw_state.pll1,
12196 pipe_config->dpll_hw_state.pll2,
12197 pipe_config->dpll_hw_state.pll3,
12198 pipe_config->dpll_hw_state.pll6,
12199 pipe_config->dpll_hw_state.pll8,
12200 pipe_config->dpll_hw_state.pll9,
12201 pipe_config->dpll_hw_state.pll10,
12202 pipe_config->dpll_hw_state.pcsdw12);
12203 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12204 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12205 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12206 pipe_config->ddi_pll_sel,
12207 pipe_config->dpll_hw_state.ctrl1,
12208 pipe_config->dpll_hw_state.cfgcr1,
12209 pipe_config->dpll_hw_state.cfgcr2);
12210 } else if (HAS_DDI(dev)) {
12211 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12212 pipe_config->ddi_pll_sel,
12213 pipe_config->dpll_hw_state.wrpll,
12214 pipe_config->dpll_hw_state.spll);
12215 } else {
12216 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12217 "fp0: 0x%x, fp1: 0x%x\n",
12218 pipe_config->dpll_hw_state.dpll,
12219 pipe_config->dpll_hw_state.dpll_md,
12220 pipe_config->dpll_hw_state.fp0,
12221 pipe_config->dpll_hw_state.fp1);
12222 }
12223
12224 DRM_DEBUG_KMS("planes on this crtc\n");
12225 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12226 intel_plane = to_intel_plane(plane);
12227 if (intel_plane->pipe != crtc->pipe)
12228 continue;
12229
12230 state = to_intel_plane_state(plane->state);
12231 fb = state->base.fb;
12232 if (!fb) {
12233 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12234 "disabled, scaler_id = %d\n",
12235 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12236 plane->base.id, intel_plane->pipe,
12237 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12238 drm_plane_index(plane), state->scaler_id);
12239 continue;
12240 }
12241
12242 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12243 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12244 plane->base.id, intel_plane->pipe,
12245 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12246 drm_plane_index(plane));
12247 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12248 fb->base.id, fb->width, fb->height, fb->pixel_format);
12249 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12250 state->scaler_id,
12251 state->src.x1 >> 16, state->src.y1 >> 16,
12252 drm_rect_width(&state->src) >> 16,
12253 drm_rect_height(&state->src) >> 16,
12254 state->dst.x1, state->dst.y1,
12255 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12256 }
12257 }
12258
12259 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12260 {
12261 struct drm_device *dev = state->dev;
12262 struct drm_connector *connector;
12263 unsigned int used_ports = 0;
12264
12265 /*
12266 * Walk the connector list instead of the encoder
12267 * list to detect the problem on ddi platforms
12268 * where there's just one encoder per digital port.
12269 */
12270 drm_for_each_connector(connector, dev) {
12271 struct drm_connector_state *connector_state;
12272 struct intel_encoder *encoder;
12273
12274 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12275 if (!connector_state)
12276 connector_state = connector->state;
12277
12278 if (!connector_state->best_encoder)
12279 continue;
12280
12281 encoder = to_intel_encoder(connector_state->best_encoder);
12282
12283 WARN_ON(!connector_state->crtc);
12284
12285 switch (encoder->type) {
12286 unsigned int port_mask;
12287 case INTEL_OUTPUT_UNKNOWN:
12288 if (WARN_ON(!HAS_DDI(dev)))
12289 break;
12290 case INTEL_OUTPUT_DISPLAYPORT:
12291 case INTEL_OUTPUT_HDMI:
12292 case INTEL_OUTPUT_EDP:
12293 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12294
12295 /* the same port mustn't appear more than once */
12296 if (used_ports & port_mask)
12297 return false;
12298
12299 used_ports |= port_mask;
12300 default:
12301 break;
12302 }
12303 }
12304
12305 return true;
12306 }
12307
12308 static void
12309 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12310 {
12311 struct drm_crtc_state tmp_state;
12312 struct intel_crtc_scaler_state scaler_state;
12313 struct intel_dpll_hw_state dpll_hw_state;
12314 struct intel_shared_dpll *shared_dpll;
12315 uint32_t ddi_pll_sel;
12316 bool force_thru;
12317
12318 /* FIXME: before the switch to atomic started, a new pipe_config was
12319 * kzalloc'd. Code that depends on any field being zero should be
12320 * fixed, so that the crtc_state can be safely duplicated. For now,
12321 * only fields that are know to not cause problems are preserved. */
12322
12323 tmp_state = crtc_state->base;
12324 scaler_state = crtc_state->scaler_state;
12325 shared_dpll = crtc_state->shared_dpll;
12326 dpll_hw_state = crtc_state->dpll_hw_state;
12327 ddi_pll_sel = crtc_state->ddi_pll_sel;
12328 force_thru = crtc_state->pch_pfit.force_thru;
12329
12330 memset(crtc_state, 0, sizeof *crtc_state);
12331
12332 crtc_state->base = tmp_state;
12333 crtc_state->scaler_state = scaler_state;
12334 crtc_state->shared_dpll = shared_dpll;
12335 crtc_state->dpll_hw_state = dpll_hw_state;
12336 crtc_state->ddi_pll_sel = ddi_pll_sel;
12337 crtc_state->pch_pfit.force_thru = force_thru;
12338 }
12339
12340 static int
12341 intel_modeset_pipe_config(struct drm_crtc *crtc,
12342 struct intel_crtc_state *pipe_config)
12343 {
12344 struct drm_atomic_state *state = pipe_config->base.state;
12345 struct intel_encoder *encoder;
12346 struct drm_connector *connector;
12347 struct drm_connector_state *connector_state;
12348 int base_bpp, ret = -EINVAL;
12349 int i;
12350 bool retry = true;
12351
12352 clear_intel_crtc_state(pipe_config);
12353
12354 pipe_config->cpu_transcoder =
12355 (enum transcoder) to_intel_crtc(crtc)->pipe;
12356
12357 /*
12358 * Sanitize sync polarity flags based on requested ones. If neither
12359 * positive or negative polarity is requested, treat this as meaning
12360 * negative polarity.
12361 */
12362 if (!(pipe_config->base.adjusted_mode.flags &
12363 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12364 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12365
12366 if (!(pipe_config->base.adjusted_mode.flags &
12367 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12368 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12369
12370 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12371 pipe_config);
12372 if (base_bpp < 0)
12373 goto fail;
12374
12375 /*
12376 * Determine the real pipe dimensions. Note that stereo modes can
12377 * increase the actual pipe size due to the frame doubling and
12378 * insertion of additional space for blanks between the frame. This
12379 * is stored in the crtc timings. We use the requested mode to do this
12380 * computation to clearly distinguish it from the adjusted mode, which
12381 * can be changed by the connectors in the below retry loop.
12382 */
12383 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12384 &pipe_config->pipe_src_w,
12385 &pipe_config->pipe_src_h);
12386
12387 encoder_retry:
12388 /* Ensure the port clock defaults are reset when retrying. */
12389 pipe_config->port_clock = 0;
12390 pipe_config->pixel_multiplier = 1;
12391
12392 /* Fill in default crtc timings, allow encoders to overwrite them. */
12393 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12394 CRTC_STEREO_DOUBLE);
12395
12396 /* Pass our mode to the connectors and the CRTC to give them a chance to
12397 * adjust it according to limitations or connector properties, and also
12398 * a chance to reject the mode entirely.
12399 */
12400 for_each_connector_in_state(state, connector, connector_state, i) {
12401 if (connector_state->crtc != crtc)
12402 continue;
12403
12404 encoder = to_intel_encoder(connector_state->best_encoder);
12405
12406 if (!(encoder->compute_config(encoder, pipe_config))) {
12407 DRM_DEBUG_KMS("Encoder config failure\n");
12408 goto fail;
12409 }
12410 }
12411
12412 /* Set default port clock if not overwritten by the encoder. Needs to be
12413 * done afterwards in case the encoder adjusts the mode. */
12414 if (!pipe_config->port_clock)
12415 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12416 * pipe_config->pixel_multiplier;
12417
12418 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12419 if (ret < 0) {
12420 DRM_DEBUG_KMS("CRTC fixup failed\n");
12421 goto fail;
12422 }
12423
12424 if (ret == RETRY) {
12425 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12426 ret = -EINVAL;
12427 goto fail;
12428 }
12429
12430 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12431 retry = false;
12432 goto encoder_retry;
12433 }
12434
12435 /* Dithering seems to not pass-through bits correctly when it should, so
12436 * only enable it on 6bpc panels. */
12437 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12438 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12439 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12440
12441 fail:
12442 return ret;
12443 }
12444
12445 static void
12446 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12447 {
12448 struct drm_crtc *crtc;
12449 struct drm_crtc_state *crtc_state;
12450 int i;
12451
12452 /* Double check state. */
12453 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12454 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12455
12456 /* Update hwmode for vblank functions */
12457 if (crtc->state->active)
12458 crtc->hwmode = crtc->state->adjusted_mode;
12459 else
12460 crtc->hwmode.crtc_clock = 0;
12461
12462 /*
12463 * Update legacy state to satisfy fbc code. This can
12464 * be removed when fbc uses the atomic state.
12465 */
12466 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12467 struct drm_plane_state *plane_state = crtc->primary->state;
12468
12469 crtc->primary->fb = plane_state->fb;
12470 crtc->x = plane_state->src_x >> 16;
12471 crtc->y = plane_state->src_y >> 16;
12472 }
12473 }
12474 }
12475
12476 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12477 {
12478 int diff;
12479
12480 if (clock1 == clock2)
12481 return true;
12482
12483 if (!clock1 || !clock2)
12484 return false;
12485
12486 diff = abs(clock1 - clock2);
12487
12488 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12489 return true;
12490
12491 return false;
12492 }
12493
12494 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12495 list_for_each_entry((intel_crtc), \
12496 &(dev)->mode_config.crtc_list, \
12497 base.head) \
12498 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12499
12500 static bool
12501 intel_compare_m_n(unsigned int m, unsigned int n,
12502 unsigned int m2, unsigned int n2,
12503 bool exact)
12504 {
12505 if (m == m2 && n == n2)
12506 return true;
12507
12508 if (exact || !m || !n || !m2 || !n2)
12509 return false;
12510
12511 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12512
12513 if (n > n2) {
12514 while (n > n2) {
12515 m2 <<= 1;
12516 n2 <<= 1;
12517 }
12518 } else if (n < n2) {
12519 while (n < n2) {
12520 m <<= 1;
12521 n <<= 1;
12522 }
12523 }
12524
12525 if (n != n2)
12526 return false;
12527
12528 return intel_fuzzy_clock_check(m, m2);
12529 }
12530
12531 static bool
12532 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12533 struct intel_link_m_n *m2_n2,
12534 bool adjust)
12535 {
12536 if (m_n->tu == m2_n2->tu &&
12537 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12538 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12539 intel_compare_m_n(m_n->link_m, m_n->link_n,
12540 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12541 if (adjust)
12542 *m2_n2 = *m_n;
12543
12544 return true;
12545 }
12546
12547 return false;
12548 }
12549
12550 static bool
12551 intel_pipe_config_compare(struct drm_device *dev,
12552 struct intel_crtc_state *current_config,
12553 struct intel_crtc_state *pipe_config,
12554 bool adjust)
12555 {
12556 bool ret = true;
12557
12558 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12559 do { \
12560 if (!adjust) \
12561 DRM_ERROR(fmt, ##__VA_ARGS__); \
12562 else \
12563 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12564 } while (0)
12565
12566 #define PIPE_CONF_CHECK_X(name) \
12567 if (current_config->name != pipe_config->name) { \
12568 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12569 "(expected 0x%08x, found 0x%08x)\n", \
12570 current_config->name, \
12571 pipe_config->name); \
12572 ret = false; \
12573 }
12574
12575 #define PIPE_CONF_CHECK_I(name) \
12576 if (current_config->name != pipe_config->name) { \
12577 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12578 "(expected %i, found %i)\n", \
12579 current_config->name, \
12580 pipe_config->name); \
12581 ret = false; \
12582 }
12583
12584 #define PIPE_CONF_CHECK_P(name) \
12585 if (current_config->name != pipe_config->name) { \
12586 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12587 "(expected %p, found %p)\n", \
12588 current_config->name, \
12589 pipe_config->name); \
12590 ret = false; \
12591 }
12592
12593 #define PIPE_CONF_CHECK_M_N(name) \
12594 if (!intel_compare_link_m_n(&current_config->name, \
12595 &pipe_config->name,\
12596 adjust)) { \
12597 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12598 "(expected tu %i gmch %i/%i link %i/%i, " \
12599 "found tu %i, gmch %i/%i link %i/%i)\n", \
12600 current_config->name.tu, \
12601 current_config->name.gmch_m, \
12602 current_config->name.gmch_n, \
12603 current_config->name.link_m, \
12604 current_config->name.link_n, \
12605 pipe_config->name.tu, \
12606 pipe_config->name.gmch_m, \
12607 pipe_config->name.gmch_n, \
12608 pipe_config->name.link_m, \
12609 pipe_config->name.link_n); \
12610 ret = false; \
12611 }
12612
12613 /* This is required for BDW+ where there is only one set of registers for
12614 * switching between high and low RR.
12615 * This macro can be used whenever a comparison has to be made between one
12616 * hw state and multiple sw state variables.
12617 */
12618 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12619 if (!intel_compare_link_m_n(&current_config->name, \
12620 &pipe_config->name, adjust) && \
12621 !intel_compare_link_m_n(&current_config->alt_name, \
12622 &pipe_config->name, adjust)) { \
12623 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12624 "(expected tu %i gmch %i/%i link %i/%i, " \
12625 "or tu %i gmch %i/%i link %i/%i, " \
12626 "found tu %i, gmch %i/%i link %i/%i)\n", \
12627 current_config->name.tu, \
12628 current_config->name.gmch_m, \
12629 current_config->name.gmch_n, \
12630 current_config->name.link_m, \
12631 current_config->name.link_n, \
12632 current_config->alt_name.tu, \
12633 current_config->alt_name.gmch_m, \
12634 current_config->alt_name.gmch_n, \
12635 current_config->alt_name.link_m, \
12636 current_config->alt_name.link_n, \
12637 pipe_config->name.tu, \
12638 pipe_config->name.gmch_m, \
12639 pipe_config->name.gmch_n, \
12640 pipe_config->name.link_m, \
12641 pipe_config->name.link_n); \
12642 ret = false; \
12643 }
12644
12645 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12646 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12647 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12648 "(expected %i, found %i)\n", \
12649 current_config->name & (mask), \
12650 pipe_config->name & (mask)); \
12651 ret = false; \
12652 }
12653
12654 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12655 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12656 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12657 "(expected %i, found %i)\n", \
12658 current_config->name, \
12659 pipe_config->name); \
12660 ret = false; \
12661 }
12662
12663 #define PIPE_CONF_QUIRK(quirk) \
12664 ((current_config->quirks | pipe_config->quirks) & (quirk))
12665
12666 PIPE_CONF_CHECK_I(cpu_transcoder);
12667
12668 PIPE_CONF_CHECK_I(has_pch_encoder);
12669 PIPE_CONF_CHECK_I(fdi_lanes);
12670 PIPE_CONF_CHECK_M_N(fdi_m_n);
12671
12672 PIPE_CONF_CHECK_I(has_dp_encoder);
12673 PIPE_CONF_CHECK_I(lane_count);
12674
12675 if (INTEL_INFO(dev)->gen < 8) {
12676 PIPE_CONF_CHECK_M_N(dp_m_n);
12677
12678 if (current_config->has_drrs)
12679 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12680 } else
12681 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12682
12683 PIPE_CONF_CHECK_I(has_dsi_encoder);
12684
12685 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12686 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12687 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12688 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12689 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12690 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12691
12692 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12693 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12694 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12695 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12696 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12697 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12698
12699 PIPE_CONF_CHECK_I(pixel_multiplier);
12700 PIPE_CONF_CHECK_I(has_hdmi_sink);
12701 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12702 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12703 PIPE_CONF_CHECK_I(limited_color_range);
12704 PIPE_CONF_CHECK_I(has_infoframe);
12705
12706 PIPE_CONF_CHECK_I(has_audio);
12707
12708 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12709 DRM_MODE_FLAG_INTERLACE);
12710
12711 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12712 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12713 DRM_MODE_FLAG_PHSYNC);
12714 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12715 DRM_MODE_FLAG_NHSYNC);
12716 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12717 DRM_MODE_FLAG_PVSYNC);
12718 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12719 DRM_MODE_FLAG_NVSYNC);
12720 }
12721
12722 PIPE_CONF_CHECK_X(gmch_pfit.control);
12723 /* pfit ratios are autocomputed by the hw on gen4+ */
12724 if (INTEL_INFO(dev)->gen < 4)
12725 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12726 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12727
12728 if (!adjust) {
12729 PIPE_CONF_CHECK_I(pipe_src_w);
12730 PIPE_CONF_CHECK_I(pipe_src_h);
12731
12732 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12733 if (current_config->pch_pfit.enabled) {
12734 PIPE_CONF_CHECK_X(pch_pfit.pos);
12735 PIPE_CONF_CHECK_X(pch_pfit.size);
12736 }
12737
12738 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12739 }
12740
12741 /* BDW+ don't expose a synchronous way to read the state */
12742 if (IS_HASWELL(dev))
12743 PIPE_CONF_CHECK_I(ips_enabled);
12744
12745 PIPE_CONF_CHECK_I(double_wide);
12746
12747 PIPE_CONF_CHECK_X(ddi_pll_sel);
12748
12749 PIPE_CONF_CHECK_P(shared_dpll);
12750 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12751 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12752 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12753 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12754 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12755 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12756 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12757 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12758 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12759
12760 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12761 PIPE_CONF_CHECK_X(dsi_pll.div);
12762
12763 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12764 PIPE_CONF_CHECK_I(pipe_bpp);
12765
12766 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12767 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12768
12769 #undef PIPE_CONF_CHECK_X
12770 #undef PIPE_CONF_CHECK_I
12771 #undef PIPE_CONF_CHECK_P
12772 #undef PIPE_CONF_CHECK_FLAGS
12773 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12774 #undef PIPE_CONF_QUIRK
12775 #undef INTEL_ERR_OR_DBG_KMS
12776
12777 return ret;
12778 }
12779
12780 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12781 const struct intel_crtc_state *pipe_config)
12782 {
12783 if (pipe_config->has_pch_encoder) {
12784 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12785 &pipe_config->fdi_m_n);
12786 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12787
12788 /*
12789 * FDI already provided one idea for the dotclock.
12790 * Yell if the encoder disagrees.
12791 */
12792 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12793 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12794 fdi_dotclock, dotclock);
12795 }
12796 }
12797
12798 static void verify_wm_state(struct drm_crtc *crtc,
12799 struct drm_crtc_state *new_state)
12800 {
12801 struct drm_device *dev = crtc->dev;
12802 struct drm_i915_private *dev_priv = dev->dev_private;
12803 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12804 struct skl_ddb_entry *hw_entry, *sw_entry;
12805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12806 const enum pipe pipe = intel_crtc->pipe;
12807 int plane;
12808
12809 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12810 return;
12811
12812 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12813 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12814
12815 /* planes */
12816 for_each_plane(dev_priv, pipe, plane) {
12817 hw_entry = &hw_ddb.plane[pipe][plane];
12818 sw_entry = &sw_ddb->plane[pipe][plane];
12819
12820 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12821 continue;
12822
12823 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12824 "(expected (%u,%u), found (%u,%u))\n",
12825 pipe_name(pipe), plane + 1,
12826 sw_entry->start, sw_entry->end,
12827 hw_entry->start, hw_entry->end);
12828 }
12829
12830 /* cursor */
12831 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12832 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12833
12834 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12835 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12836 "(expected (%u,%u), found (%u,%u))\n",
12837 pipe_name(pipe),
12838 sw_entry->start, sw_entry->end,
12839 hw_entry->start, hw_entry->end);
12840 }
12841 }
12842
12843 static void
12844 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12845 {
12846 struct drm_connector *connector;
12847
12848 drm_for_each_connector(connector, dev) {
12849 struct drm_encoder *encoder = connector->encoder;
12850 struct drm_connector_state *state = connector->state;
12851
12852 if (state->crtc != crtc)
12853 continue;
12854
12855 intel_connector_verify_state(to_intel_connector(connector));
12856
12857 I915_STATE_WARN(state->best_encoder != encoder,
12858 "connector's atomic encoder doesn't match legacy encoder\n");
12859 }
12860 }
12861
12862 static void
12863 verify_encoder_state(struct drm_device *dev)
12864 {
12865 struct intel_encoder *encoder;
12866 struct intel_connector *connector;
12867
12868 for_each_intel_encoder(dev, encoder) {
12869 bool enabled = false;
12870 enum pipe pipe;
12871
12872 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12873 encoder->base.base.id,
12874 encoder->base.name);
12875
12876 for_each_intel_connector(dev, connector) {
12877 if (connector->base.state->best_encoder != &encoder->base)
12878 continue;
12879 enabled = true;
12880
12881 I915_STATE_WARN(connector->base.state->crtc !=
12882 encoder->base.crtc,
12883 "connector's crtc doesn't match encoder crtc\n");
12884 }
12885
12886 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12887 "encoder's enabled state mismatch "
12888 "(expected %i, found %i)\n",
12889 !!encoder->base.crtc, enabled);
12890
12891 if (!encoder->base.crtc) {
12892 bool active;
12893
12894 active = encoder->get_hw_state(encoder, &pipe);
12895 I915_STATE_WARN(active,
12896 "encoder detached but still enabled on pipe %c.\n",
12897 pipe_name(pipe));
12898 }
12899 }
12900 }
12901
12902 static void
12903 verify_crtc_state(struct drm_crtc *crtc,
12904 struct drm_crtc_state *old_crtc_state,
12905 struct drm_crtc_state *new_crtc_state)
12906 {
12907 struct drm_device *dev = crtc->dev;
12908 struct drm_i915_private *dev_priv = dev->dev_private;
12909 struct intel_encoder *encoder;
12910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12911 struct intel_crtc_state *pipe_config, *sw_config;
12912 struct drm_atomic_state *old_state;
12913 bool active;
12914
12915 old_state = old_crtc_state->state;
12916 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12917 pipe_config = to_intel_crtc_state(old_crtc_state);
12918 memset(pipe_config, 0, sizeof(*pipe_config));
12919 pipe_config->base.crtc = crtc;
12920 pipe_config->base.state = old_state;
12921
12922 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12923
12924 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12925
12926 /* hw state is inconsistent with the pipe quirk */
12927 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12928 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12929 active = new_crtc_state->active;
12930
12931 I915_STATE_WARN(new_crtc_state->active != active,
12932 "crtc active state doesn't match with hw state "
12933 "(expected %i, found %i)\n", new_crtc_state->active, active);
12934
12935 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12936 "transitional active state does not match atomic hw state "
12937 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12938
12939 for_each_encoder_on_crtc(dev, crtc, encoder) {
12940 enum pipe pipe;
12941
12942 active = encoder->get_hw_state(encoder, &pipe);
12943 I915_STATE_WARN(active != new_crtc_state->active,
12944 "[ENCODER:%i] active %i with crtc active %i\n",
12945 encoder->base.base.id, active, new_crtc_state->active);
12946
12947 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12948 "Encoder connected to wrong pipe %c\n",
12949 pipe_name(pipe));
12950
12951 if (active)
12952 encoder->get_config(encoder, pipe_config);
12953 }
12954
12955 if (!new_crtc_state->active)
12956 return;
12957
12958 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12959
12960 sw_config = to_intel_crtc_state(crtc->state);
12961 if (!intel_pipe_config_compare(dev, sw_config,
12962 pipe_config, false)) {
12963 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12964 intel_dump_pipe_config(intel_crtc, pipe_config,
12965 "[hw state]");
12966 intel_dump_pipe_config(intel_crtc, sw_config,
12967 "[sw state]");
12968 }
12969 }
12970
12971 static void
12972 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12973 struct intel_shared_dpll *pll,
12974 struct drm_crtc *crtc,
12975 struct drm_crtc_state *new_state)
12976 {
12977 struct intel_dpll_hw_state dpll_hw_state;
12978 unsigned crtc_mask;
12979 bool active;
12980
12981 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12982
12983 DRM_DEBUG_KMS("%s\n", pll->name);
12984
12985 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12986
12987 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12988 I915_STATE_WARN(!pll->on && pll->active_mask,
12989 "pll in active use but not on in sw tracking\n");
12990 I915_STATE_WARN(pll->on && !pll->active_mask,
12991 "pll is on but not used by any active crtc\n");
12992 I915_STATE_WARN(pll->on != active,
12993 "pll on state mismatch (expected %i, found %i)\n",
12994 pll->on, active);
12995 }
12996
12997 if (!crtc) {
12998 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12999 "more active pll users than references: %x vs %x\n",
13000 pll->active_mask, pll->config.crtc_mask);
13001
13002 return;
13003 }
13004
13005 crtc_mask = 1 << drm_crtc_index(crtc);
13006
13007 if (new_state->active)
13008 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13009 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13010 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13011 else
13012 I915_STATE_WARN(pll->active_mask & crtc_mask,
13013 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13014 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13015
13016 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13017 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13018 crtc_mask, pll->config.crtc_mask);
13019
13020 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13021 &dpll_hw_state,
13022 sizeof(dpll_hw_state)),
13023 "pll hw state mismatch\n");
13024 }
13025
13026 static void
13027 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13028 struct drm_crtc_state *old_crtc_state,
13029 struct drm_crtc_state *new_crtc_state)
13030 {
13031 struct drm_i915_private *dev_priv = dev->dev_private;
13032 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13033 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13034
13035 if (new_state->shared_dpll)
13036 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13037
13038 if (old_state->shared_dpll &&
13039 old_state->shared_dpll != new_state->shared_dpll) {
13040 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13041 struct intel_shared_dpll *pll = old_state->shared_dpll;
13042
13043 I915_STATE_WARN(pll->active_mask & crtc_mask,
13044 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13045 pipe_name(drm_crtc_index(crtc)));
13046 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13047 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13048 pipe_name(drm_crtc_index(crtc)));
13049 }
13050 }
13051
13052 static void
13053 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13054 struct drm_crtc_state *old_state,
13055 struct drm_crtc_state *new_state)
13056 {
13057 if (!needs_modeset(new_state) &&
13058 !to_intel_crtc_state(new_state)->update_pipe)
13059 return;
13060
13061 verify_wm_state(crtc, new_state);
13062 verify_connector_state(crtc->dev, crtc);
13063 verify_crtc_state(crtc, old_state, new_state);
13064 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13065 }
13066
13067 static void
13068 verify_disabled_dpll_state(struct drm_device *dev)
13069 {
13070 struct drm_i915_private *dev_priv = dev->dev_private;
13071 int i;
13072
13073 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13074 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13075 }
13076
13077 static void
13078 intel_modeset_verify_disabled(struct drm_device *dev)
13079 {
13080 verify_encoder_state(dev);
13081 verify_connector_state(dev, NULL);
13082 verify_disabled_dpll_state(dev);
13083 }
13084
13085 static void update_scanline_offset(struct intel_crtc *crtc)
13086 {
13087 struct drm_device *dev = crtc->base.dev;
13088
13089 /*
13090 * The scanline counter increments at the leading edge of hsync.
13091 *
13092 * On most platforms it starts counting from vtotal-1 on the
13093 * first active line. That means the scanline counter value is
13094 * always one less than what we would expect. Ie. just after
13095 * start of vblank, which also occurs at start of hsync (on the
13096 * last active line), the scanline counter will read vblank_start-1.
13097 *
13098 * On gen2 the scanline counter starts counting from 1 instead
13099 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13100 * to keep the value positive), instead of adding one.
13101 *
13102 * On HSW+ the behaviour of the scanline counter depends on the output
13103 * type. For DP ports it behaves like most other platforms, but on HDMI
13104 * there's an extra 1 line difference. So we need to add two instead of
13105 * one to the value.
13106 */
13107 if (IS_GEN2(dev)) {
13108 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13109 int vtotal;
13110
13111 vtotal = adjusted_mode->crtc_vtotal;
13112 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13113 vtotal /= 2;
13114
13115 crtc->scanline_offset = vtotal - 1;
13116 } else if (HAS_DDI(dev) &&
13117 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13118 crtc->scanline_offset = 2;
13119 } else
13120 crtc->scanline_offset = 1;
13121 }
13122
13123 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13124 {
13125 struct drm_device *dev = state->dev;
13126 struct drm_i915_private *dev_priv = to_i915(dev);
13127 struct intel_shared_dpll_config *shared_dpll = NULL;
13128 struct drm_crtc *crtc;
13129 struct drm_crtc_state *crtc_state;
13130 int i;
13131
13132 if (!dev_priv->display.crtc_compute_clock)
13133 return;
13134
13135 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13137 struct intel_shared_dpll *old_dpll =
13138 to_intel_crtc_state(crtc->state)->shared_dpll;
13139
13140 if (!needs_modeset(crtc_state))
13141 continue;
13142
13143 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13144
13145 if (!old_dpll)
13146 continue;
13147
13148 if (!shared_dpll)
13149 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13150
13151 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13152 }
13153 }
13154
13155 /*
13156 * This implements the workaround described in the "notes" section of the mode
13157 * set sequence documentation. When going from no pipes or single pipe to
13158 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13159 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13160 */
13161 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13162 {
13163 struct drm_crtc_state *crtc_state;
13164 struct intel_crtc *intel_crtc;
13165 struct drm_crtc *crtc;
13166 struct intel_crtc_state *first_crtc_state = NULL;
13167 struct intel_crtc_state *other_crtc_state = NULL;
13168 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13169 int i;
13170
13171 /* look at all crtc's that are going to be enabled in during modeset */
13172 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13173 intel_crtc = to_intel_crtc(crtc);
13174
13175 if (!crtc_state->active || !needs_modeset(crtc_state))
13176 continue;
13177
13178 if (first_crtc_state) {
13179 other_crtc_state = to_intel_crtc_state(crtc_state);
13180 break;
13181 } else {
13182 first_crtc_state = to_intel_crtc_state(crtc_state);
13183 first_pipe = intel_crtc->pipe;
13184 }
13185 }
13186
13187 /* No workaround needed? */
13188 if (!first_crtc_state)
13189 return 0;
13190
13191 /* w/a possibly needed, check how many crtc's are already enabled. */
13192 for_each_intel_crtc(state->dev, intel_crtc) {
13193 struct intel_crtc_state *pipe_config;
13194
13195 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13196 if (IS_ERR(pipe_config))
13197 return PTR_ERR(pipe_config);
13198
13199 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13200
13201 if (!pipe_config->base.active ||
13202 needs_modeset(&pipe_config->base))
13203 continue;
13204
13205 /* 2 or more enabled crtcs means no need for w/a */
13206 if (enabled_pipe != INVALID_PIPE)
13207 return 0;
13208
13209 enabled_pipe = intel_crtc->pipe;
13210 }
13211
13212 if (enabled_pipe != INVALID_PIPE)
13213 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13214 else if (other_crtc_state)
13215 other_crtc_state->hsw_workaround_pipe = first_pipe;
13216
13217 return 0;
13218 }
13219
13220 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13221 {
13222 struct drm_crtc *crtc;
13223 struct drm_crtc_state *crtc_state;
13224 int ret = 0;
13225
13226 /* add all active pipes to the state */
13227 for_each_crtc(state->dev, crtc) {
13228 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13229 if (IS_ERR(crtc_state))
13230 return PTR_ERR(crtc_state);
13231
13232 if (!crtc_state->active || needs_modeset(crtc_state))
13233 continue;
13234
13235 crtc_state->mode_changed = true;
13236
13237 ret = drm_atomic_add_affected_connectors(state, crtc);
13238 if (ret)
13239 break;
13240
13241 ret = drm_atomic_add_affected_planes(state, crtc);
13242 if (ret)
13243 break;
13244 }
13245
13246 return ret;
13247 }
13248
13249 static int intel_modeset_checks(struct drm_atomic_state *state)
13250 {
13251 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13252 struct drm_i915_private *dev_priv = state->dev->dev_private;
13253 struct drm_crtc *crtc;
13254 struct drm_crtc_state *crtc_state;
13255 int ret = 0, i;
13256
13257 if (!check_digital_port_conflicts(state)) {
13258 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13259 return -EINVAL;
13260 }
13261
13262 intel_state->modeset = true;
13263 intel_state->active_crtcs = dev_priv->active_crtcs;
13264
13265 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13266 if (crtc_state->active)
13267 intel_state->active_crtcs |= 1 << i;
13268 else
13269 intel_state->active_crtcs &= ~(1 << i);
13270
13271 if (crtc_state->active != crtc->state->active)
13272 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13273 }
13274
13275 /*
13276 * See if the config requires any additional preparation, e.g.
13277 * to adjust global state with pipes off. We need to do this
13278 * here so we can get the modeset_pipe updated config for the new
13279 * mode set on this crtc. For other crtcs we need to use the
13280 * adjusted_mode bits in the crtc directly.
13281 */
13282 if (dev_priv->display.modeset_calc_cdclk) {
13283 ret = dev_priv->display.modeset_calc_cdclk(state);
13284
13285 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13286 ret = intel_modeset_all_pipes(state);
13287
13288 if (ret < 0)
13289 return ret;
13290
13291 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13292 intel_state->cdclk, intel_state->dev_cdclk);
13293 } else
13294 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13295
13296 intel_modeset_clear_plls(state);
13297
13298 if (IS_HASWELL(dev_priv))
13299 return haswell_mode_set_planes_workaround(state);
13300
13301 return 0;
13302 }
13303
13304 /*
13305 * Handle calculation of various watermark data at the end of the atomic check
13306 * phase. The code here should be run after the per-crtc and per-plane 'check'
13307 * handlers to ensure that all derived state has been updated.
13308 */
13309 static int calc_watermark_data(struct drm_atomic_state *state)
13310 {
13311 struct drm_device *dev = state->dev;
13312 struct drm_i915_private *dev_priv = to_i915(dev);
13313
13314 /* Is there platform-specific watermark information to calculate? */
13315 if (dev_priv->display.compute_global_watermarks)
13316 return dev_priv->display.compute_global_watermarks(state);
13317
13318 return 0;
13319 }
13320
13321 /**
13322 * intel_atomic_check - validate state object
13323 * @dev: drm device
13324 * @state: state to validate
13325 */
13326 static int intel_atomic_check(struct drm_device *dev,
13327 struct drm_atomic_state *state)
13328 {
13329 struct drm_i915_private *dev_priv = to_i915(dev);
13330 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13331 struct drm_crtc *crtc;
13332 struct drm_crtc_state *crtc_state;
13333 int ret, i;
13334 bool any_ms = false;
13335
13336 ret = drm_atomic_helper_check_modeset(dev, state);
13337 if (ret)
13338 return ret;
13339
13340 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13341 struct intel_crtc_state *pipe_config =
13342 to_intel_crtc_state(crtc_state);
13343
13344 /* Catch I915_MODE_FLAG_INHERITED */
13345 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13346 crtc_state->mode_changed = true;
13347
13348 if (!crtc_state->enable) {
13349 if (needs_modeset(crtc_state))
13350 any_ms = true;
13351 continue;
13352 }
13353
13354 if (!needs_modeset(crtc_state))
13355 continue;
13356
13357 /* FIXME: For only active_changed we shouldn't need to do any
13358 * state recomputation at all. */
13359
13360 ret = drm_atomic_add_affected_connectors(state, crtc);
13361 if (ret)
13362 return ret;
13363
13364 ret = intel_modeset_pipe_config(crtc, pipe_config);
13365 if (ret) {
13366 intel_dump_pipe_config(to_intel_crtc(crtc),
13367 pipe_config, "[failed]");
13368 return ret;
13369 }
13370
13371 if (i915.fastboot &&
13372 intel_pipe_config_compare(dev,
13373 to_intel_crtc_state(crtc->state),
13374 pipe_config, true)) {
13375 crtc_state->mode_changed = false;
13376 to_intel_crtc_state(crtc_state)->update_pipe = true;
13377 }
13378
13379 if (needs_modeset(crtc_state)) {
13380 any_ms = true;
13381
13382 ret = drm_atomic_add_affected_planes(state, crtc);
13383 if (ret)
13384 return ret;
13385 }
13386
13387 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13388 needs_modeset(crtc_state) ?
13389 "[modeset]" : "[fastset]");
13390 }
13391
13392 if (any_ms) {
13393 ret = intel_modeset_checks(state);
13394
13395 if (ret)
13396 return ret;
13397 } else
13398 intel_state->cdclk = dev_priv->cdclk_freq;
13399
13400 ret = drm_atomic_helper_check_planes(dev, state);
13401 if (ret)
13402 return ret;
13403
13404 intel_fbc_choose_crtc(dev_priv, state);
13405 return calc_watermark_data(state);
13406 }
13407
13408 static int intel_atomic_prepare_commit(struct drm_device *dev,
13409 struct drm_atomic_state *state,
13410 bool async)
13411 {
13412 struct drm_i915_private *dev_priv = dev->dev_private;
13413 struct drm_plane_state *plane_state;
13414 struct drm_crtc_state *crtc_state;
13415 struct drm_plane *plane;
13416 struct drm_crtc *crtc;
13417 int i, ret;
13418
13419 if (async) {
13420 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13421 return -EINVAL;
13422 }
13423
13424 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13425 if (state->legacy_cursor_update)
13426 continue;
13427
13428 ret = intel_crtc_wait_for_pending_flips(crtc);
13429 if (ret)
13430 return ret;
13431
13432 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13433 flush_workqueue(dev_priv->wq);
13434 }
13435
13436 ret = mutex_lock_interruptible(&dev->struct_mutex);
13437 if (ret)
13438 return ret;
13439
13440 ret = drm_atomic_helper_prepare_planes(dev, state);
13441 mutex_unlock(&dev->struct_mutex);
13442
13443 if (!ret && !async) {
13444 for_each_plane_in_state(state, plane, plane_state, i) {
13445 struct intel_plane_state *intel_plane_state =
13446 to_intel_plane_state(plane_state);
13447
13448 if (!intel_plane_state->wait_req)
13449 continue;
13450
13451 ret = __i915_wait_request(intel_plane_state->wait_req,
13452 true, NULL, NULL);
13453 if (ret) {
13454 /* Any hang should be swallowed by the wait */
13455 WARN_ON(ret == -EIO);
13456 mutex_lock(&dev->struct_mutex);
13457 drm_atomic_helper_cleanup_planes(dev, state);
13458 mutex_unlock(&dev->struct_mutex);
13459 break;
13460 }
13461 }
13462 }
13463
13464 return ret;
13465 }
13466
13467 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13468 struct drm_i915_private *dev_priv,
13469 unsigned crtc_mask)
13470 {
13471 unsigned last_vblank_count[I915_MAX_PIPES];
13472 enum pipe pipe;
13473 int ret;
13474
13475 if (!crtc_mask)
13476 return;
13477
13478 for_each_pipe(dev_priv, pipe) {
13479 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13480
13481 if (!((1 << pipe) & crtc_mask))
13482 continue;
13483
13484 ret = drm_crtc_vblank_get(crtc);
13485 if (WARN_ON(ret != 0)) {
13486 crtc_mask &= ~(1 << pipe);
13487 continue;
13488 }
13489
13490 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13491 }
13492
13493 for_each_pipe(dev_priv, pipe) {
13494 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13495 long lret;
13496
13497 if (!((1 << pipe) & crtc_mask))
13498 continue;
13499
13500 lret = wait_event_timeout(dev->vblank[pipe].queue,
13501 last_vblank_count[pipe] !=
13502 drm_crtc_vblank_count(crtc),
13503 msecs_to_jiffies(50));
13504
13505 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13506
13507 drm_crtc_vblank_put(crtc);
13508 }
13509 }
13510
13511 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13512 {
13513 /* fb updated, need to unpin old fb */
13514 if (crtc_state->fb_changed)
13515 return true;
13516
13517 /* wm changes, need vblank before final wm's */
13518 if (crtc_state->update_wm_post)
13519 return true;
13520
13521 /*
13522 * cxsr is re-enabled after vblank.
13523 * This is already handled by crtc_state->update_wm_post,
13524 * but added for clarity.
13525 */
13526 if (crtc_state->disable_cxsr)
13527 return true;
13528
13529 return false;
13530 }
13531
13532 /**
13533 * intel_atomic_commit - commit validated state object
13534 * @dev: DRM device
13535 * @state: the top-level driver state object
13536 * @async: asynchronous commit
13537 *
13538 * This function commits a top-level state object that has been validated
13539 * with drm_atomic_helper_check().
13540 *
13541 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13542 * we can only handle plane-related operations and do not yet support
13543 * asynchronous commit.
13544 *
13545 * RETURNS
13546 * Zero for success or -errno.
13547 */
13548 static int intel_atomic_commit(struct drm_device *dev,
13549 struct drm_atomic_state *state,
13550 bool async)
13551 {
13552 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13553 struct drm_i915_private *dev_priv = dev->dev_private;
13554 struct drm_crtc_state *old_crtc_state;
13555 struct drm_crtc *crtc;
13556 struct intel_crtc_state *intel_cstate;
13557 int ret = 0, i;
13558 bool hw_check = intel_state->modeset;
13559 unsigned long put_domains[I915_MAX_PIPES] = {};
13560 unsigned crtc_vblank_mask = 0;
13561
13562 ret = intel_atomic_prepare_commit(dev, state, async);
13563 if (ret) {
13564 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13565 return ret;
13566 }
13567
13568 drm_atomic_helper_swap_state(dev, state);
13569 dev_priv->wm.distrust_bios_wm = false;
13570 dev_priv->wm.skl_results = intel_state->wm_results;
13571 intel_shared_dpll_commit(state);
13572
13573 if (intel_state->modeset) {
13574 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13575 sizeof(intel_state->min_pixclk));
13576 dev_priv->active_crtcs = intel_state->active_crtcs;
13577 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13578
13579 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13580 }
13581
13582 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13584
13585 if (needs_modeset(crtc->state) ||
13586 to_intel_crtc_state(crtc->state)->update_pipe) {
13587 hw_check = true;
13588
13589 put_domains[to_intel_crtc(crtc)->pipe] =
13590 modeset_get_crtc_power_domains(crtc,
13591 to_intel_crtc_state(crtc->state));
13592 }
13593
13594 if (!needs_modeset(crtc->state))
13595 continue;
13596
13597 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13598
13599 if (old_crtc_state->active) {
13600 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13601 dev_priv->display.crtc_disable(crtc);
13602 intel_crtc->active = false;
13603 intel_fbc_disable(intel_crtc);
13604 intel_disable_shared_dpll(intel_crtc);
13605
13606 /*
13607 * Underruns don't always raise
13608 * interrupts, so check manually.
13609 */
13610 intel_check_cpu_fifo_underruns(dev_priv);
13611 intel_check_pch_fifo_underruns(dev_priv);
13612
13613 if (!crtc->state->active)
13614 intel_update_watermarks(crtc);
13615 }
13616 }
13617
13618 /* Only after disabling all output pipelines that will be changed can we
13619 * update the the output configuration. */
13620 intel_modeset_update_crtc_state(state);
13621
13622 if (intel_state->modeset) {
13623 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13624
13625 if (dev_priv->display.modeset_commit_cdclk &&
13626 intel_state->dev_cdclk != dev_priv->cdclk_freq)
13627 dev_priv->display.modeset_commit_cdclk(state);
13628
13629 intel_modeset_verify_disabled(dev);
13630 }
13631
13632 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13633 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13635 bool modeset = needs_modeset(crtc->state);
13636 struct intel_crtc_state *pipe_config =
13637 to_intel_crtc_state(crtc->state);
13638 bool update_pipe = !modeset && pipe_config->update_pipe;
13639
13640 if (modeset && crtc->state->active) {
13641 update_scanline_offset(to_intel_crtc(crtc));
13642 dev_priv->display.crtc_enable(crtc);
13643 }
13644
13645 if (!modeset)
13646 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13647
13648 if (crtc->state->active &&
13649 drm_atomic_get_existing_plane_state(state, crtc->primary))
13650 intel_fbc_enable(intel_crtc);
13651
13652 if (crtc->state->active &&
13653 (crtc->state->planes_changed || update_pipe))
13654 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13655
13656 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13657 crtc_vblank_mask |= 1 << i;
13658 }
13659
13660 /* FIXME: add subpixel order */
13661
13662 if (!state->legacy_cursor_update)
13663 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13664
13665 /*
13666 * Now that the vblank has passed, we can go ahead and program the
13667 * optimal watermarks on platforms that need two-step watermark
13668 * programming.
13669 *
13670 * TODO: Move this (and other cleanup) to an async worker eventually.
13671 */
13672 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13673 intel_cstate = to_intel_crtc_state(crtc->state);
13674
13675 if (dev_priv->display.optimize_watermarks)
13676 dev_priv->display.optimize_watermarks(intel_cstate);
13677 }
13678
13679 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13680 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13681
13682 if (put_domains[i])
13683 modeset_put_power_domains(dev_priv, put_domains[i]);
13684
13685 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13686 }
13687
13688 if (intel_state->modeset)
13689 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13690
13691 mutex_lock(&dev->struct_mutex);
13692 drm_atomic_helper_cleanup_planes(dev, state);
13693 mutex_unlock(&dev->struct_mutex);
13694
13695 drm_atomic_state_free(state);
13696
13697 /* As one of the primary mmio accessors, KMS has a high likelihood
13698 * of triggering bugs in unclaimed access. After we finish
13699 * modesetting, see if an error has been flagged, and if so
13700 * enable debugging for the next modeset - and hope we catch
13701 * the culprit.
13702 *
13703 * XXX note that we assume display power is on at this point.
13704 * This might hold true now but we need to add pm helper to check
13705 * unclaimed only when the hardware is on, as atomic commits
13706 * can happen also when the device is completely off.
13707 */
13708 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13709
13710 return 0;
13711 }
13712
13713 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13714 {
13715 struct drm_device *dev = crtc->dev;
13716 struct drm_atomic_state *state;
13717 struct drm_crtc_state *crtc_state;
13718 int ret;
13719
13720 state = drm_atomic_state_alloc(dev);
13721 if (!state) {
13722 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13723 crtc->base.id);
13724 return;
13725 }
13726
13727 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13728
13729 retry:
13730 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13731 ret = PTR_ERR_OR_ZERO(crtc_state);
13732 if (!ret) {
13733 if (!crtc_state->active)
13734 goto out;
13735
13736 crtc_state->mode_changed = true;
13737 ret = drm_atomic_commit(state);
13738 }
13739
13740 if (ret == -EDEADLK) {
13741 drm_atomic_state_clear(state);
13742 drm_modeset_backoff(state->acquire_ctx);
13743 goto retry;
13744 }
13745
13746 if (ret)
13747 out:
13748 drm_atomic_state_free(state);
13749 }
13750
13751 #undef for_each_intel_crtc_masked
13752
13753 static const struct drm_crtc_funcs intel_crtc_funcs = {
13754 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13755 .set_config = drm_atomic_helper_set_config,
13756 .set_property = drm_atomic_helper_crtc_set_property,
13757 .destroy = intel_crtc_destroy,
13758 .page_flip = intel_crtc_page_flip,
13759 .atomic_duplicate_state = intel_crtc_duplicate_state,
13760 .atomic_destroy_state = intel_crtc_destroy_state,
13761 };
13762
13763 /**
13764 * intel_prepare_plane_fb - Prepare fb for usage on plane
13765 * @plane: drm plane to prepare for
13766 * @fb: framebuffer to prepare for presentation
13767 *
13768 * Prepares a framebuffer for usage on a display plane. Generally this
13769 * involves pinning the underlying object and updating the frontbuffer tracking
13770 * bits. Some older platforms need special physical address handling for
13771 * cursor planes.
13772 *
13773 * Must be called with struct_mutex held.
13774 *
13775 * Returns 0 on success, negative error code on failure.
13776 */
13777 int
13778 intel_prepare_plane_fb(struct drm_plane *plane,
13779 const struct drm_plane_state *new_state)
13780 {
13781 struct drm_device *dev = plane->dev;
13782 struct drm_framebuffer *fb = new_state->fb;
13783 struct intel_plane *intel_plane = to_intel_plane(plane);
13784 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13785 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13786 int ret = 0;
13787
13788 if (!obj && !old_obj)
13789 return 0;
13790
13791 if (old_obj) {
13792 struct drm_crtc_state *crtc_state =
13793 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13794
13795 /* Big Hammer, we also need to ensure that any pending
13796 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13797 * current scanout is retired before unpinning the old
13798 * framebuffer. Note that we rely on userspace rendering
13799 * into the buffer attached to the pipe they are waiting
13800 * on. If not, userspace generates a GPU hang with IPEHR
13801 * point to the MI_WAIT_FOR_EVENT.
13802 *
13803 * This should only fail upon a hung GPU, in which case we
13804 * can safely continue.
13805 */
13806 if (needs_modeset(crtc_state))
13807 ret = i915_gem_object_wait_rendering(old_obj, true);
13808 if (ret) {
13809 /* GPU hangs should have been swallowed by the wait */
13810 WARN_ON(ret == -EIO);
13811 return ret;
13812 }
13813 }
13814
13815 /* For framebuffer backed by dmabuf, wait for fence */
13816 if (obj && obj->base.dma_buf) {
13817 long lret;
13818
13819 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13820 false, true,
13821 MAX_SCHEDULE_TIMEOUT);
13822 if (lret == -ERESTARTSYS)
13823 return lret;
13824
13825 WARN(lret < 0, "waiting returns %li\n", lret);
13826 }
13827
13828 if (!obj) {
13829 ret = 0;
13830 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13831 INTEL_INFO(dev)->cursor_needs_physical) {
13832 int align = IS_I830(dev) ? 16 * 1024 : 256;
13833 ret = i915_gem_object_attach_phys(obj, align);
13834 if (ret)
13835 DRM_DEBUG_KMS("failed to attach phys object\n");
13836 } else {
13837 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13838 }
13839
13840 if (ret == 0) {
13841 if (obj) {
13842 struct intel_plane_state *plane_state =
13843 to_intel_plane_state(new_state);
13844
13845 i915_gem_request_assign(&plane_state->wait_req,
13846 obj->last_write_req);
13847 }
13848
13849 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13850 }
13851
13852 return ret;
13853 }
13854
13855 /**
13856 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13857 * @plane: drm plane to clean up for
13858 * @fb: old framebuffer that was on plane
13859 *
13860 * Cleans up a framebuffer that has just been removed from a plane.
13861 *
13862 * Must be called with struct_mutex held.
13863 */
13864 void
13865 intel_cleanup_plane_fb(struct drm_plane *plane,
13866 const struct drm_plane_state *old_state)
13867 {
13868 struct drm_device *dev = plane->dev;
13869 struct intel_plane *intel_plane = to_intel_plane(plane);
13870 struct intel_plane_state *old_intel_state;
13871 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13872 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13873
13874 old_intel_state = to_intel_plane_state(old_state);
13875
13876 if (!obj && !old_obj)
13877 return;
13878
13879 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13880 !INTEL_INFO(dev)->cursor_needs_physical))
13881 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13882
13883 /* prepare_fb aborted? */
13884 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13885 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13886 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13887
13888 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13889 }
13890
13891 int
13892 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13893 {
13894 int max_scale;
13895 struct drm_device *dev;
13896 struct drm_i915_private *dev_priv;
13897 int crtc_clock, cdclk;
13898
13899 if (!intel_crtc || !crtc_state->base.enable)
13900 return DRM_PLANE_HELPER_NO_SCALING;
13901
13902 dev = intel_crtc->base.dev;
13903 dev_priv = dev->dev_private;
13904 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13905 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13906
13907 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13908 return DRM_PLANE_HELPER_NO_SCALING;
13909
13910 /*
13911 * skl max scale is lower of:
13912 * close to 3 but not 3, -1 is for that purpose
13913 * or
13914 * cdclk/crtc_clock
13915 */
13916 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13917
13918 return max_scale;
13919 }
13920
13921 static int
13922 intel_check_primary_plane(struct drm_plane *plane,
13923 struct intel_crtc_state *crtc_state,
13924 struct intel_plane_state *state)
13925 {
13926 struct drm_crtc *crtc = state->base.crtc;
13927 struct drm_framebuffer *fb = state->base.fb;
13928 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13929 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13930 bool can_position = false;
13931
13932 if (INTEL_INFO(plane->dev)->gen >= 9) {
13933 /* use scaler when colorkey is not required */
13934 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13935 min_scale = 1;
13936 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13937 }
13938 can_position = true;
13939 }
13940
13941 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13942 &state->dst, &state->clip,
13943 min_scale, max_scale,
13944 can_position, true,
13945 &state->visible);
13946 }
13947
13948 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13949 struct drm_crtc_state *old_crtc_state)
13950 {
13951 struct drm_device *dev = crtc->dev;
13952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13953 struct intel_crtc_state *old_intel_state =
13954 to_intel_crtc_state(old_crtc_state);
13955 bool modeset = needs_modeset(crtc->state);
13956
13957 /* Perform vblank evasion around commit operation */
13958 intel_pipe_update_start(intel_crtc);
13959
13960 if (modeset)
13961 return;
13962
13963 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13964 intel_color_set_csc(crtc->state);
13965 intel_color_load_luts(crtc->state);
13966 }
13967
13968 if (to_intel_crtc_state(crtc->state)->update_pipe)
13969 intel_update_pipe_config(intel_crtc, old_intel_state);
13970 else if (INTEL_INFO(dev)->gen >= 9)
13971 skl_detach_scalers(intel_crtc);
13972 }
13973
13974 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13975 struct drm_crtc_state *old_crtc_state)
13976 {
13977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13978
13979 intel_pipe_update_end(intel_crtc);
13980 }
13981
13982 /**
13983 * intel_plane_destroy - destroy a plane
13984 * @plane: plane to destroy
13985 *
13986 * Common destruction function for all types of planes (primary, cursor,
13987 * sprite).
13988 */
13989 void intel_plane_destroy(struct drm_plane *plane)
13990 {
13991 struct intel_plane *intel_plane = to_intel_plane(plane);
13992 drm_plane_cleanup(plane);
13993 kfree(intel_plane);
13994 }
13995
13996 const struct drm_plane_funcs intel_plane_funcs = {
13997 .update_plane = drm_atomic_helper_update_plane,
13998 .disable_plane = drm_atomic_helper_disable_plane,
13999 .destroy = intel_plane_destroy,
14000 .set_property = drm_atomic_helper_plane_set_property,
14001 .atomic_get_property = intel_plane_atomic_get_property,
14002 .atomic_set_property = intel_plane_atomic_set_property,
14003 .atomic_duplicate_state = intel_plane_duplicate_state,
14004 .atomic_destroy_state = intel_plane_destroy_state,
14005
14006 };
14007
14008 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14009 int pipe)
14010 {
14011 struct intel_plane *primary = NULL;
14012 struct intel_plane_state *state = NULL;
14013 const uint32_t *intel_primary_formats;
14014 unsigned int num_formats;
14015 int ret;
14016
14017 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14018 if (!primary)
14019 goto fail;
14020
14021 state = intel_create_plane_state(&primary->base);
14022 if (!state)
14023 goto fail;
14024 primary->base.state = &state->base;
14025
14026 primary->can_scale = false;
14027 primary->max_downscale = 1;
14028 if (INTEL_INFO(dev)->gen >= 9) {
14029 primary->can_scale = true;
14030 state->scaler_id = -1;
14031 }
14032 primary->pipe = pipe;
14033 primary->plane = pipe;
14034 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14035 primary->check_plane = intel_check_primary_plane;
14036 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14037 primary->plane = !pipe;
14038
14039 if (INTEL_INFO(dev)->gen >= 9) {
14040 intel_primary_formats = skl_primary_formats;
14041 num_formats = ARRAY_SIZE(skl_primary_formats);
14042
14043 primary->update_plane = skylake_update_primary_plane;
14044 primary->disable_plane = skylake_disable_primary_plane;
14045 } else if (HAS_PCH_SPLIT(dev)) {
14046 intel_primary_formats = i965_primary_formats;
14047 num_formats = ARRAY_SIZE(i965_primary_formats);
14048
14049 primary->update_plane = ironlake_update_primary_plane;
14050 primary->disable_plane = i9xx_disable_primary_plane;
14051 } else if (INTEL_INFO(dev)->gen >= 4) {
14052 intel_primary_formats = i965_primary_formats;
14053 num_formats = ARRAY_SIZE(i965_primary_formats);
14054
14055 primary->update_plane = i9xx_update_primary_plane;
14056 primary->disable_plane = i9xx_disable_primary_plane;
14057 } else {
14058 intel_primary_formats = i8xx_primary_formats;
14059 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14060
14061 primary->update_plane = i9xx_update_primary_plane;
14062 primary->disable_plane = i9xx_disable_primary_plane;
14063 }
14064
14065 ret = drm_universal_plane_init(dev, &primary->base, 0,
14066 &intel_plane_funcs,
14067 intel_primary_formats, num_formats,
14068 DRM_PLANE_TYPE_PRIMARY, NULL);
14069 if (ret)
14070 goto fail;
14071
14072 if (INTEL_INFO(dev)->gen >= 4)
14073 intel_create_rotation_property(dev, primary);
14074
14075 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14076
14077 return &primary->base;
14078
14079 fail:
14080 kfree(state);
14081 kfree(primary);
14082
14083 return NULL;
14084 }
14085
14086 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14087 {
14088 if (!dev->mode_config.rotation_property) {
14089 unsigned long flags = BIT(DRM_ROTATE_0) |
14090 BIT(DRM_ROTATE_180);
14091
14092 if (INTEL_INFO(dev)->gen >= 9)
14093 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14094
14095 dev->mode_config.rotation_property =
14096 drm_mode_create_rotation_property(dev, flags);
14097 }
14098 if (dev->mode_config.rotation_property)
14099 drm_object_attach_property(&plane->base.base,
14100 dev->mode_config.rotation_property,
14101 plane->base.state->rotation);
14102 }
14103
14104 static int
14105 intel_check_cursor_plane(struct drm_plane *plane,
14106 struct intel_crtc_state *crtc_state,
14107 struct intel_plane_state *state)
14108 {
14109 struct drm_crtc *crtc = crtc_state->base.crtc;
14110 struct drm_framebuffer *fb = state->base.fb;
14111 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14112 enum pipe pipe = to_intel_plane(plane)->pipe;
14113 unsigned stride;
14114 int ret;
14115
14116 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14117 &state->dst, &state->clip,
14118 DRM_PLANE_HELPER_NO_SCALING,
14119 DRM_PLANE_HELPER_NO_SCALING,
14120 true, true, &state->visible);
14121 if (ret)
14122 return ret;
14123
14124 /* if we want to turn off the cursor ignore width and height */
14125 if (!obj)
14126 return 0;
14127
14128 /* Check for which cursor types we support */
14129 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14130 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14131 state->base.crtc_w, state->base.crtc_h);
14132 return -EINVAL;
14133 }
14134
14135 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14136 if (obj->base.size < stride * state->base.crtc_h) {
14137 DRM_DEBUG_KMS("buffer is too small\n");
14138 return -ENOMEM;
14139 }
14140
14141 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14142 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14143 return -EINVAL;
14144 }
14145
14146 /*
14147 * There's something wrong with the cursor on CHV pipe C.
14148 * If it straddles the left edge of the screen then
14149 * moving it away from the edge or disabling it often
14150 * results in a pipe underrun, and often that can lead to
14151 * dead pipe (constant underrun reported, and it scans
14152 * out just a solid color). To recover from that, the
14153 * display power well must be turned off and on again.
14154 * Refuse the put the cursor into that compromised position.
14155 */
14156 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14157 state->visible && state->base.crtc_x < 0) {
14158 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14159 return -EINVAL;
14160 }
14161
14162 return 0;
14163 }
14164
14165 static void
14166 intel_disable_cursor_plane(struct drm_plane *plane,
14167 struct drm_crtc *crtc)
14168 {
14169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14170
14171 intel_crtc->cursor_addr = 0;
14172 intel_crtc_update_cursor(crtc, NULL);
14173 }
14174
14175 static void
14176 intel_update_cursor_plane(struct drm_plane *plane,
14177 const struct intel_crtc_state *crtc_state,
14178 const struct intel_plane_state *state)
14179 {
14180 struct drm_crtc *crtc = crtc_state->base.crtc;
14181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14182 struct drm_device *dev = plane->dev;
14183 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14184 uint32_t addr;
14185
14186 if (!obj)
14187 addr = 0;
14188 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14189 addr = i915_gem_obj_ggtt_offset(obj);
14190 else
14191 addr = obj->phys_handle->busaddr;
14192
14193 intel_crtc->cursor_addr = addr;
14194 intel_crtc_update_cursor(crtc, state);
14195 }
14196
14197 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14198 int pipe)
14199 {
14200 struct intel_plane *cursor = NULL;
14201 struct intel_plane_state *state = NULL;
14202 int ret;
14203
14204 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14205 if (!cursor)
14206 goto fail;
14207
14208 state = intel_create_plane_state(&cursor->base);
14209 if (!state)
14210 goto fail;
14211 cursor->base.state = &state->base;
14212
14213 cursor->can_scale = false;
14214 cursor->max_downscale = 1;
14215 cursor->pipe = pipe;
14216 cursor->plane = pipe;
14217 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14218 cursor->check_plane = intel_check_cursor_plane;
14219 cursor->update_plane = intel_update_cursor_plane;
14220 cursor->disable_plane = intel_disable_cursor_plane;
14221
14222 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14223 &intel_plane_funcs,
14224 intel_cursor_formats,
14225 ARRAY_SIZE(intel_cursor_formats),
14226 DRM_PLANE_TYPE_CURSOR, NULL);
14227 if (ret)
14228 goto fail;
14229
14230 if (INTEL_INFO(dev)->gen >= 4) {
14231 if (!dev->mode_config.rotation_property)
14232 dev->mode_config.rotation_property =
14233 drm_mode_create_rotation_property(dev,
14234 BIT(DRM_ROTATE_0) |
14235 BIT(DRM_ROTATE_180));
14236 if (dev->mode_config.rotation_property)
14237 drm_object_attach_property(&cursor->base.base,
14238 dev->mode_config.rotation_property,
14239 state->base.rotation);
14240 }
14241
14242 if (INTEL_INFO(dev)->gen >=9)
14243 state->scaler_id = -1;
14244
14245 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14246
14247 return &cursor->base;
14248
14249 fail:
14250 kfree(state);
14251 kfree(cursor);
14252
14253 return NULL;
14254 }
14255
14256 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14257 struct intel_crtc_state *crtc_state)
14258 {
14259 int i;
14260 struct intel_scaler *intel_scaler;
14261 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14262
14263 for (i = 0; i < intel_crtc->num_scalers; i++) {
14264 intel_scaler = &scaler_state->scalers[i];
14265 intel_scaler->in_use = 0;
14266 intel_scaler->mode = PS_SCALER_MODE_DYN;
14267 }
14268
14269 scaler_state->scaler_id = -1;
14270 }
14271
14272 static void intel_crtc_init(struct drm_device *dev, int pipe)
14273 {
14274 struct drm_i915_private *dev_priv = dev->dev_private;
14275 struct intel_crtc *intel_crtc;
14276 struct intel_crtc_state *crtc_state = NULL;
14277 struct drm_plane *primary = NULL;
14278 struct drm_plane *cursor = NULL;
14279 int ret;
14280
14281 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14282 if (intel_crtc == NULL)
14283 return;
14284
14285 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14286 if (!crtc_state)
14287 goto fail;
14288 intel_crtc->config = crtc_state;
14289 intel_crtc->base.state = &crtc_state->base;
14290 crtc_state->base.crtc = &intel_crtc->base;
14291
14292 /* initialize shared scalers */
14293 if (INTEL_INFO(dev)->gen >= 9) {
14294 if (pipe == PIPE_C)
14295 intel_crtc->num_scalers = 1;
14296 else
14297 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14298
14299 skl_init_scalers(dev, intel_crtc, crtc_state);
14300 }
14301
14302 primary = intel_primary_plane_create(dev, pipe);
14303 if (!primary)
14304 goto fail;
14305
14306 cursor = intel_cursor_plane_create(dev, pipe);
14307 if (!cursor)
14308 goto fail;
14309
14310 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14311 cursor, &intel_crtc_funcs, NULL);
14312 if (ret)
14313 goto fail;
14314
14315 /*
14316 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14317 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14318 */
14319 intel_crtc->pipe = pipe;
14320 intel_crtc->plane = pipe;
14321 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14322 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14323 intel_crtc->plane = !pipe;
14324 }
14325
14326 intel_crtc->cursor_base = ~0;
14327 intel_crtc->cursor_cntl = ~0;
14328 intel_crtc->cursor_size = ~0;
14329
14330 intel_crtc->wm.cxsr_allowed = true;
14331
14332 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14333 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14334 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14335 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14336
14337 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14338
14339 intel_color_init(&intel_crtc->base);
14340
14341 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14342 return;
14343
14344 fail:
14345 if (primary)
14346 drm_plane_cleanup(primary);
14347 if (cursor)
14348 drm_plane_cleanup(cursor);
14349 kfree(crtc_state);
14350 kfree(intel_crtc);
14351 }
14352
14353 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14354 {
14355 struct drm_encoder *encoder = connector->base.encoder;
14356 struct drm_device *dev = connector->base.dev;
14357
14358 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14359
14360 if (!encoder || WARN_ON(!encoder->crtc))
14361 return INVALID_PIPE;
14362
14363 return to_intel_crtc(encoder->crtc)->pipe;
14364 }
14365
14366 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14367 struct drm_file *file)
14368 {
14369 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14370 struct drm_crtc *drmmode_crtc;
14371 struct intel_crtc *crtc;
14372
14373 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14374
14375 if (!drmmode_crtc) {
14376 DRM_ERROR("no such CRTC id\n");
14377 return -ENOENT;
14378 }
14379
14380 crtc = to_intel_crtc(drmmode_crtc);
14381 pipe_from_crtc_id->pipe = crtc->pipe;
14382
14383 return 0;
14384 }
14385
14386 static int intel_encoder_clones(struct intel_encoder *encoder)
14387 {
14388 struct drm_device *dev = encoder->base.dev;
14389 struct intel_encoder *source_encoder;
14390 int index_mask = 0;
14391 int entry = 0;
14392
14393 for_each_intel_encoder(dev, source_encoder) {
14394 if (encoders_cloneable(encoder, source_encoder))
14395 index_mask |= (1 << entry);
14396
14397 entry++;
14398 }
14399
14400 return index_mask;
14401 }
14402
14403 static bool has_edp_a(struct drm_device *dev)
14404 {
14405 struct drm_i915_private *dev_priv = dev->dev_private;
14406
14407 if (!IS_MOBILE(dev))
14408 return false;
14409
14410 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14411 return false;
14412
14413 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14414 return false;
14415
14416 return true;
14417 }
14418
14419 static bool intel_crt_present(struct drm_device *dev)
14420 {
14421 struct drm_i915_private *dev_priv = dev->dev_private;
14422
14423 if (INTEL_INFO(dev)->gen >= 9)
14424 return false;
14425
14426 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14427 return false;
14428
14429 if (IS_CHERRYVIEW(dev))
14430 return false;
14431
14432 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14433 return false;
14434
14435 /* DDI E can't be used if DDI A requires 4 lanes */
14436 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14437 return false;
14438
14439 if (!dev_priv->vbt.int_crt_support)
14440 return false;
14441
14442 return true;
14443 }
14444
14445 static void intel_setup_outputs(struct drm_device *dev)
14446 {
14447 struct drm_i915_private *dev_priv = dev->dev_private;
14448 struct intel_encoder *encoder;
14449 bool dpd_is_edp = false;
14450
14451 intel_lvds_init(dev);
14452
14453 if (intel_crt_present(dev))
14454 intel_crt_init(dev);
14455
14456 if (IS_BROXTON(dev)) {
14457 /*
14458 * FIXME: Broxton doesn't support port detection via the
14459 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14460 * detect the ports.
14461 */
14462 intel_ddi_init(dev, PORT_A);
14463 intel_ddi_init(dev, PORT_B);
14464 intel_ddi_init(dev, PORT_C);
14465
14466 intel_dsi_init(dev);
14467 } else if (HAS_DDI(dev)) {
14468 int found;
14469
14470 /*
14471 * Haswell uses DDI functions to detect digital outputs.
14472 * On SKL pre-D0 the strap isn't connected, so we assume
14473 * it's there.
14474 */
14475 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14476 /* WaIgnoreDDIAStrap: skl */
14477 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14478 intel_ddi_init(dev, PORT_A);
14479
14480 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14481 * register */
14482 found = I915_READ(SFUSE_STRAP);
14483
14484 if (found & SFUSE_STRAP_DDIB_DETECTED)
14485 intel_ddi_init(dev, PORT_B);
14486 if (found & SFUSE_STRAP_DDIC_DETECTED)
14487 intel_ddi_init(dev, PORT_C);
14488 if (found & SFUSE_STRAP_DDID_DETECTED)
14489 intel_ddi_init(dev, PORT_D);
14490 /*
14491 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14492 */
14493 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14494 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14495 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14496 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14497 intel_ddi_init(dev, PORT_E);
14498
14499 } else if (HAS_PCH_SPLIT(dev)) {
14500 int found;
14501 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14502
14503 if (has_edp_a(dev))
14504 intel_dp_init(dev, DP_A, PORT_A);
14505
14506 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14507 /* PCH SDVOB multiplex with HDMIB */
14508 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14509 if (!found)
14510 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14511 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14512 intel_dp_init(dev, PCH_DP_B, PORT_B);
14513 }
14514
14515 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14516 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14517
14518 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14519 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14520
14521 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14522 intel_dp_init(dev, PCH_DP_C, PORT_C);
14523
14524 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14525 intel_dp_init(dev, PCH_DP_D, PORT_D);
14526 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14527 /*
14528 * The DP_DETECTED bit is the latched state of the DDC
14529 * SDA pin at boot. However since eDP doesn't require DDC
14530 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14531 * eDP ports may have been muxed to an alternate function.
14532 * Thus we can't rely on the DP_DETECTED bit alone to detect
14533 * eDP ports. Consult the VBT as well as DP_DETECTED to
14534 * detect eDP ports.
14535 */
14536 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14537 !intel_dp_is_edp(dev, PORT_B))
14538 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14539 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14540 intel_dp_is_edp(dev, PORT_B))
14541 intel_dp_init(dev, VLV_DP_B, PORT_B);
14542
14543 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14544 !intel_dp_is_edp(dev, PORT_C))
14545 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14546 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14547 intel_dp_is_edp(dev, PORT_C))
14548 intel_dp_init(dev, VLV_DP_C, PORT_C);
14549
14550 if (IS_CHERRYVIEW(dev)) {
14551 /* eDP not supported on port D, so don't check VBT */
14552 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14553 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14554 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14555 intel_dp_init(dev, CHV_DP_D, PORT_D);
14556 }
14557
14558 intel_dsi_init(dev);
14559 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14560 bool found = false;
14561
14562 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14563 DRM_DEBUG_KMS("probing SDVOB\n");
14564 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14565 if (!found && IS_G4X(dev)) {
14566 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14567 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14568 }
14569
14570 if (!found && IS_G4X(dev))
14571 intel_dp_init(dev, DP_B, PORT_B);
14572 }
14573
14574 /* Before G4X SDVOC doesn't have its own detect register */
14575
14576 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14577 DRM_DEBUG_KMS("probing SDVOC\n");
14578 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14579 }
14580
14581 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14582
14583 if (IS_G4X(dev)) {
14584 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14585 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14586 }
14587 if (IS_G4X(dev))
14588 intel_dp_init(dev, DP_C, PORT_C);
14589 }
14590
14591 if (IS_G4X(dev) &&
14592 (I915_READ(DP_D) & DP_DETECTED))
14593 intel_dp_init(dev, DP_D, PORT_D);
14594 } else if (IS_GEN2(dev))
14595 intel_dvo_init(dev);
14596
14597 if (SUPPORTS_TV(dev))
14598 intel_tv_init(dev);
14599
14600 intel_psr_init(dev);
14601
14602 for_each_intel_encoder(dev, encoder) {
14603 encoder->base.possible_crtcs = encoder->crtc_mask;
14604 encoder->base.possible_clones =
14605 intel_encoder_clones(encoder);
14606 }
14607
14608 intel_init_pch_refclk(dev);
14609
14610 drm_helper_move_panel_connectors_to_head(dev);
14611 }
14612
14613 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14614 {
14615 struct drm_device *dev = fb->dev;
14616 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14617
14618 drm_framebuffer_cleanup(fb);
14619 mutex_lock(&dev->struct_mutex);
14620 WARN_ON(!intel_fb->obj->framebuffer_references--);
14621 drm_gem_object_unreference(&intel_fb->obj->base);
14622 mutex_unlock(&dev->struct_mutex);
14623 kfree(intel_fb);
14624 }
14625
14626 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14627 struct drm_file *file,
14628 unsigned int *handle)
14629 {
14630 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14631 struct drm_i915_gem_object *obj = intel_fb->obj;
14632
14633 if (obj->userptr.mm) {
14634 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14635 return -EINVAL;
14636 }
14637
14638 return drm_gem_handle_create(file, &obj->base, handle);
14639 }
14640
14641 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14642 struct drm_file *file,
14643 unsigned flags, unsigned color,
14644 struct drm_clip_rect *clips,
14645 unsigned num_clips)
14646 {
14647 struct drm_device *dev = fb->dev;
14648 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14649 struct drm_i915_gem_object *obj = intel_fb->obj;
14650
14651 mutex_lock(&dev->struct_mutex);
14652 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14653 mutex_unlock(&dev->struct_mutex);
14654
14655 return 0;
14656 }
14657
14658 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14659 .destroy = intel_user_framebuffer_destroy,
14660 .create_handle = intel_user_framebuffer_create_handle,
14661 .dirty = intel_user_framebuffer_dirty,
14662 };
14663
14664 static
14665 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14666 uint32_t pixel_format)
14667 {
14668 u32 gen = INTEL_INFO(dev)->gen;
14669
14670 if (gen >= 9) {
14671 int cpp = drm_format_plane_cpp(pixel_format, 0);
14672
14673 /* "The stride in bytes must not exceed the of the size of 8K
14674 * pixels and 32K bytes."
14675 */
14676 return min(8192 * cpp, 32768);
14677 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14678 return 32*1024;
14679 } else if (gen >= 4) {
14680 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14681 return 16*1024;
14682 else
14683 return 32*1024;
14684 } else if (gen >= 3) {
14685 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14686 return 8*1024;
14687 else
14688 return 16*1024;
14689 } else {
14690 /* XXX DSPC is limited to 4k tiled */
14691 return 8*1024;
14692 }
14693 }
14694
14695 static int intel_framebuffer_init(struct drm_device *dev,
14696 struct intel_framebuffer *intel_fb,
14697 struct drm_mode_fb_cmd2 *mode_cmd,
14698 struct drm_i915_gem_object *obj)
14699 {
14700 struct drm_i915_private *dev_priv = to_i915(dev);
14701 unsigned int aligned_height;
14702 int ret;
14703 u32 pitch_limit, stride_alignment;
14704
14705 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14706
14707 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14708 /* Enforce that fb modifier and tiling mode match, but only for
14709 * X-tiled. This is needed for FBC. */
14710 if (!!(obj->tiling_mode == I915_TILING_X) !=
14711 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14712 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14713 return -EINVAL;
14714 }
14715 } else {
14716 if (obj->tiling_mode == I915_TILING_X)
14717 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14718 else if (obj->tiling_mode == I915_TILING_Y) {
14719 DRM_DEBUG("No Y tiling for legacy addfb\n");
14720 return -EINVAL;
14721 }
14722 }
14723
14724 /* Passed in modifier sanity checking. */
14725 switch (mode_cmd->modifier[0]) {
14726 case I915_FORMAT_MOD_Y_TILED:
14727 case I915_FORMAT_MOD_Yf_TILED:
14728 if (INTEL_INFO(dev)->gen < 9) {
14729 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14730 mode_cmd->modifier[0]);
14731 return -EINVAL;
14732 }
14733 case DRM_FORMAT_MOD_NONE:
14734 case I915_FORMAT_MOD_X_TILED:
14735 break;
14736 default:
14737 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14738 mode_cmd->modifier[0]);
14739 return -EINVAL;
14740 }
14741
14742 stride_alignment = intel_fb_stride_alignment(dev_priv,
14743 mode_cmd->modifier[0],
14744 mode_cmd->pixel_format);
14745 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14746 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14747 mode_cmd->pitches[0], stride_alignment);
14748 return -EINVAL;
14749 }
14750
14751 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14752 mode_cmd->pixel_format);
14753 if (mode_cmd->pitches[0] > pitch_limit) {
14754 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14755 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14756 "tiled" : "linear",
14757 mode_cmd->pitches[0], pitch_limit);
14758 return -EINVAL;
14759 }
14760
14761 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14762 mode_cmd->pitches[0] != obj->stride) {
14763 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14764 mode_cmd->pitches[0], obj->stride);
14765 return -EINVAL;
14766 }
14767
14768 /* Reject formats not supported by any plane early. */
14769 switch (mode_cmd->pixel_format) {
14770 case DRM_FORMAT_C8:
14771 case DRM_FORMAT_RGB565:
14772 case DRM_FORMAT_XRGB8888:
14773 case DRM_FORMAT_ARGB8888:
14774 break;
14775 case DRM_FORMAT_XRGB1555:
14776 if (INTEL_INFO(dev)->gen > 3) {
14777 DRM_DEBUG("unsupported pixel format: %s\n",
14778 drm_get_format_name(mode_cmd->pixel_format));
14779 return -EINVAL;
14780 }
14781 break;
14782 case DRM_FORMAT_ABGR8888:
14783 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14784 INTEL_INFO(dev)->gen < 9) {
14785 DRM_DEBUG("unsupported pixel format: %s\n",
14786 drm_get_format_name(mode_cmd->pixel_format));
14787 return -EINVAL;
14788 }
14789 break;
14790 case DRM_FORMAT_XBGR8888:
14791 case DRM_FORMAT_XRGB2101010:
14792 case DRM_FORMAT_XBGR2101010:
14793 if (INTEL_INFO(dev)->gen < 4) {
14794 DRM_DEBUG("unsupported pixel format: %s\n",
14795 drm_get_format_name(mode_cmd->pixel_format));
14796 return -EINVAL;
14797 }
14798 break;
14799 case DRM_FORMAT_ABGR2101010:
14800 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14801 DRM_DEBUG("unsupported pixel format: %s\n",
14802 drm_get_format_name(mode_cmd->pixel_format));
14803 return -EINVAL;
14804 }
14805 break;
14806 case DRM_FORMAT_YUYV:
14807 case DRM_FORMAT_UYVY:
14808 case DRM_FORMAT_YVYU:
14809 case DRM_FORMAT_VYUY:
14810 if (INTEL_INFO(dev)->gen < 5) {
14811 DRM_DEBUG("unsupported pixel format: %s\n",
14812 drm_get_format_name(mode_cmd->pixel_format));
14813 return -EINVAL;
14814 }
14815 break;
14816 default:
14817 DRM_DEBUG("unsupported pixel format: %s\n",
14818 drm_get_format_name(mode_cmd->pixel_format));
14819 return -EINVAL;
14820 }
14821
14822 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14823 if (mode_cmd->offsets[0] != 0)
14824 return -EINVAL;
14825
14826 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14827 mode_cmd->pixel_format,
14828 mode_cmd->modifier[0]);
14829 /* FIXME drm helper for size checks (especially planar formats)? */
14830 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14831 return -EINVAL;
14832
14833 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14834 intel_fb->obj = obj;
14835
14836 intel_fill_fb_info(dev_priv, &intel_fb->base);
14837
14838 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14839 if (ret) {
14840 DRM_ERROR("framebuffer init failed %d\n", ret);
14841 return ret;
14842 }
14843
14844 intel_fb->obj->framebuffer_references++;
14845
14846 return 0;
14847 }
14848
14849 static struct drm_framebuffer *
14850 intel_user_framebuffer_create(struct drm_device *dev,
14851 struct drm_file *filp,
14852 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14853 {
14854 struct drm_framebuffer *fb;
14855 struct drm_i915_gem_object *obj;
14856 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14857
14858 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14859 mode_cmd.handles[0]));
14860 if (&obj->base == NULL)
14861 return ERR_PTR(-ENOENT);
14862
14863 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14864 if (IS_ERR(fb))
14865 drm_gem_object_unreference_unlocked(&obj->base);
14866
14867 return fb;
14868 }
14869
14870 #ifndef CONFIG_DRM_FBDEV_EMULATION
14871 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14872 {
14873 }
14874 #endif
14875
14876 static const struct drm_mode_config_funcs intel_mode_funcs = {
14877 .fb_create = intel_user_framebuffer_create,
14878 .output_poll_changed = intel_fbdev_output_poll_changed,
14879 .atomic_check = intel_atomic_check,
14880 .atomic_commit = intel_atomic_commit,
14881 .atomic_state_alloc = intel_atomic_state_alloc,
14882 .atomic_state_clear = intel_atomic_state_clear,
14883 };
14884
14885 /**
14886 * intel_init_display_hooks - initialize the display modesetting hooks
14887 * @dev_priv: device private
14888 */
14889 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14890 {
14891 if (INTEL_INFO(dev_priv)->gen >= 9) {
14892 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14893 dev_priv->display.get_initial_plane_config =
14894 skylake_get_initial_plane_config;
14895 dev_priv->display.crtc_compute_clock =
14896 haswell_crtc_compute_clock;
14897 dev_priv->display.crtc_enable = haswell_crtc_enable;
14898 dev_priv->display.crtc_disable = haswell_crtc_disable;
14899 } else if (HAS_DDI(dev_priv)) {
14900 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14901 dev_priv->display.get_initial_plane_config =
14902 ironlake_get_initial_plane_config;
14903 dev_priv->display.crtc_compute_clock =
14904 haswell_crtc_compute_clock;
14905 dev_priv->display.crtc_enable = haswell_crtc_enable;
14906 dev_priv->display.crtc_disable = haswell_crtc_disable;
14907 } else if (HAS_PCH_SPLIT(dev_priv)) {
14908 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14909 dev_priv->display.get_initial_plane_config =
14910 ironlake_get_initial_plane_config;
14911 dev_priv->display.crtc_compute_clock =
14912 ironlake_crtc_compute_clock;
14913 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14914 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14915 } else if (IS_CHERRYVIEW(dev_priv)) {
14916 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14917 dev_priv->display.get_initial_plane_config =
14918 i9xx_get_initial_plane_config;
14919 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14920 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14921 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14922 } else if (IS_VALLEYVIEW(dev_priv)) {
14923 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14924 dev_priv->display.get_initial_plane_config =
14925 i9xx_get_initial_plane_config;
14926 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14927 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14928 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14929 } else if (IS_G4X(dev_priv)) {
14930 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14931 dev_priv->display.get_initial_plane_config =
14932 i9xx_get_initial_plane_config;
14933 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14934 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14935 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14936 } else if (IS_PINEVIEW(dev_priv)) {
14937 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14938 dev_priv->display.get_initial_plane_config =
14939 i9xx_get_initial_plane_config;
14940 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14941 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14942 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14943 } else if (!IS_GEN2(dev_priv)) {
14944 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14945 dev_priv->display.get_initial_plane_config =
14946 i9xx_get_initial_plane_config;
14947 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14948 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14949 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14950 } else {
14951 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14952 dev_priv->display.get_initial_plane_config =
14953 i9xx_get_initial_plane_config;
14954 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14955 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14956 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14957 }
14958
14959 /* Returns the core display clock speed */
14960 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14961 dev_priv->display.get_display_clock_speed =
14962 skylake_get_display_clock_speed;
14963 else if (IS_BROXTON(dev_priv))
14964 dev_priv->display.get_display_clock_speed =
14965 broxton_get_display_clock_speed;
14966 else if (IS_BROADWELL(dev_priv))
14967 dev_priv->display.get_display_clock_speed =
14968 broadwell_get_display_clock_speed;
14969 else if (IS_HASWELL(dev_priv))
14970 dev_priv->display.get_display_clock_speed =
14971 haswell_get_display_clock_speed;
14972 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14973 dev_priv->display.get_display_clock_speed =
14974 valleyview_get_display_clock_speed;
14975 else if (IS_GEN5(dev_priv))
14976 dev_priv->display.get_display_clock_speed =
14977 ilk_get_display_clock_speed;
14978 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14979 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14980 dev_priv->display.get_display_clock_speed =
14981 i945_get_display_clock_speed;
14982 else if (IS_GM45(dev_priv))
14983 dev_priv->display.get_display_clock_speed =
14984 gm45_get_display_clock_speed;
14985 else if (IS_CRESTLINE(dev_priv))
14986 dev_priv->display.get_display_clock_speed =
14987 i965gm_get_display_clock_speed;
14988 else if (IS_PINEVIEW(dev_priv))
14989 dev_priv->display.get_display_clock_speed =
14990 pnv_get_display_clock_speed;
14991 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14992 dev_priv->display.get_display_clock_speed =
14993 g33_get_display_clock_speed;
14994 else if (IS_I915G(dev_priv))
14995 dev_priv->display.get_display_clock_speed =
14996 i915_get_display_clock_speed;
14997 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14998 dev_priv->display.get_display_clock_speed =
14999 i9xx_misc_get_display_clock_speed;
15000 else if (IS_I915GM(dev_priv))
15001 dev_priv->display.get_display_clock_speed =
15002 i915gm_get_display_clock_speed;
15003 else if (IS_I865G(dev_priv))
15004 dev_priv->display.get_display_clock_speed =
15005 i865_get_display_clock_speed;
15006 else if (IS_I85X(dev_priv))
15007 dev_priv->display.get_display_clock_speed =
15008 i85x_get_display_clock_speed;
15009 else { /* 830 */
15010 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15011 dev_priv->display.get_display_clock_speed =
15012 i830_get_display_clock_speed;
15013 }
15014
15015 if (IS_GEN5(dev_priv)) {
15016 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15017 } else if (IS_GEN6(dev_priv)) {
15018 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15019 } else if (IS_IVYBRIDGE(dev_priv)) {
15020 /* FIXME: detect B0+ stepping and use auto training */
15021 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15022 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15023 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15024 }
15025
15026 if (IS_BROADWELL(dev_priv)) {
15027 dev_priv->display.modeset_commit_cdclk =
15028 broadwell_modeset_commit_cdclk;
15029 dev_priv->display.modeset_calc_cdclk =
15030 broadwell_modeset_calc_cdclk;
15031 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15032 dev_priv->display.modeset_commit_cdclk =
15033 valleyview_modeset_commit_cdclk;
15034 dev_priv->display.modeset_calc_cdclk =
15035 valleyview_modeset_calc_cdclk;
15036 } else if (IS_BROXTON(dev_priv)) {
15037 dev_priv->display.modeset_commit_cdclk =
15038 broxton_modeset_commit_cdclk;
15039 dev_priv->display.modeset_calc_cdclk =
15040 broxton_modeset_calc_cdclk;
15041 }
15042
15043 switch (INTEL_INFO(dev_priv)->gen) {
15044 case 2:
15045 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15046 break;
15047
15048 case 3:
15049 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15050 break;
15051
15052 case 4:
15053 case 5:
15054 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15055 break;
15056
15057 case 6:
15058 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15059 break;
15060 case 7:
15061 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15062 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15063 break;
15064 case 9:
15065 /* Drop through - unsupported since execlist only. */
15066 default:
15067 /* Default just returns -ENODEV to indicate unsupported */
15068 dev_priv->display.queue_flip = intel_default_queue_flip;
15069 }
15070 }
15071
15072 /*
15073 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15074 * resume, or other times. This quirk makes sure that's the case for
15075 * affected systems.
15076 */
15077 static void quirk_pipea_force(struct drm_device *dev)
15078 {
15079 struct drm_i915_private *dev_priv = dev->dev_private;
15080
15081 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15082 DRM_INFO("applying pipe a force quirk\n");
15083 }
15084
15085 static void quirk_pipeb_force(struct drm_device *dev)
15086 {
15087 struct drm_i915_private *dev_priv = dev->dev_private;
15088
15089 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15090 DRM_INFO("applying pipe b force quirk\n");
15091 }
15092
15093 /*
15094 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15095 */
15096 static void quirk_ssc_force_disable(struct drm_device *dev)
15097 {
15098 struct drm_i915_private *dev_priv = dev->dev_private;
15099 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15100 DRM_INFO("applying lvds SSC disable quirk\n");
15101 }
15102
15103 /*
15104 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15105 * brightness value
15106 */
15107 static void quirk_invert_brightness(struct drm_device *dev)
15108 {
15109 struct drm_i915_private *dev_priv = dev->dev_private;
15110 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15111 DRM_INFO("applying inverted panel brightness quirk\n");
15112 }
15113
15114 /* Some VBT's incorrectly indicate no backlight is present */
15115 static void quirk_backlight_present(struct drm_device *dev)
15116 {
15117 struct drm_i915_private *dev_priv = dev->dev_private;
15118 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15119 DRM_INFO("applying backlight present quirk\n");
15120 }
15121
15122 struct intel_quirk {
15123 int device;
15124 int subsystem_vendor;
15125 int subsystem_device;
15126 void (*hook)(struct drm_device *dev);
15127 };
15128
15129 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15130 struct intel_dmi_quirk {
15131 void (*hook)(struct drm_device *dev);
15132 const struct dmi_system_id (*dmi_id_list)[];
15133 };
15134
15135 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15136 {
15137 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15138 return 1;
15139 }
15140
15141 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15142 {
15143 .dmi_id_list = &(const struct dmi_system_id[]) {
15144 {
15145 .callback = intel_dmi_reverse_brightness,
15146 .ident = "NCR Corporation",
15147 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15148 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15149 },
15150 },
15151 { } /* terminating entry */
15152 },
15153 .hook = quirk_invert_brightness,
15154 },
15155 };
15156
15157 static struct intel_quirk intel_quirks[] = {
15158 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15159 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15160
15161 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15162 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15163
15164 /* 830 needs to leave pipe A & dpll A up */
15165 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15166
15167 /* 830 needs to leave pipe B & dpll B up */
15168 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15169
15170 /* Lenovo U160 cannot use SSC on LVDS */
15171 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15172
15173 /* Sony Vaio Y cannot use SSC on LVDS */
15174 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15175
15176 /* Acer Aspire 5734Z must invert backlight brightness */
15177 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15178
15179 /* Acer/eMachines G725 */
15180 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15181
15182 /* Acer/eMachines e725 */
15183 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15184
15185 /* Acer/Packard Bell NCL20 */
15186 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15187
15188 /* Acer Aspire 4736Z */
15189 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15190
15191 /* Acer Aspire 5336 */
15192 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15193
15194 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15195 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15196
15197 /* Acer C720 Chromebook (Core i3 4005U) */
15198 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15199
15200 /* Apple Macbook 2,1 (Core 2 T7400) */
15201 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15202
15203 /* Apple Macbook 4,1 */
15204 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15205
15206 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15207 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15208
15209 /* HP Chromebook 14 (Celeron 2955U) */
15210 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15211
15212 /* Dell Chromebook 11 */
15213 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15214
15215 /* Dell Chromebook 11 (2015 version) */
15216 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15217 };
15218
15219 static void intel_init_quirks(struct drm_device *dev)
15220 {
15221 struct pci_dev *d = dev->pdev;
15222 int i;
15223
15224 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15225 struct intel_quirk *q = &intel_quirks[i];
15226
15227 if (d->device == q->device &&
15228 (d->subsystem_vendor == q->subsystem_vendor ||
15229 q->subsystem_vendor == PCI_ANY_ID) &&
15230 (d->subsystem_device == q->subsystem_device ||
15231 q->subsystem_device == PCI_ANY_ID))
15232 q->hook(dev);
15233 }
15234 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15235 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15236 intel_dmi_quirks[i].hook(dev);
15237 }
15238 }
15239
15240 /* Disable the VGA plane that we never use */
15241 static void i915_disable_vga(struct drm_device *dev)
15242 {
15243 struct drm_i915_private *dev_priv = dev->dev_private;
15244 u8 sr1;
15245 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15246
15247 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15248 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15249 outb(SR01, VGA_SR_INDEX);
15250 sr1 = inb(VGA_SR_DATA);
15251 outb(sr1 | 1<<5, VGA_SR_DATA);
15252 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15253 udelay(300);
15254
15255 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15256 POSTING_READ(vga_reg);
15257 }
15258
15259 void intel_modeset_init_hw(struct drm_device *dev)
15260 {
15261 struct drm_i915_private *dev_priv = dev->dev_private;
15262
15263 intel_update_cdclk(dev);
15264
15265 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15266
15267 intel_init_clock_gating(dev);
15268 intel_enable_gt_powersave(dev_priv);
15269 }
15270
15271 /*
15272 * Calculate what we think the watermarks should be for the state we've read
15273 * out of the hardware and then immediately program those watermarks so that
15274 * we ensure the hardware settings match our internal state.
15275 *
15276 * We can calculate what we think WM's should be by creating a duplicate of the
15277 * current state (which was constructed during hardware readout) and running it
15278 * through the atomic check code to calculate new watermark values in the
15279 * state object.
15280 */
15281 static void sanitize_watermarks(struct drm_device *dev)
15282 {
15283 struct drm_i915_private *dev_priv = to_i915(dev);
15284 struct drm_atomic_state *state;
15285 struct drm_crtc *crtc;
15286 struct drm_crtc_state *cstate;
15287 struct drm_modeset_acquire_ctx ctx;
15288 int ret;
15289 int i;
15290
15291 /* Only supported on platforms that use atomic watermark design */
15292 if (!dev_priv->display.optimize_watermarks)
15293 return;
15294
15295 /*
15296 * We need to hold connection_mutex before calling duplicate_state so
15297 * that the connector loop is protected.
15298 */
15299 drm_modeset_acquire_init(&ctx, 0);
15300 retry:
15301 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15302 if (ret == -EDEADLK) {
15303 drm_modeset_backoff(&ctx);
15304 goto retry;
15305 } else if (WARN_ON(ret)) {
15306 goto fail;
15307 }
15308
15309 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15310 if (WARN_ON(IS_ERR(state)))
15311 goto fail;
15312
15313 /*
15314 * Hardware readout is the only time we don't want to calculate
15315 * intermediate watermarks (since we don't trust the current
15316 * watermarks).
15317 */
15318 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15319
15320 ret = intel_atomic_check(dev, state);
15321 if (ret) {
15322 /*
15323 * If we fail here, it means that the hardware appears to be
15324 * programmed in a way that shouldn't be possible, given our
15325 * understanding of watermark requirements. This might mean a
15326 * mistake in the hardware readout code or a mistake in the
15327 * watermark calculations for a given platform. Raise a WARN
15328 * so that this is noticeable.
15329 *
15330 * If this actually happens, we'll have to just leave the
15331 * BIOS-programmed watermarks untouched and hope for the best.
15332 */
15333 WARN(true, "Could not determine valid watermarks for inherited state\n");
15334 goto fail;
15335 }
15336
15337 /* Write calculated watermark values back */
15338 for_each_crtc_in_state(state, crtc, cstate, i) {
15339 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15340
15341 cs->wm.need_postvbl_update = true;
15342 dev_priv->display.optimize_watermarks(cs);
15343 }
15344
15345 drm_atomic_state_free(state);
15346 fail:
15347 drm_modeset_drop_locks(&ctx);
15348 drm_modeset_acquire_fini(&ctx);
15349 }
15350
15351 void intel_modeset_init(struct drm_device *dev)
15352 {
15353 struct drm_i915_private *dev_priv = to_i915(dev);
15354 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15355 int sprite, ret;
15356 enum pipe pipe;
15357 struct intel_crtc *crtc;
15358
15359 drm_mode_config_init(dev);
15360
15361 dev->mode_config.min_width = 0;
15362 dev->mode_config.min_height = 0;
15363
15364 dev->mode_config.preferred_depth = 24;
15365 dev->mode_config.prefer_shadow = 1;
15366
15367 dev->mode_config.allow_fb_modifiers = true;
15368
15369 dev->mode_config.funcs = &intel_mode_funcs;
15370
15371 intel_init_quirks(dev);
15372
15373 intel_init_pm(dev);
15374
15375 if (INTEL_INFO(dev)->num_pipes == 0)
15376 return;
15377
15378 /*
15379 * There may be no VBT; and if the BIOS enabled SSC we can
15380 * just keep using it to avoid unnecessary flicker. Whereas if the
15381 * BIOS isn't using it, don't assume it will work even if the VBT
15382 * indicates as much.
15383 */
15384 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15385 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15386 DREF_SSC1_ENABLE);
15387
15388 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15389 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15390 bios_lvds_use_ssc ? "en" : "dis",
15391 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15392 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15393 }
15394 }
15395
15396 if (IS_GEN2(dev)) {
15397 dev->mode_config.max_width = 2048;
15398 dev->mode_config.max_height = 2048;
15399 } else if (IS_GEN3(dev)) {
15400 dev->mode_config.max_width = 4096;
15401 dev->mode_config.max_height = 4096;
15402 } else {
15403 dev->mode_config.max_width = 8192;
15404 dev->mode_config.max_height = 8192;
15405 }
15406
15407 if (IS_845G(dev) || IS_I865G(dev)) {
15408 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15409 dev->mode_config.cursor_height = 1023;
15410 } else if (IS_GEN2(dev)) {
15411 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15412 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15413 } else {
15414 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15415 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15416 }
15417
15418 dev->mode_config.fb_base = ggtt->mappable_base;
15419
15420 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15421 INTEL_INFO(dev)->num_pipes,
15422 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15423
15424 for_each_pipe(dev_priv, pipe) {
15425 intel_crtc_init(dev, pipe);
15426 for_each_sprite(dev_priv, pipe, sprite) {
15427 ret = intel_plane_init(dev, pipe, sprite);
15428 if (ret)
15429 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15430 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15431 }
15432 }
15433
15434 intel_update_czclk(dev_priv);
15435 intel_update_cdclk(dev);
15436
15437 intel_shared_dpll_init(dev);
15438
15439 /* Just disable it once at startup */
15440 i915_disable_vga(dev);
15441 intel_setup_outputs(dev);
15442
15443 drm_modeset_lock_all(dev);
15444 intel_modeset_setup_hw_state(dev);
15445 drm_modeset_unlock_all(dev);
15446
15447 for_each_intel_crtc(dev, crtc) {
15448 struct intel_initial_plane_config plane_config = {};
15449
15450 if (!crtc->active)
15451 continue;
15452
15453 /*
15454 * Note that reserving the BIOS fb up front prevents us
15455 * from stuffing other stolen allocations like the ring
15456 * on top. This prevents some ugliness at boot time, and
15457 * can even allow for smooth boot transitions if the BIOS
15458 * fb is large enough for the active pipe configuration.
15459 */
15460 dev_priv->display.get_initial_plane_config(crtc,
15461 &plane_config);
15462
15463 /*
15464 * If the fb is shared between multiple heads, we'll
15465 * just get the first one.
15466 */
15467 intel_find_initial_plane_obj(crtc, &plane_config);
15468 }
15469
15470 /*
15471 * Make sure hardware watermarks really match the state we read out.
15472 * Note that we need to do this after reconstructing the BIOS fb's
15473 * since the watermark calculation done here will use pstate->fb.
15474 */
15475 sanitize_watermarks(dev);
15476 }
15477
15478 static void intel_enable_pipe_a(struct drm_device *dev)
15479 {
15480 struct intel_connector *connector;
15481 struct drm_connector *crt = NULL;
15482 struct intel_load_detect_pipe load_detect_temp;
15483 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15484
15485 /* We can't just switch on the pipe A, we need to set things up with a
15486 * proper mode and output configuration. As a gross hack, enable pipe A
15487 * by enabling the load detect pipe once. */
15488 for_each_intel_connector(dev, connector) {
15489 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15490 crt = &connector->base;
15491 break;
15492 }
15493 }
15494
15495 if (!crt)
15496 return;
15497
15498 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15499 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15500 }
15501
15502 static bool
15503 intel_check_plane_mapping(struct intel_crtc *crtc)
15504 {
15505 struct drm_device *dev = crtc->base.dev;
15506 struct drm_i915_private *dev_priv = dev->dev_private;
15507 u32 val;
15508
15509 if (INTEL_INFO(dev)->num_pipes == 1)
15510 return true;
15511
15512 val = I915_READ(DSPCNTR(!crtc->plane));
15513
15514 if ((val & DISPLAY_PLANE_ENABLE) &&
15515 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15516 return false;
15517
15518 return true;
15519 }
15520
15521 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15522 {
15523 struct drm_device *dev = crtc->base.dev;
15524 struct intel_encoder *encoder;
15525
15526 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15527 return true;
15528
15529 return false;
15530 }
15531
15532 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15533 {
15534 struct drm_device *dev = encoder->base.dev;
15535 struct intel_connector *connector;
15536
15537 for_each_connector_on_encoder(dev, &encoder->base, connector)
15538 return true;
15539
15540 return false;
15541 }
15542
15543 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15544 {
15545 struct drm_device *dev = crtc->base.dev;
15546 struct drm_i915_private *dev_priv = dev->dev_private;
15547 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15548
15549 /* Clear any frame start delays used for debugging left by the BIOS */
15550 if (!transcoder_is_dsi(cpu_transcoder)) {
15551 i915_reg_t reg = PIPECONF(cpu_transcoder);
15552
15553 I915_WRITE(reg,
15554 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15555 }
15556
15557 /* restore vblank interrupts to correct state */
15558 drm_crtc_vblank_reset(&crtc->base);
15559 if (crtc->active) {
15560 struct intel_plane *plane;
15561
15562 drm_crtc_vblank_on(&crtc->base);
15563
15564 /* Disable everything but the primary plane */
15565 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15566 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15567 continue;
15568
15569 plane->disable_plane(&plane->base, &crtc->base);
15570 }
15571 }
15572
15573 /* We need to sanitize the plane -> pipe mapping first because this will
15574 * disable the crtc (and hence change the state) if it is wrong. Note
15575 * that gen4+ has a fixed plane -> pipe mapping. */
15576 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15577 bool plane;
15578
15579 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15580 crtc->base.base.id);
15581
15582 /* Pipe has the wrong plane attached and the plane is active.
15583 * Temporarily change the plane mapping and disable everything
15584 * ... */
15585 plane = crtc->plane;
15586 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15587 crtc->plane = !plane;
15588 intel_crtc_disable_noatomic(&crtc->base);
15589 crtc->plane = plane;
15590 }
15591
15592 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15593 crtc->pipe == PIPE_A && !crtc->active) {
15594 /* BIOS forgot to enable pipe A, this mostly happens after
15595 * resume. Force-enable the pipe to fix this, the update_dpms
15596 * call below we restore the pipe to the right state, but leave
15597 * the required bits on. */
15598 intel_enable_pipe_a(dev);
15599 }
15600
15601 /* Adjust the state of the output pipe according to whether we
15602 * have active connectors/encoders. */
15603 if (crtc->active && !intel_crtc_has_encoders(crtc))
15604 intel_crtc_disable_noatomic(&crtc->base);
15605
15606 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15607 /*
15608 * We start out with underrun reporting disabled to avoid races.
15609 * For correct bookkeeping mark this on active crtcs.
15610 *
15611 * Also on gmch platforms we dont have any hardware bits to
15612 * disable the underrun reporting. Which means we need to start
15613 * out with underrun reporting disabled also on inactive pipes,
15614 * since otherwise we'll complain about the garbage we read when
15615 * e.g. coming up after runtime pm.
15616 *
15617 * No protection against concurrent access is required - at
15618 * worst a fifo underrun happens which also sets this to false.
15619 */
15620 crtc->cpu_fifo_underrun_disabled = true;
15621 crtc->pch_fifo_underrun_disabled = true;
15622 }
15623 }
15624
15625 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15626 {
15627 struct intel_connector *connector;
15628 struct drm_device *dev = encoder->base.dev;
15629
15630 /* We need to check both for a crtc link (meaning that the
15631 * encoder is active and trying to read from a pipe) and the
15632 * pipe itself being active. */
15633 bool has_active_crtc = encoder->base.crtc &&
15634 to_intel_crtc(encoder->base.crtc)->active;
15635
15636 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15637 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15638 encoder->base.base.id,
15639 encoder->base.name);
15640
15641 /* Connector is active, but has no active pipe. This is
15642 * fallout from our resume register restoring. Disable
15643 * the encoder manually again. */
15644 if (encoder->base.crtc) {
15645 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15646 encoder->base.base.id,
15647 encoder->base.name);
15648 encoder->disable(encoder);
15649 if (encoder->post_disable)
15650 encoder->post_disable(encoder);
15651 }
15652 encoder->base.crtc = NULL;
15653
15654 /* Inconsistent output/port/pipe state happens presumably due to
15655 * a bug in one of the get_hw_state functions. Or someplace else
15656 * in our code, like the register restore mess on resume. Clamp
15657 * things to off as a safer default. */
15658 for_each_intel_connector(dev, connector) {
15659 if (connector->encoder != encoder)
15660 continue;
15661 connector->base.dpms = DRM_MODE_DPMS_OFF;
15662 connector->base.encoder = NULL;
15663 }
15664 }
15665 /* Enabled encoders without active connectors will be fixed in
15666 * the crtc fixup. */
15667 }
15668
15669 void i915_redisable_vga_power_on(struct drm_device *dev)
15670 {
15671 struct drm_i915_private *dev_priv = dev->dev_private;
15672 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15673
15674 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15675 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15676 i915_disable_vga(dev);
15677 }
15678 }
15679
15680 void i915_redisable_vga(struct drm_device *dev)
15681 {
15682 struct drm_i915_private *dev_priv = dev->dev_private;
15683
15684 /* This function can be called both from intel_modeset_setup_hw_state or
15685 * at a very early point in our resume sequence, where the power well
15686 * structures are not yet restored. Since this function is at a very
15687 * paranoid "someone might have enabled VGA while we were not looking"
15688 * level, just check if the power well is enabled instead of trying to
15689 * follow the "don't touch the power well if we don't need it" policy
15690 * the rest of the driver uses. */
15691 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15692 return;
15693
15694 i915_redisable_vga_power_on(dev);
15695
15696 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15697 }
15698
15699 static bool primary_get_hw_state(struct intel_plane *plane)
15700 {
15701 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15702
15703 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15704 }
15705
15706 /* FIXME read out full plane state for all planes */
15707 static void readout_plane_state(struct intel_crtc *crtc)
15708 {
15709 struct drm_plane *primary = crtc->base.primary;
15710 struct intel_plane_state *plane_state =
15711 to_intel_plane_state(primary->state);
15712
15713 plane_state->visible = crtc->active &&
15714 primary_get_hw_state(to_intel_plane(primary));
15715
15716 if (plane_state->visible)
15717 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15718 }
15719
15720 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15721 {
15722 struct drm_i915_private *dev_priv = dev->dev_private;
15723 enum pipe pipe;
15724 struct intel_crtc *crtc;
15725 struct intel_encoder *encoder;
15726 struct intel_connector *connector;
15727 int i;
15728
15729 dev_priv->active_crtcs = 0;
15730
15731 for_each_intel_crtc(dev, crtc) {
15732 struct intel_crtc_state *crtc_state = crtc->config;
15733 int pixclk = 0;
15734
15735 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15736 memset(crtc_state, 0, sizeof(*crtc_state));
15737 crtc_state->base.crtc = &crtc->base;
15738
15739 crtc_state->base.active = crtc_state->base.enable =
15740 dev_priv->display.get_pipe_config(crtc, crtc_state);
15741
15742 crtc->base.enabled = crtc_state->base.enable;
15743 crtc->active = crtc_state->base.active;
15744
15745 if (crtc_state->base.active) {
15746 dev_priv->active_crtcs |= 1 << crtc->pipe;
15747
15748 if (IS_BROADWELL(dev_priv)) {
15749 pixclk = ilk_pipe_pixel_rate(crtc_state);
15750
15751 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15752 if (crtc_state->ips_enabled)
15753 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15754 } else if (IS_VALLEYVIEW(dev_priv) ||
15755 IS_CHERRYVIEW(dev_priv) ||
15756 IS_BROXTON(dev_priv))
15757 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15758 else
15759 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15760 }
15761
15762 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15763
15764 readout_plane_state(crtc);
15765
15766 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15767 crtc->base.base.id,
15768 crtc->active ? "enabled" : "disabled");
15769 }
15770
15771 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15772 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15773
15774 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15775 &pll->config.hw_state);
15776 pll->config.crtc_mask = 0;
15777 for_each_intel_crtc(dev, crtc) {
15778 if (crtc->active && crtc->config->shared_dpll == pll)
15779 pll->config.crtc_mask |= 1 << crtc->pipe;
15780 }
15781 pll->active_mask = pll->config.crtc_mask;
15782
15783 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15784 pll->name, pll->config.crtc_mask, pll->on);
15785 }
15786
15787 for_each_intel_encoder(dev, encoder) {
15788 pipe = 0;
15789
15790 if (encoder->get_hw_state(encoder, &pipe)) {
15791 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15792 encoder->base.crtc = &crtc->base;
15793 encoder->get_config(encoder, crtc->config);
15794 } else {
15795 encoder->base.crtc = NULL;
15796 }
15797
15798 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15799 encoder->base.base.id,
15800 encoder->base.name,
15801 encoder->base.crtc ? "enabled" : "disabled",
15802 pipe_name(pipe));
15803 }
15804
15805 for_each_intel_connector(dev, connector) {
15806 if (connector->get_hw_state(connector)) {
15807 connector->base.dpms = DRM_MODE_DPMS_ON;
15808
15809 encoder = connector->encoder;
15810 connector->base.encoder = &encoder->base;
15811
15812 if (encoder->base.crtc &&
15813 encoder->base.crtc->state->active) {
15814 /*
15815 * This has to be done during hardware readout
15816 * because anything calling .crtc_disable may
15817 * rely on the connector_mask being accurate.
15818 */
15819 encoder->base.crtc->state->connector_mask |=
15820 1 << drm_connector_index(&connector->base);
15821 encoder->base.crtc->state->encoder_mask |=
15822 1 << drm_encoder_index(&encoder->base);
15823 }
15824
15825 } else {
15826 connector->base.dpms = DRM_MODE_DPMS_OFF;
15827 connector->base.encoder = NULL;
15828 }
15829 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15830 connector->base.base.id,
15831 connector->base.name,
15832 connector->base.encoder ? "enabled" : "disabled");
15833 }
15834
15835 for_each_intel_crtc(dev, crtc) {
15836 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15837
15838 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15839 if (crtc->base.state->active) {
15840 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15841 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15842 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15843
15844 /*
15845 * The initial mode needs to be set in order to keep
15846 * the atomic core happy. It wants a valid mode if the
15847 * crtc's enabled, so we do the above call.
15848 *
15849 * At this point some state updated by the connectors
15850 * in their ->detect() callback has not run yet, so
15851 * no recalculation can be done yet.
15852 *
15853 * Even if we could do a recalculation and modeset
15854 * right now it would cause a double modeset if
15855 * fbdev or userspace chooses a different initial mode.
15856 *
15857 * If that happens, someone indicated they wanted a
15858 * mode change, which means it's safe to do a full
15859 * recalculation.
15860 */
15861 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15862
15863 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15864 update_scanline_offset(crtc);
15865 }
15866
15867 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15868 }
15869 }
15870
15871 /* Scan out the current hw modeset state,
15872 * and sanitizes it to the current state
15873 */
15874 static void
15875 intel_modeset_setup_hw_state(struct drm_device *dev)
15876 {
15877 struct drm_i915_private *dev_priv = dev->dev_private;
15878 enum pipe pipe;
15879 struct intel_crtc *crtc;
15880 struct intel_encoder *encoder;
15881 int i;
15882
15883 intel_modeset_readout_hw_state(dev);
15884
15885 /* HW state is read out, now we need to sanitize this mess. */
15886 for_each_intel_encoder(dev, encoder) {
15887 intel_sanitize_encoder(encoder);
15888 }
15889
15890 for_each_pipe(dev_priv, pipe) {
15891 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15892 intel_sanitize_crtc(crtc);
15893 intel_dump_pipe_config(crtc, crtc->config,
15894 "[setup_hw_state]");
15895 }
15896
15897 intel_modeset_update_connector_atomic_state(dev);
15898
15899 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15900 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15901
15902 if (!pll->on || pll->active_mask)
15903 continue;
15904
15905 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15906
15907 pll->funcs.disable(dev_priv, pll);
15908 pll->on = false;
15909 }
15910
15911 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15912 vlv_wm_get_hw_state(dev);
15913 else if (IS_GEN9(dev))
15914 skl_wm_get_hw_state(dev);
15915 else if (HAS_PCH_SPLIT(dev))
15916 ilk_wm_get_hw_state(dev);
15917
15918 for_each_intel_crtc(dev, crtc) {
15919 unsigned long put_domains;
15920
15921 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15922 if (WARN_ON(put_domains))
15923 modeset_put_power_domains(dev_priv, put_domains);
15924 }
15925 intel_display_set_init_power(dev_priv, false);
15926
15927 intel_fbc_init_pipe_state(dev_priv);
15928 }
15929
15930 void intel_display_resume(struct drm_device *dev)
15931 {
15932 struct drm_i915_private *dev_priv = to_i915(dev);
15933 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15934 struct drm_modeset_acquire_ctx ctx;
15935 int ret;
15936 bool setup = false;
15937
15938 dev_priv->modeset_restore_state = NULL;
15939
15940 /*
15941 * This is a cludge because with real atomic modeset mode_config.mutex
15942 * won't be taken. Unfortunately some probed state like
15943 * audio_codec_enable is still protected by mode_config.mutex, so lock
15944 * it here for now.
15945 */
15946 mutex_lock(&dev->mode_config.mutex);
15947 drm_modeset_acquire_init(&ctx, 0);
15948
15949 retry:
15950 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15951
15952 if (ret == 0 && !setup) {
15953 setup = true;
15954
15955 intel_modeset_setup_hw_state(dev);
15956 i915_redisable_vga(dev);
15957 }
15958
15959 if (ret == 0 && state) {
15960 struct drm_crtc_state *crtc_state;
15961 struct drm_crtc *crtc;
15962 int i;
15963
15964 state->acquire_ctx = &ctx;
15965
15966 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15967 /*
15968 * Force recalculation even if we restore
15969 * current state. With fast modeset this may not result
15970 * in a modeset when the state is compatible.
15971 */
15972 crtc_state->mode_changed = true;
15973 }
15974
15975 ret = drm_atomic_commit(state);
15976 }
15977
15978 if (ret == -EDEADLK) {
15979 drm_modeset_backoff(&ctx);
15980 goto retry;
15981 }
15982
15983 drm_modeset_drop_locks(&ctx);
15984 drm_modeset_acquire_fini(&ctx);
15985 mutex_unlock(&dev->mode_config.mutex);
15986
15987 if (ret) {
15988 DRM_ERROR("Restoring old state failed with %i\n", ret);
15989 drm_atomic_state_free(state);
15990 }
15991 }
15992
15993 void intel_modeset_gem_init(struct drm_device *dev)
15994 {
15995 struct drm_i915_private *dev_priv = to_i915(dev);
15996 struct drm_crtc *c;
15997 struct drm_i915_gem_object *obj;
15998 int ret;
15999
16000 intel_init_gt_powersave(dev_priv);
16001
16002 intel_modeset_init_hw(dev);
16003
16004 intel_setup_overlay(dev_priv);
16005
16006 /*
16007 * Make sure any fbs we allocated at startup are properly
16008 * pinned & fenced. When we do the allocation it's too early
16009 * for this.
16010 */
16011 for_each_crtc(dev, c) {
16012 obj = intel_fb_obj(c->primary->fb);
16013 if (obj == NULL)
16014 continue;
16015
16016 mutex_lock(&dev->struct_mutex);
16017 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16018 c->primary->state->rotation);
16019 mutex_unlock(&dev->struct_mutex);
16020 if (ret) {
16021 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16022 to_intel_crtc(c)->pipe);
16023 drm_framebuffer_unreference(c->primary->fb);
16024 c->primary->fb = NULL;
16025 c->primary->crtc = c->primary->state->crtc = NULL;
16026 update_state_fb(c->primary);
16027 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16028 }
16029 }
16030
16031 intel_backlight_register(dev);
16032 }
16033
16034 void intel_connector_unregister(struct intel_connector *intel_connector)
16035 {
16036 struct drm_connector *connector = &intel_connector->base;
16037
16038 intel_panel_destroy_backlight(connector);
16039 drm_connector_unregister(connector);
16040 }
16041
16042 void intel_modeset_cleanup(struct drm_device *dev)
16043 {
16044 struct drm_i915_private *dev_priv = dev->dev_private;
16045 struct intel_connector *connector;
16046
16047 intel_disable_gt_powersave(dev_priv);
16048
16049 intel_backlight_unregister(dev);
16050
16051 /*
16052 * Interrupts and polling as the first thing to avoid creating havoc.
16053 * Too much stuff here (turning of connectors, ...) would
16054 * experience fancy races otherwise.
16055 */
16056 intel_irq_uninstall(dev_priv);
16057
16058 /*
16059 * Due to the hpd irq storm handling the hotplug work can re-arm the
16060 * poll handlers. Hence disable polling after hpd handling is shut down.
16061 */
16062 drm_kms_helper_poll_fini(dev);
16063
16064 intel_unregister_dsm_handler();
16065
16066 intel_fbc_global_disable(dev_priv);
16067
16068 /* flush any delayed tasks or pending work */
16069 flush_scheduled_work();
16070
16071 /* destroy the backlight and sysfs files before encoders/connectors */
16072 for_each_intel_connector(dev, connector)
16073 connector->unregister(connector);
16074
16075 drm_mode_config_cleanup(dev);
16076
16077 intel_cleanup_overlay(dev_priv);
16078
16079 intel_cleanup_gt_powersave(dev_priv);
16080
16081 intel_teardown_gmbus(dev);
16082 }
16083
16084 /*
16085 * Return which encoder is currently attached for connector.
16086 */
16087 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16088 {
16089 return &intel_attached_encoder(connector)->base;
16090 }
16091
16092 void intel_connector_attach_encoder(struct intel_connector *connector,
16093 struct intel_encoder *encoder)
16094 {
16095 connector->encoder = encoder;
16096 drm_mode_connector_attach_encoder(&connector->base,
16097 &encoder->base);
16098 }
16099
16100 /*
16101 * set vga decode state - true == enable VGA decode
16102 */
16103 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16104 {
16105 struct drm_i915_private *dev_priv = dev->dev_private;
16106 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16107 u16 gmch_ctrl;
16108
16109 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16110 DRM_ERROR("failed to read control word\n");
16111 return -EIO;
16112 }
16113
16114 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16115 return 0;
16116
16117 if (state)
16118 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16119 else
16120 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16121
16122 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16123 DRM_ERROR("failed to write control word\n");
16124 return -EIO;
16125 }
16126
16127 return 0;
16128 }
16129
16130 struct intel_display_error_state {
16131
16132 u32 power_well_driver;
16133
16134 int num_transcoders;
16135
16136 struct intel_cursor_error_state {
16137 u32 control;
16138 u32 position;
16139 u32 base;
16140 u32 size;
16141 } cursor[I915_MAX_PIPES];
16142
16143 struct intel_pipe_error_state {
16144 bool power_domain_on;
16145 u32 source;
16146 u32 stat;
16147 } pipe[I915_MAX_PIPES];
16148
16149 struct intel_plane_error_state {
16150 u32 control;
16151 u32 stride;
16152 u32 size;
16153 u32 pos;
16154 u32 addr;
16155 u32 surface;
16156 u32 tile_offset;
16157 } plane[I915_MAX_PIPES];
16158
16159 struct intel_transcoder_error_state {
16160 bool power_domain_on;
16161 enum transcoder cpu_transcoder;
16162
16163 u32 conf;
16164
16165 u32 htotal;
16166 u32 hblank;
16167 u32 hsync;
16168 u32 vtotal;
16169 u32 vblank;
16170 u32 vsync;
16171 } transcoder[4];
16172 };
16173
16174 struct intel_display_error_state *
16175 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16176 {
16177 struct intel_display_error_state *error;
16178 int transcoders[] = {
16179 TRANSCODER_A,
16180 TRANSCODER_B,
16181 TRANSCODER_C,
16182 TRANSCODER_EDP,
16183 };
16184 int i;
16185
16186 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16187 return NULL;
16188
16189 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16190 if (error == NULL)
16191 return NULL;
16192
16193 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16194 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16195
16196 for_each_pipe(dev_priv, i) {
16197 error->pipe[i].power_domain_on =
16198 __intel_display_power_is_enabled(dev_priv,
16199 POWER_DOMAIN_PIPE(i));
16200 if (!error->pipe[i].power_domain_on)
16201 continue;
16202
16203 error->cursor[i].control = I915_READ(CURCNTR(i));
16204 error->cursor[i].position = I915_READ(CURPOS(i));
16205 error->cursor[i].base = I915_READ(CURBASE(i));
16206
16207 error->plane[i].control = I915_READ(DSPCNTR(i));
16208 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16209 if (INTEL_GEN(dev_priv) <= 3) {
16210 error->plane[i].size = I915_READ(DSPSIZE(i));
16211 error->plane[i].pos = I915_READ(DSPPOS(i));
16212 }
16213 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16214 error->plane[i].addr = I915_READ(DSPADDR(i));
16215 if (INTEL_GEN(dev_priv) >= 4) {
16216 error->plane[i].surface = I915_READ(DSPSURF(i));
16217 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16218 }
16219
16220 error->pipe[i].source = I915_READ(PIPESRC(i));
16221
16222 if (HAS_GMCH_DISPLAY(dev_priv))
16223 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16224 }
16225
16226 /* Note: this does not include DSI transcoders. */
16227 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16228 if (HAS_DDI(dev_priv))
16229 error->num_transcoders++; /* Account for eDP. */
16230
16231 for (i = 0; i < error->num_transcoders; i++) {
16232 enum transcoder cpu_transcoder = transcoders[i];
16233
16234 error->transcoder[i].power_domain_on =
16235 __intel_display_power_is_enabled(dev_priv,
16236 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16237 if (!error->transcoder[i].power_domain_on)
16238 continue;
16239
16240 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16241
16242 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16243 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16244 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16245 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16246 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16247 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16248 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16249 }
16250
16251 return error;
16252 }
16253
16254 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16255
16256 void
16257 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16258 struct drm_device *dev,
16259 struct intel_display_error_state *error)
16260 {
16261 struct drm_i915_private *dev_priv = dev->dev_private;
16262 int i;
16263
16264 if (!error)
16265 return;
16266
16267 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16268 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16269 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16270 error->power_well_driver);
16271 for_each_pipe(dev_priv, i) {
16272 err_printf(m, "Pipe [%d]:\n", i);
16273 err_printf(m, " Power: %s\n",
16274 onoff(error->pipe[i].power_domain_on));
16275 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16276 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16277
16278 err_printf(m, "Plane [%d]:\n", i);
16279 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16280 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16281 if (INTEL_INFO(dev)->gen <= 3) {
16282 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16283 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16284 }
16285 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16286 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16287 if (INTEL_INFO(dev)->gen >= 4) {
16288 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16289 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16290 }
16291
16292 err_printf(m, "Cursor [%d]:\n", i);
16293 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16294 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16295 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16296 }
16297
16298 for (i = 0; i < error->num_transcoders; i++) {
16299 err_printf(m, "CPU transcoder: %s\n",
16300 transcoder_name(error->transcoder[i].cpu_transcoder));
16301 err_printf(m, " Power: %s\n",
16302 onoff(error->transcoder[i].power_domain_on));
16303 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16304 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16305 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16306 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16307 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16308 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16309 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16310 }
16311 }
Linux kernel - Deliverables
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