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drm/i915: Mass convert dev->dev_private to to_i915(dev)
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_gem_dmabuf.h"
40 #include "intel_dsi.h"
41 #include "i915_trace.h"
42 #include <drm/drm_atomic.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_dp_helper.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_plane_helper.h>
47 #include <drm/drm_rect.h>
48 #include <linux/dma_remapping.h>
49 #include <linux/reservation.h>
50
51 static bool is_mmio_work(struct intel_flip_work *work)
52 {
53 return work->mmio_work.func;
54 }
55
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB1555,
61 DRM_FORMAT_XRGB8888,
62 };
63
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_C8,
67 DRM_FORMAT_RGB565,
68 DRM_FORMAT_XRGB8888,
69 DRM_FORMAT_XBGR8888,
70 DRM_FORMAT_XRGB2101010,
71 DRM_FORMAT_XBGR2101010,
72 };
73
74 static const uint32_t skl_primary_formats[] = {
75 DRM_FORMAT_C8,
76 DRM_FORMAT_RGB565,
77 DRM_FORMAT_XRGB8888,
78 DRM_FORMAT_XBGR8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_XRGB2101010,
82 DRM_FORMAT_XBGR2101010,
83 DRM_FORMAT_YUYV,
84 DRM_FORMAT_YVYU,
85 DRM_FORMAT_UYVY,
86 DRM_FORMAT_VYUY,
87 };
88
89 /* Cursor formats */
90 static const uint32_t intel_cursor_formats[] = {
91 DRM_FORMAT_ARGB8888,
92 };
93
94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
95 struct intel_crtc_state *pipe_config);
96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 struct intel_crtc_state *pipe_config);
98
99 static int intel_framebuffer_init(struct drm_device *dev,
100 struct intel_framebuffer *ifb,
101 struct drm_mode_fb_cmd2 *mode_cmd,
102 struct drm_i915_gem_object *obj);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
126 static int bxt_calc_cdclk(int max_pixclk);
127
128 struct intel_limit {
129 struct {
130 int min, max;
131 } dot, vco, n, m, m1, m2, p, p1;
132
133 struct {
134 int dot_limit;
135 int p2_slow, p2_fast;
136 } p2;
137 };
138
139 /* returns HPLL frequency in kHz */
140 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
141 {
142 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
143
144 /* Obtain SKU information */
145 mutex_lock(&dev_priv->sb_lock);
146 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
147 CCK_FUSE_HPLL_FREQ_MASK;
148 mutex_unlock(&dev_priv->sb_lock);
149
150 return vco_freq[hpll_freq] * 1000;
151 }
152
153 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
154 const char *name, u32 reg, int ref_freq)
155 {
156 u32 val;
157 int divider;
158
159 mutex_lock(&dev_priv->sb_lock);
160 val = vlv_cck_read(dev_priv, reg);
161 mutex_unlock(&dev_priv->sb_lock);
162
163 divider = val & CCK_FREQUENCY_VALUES;
164
165 WARN((val & CCK_FREQUENCY_STATUS) !=
166 (divider << CCK_FREQUENCY_STATUS_SHIFT),
167 "%s change in progress\n", name);
168
169 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
170 }
171
172 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
173 const char *name, u32 reg)
174 {
175 if (dev_priv->hpll_freq == 0)
176 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
177
178 return vlv_get_cck_clock(dev_priv, name, reg,
179 dev_priv->hpll_freq);
180 }
181
182 static int
183 intel_pch_rawclk(struct drm_i915_private *dev_priv)
184 {
185 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
186 }
187
188 static int
189 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
190 {
191 /* RAWCLK_FREQ_VLV register updated from power well code */
192 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
193 CCK_DISPLAY_REF_CLOCK_CONTROL);
194 }
195
196 static int
197 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
198 {
199 uint32_t clkcfg;
200
201 /* hrawclock is 1/4 the FSB frequency */
202 clkcfg = I915_READ(CLKCFG);
203 switch (clkcfg & CLKCFG_FSB_MASK) {
204 case CLKCFG_FSB_400:
205 return 100000;
206 case CLKCFG_FSB_533:
207 return 133333;
208 case CLKCFG_FSB_667:
209 return 166667;
210 case CLKCFG_FSB_800:
211 return 200000;
212 case CLKCFG_FSB_1067:
213 return 266667;
214 case CLKCFG_FSB_1333:
215 return 333333;
216 /* these two are just a guess; one of them might be right */
217 case CLKCFG_FSB_1600:
218 case CLKCFG_FSB_1600_ALT:
219 return 400000;
220 default:
221 return 133333;
222 }
223 }
224
225 void intel_update_rawclk(struct drm_i915_private *dev_priv)
226 {
227 if (HAS_PCH_SPLIT(dev_priv))
228 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
229 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
230 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
231 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
232 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
233 else
234 return; /* no rawclk on other platforms, or no need to know it */
235
236 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
237 }
238
239 static void intel_update_czclk(struct drm_i915_private *dev_priv)
240 {
241 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
242 return;
243
244 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
245 CCK_CZ_CLOCK_CONTROL);
246
247 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
248 }
249
250 static inline u32 /* units of 100MHz */
251 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
252 const struct intel_crtc_state *pipe_config)
253 {
254 if (HAS_DDI(dev_priv))
255 return pipe_config->port_clock; /* SPLL */
256 else if (IS_GEN5(dev_priv))
257 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
258 else
259 return 270000;
260 }
261
262 static const struct intel_limit intel_limits_i8xx_dac = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 908000, .max = 1512000 },
265 .n = { .min = 2, .max = 16 },
266 .m = { .min = 96, .max = 140 },
267 .m1 = { .min = 18, .max = 26 },
268 .m2 = { .min = 6, .max = 16 },
269 .p = { .min = 4, .max = 128 },
270 .p1 = { .min = 2, .max = 33 },
271 .p2 = { .dot_limit = 165000,
272 .p2_slow = 4, .p2_fast = 2 },
273 };
274
275 static const struct intel_limit intel_limits_i8xx_dvo = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 908000, .max = 1512000 },
278 .n = { .min = 2, .max = 16 },
279 .m = { .min = 96, .max = 140 },
280 .m1 = { .min = 18, .max = 26 },
281 .m2 = { .min = 6, .max = 16 },
282 .p = { .min = 4, .max = 128 },
283 .p1 = { .min = 2, .max = 33 },
284 .p2 = { .dot_limit = 165000,
285 .p2_slow = 4, .p2_fast = 4 },
286 };
287
288 static const struct intel_limit intel_limits_i8xx_lvds = {
289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 908000, .max = 1512000 },
291 .n = { .min = 2, .max = 16 },
292 .m = { .min = 96, .max = 140 },
293 .m1 = { .min = 18, .max = 26 },
294 .m2 = { .min = 6, .max = 16 },
295 .p = { .min = 4, .max = 128 },
296 .p1 = { .min = 1, .max = 6 },
297 .p2 = { .dot_limit = 165000,
298 .p2_slow = 14, .p2_fast = 7 },
299 };
300
301 static const struct intel_limit intel_limits_i9xx_sdvo = {
302 .dot = { .min = 20000, .max = 400000 },
303 .vco = { .min = 1400000, .max = 2800000 },
304 .n = { .min = 1, .max = 6 },
305 .m = { .min = 70, .max = 120 },
306 .m1 = { .min = 8, .max = 18 },
307 .m2 = { .min = 3, .max = 7 },
308 .p = { .min = 5, .max = 80 },
309 .p1 = { .min = 1, .max = 8 },
310 .p2 = { .dot_limit = 200000,
311 .p2_slow = 10, .p2_fast = 5 },
312 };
313
314 static const struct intel_limit intel_limits_i9xx_lvds = {
315 .dot = { .min = 20000, .max = 400000 },
316 .vco = { .min = 1400000, .max = 2800000 },
317 .n = { .min = 1, .max = 6 },
318 .m = { .min = 70, .max = 120 },
319 .m1 = { .min = 8, .max = 18 },
320 .m2 = { .min = 3, .max = 7 },
321 .p = { .min = 7, .max = 98 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 112000,
324 .p2_slow = 14, .p2_fast = 7 },
325 };
326
327
328 static const struct intel_limit intel_limits_g4x_sdvo = {
329 .dot = { .min = 25000, .max = 270000 },
330 .vco = { .min = 1750000, .max = 3500000},
331 .n = { .min = 1, .max = 4 },
332 .m = { .min = 104, .max = 138 },
333 .m1 = { .min = 17, .max = 23 },
334 .m2 = { .min = 5, .max = 11 },
335 .p = { .min = 10, .max = 30 },
336 .p1 = { .min = 1, .max = 3},
337 .p2 = { .dot_limit = 270000,
338 .p2_slow = 10,
339 .p2_fast = 10
340 },
341 };
342
343 static const struct intel_limit intel_limits_g4x_hdmi = {
344 .dot = { .min = 22000, .max = 400000 },
345 .vco = { .min = 1750000, .max = 3500000},
346 .n = { .min = 1, .max = 4 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 16, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 5, .max = 80 },
351 .p1 = { .min = 1, .max = 8},
352 .p2 = { .dot_limit = 165000,
353 .p2_slow = 10, .p2_fast = 5 },
354 };
355
356 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
357 .dot = { .min = 20000, .max = 115000 },
358 .vco = { .min = 1750000, .max = 3500000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 104, .max = 138 },
361 .m1 = { .min = 17, .max = 23 },
362 .m2 = { .min = 5, .max = 11 },
363 .p = { .min = 28, .max = 112 },
364 .p1 = { .min = 2, .max = 8 },
365 .p2 = { .dot_limit = 0,
366 .p2_slow = 14, .p2_fast = 14
367 },
368 };
369
370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
371 .dot = { .min = 80000, .max = 224000 },
372 .vco = { .min = 1750000, .max = 3500000 },
373 .n = { .min = 1, .max = 3 },
374 .m = { .min = 104, .max = 138 },
375 .m1 = { .min = 17, .max = 23 },
376 .m2 = { .min = 5, .max = 11 },
377 .p = { .min = 14, .max = 42 },
378 .p1 = { .min = 2, .max = 6 },
379 .p2 = { .dot_limit = 0,
380 .p2_slow = 7, .p2_fast = 7
381 },
382 };
383
384 static const struct intel_limit intel_limits_pineview_sdvo = {
385 .dot = { .min = 20000, .max = 400000},
386 .vco = { .min = 1700000, .max = 3500000 },
387 /* Pineview's Ncounter is a ring counter */
388 .n = { .min = 3, .max = 6 },
389 .m = { .min = 2, .max = 256 },
390 /* Pineview only has one combined m divider, which we treat as m2. */
391 .m1 = { .min = 0, .max = 0 },
392 .m2 = { .min = 0, .max = 254 },
393 .p = { .min = 5, .max = 80 },
394 .p1 = { .min = 1, .max = 8 },
395 .p2 = { .dot_limit = 200000,
396 .p2_slow = 10, .p2_fast = 5 },
397 };
398
399 static const struct intel_limit intel_limits_pineview_lvds = {
400 .dot = { .min = 20000, .max = 400000 },
401 .vco = { .min = 1700000, .max = 3500000 },
402 .n = { .min = 3, .max = 6 },
403 .m = { .min = 2, .max = 256 },
404 .m1 = { .min = 0, .max = 0 },
405 .m2 = { .min = 0, .max = 254 },
406 .p = { .min = 7, .max = 112 },
407 .p1 = { .min = 1, .max = 8 },
408 .p2 = { .dot_limit = 112000,
409 .p2_slow = 14, .p2_fast = 14 },
410 };
411
412 /* Ironlake / Sandybridge
413 *
414 * We calculate clock using (register_value + 2) for N/M1/M2, so here
415 * the range value for them is (actual_value - 2).
416 */
417 static const struct intel_limit intel_limits_ironlake_dac = {
418 .dot = { .min = 25000, .max = 350000 },
419 .vco = { .min = 1760000, .max = 3510000 },
420 .n = { .min = 1, .max = 5 },
421 .m = { .min = 79, .max = 127 },
422 .m1 = { .min = 12, .max = 22 },
423 .m2 = { .min = 5, .max = 9 },
424 .p = { .min = 5, .max = 80 },
425 .p1 = { .min = 1, .max = 8 },
426 .p2 = { .dot_limit = 225000,
427 .p2_slow = 10, .p2_fast = 5 },
428 };
429
430 static const struct intel_limit intel_limits_ironlake_single_lvds = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 3 },
434 .m = { .min = 79, .max = 118 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 127 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 56 },
451 .p1 = { .min = 2, .max = 8 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 /* LVDS 100mhz refclk limits. */
457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
458 .dot = { .min = 25000, .max = 350000 },
459 .vco = { .min = 1760000, .max = 3510000 },
460 .n = { .min = 1, .max = 2 },
461 .m = { .min = 79, .max = 126 },
462 .m1 = { .min = 12, .max = 22 },
463 .m2 = { .min = 5, .max = 9 },
464 .p = { .min = 28, .max = 112 },
465 .p1 = { .min = 2, .max = 8 },
466 .p2 = { .dot_limit = 225000,
467 .p2_slow = 14, .p2_fast = 14 },
468 };
469
470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
471 .dot = { .min = 25000, .max = 350000 },
472 .vco = { .min = 1760000, .max = 3510000 },
473 .n = { .min = 1, .max = 3 },
474 .m = { .min = 79, .max = 126 },
475 .m1 = { .min = 12, .max = 22 },
476 .m2 = { .min = 5, .max = 9 },
477 .p = { .min = 14, .max = 42 },
478 .p1 = { .min = 2, .max = 6 },
479 .p2 = { .dot_limit = 225000,
480 .p2_slow = 7, .p2_fast = 7 },
481 };
482
483 static const struct intel_limit intel_limits_vlv = {
484 /*
485 * These are the data rate limits (measured in fast clocks)
486 * since those are the strictest limits we have. The fast
487 * clock and actual rate limits are more relaxed, so checking
488 * them would make no difference.
489 */
490 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
491 .vco = { .min = 4000000, .max = 6000000 },
492 .n = { .min = 1, .max = 7 },
493 .m1 = { .min = 2, .max = 3 },
494 .m2 = { .min = 11, .max = 156 },
495 .p1 = { .min = 2, .max = 3 },
496 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
497 };
498
499 static const struct intel_limit intel_limits_chv = {
500 /*
501 * These are the data rate limits (measured in fast clocks)
502 * since those are the strictest limits we have. The fast
503 * clock and actual rate limits are more relaxed, so checking
504 * them would make no difference.
505 */
506 .dot = { .min = 25000 * 5, .max = 540000 * 5},
507 .vco = { .min = 4800000, .max = 6480000 },
508 .n = { .min = 1, .max = 1 },
509 .m1 = { .min = 2, .max = 2 },
510 .m2 = { .min = 24 << 22, .max = 175 << 22 },
511 .p1 = { .min = 2, .max = 4 },
512 .p2 = { .p2_slow = 1, .p2_fast = 14 },
513 };
514
515 static const struct intel_limit intel_limits_bxt = {
516 /* FIXME: find real dot limits */
517 .dot = { .min = 0, .max = INT_MAX },
518 .vco = { .min = 4800000, .max = 6700000 },
519 .n = { .min = 1, .max = 1 },
520 .m1 = { .min = 2, .max = 2 },
521 /* FIXME: find real m2 limits */
522 .m2 = { .min = 2 << 22, .max = 255 << 22 },
523 .p1 = { .min = 2, .max = 4 },
524 .p2 = { .p2_slow = 1, .p2_fast = 20 },
525 };
526
527 static bool
528 needs_modeset(struct drm_crtc_state *state)
529 {
530 return drm_atomic_crtc_needs_modeset(state);
531 }
532
533 /**
534 * Returns whether any output on the specified pipe is of the specified type
535 */
536 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
537 {
538 struct drm_device *dev = crtc->base.dev;
539 struct intel_encoder *encoder;
540
541 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
542 if (encoder->type == type)
543 return true;
544
545 return false;
546 }
547
548 /**
549 * Returns whether any output on the specified pipe will have the specified
550 * type after a staged modeset is complete, i.e., the same as
551 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
552 * encoder->crtc.
553 */
554 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
555 int type)
556 {
557 struct drm_atomic_state *state = crtc_state->base.state;
558 struct drm_connector *connector;
559 struct drm_connector_state *connector_state;
560 struct intel_encoder *encoder;
561 int i, num_connectors = 0;
562
563 for_each_connector_in_state(state, connector, connector_state, i) {
564 if (connector_state->crtc != crtc_state->base.crtc)
565 continue;
566
567 num_connectors++;
568
569 encoder = to_intel_encoder(connector_state->best_encoder);
570 if (encoder->type == type)
571 return true;
572 }
573
574 WARN_ON(num_connectors == 0);
575
576 return false;
577 }
578
579 /*
580 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
581 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
582 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
583 * The helpers' return value is the rate of the clock that is fed to the
584 * display engine's pipe which can be the above fast dot clock rate or a
585 * divided-down version of it.
586 */
587 /* m1 is reserved as 0 in Pineview, n is a ring counter */
588 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
589 {
590 clock->m = clock->m2 + 2;
591 clock->p = clock->p1 * clock->p2;
592 if (WARN_ON(clock->n == 0 || clock->p == 0))
593 return 0;
594 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
595 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
596
597 return clock->dot;
598 }
599
600 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
601 {
602 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
603 }
604
605 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
606 {
607 clock->m = i9xx_dpll_compute_m(clock);
608 clock->p = clock->p1 * clock->p2;
609 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
610 return 0;
611 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
612 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
613
614 return clock->dot;
615 }
616
617 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
618 {
619 clock->m = clock->m1 * clock->m2;
620 clock->p = clock->p1 * clock->p2;
621 if (WARN_ON(clock->n == 0 || clock->p == 0))
622 return 0;
623 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
624 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
625
626 return clock->dot / 5;
627 }
628
629 int chv_calc_dpll_params(int refclk, struct dpll *clock)
630 {
631 clock->m = clock->m1 * clock->m2;
632 clock->p = clock->p1 * clock->p2;
633 if (WARN_ON(clock->n == 0 || clock->p == 0))
634 return 0;
635 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
636 clock->n << 22);
637 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
638
639 return clock->dot / 5;
640 }
641
642 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
643 /**
644 * Returns whether the given set of divisors are valid for a given refclk with
645 * the given connectors.
646 */
647
648 static bool intel_PLL_is_valid(struct drm_device *dev,
649 const struct intel_limit *limit,
650 const struct dpll *clock)
651 {
652 if (clock->n < limit->n.min || limit->n.max < clock->n)
653 INTELPllInvalid("n out of range\n");
654 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
655 INTELPllInvalid("p1 out of range\n");
656 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
657 INTELPllInvalid("m2 out of range\n");
658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
659 INTELPllInvalid("m1 out of range\n");
660
661 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
662 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
663 if (clock->m1 <= clock->m2)
664 INTELPllInvalid("m1 <= m2\n");
665
666 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
667 if (clock->p < limit->p.min || limit->p.max < clock->p)
668 INTELPllInvalid("p out of range\n");
669 if (clock->m < limit->m.min || limit->m.max < clock->m)
670 INTELPllInvalid("m out of range\n");
671 }
672
673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
674 INTELPllInvalid("vco out of range\n");
675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
679 INTELPllInvalid("dot out of range\n");
680
681 return true;
682 }
683
684 static int
685 i9xx_select_p2_div(const struct intel_limit *limit,
686 const struct intel_crtc_state *crtc_state,
687 int target)
688 {
689 struct drm_device *dev = crtc_state->base.crtc->dev;
690
691 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
692 /*
693 * For LVDS just rely on its current settings for dual-channel.
694 * We haven't figured out how to reliably set up different
695 * single/dual channel state, if we even can.
696 */
697 if (intel_is_dual_link_lvds(dev))
698 return limit->p2.p2_fast;
699 else
700 return limit->p2.p2_slow;
701 } else {
702 if (target < limit->p2.dot_limit)
703 return limit->p2.p2_slow;
704 else
705 return limit->p2.p2_fast;
706 }
707 }
708
709 /*
710 * Returns a set of divisors for the desired target clock with the given
711 * refclk, or FALSE. The returned values represent the clock equation:
712 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
713 *
714 * Target and reference clocks are specified in kHz.
715 *
716 * If match_clock is provided, then best_clock P divider must match the P
717 * divider from @match_clock used for LVDS downclocking.
718 */
719 static bool
720 i9xx_find_best_dpll(const struct intel_limit *limit,
721 struct intel_crtc_state *crtc_state,
722 int target, int refclk, struct dpll *match_clock,
723 struct dpll *best_clock)
724 {
725 struct drm_device *dev = crtc_state->base.crtc->dev;
726 struct dpll clock;
727 int err = target;
728
729 memset(best_clock, 0, sizeof(*best_clock));
730
731 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
732
733 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
734 clock.m1++) {
735 for (clock.m2 = limit->m2.min;
736 clock.m2 <= limit->m2.max; clock.m2++) {
737 if (clock.m2 >= clock.m1)
738 break;
739 for (clock.n = limit->n.min;
740 clock.n <= limit->n.max; clock.n++) {
741 for (clock.p1 = limit->p1.min;
742 clock.p1 <= limit->p1.max; clock.p1++) {
743 int this_err;
744
745 i9xx_calc_dpll_params(refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
748 continue;
749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
752
753 this_err = abs(clock.dot - target);
754 if (this_err < err) {
755 *best_clock = clock;
756 err = this_err;
757 }
758 }
759 }
760 }
761 }
762
763 return (err != target);
764 }
765
766 /*
767 * Returns a set of divisors for the desired target clock with the given
768 * refclk, or FALSE. The returned values represent the clock equation:
769 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
770 *
771 * Target and reference clocks are specified in kHz.
772 *
773 * If match_clock is provided, then best_clock P divider must match the P
774 * divider from @match_clock used for LVDS downclocking.
775 */
776 static bool
777 pnv_find_best_dpll(const struct intel_limit *limit,
778 struct intel_crtc_state *crtc_state,
779 int target, int refclk, struct dpll *match_clock,
780 struct dpll *best_clock)
781 {
782 struct drm_device *dev = crtc_state->base.crtc->dev;
783 struct dpll clock;
784 int err = target;
785
786 memset(best_clock, 0, sizeof(*best_clock));
787
788 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
789
790 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
791 clock.m1++) {
792 for (clock.m2 = limit->m2.min;
793 clock.m2 <= limit->m2.max; clock.m2++) {
794 for (clock.n = limit->n.min;
795 clock.n <= limit->n.max; clock.n++) {
796 for (clock.p1 = limit->p1.min;
797 clock.p1 <= limit->p1.max; clock.p1++) {
798 int this_err;
799
800 pnv_calc_dpll_params(refclk, &clock);
801 if (!intel_PLL_is_valid(dev, limit,
802 &clock))
803 continue;
804 if (match_clock &&
805 clock.p != match_clock->p)
806 continue;
807
808 this_err = abs(clock.dot - target);
809 if (this_err < err) {
810 *best_clock = clock;
811 err = this_err;
812 }
813 }
814 }
815 }
816 }
817
818 return (err != target);
819 }
820
821 /*
822 * Returns a set of divisors for the desired target clock with the given
823 * refclk, or FALSE. The returned values represent the clock equation:
824 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
825 *
826 * Target and reference clocks are specified in kHz.
827 *
828 * If match_clock is provided, then best_clock P divider must match the P
829 * divider from @match_clock used for LVDS downclocking.
830 */
831 static bool
832 g4x_find_best_dpll(const struct intel_limit *limit,
833 struct intel_crtc_state *crtc_state,
834 int target, int refclk, struct dpll *match_clock,
835 struct dpll *best_clock)
836 {
837 struct drm_device *dev = crtc_state->base.crtc->dev;
838 struct dpll clock;
839 int max_n;
840 bool found = false;
841 /* approximately equals target * 0.00585 */
842 int err_most = (target >> 8) + (target >> 9);
843
844 memset(best_clock, 0, sizeof(*best_clock));
845
846 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
847
848 max_n = limit->n.max;
849 /* based on hardware requirement, prefer smaller n to precision */
850 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
851 /* based on hardware requirement, prefere larger m1,m2 */
852 for (clock.m1 = limit->m1.max;
853 clock.m1 >= limit->m1.min; clock.m1--) {
854 for (clock.m2 = limit->m2.max;
855 clock.m2 >= limit->m2.min; clock.m2--) {
856 for (clock.p1 = limit->p1.max;
857 clock.p1 >= limit->p1.min; clock.p1--) {
858 int this_err;
859
860 i9xx_calc_dpll_params(refclk, &clock);
861 if (!intel_PLL_is_valid(dev, limit,
862 &clock))
863 continue;
864
865 this_err = abs(clock.dot - target);
866 if (this_err < err_most) {
867 *best_clock = clock;
868 err_most = this_err;
869 max_n = clock.n;
870 found = true;
871 }
872 }
873 }
874 }
875 }
876 return found;
877 }
878
879 /*
880 * Check if the calculated PLL configuration is more optimal compared to the
881 * best configuration and error found so far. Return the calculated error.
882 */
883 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
884 const struct dpll *calculated_clock,
885 const struct dpll *best_clock,
886 unsigned int best_error_ppm,
887 unsigned int *error_ppm)
888 {
889 /*
890 * For CHV ignore the error and consider only the P value.
891 * Prefer a bigger P value based on HW requirements.
892 */
893 if (IS_CHERRYVIEW(dev)) {
894 *error_ppm = 0;
895
896 return calculated_clock->p > best_clock->p;
897 }
898
899 if (WARN_ON_ONCE(!target_freq))
900 return false;
901
902 *error_ppm = div_u64(1000000ULL *
903 abs(target_freq - calculated_clock->dot),
904 target_freq);
905 /*
906 * Prefer a better P value over a better (smaller) error if the error
907 * is small. Ensure this preference for future configurations too by
908 * setting the error to 0.
909 */
910 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
911 *error_ppm = 0;
912
913 return true;
914 }
915
916 return *error_ppm + 10 < best_error_ppm;
917 }
918
919 /*
920 * Returns a set of divisors for the desired target clock with the given
921 * refclk, or FALSE. The returned values represent the clock equation:
922 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
923 */
924 static bool
925 vlv_find_best_dpll(const struct intel_limit *limit,
926 struct intel_crtc_state *crtc_state,
927 int target, int refclk, struct dpll *match_clock,
928 struct dpll *best_clock)
929 {
930 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
931 struct drm_device *dev = crtc->base.dev;
932 struct dpll clock;
933 unsigned int bestppm = 1000000;
934 /* min update 19.2 MHz */
935 int max_n = min(limit->n.max, refclk / 19200);
936 bool found = false;
937
938 target *= 5; /* fast clock */
939
940 memset(best_clock, 0, sizeof(*best_clock));
941
942 /* based on hardware requirement, prefer smaller n to precision */
943 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
944 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
945 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
947 clock.p = clock.p1 * clock.p2;
948 /* based on hardware requirement, prefer bigger m1,m2 values */
949 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
950 unsigned int ppm;
951
952 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
953 refclk * clock.m1);
954
955 vlv_calc_dpll_params(refclk, &clock);
956
957 if (!intel_PLL_is_valid(dev, limit,
958 &clock))
959 continue;
960
961 if (!vlv_PLL_is_optimal(dev, target,
962 &clock,
963 best_clock,
964 bestppm, &ppm))
965 continue;
966
967 *best_clock = clock;
968 bestppm = ppm;
969 found = true;
970 }
971 }
972 }
973 }
974
975 return found;
976 }
977
978 /*
979 * Returns a set of divisors for the desired target clock with the given
980 * refclk, or FALSE. The returned values represent the clock equation:
981 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
982 */
983 static bool
984 chv_find_best_dpll(const struct intel_limit *limit,
985 struct intel_crtc_state *crtc_state,
986 int target, int refclk, struct dpll *match_clock,
987 struct dpll *best_clock)
988 {
989 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
990 struct drm_device *dev = crtc->base.dev;
991 unsigned int best_error_ppm;
992 struct dpll clock;
993 uint64_t m2;
994 int found = false;
995
996 memset(best_clock, 0, sizeof(*best_clock));
997 best_error_ppm = 1000000;
998
999 /*
1000 * Based on hardware doc, the n always set to 1, and m1 always
1001 * set to 2. If requires to support 200Mhz refclk, we need to
1002 * revisit this because n may not 1 anymore.
1003 */
1004 clock.n = 1, clock.m1 = 2;
1005 target *= 5; /* fast clock */
1006
1007 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1008 for (clock.p2 = limit->p2.p2_fast;
1009 clock.p2 >= limit->p2.p2_slow;
1010 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1011 unsigned int error_ppm;
1012
1013 clock.p = clock.p1 * clock.p2;
1014
1015 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1016 clock.n) << 22, refclk * clock.m1);
1017
1018 if (m2 > INT_MAX/clock.m1)
1019 continue;
1020
1021 clock.m2 = m2;
1022
1023 chv_calc_dpll_params(refclk, &clock);
1024
1025 if (!intel_PLL_is_valid(dev, limit, &clock))
1026 continue;
1027
1028 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1029 best_error_ppm, &error_ppm))
1030 continue;
1031
1032 *best_clock = clock;
1033 best_error_ppm = error_ppm;
1034 found = true;
1035 }
1036 }
1037
1038 return found;
1039 }
1040
1041 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1042 struct dpll *best_clock)
1043 {
1044 int refclk = 100000;
1045 const struct intel_limit *limit = &intel_limits_bxt;
1046
1047 return chv_find_best_dpll(limit, crtc_state,
1048 target_clock, refclk, NULL, best_clock);
1049 }
1050
1051 bool intel_crtc_active(struct drm_crtc *crtc)
1052 {
1053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1054
1055 /* Be paranoid as we can arrive here with only partial
1056 * state retrieved from the hardware during setup.
1057 *
1058 * We can ditch the adjusted_mode.crtc_clock check as soon
1059 * as Haswell has gained clock readout/fastboot support.
1060 *
1061 * We can ditch the crtc->primary->fb check as soon as we can
1062 * properly reconstruct framebuffers.
1063 *
1064 * FIXME: The intel_crtc->active here should be switched to
1065 * crtc->state->active once we have proper CRTC states wired up
1066 * for atomic.
1067 */
1068 return intel_crtc->active && crtc->primary->state->fb &&
1069 intel_crtc->config->base.adjusted_mode.crtc_clock;
1070 }
1071
1072 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1073 enum pipe pipe)
1074 {
1075 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1077
1078 return intel_crtc->config->cpu_transcoder;
1079 }
1080
1081 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1082 {
1083 struct drm_i915_private *dev_priv = to_i915(dev);
1084 i915_reg_t reg = PIPEDSL(pipe);
1085 u32 line1, line2;
1086 u32 line_mask;
1087
1088 if (IS_GEN2(dev))
1089 line_mask = DSL_LINEMASK_GEN2;
1090 else
1091 line_mask = DSL_LINEMASK_GEN3;
1092
1093 line1 = I915_READ(reg) & line_mask;
1094 msleep(5);
1095 line2 = I915_READ(reg) & line_mask;
1096
1097 return line1 == line2;
1098 }
1099
1100 /*
1101 * intel_wait_for_pipe_off - wait for pipe to turn off
1102 * @crtc: crtc whose pipe to wait for
1103 *
1104 * After disabling a pipe, we can't wait for vblank in the usual way,
1105 * spinning on the vblank interrupt status bit, since we won't actually
1106 * see an interrupt when the pipe is disabled.
1107 *
1108 * On Gen4 and above:
1109 * wait for the pipe register state bit to turn off
1110 *
1111 * Otherwise:
1112 * wait for the display line value to settle (it usually
1113 * ends up stopping at the start of the next frame).
1114 *
1115 */
1116 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1117 {
1118 struct drm_device *dev = crtc->base.dev;
1119 struct drm_i915_private *dev_priv = to_i915(dev);
1120 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1121 enum pipe pipe = crtc->pipe;
1122
1123 if (INTEL_INFO(dev)->gen >= 4) {
1124 i915_reg_t reg = PIPECONF(cpu_transcoder);
1125
1126 /* Wait for the Pipe State to go off */
1127 if (intel_wait_for_register(dev_priv,
1128 reg, I965_PIPECONF_ACTIVE, 0,
1129 100))
1130 WARN(1, "pipe_off wait timed out\n");
1131 } else {
1132 /* Wait for the display line to settle */
1133 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1134 WARN(1, "pipe_off wait timed out\n");
1135 }
1136 }
1137
1138 /* Only for pre-ILK configs */
1139 void assert_pll(struct drm_i915_private *dev_priv,
1140 enum pipe pipe, bool state)
1141 {
1142 u32 val;
1143 bool cur_state;
1144
1145 val = I915_READ(DPLL(pipe));
1146 cur_state = !!(val & DPLL_VCO_ENABLE);
1147 I915_STATE_WARN(cur_state != state,
1148 "PLL state assertion failure (expected %s, current %s)\n",
1149 onoff(state), onoff(cur_state));
1150 }
1151
1152 /* XXX: the dsi pll is shared between MIPI DSI ports */
1153 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1154 {
1155 u32 val;
1156 bool cur_state;
1157
1158 mutex_lock(&dev_priv->sb_lock);
1159 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1160 mutex_unlock(&dev_priv->sb_lock);
1161
1162 cur_state = val & DSI_PLL_VCO_EN;
1163 I915_STATE_WARN(cur_state != state,
1164 "DSI PLL state assertion failure (expected %s, current %s)\n",
1165 onoff(state), onoff(cur_state));
1166 }
1167
1168 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1169 enum pipe pipe, bool state)
1170 {
1171 bool cur_state;
1172 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1173 pipe);
1174
1175 if (HAS_DDI(dev_priv)) {
1176 /* DDI does not have a specific FDI_TX register */
1177 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1178 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1179 } else {
1180 u32 val = I915_READ(FDI_TX_CTL(pipe));
1181 cur_state = !!(val & FDI_TX_ENABLE);
1182 }
1183 I915_STATE_WARN(cur_state != state,
1184 "FDI TX state assertion failure (expected %s, current %s)\n",
1185 onoff(state), onoff(cur_state));
1186 }
1187 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1188 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1189
1190 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1191 enum pipe pipe, bool state)
1192 {
1193 u32 val;
1194 bool cur_state;
1195
1196 val = I915_READ(FDI_RX_CTL(pipe));
1197 cur_state = !!(val & FDI_RX_ENABLE);
1198 I915_STATE_WARN(cur_state != state,
1199 "FDI RX state assertion failure (expected %s, current %s)\n",
1200 onoff(state), onoff(cur_state));
1201 }
1202 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1203 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1204
1205 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1206 enum pipe pipe)
1207 {
1208 u32 val;
1209
1210 /* ILK FDI PLL is always enabled */
1211 if (IS_GEN5(dev_priv))
1212 return;
1213
1214 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1215 if (HAS_DDI(dev_priv))
1216 return;
1217
1218 val = I915_READ(FDI_TX_CTL(pipe));
1219 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1220 }
1221
1222 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1223 enum pipe pipe, bool state)
1224 {
1225 u32 val;
1226 bool cur_state;
1227
1228 val = I915_READ(FDI_RX_CTL(pipe));
1229 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1230 I915_STATE_WARN(cur_state != state,
1231 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1232 onoff(state), onoff(cur_state));
1233 }
1234
1235 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1236 enum pipe pipe)
1237 {
1238 struct drm_device *dev = dev_priv->dev;
1239 i915_reg_t pp_reg;
1240 u32 val;
1241 enum pipe panel_pipe = PIPE_A;
1242 bool locked = true;
1243
1244 if (WARN_ON(HAS_DDI(dev)))
1245 return;
1246
1247 if (HAS_PCH_SPLIT(dev)) {
1248 u32 port_sel;
1249
1250 pp_reg = PCH_PP_CONTROL;
1251 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1252
1253 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1254 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1255 panel_pipe = PIPE_B;
1256 /* XXX: else fix for eDP */
1257 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1258 /* presumably write lock depends on pipe, not port select */
1259 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1260 panel_pipe = pipe;
1261 } else {
1262 pp_reg = PP_CONTROL;
1263 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1264 panel_pipe = PIPE_B;
1265 }
1266
1267 val = I915_READ(pp_reg);
1268 if (!(val & PANEL_POWER_ON) ||
1269 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1270 locked = false;
1271
1272 I915_STATE_WARN(panel_pipe == pipe && locked,
1273 "panel assertion failure, pipe %c regs locked\n",
1274 pipe_name(pipe));
1275 }
1276
1277 static void assert_cursor(struct drm_i915_private *dev_priv,
1278 enum pipe pipe, bool state)
1279 {
1280 struct drm_device *dev = dev_priv->dev;
1281 bool cur_state;
1282
1283 if (IS_845G(dev) || IS_I865G(dev))
1284 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1285 else
1286 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1287
1288 I915_STATE_WARN(cur_state != state,
1289 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1290 pipe_name(pipe), onoff(state), onoff(cur_state));
1291 }
1292 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1293 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1294
1295 void assert_pipe(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, bool state)
1297 {
1298 bool cur_state;
1299 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1300 pipe);
1301 enum intel_display_power_domain power_domain;
1302
1303 /* if we need the pipe quirk it must be always on */
1304 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1305 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1306 state = true;
1307
1308 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1309 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1310 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1311 cur_state = !!(val & PIPECONF_ENABLE);
1312
1313 intel_display_power_put(dev_priv, power_domain);
1314 } else {
1315 cur_state = false;
1316 }
1317
1318 I915_STATE_WARN(cur_state != state,
1319 "pipe %c assertion failure (expected %s, current %s)\n",
1320 pipe_name(pipe), onoff(state), onoff(cur_state));
1321 }
1322
1323 static void assert_plane(struct drm_i915_private *dev_priv,
1324 enum plane plane, bool state)
1325 {
1326 u32 val;
1327 bool cur_state;
1328
1329 val = I915_READ(DSPCNTR(plane));
1330 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1331 I915_STATE_WARN(cur_state != state,
1332 "plane %c assertion failure (expected %s, current %s)\n",
1333 plane_name(plane), onoff(state), onoff(cur_state));
1334 }
1335
1336 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1337 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1338
1339 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341 {
1342 struct drm_device *dev = dev_priv->dev;
1343 int i;
1344
1345 /* Primary planes are fixed to pipes on gen4+ */
1346 if (INTEL_INFO(dev)->gen >= 4) {
1347 u32 val = I915_READ(DSPCNTR(pipe));
1348 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1349 "plane %c assertion failure, should be disabled but not\n",
1350 plane_name(pipe));
1351 return;
1352 }
1353
1354 /* Need to check both planes against the pipe */
1355 for_each_pipe(dev_priv, i) {
1356 u32 val = I915_READ(DSPCNTR(i));
1357 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1358 DISPPLANE_SEL_PIPE_SHIFT;
1359 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1360 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1361 plane_name(i), pipe_name(pipe));
1362 }
1363 }
1364
1365 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe)
1367 {
1368 struct drm_device *dev = dev_priv->dev;
1369 int sprite;
1370
1371 if (INTEL_INFO(dev)->gen >= 9) {
1372 for_each_sprite(dev_priv, pipe, sprite) {
1373 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1374 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1375 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1376 sprite, pipe_name(pipe));
1377 }
1378 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1379 for_each_sprite(dev_priv, pipe, sprite) {
1380 u32 val = I915_READ(SPCNTR(pipe, sprite));
1381 I915_STATE_WARN(val & SP_ENABLE,
1382 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1383 sprite_name(pipe, sprite), pipe_name(pipe));
1384 }
1385 } else if (INTEL_INFO(dev)->gen >= 7) {
1386 u32 val = I915_READ(SPRCTL(pipe));
1387 I915_STATE_WARN(val & SPRITE_ENABLE,
1388 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(pipe), pipe_name(pipe));
1390 } else if (INTEL_INFO(dev)->gen >= 5) {
1391 u32 val = I915_READ(DVSCNTR(pipe));
1392 I915_STATE_WARN(val & DVS_ENABLE,
1393 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1394 plane_name(pipe), pipe_name(pipe));
1395 }
1396 }
1397
1398 static void assert_vblank_disabled(struct drm_crtc *crtc)
1399 {
1400 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1401 drm_crtc_vblank_put(crtc);
1402 }
1403
1404 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe)
1406 {
1407 u32 val;
1408 bool enabled;
1409
1410 val = I915_READ(PCH_TRANSCONF(pipe));
1411 enabled = !!(val & TRANS_ENABLE);
1412 I915_STATE_WARN(enabled,
1413 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1414 pipe_name(pipe));
1415 }
1416
1417 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1418 enum pipe pipe, u32 port_sel, u32 val)
1419 {
1420 if ((val & DP_PORT_EN) == 0)
1421 return false;
1422
1423 if (HAS_PCH_CPT(dev_priv)) {
1424 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1425 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1426 return false;
1427 } else if (IS_CHERRYVIEW(dev_priv)) {
1428 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1429 return false;
1430 } else {
1431 if ((val & DP_PIPE_MASK) != (pipe << 30))
1432 return false;
1433 }
1434 return true;
1435 }
1436
1437 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, u32 val)
1439 {
1440 if ((val & SDVO_ENABLE) == 0)
1441 return false;
1442
1443 if (HAS_PCH_CPT(dev_priv)) {
1444 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1445 return false;
1446 } else if (IS_CHERRYVIEW(dev_priv)) {
1447 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1448 return false;
1449 } else {
1450 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1451 return false;
1452 }
1453 return true;
1454 }
1455
1456 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, u32 val)
1458 {
1459 if ((val & LVDS_PORT_EN) == 0)
1460 return false;
1461
1462 if (HAS_PCH_CPT(dev_priv)) {
1463 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1464 return false;
1465 } else {
1466 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1467 return false;
1468 }
1469 return true;
1470 }
1471
1472 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1473 enum pipe pipe, u32 val)
1474 {
1475 if ((val & ADPA_DAC_ENABLE) == 0)
1476 return false;
1477 if (HAS_PCH_CPT(dev_priv)) {
1478 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1479 return false;
1480 } else {
1481 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1482 return false;
1483 }
1484 return true;
1485 }
1486
1487 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1488 enum pipe pipe, i915_reg_t reg,
1489 u32 port_sel)
1490 {
1491 u32 val = I915_READ(reg);
1492 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1493 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1494 i915_mmio_reg_offset(reg), pipe_name(pipe));
1495
1496 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1497 && (val & DP_PIPEB_SELECT),
1498 "IBX PCH dp port still using transcoder B\n");
1499 }
1500
1501 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1502 enum pipe pipe, i915_reg_t reg)
1503 {
1504 u32 val = I915_READ(reg);
1505 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1506 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1507 i915_mmio_reg_offset(reg), pipe_name(pipe));
1508
1509 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1510 && (val & SDVO_PIPE_B_SELECT),
1511 "IBX PCH hdmi port still using transcoder B\n");
1512 }
1513
1514 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1515 enum pipe pipe)
1516 {
1517 u32 val;
1518
1519 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1520 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1521 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1522
1523 val = I915_READ(PCH_ADPA);
1524 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1525 "PCH VGA enabled on transcoder %c, should be disabled\n",
1526 pipe_name(pipe));
1527
1528 val = I915_READ(PCH_LVDS);
1529 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1530 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1531 pipe_name(pipe));
1532
1533 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1534 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1535 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1536 }
1537
1538 static void _vlv_enable_pll(struct intel_crtc *crtc,
1539 const struct intel_crtc_state *pipe_config)
1540 {
1541 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1542 enum pipe pipe = crtc->pipe;
1543
1544 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1545 POSTING_READ(DPLL(pipe));
1546 udelay(150);
1547
1548 if (intel_wait_for_register(dev_priv,
1549 DPLL(pipe),
1550 DPLL_LOCK_VLV,
1551 DPLL_LOCK_VLV,
1552 1))
1553 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1554 }
1555
1556 static void vlv_enable_pll(struct intel_crtc *crtc,
1557 const struct intel_crtc_state *pipe_config)
1558 {
1559 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1560 enum pipe pipe = crtc->pipe;
1561
1562 assert_pipe_disabled(dev_priv, pipe);
1563
1564 /* PLL is protected by panel, make sure we can write it */
1565 assert_panel_unlocked(dev_priv, pipe);
1566
1567 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1568 _vlv_enable_pll(crtc, pipe_config);
1569
1570 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1571 POSTING_READ(DPLL_MD(pipe));
1572 }
1573
1574
1575 static void _chv_enable_pll(struct intel_crtc *crtc,
1576 const struct intel_crtc_state *pipe_config)
1577 {
1578 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1579 enum pipe pipe = crtc->pipe;
1580 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1581 u32 tmp;
1582
1583 mutex_lock(&dev_priv->sb_lock);
1584
1585 /* Enable back the 10bit clock to display controller */
1586 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1587 tmp |= DPIO_DCLKP_EN;
1588 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1589
1590 mutex_unlock(&dev_priv->sb_lock);
1591
1592 /*
1593 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1594 */
1595 udelay(1);
1596
1597 /* Enable PLL */
1598 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1599
1600 /* Check PLL is locked */
1601 if (intel_wait_for_register(dev_priv,
1602 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1603 1))
1604 DRM_ERROR("PLL %d failed to lock\n", pipe);
1605 }
1606
1607 static void chv_enable_pll(struct intel_crtc *crtc,
1608 const struct intel_crtc_state *pipe_config)
1609 {
1610 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1611 enum pipe pipe = crtc->pipe;
1612
1613 assert_pipe_disabled(dev_priv, pipe);
1614
1615 /* PLL is protected by panel, make sure we can write it */
1616 assert_panel_unlocked(dev_priv, pipe);
1617
1618 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1619 _chv_enable_pll(crtc, pipe_config);
1620
1621 if (pipe != PIPE_A) {
1622 /*
1623 * WaPixelRepeatModeFixForC0:chv
1624 *
1625 * DPLLCMD is AWOL. Use chicken bits to propagate
1626 * the value from DPLLBMD to either pipe B or C.
1627 */
1628 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1629 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1630 I915_WRITE(CBR4_VLV, 0);
1631 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1632
1633 /*
1634 * DPLLB VGA mode also seems to cause problems.
1635 * We should always have it disabled.
1636 */
1637 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1638 } else {
1639 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1640 POSTING_READ(DPLL_MD(pipe));
1641 }
1642 }
1643
1644 static int intel_num_dvo_pipes(struct drm_device *dev)
1645 {
1646 struct intel_crtc *crtc;
1647 int count = 0;
1648
1649 for_each_intel_crtc(dev, crtc)
1650 count += crtc->base.state->active &&
1651 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1652
1653 return count;
1654 }
1655
1656 static void i9xx_enable_pll(struct intel_crtc *crtc)
1657 {
1658 struct drm_device *dev = crtc->base.dev;
1659 struct drm_i915_private *dev_priv = to_i915(dev);
1660 i915_reg_t reg = DPLL(crtc->pipe);
1661 u32 dpll = crtc->config->dpll_hw_state.dpll;
1662
1663 assert_pipe_disabled(dev_priv, crtc->pipe);
1664
1665 /* PLL is protected by panel, make sure we can write it */
1666 if (IS_MOBILE(dev) && !IS_I830(dev))
1667 assert_panel_unlocked(dev_priv, crtc->pipe);
1668
1669 /* Enable DVO 2x clock on both PLLs if necessary */
1670 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1671 /*
1672 * It appears to be important that we don't enable this
1673 * for the current pipe before otherwise configuring the
1674 * PLL. No idea how this should be handled if multiple
1675 * DVO outputs are enabled simultaneosly.
1676 */
1677 dpll |= DPLL_DVO_2X_MODE;
1678 I915_WRITE(DPLL(!crtc->pipe),
1679 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1680 }
1681
1682 /*
1683 * Apparently we need to have VGA mode enabled prior to changing
1684 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1685 * dividers, even though the register value does change.
1686 */
1687 I915_WRITE(reg, 0);
1688
1689 I915_WRITE(reg, dpll);
1690
1691 /* Wait for the clocks to stabilize. */
1692 POSTING_READ(reg);
1693 udelay(150);
1694
1695 if (INTEL_INFO(dev)->gen >= 4) {
1696 I915_WRITE(DPLL_MD(crtc->pipe),
1697 crtc->config->dpll_hw_state.dpll_md);
1698 } else {
1699 /* The pixel multiplier can only be updated once the
1700 * DPLL is enabled and the clocks are stable.
1701 *
1702 * So write it again.
1703 */
1704 I915_WRITE(reg, dpll);
1705 }
1706
1707 /* We do this three times for luck */
1708 I915_WRITE(reg, dpll);
1709 POSTING_READ(reg);
1710 udelay(150); /* wait for warmup */
1711 I915_WRITE(reg, dpll);
1712 POSTING_READ(reg);
1713 udelay(150); /* wait for warmup */
1714 I915_WRITE(reg, dpll);
1715 POSTING_READ(reg);
1716 udelay(150); /* wait for warmup */
1717 }
1718
1719 /**
1720 * i9xx_disable_pll - disable a PLL
1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe PLL to disable
1723 *
1724 * Disable the PLL for @pipe, making sure the pipe is off first.
1725 *
1726 * Note! This is for pre-ILK only.
1727 */
1728 static void i9xx_disable_pll(struct intel_crtc *crtc)
1729 {
1730 struct drm_device *dev = crtc->base.dev;
1731 struct drm_i915_private *dev_priv = to_i915(dev);
1732 enum pipe pipe = crtc->pipe;
1733
1734 /* Disable DVO 2x clock on both PLLs if necessary */
1735 if (IS_I830(dev) &&
1736 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1737 !intel_num_dvo_pipes(dev)) {
1738 I915_WRITE(DPLL(PIPE_B),
1739 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1740 I915_WRITE(DPLL(PIPE_A),
1741 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1742 }
1743
1744 /* Don't disable pipe or pipe PLLs if needed */
1745 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1746 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1747 return;
1748
1749 /* Make sure the pipe isn't still relying on us */
1750 assert_pipe_disabled(dev_priv, pipe);
1751
1752 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1753 POSTING_READ(DPLL(pipe));
1754 }
1755
1756 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1757 {
1758 u32 val;
1759
1760 /* Make sure the pipe isn't still relying on us */
1761 assert_pipe_disabled(dev_priv, pipe);
1762
1763 val = DPLL_INTEGRATED_REF_CLK_VLV |
1764 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1765 if (pipe != PIPE_A)
1766 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1767
1768 I915_WRITE(DPLL(pipe), val);
1769 POSTING_READ(DPLL(pipe));
1770 }
1771
1772 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1773 {
1774 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1775 u32 val;
1776
1777 /* Make sure the pipe isn't still relying on us */
1778 assert_pipe_disabled(dev_priv, pipe);
1779
1780 val = DPLL_SSC_REF_CLK_CHV |
1781 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1782 if (pipe != PIPE_A)
1783 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1784
1785 I915_WRITE(DPLL(pipe), val);
1786 POSTING_READ(DPLL(pipe));
1787
1788 mutex_lock(&dev_priv->sb_lock);
1789
1790 /* Disable 10bit clock to display controller */
1791 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1792 val &= ~DPIO_DCLKP_EN;
1793 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1794
1795 mutex_unlock(&dev_priv->sb_lock);
1796 }
1797
1798 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1799 struct intel_digital_port *dport,
1800 unsigned int expected_mask)
1801 {
1802 u32 port_mask;
1803 i915_reg_t dpll_reg;
1804
1805 switch (dport->port) {
1806 case PORT_B:
1807 port_mask = DPLL_PORTB_READY_MASK;
1808 dpll_reg = DPLL(0);
1809 break;
1810 case PORT_C:
1811 port_mask = DPLL_PORTC_READY_MASK;
1812 dpll_reg = DPLL(0);
1813 expected_mask <<= 4;
1814 break;
1815 case PORT_D:
1816 port_mask = DPLL_PORTD_READY_MASK;
1817 dpll_reg = DPIO_PHY_STATUS;
1818 break;
1819 default:
1820 BUG();
1821 }
1822
1823 if (intel_wait_for_register(dev_priv,
1824 dpll_reg, port_mask, expected_mask,
1825 1000))
1826 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1827 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1828 }
1829
1830 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1831 enum pipe pipe)
1832 {
1833 struct drm_device *dev = dev_priv->dev;
1834 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1836 i915_reg_t reg;
1837 uint32_t val, pipeconf_val;
1838
1839 /* Make sure PCH DPLL is enabled */
1840 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1841
1842 /* FDI must be feeding us bits for PCH ports */
1843 assert_fdi_tx_enabled(dev_priv, pipe);
1844 assert_fdi_rx_enabled(dev_priv, pipe);
1845
1846 if (HAS_PCH_CPT(dev)) {
1847 /* Workaround: Set the timing override bit before enabling the
1848 * pch transcoder. */
1849 reg = TRANS_CHICKEN2(pipe);
1850 val = I915_READ(reg);
1851 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1852 I915_WRITE(reg, val);
1853 }
1854
1855 reg = PCH_TRANSCONF(pipe);
1856 val = I915_READ(reg);
1857 pipeconf_val = I915_READ(PIPECONF(pipe));
1858
1859 if (HAS_PCH_IBX(dev_priv)) {
1860 /*
1861 * Make the BPC in transcoder be consistent with
1862 * that in pipeconf reg. For HDMI we must use 8bpc
1863 * here for both 8bpc and 12bpc.
1864 */
1865 val &= ~PIPECONF_BPC_MASK;
1866 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1867 val |= PIPECONF_8BPC;
1868 else
1869 val |= pipeconf_val & PIPECONF_BPC_MASK;
1870 }
1871
1872 val &= ~TRANS_INTERLACE_MASK;
1873 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1874 if (HAS_PCH_IBX(dev_priv) &&
1875 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1876 val |= TRANS_LEGACY_INTERLACED_ILK;
1877 else
1878 val |= TRANS_INTERLACED;
1879 else
1880 val |= TRANS_PROGRESSIVE;
1881
1882 I915_WRITE(reg, val | TRANS_ENABLE);
1883 if (intel_wait_for_register(dev_priv,
1884 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1885 100))
1886 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1887 }
1888
1889 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1890 enum transcoder cpu_transcoder)
1891 {
1892 u32 val, pipeconf_val;
1893
1894 /* FDI must be feeding us bits for PCH ports */
1895 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1896 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1897
1898 /* Workaround: set timing override bit. */
1899 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1900 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1901 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1902
1903 val = TRANS_ENABLE;
1904 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1905
1906 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1907 PIPECONF_INTERLACED_ILK)
1908 val |= TRANS_INTERLACED;
1909 else
1910 val |= TRANS_PROGRESSIVE;
1911
1912 I915_WRITE(LPT_TRANSCONF, val);
1913 if (intel_wait_for_register(dev_priv,
1914 LPT_TRANSCONF,
1915 TRANS_STATE_ENABLE,
1916 TRANS_STATE_ENABLE,
1917 100))
1918 DRM_ERROR("Failed to enable PCH transcoder\n");
1919 }
1920
1921 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1922 enum pipe pipe)
1923 {
1924 struct drm_device *dev = dev_priv->dev;
1925 i915_reg_t reg;
1926 uint32_t val;
1927
1928 /* FDI relies on the transcoder */
1929 assert_fdi_tx_disabled(dev_priv, pipe);
1930 assert_fdi_rx_disabled(dev_priv, pipe);
1931
1932 /* Ports must be off as well */
1933 assert_pch_ports_disabled(dev_priv, pipe);
1934
1935 reg = PCH_TRANSCONF(pipe);
1936 val = I915_READ(reg);
1937 val &= ~TRANS_ENABLE;
1938 I915_WRITE(reg, val);
1939 /* wait for PCH transcoder off, transcoder state */
1940 if (intel_wait_for_register(dev_priv,
1941 reg, TRANS_STATE_ENABLE, 0,
1942 50))
1943 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1944
1945 if (HAS_PCH_CPT(dev)) {
1946 /* Workaround: Clear the timing override chicken bit again. */
1947 reg = TRANS_CHICKEN2(pipe);
1948 val = I915_READ(reg);
1949 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1950 I915_WRITE(reg, val);
1951 }
1952 }
1953
1954 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1955 {
1956 u32 val;
1957
1958 val = I915_READ(LPT_TRANSCONF);
1959 val &= ~TRANS_ENABLE;
1960 I915_WRITE(LPT_TRANSCONF, val);
1961 /* wait for PCH transcoder off, transcoder state */
1962 if (intel_wait_for_register(dev_priv,
1963 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1964 50))
1965 DRM_ERROR("Failed to disable PCH transcoder\n");
1966
1967 /* Workaround: clear timing override bit. */
1968 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1969 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1970 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1971 }
1972
1973 /**
1974 * intel_enable_pipe - enable a pipe, asserting requirements
1975 * @crtc: crtc responsible for the pipe
1976 *
1977 * Enable @crtc's pipe, making sure that various hardware specific requirements
1978 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1979 */
1980 static void intel_enable_pipe(struct intel_crtc *crtc)
1981 {
1982 struct drm_device *dev = crtc->base.dev;
1983 struct drm_i915_private *dev_priv = to_i915(dev);
1984 enum pipe pipe = crtc->pipe;
1985 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1986 enum pipe pch_transcoder;
1987 i915_reg_t reg;
1988 u32 val;
1989
1990 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1991
1992 assert_planes_disabled(dev_priv, pipe);
1993 assert_cursor_disabled(dev_priv, pipe);
1994 assert_sprites_disabled(dev_priv, pipe);
1995
1996 if (HAS_PCH_LPT(dev_priv))
1997 pch_transcoder = TRANSCODER_A;
1998 else
1999 pch_transcoder = pipe;
2000
2001 /*
2002 * A pipe without a PLL won't actually be able to drive bits from
2003 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2004 * need the check.
2005 */
2006 if (HAS_GMCH_DISPLAY(dev_priv))
2007 if (crtc->config->has_dsi_encoder)
2008 assert_dsi_pll_enabled(dev_priv);
2009 else
2010 assert_pll_enabled(dev_priv, pipe);
2011 else {
2012 if (crtc->config->has_pch_encoder) {
2013 /* if driving the PCH, we need FDI enabled */
2014 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2015 assert_fdi_tx_pll_enabled(dev_priv,
2016 (enum pipe) cpu_transcoder);
2017 }
2018 /* FIXME: assert CPU port conditions for SNB+ */
2019 }
2020
2021 reg = PIPECONF(cpu_transcoder);
2022 val = I915_READ(reg);
2023 if (val & PIPECONF_ENABLE) {
2024 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2025 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2026 return;
2027 }
2028
2029 I915_WRITE(reg, val | PIPECONF_ENABLE);
2030 POSTING_READ(reg);
2031
2032 /*
2033 * Until the pipe starts DSL will read as 0, which would cause
2034 * an apparent vblank timestamp jump, which messes up also the
2035 * frame count when it's derived from the timestamps. So let's
2036 * wait for the pipe to start properly before we call
2037 * drm_crtc_vblank_on()
2038 */
2039 if (dev->max_vblank_count == 0 &&
2040 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2041 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2042 }
2043
2044 /**
2045 * intel_disable_pipe - disable a pipe, asserting requirements
2046 * @crtc: crtc whose pipes is to be disabled
2047 *
2048 * Disable the pipe of @crtc, making sure that various hardware
2049 * specific requirements are met, if applicable, e.g. plane
2050 * disabled, panel fitter off, etc.
2051 *
2052 * Will wait until the pipe has shut down before returning.
2053 */
2054 static void intel_disable_pipe(struct intel_crtc *crtc)
2055 {
2056 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2057 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2058 enum pipe pipe = crtc->pipe;
2059 i915_reg_t reg;
2060 u32 val;
2061
2062 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2063
2064 /*
2065 * Make sure planes won't keep trying to pump pixels to us,
2066 * or we might hang the display.
2067 */
2068 assert_planes_disabled(dev_priv, pipe);
2069 assert_cursor_disabled(dev_priv, pipe);
2070 assert_sprites_disabled(dev_priv, pipe);
2071
2072 reg = PIPECONF(cpu_transcoder);
2073 val = I915_READ(reg);
2074 if ((val & PIPECONF_ENABLE) == 0)
2075 return;
2076
2077 /*
2078 * Double wide has implications for planes
2079 * so best keep it disabled when not needed.
2080 */
2081 if (crtc->config->double_wide)
2082 val &= ~PIPECONF_DOUBLE_WIDE;
2083
2084 /* Don't disable pipe or pipe PLLs if needed */
2085 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2086 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2087 val &= ~PIPECONF_ENABLE;
2088
2089 I915_WRITE(reg, val);
2090 if ((val & PIPECONF_ENABLE) == 0)
2091 intel_wait_for_pipe_off(crtc);
2092 }
2093
2094 static bool need_vtd_wa(struct drm_device *dev)
2095 {
2096 #ifdef CONFIG_INTEL_IOMMU
2097 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2098 return true;
2099 #endif
2100 return false;
2101 }
2102
2103 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2104 {
2105 return IS_GEN2(dev_priv) ? 2048 : 4096;
2106 }
2107
2108 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2109 uint64_t fb_modifier, unsigned int cpp)
2110 {
2111 switch (fb_modifier) {
2112 case DRM_FORMAT_MOD_NONE:
2113 return cpp;
2114 case I915_FORMAT_MOD_X_TILED:
2115 if (IS_GEN2(dev_priv))
2116 return 128;
2117 else
2118 return 512;
2119 case I915_FORMAT_MOD_Y_TILED:
2120 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2121 return 128;
2122 else
2123 return 512;
2124 case I915_FORMAT_MOD_Yf_TILED:
2125 switch (cpp) {
2126 case 1:
2127 return 64;
2128 case 2:
2129 case 4:
2130 return 128;
2131 case 8:
2132 case 16:
2133 return 256;
2134 default:
2135 MISSING_CASE(cpp);
2136 return cpp;
2137 }
2138 break;
2139 default:
2140 MISSING_CASE(fb_modifier);
2141 return cpp;
2142 }
2143 }
2144
2145 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2146 uint64_t fb_modifier, unsigned int cpp)
2147 {
2148 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2149 return 1;
2150 else
2151 return intel_tile_size(dev_priv) /
2152 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2153 }
2154
2155 /* Return the tile dimensions in pixel units */
2156 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2157 unsigned int *tile_width,
2158 unsigned int *tile_height,
2159 uint64_t fb_modifier,
2160 unsigned int cpp)
2161 {
2162 unsigned int tile_width_bytes =
2163 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2164
2165 *tile_width = tile_width_bytes / cpp;
2166 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2167 }
2168
2169 unsigned int
2170 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2171 uint32_t pixel_format, uint64_t fb_modifier)
2172 {
2173 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2174 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2175
2176 return ALIGN(height, tile_height);
2177 }
2178
2179 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2180 {
2181 unsigned int size = 0;
2182 int i;
2183
2184 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2185 size += rot_info->plane[i].width * rot_info->plane[i].height;
2186
2187 return size;
2188 }
2189
2190 static void
2191 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2192 const struct drm_framebuffer *fb,
2193 unsigned int rotation)
2194 {
2195 if (intel_rotation_90_or_270(rotation)) {
2196 *view = i915_ggtt_view_rotated;
2197 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2198 } else {
2199 *view = i915_ggtt_view_normal;
2200 }
2201 }
2202
2203 static void
2204 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2205 struct drm_framebuffer *fb)
2206 {
2207 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2208 unsigned int tile_size, tile_width, tile_height, cpp;
2209
2210 tile_size = intel_tile_size(dev_priv);
2211
2212 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2213 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2214 fb->modifier[0], cpp);
2215
2216 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2217 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2218
2219 if (info->pixel_format == DRM_FORMAT_NV12) {
2220 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2221 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2222 fb->modifier[1], cpp);
2223
2224 info->uv_offset = fb->offsets[1];
2225 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2226 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2227 }
2228 }
2229
2230 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2231 {
2232 if (INTEL_INFO(dev_priv)->gen >= 9)
2233 return 256 * 1024;
2234 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2235 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2236 return 128 * 1024;
2237 else if (INTEL_INFO(dev_priv)->gen >= 4)
2238 return 4 * 1024;
2239 else
2240 return 0;
2241 }
2242
2243 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2244 uint64_t fb_modifier)
2245 {
2246 switch (fb_modifier) {
2247 case DRM_FORMAT_MOD_NONE:
2248 return intel_linear_alignment(dev_priv);
2249 case I915_FORMAT_MOD_X_TILED:
2250 if (INTEL_INFO(dev_priv)->gen >= 9)
2251 return 256 * 1024;
2252 return 0;
2253 case I915_FORMAT_MOD_Y_TILED:
2254 case I915_FORMAT_MOD_Yf_TILED:
2255 return 1 * 1024 * 1024;
2256 default:
2257 MISSING_CASE(fb_modifier);
2258 return 0;
2259 }
2260 }
2261
2262 int
2263 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2264 unsigned int rotation)
2265 {
2266 struct drm_device *dev = fb->dev;
2267 struct drm_i915_private *dev_priv = to_i915(dev);
2268 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2269 struct i915_ggtt_view view;
2270 u32 alignment;
2271 int ret;
2272
2273 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2274
2275 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2276
2277 intel_fill_fb_ggtt_view(&view, fb, rotation);
2278
2279 /* Note that the w/a also requires 64 PTE of padding following the
2280 * bo. We currently fill all unused PTE with the shadow page and so
2281 * we should always have valid PTE following the scanout preventing
2282 * the VT-d warning.
2283 */
2284 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2285 alignment = 256 * 1024;
2286
2287 /*
2288 * Global gtt pte registers are special registers which actually forward
2289 * writes to a chunk of system memory. Which means that there is no risk
2290 * that the register values disappear as soon as we call
2291 * intel_runtime_pm_put(), so it is correct to wrap only the
2292 * pin/unpin/fence and not more.
2293 */
2294 intel_runtime_pm_get(dev_priv);
2295
2296 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2297 &view);
2298 if (ret)
2299 goto err_pm;
2300
2301 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2302 * fence, whereas 965+ only requires a fence if using
2303 * framebuffer compression. For simplicity, we always install
2304 * a fence as the cost is not that onerous.
2305 */
2306 if (view.type == I915_GGTT_VIEW_NORMAL) {
2307 ret = i915_gem_object_get_fence(obj);
2308 if (ret == -EDEADLK) {
2309 /*
2310 * -EDEADLK means there are no free fences
2311 * no pending flips.
2312 *
2313 * This is propagated to atomic, but it uses
2314 * -EDEADLK to force a locking recovery, so
2315 * change the returned error to -EBUSY.
2316 */
2317 ret = -EBUSY;
2318 goto err_unpin;
2319 } else if (ret)
2320 goto err_unpin;
2321
2322 i915_gem_object_pin_fence(obj);
2323 }
2324
2325 intel_runtime_pm_put(dev_priv);
2326 return 0;
2327
2328 err_unpin:
2329 i915_gem_object_unpin_from_display_plane(obj, &view);
2330 err_pm:
2331 intel_runtime_pm_put(dev_priv);
2332 return ret;
2333 }
2334
2335 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2336 {
2337 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2338 struct i915_ggtt_view view;
2339
2340 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2341
2342 intel_fill_fb_ggtt_view(&view, fb, rotation);
2343
2344 if (view.type == I915_GGTT_VIEW_NORMAL)
2345 i915_gem_object_unpin_fence(obj);
2346
2347 i915_gem_object_unpin_from_display_plane(obj, &view);
2348 }
2349
2350 /*
2351 * Adjust the tile offset by moving the difference into
2352 * the x/y offsets.
2353 *
2354 * Input tile dimensions and pitch must already be
2355 * rotated to match x and y, and in pixel units.
2356 */
2357 static u32 intel_adjust_tile_offset(int *x, int *y,
2358 unsigned int tile_width,
2359 unsigned int tile_height,
2360 unsigned int tile_size,
2361 unsigned int pitch_tiles,
2362 u32 old_offset,
2363 u32 new_offset)
2364 {
2365 unsigned int tiles;
2366
2367 WARN_ON(old_offset & (tile_size - 1));
2368 WARN_ON(new_offset & (tile_size - 1));
2369 WARN_ON(new_offset > old_offset);
2370
2371 tiles = (old_offset - new_offset) / tile_size;
2372
2373 *y += tiles / pitch_tiles * tile_height;
2374 *x += tiles % pitch_tiles * tile_width;
2375
2376 return new_offset;
2377 }
2378
2379 /*
2380 * Computes the linear offset to the base tile and adjusts
2381 * x, y. bytes per pixel is assumed to be a power-of-two.
2382 *
2383 * In the 90/270 rotated case, x and y are assumed
2384 * to be already rotated to match the rotated GTT view, and
2385 * pitch is the tile_height aligned framebuffer height.
2386 */
2387 u32 intel_compute_tile_offset(int *x, int *y,
2388 const struct drm_framebuffer *fb, int plane,
2389 unsigned int pitch,
2390 unsigned int rotation)
2391 {
2392 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2393 uint64_t fb_modifier = fb->modifier[plane];
2394 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2395 u32 offset, offset_aligned, alignment;
2396
2397 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2398 if (alignment)
2399 alignment--;
2400
2401 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2402 unsigned int tile_size, tile_width, tile_height;
2403 unsigned int tile_rows, tiles, pitch_tiles;
2404
2405 tile_size = intel_tile_size(dev_priv);
2406 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2407 fb_modifier, cpp);
2408
2409 if (intel_rotation_90_or_270(rotation)) {
2410 pitch_tiles = pitch / tile_height;
2411 swap(tile_width, tile_height);
2412 } else {
2413 pitch_tiles = pitch / (tile_width * cpp);
2414 }
2415
2416 tile_rows = *y / tile_height;
2417 *y %= tile_height;
2418
2419 tiles = *x / tile_width;
2420 *x %= tile_width;
2421
2422 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2423 offset_aligned = offset & ~alignment;
2424
2425 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2426 tile_size, pitch_tiles,
2427 offset, offset_aligned);
2428 } else {
2429 offset = *y * pitch + *x * cpp;
2430 offset_aligned = offset & ~alignment;
2431
2432 *y = (offset & alignment) / pitch;
2433 *x = ((offset & alignment) - *y * pitch) / cpp;
2434 }
2435
2436 return offset_aligned;
2437 }
2438
2439 static int i9xx_format_to_fourcc(int format)
2440 {
2441 switch (format) {
2442 case DISPPLANE_8BPP:
2443 return DRM_FORMAT_C8;
2444 case DISPPLANE_BGRX555:
2445 return DRM_FORMAT_XRGB1555;
2446 case DISPPLANE_BGRX565:
2447 return DRM_FORMAT_RGB565;
2448 default:
2449 case DISPPLANE_BGRX888:
2450 return DRM_FORMAT_XRGB8888;
2451 case DISPPLANE_RGBX888:
2452 return DRM_FORMAT_XBGR8888;
2453 case DISPPLANE_BGRX101010:
2454 return DRM_FORMAT_XRGB2101010;
2455 case DISPPLANE_RGBX101010:
2456 return DRM_FORMAT_XBGR2101010;
2457 }
2458 }
2459
2460 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2461 {
2462 switch (format) {
2463 case PLANE_CTL_FORMAT_RGB_565:
2464 return DRM_FORMAT_RGB565;
2465 default:
2466 case PLANE_CTL_FORMAT_XRGB_8888:
2467 if (rgb_order) {
2468 if (alpha)
2469 return DRM_FORMAT_ABGR8888;
2470 else
2471 return DRM_FORMAT_XBGR8888;
2472 } else {
2473 if (alpha)
2474 return DRM_FORMAT_ARGB8888;
2475 else
2476 return DRM_FORMAT_XRGB8888;
2477 }
2478 case PLANE_CTL_FORMAT_XRGB_2101010:
2479 if (rgb_order)
2480 return DRM_FORMAT_XBGR2101010;
2481 else
2482 return DRM_FORMAT_XRGB2101010;
2483 }
2484 }
2485
2486 static bool
2487 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2488 struct intel_initial_plane_config *plane_config)
2489 {
2490 struct drm_device *dev = crtc->base.dev;
2491 struct drm_i915_private *dev_priv = to_i915(dev);
2492 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2493 struct drm_i915_gem_object *obj = NULL;
2494 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2495 struct drm_framebuffer *fb = &plane_config->fb->base;
2496 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2497 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2498 PAGE_SIZE);
2499
2500 size_aligned -= base_aligned;
2501
2502 if (plane_config->size == 0)
2503 return false;
2504
2505 /* If the FB is too big, just don't use it since fbdev is not very
2506 * important and we should probably use that space with FBC or other
2507 * features. */
2508 if (size_aligned * 2 > ggtt->stolen_usable_size)
2509 return false;
2510
2511 mutex_lock(&dev->struct_mutex);
2512
2513 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2514 base_aligned,
2515 base_aligned,
2516 size_aligned);
2517 if (!obj) {
2518 mutex_unlock(&dev->struct_mutex);
2519 return false;
2520 }
2521
2522 obj->tiling_mode = plane_config->tiling;
2523 if (obj->tiling_mode == I915_TILING_X)
2524 obj->stride = fb->pitches[0];
2525
2526 mode_cmd.pixel_format = fb->pixel_format;
2527 mode_cmd.width = fb->width;
2528 mode_cmd.height = fb->height;
2529 mode_cmd.pitches[0] = fb->pitches[0];
2530 mode_cmd.modifier[0] = fb->modifier[0];
2531 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2532
2533 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2534 &mode_cmd, obj)) {
2535 DRM_DEBUG_KMS("intel fb init failed\n");
2536 goto out_unref_obj;
2537 }
2538
2539 mutex_unlock(&dev->struct_mutex);
2540
2541 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2542 return true;
2543
2544 out_unref_obj:
2545 drm_gem_object_unreference(&obj->base);
2546 mutex_unlock(&dev->struct_mutex);
2547 return false;
2548 }
2549
2550 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2551 static void
2552 update_state_fb(struct drm_plane *plane)
2553 {
2554 if (plane->fb == plane->state->fb)
2555 return;
2556
2557 if (plane->state->fb)
2558 drm_framebuffer_unreference(plane->state->fb);
2559 plane->state->fb = plane->fb;
2560 if (plane->state->fb)
2561 drm_framebuffer_reference(plane->state->fb);
2562 }
2563
2564 static void
2565 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2566 struct intel_initial_plane_config *plane_config)
2567 {
2568 struct drm_device *dev = intel_crtc->base.dev;
2569 struct drm_i915_private *dev_priv = to_i915(dev);
2570 struct drm_crtc *c;
2571 struct intel_crtc *i;
2572 struct drm_i915_gem_object *obj;
2573 struct drm_plane *primary = intel_crtc->base.primary;
2574 struct drm_plane_state *plane_state = primary->state;
2575 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2576 struct intel_plane *intel_plane = to_intel_plane(primary);
2577 struct intel_plane_state *intel_state =
2578 to_intel_plane_state(plane_state);
2579 struct drm_framebuffer *fb;
2580
2581 if (!plane_config->fb)
2582 return;
2583
2584 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2585 fb = &plane_config->fb->base;
2586 goto valid_fb;
2587 }
2588
2589 kfree(plane_config->fb);
2590
2591 /*
2592 * Failed to alloc the obj, check to see if we should share
2593 * an fb with another CRTC instead
2594 */
2595 for_each_crtc(dev, c) {
2596 i = to_intel_crtc(c);
2597
2598 if (c == &intel_crtc->base)
2599 continue;
2600
2601 if (!i->active)
2602 continue;
2603
2604 fb = c->primary->fb;
2605 if (!fb)
2606 continue;
2607
2608 obj = intel_fb_obj(fb);
2609 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2610 drm_framebuffer_reference(fb);
2611 goto valid_fb;
2612 }
2613 }
2614
2615 /*
2616 * We've failed to reconstruct the BIOS FB. Current display state
2617 * indicates that the primary plane is visible, but has a NULL FB,
2618 * which will lead to problems later if we don't fix it up. The
2619 * simplest solution is to just disable the primary plane now and
2620 * pretend the BIOS never had it enabled.
2621 */
2622 to_intel_plane_state(plane_state)->visible = false;
2623 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2624 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2625 intel_plane->disable_plane(primary, &intel_crtc->base);
2626
2627 return;
2628
2629 valid_fb:
2630 plane_state->src_x = 0;
2631 plane_state->src_y = 0;
2632 plane_state->src_w = fb->width << 16;
2633 plane_state->src_h = fb->height << 16;
2634
2635 plane_state->crtc_x = 0;
2636 plane_state->crtc_y = 0;
2637 plane_state->crtc_w = fb->width;
2638 plane_state->crtc_h = fb->height;
2639
2640 intel_state->src.x1 = plane_state->src_x;
2641 intel_state->src.y1 = plane_state->src_y;
2642 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2643 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2644 intel_state->dst.x1 = plane_state->crtc_x;
2645 intel_state->dst.y1 = plane_state->crtc_y;
2646 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2647 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2648
2649 obj = intel_fb_obj(fb);
2650 if (obj->tiling_mode != I915_TILING_NONE)
2651 dev_priv->preserve_bios_swizzle = true;
2652
2653 drm_framebuffer_reference(fb);
2654 primary->fb = primary->state->fb = fb;
2655 primary->crtc = primary->state->crtc = &intel_crtc->base;
2656 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2657 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2658 }
2659
2660 static void i9xx_update_primary_plane(struct drm_plane *primary,
2661 const struct intel_crtc_state *crtc_state,
2662 const struct intel_plane_state *plane_state)
2663 {
2664 struct drm_device *dev = primary->dev;
2665 struct drm_i915_private *dev_priv = to_i915(dev);
2666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2667 struct drm_framebuffer *fb = plane_state->base.fb;
2668 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2669 int plane = intel_crtc->plane;
2670 u32 linear_offset;
2671 u32 dspcntr;
2672 i915_reg_t reg = DSPCNTR(plane);
2673 unsigned int rotation = plane_state->base.rotation;
2674 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2675 int x = plane_state->src.x1 >> 16;
2676 int y = plane_state->src.y1 >> 16;
2677
2678 dspcntr = DISPPLANE_GAMMA_ENABLE;
2679
2680 dspcntr |= DISPLAY_PLANE_ENABLE;
2681
2682 if (INTEL_INFO(dev)->gen < 4) {
2683 if (intel_crtc->pipe == PIPE_B)
2684 dspcntr |= DISPPLANE_SEL_PIPE_B;
2685
2686 /* pipesrc and dspsize control the size that is scaled from,
2687 * which should always be the user's requested size.
2688 */
2689 I915_WRITE(DSPSIZE(plane),
2690 ((crtc_state->pipe_src_h - 1) << 16) |
2691 (crtc_state->pipe_src_w - 1));
2692 I915_WRITE(DSPPOS(plane), 0);
2693 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2694 I915_WRITE(PRIMSIZE(plane),
2695 ((crtc_state->pipe_src_h - 1) << 16) |
2696 (crtc_state->pipe_src_w - 1));
2697 I915_WRITE(PRIMPOS(plane), 0);
2698 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2699 }
2700
2701 switch (fb->pixel_format) {
2702 case DRM_FORMAT_C8:
2703 dspcntr |= DISPPLANE_8BPP;
2704 break;
2705 case DRM_FORMAT_XRGB1555:
2706 dspcntr |= DISPPLANE_BGRX555;
2707 break;
2708 case DRM_FORMAT_RGB565:
2709 dspcntr |= DISPPLANE_BGRX565;
2710 break;
2711 case DRM_FORMAT_XRGB8888:
2712 dspcntr |= DISPPLANE_BGRX888;
2713 break;
2714 case DRM_FORMAT_XBGR8888:
2715 dspcntr |= DISPPLANE_RGBX888;
2716 break;
2717 case DRM_FORMAT_XRGB2101010:
2718 dspcntr |= DISPPLANE_BGRX101010;
2719 break;
2720 case DRM_FORMAT_XBGR2101010:
2721 dspcntr |= DISPPLANE_RGBX101010;
2722 break;
2723 default:
2724 BUG();
2725 }
2726
2727 if (INTEL_INFO(dev)->gen >= 4 &&
2728 obj->tiling_mode != I915_TILING_NONE)
2729 dspcntr |= DISPPLANE_TILED;
2730
2731 if (IS_G4X(dev))
2732 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2733
2734 linear_offset = y * fb->pitches[0] + x * cpp;
2735
2736 if (INTEL_INFO(dev)->gen >= 4) {
2737 intel_crtc->dspaddr_offset =
2738 intel_compute_tile_offset(&x, &y, fb, 0,
2739 fb->pitches[0], rotation);
2740 linear_offset -= intel_crtc->dspaddr_offset;
2741 } else {
2742 intel_crtc->dspaddr_offset = linear_offset;
2743 }
2744
2745 if (rotation == BIT(DRM_ROTATE_180)) {
2746 dspcntr |= DISPPLANE_ROTATE_180;
2747
2748 x += (crtc_state->pipe_src_w - 1);
2749 y += (crtc_state->pipe_src_h - 1);
2750
2751 /* Finding the last pixel of the last line of the display
2752 data and adding to linear_offset*/
2753 linear_offset +=
2754 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2755 (crtc_state->pipe_src_w - 1) * cpp;
2756 }
2757
2758 intel_crtc->adjusted_x = x;
2759 intel_crtc->adjusted_y = y;
2760
2761 I915_WRITE(reg, dspcntr);
2762
2763 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2764 if (INTEL_INFO(dev)->gen >= 4) {
2765 I915_WRITE(DSPSURF(plane),
2766 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2767 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2768 I915_WRITE(DSPLINOFF(plane), linear_offset);
2769 } else
2770 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2771 POSTING_READ(reg);
2772 }
2773
2774 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2775 struct drm_crtc *crtc)
2776 {
2777 struct drm_device *dev = crtc->dev;
2778 struct drm_i915_private *dev_priv = to_i915(dev);
2779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2780 int plane = intel_crtc->plane;
2781
2782 I915_WRITE(DSPCNTR(plane), 0);
2783 if (INTEL_INFO(dev_priv)->gen >= 4)
2784 I915_WRITE(DSPSURF(plane), 0);
2785 else
2786 I915_WRITE(DSPADDR(plane), 0);
2787 POSTING_READ(DSPCNTR(plane));
2788 }
2789
2790 static void ironlake_update_primary_plane(struct drm_plane *primary,
2791 const struct intel_crtc_state *crtc_state,
2792 const struct intel_plane_state *plane_state)
2793 {
2794 struct drm_device *dev = primary->dev;
2795 struct drm_i915_private *dev_priv = to_i915(dev);
2796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2797 struct drm_framebuffer *fb = plane_state->base.fb;
2798 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2799 int plane = intel_crtc->plane;
2800 u32 linear_offset;
2801 u32 dspcntr;
2802 i915_reg_t reg = DSPCNTR(plane);
2803 unsigned int rotation = plane_state->base.rotation;
2804 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2805 int x = plane_state->src.x1 >> 16;
2806 int y = plane_state->src.y1 >> 16;
2807
2808 dspcntr = DISPPLANE_GAMMA_ENABLE;
2809 dspcntr |= DISPLAY_PLANE_ENABLE;
2810
2811 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2812 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2813
2814 switch (fb->pixel_format) {
2815 case DRM_FORMAT_C8:
2816 dspcntr |= DISPPLANE_8BPP;
2817 break;
2818 case DRM_FORMAT_RGB565:
2819 dspcntr |= DISPPLANE_BGRX565;
2820 break;
2821 case DRM_FORMAT_XRGB8888:
2822 dspcntr |= DISPPLANE_BGRX888;
2823 break;
2824 case DRM_FORMAT_XBGR8888:
2825 dspcntr |= DISPPLANE_RGBX888;
2826 break;
2827 case DRM_FORMAT_XRGB2101010:
2828 dspcntr |= DISPPLANE_BGRX101010;
2829 break;
2830 case DRM_FORMAT_XBGR2101010:
2831 dspcntr |= DISPPLANE_RGBX101010;
2832 break;
2833 default:
2834 BUG();
2835 }
2836
2837 if (obj->tiling_mode != I915_TILING_NONE)
2838 dspcntr |= DISPPLANE_TILED;
2839
2840 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2841 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2842
2843 linear_offset = y * fb->pitches[0] + x * cpp;
2844 intel_crtc->dspaddr_offset =
2845 intel_compute_tile_offset(&x, &y, fb, 0,
2846 fb->pitches[0], rotation);
2847 linear_offset -= intel_crtc->dspaddr_offset;
2848 if (rotation == BIT(DRM_ROTATE_180)) {
2849 dspcntr |= DISPPLANE_ROTATE_180;
2850
2851 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2852 x += (crtc_state->pipe_src_w - 1);
2853 y += (crtc_state->pipe_src_h - 1);
2854
2855 /* Finding the last pixel of the last line of the display
2856 data and adding to linear_offset*/
2857 linear_offset +=
2858 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2859 (crtc_state->pipe_src_w - 1) * cpp;
2860 }
2861 }
2862
2863 intel_crtc->adjusted_x = x;
2864 intel_crtc->adjusted_y = y;
2865
2866 I915_WRITE(reg, dspcntr);
2867
2868 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2869 I915_WRITE(DSPSURF(plane),
2870 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2871 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2872 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873 } else {
2874 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876 }
2877 POSTING_READ(reg);
2878 }
2879
2880 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2881 uint64_t fb_modifier, uint32_t pixel_format)
2882 {
2883 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2884 return 64;
2885 } else {
2886 int cpp = drm_format_plane_cpp(pixel_format, 0);
2887
2888 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2889 }
2890 }
2891
2892 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2893 struct drm_i915_gem_object *obj,
2894 unsigned int plane)
2895 {
2896 struct i915_ggtt_view view;
2897 struct i915_vma *vma;
2898 u64 offset;
2899
2900 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2901 intel_plane->base.state->rotation);
2902
2903 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2904 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2905 view.type))
2906 return -1;
2907
2908 offset = vma->node.start;
2909
2910 if (plane == 1) {
2911 offset += vma->ggtt_view.params.rotated.uv_start_page *
2912 PAGE_SIZE;
2913 }
2914
2915 WARN_ON(upper_32_bits(offset));
2916
2917 return lower_32_bits(offset);
2918 }
2919
2920 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2921 {
2922 struct drm_device *dev = intel_crtc->base.dev;
2923 struct drm_i915_private *dev_priv = to_i915(dev);
2924
2925 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2926 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2927 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2928 }
2929
2930 /*
2931 * This function detaches (aka. unbinds) unused scalers in hardware
2932 */
2933 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2934 {
2935 struct intel_crtc_scaler_state *scaler_state;
2936 int i;
2937
2938 scaler_state = &intel_crtc->config->scaler_state;
2939
2940 /* loop through and disable scalers that aren't in use */
2941 for (i = 0; i < intel_crtc->num_scalers; i++) {
2942 if (!scaler_state->scalers[i].in_use)
2943 skl_detach_scaler(intel_crtc, i);
2944 }
2945 }
2946
2947 u32 skl_plane_ctl_format(uint32_t pixel_format)
2948 {
2949 switch (pixel_format) {
2950 case DRM_FORMAT_C8:
2951 return PLANE_CTL_FORMAT_INDEXED;
2952 case DRM_FORMAT_RGB565:
2953 return PLANE_CTL_FORMAT_RGB_565;
2954 case DRM_FORMAT_XBGR8888:
2955 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2956 case DRM_FORMAT_XRGB8888:
2957 return PLANE_CTL_FORMAT_XRGB_8888;
2958 /*
2959 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2960 * to be already pre-multiplied. We need to add a knob (or a different
2961 * DRM_FORMAT) for user-space to configure that.
2962 */
2963 case DRM_FORMAT_ABGR8888:
2964 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2965 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2966 case DRM_FORMAT_ARGB8888:
2967 return PLANE_CTL_FORMAT_XRGB_8888 |
2968 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2969 case DRM_FORMAT_XRGB2101010:
2970 return PLANE_CTL_FORMAT_XRGB_2101010;
2971 case DRM_FORMAT_XBGR2101010:
2972 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2973 case DRM_FORMAT_YUYV:
2974 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2975 case DRM_FORMAT_YVYU:
2976 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2977 case DRM_FORMAT_UYVY:
2978 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2979 case DRM_FORMAT_VYUY:
2980 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2981 default:
2982 MISSING_CASE(pixel_format);
2983 }
2984
2985 return 0;
2986 }
2987
2988 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2989 {
2990 switch (fb_modifier) {
2991 case DRM_FORMAT_MOD_NONE:
2992 break;
2993 case I915_FORMAT_MOD_X_TILED:
2994 return PLANE_CTL_TILED_X;
2995 case I915_FORMAT_MOD_Y_TILED:
2996 return PLANE_CTL_TILED_Y;
2997 case I915_FORMAT_MOD_Yf_TILED:
2998 return PLANE_CTL_TILED_YF;
2999 default:
3000 MISSING_CASE(fb_modifier);
3001 }
3002
3003 return 0;
3004 }
3005
3006 u32 skl_plane_ctl_rotation(unsigned int rotation)
3007 {
3008 switch (rotation) {
3009 case BIT(DRM_ROTATE_0):
3010 break;
3011 /*
3012 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3013 * while i915 HW rotation is clockwise, thats why this swapping.
3014 */
3015 case BIT(DRM_ROTATE_90):
3016 return PLANE_CTL_ROTATE_270;
3017 case BIT(DRM_ROTATE_180):
3018 return PLANE_CTL_ROTATE_180;
3019 case BIT(DRM_ROTATE_270):
3020 return PLANE_CTL_ROTATE_90;
3021 default:
3022 MISSING_CASE(rotation);
3023 }
3024
3025 return 0;
3026 }
3027
3028 static void skylake_update_primary_plane(struct drm_plane *plane,
3029 const struct intel_crtc_state *crtc_state,
3030 const struct intel_plane_state *plane_state)
3031 {
3032 struct drm_device *dev = plane->dev;
3033 struct drm_i915_private *dev_priv = to_i915(dev);
3034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3035 struct drm_framebuffer *fb = plane_state->base.fb;
3036 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3037 int pipe = intel_crtc->pipe;
3038 u32 plane_ctl, stride_div, stride;
3039 u32 tile_height, plane_offset, plane_size;
3040 unsigned int rotation = plane_state->base.rotation;
3041 int x_offset, y_offset;
3042 u32 surf_addr;
3043 int scaler_id = plane_state->scaler_id;
3044 int src_x = plane_state->src.x1 >> 16;
3045 int src_y = plane_state->src.y1 >> 16;
3046 int src_w = drm_rect_width(&plane_state->src) >> 16;
3047 int src_h = drm_rect_height(&plane_state->src) >> 16;
3048 int dst_x = plane_state->dst.x1;
3049 int dst_y = plane_state->dst.y1;
3050 int dst_w = drm_rect_width(&plane_state->dst);
3051 int dst_h = drm_rect_height(&plane_state->dst);
3052
3053 plane_ctl = PLANE_CTL_ENABLE |
3054 PLANE_CTL_PIPE_GAMMA_ENABLE |
3055 PLANE_CTL_PIPE_CSC_ENABLE;
3056
3057 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3058 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3059 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3060 plane_ctl |= skl_plane_ctl_rotation(rotation);
3061
3062 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3063 fb->pixel_format);
3064 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3065
3066 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3067
3068 if (intel_rotation_90_or_270(rotation)) {
3069 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3070
3071 /* stride = Surface height in tiles */
3072 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3073 stride = DIV_ROUND_UP(fb->height, tile_height);
3074 x_offset = stride * tile_height - src_y - src_h;
3075 y_offset = src_x;
3076 plane_size = (src_w - 1) << 16 | (src_h - 1);
3077 } else {
3078 stride = fb->pitches[0] / stride_div;
3079 x_offset = src_x;
3080 y_offset = src_y;
3081 plane_size = (src_h - 1) << 16 | (src_w - 1);
3082 }
3083 plane_offset = y_offset << 16 | x_offset;
3084
3085 intel_crtc->adjusted_x = x_offset;
3086 intel_crtc->adjusted_y = y_offset;
3087
3088 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3089 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3090 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3091 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3092
3093 if (scaler_id >= 0) {
3094 uint32_t ps_ctrl = 0;
3095
3096 WARN_ON(!dst_w || !dst_h);
3097 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3098 crtc_state->scaler_state.scalers[scaler_id].mode;
3099 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3100 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3101 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3102 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3103 I915_WRITE(PLANE_POS(pipe, 0), 0);
3104 } else {
3105 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3106 }
3107
3108 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3109
3110 POSTING_READ(PLANE_SURF(pipe, 0));
3111 }
3112
3113 static void skylake_disable_primary_plane(struct drm_plane *primary,
3114 struct drm_crtc *crtc)
3115 {
3116 struct drm_device *dev = crtc->dev;
3117 struct drm_i915_private *dev_priv = to_i915(dev);
3118 int pipe = to_intel_crtc(crtc)->pipe;
3119
3120 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3121 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3122 POSTING_READ(PLANE_SURF(pipe, 0));
3123 }
3124
3125 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3126 static int
3127 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3128 int x, int y, enum mode_set_atomic state)
3129 {
3130 /* Support for kgdboc is disabled, this needs a major rework. */
3131 DRM_ERROR("legacy panic handler not supported any more.\n");
3132
3133 return -ENODEV;
3134 }
3135
3136 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3137 {
3138 struct intel_crtc *crtc;
3139
3140 for_each_intel_crtc(dev_priv->dev, crtc)
3141 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3142 }
3143
3144 static void intel_update_primary_planes(struct drm_device *dev)
3145 {
3146 struct drm_crtc *crtc;
3147
3148 for_each_crtc(dev, crtc) {
3149 struct intel_plane *plane = to_intel_plane(crtc->primary);
3150 struct intel_plane_state *plane_state;
3151
3152 drm_modeset_lock_crtc(crtc, &plane->base);
3153 plane_state = to_intel_plane_state(plane->base.state);
3154
3155 if (plane_state->visible)
3156 plane->update_plane(&plane->base,
3157 to_intel_crtc_state(crtc->state),
3158 plane_state);
3159
3160 drm_modeset_unlock_crtc(crtc);
3161 }
3162 }
3163
3164 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3165 {
3166 /* no reset support for gen2 */
3167 if (IS_GEN2(dev_priv))
3168 return;
3169
3170 /* reset doesn't touch the display */
3171 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3172 return;
3173
3174 drm_modeset_lock_all(dev_priv->dev);
3175 /*
3176 * Disabling the crtcs gracefully seems nicer. Also the
3177 * g33 docs say we should at least disable all the planes.
3178 */
3179 intel_display_suspend(dev_priv->dev);
3180 }
3181
3182 void intel_finish_reset(struct drm_i915_private *dev_priv)
3183 {
3184 /*
3185 * Flips in the rings will be nuked by the reset,
3186 * so complete all pending flips so that user space
3187 * will get its events and not get stuck.
3188 */
3189 intel_complete_page_flips(dev_priv);
3190
3191 /* no reset support for gen2 */
3192 if (IS_GEN2(dev_priv))
3193 return;
3194
3195 /* reset doesn't touch the display */
3196 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3197 /*
3198 * Flips in the rings have been nuked by the reset,
3199 * so update the base address of all primary
3200 * planes to the the last fb to make sure we're
3201 * showing the correct fb after a reset.
3202 *
3203 * FIXME: Atomic will make this obsolete since we won't schedule
3204 * CS-based flips (which might get lost in gpu resets) any more.
3205 */
3206 intel_update_primary_planes(dev_priv->dev);
3207 return;
3208 }
3209
3210 /*
3211 * The display has been reset as well,
3212 * so need a full re-initialization.
3213 */
3214 intel_runtime_pm_disable_interrupts(dev_priv);
3215 intel_runtime_pm_enable_interrupts(dev_priv);
3216
3217 intel_modeset_init_hw(dev_priv->dev);
3218
3219 spin_lock_irq(&dev_priv->irq_lock);
3220 if (dev_priv->display.hpd_irq_setup)
3221 dev_priv->display.hpd_irq_setup(dev_priv);
3222 spin_unlock_irq(&dev_priv->irq_lock);
3223
3224 intel_display_resume(dev_priv->dev);
3225
3226 intel_hpd_init(dev_priv);
3227
3228 drm_modeset_unlock_all(dev_priv->dev);
3229 }
3230
3231 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3232 {
3233 struct drm_device *dev = crtc->dev;
3234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3235 unsigned reset_counter;
3236 bool pending;
3237
3238 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3239 if (intel_crtc->reset_counter != reset_counter)
3240 return false;
3241
3242 spin_lock_irq(&dev->event_lock);
3243 pending = to_intel_crtc(crtc)->flip_work != NULL;
3244 spin_unlock_irq(&dev->event_lock);
3245
3246 return pending;
3247 }
3248
3249 static void intel_update_pipe_config(struct intel_crtc *crtc,
3250 struct intel_crtc_state *old_crtc_state)
3251 {
3252 struct drm_device *dev = crtc->base.dev;
3253 struct drm_i915_private *dev_priv = to_i915(dev);
3254 struct intel_crtc_state *pipe_config =
3255 to_intel_crtc_state(crtc->base.state);
3256
3257 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3258 crtc->base.mode = crtc->base.state->mode;
3259
3260 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3261 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3262 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3263
3264 /*
3265 * Update pipe size and adjust fitter if needed: the reason for this is
3266 * that in compute_mode_changes we check the native mode (not the pfit
3267 * mode) to see if we can flip rather than do a full mode set. In the
3268 * fastboot case, we'll flip, but if we don't update the pipesrc and
3269 * pfit state, we'll end up with a big fb scanned out into the wrong
3270 * sized surface.
3271 */
3272
3273 I915_WRITE(PIPESRC(crtc->pipe),
3274 ((pipe_config->pipe_src_w - 1) << 16) |
3275 (pipe_config->pipe_src_h - 1));
3276
3277 /* on skylake this is done by detaching scalers */
3278 if (INTEL_INFO(dev)->gen >= 9) {
3279 skl_detach_scalers(crtc);
3280
3281 if (pipe_config->pch_pfit.enabled)
3282 skylake_pfit_enable(crtc);
3283 } else if (HAS_PCH_SPLIT(dev)) {
3284 if (pipe_config->pch_pfit.enabled)
3285 ironlake_pfit_enable(crtc);
3286 else if (old_crtc_state->pch_pfit.enabled)
3287 ironlake_pfit_disable(crtc, true);
3288 }
3289 }
3290
3291 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3292 {
3293 struct drm_device *dev = crtc->dev;
3294 struct drm_i915_private *dev_priv = to_i915(dev);
3295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3296 int pipe = intel_crtc->pipe;
3297 i915_reg_t reg;
3298 u32 temp;
3299
3300 /* enable normal train */
3301 reg = FDI_TX_CTL(pipe);
3302 temp = I915_READ(reg);
3303 if (IS_IVYBRIDGE(dev)) {
3304 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3305 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3306 } else {
3307 temp &= ~FDI_LINK_TRAIN_NONE;
3308 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3309 }
3310 I915_WRITE(reg, temp);
3311
3312 reg = FDI_RX_CTL(pipe);
3313 temp = I915_READ(reg);
3314 if (HAS_PCH_CPT(dev)) {
3315 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3316 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3317 } else {
3318 temp &= ~FDI_LINK_TRAIN_NONE;
3319 temp |= FDI_LINK_TRAIN_NONE;
3320 }
3321 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3322
3323 /* wait one idle pattern time */
3324 POSTING_READ(reg);
3325 udelay(1000);
3326
3327 /* IVB wants error correction enabled */
3328 if (IS_IVYBRIDGE(dev))
3329 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3330 FDI_FE_ERRC_ENABLE);
3331 }
3332
3333 /* The FDI link training functions for ILK/Ibexpeak. */
3334 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3335 {
3336 struct drm_device *dev = crtc->dev;
3337 struct drm_i915_private *dev_priv = to_i915(dev);
3338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3339 int pipe = intel_crtc->pipe;
3340 i915_reg_t reg;
3341 u32 temp, tries;
3342
3343 /* FDI needs bits from pipe first */
3344 assert_pipe_enabled(dev_priv, pipe);
3345
3346 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3347 for train result */
3348 reg = FDI_RX_IMR(pipe);
3349 temp = I915_READ(reg);
3350 temp &= ~FDI_RX_SYMBOL_LOCK;
3351 temp &= ~FDI_RX_BIT_LOCK;
3352 I915_WRITE(reg, temp);
3353 I915_READ(reg);
3354 udelay(150);
3355
3356 /* enable CPU FDI TX and PCH FDI RX */
3357 reg = FDI_TX_CTL(pipe);
3358 temp = I915_READ(reg);
3359 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3360 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3361 temp &= ~FDI_LINK_TRAIN_NONE;
3362 temp |= FDI_LINK_TRAIN_PATTERN_1;
3363 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3364
3365 reg = FDI_RX_CTL(pipe);
3366 temp = I915_READ(reg);
3367 temp &= ~FDI_LINK_TRAIN_NONE;
3368 temp |= FDI_LINK_TRAIN_PATTERN_1;
3369 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3370
3371 POSTING_READ(reg);
3372 udelay(150);
3373
3374 /* Ironlake workaround, enable clock pointer after FDI enable*/
3375 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3376 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3377 FDI_RX_PHASE_SYNC_POINTER_EN);
3378
3379 reg = FDI_RX_IIR(pipe);
3380 for (tries = 0; tries < 5; tries++) {
3381 temp = I915_READ(reg);
3382 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3383
3384 if ((temp & FDI_RX_BIT_LOCK)) {
3385 DRM_DEBUG_KMS("FDI train 1 done.\n");
3386 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3387 break;
3388 }
3389 }
3390 if (tries == 5)
3391 DRM_ERROR("FDI train 1 fail!\n");
3392
3393 /* Train 2 */
3394 reg = FDI_TX_CTL(pipe);
3395 temp = I915_READ(reg);
3396 temp &= ~FDI_LINK_TRAIN_NONE;
3397 temp |= FDI_LINK_TRAIN_PATTERN_2;
3398 I915_WRITE(reg, temp);
3399
3400 reg = FDI_RX_CTL(pipe);
3401 temp = I915_READ(reg);
3402 temp &= ~FDI_LINK_TRAIN_NONE;
3403 temp |= FDI_LINK_TRAIN_PATTERN_2;
3404 I915_WRITE(reg, temp);
3405
3406 POSTING_READ(reg);
3407 udelay(150);
3408
3409 reg = FDI_RX_IIR(pipe);
3410 for (tries = 0; tries < 5; tries++) {
3411 temp = I915_READ(reg);
3412 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3413
3414 if (temp & FDI_RX_SYMBOL_LOCK) {
3415 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3416 DRM_DEBUG_KMS("FDI train 2 done.\n");
3417 break;
3418 }
3419 }
3420 if (tries == 5)
3421 DRM_ERROR("FDI train 2 fail!\n");
3422
3423 DRM_DEBUG_KMS("FDI train done\n");
3424
3425 }
3426
3427 static const int snb_b_fdi_train_param[] = {
3428 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3429 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3430 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3431 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3432 };
3433
3434 /* The FDI link training functions for SNB/Cougarpoint. */
3435 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3436 {
3437 struct drm_device *dev = crtc->dev;
3438 struct drm_i915_private *dev_priv = to_i915(dev);
3439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3440 int pipe = intel_crtc->pipe;
3441 i915_reg_t reg;
3442 u32 temp, i, retry;
3443
3444 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3445 for train result */
3446 reg = FDI_RX_IMR(pipe);
3447 temp = I915_READ(reg);
3448 temp &= ~FDI_RX_SYMBOL_LOCK;
3449 temp &= ~FDI_RX_BIT_LOCK;
3450 I915_WRITE(reg, temp);
3451
3452 POSTING_READ(reg);
3453 udelay(150);
3454
3455 /* enable CPU FDI TX and PCH FDI RX */
3456 reg = FDI_TX_CTL(pipe);
3457 temp = I915_READ(reg);
3458 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3459 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3460 temp &= ~FDI_LINK_TRAIN_NONE;
3461 temp |= FDI_LINK_TRAIN_PATTERN_1;
3462 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3463 /* SNB-B */
3464 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3465 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3466
3467 I915_WRITE(FDI_RX_MISC(pipe),
3468 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3469
3470 reg = FDI_RX_CTL(pipe);
3471 temp = I915_READ(reg);
3472 if (HAS_PCH_CPT(dev)) {
3473 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3474 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3475 } else {
3476 temp &= ~FDI_LINK_TRAIN_NONE;
3477 temp |= FDI_LINK_TRAIN_PATTERN_1;
3478 }
3479 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3480
3481 POSTING_READ(reg);
3482 udelay(150);
3483
3484 for (i = 0; i < 4; i++) {
3485 reg = FDI_TX_CTL(pipe);
3486 temp = I915_READ(reg);
3487 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3488 temp |= snb_b_fdi_train_param[i];
3489 I915_WRITE(reg, temp);
3490
3491 POSTING_READ(reg);
3492 udelay(500);
3493
3494 for (retry = 0; retry < 5; retry++) {
3495 reg = FDI_RX_IIR(pipe);
3496 temp = I915_READ(reg);
3497 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3498 if (temp & FDI_RX_BIT_LOCK) {
3499 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3500 DRM_DEBUG_KMS("FDI train 1 done.\n");
3501 break;
3502 }
3503 udelay(50);
3504 }
3505 if (retry < 5)
3506 break;
3507 }
3508 if (i == 4)
3509 DRM_ERROR("FDI train 1 fail!\n");
3510
3511 /* Train 2 */
3512 reg = FDI_TX_CTL(pipe);
3513 temp = I915_READ(reg);
3514 temp &= ~FDI_LINK_TRAIN_NONE;
3515 temp |= FDI_LINK_TRAIN_PATTERN_2;
3516 if (IS_GEN6(dev)) {
3517 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3518 /* SNB-B */
3519 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3520 }
3521 I915_WRITE(reg, temp);
3522
3523 reg = FDI_RX_CTL(pipe);
3524 temp = I915_READ(reg);
3525 if (HAS_PCH_CPT(dev)) {
3526 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3527 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3528 } else {
3529 temp &= ~FDI_LINK_TRAIN_NONE;
3530 temp |= FDI_LINK_TRAIN_PATTERN_2;
3531 }
3532 I915_WRITE(reg, temp);
3533
3534 POSTING_READ(reg);
3535 udelay(150);
3536
3537 for (i = 0; i < 4; i++) {
3538 reg = FDI_TX_CTL(pipe);
3539 temp = I915_READ(reg);
3540 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3541 temp |= snb_b_fdi_train_param[i];
3542 I915_WRITE(reg, temp);
3543
3544 POSTING_READ(reg);
3545 udelay(500);
3546
3547 for (retry = 0; retry < 5; retry++) {
3548 reg = FDI_RX_IIR(pipe);
3549 temp = I915_READ(reg);
3550 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3551 if (temp & FDI_RX_SYMBOL_LOCK) {
3552 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3553 DRM_DEBUG_KMS("FDI train 2 done.\n");
3554 break;
3555 }
3556 udelay(50);
3557 }
3558 if (retry < 5)
3559 break;
3560 }
3561 if (i == 4)
3562 DRM_ERROR("FDI train 2 fail!\n");
3563
3564 DRM_DEBUG_KMS("FDI train done.\n");
3565 }
3566
3567 /* Manual link training for Ivy Bridge A0 parts */
3568 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3569 {
3570 struct drm_device *dev = crtc->dev;
3571 struct drm_i915_private *dev_priv = to_i915(dev);
3572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3573 int pipe = intel_crtc->pipe;
3574 i915_reg_t reg;
3575 u32 temp, i, j;
3576
3577 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3578 for train result */
3579 reg = FDI_RX_IMR(pipe);
3580 temp = I915_READ(reg);
3581 temp &= ~FDI_RX_SYMBOL_LOCK;
3582 temp &= ~FDI_RX_BIT_LOCK;
3583 I915_WRITE(reg, temp);
3584
3585 POSTING_READ(reg);
3586 udelay(150);
3587
3588 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3589 I915_READ(FDI_RX_IIR(pipe)));
3590
3591 /* Try each vswing and preemphasis setting twice before moving on */
3592 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3593 /* disable first in case we need to retry */
3594 reg = FDI_TX_CTL(pipe);
3595 temp = I915_READ(reg);
3596 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3597 temp &= ~FDI_TX_ENABLE;
3598 I915_WRITE(reg, temp);
3599
3600 reg = FDI_RX_CTL(pipe);
3601 temp = I915_READ(reg);
3602 temp &= ~FDI_LINK_TRAIN_AUTO;
3603 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3604 temp &= ~FDI_RX_ENABLE;
3605 I915_WRITE(reg, temp);
3606
3607 /* enable CPU FDI TX and PCH FDI RX */
3608 reg = FDI_TX_CTL(pipe);
3609 temp = I915_READ(reg);
3610 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3611 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3612 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3614 temp |= snb_b_fdi_train_param[j/2];
3615 temp |= FDI_COMPOSITE_SYNC;
3616 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3617
3618 I915_WRITE(FDI_RX_MISC(pipe),
3619 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3620
3621 reg = FDI_RX_CTL(pipe);
3622 temp = I915_READ(reg);
3623 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3624 temp |= FDI_COMPOSITE_SYNC;
3625 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3626
3627 POSTING_READ(reg);
3628 udelay(1); /* should be 0.5us */
3629
3630 for (i = 0; i < 4; i++) {
3631 reg = FDI_RX_IIR(pipe);
3632 temp = I915_READ(reg);
3633 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3634
3635 if (temp & FDI_RX_BIT_LOCK ||
3636 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3637 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3638 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3639 i);
3640 break;
3641 }
3642 udelay(1); /* should be 0.5us */
3643 }
3644 if (i == 4) {
3645 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3646 continue;
3647 }
3648
3649 /* Train 2 */
3650 reg = FDI_TX_CTL(pipe);
3651 temp = I915_READ(reg);
3652 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3653 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3654 I915_WRITE(reg, temp);
3655
3656 reg = FDI_RX_CTL(pipe);
3657 temp = I915_READ(reg);
3658 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3659 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3660 I915_WRITE(reg, temp);
3661
3662 POSTING_READ(reg);
3663 udelay(2); /* should be 1.5us */
3664
3665 for (i = 0; i < 4; i++) {
3666 reg = FDI_RX_IIR(pipe);
3667 temp = I915_READ(reg);
3668 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3669
3670 if (temp & FDI_RX_SYMBOL_LOCK ||
3671 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3672 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3673 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3674 i);
3675 goto train_done;
3676 }
3677 udelay(2); /* should be 1.5us */
3678 }
3679 if (i == 4)
3680 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3681 }
3682
3683 train_done:
3684 DRM_DEBUG_KMS("FDI train done.\n");
3685 }
3686
3687 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3688 {
3689 struct drm_device *dev = intel_crtc->base.dev;
3690 struct drm_i915_private *dev_priv = to_i915(dev);
3691 int pipe = intel_crtc->pipe;
3692 i915_reg_t reg;
3693 u32 temp;
3694
3695 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3696 reg = FDI_RX_CTL(pipe);
3697 temp = I915_READ(reg);
3698 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3699 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3700 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3701 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3702
3703 POSTING_READ(reg);
3704 udelay(200);
3705
3706 /* Switch from Rawclk to PCDclk */
3707 temp = I915_READ(reg);
3708 I915_WRITE(reg, temp | FDI_PCDCLK);
3709
3710 POSTING_READ(reg);
3711 udelay(200);
3712
3713 /* Enable CPU FDI TX PLL, always on for Ironlake */
3714 reg = FDI_TX_CTL(pipe);
3715 temp = I915_READ(reg);
3716 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3717 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3718
3719 POSTING_READ(reg);
3720 udelay(100);
3721 }
3722 }
3723
3724 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3725 {
3726 struct drm_device *dev = intel_crtc->base.dev;
3727 struct drm_i915_private *dev_priv = to_i915(dev);
3728 int pipe = intel_crtc->pipe;
3729 i915_reg_t reg;
3730 u32 temp;
3731
3732 /* Switch from PCDclk to Rawclk */
3733 reg = FDI_RX_CTL(pipe);
3734 temp = I915_READ(reg);
3735 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3736
3737 /* Disable CPU FDI TX PLL */
3738 reg = FDI_TX_CTL(pipe);
3739 temp = I915_READ(reg);
3740 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3741
3742 POSTING_READ(reg);
3743 udelay(100);
3744
3745 reg = FDI_RX_CTL(pipe);
3746 temp = I915_READ(reg);
3747 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3748
3749 /* Wait for the clocks to turn off. */
3750 POSTING_READ(reg);
3751 udelay(100);
3752 }
3753
3754 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3755 {
3756 struct drm_device *dev = crtc->dev;
3757 struct drm_i915_private *dev_priv = to_i915(dev);
3758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3759 int pipe = intel_crtc->pipe;
3760 i915_reg_t reg;
3761 u32 temp;
3762
3763 /* disable CPU FDI tx and PCH FDI rx */
3764 reg = FDI_TX_CTL(pipe);
3765 temp = I915_READ(reg);
3766 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3767 POSTING_READ(reg);
3768
3769 reg = FDI_RX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 temp &= ~(0x7 << 16);
3772 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3773 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3774
3775 POSTING_READ(reg);
3776 udelay(100);
3777
3778 /* Ironlake workaround, disable clock pointer after downing FDI */
3779 if (HAS_PCH_IBX(dev))
3780 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3781
3782 /* still set train pattern 1 */
3783 reg = FDI_TX_CTL(pipe);
3784 temp = I915_READ(reg);
3785 temp &= ~FDI_LINK_TRAIN_NONE;
3786 temp |= FDI_LINK_TRAIN_PATTERN_1;
3787 I915_WRITE(reg, temp);
3788
3789 reg = FDI_RX_CTL(pipe);
3790 temp = I915_READ(reg);
3791 if (HAS_PCH_CPT(dev)) {
3792 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3793 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3794 } else {
3795 temp &= ~FDI_LINK_TRAIN_NONE;
3796 temp |= FDI_LINK_TRAIN_PATTERN_1;
3797 }
3798 /* BPC in FDI rx is consistent with that in PIPECONF */
3799 temp &= ~(0x07 << 16);
3800 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3801 I915_WRITE(reg, temp);
3802
3803 POSTING_READ(reg);
3804 udelay(100);
3805 }
3806
3807 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3808 {
3809 struct intel_crtc *crtc;
3810
3811 /* Note that we don't need to be called with mode_config.lock here
3812 * as our list of CRTC objects is static for the lifetime of the
3813 * device and so cannot disappear as we iterate. Similarly, we can
3814 * happily treat the predicates as racy, atomic checks as userspace
3815 * cannot claim and pin a new fb without at least acquring the
3816 * struct_mutex and so serialising with us.
3817 */
3818 for_each_intel_crtc(dev, crtc) {
3819 if (atomic_read(&crtc->unpin_work_count) == 0)
3820 continue;
3821
3822 if (crtc->flip_work)
3823 intel_wait_for_vblank(dev, crtc->pipe);
3824
3825 return true;
3826 }
3827
3828 return false;
3829 }
3830
3831 static void page_flip_completed(struct intel_crtc *intel_crtc)
3832 {
3833 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3834 struct intel_flip_work *work = intel_crtc->flip_work;
3835
3836 intel_crtc->flip_work = NULL;
3837
3838 if (work->event)
3839 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3840
3841 drm_crtc_vblank_put(&intel_crtc->base);
3842
3843 wake_up_all(&dev_priv->pending_flip_queue);
3844 queue_work(dev_priv->wq, &work->unpin_work);
3845
3846 trace_i915_flip_complete(intel_crtc->plane,
3847 work->pending_flip_obj);
3848 }
3849
3850 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3851 {
3852 struct drm_device *dev = crtc->dev;
3853 struct drm_i915_private *dev_priv = to_i915(dev);
3854 long ret;
3855
3856 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3857
3858 ret = wait_event_interruptible_timeout(
3859 dev_priv->pending_flip_queue,
3860 !intel_crtc_has_pending_flip(crtc),
3861 60*HZ);
3862
3863 if (ret < 0)
3864 return ret;
3865
3866 if (ret == 0) {
3867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3868 struct intel_flip_work *work;
3869
3870 spin_lock_irq(&dev->event_lock);
3871 work = intel_crtc->flip_work;
3872 if (work && !is_mmio_work(work)) {
3873 WARN_ONCE(1, "Removing stuck page flip\n");
3874 page_flip_completed(intel_crtc);
3875 }
3876 spin_unlock_irq(&dev->event_lock);
3877 }
3878
3879 return 0;
3880 }
3881
3882 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3883 {
3884 u32 temp;
3885
3886 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3887
3888 mutex_lock(&dev_priv->sb_lock);
3889
3890 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3891 temp |= SBI_SSCCTL_DISABLE;
3892 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3893
3894 mutex_unlock(&dev_priv->sb_lock);
3895 }
3896
3897 /* Program iCLKIP clock to the desired frequency */
3898 static void lpt_program_iclkip(struct drm_crtc *crtc)
3899 {
3900 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3901 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3902 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3903 u32 temp;
3904
3905 lpt_disable_iclkip(dev_priv);
3906
3907 /* The iCLK virtual clock root frequency is in MHz,
3908 * but the adjusted_mode->crtc_clock in in KHz. To get the
3909 * divisors, it is necessary to divide one by another, so we
3910 * convert the virtual clock precision to KHz here for higher
3911 * precision.
3912 */
3913 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3914 u32 iclk_virtual_root_freq = 172800 * 1000;
3915 u32 iclk_pi_range = 64;
3916 u32 desired_divisor;
3917
3918 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3919 clock << auxdiv);
3920 divsel = (desired_divisor / iclk_pi_range) - 2;
3921 phaseinc = desired_divisor % iclk_pi_range;
3922
3923 /*
3924 * Near 20MHz is a corner case which is
3925 * out of range for the 7-bit divisor
3926 */
3927 if (divsel <= 0x7f)
3928 break;
3929 }
3930
3931 /* This should not happen with any sane values */
3932 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3933 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3934 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3935 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3936
3937 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3938 clock,
3939 auxdiv,
3940 divsel,
3941 phasedir,
3942 phaseinc);
3943
3944 mutex_lock(&dev_priv->sb_lock);
3945
3946 /* Program SSCDIVINTPHASE6 */
3947 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3948 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3949 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3950 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3951 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3952 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3953 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3954 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3955
3956 /* Program SSCAUXDIV */
3957 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3958 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3959 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3960 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3961
3962 /* Enable modulator and associated divider */
3963 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3964 temp &= ~SBI_SSCCTL_DISABLE;
3965 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3966
3967 mutex_unlock(&dev_priv->sb_lock);
3968
3969 /* Wait for initialization time */
3970 udelay(24);
3971
3972 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3973 }
3974
3975 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3976 {
3977 u32 divsel, phaseinc, auxdiv;
3978 u32 iclk_virtual_root_freq = 172800 * 1000;
3979 u32 iclk_pi_range = 64;
3980 u32 desired_divisor;
3981 u32 temp;
3982
3983 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3984 return 0;
3985
3986 mutex_lock(&dev_priv->sb_lock);
3987
3988 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3989 if (temp & SBI_SSCCTL_DISABLE) {
3990 mutex_unlock(&dev_priv->sb_lock);
3991 return 0;
3992 }
3993
3994 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3995 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3996 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3997 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3998 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3999
4000 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4001 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4002 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4003
4004 mutex_unlock(&dev_priv->sb_lock);
4005
4006 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4007
4008 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4009 desired_divisor << auxdiv);
4010 }
4011
4012 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4013 enum pipe pch_transcoder)
4014 {
4015 struct drm_device *dev = crtc->base.dev;
4016 struct drm_i915_private *dev_priv = to_i915(dev);
4017 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4018
4019 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4020 I915_READ(HTOTAL(cpu_transcoder)));
4021 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4022 I915_READ(HBLANK(cpu_transcoder)));
4023 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4024 I915_READ(HSYNC(cpu_transcoder)));
4025
4026 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4027 I915_READ(VTOTAL(cpu_transcoder)));
4028 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4029 I915_READ(VBLANK(cpu_transcoder)));
4030 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4031 I915_READ(VSYNC(cpu_transcoder)));
4032 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4033 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4034 }
4035
4036 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4037 {
4038 struct drm_i915_private *dev_priv = to_i915(dev);
4039 uint32_t temp;
4040
4041 temp = I915_READ(SOUTH_CHICKEN1);
4042 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4043 return;
4044
4045 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4046 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4047
4048 temp &= ~FDI_BC_BIFURCATION_SELECT;
4049 if (enable)
4050 temp |= FDI_BC_BIFURCATION_SELECT;
4051
4052 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4053 I915_WRITE(SOUTH_CHICKEN1, temp);
4054 POSTING_READ(SOUTH_CHICKEN1);
4055 }
4056
4057 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4058 {
4059 struct drm_device *dev = intel_crtc->base.dev;
4060
4061 switch (intel_crtc->pipe) {
4062 case PIPE_A:
4063 break;
4064 case PIPE_B:
4065 if (intel_crtc->config->fdi_lanes > 2)
4066 cpt_set_fdi_bc_bifurcation(dev, false);
4067 else
4068 cpt_set_fdi_bc_bifurcation(dev, true);
4069
4070 break;
4071 case PIPE_C:
4072 cpt_set_fdi_bc_bifurcation(dev, true);
4073
4074 break;
4075 default:
4076 BUG();
4077 }
4078 }
4079
4080 /* Return which DP Port should be selected for Transcoder DP control */
4081 static enum port
4082 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4083 {
4084 struct drm_device *dev = crtc->dev;
4085 struct intel_encoder *encoder;
4086
4087 for_each_encoder_on_crtc(dev, crtc, encoder) {
4088 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4089 encoder->type == INTEL_OUTPUT_EDP)
4090 return enc_to_dig_port(&encoder->base)->port;
4091 }
4092
4093 return -1;
4094 }
4095
4096 /*
4097 * Enable PCH resources required for PCH ports:
4098 * - PCH PLLs
4099 * - FDI training & RX/TX
4100 * - update transcoder timings
4101 * - DP transcoding bits
4102 * - transcoder
4103 */
4104 static void ironlake_pch_enable(struct drm_crtc *crtc)
4105 {
4106 struct drm_device *dev = crtc->dev;
4107 struct drm_i915_private *dev_priv = to_i915(dev);
4108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4109 int pipe = intel_crtc->pipe;
4110 u32 temp;
4111
4112 assert_pch_transcoder_disabled(dev_priv, pipe);
4113
4114 if (IS_IVYBRIDGE(dev))
4115 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4116
4117 /* Write the TU size bits before fdi link training, so that error
4118 * detection works. */
4119 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4120 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4121
4122 /* For PCH output, training FDI link */
4123 dev_priv->display.fdi_link_train(crtc);
4124
4125 /* We need to program the right clock selection before writing the pixel
4126 * mutliplier into the DPLL. */
4127 if (HAS_PCH_CPT(dev)) {
4128 u32 sel;
4129
4130 temp = I915_READ(PCH_DPLL_SEL);
4131 temp |= TRANS_DPLL_ENABLE(pipe);
4132 sel = TRANS_DPLLB_SEL(pipe);
4133 if (intel_crtc->config->shared_dpll ==
4134 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4135 temp |= sel;
4136 else
4137 temp &= ~sel;
4138 I915_WRITE(PCH_DPLL_SEL, temp);
4139 }
4140
4141 /* XXX: pch pll's can be enabled any time before we enable the PCH
4142 * transcoder, and we actually should do this to not upset any PCH
4143 * transcoder that already use the clock when we share it.
4144 *
4145 * Note that enable_shared_dpll tries to do the right thing, but
4146 * get_shared_dpll unconditionally resets the pll - we need that to have
4147 * the right LVDS enable sequence. */
4148 intel_enable_shared_dpll(intel_crtc);
4149
4150 /* set transcoder timing, panel must allow it */
4151 assert_panel_unlocked(dev_priv, pipe);
4152 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4153
4154 intel_fdi_normal_train(crtc);
4155
4156 /* For PCH DP, enable TRANS_DP_CTL */
4157 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4158 const struct drm_display_mode *adjusted_mode =
4159 &intel_crtc->config->base.adjusted_mode;
4160 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4161 i915_reg_t reg = TRANS_DP_CTL(pipe);
4162 temp = I915_READ(reg);
4163 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4164 TRANS_DP_SYNC_MASK |
4165 TRANS_DP_BPC_MASK);
4166 temp |= TRANS_DP_OUTPUT_ENABLE;
4167 temp |= bpc << 9; /* same format but at 11:9 */
4168
4169 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4170 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4171 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4172 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4173
4174 switch (intel_trans_dp_port_sel(crtc)) {
4175 case PORT_B:
4176 temp |= TRANS_DP_PORT_SEL_B;
4177 break;
4178 case PORT_C:
4179 temp |= TRANS_DP_PORT_SEL_C;
4180 break;
4181 case PORT_D:
4182 temp |= TRANS_DP_PORT_SEL_D;
4183 break;
4184 default:
4185 BUG();
4186 }
4187
4188 I915_WRITE(reg, temp);
4189 }
4190
4191 ironlake_enable_pch_transcoder(dev_priv, pipe);
4192 }
4193
4194 static void lpt_pch_enable(struct drm_crtc *crtc)
4195 {
4196 struct drm_device *dev = crtc->dev;
4197 struct drm_i915_private *dev_priv = to_i915(dev);
4198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4199 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4200
4201 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4202
4203 lpt_program_iclkip(crtc);
4204
4205 /* Set transcoder timing. */
4206 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4207
4208 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4209 }
4210
4211 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4212 {
4213 struct drm_i915_private *dev_priv = to_i915(dev);
4214 i915_reg_t dslreg = PIPEDSL(pipe);
4215 u32 temp;
4216
4217 temp = I915_READ(dslreg);
4218 udelay(500);
4219 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4220 if (wait_for(I915_READ(dslreg) != temp, 5))
4221 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4222 }
4223 }
4224
4225 static int
4226 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4227 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4228 int src_w, int src_h, int dst_w, int dst_h)
4229 {
4230 struct intel_crtc_scaler_state *scaler_state =
4231 &crtc_state->scaler_state;
4232 struct intel_crtc *intel_crtc =
4233 to_intel_crtc(crtc_state->base.crtc);
4234 int need_scaling;
4235
4236 need_scaling = intel_rotation_90_or_270(rotation) ?
4237 (src_h != dst_w || src_w != dst_h):
4238 (src_w != dst_w || src_h != dst_h);
4239
4240 /*
4241 * if plane is being disabled or scaler is no more required or force detach
4242 * - free scaler binded to this plane/crtc
4243 * - in order to do this, update crtc->scaler_usage
4244 *
4245 * Here scaler state in crtc_state is set free so that
4246 * scaler can be assigned to other user. Actual register
4247 * update to free the scaler is done in plane/panel-fit programming.
4248 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4249 */
4250 if (force_detach || !need_scaling) {
4251 if (*scaler_id >= 0) {
4252 scaler_state->scaler_users &= ~(1 << scaler_user);
4253 scaler_state->scalers[*scaler_id].in_use = 0;
4254
4255 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4256 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4257 intel_crtc->pipe, scaler_user, *scaler_id,
4258 scaler_state->scaler_users);
4259 *scaler_id = -1;
4260 }
4261 return 0;
4262 }
4263
4264 /* range checks */
4265 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4266 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4267
4268 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4269 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4270 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4271 "size is out of scaler range\n",
4272 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4273 return -EINVAL;
4274 }
4275
4276 /* mark this plane as a scaler user in crtc_state */
4277 scaler_state->scaler_users |= (1 << scaler_user);
4278 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4279 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4280 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4281 scaler_state->scaler_users);
4282
4283 return 0;
4284 }
4285
4286 /**
4287 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4288 *
4289 * @state: crtc's scaler state
4290 *
4291 * Return
4292 * 0 - scaler_usage updated successfully
4293 * error - requested scaling cannot be supported or other error condition
4294 */
4295 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4296 {
4297 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4298 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4299
4300 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4301 intel_crtc->base.base.id, intel_crtc->base.name,
4302 intel_crtc->pipe, SKL_CRTC_INDEX);
4303
4304 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4305 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4306 state->pipe_src_w, state->pipe_src_h,
4307 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4308 }
4309
4310 /**
4311 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4312 *
4313 * @state: crtc's scaler state
4314 * @plane_state: atomic plane state to update
4315 *
4316 * Return
4317 * 0 - scaler_usage updated successfully
4318 * error - requested scaling cannot be supported or other error condition
4319 */
4320 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4321 struct intel_plane_state *plane_state)
4322 {
4323
4324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4325 struct intel_plane *intel_plane =
4326 to_intel_plane(plane_state->base.plane);
4327 struct drm_framebuffer *fb = plane_state->base.fb;
4328 int ret;
4329
4330 bool force_detach = !fb || !plane_state->visible;
4331
4332 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4333 intel_plane->base.base.id, intel_plane->base.name,
4334 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4335
4336 ret = skl_update_scaler(crtc_state, force_detach,
4337 drm_plane_index(&intel_plane->base),
4338 &plane_state->scaler_id,
4339 plane_state->base.rotation,
4340 drm_rect_width(&plane_state->src) >> 16,
4341 drm_rect_height(&plane_state->src) >> 16,
4342 drm_rect_width(&plane_state->dst),
4343 drm_rect_height(&plane_state->dst));
4344
4345 if (ret || plane_state->scaler_id < 0)
4346 return ret;
4347
4348 /* check colorkey */
4349 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4350 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4351 intel_plane->base.base.id,
4352 intel_plane->base.name);
4353 return -EINVAL;
4354 }
4355
4356 /* Check src format */
4357 switch (fb->pixel_format) {
4358 case DRM_FORMAT_RGB565:
4359 case DRM_FORMAT_XBGR8888:
4360 case DRM_FORMAT_XRGB8888:
4361 case DRM_FORMAT_ABGR8888:
4362 case DRM_FORMAT_ARGB8888:
4363 case DRM_FORMAT_XRGB2101010:
4364 case DRM_FORMAT_XBGR2101010:
4365 case DRM_FORMAT_YUYV:
4366 case DRM_FORMAT_YVYU:
4367 case DRM_FORMAT_UYVY:
4368 case DRM_FORMAT_VYUY:
4369 break;
4370 default:
4371 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4372 intel_plane->base.base.id, intel_plane->base.name,
4373 fb->base.id, fb->pixel_format);
4374 return -EINVAL;
4375 }
4376
4377 return 0;
4378 }
4379
4380 static void skylake_scaler_disable(struct intel_crtc *crtc)
4381 {
4382 int i;
4383
4384 for (i = 0; i < crtc->num_scalers; i++)
4385 skl_detach_scaler(crtc, i);
4386 }
4387
4388 static void skylake_pfit_enable(struct intel_crtc *crtc)
4389 {
4390 struct drm_device *dev = crtc->base.dev;
4391 struct drm_i915_private *dev_priv = to_i915(dev);
4392 int pipe = crtc->pipe;
4393 struct intel_crtc_scaler_state *scaler_state =
4394 &crtc->config->scaler_state;
4395
4396 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4397
4398 if (crtc->config->pch_pfit.enabled) {
4399 int id;
4400
4401 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4402 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4403 return;
4404 }
4405
4406 id = scaler_state->scaler_id;
4407 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4408 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4409 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4410 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4411
4412 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4413 }
4414 }
4415
4416 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4417 {
4418 struct drm_device *dev = crtc->base.dev;
4419 struct drm_i915_private *dev_priv = to_i915(dev);
4420 int pipe = crtc->pipe;
4421
4422 if (crtc->config->pch_pfit.enabled) {
4423 /* Force use of hard-coded filter coefficients
4424 * as some pre-programmed values are broken,
4425 * e.g. x201.
4426 */
4427 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4428 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4429 PF_PIPE_SEL_IVB(pipe));
4430 else
4431 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4432 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4433 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4434 }
4435 }
4436
4437 void hsw_enable_ips(struct intel_crtc *crtc)
4438 {
4439 struct drm_device *dev = crtc->base.dev;
4440 struct drm_i915_private *dev_priv = to_i915(dev);
4441
4442 if (!crtc->config->ips_enabled)
4443 return;
4444
4445 /*
4446 * We can only enable IPS after we enable a plane and wait for a vblank
4447 * This function is called from post_plane_update, which is run after
4448 * a vblank wait.
4449 */
4450
4451 assert_plane_enabled(dev_priv, crtc->plane);
4452 if (IS_BROADWELL(dev)) {
4453 mutex_lock(&dev_priv->rps.hw_lock);
4454 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4455 mutex_unlock(&dev_priv->rps.hw_lock);
4456 /* Quoting Art Runyan: "its not safe to expect any particular
4457 * value in IPS_CTL bit 31 after enabling IPS through the
4458 * mailbox." Moreover, the mailbox may return a bogus state,
4459 * so we need to just enable it and continue on.
4460 */
4461 } else {
4462 I915_WRITE(IPS_CTL, IPS_ENABLE);
4463 /* The bit only becomes 1 in the next vblank, so this wait here
4464 * is essentially intel_wait_for_vblank. If we don't have this
4465 * and don't wait for vblanks until the end of crtc_enable, then
4466 * the HW state readout code will complain that the expected
4467 * IPS_CTL value is not the one we read. */
4468 if (intel_wait_for_register(dev_priv,
4469 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4470 50))
4471 DRM_ERROR("Timed out waiting for IPS enable\n");
4472 }
4473 }
4474
4475 void hsw_disable_ips(struct intel_crtc *crtc)
4476 {
4477 struct drm_device *dev = crtc->base.dev;
4478 struct drm_i915_private *dev_priv = to_i915(dev);
4479
4480 if (!crtc->config->ips_enabled)
4481 return;
4482
4483 assert_plane_enabled(dev_priv, crtc->plane);
4484 if (IS_BROADWELL(dev)) {
4485 mutex_lock(&dev_priv->rps.hw_lock);
4486 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4487 mutex_unlock(&dev_priv->rps.hw_lock);
4488 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4489 if (intel_wait_for_register(dev_priv,
4490 IPS_CTL, IPS_ENABLE, 0,
4491 42))
4492 DRM_ERROR("Timed out waiting for IPS disable\n");
4493 } else {
4494 I915_WRITE(IPS_CTL, 0);
4495 POSTING_READ(IPS_CTL);
4496 }
4497
4498 /* We need to wait for a vblank before we can disable the plane. */
4499 intel_wait_for_vblank(dev, crtc->pipe);
4500 }
4501
4502 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4503 {
4504 if (intel_crtc->overlay) {
4505 struct drm_device *dev = intel_crtc->base.dev;
4506 struct drm_i915_private *dev_priv = to_i915(dev);
4507
4508 mutex_lock(&dev->struct_mutex);
4509 dev_priv->mm.interruptible = false;
4510 (void) intel_overlay_switch_off(intel_crtc->overlay);
4511 dev_priv->mm.interruptible = true;
4512 mutex_unlock(&dev->struct_mutex);
4513 }
4514
4515 /* Let userspace switch the overlay on again. In most cases userspace
4516 * has to recompute where to put it anyway.
4517 */
4518 }
4519
4520 /**
4521 * intel_post_enable_primary - Perform operations after enabling primary plane
4522 * @crtc: the CRTC whose primary plane was just enabled
4523 *
4524 * Performs potentially sleeping operations that must be done after the primary
4525 * plane is enabled, such as updating FBC and IPS. Note that this may be
4526 * called due to an explicit primary plane update, or due to an implicit
4527 * re-enable that is caused when a sprite plane is updated to no longer
4528 * completely hide the primary plane.
4529 */
4530 static void
4531 intel_post_enable_primary(struct drm_crtc *crtc)
4532 {
4533 struct drm_device *dev = crtc->dev;
4534 struct drm_i915_private *dev_priv = to_i915(dev);
4535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4536 int pipe = intel_crtc->pipe;
4537
4538 /*
4539 * FIXME IPS should be fine as long as one plane is
4540 * enabled, but in practice it seems to have problems
4541 * when going from primary only to sprite only and vice
4542 * versa.
4543 */
4544 hsw_enable_ips(intel_crtc);
4545
4546 /*
4547 * Gen2 reports pipe underruns whenever all planes are disabled.
4548 * So don't enable underrun reporting before at least some planes
4549 * are enabled.
4550 * FIXME: Need to fix the logic to work when we turn off all planes
4551 * but leave the pipe running.
4552 */
4553 if (IS_GEN2(dev))
4554 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4555
4556 /* Underruns don't always raise interrupts, so check manually. */
4557 intel_check_cpu_fifo_underruns(dev_priv);
4558 intel_check_pch_fifo_underruns(dev_priv);
4559 }
4560
4561 /* FIXME move all this to pre_plane_update() with proper state tracking */
4562 static void
4563 intel_pre_disable_primary(struct drm_crtc *crtc)
4564 {
4565 struct drm_device *dev = crtc->dev;
4566 struct drm_i915_private *dev_priv = to_i915(dev);
4567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4568 int pipe = intel_crtc->pipe;
4569
4570 /*
4571 * Gen2 reports pipe underruns whenever all planes are disabled.
4572 * So diasble underrun reporting before all the planes get disabled.
4573 * FIXME: Need to fix the logic to work when we turn off all planes
4574 * but leave the pipe running.
4575 */
4576 if (IS_GEN2(dev))
4577 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4578
4579 /*
4580 * FIXME IPS should be fine as long as one plane is
4581 * enabled, but in practice it seems to have problems
4582 * when going from primary only to sprite only and vice
4583 * versa.
4584 */
4585 hsw_disable_ips(intel_crtc);
4586 }
4587
4588 /* FIXME get rid of this and use pre_plane_update */
4589 static void
4590 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4591 {
4592 struct drm_device *dev = crtc->dev;
4593 struct drm_i915_private *dev_priv = to_i915(dev);
4594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4595 int pipe = intel_crtc->pipe;
4596
4597 intel_pre_disable_primary(crtc);
4598
4599 /*
4600 * Vblank time updates from the shadow to live plane control register
4601 * are blocked if the memory self-refresh mode is active at that
4602 * moment. So to make sure the plane gets truly disabled, disable
4603 * first the self-refresh mode. The self-refresh enable bit in turn
4604 * will be checked/applied by the HW only at the next frame start
4605 * event which is after the vblank start event, so we need to have a
4606 * wait-for-vblank between disabling the plane and the pipe.
4607 */
4608 if (HAS_GMCH_DISPLAY(dev)) {
4609 intel_set_memory_cxsr(dev_priv, false);
4610 dev_priv->wm.vlv.cxsr = false;
4611 intel_wait_for_vblank(dev, pipe);
4612 }
4613 }
4614
4615 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4616 {
4617 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4618 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4619 struct intel_crtc_state *pipe_config =
4620 to_intel_crtc_state(crtc->base.state);
4621 struct drm_device *dev = crtc->base.dev;
4622 struct drm_plane *primary = crtc->base.primary;
4623 struct drm_plane_state *old_pri_state =
4624 drm_atomic_get_existing_plane_state(old_state, primary);
4625
4626 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4627
4628 crtc->wm.cxsr_allowed = true;
4629
4630 if (pipe_config->update_wm_post && pipe_config->base.active)
4631 intel_update_watermarks(&crtc->base);
4632
4633 if (old_pri_state) {
4634 struct intel_plane_state *primary_state =
4635 to_intel_plane_state(primary->state);
4636 struct intel_plane_state *old_primary_state =
4637 to_intel_plane_state(old_pri_state);
4638
4639 intel_fbc_post_update(crtc);
4640
4641 if (primary_state->visible &&
4642 (needs_modeset(&pipe_config->base) ||
4643 !old_primary_state->visible))
4644 intel_post_enable_primary(&crtc->base);
4645 }
4646 }
4647
4648 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4649 {
4650 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4651 struct drm_device *dev = crtc->base.dev;
4652 struct drm_i915_private *dev_priv = to_i915(dev);
4653 struct intel_crtc_state *pipe_config =
4654 to_intel_crtc_state(crtc->base.state);
4655 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4656 struct drm_plane *primary = crtc->base.primary;
4657 struct drm_plane_state *old_pri_state =
4658 drm_atomic_get_existing_plane_state(old_state, primary);
4659 bool modeset = needs_modeset(&pipe_config->base);
4660
4661 if (old_pri_state) {
4662 struct intel_plane_state *primary_state =
4663 to_intel_plane_state(primary->state);
4664 struct intel_plane_state *old_primary_state =
4665 to_intel_plane_state(old_pri_state);
4666
4667 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4668
4669 if (old_primary_state->visible &&
4670 (modeset || !primary_state->visible))
4671 intel_pre_disable_primary(&crtc->base);
4672 }
4673
4674 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
4675 crtc->wm.cxsr_allowed = false;
4676
4677 /*
4678 * Vblank time updates from the shadow to live plane control register
4679 * are blocked if the memory self-refresh mode is active at that
4680 * moment. So to make sure the plane gets truly disabled, disable
4681 * first the self-refresh mode. The self-refresh enable bit in turn
4682 * will be checked/applied by the HW only at the next frame start
4683 * event which is after the vblank start event, so we need to have a
4684 * wait-for-vblank between disabling the plane and the pipe.
4685 */
4686 if (old_crtc_state->base.active) {
4687 intel_set_memory_cxsr(dev_priv, false);
4688 dev_priv->wm.vlv.cxsr = false;
4689 intel_wait_for_vblank(dev, crtc->pipe);
4690 }
4691 }
4692
4693 /*
4694 * IVB workaround: must disable low power watermarks for at least
4695 * one frame before enabling scaling. LP watermarks can be re-enabled
4696 * when scaling is disabled.
4697 *
4698 * WaCxSRDisabledForSpriteScaling:ivb
4699 */
4700 if (pipe_config->disable_lp_wm) {
4701 ilk_disable_lp_wm(dev);
4702 intel_wait_for_vblank(dev, crtc->pipe);
4703 }
4704
4705 /*
4706 * If we're doing a modeset, we're done. No need to do any pre-vblank
4707 * watermark programming here.
4708 */
4709 if (needs_modeset(&pipe_config->base))
4710 return;
4711
4712 /*
4713 * For platforms that support atomic watermarks, program the
4714 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4715 * will be the intermediate values that are safe for both pre- and
4716 * post- vblank; when vblank happens, the 'active' values will be set
4717 * to the final 'target' values and we'll do this again to get the
4718 * optimal watermarks. For gen9+ platforms, the values we program here
4719 * will be the final target values which will get automatically latched
4720 * at vblank time; no further programming will be necessary.
4721 *
4722 * If a platform hasn't been transitioned to atomic watermarks yet,
4723 * we'll continue to update watermarks the old way, if flags tell
4724 * us to.
4725 */
4726 if (dev_priv->display.initial_watermarks != NULL)
4727 dev_priv->display.initial_watermarks(pipe_config);
4728 else if (pipe_config->update_wm_pre)
4729 intel_update_watermarks(&crtc->base);
4730 }
4731
4732 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4733 {
4734 struct drm_device *dev = crtc->dev;
4735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4736 struct drm_plane *p;
4737 int pipe = intel_crtc->pipe;
4738
4739 intel_crtc_dpms_overlay_disable(intel_crtc);
4740
4741 drm_for_each_plane_mask(p, dev, plane_mask)
4742 to_intel_plane(p)->disable_plane(p, crtc);
4743
4744 /*
4745 * FIXME: Once we grow proper nuclear flip support out of this we need
4746 * to compute the mask of flip planes precisely. For the time being
4747 * consider this a flip to a NULL plane.
4748 */
4749 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4750 }
4751
4752 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4753 {
4754 struct drm_device *dev = crtc->dev;
4755 struct drm_i915_private *dev_priv = to_i915(dev);
4756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4757 struct intel_encoder *encoder;
4758 int pipe = intel_crtc->pipe;
4759 struct intel_crtc_state *pipe_config =
4760 to_intel_crtc_state(crtc->state);
4761
4762 if (WARN_ON(intel_crtc->active))
4763 return;
4764
4765 /*
4766 * Sometimes spurious CPU pipe underruns happen during FDI
4767 * training, at least with VGA+HDMI cloning. Suppress them.
4768 *
4769 * On ILK we get an occasional spurious CPU pipe underruns
4770 * between eDP port A enable and vdd enable. Also PCH port
4771 * enable seems to result in the occasional CPU pipe underrun.
4772 *
4773 * Spurious PCH underruns also occur during PCH enabling.
4774 */
4775 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4776 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4777 if (intel_crtc->config->has_pch_encoder)
4778 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4779
4780 if (intel_crtc->config->has_pch_encoder)
4781 intel_prepare_shared_dpll(intel_crtc);
4782
4783 if (intel_crtc->config->has_dp_encoder)
4784 intel_dp_set_m_n(intel_crtc, M1_N1);
4785
4786 intel_set_pipe_timings(intel_crtc);
4787 intel_set_pipe_src_size(intel_crtc);
4788
4789 if (intel_crtc->config->has_pch_encoder) {
4790 intel_cpu_transcoder_set_m_n(intel_crtc,
4791 &intel_crtc->config->fdi_m_n, NULL);
4792 }
4793
4794 ironlake_set_pipeconf(crtc);
4795
4796 intel_crtc->active = true;
4797
4798 for_each_encoder_on_crtc(dev, crtc, encoder)
4799 if (encoder->pre_enable)
4800 encoder->pre_enable(encoder);
4801
4802 if (intel_crtc->config->has_pch_encoder) {
4803 /* Note: FDI PLL enabling _must_ be done before we enable the
4804 * cpu pipes, hence this is separate from all the other fdi/pch
4805 * enabling. */
4806 ironlake_fdi_pll_enable(intel_crtc);
4807 } else {
4808 assert_fdi_tx_disabled(dev_priv, pipe);
4809 assert_fdi_rx_disabled(dev_priv, pipe);
4810 }
4811
4812 ironlake_pfit_enable(intel_crtc);
4813
4814 /*
4815 * On ILK+ LUT must be loaded before the pipe is running but with
4816 * clocks enabled
4817 */
4818 intel_color_load_luts(&pipe_config->base);
4819
4820 if (dev_priv->display.initial_watermarks != NULL)
4821 dev_priv->display.initial_watermarks(intel_crtc->config);
4822 intel_enable_pipe(intel_crtc);
4823
4824 if (intel_crtc->config->has_pch_encoder)
4825 ironlake_pch_enable(crtc);
4826
4827 assert_vblank_disabled(crtc);
4828 drm_crtc_vblank_on(crtc);
4829
4830 for_each_encoder_on_crtc(dev, crtc, encoder)
4831 encoder->enable(encoder);
4832
4833 if (HAS_PCH_CPT(dev))
4834 cpt_verify_modeset(dev, intel_crtc->pipe);
4835
4836 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4837 if (intel_crtc->config->has_pch_encoder)
4838 intel_wait_for_vblank(dev, pipe);
4839 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4840 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4841 }
4842
4843 /* IPS only exists on ULT machines and is tied to pipe A. */
4844 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4845 {
4846 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4847 }
4848
4849 static void haswell_crtc_enable(struct drm_crtc *crtc)
4850 {
4851 struct drm_device *dev = crtc->dev;
4852 struct drm_i915_private *dev_priv = to_i915(dev);
4853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854 struct intel_encoder *encoder;
4855 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4856 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4857 struct intel_crtc_state *pipe_config =
4858 to_intel_crtc_state(crtc->state);
4859
4860 if (WARN_ON(intel_crtc->active))
4861 return;
4862
4863 if (intel_crtc->config->has_pch_encoder)
4864 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4865 false);
4866
4867 for_each_encoder_on_crtc(dev, crtc, encoder)
4868 if (encoder->pre_pll_enable)
4869 encoder->pre_pll_enable(encoder);
4870
4871 if (intel_crtc->config->shared_dpll)
4872 intel_enable_shared_dpll(intel_crtc);
4873
4874 if (intel_crtc->config->has_dp_encoder)
4875 intel_dp_set_m_n(intel_crtc, M1_N1);
4876
4877 if (!intel_crtc->config->has_dsi_encoder)
4878 intel_set_pipe_timings(intel_crtc);
4879
4880 intel_set_pipe_src_size(intel_crtc);
4881
4882 if (cpu_transcoder != TRANSCODER_EDP &&
4883 !transcoder_is_dsi(cpu_transcoder)) {
4884 I915_WRITE(PIPE_MULT(cpu_transcoder),
4885 intel_crtc->config->pixel_multiplier - 1);
4886 }
4887
4888 if (intel_crtc->config->has_pch_encoder) {
4889 intel_cpu_transcoder_set_m_n(intel_crtc,
4890 &intel_crtc->config->fdi_m_n, NULL);
4891 }
4892
4893 if (!intel_crtc->config->has_dsi_encoder)
4894 haswell_set_pipeconf(crtc);
4895
4896 haswell_set_pipemisc(crtc);
4897
4898 intel_color_set_csc(&pipe_config->base);
4899
4900 intel_crtc->active = true;
4901
4902 if (intel_crtc->config->has_pch_encoder)
4903 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4904 else
4905 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4906
4907 for_each_encoder_on_crtc(dev, crtc, encoder) {
4908 if (encoder->pre_enable)
4909 encoder->pre_enable(encoder);
4910 }
4911
4912 if (intel_crtc->config->has_pch_encoder)
4913 dev_priv->display.fdi_link_train(crtc);
4914
4915 if (!intel_crtc->config->has_dsi_encoder)
4916 intel_ddi_enable_pipe_clock(intel_crtc);
4917
4918 if (INTEL_INFO(dev)->gen >= 9)
4919 skylake_pfit_enable(intel_crtc);
4920 else
4921 ironlake_pfit_enable(intel_crtc);
4922
4923 /*
4924 * On ILK+ LUT must be loaded before the pipe is running but with
4925 * clocks enabled
4926 */
4927 intel_color_load_luts(&pipe_config->base);
4928
4929 intel_ddi_set_pipe_settings(crtc);
4930 if (!intel_crtc->config->has_dsi_encoder)
4931 intel_ddi_enable_transcoder_func(crtc);
4932
4933 if (dev_priv->display.initial_watermarks != NULL)
4934 dev_priv->display.initial_watermarks(pipe_config);
4935 else
4936 intel_update_watermarks(crtc);
4937
4938 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4939 if (!intel_crtc->config->has_dsi_encoder)
4940 intel_enable_pipe(intel_crtc);
4941
4942 if (intel_crtc->config->has_pch_encoder)
4943 lpt_pch_enable(crtc);
4944
4945 if (intel_crtc->config->dp_encoder_is_mst)
4946 intel_ddi_set_vc_payload_alloc(crtc, true);
4947
4948 assert_vblank_disabled(crtc);
4949 drm_crtc_vblank_on(crtc);
4950
4951 for_each_encoder_on_crtc(dev, crtc, encoder) {
4952 encoder->enable(encoder);
4953 intel_opregion_notify_encoder(encoder, true);
4954 }
4955
4956 if (intel_crtc->config->has_pch_encoder) {
4957 intel_wait_for_vblank(dev, pipe);
4958 intel_wait_for_vblank(dev, pipe);
4959 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4960 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4961 true);
4962 }
4963
4964 /* If we change the relative order between pipe/planes enabling, we need
4965 * to change the workaround. */
4966 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4967 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4968 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4969 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4970 }
4971 }
4972
4973 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4974 {
4975 struct drm_device *dev = crtc->base.dev;
4976 struct drm_i915_private *dev_priv = to_i915(dev);
4977 int pipe = crtc->pipe;
4978
4979 /* To avoid upsetting the power well on haswell only disable the pfit if
4980 * it's in use. The hw state code will make sure we get this right. */
4981 if (force || crtc->config->pch_pfit.enabled) {
4982 I915_WRITE(PF_CTL(pipe), 0);
4983 I915_WRITE(PF_WIN_POS(pipe), 0);
4984 I915_WRITE(PF_WIN_SZ(pipe), 0);
4985 }
4986 }
4987
4988 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4989 {
4990 struct drm_device *dev = crtc->dev;
4991 struct drm_i915_private *dev_priv = to_i915(dev);
4992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4993 struct intel_encoder *encoder;
4994 int pipe = intel_crtc->pipe;
4995
4996 /*
4997 * Sometimes spurious CPU pipe underruns happen when the
4998 * pipe is already disabled, but FDI RX/TX is still enabled.
4999 * Happens at least with VGA+HDMI cloning. Suppress them.
5000 */
5001 if (intel_crtc->config->has_pch_encoder) {
5002 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5003 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5004 }
5005
5006 for_each_encoder_on_crtc(dev, crtc, encoder)
5007 encoder->disable(encoder);
5008
5009 drm_crtc_vblank_off(crtc);
5010 assert_vblank_disabled(crtc);
5011
5012 intel_disable_pipe(intel_crtc);
5013
5014 ironlake_pfit_disable(intel_crtc, false);
5015
5016 if (intel_crtc->config->has_pch_encoder)
5017 ironlake_fdi_disable(crtc);
5018
5019 for_each_encoder_on_crtc(dev, crtc, encoder)
5020 if (encoder->post_disable)
5021 encoder->post_disable(encoder);
5022
5023 if (intel_crtc->config->has_pch_encoder) {
5024 ironlake_disable_pch_transcoder(dev_priv, pipe);
5025
5026 if (HAS_PCH_CPT(dev)) {
5027 i915_reg_t reg;
5028 u32 temp;
5029
5030 /* disable TRANS_DP_CTL */
5031 reg = TRANS_DP_CTL(pipe);
5032 temp = I915_READ(reg);
5033 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5034 TRANS_DP_PORT_SEL_MASK);
5035 temp |= TRANS_DP_PORT_SEL_NONE;
5036 I915_WRITE(reg, temp);
5037
5038 /* disable DPLL_SEL */
5039 temp = I915_READ(PCH_DPLL_SEL);
5040 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5041 I915_WRITE(PCH_DPLL_SEL, temp);
5042 }
5043
5044 ironlake_fdi_pll_disable(intel_crtc);
5045 }
5046
5047 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5048 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5049 }
5050
5051 static void haswell_crtc_disable(struct drm_crtc *crtc)
5052 {
5053 struct drm_device *dev = crtc->dev;
5054 struct drm_i915_private *dev_priv = to_i915(dev);
5055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5056 struct intel_encoder *encoder;
5057 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5058
5059 if (intel_crtc->config->has_pch_encoder)
5060 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5061 false);
5062
5063 for_each_encoder_on_crtc(dev, crtc, encoder) {
5064 intel_opregion_notify_encoder(encoder, false);
5065 encoder->disable(encoder);
5066 }
5067
5068 drm_crtc_vblank_off(crtc);
5069 assert_vblank_disabled(crtc);
5070
5071 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5072 if (!intel_crtc->config->has_dsi_encoder)
5073 intel_disable_pipe(intel_crtc);
5074
5075 if (intel_crtc->config->dp_encoder_is_mst)
5076 intel_ddi_set_vc_payload_alloc(crtc, false);
5077
5078 if (!intel_crtc->config->has_dsi_encoder)
5079 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5080
5081 if (INTEL_INFO(dev)->gen >= 9)
5082 skylake_scaler_disable(intel_crtc);
5083 else
5084 ironlake_pfit_disable(intel_crtc, false);
5085
5086 if (!intel_crtc->config->has_dsi_encoder)
5087 intel_ddi_disable_pipe_clock(intel_crtc);
5088
5089 for_each_encoder_on_crtc(dev, crtc, encoder)
5090 if (encoder->post_disable)
5091 encoder->post_disable(encoder);
5092
5093 if (intel_crtc->config->has_pch_encoder) {
5094 lpt_disable_pch_transcoder(dev_priv);
5095 lpt_disable_iclkip(dev_priv);
5096 intel_ddi_fdi_disable(crtc);
5097
5098 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5099 true);
5100 }
5101 }
5102
5103 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5104 {
5105 struct drm_device *dev = crtc->base.dev;
5106 struct drm_i915_private *dev_priv = to_i915(dev);
5107 struct intel_crtc_state *pipe_config = crtc->config;
5108
5109 if (!pipe_config->gmch_pfit.control)
5110 return;
5111
5112 /*
5113 * The panel fitter should only be adjusted whilst the pipe is disabled,
5114 * according to register description and PRM.
5115 */
5116 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5117 assert_pipe_disabled(dev_priv, crtc->pipe);
5118
5119 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5120 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5121
5122 /* Border color in case we don't scale up to the full screen. Black by
5123 * default, change to something else for debugging. */
5124 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5125 }
5126
5127 static enum intel_display_power_domain port_to_power_domain(enum port port)
5128 {
5129 switch (port) {
5130 case PORT_A:
5131 return POWER_DOMAIN_PORT_DDI_A_LANES;
5132 case PORT_B:
5133 return POWER_DOMAIN_PORT_DDI_B_LANES;
5134 case PORT_C:
5135 return POWER_DOMAIN_PORT_DDI_C_LANES;
5136 case PORT_D:
5137 return POWER_DOMAIN_PORT_DDI_D_LANES;
5138 case PORT_E:
5139 return POWER_DOMAIN_PORT_DDI_E_LANES;
5140 default:
5141 MISSING_CASE(port);
5142 return POWER_DOMAIN_PORT_OTHER;
5143 }
5144 }
5145
5146 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5147 {
5148 switch (port) {
5149 case PORT_A:
5150 return POWER_DOMAIN_AUX_A;
5151 case PORT_B:
5152 return POWER_DOMAIN_AUX_B;
5153 case PORT_C:
5154 return POWER_DOMAIN_AUX_C;
5155 case PORT_D:
5156 return POWER_DOMAIN_AUX_D;
5157 case PORT_E:
5158 /* FIXME: Check VBT for actual wiring of PORT E */
5159 return POWER_DOMAIN_AUX_D;
5160 default:
5161 MISSING_CASE(port);
5162 return POWER_DOMAIN_AUX_A;
5163 }
5164 }
5165
5166 enum intel_display_power_domain
5167 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5168 {
5169 struct drm_device *dev = intel_encoder->base.dev;
5170 struct intel_digital_port *intel_dig_port;
5171
5172 switch (intel_encoder->type) {
5173 case INTEL_OUTPUT_UNKNOWN:
5174 /* Only DDI platforms should ever use this output type */
5175 WARN_ON_ONCE(!HAS_DDI(dev));
5176 case INTEL_OUTPUT_DISPLAYPORT:
5177 case INTEL_OUTPUT_HDMI:
5178 case INTEL_OUTPUT_EDP:
5179 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5180 return port_to_power_domain(intel_dig_port->port);
5181 case INTEL_OUTPUT_DP_MST:
5182 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5183 return port_to_power_domain(intel_dig_port->port);
5184 case INTEL_OUTPUT_ANALOG:
5185 return POWER_DOMAIN_PORT_CRT;
5186 case INTEL_OUTPUT_DSI:
5187 return POWER_DOMAIN_PORT_DSI;
5188 default:
5189 return POWER_DOMAIN_PORT_OTHER;
5190 }
5191 }
5192
5193 enum intel_display_power_domain
5194 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5195 {
5196 struct drm_device *dev = intel_encoder->base.dev;
5197 struct intel_digital_port *intel_dig_port;
5198
5199 switch (intel_encoder->type) {
5200 case INTEL_OUTPUT_UNKNOWN:
5201 case INTEL_OUTPUT_HDMI:
5202 /*
5203 * Only DDI platforms should ever use these output types.
5204 * We can get here after the HDMI detect code has already set
5205 * the type of the shared encoder. Since we can't be sure
5206 * what's the status of the given connectors, play safe and
5207 * run the DP detection too.
5208 */
5209 WARN_ON_ONCE(!HAS_DDI(dev));
5210 case INTEL_OUTPUT_DISPLAYPORT:
5211 case INTEL_OUTPUT_EDP:
5212 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5213 return port_to_aux_power_domain(intel_dig_port->port);
5214 case INTEL_OUTPUT_DP_MST:
5215 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5216 return port_to_aux_power_domain(intel_dig_port->port);
5217 default:
5218 MISSING_CASE(intel_encoder->type);
5219 return POWER_DOMAIN_AUX_A;
5220 }
5221 }
5222
5223 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5224 struct intel_crtc_state *crtc_state)
5225 {
5226 struct drm_device *dev = crtc->dev;
5227 struct drm_encoder *encoder;
5228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5229 enum pipe pipe = intel_crtc->pipe;
5230 unsigned long mask;
5231 enum transcoder transcoder = crtc_state->cpu_transcoder;
5232
5233 if (!crtc_state->base.active)
5234 return 0;
5235
5236 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5237 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5238 if (crtc_state->pch_pfit.enabled ||
5239 crtc_state->pch_pfit.force_thru)
5240 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5241
5242 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5243 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5244
5245 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5246 }
5247
5248 if (crtc_state->shared_dpll)
5249 mask |= BIT(POWER_DOMAIN_PLLS);
5250
5251 return mask;
5252 }
5253
5254 static unsigned long
5255 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5256 struct intel_crtc_state *crtc_state)
5257 {
5258 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5260 enum intel_display_power_domain domain;
5261 unsigned long domains, new_domains, old_domains;
5262
5263 old_domains = intel_crtc->enabled_power_domains;
5264 intel_crtc->enabled_power_domains = new_domains =
5265 get_crtc_power_domains(crtc, crtc_state);
5266
5267 domains = new_domains & ~old_domains;
5268
5269 for_each_power_domain(domain, domains)
5270 intel_display_power_get(dev_priv, domain);
5271
5272 return old_domains & ~new_domains;
5273 }
5274
5275 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5276 unsigned long domains)
5277 {
5278 enum intel_display_power_domain domain;
5279
5280 for_each_power_domain(domain, domains)
5281 intel_display_power_put(dev_priv, domain);
5282 }
5283
5284 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5285 {
5286 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5287
5288 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5289 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5290 return max_cdclk_freq;
5291 else if (IS_CHERRYVIEW(dev_priv))
5292 return max_cdclk_freq*95/100;
5293 else if (INTEL_INFO(dev_priv)->gen < 4)
5294 return 2*max_cdclk_freq*90/100;
5295 else
5296 return max_cdclk_freq*90/100;
5297 }
5298
5299 static int skl_calc_cdclk(int max_pixclk, int vco);
5300
5301 static void intel_update_max_cdclk(struct drm_device *dev)
5302 {
5303 struct drm_i915_private *dev_priv = to_i915(dev);
5304
5305 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5306 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5307 int max_cdclk, vco;
5308
5309 vco = dev_priv->skl_preferred_vco_freq;
5310 WARN_ON(vco != 8100000 && vco != 8640000);
5311
5312 /*
5313 * Use the lower (vco 8640) cdclk values as a
5314 * first guess. skl_calc_cdclk() will correct it
5315 * if the preferred vco is 8100 instead.
5316 */
5317 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5318 max_cdclk = 617143;
5319 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5320 max_cdclk = 540000;
5321 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5322 max_cdclk = 432000;
5323 else
5324 max_cdclk = 308571;
5325
5326 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5327 } else if (IS_BROXTON(dev)) {
5328 dev_priv->max_cdclk_freq = 624000;
5329 } else if (IS_BROADWELL(dev)) {
5330 /*
5331 * FIXME with extra cooling we can allow
5332 * 540 MHz for ULX and 675 Mhz for ULT.
5333 * How can we know if extra cooling is
5334 * available? PCI ID, VTB, something else?
5335 */
5336 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5337 dev_priv->max_cdclk_freq = 450000;
5338 else if (IS_BDW_ULX(dev))
5339 dev_priv->max_cdclk_freq = 450000;
5340 else if (IS_BDW_ULT(dev))
5341 dev_priv->max_cdclk_freq = 540000;
5342 else
5343 dev_priv->max_cdclk_freq = 675000;
5344 } else if (IS_CHERRYVIEW(dev)) {
5345 dev_priv->max_cdclk_freq = 320000;
5346 } else if (IS_VALLEYVIEW(dev)) {
5347 dev_priv->max_cdclk_freq = 400000;
5348 } else {
5349 /* otherwise assume cdclk is fixed */
5350 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5351 }
5352
5353 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5354
5355 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5356 dev_priv->max_cdclk_freq);
5357
5358 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5359 dev_priv->max_dotclk_freq);
5360 }
5361
5362 static void intel_update_cdclk(struct drm_device *dev)
5363 {
5364 struct drm_i915_private *dev_priv = to_i915(dev);
5365
5366 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5367
5368 if (INTEL_GEN(dev_priv) >= 9)
5369 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5370 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5371 dev_priv->cdclk_pll.ref);
5372 else
5373 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5374 dev_priv->cdclk_freq);
5375
5376 /*
5377 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5378 * Programmng [sic] note: bit[9:2] should be programmed to the number
5379 * of cdclk that generates 4MHz reference clock freq which is used to
5380 * generate GMBus clock. This will vary with the cdclk freq.
5381 */
5382 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5383 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5384 }
5385
5386 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5387 static int skl_cdclk_decimal(int cdclk)
5388 {
5389 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5390 }
5391
5392 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5393 {
5394 int ratio;
5395
5396 if (cdclk == dev_priv->cdclk_pll.ref)
5397 return 0;
5398
5399 switch (cdclk) {
5400 default:
5401 MISSING_CASE(cdclk);
5402 case 144000:
5403 case 288000:
5404 case 384000:
5405 case 576000:
5406 ratio = 60;
5407 break;
5408 case 624000:
5409 ratio = 65;
5410 break;
5411 }
5412
5413 return dev_priv->cdclk_pll.ref * ratio;
5414 }
5415
5416 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5417 {
5418 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5419
5420 /* Timeout 200us */
5421 if (intel_wait_for_register(dev_priv,
5422 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5423 1))
5424 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5425
5426 dev_priv->cdclk_pll.vco = 0;
5427 }
5428
5429 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5430 {
5431 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5432 u32 val;
5433
5434 val = I915_READ(BXT_DE_PLL_CTL);
5435 val &= ~BXT_DE_PLL_RATIO_MASK;
5436 val |= BXT_DE_PLL_RATIO(ratio);
5437 I915_WRITE(BXT_DE_PLL_CTL, val);
5438
5439 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5440
5441 /* Timeout 200us */
5442 if (intel_wait_for_register(dev_priv,
5443 BXT_DE_PLL_ENABLE,
5444 BXT_DE_PLL_LOCK,
5445 BXT_DE_PLL_LOCK,
5446 1))
5447 DRM_ERROR("timeout waiting for DE PLL lock\n");
5448
5449 dev_priv->cdclk_pll.vco = vco;
5450 }
5451
5452 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5453 {
5454 u32 val, divider;
5455 int vco, ret;
5456
5457 vco = bxt_de_pll_vco(dev_priv, cdclk);
5458
5459 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5460
5461 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5462 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5463 case 8:
5464 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5465 break;
5466 case 4:
5467 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5468 break;
5469 case 3:
5470 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5471 break;
5472 case 2:
5473 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5474 break;
5475 default:
5476 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5477 WARN_ON(vco != 0);
5478
5479 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5480 break;
5481 }
5482
5483 /* Inform power controller of upcoming frequency change */
5484 mutex_lock(&dev_priv->rps.hw_lock);
5485 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5486 0x80000000);
5487 mutex_unlock(&dev_priv->rps.hw_lock);
5488
5489 if (ret) {
5490 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5491 ret, cdclk);
5492 return;
5493 }
5494
5495 if (dev_priv->cdclk_pll.vco != 0 &&
5496 dev_priv->cdclk_pll.vco != vco)
5497 bxt_de_pll_disable(dev_priv);
5498
5499 if (dev_priv->cdclk_pll.vco != vco)
5500 bxt_de_pll_enable(dev_priv, vco);
5501
5502 val = divider | skl_cdclk_decimal(cdclk);
5503 /*
5504 * FIXME if only the cd2x divider needs changing, it could be done
5505 * without shutting off the pipe (if only one pipe is active).
5506 */
5507 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5508 /*
5509 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5510 * enable otherwise.
5511 */
5512 if (cdclk >= 500000)
5513 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5514 I915_WRITE(CDCLK_CTL, val);
5515
5516 mutex_lock(&dev_priv->rps.hw_lock);
5517 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5518 DIV_ROUND_UP(cdclk, 25000));
5519 mutex_unlock(&dev_priv->rps.hw_lock);
5520
5521 if (ret) {
5522 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5523 ret, cdclk);
5524 return;
5525 }
5526
5527 intel_update_cdclk(dev_priv->dev);
5528 }
5529
5530 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5531 {
5532 u32 cdctl, expected;
5533
5534 intel_update_cdclk(dev_priv->dev);
5535
5536 if (dev_priv->cdclk_pll.vco == 0 ||
5537 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5538 goto sanitize;
5539
5540 /* DPLL okay; verify the cdclock
5541 *
5542 * Some BIOS versions leave an incorrect decimal frequency value and
5543 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5544 * so sanitize this register.
5545 */
5546 cdctl = I915_READ(CDCLK_CTL);
5547 /*
5548 * Let's ignore the pipe field, since BIOS could have configured the
5549 * dividers both synching to an active pipe, or asynchronously
5550 * (PIPE_NONE).
5551 */
5552 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5553
5554 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5555 skl_cdclk_decimal(dev_priv->cdclk_freq);
5556 /*
5557 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5558 * enable otherwise.
5559 */
5560 if (dev_priv->cdclk_freq >= 500000)
5561 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5562
5563 if (cdctl == expected)
5564 /* All well; nothing to sanitize */
5565 return;
5566
5567 sanitize:
5568 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5569
5570 /* force cdclk programming */
5571 dev_priv->cdclk_freq = 0;
5572
5573 /* force full PLL disable + enable */
5574 dev_priv->cdclk_pll.vco = -1;
5575 }
5576
5577 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
5578 {
5579 bxt_sanitize_cdclk(dev_priv);
5580
5581 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
5582 return;
5583
5584 /*
5585 * FIXME:
5586 * - The initial CDCLK needs to be read from VBT.
5587 * Need to make this change after VBT has changes for BXT.
5588 */
5589 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
5590 }
5591
5592 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
5593 {
5594 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
5595 }
5596
5597 static int skl_calc_cdclk(int max_pixclk, int vco)
5598 {
5599 if (vco == 8640000) {
5600 if (max_pixclk > 540000)
5601 return 617143;
5602 else if (max_pixclk > 432000)
5603 return 540000;
5604 else if (max_pixclk > 308571)
5605 return 432000;
5606 else
5607 return 308571;
5608 } else {
5609 if (max_pixclk > 540000)
5610 return 675000;
5611 else if (max_pixclk > 450000)
5612 return 540000;
5613 else if (max_pixclk > 337500)
5614 return 450000;
5615 else
5616 return 337500;
5617 }
5618 }
5619
5620 static void
5621 skl_dpll0_update(struct drm_i915_private *dev_priv)
5622 {
5623 u32 val;
5624
5625 dev_priv->cdclk_pll.ref = 24000;
5626 dev_priv->cdclk_pll.vco = 0;
5627
5628 val = I915_READ(LCPLL1_CTL);
5629 if ((val & LCPLL_PLL_ENABLE) == 0)
5630 return;
5631
5632 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
5633 return;
5634
5635 val = I915_READ(DPLL_CTRL1);
5636
5637 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5638 DPLL_CTRL1_SSC(SKL_DPLL0) |
5639 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5640 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
5641 return;
5642
5643 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5644 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5645 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5646 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5647 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5648 dev_priv->cdclk_pll.vco = 8100000;
5649 break;
5650 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5651 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5652 dev_priv->cdclk_pll.vco = 8640000;
5653 break;
5654 default:
5655 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5656 break;
5657 }
5658 }
5659
5660 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5661 {
5662 bool changed = dev_priv->skl_preferred_vco_freq != vco;
5663
5664 dev_priv->skl_preferred_vco_freq = vco;
5665
5666 if (changed)
5667 intel_update_max_cdclk(dev_priv->dev);
5668 }
5669
5670 static void
5671 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5672 {
5673 int min_cdclk = skl_calc_cdclk(0, vco);
5674 u32 val;
5675
5676 WARN_ON(vco != 8100000 && vco != 8640000);
5677
5678 /* select the minimum CDCLK before enabling DPLL 0 */
5679 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5680 I915_WRITE(CDCLK_CTL, val);
5681 POSTING_READ(CDCLK_CTL);
5682
5683 /*
5684 * We always enable DPLL0 with the lowest link rate possible, but still
5685 * taking into account the VCO required to operate the eDP panel at the
5686 * desired frequency. The usual DP link rates operate with a VCO of
5687 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5688 * The modeset code is responsible for the selection of the exact link
5689 * rate later on, with the constraint of choosing a frequency that
5690 * works with vco.
5691 */
5692 val = I915_READ(DPLL_CTRL1);
5693
5694 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5695 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5696 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5697 if (vco == 8640000)
5698 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5699 SKL_DPLL0);
5700 else
5701 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5702 SKL_DPLL0);
5703
5704 I915_WRITE(DPLL_CTRL1, val);
5705 POSTING_READ(DPLL_CTRL1);
5706
5707 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5708
5709 if (intel_wait_for_register(dev_priv,
5710 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
5711 5))
5712 DRM_ERROR("DPLL0 not locked\n");
5713
5714 dev_priv->cdclk_pll.vco = vco;
5715
5716 /* We'll want to keep using the current vco from now on. */
5717 skl_set_preferred_cdclk_vco(dev_priv, vco);
5718 }
5719
5720 static void
5721 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5722 {
5723 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5724 if (intel_wait_for_register(dev_priv,
5725 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
5726 1))
5727 DRM_ERROR("Couldn't disable DPLL0\n");
5728
5729 dev_priv->cdclk_pll.vco = 0;
5730 }
5731
5732 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5733 {
5734 int ret;
5735 u32 val;
5736
5737 /* inform PCU we want to change CDCLK */
5738 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5739 mutex_lock(&dev_priv->rps.hw_lock);
5740 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5741 mutex_unlock(&dev_priv->rps.hw_lock);
5742
5743 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5744 }
5745
5746 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5747 {
5748 unsigned int i;
5749
5750 for (i = 0; i < 15; i++) {
5751 if (skl_cdclk_pcu_ready(dev_priv))
5752 return true;
5753 udelay(10);
5754 }
5755
5756 return false;
5757 }
5758
5759 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5760 {
5761 struct drm_device *dev = dev_priv->dev;
5762 u32 freq_select, pcu_ack;
5763
5764 WARN_ON((cdclk == 24000) != (vco == 0));
5765
5766 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5767
5768 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5769 DRM_ERROR("failed to inform PCU about cdclk change\n");
5770 return;
5771 }
5772
5773 /* set CDCLK_CTL */
5774 switch (cdclk) {
5775 case 450000:
5776 case 432000:
5777 freq_select = CDCLK_FREQ_450_432;
5778 pcu_ack = 1;
5779 break;
5780 case 540000:
5781 freq_select = CDCLK_FREQ_540;
5782 pcu_ack = 2;
5783 break;
5784 case 308571:
5785 case 337500:
5786 default:
5787 freq_select = CDCLK_FREQ_337_308;
5788 pcu_ack = 0;
5789 break;
5790 case 617143:
5791 case 675000:
5792 freq_select = CDCLK_FREQ_675_617;
5793 pcu_ack = 3;
5794 break;
5795 }
5796
5797 if (dev_priv->cdclk_pll.vco != 0 &&
5798 dev_priv->cdclk_pll.vco != vco)
5799 skl_dpll0_disable(dev_priv);
5800
5801 if (dev_priv->cdclk_pll.vco != vco)
5802 skl_dpll0_enable(dev_priv, vco);
5803
5804 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5805 POSTING_READ(CDCLK_CTL);
5806
5807 /* inform PCU of the change */
5808 mutex_lock(&dev_priv->rps.hw_lock);
5809 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5810 mutex_unlock(&dev_priv->rps.hw_lock);
5811
5812 intel_update_cdclk(dev);
5813 }
5814
5815 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5816
5817 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5818 {
5819 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5820 }
5821
5822 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5823 {
5824 int cdclk, vco;
5825
5826 skl_sanitize_cdclk(dev_priv);
5827
5828 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
5829 /*
5830 * Use the current vco as our initial
5831 * guess as to what the preferred vco is.
5832 */
5833 if (dev_priv->skl_preferred_vco_freq == 0)
5834 skl_set_preferred_cdclk_vco(dev_priv,
5835 dev_priv->cdclk_pll.vco);
5836 return;
5837 }
5838
5839 vco = dev_priv->skl_preferred_vco_freq;
5840 if (vco == 0)
5841 vco = 8100000;
5842 cdclk = skl_calc_cdclk(0, vco);
5843
5844 skl_set_cdclk(dev_priv, cdclk, vco);
5845 }
5846
5847 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5848 {
5849 uint32_t cdctl, expected;
5850
5851 /*
5852 * check if the pre-os intialized the display
5853 * There is SWF18 scratchpad register defined which is set by the
5854 * pre-os which can be used by the OS drivers to check the status
5855 */
5856 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5857 goto sanitize;
5858
5859 intel_update_cdclk(dev_priv->dev);
5860 /* Is PLL enabled and locked ? */
5861 if (dev_priv->cdclk_pll.vco == 0 ||
5862 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5863 goto sanitize;
5864
5865 /* DPLL okay; verify the cdclock
5866 *
5867 * Noticed in some instances that the freq selection is correct but
5868 * decimal part is programmed wrong from BIOS where pre-os does not
5869 * enable display. Verify the same as well.
5870 */
5871 cdctl = I915_READ(CDCLK_CTL);
5872 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5873 skl_cdclk_decimal(dev_priv->cdclk_freq);
5874 if (cdctl == expected)
5875 /* All well; nothing to sanitize */
5876 return;
5877
5878 sanitize:
5879 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5880
5881 /* force cdclk programming */
5882 dev_priv->cdclk_freq = 0;
5883 /* force full PLL disable + enable */
5884 dev_priv->cdclk_pll.vco = -1;
5885 }
5886
5887 /* Adjust CDclk dividers to allow high res or save power if possible */
5888 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5889 {
5890 struct drm_i915_private *dev_priv = to_i915(dev);
5891 u32 val, cmd;
5892
5893 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5894 != dev_priv->cdclk_freq);
5895
5896 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5897 cmd = 2;
5898 else if (cdclk == 266667)
5899 cmd = 1;
5900 else
5901 cmd = 0;
5902
5903 mutex_lock(&dev_priv->rps.hw_lock);
5904 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5905 val &= ~DSPFREQGUAR_MASK;
5906 val |= (cmd << DSPFREQGUAR_SHIFT);
5907 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5908 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5909 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5910 50)) {
5911 DRM_ERROR("timed out waiting for CDclk change\n");
5912 }
5913 mutex_unlock(&dev_priv->rps.hw_lock);
5914
5915 mutex_lock(&dev_priv->sb_lock);
5916
5917 if (cdclk == 400000) {
5918 u32 divider;
5919
5920 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5921
5922 /* adjust cdclk divider */
5923 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5924 val &= ~CCK_FREQUENCY_VALUES;
5925 val |= divider;
5926 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5927
5928 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5929 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5930 50))
5931 DRM_ERROR("timed out waiting for CDclk change\n");
5932 }
5933
5934 /* adjust self-refresh exit latency value */
5935 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5936 val &= ~0x7f;
5937
5938 /*
5939 * For high bandwidth configs, we set a higher latency in the bunit
5940 * so that the core display fetch happens in time to avoid underruns.
5941 */
5942 if (cdclk == 400000)
5943 val |= 4500 / 250; /* 4.5 usec */
5944 else
5945 val |= 3000 / 250; /* 3.0 usec */
5946 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5947
5948 mutex_unlock(&dev_priv->sb_lock);
5949
5950 intel_update_cdclk(dev);
5951 }
5952
5953 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5954 {
5955 struct drm_i915_private *dev_priv = to_i915(dev);
5956 u32 val, cmd;
5957
5958 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5959 != dev_priv->cdclk_freq);
5960
5961 switch (cdclk) {
5962 case 333333:
5963 case 320000:
5964 case 266667:
5965 case 200000:
5966 break;
5967 default:
5968 MISSING_CASE(cdclk);
5969 return;
5970 }
5971
5972 /*
5973 * Specs are full of misinformation, but testing on actual
5974 * hardware has shown that we just need to write the desired
5975 * CCK divider into the Punit register.
5976 */
5977 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5978
5979 mutex_lock(&dev_priv->rps.hw_lock);
5980 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5981 val &= ~DSPFREQGUAR_MASK_CHV;
5982 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5983 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5984 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5985 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5986 50)) {
5987 DRM_ERROR("timed out waiting for CDclk change\n");
5988 }
5989 mutex_unlock(&dev_priv->rps.hw_lock);
5990
5991 intel_update_cdclk(dev);
5992 }
5993
5994 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5995 int max_pixclk)
5996 {
5997 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5998 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5999
6000 /*
6001 * Really only a few cases to deal with, as only 4 CDclks are supported:
6002 * 200MHz
6003 * 267MHz
6004 * 320/333MHz (depends on HPLL freq)
6005 * 400MHz (VLV only)
6006 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6007 * of the lower bin and adjust if needed.
6008 *
6009 * We seem to get an unstable or solid color picture at 200MHz.
6010 * Not sure what's wrong. For now use 200MHz only when all pipes
6011 * are off.
6012 */
6013 if (!IS_CHERRYVIEW(dev_priv) &&
6014 max_pixclk > freq_320*limit/100)
6015 return 400000;
6016 else if (max_pixclk > 266667*limit/100)
6017 return freq_320;
6018 else if (max_pixclk > 0)
6019 return 266667;
6020 else
6021 return 200000;
6022 }
6023
6024 static int bxt_calc_cdclk(int max_pixclk)
6025 {
6026 if (max_pixclk > 576000)
6027 return 624000;
6028 else if (max_pixclk > 384000)
6029 return 576000;
6030 else if (max_pixclk > 288000)
6031 return 384000;
6032 else if (max_pixclk > 144000)
6033 return 288000;
6034 else
6035 return 144000;
6036 }
6037
6038 /* Compute the max pixel clock for new configuration. */
6039 static int intel_mode_max_pixclk(struct drm_device *dev,
6040 struct drm_atomic_state *state)
6041 {
6042 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6043 struct drm_i915_private *dev_priv = to_i915(dev);
6044 struct drm_crtc *crtc;
6045 struct drm_crtc_state *crtc_state;
6046 unsigned max_pixclk = 0, i;
6047 enum pipe pipe;
6048
6049 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6050 sizeof(intel_state->min_pixclk));
6051
6052 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6053 int pixclk = 0;
6054
6055 if (crtc_state->enable)
6056 pixclk = crtc_state->adjusted_mode.crtc_clock;
6057
6058 intel_state->min_pixclk[i] = pixclk;
6059 }
6060
6061 for_each_pipe(dev_priv, pipe)
6062 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6063
6064 return max_pixclk;
6065 }
6066
6067 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6068 {
6069 struct drm_device *dev = state->dev;
6070 struct drm_i915_private *dev_priv = to_i915(dev);
6071 int max_pixclk = intel_mode_max_pixclk(dev, state);
6072 struct intel_atomic_state *intel_state =
6073 to_intel_atomic_state(state);
6074
6075 intel_state->cdclk = intel_state->dev_cdclk =
6076 valleyview_calc_cdclk(dev_priv, max_pixclk);
6077
6078 if (!intel_state->active_crtcs)
6079 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6080
6081 return 0;
6082 }
6083
6084 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6085 {
6086 int max_pixclk = ilk_max_pixel_rate(state);
6087 struct intel_atomic_state *intel_state =
6088 to_intel_atomic_state(state);
6089
6090 intel_state->cdclk = intel_state->dev_cdclk =
6091 bxt_calc_cdclk(max_pixclk);
6092
6093 if (!intel_state->active_crtcs)
6094 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6095
6096 return 0;
6097 }
6098
6099 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6100 {
6101 unsigned int credits, default_credits;
6102
6103 if (IS_CHERRYVIEW(dev_priv))
6104 default_credits = PFI_CREDIT(12);
6105 else
6106 default_credits = PFI_CREDIT(8);
6107
6108 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6109 /* CHV suggested value is 31 or 63 */
6110 if (IS_CHERRYVIEW(dev_priv))
6111 credits = PFI_CREDIT_63;
6112 else
6113 credits = PFI_CREDIT(15);
6114 } else {
6115 credits = default_credits;
6116 }
6117
6118 /*
6119 * WA - write default credits before re-programming
6120 * FIXME: should we also set the resend bit here?
6121 */
6122 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6123 default_credits);
6124
6125 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6126 credits | PFI_CREDIT_RESEND);
6127
6128 /*
6129 * FIXME is this guaranteed to clear
6130 * immediately or should we poll for it?
6131 */
6132 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6133 }
6134
6135 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6136 {
6137 struct drm_device *dev = old_state->dev;
6138 struct drm_i915_private *dev_priv = to_i915(dev);
6139 struct intel_atomic_state *old_intel_state =
6140 to_intel_atomic_state(old_state);
6141 unsigned req_cdclk = old_intel_state->dev_cdclk;
6142
6143 /*
6144 * FIXME: We can end up here with all power domains off, yet
6145 * with a CDCLK frequency other than the minimum. To account
6146 * for this take the PIPE-A power domain, which covers the HW
6147 * blocks needed for the following programming. This can be
6148 * removed once it's guaranteed that we get here either with
6149 * the minimum CDCLK set, or the required power domains
6150 * enabled.
6151 */
6152 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6153
6154 if (IS_CHERRYVIEW(dev))
6155 cherryview_set_cdclk(dev, req_cdclk);
6156 else
6157 valleyview_set_cdclk(dev, req_cdclk);
6158
6159 vlv_program_pfi_credits(dev_priv);
6160
6161 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6162 }
6163
6164 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6165 {
6166 struct drm_device *dev = crtc->dev;
6167 struct drm_i915_private *dev_priv = to_i915(dev);
6168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6169 struct intel_encoder *encoder;
6170 struct intel_crtc_state *pipe_config =
6171 to_intel_crtc_state(crtc->state);
6172 int pipe = intel_crtc->pipe;
6173
6174 if (WARN_ON(intel_crtc->active))
6175 return;
6176
6177 if (intel_crtc->config->has_dp_encoder)
6178 intel_dp_set_m_n(intel_crtc, M1_N1);
6179
6180 intel_set_pipe_timings(intel_crtc);
6181 intel_set_pipe_src_size(intel_crtc);
6182
6183 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6184 struct drm_i915_private *dev_priv = to_i915(dev);
6185
6186 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6187 I915_WRITE(CHV_CANVAS(pipe), 0);
6188 }
6189
6190 i9xx_set_pipeconf(intel_crtc);
6191
6192 intel_crtc->active = true;
6193
6194 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6195
6196 for_each_encoder_on_crtc(dev, crtc, encoder)
6197 if (encoder->pre_pll_enable)
6198 encoder->pre_pll_enable(encoder);
6199
6200 if (IS_CHERRYVIEW(dev)) {
6201 chv_prepare_pll(intel_crtc, intel_crtc->config);
6202 chv_enable_pll(intel_crtc, intel_crtc->config);
6203 } else {
6204 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6205 vlv_enable_pll(intel_crtc, intel_crtc->config);
6206 }
6207
6208 for_each_encoder_on_crtc(dev, crtc, encoder)
6209 if (encoder->pre_enable)
6210 encoder->pre_enable(encoder);
6211
6212 i9xx_pfit_enable(intel_crtc);
6213
6214 intel_color_load_luts(&pipe_config->base);
6215
6216 intel_update_watermarks(crtc);
6217 intel_enable_pipe(intel_crtc);
6218
6219 assert_vblank_disabled(crtc);
6220 drm_crtc_vblank_on(crtc);
6221
6222 for_each_encoder_on_crtc(dev, crtc, encoder)
6223 encoder->enable(encoder);
6224 }
6225
6226 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6227 {
6228 struct drm_device *dev = crtc->base.dev;
6229 struct drm_i915_private *dev_priv = to_i915(dev);
6230
6231 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6232 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6233 }
6234
6235 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6236 {
6237 struct drm_device *dev = crtc->dev;
6238 struct drm_i915_private *dev_priv = to_i915(dev);
6239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6240 struct intel_encoder *encoder;
6241 struct intel_crtc_state *pipe_config =
6242 to_intel_crtc_state(crtc->state);
6243 enum pipe pipe = intel_crtc->pipe;
6244
6245 if (WARN_ON(intel_crtc->active))
6246 return;
6247
6248 i9xx_set_pll_dividers(intel_crtc);
6249
6250 if (intel_crtc->config->has_dp_encoder)
6251 intel_dp_set_m_n(intel_crtc, M1_N1);
6252
6253 intel_set_pipe_timings(intel_crtc);
6254 intel_set_pipe_src_size(intel_crtc);
6255
6256 i9xx_set_pipeconf(intel_crtc);
6257
6258 intel_crtc->active = true;
6259
6260 if (!IS_GEN2(dev))
6261 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6262
6263 for_each_encoder_on_crtc(dev, crtc, encoder)
6264 if (encoder->pre_enable)
6265 encoder->pre_enable(encoder);
6266
6267 i9xx_enable_pll(intel_crtc);
6268
6269 i9xx_pfit_enable(intel_crtc);
6270
6271 intel_color_load_luts(&pipe_config->base);
6272
6273 intel_update_watermarks(crtc);
6274 intel_enable_pipe(intel_crtc);
6275
6276 assert_vblank_disabled(crtc);
6277 drm_crtc_vblank_on(crtc);
6278
6279 for_each_encoder_on_crtc(dev, crtc, encoder)
6280 encoder->enable(encoder);
6281 }
6282
6283 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6284 {
6285 struct drm_device *dev = crtc->base.dev;
6286 struct drm_i915_private *dev_priv = to_i915(dev);
6287
6288 if (!crtc->config->gmch_pfit.control)
6289 return;
6290
6291 assert_pipe_disabled(dev_priv, crtc->pipe);
6292
6293 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6294 I915_READ(PFIT_CONTROL));
6295 I915_WRITE(PFIT_CONTROL, 0);
6296 }
6297
6298 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6299 {
6300 struct drm_device *dev = crtc->dev;
6301 struct drm_i915_private *dev_priv = to_i915(dev);
6302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6303 struct intel_encoder *encoder;
6304 int pipe = intel_crtc->pipe;
6305
6306 /*
6307 * On gen2 planes are double buffered but the pipe isn't, so we must
6308 * wait for planes to fully turn off before disabling the pipe.
6309 */
6310 if (IS_GEN2(dev))
6311 intel_wait_for_vblank(dev, pipe);
6312
6313 for_each_encoder_on_crtc(dev, crtc, encoder)
6314 encoder->disable(encoder);
6315
6316 drm_crtc_vblank_off(crtc);
6317 assert_vblank_disabled(crtc);
6318
6319 intel_disable_pipe(intel_crtc);
6320
6321 i9xx_pfit_disable(intel_crtc);
6322
6323 for_each_encoder_on_crtc(dev, crtc, encoder)
6324 if (encoder->post_disable)
6325 encoder->post_disable(encoder);
6326
6327 if (!intel_crtc->config->has_dsi_encoder) {
6328 if (IS_CHERRYVIEW(dev))
6329 chv_disable_pll(dev_priv, pipe);
6330 else if (IS_VALLEYVIEW(dev))
6331 vlv_disable_pll(dev_priv, pipe);
6332 else
6333 i9xx_disable_pll(intel_crtc);
6334 }
6335
6336 for_each_encoder_on_crtc(dev, crtc, encoder)
6337 if (encoder->post_pll_disable)
6338 encoder->post_pll_disable(encoder);
6339
6340 if (!IS_GEN2(dev))
6341 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6342 }
6343
6344 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6345 {
6346 struct intel_encoder *encoder;
6347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6348 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6349 enum intel_display_power_domain domain;
6350 unsigned long domains;
6351
6352 if (!intel_crtc->active)
6353 return;
6354
6355 if (to_intel_plane_state(crtc->primary->state)->visible) {
6356 WARN_ON(intel_crtc->flip_work);
6357
6358 intel_pre_disable_primary_noatomic(crtc);
6359
6360 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6361 to_intel_plane_state(crtc->primary->state)->visible = false;
6362 }
6363
6364 dev_priv->display.crtc_disable(crtc);
6365
6366 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6367 crtc->base.id, crtc->name);
6368
6369 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6370 crtc->state->active = false;
6371 intel_crtc->active = false;
6372 crtc->enabled = false;
6373 crtc->state->connector_mask = 0;
6374 crtc->state->encoder_mask = 0;
6375
6376 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6377 encoder->base.crtc = NULL;
6378
6379 intel_fbc_disable(intel_crtc);
6380 intel_update_watermarks(crtc);
6381 intel_disable_shared_dpll(intel_crtc);
6382
6383 domains = intel_crtc->enabled_power_domains;
6384 for_each_power_domain(domain, domains)
6385 intel_display_power_put(dev_priv, domain);
6386 intel_crtc->enabled_power_domains = 0;
6387
6388 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6389 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6390 }
6391
6392 /*
6393 * turn all crtc's off, but do not adjust state
6394 * This has to be paired with a call to intel_modeset_setup_hw_state.
6395 */
6396 int intel_display_suspend(struct drm_device *dev)
6397 {
6398 struct drm_i915_private *dev_priv = to_i915(dev);
6399 struct drm_atomic_state *state;
6400 int ret;
6401
6402 state = drm_atomic_helper_suspend(dev);
6403 ret = PTR_ERR_OR_ZERO(state);
6404 if (ret)
6405 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6406 else
6407 dev_priv->modeset_restore_state = state;
6408 return ret;
6409 }
6410
6411 void intel_encoder_destroy(struct drm_encoder *encoder)
6412 {
6413 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6414
6415 drm_encoder_cleanup(encoder);
6416 kfree(intel_encoder);
6417 }
6418
6419 /* Cross check the actual hw state with our own modeset state tracking (and it's
6420 * internal consistency). */
6421 static void intel_connector_verify_state(struct intel_connector *connector)
6422 {
6423 struct drm_crtc *crtc = connector->base.state->crtc;
6424
6425 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6426 connector->base.base.id,
6427 connector->base.name);
6428
6429 if (connector->get_hw_state(connector)) {
6430 struct intel_encoder *encoder = connector->encoder;
6431 struct drm_connector_state *conn_state = connector->base.state;
6432
6433 I915_STATE_WARN(!crtc,
6434 "connector enabled without attached crtc\n");
6435
6436 if (!crtc)
6437 return;
6438
6439 I915_STATE_WARN(!crtc->state->active,
6440 "connector is active, but attached crtc isn't\n");
6441
6442 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6443 return;
6444
6445 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6446 "atomic encoder doesn't match attached encoder\n");
6447
6448 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6449 "attached encoder crtc differs from connector crtc\n");
6450 } else {
6451 I915_STATE_WARN(crtc && crtc->state->active,
6452 "attached crtc is active, but connector isn't\n");
6453 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6454 "best encoder set without crtc!\n");
6455 }
6456 }
6457
6458 int intel_connector_init(struct intel_connector *connector)
6459 {
6460 drm_atomic_helper_connector_reset(&connector->base);
6461
6462 if (!connector->base.state)
6463 return -ENOMEM;
6464
6465 return 0;
6466 }
6467
6468 struct intel_connector *intel_connector_alloc(void)
6469 {
6470 struct intel_connector *connector;
6471
6472 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6473 if (!connector)
6474 return NULL;
6475
6476 if (intel_connector_init(connector) < 0) {
6477 kfree(connector);
6478 return NULL;
6479 }
6480
6481 return connector;
6482 }
6483
6484 /* Simple connector->get_hw_state implementation for encoders that support only
6485 * one connector and no cloning and hence the encoder state determines the state
6486 * of the connector. */
6487 bool intel_connector_get_hw_state(struct intel_connector *connector)
6488 {
6489 enum pipe pipe = 0;
6490 struct intel_encoder *encoder = connector->encoder;
6491
6492 return encoder->get_hw_state(encoder, &pipe);
6493 }
6494
6495 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6496 {
6497 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6498 return crtc_state->fdi_lanes;
6499
6500 return 0;
6501 }
6502
6503 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6504 struct intel_crtc_state *pipe_config)
6505 {
6506 struct drm_atomic_state *state = pipe_config->base.state;
6507 struct intel_crtc *other_crtc;
6508 struct intel_crtc_state *other_crtc_state;
6509
6510 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6511 pipe_name(pipe), pipe_config->fdi_lanes);
6512 if (pipe_config->fdi_lanes > 4) {
6513 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6514 pipe_name(pipe), pipe_config->fdi_lanes);
6515 return -EINVAL;
6516 }
6517
6518 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6519 if (pipe_config->fdi_lanes > 2) {
6520 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6521 pipe_config->fdi_lanes);
6522 return -EINVAL;
6523 } else {
6524 return 0;
6525 }
6526 }
6527
6528 if (INTEL_INFO(dev)->num_pipes == 2)
6529 return 0;
6530
6531 /* Ivybridge 3 pipe is really complicated */
6532 switch (pipe) {
6533 case PIPE_A:
6534 return 0;
6535 case PIPE_B:
6536 if (pipe_config->fdi_lanes <= 2)
6537 return 0;
6538
6539 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6540 other_crtc_state =
6541 intel_atomic_get_crtc_state(state, other_crtc);
6542 if (IS_ERR(other_crtc_state))
6543 return PTR_ERR(other_crtc_state);
6544
6545 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6546 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6547 pipe_name(pipe), pipe_config->fdi_lanes);
6548 return -EINVAL;
6549 }
6550 return 0;
6551 case PIPE_C:
6552 if (pipe_config->fdi_lanes > 2) {
6553 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6554 pipe_name(pipe), pipe_config->fdi_lanes);
6555 return -EINVAL;
6556 }
6557
6558 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6559 other_crtc_state =
6560 intel_atomic_get_crtc_state(state, other_crtc);
6561 if (IS_ERR(other_crtc_state))
6562 return PTR_ERR(other_crtc_state);
6563
6564 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6565 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6566 return -EINVAL;
6567 }
6568 return 0;
6569 default:
6570 BUG();
6571 }
6572 }
6573
6574 #define RETRY 1
6575 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6576 struct intel_crtc_state *pipe_config)
6577 {
6578 struct drm_device *dev = intel_crtc->base.dev;
6579 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6580 int lane, link_bw, fdi_dotclock, ret;
6581 bool needs_recompute = false;
6582
6583 retry:
6584 /* FDI is a binary signal running at ~2.7GHz, encoding
6585 * each output octet as 10 bits. The actual frequency
6586 * is stored as a divider into a 100MHz clock, and the
6587 * mode pixel clock is stored in units of 1KHz.
6588 * Hence the bw of each lane in terms of the mode signal
6589 * is:
6590 */
6591 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6592
6593 fdi_dotclock = adjusted_mode->crtc_clock;
6594
6595 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6596 pipe_config->pipe_bpp);
6597
6598 pipe_config->fdi_lanes = lane;
6599
6600 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6601 link_bw, &pipe_config->fdi_m_n);
6602
6603 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6604 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6605 pipe_config->pipe_bpp -= 2*3;
6606 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6607 pipe_config->pipe_bpp);
6608 needs_recompute = true;
6609 pipe_config->bw_constrained = true;
6610
6611 goto retry;
6612 }
6613
6614 if (needs_recompute)
6615 return RETRY;
6616
6617 return ret;
6618 }
6619
6620 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6621 struct intel_crtc_state *pipe_config)
6622 {
6623 if (pipe_config->pipe_bpp > 24)
6624 return false;
6625
6626 /* HSW can handle pixel rate up to cdclk? */
6627 if (IS_HASWELL(dev_priv))
6628 return true;
6629
6630 /*
6631 * We compare against max which means we must take
6632 * the increased cdclk requirement into account when
6633 * calculating the new cdclk.
6634 *
6635 * Should measure whether using a lower cdclk w/o IPS
6636 */
6637 return ilk_pipe_pixel_rate(pipe_config) <=
6638 dev_priv->max_cdclk_freq * 95 / 100;
6639 }
6640
6641 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6642 struct intel_crtc_state *pipe_config)
6643 {
6644 struct drm_device *dev = crtc->base.dev;
6645 struct drm_i915_private *dev_priv = to_i915(dev);
6646
6647 pipe_config->ips_enabled = i915.enable_ips &&
6648 hsw_crtc_supports_ips(crtc) &&
6649 pipe_config_supports_ips(dev_priv, pipe_config);
6650 }
6651
6652 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6653 {
6654 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6655
6656 /* GDG double wide on either pipe, otherwise pipe A only */
6657 return INTEL_INFO(dev_priv)->gen < 4 &&
6658 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6659 }
6660
6661 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6662 struct intel_crtc_state *pipe_config)
6663 {
6664 struct drm_device *dev = crtc->base.dev;
6665 struct drm_i915_private *dev_priv = to_i915(dev);
6666 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6667 int clock_limit = dev_priv->max_dotclk_freq;
6668
6669 if (INTEL_INFO(dev)->gen < 4) {
6670 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6671
6672 /*
6673 * Enable double wide mode when the dot clock
6674 * is > 90% of the (display) core speed.
6675 */
6676 if (intel_crtc_supports_double_wide(crtc) &&
6677 adjusted_mode->crtc_clock > clock_limit) {
6678 clock_limit = dev_priv->max_dotclk_freq;
6679 pipe_config->double_wide = true;
6680 }
6681 }
6682
6683 if (adjusted_mode->crtc_clock > clock_limit) {
6684 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6685 adjusted_mode->crtc_clock, clock_limit,
6686 yesno(pipe_config->double_wide));
6687 return -EINVAL;
6688 }
6689
6690 /*
6691 * Pipe horizontal size must be even in:
6692 * - DVO ganged mode
6693 * - LVDS dual channel mode
6694 * - Double wide pipe
6695 */
6696 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6697 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6698 pipe_config->pipe_src_w &= ~1;
6699
6700 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6701 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6702 */
6703 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6704 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6705 return -EINVAL;
6706
6707 if (HAS_IPS(dev))
6708 hsw_compute_ips_config(crtc, pipe_config);
6709
6710 if (pipe_config->has_pch_encoder)
6711 return ironlake_fdi_compute_config(crtc, pipe_config);
6712
6713 return 0;
6714 }
6715
6716 static int skylake_get_display_clock_speed(struct drm_device *dev)
6717 {
6718 struct drm_i915_private *dev_priv = to_i915(dev);
6719 uint32_t cdctl;
6720
6721 skl_dpll0_update(dev_priv);
6722
6723 if (dev_priv->cdclk_pll.vco == 0)
6724 return dev_priv->cdclk_pll.ref;
6725
6726 cdctl = I915_READ(CDCLK_CTL);
6727
6728 if (dev_priv->cdclk_pll.vco == 8640000) {
6729 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6730 case CDCLK_FREQ_450_432:
6731 return 432000;
6732 case CDCLK_FREQ_337_308:
6733 return 308571;
6734 case CDCLK_FREQ_540:
6735 return 540000;
6736 case CDCLK_FREQ_675_617:
6737 return 617143;
6738 default:
6739 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6740 }
6741 } else {
6742 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6743 case CDCLK_FREQ_450_432:
6744 return 450000;
6745 case CDCLK_FREQ_337_308:
6746 return 337500;
6747 case CDCLK_FREQ_540:
6748 return 540000;
6749 case CDCLK_FREQ_675_617:
6750 return 675000;
6751 default:
6752 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6753 }
6754 }
6755
6756 return dev_priv->cdclk_pll.ref;
6757 }
6758
6759 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
6760 {
6761 u32 val;
6762
6763 dev_priv->cdclk_pll.ref = 19200;
6764 dev_priv->cdclk_pll.vco = 0;
6765
6766 val = I915_READ(BXT_DE_PLL_ENABLE);
6767 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
6768 return;
6769
6770 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
6771 return;
6772
6773 val = I915_READ(BXT_DE_PLL_CTL);
6774 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
6775 dev_priv->cdclk_pll.ref;
6776 }
6777
6778 static int broxton_get_display_clock_speed(struct drm_device *dev)
6779 {
6780 struct drm_i915_private *dev_priv = to_i915(dev);
6781 u32 divider;
6782 int div, vco;
6783
6784 bxt_de_pll_update(dev_priv);
6785
6786 vco = dev_priv->cdclk_pll.vco;
6787 if (vco == 0)
6788 return dev_priv->cdclk_pll.ref;
6789
6790 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
6791
6792 switch (divider) {
6793 case BXT_CDCLK_CD2X_DIV_SEL_1:
6794 div = 2;
6795 break;
6796 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6797 div = 3;
6798 break;
6799 case BXT_CDCLK_CD2X_DIV_SEL_2:
6800 div = 4;
6801 break;
6802 case BXT_CDCLK_CD2X_DIV_SEL_4:
6803 div = 8;
6804 break;
6805 default:
6806 MISSING_CASE(divider);
6807 return dev_priv->cdclk_pll.ref;
6808 }
6809
6810 return DIV_ROUND_CLOSEST(vco, div);
6811 }
6812
6813 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6814 {
6815 struct drm_i915_private *dev_priv = to_i915(dev);
6816 uint32_t lcpll = I915_READ(LCPLL_CTL);
6817 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6818
6819 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6820 return 800000;
6821 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6822 return 450000;
6823 else if (freq == LCPLL_CLK_FREQ_450)
6824 return 450000;
6825 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6826 return 540000;
6827 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6828 return 337500;
6829 else
6830 return 675000;
6831 }
6832
6833 static int haswell_get_display_clock_speed(struct drm_device *dev)
6834 {
6835 struct drm_i915_private *dev_priv = to_i915(dev);
6836 uint32_t lcpll = I915_READ(LCPLL_CTL);
6837 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6838
6839 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6840 return 800000;
6841 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6842 return 450000;
6843 else if (freq == LCPLL_CLK_FREQ_450)
6844 return 450000;
6845 else if (IS_HSW_ULT(dev))
6846 return 337500;
6847 else
6848 return 540000;
6849 }
6850
6851 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6852 {
6853 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6854 CCK_DISPLAY_CLOCK_CONTROL);
6855 }
6856
6857 static int ilk_get_display_clock_speed(struct drm_device *dev)
6858 {
6859 return 450000;
6860 }
6861
6862 static int i945_get_display_clock_speed(struct drm_device *dev)
6863 {
6864 return 400000;
6865 }
6866
6867 static int i915_get_display_clock_speed(struct drm_device *dev)
6868 {
6869 return 333333;
6870 }
6871
6872 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6873 {
6874 return 200000;
6875 }
6876
6877 static int pnv_get_display_clock_speed(struct drm_device *dev)
6878 {
6879 u16 gcfgc = 0;
6880
6881 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6882
6883 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6884 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6885 return 266667;
6886 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6887 return 333333;
6888 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6889 return 444444;
6890 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6891 return 200000;
6892 default:
6893 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6894 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6895 return 133333;
6896 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6897 return 166667;
6898 }
6899 }
6900
6901 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6902 {
6903 u16 gcfgc = 0;
6904
6905 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6906
6907 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6908 return 133333;
6909 else {
6910 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6911 case GC_DISPLAY_CLOCK_333_MHZ:
6912 return 333333;
6913 default:
6914 case GC_DISPLAY_CLOCK_190_200_MHZ:
6915 return 190000;
6916 }
6917 }
6918 }
6919
6920 static int i865_get_display_clock_speed(struct drm_device *dev)
6921 {
6922 return 266667;
6923 }
6924
6925 static int i85x_get_display_clock_speed(struct drm_device *dev)
6926 {
6927 u16 hpllcc = 0;
6928
6929 /*
6930 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6931 * encoding is different :(
6932 * FIXME is this the right way to detect 852GM/852GMV?
6933 */
6934 if (dev->pdev->revision == 0x1)
6935 return 133333;
6936
6937 pci_bus_read_config_word(dev->pdev->bus,
6938 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6939
6940 /* Assume that the hardware is in the high speed state. This
6941 * should be the default.
6942 */
6943 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6944 case GC_CLOCK_133_200:
6945 case GC_CLOCK_133_200_2:
6946 case GC_CLOCK_100_200:
6947 return 200000;
6948 case GC_CLOCK_166_250:
6949 return 250000;
6950 case GC_CLOCK_100_133:
6951 return 133333;
6952 case GC_CLOCK_133_266:
6953 case GC_CLOCK_133_266_2:
6954 case GC_CLOCK_166_266:
6955 return 266667;
6956 }
6957
6958 /* Shouldn't happen */
6959 return 0;
6960 }
6961
6962 static int i830_get_display_clock_speed(struct drm_device *dev)
6963 {
6964 return 133333;
6965 }
6966
6967 static unsigned int intel_hpll_vco(struct drm_device *dev)
6968 {
6969 struct drm_i915_private *dev_priv = to_i915(dev);
6970 static const unsigned int blb_vco[8] = {
6971 [0] = 3200000,
6972 [1] = 4000000,
6973 [2] = 5333333,
6974 [3] = 4800000,
6975 [4] = 6400000,
6976 };
6977 static const unsigned int pnv_vco[8] = {
6978 [0] = 3200000,
6979 [1] = 4000000,
6980 [2] = 5333333,
6981 [3] = 4800000,
6982 [4] = 2666667,
6983 };
6984 static const unsigned int cl_vco[8] = {
6985 [0] = 3200000,
6986 [1] = 4000000,
6987 [2] = 5333333,
6988 [3] = 6400000,
6989 [4] = 3333333,
6990 [5] = 3566667,
6991 [6] = 4266667,
6992 };
6993 static const unsigned int elk_vco[8] = {
6994 [0] = 3200000,
6995 [1] = 4000000,
6996 [2] = 5333333,
6997 [3] = 4800000,
6998 };
6999 static const unsigned int ctg_vco[8] = {
7000 [0] = 3200000,
7001 [1] = 4000000,
7002 [2] = 5333333,
7003 [3] = 6400000,
7004 [4] = 2666667,
7005 [5] = 4266667,
7006 };
7007 const unsigned int *vco_table;
7008 unsigned int vco;
7009 uint8_t tmp = 0;
7010
7011 /* FIXME other chipsets? */
7012 if (IS_GM45(dev))
7013 vco_table = ctg_vco;
7014 else if (IS_G4X(dev))
7015 vco_table = elk_vco;
7016 else if (IS_CRESTLINE(dev))
7017 vco_table = cl_vco;
7018 else if (IS_PINEVIEW(dev))
7019 vco_table = pnv_vco;
7020 else if (IS_G33(dev))
7021 vco_table = blb_vco;
7022 else
7023 return 0;
7024
7025 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7026
7027 vco = vco_table[tmp & 0x7];
7028 if (vco == 0)
7029 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7030 else
7031 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7032
7033 return vco;
7034 }
7035
7036 static int gm45_get_display_clock_speed(struct drm_device *dev)
7037 {
7038 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7039 uint16_t tmp = 0;
7040
7041 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7042
7043 cdclk_sel = (tmp >> 12) & 0x1;
7044
7045 switch (vco) {
7046 case 2666667:
7047 case 4000000:
7048 case 5333333:
7049 return cdclk_sel ? 333333 : 222222;
7050 case 3200000:
7051 return cdclk_sel ? 320000 : 228571;
7052 default:
7053 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7054 return 222222;
7055 }
7056 }
7057
7058 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7059 {
7060 static const uint8_t div_3200[] = { 16, 10, 8 };
7061 static const uint8_t div_4000[] = { 20, 12, 10 };
7062 static const uint8_t div_5333[] = { 24, 16, 14 };
7063 const uint8_t *div_table;
7064 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7065 uint16_t tmp = 0;
7066
7067 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7068
7069 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7070
7071 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7072 goto fail;
7073
7074 switch (vco) {
7075 case 3200000:
7076 div_table = div_3200;
7077 break;
7078 case 4000000:
7079 div_table = div_4000;
7080 break;
7081 case 5333333:
7082 div_table = div_5333;
7083 break;
7084 default:
7085 goto fail;
7086 }
7087
7088 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7089
7090 fail:
7091 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7092 return 200000;
7093 }
7094
7095 static int g33_get_display_clock_speed(struct drm_device *dev)
7096 {
7097 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7098 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7099 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7100 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7101 const uint8_t *div_table;
7102 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7103 uint16_t tmp = 0;
7104
7105 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7106
7107 cdclk_sel = (tmp >> 4) & 0x7;
7108
7109 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7110 goto fail;
7111
7112 switch (vco) {
7113 case 3200000:
7114 div_table = div_3200;
7115 break;
7116 case 4000000:
7117 div_table = div_4000;
7118 break;
7119 case 4800000:
7120 div_table = div_4800;
7121 break;
7122 case 5333333:
7123 div_table = div_5333;
7124 break;
7125 default:
7126 goto fail;
7127 }
7128
7129 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7130
7131 fail:
7132 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7133 return 190476;
7134 }
7135
7136 static void
7137 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7138 {
7139 while (*num > DATA_LINK_M_N_MASK ||
7140 *den > DATA_LINK_M_N_MASK) {
7141 *num >>= 1;
7142 *den >>= 1;
7143 }
7144 }
7145
7146 static void compute_m_n(unsigned int m, unsigned int n,
7147 uint32_t *ret_m, uint32_t *ret_n)
7148 {
7149 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7150 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7151 intel_reduce_m_n_ratio(ret_m, ret_n);
7152 }
7153
7154 void
7155 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7156 int pixel_clock, int link_clock,
7157 struct intel_link_m_n *m_n)
7158 {
7159 m_n->tu = 64;
7160
7161 compute_m_n(bits_per_pixel * pixel_clock,
7162 link_clock * nlanes * 8,
7163 &m_n->gmch_m, &m_n->gmch_n);
7164
7165 compute_m_n(pixel_clock, link_clock,
7166 &m_n->link_m, &m_n->link_n);
7167 }
7168
7169 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7170 {
7171 if (i915.panel_use_ssc >= 0)
7172 return i915.panel_use_ssc != 0;
7173 return dev_priv->vbt.lvds_use_ssc
7174 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7175 }
7176
7177 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7178 {
7179 return (1 << dpll->n) << 16 | dpll->m2;
7180 }
7181
7182 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7183 {
7184 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7185 }
7186
7187 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7188 struct intel_crtc_state *crtc_state,
7189 struct dpll *reduced_clock)
7190 {
7191 struct drm_device *dev = crtc->base.dev;
7192 u32 fp, fp2 = 0;
7193
7194 if (IS_PINEVIEW(dev)) {
7195 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7196 if (reduced_clock)
7197 fp2 = pnv_dpll_compute_fp(reduced_clock);
7198 } else {
7199 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7200 if (reduced_clock)
7201 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7202 }
7203
7204 crtc_state->dpll_hw_state.fp0 = fp;
7205
7206 crtc->lowfreq_avail = false;
7207 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7208 reduced_clock) {
7209 crtc_state->dpll_hw_state.fp1 = fp2;
7210 crtc->lowfreq_avail = true;
7211 } else {
7212 crtc_state->dpll_hw_state.fp1 = fp;
7213 }
7214 }
7215
7216 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7217 pipe)
7218 {
7219 u32 reg_val;
7220
7221 /*
7222 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7223 * and set it to a reasonable value instead.
7224 */
7225 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7226 reg_val &= 0xffffff00;
7227 reg_val |= 0x00000030;
7228 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7229
7230 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7231 reg_val &= 0x8cffffff;
7232 reg_val = 0x8c000000;
7233 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7234
7235 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7236 reg_val &= 0xffffff00;
7237 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7238
7239 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7240 reg_val &= 0x00ffffff;
7241 reg_val |= 0xb0000000;
7242 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7243 }
7244
7245 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7246 struct intel_link_m_n *m_n)
7247 {
7248 struct drm_device *dev = crtc->base.dev;
7249 struct drm_i915_private *dev_priv = to_i915(dev);
7250 int pipe = crtc->pipe;
7251
7252 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7253 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7254 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7255 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7256 }
7257
7258 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7259 struct intel_link_m_n *m_n,
7260 struct intel_link_m_n *m2_n2)
7261 {
7262 struct drm_device *dev = crtc->base.dev;
7263 struct drm_i915_private *dev_priv = to_i915(dev);
7264 int pipe = crtc->pipe;
7265 enum transcoder transcoder = crtc->config->cpu_transcoder;
7266
7267 if (INTEL_INFO(dev)->gen >= 5) {
7268 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7269 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7270 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7271 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7272 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7273 * for gen < 8) and if DRRS is supported (to make sure the
7274 * registers are not unnecessarily accessed).
7275 */
7276 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7277 crtc->config->has_drrs) {
7278 I915_WRITE(PIPE_DATA_M2(transcoder),
7279 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7280 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7281 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7282 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7283 }
7284 } else {
7285 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7286 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7287 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7288 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7289 }
7290 }
7291
7292 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7293 {
7294 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7295
7296 if (m_n == M1_N1) {
7297 dp_m_n = &crtc->config->dp_m_n;
7298 dp_m2_n2 = &crtc->config->dp_m2_n2;
7299 } else if (m_n == M2_N2) {
7300
7301 /*
7302 * M2_N2 registers are not supported. Hence m2_n2 divider value
7303 * needs to be programmed into M1_N1.
7304 */
7305 dp_m_n = &crtc->config->dp_m2_n2;
7306 } else {
7307 DRM_ERROR("Unsupported divider value\n");
7308 return;
7309 }
7310
7311 if (crtc->config->has_pch_encoder)
7312 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7313 else
7314 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7315 }
7316
7317 static void vlv_compute_dpll(struct intel_crtc *crtc,
7318 struct intel_crtc_state *pipe_config)
7319 {
7320 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7321 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7322 if (crtc->pipe != PIPE_A)
7323 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7324
7325 /* DPLL not used with DSI, but still need the rest set up */
7326 if (!pipe_config->has_dsi_encoder)
7327 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7328 DPLL_EXT_BUFFER_ENABLE_VLV;
7329
7330 pipe_config->dpll_hw_state.dpll_md =
7331 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7332 }
7333
7334 static void chv_compute_dpll(struct intel_crtc *crtc,
7335 struct intel_crtc_state *pipe_config)
7336 {
7337 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7338 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7339 if (crtc->pipe != PIPE_A)
7340 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7341
7342 /* DPLL not used with DSI, but still need the rest set up */
7343 if (!pipe_config->has_dsi_encoder)
7344 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7345
7346 pipe_config->dpll_hw_state.dpll_md =
7347 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7348 }
7349
7350 static void vlv_prepare_pll(struct intel_crtc *crtc,
7351 const struct intel_crtc_state *pipe_config)
7352 {
7353 struct drm_device *dev = crtc->base.dev;
7354 struct drm_i915_private *dev_priv = to_i915(dev);
7355 enum pipe pipe = crtc->pipe;
7356 u32 mdiv;
7357 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7358 u32 coreclk, reg_val;
7359
7360 /* Enable Refclk */
7361 I915_WRITE(DPLL(pipe),
7362 pipe_config->dpll_hw_state.dpll &
7363 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7364
7365 /* No need to actually set up the DPLL with DSI */
7366 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7367 return;
7368
7369 mutex_lock(&dev_priv->sb_lock);
7370
7371 bestn = pipe_config->dpll.n;
7372 bestm1 = pipe_config->dpll.m1;
7373 bestm2 = pipe_config->dpll.m2;
7374 bestp1 = pipe_config->dpll.p1;
7375 bestp2 = pipe_config->dpll.p2;
7376
7377 /* See eDP HDMI DPIO driver vbios notes doc */
7378
7379 /* PLL B needs special handling */
7380 if (pipe == PIPE_B)
7381 vlv_pllb_recal_opamp(dev_priv, pipe);
7382
7383 /* Set up Tx target for periodic Rcomp update */
7384 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7385
7386 /* Disable target IRef on PLL */
7387 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7388 reg_val &= 0x00ffffff;
7389 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7390
7391 /* Disable fast lock */
7392 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7393
7394 /* Set idtafcrecal before PLL is enabled */
7395 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7396 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7397 mdiv |= ((bestn << DPIO_N_SHIFT));
7398 mdiv |= (1 << DPIO_K_SHIFT);
7399
7400 /*
7401 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7402 * but we don't support that).
7403 * Note: don't use the DAC post divider as it seems unstable.
7404 */
7405 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7406 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7407
7408 mdiv |= DPIO_ENABLE_CALIBRATION;
7409 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7410
7411 /* Set HBR and RBR LPF coefficients */
7412 if (pipe_config->port_clock == 162000 ||
7413 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7414 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7415 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7416 0x009f0003);
7417 else
7418 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7419 0x00d0000f);
7420
7421 if (pipe_config->has_dp_encoder) {
7422 /* Use SSC source */
7423 if (pipe == PIPE_A)
7424 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7425 0x0df40000);
7426 else
7427 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7428 0x0df70000);
7429 } else { /* HDMI or VGA */
7430 /* Use bend source */
7431 if (pipe == PIPE_A)
7432 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7433 0x0df70000);
7434 else
7435 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7436 0x0df40000);
7437 }
7438
7439 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7440 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7441 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7442 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7443 coreclk |= 0x01000000;
7444 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7445
7446 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7447 mutex_unlock(&dev_priv->sb_lock);
7448 }
7449
7450 static void chv_prepare_pll(struct intel_crtc *crtc,
7451 const struct intel_crtc_state *pipe_config)
7452 {
7453 struct drm_device *dev = crtc->base.dev;
7454 struct drm_i915_private *dev_priv = to_i915(dev);
7455 enum pipe pipe = crtc->pipe;
7456 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7457 u32 loopfilter, tribuf_calcntr;
7458 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7459 u32 dpio_val;
7460 int vco;
7461
7462 /* Enable Refclk and SSC */
7463 I915_WRITE(DPLL(pipe),
7464 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7465
7466 /* No need to actually set up the DPLL with DSI */
7467 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7468 return;
7469
7470 bestn = pipe_config->dpll.n;
7471 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7472 bestm1 = pipe_config->dpll.m1;
7473 bestm2 = pipe_config->dpll.m2 >> 22;
7474 bestp1 = pipe_config->dpll.p1;
7475 bestp2 = pipe_config->dpll.p2;
7476 vco = pipe_config->dpll.vco;
7477 dpio_val = 0;
7478 loopfilter = 0;
7479
7480 mutex_lock(&dev_priv->sb_lock);
7481
7482 /* p1 and p2 divider */
7483 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7484 5 << DPIO_CHV_S1_DIV_SHIFT |
7485 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7486 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7487 1 << DPIO_CHV_K_DIV_SHIFT);
7488
7489 /* Feedback post-divider - m2 */
7490 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7491
7492 /* Feedback refclk divider - n and m1 */
7493 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7494 DPIO_CHV_M1_DIV_BY_2 |
7495 1 << DPIO_CHV_N_DIV_SHIFT);
7496
7497 /* M2 fraction division */
7498 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7499
7500 /* M2 fraction division enable */
7501 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7502 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7503 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7504 if (bestm2_frac)
7505 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7506 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7507
7508 /* Program digital lock detect threshold */
7509 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7510 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7511 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7512 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7513 if (!bestm2_frac)
7514 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7515 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7516
7517 /* Loop filter */
7518 if (vco == 5400000) {
7519 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7520 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7521 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7522 tribuf_calcntr = 0x9;
7523 } else if (vco <= 6200000) {
7524 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7525 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7526 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7527 tribuf_calcntr = 0x9;
7528 } else if (vco <= 6480000) {
7529 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7530 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7531 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7532 tribuf_calcntr = 0x8;
7533 } else {
7534 /* Not supported. Apply the same limits as in the max case */
7535 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7536 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7537 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7538 tribuf_calcntr = 0;
7539 }
7540 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7541
7542 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7543 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7544 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7545 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7546
7547 /* AFC Recal */
7548 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7549 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7550 DPIO_AFC_RECAL);
7551
7552 mutex_unlock(&dev_priv->sb_lock);
7553 }
7554
7555 /**
7556 * vlv_force_pll_on - forcibly enable just the PLL
7557 * @dev_priv: i915 private structure
7558 * @pipe: pipe PLL to enable
7559 * @dpll: PLL configuration
7560 *
7561 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7562 * in cases where we need the PLL enabled even when @pipe is not going to
7563 * be enabled.
7564 */
7565 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7566 const struct dpll *dpll)
7567 {
7568 struct intel_crtc *crtc =
7569 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7570 struct intel_crtc_state *pipe_config;
7571
7572 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7573 if (!pipe_config)
7574 return -ENOMEM;
7575
7576 pipe_config->base.crtc = &crtc->base;
7577 pipe_config->pixel_multiplier = 1;
7578 pipe_config->dpll = *dpll;
7579
7580 if (IS_CHERRYVIEW(dev)) {
7581 chv_compute_dpll(crtc, pipe_config);
7582 chv_prepare_pll(crtc, pipe_config);
7583 chv_enable_pll(crtc, pipe_config);
7584 } else {
7585 vlv_compute_dpll(crtc, pipe_config);
7586 vlv_prepare_pll(crtc, pipe_config);
7587 vlv_enable_pll(crtc, pipe_config);
7588 }
7589
7590 kfree(pipe_config);
7591
7592 return 0;
7593 }
7594
7595 /**
7596 * vlv_force_pll_off - forcibly disable just the PLL
7597 * @dev_priv: i915 private structure
7598 * @pipe: pipe PLL to disable
7599 *
7600 * Disable the PLL for @pipe. To be used in cases where we need
7601 * the PLL enabled even when @pipe is not going to be enabled.
7602 */
7603 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7604 {
7605 if (IS_CHERRYVIEW(dev))
7606 chv_disable_pll(to_i915(dev), pipe);
7607 else
7608 vlv_disable_pll(to_i915(dev), pipe);
7609 }
7610
7611 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7612 struct intel_crtc_state *crtc_state,
7613 struct dpll *reduced_clock)
7614 {
7615 struct drm_device *dev = crtc->base.dev;
7616 struct drm_i915_private *dev_priv = to_i915(dev);
7617 u32 dpll;
7618 bool is_sdvo;
7619 struct dpll *clock = &crtc_state->dpll;
7620
7621 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7622
7623 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7624 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7625
7626 dpll = DPLL_VGA_MODE_DIS;
7627
7628 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7629 dpll |= DPLLB_MODE_LVDS;
7630 else
7631 dpll |= DPLLB_MODE_DAC_SERIAL;
7632
7633 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7634 dpll |= (crtc_state->pixel_multiplier - 1)
7635 << SDVO_MULTIPLIER_SHIFT_HIRES;
7636 }
7637
7638 if (is_sdvo)
7639 dpll |= DPLL_SDVO_HIGH_SPEED;
7640
7641 if (crtc_state->has_dp_encoder)
7642 dpll |= DPLL_SDVO_HIGH_SPEED;
7643
7644 /* compute bitmask from p1 value */
7645 if (IS_PINEVIEW(dev))
7646 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7647 else {
7648 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7649 if (IS_G4X(dev) && reduced_clock)
7650 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7651 }
7652 switch (clock->p2) {
7653 case 5:
7654 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7655 break;
7656 case 7:
7657 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7658 break;
7659 case 10:
7660 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7661 break;
7662 case 14:
7663 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7664 break;
7665 }
7666 if (INTEL_INFO(dev)->gen >= 4)
7667 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7668
7669 if (crtc_state->sdvo_tv_clock)
7670 dpll |= PLL_REF_INPUT_TVCLKINBC;
7671 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7672 intel_panel_use_ssc(dev_priv))
7673 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7674 else
7675 dpll |= PLL_REF_INPUT_DREFCLK;
7676
7677 dpll |= DPLL_VCO_ENABLE;
7678 crtc_state->dpll_hw_state.dpll = dpll;
7679
7680 if (INTEL_INFO(dev)->gen >= 4) {
7681 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7682 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7683 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7684 }
7685 }
7686
7687 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7688 struct intel_crtc_state *crtc_state,
7689 struct dpll *reduced_clock)
7690 {
7691 struct drm_device *dev = crtc->base.dev;
7692 struct drm_i915_private *dev_priv = to_i915(dev);
7693 u32 dpll;
7694 struct dpll *clock = &crtc_state->dpll;
7695
7696 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7697
7698 dpll = DPLL_VGA_MODE_DIS;
7699
7700 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7701 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7702 } else {
7703 if (clock->p1 == 2)
7704 dpll |= PLL_P1_DIVIDE_BY_TWO;
7705 else
7706 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7707 if (clock->p2 == 4)
7708 dpll |= PLL_P2_DIVIDE_BY_4;
7709 }
7710
7711 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7712 dpll |= DPLL_DVO_2X_MODE;
7713
7714 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7715 intel_panel_use_ssc(dev_priv))
7716 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7717 else
7718 dpll |= PLL_REF_INPUT_DREFCLK;
7719
7720 dpll |= DPLL_VCO_ENABLE;
7721 crtc_state->dpll_hw_state.dpll = dpll;
7722 }
7723
7724 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7725 {
7726 struct drm_device *dev = intel_crtc->base.dev;
7727 struct drm_i915_private *dev_priv = to_i915(dev);
7728 enum pipe pipe = intel_crtc->pipe;
7729 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7730 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7731 uint32_t crtc_vtotal, crtc_vblank_end;
7732 int vsyncshift = 0;
7733
7734 /* We need to be careful not to changed the adjusted mode, for otherwise
7735 * the hw state checker will get angry at the mismatch. */
7736 crtc_vtotal = adjusted_mode->crtc_vtotal;
7737 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7738
7739 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7740 /* the chip adds 2 halflines automatically */
7741 crtc_vtotal -= 1;
7742 crtc_vblank_end -= 1;
7743
7744 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7745 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7746 else
7747 vsyncshift = adjusted_mode->crtc_hsync_start -
7748 adjusted_mode->crtc_htotal / 2;
7749 if (vsyncshift < 0)
7750 vsyncshift += adjusted_mode->crtc_htotal;
7751 }
7752
7753 if (INTEL_INFO(dev)->gen > 3)
7754 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7755
7756 I915_WRITE(HTOTAL(cpu_transcoder),
7757 (adjusted_mode->crtc_hdisplay - 1) |
7758 ((adjusted_mode->crtc_htotal - 1) << 16));
7759 I915_WRITE(HBLANK(cpu_transcoder),
7760 (adjusted_mode->crtc_hblank_start - 1) |
7761 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7762 I915_WRITE(HSYNC(cpu_transcoder),
7763 (adjusted_mode->crtc_hsync_start - 1) |
7764 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7765
7766 I915_WRITE(VTOTAL(cpu_transcoder),
7767 (adjusted_mode->crtc_vdisplay - 1) |
7768 ((crtc_vtotal - 1) << 16));
7769 I915_WRITE(VBLANK(cpu_transcoder),
7770 (adjusted_mode->crtc_vblank_start - 1) |
7771 ((crtc_vblank_end - 1) << 16));
7772 I915_WRITE(VSYNC(cpu_transcoder),
7773 (adjusted_mode->crtc_vsync_start - 1) |
7774 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7775
7776 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7777 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7778 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7779 * bits. */
7780 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7781 (pipe == PIPE_B || pipe == PIPE_C))
7782 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7783
7784 }
7785
7786 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7787 {
7788 struct drm_device *dev = intel_crtc->base.dev;
7789 struct drm_i915_private *dev_priv = to_i915(dev);
7790 enum pipe pipe = intel_crtc->pipe;
7791
7792 /* pipesrc controls the size that is scaled from, which should
7793 * always be the user's requested size.
7794 */
7795 I915_WRITE(PIPESRC(pipe),
7796 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7797 (intel_crtc->config->pipe_src_h - 1));
7798 }
7799
7800 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7801 struct intel_crtc_state *pipe_config)
7802 {
7803 struct drm_device *dev = crtc->base.dev;
7804 struct drm_i915_private *dev_priv = to_i915(dev);
7805 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7806 uint32_t tmp;
7807
7808 tmp = I915_READ(HTOTAL(cpu_transcoder));
7809 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7810 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7811 tmp = I915_READ(HBLANK(cpu_transcoder));
7812 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7813 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7814 tmp = I915_READ(HSYNC(cpu_transcoder));
7815 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7816 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7817
7818 tmp = I915_READ(VTOTAL(cpu_transcoder));
7819 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7820 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7821 tmp = I915_READ(VBLANK(cpu_transcoder));
7822 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7823 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7824 tmp = I915_READ(VSYNC(cpu_transcoder));
7825 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7826 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7827
7828 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7829 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7830 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7831 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7832 }
7833 }
7834
7835 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7836 struct intel_crtc_state *pipe_config)
7837 {
7838 struct drm_device *dev = crtc->base.dev;
7839 struct drm_i915_private *dev_priv = to_i915(dev);
7840 u32 tmp;
7841
7842 tmp = I915_READ(PIPESRC(crtc->pipe));
7843 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7844 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7845
7846 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7847 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7848 }
7849
7850 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7851 struct intel_crtc_state *pipe_config)
7852 {
7853 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7854 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7855 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7856 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7857
7858 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7859 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7860 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7861 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7862
7863 mode->flags = pipe_config->base.adjusted_mode.flags;
7864 mode->type = DRM_MODE_TYPE_DRIVER;
7865
7866 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7867 mode->flags |= pipe_config->base.adjusted_mode.flags;
7868
7869 mode->hsync = drm_mode_hsync(mode);
7870 mode->vrefresh = drm_mode_vrefresh(mode);
7871 drm_mode_set_name(mode);
7872 }
7873
7874 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7875 {
7876 struct drm_device *dev = intel_crtc->base.dev;
7877 struct drm_i915_private *dev_priv = to_i915(dev);
7878 uint32_t pipeconf;
7879
7880 pipeconf = 0;
7881
7882 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7883 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7884 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7885
7886 if (intel_crtc->config->double_wide)
7887 pipeconf |= PIPECONF_DOUBLE_WIDE;
7888
7889 /* only g4x and later have fancy bpc/dither controls */
7890 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7891 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7892 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7893 pipeconf |= PIPECONF_DITHER_EN |
7894 PIPECONF_DITHER_TYPE_SP;
7895
7896 switch (intel_crtc->config->pipe_bpp) {
7897 case 18:
7898 pipeconf |= PIPECONF_6BPC;
7899 break;
7900 case 24:
7901 pipeconf |= PIPECONF_8BPC;
7902 break;
7903 case 30:
7904 pipeconf |= PIPECONF_10BPC;
7905 break;
7906 default:
7907 /* Case prevented by intel_choose_pipe_bpp_dither. */
7908 BUG();
7909 }
7910 }
7911
7912 if (HAS_PIPE_CXSR(dev)) {
7913 if (intel_crtc->lowfreq_avail) {
7914 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7915 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7916 } else {
7917 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7918 }
7919 }
7920
7921 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7922 if (INTEL_INFO(dev)->gen < 4 ||
7923 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7924 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7925 else
7926 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7927 } else
7928 pipeconf |= PIPECONF_PROGRESSIVE;
7929
7930 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7931 intel_crtc->config->limited_color_range)
7932 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7933
7934 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7935 POSTING_READ(PIPECONF(intel_crtc->pipe));
7936 }
7937
7938 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7939 struct intel_crtc_state *crtc_state)
7940 {
7941 struct drm_device *dev = crtc->base.dev;
7942 struct drm_i915_private *dev_priv = to_i915(dev);
7943 const struct intel_limit *limit;
7944 int refclk = 48000;
7945
7946 memset(&crtc_state->dpll_hw_state, 0,
7947 sizeof(crtc_state->dpll_hw_state));
7948
7949 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7950 if (intel_panel_use_ssc(dev_priv)) {
7951 refclk = dev_priv->vbt.lvds_ssc_freq;
7952 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7953 }
7954
7955 limit = &intel_limits_i8xx_lvds;
7956 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7957 limit = &intel_limits_i8xx_dvo;
7958 } else {
7959 limit = &intel_limits_i8xx_dac;
7960 }
7961
7962 if (!crtc_state->clock_set &&
7963 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7964 refclk, NULL, &crtc_state->dpll)) {
7965 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7966 return -EINVAL;
7967 }
7968
7969 i8xx_compute_dpll(crtc, crtc_state, NULL);
7970
7971 return 0;
7972 }
7973
7974 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7975 struct intel_crtc_state *crtc_state)
7976 {
7977 struct drm_device *dev = crtc->base.dev;
7978 struct drm_i915_private *dev_priv = to_i915(dev);
7979 const struct intel_limit *limit;
7980 int refclk = 96000;
7981
7982 memset(&crtc_state->dpll_hw_state, 0,
7983 sizeof(crtc_state->dpll_hw_state));
7984
7985 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7986 if (intel_panel_use_ssc(dev_priv)) {
7987 refclk = dev_priv->vbt.lvds_ssc_freq;
7988 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7989 }
7990
7991 if (intel_is_dual_link_lvds(dev))
7992 limit = &intel_limits_g4x_dual_channel_lvds;
7993 else
7994 limit = &intel_limits_g4x_single_channel_lvds;
7995 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7996 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7997 limit = &intel_limits_g4x_hdmi;
7998 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7999 limit = &intel_limits_g4x_sdvo;
8000 } else {
8001 /* The option is for other outputs */
8002 limit = &intel_limits_i9xx_sdvo;
8003 }
8004
8005 if (!crtc_state->clock_set &&
8006 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8007 refclk, NULL, &crtc_state->dpll)) {
8008 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8009 return -EINVAL;
8010 }
8011
8012 i9xx_compute_dpll(crtc, crtc_state, NULL);
8013
8014 return 0;
8015 }
8016
8017 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8018 struct intel_crtc_state *crtc_state)
8019 {
8020 struct drm_device *dev = crtc->base.dev;
8021 struct drm_i915_private *dev_priv = to_i915(dev);
8022 const struct intel_limit *limit;
8023 int refclk = 96000;
8024
8025 memset(&crtc_state->dpll_hw_state, 0,
8026 sizeof(crtc_state->dpll_hw_state));
8027
8028 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8029 if (intel_panel_use_ssc(dev_priv)) {
8030 refclk = dev_priv->vbt.lvds_ssc_freq;
8031 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8032 }
8033
8034 limit = &intel_limits_pineview_lvds;
8035 } else {
8036 limit = &intel_limits_pineview_sdvo;
8037 }
8038
8039 if (!crtc_state->clock_set &&
8040 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8041 refclk, NULL, &crtc_state->dpll)) {
8042 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8043 return -EINVAL;
8044 }
8045
8046 i9xx_compute_dpll(crtc, crtc_state, NULL);
8047
8048 return 0;
8049 }
8050
8051 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8052 struct intel_crtc_state *crtc_state)
8053 {
8054 struct drm_device *dev = crtc->base.dev;
8055 struct drm_i915_private *dev_priv = to_i915(dev);
8056 const struct intel_limit *limit;
8057 int refclk = 96000;
8058
8059 memset(&crtc_state->dpll_hw_state, 0,
8060 sizeof(crtc_state->dpll_hw_state));
8061
8062 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8063 if (intel_panel_use_ssc(dev_priv)) {
8064 refclk = dev_priv->vbt.lvds_ssc_freq;
8065 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8066 }
8067
8068 limit = &intel_limits_i9xx_lvds;
8069 } else {
8070 limit = &intel_limits_i9xx_sdvo;
8071 }
8072
8073 if (!crtc_state->clock_set &&
8074 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8075 refclk, NULL, &crtc_state->dpll)) {
8076 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8077 return -EINVAL;
8078 }
8079
8080 i9xx_compute_dpll(crtc, crtc_state, NULL);
8081
8082 return 0;
8083 }
8084
8085 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8086 struct intel_crtc_state *crtc_state)
8087 {
8088 int refclk = 100000;
8089 const struct intel_limit *limit = &intel_limits_chv;
8090
8091 memset(&crtc_state->dpll_hw_state, 0,
8092 sizeof(crtc_state->dpll_hw_state));
8093
8094 if (!crtc_state->clock_set &&
8095 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8096 refclk, NULL, &crtc_state->dpll)) {
8097 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8098 return -EINVAL;
8099 }
8100
8101 chv_compute_dpll(crtc, crtc_state);
8102
8103 return 0;
8104 }
8105
8106 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8107 struct intel_crtc_state *crtc_state)
8108 {
8109 int refclk = 100000;
8110 const struct intel_limit *limit = &intel_limits_vlv;
8111
8112 memset(&crtc_state->dpll_hw_state, 0,
8113 sizeof(crtc_state->dpll_hw_state));
8114
8115 if (!crtc_state->clock_set &&
8116 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8117 refclk, NULL, &crtc_state->dpll)) {
8118 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8119 return -EINVAL;
8120 }
8121
8122 vlv_compute_dpll(crtc, crtc_state);
8123
8124 return 0;
8125 }
8126
8127 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8128 struct intel_crtc_state *pipe_config)
8129 {
8130 struct drm_device *dev = crtc->base.dev;
8131 struct drm_i915_private *dev_priv = to_i915(dev);
8132 uint32_t tmp;
8133
8134 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8135 return;
8136
8137 tmp = I915_READ(PFIT_CONTROL);
8138 if (!(tmp & PFIT_ENABLE))
8139 return;
8140
8141 /* Check whether the pfit is attached to our pipe. */
8142 if (INTEL_INFO(dev)->gen < 4) {
8143 if (crtc->pipe != PIPE_B)
8144 return;
8145 } else {
8146 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8147 return;
8148 }
8149
8150 pipe_config->gmch_pfit.control = tmp;
8151 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8152 }
8153
8154 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8155 struct intel_crtc_state *pipe_config)
8156 {
8157 struct drm_device *dev = crtc->base.dev;
8158 struct drm_i915_private *dev_priv = to_i915(dev);
8159 int pipe = pipe_config->cpu_transcoder;
8160 struct dpll clock;
8161 u32 mdiv;
8162 int refclk = 100000;
8163
8164 /* In case of DSI, DPLL will not be used */
8165 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8166 return;
8167
8168 mutex_lock(&dev_priv->sb_lock);
8169 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8170 mutex_unlock(&dev_priv->sb_lock);
8171
8172 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8173 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8174 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8175 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8176 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8177
8178 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8179 }
8180
8181 static void
8182 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8183 struct intel_initial_plane_config *plane_config)
8184 {
8185 struct drm_device *dev = crtc->base.dev;
8186 struct drm_i915_private *dev_priv = to_i915(dev);
8187 u32 val, base, offset;
8188 int pipe = crtc->pipe, plane = crtc->plane;
8189 int fourcc, pixel_format;
8190 unsigned int aligned_height;
8191 struct drm_framebuffer *fb;
8192 struct intel_framebuffer *intel_fb;
8193
8194 val = I915_READ(DSPCNTR(plane));
8195 if (!(val & DISPLAY_PLANE_ENABLE))
8196 return;
8197
8198 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8199 if (!intel_fb) {
8200 DRM_DEBUG_KMS("failed to alloc fb\n");
8201 return;
8202 }
8203
8204 fb = &intel_fb->base;
8205
8206 if (INTEL_INFO(dev)->gen >= 4) {
8207 if (val & DISPPLANE_TILED) {
8208 plane_config->tiling = I915_TILING_X;
8209 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8210 }
8211 }
8212
8213 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8214 fourcc = i9xx_format_to_fourcc(pixel_format);
8215 fb->pixel_format = fourcc;
8216 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8217
8218 if (INTEL_INFO(dev)->gen >= 4) {
8219 if (plane_config->tiling)
8220 offset = I915_READ(DSPTILEOFF(plane));
8221 else
8222 offset = I915_READ(DSPLINOFF(plane));
8223 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8224 } else {
8225 base = I915_READ(DSPADDR(plane));
8226 }
8227 plane_config->base = base;
8228
8229 val = I915_READ(PIPESRC(pipe));
8230 fb->width = ((val >> 16) & 0xfff) + 1;
8231 fb->height = ((val >> 0) & 0xfff) + 1;
8232
8233 val = I915_READ(DSPSTRIDE(pipe));
8234 fb->pitches[0] = val & 0xffffffc0;
8235
8236 aligned_height = intel_fb_align_height(dev, fb->height,
8237 fb->pixel_format,
8238 fb->modifier[0]);
8239
8240 plane_config->size = fb->pitches[0] * aligned_height;
8241
8242 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8243 pipe_name(pipe), plane, fb->width, fb->height,
8244 fb->bits_per_pixel, base, fb->pitches[0],
8245 plane_config->size);
8246
8247 plane_config->fb = intel_fb;
8248 }
8249
8250 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8251 struct intel_crtc_state *pipe_config)
8252 {
8253 struct drm_device *dev = crtc->base.dev;
8254 struct drm_i915_private *dev_priv = to_i915(dev);
8255 int pipe = pipe_config->cpu_transcoder;
8256 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8257 struct dpll clock;
8258 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8259 int refclk = 100000;
8260
8261 /* In case of DSI, DPLL will not be used */
8262 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8263 return;
8264
8265 mutex_lock(&dev_priv->sb_lock);
8266 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8267 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8268 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8269 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8270 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8271 mutex_unlock(&dev_priv->sb_lock);
8272
8273 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8274 clock.m2 = (pll_dw0 & 0xff) << 22;
8275 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8276 clock.m2 |= pll_dw2 & 0x3fffff;
8277 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8278 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8279 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8280
8281 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8282 }
8283
8284 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8285 struct intel_crtc_state *pipe_config)
8286 {
8287 struct drm_device *dev = crtc->base.dev;
8288 struct drm_i915_private *dev_priv = to_i915(dev);
8289 enum intel_display_power_domain power_domain;
8290 uint32_t tmp;
8291 bool ret;
8292
8293 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8294 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8295 return false;
8296
8297 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8298 pipe_config->shared_dpll = NULL;
8299
8300 ret = false;
8301
8302 tmp = I915_READ(PIPECONF(crtc->pipe));
8303 if (!(tmp & PIPECONF_ENABLE))
8304 goto out;
8305
8306 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8307 switch (tmp & PIPECONF_BPC_MASK) {
8308 case PIPECONF_6BPC:
8309 pipe_config->pipe_bpp = 18;
8310 break;
8311 case PIPECONF_8BPC:
8312 pipe_config->pipe_bpp = 24;
8313 break;
8314 case PIPECONF_10BPC:
8315 pipe_config->pipe_bpp = 30;
8316 break;
8317 default:
8318 break;
8319 }
8320 }
8321
8322 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8323 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8324 pipe_config->limited_color_range = true;
8325
8326 if (INTEL_INFO(dev)->gen < 4)
8327 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8328
8329 intel_get_pipe_timings(crtc, pipe_config);
8330 intel_get_pipe_src_size(crtc, pipe_config);
8331
8332 i9xx_get_pfit_config(crtc, pipe_config);
8333
8334 if (INTEL_INFO(dev)->gen >= 4) {
8335 /* No way to read it out on pipes B and C */
8336 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8337 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8338 else
8339 tmp = I915_READ(DPLL_MD(crtc->pipe));
8340 pipe_config->pixel_multiplier =
8341 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8342 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8343 pipe_config->dpll_hw_state.dpll_md = tmp;
8344 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8345 tmp = I915_READ(DPLL(crtc->pipe));
8346 pipe_config->pixel_multiplier =
8347 ((tmp & SDVO_MULTIPLIER_MASK)
8348 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8349 } else {
8350 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8351 * port and will be fixed up in the encoder->get_config
8352 * function. */
8353 pipe_config->pixel_multiplier = 1;
8354 }
8355 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8356 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8357 /*
8358 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8359 * on 830. Filter it out here so that we don't
8360 * report errors due to that.
8361 */
8362 if (IS_I830(dev))
8363 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8364
8365 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8366 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8367 } else {
8368 /* Mask out read-only status bits. */
8369 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8370 DPLL_PORTC_READY_MASK |
8371 DPLL_PORTB_READY_MASK);
8372 }
8373
8374 if (IS_CHERRYVIEW(dev))
8375 chv_crtc_clock_get(crtc, pipe_config);
8376 else if (IS_VALLEYVIEW(dev))
8377 vlv_crtc_clock_get(crtc, pipe_config);
8378 else
8379 i9xx_crtc_clock_get(crtc, pipe_config);
8380
8381 /*
8382 * Normally the dotclock is filled in by the encoder .get_config()
8383 * but in case the pipe is enabled w/o any ports we need a sane
8384 * default.
8385 */
8386 pipe_config->base.adjusted_mode.crtc_clock =
8387 pipe_config->port_clock / pipe_config->pixel_multiplier;
8388
8389 ret = true;
8390
8391 out:
8392 intel_display_power_put(dev_priv, power_domain);
8393
8394 return ret;
8395 }
8396
8397 static void ironlake_init_pch_refclk(struct drm_device *dev)
8398 {
8399 struct drm_i915_private *dev_priv = to_i915(dev);
8400 struct intel_encoder *encoder;
8401 int i;
8402 u32 val, final;
8403 bool has_lvds = false;
8404 bool has_cpu_edp = false;
8405 bool has_panel = false;
8406 bool has_ck505 = false;
8407 bool can_ssc = false;
8408 bool using_ssc_source = false;
8409
8410 /* We need to take the global config into account */
8411 for_each_intel_encoder(dev, encoder) {
8412 switch (encoder->type) {
8413 case INTEL_OUTPUT_LVDS:
8414 has_panel = true;
8415 has_lvds = true;
8416 break;
8417 case INTEL_OUTPUT_EDP:
8418 has_panel = true;
8419 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8420 has_cpu_edp = true;
8421 break;
8422 default:
8423 break;
8424 }
8425 }
8426
8427 if (HAS_PCH_IBX(dev)) {
8428 has_ck505 = dev_priv->vbt.display_clock_mode;
8429 can_ssc = has_ck505;
8430 } else {
8431 has_ck505 = false;
8432 can_ssc = true;
8433 }
8434
8435 /* Check if any DPLLs are using the SSC source */
8436 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8437 u32 temp = I915_READ(PCH_DPLL(i));
8438
8439 if (!(temp & DPLL_VCO_ENABLE))
8440 continue;
8441
8442 if ((temp & PLL_REF_INPUT_MASK) ==
8443 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8444 using_ssc_source = true;
8445 break;
8446 }
8447 }
8448
8449 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8450 has_panel, has_lvds, has_ck505, using_ssc_source);
8451
8452 /* Ironlake: try to setup display ref clock before DPLL
8453 * enabling. This is only under driver's control after
8454 * PCH B stepping, previous chipset stepping should be
8455 * ignoring this setting.
8456 */
8457 val = I915_READ(PCH_DREF_CONTROL);
8458
8459 /* As we must carefully and slowly disable/enable each source in turn,
8460 * compute the final state we want first and check if we need to
8461 * make any changes at all.
8462 */
8463 final = val;
8464 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8465 if (has_ck505)
8466 final |= DREF_NONSPREAD_CK505_ENABLE;
8467 else
8468 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8469
8470 final &= ~DREF_SSC_SOURCE_MASK;
8471 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8472 final &= ~DREF_SSC1_ENABLE;
8473
8474 if (has_panel) {
8475 final |= DREF_SSC_SOURCE_ENABLE;
8476
8477 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8478 final |= DREF_SSC1_ENABLE;
8479
8480 if (has_cpu_edp) {
8481 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8482 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8483 else
8484 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8485 } else
8486 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8487 } else if (using_ssc_source) {
8488 final |= DREF_SSC_SOURCE_ENABLE;
8489 final |= DREF_SSC1_ENABLE;
8490 }
8491
8492 if (final == val)
8493 return;
8494
8495 /* Always enable nonspread source */
8496 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8497
8498 if (has_ck505)
8499 val |= DREF_NONSPREAD_CK505_ENABLE;
8500 else
8501 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8502
8503 if (has_panel) {
8504 val &= ~DREF_SSC_SOURCE_MASK;
8505 val |= DREF_SSC_SOURCE_ENABLE;
8506
8507 /* SSC must be turned on before enabling the CPU output */
8508 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8509 DRM_DEBUG_KMS("Using SSC on panel\n");
8510 val |= DREF_SSC1_ENABLE;
8511 } else
8512 val &= ~DREF_SSC1_ENABLE;
8513
8514 /* Get SSC going before enabling the outputs */
8515 I915_WRITE(PCH_DREF_CONTROL, val);
8516 POSTING_READ(PCH_DREF_CONTROL);
8517 udelay(200);
8518
8519 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8520
8521 /* Enable CPU source on CPU attached eDP */
8522 if (has_cpu_edp) {
8523 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8524 DRM_DEBUG_KMS("Using SSC on eDP\n");
8525 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8526 } else
8527 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8528 } else
8529 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8530
8531 I915_WRITE(PCH_DREF_CONTROL, val);
8532 POSTING_READ(PCH_DREF_CONTROL);
8533 udelay(200);
8534 } else {
8535 DRM_DEBUG_KMS("Disabling CPU source output\n");
8536
8537 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8538
8539 /* Turn off CPU output */
8540 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8541
8542 I915_WRITE(PCH_DREF_CONTROL, val);
8543 POSTING_READ(PCH_DREF_CONTROL);
8544 udelay(200);
8545
8546 if (!using_ssc_source) {
8547 DRM_DEBUG_KMS("Disabling SSC source\n");
8548
8549 /* Turn off the SSC source */
8550 val &= ~DREF_SSC_SOURCE_MASK;
8551 val |= DREF_SSC_SOURCE_DISABLE;
8552
8553 /* Turn off SSC1 */
8554 val &= ~DREF_SSC1_ENABLE;
8555
8556 I915_WRITE(PCH_DREF_CONTROL, val);
8557 POSTING_READ(PCH_DREF_CONTROL);
8558 udelay(200);
8559 }
8560 }
8561
8562 BUG_ON(val != final);
8563 }
8564
8565 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8566 {
8567 uint32_t tmp;
8568
8569 tmp = I915_READ(SOUTH_CHICKEN2);
8570 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8571 I915_WRITE(SOUTH_CHICKEN2, tmp);
8572
8573 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8574 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8575 DRM_ERROR("FDI mPHY reset assert timeout\n");
8576
8577 tmp = I915_READ(SOUTH_CHICKEN2);
8578 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8579 I915_WRITE(SOUTH_CHICKEN2, tmp);
8580
8581 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8582 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8583 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8584 }
8585
8586 /* WaMPhyProgramming:hsw */
8587 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8588 {
8589 uint32_t tmp;
8590
8591 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8592 tmp &= ~(0xFF << 24);
8593 tmp |= (0x12 << 24);
8594 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8595
8596 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8597 tmp |= (1 << 11);
8598 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8599
8600 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8601 tmp |= (1 << 11);
8602 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8603
8604 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8605 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8606 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8607
8608 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8609 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8610 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8611
8612 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8613 tmp &= ~(7 << 13);
8614 tmp |= (5 << 13);
8615 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8616
8617 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8618 tmp &= ~(7 << 13);
8619 tmp |= (5 << 13);
8620 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8621
8622 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8623 tmp &= ~0xFF;
8624 tmp |= 0x1C;
8625 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8626
8627 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8628 tmp &= ~0xFF;
8629 tmp |= 0x1C;
8630 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8631
8632 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8633 tmp &= ~(0xFF << 16);
8634 tmp |= (0x1C << 16);
8635 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8636
8637 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8638 tmp &= ~(0xFF << 16);
8639 tmp |= (0x1C << 16);
8640 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8641
8642 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8643 tmp |= (1 << 27);
8644 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8645
8646 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8647 tmp |= (1 << 27);
8648 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8649
8650 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8651 tmp &= ~(0xF << 28);
8652 tmp |= (4 << 28);
8653 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8654
8655 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8656 tmp &= ~(0xF << 28);
8657 tmp |= (4 << 28);
8658 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8659 }
8660
8661 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8662 * Programming" based on the parameters passed:
8663 * - Sequence to enable CLKOUT_DP
8664 * - Sequence to enable CLKOUT_DP without spread
8665 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8666 */
8667 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8668 bool with_fdi)
8669 {
8670 struct drm_i915_private *dev_priv = to_i915(dev);
8671 uint32_t reg, tmp;
8672
8673 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8674 with_spread = true;
8675 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8676 with_fdi = false;
8677
8678 mutex_lock(&dev_priv->sb_lock);
8679
8680 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8681 tmp &= ~SBI_SSCCTL_DISABLE;
8682 tmp |= SBI_SSCCTL_PATHALT;
8683 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8684
8685 udelay(24);
8686
8687 if (with_spread) {
8688 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8689 tmp &= ~SBI_SSCCTL_PATHALT;
8690 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8691
8692 if (with_fdi) {
8693 lpt_reset_fdi_mphy(dev_priv);
8694 lpt_program_fdi_mphy(dev_priv);
8695 }
8696 }
8697
8698 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8699 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8700 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8701 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8702
8703 mutex_unlock(&dev_priv->sb_lock);
8704 }
8705
8706 /* Sequence to disable CLKOUT_DP */
8707 static void lpt_disable_clkout_dp(struct drm_device *dev)
8708 {
8709 struct drm_i915_private *dev_priv = to_i915(dev);
8710 uint32_t reg, tmp;
8711
8712 mutex_lock(&dev_priv->sb_lock);
8713
8714 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8715 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8716 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8717 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8718
8719 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8720 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8721 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8722 tmp |= SBI_SSCCTL_PATHALT;
8723 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8724 udelay(32);
8725 }
8726 tmp |= SBI_SSCCTL_DISABLE;
8727 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8728 }
8729
8730 mutex_unlock(&dev_priv->sb_lock);
8731 }
8732
8733 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8734
8735 static const uint16_t sscdivintphase[] = {
8736 [BEND_IDX( 50)] = 0x3B23,
8737 [BEND_IDX( 45)] = 0x3B23,
8738 [BEND_IDX( 40)] = 0x3C23,
8739 [BEND_IDX( 35)] = 0x3C23,
8740 [BEND_IDX( 30)] = 0x3D23,
8741 [BEND_IDX( 25)] = 0x3D23,
8742 [BEND_IDX( 20)] = 0x3E23,
8743 [BEND_IDX( 15)] = 0x3E23,
8744 [BEND_IDX( 10)] = 0x3F23,
8745 [BEND_IDX( 5)] = 0x3F23,
8746 [BEND_IDX( 0)] = 0x0025,
8747 [BEND_IDX( -5)] = 0x0025,
8748 [BEND_IDX(-10)] = 0x0125,
8749 [BEND_IDX(-15)] = 0x0125,
8750 [BEND_IDX(-20)] = 0x0225,
8751 [BEND_IDX(-25)] = 0x0225,
8752 [BEND_IDX(-30)] = 0x0325,
8753 [BEND_IDX(-35)] = 0x0325,
8754 [BEND_IDX(-40)] = 0x0425,
8755 [BEND_IDX(-45)] = 0x0425,
8756 [BEND_IDX(-50)] = 0x0525,
8757 };
8758
8759 /*
8760 * Bend CLKOUT_DP
8761 * steps -50 to 50 inclusive, in steps of 5
8762 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8763 * change in clock period = -(steps / 10) * 5.787 ps
8764 */
8765 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8766 {
8767 uint32_t tmp;
8768 int idx = BEND_IDX(steps);
8769
8770 if (WARN_ON(steps % 5 != 0))
8771 return;
8772
8773 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8774 return;
8775
8776 mutex_lock(&dev_priv->sb_lock);
8777
8778 if (steps % 10 != 0)
8779 tmp = 0xAAAAAAAB;
8780 else
8781 tmp = 0x00000000;
8782 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8783
8784 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8785 tmp &= 0xffff0000;
8786 tmp |= sscdivintphase[idx];
8787 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8788
8789 mutex_unlock(&dev_priv->sb_lock);
8790 }
8791
8792 #undef BEND_IDX
8793
8794 static void lpt_init_pch_refclk(struct drm_device *dev)
8795 {
8796 struct intel_encoder *encoder;
8797 bool has_vga = false;
8798
8799 for_each_intel_encoder(dev, encoder) {
8800 switch (encoder->type) {
8801 case INTEL_OUTPUT_ANALOG:
8802 has_vga = true;
8803 break;
8804 default:
8805 break;
8806 }
8807 }
8808
8809 if (has_vga) {
8810 lpt_bend_clkout_dp(to_i915(dev), 0);
8811 lpt_enable_clkout_dp(dev, true, true);
8812 } else {
8813 lpt_disable_clkout_dp(dev);
8814 }
8815 }
8816
8817 /*
8818 * Initialize reference clocks when the driver loads
8819 */
8820 void intel_init_pch_refclk(struct drm_device *dev)
8821 {
8822 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8823 ironlake_init_pch_refclk(dev);
8824 else if (HAS_PCH_LPT(dev))
8825 lpt_init_pch_refclk(dev);
8826 }
8827
8828 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8829 {
8830 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8832 int pipe = intel_crtc->pipe;
8833 uint32_t val;
8834
8835 val = 0;
8836
8837 switch (intel_crtc->config->pipe_bpp) {
8838 case 18:
8839 val |= PIPECONF_6BPC;
8840 break;
8841 case 24:
8842 val |= PIPECONF_8BPC;
8843 break;
8844 case 30:
8845 val |= PIPECONF_10BPC;
8846 break;
8847 case 36:
8848 val |= PIPECONF_12BPC;
8849 break;
8850 default:
8851 /* Case prevented by intel_choose_pipe_bpp_dither. */
8852 BUG();
8853 }
8854
8855 if (intel_crtc->config->dither)
8856 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8857
8858 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8859 val |= PIPECONF_INTERLACED_ILK;
8860 else
8861 val |= PIPECONF_PROGRESSIVE;
8862
8863 if (intel_crtc->config->limited_color_range)
8864 val |= PIPECONF_COLOR_RANGE_SELECT;
8865
8866 I915_WRITE(PIPECONF(pipe), val);
8867 POSTING_READ(PIPECONF(pipe));
8868 }
8869
8870 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8871 {
8872 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8874 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8875 u32 val = 0;
8876
8877 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8878 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8879
8880 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8881 val |= PIPECONF_INTERLACED_ILK;
8882 else
8883 val |= PIPECONF_PROGRESSIVE;
8884
8885 I915_WRITE(PIPECONF(cpu_transcoder), val);
8886 POSTING_READ(PIPECONF(cpu_transcoder));
8887 }
8888
8889 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8890 {
8891 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8893
8894 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8895 u32 val = 0;
8896
8897 switch (intel_crtc->config->pipe_bpp) {
8898 case 18:
8899 val |= PIPEMISC_DITHER_6_BPC;
8900 break;
8901 case 24:
8902 val |= PIPEMISC_DITHER_8_BPC;
8903 break;
8904 case 30:
8905 val |= PIPEMISC_DITHER_10_BPC;
8906 break;
8907 case 36:
8908 val |= PIPEMISC_DITHER_12_BPC;
8909 break;
8910 default:
8911 /* Case prevented by pipe_config_set_bpp. */
8912 BUG();
8913 }
8914
8915 if (intel_crtc->config->dither)
8916 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8917
8918 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8919 }
8920 }
8921
8922 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8923 {
8924 /*
8925 * Account for spread spectrum to avoid
8926 * oversubscribing the link. Max center spread
8927 * is 2.5%; use 5% for safety's sake.
8928 */
8929 u32 bps = target_clock * bpp * 21 / 20;
8930 return DIV_ROUND_UP(bps, link_bw * 8);
8931 }
8932
8933 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8934 {
8935 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8936 }
8937
8938 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8939 struct intel_crtc_state *crtc_state,
8940 struct dpll *reduced_clock)
8941 {
8942 struct drm_crtc *crtc = &intel_crtc->base;
8943 struct drm_device *dev = crtc->dev;
8944 struct drm_i915_private *dev_priv = to_i915(dev);
8945 struct drm_atomic_state *state = crtc_state->base.state;
8946 struct drm_connector *connector;
8947 struct drm_connector_state *connector_state;
8948 struct intel_encoder *encoder;
8949 u32 dpll, fp, fp2;
8950 int factor, i;
8951 bool is_lvds = false, is_sdvo = false;
8952
8953 for_each_connector_in_state(state, connector, connector_state, i) {
8954 if (connector_state->crtc != crtc_state->base.crtc)
8955 continue;
8956
8957 encoder = to_intel_encoder(connector_state->best_encoder);
8958
8959 switch (encoder->type) {
8960 case INTEL_OUTPUT_LVDS:
8961 is_lvds = true;
8962 break;
8963 case INTEL_OUTPUT_SDVO:
8964 case INTEL_OUTPUT_HDMI:
8965 is_sdvo = true;
8966 break;
8967 default:
8968 break;
8969 }
8970 }
8971
8972 /* Enable autotuning of the PLL clock (if permissible) */
8973 factor = 21;
8974 if (is_lvds) {
8975 if ((intel_panel_use_ssc(dev_priv) &&
8976 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8977 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8978 factor = 25;
8979 } else if (crtc_state->sdvo_tv_clock)
8980 factor = 20;
8981
8982 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8983
8984 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8985 fp |= FP_CB_TUNE;
8986
8987 if (reduced_clock) {
8988 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8989
8990 if (reduced_clock->m < factor * reduced_clock->n)
8991 fp2 |= FP_CB_TUNE;
8992 } else {
8993 fp2 = fp;
8994 }
8995
8996 dpll = 0;
8997
8998 if (is_lvds)
8999 dpll |= DPLLB_MODE_LVDS;
9000 else
9001 dpll |= DPLLB_MODE_DAC_SERIAL;
9002
9003 dpll |= (crtc_state->pixel_multiplier - 1)
9004 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9005
9006 if (is_sdvo)
9007 dpll |= DPLL_SDVO_HIGH_SPEED;
9008 if (crtc_state->has_dp_encoder)
9009 dpll |= DPLL_SDVO_HIGH_SPEED;
9010
9011 /* compute bitmask from p1 value */
9012 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9013 /* also FPA1 */
9014 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9015
9016 switch (crtc_state->dpll.p2) {
9017 case 5:
9018 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9019 break;
9020 case 7:
9021 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9022 break;
9023 case 10:
9024 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9025 break;
9026 case 14:
9027 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9028 break;
9029 }
9030
9031 if (is_lvds && intel_panel_use_ssc(dev_priv))
9032 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9033 else
9034 dpll |= PLL_REF_INPUT_DREFCLK;
9035
9036 dpll |= DPLL_VCO_ENABLE;
9037
9038 crtc_state->dpll_hw_state.dpll = dpll;
9039 crtc_state->dpll_hw_state.fp0 = fp;
9040 crtc_state->dpll_hw_state.fp1 = fp2;
9041 }
9042
9043 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9044 struct intel_crtc_state *crtc_state)
9045 {
9046 struct drm_device *dev = crtc->base.dev;
9047 struct drm_i915_private *dev_priv = to_i915(dev);
9048 struct dpll reduced_clock;
9049 bool has_reduced_clock = false;
9050 struct intel_shared_dpll *pll;
9051 const struct intel_limit *limit;
9052 int refclk = 120000;
9053
9054 memset(&crtc_state->dpll_hw_state, 0,
9055 sizeof(crtc_state->dpll_hw_state));
9056
9057 crtc->lowfreq_avail = false;
9058
9059 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9060 if (!crtc_state->has_pch_encoder)
9061 return 0;
9062
9063 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9064 if (intel_panel_use_ssc(dev_priv)) {
9065 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9066 dev_priv->vbt.lvds_ssc_freq);
9067 refclk = dev_priv->vbt.lvds_ssc_freq;
9068 }
9069
9070 if (intel_is_dual_link_lvds(dev)) {
9071 if (refclk == 100000)
9072 limit = &intel_limits_ironlake_dual_lvds_100m;
9073 else
9074 limit = &intel_limits_ironlake_dual_lvds;
9075 } else {
9076 if (refclk == 100000)
9077 limit = &intel_limits_ironlake_single_lvds_100m;
9078 else
9079 limit = &intel_limits_ironlake_single_lvds;
9080 }
9081 } else {
9082 limit = &intel_limits_ironlake_dac;
9083 }
9084
9085 if (!crtc_state->clock_set &&
9086 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9087 refclk, NULL, &crtc_state->dpll)) {
9088 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9089 return -EINVAL;
9090 }
9091
9092 ironlake_compute_dpll(crtc, crtc_state,
9093 has_reduced_clock ? &reduced_clock : NULL);
9094
9095 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9096 if (pll == NULL) {
9097 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9098 pipe_name(crtc->pipe));
9099 return -EINVAL;
9100 }
9101
9102 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9103 has_reduced_clock)
9104 crtc->lowfreq_avail = true;
9105
9106 return 0;
9107 }
9108
9109 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9110 struct intel_link_m_n *m_n)
9111 {
9112 struct drm_device *dev = crtc->base.dev;
9113 struct drm_i915_private *dev_priv = to_i915(dev);
9114 enum pipe pipe = crtc->pipe;
9115
9116 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9117 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9118 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9119 & ~TU_SIZE_MASK;
9120 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9121 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9122 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9123 }
9124
9125 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9126 enum transcoder transcoder,
9127 struct intel_link_m_n *m_n,
9128 struct intel_link_m_n *m2_n2)
9129 {
9130 struct drm_device *dev = crtc->base.dev;
9131 struct drm_i915_private *dev_priv = to_i915(dev);
9132 enum pipe pipe = crtc->pipe;
9133
9134 if (INTEL_INFO(dev)->gen >= 5) {
9135 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9136 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9137 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9138 & ~TU_SIZE_MASK;
9139 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9140 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9141 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9142 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9143 * gen < 8) and if DRRS is supported (to make sure the
9144 * registers are not unnecessarily read).
9145 */
9146 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9147 crtc->config->has_drrs) {
9148 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9149 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9150 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9151 & ~TU_SIZE_MASK;
9152 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9153 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9154 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9155 }
9156 } else {
9157 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9158 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9159 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9160 & ~TU_SIZE_MASK;
9161 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9162 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9163 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9164 }
9165 }
9166
9167 void intel_dp_get_m_n(struct intel_crtc *crtc,
9168 struct intel_crtc_state *pipe_config)
9169 {
9170 if (pipe_config->has_pch_encoder)
9171 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9172 else
9173 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9174 &pipe_config->dp_m_n,
9175 &pipe_config->dp_m2_n2);
9176 }
9177
9178 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9179 struct intel_crtc_state *pipe_config)
9180 {
9181 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9182 &pipe_config->fdi_m_n, NULL);
9183 }
9184
9185 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9186 struct intel_crtc_state *pipe_config)
9187 {
9188 struct drm_device *dev = crtc->base.dev;
9189 struct drm_i915_private *dev_priv = to_i915(dev);
9190 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9191 uint32_t ps_ctrl = 0;
9192 int id = -1;
9193 int i;
9194
9195 /* find scaler attached to this pipe */
9196 for (i = 0; i < crtc->num_scalers; i++) {
9197 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9198 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9199 id = i;
9200 pipe_config->pch_pfit.enabled = true;
9201 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9202 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9203 break;
9204 }
9205 }
9206
9207 scaler_state->scaler_id = id;
9208 if (id >= 0) {
9209 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9210 } else {
9211 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9212 }
9213 }
9214
9215 static void
9216 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9217 struct intel_initial_plane_config *plane_config)
9218 {
9219 struct drm_device *dev = crtc->base.dev;
9220 struct drm_i915_private *dev_priv = to_i915(dev);
9221 u32 val, base, offset, stride_mult, tiling;
9222 int pipe = crtc->pipe;
9223 int fourcc, pixel_format;
9224 unsigned int aligned_height;
9225 struct drm_framebuffer *fb;
9226 struct intel_framebuffer *intel_fb;
9227
9228 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9229 if (!intel_fb) {
9230 DRM_DEBUG_KMS("failed to alloc fb\n");
9231 return;
9232 }
9233
9234 fb = &intel_fb->base;
9235
9236 val = I915_READ(PLANE_CTL(pipe, 0));
9237 if (!(val & PLANE_CTL_ENABLE))
9238 goto error;
9239
9240 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9241 fourcc = skl_format_to_fourcc(pixel_format,
9242 val & PLANE_CTL_ORDER_RGBX,
9243 val & PLANE_CTL_ALPHA_MASK);
9244 fb->pixel_format = fourcc;
9245 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9246
9247 tiling = val & PLANE_CTL_TILED_MASK;
9248 switch (tiling) {
9249 case PLANE_CTL_TILED_LINEAR:
9250 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9251 break;
9252 case PLANE_CTL_TILED_X:
9253 plane_config->tiling = I915_TILING_X;
9254 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9255 break;
9256 case PLANE_CTL_TILED_Y:
9257 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9258 break;
9259 case PLANE_CTL_TILED_YF:
9260 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9261 break;
9262 default:
9263 MISSING_CASE(tiling);
9264 goto error;
9265 }
9266
9267 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9268 plane_config->base = base;
9269
9270 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9271
9272 val = I915_READ(PLANE_SIZE(pipe, 0));
9273 fb->height = ((val >> 16) & 0xfff) + 1;
9274 fb->width = ((val >> 0) & 0x1fff) + 1;
9275
9276 val = I915_READ(PLANE_STRIDE(pipe, 0));
9277 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9278 fb->pixel_format);
9279 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9280
9281 aligned_height = intel_fb_align_height(dev, fb->height,
9282 fb->pixel_format,
9283 fb->modifier[0]);
9284
9285 plane_config->size = fb->pitches[0] * aligned_height;
9286
9287 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9288 pipe_name(pipe), fb->width, fb->height,
9289 fb->bits_per_pixel, base, fb->pitches[0],
9290 plane_config->size);
9291
9292 plane_config->fb = intel_fb;
9293 return;
9294
9295 error:
9296 kfree(fb);
9297 }
9298
9299 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9300 struct intel_crtc_state *pipe_config)
9301 {
9302 struct drm_device *dev = crtc->base.dev;
9303 struct drm_i915_private *dev_priv = to_i915(dev);
9304 uint32_t tmp;
9305
9306 tmp = I915_READ(PF_CTL(crtc->pipe));
9307
9308 if (tmp & PF_ENABLE) {
9309 pipe_config->pch_pfit.enabled = true;
9310 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9311 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9312
9313 /* We currently do not free assignements of panel fitters on
9314 * ivb/hsw (since we don't use the higher upscaling modes which
9315 * differentiates them) so just WARN about this case for now. */
9316 if (IS_GEN7(dev)) {
9317 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9318 PF_PIPE_SEL_IVB(crtc->pipe));
9319 }
9320 }
9321 }
9322
9323 static void
9324 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9325 struct intel_initial_plane_config *plane_config)
9326 {
9327 struct drm_device *dev = crtc->base.dev;
9328 struct drm_i915_private *dev_priv = to_i915(dev);
9329 u32 val, base, offset;
9330 int pipe = crtc->pipe;
9331 int fourcc, pixel_format;
9332 unsigned int aligned_height;
9333 struct drm_framebuffer *fb;
9334 struct intel_framebuffer *intel_fb;
9335
9336 val = I915_READ(DSPCNTR(pipe));
9337 if (!(val & DISPLAY_PLANE_ENABLE))
9338 return;
9339
9340 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9341 if (!intel_fb) {
9342 DRM_DEBUG_KMS("failed to alloc fb\n");
9343 return;
9344 }
9345
9346 fb = &intel_fb->base;
9347
9348 if (INTEL_INFO(dev)->gen >= 4) {
9349 if (val & DISPPLANE_TILED) {
9350 plane_config->tiling = I915_TILING_X;
9351 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9352 }
9353 }
9354
9355 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9356 fourcc = i9xx_format_to_fourcc(pixel_format);
9357 fb->pixel_format = fourcc;
9358 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9359
9360 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9361 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9362 offset = I915_READ(DSPOFFSET(pipe));
9363 } else {
9364 if (plane_config->tiling)
9365 offset = I915_READ(DSPTILEOFF(pipe));
9366 else
9367 offset = I915_READ(DSPLINOFF(pipe));
9368 }
9369 plane_config->base = base;
9370
9371 val = I915_READ(PIPESRC(pipe));
9372 fb->width = ((val >> 16) & 0xfff) + 1;
9373 fb->height = ((val >> 0) & 0xfff) + 1;
9374
9375 val = I915_READ(DSPSTRIDE(pipe));
9376 fb->pitches[0] = val & 0xffffffc0;
9377
9378 aligned_height = intel_fb_align_height(dev, fb->height,
9379 fb->pixel_format,
9380 fb->modifier[0]);
9381
9382 plane_config->size = fb->pitches[0] * aligned_height;
9383
9384 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9385 pipe_name(pipe), fb->width, fb->height,
9386 fb->bits_per_pixel, base, fb->pitches[0],
9387 plane_config->size);
9388
9389 plane_config->fb = intel_fb;
9390 }
9391
9392 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9393 struct intel_crtc_state *pipe_config)
9394 {
9395 struct drm_device *dev = crtc->base.dev;
9396 struct drm_i915_private *dev_priv = to_i915(dev);
9397 enum intel_display_power_domain power_domain;
9398 uint32_t tmp;
9399 bool ret;
9400
9401 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9402 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9403 return false;
9404
9405 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9406 pipe_config->shared_dpll = NULL;
9407
9408 ret = false;
9409 tmp = I915_READ(PIPECONF(crtc->pipe));
9410 if (!(tmp & PIPECONF_ENABLE))
9411 goto out;
9412
9413 switch (tmp & PIPECONF_BPC_MASK) {
9414 case PIPECONF_6BPC:
9415 pipe_config->pipe_bpp = 18;
9416 break;
9417 case PIPECONF_8BPC:
9418 pipe_config->pipe_bpp = 24;
9419 break;
9420 case PIPECONF_10BPC:
9421 pipe_config->pipe_bpp = 30;
9422 break;
9423 case PIPECONF_12BPC:
9424 pipe_config->pipe_bpp = 36;
9425 break;
9426 default:
9427 break;
9428 }
9429
9430 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9431 pipe_config->limited_color_range = true;
9432
9433 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9434 struct intel_shared_dpll *pll;
9435 enum intel_dpll_id pll_id;
9436
9437 pipe_config->has_pch_encoder = true;
9438
9439 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9440 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9441 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9442
9443 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9444
9445 if (HAS_PCH_IBX(dev_priv)) {
9446 /*
9447 * The pipe->pch transcoder and pch transcoder->pll
9448 * mapping is fixed.
9449 */
9450 pll_id = (enum intel_dpll_id) crtc->pipe;
9451 } else {
9452 tmp = I915_READ(PCH_DPLL_SEL);
9453 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9454 pll_id = DPLL_ID_PCH_PLL_B;
9455 else
9456 pll_id= DPLL_ID_PCH_PLL_A;
9457 }
9458
9459 pipe_config->shared_dpll =
9460 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9461 pll = pipe_config->shared_dpll;
9462
9463 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9464 &pipe_config->dpll_hw_state));
9465
9466 tmp = pipe_config->dpll_hw_state.dpll;
9467 pipe_config->pixel_multiplier =
9468 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9469 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9470
9471 ironlake_pch_clock_get(crtc, pipe_config);
9472 } else {
9473 pipe_config->pixel_multiplier = 1;
9474 }
9475
9476 intel_get_pipe_timings(crtc, pipe_config);
9477 intel_get_pipe_src_size(crtc, pipe_config);
9478
9479 ironlake_get_pfit_config(crtc, pipe_config);
9480
9481 ret = true;
9482
9483 out:
9484 intel_display_power_put(dev_priv, power_domain);
9485
9486 return ret;
9487 }
9488
9489 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9490 {
9491 struct drm_device *dev = dev_priv->dev;
9492 struct intel_crtc *crtc;
9493
9494 for_each_intel_crtc(dev, crtc)
9495 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9496 pipe_name(crtc->pipe));
9497
9498 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9499 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9500 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9501 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9502 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9503 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9504 "CPU PWM1 enabled\n");
9505 if (IS_HASWELL(dev))
9506 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9507 "CPU PWM2 enabled\n");
9508 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9509 "PCH PWM1 enabled\n");
9510 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9511 "Utility pin enabled\n");
9512 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9513
9514 /*
9515 * In theory we can still leave IRQs enabled, as long as only the HPD
9516 * interrupts remain enabled. We used to check for that, but since it's
9517 * gen-specific and since we only disable LCPLL after we fully disable
9518 * the interrupts, the check below should be enough.
9519 */
9520 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9521 }
9522
9523 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9524 {
9525 struct drm_device *dev = dev_priv->dev;
9526
9527 if (IS_HASWELL(dev))
9528 return I915_READ(D_COMP_HSW);
9529 else
9530 return I915_READ(D_COMP_BDW);
9531 }
9532
9533 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9534 {
9535 struct drm_device *dev = dev_priv->dev;
9536
9537 if (IS_HASWELL(dev)) {
9538 mutex_lock(&dev_priv->rps.hw_lock);
9539 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9540 val))
9541 DRM_ERROR("Failed to write to D_COMP\n");
9542 mutex_unlock(&dev_priv->rps.hw_lock);
9543 } else {
9544 I915_WRITE(D_COMP_BDW, val);
9545 POSTING_READ(D_COMP_BDW);
9546 }
9547 }
9548
9549 /*
9550 * This function implements pieces of two sequences from BSpec:
9551 * - Sequence for display software to disable LCPLL
9552 * - Sequence for display software to allow package C8+
9553 * The steps implemented here are just the steps that actually touch the LCPLL
9554 * register. Callers should take care of disabling all the display engine
9555 * functions, doing the mode unset, fixing interrupts, etc.
9556 */
9557 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9558 bool switch_to_fclk, bool allow_power_down)
9559 {
9560 uint32_t val;
9561
9562 assert_can_disable_lcpll(dev_priv);
9563
9564 val = I915_READ(LCPLL_CTL);
9565
9566 if (switch_to_fclk) {
9567 val |= LCPLL_CD_SOURCE_FCLK;
9568 I915_WRITE(LCPLL_CTL, val);
9569
9570 if (wait_for_us(I915_READ(LCPLL_CTL) &
9571 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9572 DRM_ERROR("Switching to FCLK failed\n");
9573
9574 val = I915_READ(LCPLL_CTL);
9575 }
9576
9577 val |= LCPLL_PLL_DISABLE;
9578 I915_WRITE(LCPLL_CTL, val);
9579 POSTING_READ(LCPLL_CTL);
9580
9581 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9582 DRM_ERROR("LCPLL still locked\n");
9583
9584 val = hsw_read_dcomp(dev_priv);
9585 val |= D_COMP_COMP_DISABLE;
9586 hsw_write_dcomp(dev_priv, val);
9587 ndelay(100);
9588
9589 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9590 1))
9591 DRM_ERROR("D_COMP RCOMP still in progress\n");
9592
9593 if (allow_power_down) {
9594 val = I915_READ(LCPLL_CTL);
9595 val |= LCPLL_POWER_DOWN_ALLOW;
9596 I915_WRITE(LCPLL_CTL, val);
9597 POSTING_READ(LCPLL_CTL);
9598 }
9599 }
9600
9601 /*
9602 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9603 * source.
9604 */
9605 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9606 {
9607 uint32_t val;
9608
9609 val = I915_READ(LCPLL_CTL);
9610
9611 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9612 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9613 return;
9614
9615 /*
9616 * Make sure we're not on PC8 state before disabling PC8, otherwise
9617 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9618 */
9619 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9620
9621 if (val & LCPLL_POWER_DOWN_ALLOW) {
9622 val &= ~LCPLL_POWER_DOWN_ALLOW;
9623 I915_WRITE(LCPLL_CTL, val);
9624 POSTING_READ(LCPLL_CTL);
9625 }
9626
9627 val = hsw_read_dcomp(dev_priv);
9628 val |= D_COMP_COMP_FORCE;
9629 val &= ~D_COMP_COMP_DISABLE;
9630 hsw_write_dcomp(dev_priv, val);
9631
9632 val = I915_READ(LCPLL_CTL);
9633 val &= ~LCPLL_PLL_DISABLE;
9634 I915_WRITE(LCPLL_CTL, val);
9635
9636 if (intel_wait_for_register(dev_priv,
9637 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9638 5))
9639 DRM_ERROR("LCPLL not locked yet\n");
9640
9641 if (val & LCPLL_CD_SOURCE_FCLK) {
9642 val = I915_READ(LCPLL_CTL);
9643 val &= ~LCPLL_CD_SOURCE_FCLK;
9644 I915_WRITE(LCPLL_CTL, val);
9645
9646 if (wait_for_us((I915_READ(LCPLL_CTL) &
9647 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9648 DRM_ERROR("Switching back to LCPLL failed\n");
9649 }
9650
9651 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9652 intel_update_cdclk(dev_priv->dev);
9653 }
9654
9655 /*
9656 * Package states C8 and deeper are really deep PC states that can only be
9657 * reached when all the devices on the system allow it, so even if the graphics
9658 * device allows PC8+, it doesn't mean the system will actually get to these
9659 * states. Our driver only allows PC8+ when going into runtime PM.
9660 *
9661 * The requirements for PC8+ are that all the outputs are disabled, the power
9662 * well is disabled and most interrupts are disabled, and these are also
9663 * requirements for runtime PM. When these conditions are met, we manually do
9664 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9665 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9666 * hang the machine.
9667 *
9668 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9669 * the state of some registers, so when we come back from PC8+ we need to
9670 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9671 * need to take care of the registers kept by RC6. Notice that this happens even
9672 * if we don't put the device in PCI D3 state (which is what currently happens
9673 * because of the runtime PM support).
9674 *
9675 * For more, read "Display Sequences for Package C8" on the hardware
9676 * documentation.
9677 */
9678 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9679 {
9680 struct drm_device *dev = dev_priv->dev;
9681 uint32_t val;
9682
9683 DRM_DEBUG_KMS("Enabling package C8+\n");
9684
9685 if (HAS_PCH_LPT_LP(dev)) {
9686 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9687 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9688 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9689 }
9690
9691 lpt_disable_clkout_dp(dev);
9692 hsw_disable_lcpll(dev_priv, true, true);
9693 }
9694
9695 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9696 {
9697 struct drm_device *dev = dev_priv->dev;
9698 uint32_t val;
9699
9700 DRM_DEBUG_KMS("Disabling package C8+\n");
9701
9702 hsw_restore_lcpll(dev_priv);
9703 lpt_init_pch_refclk(dev);
9704
9705 if (HAS_PCH_LPT_LP(dev)) {
9706 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9707 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9708 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9709 }
9710 }
9711
9712 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9713 {
9714 struct drm_device *dev = old_state->dev;
9715 struct intel_atomic_state *old_intel_state =
9716 to_intel_atomic_state(old_state);
9717 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9718
9719 bxt_set_cdclk(to_i915(dev), req_cdclk);
9720 }
9721
9722 /* compute the max rate for new configuration */
9723 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9724 {
9725 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9726 struct drm_i915_private *dev_priv = to_i915(state->dev);
9727 struct drm_crtc *crtc;
9728 struct drm_crtc_state *cstate;
9729 struct intel_crtc_state *crtc_state;
9730 unsigned max_pixel_rate = 0, i;
9731 enum pipe pipe;
9732
9733 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9734 sizeof(intel_state->min_pixclk));
9735
9736 for_each_crtc_in_state(state, crtc, cstate, i) {
9737 int pixel_rate;
9738
9739 crtc_state = to_intel_crtc_state(cstate);
9740 if (!crtc_state->base.enable) {
9741 intel_state->min_pixclk[i] = 0;
9742 continue;
9743 }
9744
9745 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9746
9747 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9748 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9749 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9750
9751 intel_state->min_pixclk[i] = pixel_rate;
9752 }
9753
9754 for_each_pipe(dev_priv, pipe)
9755 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9756
9757 return max_pixel_rate;
9758 }
9759
9760 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9761 {
9762 struct drm_i915_private *dev_priv = to_i915(dev);
9763 uint32_t val, data;
9764 int ret;
9765
9766 if (WARN((I915_READ(LCPLL_CTL) &
9767 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9768 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9769 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9770 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9771 "trying to change cdclk frequency with cdclk not enabled\n"))
9772 return;
9773
9774 mutex_lock(&dev_priv->rps.hw_lock);
9775 ret = sandybridge_pcode_write(dev_priv,
9776 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9777 mutex_unlock(&dev_priv->rps.hw_lock);
9778 if (ret) {
9779 DRM_ERROR("failed to inform pcode about cdclk change\n");
9780 return;
9781 }
9782
9783 val = I915_READ(LCPLL_CTL);
9784 val |= LCPLL_CD_SOURCE_FCLK;
9785 I915_WRITE(LCPLL_CTL, val);
9786
9787 if (wait_for_us(I915_READ(LCPLL_CTL) &
9788 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9789 DRM_ERROR("Switching to FCLK failed\n");
9790
9791 val = I915_READ(LCPLL_CTL);
9792 val &= ~LCPLL_CLK_FREQ_MASK;
9793
9794 switch (cdclk) {
9795 case 450000:
9796 val |= LCPLL_CLK_FREQ_450;
9797 data = 0;
9798 break;
9799 case 540000:
9800 val |= LCPLL_CLK_FREQ_54O_BDW;
9801 data = 1;
9802 break;
9803 case 337500:
9804 val |= LCPLL_CLK_FREQ_337_5_BDW;
9805 data = 2;
9806 break;
9807 case 675000:
9808 val |= LCPLL_CLK_FREQ_675_BDW;
9809 data = 3;
9810 break;
9811 default:
9812 WARN(1, "invalid cdclk frequency\n");
9813 return;
9814 }
9815
9816 I915_WRITE(LCPLL_CTL, val);
9817
9818 val = I915_READ(LCPLL_CTL);
9819 val &= ~LCPLL_CD_SOURCE_FCLK;
9820 I915_WRITE(LCPLL_CTL, val);
9821
9822 if (wait_for_us((I915_READ(LCPLL_CTL) &
9823 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9824 DRM_ERROR("Switching back to LCPLL failed\n");
9825
9826 mutex_lock(&dev_priv->rps.hw_lock);
9827 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9828 mutex_unlock(&dev_priv->rps.hw_lock);
9829
9830 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9831
9832 intel_update_cdclk(dev);
9833
9834 WARN(cdclk != dev_priv->cdclk_freq,
9835 "cdclk requested %d kHz but got %d kHz\n",
9836 cdclk, dev_priv->cdclk_freq);
9837 }
9838
9839 static int broadwell_calc_cdclk(int max_pixclk)
9840 {
9841 if (max_pixclk > 540000)
9842 return 675000;
9843 else if (max_pixclk > 450000)
9844 return 540000;
9845 else if (max_pixclk > 337500)
9846 return 450000;
9847 else
9848 return 337500;
9849 }
9850
9851 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9852 {
9853 struct drm_i915_private *dev_priv = to_i915(state->dev);
9854 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9855 int max_pixclk = ilk_max_pixel_rate(state);
9856 int cdclk;
9857
9858 /*
9859 * FIXME should also account for plane ratio
9860 * once 64bpp pixel formats are supported.
9861 */
9862 cdclk = broadwell_calc_cdclk(max_pixclk);
9863
9864 if (cdclk > dev_priv->max_cdclk_freq) {
9865 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9866 cdclk, dev_priv->max_cdclk_freq);
9867 return -EINVAL;
9868 }
9869
9870 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9871 if (!intel_state->active_crtcs)
9872 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9873
9874 return 0;
9875 }
9876
9877 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9878 {
9879 struct drm_device *dev = old_state->dev;
9880 struct intel_atomic_state *old_intel_state =
9881 to_intel_atomic_state(old_state);
9882 unsigned req_cdclk = old_intel_state->dev_cdclk;
9883
9884 broadwell_set_cdclk(dev, req_cdclk);
9885 }
9886
9887 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9888 {
9889 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9890 struct drm_i915_private *dev_priv = to_i915(state->dev);
9891 const int max_pixclk = ilk_max_pixel_rate(state);
9892 int vco = intel_state->cdclk_pll_vco;
9893 int cdclk;
9894
9895 /*
9896 * FIXME should also account for plane ratio
9897 * once 64bpp pixel formats are supported.
9898 */
9899 cdclk = skl_calc_cdclk(max_pixclk, vco);
9900
9901 /*
9902 * FIXME move the cdclk caclulation to
9903 * compute_config() so we can fail gracegully.
9904 */
9905 if (cdclk > dev_priv->max_cdclk_freq) {
9906 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9907 cdclk, dev_priv->max_cdclk_freq);
9908 cdclk = dev_priv->max_cdclk_freq;
9909 }
9910
9911 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9912 if (!intel_state->active_crtcs)
9913 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
9914
9915 return 0;
9916 }
9917
9918 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9919 {
9920 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9921 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9922 unsigned int req_cdclk = intel_state->dev_cdclk;
9923 unsigned int req_vco = intel_state->cdclk_pll_vco;
9924
9925 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
9926 }
9927
9928 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9929 struct intel_crtc_state *crtc_state)
9930 {
9931 struct intel_encoder *intel_encoder =
9932 intel_ddi_get_crtc_new_encoder(crtc_state);
9933
9934 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9935 if (!intel_ddi_pll_select(crtc, crtc_state))
9936 return -EINVAL;
9937 }
9938
9939 crtc->lowfreq_avail = false;
9940
9941 return 0;
9942 }
9943
9944 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9945 enum port port,
9946 struct intel_crtc_state *pipe_config)
9947 {
9948 enum intel_dpll_id id;
9949
9950 switch (port) {
9951 case PORT_A:
9952 pipe_config->ddi_pll_sel = SKL_DPLL0;
9953 id = DPLL_ID_SKL_DPLL0;
9954 break;
9955 case PORT_B:
9956 pipe_config->ddi_pll_sel = SKL_DPLL1;
9957 id = DPLL_ID_SKL_DPLL1;
9958 break;
9959 case PORT_C:
9960 pipe_config->ddi_pll_sel = SKL_DPLL2;
9961 id = DPLL_ID_SKL_DPLL2;
9962 break;
9963 default:
9964 DRM_ERROR("Incorrect port type\n");
9965 return;
9966 }
9967
9968 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9969 }
9970
9971 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9972 enum port port,
9973 struct intel_crtc_state *pipe_config)
9974 {
9975 enum intel_dpll_id id;
9976 u32 temp;
9977
9978 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9979 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9980
9981 switch (pipe_config->ddi_pll_sel) {
9982 case SKL_DPLL0:
9983 id = DPLL_ID_SKL_DPLL0;
9984 break;
9985 case SKL_DPLL1:
9986 id = DPLL_ID_SKL_DPLL1;
9987 break;
9988 case SKL_DPLL2:
9989 id = DPLL_ID_SKL_DPLL2;
9990 break;
9991 case SKL_DPLL3:
9992 id = DPLL_ID_SKL_DPLL3;
9993 break;
9994 default:
9995 MISSING_CASE(pipe_config->ddi_pll_sel);
9996 return;
9997 }
9998
9999 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10000 }
10001
10002 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10003 enum port port,
10004 struct intel_crtc_state *pipe_config)
10005 {
10006 enum intel_dpll_id id;
10007
10008 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10009
10010 switch (pipe_config->ddi_pll_sel) {
10011 case PORT_CLK_SEL_WRPLL1:
10012 id = DPLL_ID_WRPLL1;
10013 break;
10014 case PORT_CLK_SEL_WRPLL2:
10015 id = DPLL_ID_WRPLL2;
10016 break;
10017 case PORT_CLK_SEL_SPLL:
10018 id = DPLL_ID_SPLL;
10019 break;
10020 case PORT_CLK_SEL_LCPLL_810:
10021 id = DPLL_ID_LCPLL_810;
10022 break;
10023 case PORT_CLK_SEL_LCPLL_1350:
10024 id = DPLL_ID_LCPLL_1350;
10025 break;
10026 case PORT_CLK_SEL_LCPLL_2700:
10027 id = DPLL_ID_LCPLL_2700;
10028 break;
10029 default:
10030 MISSING_CASE(pipe_config->ddi_pll_sel);
10031 /* fall through */
10032 case PORT_CLK_SEL_NONE:
10033 return;
10034 }
10035
10036 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10037 }
10038
10039 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10040 struct intel_crtc_state *pipe_config,
10041 unsigned long *power_domain_mask)
10042 {
10043 struct drm_device *dev = crtc->base.dev;
10044 struct drm_i915_private *dev_priv = to_i915(dev);
10045 enum intel_display_power_domain power_domain;
10046 u32 tmp;
10047
10048 /*
10049 * The pipe->transcoder mapping is fixed with the exception of the eDP
10050 * transcoder handled below.
10051 */
10052 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10053
10054 /*
10055 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10056 * consistency and less surprising code; it's in always on power).
10057 */
10058 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10059 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10060 enum pipe trans_edp_pipe;
10061 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10062 default:
10063 WARN(1, "unknown pipe linked to edp transcoder\n");
10064 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10065 case TRANS_DDI_EDP_INPUT_A_ON:
10066 trans_edp_pipe = PIPE_A;
10067 break;
10068 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10069 trans_edp_pipe = PIPE_B;
10070 break;
10071 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10072 trans_edp_pipe = PIPE_C;
10073 break;
10074 }
10075
10076 if (trans_edp_pipe == crtc->pipe)
10077 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10078 }
10079
10080 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10081 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10082 return false;
10083 *power_domain_mask |= BIT(power_domain);
10084
10085 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10086
10087 return tmp & PIPECONF_ENABLE;
10088 }
10089
10090 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10091 struct intel_crtc_state *pipe_config,
10092 unsigned long *power_domain_mask)
10093 {
10094 struct drm_device *dev = crtc->base.dev;
10095 struct drm_i915_private *dev_priv = to_i915(dev);
10096 enum intel_display_power_domain power_domain;
10097 enum port port;
10098 enum transcoder cpu_transcoder;
10099 u32 tmp;
10100
10101 pipe_config->has_dsi_encoder = false;
10102
10103 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10104 if (port == PORT_A)
10105 cpu_transcoder = TRANSCODER_DSI_A;
10106 else
10107 cpu_transcoder = TRANSCODER_DSI_C;
10108
10109 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10110 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10111 continue;
10112 *power_domain_mask |= BIT(power_domain);
10113
10114 /*
10115 * The PLL needs to be enabled with a valid divider
10116 * configuration, otherwise accessing DSI registers will hang
10117 * the machine. See BSpec North Display Engine
10118 * registers/MIPI[BXT]. We can break out here early, since we
10119 * need the same DSI PLL to be enabled for both DSI ports.
10120 */
10121 if (!intel_dsi_pll_is_enabled(dev_priv))
10122 break;
10123
10124 /* XXX: this works for video mode only */
10125 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10126 if (!(tmp & DPI_ENABLE))
10127 continue;
10128
10129 tmp = I915_READ(MIPI_CTRL(port));
10130 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10131 continue;
10132
10133 pipe_config->cpu_transcoder = cpu_transcoder;
10134 pipe_config->has_dsi_encoder = true;
10135 break;
10136 }
10137
10138 return pipe_config->has_dsi_encoder;
10139 }
10140
10141 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10142 struct intel_crtc_state *pipe_config)
10143 {
10144 struct drm_device *dev = crtc->base.dev;
10145 struct drm_i915_private *dev_priv = to_i915(dev);
10146 struct intel_shared_dpll *pll;
10147 enum port port;
10148 uint32_t tmp;
10149
10150 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10151
10152 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10153
10154 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10155 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10156 else if (IS_BROXTON(dev))
10157 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10158 else
10159 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10160
10161 pll = pipe_config->shared_dpll;
10162 if (pll) {
10163 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10164 &pipe_config->dpll_hw_state));
10165 }
10166
10167 /*
10168 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10169 * DDI E. So just check whether this pipe is wired to DDI E and whether
10170 * the PCH transcoder is on.
10171 */
10172 if (INTEL_INFO(dev)->gen < 9 &&
10173 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10174 pipe_config->has_pch_encoder = true;
10175
10176 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10177 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10178 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10179
10180 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10181 }
10182 }
10183
10184 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10185 struct intel_crtc_state *pipe_config)
10186 {
10187 struct drm_device *dev = crtc->base.dev;
10188 struct drm_i915_private *dev_priv = to_i915(dev);
10189 enum intel_display_power_domain power_domain;
10190 unsigned long power_domain_mask;
10191 bool active;
10192
10193 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10194 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10195 return false;
10196 power_domain_mask = BIT(power_domain);
10197
10198 pipe_config->shared_dpll = NULL;
10199
10200 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10201
10202 if (IS_BROXTON(dev_priv)) {
10203 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10204 &power_domain_mask);
10205 WARN_ON(active && pipe_config->has_dsi_encoder);
10206 if (pipe_config->has_dsi_encoder)
10207 active = true;
10208 }
10209
10210 if (!active)
10211 goto out;
10212
10213 if (!pipe_config->has_dsi_encoder) {
10214 haswell_get_ddi_port_state(crtc, pipe_config);
10215 intel_get_pipe_timings(crtc, pipe_config);
10216 }
10217
10218 intel_get_pipe_src_size(crtc, pipe_config);
10219
10220 pipe_config->gamma_mode =
10221 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10222
10223 if (INTEL_INFO(dev)->gen >= 9) {
10224 skl_init_scalers(dev, crtc, pipe_config);
10225 }
10226
10227 if (INTEL_INFO(dev)->gen >= 9) {
10228 pipe_config->scaler_state.scaler_id = -1;
10229 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10230 }
10231
10232 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10233 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10234 power_domain_mask |= BIT(power_domain);
10235 if (INTEL_INFO(dev)->gen >= 9)
10236 skylake_get_pfit_config(crtc, pipe_config);
10237 else
10238 ironlake_get_pfit_config(crtc, pipe_config);
10239 }
10240
10241 if (IS_HASWELL(dev))
10242 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10243 (I915_READ(IPS_CTL) & IPS_ENABLE);
10244
10245 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10246 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10247 pipe_config->pixel_multiplier =
10248 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10249 } else {
10250 pipe_config->pixel_multiplier = 1;
10251 }
10252
10253 out:
10254 for_each_power_domain(power_domain, power_domain_mask)
10255 intel_display_power_put(dev_priv, power_domain);
10256
10257 return active;
10258 }
10259
10260 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10261 const struct intel_plane_state *plane_state)
10262 {
10263 struct drm_device *dev = crtc->dev;
10264 struct drm_i915_private *dev_priv = to_i915(dev);
10265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10266 uint32_t cntl = 0, size = 0;
10267
10268 if (plane_state && plane_state->visible) {
10269 unsigned int width = plane_state->base.crtc_w;
10270 unsigned int height = plane_state->base.crtc_h;
10271 unsigned int stride = roundup_pow_of_two(width) * 4;
10272
10273 switch (stride) {
10274 default:
10275 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10276 width, stride);
10277 stride = 256;
10278 /* fallthrough */
10279 case 256:
10280 case 512:
10281 case 1024:
10282 case 2048:
10283 break;
10284 }
10285
10286 cntl |= CURSOR_ENABLE |
10287 CURSOR_GAMMA_ENABLE |
10288 CURSOR_FORMAT_ARGB |
10289 CURSOR_STRIDE(stride);
10290
10291 size = (height << 12) | width;
10292 }
10293
10294 if (intel_crtc->cursor_cntl != 0 &&
10295 (intel_crtc->cursor_base != base ||
10296 intel_crtc->cursor_size != size ||
10297 intel_crtc->cursor_cntl != cntl)) {
10298 /* On these chipsets we can only modify the base/size/stride
10299 * whilst the cursor is disabled.
10300 */
10301 I915_WRITE(CURCNTR(PIPE_A), 0);
10302 POSTING_READ(CURCNTR(PIPE_A));
10303 intel_crtc->cursor_cntl = 0;
10304 }
10305
10306 if (intel_crtc->cursor_base != base) {
10307 I915_WRITE(CURBASE(PIPE_A), base);
10308 intel_crtc->cursor_base = base;
10309 }
10310
10311 if (intel_crtc->cursor_size != size) {
10312 I915_WRITE(CURSIZE, size);
10313 intel_crtc->cursor_size = size;
10314 }
10315
10316 if (intel_crtc->cursor_cntl != cntl) {
10317 I915_WRITE(CURCNTR(PIPE_A), cntl);
10318 POSTING_READ(CURCNTR(PIPE_A));
10319 intel_crtc->cursor_cntl = cntl;
10320 }
10321 }
10322
10323 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10324 const struct intel_plane_state *plane_state)
10325 {
10326 struct drm_device *dev = crtc->dev;
10327 struct drm_i915_private *dev_priv = to_i915(dev);
10328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10329 int pipe = intel_crtc->pipe;
10330 uint32_t cntl = 0;
10331
10332 if (plane_state && plane_state->visible) {
10333 cntl = MCURSOR_GAMMA_ENABLE;
10334 switch (plane_state->base.crtc_w) {
10335 case 64:
10336 cntl |= CURSOR_MODE_64_ARGB_AX;
10337 break;
10338 case 128:
10339 cntl |= CURSOR_MODE_128_ARGB_AX;
10340 break;
10341 case 256:
10342 cntl |= CURSOR_MODE_256_ARGB_AX;
10343 break;
10344 default:
10345 MISSING_CASE(plane_state->base.crtc_w);
10346 return;
10347 }
10348 cntl |= pipe << 28; /* Connect to correct pipe */
10349
10350 if (HAS_DDI(dev))
10351 cntl |= CURSOR_PIPE_CSC_ENABLE;
10352
10353 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10354 cntl |= CURSOR_ROTATE_180;
10355 }
10356
10357 if (intel_crtc->cursor_cntl != cntl) {
10358 I915_WRITE(CURCNTR(pipe), cntl);
10359 POSTING_READ(CURCNTR(pipe));
10360 intel_crtc->cursor_cntl = cntl;
10361 }
10362
10363 /* and commit changes on next vblank */
10364 I915_WRITE(CURBASE(pipe), base);
10365 POSTING_READ(CURBASE(pipe));
10366
10367 intel_crtc->cursor_base = base;
10368 }
10369
10370 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10371 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10372 const struct intel_plane_state *plane_state)
10373 {
10374 struct drm_device *dev = crtc->dev;
10375 struct drm_i915_private *dev_priv = to_i915(dev);
10376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10377 int pipe = intel_crtc->pipe;
10378 u32 base = intel_crtc->cursor_addr;
10379 u32 pos = 0;
10380
10381 if (plane_state) {
10382 int x = plane_state->base.crtc_x;
10383 int y = plane_state->base.crtc_y;
10384
10385 if (x < 0) {
10386 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10387 x = -x;
10388 }
10389 pos |= x << CURSOR_X_SHIFT;
10390
10391 if (y < 0) {
10392 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10393 y = -y;
10394 }
10395 pos |= y << CURSOR_Y_SHIFT;
10396
10397 /* ILK+ do this automagically */
10398 if (HAS_GMCH_DISPLAY(dev) &&
10399 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10400 base += (plane_state->base.crtc_h *
10401 plane_state->base.crtc_w - 1) * 4;
10402 }
10403 }
10404
10405 I915_WRITE(CURPOS(pipe), pos);
10406
10407 if (IS_845G(dev) || IS_I865G(dev))
10408 i845_update_cursor(crtc, base, plane_state);
10409 else
10410 i9xx_update_cursor(crtc, base, plane_state);
10411 }
10412
10413 static bool cursor_size_ok(struct drm_device *dev,
10414 uint32_t width, uint32_t height)
10415 {
10416 if (width == 0 || height == 0)
10417 return false;
10418
10419 /*
10420 * 845g/865g are special in that they are only limited by
10421 * the width of their cursors, the height is arbitrary up to
10422 * the precision of the register. Everything else requires
10423 * square cursors, limited to a few power-of-two sizes.
10424 */
10425 if (IS_845G(dev) || IS_I865G(dev)) {
10426 if ((width & 63) != 0)
10427 return false;
10428
10429 if (width > (IS_845G(dev) ? 64 : 512))
10430 return false;
10431
10432 if (height > 1023)
10433 return false;
10434 } else {
10435 switch (width | height) {
10436 case 256:
10437 case 128:
10438 if (IS_GEN2(dev))
10439 return false;
10440 case 64:
10441 break;
10442 default:
10443 return false;
10444 }
10445 }
10446
10447 return true;
10448 }
10449
10450 /* VESA 640x480x72Hz mode to set on the pipe */
10451 static struct drm_display_mode load_detect_mode = {
10452 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10453 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10454 };
10455
10456 struct drm_framebuffer *
10457 __intel_framebuffer_create(struct drm_device *dev,
10458 struct drm_mode_fb_cmd2 *mode_cmd,
10459 struct drm_i915_gem_object *obj)
10460 {
10461 struct intel_framebuffer *intel_fb;
10462 int ret;
10463
10464 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10465 if (!intel_fb)
10466 return ERR_PTR(-ENOMEM);
10467
10468 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10469 if (ret)
10470 goto err;
10471
10472 return &intel_fb->base;
10473
10474 err:
10475 kfree(intel_fb);
10476 return ERR_PTR(ret);
10477 }
10478
10479 static struct drm_framebuffer *
10480 intel_framebuffer_create(struct drm_device *dev,
10481 struct drm_mode_fb_cmd2 *mode_cmd,
10482 struct drm_i915_gem_object *obj)
10483 {
10484 struct drm_framebuffer *fb;
10485 int ret;
10486
10487 ret = i915_mutex_lock_interruptible(dev);
10488 if (ret)
10489 return ERR_PTR(ret);
10490 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10491 mutex_unlock(&dev->struct_mutex);
10492
10493 return fb;
10494 }
10495
10496 static u32
10497 intel_framebuffer_pitch_for_width(int width, int bpp)
10498 {
10499 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10500 return ALIGN(pitch, 64);
10501 }
10502
10503 static u32
10504 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10505 {
10506 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10507 return PAGE_ALIGN(pitch * mode->vdisplay);
10508 }
10509
10510 static struct drm_framebuffer *
10511 intel_framebuffer_create_for_mode(struct drm_device *dev,
10512 struct drm_display_mode *mode,
10513 int depth, int bpp)
10514 {
10515 struct drm_framebuffer *fb;
10516 struct drm_i915_gem_object *obj;
10517 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10518
10519 obj = i915_gem_object_create(dev,
10520 intel_framebuffer_size_for_mode(mode, bpp));
10521 if (IS_ERR(obj))
10522 return ERR_CAST(obj);
10523
10524 mode_cmd.width = mode->hdisplay;
10525 mode_cmd.height = mode->vdisplay;
10526 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10527 bpp);
10528 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10529
10530 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10531 if (IS_ERR(fb))
10532 drm_gem_object_unreference_unlocked(&obj->base);
10533
10534 return fb;
10535 }
10536
10537 static struct drm_framebuffer *
10538 mode_fits_in_fbdev(struct drm_device *dev,
10539 struct drm_display_mode *mode)
10540 {
10541 #ifdef CONFIG_DRM_FBDEV_EMULATION
10542 struct drm_i915_private *dev_priv = to_i915(dev);
10543 struct drm_i915_gem_object *obj;
10544 struct drm_framebuffer *fb;
10545
10546 if (!dev_priv->fbdev)
10547 return NULL;
10548
10549 if (!dev_priv->fbdev->fb)
10550 return NULL;
10551
10552 obj = dev_priv->fbdev->fb->obj;
10553 BUG_ON(!obj);
10554
10555 fb = &dev_priv->fbdev->fb->base;
10556 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10557 fb->bits_per_pixel))
10558 return NULL;
10559
10560 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10561 return NULL;
10562
10563 drm_framebuffer_reference(fb);
10564 return fb;
10565 #else
10566 return NULL;
10567 #endif
10568 }
10569
10570 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10571 struct drm_crtc *crtc,
10572 struct drm_display_mode *mode,
10573 struct drm_framebuffer *fb,
10574 int x, int y)
10575 {
10576 struct drm_plane_state *plane_state;
10577 int hdisplay, vdisplay;
10578 int ret;
10579
10580 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10581 if (IS_ERR(plane_state))
10582 return PTR_ERR(plane_state);
10583
10584 if (mode)
10585 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10586 else
10587 hdisplay = vdisplay = 0;
10588
10589 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10590 if (ret)
10591 return ret;
10592 drm_atomic_set_fb_for_plane(plane_state, fb);
10593 plane_state->crtc_x = 0;
10594 plane_state->crtc_y = 0;
10595 plane_state->crtc_w = hdisplay;
10596 plane_state->crtc_h = vdisplay;
10597 plane_state->src_x = x << 16;
10598 plane_state->src_y = y << 16;
10599 plane_state->src_w = hdisplay << 16;
10600 plane_state->src_h = vdisplay << 16;
10601
10602 return 0;
10603 }
10604
10605 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10606 struct drm_display_mode *mode,
10607 struct intel_load_detect_pipe *old,
10608 struct drm_modeset_acquire_ctx *ctx)
10609 {
10610 struct intel_crtc *intel_crtc;
10611 struct intel_encoder *intel_encoder =
10612 intel_attached_encoder(connector);
10613 struct drm_crtc *possible_crtc;
10614 struct drm_encoder *encoder = &intel_encoder->base;
10615 struct drm_crtc *crtc = NULL;
10616 struct drm_device *dev = encoder->dev;
10617 struct drm_framebuffer *fb;
10618 struct drm_mode_config *config = &dev->mode_config;
10619 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10620 struct drm_connector_state *connector_state;
10621 struct intel_crtc_state *crtc_state;
10622 int ret, i = -1;
10623
10624 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10625 connector->base.id, connector->name,
10626 encoder->base.id, encoder->name);
10627
10628 old->restore_state = NULL;
10629
10630 retry:
10631 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10632 if (ret)
10633 goto fail;
10634
10635 /*
10636 * Algorithm gets a little messy:
10637 *
10638 * - if the connector already has an assigned crtc, use it (but make
10639 * sure it's on first)
10640 *
10641 * - try to find the first unused crtc that can drive this connector,
10642 * and use that if we find one
10643 */
10644
10645 /* See if we already have a CRTC for this connector */
10646 if (connector->state->crtc) {
10647 crtc = connector->state->crtc;
10648
10649 ret = drm_modeset_lock(&crtc->mutex, ctx);
10650 if (ret)
10651 goto fail;
10652
10653 /* Make sure the crtc and connector are running */
10654 goto found;
10655 }
10656
10657 /* Find an unused one (if possible) */
10658 for_each_crtc(dev, possible_crtc) {
10659 i++;
10660 if (!(encoder->possible_crtcs & (1 << i)))
10661 continue;
10662
10663 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10664 if (ret)
10665 goto fail;
10666
10667 if (possible_crtc->state->enable) {
10668 drm_modeset_unlock(&possible_crtc->mutex);
10669 continue;
10670 }
10671
10672 crtc = possible_crtc;
10673 break;
10674 }
10675
10676 /*
10677 * If we didn't find an unused CRTC, don't use any.
10678 */
10679 if (!crtc) {
10680 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10681 goto fail;
10682 }
10683
10684 found:
10685 intel_crtc = to_intel_crtc(crtc);
10686
10687 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10688 if (ret)
10689 goto fail;
10690
10691 state = drm_atomic_state_alloc(dev);
10692 restore_state = drm_atomic_state_alloc(dev);
10693 if (!state || !restore_state) {
10694 ret = -ENOMEM;
10695 goto fail;
10696 }
10697
10698 state->acquire_ctx = ctx;
10699 restore_state->acquire_ctx = ctx;
10700
10701 connector_state = drm_atomic_get_connector_state(state, connector);
10702 if (IS_ERR(connector_state)) {
10703 ret = PTR_ERR(connector_state);
10704 goto fail;
10705 }
10706
10707 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10708 if (ret)
10709 goto fail;
10710
10711 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10712 if (IS_ERR(crtc_state)) {
10713 ret = PTR_ERR(crtc_state);
10714 goto fail;
10715 }
10716
10717 crtc_state->base.active = crtc_state->base.enable = true;
10718
10719 if (!mode)
10720 mode = &load_detect_mode;
10721
10722 /* We need a framebuffer large enough to accommodate all accesses
10723 * that the plane may generate whilst we perform load detection.
10724 * We can not rely on the fbcon either being present (we get called
10725 * during its initialisation to detect all boot displays, or it may
10726 * not even exist) or that it is large enough to satisfy the
10727 * requested mode.
10728 */
10729 fb = mode_fits_in_fbdev(dev, mode);
10730 if (fb == NULL) {
10731 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10732 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10733 } else
10734 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10735 if (IS_ERR(fb)) {
10736 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10737 goto fail;
10738 }
10739
10740 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10741 if (ret)
10742 goto fail;
10743
10744 drm_framebuffer_unreference(fb);
10745
10746 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10747 if (ret)
10748 goto fail;
10749
10750 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10751 if (!ret)
10752 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10753 if (!ret)
10754 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10755 if (ret) {
10756 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10757 goto fail;
10758 }
10759
10760 ret = drm_atomic_commit(state);
10761 if (ret) {
10762 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10763 goto fail;
10764 }
10765
10766 old->restore_state = restore_state;
10767
10768 /* let the connector get through one full cycle before testing */
10769 intel_wait_for_vblank(dev, intel_crtc->pipe);
10770 return true;
10771
10772 fail:
10773 drm_atomic_state_free(state);
10774 drm_atomic_state_free(restore_state);
10775 restore_state = state = NULL;
10776
10777 if (ret == -EDEADLK) {
10778 drm_modeset_backoff(ctx);
10779 goto retry;
10780 }
10781
10782 return false;
10783 }
10784
10785 void intel_release_load_detect_pipe(struct drm_connector *connector,
10786 struct intel_load_detect_pipe *old,
10787 struct drm_modeset_acquire_ctx *ctx)
10788 {
10789 struct intel_encoder *intel_encoder =
10790 intel_attached_encoder(connector);
10791 struct drm_encoder *encoder = &intel_encoder->base;
10792 struct drm_atomic_state *state = old->restore_state;
10793 int ret;
10794
10795 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10796 connector->base.id, connector->name,
10797 encoder->base.id, encoder->name);
10798
10799 if (!state)
10800 return;
10801
10802 ret = drm_atomic_commit(state);
10803 if (ret) {
10804 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10805 drm_atomic_state_free(state);
10806 }
10807 }
10808
10809 static int i9xx_pll_refclk(struct drm_device *dev,
10810 const struct intel_crtc_state *pipe_config)
10811 {
10812 struct drm_i915_private *dev_priv = to_i915(dev);
10813 u32 dpll = pipe_config->dpll_hw_state.dpll;
10814
10815 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10816 return dev_priv->vbt.lvds_ssc_freq;
10817 else if (HAS_PCH_SPLIT(dev))
10818 return 120000;
10819 else if (!IS_GEN2(dev))
10820 return 96000;
10821 else
10822 return 48000;
10823 }
10824
10825 /* Returns the clock of the currently programmed mode of the given pipe. */
10826 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10827 struct intel_crtc_state *pipe_config)
10828 {
10829 struct drm_device *dev = crtc->base.dev;
10830 struct drm_i915_private *dev_priv = to_i915(dev);
10831 int pipe = pipe_config->cpu_transcoder;
10832 u32 dpll = pipe_config->dpll_hw_state.dpll;
10833 u32 fp;
10834 struct dpll clock;
10835 int port_clock;
10836 int refclk = i9xx_pll_refclk(dev, pipe_config);
10837
10838 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10839 fp = pipe_config->dpll_hw_state.fp0;
10840 else
10841 fp = pipe_config->dpll_hw_state.fp1;
10842
10843 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10844 if (IS_PINEVIEW(dev)) {
10845 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10846 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10847 } else {
10848 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10849 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10850 }
10851
10852 if (!IS_GEN2(dev)) {
10853 if (IS_PINEVIEW(dev))
10854 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10855 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10856 else
10857 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10858 DPLL_FPA01_P1_POST_DIV_SHIFT);
10859
10860 switch (dpll & DPLL_MODE_MASK) {
10861 case DPLLB_MODE_DAC_SERIAL:
10862 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10863 5 : 10;
10864 break;
10865 case DPLLB_MODE_LVDS:
10866 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10867 7 : 14;
10868 break;
10869 default:
10870 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10871 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10872 return;
10873 }
10874
10875 if (IS_PINEVIEW(dev))
10876 port_clock = pnv_calc_dpll_params(refclk, &clock);
10877 else
10878 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10879 } else {
10880 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10881 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10882
10883 if (is_lvds) {
10884 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10885 DPLL_FPA01_P1_POST_DIV_SHIFT);
10886
10887 if (lvds & LVDS_CLKB_POWER_UP)
10888 clock.p2 = 7;
10889 else
10890 clock.p2 = 14;
10891 } else {
10892 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10893 clock.p1 = 2;
10894 else {
10895 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10896 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10897 }
10898 if (dpll & PLL_P2_DIVIDE_BY_4)
10899 clock.p2 = 4;
10900 else
10901 clock.p2 = 2;
10902 }
10903
10904 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10905 }
10906
10907 /*
10908 * This value includes pixel_multiplier. We will use
10909 * port_clock to compute adjusted_mode.crtc_clock in the
10910 * encoder's get_config() function.
10911 */
10912 pipe_config->port_clock = port_clock;
10913 }
10914
10915 int intel_dotclock_calculate(int link_freq,
10916 const struct intel_link_m_n *m_n)
10917 {
10918 /*
10919 * The calculation for the data clock is:
10920 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10921 * But we want to avoid losing precison if possible, so:
10922 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10923 *
10924 * and the link clock is simpler:
10925 * link_clock = (m * link_clock) / n
10926 */
10927
10928 if (!m_n->link_n)
10929 return 0;
10930
10931 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10932 }
10933
10934 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10935 struct intel_crtc_state *pipe_config)
10936 {
10937 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10938
10939 /* read out port_clock from the DPLL */
10940 i9xx_crtc_clock_get(crtc, pipe_config);
10941
10942 /*
10943 * In case there is an active pipe without active ports,
10944 * we may need some idea for the dotclock anyway.
10945 * Calculate one based on the FDI configuration.
10946 */
10947 pipe_config->base.adjusted_mode.crtc_clock =
10948 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10949 &pipe_config->fdi_m_n);
10950 }
10951
10952 /** Returns the currently programmed mode of the given pipe. */
10953 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10954 struct drm_crtc *crtc)
10955 {
10956 struct drm_i915_private *dev_priv = to_i915(dev);
10957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10958 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10959 struct drm_display_mode *mode;
10960 struct intel_crtc_state *pipe_config;
10961 int htot = I915_READ(HTOTAL(cpu_transcoder));
10962 int hsync = I915_READ(HSYNC(cpu_transcoder));
10963 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10964 int vsync = I915_READ(VSYNC(cpu_transcoder));
10965 enum pipe pipe = intel_crtc->pipe;
10966
10967 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10968 if (!mode)
10969 return NULL;
10970
10971 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10972 if (!pipe_config) {
10973 kfree(mode);
10974 return NULL;
10975 }
10976
10977 /*
10978 * Construct a pipe_config sufficient for getting the clock info
10979 * back out of crtc_clock_get.
10980 *
10981 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10982 * to use a real value here instead.
10983 */
10984 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10985 pipe_config->pixel_multiplier = 1;
10986 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10987 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10988 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10989 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10990
10991 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10992 mode->hdisplay = (htot & 0xffff) + 1;
10993 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10994 mode->hsync_start = (hsync & 0xffff) + 1;
10995 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10996 mode->vdisplay = (vtot & 0xffff) + 1;
10997 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10998 mode->vsync_start = (vsync & 0xffff) + 1;
10999 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11000
11001 drm_mode_set_name(mode);
11002
11003 kfree(pipe_config);
11004
11005 return mode;
11006 }
11007
11008 static void intel_crtc_destroy(struct drm_crtc *crtc)
11009 {
11010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11011 struct drm_device *dev = crtc->dev;
11012 struct intel_flip_work *work;
11013
11014 spin_lock_irq(&dev->event_lock);
11015 work = intel_crtc->flip_work;
11016 intel_crtc->flip_work = NULL;
11017 spin_unlock_irq(&dev->event_lock);
11018
11019 if (work) {
11020 cancel_work_sync(&work->mmio_work);
11021 cancel_work_sync(&work->unpin_work);
11022 kfree(work);
11023 }
11024
11025 drm_crtc_cleanup(crtc);
11026
11027 kfree(intel_crtc);
11028 }
11029
11030 static void intel_unpin_work_fn(struct work_struct *__work)
11031 {
11032 struct intel_flip_work *work =
11033 container_of(__work, struct intel_flip_work, unpin_work);
11034 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11035 struct drm_device *dev = crtc->base.dev;
11036 struct drm_plane *primary = crtc->base.primary;
11037
11038 if (is_mmio_work(work))
11039 flush_work(&work->mmio_work);
11040
11041 mutex_lock(&dev->struct_mutex);
11042 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11043 drm_gem_object_unreference(&work->pending_flip_obj->base);
11044
11045 if (work->flip_queued_req)
11046 i915_gem_request_assign(&work->flip_queued_req, NULL);
11047 mutex_unlock(&dev->struct_mutex);
11048
11049 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
11050 intel_fbc_post_update(crtc);
11051 drm_framebuffer_unreference(work->old_fb);
11052
11053 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11054 atomic_dec(&crtc->unpin_work_count);
11055
11056 kfree(work);
11057 }
11058
11059 /* Is 'a' after or equal to 'b'? */
11060 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11061 {
11062 return !((a - b) & 0x80000000);
11063 }
11064
11065 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11066 struct intel_flip_work *work)
11067 {
11068 struct drm_device *dev = crtc->base.dev;
11069 struct drm_i915_private *dev_priv = to_i915(dev);
11070 unsigned reset_counter;
11071
11072 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11073 if (crtc->reset_counter != reset_counter)
11074 return true;
11075
11076 /*
11077 * The relevant registers doen't exist on pre-ctg.
11078 * As the flip done interrupt doesn't trigger for mmio
11079 * flips on gmch platforms, a flip count check isn't
11080 * really needed there. But since ctg has the registers,
11081 * include it in the check anyway.
11082 */
11083 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11084 return true;
11085
11086 /*
11087 * BDW signals flip done immediately if the plane
11088 * is disabled, even if the plane enable is already
11089 * armed to occur at the next vblank :(
11090 */
11091
11092 /*
11093 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11094 * used the same base address. In that case the mmio flip might
11095 * have completed, but the CS hasn't even executed the flip yet.
11096 *
11097 * A flip count check isn't enough as the CS might have updated
11098 * the base address just after start of vblank, but before we
11099 * managed to process the interrupt. This means we'd complete the
11100 * CS flip too soon.
11101 *
11102 * Combining both checks should get us a good enough result. It may
11103 * still happen that the CS flip has been executed, but has not
11104 * yet actually completed. But in case the base address is the same
11105 * anyway, we don't really care.
11106 */
11107 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11108 crtc->flip_work->gtt_offset &&
11109 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11110 crtc->flip_work->flip_count);
11111 }
11112
11113 static bool
11114 __pageflip_finished_mmio(struct intel_crtc *crtc,
11115 struct intel_flip_work *work)
11116 {
11117 /*
11118 * MMIO work completes when vblank is different from
11119 * flip_queued_vblank.
11120 *
11121 * Reset counter value doesn't matter, this is handled by
11122 * i915_wait_request finishing early, so no need to handle
11123 * reset here.
11124 */
11125 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11126 }
11127
11128
11129 static bool pageflip_finished(struct intel_crtc *crtc,
11130 struct intel_flip_work *work)
11131 {
11132 if (!atomic_read(&work->pending))
11133 return false;
11134
11135 smp_rmb();
11136
11137 if (is_mmio_work(work))
11138 return __pageflip_finished_mmio(crtc, work);
11139 else
11140 return __pageflip_finished_cs(crtc, work);
11141 }
11142
11143 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11144 {
11145 struct drm_device *dev = dev_priv->dev;
11146 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11148 struct intel_flip_work *work;
11149 unsigned long flags;
11150
11151 /* Ignore early vblank irqs */
11152 if (!crtc)
11153 return;
11154
11155 /*
11156 * This is called both by irq handlers and the reset code (to complete
11157 * lost pageflips) so needs the full irqsave spinlocks.
11158 */
11159 spin_lock_irqsave(&dev->event_lock, flags);
11160 work = intel_crtc->flip_work;
11161
11162 if (work != NULL &&
11163 !is_mmio_work(work) &&
11164 pageflip_finished(intel_crtc, work))
11165 page_flip_completed(intel_crtc);
11166
11167 spin_unlock_irqrestore(&dev->event_lock, flags);
11168 }
11169
11170 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11171 {
11172 struct drm_device *dev = dev_priv->dev;
11173 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11175 struct intel_flip_work *work;
11176 unsigned long flags;
11177
11178 /* Ignore early vblank irqs */
11179 if (!crtc)
11180 return;
11181
11182 /*
11183 * This is called both by irq handlers and the reset code (to complete
11184 * lost pageflips) so needs the full irqsave spinlocks.
11185 */
11186 spin_lock_irqsave(&dev->event_lock, flags);
11187 work = intel_crtc->flip_work;
11188
11189 if (work != NULL &&
11190 is_mmio_work(work) &&
11191 pageflip_finished(intel_crtc, work))
11192 page_flip_completed(intel_crtc);
11193
11194 spin_unlock_irqrestore(&dev->event_lock, flags);
11195 }
11196
11197 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11198 struct intel_flip_work *work)
11199 {
11200 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11201
11202 /* Ensure that the work item is consistent when activating it ... */
11203 smp_mb__before_atomic();
11204 atomic_set(&work->pending, 1);
11205 }
11206
11207 static int intel_gen2_queue_flip(struct drm_device *dev,
11208 struct drm_crtc *crtc,
11209 struct drm_framebuffer *fb,
11210 struct drm_i915_gem_object *obj,
11211 struct drm_i915_gem_request *req,
11212 uint32_t flags)
11213 {
11214 struct intel_engine_cs *engine = req->engine;
11215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11216 u32 flip_mask;
11217 int ret;
11218
11219 ret = intel_ring_begin(req, 6);
11220 if (ret)
11221 return ret;
11222
11223 /* Can't queue multiple flips, so wait for the previous
11224 * one to finish before executing the next.
11225 */
11226 if (intel_crtc->plane)
11227 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11228 else
11229 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11230 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11231 intel_ring_emit(engine, MI_NOOP);
11232 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11233 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11234 intel_ring_emit(engine, fb->pitches[0]);
11235 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11236 intel_ring_emit(engine, 0); /* aux display base address, unused */
11237
11238 return 0;
11239 }
11240
11241 static int intel_gen3_queue_flip(struct drm_device *dev,
11242 struct drm_crtc *crtc,
11243 struct drm_framebuffer *fb,
11244 struct drm_i915_gem_object *obj,
11245 struct drm_i915_gem_request *req,
11246 uint32_t flags)
11247 {
11248 struct intel_engine_cs *engine = req->engine;
11249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11250 u32 flip_mask;
11251 int ret;
11252
11253 ret = intel_ring_begin(req, 6);
11254 if (ret)
11255 return ret;
11256
11257 if (intel_crtc->plane)
11258 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11259 else
11260 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11261 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11262 intel_ring_emit(engine, MI_NOOP);
11263 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11264 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11265 intel_ring_emit(engine, fb->pitches[0]);
11266 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11267 intel_ring_emit(engine, MI_NOOP);
11268
11269 return 0;
11270 }
11271
11272 static int intel_gen4_queue_flip(struct drm_device *dev,
11273 struct drm_crtc *crtc,
11274 struct drm_framebuffer *fb,
11275 struct drm_i915_gem_object *obj,
11276 struct drm_i915_gem_request *req,
11277 uint32_t flags)
11278 {
11279 struct intel_engine_cs *engine = req->engine;
11280 struct drm_i915_private *dev_priv = to_i915(dev);
11281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11282 uint32_t pf, pipesrc;
11283 int ret;
11284
11285 ret = intel_ring_begin(req, 4);
11286 if (ret)
11287 return ret;
11288
11289 /* i965+ uses the linear or tiled offsets from the
11290 * Display Registers (which do not change across a page-flip)
11291 * so we need only reprogram the base address.
11292 */
11293 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11294 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11295 intel_ring_emit(engine, fb->pitches[0]);
11296 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset |
11297 obj->tiling_mode);
11298
11299 /* XXX Enabling the panel-fitter across page-flip is so far
11300 * untested on non-native modes, so ignore it for now.
11301 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11302 */
11303 pf = 0;
11304 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11305 intel_ring_emit(engine, pf | pipesrc);
11306
11307 return 0;
11308 }
11309
11310 static int intel_gen6_queue_flip(struct drm_device *dev,
11311 struct drm_crtc *crtc,
11312 struct drm_framebuffer *fb,
11313 struct drm_i915_gem_object *obj,
11314 struct drm_i915_gem_request *req,
11315 uint32_t flags)
11316 {
11317 struct intel_engine_cs *engine = req->engine;
11318 struct drm_i915_private *dev_priv = to_i915(dev);
11319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11320 uint32_t pf, pipesrc;
11321 int ret;
11322
11323 ret = intel_ring_begin(req, 4);
11324 if (ret)
11325 return ret;
11326
11327 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11328 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11329 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11330 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11331
11332 /* Contrary to the suggestions in the documentation,
11333 * "Enable Panel Fitter" does not seem to be required when page
11334 * flipping with a non-native mode, and worse causes a normal
11335 * modeset to fail.
11336 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11337 */
11338 pf = 0;
11339 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11340 intel_ring_emit(engine, pf | pipesrc);
11341
11342 return 0;
11343 }
11344
11345 static int intel_gen7_queue_flip(struct drm_device *dev,
11346 struct drm_crtc *crtc,
11347 struct drm_framebuffer *fb,
11348 struct drm_i915_gem_object *obj,
11349 struct drm_i915_gem_request *req,
11350 uint32_t flags)
11351 {
11352 struct intel_engine_cs *engine = req->engine;
11353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11354 uint32_t plane_bit = 0;
11355 int len, ret;
11356
11357 switch (intel_crtc->plane) {
11358 case PLANE_A:
11359 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11360 break;
11361 case PLANE_B:
11362 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11363 break;
11364 case PLANE_C:
11365 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11366 break;
11367 default:
11368 WARN_ONCE(1, "unknown plane in flip command\n");
11369 return -ENODEV;
11370 }
11371
11372 len = 4;
11373 if (engine->id == RCS) {
11374 len += 6;
11375 /*
11376 * On Gen 8, SRM is now taking an extra dword to accommodate
11377 * 48bits addresses, and we need a NOOP for the batch size to
11378 * stay even.
11379 */
11380 if (IS_GEN8(dev))
11381 len += 2;
11382 }
11383
11384 /*
11385 * BSpec MI_DISPLAY_FLIP for IVB:
11386 * "The full packet must be contained within the same cache line."
11387 *
11388 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11389 * cacheline, if we ever start emitting more commands before
11390 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11391 * then do the cacheline alignment, and finally emit the
11392 * MI_DISPLAY_FLIP.
11393 */
11394 ret = intel_ring_cacheline_align(req);
11395 if (ret)
11396 return ret;
11397
11398 ret = intel_ring_begin(req, len);
11399 if (ret)
11400 return ret;
11401
11402 /* Unmask the flip-done completion message. Note that the bspec says that
11403 * we should do this for both the BCS and RCS, and that we must not unmask
11404 * more than one flip event at any time (or ensure that one flip message
11405 * can be sent by waiting for flip-done prior to queueing new flips).
11406 * Experimentation says that BCS works despite DERRMR masking all
11407 * flip-done completion events and that unmasking all planes at once
11408 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11409 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11410 */
11411 if (engine->id == RCS) {
11412 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11413 intel_ring_emit_reg(engine, DERRMR);
11414 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11415 DERRMR_PIPEB_PRI_FLIP_DONE |
11416 DERRMR_PIPEC_PRI_FLIP_DONE));
11417 if (IS_GEN8(dev))
11418 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11419 MI_SRM_LRM_GLOBAL_GTT);
11420 else
11421 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11422 MI_SRM_LRM_GLOBAL_GTT);
11423 intel_ring_emit_reg(engine, DERRMR);
11424 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11425 if (IS_GEN8(dev)) {
11426 intel_ring_emit(engine, 0);
11427 intel_ring_emit(engine, MI_NOOP);
11428 }
11429 }
11430
11431 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11432 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11433 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11434 intel_ring_emit(engine, (MI_NOOP));
11435
11436 return 0;
11437 }
11438
11439 static bool use_mmio_flip(struct intel_engine_cs *engine,
11440 struct drm_i915_gem_object *obj)
11441 {
11442 struct reservation_object *resv;
11443
11444 /*
11445 * This is not being used for older platforms, because
11446 * non-availability of flip done interrupt forces us to use
11447 * CS flips. Older platforms derive flip done using some clever
11448 * tricks involving the flip_pending status bits and vblank irqs.
11449 * So using MMIO flips there would disrupt this mechanism.
11450 */
11451
11452 if (engine == NULL)
11453 return true;
11454
11455 if (INTEL_GEN(engine->i915) < 5)
11456 return false;
11457
11458 if (i915.use_mmio_flip < 0)
11459 return false;
11460 else if (i915.use_mmio_flip > 0)
11461 return true;
11462 else if (i915.enable_execlists)
11463 return true;
11464
11465 resv = i915_gem_object_get_dmabuf_resv(obj);
11466 if (resv && !reservation_object_test_signaled_rcu(resv, false))
11467 return true;
11468
11469 return engine != i915_gem_request_get_engine(obj->last_write_req);
11470 }
11471
11472 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11473 unsigned int rotation,
11474 struct intel_flip_work *work)
11475 {
11476 struct drm_device *dev = intel_crtc->base.dev;
11477 struct drm_i915_private *dev_priv = to_i915(dev);
11478 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11479 const enum pipe pipe = intel_crtc->pipe;
11480 u32 ctl, stride, tile_height;
11481
11482 ctl = I915_READ(PLANE_CTL(pipe, 0));
11483 ctl &= ~PLANE_CTL_TILED_MASK;
11484 switch (fb->modifier[0]) {
11485 case DRM_FORMAT_MOD_NONE:
11486 break;
11487 case I915_FORMAT_MOD_X_TILED:
11488 ctl |= PLANE_CTL_TILED_X;
11489 break;
11490 case I915_FORMAT_MOD_Y_TILED:
11491 ctl |= PLANE_CTL_TILED_Y;
11492 break;
11493 case I915_FORMAT_MOD_Yf_TILED:
11494 ctl |= PLANE_CTL_TILED_YF;
11495 break;
11496 default:
11497 MISSING_CASE(fb->modifier[0]);
11498 }
11499
11500 /*
11501 * The stride is either expressed as a multiple of 64 bytes chunks for
11502 * linear buffers or in number of tiles for tiled buffers.
11503 */
11504 if (intel_rotation_90_or_270(rotation)) {
11505 /* stride = Surface height in tiles */
11506 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11507 stride = DIV_ROUND_UP(fb->height, tile_height);
11508 } else {
11509 stride = fb->pitches[0] /
11510 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11511 fb->pixel_format);
11512 }
11513
11514 /*
11515 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11516 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11517 */
11518 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11519 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11520
11521 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11522 POSTING_READ(PLANE_SURF(pipe, 0));
11523 }
11524
11525 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11526 struct intel_flip_work *work)
11527 {
11528 struct drm_device *dev = intel_crtc->base.dev;
11529 struct drm_i915_private *dev_priv = to_i915(dev);
11530 struct intel_framebuffer *intel_fb =
11531 to_intel_framebuffer(intel_crtc->base.primary->fb);
11532 struct drm_i915_gem_object *obj = intel_fb->obj;
11533 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11534 u32 dspcntr;
11535
11536 dspcntr = I915_READ(reg);
11537
11538 if (obj->tiling_mode != I915_TILING_NONE)
11539 dspcntr |= DISPPLANE_TILED;
11540 else
11541 dspcntr &= ~DISPPLANE_TILED;
11542
11543 I915_WRITE(reg, dspcntr);
11544
11545 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11546 POSTING_READ(DSPSURF(intel_crtc->plane));
11547 }
11548
11549 static void intel_mmio_flip_work_func(struct work_struct *w)
11550 {
11551 struct intel_flip_work *work =
11552 container_of(w, struct intel_flip_work, mmio_work);
11553 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11554 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11555 struct intel_framebuffer *intel_fb =
11556 to_intel_framebuffer(crtc->base.primary->fb);
11557 struct drm_i915_gem_object *obj = intel_fb->obj;
11558 struct reservation_object *resv;
11559
11560 if (work->flip_queued_req)
11561 WARN_ON(__i915_wait_request(work->flip_queued_req,
11562 false, NULL,
11563 &dev_priv->rps.mmioflips));
11564
11565 /* For framebuffer backed by dmabuf, wait for fence */
11566 resv = i915_gem_object_get_dmabuf_resv(obj);
11567 if (resv)
11568 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
11569 MAX_SCHEDULE_TIMEOUT) < 0);
11570
11571 intel_pipe_update_start(crtc);
11572
11573 if (INTEL_GEN(dev_priv) >= 9)
11574 skl_do_mmio_flip(crtc, work->rotation, work);
11575 else
11576 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11577 ilk_do_mmio_flip(crtc, work);
11578
11579 intel_pipe_update_end(crtc, work);
11580 }
11581
11582 static int intel_default_queue_flip(struct drm_device *dev,
11583 struct drm_crtc *crtc,
11584 struct drm_framebuffer *fb,
11585 struct drm_i915_gem_object *obj,
11586 struct drm_i915_gem_request *req,
11587 uint32_t flags)
11588 {
11589 return -ENODEV;
11590 }
11591
11592 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11593 struct intel_crtc *intel_crtc,
11594 struct intel_flip_work *work)
11595 {
11596 u32 addr, vblank;
11597
11598 if (!atomic_read(&work->pending))
11599 return false;
11600
11601 smp_rmb();
11602
11603 vblank = intel_crtc_get_vblank_counter(intel_crtc);
11604 if (work->flip_ready_vblank == 0) {
11605 if (work->flip_queued_req &&
11606 !i915_gem_request_completed(work->flip_queued_req))
11607 return false;
11608
11609 work->flip_ready_vblank = vblank;
11610 }
11611
11612 if (vblank - work->flip_ready_vblank < 3)
11613 return false;
11614
11615 /* Potential stall - if we see that the flip has happened,
11616 * assume a missed interrupt. */
11617 if (INTEL_GEN(dev_priv) >= 4)
11618 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11619 else
11620 addr = I915_READ(DSPADDR(intel_crtc->plane));
11621
11622 /* There is a potential issue here with a false positive after a flip
11623 * to the same address. We could address this by checking for a
11624 * non-incrementing frame counter.
11625 */
11626 return addr == work->gtt_offset;
11627 }
11628
11629 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11630 {
11631 struct drm_device *dev = dev_priv->dev;
11632 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11634 struct intel_flip_work *work;
11635
11636 WARN_ON(!in_interrupt());
11637
11638 if (crtc == NULL)
11639 return;
11640
11641 spin_lock(&dev->event_lock);
11642 work = intel_crtc->flip_work;
11643
11644 if (work != NULL && !is_mmio_work(work) &&
11645 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
11646 WARN_ONCE(1,
11647 "Kicking stuck page flip: queued at %d, now %d\n",
11648 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
11649 page_flip_completed(intel_crtc);
11650 work = NULL;
11651 }
11652
11653 if (work != NULL && !is_mmio_work(work) &&
11654 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
11655 intel_queue_rps_boost_for_request(work->flip_queued_req);
11656 spin_unlock(&dev->event_lock);
11657 }
11658
11659 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11660 struct drm_framebuffer *fb,
11661 struct drm_pending_vblank_event *event,
11662 uint32_t page_flip_flags)
11663 {
11664 struct drm_device *dev = crtc->dev;
11665 struct drm_i915_private *dev_priv = to_i915(dev);
11666 struct drm_framebuffer *old_fb = crtc->primary->fb;
11667 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11669 struct drm_plane *primary = crtc->primary;
11670 enum pipe pipe = intel_crtc->pipe;
11671 struct intel_flip_work *work;
11672 struct intel_engine_cs *engine;
11673 bool mmio_flip;
11674 struct drm_i915_gem_request *request = NULL;
11675 int ret;
11676
11677 /*
11678 * drm_mode_page_flip_ioctl() should already catch this, but double
11679 * check to be safe. In the future we may enable pageflipping from
11680 * a disabled primary plane.
11681 */
11682 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11683 return -EBUSY;
11684
11685 /* Can't change pixel format via MI display flips. */
11686 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11687 return -EINVAL;
11688
11689 /*
11690 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11691 * Note that pitch changes could also affect these register.
11692 */
11693 if (INTEL_INFO(dev)->gen > 3 &&
11694 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11695 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11696 return -EINVAL;
11697
11698 if (i915_terminally_wedged(&dev_priv->gpu_error))
11699 goto out_hang;
11700
11701 work = kzalloc(sizeof(*work), GFP_KERNEL);
11702 if (work == NULL)
11703 return -ENOMEM;
11704
11705 work->event = event;
11706 work->crtc = crtc;
11707 work->old_fb = old_fb;
11708 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
11709
11710 ret = drm_crtc_vblank_get(crtc);
11711 if (ret)
11712 goto free_work;
11713
11714 /* We borrow the event spin lock for protecting flip_work */
11715 spin_lock_irq(&dev->event_lock);
11716 if (intel_crtc->flip_work) {
11717 /* Before declaring the flip queue wedged, check if
11718 * the hardware completed the operation behind our backs.
11719 */
11720 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
11721 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11722 page_flip_completed(intel_crtc);
11723 } else {
11724 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11725 spin_unlock_irq(&dev->event_lock);
11726
11727 drm_crtc_vblank_put(crtc);
11728 kfree(work);
11729 return -EBUSY;
11730 }
11731 }
11732 intel_crtc->flip_work = work;
11733 spin_unlock_irq(&dev->event_lock);
11734
11735 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11736 flush_workqueue(dev_priv->wq);
11737
11738 /* Reference the objects for the scheduled work. */
11739 drm_framebuffer_reference(work->old_fb);
11740 drm_gem_object_reference(&obj->base);
11741
11742 crtc->primary->fb = fb;
11743 update_state_fb(crtc->primary);
11744
11745 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
11746 to_intel_plane_state(primary->state));
11747
11748 work->pending_flip_obj = obj;
11749
11750 ret = i915_mutex_lock_interruptible(dev);
11751 if (ret)
11752 goto cleanup;
11753
11754 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11755 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11756 ret = -EIO;
11757 goto cleanup;
11758 }
11759
11760 atomic_inc(&intel_crtc->unpin_work_count);
11761
11762 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11763 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11764
11765 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11766 engine = &dev_priv->engine[BCS];
11767 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11768 /* vlv: DISPLAY_FLIP fails to change tiling */
11769 engine = NULL;
11770 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11771 engine = &dev_priv->engine[BCS];
11772 } else if (INTEL_INFO(dev)->gen >= 7) {
11773 engine = i915_gem_request_get_engine(obj->last_write_req);
11774 if (engine == NULL || engine->id != RCS)
11775 engine = &dev_priv->engine[BCS];
11776 } else {
11777 engine = &dev_priv->engine[RCS];
11778 }
11779
11780 mmio_flip = use_mmio_flip(engine, obj);
11781
11782 /* When using CS flips, we want to emit semaphores between rings.
11783 * However, when using mmio flips we will create a task to do the
11784 * synchronisation, so all we want here is to pin the framebuffer
11785 * into the display plane and skip any waits.
11786 */
11787 if (!mmio_flip) {
11788 ret = i915_gem_object_sync(obj, engine, &request);
11789 if (!ret && !request) {
11790 request = i915_gem_request_alloc(engine, NULL);
11791 ret = PTR_ERR_OR_ZERO(request);
11792 }
11793
11794 if (ret)
11795 goto cleanup_pending;
11796 }
11797
11798 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11799 if (ret)
11800 goto cleanup_pending;
11801
11802 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11803 obj, 0);
11804 work->gtt_offset += intel_crtc->dspaddr_offset;
11805 work->rotation = crtc->primary->state->rotation;
11806
11807 if (mmio_flip) {
11808 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
11809
11810 i915_gem_request_assign(&work->flip_queued_req,
11811 obj->last_write_req);
11812
11813 schedule_work(&work->mmio_work);
11814 } else {
11815 i915_gem_request_assign(&work->flip_queued_req, request);
11816 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11817 page_flip_flags);
11818 if (ret)
11819 goto cleanup_unpin;
11820
11821 intel_mark_page_flip_active(intel_crtc, work);
11822
11823 i915_add_request_no_flush(request);
11824 }
11825
11826 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
11827 to_intel_plane(primary)->frontbuffer_bit);
11828 mutex_unlock(&dev->struct_mutex);
11829
11830 intel_frontbuffer_flip_prepare(dev,
11831 to_intel_plane(primary)->frontbuffer_bit);
11832
11833 trace_i915_flip_request(intel_crtc->plane, obj);
11834
11835 return 0;
11836
11837 cleanup_unpin:
11838 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11839 cleanup_pending:
11840 if (!IS_ERR_OR_NULL(request))
11841 i915_add_request_no_flush(request);
11842 atomic_dec(&intel_crtc->unpin_work_count);
11843 mutex_unlock(&dev->struct_mutex);
11844 cleanup:
11845 crtc->primary->fb = old_fb;
11846 update_state_fb(crtc->primary);
11847
11848 drm_gem_object_unreference_unlocked(&obj->base);
11849 drm_framebuffer_unreference(work->old_fb);
11850
11851 spin_lock_irq(&dev->event_lock);
11852 intel_crtc->flip_work = NULL;
11853 spin_unlock_irq(&dev->event_lock);
11854
11855 drm_crtc_vblank_put(crtc);
11856 free_work:
11857 kfree(work);
11858
11859 if (ret == -EIO) {
11860 struct drm_atomic_state *state;
11861 struct drm_plane_state *plane_state;
11862
11863 out_hang:
11864 state = drm_atomic_state_alloc(dev);
11865 if (!state)
11866 return -ENOMEM;
11867 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11868
11869 retry:
11870 plane_state = drm_atomic_get_plane_state(state, primary);
11871 ret = PTR_ERR_OR_ZERO(plane_state);
11872 if (!ret) {
11873 drm_atomic_set_fb_for_plane(plane_state, fb);
11874
11875 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11876 if (!ret)
11877 ret = drm_atomic_commit(state);
11878 }
11879
11880 if (ret == -EDEADLK) {
11881 drm_modeset_backoff(state->acquire_ctx);
11882 drm_atomic_state_clear(state);
11883 goto retry;
11884 }
11885
11886 if (ret)
11887 drm_atomic_state_free(state);
11888
11889 if (ret == 0 && event) {
11890 spin_lock_irq(&dev->event_lock);
11891 drm_crtc_send_vblank_event(crtc, event);
11892 spin_unlock_irq(&dev->event_lock);
11893 }
11894 }
11895 return ret;
11896 }
11897
11898
11899 /**
11900 * intel_wm_need_update - Check whether watermarks need updating
11901 * @plane: drm plane
11902 * @state: new plane state
11903 *
11904 * Check current plane state versus the new one to determine whether
11905 * watermarks need to be recalculated.
11906 *
11907 * Returns true or false.
11908 */
11909 static bool intel_wm_need_update(struct drm_plane *plane,
11910 struct drm_plane_state *state)
11911 {
11912 struct intel_plane_state *new = to_intel_plane_state(state);
11913 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11914
11915 /* Update watermarks on tiling or size changes. */
11916 if (new->visible != cur->visible)
11917 return true;
11918
11919 if (!cur->base.fb || !new->base.fb)
11920 return false;
11921
11922 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11923 cur->base.rotation != new->base.rotation ||
11924 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11925 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11926 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11927 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11928 return true;
11929
11930 return false;
11931 }
11932
11933 static bool needs_scaling(struct intel_plane_state *state)
11934 {
11935 int src_w = drm_rect_width(&state->src) >> 16;
11936 int src_h = drm_rect_height(&state->src) >> 16;
11937 int dst_w = drm_rect_width(&state->dst);
11938 int dst_h = drm_rect_height(&state->dst);
11939
11940 return (src_w != dst_w || src_h != dst_h);
11941 }
11942
11943 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11944 struct drm_plane_state *plane_state)
11945 {
11946 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11947 struct drm_crtc *crtc = crtc_state->crtc;
11948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11949 struct drm_plane *plane = plane_state->plane;
11950 struct drm_device *dev = crtc->dev;
11951 struct drm_i915_private *dev_priv = to_i915(dev);
11952 struct intel_plane_state *old_plane_state =
11953 to_intel_plane_state(plane->state);
11954 bool mode_changed = needs_modeset(crtc_state);
11955 bool was_crtc_enabled = crtc->state->active;
11956 bool is_crtc_enabled = crtc_state->active;
11957 bool turn_off, turn_on, visible, was_visible;
11958 struct drm_framebuffer *fb = plane_state->fb;
11959 int ret;
11960
11961 if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
11962 ret = skl_update_scaler_plane(
11963 to_intel_crtc_state(crtc_state),
11964 to_intel_plane_state(plane_state));
11965 if (ret)
11966 return ret;
11967 }
11968
11969 was_visible = old_plane_state->visible;
11970 visible = to_intel_plane_state(plane_state)->visible;
11971
11972 if (!was_crtc_enabled && WARN_ON(was_visible))
11973 was_visible = false;
11974
11975 /*
11976 * Visibility is calculated as if the crtc was on, but
11977 * after scaler setup everything depends on it being off
11978 * when the crtc isn't active.
11979 *
11980 * FIXME this is wrong for watermarks. Watermarks should also
11981 * be computed as if the pipe would be active. Perhaps move
11982 * per-plane wm computation to the .check_plane() hook, and
11983 * only combine the results from all planes in the current place?
11984 */
11985 if (!is_crtc_enabled)
11986 to_intel_plane_state(plane_state)->visible = visible = false;
11987
11988 if (!was_visible && !visible)
11989 return 0;
11990
11991 if (fb != old_plane_state->base.fb)
11992 pipe_config->fb_changed = true;
11993
11994 turn_off = was_visible && (!visible || mode_changed);
11995 turn_on = visible && (!was_visible || mode_changed);
11996
11997 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11998 intel_crtc->base.base.id,
11999 intel_crtc->base.name,
12000 plane->base.id, plane->name,
12001 fb ? fb->base.id : -1);
12002
12003 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12004 plane->base.id, plane->name,
12005 was_visible, visible,
12006 turn_off, turn_on, mode_changed);
12007
12008 if (turn_on) {
12009 pipe_config->update_wm_pre = true;
12010
12011 /* must disable cxsr around plane enable/disable */
12012 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12013 pipe_config->disable_cxsr = true;
12014 } else if (turn_off) {
12015 pipe_config->update_wm_post = true;
12016
12017 /* must disable cxsr around plane enable/disable */
12018 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12019 pipe_config->disable_cxsr = true;
12020 } else if (intel_wm_need_update(plane, plane_state)) {
12021 /* FIXME bollocks */
12022 pipe_config->update_wm_pre = true;
12023 pipe_config->update_wm_post = true;
12024 }
12025
12026 /* Pre-gen9 platforms need two-step watermark updates */
12027 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12028 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12029 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12030
12031 if (visible || was_visible)
12032 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12033
12034 /*
12035 * WaCxSRDisabledForSpriteScaling:ivb
12036 *
12037 * cstate->update_wm was already set above, so this flag will
12038 * take effect when we commit and program watermarks.
12039 */
12040 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12041 needs_scaling(to_intel_plane_state(plane_state)) &&
12042 !needs_scaling(old_plane_state))
12043 pipe_config->disable_lp_wm = true;
12044
12045 return 0;
12046 }
12047
12048 static bool encoders_cloneable(const struct intel_encoder *a,
12049 const struct intel_encoder *b)
12050 {
12051 /* masks could be asymmetric, so check both ways */
12052 return a == b || (a->cloneable & (1 << b->type) &&
12053 b->cloneable & (1 << a->type));
12054 }
12055
12056 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12057 struct intel_crtc *crtc,
12058 struct intel_encoder *encoder)
12059 {
12060 struct intel_encoder *source_encoder;
12061 struct drm_connector *connector;
12062 struct drm_connector_state *connector_state;
12063 int i;
12064
12065 for_each_connector_in_state(state, connector, connector_state, i) {
12066 if (connector_state->crtc != &crtc->base)
12067 continue;
12068
12069 source_encoder =
12070 to_intel_encoder(connector_state->best_encoder);
12071 if (!encoders_cloneable(encoder, source_encoder))
12072 return false;
12073 }
12074
12075 return true;
12076 }
12077
12078 static bool check_encoder_cloning(struct drm_atomic_state *state,
12079 struct intel_crtc *crtc)
12080 {
12081 struct intel_encoder *encoder;
12082 struct drm_connector *connector;
12083 struct drm_connector_state *connector_state;
12084 int i;
12085
12086 for_each_connector_in_state(state, connector, connector_state, i) {
12087 if (connector_state->crtc != &crtc->base)
12088 continue;
12089
12090 encoder = to_intel_encoder(connector_state->best_encoder);
12091 if (!check_single_encoder_cloning(state, crtc, encoder))
12092 return false;
12093 }
12094
12095 return true;
12096 }
12097
12098 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12099 struct drm_crtc_state *crtc_state)
12100 {
12101 struct drm_device *dev = crtc->dev;
12102 struct drm_i915_private *dev_priv = to_i915(dev);
12103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12104 struct intel_crtc_state *pipe_config =
12105 to_intel_crtc_state(crtc_state);
12106 struct drm_atomic_state *state = crtc_state->state;
12107 int ret;
12108 bool mode_changed = needs_modeset(crtc_state);
12109
12110 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12111 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12112 return -EINVAL;
12113 }
12114
12115 if (mode_changed && !crtc_state->active)
12116 pipe_config->update_wm_post = true;
12117
12118 if (mode_changed && crtc_state->enable &&
12119 dev_priv->display.crtc_compute_clock &&
12120 !WARN_ON(pipe_config->shared_dpll)) {
12121 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12122 pipe_config);
12123 if (ret)
12124 return ret;
12125 }
12126
12127 if (crtc_state->color_mgmt_changed) {
12128 ret = intel_color_check(crtc, crtc_state);
12129 if (ret)
12130 return ret;
12131 }
12132
12133 ret = 0;
12134 if (dev_priv->display.compute_pipe_wm) {
12135 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12136 if (ret) {
12137 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12138 return ret;
12139 }
12140 }
12141
12142 if (dev_priv->display.compute_intermediate_wm &&
12143 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12144 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12145 return 0;
12146
12147 /*
12148 * Calculate 'intermediate' watermarks that satisfy both the
12149 * old state and the new state. We can program these
12150 * immediately.
12151 */
12152 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12153 intel_crtc,
12154 pipe_config);
12155 if (ret) {
12156 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12157 return ret;
12158 }
12159 } else if (dev_priv->display.compute_intermediate_wm) {
12160 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12161 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12162 }
12163
12164 if (INTEL_INFO(dev)->gen >= 9) {
12165 if (mode_changed)
12166 ret = skl_update_scaler_crtc(pipe_config);
12167
12168 if (!ret)
12169 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12170 pipe_config);
12171 }
12172
12173 return ret;
12174 }
12175
12176 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12177 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12178 .atomic_begin = intel_begin_crtc_commit,
12179 .atomic_flush = intel_finish_crtc_commit,
12180 .atomic_check = intel_crtc_atomic_check,
12181 };
12182
12183 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12184 {
12185 struct intel_connector *connector;
12186
12187 for_each_intel_connector(dev, connector) {
12188 if (connector->base.state->crtc)
12189 drm_connector_unreference(&connector->base);
12190
12191 if (connector->base.encoder) {
12192 connector->base.state->best_encoder =
12193 connector->base.encoder;
12194 connector->base.state->crtc =
12195 connector->base.encoder->crtc;
12196
12197 drm_connector_reference(&connector->base);
12198 } else {
12199 connector->base.state->best_encoder = NULL;
12200 connector->base.state->crtc = NULL;
12201 }
12202 }
12203 }
12204
12205 static void
12206 connected_sink_compute_bpp(struct intel_connector *connector,
12207 struct intel_crtc_state *pipe_config)
12208 {
12209 int bpp = pipe_config->pipe_bpp;
12210
12211 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12212 connector->base.base.id,
12213 connector->base.name);
12214
12215 /* Don't use an invalid EDID bpc value */
12216 if (connector->base.display_info.bpc &&
12217 connector->base.display_info.bpc * 3 < bpp) {
12218 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12219 bpp, connector->base.display_info.bpc*3);
12220 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12221 }
12222
12223 /* Clamp bpp to default limit on screens without EDID 1.4 */
12224 if (connector->base.display_info.bpc == 0) {
12225 int type = connector->base.connector_type;
12226 int clamp_bpp = 24;
12227
12228 /* Fall back to 18 bpp when DP sink capability is unknown. */
12229 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12230 type == DRM_MODE_CONNECTOR_eDP)
12231 clamp_bpp = 18;
12232
12233 if (bpp > clamp_bpp) {
12234 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12235 bpp, clamp_bpp);
12236 pipe_config->pipe_bpp = clamp_bpp;
12237 }
12238 }
12239 }
12240
12241 static int
12242 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12243 struct intel_crtc_state *pipe_config)
12244 {
12245 struct drm_device *dev = crtc->base.dev;
12246 struct drm_atomic_state *state;
12247 struct drm_connector *connector;
12248 struct drm_connector_state *connector_state;
12249 int bpp, i;
12250
12251 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12252 bpp = 10*3;
12253 else if (INTEL_INFO(dev)->gen >= 5)
12254 bpp = 12*3;
12255 else
12256 bpp = 8*3;
12257
12258
12259 pipe_config->pipe_bpp = bpp;
12260
12261 state = pipe_config->base.state;
12262
12263 /* Clamp display bpp to EDID value */
12264 for_each_connector_in_state(state, connector, connector_state, i) {
12265 if (connector_state->crtc != &crtc->base)
12266 continue;
12267
12268 connected_sink_compute_bpp(to_intel_connector(connector),
12269 pipe_config);
12270 }
12271
12272 return bpp;
12273 }
12274
12275 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12276 {
12277 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12278 "type: 0x%x flags: 0x%x\n",
12279 mode->crtc_clock,
12280 mode->crtc_hdisplay, mode->crtc_hsync_start,
12281 mode->crtc_hsync_end, mode->crtc_htotal,
12282 mode->crtc_vdisplay, mode->crtc_vsync_start,
12283 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12284 }
12285
12286 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12287 struct intel_crtc_state *pipe_config,
12288 const char *context)
12289 {
12290 struct drm_device *dev = crtc->base.dev;
12291 struct drm_plane *plane;
12292 struct intel_plane *intel_plane;
12293 struct intel_plane_state *state;
12294 struct drm_framebuffer *fb;
12295
12296 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12297 crtc->base.base.id, crtc->base.name,
12298 context, pipe_config, pipe_name(crtc->pipe));
12299
12300 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12301 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12302 pipe_config->pipe_bpp, pipe_config->dither);
12303 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12304 pipe_config->has_pch_encoder,
12305 pipe_config->fdi_lanes,
12306 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12307 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12308 pipe_config->fdi_m_n.tu);
12309 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12310 pipe_config->has_dp_encoder,
12311 pipe_config->lane_count,
12312 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12313 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12314 pipe_config->dp_m_n.tu);
12315
12316 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12317 pipe_config->has_dp_encoder,
12318 pipe_config->lane_count,
12319 pipe_config->dp_m2_n2.gmch_m,
12320 pipe_config->dp_m2_n2.gmch_n,
12321 pipe_config->dp_m2_n2.link_m,
12322 pipe_config->dp_m2_n2.link_n,
12323 pipe_config->dp_m2_n2.tu);
12324
12325 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12326 pipe_config->has_audio,
12327 pipe_config->has_infoframe);
12328
12329 DRM_DEBUG_KMS("requested mode:\n");
12330 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12331 DRM_DEBUG_KMS("adjusted mode:\n");
12332 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12333 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12334 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12335 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12336 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12337 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12338 crtc->num_scalers,
12339 pipe_config->scaler_state.scaler_users,
12340 pipe_config->scaler_state.scaler_id);
12341 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12342 pipe_config->gmch_pfit.control,
12343 pipe_config->gmch_pfit.pgm_ratios,
12344 pipe_config->gmch_pfit.lvds_border_bits);
12345 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12346 pipe_config->pch_pfit.pos,
12347 pipe_config->pch_pfit.size,
12348 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12349 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12350 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12351
12352 if (IS_BROXTON(dev)) {
12353 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12354 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12355 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12356 pipe_config->ddi_pll_sel,
12357 pipe_config->dpll_hw_state.ebb0,
12358 pipe_config->dpll_hw_state.ebb4,
12359 pipe_config->dpll_hw_state.pll0,
12360 pipe_config->dpll_hw_state.pll1,
12361 pipe_config->dpll_hw_state.pll2,
12362 pipe_config->dpll_hw_state.pll3,
12363 pipe_config->dpll_hw_state.pll6,
12364 pipe_config->dpll_hw_state.pll8,
12365 pipe_config->dpll_hw_state.pll9,
12366 pipe_config->dpll_hw_state.pll10,
12367 pipe_config->dpll_hw_state.pcsdw12);
12368 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12369 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12370 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12371 pipe_config->ddi_pll_sel,
12372 pipe_config->dpll_hw_state.ctrl1,
12373 pipe_config->dpll_hw_state.cfgcr1,
12374 pipe_config->dpll_hw_state.cfgcr2);
12375 } else if (HAS_DDI(dev)) {
12376 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12377 pipe_config->ddi_pll_sel,
12378 pipe_config->dpll_hw_state.wrpll,
12379 pipe_config->dpll_hw_state.spll);
12380 } else {
12381 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12382 "fp0: 0x%x, fp1: 0x%x\n",
12383 pipe_config->dpll_hw_state.dpll,
12384 pipe_config->dpll_hw_state.dpll_md,
12385 pipe_config->dpll_hw_state.fp0,
12386 pipe_config->dpll_hw_state.fp1);
12387 }
12388
12389 DRM_DEBUG_KMS("planes on this crtc\n");
12390 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12391 intel_plane = to_intel_plane(plane);
12392 if (intel_plane->pipe != crtc->pipe)
12393 continue;
12394
12395 state = to_intel_plane_state(plane->state);
12396 fb = state->base.fb;
12397 if (!fb) {
12398 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12399 plane->base.id, plane->name, state->scaler_id);
12400 continue;
12401 }
12402
12403 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12404 plane->base.id, plane->name);
12405 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12406 fb->base.id, fb->width, fb->height,
12407 drm_get_format_name(fb->pixel_format));
12408 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12409 state->scaler_id,
12410 state->src.x1 >> 16, state->src.y1 >> 16,
12411 drm_rect_width(&state->src) >> 16,
12412 drm_rect_height(&state->src) >> 16,
12413 state->dst.x1, state->dst.y1,
12414 drm_rect_width(&state->dst),
12415 drm_rect_height(&state->dst));
12416 }
12417 }
12418
12419 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12420 {
12421 struct drm_device *dev = state->dev;
12422 struct drm_connector *connector;
12423 unsigned int used_ports = 0;
12424
12425 /*
12426 * Walk the connector list instead of the encoder
12427 * list to detect the problem on ddi platforms
12428 * where there's just one encoder per digital port.
12429 */
12430 drm_for_each_connector(connector, dev) {
12431 struct drm_connector_state *connector_state;
12432 struct intel_encoder *encoder;
12433
12434 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12435 if (!connector_state)
12436 connector_state = connector->state;
12437
12438 if (!connector_state->best_encoder)
12439 continue;
12440
12441 encoder = to_intel_encoder(connector_state->best_encoder);
12442
12443 WARN_ON(!connector_state->crtc);
12444
12445 switch (encoder->type) {
12446 unsigned int port_mask;
12447 case INTEL_OUTPUT_UNKNOWN:
12448 if (WARN_ON(!HAS_DDI(dev)))
12449 break;
12450 case INTEL_OUTPUT_DISPLAYPORT:
12451 case INTEL_OUTPUT_HDMI:
12452 case INTEL_OUTPUT_EDP:
12453 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12454
12455 /* the same port mustn't appear more than once */
12456 if (used_ports & port_mask)
12457 return false;
12458
12459 used_ports |= port_mask;
12460 default:
12461 break;
12462 }
12463 }
12464
12465 return true;
12466 }
12467
12468 static void
12469 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12470 {
12471 struct drm_crtc_state tmp_state;
12472 struct intel_crtc_scaler_state scaler_state;
12473 struct intel_dpll_hw_state dpll_hw_state;
12474 struct intel_shared_dpll *shared_dpll;
12475 uint32_t ddi_pll_sel;
12476 bool force_thru;
12477
12478 /* FIXME: before the switch to atomic started, a new pipe_config was
12479 * kzalloc'd. Code that depends on any field being zero should be
12480 * fixed, so that the crtc_state can be safely duplicated. For now,
12481 * only fields that are know to not cause problems are preserved. */
12482
12483 tmp_state = crtc_state->base;
12484 scaler_state = crtc_state->scaler_state;
12485 shared_dpll = crtc_state->shared_dpll;
12486 dpll_hw_state = crtc_state->dpll_hw_state;
12487 ddi_pll_sel = crtc_state->ddi_pll_sel;
12488 force_thru = crtc_state->pch_pfit.force_thru;
12489
12490 memset(crtc_state, 0, sizeof *crtc_state);
12491
12492 crtc_state->base = tmp_state;
12493 crtc_state->scaler_state = scaler_state;
12494 crtc_state->shared_dpll = shared_dpll;
12495 crtc_state->dpll_hw_state = dpll_hw_state;
12496 crtc_state->ddi_pll_sel = ddi_pll_sel;
12497 crtc_state->pch_pfit.force_thru = force_thru;
12498 }
12499
12500 static int
12501 intel_modeset_pipe_config(struct drm_crtc *crtc,
12502 struct intel_crtc_state *pipe_config)
12503 {
12504 struct drm_atomic_state *state = pipe_config->base.state;
12505 struct intel_encoder *encoder;
12506 struct drm_connector *connector;
12507 struct drm_connector_state *connector_state;
12508 int base_bpp, ret = -EINVAL;
12509 int i;
12510 bool retry = true;
12511
12512 clear_intel_crtc_state(pipe_config);
12513
12514 pipe_config->cpu_transcoder =
12515 (enum transcoder) to_intel_crtc(crtc)->pipe;
12516
12517 /*
12518 * Sanitize sync polarity flags based on requested ones. If neither
12519 * positive or negative polarity is requested, treat this as meaning
12520 * negative polarity.
12521 */
12522 if (!(pipe_config->base.adjusted_mode.flags &
12523 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12524 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12525
12526 if (!(pipe_config->base.adjusted_mode.flags &
12527 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12528 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12529
12530 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12531 pipe_config);
12532 if (base_bpp < 0)
12533 goto fail;
12534
12535 /*
12536 * Determine the real pipe dimensions. Note that stereo modes can
12537 * increase the actual pipe size due to the frame doubling and
12538 * insertion of additional space for blanks between the frame. This
12539 * is stored in the crtc timings. We use the requested mode to do this
12540 * computation to clearly distinguish it from the adjusted mode, which
12541 * can be changed by the connectors in the below retry loop.
12542 */
12543 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12544 &pipe_config->pipe_src_w,
12545 &pipe_config->pipe_src_h);
12546
12547 encoder_retry:
12548 /* Ensure the port clock defaults are reset when retrying. */
12549 pipe_config->port_clock = 0;
12550 pipe_config->pixel_multiplier = 1;
12551
12552 /* Fill in default crtc timings, allow encoders to overwrite them. */
12553 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12554 CRTC_STEREO_DOUBLE);
12555
12556 /* Pass our mode to the connectors and the CRTC to give them a chance to
12557 * adjust it according to limitations or connector properties, and also
12558 * a chance to reject the mode entirely.
12559 */
12560 for_each_connector_in_state(state, connector, connector_state, i) {
12561 if (connector_state->crtc != crtc)
12562 continue;
12563
12564 encoder = to_intel_encoder(connector_state->best_encoder);
12565
12566 if (!(encoder->compute_config(encoder, pipe_config))) {
12567 DRM_DEBUG_KMS("Encoder config failure\n");
12568 goto fail;
12569 }
12570 }
12571
12572 /* Set default port clock if not overwritten by the encoder. Needs to be
12573 * done afterwards in case the encoder adjusts the mode. */
12574 if (!pipe_config->port_clock)
12575 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12576 * pipe_config->pixel_multiplier;
12577
12578 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12579 if (ret < 0) {
12580 DRM_DEBUG_KMS("CRTC fixup failed\n");
12581 goto fail;
12582 }
12583
12584 if (ret == RETRY) {
12585 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12586 ret = -EINVAL;
12587 goto fail;
12588 }
12589
12590 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12591 retry = false;
12592 goto encoder_retry;
12593 }
12594
12595 /* Dithering seems to not pass-through bits correctly when it should, so
12596 * only enable it on 6bpc panels. */
12597 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12598 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12599 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12600
12601 fail:
12602 return ret;
12603 }
12604
12605 static void
12606 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12607 {
12608 struct drm_crtc *crtc;
12609 struct drm_crtc_state *crtc_state;
12610 int i;
12611
12612 /* Double check state. */
12613 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12614 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12615
12616 /* Update hwmode for vblank functions */
12617 if (crtc->state->active)
12618 crtc->hwmode = crtc->state->adjusted_mode;
12619 else
12620 crtc->hwmode.crtc_clock = 0;
12621
12622 /*
12623 * Update legacy state to satisfy fbc code. This can
12624 * be removed when fbc uses the atomic state.
12625 */
12626 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12627 struct drm_plane_state *plane_state = crtc->primary->state;
12628
12629 crtc->primary->fb = plane_state->fb;
12630 crtc->x = plane_state->src_x >> 16;
12631 crtc->y = plane_state->src_y >> 16;
12632 }
12633 }
12634 }
12635
12636 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12637 {
12638 int diff;
12639
12640 if (clock1 == clock2)
12641 return true;
12642
12643 if (!clock1 || !clock2)
12644 return false;
12645
12646 diff = abs(clock1 - clock2);
12647
12648 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12649 return true;
12650
12651 return false;
12652 }
12653
12654 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12655 list_for_each_entry((intel_crtc), \
12656 &(dev)->mode_config.crtc_list, \
12657 base.head) \
12658 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12659
12660 static bool
12661 intel_compare_m_n(unsigned int m, unsigned int n,
12662 unsigned int m2, unsigned int n2,
12663 bool exact)
12664 {
12665 if (m == m2 && n == n2)
12666 return true;
12667
12668 if (exact || !m || !n || !m2 || !n2)
12669 return false;
12670
12671 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12672
12673 if (n > n2) {
12674 while (n > n2) {
12675 m2 <<= 1;
12676 n2 <<= 1;
12677 }
12678 } else if (n < n2) {
12679 while (n < n2) {
12680 m <<= 1;
12681 n <<= 1;
12682 }
12683 }
12684
12685 if (n != n2)
12686 return false;
12687
12688 return intel_fuzzy_clock_check(m, m2);
12689 }
12690
12691 static bool
12692 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12693 struct intel_link_m_n *m2_n2,
12694 bool adjust)
12695 {
12696 if (m_n->tu == m2_n2->tu &&
12697 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12698 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12699 intel_compare_m_n(m_n->link_m, m_n->link_n,
12700 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12701 if (adjust)
12702 *m2_n2 = *m_n;
12703
12704 return true;
12705 }
12706
12707 return false;
12708 }
12709
12710 static bool
12711 intel_pipe_config_compare(struct drm_device *dev,
12712 struct intel_crtc_state *current_config,
12713 struct intel_crtc_state *pipe_config,
12714 bool adjust)
12715 {
12716 bool ret = true;
12717
12718 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12719 do { \
12720 if (!adjust) \
12721 DRM_ERROR(fmt, ##__VA_ARGS__); \
12722 else \
12723 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12724 } while (0)
12725
12726 #define PIPE_CONF_CHECK_X(name) \
12727 if (current_config->name != pipe_config->name) { \
12728 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12729 "(expected 0x%08x, found 0x%08x)\n", \
12730 current_config->name, \
12731 pipe_config->name); \
12732 ret = false; \
12733 }
12734
12735 #define PIPE_CONF_CHECK_I(name) \
12736 if (current_config->name != pipe_config->name) { \
12737 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12738 "(expected %i, found %i)\n", \
12739 current_config->name, \
12740 pipe_config->name); \
12741 ret = false; \
12742 }
12743
12744 #define PIPE_CONF_CHECK_P(name) \
12745 if (current_config->name != pipe_config->name) { \
12746 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12747 "(expected %p, found %p)\n", \
12748 current_config->name, \
12749 pipe_config->name); \
12750 ret = false; \
12751 }
12752
12753 #define PIPE_CONF_CHECK_M_N(name) \
12754 if (!intel_compare_link_m_n(&current_config->name, \
12755 &pipe_config->name,\
12756 adjust)) { \
12757 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12758 "(expected tu %i gmch %i/%i link %i/%i, " \
12759 "found tu %i, gmch %i/%i link %i/%i)\n", \
12760 current_config->name.tu, \
12761 current_config->name.gmch_m, \
12762 current_config->name.gmch_n, \
12763 current_config->name.link_m, \
12764 current_config->name.link_n, \
12765 pipe_config->name.tu, \
12766 pipe_config->name.gmch_m, \
12767 pipe_config->name.gmch_n, \
12768 pipe_config->name.link_m, \
12769 pipe_config->name.link_n); \
12770 ret = false; \
12771 }
12772
12773 /* This is required for BDW+ where there is only one set of registers for
12774 * switching between high and low RR.
12775 * This macro can be used whenever a comparison has to be made between one
12776 * hw state and multiple sw state variables.
12777 */
12778 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12779 if (!intel_compare_link_m_n(&current_config->name, \
12780 &pipe_config->name, adjust) && \
12781 !intel_compare_link_m_n(&current_config->alt_name, \
12782 &pipe_config->name, adjust)) { \
12783 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12784 "(expected tu %i gmch %i/%i link %i/%i, " \
12785 "or tu %i gmch %i/%i link %i/%i, " \
12786 "found tu %i, gmch %i/%i link %i/%i)\n", \
12787 current_config->name.tu, \
12788 current_config->name.gmch_m, \
12789 current_config->name.gmch_n, \
12790 current_config->name.link_m, \
12791 current_config->name.link_n, \
12792 current_config->alt_name.tu, \
12793 current_config->alt_name.gmch_m, \
12794 current_config->alt_name.gmch_n, \
12795 current_config->alt_name.link_m, \
12796 current_config->alt_name.link_n, \
12797 pipe_config->name.tu, \
12798 pipe_config->name.gmch_m, \
12799 pipe_config->name.gmch_n, \
12800 pipe_config->name.link_m, \
12801 pipe_config->name.link_n); \
12802 ret = false; \
12803 }
12804
12805 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12806 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12807 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12808 "(expected %i, found %i)\n", \
12809 current_config->name & (mask), \
12810 pipe_config->name & (mask)); \
12811 ret = false; \
12812 }
12813
12814 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12815 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12816 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12817 "(expected %i, found %i)\n", \
12818 current_config->name, \
12819 pipe_config->name); \
12820 ret = false; \
12821 }
12822
12823 #define PIPE_CONF_QUIRK(quirk) \
12824 ((current_config->quirks | pipe_config->quirks) & (quirk))
12825
12826 PIPE_CONF_CHECK_I(cpu_transcoder);
12827
12828 PIPE_CONF_CHECK_I(has_pch_encoder);
12829 PIPE_CONF_CHECK_I(fdi_lanes);
12830 PIPE_CONF_CHECK_M_N(fdi_m_n);
12831
12832 PIPE_CONF_CHECK_I(has_dp_encoder);
12833 PIPE_CONF_CHECK_I(lane_count);
12834 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12835
12836 if (INTEL_INFO(dev)->gen < 8) {
12837 PIPE_CONF_CHECK_M_N(dp_m_n);
12838
12839 if (current_config->has_drrs)
12840 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12841 } else
12842 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12843
12844 PIPE_CONF_CHECK_I(has_dsi_encoder);
12845
12846 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12847 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12848 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12849 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12850 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12851 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12852
12853 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12854 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12855 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12856 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12857 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12858 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12859
12860 PIPE_CONF_CHECK_I(pixel_multiplier);
12861 PIPE_CONF_CHECK_I(has_hdmi_sink);
12862 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12863 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12864 PIPE_CONF_CHECK_I(limited_color_range);
12865 PIPE_CONF_CHECK_I(has_infoframe);
12866
12867 PIPE_CONF_CHECK_I(has_audio);
12868
12869 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12870 DRM_MODE_FLAG_INTERLACE);
12871
12872 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12873 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12874 DRM_MODE_FLAG_PHSYNC);
12875 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12876 DRM_MODE_FLAG_NHSYNC);
12877 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12878 DRM_MODE_FLAG_PVSYNC);
12879 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12880 DRM_MODE_FLAG_NVSYNC);
12881 }
12882
12883 PIPE_CONF_CHECK_X(gmch_pfit.control);
12884 /* pfit ratios are autocomputed by the hw on gen4+ */
12885 if (INTEL_INFO(dev)->gen < 4)
12886 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12887 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12888
12889 if (!adjust) {
12890 PIPE_CONF_CHECK_I(pipe_src_w);
12891 PIPE_CONF_CHECK_I(pipe_src_h);
12892
12893 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12894 if (current_config->pch_pfit.enabled) {
12895 PIPE_CONF_CHECK_X(pch_pfit.pos);
12896 PIPE_CONF_CHECK_X(pch_pfit.size);
12897 }
12898
12899 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12900 }
12901
12902 /* BDW+ don't expose a synchronous way to read the state */
12903 if (IS_HASWELL(dev))
12904 PIPE_CONF_CHECK_I(ips_enabled);
12905
12906 PIPE_CONF_CHECK_I(double_wide);
12907
12908 PIPE_CONF_CHECK_X(ddi_pll_sel);
12909
12910 PIPE_CONF_CHECK_P(shared_dpll);
12911 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12912 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12913 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12914 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12915 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12916 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12917 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12918 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12919 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12920
12921 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12922 PIPE_CONF_CHECK_X(dsi_pll.div);
12923
12924 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12925 PIPE_CONF_CHECK_I(pipe_bpp);
12926
12927 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12928 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12929
12930 #undef PIPE_CONF_CHECK_X
12931 #undef PIPE_CONF_CHECK_I
12932 #undef PIPE_CONF_CHECK_P
12933 #undef PIPE_CONF_CHECK_FLAGS
12934 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12935 #undef PIPE_CONF_QUIRK
12936 #undef INTEL_ERR_OR_DBG_KMS
12937
12938 return ret;
12939 }
12940
12941 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12942 const struct intel_crtc_state *pipe_config)
12943 {
12944 if (pipe_config->has_pch_encoder) {
12945 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12946 &pipe_config->fdi_m_n);
12947 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12948
12949 /*
12950 * FDI already provided one idea for the dotclock.
12951 * Yell if the encoder disagrees.
12952 */
12953 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12954 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12955 fdi_dotclock, dotclock);
12956 }
12957 }
12958
12959 static void verify_wm_state(struct drm_crtc *crtc,
12960 struct drm_crtc_state *new_state)
12961 {
12962 struct drm_device *dev = crtc->dev;
12963 struct drm_i915_private *dev_priv = to_i915(dev);
12964 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12965 struct skl_ddb_entry *hw_entry, *sw_entry;
12966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12967 const enum pipe pipe = intel_crtc->pipe;
12968 int plane;
12969
12970 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12971 return;
12972
12973 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12974 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12975
12976 /* planes */
12977 for_each_plane(dev_priv, pipe, plane) {
12978 hw_entry = &hw_ddb.plane[pipe][plane];
12979 sw_entry = &sw_ddb->plane[pipe][plane];
12980
12981 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12982 continue;
12983
12984 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12985 "(expected (%u,%u), found (%u,%u))\n",
12986 pipe_name(pipe), plane + 1,
12987 sw_entry->start, sw_entry->end,
12988 hw_entry->start, hw_entry->end);
12989 }
12990
12991 /* cursor */
12992 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12993 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12994
12995 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12996 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12997 "(expected (%u,%u), found (%u,%u))\n",
12998 pipe_name(pipe),
12999 sw_entry->start, sw_entry->end,
13000 hw_entry->start, hw_entry->end);
13001 }
13002 }
13003
13004 static void
13005 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13006 {
13007 struct drm_connector *connector;
13008
13009 drm_for_each_connector(connector, dev) {
13010 struct drm_encoder *encoder = connector->encoder;
13011 struct drm_connector_state *state = connector->state;
13012
13013 if (state->crtc != crtc)
13014 continue;
13015
13016 intel_connector_verify_state(to_intel_connector(connector));
13017
13018 I915_STATE_WARN(state->best_encoder != encoder,
13019 "connector's atomic encoder doesn't match legacy encoder\n");
13020 }
13021 }
13022
13023 static void
13024 verify_encoder_state(struct drm_device *dev)
13025 {
13026 struct intel_encoder *encoder;
13027 struct intel_connector *connector;
13028
13029 for_each_intel_encoder(dev, encoder) {
13030 bool enabled = false;
13031 enum pipe pipe;
13032
13033 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13034 encoder->base.base.id,
13035 encoder->base.name);
13036
13037 for_each_intel_connector(dev, connector) {
13038 if (connector->base.state->best_encoder != &encoder->base)
13039 continue;
13040 enabled = true;
13041
13042 I915_STATE_WARN(connector->base.state->crtc !=
13043 encoder->base.crtc,
13044 "connector's crtc doesn't match encoder crtc\n");
13045 }
13046
13047 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13048 "encoder's enabled state mismatch "
13049 "(expected %i, found %i)\n",
13050 !!encoder->base.crtc, enabled);
13051
13052 if (!encoder->base.crtc) {
13053 bool active;
13054
13055 active = encoder->get_hw_state(encoder, &pipe);
13056 I915_STATE_WARN(active,
13057 "encoder detached but still enabled on pipe %c.\n",
13058 pipe_name(pipe));
13059 }
13060 }
13061 }
13062
13063 static void
13064 verify_crtc_state(struct drm_crtc *crtc,
13065 struct drm_crtc_state *old_crtc_state,
13066 struct drm_crtc_state *new_crtc_state)
13067 {
13068 struct drm_device *dev = crtc->dev;
13069 struct drm_i915_private *dev_priv = to_i915(dev);
13070 struct intel_encoder *encoder;
13071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13072 struct intel_crtc_state *pipe_config, *sw_config;
13073 struct drm_atomic_state *old_state;
13074 bool active;
13075
13076 old_state = old_crtc_state->state;
13077 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13078 pipe_config = to_intel_crtc_state(old_crtc_state);
13079 memset(pipe_config, 0, sizeof(*pipe_config));
13080 pipe_config->base.crtc = crtc;
13081 pipe_config->base.state = old_state;
13082
13083 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13084
13085 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13086
13087 /* hw state is inconsistent with the pipe quirk */
13088 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13089 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13090 active = new_crtc_state->active;
13091
13092 I915_STATE_WARN(new_crtc_state->active != active,
13093 "crtc active state doesn't match with hw state "
13094 "(expected %i, found %i)\n", new_crtc_state->active, active);
13095
13096 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13097 "transitional active state does not match atomic hw state "
13098 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13099
13100 for_each_encoder_on_crtc(dev, crtc, encoder) {
13101 enum pipe pipe;
13102
13103 active = encoder->get_hw_state(encoder, &pipe);
13104 I915_STATE_WARN(active != new_crtc_state->active,
13105 "[ENCODER:%i] active %i with crtc active %i\n",
13106 encoder->base.base.id, active, new_crtc_state->active);
13107
13108 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13109 "Encoder connected to wrong pipe %c\n",
13110 pipe_name(pipe));
13111
13112 if (active)
13113 encoder->get_config(encoder, pipe_config);
13114 }
13115
13116 if (!new_crtc_state->active)
13117 return;
13118
13119 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13120
13121 sw_config = to_intel_crtc_state(crtc->state);
13122 if (!intel_pipe_config_compare(dev, sw_config,
13123 pipe_config, false)) {
13124 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13125 intel_dump_pipe_config(intel_crtc, pipe_config,
13126 "[hw state]");
13127 intel_dump_pipe_config(intel_crtc, sw_config,
13128 "[sw state]");
13129 }
13130 }
13131
13132 static void
13133 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13134 struct intel_shared_dpll *pll,
13135 struct drm_crtc *crtc,
13136 struct drm_crtc_state *new_state)
13137 {
13138 struct intel_dpll_hw_state dpll_hw_state;
13139 unsigned crtc_mask;
13140 bool active;
13141
13142 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13143
13144 DRM_DEBUG_KMS("%s\n", pll->name);
13145
13146 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13147
13148 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13149 I915_STATE_WARN(!pll->on && pll->active_mask,
13150 "pll in active use but not on in sw tracking\n");
13151 I915_STATE_WARN(pll->on && !pll->active_mask,
13152 "pll is on but not used by any active crtc\n");
13153 I915_STATE_WARN(pll->on != active,
13154 "pll on state mismatch (expected %i, found %i)\n",
13155 pll->on, active);
13156 }
13157
13158 if (!crtc) {
13159 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13160 "more active pll users than references: %x vs %x\n",
13161 pll->active_mask, pll->config.crtc_mask);
13162
13163 return;
13164 }
13165
13166 crtc_mask = 1 << drm_crtc_index(crtc);
13167
13168 if (new_state->active)
13169 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13170 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13171 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13172 else
13173 I915_STATE_WARN(pll->active_mask & crtc_mask,
13174 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13175 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13176
13177 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13178 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13179 crtc_mask, pll->config.crtc_mask);
13180
13181 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13182 &dpll_hw_state,
13183 sizeof(dpll_hw_state)),
13184 "pll hw state mismatch\n");
13185 }
13186
13187 static void
13188 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13189 struct drm_crtc_state *old_crtc_state,
13190 struct drm_crtc_state *new_crtc_state)
13191 {
13192 struct drm_i915_private *dev_priv = to_i915(dev);
13193 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13194 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13195
13196 if (new_state->shared_dpll)
13197 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13198
13199 if (old_state->shared_dpll &&
13200 old_state->shared_dpll != new_state->shared_dpll) {
13201 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13202 struct intel_shared_dpll *pll = old_state->shared_dpll;
13203
13204 I915_STATE_WARN(pll->active_mask & crtc_mask,
13205 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13206 pipe_name(drm_crtc_index(crtc)));
13207 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13208 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13209 pipe_name(drm_crtc_index(crtc)));
13210 }
13211 }
13212
13213 static void
13214 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13215 struct drm_crtc_state *old_state,
13216 struct drm_crtc_state *new_state)
13217 {
13218 if (!needs_modeset(new_state) &&
13219 !to_intel_crtc_state(new_state)->update_pipe)
13220 return;
13221
13222 verify_wm_state(crtc, new_state);
13223 verify_connector_state(crtc->dev, crtc);
13224 verify_crtc_state(crtc, old_state, new_state);
13225 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13226 }
13227
13228 static void
13229 verify_disabled_dpll_state(struct drm_device *dev)
13230 {
13231 struct drm_i915_private *dev_priv = to_i915(dev);
13232 int i;
13233
13234 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13235 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13236 }
13237
13238 static void
13239 intel_modeset_verify_disabled(struct drm_device *dev)
13240 {
13241 verify_encoder_state(dev);
13242 verify_connector_state(dev, NULL);
13243 verify_disabled_dpll_state(dev);
13244 }
13245
13246 static void update_scanline_offset(struct intel_crtc *crtc)
13247 {
13248 struct drm_device *dev = crtc->base.dev;
13249
13250 /*
13251 * The scanline counter increments at the leading edge of hsync.
13252 *
13253 * On most platforms it starts counting from vtotal-1 on the
13254 * first active line. That means the scanline counter value is
13255 * always one less than what we would expect. Ie. just after
13256 * start of vblank, which also occurs at start of hsync (on the
13257 * last active line), the scanline counter will read vblank_start-1.
13258 *
13259 * On gen2 the scanline counter starts counting from 1 instead
13260 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13261 * to keep the value positive), instead of adding one.
13262 *
13263 * On HSW+ the behaviour of the scanline counter depends on the output
13264 * type. For DP ports it behaves like most other platforms, but on HDMI
13265 * there's an extra 1 line difference. So we need to add two instead of
13266 * one to the value.
13267 */
13268 if (IS_GEN2(dev)) {
13269 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13270 int vtotal;
13271
13272 vtotal = adjusted_mode->crtc_vtotal;
13273 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13274 vtotal /= 2;
13275
13276 crtc->scanline_offset = vtotal - 1;
13277 } else if (HAS_DDI(dev) &&
13278 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13279 crtc->scanline_offset = 2;
13280 } else
13281 crtc->scanline_offset = 1;
13282 }
13283
13284 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13285 {
13286 struct drm_device *dev = state->dev;
13287 struct drm_i915_private *dev_priv = to_i915(dev);
13288 struct intel_shared_dpll_config *shared_dpll = NULL;
13289 struct drm_crtc *crtc;
13290 struct drm_crtc_state *crtc_state;
13291 int i;
13292
13293 if (!dev_priv->display.crtc_compute_clock)
13294 return;
13295
13296 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13298 struct intel_shared_dpll *old_dpll =
13299 to_intel_crtc_state(crtc->state)->shared_dpll;
13300
13301 if (!needs_modeset(crtc_state))
13302 continue;
13303
13304 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13305
13306 if (!old_dpll)
13307 continue;
13308
13309 if (!shared_dpll)
13310 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13311
13312 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13313 }
13314 }
13315
13316 /*
13317 * This implements the workaround described in the "notes" section of the mode
13318 * set sequence documentation. When going from no pipes or single pipe to
13319 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13320 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13321 */
13322 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13323 {
13324 struct drm_crtc_state *crtc_state;
13325 struct intel_crtc *intel_crtc;
13326 struct drm_crtc *crtc;
13327 struct intel_crtc_state *first_crtc_state = NULL;
13328 struct intel_crtc_state *other_crtc_state = NULL;
13329 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13330 int i;
13331
13332 /* look at all crtc's that are going to be enabled in during modeset */
13333 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13334 intel_crtc = to_intel_crtc(crtc);
13335
13336 if (!crtc_state->active || !needs_modeset(crtc_state))
13337 continue;
13338
13339 if (first_crtc_state) {
13340 other_crtc_state = to_intel_crtc_state(crtc_state);
13341 break;
13342 } else {
13343 first_crtc_state = to_intel_crtc_state(crtc_state);
13344 first_pipe = intel_crtc->pipe;
13345 }
13346 }
13347
13348 /* No workaround needed? */
13349 if (!first_crtc_state)
13350 return 0;
13351
13352 /* w/a possibly needed, check how many crtc's are already enabled. */
13353 for_each_intel_crtc(state->dev, intel_crtc) {
13354 struct intel_crtc_state *pipe_config;
13355
13356 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13357 if (IS_ERR(pipe_config))
13358 return PTR_ERR(pipe_config);
13359
13360 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13361
13362 if (!pipe_config->base.active ||
13363 needs_modeset(&pipe_config->base))
13364 continue;
13365
13366 /* 2 or more enabled crtcs means no need for w/a */
13367 if (enabled_pipe != INVALID_PIPE)
13368 return 0;
13369
13370 enabled_pipe = intel_crtc->pipe;
13371 }
13372
13373 if (enabled_pipe != INVALID_PIPE)
13374 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13375 else if (other_crtc_state)
13376 other_crtc_state->hsw_workaround_pipe = first_pipe;
13377
13378 return 0;
13379 }
13380
13381 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13382 {
13383 struct drm_crtc *crtc;
13384 struct drm_crtc_state *crtc_state;
13385 int ret = 0;
13386
13387 /* add all active pipes to the state */
13388 for_each_crtc(state->dev, crtc) {
13389 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13390 if (IS_ERR(crtc_state))
13391 return PTR_ERR(crtc_state);
13392
13393 if (!crtc_state->active || needs_modeset(crtc_state))
13394 continue;
13395
13396 crtc_state->mode_changed = true;
13397
13398 ret = drm_atomic_add_affected_connectors(state, crtc);
13399 if (ret)
13400 break;
13401
13402 ret = drm_atomic_add_affected_planes(state, crtc);
13403 if (ret)
13404 break;
13405 }
13406
13407 return ret;
13408 }
13409
13410 static int intel_modeset_checks(struct drm_atomic_state *state)
13411 {
13412 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13413 struct drm_i915_private *dev_priv = to_i915(state->dev);
13414 struct drm_crtc *crtc;
13415 struct drm_crtc_state *crtc_state;
13416 int ret = 0, i;
13417
13418 if (!check_digital_port_conflicts(state)) {
13419 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13420 return -EINVAL;
13421 }
13422
13423 intel_state->modeset = true;
13424 intel_state->active_crtcs = dev_priv->active_crtcs;
13425
13426 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13427 if (crtc_state->active)
13428 intel_state->active_crtcs |= 1 << i;
13429 else
13430 intel_state->active_crtcs &= ~(1 << i);
13431
13432 if (crtc_state->active != crtc->state->active)
13433 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13434 }
13435
13436 /*
13437 * See if the config requires any additional preparation, e.g.
13438 * to adjust global state with pipes off. We need to do this
13439 * here so we can get the modeset_pipe updated config for the new
13440 * mode set on this crtc. For other crtcs we need to use the
13441 * adjusted_mode bits in the crtc directly.
13442 */
13443 if (dev_priv->display.modeset_calc_cdclk) {
13444 if (!intel_state->cdclk_pll_vco)
13445 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13446 if (!intel_state->cdclk_pll_vco)
13447 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13448
13449 ret = dev_priv->display.modeset_calc_cdclk(state);
13450 if (ret < 0)
13451 return ret;
13452
13453 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13454 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13455 ret = intel_modeset_all_pipes(state);
13456
13457 if (ret < 0)
13458 return ret;
13459
13460 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13461 intel_state->cdclk, intel_state->dev_cdclk);
13462 } else
13463 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13464
13465 intel_modeset_clear_plls(state);
13466
13467 if (IS_HASWELL(dev_priv))
13468 return haswell_mode_set_planes_workaround(state);
13469
13470 return 0;
13471 }
13472
13473 /*
13474 * Handle calculation of various watermark data at the end of the atomic check
13475 * phase. The code here should be run after the per-crtc and per-plane 'check'
13476 * handlers to ensure that all derived state has been updated.
13477 */
13478 static int calc_watermark_data(struct drm_atomic_state *state)
13479 {
13480 struct drm_device *dev = state->dev;
13481 struct drm_i915_private *dev_priv = to_i915(dev);
13482
13483 /* Is there platform-specific watermark information to calculate? */
13484 if (dev_priv->display.compute_global_watermarks)
13485 return dev_priv->display.compute_global_watermarks(state);
13486
13487 return 0;
13488 }
13489
13490 /**
13491 * intel_atomic_check - validate state object
13492 * @dev: drm device
13493 * @state: state to validate
13494 */
13495 static int intel_atomic_check(struct drm_device *dev,
13496 struct drm_atomic_state *state)
13497 {
13498 struct drm_i915_private *dev_priv = to_i915(dev);
13499 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13500 struct drm_crtc *crtc;
13501 struct drm_crtc_state *crtc_state;
13502 int ret, i;
13503 bool any_ms = false;
13504
13505 ret = drm_atomic_helper_check_modeset(dev, state);
13506 if (ret)
13507 return ret;
13508
13509 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13510 struct intel_crtc_state *pipe_config =
13511 to_intel_crtc_state(crtc_state);
13512
13513 /* Catch I915_MODE_FLAG_INHERITED */
13514 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13515 crtc_state->mode_changed = true;
13516
13517 if (!needs_modeset(crtc_state))
13518 continue;
13519
13520 if (!crtc_state->enable) {
13521 any_ms = true;
13522 continue;
13523 }
13524
13525 /* FIXME: For only active_changed we shouldn't need to do any
13526 * state recomputation at all. */
13527
13528 ret = drm_atomic_add_affected_connectors(state, crtc);
13529 if (ret)
13530 return ret;
13531
13532 ret = intel_modeset_pipe_config(crtc, pipe_config);
13533 if (ret) {
13534 intel_dump_pipe_config(to_intel_crtc(crtc),
13535 pipe_config, "[failed]");
13536 return ret;
13537 }
13538
13539 if (i915.fastboot &&
13540 intel_pipe_config_compare(dev,
13541 to_intel_crtc_state(crtc->state),
13542 pipe_config, true)) {
13543 crtc_state->mode_changed = false;
13544 to_intel_crtc_state(crtc_state)->update_pipe = true;
13545 }
13546
13547 if (needs_modeset(crtc_state))
13548 any_ms = true;
13549
13550 ret = drm_atomic_add_affected_planes(state, crtc);
13551 if (ret)
13552 return ret;
13553
13554 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13555 needs_modeset(crtc_state) ?
13556 "[modeset]" : "[fastset]");
13557 }
13558
13559 if (any_ms) {
13560 ret = intel_modeset_checks(state);
13561
13562 if (ret)
13563 return ret;
13564 } else
13565 intel_state->cdclk = dev_priv->cdclk_freq;
13566
13567 ret = drm_atomic_helper_check_planes(dev, state);
13568 if (ret)
13569 return ret;
13570
13571 intel_fbc_choose_crtc(dev_priv, state);
13572 return calc_watermark_data(state);
13573 }
13574
13575 static int intel_atomic_prepare_commit(struct drm_device *dev,
13576 struct drm_atomic_state *state,
13577 bool nonblock)
13578 {
13579 struct drm_i915_private *dev_priv = to_i915(dev);
13580 struct drm_plane_state *plane_state;
13581 struct drm_crtc_state *crtc_state;
13582 struct drm_plane *plane;
13583 struct drm_crtc *crtc;
13584 int i, ret;
13585
13586 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13587 if (state->legacy_cursor_update)
13588 continue;
13589
13590 ret = intel_crtc_wait_for_pending_flips(crtc);
13591 if (ret)
13592 return ret;
13593
13594 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13595 flush_workqueue(dev_priv->wq);
13596 }
13597
13598 ret = mutex_lock_interruptible(&dev->struct_mutex);
13599 if (ret)
13600 return ret;
13601
13602 ret = drm_atomic_helper_prepare_planes(dev, state);
13603 mutex_unlock(&dev->struct_mutex);
13604
13605 if (!ret && !nonblock) {
13606 for_each_plane_in_state(state, plane, plane_state, i) {
13607 struct intel_plane_state *intel_plane_state =
13608 to_intel_plane_state(plane_state);
13609
13610 if (!intel_plane_state->wait_req)
13611 continue;
13612
13613 ret = __i915_wait_request(intel_plane_state->wait_req,
13614 true, NULL, NULL);
13615 if (ret) {
13616 /* Any hang should be swallowed by the wait */
13617 WARN_ON(ret == -EIO);
13618 mutex_lock(&dev->struct_mutex);
13619 drm_atomic_helper_cleanup_planes(dev, state);
13620 mutex_unlock(&dev->struct_mutex);
13621 break;
13622 }
13623 }
13624 }
13625
13626 return ret;
13627 }
13628
13629 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13630 {
13631 struct drm_device *dev = crtc->base.dev;
13632
13633 if (!dev->max_vblank_count)
13634 return drm_accurate_vblank_count(&crtc->base);
13635
13636 return dev->driver->get_vblank_counter(dev, crtc->pipe);
13637 }
13638
13639 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13640 struct drm_i915_private *dev_priv,
13641 unsigned crtc_mask)
13642 {
13643 unsigned last_vblank_count[I915_MAX_PIPES];
13644 enum pipe pipe;
13645 int ret;
13646
13647 if (!crtc_mask)
13648 return;
13649
13650 for_each_pipe(dev_priv, pipe) {
13651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13652
13653 if (!((1 << pipe) & crtc_mask))
13654 continue;
13655
13656 ret = drm_crtc_vblank_get(crtc);
13657 if (WARN_ON(ret != 0)) {
13658 crtc_mask &= ~(1 << pipe);
13659 continue;
13660 }
13661
13662 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13663 }
13664
13665 for_each_pipe(dev_priv, pipe) {
13666 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13667 long lret;
13668
13669 if (!((1 << pipe) & crtc_mask))
13670 continue;
13671
13672 lret = wait_event_timeout(dev->vblank[pipe].queue,
13673 last_vblank_count[pipe] !=
13674 drm_crtc_vblank_count(crtc),
13675 msecs_to_jiffies(50));
13676
13677 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13678
13679 drm_crtc_vblank_put(crtc);
13680 }
13681 }
13682
13683 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13684 {
13685 /* fb updated, need to unpin old fb */
13686 if (crtc_state->fb_changed)
13687 return true;
13688
13689 /* wm changes, need vblank before final wm's */
13690 if (crtc_state->update_wm_post)
13691 return true;
13692
13693 /*
13694 * cxsr is re-enabled after vblank.
13695 * This is already handled by crtc_state->update_wm_post,
13696 * but added for clarity.
13697 */
13698 if (crtc_state->disable_cxsr)
13699 return true;
13700
13701 return false;
13702 }
13703
13704 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13705 {
13706 struct drm_device *dev = state->dev;
13707 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13708 struct drm_i915_private *dev_priv = to_i915(dev);
13709 struct drm_crtc_state *old_crtc_state;
13710 struct drm_crtc *crtc;
13711 struct intel_crtc_state *intel_cstate;
13712 struct drm_plane *plane;
13713 struct drm_plane_state *plane_state;
13714 bool hw_check = intel_state->modeset;
13715 unsigned long put_domains[I915_MAX_PIPES] = {};
13716 unsigned crtc_vblank_mask = 0;
13717 int i, ret;
13718
13719 for_each_plane_in_state(state, plane, plane_state, i) {
13720 struct intel_plane_state *intel_plane_state =
13721 to_intel_plane_state(plane_state);
13722
13723 if (!intel_plane_state->wait_req)
13724 continue;
13725
13726 ret = __i915_wait_request(intel_plane_state->wait_req,
13727 true, NULL, NULL);
13728 /* EIO should be eaten, and we can't get interrupted in the
13729 * worker, and blocking commits have waited already. */
13730 WARN_ON(ret);
13731 }
13732
13733 drm_atomic_helper_wait_for_dependencies(state);
13734
13735 if (intel_state->modeset) {
13736 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13737 sizeof(intel_state->min_pixclk));
13738 dev_priv->active_crtcs = intel_state->active_crtcs;
13739 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13740
13741 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13742 }
13743
13744 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13746
13747 if (needs_modeset(crtc->state) ||
13748 to_intel_crtc_state(crtc->state)->update_pipe) {
13749 hw_check = true;
13750
13751 put_domains[to_intel_crtc(crtc)->pipe] =
13752 modeset_get_crtc_power_domains(crtc,
13753 to_intel_crtc_state(crtc->state));
13754 }
13755
13756 if (!needs_modeset(crtc->state))
13757 continue;
13758
13759 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13760
13761 if (old_crtc_state->active) {
13762 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13763 dev_priv->display.crtc_disable(crtc);
13764 intel_crtc->active = false;
13765 intel_fbc_disable(intel_crtc);
13766 intel_disable_shared_dpll(intel_crtc);
13767
13768 /*
13769 * Underruns don't always raise
13770 * interrupts, so check manually.
13771 */
13772 intel_check_cpu_fifo_underruns(dev_priv);
13773 intel_check_pch_fifo_underruns(dev_priv);
13774
13775 if (!crtc->state->active)
13776 intel_update_watermarks(crtc);
13777 }
13778 }
13779
13780 /* Only after disabling all output pipelines that will be changed can we
13781 * update the the output configuration. */
13782 intel_modeset_update_crtc_state(state);
13783
13784 if (intel_state->modeset) {
13785 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13786
13787 if (dev_priv->display.modeset_commit_cdclk &&
13788 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13789 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
13790 dev_priv->display.modeset_commit_cdclk(state);
13791
13792 intel_modeset_verify_disabled(dev);
13793 }
13794
13795 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13796 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13798 bool modeset = needs_modeset(crtc->state);
13799 struct intel_crtc_state *pipe_config =
13800 to_intel_crtc_state(crtc->state);
13801
13802 if (modeset && crtc->state->active) {
13803 update_scanline_offset(to_intel_crtc(crtc));
13804 dev_priv->display.crtc_enable(crtc);
13805 }
13806
13807 /* Complete events for now disable pipes here. */
13808 if (modeset && !crtc->state->active && crtc->state->event) {
13809 spin_lock_irq(&dev->event_lock);
13810 drm_crtc_send_vblank_event(crtc, crtc->state->event);
13811 spin_unlock_irq(&dev->event_lock);
13812
13813 crtc->state->event = NULL;
13814 }
13815
13816 if (!modeset)
13817 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13818
13819 if (crtc->state->active &&
13820 drm_atomic_get_existing_plane_state(state, crtc->primary))
13821 intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state));
13822
13823 if (crtc->state->active)
13824 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13825
13826 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13827 crtc_vblank_mask |= 1 << i;
13828 }
13829
13830 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13831 * already, but still need the state for the delayed optimization. To
13832 * fix this:
13833 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13834 * - schedule that vblank worker _before_ calling hw_done
13835 * - at the start of commit_tail, cancel it _synchrously
13836 * - switch over to the vblank wait helper in the core after that since
13837 * we don't need out special handling any more.
13838 */
13839 if (!state->legacy_cursor_update)
13840 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13841
13842 /*
13843 * Now that the vblank has passed, we can go ahead and program the
13844 * optimal watermarks on platforms that need two-step watermark
13845 * programming.
13846 *
13847 * TODO: Move this (and other cleanup) to an async worker eventually.
13848 */
13849 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13850 intel_cstate = to_intel_crtc_state(crtc->state);
13851
13852 if (dev_priv->display.optimize_watermarks)
13853 dev_priv->display.optimize_watermarks(intel_cstate);
13854 }
13855
13856 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13857 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13858
13859 if (put_domains[i])
13860 modeset_put_power_domains(dev_priv, put_domains[i]);
13861
13862 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13863 }
13864
13865 drm_atomic_helper_commit_hw_done(state);
13866
13867 if (intel_state->modeset)
13868 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13869
13870 mutex_lock(&dev->struct_mutex);
13871 drm_atomic_helper_cleanup_planes(dev, state);
13872 mutex_unlock(&dev->struct_mutex);
13873
13874 drm_atomic_helper_commit_cleanup_done(state);
13875
13876 drm_atomic_state_free(state);
13877
13878 /* As one of the primary mmio accessors, KMS has a high likelihood
13879 * of triggering bugs in unclaimed access. After we finish
13880 * modesetting, see if an error has been flagged, and if so
13881 * enable debugging for the next modeset - and hope we catch
13882 * the culprit.
13883 *
13884 * XXX note that we assume display power is on at this point.
13885 * This might hold true now but we need to add pm helper to check
13886 * unclaimed only when the hardware is on, as atomic commits
13887 * can happen also when the device is completely off.
13888 */
13889 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13890 }
13891
13892 static void intel_atomic_commit_work(struct work_struct *work)
13893 {
13894 struct drm_atomic_state *state = container_of(work,
13895 struct drm_atomic_state,
13896 commit_work);
13897 intel_atomic_commit_tail(state);
13898 }
13899
13900 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13901 {
13902 struct drm_plane_state *old_plane_state;
13903 struct drm_plane *plane;
13904 struct drm_i915_gem_object *obj, *old_obj;
13905 struct intel_plane *intel_plane;
13906 int i;
13907
13908 mutex_lock(&state->dev->struct_mutex);
13909 for_each_plane_in_state(state, plane, old_plane_state, i) {
13910 obj = intel_fb_obj(plane->state->fb);
13911 old_obj = intel_fb_obj(old_plane_state->fb);
13912 intel_plane = to_intel_plane(plane);
13913
13914 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13915 }
13916 mutex_unlock(&state->dev->struct_mutex);
13917 }
13918
13919 /**
13920 * intel_atomic_commit - commit validated state object
13921 * @dev: DRM device
13922 * @state: the top-level driver state object
13923 * @nonblock: nonblocking commit
13924 *
13925 * This function commits a top-level state object that has been validated
13926 * with drm_atomic_helper_check().
13927 *
13928 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13929 * nonblocking commits are only safe for pure plane updates. Everything else
13930 * should work though.
13931 *
13932 * RETURNS
13933 * Zero for success or -errno.
13934 */
13935 static int intel_atomic_commit(struct drm_device *dev,
13936 struct drm_atomic_state *state,
13937 bool nonblock)
13938 {
13939 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13940 struct drm_i915_private *dev_priv = to_i915(dev);
13941 int ret = 0;
13942
13943 if (intel_state->modeset && nonblock) {
13944 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
13945 return -EINVAL;
13946 }
13947
13948 ret = drm_atomic_helper_setup_commit(state, nonblock);
13949 if (ret)
13950 return ret;
13951
13952 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
13953
13954 ret = intel_atomic_prepare_commit(dev, state, nonblock);
13955 if (ret) {
13956 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13957 return ret;
13958 }
13959
13960 drm_atomic_helper_swap_state(state, true);
13961 dev_priv->wm.distrust_bios_wm = false;
13962 dev_priv->wm.skl_results = intel_state->wm_results;
13963 intel_shared_dpll_commit(state);
13964 intel_atomic_track_fbs(state);
13965
13966 if (nonblock)
13967 queue_work(system_unbound_wq, &state->commit_work);
13968 else
13969 intel_atomic_commit_tail(state);
13970
13971 return 0;
13972 }
13973
13974 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13975 {
13976 struct drm_device *dev = crtc->dev;
13977 struct drm_atomic_state *state;
13978 struct drm_crtc_state *crtc_state;
13979 int ret;
13980
13981 state = drm_atomic_state_alloc(dev);
13982 if (!state) {
13983 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13984 crtc->base.id, crtc->name);
13985 return;
13986 }
13987
13988 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13989
13990 retry:
13991 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13992 ret = PTR_ERR_OR_ZERO(crtc_state);
13993 if (!ret) {
13994 if (!crtc_state->active)
13995 goto out;
13996
13997 crtc_state->mode_changed = true;
13998 ret = drm_atomic_commit(state);
13999 }
14000
14001 if (ret == -EDEADLK) {
14002 drm_atomic_state_clear(state);
14003 drm_modeset_backoff(state->acquire_ctx);
14004 goto retry;
14005 }
14006
14007 if (ret)
14008 out:
14009 drm_atomic_state_free(state);
14010 }
14011
14012 #undef for_each_intel_crtc_masked
14013
14014 static const struct drm_crtc_funcs intel_crtc_funcs = {
14015 .gamma_set = drm_atomic_helper_legacy_gamma_set,
14016 .set_config = drm_atomic_helper_set_config,
14017 .set_property = drm_atomic_helper_crtc_set_property,
14018 .destroy = intel_crtc_destroy,
14019 .page_flip = intel_crtc_page_flip,
14020 .atomic_duplicate_state = intel_crtc_duplicate_state,
14021 .atomic_destroy_state = intel_crtc_destroy_state,
14022 };
14023
14024 /**
14025 * intel_prepare_plane_fb - Prepare fb for usage on plane
14026 * @plane: drm plane to prepare for
14027 * @fb: framebuffer to prepare for presentation
14028 *
14029 * Prepares a framebuffer for usage on a display plane. Generally this
14030 * involves pinning the underlying object and updating the frontbuffer tracking
14031 * bits. Some older platforms need special physical address handling for
14032 * cursor planes.
14033 *
14034 * Must be called with struct_mutex held.
14035 *
14036 * Returns 0 on success, negative error code on failure.
14037 */
14038 int
14039 intel_prepare_plane_fb(struct drm_plane *plane,
14040 const struct drm_plane_state *new_state)
14041 {
14042 struct drm_device *dev = plane->dev;
14043 struct drm_framebuffer *fb = new_state->fb;
14044 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14045 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14046 struct reservation_object *resv;
14047 int ret = 0;
14048
14049 if (!obj && !old_obj)
14050 return 0;
14051
14052 if (old_obj) {
14053 struct drm_crtc_state *crtc_state =
14054 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14055
14056 /* Big Hammer, we also need to ensure that any pending
14057 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14058 * current scanout is retired before unpinning the old
14059 * framebuffer. Note that we rely on userspace rendering
14060 * into the buffer attached to the pipe they are waiting
14061 * on. If not, userspace generates a GPU hang with IPEHR
14062 * point to the MI_WAIT_FOR_EVENT.
14063 *
14064 * This should only fail upon a hung GPU, in which case we
14065 * can safely continue.
14066 */
14067 if (needs_modeset(crtc_state))
14068 ret = i915_gem_object_wait_rendering(old_obj, true);
14069 if (ret) {
14070 /* GPU hangs should have been swallowed by the wait */
14071 WARN_ON(ret == -EIO);
14072 return ret;
14073 }
14074 }
14075
14076 if (!obj)
14077 return 0;
14078
14079 /* For framebuffer backed by dmabuf, wait for fence */
14080 resv = i915_gem_object_get_dmabuf_resv(obj);
14081 if (resv) {
14082 long lret;
14083
14084 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14085 MAX_SCHEDULE_TIMEOUT);
14086 if (lret == -ERESTARTSYS)
14087 return lret;
14088
14089 WARN(lret < 0, "waiting returns %li\n", lret);
14090 }
14091
14092 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14093 INTEL_INFO(dev)->cursor_needs_physical) {
14094 int align = IS_I830(dev) ? 16 * 1024 : 256;
14095 ret = i915_gem_object_attach_phys(obj, align);
14096 if (ret)
14097 DRM_DEBUG_KMS("failed to attach phys object\n");
14098 } else {
14099 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14100 }
14101
14102 if (ret == 0) {
14103 struct intel_plane_state *plane_state =
14104 to_intel_plane_state(new_state);
14105
14106 i915_gem_request_assign(&plane_state->wait_req,
14107 obj->last_write_req);
14108 }
14109
14110 return ret;
14111 }
14112
14113 /**
14114 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14115 * @plane: drm plane to clean up for
14116 * @fb: old framebuffer that was on plane
14117 *
14118 * Cleans up a framebuffer that has just been removed from a plane.
14119 *
14120 * Must be called with struct_mutex held.
14121 */
14122 void
14123 intel_cleanup_plane_fb(struct drm_plane *plane,
14124 const struct drm_plane_state *old_state)
14125 {
14126 struct drm_device *dev = plane->dev;
14127 struct intel_plane_state *old_intel_state;
14128 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14129 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14130
14131 old_intel_state = to_intel_plane_state(old_state);
14132
14133 if (!obj && !old_obj)
14134 return;
14135
14136 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14137 !INTEL_INFO(dev)->cursor_needs_physical))
14138 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14139
14140 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14141 }
14142
14143 int
14144 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14145 {
14146 int max_scale;
14147 struct drm_device *dev;
14148 struct drm_i915_private *dev_priv;
14149 int crtc_clock, cdclk;
14150
14151 if (!intel_crtc || !crtc_state->base.enable)
14152 return DRM_PLANE_HELPER_NO_SCALING;
14153
14154 dev = intel_crtc->base.dev;
14155 dev_priv = dev->dev_private;
14156 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14157 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14158
14159 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14160 return DRM_PLANE_HELPER_NO_SCALING;
14161
14162 /*
14163 * skl max scale is lower of:
14164 * close to 3 but not 3, -1 is for that purpose
14165 * or
14166 * cdclk/crtc_clock
14167 */
14168 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14169
14170 return max_scale;
14171 }
14172
14173 static int
14174 intel_check_primary_plane(struct drm_plane *plane,
14175 struct intel_crtc_state *crtc_state,
14176 struct intel_plane_state *state)
14177 {
14178 struct drm_crtc *crtc = state->base.crtc;
14179 struct drm_framebuffer *fb = state->base.fb;
14180 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14181 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14182 bool can_position = false;
14183
14184 if (INTEL_INFO(plane->dev)->gen >= 9) {
14185 /* use scaler when colorkey is not required */
14186 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14187 min_scale = 1;
14188 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14189 }
14190 can_position = true;
14191 }
14192
14193 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14194 &state->dst, &state->clip,
14195 state->base.rotation,
14196 min_scale, max_scale,
14197 can_position, true,
14198 &state->visible);
14199 }
14200
14201 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14202 struct drm_crtc_state *old_crtc_state)
14203 {
14204 struct drm_device *dev = crtc->dev;
14205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14206 struct intel_crtc_state *old_intel_state =
14207 to_intel_crtc_state(old_crtc_state);
14208 bool modeset = needs_modeset(crtc->state);
14209
14210 /* Perform vblank evasion around commit operation */
14211 intel_pipe_update_start(intel_crtc);
14212
14213 if (modeset)
14214 return;
14215
14216 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14217 intel_color_set_csc(crtc->state);
14218 intel_color_load_luts(crtc->state);
14219 }
14220
14221 if (to_intel_crtc_state(crtc->state)->update_pipe)
14222 intel_update_pipe_config(intel_crtc, old_intel_state);
14223 else if (INTEL_INFO(dev)->gen >= 9)
14224 skl_detach_scalers(intel_crtc);
14225 }
14226
14227 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14228 struct drm_crtc_state *old_crtc_state)
14229 {
14230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14231
14232 intel_pipe_update_end(intel_crtc, NULL);
14233 }
14234
14235 /**
14236 * intel_plane_destroy - destroy a plane
14237 * @plane: plane to destroy
14238 *
14239 * Common destruction function for all types of planes (primary, cursor,
14240 * sprite).
14241 */
14242 void intel_plane_destroy(struct drm_plane *plane)
14243 {
14244 if (!plane)
14245 return;
14246
14247 drm_plane_cleanup(plane);
14248 kfree(to_intel_plane(plane));
14249 }
14250
14251 const struct drm_plane_funcs intel_plane_funcs = {
14252 .update_plane = drm_atomic_helper_update_plane,
14253 .disable_plane = drm_atomic_helper_disable_plane,
14254 .destroy = intel_plane_destroy,
14255 .set_property = drm_atomic_helper_plane_set_property,
14256 .atomic_get_property = intel_plane_atomic_get_property,
14257 .atomic_set_property = intel_plane_atomic_set_property,
14258 .atomic_duplicate_state = intel_plane_duplicate_state,
14259 .atomic_destroy_state = intel_plane_destroy_state,
14260
14261 };
14262
14263 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14264 int pipe)
14265 {
14266 struct intel_plane *primary = NULL;
14267 struct intel_plane_state *state = NULL;
14268 const uint32_t *intel_primary_formats;
14269 unsigned int num_formats;
14270 int ret;
14271
14272 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14273 if (!primary)
14274 goto fail;
14275
14276 state = intel_create_plane_state(&primary->base);
14277 if (!state)
14278 goto fail;
14279 primary->base.state = &state->base;
14280
14281 primary->can_scale = false;
14282 primary->max_downscale = 1;
14283 if (INTEL_INFO(dev)->gen >= 9) {
14284 primary->can_scale = true;
14285 state->scaler_id = -1;
14286 }
14287 primary->pipe = pipe;
14288 primary->plane = pipe;
14289 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14290 primary->check_plane = intel_check_primary_plane;
14291 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14292 primary->plane = !pipe;
14293
14294 if (INTEL_INFO(dev)->gen >= 9) {
14295 intel_primary_formats = skl_primary_formats;
14296 num_formats = ARRAY_SIZE(skl_primary_formats);
14297
14298 primary->update_plane = skylake_update_primary_plane;
14299 primary->disable_plane = skylake_disable_primary_plane;
14300 } else if (HAS_PCH_SPLIT(dev)) {
14301 intel_primary_formats = i965_primary_formats;
14302 num_formats = ARRAY_SIZE(i965_primary_formats);
14303
14304 primary->update_plane = ironlake_update_primary_plane;
14305 primary->disable_plane = i9xx_disable_primary_plane;
14306 } else if (INTEL_INFO(dev)->gen >= 4) {
14307 intel_primary_formats = i965_primary_formats;
14308 num_formats = ARRAY_SIZE(i965_primary_formats);
14309
14310 primary->update_plane = i9xx_update_primary_plane;
14311 primary->disable_plane = i9xx_disable_primary_plane;
14312 } else {
14313 intel_primary_formats = i8xx_primary_formats;
14314 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14315
14316 primary->update_plane = i9xx_update_primary_plane;
14317 primary->disable_plane = i9xx_disable_primary_plane;
14318 }
14319
14320 if (INTEL_INFO(dev)->gen >= 9)
14321 ret = drm_universal_plane_init(dev, &primary->base, 0,
14322 &intel_plane_funcs,
14323 intel_primary_formats, num_formats,
14324 DRM_PLANE_TYPE_PRIMARY,
14325 "plane 1%c", pipe_name(pipe));
14326 else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14327 ret = drm_universal_plane_init(dev, &primary->base, 0,
14328 &intel_plane_funcs,
14329 intel_primary_formats, num_formats,
14330 DRM_PLANE_TYPE_PRIMARY,
14331 "primary %c", pipe_name(pipe));
14332 else
14333 ret = drm_universal_plane_init(dev, &primary->base, 0,
14334 &intel_plane_funcs,
14335 intel_primary_formats, num_formats,
14336 DRM_PLANE_TYPE_PRIMARY,
14337 "plane %c", plane_name(primary->plane));
14338 if (ret)
14339 goto fail;
14340
14341 if (INTEL_INFO(dev)->gen >= 4)
14342 intel_create_rotation_property(dev, primary);
14343
14344 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14345
14346 return &primary->base;
14347
14348 fail:
14349 kfree(state);
14350 kfree(primary);
14351
14352 return NULL;
14353 }
14354
14355 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14356 {
14357 if (!dev->mode_config.rotation_property) {
14358 unsigned long flags = BIT(DRM_ROTATE_0) |
14359 BIT(DRM_ROTATE_180);
14360
14361 if (INTEL_INFO(dev)->gen >= 9)
14362 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14363
14364 dev->mode_config.rotation_property =
14365 drm_mode_create_rotation_property(dev, flags);
14366 }
14367 if (dev->mode_config.rotation_property)
14368 drm_object_attach_property(&plane->base.base,
14369 dev->mode_config.rotation_property,
14370 plane->base.state->rotation);
14371 }
14372
14373 static int
14374 intel_check_cursor_plane(struct drm_plane *plane,
14375 struct intel_crtc_state *crtc_state,
14376 struct intel_plane_state *state)
14377 {
14378 struct drm_crtc *crtc = crtc_state->base.crtc;
14379 struct drm_framebuffer *fb = state->base.fb;
14380 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14381 enum pipe pipe = to_intel_plane(plane)->pipe;
14382 unsigned stride;
14383 int ret;
14384
14385 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14386 &state->dst, &state->clip,
14387 state->base.rotation,
14388 DRM_PLANE_HELPER_NO_SCALING,
14389 DRM_PLANE_HELPER_NO_SCALING,
14390 true, true, &state->visible);
14391 if (ret)
14392 return ret;
14393
14394 /* if we want to turn off the cursor ignore width and height */
14395 if (!obj)
14396 return 0;
14397
14398 /* Check for which cursor types we support */
14399 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14400 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14401 state->base.crtc_w, state->base.crtc_h);
14402 return -EINVAL;
14403 }
14404
14405 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14406 if (obj->base.size < stride * state->base.crtc_h) {
14407 DRM_DEBUG_KMS("buffer is too small\n");
14408 return -ENOMEM;
14409 }
14410
14411 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14412 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14413 return -EINVAL;
14414 }
14415
14416 /*
14417 * There's something wrong with the cursor on CHV pipe C.
14418 * If it straddles the left edge of the screen then
14419 * moving it away from the edge or disabling it often
14420 * results in a pipe underrun, and often that can lead to
14421 * dead pipe (constant underrun reported, and it scans
14422 * out just a solid color). To recover from that, the
14423 * display power well must be turned off and on again.
14424 * Refuse the put the cursor into that compromised position.
14425 */
14426 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14427 state->visible && state->base.crtc_x < 0) {
14428 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14429 return -EINVAL;
14430 }
14431
14432 return 0;
14433 }
14434
14435 static void
14436 intel_disable_cursor_plane(struct drm_plane *plane,
14437 struct drm_crtc *crtc)
14438 {
14439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14440
14441 intel_crtc->cursor_addr = 0;
14442 intel_crtc_update_cursor(crtc, NULL);
14443 }
14444
14445 static void
14446 intel_update_cursor_plane(struct drm_plane *plane,
14447 const struct intel_crtc_state *crtc_state,
14448 const struct intel_plane_state *state)
14449 {
14450 struct drm_crtc *crtc = crtc_state->base.crtc;
14451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14452 struct drm_device *dev = plane->dev;
14453 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14454 uint32_t addr;
14455
14456 if (!obj)
14457 addr = 0;
14458 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14459 addr = i915_gem_obj_ggtt_offset(obj);
14460 else
14461 addr = obj->phys_handle->busaddr;
14462
14463 intel_crtc->cursor_addr = addr;
14464 intel_crtc_update_cursor(crtc, state);
14465 }
14466
14467 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14468 int pipe)
14469 {
14470 struct intel_plane *cursor = NULL;
14471 struct intel_plane_state *state = NULL;
14472 int ret;
14473
14474 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14475 if (!cursor)
14476 goto fail;
14477
14478 state = intel_create_plane_state(&cursor->base);
14479 if (!state)
14480 goto fail;
14481 cursor->base.state = &state->base;
14482
14483 cursor->can_scale = false;
14484 cursor->max_downscale = 1;
14485 cursor->pipe = pipe;
14486 cursor->plane = pipe;
14487 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14488 cursor->check_plane = intel_check_cursor_plane;
14489 cursor->update_plane = intel_update_cursor_plane;
14490 cursor->disable_plane = intel_disable_cursor_plane;
14491
14492 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14493 &intel_plane_funcs,
14494 intel_cursor_formats,
14495 ARRAY_SIZE(intel_cursor_formats),
14496 DRM_PLANE_TYPE_CURSOR,
14497 "cursor %c", pipe_name(pipe));
14498 if (ret)
14499 goto fail;
14500
14501 if (INTEL_INFO(dev)->gen >= 4) {
14502 if (!dev->mode_config.rotation_property)
14503 dev->mode_config.rotation_property =
14504 drm_mode_create_rotation_property(dev,
14505 BIT(DRM_ROTATE_0) |
14506 BIT(DRM_ROTATE_180));
14507 if (dev->mode_config.rotation_property)
14508 drm_object_attach_property(&cursor->base.base,
14509 dev->mode_config.rotation_property,
14510 state->base.rotation);
14511 }
14512
14513 if (INTEL_INFO(dev)->gen >=9)
14514 state->scaler_id = -1;
14515
14516 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14517
14518 return &cursor->base;
14519
14520 fail:
14521 kfree(state);
14522 kfree(cursor);
14523
14524 return NULL;
14525 }
14526
14527 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14528 struct intel_crtc_state *crtc_state)
14529 {
14530 int i;
14531 struct intel_scaler *intel_scaler;
14532 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14533
14534 for (i = 0; i < intel_crtc->num_scalers; i++) {
14535 intel_scaler = &scaler_state->scalers[i];
14536 intel_scaler->in_use = 0;
14537 intel_scaler->mode = PS_SCALER_MODE_DYN;
14538 }
14539
14540 scaler_state->scaler_id = -1;
14541 }
14542
14543 static void intel_crtc_init(struct drm_device *dev, int pipe)
14544 {
14545 struct drm_i915_private *dev_priv = to_i915(dev);
14546 struct intel_crtc *intel_crtc;
14547 struct intel_crtc_state *crtc_state = NULL;
14548 struct drm_plane *primary = NULL;
14549 struct drm_plane *cursor = NULL;
14550 int ret;
14551
14552 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14553 if (intel_crtc == NULL)
14554 return;
14555
14556 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14557 if (!crtc_state)
14558 goto fail;
14559 intel_crtc->config = crtc_state;
14560 intel_crtc->base.state = &crtc_state->base;
14561 crtc_state->base.crtc = &intel_crtc->base;
14562
14563 /* initialize shared scalers */
14564 if (INTEL_INFO(dev)->gen >= 9) {
14565 if (pipe == PIPE_C)
14566 intel_crtc->num_scalers = 1;
14567 else
14568 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14569
14570 skl_init_scalers(dev, intel_crtc, crtc_state);
14571 }
14572
14573 primary = intel_primary_plane_create(dev, pipe);
14574 if (!primary)
14575 goto fail;
14576
14577 cursor = intel_cursor_plane_create(dev, pipe);
14578 if (!cursor)
14579 goto fail;
14580
14581 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14582 cursor, &intel_crtc_funcs,
14583 "pipe %c", pipe_name(pipe));
14584 if (ret)
14585 goto fail;
14586
14587 /*
14588 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14589 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14590 */
14591 intel_crtc->pipe = pipe;
14592 intel_crtc->plane = pipe;
14593 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14594 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14595 intel_crtc->plane = !pipe;
14596 }
14597
14598 intel_crtc->cursor_base = ~0;
14599 intel_crtc->cursor_cntl = ~0;
14600 intel_crtc->cursor_size = ~0;
14601
14602 intel_crtc->wm.cxsr_allowed = true;
14603
14604 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14605 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14606 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14607 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14608
14609 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14610
14611 intel_color_init(&intel_crtc->base);
14612
14613 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14614 return;
14615
14616 fail:
14617 intel_plane_destroy(primary);
14618 intel_plane_destroy(cursor);
14619 kfree(crtc_state);
14620 kfree(intel_crtc);
14621 }
14622
14623 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14624 {
14625 struct drm_encoder *encoder = connector->base.encoder;
14626 struct drm_device *dev = connector->base.dev;
14627
14628 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14629
14630 if (!encoder || WARN_ON(!encoder->crtc))
14631 return INVALID_PIPE;
14632
14633 return to_intel_crtc(encoder->crtc)->pipe;
14634 }
14635
14636 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14637 struct drm_file *file)
14638 {
14639 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14640 struct drm_crtc *drmmode_crtc;
14641 struct intel_crtc *crtc;
14642
14643 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14644 if (!drmmode_crtc)
14645 return -ENOENT;
14646
14647 crtc = to_intel_crtc(drmmode_crtc);
14648 pipe_from_crtc_id->pipe = crtc->pipe;
14649
14650 return 0;
14651 }
14652
14653 static int intel_encoder_clones(struct intel_encoder *encoder)
14654 {
14655 struct drm_device *dev = encoder->base.dev;
14656 struct intel_encoder *source_encoder;
14657 int index_mask = 0;
14658 int entry = 0;
14659
14660 for_each_intel_encoder(dev, source_encoder) {
14661 if (encoders_cloneable(encoder, source_encoder))
14662 index_mask |= (1 << entry);
14663
14664 entry++;
14665 }
14666
14667 return index_mask;
14668 }
14669
14670 static bool has_edp_a(struct drm_device *dev)
14671 {
14672 struct drm_i915_private *dev_priv = to_i915(dev);
14673
14674 if (!IS_MOBILE(dev))
14675 return false;
14676
14677 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14678 return false;
14679
14680 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14681 return false;
14682
14683 return true;
14684 }
14685
14686 static bool intel_crt_present(struct drm_device *dev)
14687 {
14688 struct drm_i915_private *dev_priv = to_i915(dev);
14689
14690 if (INTEL_INFO(dev)->gen >= 9)
14691 return false;
14692
14693 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14694 return false;
14695
14696 if (IS_CHERRYVIEW(dev))
14697 return false;
14698
14699 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14700 return false;
14701
14702 /* DDI E can't be used if DDI A requires 4 lanes */
14703 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14704 return false;
14705
14706 if (!dev_priv->vbt.int_crt_support)
14707 return false;
14708
14709 return true;
14710 }
14711
14712 static void intel_setup_outputs(struct drm_device *dev)
14713 {
14714 struct drm_i915_private *dev_priv = to_i915(dev);
14715 struct intel_encoder *encoder;
14716 bool dpd_is_edp = false;
14717
14718 /*
14719 * intel_edp_init_connector() depends on this completing first, to
14720 * prevent the registeration of both eDP and LVDS and the incorrect
14721 * sharing of the PPS.
14722 */
14723 intel_lvds_init(dev);
14724
14725 if (intel_crt_present(dev))
14726 intel_crt_init(dev);
14727
14728 if (IS_BROXTON(dev)) {
14729 /*
14730 * FIXME: Broxton doesn't support port detection via the
14731 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14732 * detect the ports.
14733 */
14734 intel_ddi_init(dev, PORT_A);
14735 intel_ddi_init(dev, PORT_B);
14736 intel_ddi_init(dev, PORT_C);
14737
14738 intel_dsi_init(dev);
14739 } else if (HAS_DDI(dev)) {
14740 int found;
14741
14742 /*
14743 * Haswell uses DDI functions to detect digital outputs.
14744 * On SKL pre-D0 the strap isn't connected, so we assume
14745 * it's there.
14746 */
14747 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14748 /* WaIgnoreDDIAStrap: skl */
14749 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14750 intel_ddi_init(dev, PORT_A);
14751
14752 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14753 * register */
14754 found = I915_READ(SFUSE_STRAP);
14755
14756 if (found & SFUSE_STRAP_DDIB_DETECTED)
14757 intel_ddi_init(dev, PORT_B);
14758 if (found & SFUSE_STRAP_DDIC_DETECTED)
14759 intel_ddi_init(dev, PORT_C);
14760 if (found & SFUSE_STRAP_DDID_DETECTED)
14761 intel_ddi_init(dev, PORT_D);
14762 /*
14763 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14764 */
14765 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14766 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14767 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14768 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14769 intel_ddi_init(dev, PORT_E);
14770
14771 } else if (HAS_PCH_SPLIT(dev)) {
14772 int found;
14773 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14774
14775 if (has_edp_a(dev))
14776 intel_dp_init(dev, DP_A, PORT_A);
14777
14778 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14779 /* PCH SDVOB multiplex with HDMIB */
14780 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14781 if (!found)
14782 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14783 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14784 intel_dp_init(dev, PCH_DP_B, PORT_B);
14785 }
14786
14787 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14788 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14789
14790 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14791 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14792
14793 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14794 intel_dp_init(dev, PCH_DP_C, PORT_C);
14795
14796 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14797 intel_dp_init(dev, PCH_DP_D, PORT_D);
14798 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14799 bool has_edp, has_port;
14800
14801 /*
14802 * The DP_DETECTED bit is the latched state of the DDC
14803 * SDA pin at boot. However since eDP doesn't require DDC
14804 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14805 * eDP ports may have been muxed to an alternate function.
14806 * Thus we can't rely on the DP_DETECTED bit alone to detect
14807 * eDP ports. Consult the VBT as well as DP_DETECTED to
14808 * detect eDP ports.
14809 *
14810 * Sadly the straps seem to be missing sometimes even for HDMI
14811 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14812 * and VBT for the presence of the port. Additionally we can't
14813 * trust the port type the VBT declares as we've seen at least
14814 * HDMI ports that the VBT claim are DP or eDP.
14815 */
14816 has_edp = intel_dp_is_edp(dev, PORT_B);
14817 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14818 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14819 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
14820 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14821 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14822
14823 has_edp = intel_dp_is_edp(dev, PORT_C);
14824 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14825 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14826 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
14827 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14828 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14829
14830 if (IS_CHERRYVIEW(dev)) {
14831 /*
14832 * eDP not supported on port D,
14833 * so no need to worry about it
14834 */
14835 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14836 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14837 intel_dp_init(dev, CHV_DP_D, PORT_D);
14838 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14839 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14840 }
14841
14842 intel_dsi_init(dev);
14843 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14844 bool found = false;
14845
14846 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14847 DRM_DEBUG_KMS("probing SDVOB\n");
14848 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14849 if (!found && IS_G4X(dev)) {
14850 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14851 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14852 }
14853
14854 if (!found && IS_G4X(dev))
14855 intel_dp_init(dev, DP_B, PORT_B);
14856 }
14857
14858 /* Before G4X SDVOC doesn't have its own detect register */
14859
14860 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14861 DRM_DEBUG_KMS("probing SDVOC\n");
14862 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14863 }
14864
14865 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14866
14867 if (IS_G4X(dev)) {
14868 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14869 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14870 }
14871 if (IS_G4X(dev))
14872 intel_dp_init(dev, DP_C, PORT_C);
14873 }
14874
14875 if (IS_G4X(dev) &&
14876 (I915_READ(DP_D) & DP_DETECTED))
14877 intel_dp_init(dev, DP_D, PORT_D);
14878 } else if (IS_GEN2(dev))
14879 intel_dvo_init(dev);
14880
14881 if (SUPPORTS_TV(dev))
14882 intel_tv_init(dev);
14883
14884 intel_psr_init(dev);
14885
14886 for_each_intel_encoder(dev, encoder) {
14887 encoder->base.possible_crtcs = encoder->crtc_mask;
14888 encoder->base.possible_clones =
14889 intel_encoder_clones(encoder);
14890 }
14891
14892 intel_init_pch_refclk(dev);
14893
14894 drm_helper_move_panel_connectors_to_head(dev);
14895 }
14896
14897 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14898 {
14899 struct drm_device *dev = fb->dev;
14900 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14901
14902 drm_framebuffer_cleanup(fb);
14903 mutex_lock(&dev->struct_mutex);
14904 WARN_ON(!intel_fb->obj->framebuffer_references--);
14905 drm_gem_object_unreference(&intel_fb->obj->base);
14906 mutex_unlock(&dev->struct_mutex);
14907 kfree(intel_fb);
14908 }
14909
14910 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14911 struct drm_file *file,
14912 unsigned int *handle)
14913 {
14914 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14915 struct drm_i915_gem_object *obj = intel_fb->obj;
14916
14917 if (obj->userptr.mm) {
14918 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14919 return -EINVAL;
14920 }
14921
14922 return drm_gem_handle_create(file, &obj->base, handle);
14923 }
14924
14925 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14926 struct drm_file *file,
14927 unsigned flags, unsigned color,
14928 struct drm_clip_rect *clips,
14929 unsigned num_clips)
14930 {
14931 struct drm_device *dev = fb->dev;
14932 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14933 struct drm_i915_gem_object *obj = intel_fb->obj;
14934
14935 mutex_lock(&dev->struct_mutex);
14936 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14937 mutex_unlock(&dev->struct_mutex);
14938
14939 return 0;
14940 }
14941
14942 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14943 .destroy = intel_user_framebuffer_destroy,
14944 .create_handle = intel_user_framebuffer_create_handle,
14945 .dirty = intel_user_framebuffer_dirty,
14946 };
14947
14948 static
14949 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14950 uint32_t pixel_format)
14951 {
14952 u32 gen = INTEL_INFO(dev)->gen;
14953
14954 if (gen >= 9) {
14955 int cpp = drm_format_plane_cpp(pixel_format, 0);
14956
14957 /* "The stride in bytes must not exceed the of the size of 8K
14958 * pixels and 32K bytes."
14959 */
14960 return min(8192 * cpp, 32768);
14961 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14962 return 32*1024;
14963 } else if (gen >= 4) {
14964 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14965 return 16*1024;
14966 else
14967 return 32*1024;
14968 } else if (gen >= 3) {
14969 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14970 return 8*1024;
14971 else
14972 return 16*1024;
14973 } else {
14974 /* XXX DSPC is limited to 4k tiled */
14975 return 8*1024;
14976 }
14977 }
14978
14979 static int intel_framebuffer_init(struct drm_device *dev,
14980 struct intel_framebuffer *intel_fb,
14981 struct drm_mode_fb_cmd2 *mode_cmd,
14982 struct drm_i915_gem_object *obj)
14983 {
14984 struct drm_i915_private *dev_priv = to_i915(dev);
14985 unsigned int aligned_height;
14986 int ret;
14987 u32 pitch_limit, stride_alignment;
14988
14989 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14990
14991 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14992 /* Enforce that fb modifier and tiling mode match, but only for
14993 * X-tiled. This is needed for FBC. */
14994 if (!!(obj->tiling_mode == I915_TILING_X) !=
14995 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14996 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14997 return -EINVAL;
14998 }
14999 } else {
15000 if (obj->tiling_mode == I915_TILING_X)
15001 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15002 else if (obj->tiling_mode == I915_TILING_Y) {
15003 DRM_DEBUG("No Y tiling for legacy addfb\n");
15004 return -EINVAL;
15005 }
15006 }
15007
15008 /* Passed in modifier sanity checking. */
15009 switch (mode_cmd->modifier[0]) {
15010 case I915_FORMAT_MOD_Y_TILED:
15011 case I915_FORMAT_MOD_Yf_TILED:
15012 if (INTEL_INFO(dev)->gen < 9) {
15013 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15014 mode_cmd->modifier[0]);
15015 return -EINVAL;
15016 }
15017 case DRM_FORMAT_MOD_NONE:
15018 case I915_FORMAT_MOD_X_TILED:
15019 break;
15020 default:
15021 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15022 mode_cmd->modifier[0]);
15023 return -EINVAL;
15024 }
15025
15026 stride_alignment = intel_fb_stride_alignment(dev_priv,
15027 mode_cmd->modifier[0],
15028 mode_cmd->pixel_format);
15029 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15030 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15031 mode_cmd->pitches[0], stride_alignment);
15032 return -EINVAL;
15033 }
15034
15035 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15036 mode_cmd->pixel_format);
15037 if (mode_cmd->pitches[0] > pitch_limit) {
15038 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15039 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15040 "tiled" : "linear",
15041 mode_cmd->pitches[0], pitch_limit);
15042 return -EINVAL;
15043 }
15044
15045 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
15046 mode_cmd->pitches[0] != obj->stride) {
15047 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15048 mode_cmd->pitches[0], obj->stride);
15049 return -EINVAL;
15050 }
15051
15052 /* Reject formats not supported by any plane early. */
15053 switch (mode_cmd->pixel_format) {
15054 case DRM_FORMAT_C8:
15055 case DRM_FORMAT_RGB565:
15056 case DRM_FORMAT_XRGB8888:
15057 case DRM_FORMAT_ARGB8888:
15058 break;
15059 case DRM_FORMAT_XRGB1555:
15060 if (INTEL_INFO(dev)->gen > 3) {
15061 DRM_DEBUG("unsupported pixel format: %s\n",
15062 drm_get_format_name(mode_cmd->pixel_format));
15063 return -EINVAL;
15064 }
15065 break;
15066 case DRM_FORMAT_ABGR8888:
15067 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15068 INTEL_INFO(dev)->gen < 9) {
15069 DRM_DEBUG("unsupported pixel format: %s\n",
15070 drm_get_format_name(mode_cmd->pixel_format));
15071 return -EINVAL;
15072 }
15073 break;
15074 case DRM_FORMAT_XBGR8888:
15075 case DRM_FORMAT_XRGB2101010:
15076 case DRM_FORMAT_XBGR2101010:
15077 if (INTEL_INFO(dev)->gen < 4) {
15078 DRM_DEBUG("unsupported pixel format: %s\n",
15079 drm_get_format_name(mode_cmd->pixel_format));
15080 return -EINVAL;
15081 }
15082 break;
15083 case DRM_FORMAT_ABGR2101010:
15084 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15085 DRM_DEBUG("unsupported pixel format: %s\n",
15086 drm_get_format_name(mode_cmd->pixel_format));
15087 return -EINVAL;
15088 }
15089 break;
15090 case DRM_FORMAT_YUYV:
15091 case DRM_FORMAT_UYVY:
15092 case DRM_FORMAT_YVYU:
15093 case DRM_FORMAT_VYUY:
15094 if (INTEL_INFO(dev)->gen < 5) {
15095 DRM_DEBUG("unsupported pixel format: %s\n",
15096 drm_get_format_name(mode_cmd->pixel_format));
15097 return -EINVAL;
15098 }
15099 break;
15100 default:
15101 DRM_DEBUG("unsupported pixel format: %s\n",
15102 drm_get_format_name(mode_cmd->pixel_format));
15103 return -EINVAL;
15104 }
15105
15106 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15107 if (mode_cmd->offsets[0] != 0)
15108 return -EINVAL;
15109
15110 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
15111 mode_cmd->pixel_format,
15112 mode_cmd->modifier[0]);
15113 /* FIXME drm helper for size checks (especially planar formats)? */
15114 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
15115 return -EINVAL;
15116
15117 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15118 intel_fb->obj = obj;
15119
15120 intel_fill_fb_info(dev_priv, &intel_fb->base);
15121
15122 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15123 if (ret) {
15124 DRM_ERROR("framebuffer init failed %d\n", ret);
15125 return ret;
15126 }
15127
15128 intel_fb->obj->framebuffer_references++;
15129
15130 return 0;
15131 }
15132
15133 static struct drm_framebuffer *
15134 intel_user_framebuffer_create(struct drm_device *dev,
15135 struct drm_file *filp,
15136 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15137 {
15138 struct drm_framebuffer *fb;
15139 struct drm_i915_gem_object *obj;
15140 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15141
15142 obj = to_intel_bo(drm_gem_object_lookup(filp, mode_cmd.handles[0]));
15143 if (&obj->base == NULL)
15144 return ERR_PTR(-ENOENT);
15145
15146 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15147 if (IS_ERR(fb))
15148 drm_gem_object_unreference_unlocked(&obj->base);
15149
15150 return fb;
15151 }
15152
15153 #ifndef CONFIG_DRM_FBDEV_EMULATION
15154 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15155 {
15156 }
15157 #endif
15158
15159 static const struct drm_mode_config_funcs intel_mode_funcs = {
15160 .fb_create = intel_user_framebuffer_create,
15161 .output_poll_changed = intel_fbdev_output_poll_changed,
15162 .atomic_check = intel_atomic_check,
15163 .atomic_commit = intel_atomic_commit,
15164 .atomic_state_alloc = intel_atomic_state_alloc,
15165 .atomic_state_clear = intel_atomic_state_clear,
15166 };
15167
15168 /**
15169 * intel_init_display_hooks - initialize the display modesetting hooks
15170 * @dev_priv: device private
15171 */
15172 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15173 {
15174 if (INTEL_INFO(dev_priv)->gen >= 9) {
15175 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15176 dev_priv->display.get_initial_plane_config =
15177 skylake_get_initial_plane_config;
15178 dev_priv->display.crtc_compute_clock =
15179 haswell_crtc_compute_clock;
15180 dev_priv->display.crtc_enable = haswell_crtc_enable;
15181 dev_priv->display.crtc_disable = haswell_crtc_disable;
15182 } else if (HAS_DDI(dev_priv)) {
15183 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15184 dev_priv->display.get_initial_plane_config =
15185 ironlake_get_initial_plane_config;
15186 dev_priv->display.crtc_compute_clock =
15187 haswell_crtc_compute_clock;
15188 dev_priv->display.crtc_enable = haswell_crtc_enable;
15189 dev_priv->display.crtc_disable = haswell_crtc_disable;
15190 } else if (HAS_PCH_SPLIT(dev_priv)) {
15191 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15192 dev_priv->display.get_initial_plane_config =
15193 ironlake_get_initial_plane_config;
15194 dev_priv->display.crtc_compute_clock =
15195 ironlake_crtc_compute_clock;
15196 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15197 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15198 } else if (IS_CHERRYVIEW(dev_priv)) {
15199 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15200 dev_priv->display.get_initial_plane_config =
15201 i9xx_get_initial_plane_config;
15202 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15203 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15204 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15205 } else if (IS_VALLEYVIEW(dev_priv)) {
15206 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15207 dev_priv->display.get_initial_plane_config =
15208 i9xx_get_initial_plane_config;
15209 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15210 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15211 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15212 } else if (IS_G4X(dev_priv)) {
15213 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15214 dev_priv->display.get_initial_plane_config =
15215 i9xx_get_initial_plane_config;
15216 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15217 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15218 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15219 } else if (IS_PINEVIEW(dev_priv)) {
15220 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15221 dev_priv->display.get_initial_plane_config =
15222 i9xx_get_initial_plane_config;
15223 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15224 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15225 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15226 } else if (!IS_GEN2(dev_priv)) {
15227 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15228 dev_priv->display.get_initial_plane_config =
15229 i9xx_get_initial_plane_config;
15230 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15231 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15232 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15233 } else {
15234 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15235 dev_priv->display.get_initial_plane_config =
15236 i9xx_get_initial_plane_config;
15237 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15238 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15239 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15240 }
15241
15242 /* Returns the core display clock speed */
15243 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15244 dev_priv->display.get_display_clock_speed =
15245 skylake_get_display_clock_speed;
15246 else if (IS_BROXTON(dev_priv))
15247 dev_priv->display.get_display_clock_speed =
15248 broxton_get_display_clock_speed;
15249 else if (IS_BROADWELL(dev_priv))
15250 dev_priv->display.get_display_clock_speed =
15251 broadwell_get_display_clock_speed;
15252 else if (IS_HASWELL(dev_priv))
15253 dev_priv->display.get_display_clock_speed =
15254 haswell_get_display_clock_speed;
15255 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15256 dev_priv->display.get_display_clock_speed =
15257 valleyview_get_display_clock_speed;
15258 else if (IS_GEN5(dev_priv))
15259 dev_priv->display.get_display_clock_speed =
15260 ilk_get_display_clock_speed;
15261 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15262 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15263 dev_priv->display.get_display_clock_speed =
15264 i945_get_display_clock_speed;
15265 else if (IS_GM45(dev_priv))
15266 dev_priv->display.get_display_clock_speed =
15267 gm45_get_display_clock_speed;
15268 else if (IS_CRESTLINE(dev_priv))
15269 dev_priv->display.get_display_clock_speed =
15270 i965gm_get_display_clock_speed;
15271 else if (IS_PINEVIEW(dev_priv))
15272 dev_priv->display.get_display_clock_speed =
15273 pnv_get_display_clock_speed;
15274 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15275 dev_priv->display.get_display_clock_speed =
15276 g33_get_display_clock_speed;
15277 else if (IS_I915G(dev_priv))
15278 dev_priv->display.get_display_clock_speed =
15279 i915_get_display_clock_speed;
15280 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15281 dev_priv->display.get_display_clock_speed =
15282 i9xx_misc_get_display_clock_speed;
15283 else if (IS_I915GM(dev_priv))
15284 dev_priv->display.get_display_clock_speed =
15285 i915gm_get_display_clock_speed;
15286 else if (IS_I865G(dev_priv))
15287 dev_priv->display.get_display_clock_speed =
15288 i865_get_display_clock_speed;
15289 else if (IS_I85X(dev_priv))
15290 dev_priv->display.get_display_clock_speed =
15291 i85x_get_display_clock_speed;
15292 else { /* 830 */
15293 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15294 dev_priv->display.get_display_clock_speed =
15295 i830_get_display_clock_speed;
15296 }
15297
15298 if (IS_GEN5(dev_priv)) {
15299 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15300 } else if (IS_GEN6(dev_priv)) {
15301 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15302 } else if (IS_IVYBRIDGE(dev_priv)) {
15303 /* FIXME: detect B0+ stepping and use auto training */
15304 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15305 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15306 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15307 }
15308
15309 if (IS_BROADWELL(dev_priv)) {
15310 dev_priv->display.modeset_commit_cdclk =
15311 broadwell_modeset_commit_cdclk;
15312 dev_priv->display.modeset_calc_cdclk =
15313 broadwell_modeset_calc_cdclk;
15314 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15315 dev_priv->display.modeset_commit_cdclk =
15316 valleyview_modeset_commit_cdclk;
15317 dev_priv->display.modeset_calc_cdclk =
15318 valleyview_modeset_calc_cdclk;
15319 } else if (IS_BROXTON(dev_priv)) {
15320 dev_priv->display.modeset_commit_cdclk =
15321 bxt_modeset_commit_cdclk;
15322 dev_priv->display.modeset_calc_cdclk =
15323 bxt_modeset_calc_cdclk;
15324 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15325 dev_priv->display.modeset_commit_cdclk =
15326 skl_modeset_commit_cdclk;
15327 dev_priv->display.modeset_calc_cdclk =
15328 skl_modeset_calc_cdclk;
15329 }
15330
15331 switch (INTEL_INFO(dev_priv)->gen) {
15332 case 2:
15333 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15334 break;
15335
15336 case 3:
15337 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15338 break;
15339
15340 case 4:
15341 case 5:
15342 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15343 break;
15344
15345 case 6:
15346 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15347 break;
15348 case 7:
15349 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15350 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15351 break;
15352 case 9:
15353 /* Drop through - unsupported since execlist only. */
15354 default:
15355 /* Default just returns -ENODEV to indicate unsupported */
15356 dev_priv->display.queue_flip = intel_default_queue_flip;
15357 }
15358 }
15359
15360 /*
15361 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15362 * resume, or other times. This quirk makes sure that's the case for
15363 * affected systems.
15364 */
15365 static void quirk_pipea_force(struct drm_device *dev)
15366 {
15367 struct drm_i915_private *dev_priv = to_i915(dev);
15368
15369 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15370 DRM_INFO("applying pipe a force quirk\n");
15371 }
15372
15373 static void quirk_pipeb_force(struct drm_device *dev)
15374 {
15375 struct drm_i915_private *dev_priv = to_i915(dev);
15376
15377 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15378 DRM_INFO("applying pipe b force quirk\n");
15379 }
15380
15381 /*
15382 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15383 */
15384 static void quirk_ssc_force_disable(struct drm_device *dev)
15385 {
15386 struct drm_i915_private *dev_priv = to_i915(dev);
15387 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15388 DRM_INFO("applying lvds SSC disable quirk\n");
15389 }
15390
15391 /*
15392 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15393 * brightness value
15394 */
15395 static void quirk_invert_brightness(struct drm_device *dev)
15396 {
15397 struct drm_i915_private *dev_priv = to_i915(dev);
15398 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15399 DRM_INFO("applying inverted panel brightness quirk\n");
15400 }
15401
15402 /* Some VBT's incorrectly indicate no backlight is present */
15403 static void quirk_backlight_present(struct drm_device *dev)
15404 {
15405 struct drm_i915_private *dev_priv = to_i915(dev);
15406 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15407 DRM_INFO("applying backlight present quirk\n");
15408 }
15409
15410 struct intel_quirk {
15411 int device;
15412 int subsystem_vendor;
15413 int subsystem_device;
15414 void (*hook)(struct drm_device *dev);
15415 };
15416
15417 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15418 struct intel_dmi_quirk {
15419 void (*hook)(struct drm_device *dev);
15420 const struct dmi_system_id (*dmi_id_list)[];
15421 };
15422
15423 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15424 {
15425 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15426 return 1;
15427 }
15428
15429 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15430 {
15431 .dmi_id_list = &(const struct dmi_system_id[]) {
15432 {
15433 .callback = intel_dmi_reverse_brightness,
15434 .ident = "NCR Corporation",
15435 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15436 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15437 },
15438 },
15439 { } /* terminating entry */
15440 },
15441 .hook = quirk_invert_brightness,
15442 },
15443 };
15444
15445 static struct intel_quirk intel_quirks[] = {
15446 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15447 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15448
15449 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15450 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15451
15452 /* 830 needs to leave pipe A & dpll A up */
15453 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15454
15455 /* 830 needs to leave pipe B & dpll B up */
15456 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15457
15458 /* Lenovo U160 cannot use SSC on LVDS */
15459 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15460
15461 /* Sony Vaio Y cannot use SSC on LVDS */
15462 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15463
15464 /* Acer Aspire 5734Z must invert backlight brightness */
15465 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15466
15467 /* Acer/eMachines G725 */
15468 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15469
15470 /* Acer/eMachines e725 */
15471 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15472
15473 /* Acer/Packard Bell NCL20 */
15474 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15475
15476 /* Acer Aspire 4736Z */
15477 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15478
15479 /* Acer Aspire 5336 */
15480 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15481
15482 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15483 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15484
15485 /* Acer C720 Chromebook (Core i3 4005U) */
15486 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15487
15488 /* Apple Macbook 2,1 (Core 2 T7400) */
15489 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15490
15491 /* Apple Macbook 4,1 */
15492 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15493
15494 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15495 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15496
15497 /* HP Chromebook 14 (Celeron 2955U) */
15498 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15499
15500 /* Dell Chromebook 11 */
15501 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15502
15503 /* Dell Chromebook 11 (2015 version) */
15504 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15505 };
15506
15507 static void intel_init_quirks(struct drm_device *dev)
15508 {
15509 struct pci_dev *d = dev->pdev;
15510 int i;
15511
15512 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15513 struct intel_quirk *q = &intel_quirks[i];
15514
15515 if (d->device == q->device &&
15516 (d->subsystem_vendor == q->subsystem_vendor ||
15517 q->subsystem_vendor == PCI_ANY_ID) &&
15518 (d->subsystem_device == q->subsystem_device ||
15519 q->subsystem_device == PCI_ANY_ID))
15520 q->hook(dev);
15521 }
15522 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15523 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15524 intel_dmi_quirks[i].hook(dev);
15525 }
15526 }
15527
15528 /* Disable the VGA plane that we never use */
15529 static void i915_disable_vga(struct drm_device *dev)
15530 {
15531 struct drm_i915_private *dev_priv = to_i915(dev);
15532 u8 sr1;
15533 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15534
15535 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15536 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15537 outb(SR01, VGA_SR_INDEX);
15538 sr1 = inb(VGA_SR_DATA);
15539 outb(sr1 | 1<<5, VGA_SR_DATA);
15540 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15541 udelay(300);
15542
15543 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15544 POSTING_READ(vga_reg);
15545 }
15546
15547 void intel_modeset_init_hw(struct drm_device *dev)
15548 {
15549 struct drm_i915_private *dev_priv = to_i915(dev);
15550
15551 intel_update_cdclk(dev);
15552
15553 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15554
15555 intel_init_clock_gating(dev);
15556 intel_enable_gt_powersave(dev_priv);
15557 }
15558
15559 /*
15560 * Calculate what we think the watermarks should be for the state we've read
15561 * out of the hardware and then immediately program those watermarks so that
15562 * we ensure the hardware settings match our internal state.
15563 *
15564 * We can calculate what we think WM's should be by creating a duplicate of the
15565 * current state (which was constructed during hardware readout) and running it
15566 * through the atomic check code to calculate new watermark values in the
15567 * state object.
15568 */
15569 static void sanitize_watermarks(struct drm_device *dev)
15570 {
15571 struct drm_i915_private *dev_priv = to_i915(dev);
15572 struct drm_atomic_state *state;
15573 struct drm_crtc *crtc;
15574 struct drm_crtc_state *cstate;
15575 struct drm_modeset_acquire_ctx ctx;
15576 int ret;
15577 int i;
15578
15579 /* Only supported on platforms that use atomic watermark design */
15580 if (!dev_priv->display.optimize_watermarks)
15581 return;
15582
15583 /*
15584 * We need to hold connection_mutex before calling duplicate_state so
15585 * that the connector loop is protected.
15586 */
15587 drm_modeset_acquire_init(&ctx, 0);
15588 retry:
15589 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15590 if (ret == -EDEADLK) {
15591 drm_modeset_backoff(&ctx);
15592 goto retry;
15593 } else if (WARN_ON(ret)) {
15594 goto fail;
15595 }
15596
15597 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15598 if (WARN_ON(IS_ERR(state)))
15599 goto fail;
15600
15601 /*
15602 * Hardware readout is the only time we don't want to calculate
15603 * intermediate watermarks (since we don't trust the current
15604 * watermarks).
15605 */
15606 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15607
15608 ret = intel_atomic_check(dev, state);
15609 if (ret) {
15610 /*
15611 * If we fail here, it means that the hardware appears to be
15612 * programmed in a way that shouldn't be possible, given our
15613 * understanding of watermark requirements. This might mean a
15614 * mistake in the hardware readout code or a mistake in the
15615 * watermark calculations for a given platform. Raise a WARN
15616 * so that this is noticeable.
15617 *
15618 * If this actually happens, we'll have to just leave the
15619 * BIOS-programmed watermarks untouched and hope for the best.
15620 */
15621 WARN(true, "Could not determine valid watermarks for inherited state\n");
15622 goto fail;
15623 }
15624
15625 /* Write calculated watermark values back */
15626 for_each_crtc_in_state(state, crtc, cstate, i) {
15627 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15628
15629 cs->wm.need_postvbl_update = true;
15630 dev_priv->display.optimize_watermarks(cs);
15631 }
15632
15633 drm_atomic_state_free(state);
15634 fail:
15635 drm_modeset_drop_locks(&ctx);
15636 drm_modeset_acquire_fini(&ctx);
15637 }
15638
15639 void intel_modeset_init(struct drm_device *dev)
15640 {
15641 struct drm_i915_private *dev_priv = to_i915(dev);
15642 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15643 int sprite, ret;
15644 enum pipe pipe;
15645 struct intel_crtc *crtc;
15646
15647 drm_mode_config_init(dev);
15648
15649 dev->mode_config.min_width = 0;
15650 dev->mode_config.min_height = 0;
15651
15652 dev->mode_config.preferred_depth = 24;
15653 dev->mode_config.prefer_shadow = 1;
15654
15655 dev->mode_config.allow_fb_modifiers = true;
15656
15657 dev->mode_config.funcs = &intel_mode_funcs;
15658
15659 intel_init_quirks(dev);
15660
15661 intel_init_pm(dev);
15662
15663 if (INTEL_INFO(dev)->num_pipes == 0)
15664 return;
15665
15666 /*
15667 * There may be no VBT; and if the BIOS enabled SSC we can
15668 * just keep using it to avoid unnecessary flicker. Whereas if the
15669 * BIOS isn't using it, don't assume it will work even if the VBT
15670 * indicates as much.
15671 */
15672 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15673 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15674 DREF_SSC1_ENABLE);
15675
15676 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15677 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15678 bios_lvds_use_ssc ? "en" : "dis",
15679 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15680 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15681 }
15682 }
15683
15684 if (IS_GEN2(dev)) {
15685 dev->mode_config.max_width = 2048;
15686 dev->mode_config.max_height = 2048;
15687 } else if (IS_GEN3(dev)) {
15688 dev->mode_config.max_width = 4096;
15689 dev->mode_config.max_height = 4096;
15690 } else {
15691 dev->mode_config.max_width = 8192;
15692 dev->mode_config.max_height = 8192;
15693 }
15694
15695 if (IS_845G(dev) || IS_I865G(dev)) {
15696 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15697 dev->mode_config.cursor_height = 1023;
15698 } else if (IS_GEN2(dev)) {
15699 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15700 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15701 } else {
15702 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15703 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15704 }
15705
15706 dev->mode_config.fb_base = ggtt->mappable_base;
15707
15708 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15709 INTEL_INFO(dev)->num_pipes,
15710 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15711
15712 for_each_pipe(dev_priv, pipe) {
15713 intel_crtc_init(dev, pipe);
15714 for_each_sprite(dev_priv, pipe, sprite) {
15715 ret = intel_plane_init(dev, pipe, sprite);
15716 if (ret)
15717 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15718 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15719 }
15720 }
15721
15722 intel_update_czclk(dev_priv);
15723 intel_update_cdclk(dev);
15724
15725 intel_shared_dpll_init(dev);
15726
15727 if (dev_priv->max_cdclk_freq == 0)
15728 intel_update_max_cdclk(dev);
15729
15730 /* Just disable it once at startup */
15731 i915_disable_vga(dev);
15732 intel_setup_outputs(dev);
15733
15734 drm_modeset_lock_all(dev);
15735 intel_modeset_setup_hw_state(dev);
15736 drm_modeset_unlock_all(dev);
15737
15738 for_each_intel_crtc(dev, crtc) {
15739 struct intel_initial_plane_config plane_config = {};
15740
15741 if (!crtc->active)
15742 continue;
15743
15744 /*
15745 * Note that reserving the BIOS fb up front prevents us
15746 * from stuffing other stolen allocations like the ring
15747 * on top. This prevents some ugliness at boot time, and
15748 * can even allow for smooth boot transitions if the BIOS
15749 * fb is large enough for the active pipe configuration.
15750 */
15751 dev_priv->display.get_initial_plane_config(crtc,
15752 &plane_config);
15753
15754 /*
15755 * If the fb is shared between multiple heads, we'll
15756 * just get the first one.
15757 */
15758 intel_find_initial_plane_obj(crtc, &plane_config);
15759 }
15760
15761 /*
15762 * Make sure hardware watermarks really match the state we read out.
15763 * Note that we need to do this after reconstructing the BIOS fb's
15764 * since the watermark calculation done here will use pstate->fb.
15765 */
15766 sanitize_watermarks(dev);
15767 }
15768
15769 static void intel_enable_pipe_a(struct drm_device *dev)
15770 {
15771 struct intel_connector *connector;
15772 struct drm_connector *crt = NULL;
15773 struct intel_load_detect_pipe load_detect_temp;
15774 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15775
15776 /* We can't just switch on the pipe A, we need to set things up with a
15777 * proper mode and output configuration. As a gross hack, enable pipe A
15778 * by enabling the load detect pipe once. */
15779 for_each_intel_connector(dev, connector) {
15780 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15781 crt = &connector->base;
15782 break;
15783 }
15784 }
15785
15786 if (!crt)
15787 return;
15788
15789 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15790 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15791 }
15792
15793 static bool
15794 intel_check_plane_mapping(struct intel_crtc *crtc)
15795 {
15796 struct drm_device *dev = crtc->base.dev;
15797 struct drm_i915_private *dev_priv = to_i915(dev);
15798 u32 val;
15799
15800 if (INTEL_INFO(dev)->num_pipes == 1)
15801 return true;
15802
15803 val = I915_READ(DSPCNTR(!crtc->plane));
15804
15805 if ((val & DISPLAY_PLANE_ENABLE) &&
15806 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15807 return false;
15808
15809 return true;
15810 }
15811
15812 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15813 {
15814 struct drm_device *dev = crtc->base.dev;
15815 struct intel_encoder *encoder;
15816
15817 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15818 return true;
15819
15820 return false;
15821 }
15822
15823 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15824 {
15825 struct drm_device *dev = encoder->base.dev;
15826 struct intel_connector *connector;
15827
15828 for_each_connector_on_encoder(dev, &encoder->base, connector)
15829 return true;
15830
15831 return false;
15832 }
15833
15834 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15835 {
15836 struct drm_device *dev = crtc->base.dev;
15837 struct drm_i915_private *dev_priv = to_i915(dev);
15838 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15839
15840 /* Clear any frame start delays used for debugging left by the BIOS */
15841 if (!transcoder_is_dsi(cpu_transcoder)) {
15842 i915_reg_t reg = PIPECONF(cpu_transcoder);
15843
15844 I915_WRITE(reg,
15845 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15846 }
15847
15848 /* restore vblank interrupts to correct state */
15849 drm_crtc_vblank_reset(&crtc->base);
15850 if (crtc->active) {
15851 struct intel_plane *plane;
15852
15853 drm_crtc_vblank_on(&crtc->base);
15854
15855 /* Disable everything but the primary plane */
15856 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15857 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15858 continue;
15859
15860 plane->disable_plane(&plane->base, &crtc->base);
15861 }
15862 }
15863
15864 /* We need to sanitize the plane -> pipe mapping first because this will
15865 * disable the crtc (and hence change the state) if it is wrong. Note
15866 * that gen4+ has a fixed plane -> pipe mapping. */
15867 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15868 bool plane;
15869
15870 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15871 crtc->base.base.id, crtc->base.name);
15872
15873 /* Pipe has the wrong plane attached and the plane is active.
15874 * Temporarily change the plane mapping and disable everything
15875 * ... */
15876 plane = crtc->plane;
15877 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15878 crtc->plane = !plane;
15879 intel_crtc_disable_noatomic(&crtc->base);
15880 crtc->plane = plane;
15881 }
15882
15883 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15884 crtc->pipe == PIPE_A && !crtc->active) {
15885 /* BIOS forgot to enable pipe A, this mostly happens after
15886 * resume. Force-enable the pipe to fix this, the update_dpms
15887 * call below we restore the pipe to the right state, but leave
15888 * the required bits on. */
15889 intel_enable_pipe_a(dev);
15890 }
15891
15892 /* Adjust the state of the output pipe according to whether we
15893 * have active connectors/encoders. */
15894 if (crtc->active && !intel_crtc_has_encoders(crtc))
15895 intel_crtc_disable_noatomic(&crtc->base);
15896
15897 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15898 /*
15899 * We start out with underrun reporting disabled to avoid races.
15900 * For correct bookkeeping mark this on active crtcs.
15901 *
15902 * Also on gmch platforms we dont have any hardware bits to
15903 * disable the underrun reporting. Which means we need to start
15904 * out with underrun reporting disabled also on inactive pipes,
15905 * since otherwise we'll complain about the garbage we read when
15906 * e.g. coming up after runtime pm.
15907 *
15908 * No protection against concurrent access is required - at
15909 * worst a fifo underrun happens which also sets this to false.
15910 */
15911 crtc->cpu_fifo_underrun_disabled = true;
15912 crtc->pch_fifo_underrun_disabled = true;
15913 }
15914 }
15915
15916 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15917 {
15918 struct intel_connector *connector;
15919 struct drm_device *dev = encoder->base.dev;
15920
15921 /* We need to check both for a crtc link (meaning that the
15922 * encoder is active and trying to read from a pipe) and the
15923 * pipe itself being active. */
15924 bool has_active_crtc = encoder->base.crtc &&
15925 to_intel_crtc(encoder->base.crtc)->active;
15926
15927 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15928 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15929 encoder->base.base.id,
15930 encoder->base.name);
15931
15932 /* Connector is active, but has no active pipe. This is
15933 * fallout from our resume register restoring. Disable
15934 * the encoder manually again. */
15935 if (encoder->base.crtc) {
15936 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15937 encoder->base.base.id,
15938 encoder->base.name);
15939 encoder->disable(encoder);
15940 if (encoder->post_disable)
15941 encoder->post_disable(encoder);
15942 }
15943 encoder->base.crtc = NULL;
15944
15945 /* Inconsistent output/port/pipe state happens presumably due to
15946 * a bug in one of the get_hw_state functions. Or someplace else
15947 * in our code, like the register restore mess on resume. Clamp
15948 * things to off as a safer default. */
15949 for_each_intel_connector(dev, connector) {
15950 if (connector->encoder != encoder)
15951 continue;
15952 connector->base.dpms = DRM_MODE_DPMS_OFF;
15953 connector->base.encoder = NULL;
15954 }
15955 }
15956 /* Enabled encoders without active connectors will be fixed in
15957 * the crtc fixup. */
15958 }
15959
15960 void i915_redisable_vga_power_on(struct drm_device *dev)
15961 {
15962 struct drm_i915_private *dev_priv = to_i915(dev);
15963 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15964
15965 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15966 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15967 i915_disable_vga(dev);
15968 }
15969 }
15970
15971 void i915_redisable_vga(struct drm_device *dev)
15972 {
15973 struct drm_i915_private *dev_priv = to_i915(dev);
15974
15975 /* This function can be called both from intel_modeset_setup_hw_state or
15976 * at a very early point in our resume sequence, where the power well
15977 * structures are not yet restored. Since this function is at a very
15978 * paranoid "someone might have enabled VGA while we were not looking"
15979 * level, just check if the power well is enabled instead of trying to
15980 * follow the "don't touch the power well if we don't need it" policy
15981 * the rest of the driver uses. */
15982 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15983 return;
15984
15985 i915_redisable_vga_power_on(dev);
15986
15987 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15988 }
15989
15990 static bool primary_get_hw_state(struct intel_plane *plane)
15991 {
15992 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15993
15994 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15995 }
15996
15997 /* FIXME read out full plane state for all planes */
15998 static void readout_plane_state(struct intel_crtc *crtc)
15999 {
16000 struct drm_plane *primary = crtc->base.primary;
16001 struct intel_plane_state *plane_state =
16002 to_intel_plane_state(primary->state);
16003
16004 plane_state->visible = crtc->active &&
16005 primary_get_hw_state(to_intel_plane(primary));
16006
16007 if (plane_state->visible)
16008 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16009 }
16010
16011 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16012 {
16013 struct drm_i915_private *dev_priv = to_i915(dev);
16014 enum pipe pipe;
16015 struct intel_crtc *crtc;
16016 struct intel_encoder *encoder;
16017 struct intel_connector *connector;
16018 int i;
16019
16020 dev_priv->active_crtcs = 0;
16021
16022 for_each_intel_crtc(dev, crtc) {
16023 struct intel_crtc_state *crtc_state = crtc->config;
16024 int pixclk = 0;
16025
16026 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16027 memset(crtc_state, 0, sizeof(*crtc_state));
16028 crtc_state->base.crtc = &crtc->base;
16029
16030 crtc_state->base.active = crtc_state->base.enable =
16031 dev_priv->display.get_pipe_config(crtc, crtc_state);
16032
16033 crtc->base.enabled = crtc_state->base.enable;
16034 crtc->active = crtc_state->base.active;
16035
16036 if (crtc_state->base.active) {
16037 dev_priv->active_crtcs |= 1 << crtc->pipe;
16038
16039 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16040 pixclk = ilk_pipe_pixel_rate(crtc_state);
16041 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16042 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16043 else
16044 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16045
16046 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16047 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16048 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16049 }
16050
16051 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16052
16053 readout_plane_state(crtc);
16054
16055 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16056 crtc->base.base.id, crtc->base.name,
16057 crtc->active ? "enabled" : "disabled");
16058 }
16059
16060 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16061 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16062
16063 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16064 &pll->config.hw_state);
16065 pll->config.crtc_mask = 0;
16066 for_each_intel_crtc(dev, crtc) {
16067 if (crtc->active && crtc->config->shared_dpll == pll)
16068 pll->config.crtc_mask |= 1 << crtc->pipe;
16069 }
16070 pll->active_mask = pll->config.crtc_mask;
16071
16072 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16073 pll->name, pll->config.crtc_mask, pll->on);
16074 }
16075
16076 for_each_intel_encoder(dev, encoder) {
16077 pipe = 0;
16078
16079 if (encoder->get_hw_state(encoder, &pipe)) {
16080 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16081 encoder->base.crtc = &crtc->base;
16082 encoder->get_config(encoder, crtc->config);
16083 } else {
16084 encoder->base.crtc = NULL;
16085 }
16086
16087 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16088 encoder->base.base.id,
16089 encoder->base.name,
16090 encoder->base.crtc ? "enabled" : "disabled",
16091 pipe_name(pipe));
16092 }
16093
16094 for_each_intel_connector(dev, connector) {
16095 if (connector->get_hw_state(connector)) {
16096 connector->base.dpms = DRM_MODE_DPMS_ON;
16097
16098 encoder = connector->encoder;
16099 connector->base.encoder = &encoder->base;
16100
16101 if (encoder->base.crtc &&
16102 encoder->base.crtc->state->active) {
16103 /*
16104 * This has to be done during hardware readout
16105 * because anything calling .crtc_disable may
16106 * rely on the connector_mask being accurate.
16107 */
16108 encoder->base.crtc->state->connector_mask |=
16109 1 << drm_connector_index(&connector->base);
16110 encoder->base.crtc->state->encoder_mask |=
16111 1 << drm_encoder_index(&encoder->base);
16112 }
16113
16114 } else {
16115 connector->base.dpms = DRM_MODE_DPMS_OFF;
16116 connector->base.encoder = NULL;
16117 }
16118 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16119 connector->base.base.id,
16120 connector->base.name,
16121 connector->base.encoder ? "enabled" : "disabled");
16122 }
16123
16124 for_each_intel_crtc(dev, crtc) {
16125 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16126
16127 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16128 if (crtc->base.state->active) {
16129 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16130 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16131 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16132
16133 /*
16134 * The initial mode needs to be set in order to keep
16135 * the atomic core happy. It wants a valid mode if the
16136 * crtc's enabled, so we do the above call.
16137 *
16138 * At this point some state updated by the connectors
16139 * in their ->detect() callback has not run yet, so
16140 * no recalculation can be done yet.
16141 *
16142 * Even if we could do a recalculation and modeset
16143 * right now it would cause a double modeset if
16144 * fbdev or userspace chooses a different initial mode.
16145 *
16146 * If that happens, someone indicated they wanted a
16147 * mode change, which means it's safe to do a full
16148 * recalculation.
16149 */
16150 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16151
16152 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16153 update_scanline_offset(crtc);
16154 }
16155
16156 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16157 }
16158 }
16159
16160 /* Scan out the current hw modeset state,
16161 * and sanitizes it to the current state
16162 */
16163 static void
16164 intel_modeset_setup_hw_state(struct drm_device *dev)
16165 {
16166 struct drm_i915_private *dev_priv = to_i915(dev);
16167 enum pipe pipe;
16168 struct intel_crtc *crtc;
16169 struct intel_encoder *encoder;
16170 int i;
16171
16172 intel_modeset_readout_hw_state(dev);
16173
16174 /* HW state is read out, now we need to sanitize this mess. */
16175 for_each_intel_encoder(dev, encoder) {
16176 intel_sanitize_encoder(encoder);
16177 }
16178
16179 for_each_pipe(dev_priv, pipe) {
16180 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16181 intel_sanitize_crtc(crtc);
16182 intel_dump_pipe_config(crtc, crtc->config,
16183 "[setup_hw_state]");
16184 }
16185
16186 intel_modeset_update_connector_atomic_state(dev);
16187
16188 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16189 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16190
16191 if (!pll->on || pll->active_mask)
16192 continue;
16193
16194 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16195
16196 pll->funcs.disable(dev_priv, pll);
16197 pll->on = false;
16198 }
16199
16200 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16201 vlv_wm_get_hw_state(dev);
16202 else if (IS_GEN9(dev))
16203 skl_wm_get_hw_state(dev);
16204 else if (HAS_PCH_SPLIT(dev))
16205 ilk_wm_get_hw_state(dev);
16206
16207 for_each_intel_crtc(dev, crtc) {
16208 unsigned long put_domains;
16209
16210 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16211 if (WARN_ON(put_domains))
16212 modeset_put_power_domains(dev_priv, put_domains);
16213 }
16214 intel_display_set_init_power(dev_priv, false);
16215
16216 intel_fbc_init_pipe_state(dev_priv);
16217 }
16218
16219 void intel_display_resume(struct drm_device *dev)
16220 {
16221 struct drm_i915_private *dev_priv = to_i915(dev);
16222 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16223 struct drm_modeset_acquire_ctx ctx;
16224 int ret;
16225 bool setup = false;
16226
16227 dev_priv->modeset_restore_state = NULL;
16228
16229 /*
16230 * This is a cludge because with real atomic modeset mode_config.mutex
16231 * won't be taken. Unfortunately some probed state like
16232 * audio_codec_enable is still protected by mode_config.mutex, so lock
16233 * it here for now.
16234 */
16235 mutex_lock(&dev->mode_config.mutex);
16236 drm_modeset_acquire_init(&ctx, 0);
16237
16238 retry:
16239 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16240
16241 if (ret == 0 && !setup) {
16242 setup = true;
16243
16244 intel_modeset_setup_hw_state(dev);
16245 i915_redisable_vga(dev);
16246 }
16247
16248 if (ret == 0 && state) {
16249 struct drm_crtc_state *crtc_state;
16250 struct drm_crtc *crtc;
16251 int i;
16252
16253 state->acquire_ctx = &ctx;
16254
16255 /* ignore any reset values/BIOS leftovers in the WM registers */
16256 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16257
16258 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16259 /*
16260 * Force recalculation even if we restore
16261 * current state. With fast modeset this may not result
16262 * in a modeset when the state is compatible.
16263 */
16264 crtc_state->mode_changed = true;
16265 }
16266
16267 ret = drm_atomic_commit(state);
16268 }
16269
16270 if (ret == -EDEADLK) {
16271 drm_modeset_backoff(&ctx);
16272 goto retry;
16273 }
16274
16275 drm_modeset_drop_locks(&ctx);
16276 drm_modeset_acquire_fini(&ctx);
16277 mutex_unlock(&dev->mode_config.mutex);
16278
16279 if (ret) {
16280 DRM_ERROR("Restoring old state failed with %i\n", ret);
16281 drm_atomic_state_free(state);
16282 }
16283 }
16284
16285 void intel_modeset_gem_init(struct drm_device *dev)
16286 {
16287 struct drm_i915_private *dev_priv = to_i915(dev);
16288 struct drm_crtc *c;
16289 struct drm_i915_gem_object *obj;
16290 int ret;
16291
16292 intel_init_gt_powersave(dev_priv);
16293
16294 intel_modeset_init_hw(dev);
16295
16296 intel_setup_overlay(dev_priv);
16297
16298 /*
16299 * Make sure any fbs we allocated at startup are properly
16300 * pinned & fenced. When we do the allocation it's too early
16301 * for this.
16302 */
16303 for_each_crtc(dev, c) {
16304 obj = intel_fb_obj(c->primary->fb);
16305 if (obj == NULL)
16306 continue;
16307
16308 mutex_lock(&dev->struct_mutex);
16309 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16310 c->primary->state->rotation);
16311 mutex_unlock(&dev->struct_mutex);
16312 if (ret) {
16313 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16314 to_intel_crtc(c)->pipe);
16315 drm_framebuffer_unreference(c->primary->fb);
16316 c->primary->fb = NULL;
16317 c->primary->crtc = c->primary->state->crtc = NULL;
16318 update_state_fb(c->primary);
16319 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16320 }
16321 }
16322 }
16323
16324 int intel_connector_register(struct drm_connector *connector)
16325 {
16326 struct intel_connector *intel_connector = to_intel_connector(connector);
16327 int ret;
16328
16329 ret = intel_backlight_device_register(intel_connector);
16330 if (ret)
16331 goto err;
16332
16333 return 0;
16334
16335 err:
16336 return ret;
16337 }
16338
16339 void intel_connector_unregister(struct drm_connector *connector)
16340 {
16341 struct intel_connector *intel_connector = to_intel_connector(connector);
16342
16343 intel_backlight_device_unregister(intel_connector);
16344 intel_panel_destroy_backlight(connector);
16345 }
16346
16347 void intel_modeset_cleanup(struct drm_device *dev)
16348 {
16349 struct drm_i915_private *dev_priv = to_i915(dev);
16350
16351 intel_disable_gt_powersave(dev_priv);
16352
16353 /*
16354 * Interrupts and polling as the first thing to avoid creating havoc.
16355 * Too much stuff here (turning of connectors, ...) would
16356 * experience fancy races otherwise.
16357 */
16358 intel_irq_uninstall(dev_priv);
16359
16360 /*
16361 * Due to the hpd irq storm handling the hotplug work can re-arm the
16362 * poll handlers. Hence disable polling after hpd handling is shut down.
16363 */
16364 drm_kms_helper_poll_fini(dev);
16365
16366 intel_unregister_dsm_handler();
16367
16368 intel_fbc_global_disable(dev_priv);
16369
16370 /* flush any delayed tasks or pending work */
16371 flush_scheduled_work();
16372
16373 drm_mode_config_cleanup(dev);
16374
16375 intel_cleanup_overlay(dev_priv);
16376
16377 intel_cleanup_gt_powersave(dev_priv);
16378
16379 intel_teardown_gmbus(dev);
16380 }
16381
16382 void intel_connector_attach_encoder(struct intel_connector *connector,
16383 struct intel_encoder *encoder)
16384 {
16385 connector->encoder = encoder;
16386 drm_mode_connector_attach_encoder(&connector->base,
16387 &encoder->base);
16388 }
16389
16390 /*
16391 * set vga decode state - true == enable VGA decode
16392 */
16393 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16394 {
16395 struct drm_i915_private *dev_priv = to_i915(dev);
16396 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16397 u16 gmch_ctrl;
16398
16399 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16400 DRM_ERROR("failed to read control word\n");
16401 return -EIO;
16402 }
16403
16404 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16405 return 0;
16406
16407 if (state)
16408 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16409 else
16410 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16411
16412 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16413 DRM_ERROR("failed to write control word\n");
16414 return -EIO;
16415 }
16416
16417 return 0;
16418 }
16419
16420 struct intel_display_error_state {
16421
16422 u32 power_well_driver;
16423
16424 int num_transcoders;
16425
16426 struct intel_cursor_error_state {
16427 u32 control;
16428 u32 position;
16429 u32 base;
16430 u32 size;
16431 } cursor[I915_MAX_PIPES];
16432
16433 struct intel_pipe_error_state {
16434 bool power_domain_on;
16435 u32 source;
16436 u32 stat;
16437 } pipe[I915_MAX_PIPES];
16438
16439 struct intel_plane_error_state {
16440 u32 control;
16441 u32 stride;
16442 u32 size;
16443 u32 pos;
16444 u32 addr;
16445 u32 surface;
16446 u32 tile_offset;
16447 } plane[I915_MAX_PIPES];
16448
16449 struct intel_transcoder_error_state {
16450 bool power_domain_on;
16451 enum transcoder cpu_transcoder;
16452
16453 u32 conf;
16454
16455 u32 htotal;
16456 u32 hblank;
16457 u32 hsync;
16458 u32 vtotal;
16459 u32 vblank;
16460 u32 vsync;
16461 } transcoder[4];
16462 };
16463
16464 struct intel_display_error_state *
16465 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16466 {
16467 struct intel_display_error_state *error;
16468 int transcoders[] = {
16469 TRANSCODER_A,
16470 TRANSCODER_B,
16471 TRANSCODER_C,
16472 TRANSCODER_EDP,
16473 };
16474 int i;
16475
16476 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16477 return NULL;
16478
16479 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16480 if (error == NULL)
16481 return NULL;
16482
16483 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16484 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16485
16486 for_each_pipe(dev_priv, i) {
16487 error->pipe[i].power_domain_on =
16488 __intel_display_power_is_enabled(dev_priv,
16489 POWER_DOMAIN_PIPE(i));
16490 if (!error->pipe[i].power_domain_on)
16491 continue;
16492
16493 error->cursor[i].control = I915_READ(CURCNTR(i));
16494 error->cursor[i].position = I915_READ(CURPOS(i));
16495 error->cursor[i].base = I915_READ(CURBASE(i));
16496
16497 error->plane[i].control = I915_READ(DSPCNTR(i));
16498 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16499 if (INTEL_GEN(dev_priv) <= 3) {
16500 error->plane[i].size = I915_READ(DSPSIZE(i));
16501 error->plane[i].pos = I915_READ(DSPPOS(i));
16502 }
16503 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16504 error->plane[i].addr = I915_READ(DSPADDR(i));
16505 if (INTEL_GEN(dev_priv) >= 4) {
16506 error->plane[i].surface = I915_READ(DSPSURF(i));
16507 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16508 }
16509
16510 error->pipe[i].source = I915_READ(PIPESRC(i));
16511
16512 if (HAS_GMCH_DISPLAY(dev_priv))
16513 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16514 }
16515
16516 /* Note: this does not include DSI transcoders. */
16517 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16518 if (HAS_DDI(dev_priv))
16519 error->num_transcoders++; /* Account for eDP. */
16520
16521 for (i = 0; i < error->num_transcoders; i++) {
16522 enum transcoder cpu_transcoder = transcoders[i];
16523
16524 error->transcoder[i].power_domain_on =
16525 __intel_display_power_is_enabled(dev_priv,
16526 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16527 if (!error->transcoder[i].power_domain_on)
16528 continue;
16529
16530 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16531
16532 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16533 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16534 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16535 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16536 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16537 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16538 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16539 }
16540
16541 return error;
16542 }
16543
16544 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16545
16546 void
16547 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16548 struct drm_device *dev,
16549 struct intel_display_error_state *error)
16550 {
16551 struct drm_i915_private *dev_priv = to_i915(dev);
16552 int i;
16553
16554 if (!error)
16555 return;
16556
16557 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16558 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16559 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16560 error->power_well_driver);
16561 for_each_pipe(dev_priv, i) {
16562 err_printf(m, "Pipe [%d]:\n", i);
16563 err_printf(m, " Power: %s\n",
16564 onoff(error->pipe[i].power_domain_on));
16565 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16566 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16567
16568 err_printf(m, "Plane [%d]:\n", i);
16569 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16570 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16571 if (INTEL_INFO(dev)->gen <= 3) {
16572 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16573 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16574 }
16575 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16576 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16577 if (INTEL_INFO(dev)->gen >= 4) {
16578 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16579 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16580 }
16581
16582 err_printf(m, "Cursor [%d]:\n", i);
16583 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16584 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16585 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16586 }
16587
16588 for (i = 0; i < error->num_transcoders; i++) {
16589 err_printf(m, "CPU transcoder: %s\n",
16590 transcoder_name(error->transcoder[i].cpu_transcoder));
16591 err_printf(m, " Power: %s\n",
16592 onoff(error->transcoder[i].power_domain_on));
16593 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16594 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16595 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16596 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16597 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16598 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16599 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16600 }
16601 }
Linux kernel - Deliverables
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