2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
47 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
48 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t
;
74 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
76 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
77 int, int, intel_clock_t
*, intel_clock_t
*);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
85 int target
, int refclk
, intel_clock_t
*match_clock
,
86 intel_clock_t
*best_clock
);
88 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
89 int target
, int refclk
, intel_clock_t
*match_clock
,
90 intel_clock_t
*best_clock
);
93 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
94 int target
, int refclk
, intel_clock_t
*match_clock
,
95 intel_clock_t
*best_clock
);
97 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
98 int target
, int refclk
, intel_clock_t
*match_clock
,
99 intel_clock_t
*best_clock
);
102 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
103 int target
, int refclk
, intel_clock_t
*match_clock
,
104 intel_clock_t
*best_clock
);
106 static inline u32
/* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device
*dev
)
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
111 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
116 static const intel_limit_t intel_limits_i8xx_dvo
= {
117 .dot
= { .min
= 25000, .max
= 350000 },
118 .vco
= { .min
= 930000, .max
= 1400000 },
119 .n
= { .min
= 3, .max
= 16 },
120 .m
= { .min
= 96, .max
= 140 },
121 .m1
= { .min
= 18, .max
= 26 },
122 .m2
= { .min
= 6, .max
= 16 },
123 .p
= { .min
= 4, .max
= 128 },
124 .p1
= { .min
= 2, .max
= 33 },
125 .p2
= { .dot_limit
= 165000,
126 .p2_slow
= 4, .p2_fast
= 2 },
127 .find_pll
= intel_find_best_PLL
,
130 static const intel_limit_t intel_limits_i8xx_lvds
= {
131 .dot
= { .min
= 25000, .max
= 350000 },
132 .vco
= { .min
= 930000, .max
= 1400000 },
133 .n
= { .min
= 3, .max
= 16 },
134 .m
= { .min
= 96, .max
= 140 },
135 .m1
= { .min
= 18, .max
= 26 },
136 .m2
= { .min
= 6, .max
= 16 },
137 .p
= { .min
= 4, .max
= 128 },
138 .p1
= { .min
= 1, .max
= 6 },
139 .p2
= { .dot_limit
= 165000,
140 .p2_slow
= 14, .p2_fast
= 7 },
141 .find_pll
= intel_find_best_PLL
,
144 static const intel_limit_t intel_limits_i9xx_sdvo
= {
145 .dot
= { .min
= 20000, .max
= 400000 },
146 .vco
= { .min
= 1400000, .max
= 2800000 },
147 .n
= { .min
= 1, .max
= 6 },
148 .m
= { .min
= 70, .max
= 120 },
149 .m1
= { .min
= 10, .max
= 22 },
150 .m2
= { .min
= 5, .max
= 9 },
151 .p
= { .min
= 5, .max
= 80 },
152 .p1
= { .min
= 1, .max
= 8 },
153 .p2
= { .dot_limit
= 200000,
154 .p2_slow
= 10, .p2_fast
= 5 },
155 .find_pll
= intel_find_best_PLL
,
158 static const intel_limit_t intel_limits_i9xx_lvds
= {
159 .dot
= { .min
= 20000, .max
= 400000 },
160 .vco
= { .min
= 1400000, .max
= 2800000 },
161 .n
= { .min
= 1, .max
= 6 },
162 .m
= { .min
= 70, .max
= 120 },
163 .m1
= { .min
= 10, .max
= 22 },
164 .m2
= { .min
= 5, .max
= 9 },
165 .p
= { .min
= 7, .max
= 98 },
166 .p1
= { .min
= 1, .max
= 8 },
167 .p2
= { .dot_limit
= 112000,
168 .p2_slow
= 14, .p2_fast
= 7 },
169 .find_pll
= intel_find_best_PLL
,
173 static const intel_limit_t intel_limits_g4x_sdvo
= {
174 .dot
= { .min
= 25000, .max
= 270000 },
175 .vco
= { .min
= 1750000, .max
= 3500000},
176 .n
= { .min
= 1, .max
= 4 },
177 .m
= { .min
= 104, .max
= 138 },
178 .m1
= { .min
= 17, .max
= 23 },
179 .m2
= { .min
= 5, .max
= 11 },
180 .p
= { .min
= 10, .max
= 30 },
181 .p1
= { .min
= 1, .max
= 3},
182 .p2
= { .dot_limit
= 270000,
186 .find_pll
= intel_g4x_find_best_PLL
,
189 static const intel_limit_t intel_limits_g4x_hdmi
= {
190 .dot
= { .min
= 22000, .max
= 400000 },
191 .vco
= { .min
= 1750000, .max
= 3500000},
192 .n
= { .min
= 1, .max
= 4 },
193 .m
= { .min
= 104, .max
= 138 },
194 .m1
= { .min
= 16, .max
= 23 },
195 .m2
= { .min
= 5, .max
= 11 },
196 .p
= { .min
= 5, .max
= 80 },
197 .p1
= { .min
= 1, .max
= 8},
198 .p2
= { .dot_limit
= 165000,
199 .p2_slow
= 10, .p2_fast
= 5 },
200 .find_pll
= intel_g4x_find_best_PLL
,
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
204 .dot
= { .min
= 20000, .max
= 115000 },
205 .vco
= { .min
= 1750000, .max
= 3500000 },
206 .n
= { .min
= 1, .max
= 3 },
207 .m
= { .min
= 104, .max
= 138 },
208 .m1
= { .min
= 17, .max
= 23 },
209 .m2
= { .min
= 5, .max
= 11 },
210 .p
= { .min
= 28, .max
= 112 },
211 .p1
= { .min
= 2, .max
= 8 },
212 .p2
= { .dot_limit
= 0,
213 .p2_slow
= 14, .p2_fast
= 14
215 .find_pll
= intel_g4x_find_best_PLL
,
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
219 .dot
= { .min
= 80000, .max
= 224000 },
220 .vco
= { .min
= 1750000, .max
= 3500000 },
221 .n
= { .min
= 1, .max
= 3 },
222 .m
= { .min
= 104, .max
= 138 },
223 .m1
= { .min
= 17, .max
= 23 },
224 .m2
= { .min
= 5, .max
= 11 },
225 .p
= { .min
= 14, .max
= 42 },
226 .p1
= { .min
= 2, .max
= 6 },
227 .p2
= { .dot_limit
= 0,
228 .p2_slow
= 7, .p2_fast
= 7
230 .find_pll
= intel_g4x_find_best_PLL
,
233 static const intel_limit_t intel_limits_g4x_display_port
= {
234 .dot
= { .min
= 161670, .max
= 227000 },
235 .vco
= { .min
= 1750000, .max
= 3500000},
236 .n
= { .min
= 1, .max
= 2 },
237 .m
= { .min
= 97, .max
= 108 },
238 .m1
= { .min
= 0x10, .max
= 0x12 },
239 .m2
= { .min
= 0x05, .max
= 0x06 },
240 .p
= { .min
= 10, .max
= 20 },
241 .p1
= { .min
= 1, .max
= 2},
242 .p2
= { .dot_limit
= 0,
243 .p2_slow
= 10, .p2_fast
= 10 },
244 .find_pll
= intel_find_pll_g4x_dp
,
247 static const intel_limit_t intel_limits_pineview_sdvo
= {
248 .dot
= { .min
= 20000, .max
= 400000},
249 .vco
= { .min
= 1700000, .max
= 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n
= { .min
= 3, .max
= 6 },
252 .m
= { .min
= 2, .max
= 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1
= { .min
= 0, .max
= 0 },
255 .m2
= { .min
= 0, .max
= 254 },
256 .p
= { .min
= 5, .max
= 80 },
257 .p1
= { .min
= 1, .max
= 8 },
258 .p2
= { .dot_limit
= 200000,
259 .p2_slow
= 10, .p2_fast
= 5 },
260 .find_pll
= intel_find_best_PLL
,
263 static const intel_limit_t intel_limits_pineview_lvds
= {
264 .dot
= { .min
= 20000, .max
= 400000 },
265 .vco
= { .min
= 1700000, .max
= 3500000 },
266 .n
= { .min
= 3, .max
= 6 },
267 .m
= { .min
= 2, .max
= 256 },
268 .m1
= { .min
= 0, .max
= 0 },
269 .m2
= { .min
= 0, .max
= 254 },
270 .p
= { .min
= 7, .max
= 112 },
271 .p1
= { .min
= 1, .max
= 8 },
272 .p2
= { .dot_limit
= 112000,
273 .p2_slow
= 14, .p2_fast
= 14 },
274 .find_pll
= intel_find_best_PLL
,
277 /* Ironlake / Sandybridge
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
282 static const intel_limit_t intel_limits_ironlake_dac
= {
283 .dot
= { .min
= 25000, .max
= 350000 },
284 .vco
= { .min
= 1760000, .max
= 3510000 },
285 .n
= { .min
= 1, .max
= 5 },
286 .m
= { .min
= 79, .max
= 127 },
287 .m1
= { .min
= 12, .max
= 22 },
288 .m2
= { .min
= 5, .max
= 9 },
289 .p
= { .min
= 5, .max
= 80 },
290 .p1
= { .min
= 1, .max
= 8 },
291 .p2
= { .dot_limit
= 225000,
292 .p2_slow
= 10, .p2_fast
= 5 },
293 .find_pll
= intel_g4x_find_best_PLL
,
296 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
297 .dot
= { .min
= 25000, .max
= 350000 },
298 .vco
= { .min
= 1760000, .max
= 3510000 },
299 .n
= { .min
= 1, .max
= 3 },
300 .m
= { .min
= 79, .max
= 118 },
301 .m1
= { .min
= 12, .max
= 22 },
302 .m2
= { .min
= 5, .max
= 9 },
303 .p
= { .min
= 28, .max
= 112 },
304 .p1
= { .min
= 2, .max
= 8 },
305 .p2
= { .dot_limit
= 225000,
306 .p2_slow
= 14, .p2_fast
= 14 },
307 .find_pll
= intel_g4x_find_best_PLL
,
310 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
311 .dot
= { .min
= 25000, .max
= 350000 },
312 .vco
= { .min
= 1760000, .max
= 3510000 },
313 .n
= { .min
= 1, .max
= 3 },
314 .m
= { .min
= 79, .max
= 127 },
315 .m1
= { .min
= 12, .max
= 22 },
316 .m2
= { .min
= 5, .max
= 9 },
317 .p
= { .min
= 14, .max
= 56 },
318 .p1
= { .min
= 2, .max
= 8 },
319 .p2
= { .dot_limit
= 225000,
320 .p2_slow
= 7, .p2_fast
= 7 },
321 .find_pll
= intel_g4x_find_best_PLL
,
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
326 .dot
= { .min
= 25000, .max
= 350000 },
327 .vco
= { .min
= 1760000, .max
= 3510000 },
328 .n
= { .min
= 1, .max
= 2 },
329 .m
= { .min
= 79, .max
= 126 },
330 .m1
= { .min
= 12, .max
= 22 },
331 .m2
= { .min
= 5, .max
= 9 },
332 .p
= { .min
= 28, .max
= 112 },
333 .p1
= { .min
= 2, .max
= 8 },
334 .p2
= { .dot_limit
= 225000,
335 .p2_slow
= 14, .p2_fast
= 14 },
336 .find_pll
= intel_g4x_find_best_PLL
,
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
340 .dot
= { .min
= 25000, .max
= 350000 },
341 .vco
= { .min
= 1760000, .max
= 3510000 },
342 .n
= { .min
= 1, .max
= 3 },
343 .m
= { .min
= 79, .max
= 126 },
344 .m1
= { .min
= 12, .max
= 22 },
345 .m2
= { .min
= 5, .max
= 9 },
346 .p
= { .min
= 14, .max
= 42 },
347 .p1
= { .min
= 2, .max
= 6 },
348 .p2
= { .dot_limit
= 225000,
349 .p2_slow
= 7, .p2_fast
= 7 },
350 .find_pll
= intel_g4x_find_best_PLL
,
353 static const intel_limit_t intel_limits_ironlake_display_port
= {
354 .dot
= { .min
= 25000, .max
= 350000 },
355 .vco
= { .min
= 1760000, .max
= 3510000},
356 .n
= { .min
= 1, .max
= 2 },
357 .m
= { .min
= 81, .max
= 90 },
358 .m1
= { .min
= 12, .max
= 22 },
359 .m2
= { .min
= 5, .max
= 9 },
360 .p
= { .min
= 10, .max
= 20 },
361 .p1
= { .min
= 1, .max
= 2},
362 .p2
= { .dot_limit
= 0,
363 .p2_slow
= 10, .p2_fast
= 10 },
364 .find_pll
= intel_find_pll_ironlake_dp
,
367 static const intel_limit_t intel_limits_vlv_dac
= {
368 .dot
= { .min
= 25000, .max
= 270000 },
369 .vco
= { .min
= 4000000, .max
= 6000000 },
370 .n
= { .min
= 1, .max
= 7 },
371 .m
= { .min
= 22, .max
= 450 }, /* guess */
372 .m1
= { .min
= 2, .max
= 3 },
373 .m2
= { .min
= 11, .max
= 156 },
374 .p
= { .min
= 10, .max
= 30 },
375 .p1
= { .min
= 2, .max
= 3 },
376 .p2
= { .dot_limit
= 270000,
377 .p2_slow
= 2, .p2_fast
= 20 },
378 .find_pll
= intel_vlv_find_best_pll
,
381 static const intel_limit_t intel_limits_vlv_hdmi
= {
382 .dot
= { .min
= 20000, .max
= 165000 },
383 .vco
= { .min
= 5994000, .max
= 4000000 },
384 .n
= { .min
= 1, .max
= 7 },
385 .m
= { .min
= 60, .max
= 300 }, /* guess */
386 .m1
= { .min
= 2, .max
= 3 },
387 .m2
= { .min
= 11, .max
= 156 },
388 .p
= { .min
= 10, .max
= 30 },
389 .p1
= { .min
= 2, .max
= 3 },
390 .p2
= { .dot_limit
= 270000,
391 .p2_slow
= 2, .p2_fast
= 20 },
392 .find_pll
= intel_vlv_find_best_pll
,
395 static const intel_limit_t intel_limits_vlv_dp
= {
396 .dot
= { .min
= 162000, .max
= 270000 },
397 .vco
= { .min
= 5994000, .max
= 4000000 },
398 .n
= { .min
= 1, .max
= 7 },
399 .m
= { .min
= 60, .max
= 300 }, /* guess */
400 .m1
= { .min
= 2, .max
= 3 },
401 .m2
= { .min
= 11, .max
= 156 },
402 .p
= { .min
= 10, .max
= 30 },
403 .p1
= { .min
= 2, .max
= 3 },
404 .p2
= { .dot_limit
= 270000,
405 .p2_slow
= 2, .p2_fast
= 20 },
406 .find_pll
= intel_vlv_find_best_pll
,
409 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
414 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
420 I915_WRITE(DPIO_REG
, reg
);
421 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
427 val
= I915_READ(DPIO_DATA
);
430 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
434 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
439 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
445 I915_WRITE(DPIO_DATA
, val
);
446 I915_WRITE(DPIO_REG
, reg
);
447 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
453 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
456 static void vlv_init_dpio(struct drm_device
*dev
)
458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL
, 0);
462 POSTING_READ(DPIO_CTL
);
463 I915_WRITE(DPIO_CTL
, 1);
464 POSTING_READ(DPIO_CTL
);
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id
*id
)
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id
->ident
);
473 static const struct dmi_system_id intel_dual_link_lvds
[] = {
475 .callback
= intel_dual_link_lvds_callback
,
476 .ident
= "Apple MacBook Pro (Core i5/i7 Series)",
478 DMI_MATCH(DMI_SYS_VENDOR
, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME
, "MacBookPro8,2"),
482 { } /* terminating entry */
485 static bool is_dual_link_lvds(struct drm_i915_private
*dev_priv
,
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode
> 0)
492 return i915_lvds_channel_mode
== 2;
494 if (dmi_check_system(intel_dual_link_lvds
))
497 if (dev_priv
->lvds_val
)
498 val
= dev_priv
->lvds_val
;
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
505 val
= I915_READ(reg
);
506 if (!(val
& ~(LVDS_PIPE_MASK
| LVDS_DETECTED
)))
507 val
= dev_priv
->bios_lvds_val
;
508 dev_priv
->lvds_val
= val
;
510 return (val
& LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
;
513 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
516 struct drm_device
*dev
= crtc
->dev
;
517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
518 const intel_limit_t
*limit
;
520 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
521 if (is_dual_link_lvds(dev_priv
, PCH_LVDS
)) {
522 /* LVDS dual channel */
523 if (refclk
== 100000)
524 limit
= &intel_limits_ironlake_dual_lvds_100m
;
526 limit
= &intel_limits_ironlake_dual_lvds
;
528 if (refclk
== 100000)
529 limit
= &intel_limits_ironlake_single_lvds_100m
;
531 limit
= &intel_limits_ironlake_single_lvds
;
533 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
535 limit
= &intel_limits_ironlake_display_port
;
537 limit
= &intel_limits_ironlake_dac
;
542 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
544 struct drm_device
*dev
= crtc
->dev
;
545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
546 const intel_limit_t
*limit
;
548 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
549 if (is_dual_link_lvds(dev_priv
, LVDS
))
550 /* LVDS with dual channel */
551 limit
= &intel_limits_g4x_dual_channel_lvds
;
553 /* LVDS with dual channel */
554 limit
= &intel_limits_g4x_single_channel_lvds
;
555 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
556 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
557 limit
= &intel_limits_g4x_hdmi
;
558 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
559 limit
= &intel_limits_g4x_sdvo
;
560 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
561 limit
= &intel_limits_g4x_display_port
;
562 } else /* The option is for other outputs */
563 limit
= &intel_limits_i9xx_sdvo
;
568 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
570 struct drm_device
*dev
= crtc
->dev
;
571 const intel_limit_t
*limit
;
573 if (HAS_PCH_SPLIT(dev
))
574 limit
= intel_ironlake_limit(crtc
, refclk
);
575 else if (IS_G4X(dev
)) {
576 limit
= intel_g4x_limit(crtc
);
577 } else if (IS_PINEVIEW(dev
)) {
578 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
579 limit
= &intel_limits_pineview_lvds
;
581 limit
= &intel_limits_pineview_sdvo
;
582 } else if (IS_VALLEYVIEW(dev
)) {
583 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
584 limit
= &intel_limits_vlv_dac
;
585 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
586 limit
= &intel_limits_vlv_hdmi
;
588 limit
= &intel_limits_vlv_dp
;
589 } else if (!IS_GEN2(dev
)) {
590 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
591 limit
= &intel_limits_i9xx_lvds
;
593 limit
= &intel_limits_i9xx_sdvo
;
595 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
596 limit
= &intel_limits_i8xx_lvds
;
598 limit
= &intel_limits_i8xx_dvo
;
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
606 clock
->m
= clock
->m2
+ 2;
607 clock
->p
= clock
->p1
* clock
->p2
;
608 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
609 clock
->dot
= clock
->vco
/ clock
->p
;
612 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
614 if (IS_PINEVIEW(dev
)) {
615 pineview_clock(refclk
, clock
);
618 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
619 clock
->p
= clock
->p1
* clock
->p2
;
620 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
621 clock
->dot
= clock
->vco
/ clock
->p
;
625 * Returns whether any output on the specified pipe is of the specified type
627 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
629 struct drm_device
*dev
= crtc
->dev
;
630 struct intel_encoder
*encoder
;
632 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
633 if (encoder
->type
== type
)
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
645 static bool intel_PLL_is_valid(struct drm_device
*dev
,
646 const intel_limit_t
*limit
,
647 const intel_clock_t
*clock
)
649 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
652 INTELPllInvalid("p out of range\n");
653 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
660 INTELPllInvalid("m out of range\n");
661 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
662 INTELPllInvalid("n out of range\n");
663 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
668 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
669 INTELPllInvalid("dot out of range\n");
675 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
676 int target
, int refclk
, intel_clock_t
*match_clock
,
677 intel_clock_t
*best_clock
)
680 struct drm_device
*dev
= crtc
->dev
;
681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
685 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
686 (I915_READ(LVDS
)) != 0) {
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
693 if (is_dual_link_lvds(dev_priv
, LVDS
))
694 clock
.p2
= limit
->p2
.p2_fast
;
696 clock
.p2
= limit
->p2
.p2_slow
;
698 if (target
< limit
->p2
.dot_limit
)
699 clock
.p2
= limit
->p2
.p2_slow
;
701 clock
.p2
= limit
->p2
.p2_fast
;
704 memset(best_clock
, 0, sizeof(*best_clock
));
706 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
708 for (clock
.m2
= limit
->m2
.min
;
709 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
710 /* m1 is always 0 in Pineview */
711 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
713 for (clock
.n
= limit
->n
.min
;
714 clock
.n
<= limit
->n
.max
; clock
.n
++) {
715 for (clock
.p1
= limit
->p1
.min
;
716 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
719 intel_clock(dev
, refclk
, &clock
);
720 if (!intel_PLL_is_valid(dev
, limit
,
724 clock
.p
!= match_clock
->p
)
727 this_err
= abs(clock
.dot
- target
);
728 if (this_err
< err
) {
737 return (err
!= target
);
741 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
742 int target
, int refclk
, intel_clock_t
*match_clock
,
743 intel_clock_t
*best_clock
)
745 struct drm_device
*dev
= crtc
->dev
;
746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
750 /* approximately equals target * 0.00585 */
751 int err_most
= (target
>> 8) + (target
>> 9);
754 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
757 if (HAS_PCH_SPLIT(dev
))
761 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
763 clock
.p2
= limit
->p2
.p2_fast
;
765 clock
.p2
= limit
->p2
.p2_slow
;
767 if (target
< limit
->p2
.dot_limit
)
768 clock
.p2
= limit
->p2
.p2_slow
;
770 clock
.p2
= limit
->p2
.p2_fast
;
773 memset(best_clock
, 0, sizeof(*best_clock
));
774 max_n
= limit
->n
.max
;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock
.m1
= limit
->m1
.max
;
779 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
780 for (clock
.m2
= limit
->m2
.max
;
781 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
782 for (clock
.p1
= limit
->p1
.max
;
783 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
786 intel_clock(dev
, refclk
, &clock
);
787 if (!intel_PLL_is_valid(dev
, limit
,
791 clock
.p
!= match_clock
->p
)
794 this_err
= abs(clock
.dot
- target
);
795 if (this_err
< err_most
) {
809 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
810 int target
, int refclk
, intel_clock_t
*match_clock
,
811 intel_clock_t
*best_clock
)
813 struct drm_device
*dev
= crtc
->dev
;
816 if (target
< 200000) {
829 intel_clock(dev
, refclk
, &clock
);
830 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
836 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
837 int target
, int refclk
, intel_clock_t
*match_clock
,
838 intel_clock_t
*best_clock
)
841 if (target
< 200000) {
854 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
855 clock
.p
= (clock
.p1
* clock
.p2
);
856 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
858 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
862 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
863 int target
, int refclk
, intel_clock_t
*match_clock
,
864 intel_clock_t
*best_clock
)
866 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
868 u32 updrate
, minupdate
, fracbits
, p
;
869 unsigned long bestppm
, ppm
, absppm
;
873 dotclk
= target
* 1000;
876 fastclk
= dotclk
/ (2*100);
880 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
881 bestm1
= bestm2
= bestp1
= bestp2
= 0;
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
885 updrate
= refclk
/ n
;
886 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
887 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
893 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
894 refclk
) / (2*refclk
));
897 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
898 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
899 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
900 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
904 if (absppm
< bestppm
- 10) {
921 best_clock
->n
= bestn
;
922 best_clock
->m1
= bestm1
;
923 best_clock
->m2
= bestm2
;
924 best_clock
->p1
= bestp1
;
925 best_clock
->p2
= bestp2
;
930 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
933 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
935 frame
= I915_READ(frame_reg
);
937 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
942 * intel_wait_for_vblank - wait for vblank on a given pipe
944 * @pipe: pipe to wait for
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
949 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 int pipestat_reg
= PIPESTAT(pipe
);
954 if (INTEL_INFO(dev
)->gen
>= 5) {
955 ironlake_wait_for_vblank(dev
, pipe
);
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
972 I915_WRITE(pipestat_reg
,
973 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg
) &
977 PIPE_VBLANK_INTERRUPT_STATUS
,
979 DRM_DEBUG_KMS("vblank wait timed out\n");
983 * intel_wait_for_pipe_off - wait for pipe to turn off
985 * @pipe: pipe to wait for
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
992 * wait for the pipe register state bit to turn off
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
999 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
1001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1003 if (INTEL_INFO(dev
)->gen
>= 4) {
1004 int reg
= PIPECONF(pipe
);
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1011 u32 last_line
, line_mask
;
1012 int reg
= PIPEDSL(pipe
);
1013 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1016 line_mask
= DSL_LINEMASK_GEN2
;
1018 line_mask
= DSL_LINEMASK_GEN3
;
1020 /* Wait for the display line to settle */
1022 last_line
= I915_READ(reg
) & line_mask
;
1024 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
1025 time_after(timeout
, jiffies
));
1026 if (time_after(jiffies
, timeout
))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1031 static const char *state_string(bool enabled
)
1033 return enabled
? "on" : "off";
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private
*dev_priv
,
1038 enum pipe pipe
, bool state
)
1045 val
= I915_READ(reg
);
1046 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1047 WARN(cur_state
!= state
,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state
), state_string(cur_state
));
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1056 struct intel_pch_pll
*pll
,
1057 struct intel_crtc
*crtc
,
1063 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1069 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1072 val
= I915_READ(pll
->pll_reg
);
1073 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1074 WARN(cur_state
!= state
,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1082 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1083 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1084 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state
, crtc
->pipe
, pch_dpll
)) {
1087 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1088 WARN(cur_state
!= state
,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll
->pll_reg
== _PCH_DPLL_B
,
1091 state_string(state
),
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1100 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1101 enum pipe pipe
, bool state
)
1107 if (IS_HASWELL(dev_priv
->dev
)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg
= DDI_FUNC_CTL(pipe
);
1110 val
= I915_READ(reg
);
1111 cur_state
= !!(val
& PIPE_DDI_FUNC_ENABLE
);
1113 reg
= FDI_TX_CTL(pipe
);
1114 val
= I915_READ(reg
);
1115 cur_state
= !!(val
& FDI_TX_ENABLE
);
1117 WARN(cur_state
!= state
,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state
), state_string(cur_state
));
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1124 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1125 enum pipe pipe
, bool state
)
1131 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1135 reg
= FDI_RX_CTL(pipe
);
1136 val
= I915_READ(reg
);
1137 cur_state
= !!(val
& FDI_RX_ENABLE
);
1139 WARN(cur_state
!= state
,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state
), state_string(cur_state
));
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv
->info
->gen
== 5)
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv
->dev
))
1160 reg
= FDI_TX_CTL(pipe
);
1161 val
= I915_READ(reg
);
1162 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1171 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1175 reg
= FDI_RX_CTL(pipe
);
1176 val
= I915_READ(reg
);
1177 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1180 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1183 int pp_reg
, lvds_reg
;
1185 enum pipe panel_pipe
= PIPE_A
;
1188 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1189 pp_reg
= PCH_PP_CONTROL
;
1190 lvds_reg
= PCH_LVDS
;
1192 pp_reg
= PP_CONTROL
;
1196 val
= I915_READ(pp_reg
);
1197 if (!(val
& PANEL_POWER_ON
) ||
1198 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1201 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1202 panel_pipe
= PIPE_B
;
1204 WARN(panel_pipe
== pipe
&& locked
,
1205 "panel assertion failure, pipe %c regs locked\n",
1209 void assert_pipe(struct drm_i915_private
*dev_priv
,
1210 enum pipe pipe
, bool state
)
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1220 reg
= PIPECONF(pipe
);
1221 val
= I915_READ(reg
);
1222 cur_state
= !!(val
& PIPECONF_ENABLE
);
1223 WARN(cur_state
!= state
,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1228 static void assert_plane(struct drm_i915_private
*dev_priv
,
1229 enum plane plane
, bool state
)
1235 reg
= DSPCNTR(plane
);
1236 val
= I915_READ(reg
);
1237 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1238 WARN(cur_state
!= state
,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane
), state_string(state
), state_string(cur_state
));
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1246 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1255 reg
= DSPCNTR(pipe
);
1256 val
= I915_READ(reg
);
1257 WARN((val
& DISPLAY_PLANE_ENABLE
),
1258 "plane %c assertion failure, should be disabled but not\n",
1263 /* Need to check both planes against the pipe */
1264 for (i
= 0; i
< 2; i
++) {
1266 val
= I915_READ(reg
);
1267 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1268 DISPPLANE_SEL_PIPE_SHIFT
;
1269 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i
), pipe_name(pipe
));
1275 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1280 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 val
= I915_READ(PCH_DREF_CONTROL
);
1286 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1287 DREF_SUPERSPREAD_SOURCE_MASK
));
1288 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1291 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1298 reg
= TRANSCONF(pipe
);
1299 val
= I915_READ(reg
);
1300 enabled
= !!(val
& TRANS_ENABLE
);
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1307 enum pipe pipe
, u32 port_sel
, u32 val
)
1309 if ((val
& DP_PORT_EN
) == 0)
1312 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1313 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1314 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1315 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1318 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1324 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1325 enum pipe pipe
, u32 val
)
1327 if ((val
& PORT_ENABLE
) == 0)
1330 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1331 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1334 if ((val
& TRANSCODER_MASK
) != TRANSCODER(pipe
))
1340 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1341 enum pipe pipe
, u32 val
)
1343 if ((val
& LVDS_PORT_EN
) == 0)
1346 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1347 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1350 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1356 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1357 enum pipe pipe
, u32 val
)
1359 if ((val
& ADPA_DAC_ENABLE
) == 0)
1361 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1362 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1365 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1371 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1372 enum pipe pipe
, int reg
, u32 port_sel
)
1374 u32 val
= I915_READ(reg
);
1375 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg
, pipe_name(pipe
));
1379 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1380 && (val
& DP_PIPEB_SELECT
),
1381 "IBX PCH dp port still using transcoder B\n");
1384 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1385 enum pipe pipe
, int reg
)
1387 u32 val
= I915_READ(reg
);
1388 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1389 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1390 reg
, pipe_name(pipe
));
1392 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& PORT_ENABLE
) == 0
1393 && (val
& SDVO_PIPE_B_SELECT
),
1394 "IBX PCH hdmi port still using transcoder B\n");
1397 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1403 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1404 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1405 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1408 val
= I915_READ(reg
);
1409 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1410 "PCH VGA enabled on transcoder %c, should be disabled\n",
1414 val
= I915_READ(reg
);
1415 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1416 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1419 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1420 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1421 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1425 * intel_enable_pll - enable a PLL
1426 * @dev_priv: i915 private structure
1427 * @pipe: pipe PLL to enable
1429 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1430 * make sure the PLL reg is writable first though, since the panel write
1431 * protect mechanism may be enabled.
1433 * Note! This is for pre-ILK only.
1435 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1440 /* No really, not for ILK+ */
1441 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1445 assert_panel_unlocked(dev_priv
, pipe
);
1448 val
= I915_READ(reg
);
1449 val
|= DPLL_VCO_ENABLE
;
1451 /* We do this three times for luck */
1452 I915_WRITE(reg
, val
);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg
, val
);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg
, val
);
1460 udelay(150); /* wait for warmup */
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1470 * Note! This is for pre-ILK only.
1472 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv
, pipe
);
1485 val
= I915_READ(reg
);
1486 val
&= ~DPLL_VCO_ENABLE
;
1487 I915_WRITE(reg
, val
);
1493 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
)
1495 unsigned long flags
;
1497 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1498 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1504 I915_WRITE(SBI_ADDR
,
1506 I915_WRITE(SBI_DATA
,
1508 I915_WRITE(SBI_CTL_STAT
,
1512 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1519 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1523 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
)
1525 unsigned long flags
;
1528 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1529 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1535 I915_WRITE(SBI_ADDR
,
1537 I915_WRITE(SBI_CTL_STAT
,
1541 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1547 value
= I915_READ(SBI_DATA
);
1550 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1562 static void intel_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1564 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1565 struct intel_pch_pll
*pll
;
1569 /* PCH PLLs only available on ILK, SNB and IVB */
1570 BUG_ON(dev_priv
->info
->gen
< 5);
1571 pll
= intel_crtc
->pch_pll
;
1575 if (WARN_ON(pll
->refcount
== 0))
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll
->pll_reg
, pll
->active
, pll
->on
,
1580 intel_crtc
->base
.base
.id
);
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv
);
1585 if (pll
->active
++ && pll
->on
) {
1586 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1593 val
= I915_READ(reg
);
1594 val
|= DPLL_VCO_ENABLE
;
1595 I915_WRITE(reg
, val
);
1602 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1604 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1605 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv
->info
->gen
< 5);
1614 if (WARN_ON(pll
->refcount
== 0))
1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll
->pll_reg
, pll
->active
, pll
->on
,
1619 intel_crtc
->base
.base
.id
);
1621 if (WARN_ON(pll
->active
== 0)) {
1622 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1626 if (--pll
->active
) {
1627 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1637 val
= I915_READ(reg
);
1638 val
&= ~DPLL_VCO_ENABLE
;
1639 I915_WRITE(reg
, val
);
1646 static void intel_enable_transcoder(struct drm_i915_private
*dev_priv
,
1650 u32 val
, pipeconf_val
;
1651 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv
->info
->gen
< 5);
1656 /* Make sure PCH DPLL is enabled */
1657 assert_pch_pll_enabled(dev_priv
,
1658 to_intel_crtc(crtc
)->pch_pll
,
1659 to_intel_crtc(crtc
));
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv
, pipe
);
1663 assert_fdi_rx_enabled(dev_priv
, pipe
);
1665 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669 reg
= TRANSCONF(pipe
);
1670 val
= I915_READ(reg
);
1671 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1673 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1678 val
&= ~PIPE_BPC_MASK
;
1679 val
|= pipeconf_val
& PIPE_BPC_MASK
;
1682 val
&= ~TRANS_INTERLACE_MASK
;
1683 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1684 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1685 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1686 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1688 val
|= TRANS_INTERLACED
;
1690 val
|= TRANS_PROGRESSIVE
;
1692 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1693 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1697 static void intel_disable_transcoder(struct drm_i915_private
*dev_priv
,
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv
, pipe
);
1705 assert_fdi_rx_disabled(dev_priv
, pipe
);
1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv
, pipe
);
1710 reg
= TRANSCONF(pipe
);
1711 val
= I915_READ(reg
);
1712 val
&= ~TRANS_ENABLE
;
1713 I915_WRITE(reg
, val
);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1716 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1720 * intel_enable_pipe - enable a pipe, asserting requirements
1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1728 * @pipe should be %PIPE_A or %PIPE_B.
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1733 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1744 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1745 assert_pll_enabled(dev_priv
, pipe
);
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv
, pipe
);
1750 assert_fdi_tx_pll_enabled(dev_priv
, pipe
);
1752 /* FIXME: assert CPU port conditions for SNB+ */
1755 reg
= PIPECONF(pipe
);
1756 val
= I915_READ(reg
);
1757 if (val
& PIPECONF_ENABLE
)
1760 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1761 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1765 * intel_disable_pipe - disable a pipe, asserting requirements
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1772 * @pipe should be %PIPE_A or %PIPE_B.
1774 * Will wait until the pipe has shut down before returning.
1776 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1786 assert_planes_disabled(dev_priv
, pipe
);
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1792 reg
= PIPECONF(pipe
);
1793 val
= I915_READ(reg
);
1794 if ((val
& PIPECONF_ENABLE
) == 0)
1797 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1798 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1805 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1808 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1809 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1820 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1821 enum plane plane
, enum pipe pipe
)
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv
, pipe
);
1829 reg
= DSPCNTR(plane
);
1830 val
= I915_READ(reg
);
1831 if (val
& DISPLAY_PLANE_ENABLE
)
1834 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1835 intel_flush_display_plane(dev_priv
, plane
);
1836 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1845 * Disable @plane; should be an independent operation.
1847 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1848 enum plane plane
, enum pipe pipe
)
1853 reg
= DSPCNTR(plane
);
1854 val
= I915_READ(reg
);
1855 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1858 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1859 intel_flush_display_plane(dev_priv
, plane
);
1860 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1863 static void disable_pch_dp(struct drm_i915_private
*dev_priv
,
1864 enum pipe pipe
, int reg
, u32 port_sel
)
1866 u32 val
= I915_READ(reg
);
1867 if (dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
)) {
1868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg
, pipe
);
1869 I915_WRITE(reg
, val
& ~DP_PORT_EN
);
1873 static void disable_pch_hdmi(struct drm_i915_private
*dev_priv
,
1874 enum pipe pipe
, int reg
)
1876 u32 val
= I915_READ(reg
);
1877 if (hdmi_pipe_enabled(dev_priv
, pipe
, val
)) {
1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1880 I915_WRITE(reg
, val
& ~PORT_ENABLE
);
1884 /* Disable any ports connected to this transcoder */
1885 static void intel_disable_pch_ports(struct drm_i915_private
*dev_priv
,
1890 val
= I915_READ(PCH_PP_CONTROL
);
1891 I915_WRITE(PCH_PP_CONTROL
, val
| PANEL_UNLOCK_REGS
);
1893 disable_pch_dp(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1894 disable_pch_dp(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1895 disable_pch_dp(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1898 val
= I915_READ(reg
);
1899 if (adpa_pipe_enabled(dev_priv
, pipe
, val
))
1900 I915_WRITE(reg
, val
& ~ADPA_DAC_ENABLE
);
1903 val
= I915_READ(reg
);
1904 if (lvds_pipe_enabled(dev_priv
, pipe
, val
)) {
1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe
, val
);
1906 I915_WRITE(reg
, val
& ~LVDS_PORT_EN
);
1911 disable_pch_hdmi(dev_priv
, pipe
, HDMIB
);
1912 disable_pch_hdmi(dev_priv
, pipe
, HDMIC
);
1913 disable_pch_hdmi(dev_priv
, pipe
, HDMID
);
1917 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1918 struct drm_i915_gem_object
*obj
,
1919 struct intel_ring_buffer
*pipelined
)
1921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1925 switch (obj
->tiling_mode
) {
1926 case I915_TILING_NONE
:
1927 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1928 alignment
= 128 * 1024;
1929 else if (INTEL_INFO(dev
)->gen
>= 4)
1930 alignment
= 4 * 1024;
1932 alignment
= 64 * 1024;
1935 /* pin() will align the object as required by fence */
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1946 dev_priv
->mm
.interruptible
= false;
1947 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1949 goto err_interruptible
;
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1956 ret
= i915_gem_object_get_fence(obj
);
1960 i915_gem_object_pin_fence(obj
);
1962 dev_priv
->mm
.interruptible
= true;
1966 i915_gem_object_unpin(obj
);
1968 dev_priv
->mm
.interruptible
= true;
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1974 i915_gem_object_unpin_fence(obj
);
1975 i915_gem_object_unpin(obj
);
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x
, int *y
,
1984 int tile_rows
, tiles
;
1988 tiles
= *x
/ (512/bpp
);
1991 return tile_rows
* pitch
* 8 + tiles
* 4096;
1994 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1997 struct drm_device
*dev
= crtc
->dev
;
1998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1999 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2000 struct intel_framebuffer
*intel_fb
;
2001 struct drm_i915_gem_object
*obj
;
2002 int plane
= intel_crtc
->plane
;
2003 unsigned long linear_offset
;
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2016 intel_fb
= to_intel_framebuffer(fb
);
2017 obj
= intel_fb
->obj
;
2019 reg
= DSPCNTR(plane
);
2020 dspcntr
= I915_READ(reg
);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2023 switch (fb
->bits_per_pixel
) {
2025 dspcntr
|= DISPPLANE_8BPP
;
2028 if (fb
->depth
== 15)
2029 dspcntr
|= DISPPLANE_15_16BPP
;
2031 dspcntr
|= DISPPLANE_16BPP
;
2035 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2038 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2041 if (INTEL_INFO(dev
)->gen
>= 4) {
2042 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2043 dspcntr
|= DISPPLANE_TILED
;
2045 dspcntr
&= ~DISPPLANE_TILED
;
2048 I915_WRITE(reg
, dspcntr
);
2050 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2052 if (INTEL_INFO(dev
)->gen
>= 4) {
2053 intel_crtc
->dspaddr_offset
=
2054 gen4_compute_dspaddr_offset_xtiled(&x
, &y
,
2055 fb
->bits_per_pixel
/ 8,
2057 linear_offset
-= intel_crtc
->dspaddr_offset
;
2059 intel_crtc
->dspaddr_offset
= linear_offset
;
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2064 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2065 if (INTEL_INFO(dev
)->gen
>= 4) {
2066 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2067 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2068 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2069 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2071 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2077 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2078 struct drm_framebuffer
*fb
, int x
, int y
)
2080 struct drm_device
*dev
= crtc
->dev
;
2081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2082 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2083 struct intel_framebuffer
*intel_fb
;
2084 struct drm_i915_gem_object
*obj
;
2085 int plane
= intel_crtc
->plane
;
2086 unsigned long linear_offset
;
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2100 intel_fb
= to_intel_framebuffer(fb
);
2101 obj
= intel_fb
->obj
;
2103 reg
= DSPCNTR(plane
);
2104 dspcntr
= I915_READ(reg
);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2107 switch (fb
->bits_per_pixel
) {
2109 dspcntr
|= DISPPLANE_8BPP
;
2112 if (fb
->depth
!= 16)
2115 dspcntr
|= DISPPLANE_16BPP
;
2119 if (fb
->depth
== 24)
2120 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2121 else if (fb
->depth
== 30)
2122 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
2127 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2131 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2132 dspcntr
|= DISPPLANE_TILED
;
2134 dspcntr
&= ~DISPPLANE_TILED
;
2137 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2139 I915_WRITE(reg
, dspcntr
);
2141 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2142 intel_crtc
->dspaddr_offset
=
2143 gen4_compute_dspaddr_offset_xtiled(&x
, &y
,
2144 fb
->bits_per_pixel
/ 8,
2146 linear_offset
-= intel_crtc
->dspaddr_offset
;
2148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2150 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2151 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2152 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2153 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2154 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2162 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2163 int x
, int y
, enum mode_set_atomic state
)
2165 struct drm_device
*dev
= crtc
->dev
;
2166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2168 if (dev_priv
->display
.disable_fbc
)
2169 dev_priv
->display
.disable_fbc(dev
);
2170 intel_increase_pllclock(crtc
);
2172 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2176 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2178 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2179 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2180 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2183 wait_event(dev_priv
->pending_flip_queue
,
2184 atomic_read(&dev_priv
->mm
.wedged
) ||
2185 atomic_read(&obj
->pending_flip
) == 0);
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2195 dev_priv
->mm
.interruptible
= false;
2196 ret
= i915_gem_object_finish_gpu(obj
);
2197 dev_priv
->mm
.interruptible
= was_interruptible
;
2203 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2204 struct drm_framebuffer
*old_fb
)
2206 struct drm_device
*dev
= crtc
->dev
;
2207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2208 struct drm_i915_master_private
*master_priv
;
2209 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2214 DRM_ERROR("No FB bound\n");
2218 if(intel_crtc
->plane
> dev_priv
->num_pipe
) {
2219 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2221 dev_priv
->num_pipe
);
2225 mutex_lock(&dev
->struct_mutex
);
2226 ret
= intel_pin_and_fence_fb_obj(dev
,
2227 to_intel_framebuffer(crtc
->fb
)->obj
,
2230 mutex_unlock(&dev
->struct_mutex
);
2231 DRM_ERROR("pin & fence failed\n");
2236 intel_finish_fb(old_fb
);
2238 ret
= dev_priv
->display
.update_plane(crtc
, crtc
->fb
, x
, y
);
2240 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
2241 mutex_unlock(&dev
->struct_mutex
);
2242 DRM_ERROR("failed to update base address\n");
2247 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2248 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2251 intel_update_fbc(dev
);
2252 mutex_unlock(&dev
->struct_mutex
);
2254 if (!dev
->primary
->master
)
2257 master_priv
= dev
->primary
->master
->driver_priv
;
2258 if (!master_priv
->sarea_priv
)
2261 if (intel_crtc
->pipe
) {
2262 master_priv
->sarea_priv
->pipeB_x
= x
;
2263 master_priv
->sarea_priv
->pipeB_y
= y
;
2265 master_priv
->sarea_priv
->pipeA_x
= x
;
2266 master_priv
->sarea_priv
->pipeA_y
= y
;
2272 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2274 struct drm_device
*dev
= crtc
->dev
;
2275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2278 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2279 dpa_ctl
= I915_READ(DP_A
);
2280 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2282 if (clock
< 200000) {
2284 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2285 /* workaround for 160Mhz:
2286 1) program 0x4600c bits 15:0 = 0x8124
2287 2) program 0x46010 bit 0 = 1
2288 3) program 0x46034 bit 24 = 1
2289 4) program 0x64000 bit 14 = 1
2291 temp
= I915_READ(0x4600c);
2293 I915_WRITE(0x4600c, temp
| 0x8124);
2295 temp
= I915_READ(0x46010);
2296 I915_WRITE(0x46010, temp
| 1);
2298 temp
= I915_READ(0x46034);
2299 I915_WRITE(0x46034, temp
| (1 << 24));
2301 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2303 I915_WRITE(DP_A
, dpa_ctl
);
2309 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2311 struct drm_device
*dev
= crtc
->dev
;
2312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2313 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2314 int pipe
= intel_crtc
->pipe
;
2317 /* enable normal train */
2318 reg
= FDI_TX_CTL(pipe
);
2319 temp
= I915_READ(reg
);
2320 if (IS_IVYBRIDGE(dev
)) {
2321 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2322 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2324 temp
&= ~FDI_LINK_TRAIN_NONE
;
2325 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2327 I915_WRITE(reg
, temp
);
2329 reg
= FDI_RX_CTL(pipe
);
2330 temp
= I915_READ(reg
);
2331 if (HAS_PCH_CPT(dev
)) {
2332 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2333 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2335 temp
&= ~FDI_LINK_TRAIN_NONE
;
2336 temp
|= FDI_LINK_TRAIN_NONE
;
2338 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2340 /* wait one idle pattern time */
2344 /* IVB wants error correction enabled */
2345 if (IS_IVYBRIDGE(dev
))
2346 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2347 FDI_FE_ERRC_ENABLE
);
2350 static void cpt_phase_pointer_enable(struct drm_device
*dev
, int pipe
)
2352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2353 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2355 flags
|= FDI_PHASE_SYNC_OVR(pipe
);
2356 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to unlock... */
2357 flags
|= FDI_PHASE_SYNC_EN(pipe
);
2358 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to enable */
2359 POSTING_READ(SOUTH_CHICKEN1
);
2362 /* The FDI link training functions for ILK/Ibexpeak. */
2363 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2365 struct drm_device
*dev
= crtc
->dev
;
2366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2368 int pipe
= intel_crtc
->pipe
;
2369 int plane
= intel_crtc
->plane
;
2370 u32 reg
, temp
, tries
;
2372 /* FDI needs bits from pipe & plane first */
2373 assert_pipe_enabled(dev_priv
, pipe
);
2374 assert_plane_enabled(dev_priv
, plane
);
2376 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2378 reg
= FDI_RX_IMR(pipe
);
2379 temp
= I915_READ(reg
);
2380 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2381 temp
&= ~FDI_RX_BIT_LOCK
;
2382 I915_WRITE(reg
, temp
);
2386 /* enable CPU FDI TX and PCH FDI RX */
2387 reg
= FDI_TX_CTL(pipe
);
2388 temp
= I915_READ(reg
);
2390 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2391 temp
&= ~FDI_LINK_TRAIN_NONE
;
2392 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2393 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2395 reg
= FDI_RX_CTL(pipe
);
2396 temp
= I915_READ(reg
);
2397 temp
&= ~FDI_LINK_TRAIN_NONE
;
2398 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2399 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2404 /* Ironlake workaround, enable clock pointer after FDI enable*/
2405 if (HAS_PCH_IBX(dev
)) {
2406 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2407 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2408 FDI_RX_PHASE_SYNC_POINTER_EN
);
2411 reg
= FDI_RX_IIR(pipe
);
2412 for (tries
= 0; tries
< 5; tries
++) {
2413 temp
= I915_READ(reg
);
2414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2416 if ((temp
& FDI_RX_BIT_LOCK
)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
2418 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2423 DRM_ERROR("FDI train 1 fail!\n");
2426 reg
= FDI_TX_CTL(pipe
);
2427 temp
= I915_READ(reg
);
2428 temp
&= ~FDI_LINK_TRAIN_NONE
;
2429 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2430 I915_WRITE(reg
, temp
);
2432 reg
= FDI_RX_CTL(pipe
);
2433 temp
= I915_READ(reg
);
2434 temp
&= ~FDI_LINK_TRAIN_NONE
;
2435 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2436 I915_WRITE(reg
, temp
);
2441 reg
= FDI_RX_IIR(pipe
);
2442 for (tries
= 0; tries
< 5; tries
++) {
2443 temp
= I915_READ(reg
);
2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2446 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2447 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2453 DRM_ERROR("FDI train 2 fail!\n");
2455 DRM_DEBUG_KMS("FDI train done\n");
2459 static const int snb_b_fdi_train_param
[] = {
2460 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2466 /* The FDI link training functions for SNB/Cougarpoint. */
2467 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2469 struct drm_device
*dev
= crtc
->dev
;
2470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2471 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2472 int pipe
= intel_crtc
->pipe
;
2473 u32 reg
, temp
, i
, retry
;
2475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2477 reg
= FDI_RX_IMR(pipe
);
2478 temp
= I915_READ(reg
);
2479 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2480 temp
&= ~FDI_RX_BIT_LOCK
;
2481 I915_WRITE(reg
, temp
);
2486 /* enable CPU FDI TX and PCH FDI RX */
2487 reg
= FDI_TX_CTL(pipe
);
2488 temp
= I915_READ(reg
);
2490 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2491 temp
&= ~FDI_LINK_TRAIN_NONE
;
2492 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2493 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2495 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2496 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2498 reg
= FDI_RX_CTL(pipe
);
2499 temp
= I915_READ(reg
);
2500 if (HAS_PCH_CPT(dev
)) {
2501 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2502 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2504 temp
&= ~FDI_LINK_TRAIN_NONE
;
2505 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2507 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2512 if (HAS_PCH_CPT(dev
))
2513 cpt_phase_pointer_enable(dev
, pipe
);
2515 for (i
= 0; i
< 4; i
++) {
2516 reg
= FDI_TX_CTL(pipe
);
2517 temp
= I915_READ(reg
);
2518 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2519 temp
|= snb_b_fdi_train_param
[i
];
2520 I915_WRITE(reg
, temp
);
2525 for (retry
= 0; retry
< 5; retry
++) {
2526 reg
= FDI_RX_IIR(pipe
);
2527 temp
= I915_READ(reg
);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2529 if (temp
& FDI_RX_BIT_LOCK
) {
2530 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2540 DRM_ERROR("FDI train 1 fail!\n");
2543 reg
= FDI_TX_CTL(pipe
);
2544 temp
= I915_READ(reg
);
2545 temp
&= ~FDI_LINK_TRAIN_NONE
;
2546 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2548 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2550 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2552 I915_WRITE(reg
, temp
);
2554 reg
= FDI_RX_CTL(pipe
);
2555 temp
= I915_READ(reg
);
2556 if (HAS_PCH_CPT(dev
)) {
2557 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2558 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2560 temp
&= ~FDI_LINK_TRAIN_NONE
;
2561 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2563 I915_WRITE(reg
, temp
);
2568 for (i
= 0; i
< 4; i
++) {
2569 reg
= FDI_TX_CTL(pipe
);
2570 temp
= I915_READ(reg
);
2571 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2572 temp
|= snb_b_fdi_train_param
[i
];
2573 I915_WRITE(reg
, temp
);
2578 for (retry
= 0; retry
< 5; retry
++) {
2579 reg
= FDI_RX_IIR(pipe
);
2580 temp
= I915_READ(reg
);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2582 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2583 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2593 DRM_ERROR("FDI train 2 fail!\n");
2595 DRM_DEBUG_KMS("FDI train done.\n");
2598 /* Manual link training for Ivy Bridge A0 parts */
2599 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2601 struct drm_device
*dev
= crtc
->dev
;
2602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2603 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2604 int pipe
= intel_crtc
->pipe
;
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2609 reg
= FDI_RX_IMR(pipe
);
2610 temp
= I915_READ(reg
);
2611 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2612 temp
&= ~FDI_RX_BIT_LOCK
;
2613 I915_WRITE(reg
, temp
);
2618 /* enable CPU FDI TX and PCH FDI RX */
2619 reg
= FDI_TX_CTL(pipe
);
2620 temp
= I915_READ(reg
);
2622 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2623 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2624 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2625 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2626 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2627 temp
|= FDI_COMPOSITE_SYNC
;
2628 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2630 reg
= FDI_RX_CTL(pipe
);
2631 temp
= I915_READ(reg
);
2632 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2633 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2634 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2635 temp
|= FDI_COMPOSITE_SYNC
;
2636 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2641 if (HAS_PCH_CPT(dev
))
2642 cpt_phase_pointer_enable(dev
, pipe
);
2644 for (i
= 0; i
< 4; i
++) {
2645 reg
= FDI_TX_CTL(pipe
);
2646 temp
= I915_READ(reg
);
2647 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2648 temp
|= snb_b_fdi_train_param
[i
];
2649 I915_WRITE(reg
, temp
);
2654 reg
= FDI_RX_IIR(pipe
);
2655 temp
= I915_READ(reg
);
2656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2658 if (temp
& FDI_RX_BIT_LOCK
||
2659 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2660 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2666 DRM_ERROR("FDI train 1 fail!\n");
2669 reg
= FDI_TX_CTL(pipe
);
2670 temp
= I915_READ(reg
);
2671 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2672 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2673 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2674 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2675 I915_WRITE(reg
, temp
);
2677 reg
= FDI_RX_CTL(pipe
);
2678 temp
= I915_READ(reg
);
2679 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2680 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2681 I915_WRITE(reg
, temp
);
2686 for (i
= 0; i
< 4; i
++) {
2687 reg
= FDI_TX_CTL(pipe
);
2688 temp
= I915_READ(reg
);
2689 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2690 temp
|= snb_b_fdi_train_param
[i
];
2691 I915_WRITE(reg
, temp
);
2696 reg
= FDI_RX_IIR(pipe
);
2697 temp
= I915_READ(reg
);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2700 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2701 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2702 DRM_DEBUG_KMS("FDI train 2 done.\n");
2707 DRM_ERROR("FDI train 2 fail!\n");
2709 DRM_DEBUG_KMS("FDI train done.\n");
2712 static void ironlake_fdi_pll_enable(struct drm_crtc
*crtc
)
2714 struct drm_device
*dev
= crtc
->dev
;
2715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2716 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2717 int pipe
= intel_crtc
->pipe
;
2720 /* Write the TU size bits so error detection works */
2721 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2722 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2724 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2725 reg
= FDI_RX_CTL(pipe
);
2726 temp
= I915_READ(reg
);
2727 temp
&= ~((0x7 << 19) | (0x7 << 16));
2728 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2729 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2730 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2735 /* Switch from Rawclk to PCDclk */
2736 temp
= I915_READ(reg
);
2737 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2742 /* On Haswell, the PLL configuration for ports and pipes is handled
2743 * separately, as part of DDI setup */
2744 if (!IS_HASWELL(dev
)) {
2745 /* Enable CPU FDI TX PLL, always on for Ironlake */
2746 reg
= FDI_TX_CTL(pipe
);
2747 temp
= I915_READ(reg
);
2748 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2749 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2757 static void cpt_phase_pointer_disable(struct drm_device
*dev
, int pipe
)
2759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2760 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2762 flags
&= ~(FDI_PHASE_SYNC_EN(pipe
));
2763 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to disable... */
2764 flags
&= ~(FDI_PHASE_SYNC_OVR(pipe
));
2765 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to lock */
2766 POSTING_READ(SOUTH_CHICKEN1
);
2768 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2770 struct drm_device
*dev
= crtc
->dev
;
2771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2772 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2773 int pipe
= intel_crtc
->pipe
;
2776 /* disable CPU FDI tx and PCH FDI rx */
2777 reg
= FDI_TX_CTL(pipe
);
2778 temp
= I915_READ(reg
);
2779 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2782 reg
= FDI_RX_CTL(pipe
);
2783 temp
= I915_READ(reg
);
2784 temp
&= ~(0x7 << 16);
2785 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2786 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2791 /* Ironlake workaround, disable clock pointer after downing FDI */
2792 if (HAS_PCH_IBX(dev
)) {
2793 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2794 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2795 I915_READ(FDI_RX_CHICKEN(pipe
) &
2796 ~FDI_RX_PHASE_SYNC_POINTER_EN
));
2797 } else if (HAS_PCH_CPT(dev
)) {
2798 cpt_phase_pointer_disable(dev
, pipe
);
2801 /* still set train pattern 1 */
2802 reg
= FDI_TX_CTL(pipe
);
2803 temp
= I915_READ(reg
);
2804 temp
&= ~FDI_LINK_TRAIN_NONE
;
2805 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2806 I915_WRITE(reg
, temp
);
2808 reg
= FDI_RX_CTL(pipe
);
2809 temp
= I915_READ(reg
);
2810 if (HAS_PCH_CPT(dev
)) {
2811 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2812 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2814 temp
&= ~FDI_LINK_TRAIN_NONE
;
2815 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2817 /* BPC in FDI rx is consistent with that in PIPECONF */
2818 temp
&= ~(0x07 << 16);
2819 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2820 I915_WRITE(reg
, temp
);
2826 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2828 struct drm_device
*dev
= crtc
->dev
;
2830 if (crtc
->fb
== NULL
)
2833 mutex_lock(&dev
->struct_mutex
);
2834 intel_finish_fb(crtc
->fb
);
2835 mutex_unlock(&dev
->struct_mutex
);
2838 static bool intel_crtc_driving_pch(struct drm_crtc
*crtc
)
2840 struct drm_device
*dev
= crtc
->dev
;
2841 struct intel_encoder
*encoder
;
2844 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2845 * must be driven by its own crtc; no sharing is possible.
2847 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
2849 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2850 * CPU handles all others */
2851 if (IS_HASWELL(dev
)) {
2852 /* It is still unclear how this will work on PPT, so throw up a warning */
2853 WARN_ON(!HAS_PCH_LPT(dev
));
2855 if (encoder
->type
== DRM_MODE_ENCODER_DAC
) {
2856 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2859 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2865 switch (encoder
->type
) {
2866 case INTEL_OUTPUT_EDP
:
2867 if (!intel_encoder_is_pch_edp(&encoder
->base
))
2876 /* Program iCLKIP clock to the desired frequency */
2877 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2879 struct drm_device
*dev
= crtc
->dev
;
2880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2881 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2884 /* It is necessary to ungate the pixclk gate prior to programming
2885 * the divisors, and gate it back when it is done.
2887 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2889 /* Disable SSCCTL */
2890 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2891 intel_sbi_read(dev_priv
, SBI_SSCCTL6
) |
2892 SBI_SSCCTL_DISABLE
);
2894 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2895 if (crtc
->mode
.clock
== 20000) {
2900 /* The iCLK virtual clock root frequency is in MHz,
2901 * but the crtc->mode.clock in in KHz. To get the divisors,
2902 * it is necessary to divide one by another, so we
2903 * convert the virtual clock precision to KHz here for higher
2906 u32 iclk_virtual_root_freq
= 172800 * 1000;
2907 u32 iclk_pi_range
= 64;
2908 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2910 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2911 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2912 pi_value
= desired_divisor
% iclk_pi_range
;
2915 divsel
= msb_divisor_value
- 2;
2916 phaseinc
= pi_value
;
2919 /* This should not happen with any sane values */
2920 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2921 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2922 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2923 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2925 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2932 /* Program SSCDIVINTPHASE6 */
2933 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
);
2934 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2935 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2936 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2937 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2938 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2939 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2941 intel_sbi_write(dev_priv
,
2942 SBI_SSCDIVINTPHASE6
,
2945 /* Program SSCAUXDIV */
2946 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
);
2947 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2948 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2949 intel_sbi_write(dev_priv
,
2954 /* Enable modulator and associated divider */
2955 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
);
2956 temp
&= ~SBI_SSCCTL_DISABLE
;
2957 intel_sbi_write(dev_priv
,
2961 /* Wait for initialization time */
2964 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2968 * Enable PCH resources required for PCH ports:
2970 * - FDI training & RX/TX
2971 * - update transcoder timings
2972 * - DP transcoding bits
2975 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2977 struct drm_device
*dev
= crtc
->dev
;
2978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2979 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2980 int pipe
= intel_crtc
->pipe
;
2983 assert_transcoder_disabled(dev_priv
, pipe
);
2985 /* For PCH output, training FDI link */
2986 dev_priv
->display
.fdi_link_train(crtc
);
2988 intel_enable_pch_pll(intel_crtc
);
2990 if (HAS_PCH_LPT(dev
)) {
2991 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2992 lpt_program_iclkip(crtc
);
2993 } else if (HAS_PCH_CPT(dev
)) {
2996 temp
= I915_READ(PCH_DPLL_SEL
);
3000 temp
|= TRANSA_DPLL_ENABLE
;
3001 sel
= TRANSA_DPLLB_SEL
;
3004 temp
|= TRANSB_DPLL_ENABLE
;
3005 sel
= TRANSB_DPLLB_SEL
;
3008 temp
|= TRANSC_DPLL_ENABLE
;
3009 sel
= TRANSC_DPLLB_SEL
;
3012 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
3016 I915_WRITE(PCH_DPLL_SEL
, temp
);
3019 /* set transcoder timing, panel must allow it */
3020 assert_panel_unlocked(dev_priv
, pipe
);
3021 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3022 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3023 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3025 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3026 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3027 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3028 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3030 if (!IS_HASWELL(dev
))
3031 intel_fdi_normal_train(crtc
);
3033 /* For PCH DP, enable TRANS_DP_CTL */
3034 if (HAS_PCH_CPT(dev
) &&
3035 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3036 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3037 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) >> 5;
3038 reg
= TRANS_DP_CTL(pipe
);
3039 temp
= I915_READ(reg
);
3040 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3041 TRANS_DP_SYNC_MASK
|
3043 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3044 TRANS_DP_ENH_FRAMING
);
3045 temp
|= bpc
<< 9; /* same format but at 11:9 */
3047 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3048 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3049 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3050 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3052 switch (intel_trans_dp_port_sel(crtc
)) {
3054 temp
|= TRANS_DP_PORT_SEL_B
;
3057 temp
|= TRANS_DP_PORT_SEL_C
;
3060 temp
|= TRANS_DP_PORT_SEL_D
;
3063 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3064 temp
|= TRANS_DP_PORT_SEL_B
;
3068 I915_WRITE(reg
, temp
);
3071 intel_enable_transcoder(dev_priv
, pipe
);
3074 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3076 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3081 if (pll
->refcount
== 0) {
3082 WARN(1, "bad PCH PLL refcount\n");
3087 intel_crtc
->pch_pll
= NULL
;
3090 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3092 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3093 struct intel_pch_pll
*pll
;
3096 pll
= intel_crtc
->pch_pll
;
3098 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3099 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3103 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3104 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3105 i
= intel_crtc
->pipe
;
3106 pll
= &dev_priv
->pch_plls
[i
];
3108 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3109 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3114 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3115 pll
= &dev_priv
->pch_plls
[i
];
3117 /* Only want to check enabled timings first */
3118 if (pll
->refcount
== 0)
3121 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3122 fp
== I915_READ(pll
->fp0_reg
)) {
3123 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3124 intel_crtc
->base
.base
.id
,
3125 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3131 /* Ok no matching timings, maybe there's a free one? */
3132 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3133 pll
= &dev_priv
->pch_plls
[i
];
3134 if (pll
->refcount
== 0) {
3135 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3136 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3144 intel_crtc
->pch_pll
= pll
;
3146 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3147 prepare
: /* separate function? */
3148 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3150 /* Wait for the clocks to stabilize before rewriting the regs */
3151 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3152 POSTING_READ(pll
->pll_reg
);
3155 I915_WRITE(pll
->fp0_reg
, fp
);
3156 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3161 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3164 int dslreg
= PIPEDSL(pipe
), tc2reg
= TRANS_CHICKEN2(pipe
);
3167 temp
= I915_READ(dslreg
);
3169 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3170 /* Without this, mode sets may fail silently on FDI */
3171 I915_WRITE(tc2reg
, TRANS_AUTOTRAIN_GEN_STALL_DIS
);
3173 I915_WRITE(tc2reg
, 0);
3174 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3175 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3179 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3181 struct drm_device
*dev
= crtc
->dev
;
3182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3183 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3184 int pipe
= intel_crtc
->pipe
;
3185 int plane
= intel_crtc
->plane
;
3189 if (intel_crtc
->active
)
3192 intel_crtc
->active
= true;
3193 intel_update_watermarks(dev
);
3195 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3196 temp
= I915_READ(PCH_LVDS
);
3197 if ((temp
& LVDS_PORT_EN
) == 0)
3198 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3201 is_pch_port
= intel_crtc_driving_pch(crtc
);
3204 ironlake_fdi_pll_enable(crtc
);
3206 ironlake_fdi_disable(crtc
);
3208 /* Enable panel fitting for LVDS */
3209 if (dev_priv
->pch_pf_size
&&
3210 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
3211 /* Force use of hard-coded filter coefficients
3212 * as some pre-programmed values are broken,
3215 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3216 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3217 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3221 * On ILK+ LUT must be loaded before the pipe is running but with
3224 intel_crtc_load_lut(crtc
);
3226 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3227 intel_enable_plane(dev_priv
, plane
, pipe
);
3230 ironlake_pch_enable(crtc
);
3232 mutex_lock(&dev
->struct_mutex
);
3233 intel_update_fbc(dev
);
3234 mutex_unlock(&dev
->struct_mutex
);
3236 intel_crtc_update_cursor(crtc
, true);
3239 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3241 struct drm_device
*dev
= crtc
->dev
;
3242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3243 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3244 int pipe
= intel_crtc
->pipe
;
3245 int plane
= intel_crtc
->plane
;
3248 if (!intel_crtc
->active
)
3251 intel_crtc_wait_for_pending_flips(crtc
);
3252 drm_vblank_off(dev
, pipe
);
3253 intel_crtc_update_cursor(crtc
, false);
3255 intel_disable_plane(dev_priv
, plane
, pipe
);
3257 if (dev_priv
->cfb_plane
== plane
)
3258 intel_disable_fbc(dev
);
3260 intel_disable_pipe(dev_priv
, pipe
);
3263 I915_WRITE(PF_CTL(pipe
), 0);
3264 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3266 ironlake_fdi_disable(crtc
);
3268 /* This is a horrible layering violation; we should be doing this in
3269 * the connector/encoder ->prepare instead, but we don't always have
3270 * enough information there about the config to know whether it will
3271 * actually be necessary or just cause undesired flicker.
3273 intel_disable_pch_ports(dev_priv
, pipe
);
3275 intel_disable_transcoder(dev_priv
, pipe
);
3277 if (HAS_PCH_CPT(dev
)) {
3278 /* disable TRANS_DP_CTL */
3279 reg
= TRANS_DP_CTL(pipe
);
3280 temp
= I915_READ(reg
);
3281 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3282 temp
|= TRANS_DP_PORT_SEL_NONE
;
3283 I915_WRITE(reg
, temp
);
3285 /* disable DPLL_SEL */
3286 temp
= I915_READ(PCH_DPLL_SEL
);
3289 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3292 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3295 /* C shares PLL A or B */
3296 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3301 I915_WRITE(PCH_DPLL_SEL
, temp
);
3304 /* disable PCH DPLL */
3305 intel_disable_pch_pll(intel_crtc
);
3307 /* Switch from PCDclk to Rawclk */
3308 reg
= FDI_RX_CTL(pipe
);
3309 temp
= I915_READ(reg
);
3310 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3312 /* Disable CPU FDI TX PLL */
3313 reg
= FDI_TX_CTL(pipe
);
3314 temp
= I915_READ(reg
);
3315 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3320 reg
= FDI_RX_CTL(pipe
);
3321 temp
= I915_READ(reg
);
3322 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3324 /* Wait for the clocks to turn off. */
3328 intel_crtc
->active
= false;
3329 intel_update_watermarks(dev
);
3331 mutex_lock(&dev
->struct_mutex
);
3332 intel_update_fbc(dev
);
3333 mutex_unlock(&dev
->struct_mutex
);
3336 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3338 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3339 int pipe
= intel_crtc
->pipe
;
3340 int plane
= intel_crtc
->plane
;
3342 /* XXX: When our outputs are all unaware of DPMS modes other than off
3343 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3346 case DRM_MODE_DPMS_ON
:
3347 case DRM_MODE_DPMS_STANDBY
:
3348 case DRM_MODE_DPMS_SUSPEND
:
3349 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe
, plane
);
3350 ironlake_crtc_enable(crtc
);
3353 case DRM_MODE_DPMS_OFF
:
3354 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe
, plane
);
3355 ironlake_crtc_disable(crtc
);
3360 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3362 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3363 intel_put_pch_pll(intel_crtc
);
3366 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3368 if (!enable
&& intel_crtc
->overlay
) {
3369 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3372 mutex_lock(&dev
->struct_mutex
);
3373 dev_priv
->mm
.interruptible
= false;
3374 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3375 dev_priv
->mm
.interruptible
= true;
3376 mutex_unlock(&dev
->struct_mutex
);
3379 /* Let userspace switch the overlay on again. In most cases userspace
3380 * has to recompute where to put it anyway.
3384 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3386 struct drm_device
*dev
= crtc
->dev
;
3387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3388 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3389 int pipe
= intel_crtc
->pipe
;
3390 int plane
= intel_crtc
->plane
;
3392 if (intel_crtc
->active
)
3395 intel_crtc
->active
= true;
3396 intel_update_watermarks(dev
);
3398 intel_enable_pll(dev_priv
, pipe
);
3399 intel_enable_pipe(dev_priv
, pipe
, false);
3400 intel_enable_plane(dev_priv
, plane
, pipe
);
3402 intel_crtc_load_lut(crtc
);
3403 intel_update_fbc(dev
);
3405 /* Give the overlay scaler a chance to enable if it's on this pipe */
3406 intel_crtc_dpms_overlay(intel_crtc
, true);
3407 intel_crtc_update_cursor(crtc
, true);
3410 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3412 struct drm_device
*dev
= crtc
->dev
;
3413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3414 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3415 int pipe
= intel_crtc
->pipe
;
3416 int plane
= intel_crtc
->plane
;
3418 if (!intel_crtc
->active
)
3421 /* Give the overlay scaler a chance to disable if it's on this pipe */
3422 intel_crtc_wait_for_pending_flips(crtc
);
3423 drm_vblank_off(dev
, pipe
);
3424 intel_crtc_dpms_overlay(intel_crtc
, false);
3425 intel_crtc_update_cursor(crtc
, false);
3427 if (dev_priv
->cfb_plane
== plane
)
3428 intel_disable_fbc(dev
);
3430 intel_disable_plane(dev_priv
, plane
, pipe
);
3431 intel_disable_pipe(dev_priv
, pipe
);
3432 intel_disable_pll(dev_priv
, pipe
);
3434 intel_crtc
->active
= false;
3435 intel_update_fbc(dev
);
3436 intel_update_watermarks(dev
);
3439 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3441 /* XXX: When our outputs are all unaware of DPMS modes other than off
3442 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3445 case DRM_MODE_DPMS_ON
:
3446 case DRM_MODE_DPMS_STANDBY
:
3447 case DRM_MODE_DPMS_SUSPEND
:
3448 i9xx_crtc_enable(crtc
);
3450 case DRM_MODE_DPMS_OFF
:
3451 i9xx_crtc_disable(crtc
);
3456 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3461 * Sets the power management mode of the pipe and plane.
3463 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3465 struct drm_device
*dev
= crtc
->dev
;
3466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3467 struct drm_i915_master_private
*master_priv
;
3468 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3469 int pipe
= intel_crtc
->pipe
;
3472 if (intel_crtc
->dpms_mode
== mode
)
3475 intel_crtc
->dpms_mode
= mode
;
3477 dev_priv
->display
.dpms(crtc
, mode
);
3479 if (!dev
->primary
->master
)
3482 master_priv
= dev
->primary
->master
->driver_priv
;
3483 if (!master_priv
->sarea_priv
)
3486 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
3490 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3491 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3494 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3495 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3498 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3503 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3505 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
3506 struct drm_device
*dev
= crtc
->dev
;
3507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3509 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
3510 dev_priv
->display
.off(crtc
);
3512 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3513 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3516 mutex_lock(&dev
->struct_mutex
);
3517 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3518 mutex_unlock(&dev
->struct_mutex
);
3522 /* Prepare for a mode set.
3524 * Note we could be a lot smarter here. We need to figure out which outputs
3525 * will be enabled, which disabled (in short, how the config will changes)
3526 * and perform the minimum necessary steps to accomplish that, e.g. updating
3527 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3528 * panel fitting is in the proper state, etc.
3530 static void i9xx_crtc_prepare(struct drm_crtc
*crtc
)
3532 i9xx_crtc_disable(crtc
);
3535 static void i9xx_crtc_commit(struct drm_crtc
*crtc
)
3537 i9xx_crtc_enable(crtc
);
3540 static void ironlake_crtc_prepare(struct drm_crtc
*crtc
)
3542 ironlake_crtc_disable(crtc
);
3545 static void ironlake_crtc_commit(struct drm_crtc
*crtc
)
3547 ironlake_crtc_enable(crtc
);
3550 void intel_encoder_prepare(struct drm_encoder
*encoder
)
3552 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3553 /* lvds has its own version of prepare see intel_lvds_prepare */
3554 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
3557 void intel_encoder_commit(struct drm_encoder
*encoder
)
3559 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3560 struct drm_device
*dev
= encoder
->dev
;
3561 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
3563 /* lvds has its own version of commit see intel_lvds_commit */
3564 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
3566 if (HAS_PCH_CPT(dev
))
3567 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3570 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3572 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3574 drm_encoder_cleanup(encoder
);
3575 kfree(intel_encoder
);
3578 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3579 const struct drm_display_mode
*mode
,
3580 struct drm_display_mode
*adjusted_mode
)
3582 struct drm_device
*dev
= crtc
->dev
;
3584 if (HAS_PCH_SPLIT(dev
)) {
3585 /* FDI link clock is fixed at 2.7G */
3586 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3590 /* All interlaced capable intel hw wants timings in frames. Note though
3591 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3592 * timings, so we need to be careful not to clobber these.*/
3593 if (!(adjusted_mode
->private_flags
& INTEL_MODE_CRTC_TIMINGS_SET
))
3594 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3599 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3601 return 400000; /* FIXME */
3604 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3609 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3614 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3619 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3623 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3625 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3628 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3629 case GC_DISPLAY_CLOCK_333_MHZ
:
3632 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3638 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3643 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3646 /* Assume that the hardware is in the high speed state. This
3647 * should be the default.
3649 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3650 case GC_CLOCK_133_200
:
3651 case GC_CLOCK_100_200
:
3653 case GC_CLOCK_166_250
:
3655 case GC_CLOCK_100_133
:
3659 /* Shouldn't happen */
3663 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3677 fdi_reduce_ratio(u32
*num
, u32
*den
)
3679 while (*num
> 0xffffff || *den
> 0xffffff) {
3686 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
3687 int link_clock
, struct fdi_m_n
*m_n
)
3689 m_n
->tu
= 64; /* default size */
3691 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3692 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3693 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3694 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3696 m_n
->link_m
= pixel_clock
;
3697 m_n
->link_n
= link_clock
;
3698 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3701 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
3703 if (i915_panel_use_ssc
>= 0)
3704 return i915_panel_use_ssc
!= 0;
3705 return dev_priv
->lvds_use_ssc
3706 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
3710 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3711 * @crtc: CRTC structure
3712 * @mode: requested mode
3714 * A pipe may be connected to one or more outputs. Based on the depth of the
3715 * attached framebuffer, choose a good color depth to use on the pipe.
3717 * If possible, match the pipe depth to the fb depth. In some cases, this
3718 * isn't ideal, because the connected output supports a lesser or restricted
3719 * set of depths. Resolve that here:
3720 * LVDS typically supports only 6bpc, so clamp down in that case
3721 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3722 * Displays may support a restricted set as well, check EDID and clamp as
3724 * DP may want to dither down to 6bpc to fit larger modes
3727 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3728 * true if they don't match).
3730 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
3731 unsigned int *pipe_bpp
,
3732 struct drm_display_mode
*mode
)
3734 struct drm_device
*dev
= crtc
->dev
;
3735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3736 struct drm_connector
*connector
;
3737 struct intel_encoder
*intel_encoder
;
3738 unsigned int display_bpc
= UINT_MAX
, bpc
;
3740 /* Walk the encoders & connectors on this crtc, get min bpc */
3741 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
3743 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
3744 unsigned int lvds_bpc
;
3746 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
3752 if (lvds_bpc
< display_bpc
) {
3753 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
3754 display_bpc
= lvds_bpc
;
3759 /* Not one of the known troublemakers, check the EDID */
3760 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
3762 if (connector
->encoder
!= &intel_encoder
->base
)
3765 /* Don't use an invalid EDID bpc value */
3766 if (connector
->display_info
.bpc
&&
3767 connector
->display_info
.bpc
< display_bpc
) {
3768 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
3769 display_bpc
= connector
->display_info
.bpc
;
3774 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3775 * through, clamp it down. (Note: >12bpc will be caught below.)
3777 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
3778 if (display_bpc
> 8 && display_bpc
< 12) {
3779 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3782 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3788 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
3789 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3794 * We could just drive the pipe at the highest bpc all the time and
3795 * enable dithering as needed, but that costs bandwidth. So choose
3796 * the minimum value that expresses the full color range of the fb but
3797 * also stays within the max display bpc discovered above.
3800 switch (crtc
->fb
->depth
) {
3802 bpc
= 8; /* since we go through a colormap */
3806 bpc
= 6; /* min is 18bpp */
3818 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3819 bpc
= min((unsigned int)8, display_bpc
);
3823 display_bpc
= min(display_bpc
, bpc
);
3825 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3828 *pipe_bpp
= display_bpc
* 3;
3830 return display_bpc
!= bpc
;
3833 static int vlv_get_refclk(struct drm_crtc
*crtc
)
3835 struct drm_device
*dev
= crtc
->dev
;
3836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3837 int refclk
= 27000; /* for DP & HDMI */
3839 return 100000; /* only one validated so far */
3841 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
3843 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3844 if (intel_panel_use_ssc(dev_priv
))
3848 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3855 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
3857 struct drm_device
*dev
= crtc
->dev
;
3858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3861 if (IS_VALLEYVIEW(dev
)) {
3862 refclk
= vlv_get_refclk(crtc
);
3863 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3864 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
3865 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3866 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3868 } else if (!IS_GEN2(dev
)) {
3877 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
3878 intel_clock_t
*clock
)
3880 /* SDVO TV has fixed PLL values depend on its clock range,
3881 this mirrors vbios setting. */
3882 if (adjusted_mode
->clock
>= 100000
3883 && adjusted_mode
->clock
< 140500) {
3889 } else if (adjusted_mode
->clock
>= 140500
3890 && adjusted_mode
->clock
<= 200000) {
3899 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
3900 intel_clock_t
*clock
,
3901 intel_clock_t
*reduced_clock
)
3903 struct drm_device
*dev
= crtc
->dev
;
3904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3905 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3906 int pipe
= intel_crtc
->pipe
;
3909 if (IS_PINEVIEW(dev
)) {
3910 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
3912 fp2
= (1 << reduced_clock
->n
) << 16 |
3913 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
3915 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
3917 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
3921 I915_WRITE(FP0(pipe
), fp
);
3923 intel_crtc
->lowfreq_avail
= false;
3924 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3925 reduced_clock
&& i915_powersave
) {
3926 I915_WRITE(FP1(pipe
), fp2
);
3927 intel_crtc
->lowfreq_avail
= true;
3929 I915_WRITE(FP1(pipe
), fp
);
3933 static void intel_update_lvds(struct drm_crtc
*crtc
, intel_clock_t
*clock
,
3934 struct drm_display_mode
*adjusted_mode
)
3936 struct drm_device
*dev
= crtc
->dev
;
3937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3938 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3939 int pipe
= intel_crtc
->pipe
;
3942 temp
= I915_READ(LVDS
);
3943 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
3945 temp
|= LVDS_PIPEB_SELECT
;
3947 temp
&= ~LVDS_PIPEB_SELECT
;
3949 /* set the corresponsding LVDS_BORDER bit */
3950 temp
|= dev_priv
->lvds_border_bits
;
3951 /* Set the B0-B3 data pairs corresponding to whether we're going to
3952 * set the DPLLs for dual-channel mode or not.
3955 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
3957 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
3959 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3960 * appropriately here, but we need to look more thoroughly into how
3961 * panels behave in the two modes.
3963 /* set the dithering flag on LVDS as needed */
3964 if (INTEL_INFO(dev
)->gen
>= 4) {
3965 if (dev_priv
->lvds_dither
)
3966 temp
|= LVDS_ENABLE_DITHER
;
3968 temp
&= ~LVDS_ENABLE_DITHER
;
3970 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
3971 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
3972 temp
|= LVDS_HSYNC_POLARITY
;
3973 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
3974 temp
|= LVDS_VSYNC_POLARITY
;
3975 I915_WRITE(LVDS
, temp
);
3978 static void vlv_update_pll(struct drm_crtc
*crtc
,
3979 struct drm_display_mode
*mode
,
3980 struct drm_display_mode
*adjusted_mode
,
3981 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
3982 int refclk
, int num_connectors
)
3984 struct drm_device
*dev
= crtc
->dev
;
3985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3986 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3987 int pipe
= intel_crtc
->pipe
;
3988 u32 dpll
, mdiv
, pdiv
;
3989 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
3992 is_hdmi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4000 /* Enable DPIO clock input */
4001 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4002 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4003 I915_WRITE(DPLL(pipe
), dpll
);
4004 POSTING_READ(DPLL(pipe
));
4006 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4007 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4008 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4009 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
4010 mdiv
|= (1 << DPIO_K_SHIFT
);
4011 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4012 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4014 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4016 pdiv
= DPIO_REFSEL_OVERRIDE
| (5 << DPIO_PLL_MODESEL_SHIFT
) |
4017 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4018 (8 << DPIO_DRIVER_CTL_SHIFT
) | (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4019 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4021 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x009f0051);
4023 dpll
|= DPLL_VCO_ENABLE
;
4024 I915_WRITE(DPLL(pipe
), dpll
);
4025 POSTING_READ(DPLL(pipe
));
4026 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4027 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4030 u32 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4033 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4037 I915_WRITE(DPLL_MD(pipe
), temp
);
4038 POSTING_READ(DPLL_MD(pipe
));
4041 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x641); /* ??? */
4044 static void i9xx_update_pll(struct drm_crtc
*crtc
,
4045 struct drm_display_mode
*mode
,
4046 struct drm_display_mode
*adjusted_mode
,
4047 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4050 struct drm_device
*dev
= crtc
->dev
;
4051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4052 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4053 int pipe
= intel_crtc
->pipe
;
4057 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4058 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4060 dpll
= DPLL_VGA_MODE_DIS
;
4062 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4063 dpll
|= DPLLB_MODE_LVDS
;
4065 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4067 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4068 if (pixel_multiplier
> 1) {
4069 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4070 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4072 dpll
|= DPLL_DVO_HIGH_SPEED
;
4074 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4075 dpll
|= DPLL_DVO_HIGH_SPEED
;
4077 /* compute bitmask from p1 value */
4078 if (IS_PINEVIEW(dev
))
4079 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4081 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4082 if (IS_G4X(dev
) && reduced_clock
)
4083 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4085 switch (clock
->p2
) {
4087 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4090 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4093 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4096 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4099 if (INTEL_INFO(dev
)->gen
>= 4)
4100 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4102 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4103 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4104 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4105 /* XXX: just matching BIOS for now */
4106 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4108 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4109 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4110 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4112 dpll
|= PLL_REF_INPUT_DREFCLK
;
4114 dpll
|= DPLL_VCO_ENABLE
;
4115 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4116 POSTING_READ(DPLL(pipe
));
4119 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4120 * This is an exception to the general rule that mode_set doesn't turn
4123 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4124 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4126 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4127 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4129 I915_WRITE(DPLL(pipe
), dpll
);
4131 /* Wait for the clocks to stabilize. */
4132 POSTING_READ(DPLL(pipe
));
4135 if (INTEL_INFO(dev
)->gen
>= 4) {
4138 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4140 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4144 I915_WRITE(DPLL_MD(pipe
), temp
);
4146 /* The pixel multiplier can only be updated once the
4147 * DPLL is enabled and the clocks are stable.
4149 * So write it again.
4151 I915_WRITE(DPLL(pipe
), dpll
);
4155 static void i8xx_update_pll(struct drm_crtc
*crtc
,
4156 struct drm_display_mode
*adjusted_mode
,
4157 intel_clock_t
*clock
,
4160 struct drm_device
*dev
= crtc
->dev
;
4161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4162 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4163 int pipe
= intel_crtc
->pipe
;
4166 dpll
= DPLL_VGA_MODE_DIS
;
4168 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4169 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4172 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4174 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4176 dpll
|= PLL_P2_DIVIDE_BY_4
;
4179 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4180 /* XXX: just matching BIOS for now */
4181 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4183 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4184 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4185 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4187 dpll
|= PLL_REF_INPUT_DREFCLK
;
4189 dpll
|= DPLL_VCO_ENABLE
;
4190 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4191 POSTING_READ(DPLL(pipe
));
4194 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4195 * This is an exception to the general rule that mode_set doesn't turn
4198 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4199 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4201 I915_WRITE(DPLL(pipe
), dpll
);
4203 /* Wait for the clocks to stabilize. */
4204 POSTING_READ(DPLL(pipe
));
4207 /* The pixel multiplier can only be updated once the
4208 * DPLL is enabled and the clocks are stable.
4210 * So write it again.
4212 I915_WRITE(DPLL(pipe
), dpll
);
4215 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4216 struct drm_display_mode
*mode
,
4217 struct drm_display_mode
*adjusted_mode
,
4219 struct drm_framebuffer
*old_fb
)
4221 struct drm_device
*dev
= crtc
->dev
;
4222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4223 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4224 int pipe
= intel_crtc
->pipe
;
4225 int plane
= intel_crtc
->plane
;
4226 int refclk
, num_connectors
= 0;
4227 intel_clock_t clock
, reduced_clock
;
4228 u32 dspcntr
, pipeconf
, vsyncshift
;
4229 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4230 bool is_lvds
= false, is_tv
= false, is_dp
= false;
4231 struct intel_encoder
*encoder
;
4232 const intel_limit_t
*limit
;
4235 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4236 switch (encoder
->type
) {
4237 case INTEL_OUTPUT_LVDS
:
4240 case INTEL_OUTPUT_SDVO
:
4241 case INTEL_OUTPUT_HDMI
:
4243 if (encoder
->needs_tv_clock
)
4246 case INTEL_OUTPUT_TVOUT
:
4249 case INTEL_OUTPUT_DISPLAYPORT
:
4257 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4260 * Returns a set of divisors for the desired target clock with the given
4261 * refclk, or FALSE. The returned values represent the clock equation:
4262 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4264 limit
= intel_limit(crtc
, refclk
);
4265 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4268 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4272 /* Ensure that the cursor is valid for the new mode before changing... */
4273 intel_crtc_update_cursor(crtc
, true);
4275 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4277 * Ensure we match the reduced clock's P to the target clock.
4278 * If the clocks don't match, we can't switch the display clock
4279 * by using the FP0/FP1. In such case we will disable the LVDS
4280 * downclock feature.
4282 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4283 dev_priv
->lvds_downclock
,
4289 if (is_sdvo
&& is_tv
)
4290 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4292 i9xx_update_pll_dividers(crtc
, &clock
, has_reduced_clock
?
4293 &reduced_clock
: NULL
);
4296 i8xx_update_pll(crtc
, adjusted_mode
, &clock
, num_connectors
);
4297 else if (IS_VALLEYVIEW(dev
))
4298 vlv_update_pll(crtc
, mode
,adjusted_mode
, &clock
, NULL
,
4299 refclk
, num_connectors
);
4301 i9xx_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4302 has_reduced_clock
? &reduced_clock
: NULL
,
4305 /* setup pipeconf */
4306 pipeconf
= I915_READ(PIPECONF(pipe
));
4308 /* Set up the display plane register */
4309 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4312 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4314 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4316 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4317 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4320 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4324 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4325 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4327 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4330 /* default to 8bpc */
4331 pipeconf
&= ~(PIPECONF_BPP_MASK
| PIPECONF_DITHER_EN
);
4333 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4334 pipeconf
|= PIPECONF_BPP_6
|
4335 PIPECONF_DITHER_EN
|
4336 PIPECONF_DITHER_TYPE_SP
;
4340 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4341 drm_mode_debug_printmodeline(mode
);
4343 if (HAS_PIPE_CXSR(dev
)) {
4344 if (intel_crtc
->lowfreq_avail
) {
4345 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4346 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4348 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4349 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4353 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4354 if (!IS_GEN2(dev
) &&
4355 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4356 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4357 /* the chip adds 2 halflines automatically */
4358 adjusted_mode
->crtc_vtotal
-= 1;
4359 adjusted_mode
->crtc_vblank_end
-= 1;
4360 vsyncshift
= adjusted_mode
->crtc_hsync_start
4361 - adjusted_mode
->crtc_htotal
/2;
4363 pipeconf
|= PIPECONF_PROGRESSIVE
;
4368 I915_WRITE(VSYNCSHIFT(pipe
), vsyncshift
);
4370 I915_WRITE(HTOTAL(pipe
),
4371 (adjusted_mode
->crtc_hdisplay
- 1) |
4372 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4373 I915_WRITE(HBLANK(pipe
),
4374 (adjusted_mode
->crtc_hblank_start
- 1) |
4375 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4376 I915_WRITE(HSYNC(pipe
),
4377 (adjusted_mode
->crtc_hsync_start
- 1) |
4378 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4380 I915_WRITE(VTOTAL(pipe
),
4381 (adjusted_mode
->crtc_vdisplay
- 1) |
4382 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4383 I915_WRITE(VBLANK(pipe
),
4384 (adjusted_mode
->crtc_vblank_start
- 1) |
4385 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4386 I915_WRITE(VSYNC(pipe
),
4387 (adjusted_mode
->crtc_vsync_start
- 1) |
4388 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4390 /* pipesrc and dspsize control the size that is scaled from,
4391 * which should always be the user's requested size.
4393 I915_WRITE(DSPSIZE(plane
),
4394 ((mode
->vdisplay
- 1) << 16) |
4395 (mode
->hdisplay
- 1));
4396 I915_WRITE(DSPPOS(plane
), 0);
4397 I915_WRITE(PIPESRC(pipe
),
4398 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4400 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4401 POSTING_READ(PIPECONF(pipe
));
4402 intel_enable_pipe(dev_priv
, pipe
, false);
4404 intel_wait_for_vblank(dev
, pipe
);
4406 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4407 POSTING_READ(DSPCNTR(plane
));
4409 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4411 intel_update_watermarks(dev
);
4417 * Initialize reference clocks when the driver loads
4419 void ironlake_init_pch_refclk(struct drm_device
*dev
)
4421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4422 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4423 struct intel_encoder
*encoder
;
4425 bool has_lvds
= false;
4426 bool has_cpu_edp
= false;
4427 bool has_pch_edp
= false;
4428 bool has_panel
= false;
4429 bool has_ck505
= false;
4430 bool can_ssc
= false;
4432 /* We need to take the global config into account */
4433 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4435 switch (encoder
->type
) {
4436 case INTEL_OUTPUT_LVDS
:
4440 case INTEL_OUTPUT_EDP
:
4442 if (intel_encoder_is_pch_edp(&encoder
->base
))
4450 if (HAS_PCH_IBX(dev
)) {
4451 has_ck505
= dev_priv
->display_clock_mode
;
4452 can_ssc
= has_ck505
;
4458 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4459 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4462 /* Ironlake: try to setup display ref clock before DPLL
4463 * enabling. This is only under driver's control after
4464 * PCH B stepping, previous chipset stepping should be
4465 * ignoring this setting.
4467 temp
= I915_READ(PCH_DREF_CONTROL
);
4468 /* Always enable nonspread source */
4469 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4472 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
4474 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4477 temp
&= ~DREF_SSC_SOURCE_MASK
;
4478 temp
|= DREF_SSC_SOURCE_ENABLE
;
4480 /* SSC must be turned on before enabling the CPU output */
4481 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4482 DRM_DEBUG_KMS("Using SSC on panel\n");
4483 temp
|= DREF_SSC1_ENABLE
;
4485 temp
&= ~DREF_SSC1_ENABLE
;
4487 /* Get SSC going before enabling the outputs */
4488 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4489 POSTING_READ(PCH_DREF_CONTROL
);
4492 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4494 /* Enable CPU source on CPU attached eDP */
4496 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4497 DRM_DEBUG_KMS("Using SSC on eDP\n");
4498 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4501 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4503 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4505 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4506 POSTING_READ(PCH_DREF_CONTROL
);
4509 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4511 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4513 /* Turn off CPU output */
4514 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4516 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4517 POSTING_READ(PCH_DREF_CONTROL
);
4520 /* Turn off the SSC source */
4521 temp
&= ~DREF_SSC_SOURCE_MASK
;
4522 temp
|= DREF_SSC_SOURCE_DISABLE
;
4525 temp
&= ~ DREF_SSC1_ENABLE
;
4527 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4528 POSTING_READ(PCH_DREF_CONTROL
);
4533 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
4535 struct drm_device
*dev
= crtc
->dev
;
4536 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4537 struct intel_encoder
*encoder
;
4538 struct intel_encoder
*edp_encoder
= NULL
;
4539 int num_connectors
= 0;
4540 bool is_lvds
= false;
4542 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4543 switch (encoder
->type
) {
4544 case INTEL_OUTPUT_LVDS
:
4547 case INTEL_OUTPUT_EDP
:
4548 edp_encoder
= encoder
;
4554 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4555 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4556 dev_priv
->lvds_ssc_freq
);
4557 return dev_priv
->lvds_ssc_freq
* 1000;
4563 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
4564 struct drm_display_mode
*mode
,
4565 struct drm_display_mode
*adjusted_mode
,
4567 struct drm_framebuffer
*old_fb
)
4569 struct drm_device
*dev
= crtc
->dev
;
4570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4571 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4572 int pipe
= intel_crtc
->pipe
;
4573 int plane
= intel_crtc
->plane
;
4574 int refclk
, num_connectors
= 0;
4575 intel_clock_t clock
, reduced_clock
;
4576 u32 dpll
, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
4577 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4578 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
4579 struct intel_encoder
*encoder
, *edp_encoder
= NULL
;
4580 const intel_limit_t
*limit
;
4582 struct fdi_m_n m_n
= {0};
4584 int target_clock
, pixel_multiplier
, lane
, link_bw
, factor
;
4585 unsigned int pipe_bpp
;
4587 bool is_cpu_edp
= false, is_pch_edp
= false;
4589 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4590 switch (encoder
->type
) {
4591 case INTEL_OUTPUT_LVDS
:
4594 case INTEL_OUTPUT_SDVO
:
4595 case INTEL_OUTPUT_HDMI
:
4597 if (encoder
->needs_tv_clock
)
4600 case INTEL_OUTPUT_TVOUT
:
4603 case INTEL_OUTPUT_ANALOG
:
4606 case INTEL_OUTPUT_DISPLAYPORT
:
4609 case INTEL_OUTPUT_EDP
:
4611 if (intel_encoder_is_pch_edp(&encoder
->base
))
4615 edp_encoder
= encoder
;
4622 refclk
= ironlake_get_refclk(crtc
);
4625 * Returns a set of divisors for the desired target clock with the given
4626 * refclk, or FALSE. The returned values represent the clock equation:
4627 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4629 limit
= intel_limit(crtc
, refclk
);
4630 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4633 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4637 /* Ensure that the cursor is valid for the new mode before changing... */
4638 intel_crtc_update_cursor(crtc
, true);
4640 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4642 * Ensure we match the reduced clock's P to the target clock.
4643 * If the clocks don't match, we can't switch the display clock
4644 * by using the FP0/FP1. In such case we will disable the LVDS
4645 * downclock feature.
4647 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4648 dev_priv
->lvds_downclock
,
4654 if (is_sdvo
&& is_tv
)
4655 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4659 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4661 /* CPU eDP doesn't require FDI link, so just set DP M/N
4662 according to current link config */
4664 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
4666 /* FDI is a binary signal running at ~2.7GHz, encoding
4667 * each output octet as 10 bits. The actual frequency
4668 * is stored as a divider into a 100MHz clock, and the
4669 * mode pixel clock is stored in units of 1KHz.
4670 * Hence the bw of each lane in terms of the mode signal
4673 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4676 /* [e]DP over FDI requires target mode clock instead of link clock. */
4678 target_clock
= intel_edp_target_clock(edp_encoder
, mode
);
4680 target_clock
= mode
->clock
;
4682 target_clock
= adjusted_mode
->clock
;
4684 /* determine panel color depth */
4685 temp
= I915_READ(PIPECONF(pipe
));
4686 temp
&= ~PIPE_BPC_MASK
;
4687 dither
= intel_choose_pipe_bpp_dither(crtc
, &pipe_bpp
, mode
);
4702 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4709 intel_crtc
->bpp
= pipe_bpp
;
4710 I915_WRITE(PIPECONF(pipe
), temp
);
4714 * Account for spread spectrum to avoid
4715 * oversubscribing the link. Max center spread
4716 * is 2.5%; use 5% for safety's sake.
4718 u32 bps
= target_clock
* intel_crtc
->bpp
* 21 / 20;
4719 lane
= bps
/ (link_bw
* 8) + 1;
4722 intel_crtc
->fdi_lanes
= lane
;
4724 if (pixel_multiplier
> 1)
4725 link_bw
*= pixel_multiplier
;
4726 ironlake_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
,
4729 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
4730 if (has_reduced_clock
)
4731 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
4734 /* Enable autotuning of the PLL clock (if permissible) */
4737 if ((intel_panel_use_ssc(dev_priv
) &&
4738 dev_priv
->lvds_ssc_freq
== 100) ||
4739 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
4741 } else if (is_sdvo
&& is_tv
)
4744 if (clock
.m
< factor
* clock
.n
)
4750 dpll
|= DPLLB_MODE_LVDS
;
4752 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4754 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4755 if (pixel_multiplier
> 1) {
4756 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
4758 dpll
|= DPLL_DVO_HIGH_SPEED
;
4760 if (is_dp
&& !is_cpu_edp
)
4761 dpll
|= DPLL_DVO_HIGH_SPEED
;
4763 /* compute bitmask from p1 value */
4764 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4766 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4770 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4773 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4776 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4779 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4783 if (is_sdvo
&& is_tv
)
4784 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4786 /* XXX: just matching BIOS for now */
4787 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4789 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4790 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4792 dpll
|= PLL_REF_INPUT_DREFCLK
;
4794 /* setup pipeconf */
4795 pipeconf
= I915_READ(PIPECONF(pipe
));
4797 /* Set up the display plane register */
4798 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4800 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
4801 drm_mode_debug_printmodeline(mode
);
4803 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4804 * pre-Haswell/LPT generation */
4805 if (HAS_PCH_LPT(dev
)) {
4806 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4808 } else if (!is_cpu_edp
) {
4809 struct intel_pch_pll
*pll
;
4811 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
4813 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4818 intel_put_pch_pll(intel_crtc
);
4820 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4821 * This is an exception to the general rule that mode_set doesn't turn
4825 temp
= I915_READ(PCH_LVDS
);
4826 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4827 if (HAS_PCH_CPT(dev
)) {
4828 temp
&= ~PORT_TRANS_SEL_MASK
;
4829 temp
|= PORT_TRANS_SEL_CPT(pipe
);
4832 temp
|= LVDS_PIPEB_SELECT
;
4834 temp
&= ~LVDS_PIPEB_SELECT
;
4837 /* set the corresponsding LVDS_BORDER bit */
4838 temp
|= dev_priv
->lvds_border_bits
;
4839 /* Set the B0-B3 data pairs corresponding to whether we're going to
4840 * set the DPLLs for dual-channel mode or not.
4843 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4845 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4847 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4848 * appropriately here, but we need to look more thoroughly into how
4849 * panels behave in the two modes.
4851 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
4852 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
4853 temp
|= LVDS_HSYNC_POLARITY
;
4854 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
4855 temp
|= LVDS_VSYNC_POLARITY
;
4856 I915_WRITE(PCH_LVDS
, temp
);
4859 pipeconf
&= ~PIPECONF_DITHER_EN
;
4860 pipeconf
&= ~PIPECONF_DITHER_TYPE_MASK
;
4861 if ((is_lvds
&& dev_priv
->lvds_dither
) || dither
) {
4862 pipeconf
|= PIPECONF_DITHER_EN
;
4863 pipeconf
|= PIPECONF_DITHER_TYPE_SP
;
4865 if (is_dp
&& !is_cpu_edp
) {
4866 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4868 /* For non-DP output, clear any trans DP clock recovery setting.*/
4869 I915_WRITE(TRANSDATA_M1(pipe
), 0);
4870 I915_WRITE(TRANSDATA_N1(pipe
), 0);
4871 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
4872 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
4875 if (intel_crtc
->pch_pll
) {
4876 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
4878 /* Wait for the clocks to stabilize. */
4879 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
4882 /* The pixel multiplier can only be updated once the
4883 * DPLL is enabled and the clocks are stable.
4885 * So write it again.
4887 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
4890 intel_crtc
->lowfreq_avail
= false;
4891 if (intel_crtc
->pch_pll
) {
4892 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
4893 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
4894 intel_crtc
->lowfreq_avail
= true;
4896 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
4900 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4901 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4902 pipeconf
|= PIPECONF_INTERLACED_ILK
;
4903 /* the chip adds 2 halflines automatically */
4904 adjusted_mode
->crtc_vtotal
-= 1;
4905 adjusted_mode
->crtc_vblank_end
-= 1;
4906 I915_WRITE(VSYNCSHIFT(pipe
),
4907 adjusted_mode
->crtc_hsync_start
4908 - adjusted_mode
->crtc_htotal
/2);
4910 pipeconf
|= PIPECONF_PROGRESSIVE
;
4911 I915_WRITE(VSYNCSHIFT(pipe
), 0);
4914 I915_WRITE(HTOTAL(pipe
),
4915 (adjusted_mode
->crtc_hdisplay
- 1) |
4916 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4917 I915_WRITE(HBLANK(pipe
),
4918 (adjusted_mode
->crtc_hblank_start
- 1) |
4919 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4920 I915_WRITE(HSYNC(pipe
),
4921 (adjusted_mode
->crtc_hsync_start
- 1) |
4922 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4924 I915_WRITE(VTOTAL(pipe
),
4925 (adjusted_mode
->crtc_vdisplay
- 1) |
4926 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4927 I915_WRITE(VBLANK(pipe
),
4928 (adjusted_mode
->crtc_vblank_start
- 1) |
4929 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4930 I915_WRITE(VSYNC(pipe
),
4931 (adjusted_mode
->crtc_vsync_start
- 1) |
4932 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4934 /* pipesrc controls the size that is scaled from, which should
4935 * always be the user's requested size.
4937 I915_WRITE(PIPESRC(pipe
),
4938 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4940 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
4941 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
4942 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
4943 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
4946 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
4948 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4949 POSTING_READ(PIPECONF(pipe
));
4951 intel_wait_for_vblank(dev
, pipe
);
4953 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4954 POSTING_READ(DSPCNTR(plane
));
4956 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4958 intel_update_watermarks(dev
);
4960 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
4965 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
4966 struct drm_display_mode
*mode
,
4967 struct drm_display_mode
*adjusted_mode
,
4969 struct drm_framebuffer
*old_fb
)
4971 struct drm_device
*dev
= crtc
->dev
;
4972 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4973 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4974 int pipe
= intel_crtc
->pipe
;
4977 drm_vblank_pre_modeset(dev
, pipe
);
4979 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
4981 drm_vblank_post_modeset(dev
, pipe
);
4984 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
4986 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_ON
;
4991 static bool intel_eld_uptodate(struct drm_connector
*connector
,
4992 int reg_eldv
, uint32_t bits_eldv
,
4993 int reg_elda
, uint32_t bits_elda
,
4996 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4997 uint8_t *eld
= connector
->eld
;
5000 i
= I915_READ(reg_eldv
);
5009 i
= I915_READ(reg_elda
);
5011 I915_WRITE(reg_elda
, i
);
5013 for (i
= 0; i
< eld
[2]; i
++)
5014 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5020 static void g4x_write_eld(struct drm_connector
*connector
,
5021 struct drm_crtc
*crtc
)
5023 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5024 uint8_t *eld
= connector
->eld
;
5029 i
= I915_READ(G4X_AUD_VID_DID
);
5031 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5032 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5034 eldv
= G4X_ELDV_DEVCTG
;
5036 if (intel_eld_uptodate(connector
,
5037 G4X_AUD_CNTL_ST
, eldv
,
5038 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5039 G4X_HDMIW_HDMIEDID
))
5042 i
= I915_READ(G4X_AUD_CNTL_ST
);
5043 i
&= ~(eldv
| G4X_ELD_ADDR
);
5044 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5045 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5050 len
= min_t(uint8_t, eld
[2], len
);
5051 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5052 for (i
= 0; i
< len
; i
++)
5053 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5055 i
= I915_READ(G4X_AUD_CNTL_ST
);
5057 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5060 static void ironlake_write_eld(struct drm_connector
*connector
,
5061 struct drm_crtc
*crtc
)
5063 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5064 uint8_t *eld
= connector
->eld
;
5073 if (HAS_PCH_IBX(connector
->dev
)) {
5074 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID_A
;
5075 aud_config
= IBX_AUD_CONFIG_A
;
5076 aud_cntl_st
= IBX_AUD_CNTL_ST_A
;
5077 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
5079 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID_A
;
5080 aud_config
= CPT_AUD_CONFIG_A
;
5081 aud_cntl_st
= CPT_AUD_CNTL_ST_A
;
5082 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
5085 i
= to_intel_crtc(crtc
)->pipe
;
5086 hdmiw_hdmiedid
+= i
* 0x100;
5087 aud_cntl_st
+= i
* 0x100;
5088 aud_config
+= i
* 0x100;
5090 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i
));
5092 i
= I915_READ(aud_cntl_st
);
5093 i
= (i
>> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5095 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5096 /* operate blindly on all ports */
5097 eldv
= IBX_ELD_VALIDB
;
5098 eldv
|= IBX_ELD_VALIDB
<< 4;
5099 eldv
|= IBX_ELD_VALIDB
<< 8;
5101 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
5102 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
5105 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5106 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5107 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5108 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5110 I915_WRITE(aud_config
, 0);
5112 if (intel_eld_uptodate(connector
,
5113 aud_cntrl_st2
, eldv
,
5114 aud_cntl_st
, IBX_ELD_ADDRESS
,
5118 i
= I915_READ(aud_cntrl_st2
);
5120 I915_WRITE(aud_cntrl_st2
, i
);
5125 i
= I915_READ(aud_cntl_st
);
5126 i
&= ~IBX_ELD_ADDRESS
;
5127 I915_WRITE(aud_cntl_st
, i
);
5129 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5130 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5131 for (i
= 0; i
< len
; i
++)
5132 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5134 i
= I915_READ(aud_cntrl_st2
);
5136 I915_WRITE(aud_cntrl_st2
, i
);
5139 void intel_write_eld(struct drm_encoder
*encoder
,
5140 struct drm_display_mode
*mode
)
5142 struct drm_crtc
*crtc
= encoder
->crtc
;
5143 struct drm_connector
*connector
;
5144 struct drm_device
*dev
= encoder
->dev
;
5145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5147 connector
= drm_select_eld(encoder
, mode
);
5151 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5153 drm_get_connector_name(connector
),
5154 connector
->encoder
->base
.id
,
5155 drm_get_encoder_name(connector
->encoder
));
5157 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
5159 if (dev_priv
->display
.write_eld
)
5160 dev_priv
->display
.write_eld(connector
, crtc
);
5163 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5164 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
5166 struct drm_device
*dev
= crtc
->dev
;
5167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5168 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5169 int palreg
= PALETTE(intel_crtc
->pipe
);
5172 /* The clocks have to be on to load the palette. */
5173 if (!crtc
->enabled
|| !intel_crtc
->active
)
5176 /* use legacy palette for Ironlake */
5177 if (HAS_PCH_SPLIT(dev
))
5178 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
5180 for (i
= 0; i
< 256; i
++) {
5181 I915_WRITE(palreg
+ 4 * i
,
5182 (intel_crtc
->lut_r
[i
] << 16) |
5183 (intel_crtc
->lut_g
[i
] << 8) |
5184 intel_crtc
->lut_b
[i
]);
5188 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5190 struct drm_device
*dev
= crtc
->dev
;
5191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5192 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5193 bool visible
= base
!= 0;
5196 if (intel_crtc
->cursor_visible
== visible
)
5199 cntl
= I915_READ(_CURACNTR
);
5201 /* On these chipsets we can only modify the base whilst
5202 * the cursor is disabled.
5204 I915_WRITE(_CURABASE
, base
);
5206 cntl
&= ~(CURSOR_FORMAT_MASK
);
5207 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5208 cntl
|= CURSOR_ENABLE
|
5209 CURSOR_GAMMA_ENABLE
|
5212 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
5213 I915_WRITE(_CURACNTR
, cntl
);
5215 intel_crtc
->cursor_visible
= visible
;
5218 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5220 struct drm_device
*dev
= crtc
->dev
;
5221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5222 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5223 int pipe
= intel_crtc
->pipe
;
5224 bool visible
= base
!= 0;
5226 if (intel_crtc
->cursor_visible
!= visible
) {
5227 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
5229 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
5230 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5231 cntl
|= pipe
<< 28; /* Connect to correct pipe */
5233 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5234 cntl
|= CURSOR_MODE_DISABLE
;
5236 I915_WRITE(CURCNTR(pipe
), cntl
);
5238 intel_crtc
->cursor_visible
= visible
;
5240 /* and commit changes on next vblank */
5241 I915_WRITE(CURBASE(pipe
), base
);
5244 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5246 struct drm_device
*dev
= crtc
->dev
;
5247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5248 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5249 int pipe
= intel_crtc
->pipe
;
5250 bool visible
= base
!= 0;
5252 if (intel_crtc
->cursor_visible
!= visible
) {
5253 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
5255 cntl
&= ~CURSOR_MODE
;
5256 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5258 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5259 cntl
|= CURSOR_MODE_DISABLE
;
5261 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
5263 intel_crtc
->cursor_visible
= visible
;
5265 /* and commit changes on next vblank */
5266 I915_WRITE(CURBASE_IVB(pipe
), base
);
5269 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5270 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
5273 struct drm_device
*dev
= crtc
->dev
;
5274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5275 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5276 int pipe
= intel_crtc
->pipe
;
5277 int x
= intel_crtc
->cursor_x
;
5278 int y
= intel_crtc
->cursor_y
;
5284 if (on
&& crtc
->enabled
&& crtc
->fb
) {
5285 base
= intel_crtc
->cursor_addr
;
5286 if (x
> (int) crtc
->fb
->width
)
5289 if (y
> (int) crtc
->fb
->height
)
5295 if (x
+ intel_crtc
->cursor_width
< 0)
5298 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
5301 pos
|= x
<< CURSOR_X_SHIFT
;
5304 if (y
+ intel_crtc
->cursor_height
< 0)
5307 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
5310 pos
|= y
<< CURSOR_Y_SHIFT
;
5312 visible
= base
!= 0;
5313 if (!visible
&& !intel_crtc
->cursor_visible
)
5316 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
5317 I915_WRITE(CURPOS_IVB(pipe
), pos
);
5318 ivb_update_cursor(crtc
, base
);
5320 I915_WRITE(CURPOS(pipe
), pos
);
5321 if (IS_845G(dev
) || IS_I865G(dev
))
5322 i845_update_cursor(crtc
, base
);
5324 i9xx_update_cursor(crtc
, base
);
5328 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
5329 struct drm_file
*file
,
5331 uint32_t width
, uint32_t height
)
5333 struct drm_device
*dev
= crtc
->dev
;
5334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5335 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5336 struct drm_i915_gem_object
*obj
;
5340 DRM_DEBUG_KMS("\n");
5342 /* if we want to turn off the cursor ignore width and height */
5344 DRM_DEBUG_KMS("cursor off\n");
5347 mutex_lock(&dev
->struct_mutex
);
5351 /* Currently we only support 64x64 cursors */
5352 if (width
!= 64 || height
!= 64) {
5353 DRM_ERROR("we currently only support 64x64 cursors\n");
5357 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
5358 if (&obj
->base
== NULL
)
5361 if (obj
->base
.size
< width
* height
* 4) {
5362 DRM_ERROR("buffer is to small\n");
5367 /* we only need to pin inside GTT if cursor is non-phy */
5368 mutex_lock(&dev
->struct_mutex
);
5369 if (!dev_priv
->info
->cursor_needs_physical
) {
5370 if (obj
->tiling_mode
) {
5371 DRM_ERROR("cursor cannot be tiled\n");
5376 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
5378 DRM_ERROR("failed to move cursor bo into the GTT\n");
5382 ret
= i915_gem_object_put_fence(obj
);
5384 DRM_ERROR("failed to release fence for cursor");
5388 addr
= obj
->gtt_offset
;
5390 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
5391 ret
= i915_gem_attach_phys_object(dev
, obj
,
5392 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
5395 DRM_ERROR("failed to attach phys object\n");
5398 addr
= obj
->phys_obj
->handle
->busaddr
;
5402 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
5405 if (intel_crtc
->cursor_bo
) {
5406 if (dev_priv
->info
->cursor_needs_physical
) {
5407 if (intel_crtc
->cursor_bo
!= obj
)
5408 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
5410 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
5411 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
5414 mutex_unlock(&dev
->struct_mutex
);
5416 intel_crtc
->cursor_addr
= addr
;
5417 intel_crtc
->cursor_bo
= obj
;
5418 intel_crtc
->cursor_width
= width
;
5419 intel_crtc
->cursor_height
= height
;
5421 intel_crtc_update_cursor(crtc
, true);
5425 i915_gem_object_unpin(obj
);
5427 mutex_unlock(&dev
->struct_mutex
);
5429 drm_gem_object_unreference_unlocked(&obj
->base
);
5433 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
5435 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5437 intel_crtc
->cursor_x
= x
;
5438 intel_crtc
->cursor_y
= y
;
5440 intel_crtc_update_cursor(crtc
, true);
5445 /** Sets the color ramps on behalf of RandR */
5446 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
5447 u16 blue
, int regno
)
5449 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5451 intel_crtc
->lut_r
[regno
] = red
>> 8;
5452 intel_crtc
->lut_g
[regno
] = green
>> 8;
5453 intel_crtc
->lut_b
[regno
] = blue
>> 8;
5456 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5457 u16
*blue
, int regno
)
5459 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5461 *red
= intel_crtc
->lut_r
[regno
] << 8;
5462 *green
= intel_crtc
->lut_g
[regno
] << 8;
5463 *blue
= intel_crtc
->lut_b
[regno
] << 8;
5466 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5467 u16
*blue
, uint32_t start
, uint32_t size
)
5469 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
5470 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5472 for (i
= start
; i
< end
; i
++) {
5473 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
5474 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
5475 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
5478 intel_crtc_load_lut(crtc
);
5482 * Get a pipe with a simple mode set on it for doing load-based monitor
5485 * It will be up to the load-detect code to adjust the pipe as appropriate for
5486 * its requirements. The pipe will be connected to no other encoders.
5488 * Currently this code will only succeed if there is a pipe with no encoders
5489 * configured for it. In the future, it could choose to temporarily disable
5490 * some outputs to free up a pipe for its use.
5492 * \return crtc, or NULL if no pipes are available.
5495 /* VESA 640x480x72Hz mode to set on the pipe */
5496 static struct drm_display_mode load_detect_mode
= {
5497 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
5498 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
5501 static struct drm_framebuffer
*
5502 intel_framebuffer_create(struct drm_device
*dev
,
5503 struct drm_mode_fb_cmd2
*mode_cmd
,
5504 struct drm_i915_gem_object
*obj
)
5506 struct intel_framebuffer
*intel_fb
;
5509 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
5511 drm_gem_object_unreference_unlocked(&obj
->base
);
5512 return ERR_PTR(-ENOMEM
);
5515 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
5517 drm_gem_object_unreference_unlocked(&obj
->base
);
5519 return ERR_PTR(ret
);
5522 return &intel_fb
->base
;
5526 intel_framebuffer_pitch_for_width(int width
, int bpp
)
5528 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
5529 return ALIGN(pitch
, 64);
5533 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
5535 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
5536 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
5539 static struct drm_framebuffer
*
5540 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
5541 struct drm_display_mode
*mode
,
5544 struct drm_i915_gem_object
*obj
;
5545 struct drm_mode_fb_cmd2 mode_cmd
;
5547 obj
= i915_gem_alloc_object(dev
,
5548 intel_framebuffer_size_for_mode(mode
, bpp
));
5550 return ERR_PTR(-ENOMEM
);
5552 mode_cmd
.width
= mode
->hdisplay
;
5553 mode_cmd
.height
= mode
->vdisplay
;
5554 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
5556 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
5558 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
5561 static struct drm_framebuffer
*
5562 mode_fits_in_fbdev(struct drm_device
*dev
,
5563 struct drm_display_mode
*mode
)
5565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5566 struct drm_i915_gem_object
*obj
;
5567 struct drm_framebuffer
*fb
;
5569 if (dev_priv
->fbdev
== NULL
)
5572 obj
= dev_priv
->fbdev
->ifb
.obj
;
5576 fb
= &dev_priv
->fbdev
->ifb
.base
;
5577 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
5578 fb
->bits_per_pixel
))
5581 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
5587 bool intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5588 struct drm_connector
*connector
,
5589 struct drm_display_mode
*mode
,
5590 struct intel_load_detect_pipe
*old
)
5592 struct intel_crtc
*intel_crtc
;
5593 struct drm_crtc
*possible_crtc
;
5594 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5595 struct drm_crtc
*crtc
= NULL
;
5596 struct drm_device
*dev
= encoder
->dev
;
5597 struct drm_framebuffer
*old_fb
;
5600 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5601 connector
->base
.id
, drm_get_connector_name(connector
),
5602 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5605 * Algorithm gets a little messy:
5607 * - if the connector already has an assigned crtc, use it (but make
5608 * sure it's on first)
5610 * - try to find the first unused crtc that can drive this connector,
5611 * and use that if we find one
5614 /* See if we already have a CRTC for this connector */
5615 if (encoder
->crtc
) {
5616 crtc
= encoder
->crtc
;
5618 intel_crtc
= to_intel_crtc(crtc
);
5619 old
->dpms_mode
= intel_crtc
->dpms_mode
;
5620 old
->load_detect_temp
= false;
5622 /* Make sure the crtc and connector are running */
5623 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5624 struct drm_encoder_helper_funcs
*encoder_funcs
;
5625 struct drm_crtc_helper_funcs
*crtc_funcs
;
5627 crtc_funcs
= crtc
->helper_private
;
5628 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
5630 encoder_funcs
= encoder
->helper_private
;
5631 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
5637 /* Find an unused one (if possible) */
5638 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
5640 if (!(encoder
->possible_crtcs
& (1 << i
)))
5642 if (!possible_crtc
->enabled
) {
5643 crtc
= possible_crtc
;
5649 * If we didn't find an unused CRTC, don't use any.
5652 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5656 encoder
->crtc
= crtc
;
5657 connector
->encoder
= encoder
;
5659 intel_crtc
= to_intel_crtc(crtc
);
5660 old
->dpms_mode
= intel_crtc
->dpms_mode
;
5661 old
->load_detect_temp
= true;
5662 old
->release_fb
= NULL
;
5665 mode
= &load_detect_mode
;
5669 /* We need a framebuffer large enough to accommodate all accesses
5670 * that the plane may generate whilst we perform load detection.
5671 * We can not rely on the fbcon either being present (we get called
5672 * during its initialisation to detect all boot displays, or it may
5673 * not even exist) or that it is large enough to satisfy the
5676 crtc
->fb
= mode_fits_in_fbdev(dev
, mode
);
5677 if (crtc
->fb
== NULL
) {
5678 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5679 crtc
->fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
5680 old
->release_fb
= crtc
->fb
;
5682 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5683 if (IS_ERR(crtc
->fb
)) {
5684 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5689 if (!drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, old_fb
)) {
5690 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5691 if (old
->release_fb
)
5692 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5697 /* let the connector get through one full cycle before testing */
5698 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
5703 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5704 struct drm_connector
*connector
,
5705 struct intel_load_detect_pipe
*old
)
5707 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5708 struct drm_device
*dev
= encoder
->dev
;
5709 struct drm_crtc
*crtc
= encoder
->crtc
;
5710 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
5711 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
5713 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5714 connector
->base
.id
, drm_get_connector_name(connector
),
5715 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5717 if (old
->load_detect_temp
) {
5718 connector
->encoder
= NULL
;
5719 drm_helper_disable_unused_functions(dev
);
5721 if (old
->release_fb
)
5722 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5727 /* Switch crtc and encoder back off if necessary */
5728 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5729 encoder_funcs
->dpms(encoder
, old
->dpms_mode
);
5730 crtc_funcs
->dpms(crtc
, old
->dpms_mode
);
5734 /* Returns the clock of the currently programmed mode of the given pipe. */
5735 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
5737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5738 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5739 int pipe
= intel_crtc
->pipe
;
5740 u32 dpll
= I915_READ(DPLL(pipe
));
5742 intel_clock_t clock
;
5744 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
5745 fp
= I915_READ(FP0(pipe
));
5747 fp
= I915_READ(FP1(pipe
));
5749 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
5750 if (IS_PINEVIEW(dev
)) {
5751 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
5752 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5754 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
5755 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5758 if (!IS_GEN2(dev
)) {
5759 if (IS_PINEVIEW(dev
))
5760 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
5761 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
5763 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
5764 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5766 switch (dpll
& DPLL_MODE_MASK
) {
5767 case DPLLB_MODE_DAC_SERIAL
:
5768 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
5771 case DPLLB_MODE_LVDS
:
5772 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
5776 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5777 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
5781 /* XXX: Handle the 100Mhz refclk */
5782 intel_clock(dev
, 96000, &clock
);
5784 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
5787 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
5788 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5791 if ((dpll
& PLL_REF_INPUT_MASK
) ==
5792 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
5793 /* XXX: might not be 66MHz */
5794 intel_clock(dev
, 66000, &clock
);
5796 intel_clock(dev
, 48000, &clock
);
5798 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
5801 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
5802 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
5804 if (dpll
& PLL_P2_DIVIDE_BY_4
)
5809 intel_clock(dev
, 48000, &clock
);
5813 /* XXX: It would be nice to validate the clocks, but we can't reuse
5814 * i830PllIsValid() because it relies on the xf86_config connector
5815 * configuration being accurate, which it isn't necessarily.
5821 /** Returns the currently programmed mode of the given pipe. */
5822 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
5823 struct drm_crtc
*crtc
)
5825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5826 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5827 int pipe
= intel_crtc
->pipe
;
5828 struct drm_display_mode
*mode
;
5829 int htot
= I915_READ(HTOTAL(pipe
));
5830 int hsync
= I915_READ(HSYNC(pipe
));
5831 int vtot
= I915_READ(VTOTAL(pipe
));
5832 int vsync
= I915_READ(VSYNC(pipe
));
5834 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
5838 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
5839 mode
->hdisplay
= (htot
& 0xffff) + 1;
5840 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
5841 mode
->hsync_start
= (hsync
& 0xffff) + 1;
5842 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
5843 mode
->vdisplay
= (vtot
& 0xffff) + 1;
5844 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
5845 mode
->vsync_start
= (vsync
& 0xffff) + 1;
5846 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
5848 drm_mode_set_name(mode
);
5853 #define GPU_IDLE_TIMEOUT 500 /* ms */
5855 /* When this timer fires, we've been idle for awhile */
5856 static void intel_gpu_idle_timer(unsigned long arg
)
5858 struct drm_device
*dev
= (struct drm_device
*)arg
;
5859 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5861 if (!list_empty(&dev_priv
->mm
.active_list
)) {
5862 /* Still processing requests, so just re-arm the timer. */
5863 mod_timer(&dev_priv
->idle_timer
, jiffies
+
5864 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
5868 dev_priv
->busy
= false;
5869 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
5872 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5874 static void intel_crtc_idle_timer(unsigned long arg
)
5876 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
5877 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5878 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
5879 struct intel_framebuffer
*intel_fb
;
5881 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5882 if (intel_fb
&& intel_fb
->obj
->active
) {
5883 /* The framebuffer is still being accessed by the GPU. */
5884 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5885 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5889 intel_crtc
->busy
= false;
5890 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
5893 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
5895 struct drm_device
*dev
= crtc
->dev
;
5896 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5897 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5898 int pipe
= intel_crtc
->pipe
;
5899 int dpll_reg
= DPLL(pipe
);
5902 if (HAS_PCH_SPLIT(dev
))
5905 if (!dev_priv
->lvds_downclock_avail
)
5908 dpll
= I915_READ(dpll_reg
);
5909 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
5910 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5912 assert_panel_unlocked(dev_priv
, pipe
);
5914 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
5915 I915_WRITE(dpll_reg
, dpll
);
5916 intel_wait_for_vblank(dev
, pipe
);
5918 dpll
= I915_READ(dpll_reg
);
5919 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
5920 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5923 /* Schedule downclock */
5924 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5925 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5928 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
5930 struct drm_device
*dev
= crtc
->dev
;
5931 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5932 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5934 if (HAS_PCH_SPLIT(dev
))
5937 if (!dev_priv
->lvds_downclock_avail
)
5941 * Since this is called by a timer, we should never get here in
5944 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
5945 int pipe
= intel_crtc
->pipe
;
5946 int dpll_reg
= DPLL(pipe
);
5949 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5951 assert_panel_unlocked(dev_priv
, pipe
);
5953 dpll
= I915_READ(dpll_reg
);
5954 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
5955 I915_WRITE(dpll_reg
, dpll
);
5956 intel_wait_for_vblank(dev
, pipe
);
5957 dpll
= I915_READ(dpll_reg
);
5958 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
5959 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5965 * intel_idle_update - adjust clocks for idleness
5966 * @work: work struct
5968 * Either the GPU or display (or both) went idle. Check the busy status
5969 * here and adjust the CRTC and GPU clocks as necessary.
5971 static void intel_idle_update(struct work_struct
*work
)
5973 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
5975 struct drm_device
*dev
= dev_priv
->dev
;
5976 struct drm_crtc
*crtc
;
5977 struct intel_crtc
*intel_crtc
;
5979 if (!i915_powersave
)
5982 mutex_lock(&dev
->struct_mutex
);
5984 i915_update_gfx_val(dev_priv
);
5986 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5987 /* Skip inactive CRTCs */
5991 intel_crtc
= to_intel_crtc(crtc
);
5992 if (!intel_crtc
->busy
)
5993 intel_decrease_pllclock(crtc
);
5997 mutex_unlock(&dev
->struct_mutex
);
6001 * intel_mark_busy - mark the GPU and possibly the display busy
6003 * @obj: object we're operating on
6005 * Callers can use this function to indicate that the GPU is busy processing
6006 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6007 * buffer), we'll also mark the display as busy, so we know to increase its
6010 void intel_mark_busy(struct drm_device
*dev
, struct drm_i915_gem_object
*obj
)
6012 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6013 struct drm_crtc
*crtc
= NULL
;
6014 struct intel_framebuffer
*intel_fb
;
6015 struct intel_crtc
*intel_crtc
;
6017 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
6020 if (!dev_priv
->busy
) {
6021 intel_sanitize_pm(dev
);
6022 dev_priv
->busy
= true;
6024 mod_timer(&dev_priv
->idle_timer
, jiffies
+
6025 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
6030 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6034 intel_crtc
= to_intel_crtc(crtc
);
6035 intel_fb
= to_intel_framebuffer(crtc
->fb
);
6036 if (intel_fb
->obj
== obj
) {
6037 if (!intel_crtc
->busy
) {
6038 /* Non-busy -> busy, upclock */
6039 intel_increase_pllclock(crtc
);
6040 intel_crtc
->busy
= true;
6042 /* Busy -> busy, put off timer */
6043 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
6044 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
6050 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6052 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6053 struct drm_device
*dev
= crtc
->dev
;
6054 struct intel_unpin_work
*work
;
6055 unsigned long flags
;
6057 spin_lock_irqsave(&dev
->event_lock
, flags
);
6058 work
= intel_crtc
->unpin_work
;
6059 intel_crtc
->unpin_work
= NULL
;
6060 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6063 cancel_work_sync(&work
->work
);
6067 drm_crtc_cleanup(crtc
);
6072 static void intel_unpin_work_fn(struct work_struct
*__work
)
6074 struct intel_unpin_work
*work
=
6075 container_of(__work
, struct intel_unpin_work
, work
);
6077 mutex_lock(&work
->dev
->struct_mutex
);
6078 intel_unpin_fb_obj(work
->old_fb_obj
);
6079 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6080 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6082 intel_update_fbc(work
->dev
);
6083 mutex_unlock(&work
->dev
->struct_mutex
);
6087 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6088 struct drm_crtc
*crtc
)
6090 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6091 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6092 struct intel_unpin_work
*work
;
6093 struct drm_i915_gem_object
*obj
;
6094 struct drm_pending_vblank_event
*e
;
6095 struct timeval tnow
, tvbl
;
6096 unsigned long flags
;
6098 /* Ignore early vblank irqs */
6099 if (intel_crtc
== NULL
)
6102 do_gettimeofday(&tnow
);
6104 spin_lock_irqsave(&dev
->event_lock
, flags
);
6105 work
= intel_crtc
->unpin_work
;
6106 if (work
== NULL
|| !work
->pending
) {
6107 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6111 intel_crtc
->unpin_work
= NULL
;
6115 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
6117 /* Called before vblank count and timestamps have
6118 * been updated for the vblank interval of flip
6119 * completion? Need to increment vblank count and
6120 * add one videorefresh duration to returned timestamp
6121 * to account for this. We assume this happened if we
6122 * get called over 0.9 frame durations after the last
6123 * timestamped vblank.
6125 * This calculation can not be used with vrefresh rates
6126 * below 5Hz (10Hz to be on the safe side) without
6127 * promoting to 64 integers.
6129 if (10 * (timeval_to_ns(&tnow
) - timeval_to_ns(&tvbl
)) >
6130 9 * crtc
->framedur_ns
) {
6131 e
->event
.sequence
++;
6132 tvbl
= ns_to_timeval(timeval_to_ns(&tvbl
) +
6136 e
->event
.tv_sec
= tvbl
.tv_sec
;
6137 e
->event
.tv_usec
= tvbl
.tv_usec
;
6139 list_add_tail(&e
->base
.link
,
6140 &e
->base
.file_priv
->event_list
);
6141 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
6144 drm_vblank_put(dev
, intel_crtc
->pipe
);
6146 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6148 obj
= work
->old_fb_obj
;
6150 atomic_clear_mask(1 << intel_crtc
->plane
,
6151 &obj
->pending_flip
.counter
);
6152 if (atomic_read(&obj
->pending_flip
) == 0)
6153 wake_up(&dev_priv
->pending_flip_queue
);
6155 schedule_work(&work
->work
);
6157 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
6160 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
6162 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6163 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
6165 do_intel_finish_page_flip(dev
, crtc
);
6168 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
6170 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6171 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
6173 do_intel_finish_page_flip(dev
, crtc
);
6176 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
6178 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6179 struct intel_crtc
*intel_crtc
=
6180 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
6181 unsigned long flags
;
6183 spin_lock_irqsave(&dev
->event_lock
, flags
);
6184 if (intel_crtc
->unpin_work
) {
6185 if ((++intel_crtc
->unpin_work
->pending
) > 1)
6186 DRM_ERROR("Prepared flip multiple times\n");
6188 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6190 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6193 static int intel_gen2_queue_flip(struct drm_device
*dev
,
6194 struct drm_crtc
*crtc
,
6195 struct drm_framebuffer
*fb
,
6196 struct drm_i915_gem_object
*obj
)
6198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6199 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6201 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6204 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6208 ret
= intel_ring_begin(ring
, 6);
6212 /* Can't queue multiple flips, so wait for the previous
6213 * one to finish before executing the next.
6215 if (intel_crtc
->plane
)
6216 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6218 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6219 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6220 intel_ring_emit(ring
, MI_NOOP
);
6221 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6222 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6223 intel_ring_emit(ring
, fb
->pitches
[0]);
6224 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6225 intel_ring_emit(ring
, 0); /* aux display base address, unused */
6226 intel_ring_advance(ring
);
6230 intel_unpin_fb_obj(obj
);
6235 static int intel_gen3_queue_flip(struct drm_device
*dev
,
6236 struct drm_crtc
*crtc
,
6237 struct drm_framebuffer
*fb
,
6238 struct drm_i915_gem_object
*obj
)
6240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6241 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6243 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6246 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6250 ret
= intel_ring_begin(ring
, 6);
6254 if (intel_crtc
->plane
)
6255 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6257 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6258 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6259 intel_ring_emit(ring
, MI_NOOP
);
6260 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
6261 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6262 intel_ring_emit(ring
, fb
->pitches
[0]);
6263 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6264 intel_ring_emit(ring
, MI_NOOP
);
6266 intel_ring_advance(ring
);
6270 intel_unpin_fb_obj(obj
);
6275 static int intel_gen4_queue_flip(struct drm_device
*dev
,
6276 struct drm_crtc
*crtc
,
6277 struct drm_framebuffer
*fb
,
6278 struct drm_i915_gem_object
*obj
)
6280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6281 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6282 uint32_t pf
, pipesrc
;
6283 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6286 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6290 ret
= intel_ring_begin(ring
, 4);
6294 /* i965+ uses the linear or tiled offsets from the
6295 * Display Registers (which do not change across a page-flip)
6296 * so we need only reprogram the base address.
6298 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6299 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6300 intel_ring_emit(ring
, fb
->pitches
[0]);
6301 intel_ring_emit(ring
,
6302 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
6305 /* XXX Enabling the panel-fitter across page-flip is so far
6306 * untested on non-native modes, so ignore it for now.
6307 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6310 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6311 intel_ring_emit(ring
, pf
| pipesrc
);
6312 intel_ring_advance(ring
);
6316 intel_unpin_fb_obj(obj
);
6321 static int intel_gen6_queue_flip(struct drm_device
*dev
,
6322 struct drm_crtc
*crtc
,
6323 struct drm_framebuffer
*fb
,
6324 struct drm_i915_gem_object
*obj
)
6326 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6327 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6328 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6329 uint32_t pf
, pipesrc
;
6332 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6336 ret
= intel_ring_begin(ring
, 4);
6340 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6341 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6342 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
6343 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6345 /* Contrary to the suggestions in the documentation,
6346 * "Enable Panel Fitter" does not seem to be required when page
6347 * flipping with a non-native mode, and worse causes a normal
6349 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6352 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6353 intel_ring_emit(ring
, pf
| pipesrc
);
6354 intel_ring_advance(ring
);
6358 intel_unpin_fb_obj(obj
);
6364 * On gen7 we currently use the blit ring because (in early silicon at least)
6365 * the render ring doesn't give us interrpts for page flip completion, which
6366 * means clients will hang after the first flip is queued. Fortunately the
6367 * blit ring generates interrupts properly, so use it instead.
6369 static int intel_gen7_queue_flip(struct drm_device
*dev
,
6370 struct drm_crtc
*crtc
,
6371 struct drm_framebuffer
*fb
,
6372 struct drm_i915_gem_object
*obj
)
6374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6375 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6376 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
6377 uint32_t plane_bit
= 0;
6380 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6384 switch(intel_crtc
->plane
) {
6386 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
6389 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
6392 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
6395 WARN_ONCE(1, "unknown plane in flip command\n");
6400 ret
= intel_ring_begin(ring
, 4);
6404 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
6405 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
6406 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6407 intel_ring_emit(ring
, (MI_NOOP
));
6408 intel_ring_advance(ring
);
6412 intel_unpin_fb_obj(obj
);
6417 static int intel_default_queue_flip(struct drm_device
*dev
,
6418 struct drm_crtc
*crtc
,
6419 struct drm_framebuffer
*fb
,
6420 struct drm_i915_gem_object
*obj
)
6425 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
6426 struct drm_framebuffer
*fb
,
6427 struct drm_pending_vblank_event
*event
)
6429 struct drm_device
*dev
= crtc
->dev
;
6430 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6431 struct intel_framebuffer
*intel_fb
;
6432 struct drm_i915_gem_object
*obj
;
6433 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6434 struct intel_unpin_work
*work
;
6435 unsigned long flags
;
6438 /* Can't change pixel format via MI display flips. */
6439 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
6443 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6444 * Note that pitch changes could also affect these register.
6446 if (INTEL_INFO(dev
)->gen
> 3 &&
6447 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
6448 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
6451 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
6455 work
->event
= event
;
6456 work
->dev
= crtc
->dev
;
6457 intel_fb
= to_intel_framebuffer(crtc
->fb
);
6458 work
->old_fb_obj
= intel_fb
->obj
;
6459 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
6461 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
6465 /* We borrow the event spin lock for protecting unpin_work */
6466 spin_lock_irqsave(&dev
->event_lock
, flags
);
6467 if (intel_crtc
->unpin_work
) {
6468 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6470 drm_vblank_put(dev
, intel_crtc
->pipe
);
6472 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6475 intel_crtc
->unpin_work
= work
;
6476 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6478 intel_fb
= to_intel_framebuffer(fb
);
6479 obj
= intel_fb
->obj
;
6481 ret
= i915_mutex_lock_interruptible(dev
);
6485 /* Reference the objects for the scheduled work. */
6486 drm_gem_object_reference(&work
->old_fb_obj
->base
);
6487 drm_gem_object_reference(&obj
->base
);
6491 work
->pending_flip_obj
= obj
;
6493 work
->enable_stall_check
= true;
6495 /* Block clients from rendering to the new back buffer until
6496 * the flip occurs and the object is no longer visible.
6498 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6500 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
6502 goto cleanup_pending
;
6504 intel_disable_fbc(dev
);
6505 intel_mark_busy(dev
, obj
);
6506 mutex_unlock(&dev
->struct_mutex
);
6508 trace_i915_flip_request(intel_crtc
->plane
, obj
);
6513 atomic_sub(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6514 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6515 drm_gem_object_unreference(&obj
->base
);
6516 mutex_unlock(&dev
->struct_mutex
);
6519 spin_lock_irqsave(&dev
->event_lock
, flags
);
6520 intel_crtc
->unpin_work
= NULL
;
6521 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6523 drm_vblank_put(dev
, intel_crtc
->pipe
);
6530 static void intel_sanitize_modesetting(struct drm_device
*dev
,
6531 int pipe
, int plane
)
6533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6537 /* Clear any frame start delays used for debugging left by the BIOS */
6540 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
6543 if (HAS_PCH_SPLIT(dev
))
6546 /* Who knows what state these registers were left in by the BIOS or
6549 * If we leave the registers in a conflicting state (e.g. with the
6550 * display plane reading from the other pipe than the one we intend
6551 * to use) then when we attempt to teardown the active mode, we will
6552 * not disable the pipes and planes in the correct order -- leaving
6553 * a plane reading from a disabled pipe and possibly leading to
6554 * undefined behaviour.
6557 reg
= DSPCNTR(plane
);
6558 val
= I915_READ(reg
);
6560 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
6562 if (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == pipe
)
6565 /* This display plane is active and attached to the other CPU pipe. */
6568 /* Disable the plane and wait for it to stop reading from the pipe. */
6569 intel_disable_plane(dev_priv
, plane
, pipe
);
6570 intel_disable_pipe(dev_priv
, pipe
);
6573 static void intel_crtc_reset(struct drm_crtc
*crtc
)
6575 struct drm_device
*dev
= crtc
->dev
;
6576 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6578 /* Reset flags back to the 'unknown' status so that they
6579 * will be correctly set on the initial modeset.
6581 intel_crtc
->dpms_mode
= -1;
6583 /* We need to fix up any BIOS configuration that conflicts with
6586 intel_sanitize_modesetting(dev
, intel_crtc
->pipe
, intel_crtc
->plane
);
6589 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
6590 .dpms
= intel_crtc_dpms
,
6591 .mode_fixup
= intel_crtc_mode_fixup
,
6592 .mode_set
= intel_crtc_mode_set
,
6593 .mode_set_base
= intel_pipe_set_base
,
6594 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
6595 .load_lut
= intel_crtc_load_lut
,
6596 .disable
= intel_crtc_disable
,
6599 static const struct drm_crtc_funcs intel_crtc_funcs
= {
6600 .reset
= intel_crtc_reset
,
6601 .cursor_set
= intel_crtc_cursor_set
,
6602 .cursor_move
= intel_crtc_cursor_move
,
6603 .gamma_set
= intel_crtc_gamma_set
,
6604 .set_config
= drm_crtc_helper_set_config
,
6605 .destroy
= intel_crtc_destroy
,
6606 .page_flip
= intel_crtc_page_flip
,
6609 static void intel_pch_pll_init(struct drm_device
*dev
)
6611 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6614 if (dev_priv
->num_pch_pll
== 0) {
6615 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6619 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
6620 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
6621 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
6622 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
6626 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
6628 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6629 struct intel_crtc
*intel_crtc
;
6632 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
6633 if (intel_crtc
== NULL
)
6636 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
6638 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
6639 for (i
= 0; i
< 256; i
++) {
6640 intel_crtc
->lut_r
[i
] = i
;
6641 intel_crtc
->lut_g
[i
] = i
;
6642 intel_crtc
->lut_b
[i
] = i
;
6645 /* Swap pipes & planes for FBC on pre-965 */
6646 intel_crtc
->pipe
= pipe
;
6647 intel_crtc
->plane
= pipe
;
6648 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
6649 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6650 intel_crtc
->plane
= !pipe
;
6653 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
6654 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
6655 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
6656 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
6658 intel_crtc_reset(&intel_crtc
->base
);
6659 intel_crtc
->active
= true; /* force the pipe off on setup_init_config */
6660 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
6662 if (HAS_PCH_SPLIT(dev
)) {
6663 intel_helper_funcs
.prepare
= ironlake_crtc_prepare
;
6664 intel_helper_funcs
.commit
= ironlake_crtc_commit
;
6666 intel_helper_funcs
.prepare
= i9xx_crtc_prepare
;
6667 intel_helper_funcs
.commit
= i9xx_crtc_commit
;
6670 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
6672 intel_crtc
->busy
= false;
6674 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
6675 (unsigned long)intel_crtc
);
6678 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
6679 struct drm_file
*file
)
6681 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
6682 struct drm_mode_object
*drmmode_obj
;
6683 struct intel_crtc
*crtc
;
6685 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
6688 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
6689 DRM_MODE_OBJECT_CRTC
);
6692 DRM_ERROR("no such CRTC id\n");
6696 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
6697 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
6702 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
6704 struct intel_encoder
*encoder
;
6708 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6709 if (type_mask
& encoder
->clone_mask
)
6710 index_mask
|= (1 << entry
);
6717 static bool has_edp_a(struct drm_device
*dev
)
6719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6721 if (!IS_MOBILE(dev
))
6724 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
6728 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
6734 static void intel_setup_outputs(struct drm_device
*dev
)
6736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6737 struct intel_encoder
*encoder
;
6738 bool dpd_is_edp
= false;
6741 has_lvds
= intel_lvds_init(dev
);
6742 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
6743 /* disable the panel fitter on everything but LVDS */
6744 I915_WRITE(PFIT_CONTROL
, 0);
6747 if (HAS_PCH_SPLIT(dev
)) {
6748 dpd_is_edp
= intel_dpd_is_edp(dev
);
6751 intel_dp_init(dev
, DP_A
);
6753 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6754 intel_dp_init(dev
, PCH_DP_D
);
6757 intel_crt_init(dev
);
6759 if (IS_HASWELL(dev
)) {
6762 /* Haswell uses DDI functions to detect digital outputs */
6763 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
6764 /* DDI A only supports eDP */
6766 intel_ddi_init(dev
, PORT_A
);
6768 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6770 found
= I915_READ(SFUSE_STRAP
);
6772 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
6773 intel_ddi_init(dev
, PORT_B
);
6774 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
6775 intel_ddi_init(dev
, PORT_C
);
6776 if (found
& SFUSE_STRAP_DDID_DETECTED
)
6777 intel_ddi_init(dev
, PORT_D
);
6778 } else if (HAS_PCH_SPLIT(dev
)) {
6781 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
6782 /* PCH SDVOB multiplex with HDMIB */
6783 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
6785 intel_hdmi_init(dev
, HDMIB
);
6786 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
6787 intel_dp_init(dev
, PCH_DP_B
);
6790 if (I915_READ(HDMIC
) & PORT_DETECTED
)
6791 intel_hdmi_init(dev
, HDMIC
);
6793 if (!dpd_is_edp
&& I915_READ(HDMID
) & PORT_DETECTED
)
6794 intel_hdmi_init(dev
, HDMID
);
6796 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
6797 intel_dp_init(dev
, PCH_DP_C
);
6799 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6800 intel_dp_init(dev
, PCH_DP_D
);
6801 } else if (IS_VALLEYVIEW(dev
)) {
6804 if (I915_READ(SDVOB
) & PORT_DETECTED
) {
6805 /* SDVOB multiplex with HDMIB */
6806 found
= intel_sdvo_init(dev
, SDVOB
, true);
6808 intel_hdmi_init(dev
, SDVOB
);
6809 if (!found
&& (I915_READ(DP_B
) & DP_DETECTED
))
6810 intel_dp_init(dev
, DP_B
);
6813 if (I915_READ(SDVOC
) & PORT_DETECTED
)
6814 intel_hdmi_init(dev
, SDVOC
);
6816 /* Shares lanes with HDMI on SDVOC */
6817 if (I915_READ(DP_C
) & DP_DETECTED
)
6818 intel_dp_init(dev
, DP_C
);
6819 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
6822 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6823 DRM_DEBUG_KMS("probing SDVOB\n");
6824 found
= intel_sdvo_init(dev
, SDVOB
, true);
6825 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
6826 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6827 intel_hdmi_init(dev
, SDVOB
);
6830 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
6831 DRM_DEBUG_KMS("probing DP_B\n");
6832 intel_dp_init(dev
, DP_B
);
6836 /* Before G4X SDVOC doesn't have its own detect register */
6838 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6839 DRM_DEBUG_KMS("probing SDVOC\n");
6840 found
= intel_sdvo_init(dev
, SDVOC
, false);
6843 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
6845 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
6846 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6847 intel_hdmi_init(dev
, SDVOC
);
6849 if (SUPPORTS_INTEGRATED_DP(dev
)) {
6850 DRM_DEBUG_KMS("probing DP_C\n");
6851 intel_dp_init(dev
, DP_C
);
6855 if (SUPPORTS_INTEGRATED_DP(dev
) &&
6856 (I915_READ(DP_D
) & DP_DETECTED
)) {
6857 DRM_DEBUG_KMS("probing DP_D\n");
6858 intel_dp_init(dev
, DP_D
);
6860 } else if (IS_GEN2(dev
))
6861 intel_dvo_init(dev
);
6863 if (SUPPORTS_TV(dev
))
6866 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6867 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
6868 encoder
->base
.possible_clones
=
6869 intel_encoder_clones(dev
, encoder
->clone_mask
);
6872 /* disable all the possible outputs/crtcs before entering KMS mode */
6873 drm_helper_disable_unused_functions(dev
);
6875 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
6876 ironlake_init_pch_refclk(dev
);
6879 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
6881 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6883 drm_framebuffer_cleanup(fb
);
6884 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
6889 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
6890 struct drm_file
*file
,
6891 unsigned int *handle
)
6893 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6894 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
6896 return drm_gem_handle_create(file
, &obj
->base
, handle
);
6899 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
6900 .destroy
= intel_user_framebuffer_destroy
,
6901 .create_handle
= intel_user_framebuffer_create_handle
,
6904 int intel_framebuffer_init(struct drm_device
*dev
,
6905 struct intel_framebuffer
*intel_fb
,
6906 struct drm_mode_fb_cmd2
*mode_cmd
,
6907 struct drm_i915_gem_object
*obj
)
6911 if (obj
->tiling_mode
== I915_TILING_Y
)
6914 if (mode_cmd
->pitches
[0] & 63)
6917 switch (mode_cmd
->pixel_format
) {
6918 case DRM_FORMAT_RGB332
:
6919 case DRM_FORMAT_RGB565
:
6920 case DRM_FORMAT_XRGB8888
:
6921 case DRM_FORMAT_XBGR8888
:
6922 case DRM_FORMAT_ARGB8888
:
6923 case DRM_FORMAT_XRGB2101010
:
6924 case DRM_FORMAT_ARGB2101010
:
6925 /* RGB formats are common across chipsets */
6927 case DRM_FORMAT_YUYV
:
6928 case DRM_FORMAT_UYVY
:
6929 case DRM_FORMAT_YVYU
:
6930 case DRM_FORMAT_VYUY
:
6933 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6934 mode_cmd
->pixel_format
);
6938 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
6940 DRM_ERROR("framebuffer init failed %d\n", ret
);
6944 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
6945 intel_fb
->obj
= obj
;
6949 static struct drm_framebuffer
*
6950 intel_user_framebuffer_create(struct drm_device
*dev
,
6951 struct drm_file
*filp
,
6952 struct drm_mode_fb_cmd2
*mode_cmd
)
6954 struct drm_i915_gem_object
*obj
;
6956 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
6957 mode_cmd
->handles
[0]));
6958 if (&obj
->base
== NULL
)
6959 return ERR_PTR(-ENOENT
);
6961 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
6964 static const struct drm_mode_config_funcs intel_mode_funcs
= {
6965 .fb_create
= intel_user_framebuffer_create
,
6966 .output_poll_changed
= intel_fb_output_poll_changed
,
6969 /* Set up chip specific display functions */
6970 static void intel_init_display(struct drm_device
*dev
)
6972 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6974 /* We always want a DPMS function */
6975 if (HAS_PCH_SPLIT(dev
)) {
6976 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
6977 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
6978 dev_priv
->display
.off
= ironlake_crtc_off
;
6979 dev_priv
->display
.update_plane
= ironlake_update_plane
;
6981 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
6982 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
6983 dev_priv
->display
.off
= i9xx_crtc_off
;
6984 dev_priv
->display
.update_plane
= i9xx_update_plane
;
6987 /* Returns the core display clock speed */
6988 if (IS_VALLEYVIEW(dev
))
6989 dev_priv
->display
.get_display_clock_speed
=
6990 valleyview_get_display_clock_speed
;
6991 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
6992 dev_priv
->display
.get_display_clock_speed
=
6993 i945_get_display_clock_speed
;
6994 else if (IS_I915G(dev
))
6995 dev_priv
->display
.get_display_clock_speed
=
6996 i915_get_display_clock_speed
;
6997 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
6998 dev_priv
->display
.get_display_clock_speed
=
6999 i9xx_misc_get_display_clock_speed
;
7000 else if (IS_I915GM(dev
))
7001 dev_priv
->display
.get_display_clock_speed
=
7002 i915gm_get_display_clock_speed
;
7003 else if (IS_I865G(dev
))
7004 dev_priv
->display
.get_display_clock_speed
=
7005 i865_get_display_clock_speed
;
7006 else if (IS_I85X(dev
))
7007 dev_priv
->display
.get_display_clock_speed
=
7008 i855_get_display_clock_speed
;
7010 dev_priv
->display
.get_display_clock_speed
=
7011 i830_get_display_clock_speed
;
7013 if (HAS_PCH_SPLIT(dev
)) {
7015 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
7016 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7017 } else if (IS_GEN6(dev
)) {
7018 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
7019 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7020 } else if (IS_IVYBRIDGE(dev
)) {
7021 /* FIXME: detect B0+ stepping and use auto training */
7022 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
7023 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7024 } else if (IS_HASWELL(dev
)) {
7025 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
7026 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7028 dev_priv
->display
.update_wm
= NULL
;
7029 } else if (IS_G4X(dev
)) {
7030 dev_priv
->display
.write_eld
= g4x_write_eld
;
7033 /* Default just returns -ENODEV to indicate unsupported */
7034 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
7036 switch (INTEL_INFO(dev
)->gen
) {
7038 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
7042 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
7047 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
7051 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
7054 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
7060 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7061 * resume, or other times. This quirk makes sure that's the case for
7064 static void quirk_pipea_force(struct drm_device
*dev
)
7066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7068 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
7069 DRM_INFO("applying pipe a force quirk\n");
7073 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7075 static void quirk_ssc_force_disable(struct drm_device
*dev
)
7077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7078 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
7079 DRM_INFO("applying lvds SSC disable quirk\n");
7083 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7086 static void quirk_invert_brightness(struct drm_device
*dev
)
7088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7089 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
7090 DRM_INFO("applying inverted panel brightness quirk\n");
7093 struct intel_quirk
{
7095 int subsystem_vendor
;
7096 int subsystem_device
;
7097 void (*hook
)(struct drm_device
*dev
);
7100 static struct intel_quirk intel_quirks
[] = {
7101 /* HP Mini needs pipe A force quirk (LP: #322104) */
7102 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
7104 /* Thinkpad R31 needs pipe A force quirk */
7105 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
7106 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7107 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
7109 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7110 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
7111 /* ThinkPad X40 needs pipe A force quirk */
7113 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7114 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
7116 /* 855 & before need to leave pipe A & dpll A up */
7117 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7118 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7120 /* Lenovo U160 cannot use SSC on LVDS */
7121 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
7123 /* Sony Vaio Y cannot use SSC on LVDS */
7124 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
7126 /* Acer Aspire 5734Z must invert backlight brightness */
7127 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
7130 static void intel_init_quirks(struct drm_device
*dev
)
7132 struct pci_dev
*d
= dev
->pdev
;
7135 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
7136 struct intel_quirk
*q
= &intel_quirks
[i
];
7138 if (d
->device
== q
->device
&&
7139 (d
->subsystem_vendor
== q
->subsystem_vendor
||
7140 q
->subsystem_vendor
== PCI_ANY_ID
) &&
7141 (d
->subsystem_device
== q
->subsystem_device
||
7142 q
->subsystem_device
== PCI_ANY_ID
))
7147 /* Disable the VGA plane that we never use */
7148 static void i915_disable_vga(struct drm_device
*dev
)
7150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7154 if (HAS_PCH_SPLIT(dev
))
7155 vga_reg
= CPU_VGACNTRL
;
7159 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7160 outb(SR01
, VGA_SR_INDEX
);
7161 sr1
= inb(VGA_SR_DATA
);
7162 outb(sr1
| 1<<5, VGA_SR_DATA
);
7163 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7166 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
7167 POSTING_READ(vga_reg
);
7170 void intel_modeset_init_hw(struct drm_device
*dev
)
7172 /* We attempt to init the necessary power wells early in the initialization
7173 * time, so the subsystems that expect power to be enabled can work.
7175 intel_init_power_wells(dev
);
7177 intel_prepare_ddi(dev
);
7179 intel_init_clock_gating(dev
);
7181 mutex_lock(&dev
->struct_mutex
);
7182 intel_enable_gt_powersave(dev
);
7183 mutex_unlock(&dev
->struct_mutex
);
7186 void intel_modeset_init(struct drm_device
*dev
)
7188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7191 drm_mode_config_init(dev
);
7193 dev
->mode_config
.min_width
= 0;
7194 dev
->mode_config
.min_height
= 0;
7196 dev
->mode_config
.preferred_depth
= 24;
7197 dev
->mode_config
.prefer_shadow
= 1;
7199 dev
->mode_config
.funcs
= &intel_mode_funcs
;
7201 intel_init_quirks(dev
);
7205 intel_init_display(dev
);
7208 dev
->mode_config
.max_width
= 2048;
7209 dev
->mode_config
.max_height
= 2048;
7210 } else if (IS_GEN3(dev
)) {
7211 dev
->mode_config
.max_width
= 4096;
7212 dev
->mode_config
.max_height
= 4096;
7214 dev
->mode_config
.max_width
= 8192;
7215 dev
->mode_config
.max_height
= 8192;
7217 dev
->mode_config
.fb_base
= dev_priv
->mm
.gtt_base_addr
;
7219 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7220 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
7222 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
7223 intel_crtc_init(dev
, i
);
7224 ret
= intel_plane_init(dev
, i
);
7226 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
7229 intel_pch_pll_init(dev
);
7231 /* Just disable it once at startup */
7232 i915_disable_vga(dev
);
7233 intel_setup_outputs(dev
);
7235 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
7236 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
7237 (unsigned long)dev
);
7240 void intel_modeset_gem_init(struct drm_device
*dev
)
7242 intel_modeset_init_hw(dev
);
7244 intel_setup_overlay(dev
);
7247 void intel_modeset_cleanup(struct drm_device
*dev
)
7249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7250 struct drm_crtc
*crtc
;
7251 struct intel_crtc
*intel_crtc
;
7253 drm_kms_helper_poll_fini(dev
);
7254 mutex_lock(&dev
->struct_mutex
);
7256 intel_unregister_dsm_handler();
7259 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7260 /* Skip inactive CRTCs */
7264 intel_crtc
= to_intel_crtc(crtc
);
7265 intel_increase_pllclock(crtc
);
7268 intel_disable_fbc(dev
);
7270 intel_disable_gt_powersave(dev
);
7272 ironlake_teardown_rc6(dev
);
7274 if (IS_VALLEYVIEW(dev
))
7277 mutex_unlock(&dev
->struct_mutex
);
7279 /* Disable the irq before mode object teardown, for the irq might
7280 * enqueue unpin/hotplug work. */
7281 drm_irq_uninstall(dev
);
7282 cancel_work_sync(&dev_priv
->hotplug_work
);
7283 cancel_work_sync(&dev_priv
->rps_work
);
7285 /* flush any delayed tasks or pending work */
7286 flush_scheduled_work();
7288 /* Shut off idle work before the crtcs get freed. */
7289 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7290 intel_crtc
= to_intel_crtc(crtc
);
7291 del_timer_sync(&intel_crtc
->idle_timer
);
7293 del_timer_sync(&dev_priv
->idle_timer
);
7294 cancel_work_sync(&dev_priv
->idle_work
);
7296 drm_mode_config_cleanup(dev
);
7300 * Return which encoder is currently attached for connector.
7302 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
7304 return &intel_attached_encoder(connector
)->base
;
7307 void intel_connector_attach_encoder(struct intel_connector
*connector
,
7308 struct intel_encoder
*encoder
)
7310 connector
->encoder
= encoder
;
7311 drm_mode_connector_attach_encoder(&connector
->base
,
7316 * set vga decode state - true == enable VGA decode
7318 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
7320 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7323 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
7325 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
7327 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
7328 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
7332 #ifdef CONFIG_DEBUG_FS
7333 #include <linux/seq_file.h>
7335 struct intel_display_error_state
{
7336 struct intel_cursor_error_state
{
7343 struct intel_pipe_error_state
{
7355 struct intel_plane_error_state
{
7366 struct intel_display_error_state
*
7367 intel_display_capture_error_state(struct drm_device
*dev
)
7369 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7370 struct intel_display_error_state
*error
;
7373 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
7377 for (i
= 0; i
< 2; i
++) {
7378 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
7379 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
7380 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
7382 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
7383 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
7384 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
7385 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
7386 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
7387 if (INTEL_INFO(dev
)->gen
>= 4) {
7388 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
7389 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
7392 error
->pipe
[i
].conf
= I915_READ(PIPECONF(i
));
7393 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
7394 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(i
));
7395 error
->pipe
[i
].hblank
= I915_READ(HBLANK(i
));
7396 error
->pipe
[i
].hsync
= I915_READ(HSYNC(i
));
7397 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(i
));
7398 error
->pipe
[i
].vblank
= I915_READ(VBLANK(i
));
7399 error
->pipe
[i
].vsync
= I915_READ(VSYNC(i
));
7406 intel_display_print_error_state(struct seq_file
*m
,
7407 struct drm_device
*dev
,
7408 struct intel_display_error_state
*error
)
7412 for (i
= 0; i
< 2; i
++) {
7413 seq_printf(m
, "Pipe [%d]:\n", i
);
7414 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
7415 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
7416 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
7417 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
7418 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
7419 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
7420 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
7421 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
7423 seq_printf(m
, "Plane [%d]:\n", i
);
7424 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
7425 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
7426 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
7427 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
7428 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
7429 if (INTEL_INFO(dev
)->gen
>= 4) {
7430 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
7431 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
7434 seq_printf(m
, "Cursor [%d]:\n", i
);
7435 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
7436 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
7437 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);