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drm/i915/gen9: Assume CDCLK PLL is off if it's not locked
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
50
51 static bool is_mmio_work(struct intel_flip_work *work)
52 {
53 return work->mmio_work.func;
54 }
55
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB1555,
61 DRM_FORMAT_XRGB8888,
62 };
63
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_C8,
67 DRM_FORMAT_RGB565,
68 DRM_FORMAT_XRGB8888,
69 DRM_FORMAT_XBGR8888,
70 DRM_FORMAT_XRGB2101010,
71 DRM_FORMAT_XBGR2101010,
72 };
73
74 static const uint32_t skl_primary_formats[] = {
75 DRM_FORMAT_C8,
76 DRM_FORMAT_RGB565,
77 DRM_FORMAT_XRGB8888,
78 DRM_FORMAT_XBGR8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_XRGB2101010,
82 DRM_FORMAT_XBGR2101010,
83 DRM_FORMAT_YUYV,
84 DRM_FORMAT_YVYU,
85 DRM_FORMAT_UYVY,
86 DRM_FORMAT_VYUY,
87 };
88
89 /* Cursor formats */
90 static const uint32_t intel_cursor_formats[] = {
91 DRM_FORMAT_ARGB8888,
92 };
93
94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
95 struct intel_crtc_state *pipe_config);
96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 struct intel_crtc_state *pipe_config);
98
99 static int intel_framebuffer_init(struct drm_device *dev,
100 struct intel_framebuffer *ifb,
101 struct drm_mode_fb_cmd2 *mode_cmd,
102 struct drm_i915_gem_object *obj);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
126 static int broxton_calc_cdclk(int max_pixclk);
127
128 struct intel_limit {
129 struct {
130 int min, max;
131 } dot, vco, n, m, m1, m2, p, p1;
132
133 struct {
134 int dot_limit;
135 int p2_slow, p2_fast;
136 } p2;
137 };
138
139 /* returns HPLL frequency in kHz */
140 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
141 {
142 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
143
144 /* Obtain SKU information */
145 mutex_lock(&dev_priv->sb_lock);
146 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
147 CCK_FUSE_HPLL_FREQ_MASK;
148 mutex_unlock(&dev_priv->sb_lock);
149
150 return vco_freq[hpll_freq] * 1000;
151 }
152
153 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
154 const char *name, u32 reg, int ref_freq)
155 {
156 u32 val;
157 int divider;
158
159 mutex_lock(&dev_priv->sb_lock);
160 val = vlv_cck_read(dev_priv, reg);
161 mutex_unlock(&dev_priv->sb_lock);
162
163 divider = val & CCK_FREQUENCY_VALUES;
164
165 WARN((val & CCK_FREQUENCY_STATUS) !=
166 (divider << CCK_FREQUENCY_STATUS_SHIFT),
167 "%s change in progress\n", name);
168
169 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
170 }
171
172 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
173 const char *name, u32 reg)
174 {
175 if (dev_priv->hpll_freq == 0)
176 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
177
178 return vlv_get_cck_clock(dev_priv, name, reg,
179 dev_priv->hpll_freq);
180 }
181
182 static int
183 intel_pch_rawclk(struct drm_i915_private *dev_priv)
184 {
185 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
186 }
187
188 static int
189 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
190 {
191 /* RAWCLK_FREQ_VLV register updated from power well code */
192 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
193 CCK_DISPLAY_REF_CLOCK_CONTROL);
194 }
195
196 static int
197 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
198 {
199 uint32_t clkcfg;
200
201 /* hrawclock is 1/4 the FSB frequency */
202 clkcfg = I915_READ(CLKCFG);
203 switch (clkcfg & CLKCFG_FSB_MASK) {
204 case CLKCFG_FSB_400:
205 return 100000;
206 case CLKCFG_FSB_533:
207 return 133333;
208 case CLKCFG_FSB_667:
209 return 166667;
210 case CLKCFG_FSB_800:
211 return 200000;
212 case CLKCFG_FSB_1067:
213 return 266667;
214 case CLKCFG_FSB_1333:
215 return 333333;
216 /* these two are just a guess; one of them might be right */
217 case CLKCFG_FSB_1600:
218 case CLKCFG_FSB_1600_ALT:
219 return 400000;
220 default:
221 return 133333;
222 }
223 }
224
225 void intel_update_rawclk(struct drm_i915_private *dev_priv)
226 {
227 if (HAS_PCH_SPLIT(dev_priv))
228 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
229 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
230 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
231 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
232 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
233 else
234 return; /* no rawclk on other platforms, or no need to know it */
235
236 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
237 }
238
239 static void intel_update_czclk(struct drm_i915_private *dev_priv)
240 {
241 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
242 return;
243
244 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
245 CCK_CZ_CLOCK_CONTROL);
246
247 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
248 }
249
250 static inline u32 /* units of 100MHz */
251 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
252 const struct intel_crtc_state *pipe_config)
253 {
254 if (HAS_DDI(dev_priv))
255 return pipe_config->port_clock; /* SPLL */
256 else if (IS_GEN5(dev_priv))
257 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
258 else
259 return 270000;
260 }
261
262 static const struct intel_limit intel_limits_i8xx_dac = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 908000, .max = 1512000 },
265 .n = { .min = 2, .max = 16 },
266 .m = { .min = 96, .max = 140 },
267 .m1 = { .min = 18, .max = 26 },
268 .m2 = { .min = 6, .max = 16 },
269 .p = { .min = 4, .max = 128 },
270 .p1 = { .min = 2, .max = 33 },
271 .p2 = { .dot_limit = 165000,
272 .p2_slow = 4, .p2_fast = 2 },
273 };
274
275 static const struct intel_limit intel_limits_i8xx_dvo = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 908000, .max = 1512000 },
278 .n = { .min = 2, .max = 16 },
279 .m = { .min = 96, .max = 140 },
280 .m1 = { .min = 18, .max = 26 },
281 .m2 = { .min = 6, .max = 16 },
282 .p = { .min = 4, .max = 128 },
283 .p1 = { .min = 2, .max = 33 },
284 .p2 = { .dot_limit = 165000,
285 .p2_slow = 4, .p2_fast = 4 },
286 };
287
288 static const struct intel_limit intel_limits_i8xx_lvds = {
289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 908000, .max = 1512000 },
291 .n = { .min = 2, .max = 16 },
292 .m = { .min = 96, .max = 140 },
293 .m1 = { .min = 18, .max = 26 },
294 .m2 = { .min = 6, .max = 16 },
295 .p = { .min = 4, .max = 128 },
296 .p1 = { .min = 1, .max = 6 },
297 .p2 = { .dot_limit = 165000,
298 .p2_slow = 14, .p2_fast = 7 },
299 };
300
301 static const struct intel_limit intel_limits_i9xx_sdvo = {
302 .dot = { .min = 20000, .max = 400000 },
303 .vco = { .min = 1400000, .max = 2800000 },
304 .n = { .min = 1, .max = 6 },
305 .m = { .min = 70, .max = 120 },
306 .m1 = { .min = 8, .max = 18 },
307 .m2 = { .min = 3, .max = 7 },
308 .p = { .min = 5, .max = 80 },
309 .p1 = { .min = 1, .max = 8 },
310 .p2 = { .dot_limit = 200000,
311 .p2_slow = 10, .p2_fast = 5 },
312 };
313
314 static const struct intel_limit intel_limits_i9xx_lvds = {
315 .dot = { .min = 20000, .max = 400000 },
316 .vco = { .min = 1400000, .max = 2800000 },
317 .n = { .min = 1, .max = 6 },
318 .m = { .min = 70, .max = 120 },
319 .m1 = { .min = 8, .max = 18 },
320 .m2 = { .min = 3, .max = 7 },
321 .p = { .min = 7, .max = 98 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 112000,
324 .p2_slow = 14, .p2_fast = 7 },
325 };
326
327
328 static const struct intel_limit intel_limits_g4x_sdvo = {
329 .dot = { .min = 25000, .max = 270000 },
330 .vco = { .min = 1750000, .max = 3500000},
331 .n = { .min = 1, .max = 4 },
332 .m = { .min = 104, .max = 138 },
333 .m1 = { .min = 17, .max = 23 },
334 .m2 = { .min = 5, .max = 11 },
335 .p = { .min = 10, .max = 30 },
336 .p1 = { .min = 1, .max = 3},
337 .p2 = { .dot_limit = 270000,
338 .p2_slow = 10,
339 .p2_fast = 10
340 },
341 };
342
343 static const struct intel_limit intel_limits_g4x_hdmi = {
344 .dot = { .min = 22000, .max = 400000 },
345 .vco = { .min = 1750000, .max = 3500000},
346 .n = { .min = 1, .max = 4 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 16, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 5, .max = 80 },
351 .p1 = { .min = 1, .max = 8},
352 .p2 = { .dot_limit = 165000,
353 .p2_slow = 10, .p2_fast = 5 },
354 };
355
356 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
357 .dot = { .min = 20000, .max = 115000 },
358 .vco = { .min = 1750000, .max = 3500000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 104, .max = 138 },
361 .m1 = { .min = 17, .max = 23 },
362 .m2 = { .min = 5, .max = 11 },
363 .p = { .min = 28, .max = 112 },
364 .p1 = { .min = 2, .max = 8 },
365 .p2 = { .dot_limit = 0,
366 .p2_slow = 14, .p2_fast = 14
367 },
368 };
369
370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
371 .dot = { .min = 80000, .max = 224000 },
372 .vco = { .min = 1750000, .max = 3500000 },
373 .n = { .min = 1, .max = 3 },
374 .m = { .min = 104, .max = 138 },
375 .m1 = { .min = 17, .max = 23 },
376 .m2 = { .min = 5, .max = 11 },
377 .p = { .min = 14, .max = 42 },
378 .p1 = { .min = 2, .max = 6 },
379 .p2 = { .dot_limit = 0,
380 .p2_slow = 7, .p2_fast = 7
381 },
382 };
383
384 static const struct intel_limit intel_limits_pineview_sdvo = {
385 .dot = { .min = 20000, .max = 400000},
386 .vco = { .min = 1700000, .max = 3500000 },
387 /* Pineview's Ncounter is a ring counter */
388 .n = { .min = 3, .max = 6 },
389 .m = { .min = 2, .max = 256 },
390 /* Pineview only has one combined m divider, which we treat as m2. */
391 .m1 = { .min = 0, .max = 0 },
392 .m2 = { .min = 0, .max = 254 },
393 .p = { .min = 5, .max = 80 },
394 .p1 = { .min = 1, .max = 8 },
395 .p2 = { .dot_limit = 200000,
396 .p2_slow = 10, .p2_fast = 5 },
397 };
398
399 static const struct intel_limit intel_limits_pineview_lvds = {
400 .dot = { .min = 20000, .max = 400000 },
401 .vco = { .min = 1700000, .max = 3500000 },
402 .n = { .min = 3, .max = 6 },
403 .m = { .min = 2, .max = 256 },
404 .m1 = { .min = 0, .max = 0 },
405 .m2 = { .min = 0, .max = 254 },
406 .p = { .min = 7, .max = 112 },
407 .p1 = { .min = 1, .max = 8 },
408 .p2 = { .dot_limit = 112000,
409 .p2_slow = 14, .p2_fast = 14 },
410 };
411
412 /* Ironlake / Sandybridge
413 *
414 * We calculate clock using (register_value + 2) for N/M1/M2, so here
415 * the range value for them is (actual_value - 2).
416 */
417 static const struct intel_limit intel_limits_ironlake_dac = {
418 .dot = { .min = 25000, .max = 350000 },
419 .vco = { .min = 1760000, .max = 3510000 },
420 .n = { .min = 1, .max = 5 },
421 .m = { .min = 79, .max = 127 },
422 .m1 = { .min = 12, .max = 22 },
423 .m2 = { .min = 5, .max = 9 },
424 .p = { .min = 5, .max = 80 },
425 .p1 = { .min = 1, .max = 8 },
426 .p2 = { .dot_limit = 225000,
427 .p2_slow = 10, .p2_fast = 5 },
428 };
429
430 static const struct intel_limit intel_limits_ironlake_single_lvds = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 3 },
434 .m = { .min = 79, .max = 118 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 127 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 56 },
451 .p1 = { .min = 2, .max = 8 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 /* LVDS 100mhz refclk limits. */
457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
458 .dot = { .min = 25000, .max = 350000 },
459 .vco = { .min = 1760000, .max = 3510000 },
460 .n = { .min = 1, .max = 2 },
461 .m = { .min = 79, .max = 126 },
462 .m1 = { .min = 12, .max = 22 },
463 .m2 = { .min = 5, .max = 9 },
464 .p = { .min = 28, .max = 112 },
465 .p1 = { .min = 2, .max = 8 },
466 .p2 = { .dot_limit = 225000,
467 .p2_slow = 14, .p2_fast = 14 },
468 };
469
470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
471 .dot = { .min = 25000, .max = 350000 },
472 .vco = { .min = 1760000, .max = 3510000 },
473 .n = { .min = 1, .max = 3 },
474 .m = { .min = 79, .max = 126 },
475 .m1 = { .min = 12, .max = 22 },
476 .m2 = { .min = 5, .max = 9 },
477 .p = { .min = 14, .max = 42 },
478 .p1 = { .min = 2, .max = 6 },
479 .p2 = { .dot_limit = 225000,
480 .p2_slow = 7, .p2_fast = 7 },
481 };
482
483 static const struct intel_limit intel_limits_vlv = {
484 /*
485 * These are the data rate limits (measured in fast clocks)
486 * since those are the strictest limits we have. The fast
487 * clock and actual rate limits are more relaxed, so checking
488 * them would make no difference.
489 */
490 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
491 .vco = { .min = 4000000, .max = 6000000 },
492 .n = { .min = 1, .max = 7 },
493 .m1 = { .min = 2, .max = 3 },
494 .m2 = { .min = 11, .max = 156 },
495 .p1 = { .min = 2, .max = 3 },
496 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
497 };
498
499 static const struct intel_limit intel_limits_chv = {
500 /*
501 * These are the data rate limits (measured in fast clocks)
502 * since those are the strictest limits we have. The fast
503 * clock and actual rate limits are more relaxed, so checking
504 * them would make no difference.
505 */
506 .dot = { .min = 25000 * 5, .max = 540000 * 5},
507 .vco = { .min = 4800000, .max = 6480000 },
508 .n = { .min = 1, .max = 1 },
509 .m1 = { .min = 2, .max = 2 },
510 .m2 = { .min = 24 << 22, .max = 175 << 22 },
511 .p1 = { .min = 2, .max = 4 },
512 .p2 = { .p2_slow = 1, .p2_fast = 14 },
513 };
514
515 static const struct intel_limit intel_limits_bxt = {
516 /* FIXME: find real dot limits */
517 .dot = { .min = 0, .max = INT_MAX },
518 .vco = { .min = 4800000, .max = 6700000 },
519 .n = { .min = 1, .max = 1 },
520 .m1 = { .min = 2, .max = 2 },
521 /* FIXME: find real m2 limits */
522 .m2 = { .min = 2 << 22, .max = 255 << 22 },
523 .p1 = { .min = 2, .max = 4 },
524 .p2 = { .p2_slow = 1, .p2_fast = 20 },
525 };
526
527 static bool
528 needs_modeset(struct drm_crtc_state *state)
529 {
530 return drm_atomic_crtc_needs_modeset(state);
531 }
532
533 /**
534 * Returns whether any output on the specified pipe is of the specified type
535 */
536 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
537 {
538 struct drm_device *dev = crtc->base.dev;
539 struct intel_encoder *encoder;
540
541 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
542 if (encoder->type == type)
543 return true;
544
545 return false;
546 }
547
548 /**
549 * Returns whether any output on the specified pipe will have the specified
550 * type after a staged modeset is complete, i.e., the same as
551 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
552 * encoder->crtc.
553 */
554 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
555 int type)
556 {
557 struct drm_atomic_state *state = crtc_state->base.state;
558 struct drm_connector *connector;
559 struct drm_connector_state *connector_state;
560 struct intel_encoder *encoder;
561 int i, num_connectors = 0;
562
563 for_each_connector_in_state(state, connector, connector_state, i) {
564 if (connector_state->crtc != crtc_state->base.crtc)
565 continue;
566
567 num_connectors++;
568
569 encoder = to_intel_encoder(connector_state->best_encoder);
570 if (encoder->type == type)
571 return true;
572 }
573
574 WARN_ON(num_connectors == 0);
575
576 return false;
577 }
578
579 /*
580 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
581 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
582 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
583 * The helpers' return value is the rate of the clock that is fed to the
584 * display engine's pipe which can be the above fast dot clock rate or a
585 * divided-down version of it.
586 */
587 /* m1 is reserved as 0 in Pineview, n is a ring counter */
588 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
589 {
590 clock->m = clock->m2 + 2;
591 clock->p = clock->p1 * clock->p2;
592 if (WARN_ON(clock->n == 0 || clock->p == 0))
593 return 0;
594 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
595 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
596
597 return clock->dot;
598 }
599
600 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
601 {
602 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
603 }
604
605 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
606 {
607 clock->m = i9xx_dpll_compute_m(clock);
608 clock->p = clock->p1 * clock->p2;
609 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
610 return 0;
611 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
612 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
613
614 return clock->dot;
615 }
616
617 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
618 {
619 clock->m = clock->m1 * clock->m2;
620 clock->p = clock->p1 * clock->p2;
621 if (WARN_ON(clock->n == 0 || clock->p == 0))
622 return 0;
623 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
624 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
625
626 return clock->dot / 5;
627 }
628
629 int chv_calc_dpll_params(int refclk, struct dpll *clock)
630 {
631 clock->m = clock->m1 * clock->m2;
632 clock->p = clock->p1 * clock->p2;
633 if (WARN_ON(clock->n == 0 || clock->p == 0))
634 return 0;
635 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
636 clock->n << 22);
637 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
638
639 return clock->dot / 5;
640 }
641
642 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
643 /**
644 * Returns whether the given set of divisors are valid for a given refclk with
645 * the given connectors.
646 */
647
648 static bool intel_PLL_is_valid(struct drm_device *dev,
649 const struct intel_limit *limit,
650 const struct dpll *clock)
651 {
652 if (clock->n < limit->n.min || limit->n.max < clock->n)
653 INTELPllInvalid("n out of range\n");
654 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
655 INTELPllInvalid("p1 out of range\n");
656 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
657 INTELPllInvalid("m2 out of range\n");
658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
659 INTELPllInvalid("m1 out of range\n");
660
661 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
662 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
663 if (clock->m1 <= clock->m2)
664 INTELPllInvalid("m1 <= m2\n");
665
666 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
667 if (clock->p < limit->p.min || limit->p.max < clock->p)
668 INTELPllInvalid("p out of range\n");
669 if (clock->m < limit->m.min || limit->m.max < clock->m)
670 INTELPllInvalid("m out of range\n");
671 }
672
673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
674 INTELPllInvalid("vco out of range\n");
675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
679 INTELPllInvalid("dot out of range\n");
680
681 return true;
682 }
683
684 static int
685 i9xx_select_p2_div(const struct intel_limit *limit,
686 const struct intel_crtc_state *crtc_state,
687 int target)
688 {
689 struct drm_device *dev = crtc_state->base.crtc->dev;
690
691 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
692 /*
693 * For LVDS just rely on its current settings for dual-channel.
694 * We haven't figured out how to reliably set up different
695 * single/dual channel state, if we even can.
696 */
697 if (intel_is_dual_link_lvds(dev))
698 return limit->p2.p2_fast;
699 else
700 return limit->p2.p2_slow;
701 } else {
702 if (target < limit->p2.dot_limit)
703 return limit->p2.p2_slow;
704 else
705 return limit->p2.p2_fast;
706 }
707 }
708
709 /*
710 * Returns a set of divisors for the desired target clock with the given
711 * refclk, or FALSE. The returned values represent the clock equation:
712 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
713 *
714 * Target and reference clocks are specified in kHz.
715 *
716 * If match_clock is provided, then best_clock P divider must match the P
717 * divider from @match_clock used for LVDS downclocking.
718 */
719 static bool
720 i9xx_find_best_dpll(const struct intel_limit *limit,
721 struct intel_crtc_state *crtc_state,
722 int target, int refclk, struct dpll *match_clock,
723 struct dpll *best_clock)
724 {
725 struct drm_device *dev = crtc_state->base.crtc->dev;
726 struct dpll clock;
727 int err = target;
728
729 memset(best_clock, 0, sizeof(*best_clock));
730
731 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
732
733 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
734 clock.m1++) {
735 for (clock.m2 = limit->m2.min;
736 clock.m2 <= limit->m2.max; clock.m2++) {
737 if (clock.m2 >= clock.m1)
738 break;
739 for (clock.n = limit->n.min;
740 clock.n <= limit->n.max; clock.n++) {
741 for (clock.p1 = limit->p1.min;
742 clock.p1 <= limit->p1.max; clock.p1++) {
743 int this_err;
744
745 i9xx_calc_dpll_params(refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
748 continue;
749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
752
753 this_err = abs(clock.dot - target);
754 if (this_err < err) {
755 *best_clock = clock;
756 err = this_err;
757 }
758 }
759 }
760 }
761 }
762
763 return (err != target);
764 }
765
766 /*
767 * Returns a set of divisors for the desired target clock with the given
768 * refclk, or FALSE. The returned values represent the clock equation:
769 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
770 *
771 * Target and reference clocks are specified in kHz.
772 *
773 * If match_clock is provided, then best_clock P divider must match the P
774 * divider from @match_clock used for LVDS downclocking.
775 */
776 static bool
777 pnv_find_best_dpll(const struct intel_limit *limit,
778 struct intel_crtc_state *crtc_state,
779 int target, int refclk, struct dpll *match_clock,
780 struct dpll *best_clock)
781 {
782 struct drm_device *dev = crtc_state->base.crtc->dev;
783 struct dpll clock;
784 int err = target;
785
786 memset(best_clock, 0, sizeof(*best_clock));
787
788 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
789
790 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
791 clock.m1++) {
792 for (clock.m2 = limit->m2.min;
793 clock.m2 <= limit->m2.max; clock.m2++) {
794 for (clock.n = limit->n.min;
795 clock.n <= limit->n.max; clock.n++) {
796 for (clock.p1 = limit->p1.min;
797 clock.p1 <= limit->p1.max; clock.p1++) {
798 int this_err;
799
800 pnv_calc_dpll_params(refclk, &clock);
801 if (!intel_PLL_is_valid(dev, limit,
802 &clock))
803 continue;
804 if (match_clock &&
805 clock.p != match_clock->p)
806 continue;
807
808 this_err = abs(clock.dot - target);
809 if (this_err < err) {
810 *best_clock = clock;
811 err = this_err;
812 }
813 }
814 }
815 }
816 }
817
818 return (err != target);
819 }
820
821 /*
822 * Returns a set of divisors for the desired target clock with the given
823 * refclk, or FALSE. The returned values represent the clock equation:
824 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
825 *
826 * Target and reference clocks are specified in kHz.
827 *
828 * If match_clock is provided, then best_clock P divider must match the P
829 * divider from @match_clock used for LVDS downclocking.
830 */
831 static bool
832 g4x_find_best_dpll(const struct intel_limit *limit,
833 struct intel_crtc_state *crtc_state,
834 int target, int refclk, struct dpll *match_clock,
835 struct dpll *best_clock)
836 {
837 struct drm_device *dev = crtc_state->base.crtc->dev;
838 struct dpll clock;
839 int max_n;
840 bool found = false;
841 /* approximately equals target * 0.00585 */
842 int err_most = (target >> 8) + (target >> 9);
843
844 memset(best_clock, 0, sizeof(*best_clock));
845
846 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
847
848 max_n = limit->n.max;
849 /* based on hardware requirement, prefer smaller n to precision */
850 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
851 /* based on hardware requirement, prefere larger m1,m2 */
852 for (clock.m1 = limit->m1.max;
853 clock.m1 >= limit->m1.min; clock.m1--) {
854 for (clock.m2 = limit->m2.max;
855 clock.m2 >= limit->m2.min; clock.m2--) {
856 for (clock.p1 = limit->p1.max;
857 clock.p1 >= limit->p1.min; clock.p1--) {
858 int this_err;
859
860 i9xx_calc_dpll_params(refclk, &clock);
861 if (!intel_PLL_is_valid(dev, limit,
862 &clock))
863 continue;
864
865 this_err = abs(clock.dot - target);
866 if (this_err < err_most) {
867 *best_clock = clock;
868 err_most = this_err;
869 max_n = clock.n;
870 found = true;
871 }
872 }
873 }
874 }
875 }
876 return found;
877 }
878
879 /*
880 * Check if the calculated PLL configuration is more optimal compared to the
881 * best configuration and error found so far. Return the calculated error.
882 */
883 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
884 const struct dpll *calculated_clock,
885 const struct dpll *best_clock,
886 unsigned int best_error_ppm,
887 unsigned int *error_ppm)
888 {
889 /*
890 * For CHV ignore the error and consider only the P value.
891 * Prefer a bigger P value based on HW requirements.
892 */
893 if (IS_CHERRYVIEW(dev)) {
894 *error_ppm = 0;
895
896 return calculated_clock->p > best_clock->p;
897 }
898
899 if (WARN_ON_ONCE(!target_freq))
900 return false;
901
902 *error_ppm = div_u64(1000000ULL *
903 abs(target_freq - calculated_clock->dot),
904 target_freq);
905 /*
906 * Prefer a better P value over a better (smaller) error if the error
907 * is small. Ensure this preference for future configurations too by
908 * setting the error to 0.
909 */
910 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
911 *error_ppm = 0;
912
913 return true;
914 }
915
916 return *error_ppm + 10 < best_error_ppm;
917 }
918
919 /*
920 * Returns a set of divisors for the desired target clock with the given
921 * refclk, or FALSE. The returned values represent the clock equation:
922 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
923 */
924 static bool
925 vlv_find_best_dpll(const struct intel_limit *limit,
926 struct intel_crtc_state *crtc_state,
927 int target, int refclk, struct dpll *match_clock,
928 struct dpll *best_clock)
929 {
930 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
931 struct drm_device *dev = crtc->base.dev;
932 struct dpll clock;
933 unsigned int bestppm = 1000000;
934 /* min update 19.2 MHz */
935 int max_n = min(limit->n.max, refclk / 19200);
936 bool found = false;
937
938 target *= 5; /* fast clock */
939
940 memset(best_clock, 0, sizeof(*best_clock));
941
942 /* based on hardware requirement, prefer smaller n to precision */
943 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
944 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
945 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
947 clock.p = clock.p1 * clock.p2;
948 /* based on hardware requirement, prefer bigger m1,m2 values */
949 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
950 unsigned int ppm;
951
952 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
953 refclk * clock.m1);
954
955 vlv_calc_dpll_params(refclk, &clock);
956
957 if (!intel_PLL_is_valid(dev, limit,
958 &clock))
959 continue;
960
961 if (!vlv_PLL_is_optimal(dev, target,
962 &clock,
963 best_clock,
964 bestppm, &ppm))
965 continue;
966
967 *best_clock = clock;
968 bestppm = ppm;
969 found = true;
970 }
971 }
972 }
973 }
974
975 return found;
976 }
977
978 /*
979 * Returns a set of divisors for the desired target clock with the given
980 * refclk, or FALSE. The returned values represent the clock equation:
981 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
982 */
983 static bool
984 chv_find_best_dpll(const struct intel_limit *limit,
985 struct intel_crtc_state *crtc_state,
986 int target, int refclk, struct dpll *match_clock,
987 struct dpll *best_clock)
988 {
989 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
990 struct drm_device *dev = crtc->base.dev;
991 unsigned int best_error_ppm;
992 struct dpll clock;
993 uint64_t m2;
994 int found = false;
995
996 memset(best_clock, 0, sizeof(*best_clock));
997 best_error_ppm = 1000000;
998
999 /*
1000 * Based on hardware doc, the n always set to 1, and m1 always
1001 * set to 2. If requires to support 200Mhz refclk, we need to
1002 * revisit this because n may not 1 anymore.
1003 */
1004 clock.n = 1, clock.m1 = 2;
1005 target *= 5; /* fast clock */
1006
1007 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1008 for (clock.p2 = limit->p2.p2_fast;
1009 clock.p2 >= limit->p2.p2_slow;
1010 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1011 unsigned int error_ppm;
1012
1013 clock.p = clock.p1 * clock.p2;
1014
1015 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1016 clock.n) << 22, refclk * clock.m1);
1017
1018 if (m2 > INT_MAX/clock.m1)
1019 continue;
1020
1021 clock.m2 = m2;
1022
1023 chv_calc_dpll_params(refclk, &clock);
1024
1025 if (!intel_PLL_is_valid(dev, limit, &clock))
1026 continue;
1027
1028 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1029 best_error_ppm, &error_ppm))
1030 continue;
1031
1032 *best_clock = clock;
1033 best_error_ppm = error_ppm;
1034 found = true;
1035 }
1036 }
1037
1038 return found;
1039 }
1040
1041 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1042 struct dpll *best_clock)
1043 {
1044 int refclk = 100000;
1045 const struct intel_limit *limit = &intel_limits_bxt;
1046
1047 return chv_find_best_dpll(limit, crtc_state,
1048 target_clock, refclk, NULL, best_clock);
1049 }
1050
1051 bool intel_crtc_active(struct drm_crtc *crtc)
1052 {
1053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1054
1055 /* Be paranoid as we can arrive here with only partial
1056 * state retrieved from the hardware during setup.
1057 *
1058 * We can ditch the adjusted_mode.crtc_clock check as soon
1059 * as Haswell has gained clock readout/fastboot support.
1060 *
1061 * We can ditch the crtc->primary->fb check as soon as we can
1062 * properly reconstruct framebuffers.
1063 *
1064 * FIXME: The intel_crtc->active here should be switched to
1065 * crtc->state->active once we have proper CRTC states wired up
1066 * for atomic.
1067 */
1068 return intel_crtc->active && crtc->primary->state->fb &&
1069 intel_crtc->config->base.adjusted_mode.crtc_clock;
1070 }
1071
1072 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1073 enum pipe pipe)
1074 {
1075 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1077
1078 return intel_crtc->config->cpu_transcoder;
1079 }
1080
1081 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1082 {
1083 struct drm_i915_private *dev_priv = dev->dev_private;
1084 i915_reg_t reg = PIPEDSL(pipe);
1085 u32 line1, line2;
1086 u32 line_mask;
1087
1088 if (IS_GEN2(dev))
1089 line_mask = DSL_LINEMASK_GEN2;
1090 else
1091 line_mask = DSL_LINEMASK_GEN3;
1092
1093 line1 = I915_READ(reg) & line_mask;
1094 msleep(5);
1095 line2 = I915_READ(reg) & line_mask;
1096
1097 return line1 == line2;
1098 }
1099
1100 /*
1101 * intel_wait_for_pipe_off - wait for pipe to turn off
1102 * @crtc: crtc whose pipe to wait for
1103 *
1104 * After disabling a pipe, we can't wait for vblank in the usual way,
1105 * spinning on the vblank interrupt status bit, since we won't actually
1106 * see an interrupt when the pipe is disabled.
1107 *
1108 * On Gen4 and above:
1109 * wait for the pipe register state bit to turn off
1110 *
1111 * Otherwise:
1112 * wait for the display line value to settle (it usually
1113 * ends up stopping at the start of the next frame).
1114 *
1115 */
1116 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1117 {
1118 struct drm_device *dev = crtc->base.dev;
1119 struct drm_i915_private *dev_priv = dev->dev_private;
1120 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1121 enum pipe pipe = crtc->pipe;
1122
1123 if (INTEL_INFO(dev)->gen >= 4) {
1124 i915_reg_t reg = PIPECONF(cpu_transcoder);
1125
1126 /* Wait for the Pipe State to go off */
1127 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1128 100))
1129 WARN(1, "pipe_off wait timed out\n");
1130 } else {
1131 /* Wait for the display line to settle */
1132 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1133 WARN(1, "pipe_off wait timed out\n");
1134 }
1135 }
1136
1137 /* Only for pre-ILK configs */
1138 void assert_pll(struct drm_i915_private *dev_priv,
1139 enum pipe pipe, bool state)
1140 {
1141 u32 val;
1142 bool cur_state;
1143
1144 val = I915_READ(DPLL(pipe));
1145 cur_state = !!(val & DPLL_VCO_ENABLE);
1146 I915_STATE_WARN(cur_state != state,
1147 "PLL state assertion failure (expected %s, current %s)\n",
1148 onoff(state), onoff(cur_state));
1149 }
1150
1151 /* XXX: the dsi pll is shared between MIPI DSI ports */
1152 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1153 {
1154 u32 val;
1155 bool cur_state;
1156
1157 mutex_lock(&dev_priv->sb_lock);
1158 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1159 mutex_unlock(&dev_priv->sb_lock);
1160
1161 cur_state = val & DSI_PLL_VCO_EN;
1162 I915_STATE_WARN(cur_state != state,
1163 "DSI PLL state assertion failure (expected %s, current %s)\n",
1164 onoff(state), onoff(cur_state));
1165 }
1166
1167 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1168 enum pipe pipe, bool state)
1169 {
1170 bool cur_state;
1171 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1172 pipe);
1173
1174 if (HAS_DDI(dev_priv)) {
1175 /* DDI does not have a specific FDI_TX register */
1176 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1177 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1178 } else {
1179 u32 val = I915_READ(FDI_TX_CTL(pipe));
1180 cur_state = !!(val & FDI_TX_ENABLE);
1181 }
1182 I915_STATE_WARN(cur_state != state,
1183 "FDI TX state assertion failure (expected %s, current %s)\n",
1184 onoff(state), onoff(cur_state));
1185 }
1186 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1187 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1188
1189 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, bool state)
1191 {
1192 u32 val;
1193 bool cur_state;
1194
1195 val = I915_READ(FDI_RX_CTL(pipe));
1196 cur_state = !!(val & FDI_RX_ENABLE);
1197 I915_STATE_WARN(cur_state != state,
1198 "FDI RX state assertion failure (expected %s, current %s)\n",
1199 onoff(state), onoff(cur_state));
1200 }
1201 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1202 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1203
1204 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe)
1206 {
1207 u32 val;
1208
1209 /* ILK FDI PLL is always enabled */
1210 if (IS_GEN5(dev_priv))
1211 return;
1212
1213 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1214 if (HAS_DDI(dev_priv))
1215 return;
1216
1217 val = I915_READ(FDI_TX_CTL(pipe));
1218 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1219 }
1220
1221 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1223 {
1224 u32 val;
1225 bool cur_state;
1226
1227 val = I915_READ(FDI_RX_CTL(pipe));
1228 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1229 I915_STATE_WARN(cur_state != state,
1230 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1231 onoff(state), onoff(cur_state));
1232 }
1233
1234 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1235 enum pipe pipe)
1236 {
1237 struct drm_device *dev = dev_priv->dev;
1238 i915_reg_t pp_reg;
1239 u32 val;
1240 enum pipe panel_pipe = PIPE_A;
1241 bool locked = true;
1242
1243 if (WARN_ON(HAS_DDI(dev)))
1244 return;
1245
1246 if (HAS_PCH_SPLIT(dev)) {
1247 u32 port_sel;
1248
1249 pp_reg = PCH_PP_CONTROL;
1250 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1251
1252 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1253 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1254 panel_pipe = PIPE_B;
1255 /* XXX: else fix for eDP */
1256 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1257 /* presumably write lock depends on pipe, not port select */
1258 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1259 panel_pipe = pipe;
1260 } else {
1261 pp_reg = PP_CONTROL;
1262 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1263 panel_pipe = PIPE_B;
1264 }
1265
1266 val = I915_READ(pp_reg);
1267 if (!(val & PANEL_POWER_ON) ||
1268 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1269 locked = false;
1270
1271 I915_STATE_WARN(panel_pipe == pipe && locked,
1272 "panel assertion failure, pipe %c regs locked\n",
1273 pipe_name(pipe));
1274 }
1275
1276 static void assert_cursor(struct drm_i915_private *dev_priv,
1277 enum pipe pipe, bool state)
1278 {
1279 struct drm_device *dev = dev_priv->dev;
1280 bool cur_state;
1281
1282 if (IS_845G(dev) || IS_I865G(dev))
1283 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1284 else
1285 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1286
1287 I915_STATE_WARN(cur_state != state,
1288 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1289 pipe_name(pipe), onoff(state), onoff(cur_state));
1290 }
1291 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1292 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1293
1294 void assert_pipe(struct drm_i915_private *dev_priv,
1295 enum pipe pipe, bool state)
1296 {
1297 bool cur_state;
1298 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1299 pipe);
1300 enum intel_display_power_domain power_domain;
1301
1302 /* if we need the pipe quirk it must be always on */
1303 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1304 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1305 state = true;
1306
1307 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1308 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1309 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1310 cur_state = !!(val & PIPECONF_ENABLE);
1311
1312 intel_display_power_put(dev_priv, power_domain);
1313 } else {
1314 cur_state = false;
1315 }
1316
1317 I915_STATE_WARN(cur_state != state,
1318 "pipe %c assertion failure (expected %s, current %s)\n",
1319 pipe_name(pipe), onoff(state), onoff(cur_state));
1320 }
1321
1322 static void assert_plane(struct drm_i915_private *dev_priv,
1323 enum plane plane, bool state)
1324 {
1325 u32 val;
1326 bool cur_state;
1327
1328 val = I915_READ(DSPCNTR(plane));
1329 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1330 I915_STATE_WARN(cur_state != state,
1331 "plane %c assertion failure (expected %s, current %s)\n",
1332 plane_name(plane), onoff(state), onoff(cur_state));
1333 }
1334
1335 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1337
1338 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe)
1340 {
1341 struct drm_device *dev = dev_priv->dev;
1342 int i;
1343
1344 /* Primary planes are fixed to pipes on gen4+ */
1345 if (INTEL_INFO(dev)->gen >= 4) {
1346 u32 val = I915_READ(DSPCNTR(pipe));
1347 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1348 "plane %c assertion failure, should be disabled but not\n",
1349 plane_name(pipe));
1350 return;
1351 }
1352
1353 /* Need to check both planes against the pipe */
1354 for_each_pipe(dev_priv, i) {
1355 u32 val = I915_READ(DSPCNTR(i));
1356 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1357 DISPPLANE_SEL_PIPE_SHIFT;
1358 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1359 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1360 plane_name(i), pipe_name(pipe));
1361 }
1362 }
1363
1364 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe)
1366 {
1367 struct drm_device *dev = dev_priv->dev;
1368 int sprite;
1369
1370 if (INTEL_INFO(dev)->gen >= 9) {
1371 for_each_sprite(dev_priv, pipe, sprite) {
1372 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1373 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1374 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1375 sprite, pipe_name(pipe));
1376 }
1377 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1378 for_each_sprite(dev_priv, pipe, sprite) {
1379 u32 val = I915_READ(SPCNTR(pipe, sprite));
1380 I915_STATE_WARN(val & SP_ENABLE,
1381 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1382 sprite_name(pipe, sprite), pipe_name(pipe));
1383 }
1384 } else if (INTEL_INFO(dev)->gen >= 7) {
1385 u32 val = I915_READ(SPRCTL(pipe));
1386 I915_STATE_WARN(val & SPRITE_ENABLE,
1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388 plane_name(pipe), pipe_name(pipe));
1389 } else if (INTEL_INFO(dev)->gen >= 5) {
1390 u32 val = I915_READ(DVSCNTR(pipe));
1391 I915_STATE_WARN(val & DVS_ENABLE,
1392 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(pipe), pipe_name(pipe));
1394 }
1395 }
1396
1397 static void assert_vblank_disabled(struct drm_crtc *crtc)
1398 {
1399 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1400 drm_crtc_vblank_put(crtc);
1401 }
1402
1403 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe)
1405 {
1406 u32 val;
1407 bool enabled;
1408
1409 val = I915_READ(PCH_TRANSCONF(pipe));
1410 enabled = !!(val & TRANS_ENABLE);
1411 I915_STATE_WARN(enabled,
1412 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1413 pipe_name(pipe));
1414 }
1415
1416 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1417 enum pipe pipe, u32 port_sel, u32 val)
1418 {
1419 if ((val & DP_PORT_EN) == 0)
1420 return false;
1421
1422 if (HAS_PCH_CPT(dev_priv)) {
1423 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1424 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1425 return false;
1426 } else if (IS_CHERRYVIEW(dev_priv)) {
1427 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1428 return false;
1429 } else {
1430 if ((val & DP_PIPE_MASK) != (pipe << 30))
1431 return false;
1432 }
1433 return true;
1434 }
1435
1436 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, u32 val)
1438 {
1439 if ((val & SDVO_ENABLE) == 0)
1440 return false;
1441
1442 if (HAS_PCH_CPT(dev_priv)) {
1443 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1444 return false;
1445 } else if (IS_CHERRYVIEW(dev_priv)) {
1446 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1447 return false;
1448 } else {
1449 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1450 return false;
1451 }
1452 return true;
1453 }
1454
1455 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1456 enum pipe pipe, u32 val)
1457 {
1458 if ((val & LVDS_PORT_EN) == 0)
1459 return false;
1460
1461 if (HAS_PCH_CPT(dev_priv)) {
1462 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1463 return false;
1464 } else {
1465 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1466 return false;
1467 }
1468 return true;
1469 }
1470
1471 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1472 enum pipe pipe, u32 val)
1473 {
1474 if ((val & ADPA_DAC_ENABLE) == 0)
1475 return false;
1476 if (HAS_PCH_CPT(dev_priv)) {
1477 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1478 return false;
1479 } else {
1480 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1481 return false;
1482 }
1483 return true;
1484 }
1485
1486 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1487 enum pipe pipe, i915_reg_t reg,
1488 u32 port_sel)
1489 {
1490 u32 val = I915_READ(reg);
1491 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1492 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1493 i915_mmio_reg_offset(reg), pipe_name(pipe));
1494
1495 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1496 && (val & DP_PIPEB_SELECT),
1497 "IBX PCH dp port still using transcoder B\n");
1498 }
1499
1500 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1501 enum pipe pipe, i915_reg_t reg)
1502 {
1503 u32 val = I915_READ(reg);
1504 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1505 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1506 i915_mmio_reg_offset(reg), pipe_name(pipe));
1507
1508 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1509 && (val & SDVO_PIPE_B_SELECT),
1510 "IBX PCH hdmi port still using transcoder B\n");
1511 }
1512
1513 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1514 enum pipe pipe)
1515 {
1516 u32 val;
1517
1518 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1519 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1520 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1521
1522 val = I915_READ(PCH_ADPA);
1523 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1524 "PCH VGA enabled on transcoder %c, should be disabled\n",
1525 pipe_name(pipe));
1526
1527 val = I915_READ(PCH_LVDS);
1528 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1529 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1530 pipe_name(pipe));
1531
1532 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1533 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1534 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1535 }
1536
1537 static void _vlv_enable_pll(struct intel_crtc *crtc,
1538 const struct intel_crtc_state *pipe_config)
1539 {
1540 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1541 enum pipe pipe = crtc->pipe;
1542
1543 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1544 POSTING_READ(DPLL(pipe));
1545 udelay(150);
1546
1547 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1548 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1549 }
1550
1551 static void vlv_enable_pll(struct intel_crtc *crtc,
1552 const struct intel_crtc_state *pipe_config)
1553 {
1554 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1555 enum pipe pipe = crtc->pipe;
1556
1557 assert_pipe_disabled(dev_priv, pipe);
1558
1559 /* PLL is protected by panel, make sure we can write it */
1560 assert_panel_unlocked(dev_priv, pipe);
1561
1562 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1563 _vlv_enable_pll(crtc, pipe_config);
1564
1565 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1566 POSTING_READ(DPLL_MD(pipe));
1567 }
1568
1569
1570 static void _chv_enable_pll(struct intel_crtc *crtc,
1571 const struct intel_crtc_state *pipe_config)
1572 {
1573 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1574 enum pipe pipe = crtc->pipe;
1575 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1576 u32 tmp;
1577
1578 mutex_lock(&dev_priv->sb_lock);
1579
1580 /* Enable back the 10bit clock to display controller */
1581 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1582 tmp |= DPIO_DCLKP_EN;
1583 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1584
1585 mutex_unlock(&dev_priv->sb_lock);
1586
1587 /*
1588 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1589 */
1590 udelay(1);
1591
1592 /* Enable PLL */
1593 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1594
1595 /* Check PLL is locked */
1596 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1597 DRM_ERROR("PLL %d failed to lock\n", pipe);
1598 }
1599
1600 static void chv_enable_pll(struct intel_crtc *crtc,
1601 const struct intel_crtc_state *pipe_config)
1602 {
1603 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1604 enum pipe pipe = crtc->pipe;
1605
1606 assert_pipe_disabled(dev_priv, pipe);
1607
1608 /* PLL is protected by panel, make sure we can write it */
1609 assert_panel_unlocked(dev_priv, pipe);
1610
1611 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1612 _chv_enable_pll(crtc, pipe_config);
1613
1614 if (pipe != PIPE_A) {
1615 /*
1616 * WaPixelRepeatModeFixForC0:chv
1617 *
1618 * DPLLCMD is AWOL. Use chicken bits to propagate
1619 * the value from DPLLBMD to either pipe B or C.
1620 */
1621 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1622 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1623 I915_WRITE(CBR4_VLV, 0);
1624 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1625
1626 /*
1627 * DPLLB VGA mode also seems to cause problems.
1628 * We should always have it disabled.
1629 */
1630 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1631 } else {
1632 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1633 POSTING_READ(DPLL_MD(pipe));
1634 }
1635 }
1636
1637 static int intel_num_dvo_pipes(struct drm_device *dev)
1638 {
1639 struct intel_crtc *crtc;
1640 int count = 0;
1641
1642 for_each_intel_crtc(dev, crtc)
1643 count += crtc->base.state->active &&
1644 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1645
1646 return count;
1647 }
1648
1649 static void i9xx_enable_pll(struct intel_crtc *crtc)
1650 {
1651 struct drm_device *dev = crtc->base.dev;
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 i915_reg_t reg = DPLL(crtc->pipe);
1654 u32 dpll = crtc->config->dpll_hw_state.dpll;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 /* PLL is protected by panel, make sure we can write it */
1659 if (IS_MOBILE(dev) && !IS_I830(dev))
1660 assert_panel_unlocked(dev_priv, crtc->pipe);
1661
1662 /* Enable DVO 2x clock on both PLLs if necessary */
1663 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1664 /*
1665 * It appears to be important that we don't enable this
1666 * for the current pipe before otherwise configuring the
1667 * PLL. No idea how this should be handled if multiple
1668 * DVO outputs are enabled simultaneosly.
1669 */
1670 dpll |= DPLL_DVO_2X_MODE;
1671 I915_WRITE(DPLL(!crtc->pipe),
1672 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1673 }
1674
1675 /*
1676 * Apparently we need to have VGA mode enabled prior to changing
1677 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1678 * dividers, even though the register value does change.
1679 */
1680 I915_WRITE(reg, 0);
1681
1682 I915_WRITE(reg, dpll);
1683
1684 /* Wait for the clocks to stabilize. */
1685 POSTING_READ(reg);
1686 udelay(150);
1687
1688 if (INTEL_INFO(dev)->gen >= 4) {
1689 I915_WRITE(DPLL_MD(crtc->pipe),
1690 crtc->config->dpll_hw_state.dpll_md);
1691 } else {
1692 /* The pixel multiplier can only be updated once the
1693 * DPLL is enabled and the clocks are stable.
1694 *
1695 * So write it again.
1696 */
1697 I915_WRITE(reg, dpll);
1698 }
1699
1700 /* We do this three times for luck */
1701 I915_WRITE(reg, dpll);
1702 POSTING_READ(reg);
1703 udelay(150); /* wait for warmup */
1704 I915_WRITE(reg, dpll);
1705 POSTING_READ(reg);
1706 udelay(150); /* wait for warmup */
1707 I915_WRITE(reg, dpll);
1708 POSTING_READ(reg);
1709 udelay(150); /* wait for warmup */
1710 }
1711
1712 /**
1713 * i9xx_disable_pll - disable a PLL
1714 * @dev_priv: i915 private structure
1715 * @pipe: pipe PLL to disable
1716 *
1717 * Disable the PLL for @pipe, making sure the pipe is off first.
1718 *
1719 * Note! This is for pre-ILK only.
1720 */
1721 static void i9xx_disable_pll(struct intel_crtc *crtc)
1722 {
1723 struct drm_device *dev = crtc->base.dev;
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1725 enum pipe pipe = crtc->pipe;
1726
1727 /* Disable DVO 2x clock on both PLLs if necessary */
1728 if (IS_I830(dev) &&
1729 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1730 !intel_num_dvo_pipes(dev)) {
1731 I915_WRITE(DPLL(PIPE_B),
1732 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1733 I915_WRITE(DPLL(PIPE_A),
1734 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1735 }
1736
1737 /* Don't disable pipe or pipe PLLs if needed */
1738 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1739 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1740 return;
1741
1742 /* Make sure the pipe isn't still relying on us */
1743 assert_pipe_disabled(dev_priv, pipe);
1744
1745 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1746 POSTING_READ(DPLL(pipe));
1747 }
1748
1749 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1750 {
1751 u32 val;
1752
1753 /* Make sure the pipe isn't still relying on us */
1754 assert_pipe_disabled(dev_priv, pipe);
1755
1756 val = DPLL_INTEGRATED_REF_CLK_VLV |
1757 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1758 if (pipe != PIPE_A)
1759 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1760
1761 I915_WRITE(DPLL(pipe), val);
1762 POSTING_READ(DPLL(pipe));
1763 }
1764
1765 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1766 {
1767 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1768 u32 val;
1769
1770 /* Make sure the pipe isn't still relying on us */
1771 assert_pipe_disabled(dev_priv, pipe);
1772
1773 val = DPLL_SSC_REF_CLK_CHV |
1774 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1775 if (pipe != PIPE_A)
1776 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1777
1778 I915_WRITE(DPLL(pipe), val);
1779 POSTING_READ(DPLL(pipe));
1780
1781 mutex_lock(&dev_priv->sb_lock);
1782
1783 /* Disable 10bit clock to display controller */
1784 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1785 val &= ~DPIO_DCLKP_EN;
1786 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1787
1788 mutex_unlock(&dev_priv->sb_lock);
1789 }
1790
1791 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1792 struct intel_digital_port *dport,
1793 unsigned int expected_mask)
1794 {
1795 u32 port_mask;
1796 i915_reg_t dpll_reg;
1797
1798 switch (dport->port) {
1799 case PORT_B:
1800 port_mask = DPLL_PORTB_READY_MASK;
1801 dpll_reg = DPLL(0);
1802 break;
1803 case PORT_C:
1804 port_mask = DPLL_PORTC_READY_MASK;
1805 dpll_reg = DPLL(0);
1806 expected_mask <<= 4;
1807 break;
1808 case PORT_D:
1809 port_mask = DPLL_PORTD_READY_MASK;
1810 dpll_reg = DPIO_PHY_STATUS;
1811 break;
1812 default:
1813 BUG();
1814 }
1815
1816 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1817 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1818 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1819 }
1820
1821 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1822 enum pipe pipe)
1823 {
1824 struct drm_device *dev = dev_priv->dev;
1825 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1827 i915_reg_t reg;
1828 uint32_t val, pipeconf_val;
1829
1830 /* Make sure PCH DPLL is enabled */
1831 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1832
1833 /* FDI must be feeding us bits for PCH ports */
1834 assert_fdi_tx_enabled(dev_priv, pipe);
1835 assert_fdi_rx_enabled(dev_priv, pipe);
1836
1837 if (HAS_PCH_CPT(dev)) {
1838 /* Workaround: Set the timing override bit before enabling the
1839 * pch transcoder. */
1840 reg = TRANS_CHICKEN2(pipe);
1841 val = I915_READ(reg);
1842 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1843 I915_WRITE(reg, val);
1844 }
1845
1846 reg = PCH_TRANSCONF(pipe);
1847 val = I915_READ(reg);
1848 pipeconf_val = I915_READ(PIPECONF(pipe));
1849
1850 if (HAS_PCH_IBX(dev_priv)) {
1851 /*
1852 * Make the BPC in transcoder be consistent with
1853 * that in pipeconf reg. For HDMI we must use 8bpc
1854 * here for both 8bpc and 12bpc.
1855 */
1856 val &= ~PIPECONF_BPC_MASK;
1857 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1858 val |= PIPECONF_8BPC;
1859 else
1860 val |= pipeconf_val & PIPECONF_BPC_MASK;
1861 }
1862
1863 val &= ~TRANS_INTERLACE_MASK;
1864 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1865 if (HAS_PCH_IBX(dev_priv) &&
1866 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1867 val |= TRANS_LEGACY_INTERLACED_ILK;
1868 else
1869 val |= TRANS_INTERLACED;
1870 else
1871 val |= TRANS_PROGRESSIVE;
1872
1873 I915_WRITE(reg, val | TRANS_ENABLE);
1874 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1875 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1876 }
1877
1878 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1879 enum transcoder cpu_transcoder)
1880 {
1881 u32 val, pipeconf_val;
1882
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1885 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1886
1887 /* Workaround: set timing override bit. */
1888 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1891
1892 val = TRANS_ENABLE;
1893 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1894
1895 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1896 PIPECONF_INTERLACED_ILK)
1897 val |= TRANS_INTERLACED;
1898 else
1899 val |= TRANS_PROGRESSIVE;
1900
1901 I915_WRITE(LPT_TRANSCONF, val);
1902 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1903 DRM_ERROR("Failed to enable PCH transcoder\n");
1904 }
1905
1906 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1907 enum pipe pipe)
1908 {
1909 struct drm_device *dev = dev_priv->dev;
1910 i915_reg_t reg;
1911 uint32_t val;
1912
1913 /* FDI relies on the transcoder */
1914 assert_fdi_tx_disabled(dev_priv, pipe);
1915 assert_fdi_rx_disabled(dev_priv, pipe);
1916
1917 /* Ports must be off as well */
1918 assert_pch_ports_disabled(dev_priv, pipe);
1919
1920 reg = PCH_TRANSCONF(pipe);
1921 val = I915_READ(reg);
1922 val &= ~TRANS_ENABLE;
1923 I915_WRITE(reg, val);
1924 /* wait for PCH transcoder off, transcoder state */
1925 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1926 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1927
1928 if (HAS_PCH_CPT(dev)) {
1929 /* Workaround: Clear the timing override chicken bit again. */
1930 reg = TRANS_CHICKEN2(pipe);
1931 val = I915_READ(reg);
1932 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1933 I915_WRITE(reg, val);
1934 }
1935 }
1936
1937 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1938 {
1939 u32 val;
1940
1941 val = I915_READ(LPT_TRANSCONF);
1942 val &= ~TRANS_ENABLE;
1943 I915_WRITE(LPT_TRANSCONF, val);
1944 /* wait for PCH transcoder off, transcoder state */
1945 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1946 DRM_ERROR("Failed to disable PCH transcoder\n");
1947
1948 /* Workaround: clear timing override bit. */
1949 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1950 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1951 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1952 }
1953
1954 /**
1955 * intel_enable_pipe - enable a pipe, asserting requirements
1956 * @crtc: crtc responsible for the pipe
1957 *
1958 * Enable @crtc's pipe, making sure that various hardware specific requirements
1959 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1960 */
1961 static void intel_enable_pipe(struct intel_crtc *crtc)
1962 {
1963 struct drm_device *dev = crtc->base.dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 enum pipe pipe = crtc->pipe;
1966 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1967 enum pipe pch_transcoder;
1968 i915_reg_t reg;
1969 u32 val;
1970
1971 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1972
1973 assert_planes_disabled(dev_priv, pipe);
1974 assert_cursor_disabled(dev_priv, pipe);
1975 assert_sprites_disabled(dev_priv, pipe);
1976
1977 if (HAS_PCH_LPT(dev_priv))
1978 pch_transcoder = TRANSCODER_A;
1979 else
1980 pch_transcoder = pipe;
1981
1982 /*
1983 * A pipe without a PLL won't actually be able to drive bits from
1984 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1985 * need the check.
1986 */
1987 if (HAS_GMCH_DISPLAY(dev_priv))
1988 if (crtc->config->has_dsi_encoder)
1989 assert_dsi_pll_enabled(dev_priv);
1990 else
1991 assert_pll_enabled(dev_priv, pipe);
1992 else {
1993 if (crtc->config->has_pch_encoder) {
1994 /* if driving the PCH, we need FDI enabled */
1995 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1996 assert_fdi_tx_pll_enabled(dev_priv,
1997 (enum pipe) cpu_transcoder);
1998 }
1999 /* FIXME: assert CPU port conditions for SNB+ */
2000 }
2001
2002 reg = PIPECONF(cpu_transcoder);
2003 val = I915_READ(reg);
2004 if (val & PIPECONF_ENABLE) {
2005 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2006 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2007 return;
2008 }
2009
2010 I915_WRITE(reg, val | PIPECONF_ENABLE);
2011 POSTING_READ(reg);
2012
2013 /*
2014 * Until the pipe starts DSL will read as 0, which would cause
2015 * an apparent vblank timestamp jump, which messes up also the
2016 * frame count when it's derived from the timestamps. So let's
2017 * wait for the pipe to start properly before we call
2018 * drm_crtc_vblank_on()
2019 */
2020 if (dev->max_vblank_count == 0 &&
2021 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2022 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2023 }
2024
2025 /**
2026 * intel_disable_pipe - disable a pipe, asserting requirements
2027 * @crtc: crtc whose pipes is to be disabled
2028 *
2029 * Disable the pipe of @crtc, making sure that various hardware
2030 * specific requirements are met, if applicable, e.g. plane
2031 * disabled, panel fitter off, etc.
2032 *
2033 * Will wait until the pipe has shut down before returning.
2034 */
2035 static void intel_disable_pipe(struct intel_crtc *crtc)
2036 {
2037 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2038 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2039 enum pipe pipe = crtc->pipe;
2040 i915_reg_t reg;
2041 u32 val;
2042
2043 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2044
2045 /*
2046 * Make sure planes won't keep trying to pump pixels to us,
2047 * or we might hang the display.
2048 */
2049 assert_planes_disabled(dev_priv, pipe);
2050 assert_cursor_disabled(dev_priv, pipe);
2051 assert_sprites_disabled(dev_priv, pipe);
2052
2053 reg = PIPECONF(cpu_transcoder);
2054 val = I915_READ(reg);
2055 if ((val & PIPECONF_ENABLE) == 0)
2056 return;
2057
2058 /*
2059 * Double wide has implications for planes
2060 * so best keep it disabled when not needed.
2061 */
2062 if (crtc->config->double_wide)
2063 val &= ~PIPECONF_DOUBLE_WIDE;
2064
2065 /* Don't disable pipe or pipe PLLs if needed */
2066 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2067 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2068 val &= ~PIPECONF_ENABLE;
2069
2070 I915_WRITE(reg, val);
2071 if ((val & PIPECONF_ENABLE) == 0)
2072 intel_wait_for_pipe_off(crtc);
2073 }
2074
2075 static bool need_vtd_wa(struct drm_device *dev)
2076 {
2077 #ifdef CONFIG_INTEL_IOMMU
2078 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2079 return true;
2080 #endif
2081 return false;
2082 }
2083
2084 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2085 {
2086 return IS_GEN2(dev_priv) ? 2048 : 4096;
2087 }
2088
2089 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2090 uint64_t fb_modifier, unsigned int cpp)
2091 {
2092 switch (fb_modifier) {
2093 case DRM_FORMAT_MOD_NONE:
2094 return cpp;
2095 case I915_FORMAT_MOD_X_TILED:
2096 if (IS_GEN2(dev_priv))
2097 return 128;
2098 else
2099 return 512;
2100 case I915_FORMAT_MOD_Y_TILED:
2101 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2102 return 128;
2103 else
2104 return 512;
2105 case I915_FORMAT_MOD_Yf_TILED:
2106 switch (cpp) {
2107 case 1:
2108 return 64;
2109 case 2:
2110 case 4:
2111 return 128;
2112 case 8:
2113 case 16:
2114 return 256;
2115 default:
2116 MISSING_CASE(cpp);
2117 return cpp;
2118 }
2119 break;
2120 default:
2121 MISSING_CASE(fb_modifier);
2122 return cpp;
2123 }
2124 }
2125
2126 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2127 uint64_t fb_modifier, unsigned int cpp)
2128 {
2129 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2130 return 1;
2131 else
2132 return intel_tile_size(dev_priv) /
2133 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2134 }
2135
2136 /* Return the tile dimensions in pixel units */
2137 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2138 unsigned int *tile_width,
2139 unsigned int *tile_height,
2140 uint64_t fb_modifier,
2141 unsigned int cpp)
2142 {
2143 unsigned int tile_width_bytes =
2144 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2145
2146 *tile_width = tile_width_bytes / cpp;
2147 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2148 }
2149
2150 unsigned int
2151 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2152 uint32_t pixel_format, uint64_t fb_modifier)
2153 {
2154 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2155 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2156
2157 return ALIGN(height, tile_height);
2158 }
2159
2160 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2161 {
2162 unsigned int size = 0;
2163 int i;
2164
2165 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2166 size += rot_info->plane[i].width * rot_info->plane[i].height;
2167
2168 return size;
2169 }
2170
2171 static void
2172 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2173 const struct drm_framebuffer *fb,
2174 unsigned int rotation)
2175 {
2176 if (intel_rotation_90_or_270(rotation)) {
2177 *view = i915_ggtt_view_rotated;
2178 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2179 } else {
2180 *view = i915_ggtt_view_normal;
2181 }
2182 }
2183
2184 static void
2185 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2186 struct drm_framebuffer *fb)
2187 {
2188 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2189 unsigned int tile_size, tile_width, tile_height, cpp;
2190
2191 tile_size = intel_tile_size(dev_priv);
2192
2193 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2194 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2195 fb->modifier[0], cpp);
2196
2197 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2198 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2199
2200 if (info->pixel_format == DRM_FORMAT_NV12) {
2201 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2202 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2203 fb->modifier[1], cpp);
2204
2205 info->uv_offset = fb->offsets[1];
2206 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2207 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2208 }
2209 }
2210
2211 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2212 {
2213 if (INTEL_INFO(dev_priv)->gen >= 9)
2214 return 256 * 1024;
2215 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2216 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2217 return 128 * 1024;
2218 else if (INTEL_INFO(dev_priv)->gen >= 4)
2219 return 4 * 1024;
2220 else
2221 return 0;
2222 }
2223
2224 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2225 uint64_t fb_modifier)
2226 {
2227 switch (fb_modifier) {
2228 case DRM_FORMAT_MOD_NONE:
2229 return intel_linear_alignment(dev_priv);
2230 case I915_FORMAT_MOD_X_TILED:
2231 if (INTEL_INFO(dev_priv)->gen >= 9)
2232 return 256 * 1024;
2233 return 0;
2234 case I915_FORMAT_MOD_Y_TILED:
2235 case I915_FORMAT_MOD_Yf_TILED:
2236 return 1 * 1024 * 1024;
2237 default:
2238 MISSING_CASE(fb_modifier);
2239 return 0;
2240 }
2241 }
2242
2243 int
2244 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2245 unsigned int rotation)
2246 {
2247 struct drm_device *dev = fb->dev;
2248 struct drm_i915_private *dev_priv = dev->dev_private;
2249 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2250 struct i915_ggtt_view view;
2251 u32 alignment;
2252 int ret;
2253
2254 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2255
2256 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2257
2258 intel_fill_fb_ggtt_view(&view, fb, rotation);
2259
2260 /* Note that the w/a also requires 64 PTE of padding following the
2261 * bo. We currently fill all unused PTE with the shadow page and so
2262 * we should always have valid PTE following the scanout preventing
2263 * the VT-d warning.
2264 */
2265 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2266 alignment = 256 * 1024;
2267
2268 /*
2269 * Global gtt pte registers are special registers which actually forward
2270 * writes to a chunk of system memory. Which means that there is no risk
2271 * that the register values disappear as soon as we call
2272 * intel_runtime_pm_put(), so it is correct to wrap only the
2273 * pin/unpin/fence and not more.
2274 */
2275 intel_runtime_pm_get(dev_priv);
2276
2277 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2278 &view);
2279 if (ret)
2280 goto err_pm;
2281
2282 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2283 * fence, whereas 965+ only requires a fence if using
2284 * framebuffer compression. For simplicity, we always install
2285 * a fence as the cost is not that onerous.
2286 */
2287 if (view.type == I915_GGTT_VIEW_NORMAL) {
2288 ret = i915_gem_object_get_fence(obj);
2289 if (ret == -EDEADLK) {
2290 /*
2291 * -EDEADLK means there are no free fences
2292 * no pending flips.
2293 *
2294 * This is propagated to atomic, but it uses
2295 * -EDEADLK to force a locking recovery, so
2296 * change the returned error to -EBUSY.
2297 */
2298 ret = -EBUSY;
2299 goto err_unpin;
2300 } else if (ret)
2301 goto err_unpin;
2302
2303 i915_gem_object_pin_fence(obj);
2304 }
2305
2306 intel_runtime_pm_put(dev_priv);
2307 return 0;
2308
2309 err_unpin:
2310 i915_gem_object_unpin_from_display_plane(obj, &view);
2311 err_pm:
2312 intel_runtime_pm_put(dev_priv);
2313 return ret;
2314 }
2315
2316 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2317 {
2318 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2319 struct i915_ggtt_view view;
2320
2321 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2322
2323 intel_fill_fb_ggtt_view(&view, fb, rotation);
2324
2325 if (view.type == I915_GGTT_VIEW_NORMAL)
2326 i915_gem_object_unpin_fence(obj);
2327
2328 i915_gem_object_unpin_from_display_plane(obj, &view);
2329 }
2330
2331 /*
2332 * Adjust the tile offset by moving the difference into
2333 * the x/y offsets.
2334 *
2335 * Input tile dimensions and pitch must already be
2336 * rotated to match x and y, and in pixel units.
2337 */
2338 static u32 intel_adjust_tile_offset(int *x, int *y,
2339 unsigned int tile_width,
2340 unsigned int tile_height,
2341 unsigned int tile_size,
2342 unsigned int pitch_tiles,
2343 u32 old_offset,
2344 u32 new_offset)
2345 {
2346 unsigned int tiles;
2347
2348 WARN_ON(old_offset & (tile_size - 1));
2349 WARN_ON(new_offset & (tile_size - 1));
2350 WARN_ON(new_offset > old_offset);
2351
2352 tiles = (old_offset - new_offset) / tile_size;
2353
2354 *y += tiles / pitch_tiles * tile_height;
2355 *x += tiles % pitch_tiles * tile_width;
2356
2357 return new_offset;
2358 }
2359
2360 /*
2361 * Computes the linear offset to the base tile and adjusts
2362 * x, y. bytes per pixel is assumed to be a power-of-two.
2363 *
2364 * In the 90/270 rotated case, x and y are assumed
2365 * to be already rotated to match the rotated GTT view, and
2366 * pitch is the tile_height aligned framebuffer height.
2367 */
2368 u32 intel_compute_tile_offset(int *x, int *y,
2369 const struct drm_framebuffer *fb, int plane,
2370 unsigned int pitch,
2371 unsigned int rotation)
2372 {
2373 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2374 uint64_t fb_modifier = fb->modifier[plane];
2375 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2376 u32 offset, offset_aligned, alignment;
2377
2378 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2379 if (alignment)
2380 alignment--;
2381
2382 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2383 unsigned int tile_size, tile_width, tile_height;
2384 unsigned int tile_rows, tiles, pitch_tiles;
2385
2386 tile_size = intel_tile_size(dev_priv);
2387 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2388 fb_modifier, cpp);
2389
2390 if (intel_rotation_90_or_270(rotation)) {
2391 pitch_tiles = pitch / tile_height;
2392 swap(tile_width, tile_height);
2393 } else {
2394 pitch_tiles = pitch / (tile_width * cpp);
2395 }
2396
2397 tile_rows = *y / tile_height;
2398 *y %= tile_height;
2399
2400 tiles = *x / tile_width;
2401 *x %= tile_width;
2402
2403 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2404 offset_aligned = offset & ~alignment;
2405
2406 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2407 tile_size, pitch_tiles,
2408 offset, offset_aligned);
2409 } else {
2410 offset = *y * pitch + *x * cpp;
2411 offset_aligned = offset & ~alignment;
2412
2413 *y = (offset & alignment) / pitch;
2414 *x = ((offset & alignment) - *y * pitch) / cpp;
2415 }
2416
2417 return offset_aligned;
2418 }
2419
2420 static int i9xx_format_to_fourcc(int format)
2421 {
2422 switch (format) {
2423 case DISPPLANE_8BPP:
2424 return DRM_FORMAT_C8;
2425 case DISPPLANE_BGRX555:
2426 return DRM_FORMAT_XRGB1555;
2427 case DISPPLANE_BGRX565:
2428 return DRM_FORMAT_RGB565;
2429 default:
2430 case DISPPLANE_BGRX888:
2431 return DRM_FORMAT_XRGB8888;
2432 case DISPPLANE_RGBX888:
2433 return DRM_FORMAT_XBGR8888;
2434 case DISPPLANE_BGRX101010:
2435 return DRM_FORMAT_XRGB2101010;
2436 case DISPPLANE_RGBX101010:
2437 return DRM_FORMAT_XBGR2101010;
2438 }
2439 }
2440
2441 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2442 {
2443 switch (format) {
2444 case PLANE_CTL_FORMAT_RGB_565:
2445 return DRM_FORMAT_RGB565;
2446 default:
2447 case PLANE_CTL_FORMAT_XRGB_8888:
2448 if (rgb_order) {
2449 if (alpha)
2450 return DRM_FORMAT_ABGR8888;
2451 else
2452 return DRM_FORMAT_XBGR8888;
2453 } else {
2454 if (alpha)
2455 return DRM_FORMAT_ARGB8888;
2456 else
2457 return DRM_FORMAT_XRGB8888;
2458 }
2459 case PLANE_CTL_FORMAT_XRGB_2101010:
2460 if (rgb_order)
2461 return DRM_FORMAT_XBGR2101010;
2462 else
2463 return DRM_FORMAT_XRGB2101010;
2464 }
2465 }
2466
2467 static bool
2468 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2469 struct intel_initial_plane_config *plane_config)
2470 {
2471 struct drm_device *dev = crtc->base.dev;
2472 struct drm_i915_private *dev_priv = to_i915(dev);
2473 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2474 struct drm_i915_gem_object *obj = NULL;
2475 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2476 struct drm_framebuffer *fb = &plane_config->fb->base;
2477 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2478 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2479 PAGE_SIZE);
2480
2481 size_aligned -= base_aligned;
2482
2483 if (plane_config->size == 0)
2484 return false;
2485
2486 /* If the FB is too big, just don't use it since fbdev is not very
2487 * important and we should probably use that space with FBC or other
2488 * features. */
2489 if (size_aligned * 2 > ggtt->stolen_usable_size)
2490 return false;
2491
2492 mutex_lock(&dev->struct_mutex);
2493
2494 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2495 base_aligned,
2496 base_aligned,
2497 size_aligned);
2498 if (!obj) {
2499 mutex_unlock(&dev->struct_mutex);
2500 return false;
2501 }
2502
2503 obj->tiling_mode = plane_config->tiling;
2504 if (obj->tiling_mode == I915_TILING_X)
2505 obj->stride = fb->pitches[0];
2506
2507 mode_cmd.pixel_format = fb->pixel_format;
2508 mode_cmd.width = fb->width;
2509 mode_cmd.height = fb->height;
2510 mode_cmd.pitches[0] = fb->pitches[0];
2511 mode_cmd.modifier[0] = fb->modifier[0];
2512 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2513
2514 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2515 &mode_cmd, obj)) {
2516 DRM_DEBUG_KMS("intel fb init failed\n");
2517 goto out_unref_obj;
2518 }
2519
2520 mutex_unlock(&dev->struct_mutex);
2521
2522 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2523 return true;
2524
2525 out_unref_obj:
2526 drm_gem_object_unreference(&obj->base);
2527 mutex_unlock(&dev->struct_mutex);
2528 return false;
2529 }
2530
2531 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2532 static void
2533 update_state_fb(struct drm_plane *plane)
2534 {
2535 if (plane->fb == plane->state->fb)
2536 return;
2537
2538 if (plane->state->fb)
2539 drm_framebuffer_unreference(plane->state->fb);
2540 plane->state->fb = plane->fb;
2541 if (plane->state->fb)
2542 drm_framebuffer_reference(plane->state->fb);
2543 }
2544
2545 static void
2546 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2547 struct intel_initial_plane_config *plane_config)
2548 {
2549 struct drm_device *dev = intel_crtc->base.dev;
2550 struct drm_i915_private *dev_priv = dev->dev_private;
2551 struct drm_crtc *c;
2552 struct intel_crtc *i;
2553 struct drm_i915_gem_object *obj;
2554 struct drm_plane *primary = intel_crtc->base.primary;
2555 struct drm_plane_state *plane_state = primary->state;
2556 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2557 struct intel_plane *intel_plane = to_intel_plane(primary);
2558 struct intel_plane_state *intel_state =
2559 to_intel_plane_state(plane_state);
2560 struct drm_framebuffer *fb;
2561
2562 if (!plane_config->fb)
2563 return;
2564
2565 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2566 fb = &plane_config->fb->base;
2567 goto valid_fb;
2568 }
2569
2570 kfree(plane_config->fb);
2571
2572 /*
2573 * Failed to alloc the obj, check to see if we should share
2574 * an fb with another CRTC instead
2575 */
2576 for_each_crtc(dev, c) {
2577 i = to_intel_crtc(c);
2578
2579 if (c == &intel_crtc->base)
2580 continue;
2581
2582 if (!i->active)
2583 continue;
2584
2585 fb = c->primary->fb;
2586 if (!fb)
2587 continue;
2588
2589 obj = intel_fb_obj(fb);
2590 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2591 drm_framebuffer_reference(fb);
2592 goto valid_fb;
2593 }
2594 }
2595
2596 /*
2597 * We've failed to reconstruct the BIOS FB. Current display state
2598 * indicates that the primary plane is visible, but has a NULL FB,
2599 * which will lead to problems later if we don't fix it up. The
2600 * simplest solution is to just disable the primary plane now and
2601 * pretend the BIOS never had it enabled.
2602 */
2603 to_intel_plane_state(plane_state)->visible = false;
2604 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2605 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2606 intel_plane->disable_plane(primary, &intel_crtc->base);
2607
2608 return;
2609
2610 valid_fb:
2611 plane_state->src_x = 0;
2612 plane_state->src_y = 0;
2613 plane_state->src_w = fb->width << 16;
2614 plane_state->src_h = fb->height << 16;
2615
2616 plane_state->crtc_x = 0;
2617 plane_state->crtc_y = 0;
2618 plane_state->crtc_w = fb->width;
2619 plane_state->crtc_h = fb->height;
2620
2621 intel_state->src.x1 = plane_state->src_x;
2622 intel_state->src.y1 = plane_state->src_y;
2623 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2624 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2625 intel_state->dst.x1 = plane_state->crtc_x;
2626 intel_state->dst.y1 = plane_state->crtc_y;
2627 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2628 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2629
2630 obj = intel_fb_obj(fb);
2631 if (obj->tiling_mode != I915_TILING_NONE)
2632 dev_priv->preserve_bios_swizzle = true;
2633
2634 drm_framebuffer_reference(fb);
2635 primary->fb = primary->state->fb = fb;
2636 primary->crtc = primary->state->crtc = &intel_crtc->base;
2637 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2638 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2639 }
2640
2641 static void i9xx_update_primary_plane(struct drm_plane *primary,
2642 const struct intel_crtc_state *crtc_state,
2643 const struct intel_plane_state *plane_state)
2644 {
2645 struct drm_device *dev = primary->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2648 struct drm_framebuffer *fb = plane_state->base.fb;
2649 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2650 int plane = intel_crtc->plane;
2651 u32 linear_offset;
2652 u32 dspcntr;
2653 i915_reg_t reg = DSPCNTR(plane);
2654 unsigned int rotation = plane_state->base.rotation;
2655 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2656 int x = plane_state->src.x1 >> 16;
2657 int y = plane_state->src.y1 >> 16;
2658
2659 dspcntr = DISPPLANE_GAMMA_ENABLE;
2660
2661 dspcntr |= DISPLAY_PLANE_ENABLE;
2662
2663 if (INTEL_INFO(dev)->gen < 4) {
2664 if (intel_crtc->pipe == PIPE_B)
2665 dspcntr |= DISPPLANE_SEL_PIPE_B;
2666
2667 /* pipesrc and dspsize control the size that is scaled from,
2668 * which should always be the user's requested size.
2669 */
2670 I915_WRITE(DSPSIZE(plane),
2671 ((crtc_state->pipe_src_h - 1) << 16) |
2672 (crtc_state->pipe_src_w - 1));
2673 I915_WRITE(DSPPOS(plane), 0);
2674 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2675 I915_WRITE(PRIMSIZE(plane),
2676 ((crtc_state->pipe_src_h - 1) << 16) |
2677 (crtc_state->pipe_src_w - 1));
2678 I915_WRITE(PRIMPOS(plane), 0);
2679 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2680 }
2681
2682 switch (fb->pixel_format) {
2683 case DRM_FORMAT_C8:
2684 dspcntr |= DISPPLANE_8BPP;
2685 break;
2686 case DRM_FORMAT_XRGB1555:
2687 dspcntr |= DISPPLANE_BGRX555;
2688 break;
2689 case DRM_FORMAT_RGB565:
2690 dspcntr |= DISPPLANE_BGRX565;
2691 break;
2692 case DRM_FORMAT_XRGB8888:
2693 dspcntr |= DISPPLANE_BGRX888;
2694 break;
2695 case DRM_FORMAT_XBGR8888:
2696 dspcntr |= DISPPLANE_RGBX888;
2697 break;
2698 case DRM_FORMAT_XRGB2101010:
2699 dspcntr |= DISPPLANE_BGRX101010;
2700 break;
2701 case DRM_FORMAT_XBGR2101010:
2702 dspcntr |= DISPPLANE_RGBX101010;
2703 break;
2704 default:
2705 BUG();
2706 }
2707
2708 if (INTEL_INFO(dev)->gen >= 4 &&
2709 obj->tiling_mode != I915_TILING_NONE)
2710 dspcntr |= DISPPLANE_TILED;
2711
2712 if (IS_G4X(dev))
2713 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2714
2715 linear_offset = y * fb->pitches[0] + x * cpp;
2716
2717 if (INTEL_INFO(dev)->gen >= 4) {
2718 intel_crtc->dspaddr_offset =
2719 intel_compute_tile_offset(&x, &y, fb, 0,
2720 fb->pitches[0], rotation);
2721 linear_offset -= intel_crtc->dspaddr_offset;
2722 } else {
2723 intel_crtc->dspaddr_offset = linear_offset;
2724 }
2725
2726 if (rotation == BIT(DRM_ROTATE_180)) {
2727 dspcntr |= DISPPLANE_ROTATE_180;
2728
2729 x += (crtc_state->pipe_src_w - 1);
2730 y += (crtc_state->pipe_src_h - 1);
2731
2732 /* Finding the last pixel of the last line of the display
2733 data and adding to linear_offset*/
2734 linear_offset +=
2735 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2736 (crtc_state->pipe_src_w - 1) * cpp;
2737 }
2738
2739 intel_crtc->adjusted_x = x;
2740 intel_crtc->adjusted_y = y;
2741
2742 I915_WRITE(reg, dspcntr);
2743
2744 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2745 if (INTEL_INFO(dev)->gen >= 4) {
2746 I915_WRITE(DSPSURF(plane),
2747 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2748 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2749 I915_WRITE(DSPLINOFF(plane), linear_offset);
2750 } else
2751 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2752 POSTING_READ(reg);
2753 }
2754
2755 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2756 struct drm_crtc *crtc)
2757 {
2758 struct drm_device *dev = crtc->dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2761 int plane = intel_crtc->plane;
2762
2763 I915_WRITE(DSPCNTR(plane), 0);
2764 if (INTEL_INFO(dev_priv)->gen >= 4)
2765 I915_WRITE(DSPSURF(plane), 0);
2766 else
2767 I915_WRITE(DSPADDR(plane), 0);
2768 POSTING_READ(DSPCNTR(plane));
2769 }
2770
2771 static void ironlake_update_primary_plane(struct drm_plane *primary,
2772 const struct intel_crtc_state *crtc_state,
2773 const struct intel_plane_state *plane_state)
2774 {
2775 struct drm_device *dev = primary->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2778 struct drm_framebuffer *fb = plane_state->base.fb;
2779 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2780 int plane = intel_crtc->plane;
2781 u32 linear_offset;
2782 u32 dspcntr;
2783 i915_reg_t reg = DSPCNTR(plane);
2784 unsigned int rotation = plane_state->base.rotation;
2785 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2786 int x = plane_state->src.x1 >> 16;
2787 int y = plane_state->src.y1 >> 16;
2788
2789 dspcntr = DISPPLANE_GAMMA_ENABLE;
2790 dspcntr |= DISPLAY_PLANE_ENABLE;
2791
2792 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2793 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2794
2795 switch (fb->pixel_format) {
2796 case DRM_FORMAT_C8:
2797 dspcntr |= DISPPLANE_8BPP;
2798 break;
2799 case DRM_FORMAT_RGB565:
2800 dspcntr |= DISPPLANE_BGRX565;
2801 break;
2802 case DRM_FORMAT_XRGB8888:
2803 dspcntr |= DISPPLANE_BGRX888;
2804 break;
2805 case DRM_FORMAT_XBGR8888:
2806 dspcntr |= DISPPLANE_RGBX888;
2807 break;
2808 case DRM_FORMAT_XRGB2101010:
2809 dspcntr |= DISPPLANE_BGRX101010;
2810 break;
2811 case DRM_FORMAT_XBGR2101010:
2812 dspcntr |= DISPPLANE_RGBX101010;
2813 break;
2814 default:
2815 BUG();
2816 }
2817
2818 if (obj->tiling_mode != I915_TILING_NONE)
2819 dspcntr |= DISPPLANE_TILED;
2820
2821 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2822 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2823
2824 linear_offset = y * fb->pitches[0] + x * cpp;
2825 intel_crtc->dspaddr_offset =
2826 intel_compute_tile_offset(&x, &y, fb, 0,
2827 fb->pitches[0], rotation);
2828 linear_offset -= intel_crtc->dspaddr_offset;
2829 if (rotation == BIT(DRM_ROTATE_180)) {
2830 dspcntr |= DISPPLANE_ROTATE_180;
2831
2832 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2833 x += (crtc_state->pipe_src_w - 1);
2834 y += (crtc_state->pipe_src_h - 1);
2835
2836 /* Finding the last pixel of the last line of the display
2837 data and adding to linear_offset*/
2838 linear_offset +=
2839 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2840 (crtc_state->pipe_src_w - 1) * cpp;
2841 }
2842 }
2843
2844 intel_crtc->adjusted_x = x;
2845 intel_crtc->adjusted_y = y;
2846
2847 I915_WRITE(reg, dspcntr);
2848
2849 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2850 I915_WRITE(DSPSURF(plane),
2851 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2853 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2854 } else {
2855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2856 I915_WRITE(DSPLINOFF(plane), linear_offset);
2857 }
2858 POSTING_READ(reg);
2859 }
2860
2861 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2862 uint64_t fb_modifier, uint32_t pixel_format)
2863 {
2864 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2865 return 64;
2866 } else {
2867 int cpp = drm_format_plane_cpp(pixel_format, 0);
2868
2869 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2870 }
2871 }
2872
2873 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2874 struct drm_i915_gem_object *obj,
2875 unsigned int plane)
2876 {
2877 struct i915_ggtt_view view;
2878 struct i915_vma *vma;
2879 u64 offset;
2880
2881 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2882 intel_plane->base.state->rotation);
2883
2884 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2885 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2886 view.type))
2887 return -1;
2888
2889 offset = vma->node.start;
2890
2891 if (plane == 1) {
2892 offset += vma->ggtt_view.params.rotated.uv_start_page *
2893 PAGE_SIZE;
2894 }
2895
2896 WARN_ON(upper_32_bits(offset));
2897
2898 return lower_32_bits(offset);
2899 }
2900
2901 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2902 {
2903 struct drm_device *dev = intel_crtc->base.dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905
2906 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2907 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2908 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2909 }
2910
2911 /*
2912 * This function detaches (aka. unbinds) unused scalers in hardware
2913 */
2914 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2915 {
2916 struct intel_crtc_scaler_state *scaler_state;
2917 int i;
2918
2919 scaler_state = &intel_crtc->config->scaler_state;
2920
2921 /* loop through and disable scalers that aren't in use */
2922 for (i = 0; i < intel_crtc->num_scalers; i++) {
2923 if (!scaler_state->scalers[i].in_use)
2924 skl_detach_scaler(intel_crtc, i);
2925 }
2926 }
2927
2928 u32 skl_plane_ctl_format(uint32_t pixel_format)
2929 {
2930 switch (pixel_format) {
2931 case DRM_FORMAT_C8:
2932 return PLANE_CTL_FORMAT_INDEXED;
2933 case DRM_FORMAT_RGB565:
2934 return PLANE_CTL_FORMAT_RGB_565;
2935 case DRM_FORMAT_XBGR8888:
2936 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2937 case DRM_FORMAT_XRGB8888:
2938 return PLANE_CTL_FORMAT_XRGB_8888;
2939 /*
2940 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2941 * to be already pre-multiplied. We need to add a knob (or a different
2942 * DRM_FORMAT) for user-space to configure that.
2943 */
2944 case DRM_FORMAT_ABGR8888:
2945 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2946 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2947 case DRM_FORMAT_ARGB8888:
2948 return PLANE_CTL_FORMAT_XRGB_8888 |
2949 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2950 case DRM_FORMAT_XRGB2101010:
2951 return PLANE_CTL_FORMAT_XRGB_2101010;
2952 case DRM_FORMAT_XBGR2101010:
2953 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2954 case DRM_FORMAT_YUYV:
2955 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2956 case DRM_FORMAT_YVYU:
2957 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2958 case DRM_FORMAT_UYVY:
2959 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2960 case DRM_FORMAT_VYUY:
2961 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2962 default:
2963 MISSING_CASE(pixel_format);
2964 }
2965
2966 return 0;
2967 }
2968
2969 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2970 {
2971 switch (fb_modifier) {
2972 case DRM_FORMAT_MOD_NONE:
2973 break;
2974 case I915_FORMAT_MOD_X_TILED:
2975 return PLANE_CTL_TILED_X;
2976 case I915_FORMAT_MOD_Y_TILED:
2977 return PLANE_CTL_TILED_Y;
2978 case I915_FORMAT_MOD_Yf_TILED:
2979 return PLANE_CTL_TILED_YF;
2980 default:
2981 MISSING_CASE(fb_modifier);
2982 }
2983
2984 return 0;
2985 }
2986
2987 u32 skl_plane_ctl_rotation(unsigned int rotation)
2988 {
2989 switch (rotation) {
2990 case BIT(DRM_ROTATE_0):
2991 break;
2992 /*
2993 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2994 * while i915 HW rotation is clockwise, thats why this swapping.
2995 */
2996 case BIT(DRM_ROTATE_90):
2997 return PLANE_CTL_ROTATE_270;
2998 case BIT(DRM_ROTATE_180):
2999 return PLANE_CTL_ROTATE_180;
3000 case BIT(DRM_ROTATE_270):
3001 return PLANE_CTL_ROTATE_90;
3002 default:
3003 MISSING_CASE(rotation);
3004 }
3005
3006 return 0;
3007 }
3008
3009 static void skylake_update_primary_plane(struct drm_plane *plane,
3010 const struct intel_crtc_state *crtc_state,
3011 const struct intel_plane_state *plane_state)
3012 {
3013 struct drm_device *dev = plane->dev;
3014 struct drm_i915_private *dev_priv = dev->dev_private;
3015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3016 struct drm_framebuffer *fb = plane_state->base.fb;
3017 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3018 int pipe = intel_crtc->pipe;
3019 u32 plane_ctl, stride_div, stride;
3020 u32 tile_height, plane_offset, plane_size;
3021 unsigned int rotation = plane_state->base.rotation;
3022 int x_offset, y_offset;
3023 u32 surf_addr;
3024 int scaler_id = plane_state->scaler_id;
3025 int src_x = plane_state->src.x1 >> 16;
3026 int src_y = plane_state->src.y1 >> 16;
3027 int src_w = drm_rect_width(&plane_state->src) >> 16;
3028 int src_h = drm_rect_height(&plane_state->src) >> 16;
3029 int dst_x = plane_state->dst.x1;
3030 int dst_y = plane_state->dst.y1;
3031 int dst_w = drm_rect_width(&plane_state->dst);
3032 int dst_h = drm_rect_height(&plane_state->dst);
3033
3034 plane_ctl = PLANE_CTL_ENABLE |
3035 PLANE_CTL_PIPE_GAMMA_ENABLE |
3036 PLANE_CTL_PIPE_CSC_ENABLE;
3037
3038 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3039 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3040 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3041 plane_ctl |= skl_plane_ctl_rotation(rotation);
3042
3043 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3044 fb->pixel_format);
3045 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3046
3047 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3048
3049 if (intel_rotation_90_or_270(rotation)) {
3050 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3051
3052 /* stride = Surface height in tiles */
3053 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3054 stride = DIV_ROUND_UP(fb->height, tile_height);
3055 x_offset = stride * tile_height - src_y - src_h;
3056 y_offset = src_x;
3057 plane_size = (src_w - 1) << 16 | (src_h - 1);
3058 } else {
3059 stride = fb->pitches[0] / stride_div;
3060 x_offset = src_x;
3061 y_offset = src_y;
3062 plane_size = (src_h - 1) << 16 | (src_w - 1);
3063 }
3064 plane_offset = y_offset << 16 | x_offset;
3065
3066 intel_crtc->adjusted_x = x_offset;
3067 intel_crtc->adjusted_y = y_offset;
3068
3069 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3070 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3071 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3072 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3073
3074 if (scaler_id >= 0) {
3075 uint32_t ps_ctrl = 0;
3076
3077 WARN_ON(!dst_w || !dst_h);
3078 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3079 crtc_state->scaler_state.scalers[scaler_id].mode;
3080 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3081 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3082 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3083 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3084 I915_WRITE(PLANE_POS(pipe, 0), 0);
3085 } else {
3086 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3087 }
3088
3089 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3090
3091 POSTING_READ(PLANE_SURF(pipe, 0));
3092 }
3093
3094 static void skylake_disable_primary_plane(struct drm_plane *primary,
3095 struct drm_crtc *crtc)
3096 {
3097 struct drm_device *dev = crtc->dev;
3098 struct drm_i915_private *dev_priv = dev->dev_private;
3099 int pipe = to_intel_crtc(crtc)->pipe;
3100
3101 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3102 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3103 POSTING_READ(PLANE_SURF(pipe, 0));
3104 }
3105
3106 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3107 static int
3108 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3109 int x, int y, enum mode_set_atomic state)
3110 {
3111 /* Support for kgdboc is disabled, this needs a major rework. */
3112 DRM_ERROR("legacy panic handler not supported any more.\n");
3113
3114 return -ENODEV;
3115 }
3116
3117 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3118 {
3119 struct intel_crtc *crtc;
3120
3121 for_each_intel_crtc(dev_priv->dev, crtc)
3122 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3123 }
3124
3125 static void intel_update_primary_planes(struct drm_device *dev)
3126 {
3127 struct drm_crtc *crtc;
3128
3129 for_each_crtc(dev, crtc) {
3130 struct intel_plane *plane = to_intel_plane(crtc->primary);
3131 struct intel_plane_state *plane_state;
3132
3133 drm_modeset_lock_crtc(crtc, &plane->base);
3134 plane_state = to_intel_plane_state(plane->base.state);
3135
3136 if (plane_state->visible)
3137 plane->update_plane(&plane->base,
3138 to_intel_crtc_state(crtc->state),
3139 plane_state);
3140
3141 drm_modeset_unlock_crtc(crtc);
3142 }
3143 }
3144
3145 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3146 {
3147 /* no reset support for gen2 */
3148 if (IS_GEN2(dev_priv))
3149 return;
3150
3151 /* reset doesn't touch the display */
3152 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3153 return;
3154
3155 drm_modeset_lock_all(dev_priv->dev);
3156 /*
3157 * Disabling the crtcs gracefully seems nicer. Also the
3158 * g33 docs say we should at least disable all the planes.
3159 */
3160 intel_display_suspend(dev_priv->dev);
3161 }
3162
3163 void intel_finish_reset(struct drm_i915_private *dev_priv)
3164 {
3165 /*
3166 * Flips in the rings will be nuked by the reset,
3167 * so complete all pending flips so that user space
3168 * will get its events and not get stuck.
3169 */
3170 intel_complete_page_flips(dev_priv);
3171
3172 /* no reset support for gen2 */
3173 if (IS_GEN2(dev_priv))
3174 return;
3175
3176 /* reset doesn't touch the display */
3177 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3178 /*
3179 * Flips in the rings have been nuked by the reset,
3180 * so update the base address of all primary
3181 * planes to the the last fb to make sure we're
3182 * showing the correct fb after a reset.
3183 *
3184 * FIXME: Atomic will make this obsolete since we won't schedule
3185 * CS-based flips (which might get lost in gpu resets) any more.
3186 */
3187 intel_update_primary_planes(dev_priv->dev);
3188 return;
3189 }
3190
3191 /*
3192 * The display has been reset as well,
3193 * so need a full re-initialization.
3194 */
3195 intel_runtime_pm_disable_interrupts(dev_priv);
3196 intel_runtime_pm_enable_interrupts(dev_priv);
3197
3198 intel_modeset_init_hw(dev_priv->dev);
3199
3200 spin_lock_irq(&dev_priv->irq_lock);
3201 if (dev_priv->display.hpd_irq_setup)
3202 dev_priv->display.hpd_irq_setup(dev_priv);
3203 spin_unlock_irq(&dev_priv->irq_lock);
3204
3205 intel_display_resume(dev_priv->dev);
3206
3207 intel_hpd_init(dev_priv);
3208
3209 drm_modeset_unlock_all(dev_priv->dev);
3210 }
3211
3212 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3213 {
3214 struct drm_device *dev = crtc->dev;
3215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3216 unsigned reset_counter;
3217 bool pending;
3218
3219 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3220 if (intel_crtc->reset_counter != reset_counter)
3221 return false;
3222
3223 spin_lock_irq(&dev->event_lock);
3224 pending = to_intel_crtc(crtc)->flip_work != NULL;
3225 spin_unlock_irq(&dev->event_lock);
3226
3227 return pending;
3228 }
3229
3230 static void intel_update_pipe_config(struct intel_crtc *crtc,
3231 struct intel_crtc_state *old_crtc_state)
3232 {
3233 struct drm_device *dev = crtc->base.dev;
3234 struct drm_i915_private *dev_priv = dev->dev_private;
3235 struct intel_crtc_state *pipe_config =
3236 to_intel_crtc_state(crtc->base.state);
3237
3238 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3239 crtc->base.mode = crtc->base.state->mode;
3240
3241 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3242 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3243 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3244
3245 /*
3246 * Update pipe size and adjust fitter if needed: the reason for this is
3247 * that in compute_mode_changes we check the native mode (not the pfit
3248 * mode) to see if we can flip rather than do a full mode set. In the
3249 * fastboot case, we'll flip, but if we don't update the pipesrc and
3250 * pfit state, we'll end up with a big fb scanned out into the wrong
3251 * sized surface.
3252 */
3253
3254 I915_WRITE(PIPESRC(crtc->pipe),
3255 ((pipe_config->pipe_src_w - 1) << 16) |
3256 (pipe_config->pipe_src_h - 1));
3257
3258 /* on skylake this is done by detaching scalers */
3259 if (INTEL_INFO(dev)->gen >= 9) {
3260 skl_detach_scalers(crtc);
3261
3262 if (pipe_config->pch_pfit.enabled)
3263 skylake_pfit_enable(crtc);
3264 } else if (HAS_PCH_SPLIT(dev)) {
3265 if (pipe_config->pch_pfit.enabled)
3266 ironlake_pfit_enable(crtc);
3267 else if (old_crtc_state->pch_pfit.enabled)
3268 ironlake_pfit_disable(crtc, true);
3269 }
3270 }
3271
3272 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3273 {
3274 struct drm_device *dev = crtc->dev;
3275 struct drm_i915_private *dev_priv = dev->dev_private;
3276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3277 int pipe = intel_crtc->pipe;
3278 i915_reg_t reg;
3279 u32 temp;
3280
3281 /* enable normal train */
3282 reg = FDI_TX_CTL(pipe);
3283 temp = I915_READ(reg);
3284 if (IS_IVYBRIDGE(dev)) {
3285 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3286 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3287 } else {
3288 temp &= ~FDI_LINK_TRAIN_NONE;
3289 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3290 }
3291 I915_WRITE(reg, temp);
3292
3293 reg = FDI_RX_CTL(pipe);
3294 temp = I915_READ(reg);
3295 if (HAS_PCH_CPT(dev)) {
3296 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3297 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3298 } else {
3299 temp &= ~FDI_LINK_TRAIN_NONE;
3300 temp |= FDI_LINK_TRAIN_NONE;
3301 }
3302 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3303
3304 /* wait one idle pattern time */
3305 POSTING_READ(reg);
3306 udelay(1000);
3307
3308 /* IVB wants error correction enabled */
3309 if (IS_IVYBRIDGE(dev))
3310 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3311 FDI_FE_ERRC_ENABLE);
3312 }
3313
3314 /* The FDI link training functions for ILK/Ibexpeak. */
3315 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3316 {
3317 struct drm_device *dev = crtc->dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3320 int pipe = intel_crtc->pipe;
3321 i915_reg_t reg;
3322 u32 temp, tries;
3323
3324 /* FDI needs bits from pipe first */
3325 assert_pipe_enabled(dev_priv, pipe);
3326
3327 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3328 for train result */
3329 reg = FDI_RX_IMR(pipe);
3330 temp = I915_READ(reg);
3331 temp &= ~FDI_RX_SYMBOL_LOCK;
3332 temp &= ~FDI_RX_BIT_LOCK;
3333 I915_WRITE(reg, temp);
3334 I915_READ(reg);
3335 udelay(150);
3336
3337 /* enable CPU FDI TX and PCH FDI RX */
3338 reg = FDI_TX_CTL(pipe);
3339 temp = I915_READ(reg);
3340 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3341 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3342 temp &= ~FDI_LINK_TRAIN_NONE;
3343 temp |= FDI_LINK_TRAIN_PATTERN_1;
3344 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3345
3346 reg = FDI_RX_CTL(pipe);
3347 temp = I915_READ(reg);
3348 temp &= ~FDI_LINK_TRAIN_NONE;
3349 temp |= FDI_LINK_TRAIN_PATTERN_1;
3350 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3351
3352 POSTING_READ(reg);
3353 udelay(150);
3354
3355 /* Ironlake workaround, enable clock pointer after FDI enable*/
3356 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3357 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3358 FDI_RX_PHASE_SYNC_POINTER_EN);
3359
3360 reg = FDI_RX_IIR(pipe);
3361 for (tries = 0; tries < 5; tries++) {
3362 temp = I915_READ(reg);
3363 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3364
3365 if ((temp & FDI_RX_BIT_LOCK)) {
3366 DRM_DEBUG_KMS("FDI train 1 done.\n");
3367 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3368 break;
3369 }
3370 }
3371 if (tries == 5)
3372 DRM_ERROR("FDI train 1 fail!\n");
3373
3374 /* Train 2 */
3375 reg = FDI_TX_CTL(pipe);
3376 temp = I915_READ(reg);
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_PATTERN_2;
3379 I915_WRITE(reg, temp);
3380
3381 reg = FDI_RX_CTL(pipe);
3382 temp = I915_READ(reg);
3383 temp &= ~FDI_LINK_TRAIN_NONE;
3384 temp |= FDI_LINK_TRAIN_PATTERN_2;
3385 I915_WRITE(reg, temp);
3386
3387 POSTING_READ(reg);
3388 udelay(150);
3389
3390 reg = FDI_RX_IIR(pipe);
3391 for (tries = 0; tries < 5; tries++) {
3392 temp = I915_READ(reg);
3393 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3394
3395 if (temp & FDI_RX_SYMBOL_LOCK) {
3396 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3397 DRM_DEBUG_KMS("FDI train 2 done.\n");
3398 break;
3399 }
3400 }
3401 if (tries == 5)
3402 DRM_ERROR("FDI train 2 fail!\n");
3403
3404 DRM_DEBUG_KMS("FDI train done\n");
3405
3406 }
3407
3408 static const int snb_b_fdi_train_param[] = {
3409 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3410 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3411 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3412 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3413 };
3414
3415 /* The FDI link training functions for SNB/Cougarpoint. */
3416 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3417 {
3418 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421 int pipe = intel_crtc->pipe;
3422 i915_reg_t reg;
3423 u32 temp, i, retry;
3424
3425 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3426 for train result */
3427 reg = FDI_RX_IMR(pipe);
3428 temp = I915_READ(reg);
3429 temp &= ~FDI_RX_SYMBOL_LOCK;
3430 temp &= ~FDI_RX_BIT_LOCK;
3431 I915_WRITE(reg, temp);
3432
3433 POSTING_READ(reg);
3434 udelay(150);
3435
3436 /* enable CPU FDI TX and PCH FDI RX */
3437 reg = FDI_TX_CTL(pipe);
3438 temp = I915_READ(reg);
3439 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3440 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3441 temp &= ~FDI_LINK_TRAIN_NONE;
3442 temp |= FDI_LINK_TRAIN_PATTERN_1;
3443 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3444 /* SNB-B */
3445 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3446 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3447
3448 I915_WRITE(FDI_RX_MISC(pipe),
3449 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3450
3451 reg = FDI_RX_CTL(pipe);
3452 temp = I915_READ(reg);
3453 if (HAS_PCH_CPT(dev)) {
3454 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3455 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3456 } else {
3457 temp &= ~FDI_LINK_TRAIN_NONE;
3458 temp |= FDI_LINK_TRAIN_PATTERN_1;
3459 }
3460 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3461
3462 POSTING_READ(reg);
3463 udelay(150);
3464
3465 for (i = 0; i < 4; i++) {
3466 reg = FDI_TX_CTL(pipe);
3467 temp = I915_READ(reg);
3468 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3469 temp |= snb_b_fdi_train_param[i];
3470 I915_WRITE(reg, temp);
3471
3472 POSTING_READ(reg);
3473 udelay(500);
3474
3475 for (retry = 0; retry < 5; retry++) {
3476 reg = FDI_RX_IIR(pipe);
3477 temp = I915_READ(reg);
3478 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3479 if (temp & FDI_RX_BIT_LOCK) {
3480 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3481 DRM_DEBUG_KMS("FDI train 1 done.\n");
3482 break;
3483 }
3484 udelay(50);
3485 }
3486 if (retry < 5)
3487 break;
3488 }
3489 if (i == 4)
3490 DRM_ERROR("FDI train 1 fail!\n");
3491
3492 /* Train 2 */
3493 reg = FDI_TX_CTL(pipe);
3494 temp = I915_READ(reg);
3495 temp &= ~FDI_LINK_TRAIN_NONE;
3496 temp |= FDI_LINK_TRAIN_PATTERN_2;
3497 if (IS_GEN6(dev)) {
3498 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3499 /* SNB-B */
3500 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3501 }
3502 I915_WRITE(reg, temp);
3503
3504 reg = FDI_RX_CTL(pipe);
3505 temp = I915_READ(reg);
3506 if (HAS_PCH_CPT(dev)) {
3507 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3508 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3509 } else {
3510 temp &= ~FDI_LINK_TRAIN_NONE;
3511 temp |= FDI_LINK_TRAIN_PATTERN_2;
3512 }
3513 I915_WRITE(reg, temp);
3514
3515 POSTING_READ(reg);
3516 udelay(150);
3517
3518 for (i = 0; i < 4; i++) {
3519 reg = FDI_TX_CTL(pipe);
3520 temp = I915_READ(reg);
3521 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3522 temp |= snb_b_fdi_train_param[i];
3523 I915_WRITE(reg, temp);
3524
3525 POSTING_READ(reg);
3526 udelay(500);
3527
3528 for (retry = 0; retry < 5; retry++) {
3529 reg = FDI_RX_IIR(pipe);
3530 temp = I915_READ(reg);
3531 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3532 if (temp & FDI_RX_SYMBOL_LOCK) {
3533 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3534 DRM_DEBUG_KMS("FDI train 2 done.\n");
3535 break;
3536 }
3537 udelay(50);
3538 }
3539 if (retry < 5)
3540 break;
3541 }
3542 if (i == 4)
3543 DRM_ERROR("FDI train 2 fail!\n");
3544
3545 DRM_DEBUG_KMS("FDI train done.\n");
3546 }
3547
3548 /* Manual link training for Ivy Bridge A0 parts */
3549 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3550 {
3551 struct drm_device *dev = crtc->dev;
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3554 int pipe = intel_crtc->pipe;
3555 i915_reg_t reg;
3556 u32 temp, i, j;
3557
3558 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3559 for train result */
3560 reg = FDI_RX_IMR(pipe);
3561 temp = I915_READ(reg);
3562 temp &= ~FDI_RX_SYMBOL_LOCK;
3563 temp &= ~FDI_RX_BIT_LOCK;
3564 I915_WRITE(reg, temp);
3565
3566 POSTING_READ(reg);
3567 udelay(150);
3568
3569 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3570 I915_READ(FDI_RX_IIR(pipe)));
3571
3572 /* Try each vswing and preemphasis setting twice before moving on */
3573 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3574 /* disable first in case we need to retry */
3575 reg = FDI_TX_CTL(pipe);
3576 temp = I915_READ(reg);
3577 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3578 temp &= ~FDI_TX_ENABLE;
3579 I915_WRITE(reg, temp);
3580
3581 reg = FDI_RX_CTL(pipe);
3582 temp = I915_READ(reg);
3583 temp &= ~FDI_LINK_TRAIN_AUTO;
3584 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3585 temp &= ~FDI_RX_ENABLE;
3586 I915_WRITE(reg, temp);
3587
3588 /* enable CPU FDI TX and PCH FDI RX */
3589 reg = FDI_TX_CTL(pipe);
3590 temp = I915_READ(reg);
3591 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3592 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3593 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3594 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3595 temp |= snb_b_fdi_train_param[j/2];
3596 temp |= FDI_COMPOSITE_SYNC;
3597 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3598
3599 I915_WRITE(FDI_RX_MISC(pipe),
3600 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3601
3602 reg = FDI_RX_CTL(pipe);
3603 temp = I915_READ(reg);
3604 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3605 temp |= FDI_COMPOSITE_SYNC;
3606 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3607
3608 POSTING_READ(reg);
3609 udelay(1); /* should be 0.5us */
3610
3611 for (i = 0; i < 4; i++) {
3612 reg = FDI_RX_IIR(pipe);
3613 temp = I915_READ(reg);
3614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3615
3616 if (temp & FDI_RX_BIT_LOCK ||
3617 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3618 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3619 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3620 i);
3621 break;
3622 }
3623 udelay(1); /* should be 0.5us */
3624 }
3625 if (i == 4) {
3626 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3627 continue;
3628 }
3629
3630 /* Train 2 */
3631 reg = FDI_TX_CTL(pipe);
3632 temp = I915_READ(reg);
3633 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3634 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3635 I915_WRITE(reg, temp);
3636
3637 reg = FDI_RX_CTL(pipe);
3638 temp = I915_READ(reg);
3639 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3640 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3641 I915_WRITE(reg, temp);
3642
3643 POSTING_READ(reg);
3644 udelay(2); /* should be 1.5us */
3645
3646 for (i = 0; i < 4; i++) {
3647 reg = FDI_RX_IIR(pipe);
3648 temp = I915_READ(reg);
3649 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3650
3651 if (temp & FDI_RX_SYMBOL_LOCK ||
3652 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3653 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3654 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3655 i);
3656 goto train_done;
3657 }
3658 udelay(2); /* should be 1.5us */
3659 }
3660 if (i == 4)
3661 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3662 }
3663
3664 train_done:
3665 DRM_DEBUG_KMS("FDI train done.\n");
3666 }
3667
3668 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3669 {
3670 struct drm_device *dev = intel_crtc->base.dev;
3671 struct drm_i915_private *dev_priv = dev->dev_private;
3672 int pipe = intel_crtc->pipe;
3673 i915_reg_t reg;
3674 u32 temp;
3675
3676 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3677 reg = FDI_RX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3681 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3682 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3683
3684 POSTING_READ(reg);
3685 udelay(200);
3686
3687 /* Switch from Rawclk to PCDclk */
3688 temp = I915_READ(reg);
3689 I915_WRITE(reg, temp | FDI_PCDCLK);
3690
3691 POSTING_READ(reg);
3692 udelay(200);
3693
3694 /* Enable CPU FDI TX PLL, always on for Ironlake */
3695 reg = FDI_TX_CTL(pipe);
3696 temp = I915_READ(reg);
3697 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3698 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3699
3700 POSTING_READ(reg);
3701 udelay(100);
3702 }
3703 }
3704
3705 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3706 {
3707 struct drm_device *dev = intel_crtc->base.dev;
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709 int pipe = intel_crtc->pipe;
3710 i915_reg_t reg;
3711 u32 temp;
3712
3713 /* Switch from PCDclk to Rawclk */
3714 reg = FDI_RX_CTL(pipe);
3715 temp = I915_READ(reg);
3716 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3717
3718 /* Disable CPU FDI TX PLL */
3719 reg = FDI_TX_CTL(pipe);
3720 temp = I915_READ(reg);
3721 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3722
3723 POSTING_READ(reg);
3724 udelay(100);
3725
3726 reg = FDI_RX_CTL(pipe);
3727 temp = I915_READ(reg);
3728 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3729
3730 /* Wait for the clocks to turn off. */
3731 POSTING_READ(reg);
3732 udelay(100);
3733 }
3734
3735 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3736 {
3737 struct drm_device *dev = crtc->dev;
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740 int pipe = intel_crtc->pipe;
3741 i915_reg_t reg;
3742 u32 temp;
3743
3744 /* disable CPU FDI tx and PCH FDI rx */
3745 reg = FDI_TX_CTL(pipe);
3746 temp = I915_READ(reg);
3747 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3748 POSTING_READ(reg);
3749
3750 reg = FDI_RX_CTL(pipe);
3751 temp = I915_READ(reg);
3752 temp &= ~(0x7 << 16);
3753 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3754 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3755
3756 POSTING_READ(reg);
3757 udelay(100);
3758
3759 /* Ironlake workaround, disable clock pointer after downing FDI */
3760 if (HAS_PCH_IBX(dev))
3761 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3762
3763 /* still set train pattern 1 */
3764 reg = FDI_TX_CTL(pipe);
3765 temp = I915_READ(reg);
3766 temp &= ~FDI_LINK_TRAIN_NONE;
3767 temp |= FDI_LINK_TRAIN_PATTERN_1;
3768 I915_WRITE(reg, temp);
3769
3770 reg = FDI_RX_CTL(pipe);
3771 temp = I915_READ(reg);
3772 if (HAS_PCH_CPT(dev)) {
3773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3774 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3775 } else {
3776 temp &= ~FDI_LINK_TRAIN_NONE;
3777 temp |= FDI_LINK_TRAIN_PATTERN_1;
3778 }
3779 /* BPC in FDI rx is consistent with that in PIPECONF */
3780 temp &= ~(0x07 << 16);
3781 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3782 I915_WRITE(reg, temp);
3783
3784 POSTING_READ(reg);
3785 udelay(100);
3786 }
3787
3788 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3789 {
3790 struct intel_crtc *crtc;
3791
3792 /* Note that we don't need to be called with mode_config.lock here
3793 * as our list of CRTC objects is static for the lifetime of the
3794 * device and so cannot disappear as we iterate. Similarly, we can
3795 * happily treat the predicates as racy, atomic checks as userspace
3796 * cannot claim and pin a new fb without at least acquring the
3797 * struct_mutex and so serialising with us.
3798 */
3799 for_each_intel_crtc(dev, crtc) {
3800 if (atomic_read(&crtc->unpin_work_count) == 0)
3801 continue;
3802
3803 if (crtc->flip_work)
3804 intel_wait_for_vblank(dev, crtc->pipe);
3805
3806 return true;
3807 }
3808
3809 return false;
3810 }
3811
3812 static void page_flip_completed(struct intel_crtc *intel_crtc)
3813 {
3814 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3815 struct intel_flip_work *work = intel_crtc->flip_work;
3816
3817 intel_crtc->flip_work = NULL;
3818
3819 if (work->event)
3820 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3821
3822 drm_crtc_vblank_put(&intel_crtc->base);
3823
3824 wake_up_all(&dev_priv->pending_flip_queue);
3825 queue_work(dev_priv->wq, &work->unpin_work);
3826
3827 trace_i915_flip_complete(intel_crtc->plane,
3828 work->pending_flip_obj);
3829 }
3830
3831 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3832 {
3833 struct drm_device *dev = crtc->dev;
3834 struct drm_i915_private *dev_priv = dev->dev_private;
3835 long ret;
3836
3837 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3838
3839 ret = wait_event_interruptible_timeout(
3840 dev_priv->pending_flip_queue,
3841 !intel_crtc_has_pending_flip(crtc),
3842 60*HZ);
3843
3844 if (ret < 0)
3845 return ret;
3846
3847 if (ret == 0) {
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849 struct intel_flip_work *work;
3850
3851 spin_lock_irq(&dev->event_lock);
3852 work = intel_crtc->flip_work;
3853 if (work && !is_mmio_work(work)) {
3854 WARN_ONCE(1, "Removing stuck page flip\n");
3855 page_flip_completed(intel_crtc);
3856 }
3857 spin_unlock_irq(&dev->event_lock);
3858 }
3859
3860 return 0;
3861 }
3862
3863 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3864 {
3865 u32 temp;
3866
3867 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3868
3869 mutex_lock(&dev_priv->sb_lock);
3870
3871 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3872 temp |= SBI_SSCCTL_DISABLE;
3873 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3874
3875 mutex_unlock(&dev_priv->sb_lock);
3876 }
3877
3878 /* Program iCLKIP clock to the desired frequency */
3879 static void lpt_program_iclkip(struct drm_crtc *crtc)
3880 {
3881 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3882 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3883 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3884 u32 temp;
3885
3886 lpt_disable_iclkip(dev_priv);
3887
3888 /* The iCLK virtual clock root frequency is in MHz,
3889 * but the adjusted_mode->crtc_clock in in KHz. To get the
3890 * divisors, it is necessary to divide one by another, so we
3891 * convert the virtual clock precision to KHz here for higher
3892 * precision.
3893 */
3894 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3895 u32 iclk_virtual_root_freq = 172800 * 1000;
3896 u32 iclk_pi_range = 64;
3897 u32 desired_divisor;
3898
3899 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3900 clock << auxdiv);
3901 divsel = (desired_divisor / iclk_pi_range) - 2;
3902 phaseinc = desired_divisor % iclk_pi_range;
3903
3904 /*
3905 * Near 20MHz is a corner case which is
3906 * out of range for the 7-bit divisor
3907 */
3908 if (divsel <= 0x7f)
3909 break;
3910 }
3911
3912 /* This should not happen with any sane values */
3913 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3914 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3915 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3916 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3917
3918 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3919 clock,
3920 auxdiv,
3921 divsel,
3922 phasedir,
3923 phaseinc);
3924
3925 mutex_lock(&dev_priv->sb_lock);
3926
3927 /* Program SSCDIVINTPHASE6 */
3928 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3929 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3930 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3931 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3932 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3933 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3934 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3935 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3936
3937 /* Program SSCAUXDIV */
3938 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3939 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3940 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3941 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3942
3943 /* Enable modulator and associated divider */
3944 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3945 temp &= ~SBI_SSCCTL_DISABLE;
3946 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3947
3948 mutex_unlock(&dev_priv->sb_lock);
3949
3950 /* Wait for initialization time */
3951 udelay(24);
3952
3953 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3954 }
3955
3956 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3957 {
3958 u32 divsel, phaseinc, auxdiv;
3959 u32 iclk_virtual_root_freq = 172800 * 1000;
3960 u32 iclk_pi_range = 64;
3961 u32 desired_divisor;
3962 u32 temp;
3963
3964 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3965 return 0;
3966
3967 mutex_lock(&dev_priv->sb_lock);
3968
3969 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3970 if (temp & SBI_SSCCTL_DISABLE) {
3971 mutex_unlock(&dev_priv->sb_lock);
3972 return 0;
3973 }
3974
3975 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3976 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3977 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3978 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3979 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3980
3981 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3982 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3983 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3984
3985 mutex_unlock(&dev_priv->sb_lock);
3986
3987 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3988
3989 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3990 desired_divisor << auxdiv);
3991 }
3992
3993 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3994 enum pipe pch_transcoder)
3995 {
3996 struct drm_device *dev = crtc->base.dev;
3997 struct drm_i915_private *dev_priv = dev->dev_private;
3998 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3999
4000 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4001 I915_READ(HTOTAL(cpu_transcoder)));
4002 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4003 I915_READ(HBLANK(cpu_transcoder)));
4004 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4005 I915_READ(HSYNC(cpu_transcoder)));
4006
4007 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4008 I915_READ(VTOTAL(cpu_transcoder)));
4009 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4010 I915_READ(VBLANK(cpu_transcoder)));
4011 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4012 I915_READ(VSYNC(cpu_transcoder)));
4013 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4014 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4015 }
4016
4017 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4018 {
4019 struct drm_i915_private *dev_priv = dev->dev_private;
4020 uint32_t temp;
4021
4022 temp = I915_READ(SOUTH_CHICKEN1);
4023 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4024 return;
4025
4026 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4027 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4028
4029 temp &= ~FDI_BC_BIFURCATION_SELECT;
4030 if (enable)
4031 temp |= FDI_BC_BIFURCATION_SELECT;
4032
4033 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4034 I915_WRITE(SOUTH_CHICKEN1, temp);
4035 POSTING_READ(SOUTH_CHICKEN1);
4036 }
4037
4038 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4039 {
4040 struct drm_device *dev = intel_crtc->base.dev;
4041
4042 switch (intel_crtc->pipe) {
4043 case PIPE_A:
4044 break;
4045 case PIPE_B:
4046 if (intel_crtc->config->fdi_lanes > 2)
4047 cpt_set_fdi_bc_bifurcation(dev, false);
4048 else
4049 cpt_set_fdi_bc_bifurcation(dev, true);
4050
4051 break;
4052 case PIPE_C:
4053 cpt_set_fdi_bc_bifurcation(dev, true);
4054
4055 break;
4056 default:
4057 BUG();
4058 }
4059 }
4060
4061 /* Return which DP Port should be selected for Transcoder DP control */
4062 static enum port
4063 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4064 {
4065 struct drm_device *dev = crtc->dev;
4066 struct intel_encoder *encoder;
4067
4068 for_each_encoder_on_crtc(dev, crtc, encoder) {
4069 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4070 encoder->type == INTEL_OUTPUT_EDP)
4071 return enc_to_dig_port(&encoder->base)->port;
4072 }
4073
4074 return -1;
4075 }
4076
4077 /*
4078 * Enable PCH resources required for PCH ports:
4079 * - PCH PLLs
4080 * - FDI training & RX/TX
4081 * - update transcoder timings
4082 * - DP transcoding bits
4083 * - transcoder
4084 */
4085 static void ironlake_pch_enable(struct drm_crtc *crtc)
4086 {
4087 struct drm_device *dev = crtc->dev;
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4090 int pipe = intel_crtc->pipe;
4091 u32 temp;
4092
4093 assert_pch_transcoder_disabled(dev_priv, pipe);
4094
4095 if (IS_IVYBRIDGE(dev))
4096 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4097
4098 /* Write the TU size bits before fdi link training, so that error
4099 * detection works. */
4100 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4101 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4102
4103 /* For PCH output, training FDI link */
4104 dev_priv->display.fdi_link_train(crtc);
4105
4106 /* We need to program the right clock selection before writing the pixel
4107 * mutliplier into the DPLL. */
4108 if (HAS_PCH_CPT(dev)) {
4109 u32 sel;
4110
4111 temp = I915_READ(PCH_DPLL_SEL);
4112 temp |= TRANS_DPLL_ENABLE(pipe);
4113 sel = TRANS_DPLLB_SEL(pipe);
4114 if (intel_crtc->config->shared_dpll ==
4115 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4116 temp |= sel;
4117 else
4118 temp &= ~sel;
4119 I915_WRITE(PCH_DPLL_SEL, temp);
4120 }
4121
4122 /* XXX: pch pll's can be enabled any time before we enable the PCH
4123 * transcoder, and we actually should do this to not upset any PCH
4124 * transcoder that already use the clock when we share it.
4125 *
4126 * Note that enable_shared_dpll tries to do the right thing, but
4127 * get_shared_dpll unconditionally resets the pll - we need that to have
4128 * the right LVDS enable sequence. */
4129 intel_enable_shared_dpll(intel_crtc);
4130
4131 /* set transcoder timing, panel must allow it */
4132 assert_panel_unlocked(dev_priv, pipe);
4133 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4134
4135 intel_fdi_normal_train(crtc);
4136
4137 /* For PCH DP, enable TRANS_DP_CTL */
4138 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4139 const struct drm_display_mode *adjusted_mode =
4140 &intel_crtc->config->base.adjusted_mode;
4141 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4142 i915_reg_t reg = TRANS_DP_CTL(pipe);
4143 temp = I915_READ(reg);
4144 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4145 TRANS_DP_SYNC_MASK |
4146 TRANS_DP_BPC_MASK);
4147 temp |= TRANS_DP_OUTPUT_ENABLE;
4148 temp |= bpc << 9; /* same format but at 11:9 */
4149
4150 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4151 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4152 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4153 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4154
4155 switch (intel_trans_dp_port_sel(crtc)) {
4156 case PORT_B:
4157 temp |= TRANS_DP_PORT_SEL_B;
4158 break;
4159 case PORT_C:
4160 temp |= TRANS_DP_PORT_SEL_C;
4161 break;
4162 case PORT_D:
4163 temp |= TRANS_DP_PORT_SEL_D;
4164 break;
4165 default:
4166 BUG();
4167 }
4168
4169 I915_WRITE(reg, temp);
4170 }
4171
4172 ironlake_enable_pch_transcoder(dev_priv, pipe);
4173 }
4174
4175 static void lpt_pch_enable(struct drm_crtc *crtc)
4176 {
4177 struct drm_device *dev = crtc->dev;
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4180 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4181
4182 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4183
4184 lpt_program_iclkip(crtc);
4185
4186 /* Set transcoder timing. */
4187 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4188
4189 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4190 }
4191
4192 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4193 {
4194 struct drm_i915_private *dev_priv = dev->dev_private;
4195 i915_reg_t dslreg = PIPEDSL(pipe);
4196 u32 temp;
4197
4198 temp = I915_READ(dslreg);
4199 udelay(500);
4200 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4201 if (wait_for(I915_READ(dslreg) != temp, 5))
4202 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4203 }
4204 }
4205
4206 static int
4207 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4208 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4209 int src_w, int src_h, int dst_w, int dst_h)
4210 {
4211 struct intel_crtc_scaler_state *scaler_state =
4212 &crtc_state->scaler_state;
4213 struct intel_crtc *intel_crtc =
4214 to_intel_crtc(crtc_state->base.crtc);
4215 int need_scaling;
4216
4217 need_scaling = intel_rotation_90_or_270(rotation) ?
4218 (src_h != dst_w || src_w != dst_h):
4219 (src_w != dst_w || src_h != dst_h);
4220
4221 /*
4222 * if plane is being disabled or scaler is no more required or force detach
4223 * - free scaler binded to this plane/crtc
4224 * - in order to do this, update crtc->scaler_usage
4225 *
4226 * Here scaler state in crtc_state is set free so that
4227 * scaler can be assigned to other user. Actual register
4228 * update to free the scaler is done in plane/panel-fit programming.
4229 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4230 */
4231 if (force_detach || !need_scaling) {
4232 if (*scaler_id >= 0) {
4233 scaler_state->scaler_users &= ~(1 << scaler_user);
4234 scaler_state->scalers[*scaler_id].in_use = 0;
4235
4236 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4237 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4238 intel_crtc->pipe, scaler_user, *scaler_id,
4239 scaler_state->scaler_users);
4240 *scaler_id = -1;
4241 }
4242 return 0;
4243 }
4244
4245 /* range checks */
4246 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4247 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4248
4249 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4250 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4251 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4252 "size is out of scaler range\n",
4253 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4254 return -EINVAL;
4255 }
4256
4257 /* mark this plane as a scaler user in crtc_state */
4258 scaler_state->scaler_users |= (1 << scaler_user);
4259 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4260 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4261 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4262 scaler_state->scaler_users);
4263
4264 return 0;
4265 }
4266
4267 /**
4268 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4269 *
4270 * @state: crtc's scaler state
4271 *
4272 * Return
4273 * 0 - scaler_usage updated successfully
4274 * error - requested scaling cannot be supported or other error condition
4275 */
4276 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4277 {
4278 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4279 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4280
4281 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4282 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4283
4284 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4285 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4286 state->pipe_src_w, state->pipe_src_h,
4287 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4288 }
4289
4290 /**
4291 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4292 *
4293 * @state: crtc's scaler state
4294 * @plane_state: atomic plane state to update
4295 *
4296 * Return
4297 * 0 - scaler_usage updated successfully
4298 * error - requested scaling cannot be supported or other error condition
4299 */
4300 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4301 struct intel_plane_state *plane_state)
4302 {
4303
4304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4305 struct intel_plane *intel_plane =
4306 to_intel_plane(plane_state->base.plane);
4307 struct drm_framebuffer *fb = plane_state->base.fb;
4308 int ret;
4309
4310 bool force_detach = !fb || !plane_state->visible;
4311
4312 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4313 intel_plane->base.base.id, intel_crtc->pipe,
4314 drm_plane_index(&intel_plane->base));
4315
4316 ret = skl_update_scaler(crtc_state, force_detach,
4317 drm_plane_index(&intel_plane->base),
4318 &plane_state->scaler_id,
4319 plane_state->base.rotation,
4320 drm_rect_width(&plane_state->src) >> 16,
4321 drm_rect_height(&plane_state->src) >> 16,
4322 drm_rect_width(&plane_state->dst),
4323 drm_rect_height(&plane_state->dst));
4324
4325 if (ret || plane_state->scaler_id < 0)
4326 return ret;
4327
4328 /* check colorkey */
4329 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4330 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4331 intel_plane->base.base.id);
4332 return -EINVAL;
4333 }
4334
4335 /* Check src format */
4336 switch (fb->pixel_format) {
4337 case DRM_FORMAT_RGB565:
4338 case DRM_FORMAT_XBGR8888:
4339 case DRM_FORMAT_XRGB8888:
4340 case DRM_FORMAT_ABGR8888:
4341 case DRM_FORMAT_ARGB8888:
4342 case DRM_FORMAT_XRGB2101010:
4343 case DRM_FORMAT_XBGR2101010:
4344 case DRM_FORMAT_YUYV:
4345 case DRM_FORMAT_YVYU:
4346 case DRM_FORMAT_UYVY:
4347 case DRM_FORMAT_VYUY:
4348 break;
4349 default:
4350 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4351 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4352 return -EINVAL;
4353 }
4354
4355 return 0;
4356 }
4357
4358 static void skylake_scaler_disable(struct intel_crtc *crtc)
4359 {
4360 int i;
4361
4362 for (i = 0; i < crtc->num_scalers; i++)
4363 skl_detach_scaler(crtc, i);
4364 }
4365
4366 static void skylake_pfit_enable(struct intel_crtc *crtc)
4367 {
4368 struct drm_device *dev = crtc->base.dev;
4369 struct drm_i915_private *dev_priv = dev->dev_private;
4370 int pipe = crtc->pipe;
4371 struct intel_crtc_scaler_state *scaler_state =
4372 &crtc->config->scaler_state;
4373
4374 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4375
4376 if (crtc->config->pch_pfit.enabled) {
4377 int id;
4378
4379 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4380 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4381 return;
4382 }
4383
4384 id = scaler_state->scaler_id;
4385 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4386 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4387 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4388 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4389
4390 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4391 }
4392 }
4393
4394 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4395 {
4396 struct drm_device *dev = crtc->base.dev;
4397 struct drm_i915_private *dev_priv = dev->dev_private;
4398 int pipe = crtc->pipe;
4399
4400 if (crtc->config->pch_pfit.enabled) {
4401 /* Force use of hard-coded filter coefficients
4402 * as some pre-programmed values are broken,
4403 * e.g. x201.
4404 */
4405 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4406 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4407 PF_PIPE_SEL_IVB(pipe));
4408 else
4409 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4410 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4411 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4412 }
4413 }
4414
4415 void hsw_enable_ips(struct intel_crtc *crtc)
4416 {
4417 struct drm_device *dev = crtc->base.dev;
4418 struct drm_i915_private *dev_priv = dev->dev_private;
4419
4420 if (!crtc->config->ips_enabled)
4421 return;
4422
4423 /*
4424 * We can only enable IPS after we enable a plane and wait for a vblank
4425 * This function is called from post_plane_update, which is run after
4426 * a vblank wait.
4427 */
4428
4429 assert_plane_enabled(dev_priv, crtc->plane);
4430 if (IS_BROADWELL(dev)) {
4431 mutex_lock(&dev_priv->rps.hw_lock);
4432 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4433 mutex_unlock(&dev_priv->rps.hw_lock);
4434 /* Quoting Art Runyan: "its not safe to expect any particular
4435 * value in IPS_CTL bit 31 after enabling IPS through the
4436 * mailbox." Moreover, the mailbox may return a bogus state,
4437 * so we need to just enable it and continue on.
4438 */
4439 } else {
4440 I915_WRITE(IPS_CTL, IPS_ENABLE);
4441 /* The bit only becomes 1 in the next vblank, so this wait here
4442 * is essentially intel_wait_for_vblank. If we don't have this
4443 * and don't wait for vblanks until the end of crtc_enable, then
4444 * the HW state readout code will complain that the expected
4445 * IPS_CTL value is not the one we read. */
4446 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4447 DRM_ERROR("Timed out waiting for IPS enable\n");
4448 }
4449 }
4450
4451 void hsw_disable_ips(struct intel_crtc *crtc)
4452 {
4453 struct drm_device *dev = crtc->base.dev;
4454 struct drm_i915_private *dev_priv = dev->dev_private;
4455
4456 if (!crtc->config->ips_enabled)
4457 return;
4458
4459 assert_plane_enabled(dev_priv, crtc->plane);
4460 if (IS_BROADWELL(dev)) {
4461 mutex_lock(&dev_priv->rps.hw_lock);
4462 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4463 mutex_unlock(&dev_priv->rps.hw_lock);
4464 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4465 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4466 DRM_ERROR("Timed out waiting for IPS disable\n");
4467 } else {
4468 I915_WRITE(IPS_CTL, 0);
4469 POSTING_READ(IPS_CTL);
4470 }
4471
4472 /* We need to wait for a vblank before we can disable the plane. */
4473 intel_wait_for_vblank(dev, crtc->pipe);
4474 }
4475
4476 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4477 {
4478 if (intel_crtc->overlay) {
4479 struct drm_device *dev = intel_crtc->base.dev;
4480 struct drm_i915_private *dev_priv = dev->dev_private;
4481
4482 mutex_lock(&dev->struct_mutex);
4483 dev_priv->mm.interruptible = false;
4484 (void) intel_overlay_switch_off(intel_crtc->overlay);
4485 dev_priv->mm.interruptible = true;
4486 mutex_unlock(&dev->struct_mutex);
4487 }
4488
4489 /* Let userspace switch the overlay on again. In most cases userspace
4490 * has to recompute where to put it anyway.
4491 */
4492 }
4493
4494 /**
4495 * intel_post_enable_primary - Perform operations after enabling primary plane
4496 * @crtc: the CRTC whose primary plane was just enabled
4497 *
4498 * Performs potentially sleeping operations that must be done after the primary
4499 * plane is enabled, such as updating FBC and IPS. Note that this may be
4500 * called due to an explicit primary plane update, or due to an implicit
4501 * re-enable that is caused when a sprite plane is updated to no longer
4502 * completely hide the primary plane.
4503 */
4504 static void
4505 intel_post_enable_primary(struct drm_crtc *crtc)
4506 {
4507 struct drm_device *dev = crtc->dev;
4508 struct drm_i915_private *dev_priv = dev->dev_private;
4509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4510 int pipe = intel_crtc->pipe;
4511
4512 /*
4513 * FIXME IPS should be fine as long as one plane is
4514 * enabled, but in practice it seems to have problems
4515 * when going from primary only to sprite only and vice
4516 * versa.
4517 */
4518 hsw_enable_ips(intel_crtc);
4519
4520 /*
4521 * Gen2 reports pipe underruns whenever all planes are disabled.
4522 * So don't enable underrun reporting before at least some planes
4523 * are enabled.
4524 * FIXME: Need to fix the logic to work when we turn off all planes
4525 * but leave the pipe running.
4526 */
4527 if (IS_GEN2(dev))
4528 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4529
4530 /* Underruns don't always raise interrupts, so check manually. */
4531 intel_check_cpu_fifo_underruns(dev_priv);
4532 intel_check_pch_fifo_underruns(dev_priv);
4533 }
4534
4535 /* FIXME move all this to pre_plane_update() with proper state tracking */
4536 static void
4537 intel_pre_disable_primary(struct drm_crtc *crtc)
4538 {
4539 struct drm_device *dev = crtc->dev;
4540 struct drm_i915_private *dev_priv = dev->dev_private;
4541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4542 int pipe = intel_crtc->pipe;
4543
4544 /*
4545 * Gen2 reports pipe underruns whenever all planes are disabled.
4546 * So diasble underrun reporting before all the planes get disabled.
4547 * FIXME: Need to fix the logic to work when we turn off all planes
4548 * but leave the pipe running.
4549 */
4550 if (IS_GEN2(dev))
4551 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4552
4553 /*
4554 * FIXME IPS should be fine as long as one plane is
4555 * enabled, but in practice it seems to have problems
4556 * when going from primary only to sprite only and vice
4557 * versa.
4558 */
4559 hsw_disable_ips(intel_crtc);
4560 }
4561
4562 /* FIXME get rid of this and use pre_plane_update */
4563 static void
4564 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4565 {
4566 struct drm_device *dev = crtc->dev;
4567 struct drm_i915_private *dev_priv = dev->dev_private;
4568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4569 int pipe = intel_crtc->pipe;
4570
4571 intel_pre_disable_primary(crtc);
4572
4573 /*
4574 * Vblank time updates from the shadow to live plane control register
4575 * are blocked if the memory self-refresh mode is active at that
4576 * moment. So to make sure the plane gets truly disabled, disable
4577 * first the self-refresh mode. The self-refresh enable bit in turn
4578 * will be checked/applied by the HW only at the next frame start
4579 * event which is after the vblank start event, so we need to have a
4580 * wait-for-vblank between disabling the plane and the pipe.
4581 */
4582 if (HAS_GMCH_DISPLAY(dev)) {
4583 intel_set_memory_cxsr(dev_priv, false);
4584 dev_priv->wm.vlv.cxsr = false;
4585 intel_wait_for_vblank(dev, pipe);
4586 }
4587 }
4588
4589 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4590 {
4591 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4592 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4593 struct intel_crtc_state *pipe_config =
4594 to_intel_crtc_state(crtc->base.state);
4595 struct drm_device *dev = crtc->base.dev;
4596 struct drm_plane *primary = crtc->base.primary;
4597 struct drm_plane_state *old_pri_state =
4598 drm_atomic_get_existing_plane_state(old_state, primary);
4599
4600 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4601
4602 crtc->wm.cxsr_allowed = true;
4603
4604 if (pipe_config->update_wm_post && pipe_config->base.active)
4605 intel_update_watermarks(&crtc->base);
4606
4607 if (old_pri_state) {
4608 struct intel_plane_state *primary_state =
4609 to_intel_plane_state(primary->state);
4610 struct intel_plane_state *old_primary_state =
4611 to_intel_plane_state(old_pri_state);
4612
4613 intel_fbc_post_update(crtc);
4614
4615 if (primary_state->visible &&
4616 (needs_modeset(&pipe_config->base) ||
4617 !old_primary_state->visible))
4618 intel_post_enable_primary(&crtc->base);
4619 }
4620 }
4621
4622 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4623 {
4624 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4625 struct drm_device *dev = crtc->base.dev;
4626 struct drm_i915_private *dev_priv = dev->dev_private;
4627 struct intel_crtc_state *pipe_config =
4628 to_intel_crtc_state(crtc->base.state);
4629 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4630 struct drm_plane *primary = crtc->base.primary;
4631 struct drm_plane_state *old_pri_state =
4632 drm_atomic_get_existing_plane_state(old_state, primary);
4633 bool modeset = needs_modeset(&pipe_config->base);
4634
4635 if (old_pri_state) {
4636 struct intel_plane_state *primary_state =
4637 to_intel_plane_state(primary->state);
4638 struct intel_plane_state *old_primary_state =
4639 to_intel_plane_state(old_pri_state);
4640
4641 intel_fbc_pre_update(crtc);
4642
4643 if (old_primary_state->visible &&
4644 (modeset || !primary_state->visible))
4645 intel_pre_disable_primary(&crtc->base);
4646 }
4647
4648 if (pipe_config->disable_cxsr) {
4649 crtc->wm.cxsr_allowed = false;
4650
4651 /*
4652 * Vblank time updates from the shadow to live plane control register
4653 * are blocked if the memory self-refresh mode is active at that
4654 * moment. So to make sure the plane gets truly disabled, disable
4655 * first the self-refresh mode. The self-refresh enable bit in turn
4656 * will be checked/applied by the HW only at the next frame start
4657 * event which is after the vblank start event, so we need to have a
4658 * wait-for-vblank between disabling the plane and the pipe.
4659 */
4660 if (old_crtc_state->base.active) {
4661 intel_set_memory_cxsr(dev_priv, false);
4662 dev_priv->wm.vlv.cxsr = false;
4663 intel_wait_for_vblank(dev, crtc->pipe);
4664 }
4665 }
4666
4667 /*
4668 * IVB workaround: must disable low power watermarks for at least
4669 * one frame before enabling scaling. LP watermarks can be re-enabled
4670 * when scaling is disabled.
4671 *
4672 * WaCxSRDisabledForSpriteScaling:ivb
4673 */
4674 if (pipe_config->disable_lp_wm) {
4675 ilk_disable_lp_wm(dev);
4676 intel_wait_for_vblank(dev, crtc->pipe);
4677 }
4678
4679 /*
4680 * If we're doing a modeset, we're done. No need to do any pre-vblank
4681 * watermark programming here.
4682 */
4683 if (needs_modeset(&pipe_config->base))
4684 return;
4685
4686 /*
4687 * For platforms that support atomic watermarks, program the
4688 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4689 * will be the intermediate values that are safe for both pre- and
4690 * post- vblank; when vblank happens, the 'active' values will be set
4691 * to the final 'target' values and we'll do this again to get the
4692 * optimal watermarks. For gen9+ platforms, the values we program here
4693 * will be the final target values which will get automatically latched
4694 * at vblank time; no further programming will be necessary.
4695 *
4696 * If a platform hasn't been transitioned to atomic watermarks yet,
4697 * we'll continue to update watermarks the old way, if flags tell
4698 * us to.
4699 */
4700 if (dev_priv->display.initial_watermarks != NULL)
4701 dev_priv->display.initial_watermarks(pipe_config);
4702 else if (pipe_config->update_wm_pre)
4703 intel_update_watermarks(&crtc->base);
4704 }
4705
4706 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4707 {
4708 struct drm_device *dev = crtc->dev;
4709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4710 struct drm_plane *p;
4711 int pipe = intel_crtc->pipe;
4712
4713 intel_crtc_dpms_overlay_disable(intel_crtc);
4714
4715 drm_for_each_plane_mask(p, dev, plane_mask)
4716 to_intel_plane(p)->disable_plane(p, crtc);
4717
4718 /*
4719 * FIXME: Once we grow proper nuclear flip support out of this we need
4720 * to compute the mask of flip planes precisely. For the time being
4721 * consider this a flip to a NULL plane.
4722 */
4723 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4724 }
4725
4726 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4727 {
4728 struct drm_device *dev = crtc->dev;
4729 struct drm_i915_private *dev_priv = dev->dev_private;
4730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4731 struct intel_encoder *encoder;
4732 int pipe = intel_crtc->pipe;
4733 struct intel_crtc_state *pipe_config =
4734 to_intel_crtc_state(crtc->state);
4735
4736 if (WARN_ON(intel_crtc->active))
4737 return;
4738
4739 /*
4740 * Sometimes spurious CPU pipe underruns happen during FDI
4741 * training, at least with VGA+HDMI cloning. Suppress them.
4742 *
4743 * On ILK we get an occasional spurious CPU pipe underruns
4744 * between eDP port A enable and vdd enable. Also PCH port
4745 * enable seems to result in the occasional CPU pipe underrun.
4746 *
4747 * Spurious PCH underruns also occur during PCH enabling.
4748 */
4749 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4750 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4751 if (intel_crtc->config->has_pch_encoder)
4752 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4753
4754 if (intel_crtc->config->has_pch_encoder)
4755 intel_prepare_shared_dpll(intel_crtc);
4756
4757 if (intel_crtc->config->has_dp_encoder)
4758 intel_dp_set_m_n(intel_crtc, M1_N1);
4759
4760 intel_set_pipe_timings(intel_crtc);
4761 intel_set_pipe_src_size(intel_crtc);
4762
4763 if (intel_crtc->config->has_pch_encoder) {
4764 intel_cpu_transcoder_set_m_n(intel_crtc,
4765 &intel_crtc->config->fdi_m_n, NULL);
4766 }
4767
4768 ironlake_set_pipeconf(crtc);
4769
4770 intel_crtc->active = true;
4771
4772 for_each_encoder_on_crtc(dev, crtc, encoder)
4773 if (encoder->pre_enable)
4774 encoder->pre_enable(encoder);
4775
4776 if (intel_crtc->config->has_pch_encoder) {
4777 /* Note: FDI PLL enabling _must_ be done before we enable the
4778 * cpu pipes, hence this is separate from all the other fdi/pch
4779 * enabling. */
4780 ironlake_fdi_pll_enable(intel_crtc);
4781 } else {
4782 assert_fdi_tx_disabled(dev_priv, pipe);
4783 assert_fdi_rx_disabled(dev_priv, pipe);
4784 }
4785
4786 ironlake_pfit_enable(intel_crtc);
4787
4788 /*
4789 * On ILK+ LUT must be loaded before the pipe is running but with
4790 * clocks enabled
4791 */
4792 intel_color_load_luts(&pipe_config->base);
4793
4794 if (dev_priv->display.initial_watermarks != NULL)
4795 dev_priv->display.initial_watermarks(intel_crtc->config);
4796 intel_enable_pipe(intel_crtc);
4797
4798 if (intel_crtc->config->has_pch_encoder)
4799 ironlake_pch_enable(crtc);
4800
4801 assert_vblank_disabled(crtc);
4802 drm_crtc_vblank_on(crtc);
4803
4804 for_each_encoder_on_crtc(dev, crtc, encoder)
4805 encoder->enable(encoder);
4806
4807 if (HAS_PCH_CPT(dev))
4808 cpt_verify_modeset(dev, intel_crtc->pipe);
4809
4810 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4811 if (intel_crtc->config->has_pch_encoder)
4812 intel_wait_for_vblank(dev, pipe);
4813 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4814 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4815 }
4816
4817 /* IPS only exists on ULT machines and is tied to pipe A. */
4818 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4819 {
4820 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4821 }
4822
4823 static void haswell_crtc_enable(struct drm_crtc *crtc)
4824 {
4825 struct drm_device *dev = crtc->dev;
4826 struct drm_i915_private *dev_priv = dev->dev_private;
4827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4828 struct intel_encoder *encoder;
4829 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4830 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4831 struct intel_crtc_state *pipe_config =
4832 to_intel_crtc_state(crtc->state);
4833
4834 if (WARN_ON(intel_crtc->active))
4835 return;
4836
4837 if (intel_crtc->config->has_pch_encoder)
4838 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4839 false);
4840
4841 if (intel_crtc->config->shared_dpll)
4842 intel_enable_shared_dpll(intel_crtc);
4843
4844 if (intel_crtc->config->has_dp_encoder)
4845 intel_dp_set_m_n(intel_crtc, M1_N1);
4846
4847 if (!intel_crtc->config->has_dsi_encoder)
4848 intel_set_pipe_timings(intel_crtc);
4849
4850 intel_set_pipe_src_size(intel_crtc);
4851
4852 if (cpu_transcoder != TRANSCODER_EDP &&
4853 !transcoder_is_dsi(cpu_transcoder)) {
4854 I915_WRITE(PIPE_MULT(cpu_transcoder),
4855 intel_crtc->config->pixel_multiplier - 1);
4856 }
4857
4858 if (intel_crtc->config->has_pch_encoder) {
4859 intel_cpu_transcoder_set_m_n(intel_crtc,
4860 &intel_crtc->config->fdi_m_n, NULL);
4861 }
4862
4863 if (!intel_crtc->config->has_dsi_encoder)
4864 haswell_set_pipeconf(crtc);
4865
4866 haswell_set_pipemisc(crtc);
4867
4868 intel_color_set_csc(&pipe_config->base);
4869
4870 intel_crtc->active = true;
4871
4872 if (intel_crtc->config->has_pch_encoder)
4873 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4874 else
4875 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4876
4877 for_each_encoder_on_crtc(dev, crtc, encoder) {
4878 if (encoder->pre_enable)
4879 encoder->pre_enable(encoder);
4880 }
4881
4882 if (intel_crtc->config->has_pch_encoder)
4883 dev_priv->display.fdi_link_train(crtc);
4884
4885 if (!intel_crtc->config->has_dsi_encoder)
4886 intel_ddi_enable_pipe_clock(intel_crtc);
4887
4888 if (INTEL_INFO(dev)->gen >= 9)
4889 skylake_pfit_enable(intel_crtc);
4890 else
4891 ironlake_pfit_enable(intel_crtc);
4892
4893 /*
4894 * On ILK+ LUT must be loaded before the pipe is running but with
4895 * clocks enabled
4896 */
4897 intel_color_load_luts(&pipe_config->base);
4898
4899 intel_ddi_set_pipe_settings(crtc);
4900 if (!intel_crtc->config->has_dsi_encoder)
4901 intel_ddi_enable_transcoder_func(crtc);
4902
4903 if (dev_priv->display.initial_watermarks != NULL)
4904 dev_priv->display.initial_watermarks(pipe_config);
4905 else
4906 intel_update_watermarks(crtc);
4907
4908 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4909 if (!intel_crtc->config->has_dsi_encoder)
4910 intel_enable_pipe(intel_crtc);
4911
4912 if (intel_crtc->config->has_pch_encoder)
4913 lpt_pch_enable(crtc);
4914
4915 if (intel_crtc->config->dp_encoder_is_mst)
4916 intel_ddi_set_vc_payload_alloc(crtc, true);
4917
4918 assert_vblank_disabled(crtc);
4919 drm_crtc_vblank_on(crtc);
4920
4921 for_each_encoder_on_crtc(dev, crtc, encoder) {
4922 encoder->enable(encoder);
4923 intel_opregion_notify_encoder(encoder, true);
4924 }
4925
4926 if (intel_crtc->config->has_pch_encoder) {
4927 intel_wait_for_vblank(dev, pipe);
4928 intel_wait_for_vblank(dev, pipe);
4929 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4930 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4931 true);
4932 }
4933
4934 /* If we change the relative order between pipe/planes enabling, we need
4935 * to change the workaround. */
4936 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4937 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4938 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4939 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4940 }
4941 }
4942
4943 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4944 {
4945 struct drm_device *dev = crtc->base.dev;
4946 struct drm_i915_private *dev_priv = dev->dev_private;
4947 int pipe = crtc->pipe;
4948
4949 /* To avoid upsetting the power well on haswell only disable the pfit if
4950 * it's in use. The hw state code will make sure we get this right. */
4951 if (force || crtc->config->pch_pfit.enabled) {
4952 I915_WRITE(PF_CTL(pipe), 0);
4953 I915_WRITE(PF_WIN_POS(pipe), 0);
4954 I915_WRITE(PF_WIN_SZ(pipe), 0);
4955 }
4956 }
4957
4958 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4959 {
4960 struct drm_device *dev = crtc->dev;
4961 struct drm_i915_private *dev_priv = dev->dev_private;
4962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4963 struct intel_encoder *encoder;
4964 int pipe = intel_crtc->pipe;
4965
4966 /*
4967 * Sometimes spurious CPU pipe underruns happen when the
4968 * pipe is already disabled, but FDI RX/TX is still enabled.
4969 * Happens at least with VGA+HDMI cloning. Suppress them.
4970 */
4971 if (intel_crtc->config->has_pch_encoder) {
4972 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4973 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4974 }
4975
4976 for_each_encoder_on_crtc(dev, crtc, encoder)
4977 encoder->disable(encoder);
4978
4979 drm_crtc_vblank_off(crtc);
4980 assert_vblank_disabled(crtc);
4981
4982 intel_disable_pipe(intel_crtc);
4983
4984 ironlake_pfit_disable(intel_crtc, false);
4985
4986 if (intel_crtc->config->has_pch_encoder)
4987 ironlake_fdi_disable(crtc);
4988
4989 for_each_encoder_on_crtc(dev, crtc, encoder)
4990 if (encoder->post_disable)
4991 encoder->post_disable(encoder);
4992
4993 if (intel_crtc->config->has_pch_encoder) {
4994 ironlake_disable_pch_transcoder(dev_priv, pipe);
4995
4996 if (HAS_PCH_CPT(dev)) {
4997 i915_reg_t reg;
4998 u32 temp;
4999
5000 /* disable TRANS_DP_CTL */
5001 reg = TRANS_DP_CTL(pipe);
5002 temp = I915_READ(reg);
5003 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5004 TRANS_DP_PORT_SEL_MASK);
5005 temp |= TRANS_DP_PORT_SEL_NONE;
5006 I915_WRITE(reg, temp);
5007
5008 /* disable DPLL_SEL */
5009 temp = I915_READ(PCH_DPLL_SEL);
5010 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5011 I915_WRITE(PCH_DPLL_SEL, temp);
5012 }
5013
5014 ironlake_fdi_pll_disable(intel_crtc);
5015 }
5016
5017 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5018 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5019 }
5020
5021 static void haswell_crtc_disable(struct drm_crtc *crtc)
5022 {
5023 struct drm_device *dev = crtc->dev;
5024 struct drm_i915_private *dev_priv = dev->dev_private;
5025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5026 struct intel_encoder *encoder;
5027 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5028
5029 if (intel_crtc->config->has_pch_encoder)
5030 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5031 false);
5032
5033 for_each_encoder_on_crtc(dev, crtc, encoder) {
5034 intel_opregion_notify_encoder(encoder, false);
5035 encoder->disable(encoder);
5036 }
5037
5038 drm_crtc_vblank_off(crtc);
5039 assert_vblank_disabled(crtc);
5040
5041 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5042 if (!intel_crtc->config->has_dsi_encoder)
5043 intel_disable_pipe(intel_crtc);
5044
5045 if (intel_crtc->config->dp_encoder_is_mst)
5046 intel_ddi_set_vc_payload_alloc(crtc, false);
5047
5048 if (!intel_crtc->config->has_dsi_encoder)
5049 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5050
5051 if (INTEL_INFO(dev)->gen >= 9)
5052 skylake_scaler_disable(intel_crtc);
5053 else
5054 ironlake_pfit_disable(intel_crtc, false);
5055
5056 if (!intel_crtc->config->has_dsi_encoder)
5057 intel_ddi_disable_pipe_clock(intel_crtc);
5058
5059 for_each_encoder_on_crtc(dev, crtc, encoder)
5060 if (encoder->post_disable)
5061 encoder->post_disable(encoder);
5062
5063 if (intel_crtc->config->has_pch_encoder) {
5064 lpt_disable_pch_transcoder(dev_priv);
5065 lpt_disable_iclkip(dev_priv);
5066 intel_ddi_fdi_disable(crtc);
5067
5068 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5069 true);
5070 }
5071 }
5072
5073 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5074 {
5075 struct drm_device *dev = crtc->base.dev;
5076 struct drm_i915_private *dev_priv = dev->dev_private;
5077 struct intel_crtc_state *pipe_config = crtc->config;
5078
5079 if (!pipe_config->gmch_pfit.control)
5080 return;
5081
5082 /*
5083 * The panel fitter should only be adjusted whilst the pipe is disabled,
5084 * according to register description and PRM.
5085 */
5086 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5087 assert_pipe_disabled(dev_priv, crtc->pipe);
5088
5089 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5090 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5091
5092 /* Border color in case we don't scale up to the full screen. Black by
5093 * default, change to something else for debugging. */
5094 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5095 }
5096
5097 static enum intel_display_power_domain port_to_power_domain(enum port port)
5098 {
5099 switch (port) {
5100 case PORT_A:
5101 return POWER_DOMAIN_PORT_DDI_A_LANES;
5102 case PORT_B:
5103 return POWER_DOMAIN_PORT_DDI_B_LANES;
5104 case PORT_C:
5105 return POWER_DOMAIN_PORT_DDI_C_LANES;
5106 case PORT_D:
5107 return POWER_DOMAIN_PORT_DDI_D_LANES;
5108 case PORT_E:
5109 return POWER_DOMAIN_PORT_DDI_E_LANES;
5110 default:
5111 MISSING_CASE(port);
5112 return POWER_DOMAIN_PORT_OTHER;
5113 }
5114 }
5115
5116 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5117 {
5118 switch (port) {
5119 case PORT_A:
5120 return POWER_DOMAIN_AUX_A;
5121 case PORT_B:
5122 return POWER_DOMAIN_AUX_B;
5123 case PORT_C:
5124 return POWER_DOMAIN_AUX_C;
5125 case PORT_D:
5126 return POWER_DOMAIN_AUX_D;
5127 case PORT_E:
5128 /* FIXME: Check VBT for actual wiring of PORT E */
5129 return POWER_DOMAIN_AUX_D;
5130 default:
5131 MISSING_CASE(port);
5132 return POWER_DOMAIN_AUX_A;
5133 }
5134 }
5135
5136 enum intel_display_power_domain
5137 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5138 {
5139 struct drm_device *dev = intel_encoder->base.dev;
5140 struct intel_digital_port *intel_dig_port;
5141
5142 switch (intel_encoder->type) {
5143 case INTEL_OUTPUT_UNKNOWN:
5144 /* Only DDI platforms should ever use this output type */
5145 WARN_ON_ONCE(!HAS_DDI(dev));
5146 case INTEL_OUTPUT_DISPLAYPORT:
5147 case INTEL_OUTPUT_HDMI:
5148 case INTEL_OUTPUT_EDP:
5149 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5150 return port_to_power_domain(intel_dig_port->port);
5151 case INTEL_OUTPUT_DP_MST:
5152 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5153 return port_to_power_domain(intel_dig_port->port);
5154 case INTEL_OUTPUT_ANALOG:
5155 return POWER_DOMAIN_PORT_CRT;
5156 case INTEL_OUTPUT_DSI:
5157 return POWER_DOMAIN_PORT_DSI;
5158 default:
5159 return POWER_DOMAIN_PORT_OTHER;
5160 }
5161 }
5162
5163 enum intel_display_power_domain
5164 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5165 {
5166 struct drm_device *dev = intel_encoder->base.dev;
5167 struct intel_digital_port *intel_dig_port;
5168
5169 switch (intel_encoder->type) {
5170 case INTEL_OUTPUT_UNKNOWN:
5171 case INTEL_OUTPUT_HDMI:
5172 /*
5173 * Only DDI platforms should ever use these output types.
5174 * We can get here after the HDMI detect code has already set
5175 * the type of the shared encoder. Since we can't be sure
5176 * what's the status of the given connectors, play safe and
5177 * run the DP detection too.
5178 */
5179 WARN_ON_ONCE(!HAS_DDI(dev));
5180 case INTEL_OUTPUT_DISPLAYPORT:
5181 case INTEL_OUTPUT_EDP:
5182 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5183 return port_to_aux_power_domain(intel_dig_port->port);
5184 case INTEL_OUTPUT_DP_MST:
5185 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5186 return port_to_aux_power_domain(intel_dig_port->port);
5187 default:
5188 MISSING_CASE(intel_encoder->type);
5189 return POWER_DOMAIN_AUX_A;
5190 }
5191 }
5192
5193 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5194 struct intel_crtc_state *crtc_state)
5195 {
5196 struct drm_device *dev = crtc->dev;
5197 struct drm_encoder *encoder;
5198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5199 enum pipe pipe = intel_crtc->pipe;
5200 unsigned long mask;
5201 enum transcoder transcoder = crtc_state->cpu_transcoder;
5202
5203 if (!crtc_state->base.active)
5204 return 0;
5205
5206 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5207 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5208 if (crtc_state->pch_pfit.enabled ||
5209 crtc_state->pch_pfit.force_thru)
5210 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5211
5212 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5213 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5214
5215 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5216 }
5217
5218 if (crtc_state->shared_dpll)
5219 mask |= BIT(POWER_DOMAIN_PLLS);
5220
5221 return mask;
5222 }
5223
5224 static unsigned long
5225 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5226 struct intel_crtc_state *crtc_state)
5227 {
5228 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5230 enum intel_display_power_domain domain;
5231 unsigned long domains, new_domains, old_domains;
5232
5233 old_domains = intel_crtc->enabled_power_domains;
5234 intel_crtc->enabled_power_domains = new_domains =
5235 get_crtc_power_domains(crtc, crtc_state);
5236
5237 domains = new_domains & ~old_domains;
5238
5239 for_each_power_domain(domain, domains)
5240 intel_display_power_get(dev_priv, domain);
5241
5242 return old_domains & ~new_domains;
5243 }
5244
5245 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5246 unsigned long domains)
5247 {
5248 enum intel_display_power_domain domain;
5249
5250 for_each_power_domain(domain, domains)
5251 intel_display_power_put(dev_priv, domain);
5252 }
5253
5254 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5255 {
5256 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5257
5258 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5259 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5260 return max_cdclk_freq;
5261 else if (IS_CHERRYVIEW(dev_priv))
5262 return max_cdclk_freq*95/100;
5263 else if (INTEL_INFO(dev_priv)->gen < 4)
5264 return 2*max_cdclk_freq*90/100;
5265 else
5266 return max_cdclk_freq*90/100;
5267 }
5268
5269 static int skl_calc_cdclk(int max_pixclk, int vco);
5270
5271 static void intel_update_max_cdclk(struct drm_device *dev)
5272 {
5273 struct drm_i915_private *dev_priv = dev->dev_private;
5274
5275 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5276 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5277 int max_cdclk, vco;
5278
5279 vco = dev_priv->skl_preferred_vco_freq;
5280 WARN_ON(vco != 8100000 && vco != 8640000);
5281
5282 /*
5283 * Use the lower (vco 8640) cdclk values as a
5284 * first guess. skl_calc_cdclk() will correct it
5285 * if the preferred vco is 8100 instead.
5286 */
5287 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5288 max_cdclk = 617143;
5289 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5290 max_cdclk = 540000;
5291 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5292 max_cdclk = 432000;
5293 else
5294 max_cdclk = 308571;
5295
5296 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5297 } else if (IS_BROXTON(dev)) {
5298 dev_priv->max_cdclk_freq = 624000;
5299 } else if (IS_BROADWELL(dev)) {
5300 /*
5301 * FIXME with extra cooling we can allow
5302 * 540 MHz for ULX and 675 Mhz for ULT.
5303 * How can we know if extra cooling is
5304 * available? PCI ID, VTB, something else?
5305 */
5306 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5307 dev_priv->max_cdclk_freq = 450000;
5308 else if (IS_BDW_ULX(dev))
5309 dev_priv->max_cdclk_freq = 450000;
5310 else if (IS_BDW_ULT(dev))
5311 dev_priv->max_cdclk_freq = 540000;
5312 else
5313 dev_priv->max_cdclk_freq = 675000;
5314 } else if (IS_CHERRYVIEW(dev)) {
5315 dev_priv->max_cdclk_freq = 320000;
5316 } else if (IS_VALLEYVIEW(dev)) {
5317 dev_priv->max_cdclk_freq = 400000;
5318 } else {
5319 /* otherwise assume cdclk is fixed */
5320 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5321 }
5322
5323 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5324
5325 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5326 dev_priv->max_cdclk_freq);
5327
5328 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5329 dev_priv->max_dotclk_freq);
5330 }
5331
5332 static void intel_update_cdclk(struct drm_device *dev)
5333 {
5334 struct drm_i915_private *dev_priv = dev->dev_private;
5335
5336 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5337
5338 if (INTEL_GEN(dev_priv) >= 9)
5339 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5340 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5341 dev_priv->cdclk_pll.ref);
5342 else
5343 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5344 dev_priv->cdclk_freq);
5345
5346 /*
5347 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5348 * Programmng [sic] note: bit[9:2] should be programmed to the number
5349 * of cdclk that generates 4MHz reference clock freq which is used to
5350 * generate GMBus clock. This will vary with the cdclk freq.
5351 */
5352 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5353 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5354 }
5355
5356 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5357 static int skl_cdclk_decimal(int cdclk)
5358 {
5359 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5360 }
5361
5362 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5363 {
5364 int ratio;
5365
5366 if (cdclk == dev_priv->cdclk_pll.ref)
5367 return 0;
5368
5369 switch (cdclk) {
5370 default:
5371 MISSING_CASE(cdclk);
5372 case 144000:
5373 case 288000:
5374 case 384000:
5375 case 576000:
5376 ratio = 60;
5377 break;
5378 case 624000:
5379 ratio = 65;
5380 break;
5381 }
5382
5383 return dev_priv->cdclk_pll.ref * ratio;
5384 }
5385
5386 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5387 {
5388 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5389
5390 /* Timeout 200us */
5391 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
5392 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5393
5394 dev_priv->cdclk_pll.vco = 0;
5395 }
5396
5397 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5398 {
5399 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5400 u32 val;
5401
5402 val = I915_READ(BXT_DE_PLL_CTL);
5403 val &= ~BXT_DE_PLL_RATIO_MASK;
5404 val |= BXT_DE_PLL_RATIO(ratio);
5405 I915_WRITE(BXT_DE_PLL_CTL, val);
5406
5407 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5408
5409 /* Timeout 200us */
5410 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
5411 DRM_ERROR("timeout waiting for DE PLL lock\n");
5412
5413 dev_priv->cdclk_pll.vco = vco;
5414 }
5415
5416 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5417 {
5418 u32 val, divider;
5419 int vco, ret;
5420
5421 vco = bxt_de_pll_vco(dev_priv, cdclk);
5422
5423 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5424
5425 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5426 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5427 case 8:
5428 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5429 break;
5430 case 4:
5431 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5432 break;
5433 case 3:
5434 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5435 break;
5436 case 2:
5437 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5438 break;
5439 default:
5440 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5441 WARN_ON(vco != 0);
5442
5443 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5444 break;
5445 }
5446
5447 /* Inform power controller of upcoming frequency change */
5448 mutex_lock(&dev_priv->rps.hw_lock);
5449 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5450 0x80000000);
5451 mutex_unlock(&dev_priv->rps.hw_lock);
5452
5453 if (ret) {
5454 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5455 ret, cdclk);
5456 return;
5457 }
5458
5459 if (dev_priv->cdclk_pll.vco != 0 &&
5460 dev_priv->cdclk_pll.vco != vco)
5461 bxt_de_pll_disable(dev_priv);
5462
5463 if (dev_priv->cdclk_pll.vco != vco)
5464 bxt_de_pll_enable(dev_priv, vco);
5465
5466 val = divider | skl_cdclk_decimal(cdclk);
5467 /*
5468 * FIXME if only the cd2x divider needs changing, it could be done
5469 * without shutting off the pipe (if only one pipe is active).
5470 */
5471 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5472 /*
5473 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5474 * enable otherwise.
5475 */
5476 if (cdclk >= 500000)
5477 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5478 I915_WRITE(CDCLK_CTL, val);
5479
5480 mutex_lock(&dev_priv->rps.hw_lock);
5481 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5482 DIV_ROUND_UP(cdclk, 25000));
5483 mutex_unlock(&dev_priv->rps.hw_lock);
5484
5485 if (ret) {
5486 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5487 ret, cdclk);
5488 return;
5489 }
5490
5491 intel_update_cdclk(dev_priv->dev);
5492 }
5493
5494 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5495 {
5496 intel_update_cdclk(dev_priv->dev);
5497
5498 if (dev_priv->cdclk_pll.vco != 0)
5499 return;
5500
5501 /*
5502 * FIXME:
5503 * - The initial CDCLK needs to be read from VBT.
5504 * Need to make this change after VBT has changes for BXT.
5505 */
5506 broxton_set_cdclk(dev_priv, broxton_calc_cdclk(0));
5507 }
5508
5509 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5510 {
5511 broxton_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
5512 }
5513
5514 static int skl_calc_cdclk(int max_pixclk, int vco)
5515 {
5516 if (vco == 8640000) {
5517 if (max_pixclk > 540000)
5518 return 617143;
5519 else if (max_pixclk > 432000)
5520 return 540000;
5521 else if (max_pixclk > 308571)
5522 return 432000;
5523 else
5524 return 308571;
5525 } else {
5526 if (max_pixclk > 540000)
5527 return 675000;
5528 else if (max_pixclk > 450000)
5529 return 540000;
5530 else if (max_pixclk > 337500)
5531 return 450000;
5532 else
5533 return 337500;
5534 }
5535 }
5536
5537 static void
5538 skl_dpll0_update(struct drm_i915_private *dev_priv)
5539 {
5540 u32 val;
5541
5542 dev_priv->cdclk_pll.ref = 24000;
5543 dev_priv->cdclk_pll.vco = 0;
5544
5545 val = I915_READ(LCPLL1_CTL);
5546 if ((val & LCPLL_PLL_ENABLE) == 0)
5547 return;
5548
5549 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
5550 return;
5551
5552 val = I915_READ(DPLL_CTRL1);
5553
5554 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5555 DPLL_CTRL1_SSC(SKL_DPLL0) |
5556 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5557 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
5558 return;
5559
5560 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5561 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5562 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5563 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5564 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5565 dev_priv->cdclk_pll.vco = 8100000;
5566 break;
5567 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5568 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5569 dev_priv->cdclk_pll.vco = 8640000;
5570 break;
5571 default:
5572 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5573 break;
5574 }
5575 }
5576
5577 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5578 {
5579 bool changed = dev_priv->skl_preferred_vco_freq != vco;
5580
5581 dev_priv->skl_preferred_vco_freq = vco;
5582
5583 if (changed)
5584 intel_update_max_cdclk(dev_priv->dev);
5585 }
5586
5587 static void
5588 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5589 {
5590 int min_cdclk = skl_calc_cdclk(0, vco);
5591 u32 val;
5592
5593 WARN_ON(vco != 8100000 && vco != 8640000);
5594
5595 /* select the minimum CDCLK before enabling DPLL 0 */
5596 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5597 I915_WRITE(CDCLK_CTL, val);
5598 POSTING_READ(CDCLK_CTL);
5599
5600 /*
5601 * We always enable DPLL0 with the lowest link rate possible, but still
5602 * taking into account the VCO required to operate the eDP panel at the
5603 * desired frequency. The usual DP link rates operate with a VCO of
5604 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5605 * The modeset code is responsible for the selection of the exact link
5606 * rate later on, with the constraint of choosing a frequency that
5607 * works with vco.
5608 */
5609 val = I915_READ(DPLL_CTRL1);
5610
5611 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5612 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5613 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5614 if (vco == 8640000)
5615 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5616 SKL_DPLL0);
5617 else
5618 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5619 SKL_DPLL0);
5620
5621 I915_WRITE(DPLL_CTRL1, val);
5622 POSTING_READ(DPLL_CTRL1);
5623
5624 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5625
5626 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5627 DRM_ERROR("DPLL0 not locked\n");
5628
5629 dev_priv->cdclk_pll.vco = vco;
5630
5631 /* We'll want to keep using the current vco from now on. */
5632 skl_set_preferred_cdclk_vco(dev_priv, vco);
5633 }
5634
5635 static void
5636 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5637 {
5638 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5639 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5640 DRM_ERROR("Couldn't disable DPLL0\n");
5641
5642 dev_priv->cdclk_pll.vco = 0;
5643 }
5644
5645 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5646 {
5647 int ret;
5648 u32 val;
5649
5650 /* inform PCU we want to change CDCLK */
5651 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5652 mutex_lock(&dev_priv->rps.hw_lock);
5653 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5654 mutex_unlock(&dev_priv->rps.hw_lock);
5655
5656 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5657 }
5658
5659 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5660 {
5661 unsigned int i;
5662
5663 for (i = 0; i < 15; i++) {
5664 if (skl_cdclk_pcu_ready(dev_priv))
5665 return true;
5666 udelay(10);
5667 }
5668
5669 return false;
5670 }
5671
5672 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5673 {
5674 struct drm_device *dev = dev_priv->dev;
5675 u32 freq_select, pcu_ack;
5676
5677 WARN_ON((cdclk == 24000) != (vco == 0));
5678
5679 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5680
5681 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5682 DRM_ERROR("failed to inform PCU about cdclk change\n");
5683 return;
5684 }
5685
5686 /* set CDCLK_CTL */
5687 switch (cdclk) {
5688 case 450000:
5689 case 432000:
5690 freq_select = CDCLK_FREQ_450_432;
5691 pcu_ack = 1;
5692 break;
5693 case 540000:
5694 freq_select = CDCLK_FREQ_540;
5695 pcu_ack = 2;
5696 break;
5697 case 308571:
5698 case 337500:
5699 default:
5700 freq_select = CDCLK_FREQ_337_308;
5701 pcu_ack = 0;
5702 break;
5703 case 617143:
5704 case 675000:
5705 freq_select = CDCLK_FREQ_675_617;
5706 pcu_ack = 3;
5707 break;
5708 }
5709
5710 if (dev_priv->cdclk_pll.vco != 0 &&
5711 dev_priv->cdclk_pll.vco != vco)
5712 skl_dpll0_disable(dev_priv);
5713
5714 if (dev_priv->cdclk_pll.vco != vco)
5715 skl_dpll0_enable(dev_priv, vco);
5716
5717 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5718 POSTING_READ(CDCLK_CTL);
5719
5720 /* inform PCU of the change */
5721 mutex_lock(&dev_priv->rps.hw_lock);
5722 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5723 mutex_unlock(&dev_priv->rps.hw_lock);
5724
5725 intel_update_cdclk(dev);
5726 }
5727
5728 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5729
5730 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5731 {
5732 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5733 }
5734
5735 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5736 {
5737 int cdclk, vco;
5738
5739 skl_sanitize_cdclk(dev_priv);
5740
5741 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
5742 /*
5743 * Use the current vco as our initial
5744 * guess as to what the preferred vco is.
5745 */
5746 if (dev_priv->skl_preferred_vco_freq == 0)
5747 skl_set_preferred_cdclk_vco(dev_priv,
5748 dev_priv->cdclk_pll.vco);
5749 return;
5750 }
5751
5752 vco = dev_priv->skl_preferred_vco_freq;
5753 if (vco == 0)
5754 vco = 8100000;
5755 cdclk = skl_calc_cdclk(0, vco);
5756
5757 skl_set_cdclk(dev_priv, cdclk, vco);
5758 }
5759
5760 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5761 {
5762 uint32_t cdctl, expected;
5763
5764 /*
5765 * check if the pre-os intialized the display
5766 * There is SWF18 scratchpad register defined which is set by the
5767 * pre-os which can be used by the OS drivers to check the status
5768 */
5769 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5770 goto sanitize;
5771
5772 intel_update_cdclk(dev_priv->dev);
5773 /* Is PLL enabled and locked ? */
5774 if (dev_priv->cdclk_pll.vco == 0 ||
5775 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5776 goto sanitize;
5777
5778 /* DPLL okay; verify the cdclock
5779 *
5780 * Noticed in some instances that the freq selection is correct but
5781 * decimal part is programmed wrong from BIOS where pre-os does not
5782 * enable display. Verify the same as well.
5783 */
5784 cdctl = I915_READ(CDCLK_CTL);
5785 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5786 skl_cdclk_decimal(dev_priv->cdclk_freq);
5787 if (cdctl == expected)
5788 /* All well; nothing to sanitize */
5789 return;
5790
5791 sanitize:
5792 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5793
5794 /* force cdclk programming */
5795 dev_priv->cdclk_freq = 0;
5796 /* force full PLL disable + enable */
5797 dev_priv->cdclk_pll.vco = -1;
5798 }
5799
5800 /* Adjust CDclk dividers to allow high res or save power if possible */
5801 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5802 {
5803 struct drm_i915_private *dev_priv = dev->dev_private;
5804 u32 val, cmd;
5805
5806 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5807 != dev_priv->cdclk_freq);
5808
5809 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5810 cmd = 2;
5811 else if (cdclk == 266667)
5812 cmd = 1;
5813 else
5814 cmd = 0;
5815
5816 mutex_lock(&dev_priv->rps.hw_lock);
5817 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5818 val &= ~DSPFREQGUAR_MASK;
5819 val |= (cmd << DSPFREQGUAR_SHIFT);
5820 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5821 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5822 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5823 50)) {
5824 DRM_ERROR("timed out waiting for CDclk change\n");
5825 }
5826 mutex_unlock(&dev_priv->rps.hw_lock);
5827
5828 mutex_lock(&dev_priv->sb_lock);
5829
5830 if (cdclk == 400000) {
5831 u32 divider;
5832
5833 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5834
5835 /* adjust cdclk divider */
5836 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5837 val &= ~CCK_FREQUENCY_VALUES;
5838 val |= divider;
5839 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5840
5841 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5842 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5843 50))
5844 DRM_ERROR("timed out waiting for CDclk change\n");
5845 }
5846
5847 /* adjust self-refresh exit latency value */
5848 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5849 val &= ~0x7f;
5850
5851 /*
5852 * For high bandwidth configs, we set a higher latency in the bunit
5853 * so that the core display fetch happens in time to avoid underruns.
5854 */
5855 if (cdclk == 400000)
5856 val |= 4500 / 250; /* 4.5 usec */
5857 else
5858 val |= 3000 / 250; /* 3.0 usec */
5859 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5860
5861 mutex_unlock(&dev_priv->sb_lock);
5862
5863 intel_update_cdclk(dev);
5864 }
5865
5866 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5867 {
5868 struct drm_i915_private *dev_priv = dev->dev_private;
5869 u32 val, cmd;
5870
5871 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5872 != dev_priv->cdclk_freq);
5873
5874 switch (cdclk) {
5875 case 333333:
5876 case 320000:
5877 case 266667:
5878 case 200000:
5879 break;
5880 default:
5881 MISSING_CASE(cdclk);
5882 return;
5883 }
5884
5885 /*
5886 * Specs are full of misinformation, but testing on actual
5887 * hardware has shown that we just need to write the desired
5888 * CCK divider into the Punit register.
5889 */
5890 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5891
5892 mutex_lock(&dev_priv->rps.hw_lock);
5893 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5894 val &= ~DSPFREQGUAR_MASK_CHV;
5895 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5896 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5897 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5898 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5899 50)) {
5900 DRM_ERROR("timed out waiting for CDclk change\n");
5901 }
5902 mutex_unlock(&dev_priv->rps.hw_lock);
5903
5904 intel_update_cdclk(dev);
5905 }
5906
5907 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5908 int max_pixclk)
5909 {
5910 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5911 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5912
5913 /*
5914 * Really only a few cases to deal with, as only 4 CDclks are supported:
5915 * 200MHz
5916 * 267MHz
5917 * 320/333MHz (depends on HPLL freq)
5918 * 400MHz (VLV only)
5919 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5920 * of the lower bin and adjust if needed.
5921 *
5922 * We seem to get an unstable or solid color picture at 200MHz.
5923 * Not sure what's wrong. For now use 200MHz only when all pipes
5924 * are off.
5925 */
5926 if (!IS_CHERRYVIEW(dev_priv) &&
5927 max_pixclk > freq_320*limit/100)
5928 return 400000;
5929 else if (max_pixclk > 266667*limit/100)
5930 return freq_320;
5931 else if (max_pixclk > 0)
5932 return 266667;
5933 else
5934 return 200000;
5935 }
5936
5937 static int broxton_calc_cdclk(int max_pixclk)
5938 {
5939 if (max_pixclk > 576000)
5940 return 624000;
5941 else if (max_pixclk > 384000)
5942 return 576000;
5943 else if (max_pixclk > 288000)
5944 return 384000;
5945 else if (max_pixclk > 144000)
5946 return 288000;
5947 else
5948 return 144000;
5949 }
5950
5951 /* Compute the max pixel clock for new configuration. */
5952 static int intel_mode_max_pixclk(struct drm_device *dev,
5953 struct drm_atomic_state *state)
5954 {
5955 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5956 struct drm_i915_private *dev_priv = dev->dev_private;
5957 struct drm_crtc *crtc;
5958 struct drm_crtc_state *crtc_state;
5959 unsigned max_pixclk = 0, i;
5960 enum pipe pipe;
5961
5962 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5963 sizeof(intel_state->min_pixclk));
5964
5965 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5966 int pixclk = 0;
5967
5968 if (crtc_state->enable)
5969 pixclk = crtc_state->adjusted_mode.crtc_clock;
5970
5971 intel_state->min_pixclk[i] = pixclk;
5972 }
5973
5974 for_each_pipe(dev_priv, pipe)
5975 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5976
5977 return max_pixclk;
5978 }
5979
5980 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5981 {
5982 struct drm_device *dev = state->dev;
5983 struct drm_i915_private *dev_priv = dev->dev_private;
5984 int max_pixclk = intel_mode_max_pixclk(dev, state);
5985 struct intel_atomic_state *intel_state =
5986 to_intel_atomic_state(state);
5987
5988 intel_state->cdclk = intel_state->dev_cdclk =
5989 valleyview_calc_cdclk(dev_priv, max_pixclk);
5990
5991 if (!intel_state->active_crtcs)
5992 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5993
5994 return 0;
5995 }
5996
5997 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5998 {
5999 int max_pixclk = ilk_max_pixel_rate(state);
6000 struct intel_atomic_state *intel_state =
6001 to_intel_atomic_state(state);
6002
6003 intel_state->cdclk = intel_state->dev_cdclk =
6004 broxton_calc_cdclk(max_pixclk);
6005
6006 if (!intel_state->active_crtcs)
6007 intel_state->dev_cdclk = broxton_calc_cdclk(0);
6008
6009 return 0;
6010 }
6011
6012 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6013 {
6014 unsigned int credits, default_credits;
6015
6016 if (IS_CHERRYVIEW(dev_priv))
6017 default_credits = PFI_CREDIT(12);
6018 else
6019 default_credits = PFI_CREDIT(8);
6020
6021 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6022 /* CHV suggested value is 31 or 63 */
6023 if (IS_CHERRYVIEW(dev_priv))
6024 credits = PFI_CREDIT_63;
6025 else
6026 credits = PFI_CREDIT(15);
6027 } else {
6028 credits = default_credits;
6029 }
6030
6031 /*
6032 * WA - write default credits before re-programming
6033 * FIXME: should we also set the resend bit here?
6034 */
6035 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6036 default_credits);
6037
6038 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6039 credits | PFI_CREDIT_RESEND);
6040
6041 /*
6042 * FIXME is this guaranteed to clear
6043 * immediately or should we poll for it?
6044 */
6045 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6046 }
6047
6048 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6049 {
6050 struct drm_device *dev = old_state->dev;
6051 struct drm_i915_private *dev_priv = dev->dev_private;
6052 struct intel_atomic_state *old_intel_state =
6053 to_intel_atomic_state(old_state);
6054 unsigned req_cdclk = old_intel_state->dev_cdclk;
6055
6056 /*
6057 * FIXME: We can end up here with all power domains off, yet
6058 * with a CDCLK frequency other than the minimum. To account
6059 * for this take the PIPE-A power domain, which covers the HW
6060 * blocks needed for the following programming. This can be
6061 * removed once it's guaranteed that we get here either with
6062 * the minimum CDCLK set, or the required power domains
6063 * enabled.
6064 */
6065 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6066
6067 if (IS_CHERRYVIEW(dev))
6068 cherryview_set_cdclk(dev, req_cdclk);
6069 else
6070 valleyview_set_cdclk(dev, req_cdclk);
6071
6072 vlv_program_pfi_credits(dev_priv);
6073
6074 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6075 }
6076
6077 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6078 {
6079 struct drm_device *dev = crtc->dev;
6080 struct drm_i915_private *dev_priv = to_i915(dev);
6081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6082 struct intel_encoder *encoder;
6083 struct intel_crtc_state *pipe_config =
6084 to_intel_crtc_state(crtc->state);
6085 int pipe = intel_crtc->pipe;
6086
6087 if (WARN_ON(intel_crtc->active))
6088 return;
6089
6090 if (intel_crtc->config->has_dp_encoder)
6091 intel_dp_set_m_n(intel_crtc, M1_N1);
6092
6093 intel_set_pipe_timings(intel_crtc);
6094 intel_set_pipe_src_size(intel_crtc);
6095
6096 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098
6099 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6100 I915_WRITE(CHV_CANVAS(pipe), 0);
6101 }
6102
6103 i9xx_set_pipeconf(intel_crtc);
6104
6105 intel_crtc->active = true;
6106
6107 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6108
6109 for_each_encoder_on_crtc(dev, crtc, encoder)
6110 if (encoder->pre_pll_enable)
6111 encoder->pre_pll_enable(encoder);
6112
6113 if (IS_CHERRYVIEW(dev)) {
6114 chv_prepare_pll(intel_crtc, intel_crtc->config);
6115 chv_enable_pll(intel_crtc, intel_crtc->config);
6116 } else {
6117 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6118 vlv_enable_pll(intel_crtc, intel_crtc->config);
6119 }
6120
6121 for_each_encoder_on_crtc(dev, crtc, encoder)
6122 if (encoder->pre_enable)
6123 encoder->pre_enable(encoder);
6124
6125 i9xx_pfit_enable(intel_crtc);
6126
6127 intel_color_load_luts(&pipe_config->base);
6128
6129 intel_update_watermarks(crtc);
6130 intel_enable_pipe(intel_crtc);
6131
6132 assert_vblank_disabled(crtc);
6133 drm_crtc_vblank_on(crtc);
6134
6135 for_each_encoder_on_crtc(dev, crtc, encoder)
6136 encoder->enable(encoder);
6137 }
6138
6139 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6140 {
6141 struct drm_device *dev = crtc->base.dev;
6142 struct drm_i915_private *dev_priv = dev->dev_private;
6143
6144 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6145 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6146 }
6147
6148 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6149 {
6150 struct drm_device *dev = crtc->dev;
6151 struct drm_i915_private *dev_priv = to_i915(dev);
6152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6153 struct intel_encoder *encoder;
6154 struct intel_crtc_state *pipe_config =
6155 to_intel_crtc_state(crtc->state);
6156 enum pipe pipe = intel_crtc->pipe;
6157
6158 if (WARN_ON(intel_crtc->active))
6159 return;
6160
6161 i9xx_set_pll_dividers(intel_crtc);
6162
6163 if (intel_crtc->config->has_dp_encoder)
6164 intel_dp_set_m_n(intel_crtc, M1_N1);
6165
6166 intel_set_pipe_timings(intel_crtc);
6167 intel_set_pipe_src_size(intel_crtc);
6168
6169 i9xx_set_pipeconf(intel_crtc);
6170
6171 intel_crtc->active = true;
6172
6173 if (!IS_GEN2(dev))
6174 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6175
6176 for_each_encoder_on_crtc(dev, crtc, encoder)
6177 if (encoder->pre_enable)
6178 encoder->pre_enable(encoder);
6179
6180 i9xx_enable_pll(intel_crtc);
6181
6182 i9xx_pfit_enable(intel_crtc);
6183
6184 intel_color_load_luts(&pipe_config->base);
6185
6186 intel_update_watermarks(crtc);
6187 intel_enable_pipe(intel_crtc);
6188
6189 assert_vblank_disabled(crtc);
6190 drm_crtc_vblank_on(crtc);
6191
6192 for_each_encoder_on_crtc(dev, crtc, encoder)
6193 encoder->enable(encoder);
6194 }
6195
6196 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6197 {
6198 struct drm_device *dev = crtc->base.dev;
6199 struct drm_i915_private *dev_priv = dev->dev_private;
6200
6201 if (!crtc->config->gmch_pfit.control)
6202 return;
6203
6204 assert_pipe_disabled(dev_priv, crtc->pipe);
6205
6206 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6207 I915_READ(PFIT_CONTROL));
6208 I915_WRITE(PFIT_CONTROL, 0);
6209 }
6210
6211 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6212 {
6213 struct drm_device *dev = crtc->dev;
6214 struct drm_i915_private *dev_priv = dev->dev_private;
6215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6216 struct intel_encoder *encoder;
6217 int pipe = intel_crtc->pipe;
6218
6219 /*
6220 * On gen2 planes are double buffered but the pipe isn't, so we must
6221 * wait for planes to fully turn off before disabling the pipe.
6222 */
6223 if (IS_GEN2(dev))
6224 intel_wait_for_vblank(dev, pipe);
6225
6226 for_each_encoder_on_crtc(dev, crtc, encoder)
6227 encoder->disable(encoder);
6228
6229 drm_crtc_vblank_off(crtc);
6230 assert_vblank_disabled(crtc);
6231
6232 intel_disable_pipe(intel_crtc);
6233
6234 i9xx_pfit_disable(intel_crtc);
6235
6236 for_each_encoder_on_crtc(dev, crtc, encoder)
6237 if (encoder->post_disable)
6238 encoder->post_disable(encoder);
6239
6240 if (!intel_crtc->config->has_dsi_encoder) {
6241 if (IS_CHERRYVIEW(dev))
6242 chv_disable_pll(dev_priv, pipe);
6243 else if (IS_VALLEYVIEW(dev))
6244 vlv_disable_pll(dev_priv, pipe);
6245 else
6246 i9xx_disable_pll(intel_crtc);
6247 }
6248
6249 for_each_encoder_on_crtc(dev, crtc, encoder)
6250 if (encoder->post_pll_disable)
6251 encoder->post_pll_disable(encoder);
6252
6253 if (!IS_GEN2(dev))
6254 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6255 }
6256
6257 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6258 {
6259 struct intel_encoder *encoder;
6260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6261 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6262 enum intel_display_power_domain domain;
6263 unsigned long domains;
6264
6265 if (!intel_crtc->active)
6266 return;
6267
6268 if (to_intel_plane_state(crtc->primary->state)->visible) {
6269 WARN_ON(intel_crtc->flip_work);
6270
6271 intel_pre_disable_primary_noatomic(crtc);
6272
6273 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6274 to_intel_plane_state(crtc->primary->state)->visible = false;
6275 }
6276
6277 dev_priv->display.crtc_disable(crtc);
6278
6279 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6280 crtc->base.id);
6281
6282 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6283 crtc->state->active = false;
6284 intel_crtc->active = false;
6285 crtc->enabled = false;
6286 crtc->state->connector_mask = 0;
6287 crtc->state->encoder_mask = 0;
6288
6289 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6290 encoder->base.crtc = NULL;
6291
6292 intel_fbc_disable(intel_crtc);
6293 intel_update_watermarks(crtc);
6294 intel_disable_shared_dpll(intel_crtc);
6295
6296 domains = intel_crtc->enabled_power_domains;
6297 for_each_power_domain(domain, domains)
6298 intel_display_power_put(dev_priv, domain);
6299 intel_crtc->enabled_power_domains = 0;
6300
6301 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6302 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6303 }
6304
6305 /*
6306 * turn all crtc's off, but do not adjust state
6307 * This has to be paired with a call to intel_modeset_setup_hw_state.
6308 */
6309 int intel_display_suspend(struct drm_device *dev)
6310 {
6311 struct drm_i915_private *dev_priv = to_i915(dev);
6312 struct drm_atomic_state *state;
6313 int ret;
6314
6315 state = drm_atomic_helper_suspend(dev);
6316 ret = PTR_ERR_OR_ZERO(state);
6317 if (ret)
6318 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6319 else
6320 dev_priv->modeset_restore_state = state;
6321 return ret;
6322 }
6323
6324 void intel_encoder_destroy(struct drm_encoder *encoder)
6325 {
6326 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6327
6328 drm_encoder_cleanup(encoder);
6329 kfree(intel_encoder);
6330 }
6331
6332 /* Cross check the actual hw state with our own modeset state tracking (and it's
6333 * internal consistency). */
6334 static void intel_connector_verify_state(struct intel_connector *connector)
6335 {
6336 struct drm_crtc *crtc = connector->base.state->crtc;
6337
6338 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6339 connector->base.base.id,
6340 connector->base.name);
6341
6342 if (connector->get_hw_state(connector)) {
6343 struct intel_encoder *encoder = connector->encoder;
6344 struct drm_connector_state *conn_state = connector->base.state;
6345
6346 I915_STATE_WARN(!crtc,
6347 "connector enabled without attached crtc\n");
6348
6349 if (!crtc)
6350 return;
6351
6352 I915_STATE_WARN(!crtc->state->active,
6353 "connector is active, but attached crtc isn't\n");
6354
6355 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6356 return;
6357
6358 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6359 "atomic encoder doesn't match attached encoder\n");
6360
6361 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6362 "attached encoder crtc differs from connector crtc\n");
6363 } else {
6364 I915_STATE_WARN(crtc && crtc->state->active,
6365 "attached crtc is active, but connector isn't\n");
6366 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6367 "best encoder set without crtc!\n");
6368 }
6369 }
6370
6371 int intel_connector_init(struct intel_connector *connector)
6372 {
6373 drm_atomic_helper_connector_reset(&connector->base);
6374
6375 if (!connector->base.state)
6376 return -ENOMEM;
6377
6378 return 0;
6379 }
6380
6381 struct intel_connector *intel_connector_alloc(void)
6382 {
6383 struct intel_connector *connector;
6384
6385 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6386 if (!connector)
6387 return NULL;
6388
6389 if (intel_connector_init(connector) < 0) {
6390 kfree(connector);
6391 return NULL;
6392 }
6393
6394 return connector;
6395 }
6396
6397 /* Simple connector->get_hw_state implementation for encoders that support only
6398 * one connector and no cloning and hence the encoder state determines the state
6399 * of the connector. */
6400 bool intel_connector_get_hw_state(struct intel_connector *connector)
6401 {
6402 enum pipe pipe = 0;
6403 struct intel_encoder *encoder = connector->encoder;
6404
6405 return encoder->get_hw_state(encoder, &pipe);
6406 }
6407
6408 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6409 {
6410 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6411 return crtc_state->fdi_lanes;
6412
6413 return 0;
6414 }
6415
6416 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6417 struct intel_crtc_state *pipe_config)
6418 {
6419 struct drm_atomic_state *state = pipe_config->base.state;
6420 struct intel_crtc *other_crtc;
6421 struct intel_crtc_state *other_crtc_state;
6422
6423 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6424 pipe_name(pipe), pipe_config->fdi_lanes);
6425 if (pipe_config->fdi_lanes > 4) {
6426 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6427 pipe_name(pipe), pipe_config->fdi_lanes);
6428 return -EINVAL;
6429 }
6430
6431 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6432 if (pipe_config->fdi_lanes > 2) {
6433 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6434 pipe_config->fdi_lanes);
6435 return -EINVAL;
6436 } else {
6437 return 0;
6438 }
6439 }
6440
6441 if (INTEL_INFO(dev)->num_pipes == 2)
6442 return 0;
6443
6444 /* Ivybridge 3 pipe is really complicated */
6445 switch (pipe) {
6446 case PIPE_A:
6447 return 0;
6448 case PIPE_B:
6449 if (pipe_config->fdi_lanes <= 2)
6450 return 0;
6451
6452 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6453 other_crtc_state =
6454 intel_atomic_get_crtc_state(state, other_crtc);
6455 if (IS_ERR(other_crtc_state))
6456 return PTR_ERR(other_crtc_state);
6457
6458 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6459 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6460 pipe_name(pipe), pipe_config->fdi_lanes);
6461 return -EINVAL;
6462 }
6463 return 0;
6464 case PIPE_C:
6465 if (pipe_config->fdi_lanes > 2) {
6466 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6467 pipe_name(pipe), pipe_config->fdi_lanes);
6468 return -EINVAL;
6469 }
6470
6471 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6472 other_crtc_state =
6473 intel_atomic_get_crtc_state(state, other_crtc);
6474 if (IS_ERR(other_crtc_state))
6475 return PTR_ERR(other_crtc_state);
6476
6477 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6478 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6479 return -EINVAL;
6480 }
6481 return 0;
6482 default:
6483 BUG();
6484 }
6485 }
6486
6487 #define RETRY 1
6488 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6489 struct intel_crtc_state *pipe_config)
6490 {
6491 struct drm_device *dev = intel_crtc->base.dev;
6492 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6493 int lane, link_bw, fdi_dotclock, ret;
6494 bool needs_recompute = false;
6495
6496 retry:
6497 /* FDI is a binary signal running at ~2.7GHz, encoding
6498 * each output octet as 10 bits. The actual frequency
6499 * is stored as a divider into a 100MHz clock, and the
6500 * mode pixel clock is stored in units of 1KHz.
6501 * Hence the bw of each lane in terms of the mode signal
6502 * is:
6503 */
6504 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6505
6506 fdi_dotclock = adjusted_mode->crtc_clock;
6507
6508 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6509 pipe_config->pipe_bpp);
6510
6511 pipe_config->fdi_lanes = lane;
6512
6513 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6514 link_bw, &pipe_config->fdi_m_n);
6515
6516 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6517 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6518 pipe_config->pipe_bpp -= 2*3;
6519 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6520 pipe_config->pipe_bpp);
6521 needs_recompute = true;
6522 pipe_config->bw_constrained = true;
6523
6524 goto retry;
6525 }
6526
6527 if (needs_recompute)
6528 return RETRY;
6529
6530 return ret;
6531 }
6532
6533 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6534 struct intel_crtc_state *pipe_config)
6535 {
6536 if (pipe_config->pipe_bpp > 24)
6537 return false;
6538
6539 /* HSW can handle pixel rate up to cdclk? */
6540 if (IS_HASWELL(dev_priv))
6541 return true;
6542
6543 /*
6544 * We compare against max which means we must take
6545 * the increased cdclk requirement into account when
6546 * calculating the new cdclk.
6547 *
6548 * Should measure whether using a lower cdclk w/o IPS
6549 */
6550 return ilk_pipe_pixel_rate(pipe_config) <=
6551 dev_priv->max_cdclk_freq * 95 / 100;
6552 }
6553
6554 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6555 struct intel_crtc_state *pipe_config)
6556 {
6557 struct drm_device *dev = crtc->base.dev;
6558 struct drm_i915_private *dev_priv = dev->dev_private;
6559
6560 pipe_config->ips_enabled = i915.enable_ips &&
6561 hsw_crtc_supports_ips(crtc) &&
6562 pipe_config_supports_ips(dev_priv, pipe_config);
6563 }
6564
6565 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6566 {
6567 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6568
6569 /* GDG double wide on either pipe, otherwise pipe A only */
6570 return INTEL_INFO(dev_priv)->gen < 4 &&
6571 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6572 }
6573
6574 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6575 struct intel_crtc_state *pipe_config)
6576 {
6577 struct drm_device *dev = crtc->base.dev;
6578 struct drm_i915_private *dev_priv = dev->dev_private;
6579 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6580
6581 /* FIXME should check pixel clock limits on all platforms */
6582 if (INTEL_INFO(dev)->gen < 4) {
6583 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6584
6585 /*
6586 * Enable double wide mode when the dot clock
6587 * is > 90% of the (display) core speed.
6588 */
6589 if (intel_crtc_supports_double_wide(crtc) &&
6590 adjusted_mode->crtc_clock > clock_limit) {
6591 clock_limit *= 2;
6592 pipe_config->double_wide = true;
6593 }
6594
6595 if (adjusted_mode->crtc_clock > clock_limit) {
6596 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6597 adjusted_mode->crtc_clock, clock_limit,
6598 yesno(pipe_config->double_wide));
6599 return -EINVAL;
6600 }
6601 }
6602
6603 /*
6604 * Pipe horizontal size must be even in:
6605 * - DVO ganged mode
6606 * - LVDS dual channel mode
6607 * - Double wide pipe
6608 */
6609 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6610 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6611 pipe_config->pipe_src_w &= ~1;
6612
6613 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6614 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6615 */
6616 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6617 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6618 return -EINVAL;
6619
6620 if (HAS_IPS(dev))
6621 hsw_compute_ips_config(crtc, pipe_config);
6622
6623 if (pipe_config->has_pch_encoder)
6624 return ironlake_fdi_compute_config(crtc, pipe_config);
6625
6626 return 0;
6627 }
6628
6629 static int skylake_get_display_clock_speed(struct drm_device *dev)
6630 {
6631 struct drm_i915_private *dev_priv = to_i915(dev);
6632 uint32_t cdctl;
6633
6634 skl_dpll0_update(dev_priv);
6635
6636 if (dev_priv->cdclk_pll.vco == 0)
6637 return dev_priv->cdclk_pll.ref;
6638
6639 cdctl = I915_READ(CDCLK_CTL);
6640
6641 if (dev_priv->cdclk_pll.vco == 8640000) {
6642 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6643 case CDCLK_FREQ_450_432:
6644 return 432000;
6645 case CDCLK_FREQ_337_308:
6646 return 308571;
6647 case CDCLK_FREQ_540:
6648 return 540000;
6649 case CDCLK_FREQ_675_617:
6650 return 617143;
6651 default:
6652 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6653 }
6654 } else {
6655 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6656 case CDCLK_FREQ_450_432:
6657 return 450000;
6658 case CDCLK_FREQ_337_308:
6659 return 337500;
6660 case CDCLK_FREQ_540:
6661 return 540000;
6662 case CDCLK_FREQ_675_617:
6663 return 675000;
6664 default:
6665 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6666 }
6667 }
6668
6669 return dev_priv->cdclk_pll.ref;
6670 }
6671
6672 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
6673 {
6674 u32 val;
6675
6676 dev_priv->cdclk_pll.ref = 19200;
6677 dev_priv->cdclk_pll.vco = 0;
6678
6679 val = I915_READ(BXT_DE_PLL_ENABLE);
6680 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
6681 return;
6682
6683 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
6684 return;
6685
6686 val = I915_READ(BXT_DE_PLL_CTL);
6687 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
6688 dev_priv->cdclk_pll.ref;
6689 }
6690
6691 static int broxton_get_display_clock_speed(struct drm_device *dev)
6692 {
6693 struct drm_i915_private *dev_priv = to_i915(dev);
6694 u32 divider;
6695 int div, vco;
6696
6697 bxt_de_pll_update(dev_priv);
6698
6699 vco = dev_priv->cdclk_pll.vco;
6700 if (vco == 0)
6701 return dev_priv->cdclk_pll.ref;
6702
6703 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
6704
6705 switch (divider) {
6706 case BXT_CDCLK_CD2X_DIV_SEL_1:
6707 div = 2;
6708 break;
6709 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6710 div = 3;
6711 break;
6712 case BXT_CDCLK_CD2X_DIV_SEL_2:
6713 div = 4;
6714 break;
6715 case BXT_CDCLK_CD2X_DIV_SEL_4:
6716 div = 8;
6717 break;
6718 default:
6719 MISSING_CASE(divider);
6720 return dev_priv->cdclk_pll.ref;
6721 }
6722
6723 return DIV_ROUND_CLOSEST(vco, div);
6724 }
6725
6726 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6727 {
6728 struct drm_i915_private *dev_priv = dev->dev_private;
6729 uint32_t lcpll = I915_READ(LCPLL_CTL);
6730 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6731
6732 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6733 return 800000;
6734 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6735 return 450000;
6736 else if (freq == LCPLL_CLK_FREQ_450)
6737 return 450000;
6738 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6739 return 540000;
6740 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6741 return 337500;
6742 else
6743 return 675000;
6744 }
6745
6746 static int haswell_get_display_clock_speed(struct drm_device *dev)
6747 {
6748 struct drm_i915_private *dev_priv = dev->dev_private;
6749 uint32_t lcpll = I915_READ(LCPLL_CTL);
6750 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6751
6752 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6753 return 800000;
6754 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6755 return 450000;
6756 else if (freq == LCPLL_CLK_FREQ_450)
6757 return 450000;
6758 else if (IS_HSW_ULT(dev))
6759 return 337500;
6760 else
6761 return 540000;
6762 }
6763
6764 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6765 {
6766 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6767 CCK_DISPLAY_CLOCK_CONTROL);
6768 }
6769
6770 static int ilk_get_display_clock_speed(struct drm_device *dev)
6771 {
6772 return 450000;
6773 }
6774
6775 static int i945_get_display_clock_speed(struct drm_device *dev)
6776 {
6777 return 400000;
6778 }
6779
6780 static int i915_get_display_clock_speed(struct drm_device *dev)
6781 {
6782 return 333333;
6783 }
6784
6785 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6786 {
6787 return 200000;
6788 }
6789
6790 static int pnv_get_display_clock_speed(struct drm_device *dev)
6791 {
6792 u16 gcfgc = 0;
6793
6794 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6795
6796 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6797 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6798 return 266667;
6799 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6800 return 333333;
6801 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6802 return 444444;
6803 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6804 return 200000;
6805 default:
6806 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6807 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6808 return 133333;
6809 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6810 return 166667;
6811 }
6812 }
6813
6814 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6815 {
6816 u16 gcfgc = 0;
6817
6818 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6819
6820 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6821 return 133333;
6822 else {
6823 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6824 case GC_DISPLAY_CLOCK_333_MHZ:
6825 return 333333;
6826 default:
6827 case GC_DISPLAY_CLOCK_190_200_MHZ:
6828 return 190000;
6829 }
6830 }
6831 }
6832
6833 static int i865_get_display_clock_speed(struct drm_device *dev)
6834 {
6835 return 266667;
6836 }
6837
6838 static int i85x_get_display_clock_speed(struct drm_device *dev)
6839 {
6840 u16 hpllcc = 0;
6841
6842 /*
6843 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6844 * encoding is different :(
6845 * FIXME is this the right way to detect 852GM/852GMV?
6846 */
6847 if (dev->pdev->revision == 0x1)
6848 return 133333;
6849
6850 pci_bus_read_config_word(dev->pdev->bus,
6851 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6852
6853 /* Assume that the hardware is in the high speed state. This
6854 * should be the default.
6855 */
6856 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6857 case GC_CLOCK_133_200:
6858 case GC_CLOCK_133_200_2:
6859 case GC_CLOCK_100_200:
6860 return 200000;
6861 case GC_CLOCK_166_250:
6862 return 250000;
6863 case GC_CLOCK_100_133:
6864 return 133333;
6865 case GC_CLOCK_133_266:
6866 case GC_CLOCK_133_266_2:
6867 case GC_CLOCK_166_266:
6868 return 266667;
6869 }
6870
6871 /* Shouldn't happen */
6872 return 0;
6873 }
6874
6875 static int i830_get_display_clock_speed(struct drm_device *dev)
6876 {
6877 return 133333;
6878 }
6879
6880 static unsigned int intel_hpll_vco(struct drm_device *dev)
6881 {
6882 struct drm_i915_private *dev_priv = dev->dev_private;
6883 static const unsigned int blb_vco[8] = {
6884 [0] = 3200000,
6885 [1] = 4000000,
6886 [2] = 5333333,
6887 [3] = 4800000,
6888 [4] = 6400000,
6889 };
6890 static const unsigned int pnv_vco[8] = {
6891 [0] = 3200000,
6892 [1] = 4000000,
6893 [2] = 5333333,
6894 [3] = 4800000,
6895 [4] = 2666667,
6896 };
6897 static const unsigned int cl_vco[8] = {
6898 [0] = 3200000,
6899 [1] = 4000000,
6900 [2] = 5333333,
6901 [3] = 6400000,
6902 [4] = 3333333,
6903 [5] = 3566667,
6904 [6] = 4266667,
6905 };
6906 static const unsigned int elk_vco[8] = {
6907 [0] = 3200000,
6908 [1] = 4000000,
6909 [2] = 5333333,
6910 [3] = 4800000,
6911 };
6912 static const unsigned int ctg_vco[8] = {
6913 [0] = 3200000,
6914 [1] = 4000000,
6915 [2] = 5333333,
6916 [3] = 6400000,
6917 [4] = 2666667,
6918 [5] = 4266667,
6919 };
6920 const unsigned int *vco_table;
6921 unsigned int vco;
6922 uint8_t tmp = 0;
6923
6924 /* FIXME other chipsets? */
6925 if (IS_GM45(dev))
6926 vco_table = ctg_vco;
6927 else if (IS_G4X(dev))
6928 vco_table = elk_vco;
6929 else if (IS_CRESTLINE(dev))
6930 vco_table = cl_vco;
6931 else if (IS_PINEVIEW(dev))
6932 vco_table = pnv_vco;
6933 else if (IS_G33(dev))
6934 vco_table = blb_vco;
6935 else
6936 return 0;
6937
6938 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6939
6940 vco = vco_table[tmp & 0x7];
6941 if (vco == 0)
6942 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6943 else
6944 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6945
6946 return vco;
6947 }
6948
6949 static int gm45_get_display_clock_speed(struct drm_device *dev)
6950 {
6951 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6952 uint16_t tmp = 0;
6953
6954 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6955
6956 cdclk_sel = (tmp >> 12) & 0x1;
6957
6958 switch (vco) {
6959 case 2666667:
6960 case 4000000:
6961 case 5333333:
6962 return cdclk_sel ? 333333 : 222222;
6963 case 3200000:
6964 return cdclk_sel ? 320000 : 228571;
6965 default:
6966 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6967 return 222222;
6968 }
6969 }
6970
6971 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6972 {
6973 static const uint8_t div_3200[] = { 16, 10, 8 };
6974 static const uint8_t div_4000[] = { 20, 12, 10 };
6975 static const uint8_t div_5333[] = { 24, 16, 14 };
6976 const uint8_t *div_table;
6977 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6978 uint16_t tmp = 0;
6979
6980 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6981
6982 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6983
6984 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6985 goto fail;
6986
6987 switch (vco) {
6988 case 3200000:
6989 div_table = div_3200;
6990 break;
6991 case 4000000:
6992 div_table = div_4000;
6993 break;
6994 case 5333333:
6995 div_table = div_5333;
6996 break;
6997 default:
6998 goto fail;
6999 }
7000
7001 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7002
7003 fail:
7004 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7005 return 200000;
7006 }
7007
7008 static int g33_get_display_clock_speed(struct drm_device *dev)
7009 {
7010 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7011 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7012 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7013 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7014 const uint8_t *div_table;
7015 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7016 uint16_t tmp = 0;
7017
7018 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7019
7020 cdclk_sel = (tmp >> 4) & 0x7;
7021
7022 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7023 goto fail;
7024
7025 switch (vco) {
7026 case 3200000:
7027 div_table = div_3200;
7028 break;
7029 case 4000000:
7030 div_table = div_4000;
7031 break;
7032 case 4800000:
7033 div_table = div_4800;
7034 break;
7035 case 5333333:
7036 div_table = div_5333;
7037 break;
7038 default:
7039 goto fail;
7040 }
7041
7042 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7043
7044 fail:
7045 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7046 return 190476;
7047 }
7048
7049 static void
7050 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7051 {
7052 while (*num > DATA_LINK_M_N_MASK ||
7053 *den > DATA_LINK_M_N_MASK) {
7054 *num >>= 1;
7055 *den >>= 1;
7056 }
7057 }
7058
7059 static void compute_m_n(unsigned int m, unsigned int n,
7060 uint32_t *ret_m, uint32_t *ret_n)
7061 {
7062 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7063 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7064 intel_reduce_m_n_ratio(ret_m, ret_n);
7065 }
7066
7067 void
7068 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7069 int pixel_clock, int link_clock,
7070 struct intel_link_m_n *m_n)
7071 {
7072 m_n->tu = 64;
7073
7074 compute_m_n(bits_per_pixel * pixel_clock,
7075 link_clock * nlanes * 8,
7076 &m_n->gmch_m, &m_n->gmch_n);
7077
7078 compute_m_n(pixel_clock, link_clock,
7079 &m_n->link_m, &m_n->link_n);
7080 }
7081
7082 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7083 {
7084 if (i915.panel_use_ssc >= 0)
7085 return i915.panel_use_ssc != 0;
7086 return dev_priv->vbt.lvds_use_ssc
7087 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7088 }
7089
7090 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7091 {
7092 return (1 << dpll->n) << 16 | dpll->m2;
7093 }
7094
7095 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7096 {
7097 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7098 }
7099
7100 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7101 struct intel_crtc_state *crtc_state,
7102 struct dpll *reduced_clock)
7103 {
7104 struct drm_device *dev = crtc->base.dev;
7105 u32 fp, fp2 = 0;
7106
7107 if (IS_PINEVIEW(dev)) {
7108 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7109 if (reduced_clock)
7110 fp2 = pnv_dpll_compute_fp(reduced_clock);
7111 } else {
7112 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7113 if (reduced_clock)
7114 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7115 }
7116
7117 crtc_state->dpll_hw_state.fp0 = fp;
7118
7119 crtc->lowfreq_avail = false;
7120 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7121 reduced_clock) {
7122 crtc_state->dpll_hw_state.fp1 = fp2;
7123 crtc->lowfreq_avail = true;
7124 } else {
7125 crtc_state->dpll_hw_state.fp1 = fp;
7126 }
7127 }
7128
7129 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7130 pipe)
7131 {
7132 u32 reg_val;
7133
7134 /*
7135 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7136 * and set it to a reasonable value instead.
7137 */
7138 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7139 reg_val &= 0xffffff00;
7140 reg_val |= 0x00000030;
7141 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7142
7143 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7144 reg_val &= 0x8cffffff;
7145 reg_val = 0x8c000000;
7146 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7147
7148 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7149 reg_val &= 0xffffff00;
7150 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7151
7152 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7153 reg_val &= 0x00ffffff;
7154 reg_val |= 0xb0000000;
7155 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7156 }
7157
7158 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7159 struct intel_link_m_n *m_n)
7160 {
7161 struct drm_device *dev = crtc->base.dev;
7162 struct drm_i915_private *dev_priv = dev->dev_private;
7163 int pipe = crtc->pipe;
7164
7165 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7166 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7167 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7168 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7169 }
7170
7171 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7172 struct intel_link_m_n *m_n,
7173 struct intel_link_m_n *m2_n2)
7174 {
7175 struct drm_device *dev = crtc->base.dev;
7176 struct drm_i915_private *dev_priv = dev->dev_private;
7177 int pipe = crtc->pipe;
7178 enum transcoder transcoder = crtc->config->cpu_transcoder;
7179
7180 if (INTEL_INFO(dev)->gen >= 5) {
7181 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7182 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7183 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7184 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7185 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7186 * for gen < 8) and if DRRS is supported (to make sure the
7187 * registers are not unnecessarily accessed).
7188 */
7189 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7190 crtc->config->has_drrs) {
7191 I915_WRITE(PIPE_DATA_M2(transcoder),
7192 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7193 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7194 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7195 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7196 }
7197 } else {
7198 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7199 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7200 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7201 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7202 }
7203 }
7204
7205 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7206 {
7207 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7208
7209 if (m_n == M1_N1) {
7210 dp_m_n = &crtc->config->dp_m_n;
7211 dp_m2_n2 = &crtc->config->dp_m2_n2;
7212 } else if (m_n == M2_N2) {
7213
7214 /*
7215 * M2_N2 registers are not supported. Hence m2_n2 divider value
7216 * needs to be programmed into M1_N1.
7217 */
7218 dp_m_n = &crtc->config->dp_m2_n2;
7219 } else {
7220 DRM_ERROR("Unsupported divider value\n");
7221 return;
7222 }
7223
7224 if (crtc->config->has_pch_encoder)
7225 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7226 else
7227 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7228 }
7229
7230 static void vlv_compute_dpll(struct intel_crtc *crtc,
7231 struct intel_crtc_state *pipe_config)
7232 {
7233 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7234 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7235 if (crtc->pipe != PIPE_A)
7236 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7237
7238 /* DPLL not used with DSI, but still need the rest set up */
7239 if (!pipe_config->has_dsi_encoder)
7240 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7241 DPLL_EXT_BUFFER_ENABLE_VLV;
7242
7243 pipe_config->dpll_hw_state.dpll_md =
7244 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7245 }
7246
7247 static void chv_compute_dpll(struct intel_crtc *crtc,
7248 struct intel_crtc_state *pipe_config)
7249 {
7250 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7251 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7252 if (crtc->pipe != PIPE_A)
7253 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7254
7255 /* DPLL not used with DSI, but still need the rest set up */
7256 if (!pipe_config->has_dsi_encoder)
7257 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7258
7259 pipe_config->dpll_hw_state.dpll_md =
7260 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7261 }
7262
7263 static void vlv_prepare_pll(struct intel_crtc *crtc,
7264 const struct intel_crtc_state *pipe_config)
7265 {
7266 struct drm_device *dev = crtc->base.dev;
7267 struct drm_i915_private *dev_priv = dev->dev_private;
7268 enum pipe pipe = crtc->pipe;
7269 u32 mdiv;
7270 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7271 u32 coreclk, reg_val;
7272
7273 /* Enable Refclk */
7274 I915_WRITE(DPLL(pipe),
7275 pipe_config->dpll_hw_state.dpll &
7276 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7277
7278 /* No need to actually set up the DPLL with DSI */
7279 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7280 return;
7281
7282 mutex_lock(&dev_priv->sb_lock);
7283
7284 bestn = pipe_config->dpll.n;
7285 bestm1 = pipe_config->dpll.m1;
7286 bestm2 = pipe_config->dpll.m2;
7287 bestp1 = pipe_config->dpll.p1;
7288 bestp2 = pipe_config->dpll.p2;
7289
7290 /* See eDP HDMI DPIO driver vbios notes doc */
7291
7292 /* PLL B needs special handling */
7293 if (pipe == PIPE_B)
7294 vlv_pllb_recal_opamp(dev_priv, pipe);
7295
7296 /* Set up Tx target for periodic Rcomp update */
7297 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7298
7299 /* Disable target IRef on PLL */
7300 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7301 reg_val &= 0x00ffffff;
7302 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7303
7304 /* Disable fast lock */
7305 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7306
7307 /* Set idtafcrecal before PLL is enabled */
7308 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7309 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7310 mdiv |= ((bestn << DPIO_N_SHIFT));
7311 mdiv |= (1 << DPIO_K_SHIFT);
7312
7313 /*
7314 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7315 * but we don't support that).
7316 * Note: don't use the DAC post divider as it seems unstable.
7317 */
7318 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7319 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7320
7321 mdiv |= DPIO_ENABLE_CALIBRATION;
7322 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7323
7324 /* Set HBR and RBR LPF coefficients */
7325 if (pipe_config->port_clock == 162000 ||
7326 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7327 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7328 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7329 0x009f0003);
7330 else
7331 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7332 0x00d0000f);
7333
7334 if (pipe_config->has_dp_encoder) {
7335 /* Use SSC source */
7336 if (pipe == PIPE_A)
7337 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7338 0x0df40000);
7339 else
7340 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7341 0x0df70000);
7342 } else { /* HDMI or VGA */
7343 /* Use bend source */
7344 if (pipe == PIPE_A)
7345 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7346 0x0df70000);
7347 else
7348 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7349 0x0df40000);
7350 }
7351
7352 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7353 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7354 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7355 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7356 coreclk |= 0x01000000;
7357 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7358
7359 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7360 mutex_unlock(&dev_priv->sb_lock);
7361 }
7362
7363 static void chv_prepare_pll(struct intel_crtc *crtc,
7364 const struct intel_crtc_state *pipe_config)
7365 {
7366 struct drm_device *dev = crtc->base.dev;
7367 struct drm_i915_private *dev_priv = dev->dev_private;
7368 enum pipe pipe = crtc->pipe;
7369 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7370 u32 loopfilter, tribuf_calcntr;
7371 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7372 u32 dpio_val;
7373 int vco;
7374
7375 /* Enable Refclk and SSC */
7376 I915_WRITE(DPLL(pipe),
7377 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7378
7379 /* No need to actually set up the DPLL with DSI */
7380 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7381 return;
7382
7383 bestn = pipe_config->dpll.n;
7384 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7385 bestm1 = pipe_config->dpll.m1;
7386 bestm2 = pipe_config->dpll.m2 >> 22;
7387 bestp1 = pipe_config->dpll.p1;
7388 bestp2 = pipe_config->dpll.p2;
7389 vco = pipe_config->dpll.vco;
7390 dpio_val = 0;
7391 loopfilter = 0;
7392
7393 mutex_lock(&dev_priv->sb_lock);
7394
7395 /* p1 and p2 divider */
7396 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7397 5 << DPIO_CHV_S1_DIV_SHIFT |
7398 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7399 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7400 1 << DPIO_CHV_K_DIV_SHIFT);
7401
7402 /* Feedback post-divider - m2 */
7403 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7404
7405 /* Feedback refclk divider - n and m1 */
7406 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7407 DPIO_CHV_M1_DIV_BY_2 |
7408 1 << DPIO_CHV_N_DIV_SHIFT);
7409
7410 /* M2 fraction division */
7411 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7412
7413 /* M2 fraction division enable */
7414 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7415 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7416 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7417 if (bestm2_frac)
7418 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7419 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7420
7421 /* Program digital lock detect threshold */
7422 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7423 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7424 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7425 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7426 if (!bestm2_frac)
7427 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7428 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7429
7430 /* Loop filter */
7431 if (vco == 5400000) {
7432 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7433 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7434 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7435 tribuf_calcntr = 0x9;
7436 } else if (vco <= 6200000) {
7437 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7438 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7439 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7440 tribuf_calcntr = 0x9;
7441 } else if (vco <= 6480000) {
7442 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7443 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7444 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7445 tribuf_calcntr = 0x8;
7446 } else {
7447 /* Not supported. Apply the same limits as in the max case */
7448 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7449 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7450 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7451 tribuf_calcntr = 0;
7452 }
7453 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7454
7455 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7456 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7457 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7458 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7459
7460 /* AFC Recal */
7461 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7462 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7463 DPIO_AFC_RECAL);
7464
7465 mutex_unlock(&dev_priv->sb_lock);
7466 }
7467
7468 /**
7469 * vlv_force_pll_on - forcibly enable just the PLL
7470 * @dev_priv: i915 private structure
7471 * @pipe: pipe PLL to enable
7472 * @dpll: PLL configuration
7473 *
7474 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7475 * in cases where we need the PLL enabled even when @pipe is not going to
7476 * be enabled.
7477 */
7478 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7479 const struct dpll *dpll)
7480 {
7481 struct intel_crtc *crtc =
7482 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7483 struct intel_crtc_state *pipe_config;
7484
7485 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7486 if (!pipe_config)
7487 return -ENOMEM;
7488
7489 pipe_config->base.crtc = &crtc->base;
7490 pipe_config->pixel_multiplier = 1;
7491 pipe_config->dpll = *dpll;
7492
7493 if (IS_CHERRYVIEW(dev)) {
7494 chv_compute_dpll(crtc, pipe_config);
7495 chv_prepare_pll(crtc, pipe_config);
7496 chv_enable_pll(crtc, pipe_config);
7497 } else {
7498 vlv_compute_dpll(crtc, pipe_config);
7499 vlv_prepare_pll(crtc, pipe_config);
7500 vlv_enable_pll(crtc, pipe_config);
7501 }
7502
7503 kfree(pipe_config);
7504
7505 return 0;
7506 }
7507
7508 /**
7509 * vlv_force_pll_off - forcibly disable just the PLL
7510 * @dev_priv: i915 private structure
7511 * @pipe: pipe PLL to disable
7512 *
7513 * Disable the PLL for @pipe. To be used in cases where we need
7514 * the PLL enabled even when @pipe is not going to be enabled.
7515 */
7516 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7517 {
7518 if (IS_CHERRYVIEW(dev))
7519 chv_disable_pll(to_i915(dev), pipe);
7520 else
7521 vlv_disable_pll(to_i915(dev), pipe);
7522 }
7523
7524 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7525 struct intel_crtc_state *crtc_state,
7526 struct dpll *reduced_clock)
7527 {
7528 struct drm_device *dev = crtc->base.dev;
7529 struct drm_i915_private *dev_priv = dev->dev_private;
7530 u32 dpll;
7531 bool is_sdvo;
7532 struct dpll *clock = &crtc_state->dpll;
7533
7534 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7535
7536 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7537 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7538
7539 dpll = DPLL_VGA_MODE_DIS;
7540
7541 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7542 dpll |= DPLLB_MODE_LVDS;
7543 else
7544 dpll |= DPLLB_MODE_DAC_SERIAL;
7545
7546 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7547 dpll |= (crtc_state->pixel_multiplier - 1)
7548 << SDVO_MULTIPLIER_SHIFT_HIRES;
7549 }
7550
7551 if (is_sdvo)
7552 dpll |= DPLL_SDVO_HIGH_SPEED;
7553
7554 if (crtc_state->has_dp_encoder)
7555 dpll |= DPLL_SDVO_HIGH_SPEED;
7556
7557 /* compute bitmask from p1 value */
7558 if (IS_PINEVIEW(dev))
7559 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7560 else {
7561 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7562 if (IS_G4X(dev) && reduced_clock)
7563 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7564 }
7565 switch (clock->p2) {
7566 case 5:
7567 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7568 break;
7569 case 7:
7570 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7571 break;
7572 case 10:
7573 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7574 break;
7575 case 14:
7576 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7577 break;
7578 }
7579 if (INTEL_INFO(dev)->gen >= 4)
7580 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7581
7582 if (crtc_state->sdvo_tv_clock)
7583 dpll |= PLL_REF_INPUT_TVCLKINBC;
7584 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7585 intel_panel_use_ssc(dev_priv))
7586 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7587 else
7588 dpll |= PLL_REF_INPUT_DREFCLK;
7589
7590 dpll |= DPLL_VCO_ENABLE;
7591 crtc_state->dpll_hw_state.dpll = dpll;
7592
7593 if (INTEL_INFO(dev)->gen >= 4) {
7594 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7595 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7596 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7597 }
7598 }
7599
7600 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7601 struct intel_crtc_state *crtc_state,
7602 struct dpll *reduced_clock)
7603 {
7604 struct drm_device *dev = crtc->base.dev;
7605 struct drm_i915_private *dev_priv = dev->dev_private;
7606 u32 dpll;
7607 struct dpll *clock = &crtc_state->dpll;
7608
7609 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7610
7611 dpll = DPLL_VGA_MODE_DIS;
7612
7613 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7614 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7615 } else {
7616 if (clock->p1 == 2)
7617 dpll |= PLL_P1_DIVIDE_BY_TWO;
7618 else
7619 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7620 if (clock->p2 == 4)
7621 dpll |= PLL_P2_DIVIDE_BY_4;
7622 }
7623
7624 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7625 dpll |= DPLL_DVO_2X_MODE;
7626
7627 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7628 intel_panel_use_ssc(dev_priv))
7629 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7630 else
7631 dpll |= PLL_REF_INPUT_DREFCLK;
7632
7633 dpll |= DPLL_VCO_ENABLE;
7634 crtc_state->dpll_hw_state.dpll = dpll;
7635 }
7636
7637 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7638 {
7639 struct drm_device *dev = intel_crtc->base.dev;
7640 struct drm_i915_private *dev_priv = dev->dev_private;
7641 enum pipe pipe = intel_crtc->pipe;
7642 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7643 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7644 uint32_t crtc_vtotal, crtc_vblank_end;
7645 int vsyncshift = 0;
7646
7647 /* We need to be careful not to changed the adjusted mode, for otherwise
7648 * the hw state checker will get angry at the mismatch. */
7649 crtc_vtotal = adjusted_mode->crtc_vtotal;
7650 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7651
7652 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7653 /* the chip adds 2 halflines automatically */
7654 crtc_vtotal -= 1;
7655 crtc_vblank_end -= 1;
7656
7657 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7658 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7659 else
7660 vsyncshift = adjusted_mode->crtc_hsync_start -
7661 adjusted_mode->crtc_htotal / 2;
7662 if (vsyncshift < 0)
7663 vsyncshift += adjusted_mode->crtc_htotal;
7664 }
7665
7666 if (INTEL_INFO(dev)->gen > 3)
7667 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7668
7669 I915_WRITE(HTOTAL(cpu_transcoder),
7670 (adjusted_mode->crtc_hdisplay - 1) |
7671 ((adjusted_mode->crtc_htotal - 1) << 16));
7672 I915_WRITE(HBLANK(cpu_transcoder),
7673 (adjusted_mode->crtc_hblank_start - 1) |
7674 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7675 I915_WRITE(HSYNC(cpu_transcoder),
7676 (adjusted_mode->crtc_hsync_start - 1) |
7677 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7678
7679 I915_WRITE(VTOTAL(cpu_transcoder),
7680 (adjusted_mode->crtc_vdisplay - 1) |
7681 ((crtc_vtotal - 1) << 16));
7682 I915_WRITE(VBLANK(cpu_transcoder),
7683 (adjusted_mode->crtc_vblank_start - 1) |
7684 ((crtc_vblank_end - 1) << 16));
7685 I915_WRITE(VSYNC(cpu_transcoder),
7686 (adjusted_mode->crtc_vsync_start - 1) |
7687 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7688
7689 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7690 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7691 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7692 * bits. */
7693 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7694 (pipe == PIPE_B || pipe == PIPE_C))
7695 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7696
7697 }
7698
7699 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7700 {
7701 struct drm_device *dev = intel_crtc->base.dev;
7702 struct drm_i915_private *dev_priv = dev->dev_private;
7703 enum pipe pipe = intel_crtc->pipe;
7704
7705 /* pipesrc controls the size that is scaled from, which should
7706 * always be the user's requested size.
7707 */
7708 I915_WRITE(PIPESRC(pipe),
7709 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7710 (intel_crtc->config->pipe_src_h - 1));
7711 }
7712
7713 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7714 struct intel_crtc_state *pipe_config)
7715 {
7716 struct drm_device *dev = crtc->base.dev;
7717 struct drm_i915_private *dev_priv = dev->dev_private;
7718 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7719 uint32_t tmp;
7720
7721 tmp = I915_READ(HTOTAL(cpu_transcoder));
7722 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7723 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7724 tmp = I915_READ(HBLANK(cpu_transcoder));
7725 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7726 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7727 tmp = I915_READ(HSYNC(cpu_transcoder));
7728 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7729 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7730
7731 tmp = I915_READ(VTOTAL(cpu_transcoder));
7732 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7733 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7734 tmp = I915_READ(VBLANK(cpu_transcoder));
7735 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7736 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7737 tmp = I915_READ(VSYNC(cpu_transcoder));
7738 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7739 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7740
7741 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7742 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7743 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7744 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7745 }
7746 }
7747
7748 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7749 struct intel_crtc_state *pipe_config)
7750 {
7751 struct drm_device *dev = crtc->base.dev;
7752 struct drm_i915_private *dev_priv = dev->dev_private;
7753 u32 tmp;
7754
7755 tmp = I915_READ(PIPESRC(crtc->pipe));
7756 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7757 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7758
7759 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7760 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7761 }
7762
7763 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7764 struct intel_crtc_state *pipe_config)
7765 {
7766 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7767 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7768 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7769 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7770
7771 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7772 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7773 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7774 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7775
7776 mode->flags = pipe_config->base.adjusted_mode.flags;
7777 mode->type = DRM_MODE_TYPE_DRIVER;
7778
7779 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7780 mode->flags |= pipe_config->base.adjusted_mode.flags;
7781
7782 mode->hsync = drm_mode_hsync(mode);
7783 mode->vrefresh = drm_mode_vrefresh(mode);
7784 drm_mode_set_name(mode);
7785 }
7786
7787 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7788 {
7789 struct drm_device *dev = intel_crtc->base.dev;
7790 struct drm_i915_private *dev_priv = dev->dev_private;
7791 uint32_t pipeconf;
7792
7793 pipeconf = 0;
7794
7795 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7796 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7797 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7798
7799 if (intel_crtc->config->double_wide)
7800 pipeconf |= PIPECONF_DOUBLE_WIDE;
7801
7802 /* only g4x and later have fancy bpc/dither controls */
7803 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7804 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7805 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7806 pipeconf |= PIPECONF_DITHER_EN |
7807 PIPECONF_DITHER_TYPE_SP;
7808
7809 switch (intel_crtc->config->pipe_bpp) {
7810 case 18:
7811 pipeconf |= PIPECONF_6BPC;
7812 break;
7813 case 24:
7814 pipeconf |= PIPECONF_8BPC;
7815 break;
7816 case 30:
7817 pipeconf |= PIPECONF_10BPC;
7818 break;
7819 default:
7820 /* Case prevented by intel_choose_pipe_bpp_dither. */
7821 BUG();
7822 }
7823 }
7824
7825 if (HAS_PIPE_CXSR(dev)) {
7826 if (intel_crtc->lowfreq_avail) {
7827 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7828 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7829 } else {
7830 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7831 }
7832 }
7833
7834 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7835 if (INTEL_INFO(dev)->gen < 4 ||
7836 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7837 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7838 else
7839 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7840 } else
7841 pipeconf |= PIPECONF_PROGRESSIVE;
7842
7843 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7844 intel_crtc->config->limited_color_range)
7845 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7846
7847 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7848 POSTING_READ(PIPECONF(intel_crtc->pipe));
7849 }
7850
7851 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7852 struct intel_crtc_state *crtc_state)
7853 {
7854 struct drm_device *dev = crtc->base.dev;
7855 struct drm_i915_private *dev_priv = dev->dev_private;
7856 const struct intel_limit *limit;
7857 int refclk = 48000;
7858
7859 memset(&crtc_state->dpll_hw_state, 0,
7860 sizeof(crtc_state->dpll_hw_state));
7861
7862 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7863 if (intel_panel_use_ssc(dev_priv)) {
7864 refclk = dev_priv->vbt.lvds_ssc_freq;
7865 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7866 }
7867
7868 limit = &intel_limits_i8xx_lvds;
7869 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7870 limit = &intel_limits_i8xx_dvo;
7871 } else {
7872 limit = &intel_limits_i8xx_dac;
7873 }
7874
7875 if (!crtc_state->clock_set &&
7876 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7877 refclk, NULL, &crtc_state->dpll)) {
7878 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7879 return -EINVAL;
7880 }
7881
7882 i8xx_compute_dpll(crtc, crtc_state, NULL);
7883
7884 return 0;
7885 }
7886
7887 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7888 struct intel_crtc_state *crtc_state)
7889 {
7890 struct drm_device *dev = crtc->base.dev;
7891 struct drm_i915_private *dev_priv = dev->dev_private;
7892 const struct intel_limit *limit;
7893 int refclk = 96000;
7894
7895 memset(&crtc_state->dpll_hw_state, 0,
7896 sizeof(crtc_state->dpll_hw_state));
7897
7898 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7899 if (intel_panel_use_ssc(dev_priv)) {
7900 refclk = dev_priv->vbt.lvds_ssc_freq;
7901 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7902 }
7903
7904 if (intel_is_dual_link_lvds(dev))
7905 limit = &intel_limits_g4x_dual_channel_lvds;
7906 else
7907 limit = &intel_limits_g4x_single_channel_lvds;
7908 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7909 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7910 limit = &intel_limits_g4x_hdmi;
7911 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7912 limit = &intel_limits_g4x_sdvo;
7913 } else {
7914 /* The option is for other outputs */
7915 limit = &intel_limits_i9xx_sdvo;
7916 }
7917
7918 if (!crtc_state->clock_set &&
7919 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7920 refclk, NULL, &crtc_state->dpll)) {
7921 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7922 return -EINVAL;
7923 }
7924
7925 i9xx_compute_dpll(crtc, crtc_state, NULL);
7926
7927 return 0;
7928 }
7929
7930 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7931 struct intel_crtc_state *crtc_state)
7932 {
7933 struct drm_device *dev = crtc->base.dev;
7934 struct drm_i915_private *dev_priv = dev->dev_private;
7935 const struct intel_limit *limit;
7936 int refclk = 96000;
7937
7938 memset(&crtc_state->dpll_hw_state, 0,
7939 sizeof(crtc_state->dpll_hw_state));
7940
7941 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7942 if (intel_panel_use_ssc(dev_priv)) {
7943 refclk = dev_priv->vbt.lvds_ssc_freq;
7944 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7945 }
7946
7947 limit = &intel_limits_pineview_lvds;
7948 } else {
7949 limit = &intel_limits_pineview_sdvo;
7950 }
7951
7952 if (!crtc_state->clock_set &&
7953 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7954 refclk, NULL, &crtc_state->dpll)) {
7955 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7956 return -EINVAL;
7957 }
7958
7959 i9xx_compute_dpll(crtc, crtc_state, NULL);
7960
7961 return 0;
7962 }
7963
7964 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7965 struct intel_crtc_state *crtc_state)
7966 {
7967 struct drm_device *dev = crtc->base.dev;
7968 struct drm_i915_private *dev_priv = dev->dev_private;
7969 const struct intel_limit *limit;
7970 int refclk = 96000;
7971
7972 memset(&crtc_state->dpll_hw_state, 0,
7973 sizeof(crtc_state->dpll_hw_state));
7974
7975 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7976 if (intel_panel_use_ssc(dev_priv)) {
7977 refclk = dev_priv->vbt.lvds_ssc_freq;
7978 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7979 }
7980
7981 limit = &intel_limits_i9xx_lvds;
7982 } else {
7983 limit = &intel_limits_i9xx_sdvo;
7984 }
7985
7986 if (!crtc_state->clock_set &&
7987 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7988 refclk, NULL, &crtc_state->dpll)) {
7989 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7990 return -EINVAL;
7991 }
7992
7993 i9xx_compute_dpll(crtc, crtc_state, NULL);
7994
7995 return 0;
7996 }
7997
7998 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7999 struct intel_crtc_state *crtc_state)
8000 {
8001 int refclk = 100000;
8002 const struct intel_limit *limit = &intel_limits_chv;
8003
8004 memset(&crtc_state->dpll_hw_state, 0,
8005 sizeof(crtc_state->dpll_hw_state));
8006
8007 if (!crtc_state->clock_set &&
8008 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8009 refclk, NULL, &crtc_state->dpll)) {
8010 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8011 return -EINVAL;
8012 }
8013
8014 chv_compute_dpll(crtc, crtc_state);
8015
8016 return 0;
8017 }
8018
8019 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8020 struct intel_crtc_state *crtc_state)
8021 {
8022 int refclk = 100000;
8023 const struct intel_limit *limit = &intel_limits_vlv;
8024
8025 memset(&crtc_state->dpll_hw_state, 0,
8026 sizeof(crtc_state->dpll_hw_state));
8027
8028 if (!crtc_state->clock_set &&
8029 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8030 refclk, NULL, &crtc_state->dpll)) {
8031 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8032 return -EINVAL;
8033 }
8034
8035 vlv_compute_dpll(crtc, crtc_state);
8036
8037 return 0;
8038 }
8039
8040 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8041 struct intel_crtc_state *pipe_config)
8042 {
8043 struct drm_device *dev = crtc->base.dev;
8044 struct drm_i915_private *dev_priv = dev->dev_private;
8045 uint32_t tmp;
8046
8047 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8048 return;
8049
8050 tmp = I915_READ(PFIT_CONTROL);
8051 if (!(tmp & PFIT_ENABLE))
8052 return;
8053
8054 /* Check whether the pfit is attached to our pipe. */
8055 if (INTEL_INFO(dev)->gen < 4) {
8056 if (crtc->pipe != PIPE_B)
8057 return;
8058 } else {
8059 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8060 return;
8061 }
8062
8063 pipe_config->gmch_pfit.control = tmp;
8064 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8065 }
8066
8067 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8068 struct intel_crtc_state *pipe_config)
8069 {
8070 struct drm_device *dev = crtc->base.dev;
8071 struct drm_i915_private *dev_priv = dev->dev_private;
8072 int pipe = pipe_config->cpu_transcoder;
8073 struct dpll clock;
8074 u32 mdiv;
8075 int refclk = 100000;
8076
8077 /* In case of DSI, DPLL will not be used */
8078 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8079 return;
8080
8081 mutex_lock(&dev_priv->sb_lock);
8082 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8083 mutex_unlock(&dev_priv->sb_lock);
8084
8085 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8086 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8087 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8088 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8089 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8090
8091 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8092 }
8093
8094 static void
8095 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8096 struct intel_initial_plane_config *plane_config)
8097 {
8098 struct drm_device *dev = crtc->base.dev;
8099 struct drm_i915_private *dev_priv = dev->dev_private;
8100 u32 val, base, offset;
8101 int pipe = crtc->pipe, plane = crtc->plane;
8102 int fourcc, pixel_format;
8103 unsigned int aligned_height;
8104 struct drm_framebuffer *fb;
8105 struct intel_framebuffer *intel_fb;
8106
8107 val = I915_READ(DSPCNTR(plane));
8108 if (!(val & DISPLAY_PLANE_ENABLE))
8109 return;
8110
8111 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8112 if (!intel_fb) {
8113 DRM_DEBUG_KMS("failed to alloc fb\n");
8114 return;
8115 }
8116
8117 fb = &intel_fb->base;
8118
8119 if (INTEL_INFO(dev)->gen >= 4) {
8120 if (val & DISPPLANE_TILED) {
8121 plane_config->tiling = I915_TILING_X;
8122 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8123 }
8124 }
8125
8126 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8127 fourcc = i9xx_format_to_fourcc(pixel_format);
8128 fb->pixel_format = fourcc;
8129 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8130
8131 if (INTEL_INFO(dev)->gen >= 4) {
8132 if (plane_config->tiling)
8133 offset = I915_READ(DSPTILEOFF(plane));
8134 else
8135 offset = I915_READ(DSPLINOFF(plane));
8136 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8137 } else {
8138 base = I915_READ(DSPADDR(plane));
8139 }
8140 plane_config->base = base;
8141
8142 val = I915_READ(PIPESRC(pipe));
8143 fb->width = ((val >> 16) & 0xfff) + 1;
8144 fb->height = ((val >> 0) & 0xfff) + 1;
8145
8146 val = I915_READ(DSPSTRIDE(pipe));
8147 fb->pitches[0] = val & 0xffffffc0;
8148
8149 aligned_height = intel_fb_align_height(dev, fb->height,
8150 fb->pixel_format,
8151 fb->modifier[0]);
8152
8153 plane_config->size = fb->pitches[0] * aligned_height;
8154
8155 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8156 pipe_name(pipe), plane, fb->width, fb->height,
8157 fb->bits_per_pixel, base, fb->pitches[0],
8158 plane_config->size);
8159
8160 plane_config->fb = intel_fb;
8161 }
8162
8163 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8164 struct intel_crtc_state *pipe_config)
8165 {
8166 struct drm_device *dev = crtc->base.dev;
8167 struct drm_i915_private *dev_priv = dev->dev_private;
8168 int pipe = pipe_config->cpu_transcoder;
8169 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8170 struct dpll clock;
8171 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8172 int refclk = 100000;
8173
8174 /* In case of DSI, DPLL will not be used */
8175 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8176 return;
8177
8178 mutex_lock(&dev_priv->sb_lock);
8179 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8180 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8181 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8182 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8183 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8184 mutex_unlock(&dev_priv->sb_lock);
8185
8186 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8187 clock.m2 = (pll_dw0 & 0xff) << 22;
8188 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8189 clock.m2 |= pll_dw2 & 0x3fffff;
8190 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8191 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8192 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8193
8194 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8195 }
8196
8197 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8198 struct intel_crtc_state *pipe_config)
8199 {
8200 struct drm_device *dev = crtc->base.dev;
8201 struct drm_i915_private *dev_priv = dev->dev_private;
8202 enum intel_display_power_domain power_domain;
8203 uint32_t tmp;
8204 bool ret;
8205
8206 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8207 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8208 return false;
8209
8210 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8211 pipe_config->shared_dpll = NULL;
8212
8213 ret = false;
8214
8215 tmp = I915_READ(PIPECONF(crtc->pipe));
8216 if (!(tmp & PIPECONF_ENABLE))
8217 goto out;
8218
8219 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8220 switch (tmp & PIPECONF_BPC_MASK) {
8221 case PIPECONF_6BPC:
8222 pipe_config->pipe_bpp = 18;
8223 break;
8224 case PIPECONF_8BPC:
8225 pipe_config->pipe_bpp = 24;
8226 break;
8227 case PIPECONF_10BPC:
8228 pipe_config->pipe_bpp = 30;
8229 break;
8230 default:
8231 break;
8232 }
8233 }
8234
8235 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8236 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8237 pipe_config->limited_color_range = true;
8238
8239 if (INTEL_INFO(dev)->gen < 4)
8240 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8241
8242 intel_get_pipe_timings(crtc, pipe_config);
8243 intel_get_pipe_src_size(crtc, pipe_config);
8244
8245 i9xx_get_pfit_config(crtc, pipe_config);
8246
8247 if (INTEL_INFO(dev)->gen >= 4) {
8248 /* No way to read it out on pipes B and C */
8249 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8250 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8251 else
8252 tmp = I915_READ(DPLL_MD(crtc->pipe));
8253 pipe_config->pixel_multiplier =
8254 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8255 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8256 pipe_config->dpll_hw_state.dpll_md = tmp;
8257 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8258 tmp = I915_READ(DPLL(crtc->pipe));
8259 pipe_config->pixel_multiplier =
8260 ((tmp & SDVO_MULTIPLIER_MASK)
8261 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8262 } else {
8263 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8264 * port and will be fixed up in the encoder->get_config
8265 * function. */
8266 pipe_config->pixel_multiplier = 1;
8267 }
8268 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8269 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8270 /*
8271 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8272 * on 830. Filter it out here so that we don't
8273 * report errors due to that.
8274 */
8275 if (IS_I830(dev))
8276 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8277
8278 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8279 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8280 } else {
8281 /* Mask out read-only status bits. */
8282 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8283 DPLL_PORTC_READY_MASK |
8284 DPLL_PORTB_READY_MASK);
8285 }
8286
8287 if (IS_CHERRYVIEW(dev))
8288 chv_crtc_clock_get(crtc, pipe_config);
8289 else if (IS_VALLEYVIEW(dev))
8290 vlv_crtc_clock_get(crtc, pipe_config);
8291 else
8292 i9xx_crtc_clock_get(crtc, pipe_config);
8293
8294 /*
8295 * Normally the dotclock is filled in by the encoder .get_config()
8296 * but in case the pipe is enabled w/o any ports we need a sane
8297 * default.
8298 */
8299 pipe_config->base.adjusted_mode.crtc_clock =
8300 pipe_config->port_clock / pipe_config->pixel_multiplier;
8301
8302 ret = true;
8303
8304 out:
8305 intel_display_power_put(dev_priv, power_domain);
8306
8307 return ret;
8308 }
8309
8310 static void ironlake_init_pch_refclk(struct drm_device *dev)
8311 {
8312 struct drm_i915_private *dev_priv = dev->dev_private;
8313 struct intel_encoder *encoder;
8314 u32 val, final;
8315 bool has_lvds = false;
8316 bool has_cpu_edp = false;
8317 bool has_panel = false;
8318 bool has_ck505 = false;
8319 bool can_ssc = false;
8320
8321 /* We need to take the global config into account */
8322 for_each_intel_encoder(dev, encoder) {
8323 switch (encoder->type) {
8324 case INTEL_OUTPUT_LVDS:
8325 has_panel = true;
8326 has_lvds = true;
8327 break;
8328 case INTEL_OUTPUT_EDP:
8329 has_panel = true;
8330 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8331 has_cpu_edp = true;
8332 break;
8333 default:
8334 break;
8335 }
8336 }
8337
8338 if (HAS_PCH_IBX(dev)) {
8339 has_ck505 = dev_priv->vbt.display_clock_mode;
8340 can_ssc = has_ck505;
8341 } else {
8342 has_ck505 = false;
8343 can_ssc = true;
8344 }
8345
8346 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8347 has_panel, has_lvds, has_ck505);
8348
8349 /* Ironlake: try to setup display ref clock before DPLL
8350 * enabling. This is only under driver's control after
8351 * PCH B stepping, previous chipset stepping should be
8352 * ignoring this setting.
8353 */
8354 val = I915_READ(PCH_DREF_CONTROL);
8355
8356 /* As we must carefully and slowly disable/enable each source in turn,
8357 * compute the final state we want first and check if we need to
8358 * make any changes at all.
8359 */
8360 final = val;
8361 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8362 if (has_ck505)
8363 final |= DREF_NONSPREAD_CK505_ENABLE;
8364 else
8365 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8366
8367 final &= ~DREF_SSC_SOURCE_MASK;
8368 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8369 final &= ~DREF_SSC1_ENABLE;
8370
8371 if (has_panel) {
8372 final |= DREF_SSC_SOURCE_ENABLE;
8373
8374 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8375 final |= DREF_SSC1_ENABLE;
8376
8377 if (has_cpu_edp) {
8378 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8379 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8380 else
8381 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8382 } else
8383 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8384 } else {
8385 final |= DREF_SSC_SOURCE_DISABLE;
8386 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8387 }
8388
8389 if (final == val)
8390 return;
8391
8392 /* Always enable nonspread source */
8393 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8394
8395 if (has_ck505)
8396 val |= DREF_NONSPREAD_CK505_ENABLE;
8397 else
8398 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8399
8400 if (has_panel) {
8401 val &= ~DREF_SSC_SOURCE_MASK;
8402 val |= DREF_SSC_SOURCE_ENABLE;
8403
8404 /* SSC must be turned on before enabling the CPU output */
8405 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8406 DRM_DEBUG_KMS("Using SSC on panel\n");
8407 val |= DREF_SSC1_ENABLE;
8408 } else
8409 val &= ~DREF_SSC1_ENABLE;
8410
8411 /* Get SSC going before enabling the outputs */
8412 I915_WRITE(PCH_DREF_CONTROL, val);
8413 POSTING_READ(PCH_DREF_CONTROL);
8414 udelay(200);
8415
8416 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8417
8418 /* Enable CPU source on CPU attached eDP */
8419 if (has_cpu_edp) {
8420 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8421 DRM_DEBUG_KMS("Using SSC on eDP\n");
8422 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8423 } else
8424 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8425 } else
8426 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8427
8428 I915_WRITE(PCH_DREF_CONTROL, val);
8429 POSTING_READ(PCH_DREF_CONTROL);
8430 udelay(200);
8431 } else {
8432 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8433
8434 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8435
8436 /* Turn off CPU output */
8437 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8438
8439 I915_WRITE(PCH_DREF_CONTROL, val);
8440 POSTING_READ(PCH_DREF_CONTROL);
8441 udelay(200);
8442
8443 /* Turn off the SSC source */
8444 val &= ~DREF_SSC_SOURCE_MASK;
8445 val |= DREF_SSC_SOURCE_DISABLE;
8446
8447 /* Turn off SSC1 */
8448 val &= ~DREF_SSC1_ENABLE;
8449
8450 I915_WRITE(PCH_DREF_CONTROL, val);
8451 POSTING_READ(PCH_DREF_CONTROL);
8452 udelay(200);
8453 }
8454
8455 BUG_ON(val != final);
8456 }
8457
8458 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8459 {
8460 uint32_t tmp;
8461
8462 tmp = I915_READ(SOUTH_CHICKEN2);
8463 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8464 I915_WRITE(SOUTH_CHICKEN2, tmp);
8465
8466 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8467 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8468 DRM_ERROR("FDI mPHY reset assert timeout\n");
8469
8470 tmp = I915_READ(SOUTH_CHICKEN2);
8471 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8472 I915_WRITE(SOUTH_CHICKEN2, tmp);
8473
8474 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8475 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8476 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8477 }
8478
8479 /* WaMPhyProgramming:hsw */
8480 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8481 {
8482 uint32_t tmp;
8483
8484 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8485 tmp &= ~(0xFF << 24);
8486 tmp |= (0x12 << 24);
8487 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8488
8489 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8490 tmp |= (1 << 11);
8491 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8492
8493 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8494 tmp |= (1 << 11);
8495 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8496
8497 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8498 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8499 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8500
8501 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8502 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8503 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8504
8505 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8506 tmp &= ~(7 << 13);
8507 tmp |= (5 << 13);
8508 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8509
8510 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8511 tmp &= ~(7 << 13);
8512 tmp |= (5 << 13);
8513 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8514
8515 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8516 tmp &= ~0xFF;
8517 tmp |= 0x1C;
8518 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8519
8520 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8521 tmp &= ~0xFF;
8522 tmp |= 0x1C;
8523 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8524
8525 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8526 tmp &= ~(0xFF << 16);
8527 tmp |= (0x1C << 16);
8528 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8529
8530 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8531 tmp &= ~(0xFF << 16);
8532 tmp |= (0x1C << 16);
8533 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8534
8535 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8536 tmp |= (1 << 27);
8537 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8538
8539 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8540 tmp |= (1 << 27);
8541 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8542
8543 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8544 tmp &= ~(0xF << 28);
8545 tmp |= (4 << 28);
8546 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8547
8548 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8549 tmp &= ~(0xF << 28);
8550 tmp |= (4 << 28);
8551 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8552 }
8553
8554 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8555 * Programming" based on the parameters passed:
8556 * - Sequence to enable CLKOUT_DP
8557 * - Sequence to enable CLKOUT_DP without spread
8558 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8559 */
8560 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8561 bool with_fdi)
8562 {
8563 struct drm_i915_private *dev_priv = dev->dev_private;
8564 uint32_t reg, tmp;
8565
8566 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8567 with_spread = true;
8568 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8569 with_fdi = false;
8570
8571 mutex_lock(&dev_priv->sb_lock);
8572
8573 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8574 tmp &= ~SBI_SSCCTL_DISABLE;
8575 tmp |= SBI_SSCCTL_PATHALT;
8576 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8577
8578 udelay(24);
8579
8580 if (with_spread) {
8581 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8582 tmp &= ~SBI_SSCCTL_PATHALT;
8583 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8584
8585 if (with_fdi) {
8586 lpt_reset_fdi_mphy(dev_priv);
8587 lpt_program_fdi_mphy(dev_priv);
8588 }
8589 }
8590
8591 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8592 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8593 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8594 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8595
8596 mutex_unlock(&dev_priv->sb_lock);
8597 }
8598
8599 /* Sequence to disable CLKOUT_DP */
8600 static void lpt_disable_clkout_dp(struct drm_device *dev)
8601 {
8602 struct drm_i915_private *dev_priv = dev->dev_private;
8603 uint32_t reg, tmp;
8604
8605 mutex_lock(&dev_priv->sb_lock);
8606
8607 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8608 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8609 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8610 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8611
8612 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8613 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8614 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8615 tmp |= SBI_SSCCTL_PATHALT;
8616 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8617 udelay(32);
8618 }
8619 tmp |= SBI_SSCCTL_DISABLE;
8620 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8621 }
8622
8623 mutex_unlock(&dev_priv->sb_lock);
8624 }
8625
8626 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8627
8628 static const uint16_t sscdivintphase[] = {
8629 [BEND_IDX( 50)] = 0x3B23,
8630 [BEND_IDX( 45)] = 0x3B23,
8631 [BEND_IDX( 40)] = 0x3C23,
8632 [BEND_IDX( 35)] = 0x3C23,
8633 [BEND_IDX( 30)] = 0x3D23,
8634 [BEND_IDX( 25)] = 0x3D23,
8635 [BEND_IDX( 20)] = 0x3E23,
8636 [BEND_IDX( 15)] = 0x3E23,
8637 [BEND_IDX( 10)] = 0x3F23,
8638 [BEND_IDX( 5)] = 0x3F23,
8639 [BEND_IDX( 0)] = 0x0025,
8640 [BEND_IDX( -5)] = 0x0025,
8641 [BEND_IDX(-10)] = 0x0125,
8642 [BEND_IDX(-15)] = 0x0125,
8643 [BEND_IDX(-20)] = 0x0225,
8644 [BEND_IDX(-25)] = 0x0225,
8645 [BEND_IDX(-30)] = 0x0325,
8646 [BEND_IDX(-35)] = 0x0325,
8647 [BEND_IDX(-40)] = 0x0425,
8648 [BEND_IDX(-45)] = 0x0425,
8649 [BEND_IDX(-50)] = 0x0525,
8650 };
8651
8652 /*
8653 * Bend CLKOUT_DP
8654 * steps -50 to 50 inclusive, in steps of 5
8655 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8656 * change in clock period = -(steps / 10) * 5.787 ps
8657 */
8658 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8659 {
8660 uint32_t tmp;
8661 int idx = BEND_IDX(steps);
8662
8663 if (WARN_ON(steps % 5 != 0))
8664 return;
8665
8666 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8667 return;
8668
8669 mutex_lock(&dev_priv->sb_lock);
8670
8671 if (steps % 10 != 0)
8672 tmp = 0xAAAAAAAB;
8673 else
8674 tmp = 0x00000000;
8675 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8676
8677 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8678 tmp &= 0xffff0000;
8679 tmp |= sscdivintphase[idx];
8680 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8681
8682 mutex_unlock(&dev_priv->sb_lock);
8683 }
8684
8685 #undef BEND_IDX
8686
8687 static void lpt_init_pch_refclk(struct drm_device *dev)
8688 {
8689 struct intel_encoder *encoder;
8690 bool has_vga = false;
8691
8692 for_each_intel_encoder(dev, encoder) {
8693 switch (encoder->type) {
8694 case INTEL_OUTPUT_ANALOG:
8695 has_vga = true;
8696 break;
8697 default:
8698 break;
8699 }
8700 }
8701
8702 if (has_vga) {
8703 lpt_bend_clkout_dp(to_i915(dev), 0);
8704 lpt_enable_clkout_dp(dev, true, true);
8705 } else {
8706 lpt_disable_clkout_dp(dev);
8707 }
8708 }
8709
8710 /*
8711 * Initialize reference clocks when the driver loads
8712 */
8713 void intel_init_pch_refclk(struct drm_device *dev)
8714 {
8715 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8716 ironlake_init_pch_refclk(dev);
8717 else if (HAS_PCH_LPT(dev))
8718 lpt_init_pch_refclk(dev);
8719 }
8720
8721 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8722 {
8723 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8725 int pipe = intel_crtc->pipe;
8726 uint32_t val;
8727
8728 val = 0;
8729
8730 switch (intel_crtc->config->pipe_bpp) {
8731 case 18:
8732 val |= PIPECONF_6BPC;
8733 break;
8734 case 24:
8735 val |= PIPECONF_8BPC;
8736 break;
8737 case 30:
8738 val |= PIPECONF_10BPC;
8739 break;
8740 case 36:
8741 val |= PIPECONF_12BPC;
8742 break;
8743 default:
8744 /* Case prevented by intel_choose_pipe_bpp_dither. */
8745 BUG();
8746 }
8747
8748 if (intel_crtc->config->dither)
8749 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8750
8751 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8752 val |= PIPECONF_INTERLACED_ILK;
8753 else
8754 val |= PIPECONF_PROGRESSIVE;
8755
8756 if (intel_crtc->config->limited_color_range)
8757 val |= PIPECONF_COLOR_RANGE_SELECT;
8758
8759 I915_WRITE(PIPECONF(pipe), val);
8760 POSTING_READ(PIPECONF(pipe));
8761 }
8762
8763 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8764 {
8765 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8767 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8768 u32 val = 0;
8769
8770 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8771 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8772
8773 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8774 val |= PIPECONF_INTERLACED_ILK;
8775 else
8776 val |= PIPECONF_PROGRESSIVE;
8777
8778 I915_WRITE(PIPECONF(cpu_transcoder), val);
8779 POSTING_READ(PIPECONF(cpu_transcoder));
8780 }
8781
8782 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8783 {
8784 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8786
8787 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8788 u32 val = 0;
8789
8790 switch (intel_crtc->config->pipe_bpp) {
8791 case 18:
8792 val |= PIPEMISC_DITHER_6_BPC;
8793 break;
8794 case 24:
8795 val |= PIPEMISC_DITHER_8_BPC;
8796 break;
8797 case 30:
8798 val |= PIPEMISC_DITHER_10_BPC;
8799 break;
8800 case 36:
8801 val |= PIPEMISC_DITHER_12_BPC;
8802 break;
8803 default:
8804 /* Case prevented by pipe_config_set_bpp. */
8805 BUG();
8806 }
8807
8808 if (intel_crtc->config->dither)
8809 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8810
8811 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8812 }
8813 }
8814
8815 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8816 {
8817 /*
8818 * Account for spread spectrum to avoid
8819 * oversubscribing the link. Max center spread
8820 * is 2.5%; use 5% for safety's sake.
8821 */
8822 u32 bps = target_clock * bpp * 21 / 20;
8823 return DIV_ROUND_UP(bps, link_bw * 8);
8824 }
8825
8826 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8827 {
8828 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8829 }
8830
8831 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8832 struct intel_crtc_state *crtc_state,
8833 struct dpll *reduced_clock)
8834 {
8835 struct drm_crtc *crtc = &intel_crtc->base;
8836 struct drm_device *dev = crtc->dev;
8837 struct drm_i915_private *dev_priv = dev->dev_private;
8838 struct drm_atomic_state *state = crtc_state->base.state;
8839 struct drm_connector *connector;
8840 struct drm_connector_state *connector_state;
8841 struct intel_encoder *encoder;
8842 u32 dpll, fp, fp2;
8843 int factor, i;
8844 bool is_lvds = false, is_sdvo = false;
8845
8846 for_each_connector_in_state(state, connector, connector_state, i) {
8847 if (connector_state->crtc != crtc_state->base.crtc)
8848 continue;
8849
8850 encoder = to_intel_encoder(connector_state->best_encoder);
8851
8852 switch (encoder->type) {
8853 case INTEL_OUTPUT_LVDS:
8854 is_lvds = true;
8855 break;
8856 case INTEL_OUTPUT_SDVO:
8857 case INTEL_OUTPUT_HDMI:
8858 is_sdvo = true;
8859 break;
8860 default:
8861 break;
8862 }
8863 }
8864
8865 /* Enable autotuning of the PLL clock (if permissible) */
8866 factor = 21;
8867 if (is_lvds) {
8868 if ((intel_panel_use_ssc(dev_priv) &&
8869 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8870 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8871 factor = 25;
8872 } else if (crtc_state->sdvo_tv_clock)
8873 factor = 20;
8874
8875 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8876
8877 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8878 fp |= FP_CB_TUNE;
8879
8880 if (reduced_clock) {
8881 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8882
8883 if (reduced_clock->m < factor * reduced_clock->n)
8884 fp2 |= FP_CB_TUNE;
8885 } else {
8886 fp2 = fp;
8887 }
8888
8889 dpll = 0;
8890
8891 if (is_lvds)
8892 dpll |= DPLLB_MODE_LVDS;
8893 else
8894 dpll |= DPLLB_MODE_DAC_SERIAL;
8895
8896 dpll |= (crtc_state->pixel_multiplier - 1)
8897 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8898
8899 if (is_sdvo)
8900 dpll |= DPLL_SDVO_HIGH_SPEED;
8901 if (crtc_state->has_dp_encoder)
8902 dpll |= DPLL_SDVO_HIGH_SPEED;
8903
8904 /* compute bitmask from p1 value */
8905 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8906 /* also FPA1 */
8907 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8908
8909 switch (crtc_state->dpll.p2) {
8910 case 5:
8911 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8912 break;
8913 case 7:
8914 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8915 break;
8916 case 10:
8917 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8918 break;
8919 case 14:
8920 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8921 break;
8922 }
8923
8924 if (is_lvds && intel_panel_use_ssc(dev_priv))
8925 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8926 else
8927 dpll |= PLL_REF_INPUT_DREFCLK;
8928
8929 dpll |= DPLL_VCO_ENABLE;
8930
8931 crtc_state->dpll_hw_state.dpll = dpll;
8932 crtc_state->dpll_hw_state.fp0 = fp;
8933 crtc_state->dpll_hw_state.fp1 = fp2;
8934 }
8935
8936 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8937 struct intel_crtc_state *crtc_state)
8938 {
8939 struct drm_device *dev = crtc->base.dev;
8940 struct drm_i915_private *dev_priv = dev->dev_private;
8941 struct dpll reduced_clock;
8942 bool has_reduced_clock = false;
8943 struct intel_shared_dpll *pll;
8944 const struct intel_limit *limit;
8945 int refclk = 120000;
8946
8947 memset(&crtc_state->dpll_hw_state, 0,
8948 sizeof(crtc_state->dpll_hw_state));
8949
8950 crtc->lowfreq_avail = false;
8951
8952 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8953 if (!crtc_state->has_pch_encoder)
8954 return 0;
8955
8956 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8957 if (intel_panel_use_ssc(dev_priv)) {
8958 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8959 dev_priv->vbt.lvds_ssc_freq);
8960 refclk = dev_priv->vbt.lvds_ssc_freq;
8961 }
8962
8963 if (intel_is_dual_link_lvds(dev)) {
8964 if (refclk == 100000)
8965 limit = &intel_limits_ironlake_dual_lvds_100m;
8966 else
8967 limit = &intel_limits_ironlake_dual_lvds;
8968 } else {
8969 if (refclk == 100000)
8970 limit = &intel_limits_ironlake_single_lvds_100m;
8971 else
8972 limit = &intel_limits_ironlake_single_lvds;
8973 }
8974 } else {
8975 limit = &intel_limits_ironlake_dac;
8976 }
8977
8978 if (!crtc_state->clock_set &&
8979 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8980 refclk, NULL, &crtc_state->dpll)) {
8981 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8982 return -EINVAL;
8983 }
8984
8985 ironlake_compute_dpll(crtc, crtc_state,
8986 has_reduced_clock ? &reduced_clock : NULL);
8987
8988 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8989 if (pll == NULL) {
8990 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8991 pipe_name(crtc->pipe));
8992 return -EINVAL;
8993 }
8994
8995 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8996 has_reduced_clock)
8997 crtc->lowfreq_avail = true;
8998
8999 return 0;
9000 }
9001
9002 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9003 struct intel_link_m_n *m_n)
9004 {
9005 struct drm_device *dev = crtc->base.dev;
9006 struct drm_i915_private *dev_priv = dev->dev_private;
9007 enum pipe pipe = crtc->pipe;
9008
9009 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9010 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9011 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9012 & ~TU_SIZE_MASK;
9013 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9014 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9015 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9016 }
9017
9018 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9019 enum transcoder transcoder,
9020 struct intel_link_m_n *m_n,
9021 struct intel_link_m_n *m2_n2)
9022 {
9023 struct drm_device *dev = crtc->base.dev;
9024 struct drm_i915_private *dev_priv = dev->dev_private;
9025 enum pipe pipe = crtc->pipe;
9026
9027 if (INTEL_INFO(dev)->gen >= 5) {
9028 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9029 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9030 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9031 & ~TU_SIZE_MASK;
9032 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9033 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9034 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9035 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9036 * gen < 8) and if DRRS is supported (to make sure the
9037 * registers are not unnecessarily read).
9038 */
9039 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9040 crtc->config->has_drrs) {
9041 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9042 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9043 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9044 & ~TU_SIZE_MASK;
9045 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9046 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9047 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9048 }
9049 } else {
9050 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9051 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9052 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9053 & ~TU_SIZE_MASK;
9054 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9055 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9056 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9057 }
9058 }
9059
9060 void intel_dp_get_m_n(struct intel_crtc *crtc,
9061 struct intel_crtc_state *pipe_config)
9062 {
9063 if (pipe_config->has_pch_encoder)
9064 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9065 else
9066 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9067 &pipe_config->dp_m_n,
9068 &pipe_config->dp_m2_n2);
9069 }
9070
9071 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9072 struct intel_crtc_state *pipe_config)
9073 {
9074 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9075 &pipe_config->fdi_m_n, NULL);
9076 }
9077
9078 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9079 struct intel_crtc_state *pipe_config)
9080 {
9081 struct drm_device *dev = crtc->base.dev;
9082 struct drm_i915_private *dev_priv = dev->dev_private;
9083 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9084 uint32_t ps_ctrl = 0;
9085 int id = -1;
9086 int i;
9087
9088 /* find scaler attached to this pipe */
9089 for (i = 0; i < crtc->num_scalers; i++) {
9090 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9091 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9092 id = i;
9093 pipe_config->pch_pfit.enabled = true;
9094 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9095 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9096 break;
9097 }
9098 }
9099
9100 scaler_state->scaler_id = id;
9101 if (id >= 0) {
9102 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9103 } else {
9104 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9105 }
9106 }
9107
9108 static void
9109 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9110 struct intel_initial_plane_config *plane_config)
9111 {
9112 struct drm_device *dev = crtc->base.dev;
9113 struct drm_i915_private *dev_priv = dev->dev_private;
9114 u32 val, base, offset, stride_mult, tiling;
9115 int pipe = crtc->pipe;
9116 int fourcc, pixel_format;
9117 unsigned int aligned_height;
9118 struct drm_framebuffer *fb;
9119 struct intel_framebuffer *intel_fb;
9120
9121 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9122 if (!intel_fb) {
9123 DRM_DEBUG_KMS("failed to alloc fb\n");
9124 return;
9125 }
9126
9127 fb = &intel_fb->base;
9128
9129 val = I915_READ(PLANE_CTL(pipe, 0));
9130 if (!(val & PLANE_CTL_ENABLE))
9131 goto error;
9132
9133 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9134 fourcc = skl_format_to_fourcc(pixel_format,
9135 val & PLANE_CTL_ORDER_RGBX,
9136 val & PLANE_CTL_ALPHA_MASK);
9137 fb->pixel_format = fourcc;
9138 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9139
9140 tiling = val & PLANE_CTL_TILED_MASK;
9141 switch (tiling) {
9142 case PLANE_CTL_TILED_LINEAR:
9143 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9144 break;
9145 case PLANE_CTL_TILED_X:
9146 plane_config->tiling = I915_TILING_X;
9147 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9148 break;
9149 case PLANE_CTL_TILED_Y:
9150 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9151 break;
9152 case PLANE_CTL_TILED_YF:
9153 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9154 break;
9155 default:
9156 MISSING_CASE(tiling);
9157 goto error;
9158 }
9159
9160 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9161 plane_config->base = base;
9162
9163 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9164
9165 val = I915_READ(PLANE_SIZE(pipe, 0));
9166 fb->height = ((val >> 16) & 0xfff) + 1;
9167 fb->width = ((val >> 0) & 0x1fff) + 1;
9168
9169 val = I915_READ(PLANE_STRIDE(pipe, 0));
9170 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9171 fb->pixel_format);
9172 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9173
9174 aligned_height = intel_fb_align_height(dev, fb->height,
9175 fb->pixel_format,
9176 fb->modifier[0]);
9177
9178 plane_config->size = fb->pitches[0] * aligned_height;
9179
9180 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9181 pipe_name(pipe), fb->width, fb->height,
9182 fb->bits_per_pixel, base, fb->pitches[0],
9183 plane_config->size);
9184
9185 plane_config->fb = intel_fb;
9186 return;
9187
9188 error:
9189 kfree(fb);
9190 }
9191
9192 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9193 struct intel_crtc_state *pipe_config)
9194 {
9195 struct drm_device *dev = crtc->base.dev;
9196 struct drm_i915_private *dev_priv = dev->dev_private;
9197 uint32_t tmp;
9198
9199 tmp = I915_READ(PF_CTL(crtc->pipe));
9200
9201 if (tmp & PF_ENABLE) {
9202 pipe_config->pch_pfit.enabled = true;
9203 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9204 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9205
9206 /* We currently do not free assignements of panel fitters on
9207 * ivb/hsw (since we don't use the higher upscaling modes which
9208 * differentiates them) so just WARN about this case for now. */
9209 if (IS_GEN7(dev)) {
9210 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9211 PF_PIPE_SEL_IVB(crtc->pipe));
9212 }
9213 }
9214 }
9215
9216 static void
9217 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9218 struct intel_initial_plane_config *plane_config)
9219 {
9220 struct drm_device *dev = crtc->base.dev;
9221 struct drm_i915_private *dev_priv = dev->dev_private;
9222 u32 val, base, offset;
9223 int pipe = crtc->pipe;
9224 int fourcc, pixel_format;
9225 unsigned int aligned_height;
9226 struct drm_framebuffer *fb;
9227 struct intel_framebuffer *intel_fb;
9228
9229 val = I915_READ(DSPCNTR(pipe));
9230 if (!(val & DISPLAY_PLANE_ENABLE))
9231 return;
9232
9233 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9234 if (!intel_fb) {
9235 DRM_DEBUG_KMS("failed to alloc fb\n");
9236 return;
9237 }
9238
9239 fb = &intel_fb->base;
9240
9241 if (INTEL_INFO(dev)->gen >= 4) {
9242 if (val & DISPPLANE_TILED) {
9243 plane_config->tiling = I915_TILING_X;
9244 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9245 }
9246 }
9247
9248 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9249 fourcc = i9xx_format_to_fourcc(pixel_format);
9250 fb->pixel_format = fourcc;
9251 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9252
9253 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9254 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9255 offset = I915_READ(DSPOFFSET(pipe));
9256 } else {
9257 if (plane_config->tiling)
9258 offset = I915_READ(DSPTILEOFF(pipe));
9259 else
9260 offset = I915_READ(DSPLINOFF(pipe));
9261 }
9262 plane_config->base = base;
9263
9264 val = I915_READ(PIPESRC(pipe));
9265 fb->width = ((val >> 16) & 0xfff) + 1;
9266 fb->height = ((val >> 0) & 0xfff) + 1;
9267
9268 val = I915_READ(DSPSTRIDE(pipe));
9269 fb->pitches[0] = val & 0xffffffc0;
9270
9271 aligned_height = intel_fb_align_height(dev, fb->height,
9272 fb->pixel_format,
9273 fb->modifier[0]);
9274
9275 plane_config->size = fb->pitches[0] * aligned_height;
9276
9277 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9278 pipe_name(pipe), fb->width, fb->height,
9279 fb->bits_per_pixel, base, fb->pitches[0],
9280 plane_config->size);
9281
9282 plane_config->fb = intel_fb;
9283 }
9284
9285 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9286 struct intel_crtc_state *pipe_config)
9287 {
9288 struct drm_device *dev = crtc->base.dev;
9289 struct drm_i915_private *dev_priv = dev->dev_private;
9290 enum intel_display_power_domain power_domain;
9291 uint32_t tmp;
9292 bool ret;
9293
9294 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9295 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9296 return false;
9297
9298 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9299 pipe_config->shared_dpll = NULL;
9300
9301 ret = false;
9302 tmp = I915_READ(PIPECONF(crtc->pipe));
9303 if (!(tmp & PIPECONF_ENABLE))
9304 goto out;
9305
9306 switch (tmp & PIPECONF_BPC_MASK) {
9307 case PIPECONF_6BPC:
9308 pipe_config->pipe_bpp = 18;
9309 break;
9310 case PIPECONF_8BPC:
9311 pipe_config->pipe_bpp = 24;
9312 break;
9313 case PIPECONF_10BPC:
9314 pipe_config->pipe_bpp = 30;
9315 break;
9316 case PIPECONF_12BPC:
9317 pipe_config->pipe_bpp = 36;
9318 break;
9319 default:
9320 break;
9321 }
9322
9323 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9324 pipe_config->limited_color_range = true;
9325
9326 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9327 struct intel_shared_dpll *pll;
9328 enum intel_dpll_id pll_id;
9329
9330 pipe_config->has_pch_encoder = true;
9331
9332 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9333 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9334 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9335
9336 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9337
9338 if (HAS_PCH_IBX(dev_priv)) {
9339 /*
9340 * The pipe->pch transcoder and pch transcoder->pll
9341 * mapping is fixed.
9342 */
9343 pll_id = (enum intel_dpll_id) crtc->pipe;
9344 } else {
9345 tmp = I915_READ(PCH_DPLL_SEL);
9346 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9347 pll_id = DPLL_ID_PCH_PLL_B;
9348 else
9349 pll_id= DPLL_ID_PCH_PLL_A;
9350 }
9351
9352 pipe_config->shared_dpll =
9353 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9354 pll = pipe_config->shared_dpll;
9355
9356 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9357 &pipe_config->dpll_hw_state));
9358
9359 tmp = pipe_config->dpll_hw_state.dpll;
9360 pipe_config->pixel_multiplier =
9361 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9362 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9363
9364 ironlake_pch_clock_get(crtc, pipe_config);
9365 } else {
9366 pipe_config->pixel_multiplier = 1;
9367 }
9368
9369 intel_get_pipe_timings(crtc, pipe_config);
9370 intel_get_pipe_src_size(crtc, pipe_config);
9371
9372 ironlake_get_pfit_config(crtc, pipe_config);
9373
9374 ret = true;
9375
9376 out:
9377 intel_display_power_put(dev_priv, power_domain);
9378
9379 return ret;
9380 }
9381
9382 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9383 {
9384 struct drm_device *dev = dev_priv->dev;
9385 struct intel_crtc *crtc;
9386
9387 for_each_intel_crtc(dev, crtc)
9388 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9389 pipe_name(crtc->pipe));
9390
9391 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9392 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9393 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9394 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9395 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9396 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9397 "CPU PWM1 enabled\n");
9398 if (IS_HASWELL(dev))
9399 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9400 "CPU PWM2 enabled\n");
9401 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9402 "PCH PWM1 enabled\n");
9403 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9404 "Utility pin enabled\n");
9405 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9406
9407 /*
9408 * In theory we can still leave IRQs enabled, as long as only the HPD
9409 * interrupts remain enabled. We used to check for that, but since it's
9410 * gen-specific and since we only disable LCPLL after we fully disable
9411 * the interrupts, the check below should be enough.
9412 */
9413 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9414 }
9415
9416 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9417 {
9418 struct drm_device *dev = dev_priv->dev;
9419
9420 if (IS_HASWELL(dev))
9421 return I915_READ(D_COMP_HSW);
9422 else
9423 return I915_READ(D_COMP_BDW);
9424 }
9425
9426 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9427 {
9428 struct drm_device *dev = dev_priv->dev;
9429
9430 if (IS_HASWELL(dev)) {
9431 mutex_lock(&dev_priv->rps.hw_lock);
9432 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9433 val))
9434 DRM_ERROR("Failed to write to D_COMP\n");
9435 mutex_unlock(&dev_priv->rps.hw_lock);
9436 } else {
9437 I915_WRITE(D_COMP_BDW, val);
9438 POSTING_READ(D_COMP_BDW);
9439 }
9440 }
9441
9442 /*
9443 * This function implements pieces of two sequences from BSpec:
9444 * - Sequence for display software to disable LCPLL
9445 * - Sequence for display software to allow package C8+
9446 * The steps implemented here are just the steps that actually touch the LCPLL
9447 * register. Callers should take care of disabling all the display engine
9448 * functions, doing the mode unset, fixing interrupts, etc.
9449 */
9450 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9451 bool switch_to_fclk, bool allow_power_down)
9452 {
9453 uint32_t val;
9454
9455 assert_can_disable_lcpll(dev_priv);
9456
9457 val = I915_READ(LCPLL_CTL);
9458
9459 if (switch_to_fclk) {
9460 val |= LCPLL_CD_SOURCE_FCLK;
9461 I915_WRITE(LCPLL_CTL, val);
9462
9463 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9464 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9465 DRM_ERROR("Switching to FCLK failed\n");
9466
9467 val = I915_READ(LCPLL_CTL);
9468 }
9469
9470 val |= LCPLL_PLL_DISABLE;
9471 I915_WRITE(LCPLL_CTL, val);
9472 POSTING_READ(LCPLL_CTL);
9473
9474 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9475 DRM_ERROR("LCPLL still locked\n");
9476
9477 val = hsw_read_dcomp(dev_priv);
9478 val |= D_COMP_COMP_DISABLE;
9479 hsw_write_dcomp(dev_priv, val);
9480 ndelay(100);
9481
9482 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9483 1))
9484 DRM_ERROR("D_COMP RCOMP still in progress\n");
9485
9486 if (allow_power_down) {
9487 val = I915_READ(LCPLL_CTL);
9488 val |= LCPLL_POWER_DOWN_ALLOW;
9489 I915_WRITE(LCPLL_CTL, val);
9490 POSTING_READ(LCPLL_CTL);
9491 }
9492 }
9493
9494 /*
9495 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9496 * source.
9497 */
9498 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9499 {
9500 uint32_t val;
9501
9502 val = I915_READ(LCPLL_CTL);
9503
9504 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9505 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9506 return;
9507
9508 /*
9509 * Make sure we're not on PC8 state before disabling PC8, otherwise
9510 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9511 */
9512 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9513
9514 if (val & LCPLL_POWER_DOWN_ALLOW) {
9515 val &= ~LCPLL_POWER_DOWN_ALLOW;
9516 I915_WRITE(LCPLL_CTL, val);
9517 POSTING_READ(LCPLL_CTL);
9518 }
9519
9520 val = hsw_read_dcomp(dev_priv);
9521 val |= D_COMP_COMP_FORCE;
9522 val &= ~D_COMP_COMP_DISABLE;
9523 hsw_write_dcomp(dev_priv, val);
9524
9525 val = I915_READ(LCPLL_CTL);
9526 val &= ~LCPLL_PLL_DISABLE;
9527 I915_WRITE(LCPLL_CTL, val);
9528
9529 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9530 DRM_ERROR("LCPLL not locked yet\n");
9531
9532 if (val & LCPLL_CD_SOURCE_FCLK) {
9533 val = I915_READ(LCPLL_CTL);
9534 val &= ~LCPLL_CD_SOURCE_FCLK;
9535 I915_WRITE(LCPLL_CTL, val);
9536
9537 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9538 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9539 DRM_ERROR("Switching back to LCPLL failed\n");
9540 }
9541
9542 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9543 intel_update_cdclk(dev_priv->dev);
9544 }
9545
9546 /*
9547 * Package states C8 and deeper are really deep PC states that can only be
9548 * reached when all the devices on the system allow it, so even if the graphics
9549 * device allows PC8+, it doesn't mean the system will actually get to these
9550 * states. Our driver only allows PC8+ when going into runtime PM.
9551 *
9552 * The requirements for PC8+ are that all the outputs are disabled, the power
9553 * well is disabled and most interrupts are disabled, and these are also
9554 * requirements for runtime PM. When these conditions are met, we manually do
9555 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9556 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9557 * hang the machine.
9558 *
9559 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9560 * the state of some registers, so when we come back from PC8+ we need to
9561 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9562 * need to take care of the registers kept by RC6. Notice that this happens even
9563 * if we don't put the device in PCI D3 state (which is what currently happens
9564 * because of the runtime PM support).
9565 *
9566 * For more, read "Display Sequences for Package C8" on the hardware
9567 * documentation.
9568 */
9569 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9570 {
9571 struct drm_device *dev = dev_priv->dev;
9572 uint32_t val;
9573
9574 DRM_DEBUG_KMS("Enabling package C8+\n");
9575
9576 if (HAS_PCH_LPT_LP(dev)) {
9577 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9578 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9579 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9580 }
9581
9582 lpt_disable_clkout_dp(dev);
9583 hsw_disable_lcpll(dev_priv, true, true);
9584 }
9585
9586 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9587 {
9588 struct drm_device *dev = dev_priv->dev;
9589 uint32_t val;
9590
9591 DRM_DEBUG_KMS("Disabling package C8+\n");
9592
9593 hsw_restore_lcpll(dev_priv);
9594 lpt_init_pch_refclk(dev);
9595
9596 if (HAS_PCH_LPT_LP(dev)) {
9597 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9598 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9599 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9600 }
9601 }
9602
9603 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9604 {
9605 struct drm_device *dev = old_state->dev;
9606 struct intel_atomic_state *old_intel_state =
9607 to_intel_atomic_state(old_state);
9608 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9609
9610 broxton_set_cdclk(to_i915(dev), req_cdclk);
9611 }
9612
9613 /* compute the max rate for new configuration */
9614 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9615 {
9616 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9617 struct drm_i915_private *dev_priv = state->dev->dev_private;
9618 struct drm_crtc *crtc;
9619 struct drm_crtc_state *cstate;
9620 struct intel_crtc_state *crtc_state;
9621 unsigned max_pixel_rate = 0, i;
9622 enum pipe pipe;
9623
9624 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9625 sizeof(intel_state->min_pixclk));
9626
9627 for_each_crtc_in_state(state, crtc, cstate, i) {
9628 int pixel_rate;
9629
9630 crtc_state = to_intel_crtc_state(cstate);
9631 if (!crtc_state->base.enable) {
9632 intel_state->min_pixclk[i] = 0;
9633 continue;
9634 }
9635
9636 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9637
9638 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9639 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9640 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9641
9642 intel_state->min_pixclk[i] = pixel_rate;
9643 }
9644
9645 for_each_pipe(dev_priv, pipe)
9646 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9647
9648 return max_pixel_rate;
9649 }
9650
9651 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9652 {
9653 struct drm_i915_private *dev_priv = dev->dev_private;
9654 uint32_t val, data;
9655 int ret;
9656
9657 if (WARN((I915_READ(LCPLL_CTL) &
9658 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9659 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9660 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9661 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9662 "trying to change cdclk frequency with cdclk not enabled\n"))
9663 return;
9664
9665 mutex_lock(&dev_priv->rps.hw_lock);
9666 ret = sandybridge_pcode_write(dev_priv,
9667 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9668 mutex_unlock(&dev_priv->rps.hw_lock);
9669 if (ret) {
9670 DRM_ERROR("failed to inform pcode about cdclk change\n");
9671 return;
9672 }
9673
9674 val = I915_READ(LCPLL_CTL);
9675 val |= LCPLL_CD_SOURCE_FCLK;
9676 I915_WRITE(LCPLL_CTL, val);
9677
9678 if (wait_for_us(I915_READ(LCPLL_CTL) &
9679 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9680 DRM_ERROR("Switching to FCLK failed\n");
9681
9682 val = I915_READ(LCPLL_CTL);
9683 val &= ~LCPLL_CLK_FREQ_MASK;
9684
9685 switch (cdclk) {
9686 case 450000:
9687 val |= LCPLL_CLK_FREQ_450;
9688 data = 0;
9689 break;
9690 case 540000:
9691 val |= LCPLL_CLK_FREQ_54O_BDW;
9692 data = 1;
9693 break;
9694 case 337500:
9695 val |= LCPLL_CLK_FREQ_337_5_BDW;
9696 data = 2;
9697 break;
9698 case 675000:
9699 val |= LCPLL_CLK_FREQ_675_BDW;
9700 data = 3;
9701 break;
9702 default:
9703 WARN(1, "invalid cdclk frequency\n");
9704 return;
9705 }
9706
9707 I915_WRITE(LCPLL_CTL, val);
9708
9709 val = I915_READ(LCPLL_CTL);
9710 val &= ~LCPLL_CD_SOURCE_FCLK;
9711 I915_WRITE(LCPLL_CTL, val);
9712
9713 if (wait_for_us((I915_READ(LCPLL_CTL) &
9714 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9715 DRM_ERROR("Switching back to LCPLL failed\n");
9716
9717 mutex_lock(&dev_priv->rps.hw_lock);
9718 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9719 mutex_unlock(&dev_priv->rps.hw_lock);
9720
9721 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9722
9723 intel_update_cdclk(dev);
9724
9725 WARN(cdclk != dev_priv->cdclk_freq,
9726 "cdclk requested %d kHz but got %d kHz\n",
9727 cdclk, dev_priv->cdclk_freq);
9728 }
9729
9730 static int broadwell_calc_cdclk(int max_pixclk)
9731 {
9732 if (max_pixclk > 540000)
9733 return 675000;
9734 else if (max_pixclk > 450000)
9735 return 540000;
9736 else if (max_pixclk > 337500)
9737 return 450000;
9738 else
9739 return 337500;
9740 }
9741
9742 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9743 {
9744 struct drm_i915_private *dev_priv = to_i915(state->dev);
9745 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9746 int max_pixclk = ilk_max_pixel_rate(state);
9747 int cdclk;
9748
9749 /*
9750 * FIXME should also account for plane ratio
9751 * once 64bpp pixel formats are supported.
9752 */
9753 cdclk = broadwell_calc_cdclk(max_pixclk);
9754
9755 if (cdclk > dev_priv->max_cdclk_freq) {
9756 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9757 cdclk, dev_priv->max_cdclk_freq);
9758 return -EINVAL;
9759 }
9760
9761 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9762 if (!intel_state->active_crtcs)
9763 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9764
9765 return 0;
9766 }
9767
9768 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9769 {
9770 struct drm_device *dev = old_state->dev;
9771 struct intel_atomic_state *old_intel_state =
9772 to_intel_atomic_state(old_state);
9773 unsigned req_cdclk = old_intel_state->dev_cdclk;
9774
9775 broadwell_set_cdclk(dev, req_cdclk);
9776 }
9777
9778 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9779 {
9780 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9781 struct drm_i915_private *dev_priv = to_i915(state->dev);
9782 const int max_pixclk = ilk_max_pixel_rate(state);
9783 int vco = intel_state->cdclk_pll_vco;
9784 int cdclk;
9785
9786 /*
9787 * FIXME should also account for plane ratio
9788 * once 64bpp pixel formats are supported.
9789 */
9790 cdclk = skl_calc_cdclk(max_pixclk, vco);
9791
9792 /*
9793 * FIXME move the cdclk caclulation to
9794 * compute_config() so we can fail gracegully.
9795 */
9796 if (cdclk > dev_priv->max_cdclk_freq) {
9797 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9798 cdclk, dev_priv->max_cdclk_freq);
9799 cdclk = dev_priv->max_cdclk_freq;
9800 }
9801
9802 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9803 if (!intel_state->active_crtcs)
9804 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
9805
9806 return 0;
9807 }
9808
9809 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9810 {
9811 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9812 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9813 unsigned int req_cdclk = intel_state->dev_cdclk;
9814 unsigned int req_vco = intel_state->cdclk_pll_vco;
9815
9816 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
9817 }
9818
9819 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9820 struct intel_crtc_state *crtc_state)
9821 {
9822 struct intel_encoder *intel_encoder =
9823 intel_ddi_get_crtc_new_encoder(crtc_state);
9824
9825 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9826 if (!intel_ddi_pll_select(crtc, crtc_state))
9827 return -EINVAL;
9828 }
9829
9830 crtc->lowfreq_avail = false;
9831
9832 return 0;
9833 }
9834
9835 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9836 enum port port,
9837 struct intel_crtc_state *pipe_config)
9838 {
9839 enum intel_dpll_id id;
9840
9841 switch (port) {
9842 case PORT_A:
9843 pipe_config->ddi_pll_sel = SKL_DPLL0;
9844 id = DPLL_ID_SKL_DPLL0;
9845 break;
9846 case PORT_B:
9847 pipe_config->ddi_pll_sel = SKL_DPLL1;
9848 id = DPLL_ID_SKL_DPLL1;
9849 break;
9850 case PORT_C:
9851 pipe_config->ddi_pll_sel = SKL_DPLL2;
9852 id = DPLL_ID_SKL_DPLL2;
9853 break;
9854 default:
9855 DRM_ERROR("Incorrect port type\n");
9856 return;
9857 }
9858
9859 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9860 }
9861
9862 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9863 enum port port,
9864 struct intel_crtc_state *pipe_config)
9865 {
9866 enum intel_dpll_id id;
9867 u32 temp;
9868
9869 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9870 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9871
9872 switch (pipe_config->ddi_pll_sel) {
9873 case SKL_DPLL0:
9874 id = DPLL_ID_SKL_DPLL0;
9875 break;
9876 case SKL_DPLL1:
9877 id = DPLL_ID_SKL_DPLL1;
9878 break;
9879 case SKL_DPLL2:
9880 id = DPLL_ID_SKL_DPLL2;
9881 break;
9882 case SKL_DPLL3:
9883 id = DPLL_ID_SKL_DPLL3;
9884 break;
9885 default:
9886 MISSING_CASE(pipe_config->ddi_pll_sel);
9887 return;
9888 }
9889
9890 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9891 }
9892
9893 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9894 enum port port,
9895 struct intel_crtc_state *pipe_config)
9896 {
9897 enum intel_dpll_id id;
9898
9899 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9900
9901 switch (pipe_config->ddi_pll_sel) {
9902 case PORT_CLK_SEL_WRPLL1:
9903 id = DPLL_ID_WRPLL1;
9904 break;
9905 case PORT_CLK_SEL_WRPLL2:
9906 id = DPLL_ID_WRPLL2;
9907 break;
9908 case PORT_CLK_SEL_SPLL:
9909 id = DPLL_ID_SPLL;
9910 break;
9911 case PORT_CLK_SEL_LCPLL_810:
9912 id = DPLL_ID_LCPLL_810;
9913 break;
9914 case PORT_CLK_SEL_LCPLL_1350:
9915 id = DPLL_ID_LCPLL_1350;
9916 break;
9917 case PORT_CLK_SEL_LCPLL_2700:
9918 id = DPLL_ID_LCPLL_2700;
9919 break;
9920 default:
9921 MISSING_CASE(pipe_config->ddi_pll_sel);
9922 /* fall through */
9923 case PORT_CLK_SEL_NONE:
9924 return;
9925 }
9926
9927 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9928 }
9929
9930 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9931 struct intel_crtc_state *pipe_config,
9932 unsigned long *power_domain_mask)
9933 {
9934 struct drm_device *dev = crtc->base.dev;
9935 struct drm_i915_private *dev_priv = dev->dev_private;
9936 enum intel_display_power_domain power_domain;
9937 u32 tmp;
9938
9939 /*
9940 * The pipe->transcoder mapping is fixed with the exception of the eDP
9941 * transcoder handled below.
9942 */
9943 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9944
9945 /*
9946 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9947 * consistency and less surprising code; it's in always on power).
9948 */
9949 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9950 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9951 enum pipe trans_edp_pipe;
9952 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9953 default:
9954 WARN(1, "unknown pipe linked to edp transcoder\n");
9955 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9956 case TRANS_DDI_EDP_INPUT_A_ON:
9957 trans_edp_pipe = PIPE_A;
9958 break;
9959 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9960 trans_edp_pipe = PIPE_B;
9961 break;
9962 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9963 trans_edp_pipe = PIPE_C;
9964 break;
9965 }
9966
9967 if (trans_edp_pipe == crtc->pipe)
9968 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9969 }
9970
9971 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9972 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9973 return false;
9974 *power_domain_mask |= BIT(power_domain);
9975
9976 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9977
9978 return tmp & PIPECONF_ENABLE;
9979 }
9980
9981 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9982 struct intel_crtc_state *pipe_config,
9983 unsigned long *power_domain_mask)
9984 {
9985 struct drm_device *dev = crtc->base.dev;
9986 struct drm_i915_private *dev_priv = dev->dev_private;
9987 enum intel_display_power_domain power_domain;
9988 enum port port;
9989 enum transcoder cpu_transcoder;
9990 u32 tmp;
9991
9992 pipe_config->has_dsi_encoder = false;
9993
9994 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9995 if (port == PORT_A)
9996 cpu_transcoder = TRANSCODER_DSI_A;
9997 else
9998 cpu_transcoder = TRANSCODER_DSI_C;
9999
10000 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10001 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10002 continue;
10003 *power_domain_mask |= BIT(power_domain);
10004
10005 /*
10006 * The PLL needs to be enabled with a valid divider
10007 * configuration, otherwise accessing DSI registers will hang
10008 * the machine. See BSpec North Display Engine
10009 * registers/MIPI[BXT]. We can break out here early, since we
10010 * need the same DSI PLL to be enabled for both DSI ports.
10011 */
10012 if (!intel_dsi_pll_is_enabled(dev_priv))
10013 break;
10014
10015 /* XXX: this works for video mode only */
10016 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10017 if (!(tmp & DPI_ENABLE))
10018 continue;
10019
10020 tmp = I915_READ(MIPI_CTRL(port));
10021 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10022 continue;
10023
10024 pipe_config->cpu_transcoder = cpu_transcoder;
10025 pipe_config->has_dsi_encoder = true;
10026 break;
10027 }
10028
10029 return pipe_config->has_dsi_encoder;
10030 }
10031
10032 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10033 struct intel_crtc_state *pipe_config)
10034 {
10035 struct drm_device *dev = crtc->base.dev;
10036 struct drm_i915_private *dev_priv = dev->dev_private;
10037 struct intel_shared_dpll *pll;
10038 enum port port;
10039 uint32_t tmp;
10040
10041 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10042
10043 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10044
10045 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10046 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10047 else if (IS_BROXTON(dev))
10048 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10049 else
10050 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10051
10052 pll = pipe_config->shared_dpll;
10053 if (pll) {
10054 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10055 &pipe_config->dpll_hw_state));
10056 }
10057
10058 /*
10059 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10060 * DDI E. So just check whether this pipe is wired to DDI E and whether
10061 * the PCH transcoder is on.
10062 */
10063 if (INTEL_INFO(dev)->gen < 9 &&
10064 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10065 pipe_config->has_pch_encoder = true;
10066
10067 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10068 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10069 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10070
10071 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10072 }
10073 }
10074
10075 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10076 struct intel_crtc_state *pipe_config)
10077 {
10078 struct drm_device *dev = crtc->base.dev;
10079 struct drm_i915_private *dev_priv = dev->dev_private;
10080 enum intel_display_power_domain power_domain;
10081 unsigned long power_domain_mask;
10082 bool active;
10083
10084 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10085 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10086 return false;
10087 power_domain_mask = BIT(power_domain);
10088
10089 pipe_config->shared_dpll = NULL;
10090
10091 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10092
10093 if (IS_BROXTON(dev_priv)) {
10094 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10095 &power_domain_mask);
10096 WARN_ON(active && pipe_config->has_dsi_encoder);
10097 if (pipe_config->has_dsi_encoder)
10098 active = true;
10099 }
10100
10101 if (!active)
10102 goto out;
10103
10104 if (!pipe_config->has_dsi_encoder) {
10105 haswell_get_ddi_port_state(crtc, pipe_config);
10106 intel_get_pipe_timings(crtc, pipe_config);
10107 }
10108
10109 intel_get_pipe_src_size(crtc, pipe_config);
10110
10111 pipe_config->gamma_mode =
10112 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10113
10114 if (INTEL_INFO(dev)->gen >= 9) {
10115 skl_init_scalers(dev, crtc, pipe_config);
10116 }
10117
10118 if (INTEL_INFO(dev)->gen >= 9) {
10119 pipe_config->scaler_state.scaler_id = -1;
10120 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10121 }
10122
10123 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10124 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10125 power_domain_mask |= BIT(power_domain);
10126 if (INTEL_INFO(dev)->gen >= 9)
10127 skylake_get_pfit_config(crtc, pipe_config);
10128 else
10129 ironlake_get_pfit_config(crtc, pipe_config);
10130 }
10131
10132 if (IS_HASWELL(dev))
10133 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10134 (I915_READ(IPS_CTL) & IPS_ENABLE);
10135
10136 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10137 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10138 pipe_config->pixel_multiplier =
10139 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10140 } else {
10141 pipe_config->pixel_multiplier = 1;
10142 }
10143
10144 out:
10145 for_each_power_domain(power_domain, power_domain_mask)
10146 intel_display_power_put(dev_priv, power_domain);
10147
10148 return active;
10149 }
10150
10151 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10152 const struct intel_plane_state *plane_state)
10153 {
10154 struct drm_device *dev = crtc->dev;
10155 struct drm_i915_private *dev_priv = dev->dev_private;
10156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10157 uint32_t cntl = 0, size = 0;
10158
10159 if (plane_state && plane_state->visible) {
10160 unsigned int width = plane_state->base.crtc_w;
10161 unsigned int height = plane_state->base.crtc_h;
10162 unsigned int stride = roundup_pow_of_two(width) * 4;
10163
10164 switch (stride) {
10165 default:
10166 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10167 width, stride);
10168 stride = 256;
10169 /* fallthrough */
10170 case 256:
10171 case 512:
10172 case 1024:
10173 case 2048:
10174 break;
10175 }
10176
10177 cntl |= CURSOR_ENABLE |
10178 CURSOR_GAMMA_ENABLE |
10179 CURSOR_FORMAT_ARGB |
10180 CURSOR_STRIDE(stride);
10181
10182 size = (height << 12) | width;
10183 }
10184
10185 if (intel_crtc->cursor_cntl != 0 &&
10186 (intel_crtc->cursor_base != base ||
10187 intel_crtc->cursor_size != size ||
10188 intel_crtc->cursor_cntl != cntl)) {
10189 /* On these chipsets we can only modify the base/size/stride
10190 * whilst the cursor is disabled.
10191 */
10192 I915_WRITE(CURCNTR(PIPE_A), 0);
10193 POSTING_READ(CURCNTR(PIPE_A));
10194 intel_crtc->cursor_cntl = 0;
10195 }
10196
10197 if (intel_crtc->cursor_base != base) {
10198 I915_WRITE(CURBASE(PIPE_A), base);
10199 intel_crtc->cursor_base = base;
10200 }
10201
10202 if (intel_crtc->cursor_size != size) {
10203 I915_WRITE(CURSIZE, size);
10204 intel_crtc->cursor_size = size;
10205 }
10206
10207 if (intel_crtc->cursor_cntl != cntl) {
10208 I915_WRITE(CURCNTR(PIPE_A), cntl);
10209 POSTING_READ(CURCNTR(PIPE_A));
10210 intel_crtc->cursor_cntl = cntl;
10211 }
10212 }
10213
10214 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10215 const struct intel_plane_state *plane_state)
10216 {
10217 struct drm_device *dev = crtc->dev;
10218 struct drm_i915_private *dev_priv = dev->dev_private;
10219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10220 int pipe = intel_crtc->pipe;
10221 uint32_t cntl = 0;
10222
10223 if (plane_state && plane_state->visible) {
10224 cntl = MCURSOR_GAMMA_ENABLE;
10225 switch (plane_state->base.crtc_w) {
10226 case 64:
10227 cntl |= CURSOR_MODE_64_ARGB_AX;
10228 break;
10229 case 128:
10230 cntl |= CURSOR_MODE_128_ARGB_AX;
10231 break;
10232 case 256:
10233 cntl |= CURSOR_MODE_256_ARGB_AX;
10234 break;
10235 default:
10236 MISSING_CASE(plane_state->base.crtc_w);
10237 return;
10238 }
10239 cntl |= pipe << 28; /* Connect to correct pipe */
10240
10241 if (HAS_DDI(dev))
10242 cntl |= CURSOR_PIPE_CSC_ENABLE;
10243
10244 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10245 cntl |= CURSOR_ROTATE_180;
10246 }
10247
10248 if (intel_crtc->cursor_cntl != cntl) {
10249 I915_WRITE(CURCNTR(pipe), cntl);
10250 POSTING_READ(CURCNTR(pipe));
10251 intel_crtc->cursor_cntl = cntl;
10252 }
10253
10254 /* and commit changes on next vblank */
10255 I915_WRITE(CURBASE(pipe), base);
10256 POSTING_READ(CURBASE(pipe));
10257
10258 intel_crtc->cursor_base = base;
10259 }
10260
10261 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10262 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10263 const struct intel_plane_state *plane_state)
10264 {
10265 struct drm_device *dev = crtc->dev;
10266 struct drm_i915_private *dev_priv = dev->dev_private;
10267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10268 int pipe = intel_crtc->pipe;
10269 u32 base = intel_crtc->cursor_addr;
10270 u32 pos = 0;
10271
10272 if (plane_state) {
10273 int x = plane_state->base.crtc_x;
10274 int y = plane_state->base.crtc_y;
10275
10276 if (x < 0) {
10277 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10278 x = -x;
10279 }
10280 pos |= x << CURSOR_X_SHIFT;
10281
10282 if (y < 0) {
10283 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10284 y = -y;
10285 }
10286 pos |= y << CURSOR_Y_SHIFT;
10287
10288 /* ILK+ do this automagically */
10289 if (HAS_GMCH_DISPLAY(dev) &&
10290 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10291 base += (plane_state->base.crtc_h *
10292 plane_state->base.crtc_w - 1) * 4;
10293 }
10294 }
10295
10296 I915_WRITE(CURPOS(pipe), pos);
10297
10298 if (IS_845G(dev) || IS_I865G(dev))
10299 i845_update_cursor(crtc, base, plane_state);
10300 else
10301 i9xx_update_cursor(crtc, base, plane_state);
10302 }
10303
10304 static bool cursor_size_ok(struct drm_device *dev,
10305 uint32_t width, uint32_t height)
10306 {
10307 if (width == 0 || height == 0)
10308 return false;
10309
10310 /*
10311 * 845g/865g are special in that they are only limited by
10312 * the width of their cursors, the height is arbitrary up to
10313 * the precision of the register. Everything else requires
10314 * square cursors, limited to a few power-of-two sizes.
10315 */
10316 if (IS_845G(dev) || IS_I865G(dev)) {
10317 if ((width & 63) != 0)
10318 return false;
10319
10320 if (width > (IS_845G(dev) ? 64 : 512))
10321 return false;
10322
10323 if (height > 1023)
10324 return false;
10325 } else {
10326 switch (width | height) {
10327 case 256:
10328 case 128:
10329 if (IS_GEN2(dev))
10330 return false;
10331 case 64:
10332 break;
10333 default:
10334 return false;
10335 }
10336 }
10337
10338 return true;
10339 }
10340
10341 /* VESA 640x480x72Hz mode to set on the pipe */
10342 static struct drm_display_mode load_detect_mode = {
10343 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10344 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10345 };
10346
10347 struct drm_framebuffer *
10348 __intel_framebuffer_create(struct drm_device *dev,
10349 struct drm_mode_fb_cmd2 *mode_cmd,
10350 struct drm_i915_gem_object *obj)
10351 {
10352 struct intel_framebuffer *intel_fb;
10353 int ret;
10354
10355 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10356 if (!intel_fb)
10357 return ERR_PTR(-ENOMEM);
10358
10359 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10360 if (ret)
10361 goto err;
10362
10363 return &intel_fb->base;
10364
10365 err:
10366 kfree(intel_fb);
10367 return ERR_PTR(ret);
10368 }
10369
10370 static struct drm_framebuffer *
10371 intel_framebuffer_create(struct drm_device *dev,
10372 struct drm_mode_fb_cmd2 *mode_cmd,
10373 struct drm_i915_gem_object *obj)
10374 {
10375 struct drm_framebuffer *fb;
10376 int ret;
10377
10378 ret = i915_mutex_lock_interruptible(dev);
10379 if (ret)
10380 return ERR_PTR(ret);
10381 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10382 mutex_unlock(&dev->struct_mutex);
10383
10384 return fb;
10385 }
10386
10387 static u32
10388 intel_framebuffer_pitch_for_width(int width, int bpp)
10389 {
10390 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10391 return ALIGN(pitch, 64);
10392 }
10393
10394 static u32
10395 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10396 {
10397 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10398 return PAGE_ALIGN(pitch * mode->vdisplay);
10399 }
10400
10401 static struct drm_framebuffer *
10402 intel_framebuffer_create_for_mode(struct drm_device *dev,
10403 struct drm_display_mode *mode,
10404 int depth, int bpp)
10405 {
10406 struct drm_framebuffer *fb;
10407 struct drm_i915_gem_object *obj;
10408 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10409
10410 obj = i915_gem_object_create(dev,
10411 intel_framebuffer_size_for_mode(mode, bpp));
10412 if (IS_ERR(obj))
10413 return ERR_CAST(obj);
10414
10415 mode_cmd.width = mode->hdisplay;
10416 mode_cmd.height = mode->vdisplay;
10417 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10418 bpp);
10419 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10420
10421 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10422 if (IS_ERR(fb))
10423 drm_gem_object_unreference_unlocked(&obj->base);
10424
10425 return fb;
10426 }
10427
10428 static struct drm_framebuffer *
10429 mode_fits_in_fbdev(struct drm_device *dev,
10430 struct drm_display_mode *mode)
10431 {
10432 #ifdef CONFIG_DRM_FBDEV_EMULATION
10433 struct drm_i915_private *dev_priv = dev->dev_private;
10434 struct drm_i915_gem_object *obj;
10435 struct drm_framebuffer *fb;
10436
10437 if (!dev_priv->fbdev)
10438 return NULL;
10439
10440 if (!dev_priv->fbdev->fb)
10441 return NULL;
10442
10443 obj = dev_priv->fbdev->fb->obj;
10444 BUG_ON(!obj);
10445
10446 fb = &dev_priv->fbdev->fb->base;
10447 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10448 fb->bits_per_pixel))
10449 return NULL;
10450
10451 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10452 return NULL;
10453
10454 drm_framebuffer_reference(fb);
10455 return fb;
10456 #else
10457 return NULL;
10458 #endif
10459 }
10460
10461 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10462 struct drm_crtc *crtc,
10463 struct drm_display_mode *mode,
10464 struct drm_framebuffer *fb,
10465 int x, int y)
10466 {
10467 struct drm_plane_state *plane_state;
10468 int hdisplay, vdisplay;
10469 int ret;
10470
10471 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10472 if (IS_ERR(plane_state))
10473 return PTR_ERR(plane_state);
10474
10475 if (mode)
10476 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10477 else
10478 hdisplay = vdisplay = 0;
10479
10480 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10481 if (ret)
10482 return ret;
10483 drm_atomic_set_fb_for_plane(plane_state, fb);
10484 plane_state->crtc_x = 0;
10485 plane_state->crtc_y = 0;
10486 plane_state->crtc_w = hdisplay;
10487 plane_state->crtc_h = vdisplay;
10488 plane_state->src_x = x << 16;
10489 plane_state->src_y = y << 16;
10490 plane_state->src_w = hdisplay << 16;
10491 plane_state->src_h = vdisplay << 16;
10492
10493 return 0;
10494 }
10495
10496 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10497 struct drm_display_mode *mode,
10498 struct intel_load_detect_pipe *old,
10499 struct drm_modeset_acquire_ctx *ctx)
10500 {
10501 struct intel_crtc *intel_crtc;
10502 struct intel_encoder *intel_encoder =
10503 intel_attached_encoder(connector);
10504 struct drm_crtc *possible_crtc;
10505 struct drm_encoder *encoder = &intel_encoder->base;
10506 struct drm_crtc *crtc = NULL;
10507 struct drm_device *dev = encoder->dev;
10508 struct drm_framebuffer *fb;
10509 struct drm_mode_config *config = &dev->mode_config;
10510 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10511 struct drm_connector_state *connector_state;
10512 struct intel_crtc_state *crtc_state;
10513 int ret, i = -1;
10514
10515 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10516 connector->base.id, connector->name,
10517 encoder->base.id, encoder->name);
10518
10519 old->restore_state = NULL;
10520
10521 retry:
10522 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10523 if (ret)
10524 goto fail;
10525
10526 /*
10527 * Algorithm gets a little messy:
10528 *
10529 * - if the connector already has an assigned crtc, use it (but make
10530 * sure it's on first)
10531 *
10532 * - try to find the first unused crtc that can drive this connector,
10533 * and use that if we find one
10534 */
10535
10536 /* See if we already have a CRTC for this connector */
10537 if (connector->state->crtc) {
10538 crtc = connector->state->crtc;
10539
10540 ret = drm_modeset_lock(&crtc->mutex, ctx);
10541 if (ret)
10542 goto fail;
10543
10544 /* Make sure the crtc and connector are running */
10545 goto found;
10546 }
10547
10548 /* Find an unused one (if possible) */
10549 for_each_crtc(dev, possible_crtc) {
10550 i++;
10551 if (!(encoder->possible_crtcs & (1 << i)))
10552 continue;
10553
10554 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10555 if (ret)
10556 goto fail;
10557
10558 if (possible_crtc->state->enable) {
10559 drm_modeset_unlock(&possible_crtc->mutex);
10560 continue;
10561 }
10562
10563 crtc = possible_crtc;
10564 break;
10565 }
10566
10567 /*
10568 * If we didn't find an unused CRTC, don't use any.
10569 */
10570 if (!crtc) {
10571 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10572 goto fail;
10573 }
10574
10575 found:
10576 intel_crtc = to_intel_crtc(crtc);
10577
10578 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10579 if (ret)
10580 goto fail;
10581
10582 state = drm_atomic_state_alloc(dev);
10583 restore_state = drm_atomic_state_alloc(dev);
10584 if (!state || !restore_state) {
10585 ret = -ENOMEM;
10586 goto fail;
10587 }
10588
10589 state->acquire_ctx = ctx;
10590 restore_state->acquire_ctx = ctx;
10591
10592 connector_state = drm_atomic_get_connector_state(state, connector);
10593 if (IS_ERR(connector_state)) {
10594 ret = PTR_ERR(connector_state);
10595 goto fail;
10596 }
10597
10598 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10599 if (ret)
10600 goto fail;
10601
10602 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10603 if (IS_ERR(crtc_state)) {
10604 ret = PTR_ERR(crtc_state);
10605 goto fail;
10606 }
10607
10608 crtc_state->base.active = crtc_state->base.enable = true;
10609
10610 if (!mode)
10611 mode = &load_detect_mode;
10612
10613 /* We need a framebuffer large enough to accommodate all accesses
10614 * that the plane may generate whilst we perform load detection.
10615 * We can not rely on the fbcon either being present (we get called
10616 * during its initialisation to detect all boot displays, or it may
10617 * not even exist) or that it is large enough to satisfy the
10618 * requested mode.
10619 */
10620 fb = mode_fits_in_fbdev(dev, mode);
10621 if (fb == NULL) {
10622 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10623 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10624 } else
10625 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10626 if (IS_ERR(fb)) {
10627 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10628 goto fail;
10629 }
10630
10631 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10632 if (ret)
10633 goto fail;
10634
10635 drm_framebuffer_unreference(fb);
10636
10637 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10638 if (ret)
10639 goto fail;
10640
10641 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10642 if (!ret)
10643 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10644 if (!ret)
10645 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10646 if (ret) {
10647 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10648 goto fail;
10649 }
10650
10651 ret = drm_atomic_commit(state);
10652 if (ret) {
10653 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10654 goto fail;
10655 }
10656
10657 old->restore_state = restore_state;
10658
10659 /* let the connector get through one full cycle before testing */
10660 intel_wait_for_vblank(dev, intel_crtc->pipe);
10661 return true;
10662
10663 fail:
10664 drm_atomic_state_free(state);
10665 drm_atomic_state_free(restore_state);
10666 restore_state = state = NULL;
10667
10668 if (ret == -EDEADLK) {
10669 drm_modeset_backoff(ctx);
10670 goto retry;
10671 }
10672
10673 return false;
10674 }
10675
10676 void intel_release_load_detect_pipe(struct drm_connector *connector,
10677 struct intel_load_detect_pipe *old,
10678 struct drm_modeset_acquire_ctx *ctx)
10679 {
10680 struct intel_encoder *intel_encoder =
10681 intel_attached_encoder(connector);
10682 struct drm_encoder *encoder = &intel_encoder->base;
10683 struct drm_atomic_state *state = old->restore_state;
10684 int ret;
10685
10686 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10687 connector->base.id, connector->name,
10688 encoder->base.id, encoder->name);
10689
10690 if (!state)
10691 return;
10692
10693 ret = drm_atomic_commit(state);
10694 if (ret) {
10695 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10696 drm_atomic_state_free(state);
10697 }
10698 }
10699
10700 static int i9xx_pll_refclk(struct drm_device *dev,
10701 const struct intel_crtc_state *pipe_config)
10702 {
10703 struct drm_i915_private *dev_priv = dev->dev_private;
10704 u32 dpll = pipe_config->dpll_hw_state.dpll;
10705
10706 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10707 return dev_priv->vbt.lvds_ssc_freq;
10708 else if (HAS_PCH_SPLIT(dev))
10709 return 120000;
10710 else if (!IS_GEN2(dev))
10711 return 96000;
10712 else
10713 return 48000;
10714 }
10715
10716 /* Returns the clock of the currently programmed mode of the given pipe. */
10717 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10718 struct intel_crtc_state *pipe_config)
10719 {
10720 struct drm_device *dev = crtc->base.dev;
10721 struct drm_i915_private *dev_priv = dev->dev_private;
10722 int pipe = pipe_config->cpu_transcoder;
10723 u32 dpll = pipe_config->dpll_hw_state.dpll;
10724 u32 fp;
10725 struct dpll clock;
10726 int port_clock;
10727 int refclk = i9xx_pll_refclk(dev, pipe_config);
10728
10729 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10730 fp = pipe_config->dpll_hw_state.fp0;
10731 else
10732 fp = pipe_config->dpll_hw_state.fp1;
10733
10734 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10735 if (IS_PINEVIEW(dev)) {
10736 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10737 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10738 } else {
10739 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10740 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10741 }
10742
10743 if (!IS_GEN2(dev)) {
10744 if (IS_PINEVIEW(dev))
10745 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10746 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10747 else
10748 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10749 DPLL_FPA01_P1_POST_DIV_SHIFT);
10750
10751 switch (dpll & DPLL_MODE_MASK) {
10752 case DPLLB_MODE_DAC_SERIAL:
10753 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10754 5 : 10;
10755 break;
10756 case DPLLB_MODE_LVDS:
10757 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10758 7 : 14;
10759 break;
10760 default:
10761 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10762 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10763 return;
10764 }
10765
10766 if (IS_PINEVIEW(dev))
10767 port_clock = pnv_calc_dpll_params(refclk, &clock);
10768 else
10769 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10770 } else {
10771 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10772 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10773
10774 if (is_lvds) {
10775 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10776 DPLL_FPA01_P1_POST_DIV_SHIFT);
10777
10778 if (lvds & LVDS_CLKB_POWER_UP)
10779 clock.p2 = 7;
10780 else
10781 clock.p2 = 14;
10782 } else {
10783 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10784 clock.p1 = 2;
10785 else {
10786 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10787 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10788 }
10789 if (dpll & PLL_P2_DIVIDE_BY_4)
10790 clock.p2 = 4;
10791 else
10792 clock.p2 = 2;
10793 }
10794
10795 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10796 }
10797
10798 /*
10799 * This value includes pixel_multiplier. We will use
10800 * port_clock to compute adjusted_mode.crtc_clock in the
10801 * encoder's get_config() function.
10802 */
10803 pipe_config->port_clock = port_clock;
10804 }
10805
10806 int intel_dotclock_calculate(int link_freq,
10807 const struct intel_link_m_n *m_n)
10808 {
10809 /*
10810 * The calculation for the data clock is:
10811 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10812 * But we want to avoid losing precison if possible, so:
10813 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10814 *
10815 * and the link clock is simpler:
10816 * link_clock = (m * link_clock) / n
10817 */
10818
10819 if (!m_n->link_n)
10820 return 0;
10821
10822 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10823 }
10824
10825 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10826 struct intel_crtc_state *pipe_config)
10827 {
10828 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10829
10830 /* read out port_clock from the DPLL */
10831 i9xx_crtc_clock_get(crtc, pipe_config);
10832
10833 /*
10834 * In case there is an active pipe without active ports,
10835 * we may need some idea for the dotclock anyway.
10836 * Calculate one based on the FDI configuration.
10837 */
10838 pipe_config->base.adjusted_mode.crtc_clock =
10839 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10840 &pipe_config->fdi_m_n);
10841 }
10842
10843 /** Returns the currently programmed mode of the given pipe. */
10844 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10845 struct drm_crtc *crtc)
10846 {
10847 struct drm_i915_private *dev_priv = dev->dev_private;
10848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10849 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10850 struct drm_display_mode *mode;
10851 struct intel_crtc_state *pipe_config;
10852 int htot = I915_READ(HTOTAL(cpu_transcoder));
10853 int hsync = I915_READ(HSYNC(cpu_transcoder));
10854 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10855 int vsync = I915_READ(VSYNC(cpu_transcoder));
10856 enum pipe pipe = intel_crtc->pipe;
10857
10858 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10859 if (!mode)
10860 return NULL;
10861
10862 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10863 if (!pipe_config) {
10864 kfree(mode);
10865 return NULL;
10866 }
10867
10868 /*
10869 * Construct a pipe_config sufficient for getting the clock info
10870 * back out of crtc_clock_get.
10871 *
10872 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10873 * to use a real value here instead.
10874 */
10875 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10876 pipe_config->pixel_multiplier = 1;
10877 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10878 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10879 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10880 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10881
10882 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10883 mode->hdisplay = (htot & 0xffff) + 1;
10884 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10885 mode->hsync_start = (hsync & 0xffff) + 1;
10886 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10887 mode->vdisplay = (vtot & 0xffff) + 1;
10888 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10889 mode->vsync_start = (vsync & 0xffff) + 1;
10890 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10891
10892 drm_mode_set_name(mode);
10893
10894 kfree(pipe_config);
10895
10896 return mode;
10897 }
10898
10899 void intel_mark_busy(struct drm_i915_private *dev_priv)
10900 {
10901 if (dev_priv->mm.busy)
10902 return;
10903
10904 intel_runtime_pm_get(dev_priv);
10905 i915_update_gfx_val(dev_priv);
10906 if (INTEL_GEN(dev_priv) >= 6)
10907 gen6_rps_busy(dev_priv);
10908 dev_priv->mm.busy = true;
10909 }
10910
10911 void intel_mark_idle(struct drm_i915_private *dev_priv)
10912 {
10913 if (!dev_priv->mm.busy)
10914 return;
10915
10916 dev_priv->mm.busy = false;
10917
10918 if (INTEL_GEN(dev_priv) >= 6)
10919 gen6_rps_idle(dev_priv);
10920
10921 intel_runtime_pm_put(dev_priv);
10922 }
10923
10924 static void intel_crtc_destroy(struct drm_crtc *crtc)
10925 {
10926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10927 struct drm_device *dev = crtc->dev;
10928 struct intel_flip_work *work;
10929
10930 spin_lock_irq(&dev->event_lock);
10931 work = intel_crtc->flip_work;
10932 intel_crtc->flip_work = NULL;
10933 spin_unlock_irq(&dev->event_lock);
10934
10935 if (work) {
10936 cancel_work_sync(&work->mmio_work);
10937 cancel_work_sync(&work->unpin_work);
10938 kfree(work);
10939 }
10940
10941 drm_crtc_cleanup(crtc);
10942
10943 kfree(intel_crtc);
10944 }
10945
10946 static void intel_unpin_work_fn(struct work_struct *__work)
10947 {
10948 struct intel_flip_work *work =
10949 container_of(__work, struct intel_flip_work, unpin_work);
10950 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10951 struct drm_device *dev = crtc->base.dev;
10952 struct drm_plane *primary = crtc->base.primary;
10953
10954 if (is_mmio_work(work))
10955 flush_work(&work->mmio_work);
10956
10957 mutex_lock(&dev->struct_mutex);
10958 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10959 drm_gem_object_unreference(&work->pending_flip_obj->base);
10960
10961 if (work->flip_queued_req)
10962 i915_gem_request_assign(&work->flip_queued_req, NULL);
10963 mutex_unlock(&dev->struct_mutex);
10964
10965 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10966 intel_fbc_post_update(crtc);
10967 drm_framebuffer_unreference(work->old_fb);
10968
10969 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10970 atomic_dec(&crtc->unpin_work_count);
10971
10972 kfree(work);
10973 }
10974
10975 /* Is 'a' after or equal to 'b'? */
10976 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10977 {
10978 return !((a - b) & 0x80000000);
10979 }
10980
10981 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10982 struct intel_flip_work *work)
10983 {
10984 struct drm_device *dev = crtc->base.dev;
10985 struct drm_i915_private *dev_priv = dev->dev_private;
10986 unsigned reset_counter;
10987
10988 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
10989 if (crtc->reset_counter != reset_counter)
10990 return true;
10991
10992 /*
10993 * The relevant registers doen't exist on pre-ctg.
10994 * As the flip done interrupt doesn't trigger for mmio
10995 * flips on gmch platforms, a flip count check isn't
10996 * really needed there. But since ctg has the registers,
10997 * include it in the check anyway.
10998 */
10999 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11000 return true;
11001
11002 /*
11003 * BDW signals flip done immediately if the plane
11004 * is disabled, even if the plane enable is already
11005 * armed to occur at the next vblank :(
11006 */
11007
11008 /*
11009 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11010 * used the same base address. In that case the mmio flip might
11011 * have completed, but the CS hasn't even executed the flip yet.
11012 *
11013 * A flip count check isn't enough as the CS might have updated
11014 * the base address just after start of vblank, but before we
11015 * managed to process the interrupt. This means we'd complete the
11016 * CS flip too soon.
11017 *
11018 * Combining both checks should get us a good enough result. It may
11019 * still happen that the CS flip has been executed, but has not
11020 * yet actually completed. But in case the base address is the same
11021 * anyway, we don't really care.
11022 */
11023 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11024 crtc->flip_work->gtt_offset &&
11025 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11026 crtc->flip_work->flip_count);
11027 }
11028
11029 static bool
11030 __pageflip_finished_mmio(struct intel_crtc *crtc,
11031 struct intel_flip_work *work)
11032 {
11033 /*
11034 * MMIO work completes when vblank is different from
11035 * flip_queued_vblank.
11036 *
11037 * Reset counter value doesn't matter, this is handled by
11038 * i915_wait_request finishing early, so no need to handle
11039 * reset here.
11040 */
11041 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11042 }
11043
11044
11045 static bool pageflip_finished(struct intel_crtc *crtc,
11046 struct intel_flip_work *work)
11047 {
11048 if (!atomic_read(&work->pending))
11049 return false;
11050
11051 smp_rmb();
11052
11053 if (is_mmio_work(work))
11054 return __pageflip_finished_mmio(crtc, work);
11055 else
11056 return __pageflip_finished_cs(crtc, work);
11057 }
11058
11059 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11060 {
11061 struct drm_device *dev = dev_priv->dev;
11062 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11064 struct intel_flip_work *work;
11065 unsigned long flags;
11066
11067 /* Ignore early vblank irqs */
11068 if (!crtc)
11069 return;
11070
11071 /*
11072 * This is called both by irq handlers and the reset code (to complete
11073 * lost pageflips) so needs the full irqsave spinlocks.
11074 */
11075 spin_lock_irqsave(&dev->event_lock, flags);
11076 work = intel_crtc->flip_work;
11077
11078 if (work != NULL &&
11079 !is_mmio_work(work) &&
11080 pageflip_finished(intel_crtc, work))
11081 page_flip_completed(intel_crtc);
11082
11083 spin_unlock_irqrestore(&dev->event_lock, flags);
11084 }
11085
11086 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11087 {
11088 struct drm_device *dev = dev_priv->dev;
11089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11091 struct intel_flip_work *work;
11092 unsigned long flags;
11093
11094 /* Ignore early vblank irqs */
11095 if (!crtc)
11096 return;
11097
11098 /*
11099 * This is called both by irq handlers and the reset code (to complete
11100 * lost pageflips) so needs the full irqsave spinlocks.
11101 */
11102 spin_lock_irqsave(&dev->event_lock, flags);
11103 work = intel_crtc->flip_work;
11104
11105 if (work != NULL &&
11106 is_mmio_work(work) &&
11107 pageflip_finished(intel_crtc, work))
11108 page_flip_completed(intel_crtc);
11109
11110 spin_unlock_irqrestore(&dev->event_lock, flags);
11111 }
11112
11113 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11114 struct intel_flip_work *work)
11115 {
11116 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11117
11118 /* Ensure that the work item is consistent when activating it ... */
11119 smp_mb__before_atomic();
11120 atomic_set(&work->pending, 1);
11121 }
11122
11123 static int intel_gen2_queue_flip(struct drm_device *dev,
11124 struct drm_crtc *crtc,
11125 struct drm_framebuffer *fb,
11126 struct drm_i915_gem_object *obj,
11127 struct drm_i915_gem_request *req,
11128 uint32_t flags)
11129 {
11130 struct intel_engine_cs *engine = req->engine;
11131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11132 u32 flip_mask;
11133 int ret;
11134
11135 ret = intel_ring_begin(req, 6);
11136 if (ret)
11137 return ret;
11138
11139 /* Can't queue multiple flips, so wait for the previous
11140 * one to finish before executing the next.
11141 */
11142 if (intel_crtc->plane)
11143 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11144 else
11145 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11146 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11147 intel_ring_emit(engine, MI_NOOP);
11148 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11149 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11150 intel_ring_emit(engine, fb->pitches[0]);
11151 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11152 intel_ring_emit(engine, 0); /* aux display base address, unused */
11153
11154 return 0;
11155 }
11156
11157 static int intel_gen3_queue_flip(struct drm_device *dev,
11158 struct drm_crtc *crtc,
11159 struct drm_framebuffer *fb,
11160 struct drm_i915_gem_object *obj,
11161 struct drm_i915_gem_request *req,
11162 uint32_t flags)
11163 {
11164 struct intel_engine_cs *engine = req->engine;
11165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11166 u32 flip_mask;
11167 int ret;
11168
11169 ret = intel_ring_begin(req, 6);
11170 if (ret)
11171 return ret;
11172
11173 if (intel_crtc->plane)
11174 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11175 else
11176 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11177 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11178 intel_ring_emit(engine, MI_NOOP);
11179 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11180 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11181 intel_ring_emit(engine, fb->pitches[0]);
11182 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11183 intel_ring_emit(engine, MI_NOOP);
11184
11185 return 0;
11186 }
11187
11188 static int intel_gen4_queue_flip(struct drm_device *dev,
11189 struct drm_crtc *crtc,
11190 struct drm_framebuffer *fb,
11191 struct drm_i915_gem_object *obj,
11192 struct drm_i915_gem_request *req,
11193 uint32_t flags)
11194 {
11195 struct intel_engine_cs *engine = req->engine;
11196 struct drm_i915_private *dev_priv = dev->dev_private;
11197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11198 uint32_t pf, pipesrc;
11199 int ret;
11200
11201 ret = intel_ring_begin(req, 4);
11202 if (ret)
11203 return ret;
11204
11205 /* i965+ uses the linear or tiled offsets from the
11206 * Display Registers (which do not change across a page-flip)
11207 * so we need only reprogram the base address.
11208 */
11209 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11210 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11211 intel_ring_emit(engine, fb->pitches[0]);
11212 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset |
11213 obj->tiling_mode);
11214
11215 /* XXX Enabling the panel-fitter across page-flip is so far
11216 * untested on non-native modes, so ignore it for now.
11217 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11218 */
11219 pf = 0;
11220 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11221 intel_ring_emit(engine, pf | pipesrc);
11222
11223 return 0;
11224 }
11225
11226 static int intel_gen6_queue_flip(struct drm_device *dev,
11227 struct drm_crtc *crtc,
11228 struct drm_framebuffer *fb,
11229 struct drm_i915_gem_object *obj,
11230 struct drm_i915_gem_request *req,
11231 uint32_t flags)
11232 {
11233 struct intel_engine_cs *engine = req->engine;
11234 struct drm_i915_private *dev_priv = dev->dev_private;
11235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11236 uint32_t pf, pipesrc;
11237 int ret;
11238
11239 ret = intel_ring_begin(req, 4);
11240 if (ret)
11241 return ret;
11242
11243 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11244 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11245 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11246 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11247
11248 /* Contrary to the suggestions in the documentation,
11249 * "Enable Panel Fitter" does not seem to be required when page
11250 * flipping with a non-native mode, and worse causes a normal
11251 * modeset to fail.
11252 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11253 */
11254 pf = 0;
11255 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11256 intel_ring_emit(engine, pf | pipesrc);
11257
11258 return 0;
11259 }
11260
11261 static int intel_gen7_queue_flip(struct drm_device *dev,
11262 struct drm_crtc *crtc,
11263 struct drm_framebuffer *fb,
11264 struct drm_i915_gem_object *obj,
11265 struct drm_i915_gem_request *req,
11266 uint32_t flags)
11267 {
11268 struct intel_engine_cs *engine = req->engine;
11269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11270 uint32_t plane_bit = 0;
11271 int len, ret;
11272
11273 switch (intel_crtc->plane) {
11274 case PLANE_A:
11275 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11276 break;
11277 case PLANE_B:
11278 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11279 break;
11280 case PLANE_C:
11281 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11282 break;
11283 default:
11284 WARN_ONCE(1, "unknown plane in flip command\n");
11285 return -ENODEV;
11286 }
11287
11288 len = 4;
11289 if (engine->id == RCS) {
11290 len += 6;
11291 /*
11292 * On Gen 8, SRM is now taking an extra dword to accommodate
11293 * 48bits addresses, and we need a NOOP for the batch size to
11294 * stay even.
11295 */
11296 if (IS_GEN8(dev))
11297 len += 2;
11298 }
11299
11300 /*
11301 * BSpec MI_DISPLAY_FLIP for IVB:
11302 * "The full packet must be contained within the same cache line."
11303 *
11304 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11305 * cacheline, if we ever start emitting more commands before
11306 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11307 * then do the cacheline alignment, and finally emit the
11308 * MI_DISPLAY_FLIP.
11309 */
11310 ret = intel_ring_cacheline_align(req);
11311 if (ret)
11312 return ret;
11313
11314 ret = intel_ring_begin(req, len);
11315 if (ret)
11316 return ret;
11317
11318 /* Unmask the flip-done completion message. Note that the bspec says that
11319 * we should do this for both the BCS and RCS, and that we must not unmask
11320 * more than one flip event at any time (or ensure that one flip message
11321 * can be sent by waiting for flip-done prior to queueing new flips).
11322 * Experimentation says that BCS works despite DERRMR masking all
11323 * flip-done completion events and that unmasking all planes at once
11324 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11325 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11326 */
11327 if (engine->id == RCS) {
11328 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11329 intel_ring_emit_reg(engine, DERRMR);
11330 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11331 DERRMR_PIPEB_PRI_FLIP_DONE |
11332 DERRMR_PIPEC_PRI_FLIP_DONE));
11333 if (IS_GEN8(dev))
11334 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11335 MI_SRM_LRM_GLOBAL_GTT);
11336 else
11337 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11338 MI_SRM_LRM_GLOBAL_GTT);
11339 intel_ring_emit_reg(engine, DERRMR);
11340 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11341 if (IS_GEN8(dev)) {
11342 intel_ring_emit(engine, 0);
11343 intel_ring_emit(engine, MI_NOOP);
11344 }
11345 }
11346
11347 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11348 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11349 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11350 intel_ring_emit(engine, (MI_NOOP));
11351
11352 return 0;
11353 }
11354
11355 static bool use_mmio_flip(struct intel_engine_cs *engine,
11356 struct drm_i915_gem_object *obj)
11357 {
11358 /*
11359 * This is not being used for older platforms, because
11360 * non-availability of flip done interrupt forces us to use
11361 * CS flips. Older platforms derive flip done using some clever
11362 * tricks involving the flip_pending status bits and vblank irqs.
11363 * So using MMIO flips there would disrupt this mechanism.
11364 */
11365
11366 if (engine == NULL)
11367 return true;
11368
11369 if (INTEL_GEN(engine->i915) < 5)
11370 return false;
11371
11372 if (i915.use_mmio_flip < 0)
11373 return false;
11374 else if (i915.use_mmio_flip > 0)
11375 return true;
11376 else if (i915.enable_execlists)
11377 return true;
11378 else if (obj->base.dma_buf &&
11379 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11380 false))
11381 return true;
11382 else
11383 return engine != i915_gem_request_get_engine(obj->last_write_req);
11384 }
11385
11386 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11387 unsigned int rotation,
11388 struct intel_flip_work *work)
11389 {
11390 struct drm_device *dev = intel_crtc->base.dev;
11391 struct drm_i915_private *dev_priv = dev->dev_private;
11392 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11393 const enum pipe pipe = intel_crtc->pipe;
11394 u32 ctl, stride, tile_height;
11395
11396 ctl = I915_READ(PLANE_CTL(pipe, 0));
11397 ctl &= ~PLANE_CTL_TILED_MASK;
11398 switch (fb->modifier[0]) {
11399 case DRM_FORMAT_MOD_NONE:
11400 break;
11401 case I915_FORMAT_MOD_X_TILED:
11402 ctl |= PLANE_CTL_TILED_X;
11403 break;
11404 case I915_FORMAT_MOD_Y_TILED:
11405 ctl |= PLANE_CTL_TILED_Y;
11406 break;
11407 case I915_FORMAT_MOD_Yf_TILED:
11408 ctl |= PLANE_CTL_TILED_YF;
11409 break;
11410 default:
11411 MISSING_CASE(fb->modifier[0]);
11412 }
11413
11414 /*
11415 * The stride is either expressed as a multiple of 64 bytes chunks for
11416 * linear buffers or in number of tiles for tiled buffers.
11417 */
11418 if (intel_rotation_90_or_270(rotation)) {
11419 /* stride = Surface height in tiles */
11420 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11421 stride = DIV_ROUND_UP(fb->height, tile_height);
11422 } else {
11423 stride = fb->pitches[0] /
11424 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11425 fb->pixel_format);
11426 }
11427
11428 /*
11429 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11430 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11431 */
11432 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11433 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11434
11435 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11436 POSTING_READ(PLANE_SURF(pipe, 0));
11437 }
11438
11439 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11440 struct intel_flip_work *work)
11441 {
11442 struct drm_device *dev = intel_crtc->base.dev;
11443 struct drm_i915_private *dev_priv = dev->dev_private;
11444 struct intel_framebuffer *intel_fb =
11445 to_intel_framebuffer(intel_crtc->base.primary->fb);
11446 struct drm_i915_gem_object *obj = intel_fb->obj;
11447 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11448 u32 dspcntr;
11449
11450 dspcntr = I915_READ(reg);
11451
11452 if (obj->tiling_mode != I915_TILING_NONE)
11453 dspcntr |= DISPPLANE_TILED;
11454 else
11455 dspcntr &= ~DISPPLANE_TILED;
11456
11457 I915_WRITE(reg, dspcntr);
11458
11459 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11460 POSTING_READ(DSPSURF(intel_crtc->plane));
11461 }
11462
11463 static void intel_mmio_flip_work_func(struct work_struct *w)
11464 {
11465 struct intel_flip_work *work =
11466 container_of(w, struct intel_flip_work, mmio_work);
11467 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11469 struct intel_framebuffer *intel_fb =
11470 to_intel_framebuffer(crtc->base.primary->fb);
11471 struct drm_i915_gem_object *obj = intel_fb->obj;
11472
11473 if (work->flip_queued_req)
11474 WARN_ON(__i915_wait_request(work->flip_queued_req,
11475 false, NULL,
11476 &dev_priv->rps.mmioflips));
11477
11478 /* For framebuffer backed by dmabuf, wait for fence */
11479 if (obj->base.dma_buf)
11480 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11481 false, false,
11482 MAX_SCHEDULE_TIMEOUT) < 0);
11483
11484 intel_pipe_update_start(crtc);
11485
11486 if (INTEL_GEN(dev_priv) >= 9)
11487 skl_do_mmio_flip(crtc, work->rotation, work);
11488 else
11489 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11490 ilk_do_mmio_flip(crtc, work);
11491
11492 intel_pipe_update_end(crtc, work);
11493 }
11494
11495 static int intel_default_queue_flip(struct drm_device *dev,
11496 struct drm_crtc *crtc,
11497 struct drm_framebuffer *fb,
11498 struct drm_i915_gem_object *obj,
11499 struct drm_i915_gem_request *req,
11500 uint32_t flags)
11501 {
11502 return -ENODEV;
11503 }
11504
11505 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11506 struct intel_crtc *intel_crtc,
11507 struct intel_flip_work *work)
11508 {
11509 u32 addr, vblank;
11510
11511 if (!atomic_read(&work->pending))
11512 return false;
11513
11514 smp_rmb();
11515
11516 vblank = intel_crtc_get_vblank_counter(intel_crtc);
11517 if (work->flip_ready_vblank == 0) {
11518 if (work->flip_queued_req &&
11519 !i915_gem_request_completed(work->flip_queued_req, true))
11520 return false;
11521
11522 work->flip_ready_vblank = vblank;
11523 }
11524
11525 if (vblank - work->flip_ready_vblank < 3)
11526 return false;
11527
11528 /* Potential stall - if we see that the flip has happened,
11529 * assume a missed interrupt. */
11530 if (INTEL_GEN(dev_priv) >= 4)
11531 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11532 else
11533 addr = I915_READ(DSPADDR(intel_crtc->plane));
11534
11535 /* There is a potential issue here with a false positive after a flip
11536 * to the same address. We could address this by checking for a
11537 * non-incrementing frame counter.
11538 */
11539 return addr == work->gtt_offset;
11540 }
11541
11542 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11543 {
11544 struct drm_device *dev = dev_priv->dev;
11545 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11547 struct intel_flip_work *work;
11548
11549 WARN_ON(!in_interrupt());
11550
11551 if (crtc == NULL)
11552 return;
11553
11554 spin_lock(&dev->event_lock);
11555 work = intel_crtc->flip_work;
11556
11557 if (work != NULL && !is_mmio_work(work) &&
11558 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
11559 WARN_ONCE(1,
11560 "Kicking stuck page flip: queued at %d, now %d\n",
11561 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
11562 page_flip_completed(intel_crtc);
11563 work = NULL;
11564 }
11565
11566 if (work != NULL && !is_mmio_work(work) &&
11567 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
11568 intel_queue_rps_boost_for_request(work->flip_queued_req);
11569 spin_unlock(&dev->event_lock);
11570 }
11571
11572 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11573 struct drm_framebuffer *fb,
11574 struct drm_pending_vblank_event *event,
11575 uint32_t page_flip_flags)
11576 {
11577 struct drm_device *dev = crtc->dev;
11578 struct drm_i915_private *dev_priv = dev->dev_private;
11579 struct drm_framebuffer *old_fb = crtc->primary->fb;
11580 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11582 struct drm_plane *primary = crtc->primary;
11583 enum pipe pipe = intel_crtc->pipe;
11584 struct intel_flip_work *work;
11585 struct intel_engine_cs *engine;
11586 bool mmio_flip;
11587 struct drm_i915_gem_request *request = NULL;
11588 int ret;
11589
11590 /*
11591 * drm_mode_page_flip_ioctl() should already catch this, but double
11592 * check to be safe. In the future we may enable pageflipping from
11593 * a disabled primary plane.
11594 */
11595 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11596 return -EBUSY;
11597
11598 /* Can't change pixel format via MI display flips. */
11599 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11600 return -EINVAL;
11601
11602 /*
11603 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11604 * Note that pitch changes could also affect these register.
11605 */
11606 if (INTEL_INFO(dev)->gen > 3 &&
11607 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11608 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11609 return -EINVAL;
11610
11611 if (i915_terminally_wedged(&dev_priv->gpu_error))
11612 goto out_hang;
11613
11614 work = kzalloc(sizeof(*work), GFP_KERNEL);
11615 if (work == NULL)
11616 return -ENOMEM;
11617
11618 work->event = event;
11619 work->crtc = crtc;
11620 work->old_fb = old_fb;
11621 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
11622
11623 ret = drm_crtc_vblank_get(crtc);
11624 if (ret)
11625 goto free_work;
11626
11627 /* We borrow the event spin lock for protecting flip_work */
11628 spin_lock_irq(&dev->event_lock);
11629 if (intel_crtc->flip_work) {
11630 /* Before declaring the flip queue wedged, check if
11631 * the hardware completed the operation behind our backs.
11632 */
11633 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
11634 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11635 page_flip_completed(intel_crtc);
11636 } else {
11637 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11638 spin_unlock_irq(&dev->event_lock);
11639
11640 drm_crtc_vblank_put(crtc);
11641 kfree(work);
11642 return -EBUSY;
11643 }
11644 }
11645 intel_crtc->flip_work = work;
11646 spin_unlock_irq(&dev->event_lock);
11647
11648 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11649 flush_workqueue(dev_priv->wq);
11650
11651 /* Reference the objects for the scheduled work. */
11652 drm_framebuffer_reference(work->old_fb);
11653 drm_gem_object_reference(&obj->base);
11654
11655 crtc->primary->fb = fb;
11656 update_state_fb(crtc->primary);
11657 intel_fbc_pre_update(intel_crtc);
11658
11659 work->pending_flip_obj = obj;
11660
11661 ret = i915_mutex_lock_interruptible(dev);
11662 if (ret)
11663 goto cleanup;
11664
11665 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11666 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11667 ret = -EIO;
11668 goto cleanup;
11669 }
11670
11671 atomic_inc(&intel_crtc->unpin_work_count);
11672
11673 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11674 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11675
11676 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11677 engine = &dev_priv->engine[BCS];
11678 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11679 /* vlv: DISPLAY_FLIP fails to change tiling */
11680 engine = NULL;
11681 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11682 engine = &dev_priv->engine[BCS];
11683 } else if (INTEL_INFO(dev)->gen >= 7) {
11684 engine = i915_gem_request_get_engine(obj->last_write_req);
11685 if (engine == NULL || engine->id != RCS)
11686 engine = &dev_priv->engine[BCS];
11687 } else {
11688 engine = &dev_priv->engine[RCS];
11689 }
11690
11691 mmio_flip = use_mmio_flip(engine, obj);
11692
11693 /* When using CS flips, we want to emit semaphores between rings.
11694 * However, when using mmio flips we will create a task to do the
11695 * synchronisation, so all we want here is to pin the framebuffer
11696 * into the display plane and skip any waits.
11697 */
11698 if (!mmio_flip) {
11699 ret = i915_gem_object_sync(obj, engine, &request);
11700 if (!ret && !request) {
11701 request = i915_gem_request_alloc(engine, NULL);
11702 ret = PTR_ERR_OR_ZERO(request);
11703 }
11704
11705 if (ret)
11706 goto cleanup_pending;
11707 }
11708
11709 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11710 if (ret)
11711 goto cleanup_pending;
11712
11713 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11714 obj, 0);
11715 work->gtt_offset += intel_crtc->dspaddr_offset;
11716 work->rotation = crtc->primary->state->rotation;
11717
11718 if (mmio_flip) {
11719 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
11720
11721 i915_gem_request_assign(&work->flip_queued_req,
11722 obj->last_write_req);
11723
11724 schedule_work(&work->mmio_work);
11725 } else {
11726 i915_gem_request_assign(&work->flip_queued_req, request);
11727 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11728 page_flip_flags);
11729 if (ret)
11730 goto cleanup_unpin;
11731
11732 intel_mark_page_flip_active(intel_crtc, work);
11733
11734 i915_add_request_no_flush(request);
11735 }
11736
11737 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
11738 to_intel_plane(primary)->frontbuffer_bit);
11739 mutex_unlock(&dev->struct_mutex);
11740
11741 intel_frontbuffer_flip_prepare(dev,
11742 to_intel_plane(primary)->frontbuffer_bit);
11743
11744 trace_i915_flip_request(intel_crtc->plane, obj);
11745
11746 return 0;
11747
11748 cleanup_unpin:
11749 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11750 cleanup_pending:
11751 if (!IS_ERR_OR_NULL(request))
11752 i915_add_request_no_flush(request);
11753 atomic_dec(&intel_crtc->unpin_work_count);
11754 mutex_unlock(&dev->struct_mutex);
11755 cleanup:
11756 crtc->primary->fb = old_fb;
11757 update_state_fb(crtc->primary);
11758
11759 drm_gem_object_unreference_unlocked(&obj->base);
11760 drm_framebuffer_unreference(work->old_fb);
11761
11762 spin_lock_irq(&dev->event_lock);
11763 intel_crtc->flip_work = NULL;
11764 spin_unlock_irq(&dev->event_lock);
11765
11766 drm_crtc_vblank_put(crtc);
11767 free_work:
11768 kfree(work);
11769
11770 if (ret == -EIO) {
11771 struct drm_atomic_state *state;
11772 struct drm_plane_state *plane_state;
11773
11774 out_hang:
11775 state = drm_atomic_state_alloc(dev);
11776 if (!state)
11777 return -ENOMEM;
11778 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11779
11780 retry:
11781 plane_state = drm_atomic_get_plane_state(state, primary);
11782 ret = PTR_ERR_OR_ZERO(plane_state);
11783 if (!ret) {
11784 drm_atomic_set_fb_for_plane(plane_state, fb);
11785
11786 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11787 if (!ret)
11788 ret = drm_atomic_commit(state);
11789 }
11790
11791 if (ret == -EDEADLK) {
11792 drm_modeset_backoff(state->acquire_ctx);
11793 drm_atomic_state_clear(state);
11794 goto retry;
11795 }
11796
11797 if (ret)
11798 drm_atomic_state_free(state);
11799
11800 if (ret == 0 && event) {
11801 spin_lock_irq(&dev->event_lock);
11802 drm_crtc_send_vblank_event(crtc, event);
11803 spin_unlock_irq(&dev->event_lock);
11804 }
11805 }
11806 return ret;
11807 }
11808
11809
11810 /**
11811 * intel_wm_need_update - Check whether watermarks need updating
11812 * @plane: drm plane
11813 * @state: new plane state
11814 *
11815 * Check current plane state versus the new one to determine whether
11816 * watermarks need to be recalculated.
11817 *
11818 * Returns true or false.
11819 */
11820 static bool intel_wm_need_update(struct drm_plane *plane,
11821 struct drm_plane_state *state)
11822 {
11823 struct intel_plane_state *new = to_intel_plane_state(state);
11824 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11825
11826 /* Update watermarks on tiling or size changes. */
11827 if (new->visible != cur->visible)
11828 return true;
11829
11830 if (!cur->base.fb || !new->base.fb)
11831 return false;
11832
11833 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11834 cur->base.rotation != new->base.rotation ||
11835 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11836 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11837 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11838 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11839 return true;
11840
11841 return false;
11842 }
11843
11844 static bool needs_scaling(struct intel_plane_state *state)
11845 {
11846 int src_w = drm_rect_width(&state->src) >> 16;
11847 int src_h = drm_rect_height(&state->src) >> 16;
11848 int dst_w = drm_rect_width(&state->dst);
11849 int dst_h = drm_rect_height(&state->dst);
11850
11851 return (src_w != dst_w || src_h != dst_h);
11852 }
11853
11854 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11855 struct drm_plane_state *plane_state)
11856 {
11857 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11858 struct drm_crtc *crtc = crtc_state->crtc;
11859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11860 struct drm_plane *plane = plane_state->plane;
11861 struct drm_device *dev = crtc->dev;
11862 struct drm_i915_private *dev_priv = to_i915(dev);
11863 struct intel_plane_state *old_plane_state =
11864 to_intel_plane_state(plane->state);
11865 int idx = intel_crtc->base.base.id, ret;
11866 bool mode_changed = needs_modeset(crtc_state);
11867 bool was_crtc_enabled = crtc->state->active;
11868 bool is_crtc_enabled = crtc_state->active;
11869 bool turn_off, turn_on, visible, was_visible;
11870 struct drm_framebuffer *fb = plane_state->fb;
11871
11872 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11873 plane->type != DRM_PLANE_TYPE_CURSOR) {
11874 ret = skl_update_scaler_plane(
11875 to_intel_crtc_state(crtc_state),
11876 to_intel_plane_state(plane_state));
11877 if (ret)
11878 return ret;
11879 }
11880
11881 was_visible = old_plane_state->visible;
11882 visible = to_intel_plane_state(plane_state)->visible;
11883
11884 if (!was_crtc_enabled && WARN_ON(was_visible))
11885 was_visible = false;
11886
11887 /*
11888 * Visibility is calculated as if the crtc was on, but
11889 * after scaler setup everything depends on it being off
11890 * when the crtc isn't active.
11891 *
11892 * FIXME this is wrong for watermarks. Watermarks should also
11893 * be computed as if the pipe would be active. Perhaps move
11894 * per-plane wm computation to the .check_plane() hook, and
11895 * only combine the results from all planes in the current place?
11896 */
11897 if (!is_crtc_enabled)
11898 to_intel_plane_state(plane_state)->visible = visible = false;
11899
11900 if (!was_visible && !visible)
11901 return 0;
11902
11903 if (fb != old_plane_state->base.fb)
11904 pipe_config->fb_changed = true;
11905
11906 turn_off = was_visible && (!visible || mode_changed);
11907 turn_on = visible && (!was_visible || mode_changed);
11908
11909 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11910 plane->base.id, fb ? fb->base.id : -1);
11911
11912 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11913 plane->base.id, was_visible, visible,
11914 turn_off, turn_on, mode_changed);
11915
11916 if (turn_on) {
11917 pipe_config->update_wm_pre = true;
11918
11919 /* must disable cxsr around plane enable/disable */
11920 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11921 pipe_config->disable_cxsr = true;
11922 } else if (turn_off) {
11923 pipe_config->update_wm_post = true;
11924
11925 /* must disable cxsr around plane enable/disable */
11926 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11927 pipe_config->disable_cxsr = true;
11928 } else if (intel_wm_need_update(plane, plane_state)) {
11929 /* FIXME bollocks */
11930 pipe_config->update_wm_pre = true;
11931 pipe_config->update_wm_post = true;
11932 }
11933
11934 /* Pre-gen9 platforms need two-step watermark updates */
11935 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11936 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11937 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11938
11939 if (visible || was_visible)
11940 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11941
11942 /*
11943 * WaCxSRDisabledForSpriteScaling:ivb
11944 *
11945 * cstate->update_wm was already set above, so this flag will
11946 * take effect when we commit and program watermarks.
11947 */
11948 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11949 needs_scaling(to_intel_plane_state(plane_state)) &&
11950 !needs_scaling(old_plane_state))
11951 pipe_config->disable_lp_wm = true;
11952
11953 return 0;
11954 }
11955
11956 static bool encoders_cloneable(const struct intel_encoder *a,
11957 const struct intel_encoder *b)
11958 {
11959 /* masks could be asymmetric, so check both ways */
11960 return a == b || (a->cloneable & (1 << b->type) &&
11961 b->cloneable & (1 << a->type));
11962 }
11963
11964 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11965 struct intel_crtc *crtc,
11966 struct intel_encoder *encoder)
11967 {
11968 struct intel_encoder *source_encoder;
11969 struct drm_connector *connector;
11970 struct drm_connector_state *connector_state;
11971 int i;
11972
11973 for_each_connector_in_state(state, connector, connector_state, i) {
11974 if (connector_state->crtc != &crtc->base)
11975 continue;
11976
11977 source_encoder =
11978 to_intel_encoder(connector_state->best_encoder);
11979 if (!encoders_cloneable(encoder, source_encoder))
11980 return false;
11981 }
11982
11983 return true;
11984 }
11985
11986 static bool check_encoder_cloning(struct drm_atomic_state *state,
11987 struct intel_crtc *crtc)
11988 {
11989 struct intel_encoder *encoder;
11990 struct drm_connector *connector;
11991 struct drm_connector_state *connector_state;
11992 int i;
11993
11994 for_each_connector_in_state(state, connector, connector_state, i) {
11995 if (connector_state->crtc != &crtc->base)
11996 continue;
11997
11998 encoder = to_intel_encoder(connector_state->best_encoder);
11999 if (!check_single_encoder_cloning(state, crtc, encoder))
12000 return false;
12001 }
12002
12003 return true;
12004 }
12005
12006 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12007 struct drm_crtc_state *crtc_state)
12008 {
12009 struct drm_device *dev = crtc->dev;
12010 struct drm_i915_private *dev_priv = dev->dev_private;
12011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12012 struct intel_crtc_state *pipe_config =
12013 to_intel_crtc_state(crtc_state);
12014 struct drm_atomic_state *state = crtc_state->state;
12015 int ret;
12016 bool mode_changed = needs_modeset(crtc_state);
12017
12018 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12019 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12020 return -EINVAL;
12021 }
12022
12023 if (mode_changed && !crtc_state->active)
12024 pipe_config->update_wm_post = true;
12025
12026 if (mode_changed && crtc_state->enable &&
12027 dev_priv->display.crtc_compute_clock &&
12028 !WARN_ON(pipe_config->shared_dpll)) {
12029 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12030 pipe_config);
12031 if (ret)
12032 return ret;
12033 }
12034
12035 if (crtc_state->color_mgmt_changed) {
12036 ret = intel_color_check(crtc, crtc_state);
12037 if (ret)
12038 return ret;
12039 }
12040
12041 ret = 0;
12042 if (dev_priv->display.compute_pipe_wm) {
12043 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12044 if (ret) {
12045 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12046 return ret;
12047 }
12048 }
12049
12050 if (dev_priv->display.compute_intermediate_wm &&
12051 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12052 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12053 return 0;
12054
12055 /*
12056 * Calculate 'intermediate' watermarks that satisfy both the
12057 * old state and the new state. We can program these
12058 * immediately.
12059 */
12060 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12061 intel_crtc,
12062 pipe_config);
12063 if (ret) {
12064 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12065 return ret;
12066 }
12067 } else if (dev_priv->display.compute_intermediate_wm) {
12068 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12069 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12070 }
12071
12072 if (INTEL_INFO(dev)->gen >= 9) {
12073 if (mode_changed)
12074 ret = skl_update_scaler_crtc(pipe_config);
12075
12076 if (!ret)
12077 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12078 pipe_config);
12079 }
12080
12081 return ret;
12082 }
12083
12084 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12085 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12086 .atomic_begin = intel_begin_crtc_commit,
12087 .atomic_flush = intel_finish_crtc_commit,
12088 .atomic_check = intel_crtc_atomic_check,
12089 };
12090
12091 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12092 {
12093 struct intel_connector *connector;
12094
12095 for_each_intel_connector(dev, connector) {
12096 if (connector->base.state->crtc)
12097 drm_connector_unreference(&connector->base);
12098
12099 if (connector->base.encoder) {
12100 connector->base.state->best_encoder =
12101 connector->base.encoder;
12102 connector->base.state->crtc =
12103 connector->base.encoder->crtc;
12104
12105 drm_connector_reference(&connector->base);
12106 } else {
12107 connector->base.state->best_encoder = NULL;
12108 connector->base.state->crtc = NULL;
12109 }
12110 }
12111 }
12112
12113 static void
12114 connected_sink_compute_bpp(struct intel_connector *connector,
12115 struct intel_crtc_state *pipe_config)
12116 {
12117 int bpp = pipe_config->pipe_bpp;
12118
12119 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12120 connector->base.base.id,
12121 connector->base.name);
12122
12123 /* Don't use an invalid EDID bpc value */
12124 if (connector->base.display_info.bpc &&
12125 connector->base.display_info.bpc * 3 < bpp) {
12126 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12127 bpp, connector->base.display_info.bpc*3);
12128 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12129 }
12130
12131 /* Clamp bpp to default limit on screens without EDID 1.4 */
12132 if (connector->base.display_info.bpc == 0) {
12133 int type = connector->base.connector_type;
12134 int clamp_bpp = 24;
12135
12136 /* Fall back to 18 bpp when DP sink capability is unknown. */
12137 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12138 type == DRM_MODE_CONNECTOR_eDP)
12139 clamp_bpp = 18;
12140
12141 if (bpp > clamp_bpp) {
12142 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12143 bpp, clamp_bpp);
12144 pipe_config->pipe_bpp = clamp_bpp;
12145 }
12146 }
12147 }
12148
12149 static int
12150 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12151 struct intel_crtc_state *pipe_config)
12152 {
12153 struct drm_device *dev = crtc->base.dev;
12154 struct drm_atomic_state *state;
12155 struct drm_connector *connector;
12156 struct drm_connector_state *connector_state;
12157 int bpp, i;
12158
12159 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12160 bpp = 10*3;
12161 else if (INTEL_INFO(dev)->gen >= 5)
12162 bpp = 12*3;
12163 else
12164 bpp = 8*3;
12165
12166
12167 pipe_config->pipe_bpp = bpp;
12168
12169 state = pipe_config->base.state;
12170
12171 /* Clamp display bpp to EDID value */
12172 for_each_connector_in_state(state, connector, connector_state, i) {
12173 if (connector_state->crtc != &crtc->base)
12174 continue;
12175
12176 connected_sink_compute_bpp(to_intel_connector(connector),
12177 pipe_config);
12178 }
12179
12180 return bpp;
12181 }
12182
12183 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12184 {
12185 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12186 "type: 0x%x flags: 0x%x\n",
12187 mode->crtc_clock,
12188 mode->crtc_hdisplay, mode->crtc_hsync_start,
12189 mode->crtc_hsync_end, mode->crtc_htotal,
12190 mode->crtc_vdisplay, mode->crtc_vsync_start,
12191 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12192 }
12193
12194 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12195 struct intel_crtc_state *pipe_config,
12196 const char *context)
12197 {
12198 struct drm_device *dev = crtc->base.dev;
12199 struct drm_plane *plane;
12200 struct intel_plane *intel_plane;
12201 struct intel_plane_state *state;
12202 struct drm_framebuffer *fb;
12203
12204 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12205 context, pipe_config, pipe_name(crtc->pipe));
12206
12207 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12208 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12209 pipe_config->pipe_bpp, pipe_config->dither);
12210 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12211 pipe_config->has_pch_encoder,
12212 pipe_config->fdi_lanes,
12213 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12214 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12215 pipe_config->fdi_m_n.tu);
12216 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12217 pipe_config->has_dp_encoder,
12218 pipe_config->lane_count,
12219 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12220 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12221 pipe_config->dp_m_n.tu);
12222
12223 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12224 pipe_config->has_dp_encoder,
12225 pipe_config->lane_count,
12226 pipe_config->dp_m2_n2.gmch_m,
12227 pipe_config->dp_m2_n2.gmch_n,
12228 pipe_config->dp_m2_n2.link_m,
12229 pipe_config->dp_m2_n2.link_n,
12230 pipe_config->dp_m2_n2.tu);
12231
12232 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12233 pipe_config->has_audio,
12234 pipe_config->has_infoframe);
12235
12236 DRM_DEBUG_KMS("requested mode:\n");
12237 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12238 DRM_DEBUG_KMS("adjusted mode:\n");
12239 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12240 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12241 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12242 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12243 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12244 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12245 crtc->num_scalers,
12246 pipe_config->scaler_state.scaler_users,
12247 pipe_config->scaler_state.scaler_id);
12248 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12249 pipe_config->gmch_pfit.control,
12250 pipe_config->gmch_pfit.pgm_ratios,
12251 pipe_config->gmch_pfit.lvds_border_bits);
12252 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12253 pipe_config->pch_pfit.pos,
12254 pipe_config->pch_pfit.size,
12255 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12256 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12257 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12258
12259 if (IS_BROXTON(dev)) {
12260 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12261 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12262 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12263 pipe_config->ddi_pll_sel,
12264 pipe_config->dpll_hw_state.ebb0,
12265 pipe_config->dpll_hw_state.ebb4,
12266 pipe_config->dpll_hw_state.pll0,
12267 pipe_config->dpll_hw_state.pll1,
12268 pipe_config->dpll_hw_state.pll2,
12269 pipe_config->dpll_hw_state.pll3,
12270 pipe_config->dpll_hw_state.pll6,
12271 pipe_config->dpll_hw_state.pll8,
12272 pipe_config->dpll_hw_state.pll9,
12273 pipe_config->dpll_hw_state.pll10,
12274 pipe_config->dpll_hw_state.pcsdw12);
12275 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12276 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12277 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12278 pipe_config->ddi_pll_sel,
12279 pipe_config->dpll_hw_state.ctrl1,
12280 pipe_config->dpll_hw_state.cfgcr1,
12281 pipe_config->dpll_hw_state.cfgcr2);
12282 } else if (HAS_DDI(dev)) {
12283 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12284 pipe_config->ddi_pll_sel,
12285 pipe_config->dpll_hw_state.wrpll,
12286 pipe_config->dpll_hw_state.spll);
12287 } else {
12288 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12289 "fp0: 0x%x, fp1: 0x%x\n",
12290 pipe_config->dpll_hw_state.dpll,
12291 pipe_config->dpll_hw_state.dpll_md,
12292 pipe_config->dpll_hw_state.fp0,
12293 pipe_config->dpll_hw_state.fp1);
12294 }
12295
12296 DRM_DEBUG_KMS("planes on this crtc\n");
12297 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12298 intel_plane = to_intel_plane(plane);
12299 if (intel_plane->pipe != crtc->pipe)
12300 continue;
12301
12302 state = to_intel_plane_state(plane->state);
12303 fb = state->base.fb;
12304 if (!fb) {
12305 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12306 "disabled, scaler_id = %d\n",
12307 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12308 plane->base.id, intel_plane->pipe,
12309 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12310 drm_plane_index(plane), state->scaler_id);
12311 continue;
12312 }
12313
12314 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12315 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12316 plane->base.id, intel_plane->pipe,
12317 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12318 drm_plane_index(plane));
12319 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12320 fb->base.id, fb->width, fb->height, fb->pixel_format);
12321 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12322 state->scaler_id,
12323 state->src.x1 >> 16, state->src.y1 >> 16,
12324 drm_rect_width(&state->src) >> 16,
12325 drm_rect_height(&state->src) >> 16,
12326 state->dst.x1, state->dst.y1,
12327 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12328 }
12329 }
12330
12331 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12332 {
12333 struct drm_device *dev = state->dev;
12334 struct drm_connector *connector;
12335 unsigned int used_ports = 0;
12336
12337 /*
12338 * Walk the connector list instead of the encoder
12339 * list to detect the problem on ddi platforms
12340 * where there's just one encoder per digital port.
12341 */
12342 drm_for_each_connector(connector, dev) {
12343 struct drm_connector_state *connector_state;
12344 struct intel_encoder *encoder;
12345
12346 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12347 if (!connector_state)
12348 connector_state = connector->state;
12349
12350 if (!connector_state->best_encoder)
12351 continue;
12352
12353 encoder = to_intel_encoder(connector_state->best_encoder);
12354
12355 WARN_ON(!connector_state->crtc);
12356
12357 switch (encoder->type) {
12358 unsigned int port_mask;
12359 case INTEL_OUTPUT_UNKNOWN:
12360 if (WARN_ON(!HAS_DDI(dev)))
12361 break;
12362 case INTEL_OUTPUT_DISPLAYPORT:
12363 case INTEL_OUTPUT_HDMI:
12364 case INTEL_OUTPUT_EDP:
12365 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12366
12367 /* the same port mustn't appear more than once */
12368 if (used_ports & port_mask)
12369 return false;
12370
12371 used_ports |= port_mask;
12372 default:
12373 break;
12374 }
12375 }
12376
12377 return true;
12378 }
12379
12380 static void
12381 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12382 {
12383 struct drm_crtc_state tmp_state;
12384 struct intel_crtc_scaler_state scaler_state;
12385 struct intel_dpll_hw_state dpll_hw_state;
12386 struct intel_shared_dpll *shared_dpll;
12387 uint32_t ddi_pll_sel;
12388 bool force_thru;
12389
12390 /* FIXME: before the switch to atomic started, a new pipe_config was
12391 * kzalloc'd. Code that depends on any field being zero should be
12392 * fixed, so that the crtc_state can be safely duplicated. For now,
12393 * only fields that are know to not cause problems are preserved. */
12394
12395 tmp_state = crtc_state->base;
12396 scaler_state = crtc_state->scaler_state;
12397 shared_dpll = crtc_state->shared_dpll;
12398 dpll_hw_state = crtc_state->dpll_hw_state;
12399 ddi_pll_sel = crtc_state->ddi_pll_sel;
12400 force_thru = crtc_state->pch_pfit.force_thru;
12401
12402 memset(crtc_state, 0, sizeof *crtc_state);
12403
12404 crtc_state->base = tmp_state;
12405 crtc_state->scaler_state = scaler_state;
12406 crtc_state->shared_dpll = shared_dpll;
12407 crtc_state->dpll_hw_state = dpll_hw_state;
12408 crtc_state->ddi_pll_sel = ddi_pll_sel;
12409 crtc_state->pch_pfit.force_thru = force_thru;
12410 }
12411
12412 static int
12413 intel_modeset_pipe_config(struct drm_crtc *crtc,
12414 struct intel_crtc_state *pipe_config)
12415 {
12416 struct drm_atomic_state *state = pipe_config->base.state;
12417 struct intel_encoder *encoder;
12418 struct drm_connector *connector;
12419 struct drm_connector_state *connector_state;
12420 int base_bpp, ret = -EINVAL;
12421 int i;
12422 bool retry = true;
12423
12424 clear_intel_crtc_state(pipe_config);
12425
12426 pipe_config->cpu_transcoder =
12427 (enum transcoder) to_intel_crtc(crtc)->pipe;
12428
12429 /*
12430 * Sanitize sync polarity flags based on requested ones. If neither
12431 * positive or negative polarity is requested, treat this as meaning
12432 * negative polarity.
12433 */
12434 if (!(pipe_config->base.adjusted_mode.flags &
12435 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12436 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12437
12438 if (!(pipe_config->base.adjusted_mode.flags &
12439 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12440 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12441
12442 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12443 pipe_config);
12444 if (base_bpp < 0)
12445 goto fail;
12446
12447 /*
12448 * Determine the real pipe dimensions. Note that stereo modes can
12449 * increase the actual pipe size due to the frame doubling and
12450 * insertion of additional space for blanks between the frame. This
12451 * is stored in the crtc timings. We use the requested mode to do this
12452 * computation to clearly distinguish it from the adjusted mode, which
12453 * can be changed by the connectors in the below retry loop.
12454 */
12455 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12456 &pipe_config->pipe_src_w,
12457 &pipe_config->pipe_src_h);
12458
12459 encoder_retry:
12460 /* Ensure the port clock defaults are reset when retrying. */
12461 pipe_config->port_clock = 0;
12462 pipe_config->pixel_multiplier = 1;
12463
12464 /* Fill in default crtc timings, allow encoders to overwrite them. */
12465 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12466 CRTC_STEREO_DOUBLE);
12467
12468 /* Pass our mode to the connectors and the CRTC to give them a chance to
12469 * adjust it according to limitations or connector properties, and also
12470 * a chance to reject the mode entirely.
12471 */
12472 for_each_connector_in_state(state, connector, connector_state, i) {
12473 if (connector_state->crtc != crtc)
12474 continue;
12475
12476 encoder = to_intel_encoder(connector_state->best_encoder);
12477
12478 if (!(encoder->compute_config(encoder, pipe_config))) {
12479 DRM_DEBUG_KMS("Encoder config failure\n");
12480 goto fail;
12481 }
12482 }
12483
12484 /* Set default port clock if not overwritten by the encoder. Needs to be
12485 * done afterwards in case the encoder adjusts the mode. */
12486 if (!pipe_config->port_clock)
12487 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12488 * pipe_config->pixel_multiplier;
12489
12490 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12491 if (ret < 0) {
12492 DRM_DEBUG_KMS("CRTC fixup failed\n");
12493 goto fail;
12494 }
12495
12496 if (ret == RETRY) {
12497 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12498 ret = -EINVAL;
12499 goto fail;
12500 }
12501
12502 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12503 retry = false;
12504 goto encoder_retry;
12505 }
12506
12507 /* Dithering seems to not pass-through bits correctly when it should, so
12508 * only enable it on 6bpc panels. */
12509 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12510 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12511 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12512
12513 fail:
12514 return ret;
12515 }
12516
12517 static void
12518 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12519 {
12520 struct drm_crtc *crtc;
12521 struct drm_crtc_state *crtc_state;
12522 int i;
12523
12524 /* Double check state. */
12525 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12526 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12527
12528 /* Update hwmode for vblank functions */
12529 if (crtc->state->active)
12530 crtc->hwmode = crtc->state->adjusted_mode;
12531 else
12532 crtc->hwmode.crtc_clock = 0;
12533
12534 /*
12535 * Update legacy state to satisfy fbc code. This can
12536 * be removed when fbc uses the atomic state.
12537 */
12538 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12539 struct drm_plane_state *plane_state = crtc->primary->state;
12540
12541 crtc->primary->fb = plane_state->fb;
12542 crtc->x = plane_state->src_x >> 16;
12543 crtc->y = plane_state->src_y >> 16;
12544 }
12545 }
12546 }
12547
12548 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12549 {
12550 int diff;
12551
12552 if (clock1 == clock2)
12553 return true;
12554
12555 if (!clock1 || !clock2)
12556 return false;
12557
12558 diff = abs(clock1 - clock2);
12559
12560 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12561 return true;
12562
12563 return false;
12564 }
12565
12566 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12567 list_for_each_entry((intel_crtc), \
12568 &(dev)->mode_config.crtc_list, \
12569 base.head) \
12570 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12571
12572 static bool
12573 intel_compare_m_n(unsigned int m, unsigned int n,
12574 unsigned int m2, unsigned int n2,
12575 bool exact)
12576 {
12577 if (m == m2 && n == n2)
12578 return true;
12579
12580 if (exact || !m || !n || !m2 || !n2)
12581 return false;
12582
12583 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12584
12585 if (n > n2) {
12586 while (n > n2) {
12587 m2 <<= 1;
12588 n2 <<= 1;
12589 }
12590 } else if (n < n2) {
12591 while (n < n2) {
12592 m <<= 1;
12593 n <<= 1;
12594 }
12595 }
12596
12597 if (n != n2)
12598 return false;
12599
12600 return intel_fuzzy_clock_check(m, m2);
12601 }
12602
12603 static bool
12604 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12605 struct intel_link_m_n *m2_n2,
12606 bool adjust)
12607 {
12608 if (m_n->tu == m2_n2->tu &&
12609 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12610 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12611 intel_compare_m_n(m_n->link_m, m_n->link_n,
12612 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12613 if (adjust)
12614 *m2_n2 = *m_n;
12615
12616 return true;
12617 }
12618
12619 return false;
12620 }
12621
12622 static bool
12623 intel_pipe_config_compare(struct drm_device *dev,
12624 struct intel_crtc_state *current_config,
12625 struct intel_crtc_state *pipe_config,
12626 bool adjust)
12627 {
12628 bool ret = true;
12629
12630 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12631 do { \
12632 if (!adjust) \
12633 DRM_ERROR(fmt, ##__VA_ARGS__); \
12634 else \
12635 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12636 } while (0)
12637
12638 #define PIPE_CONF_CHECK_X(name) \
12639 if (current_config->name != pipe_config->name) { \
12640 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12641 "(expected 0x%08x, found 0x%08x)\n", \
12642 current_config->name, \
12643 pipe_config->name); \
12644 ret = false; \
12645 }
12646
12647 #define PIPE_CONF_CHECK_I(name) \
12648 if (current_config->name != pipe_config->name) { \
12649 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12650 "(expected %i, found %i)\n", \
12651 current_config->name, \
12652 pipe_config->name); \
12653 ret = false; \
12654 }
12655
12656 #define PIPE_CONF_CHECK_P(name) \
12657 if (current_config->name != pipe_config->name) { \
12658 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12659 "(expected %p, found %p)\n", \
12660 current_config->name, \
12661 pipe_config->name); \
12662 ret = false; \
12663 }
12664
12665 #define PIPE_CONF_CHECK_M_N(name) \
12666 if (!intel_compare_link_m_n(&current_config->name, \
12667 &pipe_config->name,\
12668 adjust)) { \
12669 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12670 "(expected tu %i gmch %i/%i link %i/%i, " \
12671 "found tu %i, gmch %i/%i link %i/%i)\n", \
12672 current_config->name.tu, \
12673 current_config->name.gmch_m, \
12674 current_config->name.gmch_n, \
12675 current_config->name.link_m, \
12676 current_config->name.link_n, \
12677 pipe_config->name.tu, \
12678 pipe_config->name.gmch_m, \
12679 pipe_config->name.gmch_n, \
12680 pipe_config->name.link_m, \
12681 pipe_config->name.link_n); \
12682 ret = false; \
12683 }
12684
12685 /* This is required for BDW+ where there is only one set of registers for
12686 * switching between high and low RR.
12687 * This macro can be used whenever a comparison has to be made between one
12688 * hw state and multiple sw state variables.
12689 */
12690 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12691 if (!intel_compare_link_m_n(&current_config->name, \
12692 &pipe_config->name, adjust) && \
12693 !intel_compare_link_m_n(&current_config->alt_name, \
12694 &pipe_config->name, adjust)) { \
12695 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12696 "(expected tu %i gmch %i/%i link %i/%i, " \
12697 "or tu %i gmch %i/%i link %i/%i, " \
12698 "found tu %i, gmch %i/%i link %i/%i)\n", \
12699 current_config->name.tu, \
12700 current_config->name.gmch_m, \
12701 current_config->name.gmch_n, \
12702 current_config->name.link_m, \
12703 current_config->name.link_n, \
12704 current_config->alt_name.tu, \
12705 current_config->alt_name.gmch_m, \
12706 current_config->alt_name.gmch_n, \
12707 current_config->alt_name.link_m, \
12708 current_config->alt_name.link_n, \
12709 pipe_config->name.tu, \
12710 pipe_config->name.gmch_m, \
12711 pipe_config->name.gmch_n, \
12712 pipe_config->name.link_m, \
12713 pipe_config->name.link_n); \
12714 ret = false; \
12715 }
12716
12717 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12718 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12719 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12720 "(expected %i, found %i)\n", \
12721 current_config->name & (mask), \
12722 pipe_config->name & (mask)); \
12723 ret = false; \
12724 }
12725
12726 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12727 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12728 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12729 "(expected %i, found %i)\n", \
12730 current_config->name, \
12731 pipe_config->name); \
12732 ret = false; \
12733 }
12734
12735 #define PIPE_CONF_QUIRK(quirk) \
12736 ((current_config->quirks | pipe_config->quirks) & (quirk))
12737
12738 PIPE_CONF_CHECK_I(cpu_transcoder);
12739
12740 PIPE_CONF_CHECK_I(has_pch_encoder);
12741 PIPE_CONF_CHECK_I(fdi_lanes);
12742 PIPE_CONF_CHECK_M_N(fdi_m_n);
12743
12744 PIPE_CONF_CHECK_I(has_dp_encoder);
12745 PIPE_CONF_CHECK_I(lane_count);
12746
12747 if (INTEL_INFO(dev)->gen < 8) {
12748 PIPE_CONF_CHECK_M_N(dp_m_n);
12749
12750 if (current_config->has_drrs)
12751 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12752 } else
12753 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12754
12755 PIPE_CONF_CHECK_I(has_dsi_encoder);
12756
12757 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12758 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12759 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12760 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12761 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12762 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12763
12764 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12765 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12766 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12767 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12768 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12769 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12770
12771 PIPE_CONF_CHECK_I(pixel_multiplier);
12772 PIPE_CONF_CHECK_I(has_hdmi_sink);
12773 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12774 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12775 PIPE_CONF_CHECK_I(limited_color_range);
12776 PIPE_CONF_CHECK_I(has_infoframe);
12777
12778 PIPE_CONF_CHECK_I(has_audio);
12779
12780 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12781 DRM_MODE_FLAG_INTERLACE);
12782
12783 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12784 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12785 DRM_MODE_FLAG_PHSYNC);
12786 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12787 DRM_MODE_FLAG_NHSYNC);
12788 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12789 DRM_MODE_FLAG_PVSYNC);
12790 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12791 DRM_MODE_FLAG_NVSYNC);
12792 }
12793
12794 PIPE_CONF_CHECK_X(gmch_pfit.control);
12795 /* pfit ratios are autocomputed by the hw on gen4+ */
12796 if (INTEL_INFO(dev)->gen < 4)
12797 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12798 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12799
12800 if (!adjust) {
12801 PIPE_CONF_CHECK_I(pipe_src_w);
12802 PIPE_CONF_CHECK_I(pipe_src_h);
12803
12804 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12805 if (current_config->pch_pfit.enabled) {
12806 PIPE_CONF_CHECK_X(pch_pfit.pos);
12807 PIPE_CONF_CHECK_X(pch_pfit.size);
12808 }
12809
12810 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12811 }
12812
12813 /* BDW+ don't expose a synchronous way to read the state */
12814 if (IS_HASWELL(dev))
12815 PIPE_CONF_CHECK_I(ips_enabled);
12816
12817 PIPE_CONF_CHECK_I(double_wide);
12818
12819 PIPE_CONF_CHECK_X(ddi_pll_sel);
12820
12821 PIPE_CONF_CHECK_P(shared_dpll);
12822 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12823 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12824 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12825 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12826 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12827 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12828 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12829 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12830 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12831
12832 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12833 PIPE_CONF_CHECK_X(dsi_pll.div);
12834
12835 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12836 PIPE_CONF_CHECK_I(pipe_bpp);
12837
12838 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12839 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12840
12841 #undef PIPE_CONF_CHECK_X
12842 #undef PIPE_CONF_CHECK_I
12843 #undef PIPE_CONF_CHECK_P
12844 #undef PIPE_CONF_CHECK_FLAGS
12845 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12846 #undef PIPE_CONF_QUIRK
12847 #undef INTEL_ERR_OR_DBG_KMS
12848
12849 return ret;
12850 }
12851
12852 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12853 const struct intel_crtc_state *pipe_config)
12854 {
12855 if (pipe_config->has_pch_encoder) {
12856 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12857 &pipe_config->fdi_m_n);
12858 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12859
12860 /*
12861 * FDI already provided one idea for the dotclock.
12862 * Yell if the encoder disagrees.
12863 */
12864 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12865 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12866 fdi_dotclock, dotclock);
12867 }
12868 }
12869
12870 static void verify_wm_state(struct drm_crtc *crtc,
12871 struct drm_crtc_state *new_state)
12872 {
12873 struct drm_device *dev = crtc->dev;
12874 struct drm_i915_private *dev_priv = dev->dev_private;
12875 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12876 struct skl_ddb_entry *hw_entry, *sw_entry;
12877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12878 const enum pipe pipe = intel_crtc->pipe;
12879 int plane;
12880
12881 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12882 return;
12883
12884 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12885 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12886
12887 /* planes */
12888 for_each_plane(dev_priv, pipe, plane) {
12889 hw_entry = &hw_ddb.plane[pipe][plane];
12890 sw_entry = &sw_ddb->plane[pipe][plane];
12891
12892 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12893 continue;
12894
12895 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12896 "(expected (%u,%u), found (%u,%u))\n",
12897 pipe_name(pipe), plane + 1,
12898 sw_entry->start, sw_entry->end,
12899 hw_entry->start, hw_entry->end);
12900 }
12901
12902 /* cursor */
12903 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12904 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12905
12906 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12907 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12908 "(expected (%u,%u), found (%u,%u))\n",
12909 pipe_name(pipe),
12910 sw_entry->start, sw_entry->end,
12911 hw_entry->start, hw_entry->end);
12912 }
12913 }
12914
12915 static void
12916 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12917 {
12918 struct drm_connector *connector;
12919
12920 drm_for_each_connector(connector, dev) {
12921 struct drm_encoder *encoder = connector->encoder;
12922 struct drm_connector_state *state = connector->state;
12923
12924 if (state->crtc != crtc)
12925 continue;
12926
12927 intel_connector_verify_state(to_intel_connector(connector));
12928
12929 I915_STATE_WARN(state->best_encoder != encoder,
12930 "connector's atomic encoder doesn't match legacy encoder\n");
12931 }
12932 }
12933
12934 static void
12935 verify_encoder_state(struct drm_device *dev)
12936 {
12937 struct intel_encoder *encoder;
12938 struct intel_connector *connector;
12939
12940 for_each_intel_encoder(dev, encoder) {
12941 bool enabled = false;
12942 enum pipe pipe;
12943
12944 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12945 encoder->base.base.id,
12946 encoder->base.name);
12947
12948 for_each_intel_connector(dev, connector) {
12949 if (connector->base.state->best_encoder != &encoder->base)
12950 continue;
12951 enabled = true;
12952
12953 I915_STATE_WARN(connector->base.state->crtc !=
12954 encoder->base.crtc,
12955 "connector's crtc doesn't match encoder crtc\n");
12956 }
12957
12958 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12959 "encoder's enabled state mismatch "
12960 "(expected %i, found %i)\n",
12961 !!encoder->base.crtc, enabled);
12962
12963 if (!encoder->base.crtc) {
12964 bool active;
12965
12966 active = encoder->get_hw_state(encoder, &pipe);
12967 I915_STATE_WARN(active,
12968 "encoder detached but still enabled on pipe %c.\n",
12969 pipe_name(pipe));
12970 }
12971 }
12972 }
12973
12974 static void
12975 verify_crtc_state(struct drm_crtc *crtc,
12976 struct drm_crtc_state *old_crtc_state,
12977 struct drm_crtc_state *new_crtc_state)
12978 {
12979 struct drm_device *dev = crtc->dev;
12980 struct drm_i915_private *dev_priv = dev->dev_private;
12981 struct intel_encoder *encoder;
12982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12983 struct intel_crtc_state *pipe_config, *sw_config;
12984 struct drm_atomic_state *old_state;
12985 bool active;
12986
12987 old_state = old_crtc_state->state;
12988 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12989 pipe_config = to_intel_crtc_state(old_crtc_state);
12990 memset(pipe_config, 0, sizeof(*pipe_config));
12991 pipe_config->base.crtc = crtc;
12992 pipe_config->base.state = old_state;
12993
12994 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12995
12996 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12997
12998 /* hw state is inconsistent with the pipe quirk */
12999 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13000 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13001 active = new_crtc_state->active;
13002
13003 I915_STATE_WARN(new_crtc_state->active != active,
13004 "crtc active state doesn't match with hw state "
13005 "(expected %i, found %i)\n", new_crtc_state->active, active);
13006
13007 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13008 "transitional active state does not match atomic hw state "
13009 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13010
13011 for_each_encoder_on_crtc(dev, crtc, encoder) {
13012 enum pipe pipe;
13013
13014 active = encoder->get_hw_state(encoder, &pipe);
13015 I915_STATE_WARN(active != new_crtc_state->active,
13016 "[ENCODER:%i] active %i with crtc active %i\n",
13017 encoder->base.base.id, active, new_crtc_state->active);
13018
13019 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13020 "Encoder connected to wrong pipe %c\n",
13021 pipe_name(pipe));
13022
13023 if (active)
13024 encoder->get_config(encoder, pipe_config);
13025 }
13026
13027 if (!new_crtc_state->active)
13028 return;
13029
13030 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13031
13032 sw_config = to_intel_crtc_state(crtc->state);
13033 if (!intel_pipe_config_compare(dev, sw_config,
13034 pipe_config, false)) {
13035 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13036 intel_dump_pipe_config(intel_crtc, pipe_config,
13037 "[hw state]");
13038 intel_dump_pipe_config(intel_crtc, sw_config,
13039 "[sw state]");
13040 }
13041 }
13042
13043 static void
13044 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13045 struct intel_shared_dpll *pll,
13046 struct drm_crtc *crtc,
13047 struct drm_crtc_state *new_state)
13048 {
13049 struct intel_dpll_hw_state dpll_hw_state;
13050 unsigned crtc_mask;
13051 bool active;
13052
13053 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13054
13055 DRM_DEBUG_KMS("%s\n", pll->name);
13056
13057 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13058
13059 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13060 I915_STATE_WARN(!pll->on && pll->active_mask,
13061 "pll in active use but not on in sw tracking\n");
13062 I915_STATE_WARN(pll->on && !pll->active_mask,
13063 "pll is on but not used by any active crtc\n");
13064 I915_STATE_WARN(pll->on != active,
13065 "pll on state mismatch (expected %i, found %i)\n",
13066 pll->on, active);
13067 }
13068
13069 if (!crtc) {
13070 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13071 "more active pll users than references: %x vs %x\n",
13072 pll->active_mask, pll->config.crtc_mask);
13073
13074 return;
13075 }
13076
13077 crtc_mask = 1 << drm_crtc_index(crtc);
13078
13079 if (new_state->active)
13080 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13081 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13082 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13083 else
13084 I915_STATE_WARN(pll->active_mask & crtc_mask,
13085 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13086 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13087
13088 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13089 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13090 crtc_mask, pll->config.crtc_mask);
13091
13092 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13093 &dpll_hw_state,
13094 sizeof(dpll_hw_state)),
13095 "pll hw state mismatch\n");
13096 }
13097
13098 static void
13099 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13100 struct drm_crtc_state *old_crtc_state,
13101 struct drm_crtc_state *new_crtc_state)
13102 {
13103 struct drm_i915_private *dev_priv = dev->dev_private;
13104 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13105 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13106
13107 if (new_state->shared_dpll)
13108 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13109
13110 if (old_state->shared_dpll &&
13111 old_state->shared_dpll != new_state->shared_dpll) {
13112 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13113 struct intel_shared_dpll *pll = old_state->shared_dpll;
13114
13115 I915_STATE_WARN(pll->active_mask & crtc_mask,
13116 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13117 pipe_name(drm_crtc_index(crtc)));
13118 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13119 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13120 pipe_name(drm_crtc_index(crtc)));
13121 }
13122 }
13123
13124 static void
13125 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13126 struct drm_crtc_state *old_state,
13127 struct drm_crtc_state *new_state)
13128 {
13129 if (!needs_modeset(new_state) &&
13130 !to_intel_crtc_state(new_state)->update_pipe)
13131 return;
13132
13133 verify_wm_state(crtc, new_state);
13134 verify_connector_state(crtc->dev, crtc);
13135 verify_crtc_state(crtc, old_state, new_state);
13136 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13137 }
13138
13139 static void
13140 verify_disabled_dpll_state(struct drm_device *dev)
13141 {
13142 struct drm_i915_private *dev_priv = dev->dev_private;
13143 int i;
13144
13145 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13146 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13147 }
13148
13149 static void
13150 intel_modeset_verify_disabled(struct drm_device *dev)
13151 {
13152 verify_encoder_state(dev);
13153 verify_connector_state(dev, NULL);
13154 verify_disabled_dpll_state(dev);
13155 }
13156
13157 static void update_scanline_offset(struct intel_crtc *crtc)
13158 {
13159 struct drm_device *dev = crtc->base.dev;
13160
13161 /*
13162 * The scanline counter increments at the leading edge of hsync.
13163 *
13164 * On most platforms it starts counting from vtotal-1 on the
13165 * first active line. That means the scanline counter value is
13166 * always one less than what we would expect. Ie. just after
13167 * start of vblank, which also occurs at start of hsync (on the
13168 * last active line), the scanline counter will read vblank_start-1.
13169 *
13170 * On gen2 the scanline counter starts counting from 1 instead
13171 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13172 * to keep the value positive), instead of adding one.
13173 *
13174 * On HSW+ the behaviour of the scanline counter depends on the output
13175 * type. For DP ports it behaves like most other platforms, but on HDMI
13176 * there's an extra 1 line difference. So we need to add two instead of
13177 * one to the value.
13178 */
13179 if (IS_GEN2(dev)) {
13180 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13181 int vtotal;
13182
13183 vtotal = adjusted_mode->crtc_vtotal;
13184 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13185 vtotal /= 2;
13186
13187 crtc->scanline_offset = vtotal - 1;
13188 } else if (HAS_DDI(dev) &&
13189 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13190 crtc->scanline_offset = 2;
13191 } else
13192 crtc->scanline_offset = 1;
13193 }
13194
13195 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13196 {
13197 struct drm_device *dev = state->dev;
13198 struct drm_i915_private *dev_priv = to_i915(dev);
13199 struct intel_shared_dpll_config *shared_dpll = NULL;
13200 struct drm_crtc *crtc;
13201 struct drm_crtc_state *crtc_state;
13202 int i;
13203
13204 if (!dev_priv->display.crtc_compute_clock)
13205 return;
13206
13207 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13209 struct intel_shared_dpll *old_dpll =
13210 to_intel_crtc_state(crtc->state)->shared_dpll;
13211
13212 if (!needs_modeset(crtc_state))
13213 continue;
13214
13215 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13216
13217 if (!old_dpll)
13218 continue;
13219
13220 if (!shared_dpll)
13221 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13222
13223 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13224 }
13225 }
13226
13227 /*
13228 * This implements the workaround described in the "notes" section of the mode
13229 * set sequence documentation. When going from no pipes or single pipe to
13230 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13231 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13232 */
13233 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13234 {
13235 struct drm_crtc_state *crtc_state;
13236 struct intel_crtc *intel_crtc;
13237 struct drm_crtc *crtc;
13238 struct intel_crtc_state *first_crtc_state = NULL;
13239 struct intel_crtc_state *other_crtc_state = NULL;
13240 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13241 int i;
13242
13243 /* look at all crtc's that are going to be enabled in during modeset */
13244 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13245 intel_crtc = to_intel_crtc(crtc);
13246
13247 if (!crtc_state->active || !needs_modeset(crtc_state))
13248 continue;
13249
13250 if (first_crtc_state) {
13251 other_crtc_state = to_intel_crtc_state(crtc_state);
13252 break;
13253 } else {
13254 first_crtc_state = to_intel_crtc_state(crtc_state);
13255 first_pipe = intel_crtc->pipe;
13256 }
13257 }
13258
13259 /* No workaround needed? */
13260 if (!first_crtc_state)
13261 return 0;
13262
13263 /* w/a possibly needed, check how many crtc's are already enabled. */
13264 for_each_intel_crtc(state->dev, intel_crtc) {
13265 struct intel_crtc_state *pipe_config;
13266
13267 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13268 if (IS_ERR(pipe_config))
13269 return PTR_ERR(pipe_config);
13270
13271 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13272
13273 if (!pipe_config->base.active ||
13274 needs_modeset(&pipe_config->base))
13275 continue;
13276
13277 /* 2 or more enabled crtcs means no need for w/a */
13278 if (enabled_pipe != INVALID_PIPE)
13279 return 0;
13280
13281 enabled_pipe = intel_crtc->pipe;
13282 }
13283
13284 if (enabled_pipe != INVALID_PIPE)
13285 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13286 else if (other_crtc_state)
13287 other_crtc_state->hsw_workaround_pipe = first_pipe;
13288
13289 return 0;
13290 }
13291
13292 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13293 {
13294 struct drm_crtc *crtc;
13295 struct drm_crtc_state *crtc_state;
13296 int ret = 0;
13297
13298 /* add all active pipes to the state */
13299 for_each_crtc(state->dev, crtc) {
13300 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13301 if (IS_ERR(crtc_state))
13302 return PTR_ERR(crtc_state);
13303
13304 if (!crtc_state->active || needs_modeset(crtc_state))
13305 continue;
13306
13307 crtc_state->mode_changed = true;
13308
13309 ret = drm_atomic_add_affected_connectors(state, crtc);
13310 if (ret)
13311 break;
13312
13313 ret = drm_atomic_add_affected_planes(state, crtc);
13314 if (ret)
13315 break;
13316 }
13317
13318 return ret;
13319 }
13320
13321 static int intel_modeset_checks(struct drm_atomic_state *state)
13322 {
13323 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13324 struct drm_i915_private *dev_priv = state->dev->dev_private;
13325 struct drm_crtc *crtc;
13326 struct drm_crtc_state *crtc_state;
13327 int ret = 0, i;
13328
13329 if (!check_digital_port_conflicts(state)) {
13330 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13331 return -EINVAL;
13332 }
13333
13334 intel_state->modeset = true;
13335 intel_state->active_crtcs = dev_priv->active_crtcs;
13336
13337 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13338 if (crtc_state->active)
13339 intel_state->active_crtcs |= 1 << i;
13340 else
13341 intel_state->active_crtcs &= ~(1 << i);
13342
13343 if (crtc_state->active != crtc->state->active)
13344 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13345 }
13346
13347 /*
13348 * See if the config requires any additional preparation, e.g.
13349 * to adjust global state with pipes off. We need to do this
13350 * here so we can get the modeset_pipe updated config for the new
13351 * mode set on this crtc. For other crtcs we need to use the
13352 * adjusted_mode bits in the crtc directly.
13353 */
13354 if (dev_priv->display.modeset_calc_cdclk) {
13355 if (!intel_state->cdclk_pll_vco)
13356 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13357 if (!intel_state->cdclk_pll_vco)
13358 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13359
13360 ret = dev_priv->display.modeset_calc_cdclk(state);
13361 if (ret < 0)
13362 return ret;
13363
13364 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13365 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13366 ret = intel_modeset_all_pipes(state);
13367
13368 if (ret < 0)
13369 return ret;
13370
13371 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13372 intel_state->cdclk, intel_state->dev_cdclk);
13373 } else
13374 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13375
13376 intel_modeset_clear_plls(state);
13377
13378 if (IS_HASWELL(dev_priv))
13379 return haswell_mode_set_planes_workaround(state);
13380
13381 return 0;
13382 }
13383
13384 /*
13385 * Handle calculation of various watermark data at the end of the atomic check
13386 * phase. The code here should be run after the per-crtc and per-plane 'check'
13387 * handlers to ensure that all derived state has been updated.
13388 */
13389 static int calc_watermark_data(struct drm_atomic_state *state)
13390 {
13391 struct drm_device *dev = state->dev;
13392 struct drm_i915_private *dev_priv = to_i915(dev);
13393
13394 /* Is there platform-specific watermark information to calculate? */
13395 if (dev_priv->display.compute_global_watermarks)
13396 return dev_priv->display.compute_global_watermarks(state);
13397
13398 return 0;
13399 }
13400
13401 /**
13402 * intel_atomic_check - validate state object
13403 * @dev: drm device
13404 * @state: state to validate
13405 */
13406 static int intel_atomic_check(struct drm_device *dev,
13407 struct drm_atomic_state *state)
13408 {
13409 struct drm_i915_private *dev_priv = to_i915(dev);
13410 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13411 struct drm_crtc *crtc;
13412 struct drm_crtc_state *crtc_state;
13413 int ret, i;
13414 bool any_ms = false;
13415
13416 ret = drm_atomic_helper_check_modeset(dev, state);
13417 if (ret)
13418 return ret;
13419
13420 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13421 struct intel_crtc_state *pipe_config =
13422 to_intel_crtc_state(crtc_state);
13423
13424 /* Catch I915_MODE_FLAG_INHERITED */
13425 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13426 crtc_state->mode_changed = true;
13427
13428 if (!needs_modeset(crtc_state))
13429 continue;
13430
13431 if (!crtc_state->enable) {
13432 any_ms = true;
13433 continue;
13434 }
13435
13436 /* FIXME: For only active_changed we shouldn't need to do any
13437 * state recomputation at all. */
13438
13439 ret = drm_atomic_add_affected_connectors(state, crtc);
13440 if (ret)
13441 return ret;
13442
13443 ret = intel_modeset_pipe_config(crtc, pipe_config);
13444 if (ret) {
13445 intel_dump_pipe_config(to_intel_crtc(crtc),
13446 pipe_config, "[failed]");
13447 return ret;
13448 }
13449
13450 if (i915.fastboot &&
13451 intel_pipe_config_compare(dev,
13452 to_intel_crtc_state(crtc->state),
13453 pipe_config, true)) {
13454 crtc_state->mode_changed = false;
13455 to_intel_crtc_state(crtc_state)->update_pipe = true;
13456 }
13457
13458 if (needs_modeset(crtc_state))
13459 any_ms = true;
13460
13461 ret = drm_atomic_add_affected_planes(state, crtc);
13462 if (ret)
13463 return ret;
13464
13465 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13466 needs_modeset(crtc_state) ?
13467 "[modeset]" : "[fastset]");
13468 }
13469
13470 if (any_ms) {
13471 ret = intel_modeset_checks(state);
13472
13473 if (ret)
13474 return ret;
13475 } else
13476 intel_state->cdclk = dev_priv->cdclk_freq;
13477
13478 ret = drm_atomic_helper_check_planes(dev, state);
13479 if (ret)
13480 return ret;
13481
13482 intel_fbc_choose_crtc(dev_priv, state);
13483 return calc_watermark_data(state);
13484 }
13485
13486 static int intel_atomic_prepare_commit(struct drm_device *dev,
13487 struct drm_atomic_state *state,
13488 bool nonblock)
13489 {
13490 struct drm_i915_private *dev_priv = dev->dev_private;
13491 struct drm_plane_state *plane_state;
13492 struct drm_crtc_state *crtc_state;
13493 struct drm_plane *plane;
13494 struct drm_crtc *crtc;
13495 int i, ret;
13496
13497 if (nonblock) {
13498 DRM_DEBUG_KMS("i915 does not yet support nonblocking commit\n");
13499 return -EINVAL;
13500 }
13501
13502 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13503 if (state->legacy_cursor_update)
13504 continue;
13505
13506 ret = intel_crtc_wait_for_pending_flips(crtc);
13507 if (ret)
13508 return ret;
13509
13510 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13511 flush_workqueue(dev_priv->wq);
13512 }
13513
13514 ret = mutex_lock_interruptible(&dev->struct_mutex);
13515 if (ret)
13516 return ret;
13517
13518 ret = drm_atomic_helper_prepare_planes(dev, state);
13519 mutex_unlock(&dev->struct_mutex);
13520
13521 if (!ret && !nonblock) {
13522 for_each_plane_in_state(state, plane, plane_state, i) {
13523 struct intel_plane_state *intel_plane_state =
13524 to_intel_plane_state(plane_state);
13525
13526 if (!intel_plane_state->wait_req)
13527 continue;
13528
13529 ret = __i915_wait_request(intel_plane_state->wait_req,
13530 true, NULL, NULL);
13531 if (ret) {
13532 /* Any hang should be swallowed by the wait */
13533 WARN_ON(ret == -EIO);
13534 mutex_lock(&dev->struct_mutex);
13535 drm_atomic_helper_cleanup_planes(dev, state);
13536 mutex_unlock(&dev->struct_mutex);
13537 break;
13538 }
13539 }
13540 }
13541
13542 return ret;
13543 }
13544
13545 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13546 {
13547 struct drm_device *dev = crtc->base.dev;
13548
13549 if (!dev->max_vblank_count)
13550 return drm_accurate_vblank_count(&crtc->base);
13551
13552 return dev->driver->get_vblank_counter(dev, crtc->pipe);
13553 }
13554
13555 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13556 struct drm_i915_private *dev_priv,
13557 unsigned crtc_mask)
13558 {
13559 unsigned last_vblank_count[I915_MAX_PIPES];
13560 enum pipe pipe;
13561 int ret;
13562
13563 if (!crtc_mask)
13564 return;
13565
13566 for_each_pipe(dev_priv, pipe) {
13567 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13568
13569 if (!((1 << pipe) & crtc_mask))
13570 continue;
13571
13572 ret = drm_crtc_vblank_get(crtc);
13573 if (WARN_ON(ret != 0)) {
13574 crtc_mask &= ~(1 << pipe);
13575 continue;
13576 }
13577
13578 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13579 }
13580
13581 for_each_pipe(dev_priv, pipe) {
13582 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13583 long lret;
13584
13585 if (!((1 << pipe) & crtc_mask))
13586 continue;
13587
13588 lret = wait_event_timeout(dev->vblank[pipe].queue,
13589 last_vblank_count[pipe] !=
13590 drm_crtc_vblank_count(crtc),
13591 msecs_to_jiffies(50));
13592
13593 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13594
13595 drm_crtc_vblank_put(crtc);
13596 }
13597 }
13598
13599 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13600 {
13601 /* fb updated, need to unpin old fb */
13602 if (crtc_state->fb_changed)
13603 return true;
13604
13605 /* wm changes, need vblank before final wm's */
13606 if (crtc_state->update_wm_post)
13607 return true;
13608
13609 /*
13610 * cxsr is re-enabled after vblank.
13611 * This is already handled by crtc_state->update_wm_post,
13612 * but added for clarity.
13613 */
13614 if (crtc_state->disable_cxsr)
13615 return true;
13616
13617 return false;
13618 }
13619
13620 /**
13621 * intel_atomic_commit - commit validated state object
13622 * @dev: DRM device
13623 * @state: the top-level driver state object
13624 * @nonblock: nonblocking commit
13625 *
13626 * This function commits a top-level state object that has been validated
13627 * with drm_atomic_helper_check().
13628 *
13629 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13630 * we can only handle plane-related operations and do not yet support
13631 * nonblocking commit.
13632 *
13633 * RETURNS
13634 * Zero for success or -errno.
13635 */
13636 static int intel_atomic_commit(struct drm_device *dev,
13637 struct drm_atomic_state *state,
13638 bool nonblock)
13639 {
13640 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13641 struct drm_i915_private *dev_priv = dev->dev_private;
13642 struct drm_crtc_state *old_crtc_state;
13643 struct drm_crtc *crtc;
13644 struct intel_crtc_state *intel_cstate;
13645 int ret = 0, i;
13646 bool hw_check = intel_state->modeset;
13647 unsigned long put_domains[I915_MAX_PIPES] = {};
13648 unsigned crtc_vblank_mask = 0;
13649
13650 ret = intel_atomic_prepare_commit(dev, state, nonblock);
13651 if (ret) {
13652 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13653 return ret;
13654 }
13655
13656 drm_atomic_helper_swap_state(dev, state);
13657 dev_priv->wm.distrust_bios_wm = false;
13658 dev_priv->wm.skl_results = intel_state->wm_results;
13659 intel_shared_dpll_commit(state);
13660
13661 if (intel_state->modeset) {
13662 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13663 sizeof(intel_state->min_pixclk));
13664 dev_priv->active_crtcs = intel_state->active_crtcs;
13665 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13666
13667 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13668 }
13669
13670 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13672
13673 if (needs_modeset(crtc->state) ||
13674 to_intel_crtc_state(crtc->state)->update_pipe) {
13675 hw_check = true;
13676
13677 put_domains[to_intel_crtc(crtc)->pipe] =
13678 modeset_get_crtc_power_domains(crtc,
13679 to_intel_crtc_state(crtc->state));
13680 }
13681
13682 if (!needs_modeset(crtc->state))
13683 continue;
13684
13685 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13686
13687 if (old_crtc_state->active) {
13688 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13689 dev_priv->display.crtc_disable(crtc);
13690 intel_crtc->active = false;
13691 intel_fbc_disable(intel_crtc);
13692 intel_disable_shared_dpll(intel_crtc);
13693
13694 /*
13695 * Underruns don't always raise
13696 * interrupts, so check manually.
13697 */
13698 intel_check_cpu_fifo_underruns(dev_priv);
13699 intel_check_pch_fifo_underruns(dev_priv);
13700
13701 if (!crtc->state->active)
13702 intel_update_watermarks(crtc);
13703 }
13704 }
13705
13706 /* Only after disabling all output pipelines that will be changed can we
13707 * update the the output configuration. */
13708 intel_modeset_update_crtc_state(state);
13709
13710 if (intel_state->modeset) {
13711 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13712
13713 if (dev_priv->display.modeset_commit_cdclk &&
13714 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13715 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
13716 dev_priv->display.modeset_commit_cdclk(state);
13717
13718 intel_modeset_verify_disabled(dev);
13719 }
13720
13721 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13722 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13724 bool modeset = needs_modeset(crtc->state);
13725 struct intel_crtc_state *pipe_config =
13726 to_intel_crtc_state(crtc->state);
13727 bool update_pipe = !modeset && pipe_config->update_pipe;
13728
13729 if (modeset && crtc->state->active) {
13730 update_scanline_offset(to_intel_crtc(crtc));
13731 dev_priv->display.crtc_enable(crtc);
13732 }
13733
13734 if (!modeset)
13735 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13736
13737 if (crtc->state->active &&
13738 drm_atomic_get_existing_plane_state(state, crtc->primary))
13739 intel_fbc_enable(intel_crtc);
13740
13741 if (crtc->state->active &&
13742 (crtc->state->planes_changed || update_pipe))
13743 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13744
13745 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13746 crtc_vblank_mask |= 1 << i;
13747 }
13748
13749 /* FIXME: add subpixel order */
13750
13751 if (!state->legacy_cursor_update)
13752 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13753
13754 /*
13755 * Now that the vblank has passed, we can go ahead and program the
13756 * optimal watermarks on platforms that need two-step watermark
13757 * programming.
13758 *
13759 * TODO: Move this (and other cleanup) to an async worker eventually.
13760 */
13761 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13762 intel_cstate = to_intel_crtc_state(crtc->state);
13763
13764 if (dev_priv->display.optimize_watermarks)
13765 dev_priv->display.optimize_watermarks(intel_cstate);
13766 }
13767
13768 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13769 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13770
13771 if (put_domains[i])
13772 modeset_put_power_domains(dev_priv, put_domains[i]);
13773
13774 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13775 }
13776
13777 if (intel_state->modeset)
13778 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13779
13780 mutex_lock(&dev->struct_mutex);
13781 drm_atomic_helper_cleanup_planes(dev, state);
13782 mutex_unlock(&dev->struct_mutex);
13783
13784 drm_atomic_state_free(state);
13785
13786 /* As one of the primary mmio accessors, KMS has a high likelihood
13787 * of triggering bugs in unclaimed access. After we finish
13788 * modesetting, see if an error has been flagged, and if so
13789 * enable debugging for the next modeset - and hope we catch
13790 * the culprit.
13791 *
13792 * XXX note that we assume display power is on at this point.
13793 * This might hold true now but we need to add pm helper to check
13794 * unclaimed only when the hardware is on, as atomic commits
13795 * can happen also when the device is completely off.
13796 */
13797 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13798
13799 return 0;
13800 }
13801
13802 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13803 {
13804 struct drm_device *dev = crtc->dev;
13805 struct drm_atomic_state *state;
13806 struct drm_crtc_state *crtc_state;
13807 int ret;
13808
13809 state = drm_atomic_state_alloc(dev);
13810 if (!state) {
13811 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13812 crtc->base.id);
13813 return;
13814 }
13815
13816 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13817
13818 retry:
13819 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13820 ret = PTR_ERR_OR_ZERO(crtc_state);
13821 if (!ret) {
13822 if (!crtc_state->active)
13823 goto out;
13824
13825 crtc_state->mode_changed = true;
13826 ret = drm_atomic_commit(state);
13827 }
13828
13829 if (ret == -EDEADLK) {
13830 drm_atomic_state_clear(state);
13831 drm_modeset_backoff(state->acquire_ctx);
13832 goto retry;
13833 }
13834
13835 if (ret)
13836 out:
13837 drm_atomic_state_free(state);
13838 }
13839
13840 #undef for_each_intel_crtc_masked
13841
13842 static const struct drm_crtc_funcs intel_crtc_funcs = {
13843 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13844 .set_config = drm_atomic_helper_set_config,
13845 .set_property = drm_atomic_helper_crtc_set_property,
13846 .destroy = intel_crtc_destroy,
13847 .page_flip = intel_crtc_page_flip,
13848 .atomic_duplicate_state = intel_crtc_duplicate_state,
13849 .atomic_destroy_state = intel_crtc_destroy_state,
13850 };
13851
13852 /**
13853 * intel_prepare_plane_fb - Prepare fb for usage on plane
13854 * @plane: drm plane to prepare for
13855 * @fb: framebuffer to prepare for presentation
13856 *
13857 * Prepares a framebuffer for usage on a display plane. Generally this
13858 * involves pinning the underlying object and updating the frontbuffer tracking
13859 * bits. Some older platforms need special physical address handling for
13860 * cursor planes.
13861 *
13862 * Must be called with struct_mutex held.
13863 *
13864 * Returns 0 on success, negative error code on failure.
13865 */
13866 int
13867 intel_prepare_plane_fb(struct drm_plane *plane,
13868 const struct drm_plane_state *new_state)
13869 {
13870 struct drm_device *dev = plane->dev;
13871 struct drm_framebuffer *fb = new_state->fb;
13872 struct intel_plane *intel_plane = to_intel_plane(plane);
13873 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13874 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13875 int ret = 0;
13876
13877 if (!obj && !old_obj)
13878 return 0;
13879
13880 if (old_obj) {
13881 struct drm_crtc_state *crtc_state =
13882 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13883
13884 /* Big Hammer, we also need to ensure that any pending
13885 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13886 * current scanout is retired before unpinning the old
13887 * framebuffer. Note that we rely on userspace rendering
13888 * into the buffer attached to the pipe they are waiting
13889 * on. If not, userspace generates a GPU hang with IPEHR
13890 * point to the MI_WAIT_FOR_EVENT.
13891 *
13892 * This should only fail upon a hung GPU, in which case we
13893 * can safely continue.
13894 */
13895 if (needs_modeset(crtc_state))
13896 ret = i915_gem_object_wait_rendering(old_obj, true);
13897 if (ret) {
13898 /* GPU hangs should have been swallowed by the wait */
13899 WARN_ON(ret == -EIO);
13900 return ret;
13901 }
13902 }
13903
13904 /* For framebuffer backed by dmabuf, wait for fence */
13905 if (obj && obj->base.dma_buf) {
13906 long lret;
13907
13908 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13909 false, true,
13910 MAX_SCHEDULE_TIMEOUT);
13911 if (lret == -ERESTARTSYS)
13912 return lret;
13913
13914 WARN(lret < 0, "waiting returns %li\n", lret);
13915 }
13916
13917 if (!obj) {
13918 ret = 0;
13919 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13920 INTEL_INFO(dev)->cursor_needs_physical) {
13921 int align = IS_I830(dev) ? 16 * 1024 : 256;
13922 ret = i915_gem_object_attach_phys(obj, align);
13923 if (ret)
13924 DRM_DEBUG_KMS("failed to attach phys object\n");
13925 } else {
13926 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13927 }
13928
13929 if (ret == 0) {
13930 if (obj) {
13931 struct intel_plane_state *plane_state =
13932 to_intel_plane_state(new_state);
13933
13934 i915_gem_request_assign(&plane_state->wait_req,
13935 obj->last_write_req);
13936 }
13937
13938 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13939 }
13940
13941 return ret;
13942 }
13943
13944 /**
13945 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13946 * @plane: drm plane to clean up for
13947 * @fb: old framebuffer that was on plane
13948 *
13949 * Cleans up a framebuffer that has just been removed from a plane.
13950 *
13951 * Must be called with struct_mutex held.
13952 */
13953 void
13954 intel_cleanup_plane_fb(struct drm_plane *plane,
13955 const struct drm_plane_state *old_state)
13956 {
13957 struct drm_device *dev = plane->dev;
13958 struct intel_plane *intel_plane = to_intel_plane(plane);
13959 struct intel_plane_state *old_intel_state;
13960 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13961 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13962
13963 old_intel_state = to_intel_plane_state(old_state);
13964
13965 if (!obj && !old_obj)
13966 return;
13967
13968 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13969 !INTEL_INFO(dev)->cursor_needs_physical))
13970 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13971
13972 /* prepare_fb aborted? */
13973 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13974 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13975 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13976
13977 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13978 }
13979
13980 int
13981 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13982 {
13983 int max_scale;
13984 struct drm_device *dev;
13985 struct drm_i915_private *dev_priv;
13986 int crtc_clock, cdclk;
13987
13988 if (!intel_crtc || !crtc_state->base.enable)
13989 return DRM_PLANE_HELPER_NO_SCALING;
13990
13991 dev = intel_crtc->base.dev;
13992 dev_priv = dev->dev_private;
13993 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13994 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13995
13996 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13997 return DRM_PLANE_HELPER_NO_SCALING;
13998
13999 /*
14000 * skl max scale is lower of:
14001 * close to 3 but not 3, -1 is for that purpose
14002 * or
14003 * cdclk/crtc_clock
14004 */
14005 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14006
14007 return max_scale;
14008 }
14009
14010 static int
14011 intel_check_primary_plane(struct drm_plane *plane,
14012 struct intel_crtc_state *crtc_state,
14013 struct intel_plane_state *state)
14014 {
14015 struct drm_crtc *crtc = state->base.crtc;
14016 struct drm_framebuffer *fb = state->base.fb;
14017 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14018 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14019 bool can_position = false;
14020
14021 if (INTEL_INFO(plane->dev)->gen >= 9) {
14022 /* use scaler when colorkey is not required */
14023 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14024 min_scale = 1;
14025 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14026 }
14027 can_position = true;
14028 }
14029
14030 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14031 &state->dst, &state->clip,
14032 min_scale, max_scale,
14033 can_position, true,
14034 &state->visible);
14035 }
14036
14037 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14038 struct drm_crtc_state *old_crtc_state)
14039 {
14040 struct drm_device *dev = crtc->dev;
14041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14042 struct intel_crtc_state *old_intel_state =
14043 to_intel_crtc_state(old_crtc_state);
14044 bool modeset = needs_modeset(crtc->state);
14045
14046 /* Perform vblank evasion around commit operation */
14047 intel_pipe_update_start(intel_crtc);
14048
14049 if (modeset)
14050 return;
14051
14052 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14053 intel_color_set_csc(crtc->state);
14054 intel_color_load_luts(crtc->state);
14055 }
14056
14057 if (to_intel_crtc_state(crtc->state)->update_pipe)
14058 intel_update_pipe_config(intel_crtc, old_intel_state);
14059 else if (INTEL_INFO(dev)->gen >= 9)
14060 skl_detach_scalers(intel_crtc);
14061 }
14062
14063 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14064 struct drm_crtc_state *old_crtc_state)
14065 {
14066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14067
14068 intel_pipe_update_end(intel_crtc, NULL);
14069 }
14070
14071 /**
14072 * intel_plane_destroy - destroy a plane
14073 * @plane: plane to destroy
14074 *
14075 * Common destruction function for all types of planes (primary, cursor,
14076 * sprite).
14077 */
14078 void intel_plane_destroy(struct drm_plane *plane)
14079 {
14080 struct intel_plane *intel_plane = to_intel_plane(plane);
14081 drm_plane_cleanup(plane);
14082 kfree(intel_plane);
14083 }
14084
14085 const struct drm_plane_funcs intel_plane_funcs = {
14086 .update_plane = drm_atomic_helper_update_plane,
14087 .disable_plane = drm_atomic_helper_disable_plane,
14088 .destroy = intel_plane_destroy,
14089 .set_property = drm_atomic_helper_plane_set_property,
14090 .atomic_get_property = intel_plane_atomic_get_property,
14091 .atomic_set_property = intel_plane_atomic_set_property,
14092 .atomic_duplicate_state = intel_plane_duplicate_state,
14093 .atomic_destroy_state = intel_plane_destroy_state,
14094
14095 };
14096
14097 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14098 int pipe)
14099 {
14100 struct intel_plane *primary = NULL;
14101 struct intel_plane_state *state = NULL;
14102 const uint32_t *intel_primary_formats;
14103 unsigned int num_formats;
14104 int ret;
14105
14106 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14107 if (!primary)
14108 goto fail;
14109
14110 state = intel_create_plane_state(&primary->base);
14111 if (!state)
14112 goto fail;
14113 primary->base.state = &state->base;
14114
14115 primary->can_scale = false;
14116 primary->max_downscale = 1;
14117 if (INTEL_INFO(dev)->gen >= 9) {
14118 primary->can_scale = true;
14119 state->scaler_id = -1;
14120 }
14121 primary->pipe = pipe;
14122 primary->plane = pipe;
14123 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14124 primary->check_plane = intel_check_primary_plane;
14125 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14126 primary->plane = !pipe;
14127
14128 if (INTEL_INFO(dev)->gen >= 9) {
14129 intel_primary_formats = skl_primary_formats;
14130 num_formats = ARRAY_SIZE(skl_primary_formats);
14131
14132 primary->update_plane = skylake_update_primary_plane;
14133 primary->disable_plane = skylake_disable_primary_plane;
14134 } else if (HAS_PCH_SPLIT(dev)) {
14135 intel_primary_formats = i965_primary_formats;
14136 num_formats = ARRAY_SIZE(i965_primary_formats);
14137
14138 primary->update_plane = ironlake_update_primary_plane;
14139 primary->disable_plane = i9xx_disable_primary_plane;
14140 } else if (INTEL_INFO(dev)->gen >= 4) {
14141 intel_primary_formats = i965_primary_formats;
14142 num_formats = ARRAY_SIZE(i965_primary_formats);
14143
14144 primary->update_plane = i9xx_update_primary_plane;
14145 primary->disable_plane = i9xx_disable_primary_plane;
14146 } else {
14147 intel_primary_formats = i8xx_primary_formats;
14148 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14149
14150 primary->update_plane = i9xx_update_primary_plane;
14151 primary->disable_plane = i9xx_disable_primary_plane;
14152 }
14153
14154 ret = drm_universal_plane_init(dev, &primary->base, 0,
14155 &intel_plane_funcs,
14156 intel_primary_formats, num_formats,
14157 DRM_PLANE_TYPE_PRIMARY, NULL);
14158 if (ret)
14159 goto fail;
14160
14161 if (INTEL_INFO(dev)->gen >= 4)
14162 intel_create_rotation_property(dev, primary);
14163
14164 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14165
14166 return &primary->base;
14167
14168 fail:
14169 kfree(state);
14170 kfree(primary);
14171
14172 return NULL;
14173 }
14174
14175 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14176 {
14177 if (!dev->mode_config.rotation_property) {
14178 unsigned long flags = BIT(DRM_ROTATE_0) |
14179 BIT(DRM_ROTATE_180);
14180
14181 if (INTEL_INFO(dev)->gen >= 9)
14182 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14183
14184 dev->mode_config.rotation_property =
14185 drm_mode_create_rotation_property(dev, flags);
14186 }
14187 if (dev->mode_config.rotation_property)
14188 drm_object_attach_property(&plane->base.base,
14189 dev->mode_config.rotation_property,
14190 plane->base.state->rotation);
14191 }
14192
14193 static int
14194 intel_check_cursor_plane(struct drm_plane *plane,
14195 struct intel_crtc_state *crtc_state,
14196 struct intel_plane_state *state)
14197 {
14198 struct drm_crtc *crtc = crtc_state->base.crtc;
14199 struct drm_framebuffer *fb = state->base.fb;
14200 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14201 enum pipe pipe = to_intel_plane(plane)->pipe;
14202 unsigned stride;
14203 int ret;
14204
14205 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14206 &state->dst, &state->clip,
14207 DRM_PLANE_HELPER_NO_SCALING,
14208 DRM_PLANE_HELPER_NO_SCALING,
14209 true, true, &state->visible);
14210 if (ret)
14211 return ret;
14212
14213 /* if we want to turn off the cursor ignore width and height */
14214 if (!obj)
14215 return 0;
14216
14217 /* Check for which cursor types we support */
14218 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14219 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14220 state->base.crtc_w, state->base.crtc_h);
14221 return -EINVAL;
14222 }
14223
14224 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14225 if (obj->base.size < stride * state->base.crtc_h) {
14226 DRM_DEBUG_KMS("buffer is too small\n");
14227 return -ENOMEM;
14228 }
14229
14230 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14231 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14232 return -EINVAL;
14233 }
14234
14235 /*
14236 * There's something wrong with the cursor on CHV pipe C.
14237 * If it straddles the left edge of the screen then
14238 * moving it away from the edge or disabling it often
14239 * results in a pipe underrun, and often that can lead to
14240 * dead pipe (constant underrun reported, and it scans
14241 * out just a solid color). To recover from that, the
14242 * display power well must be turned off and on again.
14243 * Refuse the put the cursor into that compromised position.
14244 */
14245 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14246 state->visible && state->base.crtc_x < 0) {
14247 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14248 return -EINVAL;
14249 }
14250
14251 return 0;
14252 }
14253
14254 static void
14255 intel_disable_cursor_plane(struct drm_plane *plane,
14256 struct drm_crtc *crtc)
14257 {
14258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14259
14260 intel_crtc->cursor_addr = 0;
14261 intel_crtc_update_cursor(crtc, NULL);
14262 }
14263
14264 static void
14265 intel_update_cursor_plane(struct drm_plane *plane,
14266 const struct intel_crtc_state *crtc_state,
14267 const struct intel_plane_state *state)
14268 {
14269 struct drm_crtc *crtc = crtc_state->base.crtc;
14270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14271 struct drm_device *dev = plane->dev;
14272 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14273 uint32_t addr;
14274
14275 if (!obj)
14276 addr = 0;
14277 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14278 addr = i915_gem_obj_ggtt_offset(obj);
14279 else
14280 addr = obj->phys_handle->busaddr;
14281
14282 intel_crtc->cursor_addr = addr;
14283 intel_crtc_update_cursor(crtc, state);
14284 }
14285
14286 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14287 int pipe)
14288 {
14289 struct intel_plane *cursor = NULL;
14290 struct intel_plane_state *state = NULL;
14291 int ret;
14292
14293 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14294 if (!cursor)
14295 goto fail;
14296
14297 state = intel_create_plane_state(&cursor->base);
14298 if (!state)
14299 goto fail;
14300 cursor->base.state = &state->base;
14301
14302 cursor->can_scale = false;
14303 cursor->max_downscale = 1;
14304 cursor->pipe = pipe;
14305 cursor->plane = pipe;
14306 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14307 cursor->check_plane = intel_check_cursor_plane;
14308 cursor->update_plane = intel_update_cursor_plane;
14309 cursor->disable_plane = intel_disable_cursor_plane;
14310
14311 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14312 &intel_plane_funcs,
14313 intel_cursor_formats,
14314 ARRAY_SIZE(intel_cursor_formats),
14315 DRM_PLANE_TYPE_CURSOR, NULL);
14316 if (ret)
14317 goto fail;
14318
14319 if (INTEL_INFO(dev)->gen >= 4) {
14320 if (!dev->mode_config.rotation_property)
14321 dev->mode_config.rotation_property =
14322 drm_mode_create_rotation_property(dev,
14323 BIT(DRM_ROTATE_0) |
14324 BIT(DRM_ROTATE_180));
14325 if (dev->mode_config.rotation_property)
14326 drm_object_attach_property(&cursor->base.base,
14327 dev->mode_config.rotation_property,
14328 state->base.rotation);
14329 }
14330
14331 if (INTEL_INFO(dev)->gen >=9)
14332 state->scaler_id = -1;
14333
14334 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14335
14336 return &cursor->base;
14337
14338 fail:
14339 kfree(state);
14340 kfree(cursor);
14341
14342 return NULL;
14343 }
14344
14345 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14346 struct intel_crtc_state *crtc_state)
14347 {
14348 int i;
14349 struct intel_scaler *intel_scaler;
14350 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14351
14352 for (i = 0; i < intel_crtc->num_scalers; i++) {
14353 intel_scaler = &scaler_state->scalers[i];
14354 intel_scaler->in_use = 0;
14355 intel_scaler->mode = PS_SCALER_MODE_DYN;
14356 }
14357
14358 scaler_state->scaler_id = -1;
14359 }
14360
14361 static void intel_crtc_init(struct drm_device *dev, int pipe)
14362 {
14363 struct drm_i915_private *dev_priv = dev->dev_private;
14364 struct intel_crtc *intel_crtc;
14365 struct intel_crtc_state *crtc_state = NULL;
14366 struct drm_plane *primary = NULL;
14367 struct drm_plane *cursor = NULL;
14368 int ret;
14369
14370 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14371 if (intel_crtc == NULL)
14372 return;
14373
14374 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14375 if (!crtc_state)
14376 goto fail;
14377 intel_crtc->config = crtc_state;
14378 intel_crtc->base.state = &crtc_state->base;
14379 crtc_state->base.crtc = &intel_crtc->base;
14380
14381 /* initialize shared scalers */
14382 if (INTEL_INFO(dev)->gen >= 9) {
14383 if (pipe == PIPE_C)
14384 intel_crtc->num_scalers = 1;
14385 else
14386 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14387
14388 skl_init_scalers(dev, intel_crtc, crtc_state);
14389 }
14390
14391 primary = intel_primary_plane_create(dev, pipe);
14392 if (!primary)
14393 goto fail;
14394
14395 cursor = intel_cursor_plane_create(dev, pipe);
14396 if (!cursor)
14397 goto fail;
14398
14399 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14400 cursor, &intel_crtc_funcs, NULL);
14401 if (ret)
14402 goto fail;
14403
14404 /*
14405 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14406 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14407 */
14408 intel_crtc->pipe = pipe;
14409 intel_crtc->plane = pipe;
14410 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14411 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14412 intel_crtc->plane = !pipe;
14413 }
14414
14415 intel_crtc->cursor_base = ~0;
14416 intel_crtc->cursor_cntl = ~0;
14417 intel_crtc->cursor_size = ~0;
14418
14419 intel_crtc->wm.cxsr_allowed = true;
14420
14421 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14422 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14423 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14424 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14425
14426 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14427
14428 intel_color_init(&intel_crtc->base);
14429
14430 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14431 return;
14432
14433 fail:
14434 if (primary)
14435 drm_plane_cleanup(primary);
14436 if (cursor)
14437 drm_plane_cleanup(cursor);
14438 kfree(crtc_state);
14439 kfree(intel_crtc);
14440 }
14441
14442 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14443 {
14444 struct drm_encoder *encoder = connector->base.encoder;
14445 struct drm_device *dev = connector->base.dev;
14446
14447 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14448
14449 if (!encoder || WARN_ON(!encoder->crtc))
14450 return INVALID_PIPE;
14451
14452 return to_intel_crtc(encoder->crtc)->pipe;
14453 }
14454
14455 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14456 struct drm_file *file)
14457 {
14458 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14459 struct drm_crtc *drmmode_crtc;
14460 struct intel_crtc *crtc;
14461
14462 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14463
14464 if (!drmmode_crtc) {
14465 DRM_ERROR("no such CRTC id\n");
14466 return -ENOENT;
14467 }
14468
14469 crtc = to_intel_crtc(drmmode_crtc);
14470 pipe_from_crtc_id->pipe = crtc->pipe;
14471
14472 return 0;
14473 }
14474
14475 static int intel_encoder_clones(struct intel_encoder *encoder)
14476 {
14477 struct drm_device *dev = encoder->base.dev;
14478 struct intel_encoder *source_encoder;
14479 int index_mask = 0;
14480 int entry = 0;
14481
14482 for_each_intel_encoder(dev, source_encoder) {
14483 if (encoders_cloneable(encoder, source_encoder))
14484 index_mask |= (1 << entry);
14485
14486 entry++;
14487 }
14488
14489 return index_mask;
14490 }
14491
14492 static bool has_edp_a(struct drm_device *dev)
14493 {
14494 struct drm_i915_private *dev_priv = dev->dev_private;
14495
14496 if (!IS_MOBILE(dev))
14497 return false;
14498
14499 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14500 return false;
14501
14502 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14503 return false;
14504
14505 return true;
14506 }
14507
14508 static bool intel_crt_present(struct drm_device *dev)
14509 {
14510 struct drm_i915_private *dev_priv = dev->dev_private;
14511
14512 if (INTEL_INFO(dev)->gen >= 9)
14513 return false;
14514
14515 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14516 return false;
14517
14518 if (IS_CHERRYVIEW(dev))
14519 return false;
14520
14521 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14522 return false;
14523
14524 /* DDI E can't be used if DDI A requires 4 lanes */
14525 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14526 return false;
14527
14528 if (!dev_priv->vbt.int_crt_support)
14529 return false;
14530
14531 return true;
14532 }
14533
14534 static void intel_setup_outputs(struct drm_device *dev)
14535 {
14536 struct drm_i915_private *dev_priv = dev->dev_private;
14537 struct intel_encoder *encoder;
14538 bool dpd_is_edp = false;
14539
14540 intel_lvds_init(dev);
14541
14542 if (intel_crt_present(dev))
14543 intel_crt_init(dev);
14544
14545 if (IS_BROXTON(dev)) {
14546 /*
14547 * FIXME: Broxton doesn't support port detection via the
14548 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14549 * detect the ports.
14550 */
14551 intel_ddi_init(dev, PORT_A);
14552 intel_ddi_init(dev, PORT_B);
14553 intel_ddi_init(dev, PORT_C);
14554
14555 intel_dsi_init(dev);
14556 } else if (HAS_DDI(dev)) {
14557 int found;
14558
14559 /*
14560 * Haswell uses DDI functions to detect digital outputs.
14561 * On SKL pre-D0 the strap isn't connected, so we assume
14562 * it's there.
14563 */
14564 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14565 /* WaIgnoreDDIAStrap: skl */
14566 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14567 intel_ddi_init(dev, PORT_A);
14568
14569 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14570 * register */
14571 found = I915_READ(SFUSE_STRAP);
14572
14573 if (found & SFUSE_STRAP_DDIB_DETECTED)
14574 intel_ddi_init(dev, PORT_B);
14575 if (found & SFUSE_STRAP_DDIC_DETECTED)
14576 intel_ddi_init(dev, PORT_C);
14577 if (found & SFUSE_STRAP_DDID_DETECTED)
14578 intel_ddi_init(dev, PORT_D);
14579 /*
14580 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14581 */
14582 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14583 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14584 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14585 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14586 intel_ddi_init(dev, PORT_E);
14587
14588 } else if (HAS_PCH_SPLIT(dev)) {
14589 int found;
14590 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14591
14592 if (has_edp_a(dev))
14593 intel_dp_init(dev, DP_A, PORT_A);
14594
14595 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14596 /* PCH SDVOB multiplex with HDMIB */
14597 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14598 if (!found)
14599 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14600 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14601 intel_dp_init(dev, PCH_DP_B, PORT_B);
14602 }
14603
14604 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14605 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14606
14607 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14608 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14609
14610 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14611 intel_dp_init(dev, PCH_DP_C, PORT_C);
14612
14613 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14614 intel_dp_init(dev, PCH_DP_D, PORT_D);
14615 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14616 /*
14617 * The DP_DETECTED bit is the latched state of the DDC
14618 * SDA pin at boot. However since eDP doesn't require DDC
14619 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14620 * eDP ports may have been muxed to an alternate function.
14621 * Thus we can't rely on the DP_DETECTED bit alone to detect
14622 * eDP ports. Consult the VBT as well as DP_DETECTED to
14623 * detect eDP ports.
14624 */
14625 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14626 !intel_dp_is_edp(dev, PORT_B))
14627 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14628 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14629 intel_dp_is_edp(dev, PORT_B))
14630 intel_dp_init(dev, VLV_DP_B, PORT_B);
14631
14632 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14633 !intel_dp_is_edp(dev, PORT_C))
14634 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14635 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14636 intel_dp_is_edp(dev, PORT_C))
14637 intel_dp_init(dev, VLV_DP_C, PORT_C);
14638
14639 if (IS_CHERRYVIEW(dev)) {
14640 /* eDP not supported on port D, so don't check VBT */
14641 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14642 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14643 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14644 intel_dp_init(dev, CHV_DP_D, PORT_D);
14645 }
14646
14647 intel_dsi_init(dev);
14648 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14649 bool found = false;
14650
14651 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14652 DRM_DEBUG_KMS("probing SDVOB\n");
14653 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14654 if (!found && IS_G4X(dev)) {
14655 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14656 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14657 }
14658
14659 if (!found && IS_G4X(dev))
14660 intel_dp_init(dev, DP_B, PORT_B);
14661 }
14662
14663 /* Before G4X SDVOC doesn't have its own detect register */
14664
14665 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14666 DRM_DEBUG_KMS("probing SDVOC\n");
14667 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14668 }
14669
14670 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14671
14672 if (IS_G4X(dev)) {
14673 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14674 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14675 }
14676 if (IS_G4X(dev))
14677 intel_dp_init(dev, DP_C, PORT_C);
14678 }
14679
14680 if (IS_G4X(dev) &&
14681 (I915_READ(DP_D) & DP_DETECTED))
14682 intel_dp_init(dev, DP_D, PORT_D);
14683 } else if (IS_GEN2(dev))
14684 intel_dvo_init(dev);
14685
14686 if (SUPPORTS_TV(dev))
14687 intel_tv_init(dev);
14688
14689 intel_psr_init(dev);
14690
14691 for_each_intel_encoder(dev, encoder) {
14692 encoder->base.possible_crtcs = encoder->crtc_mask;
14693 encoder->base.possible_clones =
14694 intel_encoder_clones(encoder);
14695 }
14696
14697 intel_init_pch_refclk(dev);
14698
14699 drm_helper_move_panel_connectors_to_head(dev);
14700 }
14701
14702 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14703 {
14704 struct drm_device *dev = fb->dev;
14705 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14706
14707 drm_framebuffer_cleanup(fb);
14708 mutex_lock(&dev->struct_mutex);
14709 WARN_ON(!intel_fb->obj->framebuffer_references--);
14710 drm_gem_object_unreference(&intel_fb->obj->base);
14711 mutex_unlock(&dev->struct_mutex);
14712 kfree(intel_fb);
14713 }
14714
14715 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14716 struct drm_file *file,
14717 unsigned int *handle)
14718 {
14719 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14720 struct drm_i915_gem_object *obj = intel_fb->obj;
14721
14722 if (obj->userptr.mm) {
14723 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14724 return -EINVAL;
14725 }
14726
14727 return drm_gem_handle_create(file, &obj->base, handle);
14728 }
14729
14730 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14731 struct drm_file *file,
14732 unsigned flags, unsigned color,
14733 struct drm_clip_rect *clips,
14734 unsigned num_clips)
14735 {
14736 struct drm_device *dev = fb->dev;
14737 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14738 struct drm_i915_gem_object *obj = intel_fb->obj;
14739
14740 mutex_lock(&dev->struct_mutex);
14741 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14742 mutex_unlock(&dev->struct_mutex);
14743
14744 return 0;
14745 }
14746
14747 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14748 .destroy = intel_user_framebuffer_destroy,
14749 .create_handle = intel_user_framebuffer_create_handle,
14750 .dirty = intel_user_framebuffer_dirty,
14751 };
14752
14753 static
14754 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14755 uint32_t pixel_format)
14756 {
14757 u32 gen = INTEL_INFO(dev)->gen;
14758
14759 if (gen >= 9) {
14760 int cpp = drm_format_plane_cpp(pixel_format, 0);
14761
14762 /* "The stride in bytes must not exceed the of the size of 8K
14763 * pixels and 32K bytes."
14764 */
14765 return min(8192 * cpp, 32768);
14766 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14767 return 32*1024;
14768 } else if (gen >= 4) {
14769 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14770 return 16*1024;
14771 else
14772 return 32*1024;
14773 } else if (gen >= 3) {
14774 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14775 return 8*1024;
14776 else
14777 return 16*1024;
14778 } else {
14779 /* XXX DSPC is limited to 4k tiled */
14780 return 8*1024;
14781 }
14782 }
14783
14784 static int intel_framebuffer_init(struct drm_device *dev,
14785 struct intel_framebuffer *intel_fb,
14786 struct drm_mode_fb_cmd2 *mode_cmd,
14787 struct drm_i915_gem_object *obj)
14788 {
14789 struct drm_i915_private *dev_priv = to_i915(dev);
14790 unsigned int aligned_height;
14791 int ret;
14792 u32 pitch_limit, stride_alignment;
14793
14794 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14795
14796 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14797 /* Enforce that fb modifier and tiling mode match, but only for
14798 * X-tiled. This is needed for FBC. */
14799 if (!!(obj->tiling_mode == I915_TILING_X) !=
14800 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14801 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14802 return -EINVAL;
14803 }
14804 } else {
14805 if (obj->tiling_mode == I915_TILING_X)
14806 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14807 else if (obj->tiling_mode == I915_TILING_Y) {
14808 DRM_DEBUG("No Y tiling for legacy addfb\n");
14809 return -EINVAL;
14810 }
14811 }
14812
14813 /* Passed in modifier sanity checking. */
14814 switch (mode_cmd->modifier[0]) {
14815 case I915_FORMAT_MOD_Y_TILED:
14816 case I915_FORMAT_MOD_Yf_TILED:
14817 if (INTEL_INFO(dev)->gen < 9) {
14818 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14819 mode_cmd->modifier[0]);
14820 return -EINVAL;
14821 }
14822 case DRM_FORMAT_MOD_NONE:
14823 case I915_FORMAT_MOD_X_TILED:
14824 break;
14825 default:
14826 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14827 mode_cmd->modifier[0]);
14828 return -EINVAL;
14829 }
14830
14831 stride_alignment = intel_fb_stride_alignment(dev_priv,
14832 mode_cmd->modifier[0],
14833 mode_cmd->pixel_format);
14834 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14835 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14836 mode_cmd->pitches[0], stride_alignment);
14837 return -EINVAL;
14838 }
14839
14840 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14841 mode_cmd->pixel_format);
14842 if (mode_cmd->pitches[0] > pitch_limit) {
14843 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14844 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14845 "tiled" : "linear",
14846 mode_cmd->pitches[0], pitch_limit);
14847 return -EINVAL;
14848 }
14849
14850 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14851 mode_cmd->pitches[0] != obj->stride) {
14852 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14853 mode_cmd->pitches[0], obj->stride);
14854 return -EINVAL;
14855 }
14856
14857 /* Reject formats not supported by any plane early. */
14858 switch (mode_cmd->pixel_format) {
14859 case DRM_FORMAT_C8:
14860 case DRM_FORMAT_RGB565:
14861 case DRM_FORMAT_XRGB8888:
14862 case DRM_FORMAT_ARGB8888:
14863 break;
14864 case DRM_FORMAT_XRGB1555:
14865 if (INTEL_INFO(dev)->gen > 3) {
14866 DRM_DEBUG("unsupported pixel format: %s\n",
14867 drm_get_format_name(mode_cmd->pixel_format));
14868 return -EINVAL;
14869 }
14870 break;
14871 case DRM_FORMAT_ABGR8888:
14872 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14873 INTEL_INFO(dev)->gen < 9) {
14874 DRM_DEBUG("unsupported pixel format: %s\n",
14875 drm_get_format_name(mode_cmd->pixel_format));
14876 return -EINVAL;
14877 }
14878 break;
14879 case DRM_FORMAT_XBGR8888:
14880 case DRM_FORMAT_XRGB2101010:
14881 case DRM_FORMAT_XBGR2101010:
14882 if (INTEL_INFO(dev)->gen < 4) {
14883 DRM_DEBUG("unsupported pixel format: %s\n",
14884 drm_get_format_name(mode_cmd->pixel_format));
14885 return -EINVAL;
14886 }
14887 break;
14888 case DRM_FORMAT_ABGR2101010:
14889 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14890 DRM_DEBUG("unsupported pixel format: %s\n",
14891 drm_get_format_name(mode_cmd->pixel_format));
14892 return -EINVAL;
14893 }
14894 break;
14895 case DRM_FORMAT_YUYV:
14896 case DRM_FORMAT_UYVY:
14897 case DRM_FORMAT_YVYU:
14898 case DRM_FORMAT_VYUY:
14899 if (INTEL_INFO(dev)->gen < 5) {
14900 DRM_DEBUG("unsupported pixel format: %s\n",
14901 drm_get_format_name(mode_cmd->pixel_format));
14902 return -EINVAL;
14903 }
14904 break;
14905 default:
14906 DRM_DEBUG("unsupported pixel format: %s\n",
14907 drm_get_format_name(mode_cmd->pixel_format));
14908 return -EINVAL;
14909 }
14910
14911 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14912 if (mode_cmd->offsets[0] != 0)
14913 return -EINVAL;
14914
14915 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14916 mode_cmd->pixel_format,
14917 mode_cmd->modifier[0]);
14918 /* FIXME drm helper for size checks (especially planar formats)? */
14919 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14920 return -EINVAL;
14921
14922 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14923 intel_fb->obj = obj;
14924
14925 intel_fill_fb_info(dev_priv, &intel_fb->base);
14926
14927 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14928 if (ret) {
14929 DRM_ERROR("framebuffer init failed %d\n", ret);
14930 return ret;
14931 }
14932
14933 intel_fb->obj->framebuffer_references++;
14934
14935 return 0;
14936 }
14937
14938 static struct drm_framebuffer *
14939 intel_user_framebuffer_create(struct drm_device *dev,
14940 struct drm_file *filp,
14941 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14942 {
14943 struct drm_framebuffer *fb;
14944 struct drm_i915_gem_object *obj;
14945 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14946
14947 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14948 mode_cmd.handles[0]));
14949 if (&obj->base == NULL)
14950 return ERR_PTR(-ENOENT);
14951
14952 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14953 if (IS_ERR(fb))
14954 drm_gem_object_unreference_unlocked(&obj->base);
14955
14956 return fb;
14957 }
14958
14959 #ifndef CONFIG_DRM_FBDEV_EMULATION
14960 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14961 {
14962 }
14963 #endif
14964
14965 static const struct drm_mode_config_funcs intel_mode_funcs = {
14966 .fb_create = intel_user_framebuffer_create,
14967 .output_poll_changed = intel_fbdev_output_poll_changed,
14968 .atomic_check = intel_atomic_check,
14969 .atomic_commit = intel_atomic_commit,
14970 .atomic_state_alloc = intel_atomic_state_alloc,
14971 .atomic_state_clear = intel_atomic_state_clear,
14972 };
14973
14974 /**
14975 * intel_init_display_hooks - initialize the display modesetting hooks
14976 * @dev_priv: device private
14977 */
14978 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14979 {
14980 if (INTEL_INFO(dev_priv)->gen >= 9) {
14981 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14982 dev_priv->display.get_initial_plane_config =
14983 skylake_get_initial_plane_config;
14984 dev_priv->display.crtc_compute_clock =
14985 haswell_crtc_compute_clock;
14986 dev_priv->display.crtc_enable = haswell_crtc_enable;
14987 dev_priv->display.crtc_disable = haswell_crtc_disable;
14988 } else if (HAS_DDI(dev_priv)) {
14989 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14990 dev_priv->display.get_initial_plane_config =
14991 ironlake_get_initial_plane_config;
14992 dev_priv->display.crtc_compute_clock =
14993 haswell_crtc_compute_clock;
14994 dev_priv->display.crtc_enable = haswell_crtc_enable;
14995 dev_priv->display.crtc_disable = haswell_crtc_disable;
14996 } else if (HAS_PCH_SPLIT(dev_priv)) {
14997 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14998 dev_priv->display.get_initial_plane_config =
14999 ironlake_get_initial_plane_config;
15000 dev_priv->display.crtc_compute_clock =
15001 ironlake_crtc_compute_clock;
15002 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15003 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15004 } else if (IS_CHERRYVIEW(dev_priv)) {
15005 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15006 dev_priv->display.get_initial_plane_config =
15007 i9xx_get_initial_plane_config;
15008 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15009 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15010 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15011 } else if (IS_VALLEYVIEW(dev_priv)) {
15012 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15013 dev_priv->display.get_initial_plane_config =
15014 i9xx_get_initial_plane_config;
15015 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15016 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15017 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15018 } else if (IS_G4X(dev_priv)) {
15019 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15020 dev_priv->display.get_initial_plane_config =
15021 i9xx_get_initial_plane_config;
15022 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15023 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15024 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15025 } else if (IS_PINEVIEW(dev_priv)) {
15026 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15027 dev_priv->display.get_initial_plane_config =
15028 i9xx_get_initial_plane_config;
15029 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15030 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15031 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15032 } else if (!IS_GEN2(dev_priv)) {
15033 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15034 dev_priv->display.get_initial_plane_config =
15035 i9xx_get_initial_plane_config;
15036 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15037 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15038 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15039 } else {
15040 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15041 dev_priv->display.get_initial_plane_config =
15042 i9xx_get_initial_plane_config;
15043 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15044 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15045 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15046 }
15047
15048 /* Returns the core display clock speed */
15049 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15050 dev_priv->display.get_display_clock_speed =
15051 skylake_get_display_clock_speed;
15052 else if (IS_BROXTON(dev_priv))
15053 dev_priv->display.get_display_clock_speed =
15054 broxton_get_display_clock_speed;
15055 else if (IS_BROADWELL(dev_priv))
15056 dev_priv->display.get_display_clock_speed =
15057 broadwell_get_display_clock_speed;
15058 else if (IS_HASWELL(dev_priv))
15059 dev_priv->display.get_display_clock_speed =
15060 haswell_get_display_clock_speed;
15061 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15062 dev_priv->display.get_display_clock_speed =
15063 valleyview_get_display_clock_speed;
15064 else if (IS_GEN5(dev_priv))
15065 dev_priv->display.get_display_clock_speed =
15066 ilk_get_display_clock_speed;
15067 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15068 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15069 dev_priv->display.get_display_clock_speed =
15070 i945_get_display_clock_speed;
15071 else if (IS_GM45(dev_priv))
15072 dev_priv->display.get_display_clock_speed =
15073 gm45_get_display_clock_speed;
15074 else if (IS_CRESTLINE(dev_priv))
15075 dev_priv->display.get_display_clock_speed =
15076 i965gm_get_display_clock_speed;
15077 else if (IS_PINEVIEW(dev_priv))
15078 dev_priv->display.get_display_clock_speed =
15079 pnv_get_display_clock_speed;
15080 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15081 dev_priv->display.get_display_clock_speed =
15082 g33_get_display_clock_speed;
15083 else if (IS_I915G(dev_priv))
15084 dev_priv->display.get_display_clock_speed =
15085 i915_get_display_clock_speed;
15086 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15087 dev_priv->display.get_display_clock_speed =
15088 i9xx_misc_get_display_clock_speed;
15089 else if (IS_I915GM(dev_priv))
15090 dev_priv->display.get_display_clock_speed =
15091 i915gm_get_display_clock_speed;
15092 else if (IS_I865G(dev_priv))
15093 dev_priv->display.get_display_clock_speed =
15094 i865_get_display_clock_speed;
15095 else if (IS_I85X(dev_priv))
15096 dev_priv->display.get_display_clock_speed =
15097 i85x_get_display_clock_speed;
15098 else { /* 830 */
15099 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15100 dev_priv->display.get_display_clock_speed =
15101 i830_get_display_clock_speed;
15102 }
15103
15104 if (IS_GEN5(dev_priv)) {
15105 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15106 } else if (IS_GEN6(dev_priv)) {
15107 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15108 } else if (IS_IVYBRIDGE(dev_priv)) {
15109 /* FIXME: detect B0+ stepping and use auto training */
15110 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15111 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15112 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15113 }
15114
15115 if (IS_BROADWELL(dev_priv)) {
15116 dev_priv->display.modeset_commit_cdclk =
15117 broadwell_modeset_commit_cdclk;
15118 dev_priv->display.modeset_calc_cdclk =
15119 broadwell_modeset_calc_cdclk;
15120 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15121 dev_priv->display.modeset_commit_cdclk =
15122 valleyview_modeset_commit_cdclk;
15123 dev_priv->display.modeset_calc_cdclk =
15124 valleyview_modeset_calc_cdclk;
15125 } else if (IS_BROXTON(dev_priv)) {
15126 dev_priv->display.modeset_commit_cdclk =
15127 broxton_modeset_commit_cdclk;
15128 dev_priv->display.modeset_calc_cdclk =
15129 broxton_modeset_calc_cdclk;
15130 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15131 dev_priv->display.modeset_commit_cdclk =
15132 skl_modeset_commit_cdclk;
15133 dev_priv->display.modeset_calc_cdclk =
15134 skl_modeset_calc_cdclk;
15135 }
15136
15137 switch (INTEL_INFO(dev_priv)->gen) {
15138 case 2:
15139 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15140 break;
15141
15142 case 3:
15143 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15144 break;
15145
15146 case 4:
15147 case 5:
15148 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15149 break;
15150
15151 case 6:
15152 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15153 break;
15154 case 7:
15155 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15156 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15157 break;
15158 case 9:
15159 /* Drop through - unsupported since execlist only. */
15160 default:
15161 /* Default just returns -ENODEV to indicate unsupported */
15162 dev_priv->display.queue_flip = intel_default_queue_flip;
15163 }
15164 }
15165
15166 /*
15167 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15168 * resume, or other times. This quirk makes sure that's the case for
15169 * affected systems.
15170 */
15171 static void quirk_pipea_force(struct drm_device *dev)
15172 {
15173 struct drm_i915_private *dev_priv = dev->dev_private;
15174
15175 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15176 DRM_INFO("applying pipe a force quirk\n");
15177 }
15178
15179 static void quirk_pipeb_force(struct drm_device *dev)
15180 {
15181 struct drm_i915_private *dev_priv = dev->dev_private;
15182
15183 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15184 DRM_INFO("applying pipe b force quirk\n");
15185 }
15186
15187 /*
15188 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15189 */
15190 static void quirk_ssc_force_disable(struct drm_device *dev)
15191 {
15192 struct drm_i915_private *dev_priv = dev->dev_private;
15193 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15194 DRM_INFO("applying lvds SSC disable quirk\n");
15195 }
15196
15197 /*
15198 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15199 * brightness value
15200 */
15201 static void quirk_invert_brightness(struct drm_device *dev)
15202 {
15203 struct drm_i915_private *dev_priv = dev->dev_private;
15204 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15205 DRM_INFO("applying inverted panel brightness quirk\n");
15206 }
15207
15208 /* Some VBT's incorrectly indicate no backlight is present */
15209 static void quirk_backlight_present(struct drm_device *dev)
15210 {
15211 struct drm_i915_private *dev_priv = dev->dev_private;
15212 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15213 DRM_INFO("applying backlight present quirk\n");
15214 }
15215
15216 struct intel_quirk {
15217 int device;
15218 int subsystem_vendor;
15219 int subsystem_device;
15220 void (*hook)(struct drm_device *dev);
15221 };
15222
15223 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15224 struct intel_dmi_quirk {
15225 void (*hook)(struct drm_device *dev);
15226 const struct dmi_system_id (*dmi_id_list)[];
15227 };
15228
15229 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15230 {
15231 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15232 return 1;
15233 }
15234
15235 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15236 {
15237 .dmi_id_list = &(const struct dmi_system_id[]) {
15238 {
15239 .callback = intel_dmi_reverse_brightness,
15240 .ident = "NCR Corporation",
15241 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15242 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15243 },
15244 },
15245 { } /* terminating entry */
15246 },
15247 .hook = quirk_invert_brightness,
15248 },
15249 };
15250
15251 static struct intel_quirk intel_quirks[] = {
15252 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15253 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15254
15255 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15256 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15257
15258 /* 830 needs to leave pipe A & dpll A up */
15259 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15260
15261 /* 830 needs to leave pipe B & dpll B up */
15262 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15263
15264 /* Lenovo U160 cannot use SSC on LVDS */
15265 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15266
15267 /* Sony Vaio Y cannot use SSC on LVDS */
15268 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15269
15270 /* Acer Aspire 5734Z must invert backlight brightness */
15271 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15272
15273 /* Acer/eMachines G725 */
15274 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15275
15276 /* Acer/eMachines e725 */
15277 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15278
15279 /* Acer/Packard Bell NCL20 */
15280 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15281
15282 /* Acer Aspire 4736Z */
15283 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15284
15285 /* Acer Aspire 5336 */
15286 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15287
15288 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15289 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15290
15291 /* Acer C720 Chromebook (Core i3 4005U) */
15292 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15293
15294 /* Apple Macbook 2,1 (Core 2 T7400) */
15295 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15296
15297 /* Apple Macbook 4,1 */
15298 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15299
15300 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15301 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15302
15303 /* HP Chromebook 14 (Celeron 2955U) */
15304 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15305
15306 /* Dell Chromebook 11 */
15307 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15308
15309 /* Dell Chromebook 11 (2015 version) */
15310 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15311 };
15312
15313 static void intel_init_quirks(struct drm_device *dev)
15314 {
15315 struct pci_dev *d = dev->pdev;
15316 int i;
15317
15318 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15319 struct intel_quirk *q = &intel_quirks[i];
15320
15321 if (d->device == q->device &&
15322 (d->subsystem_vendor == q->subsystem_vendor ||
15323 q->subsystem_vendor == PCI_ANY_ID) &&
15324 (d->subsystem_device == q->subsystem_device ||
15325 q->subsystem_device == PCI_ANY_ID))
15326 q->hook(dev);
15327 }
15328 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15329 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15330 intel_dmi_quirks[i].hook(dev);
15331 }
15332 }
15333
15334 /* Disable the VGA plane that we never use */
15335 static void i915_disable_vga(struct drm_device *dev)
15336 {
15337 struct drm_i915_private *dev_priv = dev->dev_private;
15338 u8 sr1;
15339 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15340
15341 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15342 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15343 outb(SR01, VGA_SR_INDEX);
15344 sr1 = inb(VGA_SR_DATA);
15345 outb(sr1 | 1<<5, VGA_SR_DATA);
15346 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15347 udelay(300);
15348
15349 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15350 POSTING_READ(vga_reg);
15351 }
15352
15353 void intel_modeset_init_hw(struct drm_device *dev)
15354 {
15355 struct drm_i915_private *dev_priv = dev->dev_private;
15356
15357 intel_update_cdclk(dev);
15358
15359 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15360
15361 intel_init_clock_gating(dev);
15362 intel_enable_gt_powersave(dev_priv);
15363 }
15364
15365 /*
15366 * Calculate what we think the watermarks should be for the state we've read
15367 * out of the hardware and then immediately program those watermarks so that
15368 * we ensure the hardware settings match our internal state.
15369 *
15370 * We can calculate what we think WM's should be by creating a duplicate of the
15371 * current state (which was constructed during hardware readout) and running it
15372 * through the atomic check code to calculate new watermark values in the
15373 * state object.
15374 */
15375 static void sanitize_watermarks(struct drm_device *dev)
15376 {
15377 struct drm_i915_private *dev_priv = to_i915(dev);
15378 struct drm_atomic_state *state;
15379 struct drm_crtc *crtc;
15380 struct drm_crtc_state *cstate;
15381 struct drm_modeset_acquire_ctx ctx;
15382 int ret;
15383 int i;
15384
15385 /* Only supported on platforms that use atomic watermark design */
15386 if (!dev_priv->display.optimize_watermarks)
15387 return;
15388
15389 /*
15390 * We need to hold connection_mutex before calling duplicate_state so
15391 * that the connector loop is protected.
15392 */
15393 drm_modeset_acquire_init(&ctx, 0);
15394 retry:
15395 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15396 if (ret == -EDEADLK) {
15397 drm_modeset_backoff(&ctx);
15398 goto retry;
15399 } else if (WARN_ON(ret)) {
15400 goto fail;
15401 }
15402
15403 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15404 if (WARN_ON(IS_ERR(state)))
15405 goto fail;
15406
15407 /*
15408 * Hardware readout is the only time we don't want to calculate
15409 * intermediate watermarks (since we don't trust the current
15410 * watermarks).
15411 */
15412 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15413
15414 ret = intel_atomic_check(dev, state);
15415 if (ret) {
15416 /*
15417 * If we fail here, it means that the hardware appears to be
15418 * programmed in a way that shouldn't be possible, given our
15419 * understanding of watermark requirements. This might mean a
15420 * mistake in the hardware readout code or a mistake in the
15421 * watermark calculations for a given platform. Raise a WARN
15422 * so that this is noticeable.
15423 *
15424 * If this actually happens, we'll have to just leave the
15425 * BIOS-programmed watermarks untouched and hope for the best.
15426 */
15427 WARN(true, "Could not determine valid watermarks for inherited state\n");
15428 goto fail;
15429 }
15430
15431 /* Write calculated watermark values back */
15432 for_each_crtc_in_state(state, crtc, cstate, i) {
15433 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15434
15435 cs->wm.need_postvbl_update = true;
15436 dev_priv->display.optimize_watermarks(cs);
15437 }
15438
15439 drm_atomic_state_free(state);
15440 fail:
15441 drm_modeset_drop_locks(&ctx);
15442 drm_modeset_acquire_fini(&ctx);
15443 }
15444
15445 void intel_modeset_init(struct drm_device *dev)
15446 {
15447 struct drm_i915_private *dev_priv = to_i915(dev);
15448 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15449 int sprite, ret;
15450 enum pipe pipe;
15451 struct intel_crtc *crtc;
15452
15453 drm_mode_config_init(dev);
15454
15455 dev->mode_config.min_width = 0;
15456 dev->mode_config.min_height = 0;
15457
15458 dev->mode_config.preferred_depth = 24;
15459 dev->mode_config.prefer_shadow = 1;
15460
15461 dev->mode_config.allow_fb_modifiers = true;
15462
15463 dev->mode_config.funcs = &intel_mode_funcs;
15464
15465 intel_init_quirks(dev);
15466
15467 intel_init_pm(dev);
15468
15469 if (INTEL_INFO(dev)->num_pipes == 0)
15470 return;
15471
15472 /*
15473 * There may be no VBT; and if the BIOS enabled SSC we can
15474 * just keep using it to avoid unnecessary flicker. Whereas if the
15475 * BIOS isn't using it, don't assume it will work even if the VBT
15476 * indicates as much.
15477 */
15478 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15479 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15480 DREF_SSC1_ENABLE);
15481
15482 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15483 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15484 bios_lvds_use_ssc ? "en" : "dis",
15485 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15486 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15487 }
15488 }
15489
15490 if (IS_GEN2(dev)) {
15491 dev->mode_config.max_width = 2048;
15492 dev->mode_config.max_height = 2048;
15493 } else if (IS_GEN3(dev)) {
15494 dev->mode_config.max_width = 4096;
15495 dev->mode_config.max_height = 4096;
15496 } else {
15497 dev->mode_config.max_width = 8192;
15498 dev->mode_config.max_height = 8192;
15499 }
15500
15501 if (IS_845G(dev) || IS_I865G(dev)) {
15502 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15503 dev->mode_config.cursor_height = 1023;
15504 } else if (IS_GEN2(dev)) {
15505 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15506 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15507 } else {
15508 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15509 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15510 }
15511
15512 dev->mode_config.fb_base = ggtt->mappable_base;
15513
15514 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15515 INTEL_INFO(dev)->num_pipes,
15516 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15517
15518 for_each_pipe(dev_priv, pipe) {
15519 intel_crtc_init(dev, pipe);
15520 for_each_sprite(dev_priv, pipe, sprite) {
15521 ret = intel_plane_init(dev, pipe, sprite);
15522 if (ret)
15523 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15524 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15525 }
15526 }
15527
15528 intel_update_czclk(dev_priv);
15529 intel_update_cdclk(dev);
15530
15531 intel_shared_dpll_init(dev);
15532
15533 if (dev_priv->max_cdclk_freq == 0)
15534 intel_update_max_cdclk(dev);
15535
15536 /* Just disable it once at startup */
15537 i915_disable_vga(dev);
15538 intel_setup_outputs(dev);
15539
15540 drm_modeset_lock_all(dev);
15541 intel_modeset_setup_hw_state(dev);
15542 drm_modeset_unlock_all(dev);
15543
15544 for_each_intel_crtc(dev, crtc) {
15545 struct intel_initial_plane_config plane_config = {};
15546
15547 if (!crtc->active)
15548 continue;
15549
15550 /*
15551 * Note that reserving the BIOS fb up front prevents us
15552 * from stuffing other stolen allocations like the ring
15553 * on top. This prevents some ugliness at boot time, and
15554 * can even allow for smooth boot transitions if the BIOS
15555 * fb is large enough for the active pipe configuration.
15556 */
15557 dev_priv->display.get_initial_plane_config(crtc,
15558 &plane_config);
15559
15560 /*
15561 * If the fb is shared between multiple heads, we'll
15562 * just get the first one.
15563 */
15564 intel_find_initial_plane_obj(crtc, &plane_config);
15565 }
15566
15567 /*
15568 * Make sure hardware watermarks really match the state we read out.
15569 * Note that we need to do this after reconstructing the BIOS fb's
15570 * since the watermark calculation done here will use pstate->fb.
15571 */
15572 sanitize_watermarks(dev);
15573 }
15574
15575 static void intel_enable_pipe_a(struct drm_device *dev)
15576 {
15577 struct intel_connector *connector;
15578 struct drm_connector *crt = NULL;
15579 struct intel_load_detect_pipe load_detect_temp;
15580 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15581
15582 /* We can't just switch on the pipe A, we need to set things up with a
15583 * proper mode and output configuration. As a gross hack, enable pipe A
15584 * by enabling the load detect pipe once. */
15585 for_each_intel_connector(dev, connector) {
15586 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15587 crt = &connector->base;
15588 break;
15589 }
15590 }
15591
15592 if (!crt)
15593 return;
15594
15595 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15596 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15597 }
15598
15599 static bool
15600 intel_check_plane_mapping(struct intel_crtc *crtc)
15601 {
15602 struct drm_device *dev = crtc->base.dev;
15603 struct drm_i915_private *dev_priv = dev->dev_private;
15604 u32 val;
15605
15606 if (INTEL_INFO(dev)->num_pipes == 1)
15607 return true;
15608
15609 val = I915_READ(DSPCNTR(!crtc->plane));
15610
15611 if ((val & DISPLAY_PLANE_ENABLE) &&
15612 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15613 return false;
15614
15615 return true;
15616 }
15617
15618 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15619 {
15620 struct drm_device *dev = crtc->base.dev;
15621 struct intel_encoder *encoder;
15622
15623 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15624 return true;
15625
15626 return false;
15627 }
15628
15629 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15630 {
15631 struct drm_device *dev = encoder->base.dev;
15632 struct intel_connector *connector;
15633
15634 for_each_connector_on_encoder(dev, &encoder->base, connector)
15635 return true;
15636
15637 return false;
15638 }
15639
15640 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15641 {
15642 struct drm_device *dev = crtc->base.dev;
15643 struct drm_i915_private *dev_priv = dev->dev_private;
15644 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15645
15646 /* Clear any frame start delays used for debugging left by the BIOS */
15647 if (!transcoder_is_dsi(cpu_transcoder)) {
15648 i915_reg_t reg = PIPECONF(cpu_transcoder);
15649
15650 I915_WRITE(reg,
15651 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15652 }
15653
15654 /* restore vblank interrupts to correct state */
15655 drm_crtc_vblank_reset(&crtc->base);
15656 if (crtc->active) {
15657 struct intel_plane *plane;
15658
15659 drm_crtc_vblank_on(&crtc->base);
15660
15661 /* Disable everything but the primary plane */
15662 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15663 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15664 continue;
15665
15666 plane->disable_plane(&plane->base, &crtc->base);
15667 }
15668 }
15669
15670 /* We need to sanitize the plane -> pipe mapping first because this will
15671 * disable the crtc (and hence change the state) if it is wrong. Note
15672 * that gen4+ has a fixed plane -> pipe mapping. */
15673 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15674 bool plane;
15675
15676 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15677 crtc->base.base.id);
15678
15679 /* Pipe has the wrong plane attached and the plane is active.
15680 * Temporarily change the plane mapping and disable everything
15681 * ... */
15682 plane = crtc->plane;
15683 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15684 crtc->plane = !plane;
15685 intel_crtc_disable_noatomic(&crtc->base);
15686 crtc->plane = plane;
15687 }
15688
15689 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15690 crtc->pipe == PIPE_A && !crtc->active) {
15691 /* BIOS forgot to enable pipe A, this mostly happens after
15692 * resume. Force-enable the pipe to fix this, the update_dpms
15693 * call below we restore the pipe to the right state, but leave
15694 * the required bits on. */
15695 intel_enable_pipe_a(dev);
15696 }
15697
15698 /* Adjust the state of the output pipe according to whether we
15699 * have active connectors/encoders. */
15700 if (crtc->active && !intel_crtc_has_encoders(crtc))
15701 intel_crtc_disable_noatomic(&crtc->base);
15702
15703 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15704 /*
15705 * We start out with underrun reporting disabled to avoid races.
15706 * For correct bookkeeping mark this on active crtcs.
15707 *
15708 * Also on gmch platforms we dont have any hardware bits to
15709 * disable the underrun reporting. Which means we need to start
15710 * out with underrun reporting disabled also on inactive pipes,
15711 * since otherwise we'll complain about the garbage we read when
15712 * e.g. coming up after runtime pm.
15713 *
15714 * No protection against concurrent access is required - at
15715 * worst a fifo underrun happens which also sets this to false.
15716 */
15717 crtc->cpu_fifo_underrun_disabled = true;
15718 crtc->pch_fifo_underrun_disabled = true;
15719 }
15720 }
15721
15722 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15723 {
15724 struct intel_connector *connector;
15725 struct drm_device *dev = encoder->base.dev;
15726
15727 /* We need to check both for a crtc link (meaning that the
15728 * encoder is active and trying to read from a pipe) and the
15729 * pipe itself being active. */
15730 bool has_active_crtc = encoder->base.crtc &&
15731 to_intel_crtc(encoder->base.crtc)->active;
15732
15733 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15734 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15735 encoder->base.base.id,
15736 encoder->base.name);
15737
15738 /* Connector is active, but has no active pipe. This is
15739 * fallout from our resume register restoring. Disable
15740 * the encoder manually again. */
15741 if (encoder->base.crtc) {
15742 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15743 encoder->base.base.id,
15744 encoder->base.name);
15745 encoder->disable(encoder);
15746 if (encoder->post_disable)
15747 encoder->post_disable(encoder);
15748 }
15749 encoder->base.crtc = NULL;
15750
15751 /* Inconsistent output/port/pipe state happens presumably due to
15752 * a bug in one of the get_hw_state functions. Or someplace else
15753 * in our code, like the register restore mess on resume. Clamp
15754 * things to off as a safer default. */
15755 for_each_intel_connector(dev, connector) {
15756 if (connector->encoder != encoder)
15757 continue;
15758 connector->base.dpms = DRM_MODE_DPMS_OFF;
15759 connector->base.encoder = NULL;
15760 }
15761 }
15762 /* Enabled encoders without active connectors will be fixed in
15763 * the crtc fixup. */
15764 }
15765
15766 void i915_redisable_vga_power_on(struct drm_device *dev)
15767 {
15768 struct drm_i915_private *dev_priv = dev->dev_private;
15769 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15770
15771 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15772 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15773 i915_disable_vga(dev);
15774 }
15775 }
15776
15777 void i915_redisable_vga(struct drm_device *dev)
15778 {
15779 struct drm_i915_private *dev_priv = dev->dev_private;
15780
15781 /* This function can be called both from intel_modeset_setup_hw_state or
15782 * at a very early point in our resume sequence, where the power well
15783 * structures are not yet restored. Since this function is at a very
15784 * paranoid "someone might have enabled VGA while we were not looking"
15785 * level, just check if the power well is enabled instead of trying to
15786 * follow the "don't touch the power well if we don't need it" policy
15787 * the rest of the driver uses. */
15788 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15789 return;
15790
15791 i915_redisable_vga_power_on(dev);
15792
15793 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15794 }
15795
15796 static bool primary_get_hw_state(struct intel_plane *plane)
15797 {
15798 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15799
15800 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15801 }
15802
15803 /* FIXME read out full plane state for all planes */
15804 static void readout_plane_state(struct intel_crtc *crtc)
15805 {
15806 struct drm_plane *primary = crtc->base.primary;
15807 struct intel_plane_state *plane_state =
15808 to_intel_plane_state(primary->state);
15809
15810 plane_state->visible = crtc->active &&
15811 primary_get_hw_state(to_intel_plane(primary));
15812
15813 if (plane_state->visible)
15814 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15815 }
15816
15817 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15818 {
15819 struct drm_i915_private *dev_priv = dev->dev_private;
15820 enum pipe pipe;
15821 struct intel_crtc *crtc;
15822 struct intel_encoder *encoder;
15823 struct intel_connector *connector;
15824 int i;
15825
15826 dev_priv->active_crtcs = 0;
15827
15828 for_each_intel_crtc(dev, crtc) {
15829 struct intel_crtc_state *crtc_state = crtc->config;
15830 int pixclk = 0;
15831
15832 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15833 memset(crtc_state, 0, sizeof(*crtc_state));
15834 crtc_state->base.crtc = &crtc->base;
15835
15836 crtc_state->base.active = crtc_state->base.enable =
15837 dev_priv->display.get_pipe_config(crtc, crtc_state);
15838
15839 crtc->base.enabled = crtc_state->base.enable;
15840 crtc->active = crtc_state->base.active;
15841
15842 if (crtc_state->base.active) {
15843 dev_priv->active_crtcs |= 1 << crtc->pipe;
15844
15845 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15846 pixclk = ilk_pipe_pixel_rate(crtc_state);
15847 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15848 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15849 else
15850 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15851
15852 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15853 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15854 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15855 }
15856
15857 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15858
15859 readout_plane_state(crtc);
15860
15861 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15862 crtc->base.base.id,
15863 crtc->active ? "enabled" : "disabled");
15864 }
15865
15866 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15867 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15868
15869 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15870 &pll->config.hw_state);
15871 pll->config.crtc_mask = 0;
15872 for_each_intel_crtc(dev, crtc) {
15873 if (crtc->active && crtc->config->shared_dpll == pll)
15874 pll->config.crtc_mask |= 1 << crtc->pipe;
15875 }
15876 pll->active_mask = pll->config.crtc_mask;
15877
15878 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15879 pll->name, pll->config.crtc_mask, pll->on);
15880 }
15881
15882 for_each_intel_encoder(dev, encoder) {
15883 pipe = 0;
15884
15885 if (encoder->get_hw_state(encoder, &pipe)) {
15886 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15887 encoder->base.crtc = &crtc->base;
15888 encoder->get_config(encoder, crtc->config);
15889 } else {
15890 encoder->base.crtc = NULL;
15891 }
15892
15893 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15894 encoder->base.base.id,
15895 encoder->base.name,
15896 encoder->base.crtc ? "enabled" : "disabled",
15897 pipe_name(pipe));
15898 }
15899
15900 for_each_intel_connector(dev, connector) {
15901 if (connector->get_hw_state(connector)) {
15902 connector->base.dpms = DRM_MODE_DPMS_ON;
15903
15904 encoder = connector->encoder;
15905 connector->base.encoder = &encoder->base;
15906
15907 if (encoder->base.crtc &&
15908 encoder->base.crtc->state->active) {
15909 /*
15910 * This has to be done during hardware readout
15911 * because anything calling .crtc_disable may
15912 * rely on the connector_mask being accurate.
15913 */
15914 encoder->base.crtc->state->connector_mask |=
15915 1 << drm_connector_index(&connector->base);
15916 encoder->base.crtc->state->encoder_mask |=
15917 1 << drm_encoder_index(&encoder->base);
15918 }
15919
15920 } else {
15921 connector->base.dpms = DRM_MODE_DPMS_OFF;
15922 connector->base.encoder = NULL;
15923 }
15924 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15925 connector->base.base.id,
15926 connector->base.name,
15927 connector->base.encoder ? "enabled" : "disabled");
15928 }
15929
15930 for_each_intel_crtc(dev, crtc) {
15931 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15932
15933 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15934 if (crtc->base.state->active) {
15935 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15936 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15937 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15938
15939 /*
15940 * The initial mode needs to be set in order to keep
15941 * the atomic core happy. It wants a valid mode if the
15942 * crtc's enabled, so we do the above call.
15943 *
15944 * At this point some state updated by the connectors
15945 * in their ->detect() callback has not run yet, so
15946 * no recalculation can be done yet.
15947 *
15948 * Even if we could do a recalculation and modeset
15949 * right now it would cause a double modeset if
15950 * fbdev or userspace chooses a different initial mode.
15951 *
15952 * If that happens, someone indicated they wanted a
15953 * mode change, which means it's safe to do a full
15954 * recalculation.
15955 */
15956 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15957
15958 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15959 update_scanline_offset(crtc);
15960 }
15961
15962 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15963 }
15964 }
15965
15966 /* Scan out the current hw modeset state,
15967 * and sanitizes it to the current state
15968 */
15969 static void
15970 intel_modeset_setup_hw_state(struct drm_device *dev)
15971 {
15972 struct drm_i915_private *dev_priv = dev->dev_private;
15973 enum pipe pipe;
15974 struct intel_crtc *crtc;
15975 struct intel_encoder *encoder;
15976 int i;
15977
15978 intel_modeset_readout_hw_state(dev);
15979
15980 /* HW state is read out, now we need to sanitize this mess. */
15981 for_each_intel_encoder(dev, encoder) {
15982 intel_sanitize_encoder(encoder);
15983 }
15984
15985 for_each_pipe(dev_priv, pipe) {
15986 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15987 intel_sanitize_crtc(crtc);
15988 intel_dump_pipe_config(crtc, crtc->config,
15989 "[setup_hw_state]");
15990 }
15991
15992 intel_modeset_update_connector_atomic_state(dev);
15993
15994 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15995 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15996
15997 if (!pll->on || pll->active_mask)
15998 continue;
15999
16000 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16001
16002 pll->funcs.disable(dev_priv, pll);
16003 pll->on = false;
16004 }
16005
16006 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16007 vlv_wm_get_hw_state(dev);
16008 else if (IS_GEN9(dev))
16009 skl_wm_get_hw_state(dev);
16010 else if (HAS_PCH_SPLIT(dev))
16011 ilk_wm_get_hw_state(dev);
16012
16013 for_each_intel_crtc(dev, crtc) {
16014 unsigned long put_domains;
16015
16016 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16017 if (WARN_ON(put_domains))
16018 modeset_put_power_domains(dev_priv, put_domains);
16019 }
16020 intel_display_set_init_power(dev_priv, false);
16021
16022 intel_fbc_init_pipe_state(dev_priv);
16023 }
16024
16025 void intel_display_resume(struct drm_device *dev)
16026 {
16027 struct drm_i915_private *dev_priv = to_i915(dev);
16028 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16029 struct drm_modeset_acquire_ctx ctx;
16030 int ret;
16031 bool setup = false;
16032
16033 dev_priv->modeset_restore_state = NULL;
16034
16035 /*
16036 * This is a cludge because with real atomic modeset mode_config.mutex
16037 * won't be taken. Unfortunately some probed state like
16038 * audio_codec_enable is still protected by mode_config.mutex, so lock
16039 * it here for now.
16040 */
16041 mutex_lock(&dev->mode_config.mutex);
16042 drm_modeset_acquire_init(&ctx, 0);
16043
16044 retry:
16045 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16046
16047 if (ret == 0 && !setup) {
16048 setup = true;
16049
16050 intel_modeset_setup_hw_state(dev);
16051 i915_redisable_vga(dev);
16052 }
16053
16054 if (ret == 0 && state) {
16055 struct drm_crtc_state *crtc_state;
16056 struct drm_crtc *crtc;
16057 int i;
16058
16059 state->acquire_ctx = &ctx;
16060
16061 /* ignore any reset values/BIOS leftovers in the WM registers */
16062 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16063
16064 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16065 /*
16066 * Force recalculation even if we restore
16067 * current state. With fast modeset this may not result
16068 * in a modeset when the state is compatible.
16069 */
16070 crtc_state->mode_changed = true;
16071 }
16072
16073 ret = drm_atomic_commit(state);
16074 }
16075
16076 if (ret == -EDEADLK) {
16077 drm_modeset_backoff(&ctx);
16078 goto retry;
16079 }
16080
16081 drm_modeset_drop_locks(&ctx);
16082 drm_modeset_acquire_fini(&ctx);
16083 mutex_unlock(&dev->mode_config.mutex);
16084
16085 if (ret) {
16086 DRM_ERROR("Restoring old state failed with %i\n", ret);
16087 drm_atomic_state_free(state);
16088 }
16089 }
16090
16091 void intel_modeset_gem_init(struct drm_device *dev)
16092 {
16093 struct drm_i915_private *dev_priv = to_i915(dev);
16094 struct drm_crtc *c;
16095 struct drm_i915_gem_object *obj;
16096 int ret;
16097
16098 intel_init_gt_powersave(dev_priv);
16099
16100 intel_modeset_init_hw(dev);
16101
16102 intel_setup_overlay(dev_priv);
16103
16104 /*
16105 * Make sure any fbs we allocated at startup are properly
16106 * pinned & fenced. When we do the allocation it's too early
16107 * for this.
16108 */
16109 for_each_crtc(dev, c) {
16110 obj = intel_fb_obj(c->primary->fb);
16111 if (obj == NULL)
16112 continue;
16113
16114 mutex_lock(&dev->struct_mutex);
16115 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16116 c->primary->state->rotation);
16117 mutex_unlock(&dev->struct_mutex);
16118 if (ret) {
16119 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16120 to_intel_crtc(c)->pipe);
16121 drm_framebuffer_unreference(c->primary->fb);
16122 c->primary->fb = NULL;
16123 c->primary->crtc = c->primary->state->crtc = NULL;
16124 update_state_fb(c->primary);
16125 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16126 }
16127 }
16128
16129 intel_backlight_register(dev);
16130 }
16131
16132 void intel_connector_unregister(struct intel_connector *intel_connector)
16133 {
16134 struct drm_connector *connector = &intel_connector->base;
16135
16136 intel_panel_destroy_backlight(connector);
16137 drm_connector_unregister(connector);
16138 }
16139
16140 void intel_modeset_cleanup(struct drm_device *dev)
16141 {
16142 struct drm_i915_private *dev_priv = dev->dev_private;
16143 struct intel_connector *connector;
16144
16145 intel_disable_gt_powersave(dev_priv);
16146
16147 intel_backlight_unregister(dev);
16148
16149 /*
16150 * Interrupts and polling as the first thing to avoid creating havoc.
16151 * Too much stuff here (turning of connectors, ...) would
16152 * experience fancy races otherwise.
16153 */
16154 intel_irq_uninstall(dev_priv);
16155
16156 /*
16157 * Due to the hpd irq storm handling the hotplug work can re-arm the
16158 * poll handlers. Hence disable polling after hpd handling is shut down.
16159 */
16160 drm_kms_helper_poll_fini(dev);
16161
16162 intel_unregister_dsm_handler();
16163
16164 intel_fbc_global_disable(dev_priv);
16165
16166 /* flush any delayed tasks or pending work */
16167 flush_scheduled_work();
16168
16169 /* destroy the backlight and sysfs files before encoders/connectors */
16170 for_each_intel_connector(dev, connector)
16171 connector->unregister(connector);
16172
16173 drm_mode_config_cleanup(dev);
16174
16175 intel_cleanup_overlay(dev_priv);
16176
16177 intel_cleanup_gt_powersave(dev_priv);
16178
16179 intel_teardown_gmbus(dev);
16180 }
16181
16182 /*
16183 * Return which encoder is currently attached for connector.
16184 */
16185 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16186 {
16187 return &intel_attached_encoder(connector)->base;
16188 }
16189
16190 void intel_connector_attach_encoder(struct intel_connector *connector,
16191 struct intel_encoder *encoder)
16192 {
16193 connector->encoder = encoder;
16194 drm_mode_connector_attach_encoder(&connector->base,
16195 &encoder->base);
16196 }
16197
16198 /*
16199 * set vga decode state - true == enable VGA decode
16200 */
16201 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16202 {
16203 struct drm_i915_private *dev_priv = dev->dev_private;
16204 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16205 u16 gmch_ctrl;
16206
16207 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16208 DRM_ERROR("failed to read control word\n");
16209 return -EIO;
16210 }
16211
16212 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16213 return 0;
16214
16215 if (state)
16216 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16217 else
16218 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16219
16220 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16221 DRM_ERROR("failed to write control word\n");
16222 return -EIO;
16223 }
16224
16225 return 0;
16226 }
16227
16228 struct intel_display_error_state {
16229
16230 u32 power_well_driver;
16231
16232 int num_transcoders;
16233
16234 struct intel_cursor_error_state {
16235 u32 control;
16236 u32 position;
16237 u32 base;
16238 u32 size;
16239 } cursor[I915_MAX_PIPES];
16240
16241 struct intel_pipe_error_state {
16242 bool power_domain_on;
16243 u32 source;
16244 u32 stat;
16245 } pipe[I915_MAX_PIPES];
16246
16247 struct intel_plane_error_state {
16248 u32 control;
16249 u32 stride;
16250 u32 size;
16251 u32 pos;
16252 u32 addr;
16253 u32 surface;
16254 u32 tile_offset;
16255 } plane[I915_MAX_PIPES];
16256
16257 struct intel_transcoder_error_state {
16258 bool power_domain_on;
16259 enum transcoder cpu_transcoder;
16260
16261 u32 conf;
16262
16263 u32 htotal;
16264 u32 hblank;
16265 u32 hsync;
16266 u32 vtotal;
16267 u32 vblank;
16268 u32 vsync;
16269 } transcoder[4];
16270 };
16271
16272 struct intel_display_error_state *
16273 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16274 {
16275 struct intel_display_error_state *error;
16276 int transcoders[] = {
16277 TRANSCODER_A,
16278 TRANSCODER_B,
16279 TRANSCODER_C,
16280 TRANSCODER_EDP,
16281 };
16282 int i;
16283
16284 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16285 return NULL;
16286
16287 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16288 if (error == NULL)
16289 return NULL;
16290
16291 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16292 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16293
16294 for_each_pipe(dev_priv, i) {
16295 error->pipe[i].power_domain_on =
16296 __intel_display_power_is_enabled(dev_priv,
16297 POWER_DOMAIN_PIPE(i));
16298 if (!error->pipe[i].power_domain_on)
16299 continue;
16300
16301 error->cursor[i].control = I915_READ(CURCNTR(i));
16302 error->cursor[i].position = I915_READ(CURPOS(i));
16303 error->cursor[i].base = I915_READ(CURBASE(i));
16304
16305 error->plane[i].control = I915_READ(DSPCNTR(i));
16306 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16307 if (INTEL_GEN(dev_priv) <= 3) {
16308 error->plane[i].size = I915_READ(DSPSIZE(i));
16309 error->plane[i].pos = I915_READ(DSPPOS(i));
16310 }
16311 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16312 error->plane[i].addr = I915_READ(DSPADDR(i));
16313 if (INTEL_GEN(dev_priv) >= 4) {
16314 error->plane[i].surface = I915_READ(DSPSURF(i));
16315 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16316 }
16317
16318 error->pipe[i].source = I915_READ(PIPESRC(i));
16319
16320 if (HAS_GMCH_DISPLAY(dev_priv))
16321 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16322 }
16323
16324 /* Note: this does not include DSI transcoders. */
16325 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16326 if (HAS_DDI(dev_priv))
16327 error->num_transcoders++; /* Account for eDP. */
16328
16329 for (i = 0; i < error->num_transcoders; i++) {
16330 enum transcoder cpu_transcoder = transcoders[i];
16331
16332 error->transcoder[i].power_domain_on =
16333 __intel_display_power_is_enabled(dev_priv,
16334 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16335 if (!error->transcoder[i].power_domain_on)
16336 continue;
16337
16338 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16339
16340 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16341 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16342 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16343 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16344 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16345 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16346 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16347 }
16348
16349 return error;
16350 }
16351
16352 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16353
16354 void
16355 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16356 struct drm_device *dev,
16357 struct intel_display_error_state *error)
16358 {
16359 struct drm_i915_private *dev_priv = dev->dev_private;
16360 int i;
16361
16362 if (!error)
16363 return;
16364
16365 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16366 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16367 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16368 error->power_well_driver);
16369 for_each_pipe(dev_priv, i) {
16370 err_printf(m, "Pipe [%d]:\n", i);
16371 err_printf(m, " Power: %s\n",
16372 onoff(error->pipe[i].power_domain_on));
16373 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16374 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16375
16376 err_printf(m, "Plane [%d]:\n", i);
16377 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16378 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16379 if (INTEL_INFO(dev)->gen <= 3) {
16380 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16381 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16382 }
16383 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16384 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16385 if (INTEL_INFO(dev)->gen >= 4) {
16386 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16387 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16388 }
16389
16390 err_printf(m, "Cursor [%d]:\n", i);
16391 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16392 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16393 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16394 }
16395
16396 for (i = 0; i < error->num_transcoders; i++) {
16397 err_printf(m, "CPU transcoder: %s\n",
16398 transcoder_name(error->transcoder[i].cpu_transcoder));
16399 err_printf(m, " Power: %s\n",
16400 onoff(error->transcoder[i].power_domain_on));
16401 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16402 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16403 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16404 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16405 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16406 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16407 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16408 }
16409 }
Linux kernel - Deliverables
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