2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
47 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
48 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t
;
74 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
76 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
77 int, int, intel_clock_t
*, intel_clock_t
*);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
85 int target
, int refclk
, intel_clock_t
*match_clock
,
86 intel_clock_t
*best_clock
);
88 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
89 int target
, int refclk
, intel_clock_t
*match_clock
,
90 intel_clock_t
*best_clock
);
93 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
94 int target
, int refclk
, intel_clock_t
*match_clock
,
95 intel_clock_t
*best_clock
);
97 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
98 int target
, int refclk
, intel_clock_t
*match_clock
,
99 intel_clock_t
*best_clock
);
102 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
103 int target
, int refclk
, intel_clock_t
*match_clock
,
104 intel_clock_t
*best_clock
);
106 static inline u32
/* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device
*dev
)
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
111 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
116 static const intel_limit_t intel_limits_i8xx_dvo
= {
117 .dot
= { .min
= 25000, .max
= 350000 },
118 .vco
= { .min
= 930000, .max
= 1400000 },
119 .n
= { .min
= 3, .max
= 16 },
120 .m
= { .min
= 96, .max
= 140 },
121 .m1
= { .min
= 18, .max
= 26 },
122 .m2
= { .min
= 6, .max
= 16 },
123 .p
= { .min
= 4, .max
= 128 },
124 .p1
= { .min
= 2, .max
= 33 },
125 .p2
= { .dot_limit
= 165000,
126 .p2_slow
= 4, .p2_fast
= 2 },
127 .find_pll
= intel_find_best_PLL
,
130 static const intel_limit_t intel_limits_i8xx_lvds
= {
131 .dot
= { .min
= 25000, .max
= 350000 },
132 .vco
= { .min
= 930000, .max
= 1400000 },
133 .n
= { .min
= 3, .max
= 16 },
134 .m
= { .min
= 96, .max
= 140 },
135 .m1
= { .min
= 18, .max
= 26 },
136 .m2
= { .min
= 6, .max
= 16 },
137 .p
= { .min
= 4, .max
= 128 },
138 .p1
= { .min
= 1, .max
= 6 },
139 .p2
= { .dot_limit
= 165000,
140 .p2_slow
= 14, .p2_fast
= 7 },
141 .find_pll
= intel_find_best_PLL
,
144 static const intel_limit_t intel_limits_i9xx_sdvo
= {
145 .dot
= { .min
= 20000, .max
= 400000 },
146 .vco
= { .min
= 1400000, .max
= 2800000 },
147 .n
= { .min
= 1, .max
= 6 },
148 .m
= { .min
= 70, .max
= 120 },
149 .m1
= { .min
= 10, .max
= 22 },
150 .m2
= { .min
= 5, .max
= 9 },
151 .p
= { .min
= 5, .max
= 80 },
152 .p1
= { .min
= 1, .max
= 8 },
153 .p2
= { .dot_limit
= 200000,
154 .p2_slow
= 10, .p2_fast
= 5 },
155 .find_pll
= intel_find_best_PLL
,
158 static const intel_limit_t intel_limits_i9xx_lvds
= {
159 .dot
= { .min
= 20000, .max
= 400000 },
160 .vco
= { .min
= 1400000, .max
= 2800000 },
161 .n
= { .min
= 1, .max
= 6 },
162 .m
= { .min
= 70, .max
= 120 },
163 .m1
= { .min
= 10, .max
= 22 },
164 .m2
= { .min
= 5, .max
= 9 },
165 .p
= { .min
= 7, .max
= 98 },
166 .p1
= { .min
= 1, .max
= 8 },
167 .p2
= { .dot_limit
= 112000,
168 .p2_slow
= 14, .p2_fast
= 7 },
169 .find_pll
= intel_find_best_PLL
,
173 static const intel_limit_t intel_limits_g4x_sdvo
= {
174 .dot
= { .min
= 25000, .max
= 270000 },
175 .vco
= { .min
= 1750000, .max
= 3500000},
176 .n
= { .min
= 1, .max
= 4 },
177 .m
= { .min
= 104, .max
= 138 },
178 .m1
= { .min
= 17, .max
= 23 },
179 .m2
= { .min
= 5, .max
= 11 },
180 .p
= { .min
= 10, .max
= 30 },
181 .p1
= { .min
= 1, .max
= 3},
182 .p2
= { .dot_limit
= 270000,
186 .find_pll
= intel_g4x_find_best_PLL
,
189 static const intel_limit_t intel_limits_g4x_hdmi
= {
190 .dot
= { .min
= 22000, .max
= 400000 },
191 .vco
= { .min
= 1750000, .max
= 3500000},
192 .n
= { .min
= 1, .max
= 4 },
193 .m
= { .min
= 104, .max
= 138 },
194 .m1
= { .min
= 16, .max
= 23 },
195 .m2
= { .min
= 5, .max
= 11 },
196 .p
= { .min
= 5, .max
= 80 },
197 .p1
= { .min
= 1, .max
= 8},
198 .p2
= { .dot_limit
= 165000,
199 .p2_slow
= 10, .p2_fast
= 5 },
200 .find_pll
= intel_g4x_find_best_PLL
,
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
204 .dot
= { .min
= 20000, .max
= 115000 },
205 .vco
= { .min
= 1750000, .max
= 3500000 },
206 .n
= { .min
= 1, .max
= 3 },
207 .m
= { .min
= 104, .max
= 138 },
208 .m1
= { .min
= 17, .max
= 23 },
209 .m2
= { .min
= 5, .max
= 11 },
210 .p
= { .min
= 28, .max
= 112 },
211 .p1
= { .min
= 2, .max
= 8 },
212 .p2
= { .dot_limit
= 0,
213 .p2_slow
= 14, .p2_fast
= 14
215 .find_pll
= intel_g4x_find_best_PLL
,
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
219 .dot
= { .min
= 80000, .max
= 224000 },
220 .vco
= { .min
= 1750000, .max
= 3500000 },
221 .n
= { .min
= 1, .max
= 3 },
222 .m
= { .min
= 104, .max
= 138 },
223 .m1
= { .min
= 17, .max
= 23 },
224 .m2
= { .min
= 5, .max
= 11 },
225 .p
= { .min
= 14, .max
= 42 },
226 .p1
= { .min
= 2, .max
= 6 },
227 .p2
= { .dot_limit
= 0,
228 .p2_slow
= 7, .p2_fast
= 7
230 .find_pll
= intel_g4x_find_best_PLL
,
233 static const intel_limit_t intel_limits_g4x_display_port
= {
234 .dot
= { .min
= 161670, .max
= 227000 },
235 .vco
= { .min
= 1750000, .max
= 3500000},
236 .n
= { .min
= 1, .max
= 2 },
237 .m
= { .min
= 97, .max
= 108 },
238 .m1
= { .min
= 0x10, .max
= 0x12 },
239 .m2
= { .min
= 0x05, .max
= 0x06 },
240 .p
= { .min
= 10, .max
= 20 },
241 .p1
= { .min
= 1, .max
= 2},
242 .p2
= { .dot_limit
= 0,
243 .p2_slow
= 10, .p2_fast
= 10 },
244 .find_pll
= intel_find_pll_g4x_dp
,
247 static const intel_limit_t intel_limits_pineview_sdvo
= {
248 .dot
= { .min
= 20000, .max
= 400000},
249 .vco
= { .min
= 1700000, .max
= 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n
= { .min
= 3, .max
= 6 },
252 .m
= { .min
= 2, .max
= 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1
= { .min
= 0, .max
= 0 },
255 .m2
= { .min
= 0, .max
= 254 },
256 .p
= { .min
= 5, .max
= 80 },
257 .p1
= { .min
= 1, .max
= 8 },
258 .p2
= { .dot_limit
= 200000,
259 .p2_slow
= 10, .p2_fast
= 5 },
260 .find_pll
= intel_find_best_PLL
,
263 static const intel_limit_t intel_limits_pineview_lvds
= {
264 .dot
= { .min
= 20000, .max
= 400000 },
265 .vco
= { .min
= 1700000, .max
= 3500000 },
266 .n
= { .min
= 3, .max
= 6 },
267 .m
= { .min
= 2, .max
= 256 },
268 .m1
= { .min
= 0, .max
= 0 },
269 .m2
= { .min
= 0, .max
= 254 },
270 .p
= { .min
= 7, .max
= 112 },
271 .p1
= { .min
= 1, .max
= 8 },
272 .p2
= { .dot_limit
= 112000,
273 .p2_slow
= 14, .p2_fast
= 14 },
274 .find_pll
= intel_find_best_PLL
,
277 /* Ironlake / Sandybridge
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
282 static const intel_limit_t intel_limits_ironlake_dac
= {
283 .dot
= { .min
= 25000, .max
= 350000 },
284 .vco
= { .min
= 1760000, .max
= 3510000 },
285 .n
= { .min
= 1, .max
= 5 },
286 .m
= { .min
= 79, .max
= 127 },
287 .m1
= { .min
= 12, .max
= 22 },
288 .m2
= { .min
= 5, .max
= 9 },
289 .p
= { .min
= 5, .max
= 80 },
290 .p1
= { .min
= 1, .max
= 8 },
291 .p2
= { .dot_limit
= 225000,
292 .p2_slow
= 10, .p2_fast
= 5 },
293 .find_pll
= intel_g4x_find_best_PLL
,
296 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
297 .dot
= { .min
= 25000, .max
= 350000 },
298 .vco
= { .min
= 1760000, .max
= 3510000 },
299 .n
= { .min
= 1, .max
= 3 },
300 .m
= { .min
= 79, .max
= 118 },
301 .m1
= { .min
= 12, .max
= 22 },
302 .m2
= { .min
= 5, .max
= 9 },
303 .p
= { .min
= 28, .max
= 112 },
304 .p1
= { .min
= 2, .max
= 8 },
305 .p2
= { .dot_limit
= 225000,
306 .p2_slow
= 14, .p2_fast
= 14 },
307 .find_pll
= intel_g4x_find_best_PLL
,
310 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
311 .dot
= { .min
= 25000, .max
= 350000 },
312 .vco
= { .min
= 1760000, .max
= 3510000 },
313 .n
= { .min
= 1, .max
= 3 },
314 .m
= { .min
= 79, .max
= 127 },
315 .m1
= { .min
= 12, .max
= 22 },
316 .m2
= { .min
= 5, .max
= 9 },
317 .p
= { .min
= 14, .max
= 56 },
318 .p1
= { .min
= 2, .max
= 8 },
319 .p2
= { .dot_limit
= 225000,
320 .p2_slow
= 7, .p2_fast
= 7 },
321 .find_pll
= intel_g4x_find_best_PLL
,
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
326 .dot
= { .min
= 25000, .max
= 350000 },
327 .vco
= { .min
= 1760000, .max
= 3510000 },
328 .n
= { .min
= 1, .max
= 2 },
329 .m
= { .min
= 79, .max
= 126 },
330 .m1
= { .min
= 12, .max
= 22 },
331 .m2
= { .min
= 5, .max
= 9 },
332 .p
= { .min
= 28, .max
= 112 },
333 .p1
= { .min
= 2, .max
= 8 },
334 .p2
= { .dot_limit
= 225000,
335 .p2_slow
= 14, .p2_fast
= 14 },
336 .find_pll
= intel_g4x_find_best_PLL
,
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
340 .dot
= { .min
= 25000, .max
= 350000 },
341 .vco
= { .min
= 1760000, .max
= 3510000 },
342 .n
= { .min
= 1, .max
= 3 },
343 .m
= { .min
= 79, .max
= 126 },
344 .m1
= { .min
= 12, .max
= 22 },
345 .m2
= { .min
= 5, .max
= 9 },
346 .p
= { .min
= 14, .max
= 42 },
347 .p1
= { .min
= 2, .max
= 6 },
348 .p2
= { .dot_limit
= 225000,
349 .p2_slow
= 7, .p2_fast
= 7 },
350 .find_pll
= intel_g4x_find_best_PLL
,
353 static const intel_limit_t intel_limits_ironlake_display_port
= {
354 .dot
= { .min
= 25000, .max
= 350000 },
355 .vco
= { .min
= 1760000, .max
= 3510000},
356 .n
= { .min
= 1, .max
= 2 },
357 .m
= { .min
= 81, .max
= 90 },
358 .m1
= { .min
= 12, .max
= 22 },
359 .m2
= { .min
= 5, .max
= 9 },
360 .p
= { .min
= 10, .max
= 20 },
361 .p1
= { .min
= 1, .max
= 2},
362 .p2
= { .dot_limit
= 0,
363 .p2_slow
= 10, .p2_fast
= 10 },
364 .find_pll
= intel_find_pll_ironlake_dp
,
367 static const intel_limit_t intel_limits_vlv_dac
= {
368 .dot
= { .min
= 25000, .max
= 270000 },
369 .vco
= { .min
= 4000000, .max
= 6000000 },
370 .n
= { .min
= 1, .max
= 7 },
371 .m
= { .min
= 22, .max
= 450 }, /* guess */
372 .m1
= { .min
= 2, .max
= 3 },
373 .m2
= { .min
= 11, .max
= 156 },
374 .p
= { .min
= 10, .max
= 30 },
375 .p1
= { .min
= 2, .max
= 3 },
376 .p2
= { .dot_limit
= 270000,
377 .p2_slow
= 2, .p2_fast
= 20 },
378 .find_pll
= intel_vlv_find_best_pll
,
381 static const intel_limit_t intel_limits_vlv_hdmi
= {
382 .dot
= { .min
= 20000, .max
= 165000 },
383 .vco
= { .min
= 5994000, .max
= 4000000 },
384 .n
= { .min
= 1, .max
= 7 },
385 .m
= { .min
= 60, .max
= 300 }, /* guess */
386 .m1
= { .min
= 2, .max
= 3 },
387 .m2
= { .min
= 11, .max
= 156 },
388 .p
= { .min
= 10, .max
= 30 },
389 .p1
= { .min
= 2, .max
= 3 },
390 .p2
= { .dot_limit
= 270000,
391 .p2_slow
= 2, .p2_fast
= 20 },
392 .find_pll
= intel_vlv_find_best_pll
,
395 static const intel_limit_t intel_limits_vlv_dp
= {
396 .dot
= { .min
= 25000, .max
= 270000 },
397 .vco
= { .min
= 4000000, .max
= 6000000 },
398 .n
= { .min
= 1, .max
= 7 },
399 .m
= { .min
= 22, .max
= 450 },
400 .m1
= { .min
= 2, .max
= 3 },
401 .m2
= { .min
= 11, .max
= 156 },
402 .p
= { .min
= 10, .max
= 30 },
403 .p1
= { .min
= 2, .max
= 3 },
404 .p2
= { .dot_limit
= 270000,
405 .p2_slow
= 2, .p2_fast
= 20 },
406 .find_pll
= intel_vlv_find_best_pll
,
409 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
414 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
420 I915_WRITE(DPIO_REG
, reg
);
421 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
427 val
= I915_READ(DPIO_DATA
);
430 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
434 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
439 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
445 I915_WRITE(DPIO_DATA
, val
);
446 I915_WRITE(DPIO_REG
, reg
);
447 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
453 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
456 static void vlv_init_dpio(struct drm_device
*dev
)
458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL
, 0);
462 POSTING_READ(DPIO_CTL
);
463 I915_WRITE(DPIO_CTL
, 1);
464 POSTING_READ(DPIO_CTL
);
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id
*id
)
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id
->ident
);
473 static const struct dmi_system_id intel_dual_link_lvds
[] = {
475 .callback
= intel_dual_link_lvds_callback
,
476 .ident
= "Apple MacBook Pro (Core i5/i7 Series)",
478 DMI_MATCH(DMI_SYS_VENDOR
, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME
, "MacBookPro8,2"),
482 { } /* terminating entry */
485 static bool is_dual_link_lvds(struct drm_i915_private
*dev_priv
,
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode
> 0)
492 return i915_lvds_channel_mode
== 2;
494 if (dmi_check_system(intel_dual_link_lvds
))
497 if (dev_priv
->lvds_val
)
498 val
= dev_priv
->lvds_val
;
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
505 val
= I915_READ(reg
);
506 if (!(val
& ~(LVDS_PIPE_MASK
| LVDS_DETECTED
)))
507 val
= dev_priv
->bios_lvds_val
;
508 dev_priv
->lvds_val
= val
;
510 return (val
& LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
;
513 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
516 struct drm_device
*dev
= crtc
->dev
;
517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
518 const intel_limit_t
*limit
;
520 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
521 if (is_dual_link_lvds(dev_priv
, PCH_LVDS
)) {
522 /* LVDS dual channel */
523 if (refclk
== 100000)
524 limit
= &intel_limits_ironlake_dual_lvds_100m
;
526 limit
= &intel_limits_ironlake_dual_lvds
;
528 if (refclk
== 100000)
529 limit
= &intel_limits_ironlake_single_lvds_100m
;
531 limit
= &intel_limits_ironlake_single_lvds
;
533 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
535 limit
= &intel_limits_ironlake_display_port
;
537 limit
= &intel_limits_ironlake_dac
;
542 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
544 struct drm_device
*dev
= crtc
->dev
;
545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
546 const intel_limit_t
*limit
;
548 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
549 if (is_dual_link_lvds(dev_priv
, LVDS
))
550 /* LVDS with dual channel */
551 limit
= &intel_limits_g4x_dual_channel_lvds
;
553 /* LVDS with dual channel */
554 limit
= &intel_limits_g4x_single_channel_lvds
;
555 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
556 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
557 limit
= &intel_limits_g4x_hdmi
;
558 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
559 limit
= &intel_limits_g4x_sdvo
;
560 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
561 limit
= &intel_limits_g4x_display_port
;
562 } else /* The option is for other outputs */
563 limit
= &intel_limits_i9xx_sdvo
;
568 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
570 struct drm_device
*dev
= crtc
->dev
;
571 const intel_limit_t
*limit
;
573 if (HAS_PCH_SPLIT(dev
))
574 limit
= intel_ironlake_limit(crtc
, refclk
);
575 else if (IS_G4X(dev
)) {
576 limit
= intel_g4x_limit(crtc
);
577 } else if (IS_PINEVIEW(dev
)) {
578 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
579 limit
= &intel_limits_pineview_lvds
;
581 limit
= &intel_limits_pineview_sdvo
;
582 } else if (IS_VALLEYVIEW(dev
)) {
583 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
584 limit
= &intel_limits_vlv_dac
;
585 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
586 limit
= &intel_limits_vlv_hdmi
;
588 limit
= &intel_limits_vlv_dp
;
589 } else if (!IS_GEN2(dev
)) {
590 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
591 limit
= &intel_limits_i9xx_lvds
;
593 limit
= &intel_limits_i9xx_sdvo
;
595 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
596 limit
= &intel_limits_i8xx_lvds
;
598 limit
= &intel_limits_i8xx_dvo
;
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
606 clock
->m
= clock
->m2
+ 2;
607 clock
->p
= clock
->p1
* clock
->p2
;
608 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
609 clock
->dot
= clock
->vco
/ clock
->p
;
612 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
614 if (IS_PINEVIEW(dev
)) {
615 pineview_clock(refclk
, clock
);
618 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
619 clock
->p
= clock
->p1
* clock
->p2
;
620 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
621 clock
->dot
= clock
->vco
/ clock
->p
;
625 * Returns whether any output on the specified pipe is of the specified type
627 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
629 struct drm_device
*dev
= crtc
->dev
;
630 struct intel_encoder
*encoder
;
632 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
633 if (encoder
->type
== type
)
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
645 static bool intel_PLL_is_valid(struct drm_device
*dev
,
646 const intel_limit_t
*limit
,
647 const intel_clock_t
*clock
)
649 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
652 INTELPllInvalid("p out of range\n");
653 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
660 INTELPllInvalid("m out of range\n");
661 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
662 INTELPllInvalid("n out of range\n");
663 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
668 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
669 INTELPllInvalid("dot out of range\n");
675 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
676 int target
, int refclk
, intel_clock_t
*match_clock
,
677 intel_clock_t
*best_clock
)
680 struct drm_device
*dev
= crtc
->dev
;
681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
685 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
686 (I915_READ(LVDS
)) != 0) {
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
693 if (is_dual_link_lvds(dev_priv
, LVDS
))
694 clock
.p2
= limit
->p2
.p2_fast
;
696 clock
.p2
= limit
->p2
.p2_slow
;
698 if (target
< limit
->p2
.dot_limit
)
699 clock
.p2
= limit
->p2
.p2_slow
;
701 clock
.p2
= limit
->p2
.p2_fast
;
704 memset(best_clock
, 0, sizeof(*best_clock
));
706 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
708 for (clock
.m2
= limit
->m2
.min
;
709 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
710 /* m1 is always 0 in Pineview */
711 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
713 for (clock
.n
= limit
->n
.min
;
714 clock
.n
<= limit
->n
.max
; clock
.n
++) {
715 for (clock
.p1
= limit
->p1
.min
;
716 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
719 intel_clock(dev
, refclk
, &clock
);
720 if (!intel_PLL_is_valid(dev
, limit
,
724 clock
.p
!= match_clock
->p
)
727 this_err
= abs(clock
.dot
- target
);
728 if (this_err
< err
) {
737 return (err
!= target
);
741 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
742 int target
, int refclk
, intel_clock_t
*match_clock
,
743 intel_clock_t
*best_clock
)
745 struct drm_device
*dev
= crtc
->dev
;
746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
750 /* approximately equals target * 0.00585 */
751 int err_most
= (target
>> 8) + (target
>> 9);
754 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
757 if (HAS_PCH_SPLIT(dev
))
761 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
763 clock
.p2
= limit
->p2
.p2_fast
;
765 clock
.p2
= limit
->p2
.p2_slow
;
767 if (target
< limit
->p2
.dot_limit
)
768 clock
.p2
= limit
->p2
.p2_slow
;
770 clock
.p2
= limit
->p2
.p2_fast
;
773 memset(best_clock
, 0, sizeof(*best_clock
));
774 max_n
= limit
->n
.max
;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock
.m1
= limit
->m1
.max
;
779 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
780 for (clock
.m2
= limit
->m2
.max
;
781 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
782 for (clock
.p1
= limit
->p1
.max
;
783 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
786 intel_clock(dev
, refclk
, &clock
);
787 if (!intel_PLL_is_valid(dev
, limit
,
791 clock
.p
!= match_clock
->p
)
794 this_err
= abs(clock
.dot
- target
);
795 if (this_err
< err_most
) {
809 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
810 int target
, int refclk
, intel_clock_t
*match_clock
,
811 intel_clock_t
*best_clock
)
813 struct drm_device
*dev
= crtc
->dev
;
816 if (target
< 200000) {
829 intel_clock(dev
, refclk
, &clock
);
830 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
836 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
837 int target
, int refclk
, intel_clock_t
*match_clock
,
838 intel_clock_t
*best_clock
)
841 if (target
< 200000) {
854 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
855 clock
.p
= (clock
.p1
* clock
.p2
);
856 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
858 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
862 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
863 int target
, int refclk
, intel_clock_t
*match_clock
,
864 intel_clock_t
*best_clock
)
866 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
868 u32 updrate
, minupdate
, fracbits
, p
;
869 unsigned long bestppm
, ppm
, absppm
;
873 dotclk
= target
* 1000;
876 fastclk
= dotclk
/ (2*100);
880 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
881 bestm1
= bestm2
= bestp1
= bestp2
= 0;
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
885 updrate
= refclk
/ n
;
886 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
887 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
893 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
894 refclk
) / (2*refclk
));
897 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
898 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
899 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
900 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
904 if (absppm
< bestppm
- 10) {
921 best_clock
->n
= bestn
;
922 best_clock
->m1
= bestm1
;
923 best_clock
->m2
= bestm2
;
924 best_clock
->p1
= bestp1
;
925 best_clock
->p2
= bestp2
;
930 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
933 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
935 frame
= I915_READ(frame_reg
);
937 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
942 * intel_wait_for_vblank - wait for vblank on a given pipe
944 * @pipe: pipe to wait for
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
949 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 int pipestat_reg
= PIPESTAT(pipe
);
954 if (INTEL_INFO(dev
)->gen
>= 5) {
955 ironlake_wait_for_vblank(dev
, pipe
);
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
972 I915_WRITE(pipestat_reg
,
973 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg
) &
977 PIPE_VBLANK_INTERRUPT_STATUS
,
979 DRM_DEBUG_KMS("vblank wait timed out\n");
983 * intel_wait_for_pipe_off - wait for pipe to turn off
985 * @pipe: pipe to wait for
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
992 * wait for the pipe register state bit to turn off
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
999 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
1001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1003 if (INTEL_INFO(dev
)->gen
>= 4) {
1004 int reg
= PIPECONF(pipe
);
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1009 WARN(1, "pipe_off wait timed out\n");
1011 u32 last_line
, line_mask
;
1012 int reg
= PIPEDSL(pipe
);
1013 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1016 line_mask
= DSL_LINEMASK_GEN2
;
1018 line_mask
= DSL_LINEMASK_GEN3
;
1020 /* Wait for the display line to settle */
1022 last_line
= I915_READ(reg
) & line_mask
;
1024 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
1025 time_after(timeout
, jiffies
));
1026 if (time_after(jiffies
, timeout
))
1027 WARN(1, "pipe_off wait timed out\n");
1031 static const char *state_string(bool enabled
)
1033 return enabled
? "on" : "off";
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private
*dev_priv
,
1038 enum pipe pipe
, bool state
)
1045 val
= I915_READ(reg
);
1046 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1047 WARN(cur_state
!= state
,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state
), state_string(cur_state
));
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1056 struct intel_pch_pll
*pll
,
1057 struct intel_crtc
*crtc
,
1063 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1069 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1072 val
= I915_READ(pll
->pll_reg
);
1073 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1074 WARN(cur_state
!= state
,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1082 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1083 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1084 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state
, crtc
->pipe
, pch_dpll
)) {
1087 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1088 WARN(cur_state
!= state
,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll
->pll_reg
== _PCH_DPLL_B
,
1091 state_string(state
),
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1100 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1101 enum pipe pipe
, bool state
)
1107 if (IS_HASWELL(dev_priv
->dev
)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg
= DDI_FUNC_CTL(pipe
);
1110 val
= I915_READ(reg
);
1111 cur_state
= !!(val
& PIPE_DDI_FUNC_ENABLE
);
1113 reg
= FDI_TX_CTL(pipe
);
1114 val
= I915_READ(reg
);
1115 cur_state
= !!(val
& FDI_TX_ENABLE
);
1117 WARN(cur_state
!= state
,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state
), state_string(cur_state
));
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1124 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1125 enum pipe pipe
, bool state
)
1131 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1135 reg
= FDI_RX_CTL(pipe
);
1136 val
= I915_READ(reg
);
1137 cur_state
= !!(val
& FDI_RX_ENABLE
);
1139 WARN(cur_state
!= state
,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state
), state_string(cur_state
));
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv
->info
->gen
== 5)
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv
->dev
))
1160 reg
= FDI_TX_CTL(pipe
);
1161 val
= I915_READ(reg
);
1162 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1171 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1175 reg
= FDI_RX_CTL(pipe
);
1176 val
= I915_READ(reg
);
1177 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1180 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1183 int pp_reg
, lvds_reg
;
1185 enum pipe panel_pipe
= PIPE_A
;
1188 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1189 pp_reg
= PCH_PP_CONTROL
;
1190 lvds_reg
= PCH_LVDS
;
1192 pp_reg
= PP_CONTROL
;
1196 val
= I915_READ(pp_reg
);
1197 if (!(val
& PANEL_POWER_ON
) ||
1198 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1201 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1202 panel_pipe
= PIPE_B
;
1204 WARN(panel_pipe
== pipe
&& locked
,
1205 "panel assertion failure, pipe %c regs locked\n",
1209 void assert_pipe(struct drm_i915_private
*dev_priv
,
1210 enum pipe pipe
, bool state
)
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1220 reg
= PIPECONF(pipe
);
1221 val
= I915_READ(reg
);
1222 cur_state
= !!(val
& PIPECONF_ENABLE
);
1223 WARN(cur_state
!= state
,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1228 static void assert_plane(struct drm_i915_private
*dev_priv
,
1229 enum plane plane
, bool state
)
1235 reg
= DSPCNTR(plane
);
1236 val
= I915_READ(reg
);
1237 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1238 WARN(cur_state
!= state
,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane
), state_string(state
), state_string(cur_state
));
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1246 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1255 reg
= DSPCNTR(pipe
);
1256 val
= I915_READ(reg
);
1257 WARN((val
& DISPLAY_PLANE_ENABLE
),
1258 "plane %c assertion failure, should be disabled but not\n",
1263 /* Need to check both planes against the pipe */
1264 for (i
= 0; i
< 2; i
++) {
1266 val
= I915_READ(reg
);
1267 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1268 DISPPLANE_SEL_PIPE_SHIFT
;
1269 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i
), pipe_name(pipe
));
1275 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1280 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 val
= I915_READ(PCH_DREF_CONTROL
);
1286 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1287 DREF_SUPERSPREAD_SOURCE_MASK
));
1288 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1291 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1298 reg
= TRANSCONF(pipe
);
1299 val
= I915_READ(reg
);
1300 enabled
= !!(val
& TRANS_ENABLE
);
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1307 enum pipe pipe
, u32 port_sel
, u32 val
)
1309 if ((val
& DP_PORT_EN
) == 0)
1312 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1313 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1314 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1315 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1318 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1324 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1325 enum pipe pipe
, u32 val
)
1327 if ((val
& PORT_ENABLE
) == 0)
1330 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1331 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1334 if ((val
& TRANSCODER_MASK
) != TRANSCODER(pipe
))
1340 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1341 enum pipe pipe
, u32 val
)
1343 if ((val
& LVDS_PORT_EN
) == 0)
1346 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1347 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1350 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1356 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1357 enum pipe pipe
, u32 val
)
1359 if ((val
& ADPA_DAC_ENABLE
) == 0)
1361 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1362 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1365 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1371 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1372 enum pipe pipe
, int reg
, u32 port_sel
)
1374 u32 val
= I915_READ(reg
);
1375 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg
, pipe_name(pipe
));
1379 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1380 && (val
& DP_PIPEB_SELECT
),
1381 "IBX PCH dp port still using transcoder B\n");
1384 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1385 enum pipe pipe
, int reg
)
1387 u32 val
= I915_READ(reg
);
1388 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1389 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1390 reg
, pipe_name(pipe
));
1392 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& PORT_ENABLE
) == 0
1393 && (val
& SDVO_PIPE_B_SELECT
),
1394 "IBX PCH hdmi port still using transcoder B\n");
1397 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1403 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1404 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1405 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1408 val
= I915_READ(reg
);
1409 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1410 "PCH VGA enabled on transcoder %c, should be disabled\n",
1414 val
= I915_READ(reg
);
1415 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1416 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1419 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1420 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1421 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1425 * intel_enable_pll - enable a PLL
1426 * @dev_priv: i915 private structure
1427 * @pipe: pipe PLL to enable
1429 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1430 * make sure the PLL reg is writable first though, since the panel write
1431 * protect mechanism may be enabled.
1433 * Note! This is for pre-ILK only.
1435 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1437 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1442 /* No really, not for ILK+ */
1443 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1445 /* PLL is protected by panel, make sure we can write it */
1446 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1447 assert_panel_unlocked(dev_priv
, pipe
);
1450 val
= I915_READ(reg
);
1451 val
|= DPLL_VCO_ENABLE
;
1453 /* We do this three times for luck */
1454 I915_WRITE(reg
, val
);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg
, val
);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg
, val
);
1462 udelay(150); /* wait for warmup */
1466 * intel_disable_pll - disable a PLL
1467 * @dev_priv: i915 private structure
1468 * @pipe: pipe PLL to disable
1470 * Disable the PLL for @pipe, making sure the pipe is off first.
1472 * Note! This is for pre-ILK only.
1474 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1479 /* Don't disable pipe A or pipe A PLLs if needed */
1480 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1483 /* Make sure the pipe isn't still relying on us */
1484 assert_pipe_disabled(dev_priv
, pipe
);
1487 val
= I915_READ(reg
);
1488 val
&= ~DPLL_VCO_ENABLE
;
1489 I915_WRITE(reg
, val
);
1495 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
)
1497 unsigned long flags
;
1499 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1500 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1502 DRM_ERROR("timeout waiting for SBI to become ready\n");
1506 I915_WRITE(SBI_ADDR
,
1508 I915_WRITE(SBI_DATA
,
1510 I915_WRITE(SBI_CTL_STAT
,
1514 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1516 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1521 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1525 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
)
1527 unsigned long flags
;
1530 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1531 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1533 DRM_ERROR("timeout waiting for SBI to become ready\n");
1537 I915_WRITE(SBI_ADDR
,
1539 I915_WRITE(SBI_CTL_STAT
,
1543 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1545 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1549 value
= I915_READ(SBI_DATA
);
1552 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1557 * intel_enable_pch_pll - enable PCH PLL
1558 * @dev_priv: i915 private structure
1559 * @pipe: pipe PLL to enable
1561 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1562 * drives the transcoder clock.
1564 static void intel_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1566 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1567 struct intel_pch_pll
*pll
;
1571 /* PCH PLLs only available on ILK, SNB and IVB */
1572 BUG_ON(dev_priv
->info
->gen
< 5);
1573 pll
= intel_crtc
->pch_pll
;
1577 if (WARN_ON(pll
->refcount
== 0))
1580 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1581 pll
->pll_reg
, pll
->active
, pll
->on
,
1582 intel_crtc
->base
.base
.id
);
1584 /* PCH refclock must be enabled first */
1585 assert_pch_refclk_enabled(dev_priv
);
1587 if (pll
->active
++ && pll
->on
) {
1588 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1592 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1595 val
= I915_READ(reg
);
1596 val
|= DPLL_VCO_ENABLE
;
1597 I915_WRITE(reg
, val
);
1604 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1606 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1607 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1611 /* PCH only available on ILK+ */
1612 BUG_ON(dev_priv
->info
->gen
< 5);
1616 if (WARN_ON(pll
->refcount
== 0))
1619 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1620 pll
->pll_reg
, pll
->active
, pll
->on
,
1621 intel_crtc
->base
.base
.id
);
1623 if (WARN_ON(pll
->active
== 0)) {
1624 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1628 if (--pll
->active
) {
1629 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1633 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1635 /* Make sure transcoder isn't still depending on us */
1636 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1639 val
= I915_READ(reg
);
1640 val
&= ~DPLL_VCO_ENABLE
;
1641 I915_WRITE(reg
, val
);
1648 static void intel_enable_transcoder(struct drm_i915_private
*dev_priv
,
1652 u32 val
, pipeconf_val
;
1653 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1655 /* PCH only available on ILK+ */
1656 BUG_ON(dev_priv
->info
->gen
< 5);
1658 /* Make sure PCH DPLL is enabled */
1659 assert_pch_pll_enabled(dev_priv
,
1660 to_intel_crtc(crtc
)->pch_pll
,
1661 to_intel_crtc(crtc
));
1663 /* FDI must be feeding us bits for PCH ports */
1664 assert_fdi_tx_enabled(dev_priv
, pipe
);
1665 assert_fdi_rx_enabled(dev_priv
, pipe
);
1667 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1668 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1671 reg
= TRANSCONF(pipe
);
1672 val
= I915_READ(reg
);
1673 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1675 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1677 * make the BPC in transcoder be consistent with
1678 * that in pipeconf reg.
1680 val
&= ~PIPE_BPC_MASK
;
1681 val
|= pipeconf_val
& PIPE_BPC_MASK
;
1684 val
&= ~TRANS_INTERLACE_MASK
;
1685 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1686 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1687 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1688 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1690 val
|= TRANS_INTERLACED
;
1692 val
|= TRANS_PROGRESSIVE
;
1694 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1695 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1696 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1699 static void intel_disable_transcoder(struct drm_i915_private
*dev_priv
,
1705 /* FDI relies on the transcoder */
1706 assert_fdi_tx_disabled(dev_priv
, pipe
);
1707 assert_fdi_rx_disabled(dev_priv
, pipe
);
1709 /* Ports must be off as well */
1710 assert_pch_ports_disabled(dev_priv
, pipe
);
1712 reg
= TRANSCONF(pipe
);
1713 val
= I915_READ(reg
);
1714 val
&= ~TRANS_ENABLE
;
1715 I915_WRITE(reg
, val
);
1716 /* wait for PCH transcoder off, transcoder state */
1717 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1718 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1722 * intel_enable_pipe - enable a pipe, asserting requirements
1723 * @dev_priv: i915 private structure
1724 * @pipe: pipe to enable
1725 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1727 * Enable @pipe, making sure that various hardware specific requirements
1728 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1730 * @pipe should be %PIPE_A or %PIPE_B.
1732 * Will wait until the pipe is actually running (i.e. first vblank) before
1735 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1742 * A pipe without a PLL won't actually be able to drive bits from
1743 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1746 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1747 assert_pll_enabled(dev_priv
, pipe
);
1750 /* if driving the PCH, we need FDI enabled */
1751 assert_fdi_rx_pll_enabled(dev_priv
, pipe
);
1752 assert_fdi_tx_pll_enabled(dev_priv
, pipe
);
1754 /* FIXME: assert CPU port conditions for SNB+ */
1757 reg
= PIPECONF(pipe
);
1758 val
= I915_READ(reg
);
1759 if (val
& PIPECONF_ENABLE
)
1762 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1763 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1767 * intel_disable_pipe - disable a pipe, asserting requirements
1768 * @dev_priv: i915 private structure
1769 * @pipe: pipe to disable
1771 * Disable @pipe, making sure that various hardware specific requirements
1772 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1774 * @pipe should be %PIPE_A or %PIPE_B.
1776 * Will wait until the pipe has shut down before returning.
1778 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1785 * Make sure planes won't keep trying to pump pixels to us,
1786 * or we might hang the display.
1788 assert_planes_disabled(dev_priv
, pipe
);
1790 /* Don't disable pipe A or pipe A PLLs if needed */
1791 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1794 reg
= PIPECONF(pipe
);
1795 val
= I915_READ(reg
);
1796 if ((val
& PIPECONF_ENABLE
) == 0)
1799 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1800 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1804 * Plane regs are double buffered, going from enabled->disabled needs a
1805 * trigger in order to latch. The display address reg provides this.
1807 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1810 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1811 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1815 * intel_enable_plane - enable a display plane on a given pipe
1816 * @dev_priv: i915 private structure
1817 * @plane: plane to enable
1818 * @pipe: pipe being fed
1820 * Enable @plane on @pipe, making sure that @pipe is running first.
1822 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1823 enum plane plane
, enum pipe pipe
)
1828 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1829 assert_pipe_enabled(dev_priv
, pipe
);
1831 reg
= DSPCNTR(plane
);
1832 val
= I915_READ(reg
);
1833 if (val
& DISPLAY_PLANE_ENABLE
)
1836 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1837 intel_flush_display_plane(dev_priv
, plane
);
1838 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1842 * intel_disable_plane - disable a display plane
1843 * @dev_priv: i915 private structure
1844 * @plane: plane to disable
1845 * @pipe: pipe consuming the data
1847 * Disable @plane; should be an independent operation.
1849 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1850 enum plane plane
, enum pipe pipe
)
1855 reg
= DSPCNTR(plane
);
1856 val
= I915_READ(reg
);
1857 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1860 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1861 intel_flush_display_plane(dev_priv
, plane
);
1862 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1866 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1867 struct drm_i915_gem_object
*obj
,
1868 struct intel_ring_buffer
*pipelined
)
1870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1874 switch (obj
->tiling_mode
) {
1875 case I915_TILING_NONE
:
1876 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1877 alignment
= 128 * 1024;
1878 else if (INTEL_INFO(dev
)->gen
>= 4)
1879 alignment
= 4 * 1024;
1881 alignment
= 64 * 1024;
1884 /* pin() will align the object as required by fence */
1888 /* FIXME: Is this true? */
1889 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1895 dev_priv
->mm
.interruptible
= false;
1896 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1898 goto err_interruptible
;
1900 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1901 * fence, whereas 965+ only requires a fence if using
1902 * framebuffer compression. For simplicity, we always install
1903 * a fence as the cost is not that onerous.
1905 ret
= i915_gem_object_get_fence(obj
);
1909 i915_gem_object_pin_fence(obj
);
1911 dev_priv
->mm
.interruptible
= true;
1915 i915_gem_object_unpin(obj
);
1917 dev_priv
->mm
.interruptible
= true;
1921 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1923 i915_gem_object_unpin_fence(obj
);
1924 i915_gem_object_unpin(obj
);
1927 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1928 * is assumed to be a power-of-two. */
1929 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x
, int *y
,
1933 int tile_rows
, tiles
;
1937 tiles
= *x
/ (512/bpp
);
1940 return tile_rows
* pitch
* 8 + tiles
* 4096;
1943 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1946 struct drm_device
*dev
= crtc
->dev
;
1947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1948 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1949 struct intel_framebuffer
*intel_fb
;
1950 struct drm_i915_gem_object
*obj
;
1951 int plane
= intel_crtc
->plane
;
1952 unsigned long linear_offset
;
1961 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1965 intel_fb
= to_intel_framebuffer(fb
);
1966 obj
= intel_fb
->obj
;
1968 reg
= DSPCNTR(plane
);
1969 dspcntr
= I915_READ(reg
);
1970 /* Mask out pixel format bits in case we change it */
1971 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1972 switch (fb
->bits_per_pixel
) {
1974 dspcntr
|= DISPPLANE_8BPP
;
1977 if (fb
->depth
== 15)
1978 dspcntr
|= DISPPLANE_15_16BPP
;
1980 dspcntr
|= DISPPLANE_16BPP
;
1984 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1987 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
1990 if (INTEL_INFO(dev
)->gen
>= 4) {
1991 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1992 dspcntr
|= DISPPLANE_TILED
;
1994 dspcntr
&= ~DISPPLANE_TILED
;
1997 I915_WRITE(reg
, dspcntr
);
1999 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2001 if (INTEL_INFO(dev
)->gen
>= 4) {
2002 intel_crtc
->dspaddr_offset
=
2003 gen4_compute_dspaddr_offset_xtiled(&x
, &y
,
2004 fb
->bits_per_pixel
/ 8,
2006 linear_offset
-= intel_crtc
->dspaddr_offset
;
2008 intel_crtc
->dspaddr_offset
= linear_offset
;
2011 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2012 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2013 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2014 if (INTEL_INFO(dev
)->gen
>= 4) {
2015 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2016 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2017 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2018 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2020 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2026 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2027 struct drm_framebuffer
*fb
, int x
, int y
)
2029 struct drm_device
*dev
= crtc
->dev
;
2030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2031 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2032 struct intel_framebuffer
*intel_fb
;
2033 struct drm_i915_gem_object
*obj
;
2034 int plane
= intel_crtc
->plane
;
2035 unsigned long linear_offset
;
2045 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2049 intel_fb
= to_intel_framebuffer(fb
);
2050 obj
= intel_fb
->obj
;
2052 reg
= DSPCNTR(plane
);
2053 dspcntr
= I915_READ(reg
);
2054 /* Mask out pixel format bits in case we change it */
2055 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2056 switch (fb
->bits_per_pixel
) {
2058 dspcntr
|= DISPPLANE_8BPP
;
2061 if (fb
->depth
!= 16)
2064 dspcntr
|= DISPPLANE_16BPP
;
2068 if (fb
->depth
== 24)
2069 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2070 else if (fb
->depth
== 30)
2071 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
2076 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2080 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2081 dspcntr
|= DISPPLANE_TILED
;
2083 dspcntr
&= ~DISPPLANE_TILED
;
2086 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2088 I915_WRITE(reg
, dspcntr
);
2090 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2091 intel_crtc
->dspaddr_offset
=
2092 gen4_compute_dspaddr_offset_xtiled(&x
, &y
,
2093 fb
->bits_per_pixel
/ 8,
2095 linear_offset
-= intel_crtc
->dspaddr_offset
;
2097 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2099 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2100 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2101 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2102 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2103 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2109 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2111 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2112 int x
, int y
, enum mode_set_atomic state
)
2114 struct drm_device
*dev
= crtc
->dev
;
2115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2117 if (dev_priv
->display
.disable_fbc
)
2118 dev_priv
->display
.disable_fbc(dev
);
2119 intel_increase_pllclock(crtc
);
2121 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2125 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2127 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2128 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2129 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2132 wait_event(dev_priv
->pending_flip_queue
,
2133 atomic_read(&dev_priv
->mm
.wedged
) ||
2134 atomic_read(&obj
->pending_flip
) == 0);
2136 /* Big Hammer, we also need to ensure that any pending
2137 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2138 * current scanout is retired before unpinning the old
2141 * This should only fail upon a hung GPU, in which case we
2142 * can safely continue.
2144 dev_priv
->mm
.interruptible
= false;
2145 ret
= i915_gem_object_finish_gpu(obj
);
2146 dev_priv
->mm
.interruptible
= was_interruptible
;
2152 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2153 struct drm_framebuffer
*fb
)
2155 struct drm_device
*dev
= crtc
->dev
;
2156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2157 struct drm_i915_master_private
*master_priv
;
2158 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2159 struct drm_framebuffer
*old_fb
;
2164 DRM_ERROR("No FB bound\n");
2168 if(intel_crtc
->plane
> dev_priv
->num_pipe
) {
2169 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2171 dev_priv
->num_pipe
);
2175 mutex_lock(&dev
->struct_mutex
);
2176 ret
= intel_pin_and_fence_fb_obj(dev
,
2177 to_intel_framebuffer(fb
)->obj
,
2180 mutex_unlock(&dev
->struct_mutex
);
2181 DRM_ERROR("pin & fence failed\n");
2186 intel_finish_fb(crtc
->fb
);
2188 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2190 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2191 mutex_unlock(&dev
->struct_mutex
);
2192 DRM_ERROR("failed to update base address\n");
2202 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2203 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2206 intel_update_fbc(dev
);
2207 mutex_unlock(&dev
->struct_mutex
);
2209 if (!dev
->primary
->master
)
2212 master_priv
= dev
->primary
->master
->driver_priv
;
2213 if (!master_priv
->sarea_priv
)
2216 if (intel_crtc
->pipe
) {
2217 master_priv
->sarea_priv
->pipeB_x
= x
;
2218 master_priv
->sarea_priv
->pipeB_y
= y
;
2220 master_priv
->sarea_priv
->pipeA_x
= x
;
2221 master_priv
->sarea_priv
->pipeA_y
= y
;
2227 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2229 struct drm_device
*dev
= crtc
->dev
;
2230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2233 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2234 dpa_ctl
= I915_READ(DP_A
);
2235 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2237 if (clock
< 200000) {
2239 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2240 /* workaround for 160Mhz:
2241 1) program 0x4600c bits 15:0 = 0x8124
2242 2) program 0x46010 bit 0 = 1
2243 3) program 0x46034 bit 24 = 1
2244 4) program 0x64000 bit 14 = 1
2246 temp
= I915_READ(0x4600c);
2248 I915_WRITE(0x4600c, temp
| 0x8124);
2250 temp
= I915_READ(0x46010);
2251 I915_WRITE(0x46010, temp
| 1);
2253 temp
= I915_READ(0x46034);
2254 I915_WRITE(0x46034, temp
| (1 << 24));
2256 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2258 I915_WRITE(DP_A
, dpa_ctl
);
2264 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2266 struct drm_device
*dev
= crtc
->dev
;
2267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2268 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2269 int pipe
= intel_crtc
->pipe
;
2272 /* enable normal train */
2273 reg
= FDI_TX_CTL(pipe
);
2274 temp
= I915_READ(reg
);
2275 if (IS_IVYBRIDGE(dev
)) {
2276 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2277 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2279 temp
&= ~FDI_LINK_TRAIN_NONE
;
2280 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2282 I915_WRITE(reg
, temp
);
2284 reg
= FDI_RX_CTL(pipe
);
2285 temp
= I915_READ(reg
);
2286 if (HAS_PCH_CPT(dev
)) {
2287 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2288 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2290 temp
&= ~FDI_LINK_TRAIN_NONE
;
2291 temp
|= FDI_LINK_TRAIN_NONE
;
2293 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2295 /* wait one idle pattern time */
2299 /* IVB wants error correction enabled */
2300 if (IS_IVYBRIDGE(dev
))
2301 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2302 FDI_FE_ERRC_ENABLE
);
2305 static void cpt_phase_pointer_enable(struct drm_device
*dev
, int pipe
)
2307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2308 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2310 flags
|= FDI_PHASE_SYNC_OVR(pipe
);
2311 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to unlock... */
2312 flags
|= FDI_PHASE_SYNC_EN(pipe
);
2313 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to enable */
2314 POSTING_READ(SOUTH_CHICKEN1
);
2317 /* The FDI link training functions for ILK/Ibexpeak. */
2318 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2320 struct drm_device
*dev
= crtc
->dev
;
2321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2322 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2323 int pipe
= intel_crtc
->pipe
;
2324 int plane
= intel_crtc
->plane
;
2325 u32 reg
, temp
, tries
;
2327 /* FDI needs bits from pipe & plane first */
2328 assert_pipe_enabled(dev_priv
, pipe
);
2329 assert_plane_enabled(dev_priv
, plane
);
2331 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2333 reg
= FDI_RX_IMR(pipe
);
2334 temp
= I915_READ(reg
);
2335 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2336 temp
&= ~FDI_RX_BIT_LOCK
;
2337 I915_WRITE(reg
, temp
);
2341 /* enable CPU FDI TX and PCH FDI RX */
2342 reg
= FDI_TX_CTL(pipe
);
2343 temp
= I915_READ(reg
);
2345 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2346 temp
&= ~FDI_LINK_TRAIN_NONE
;
2347 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2348 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2350 reg
= FDI_RX_CTL(pipe
);
2351 temp
= I915_READ(reg
);
2352 temp
&= ~FDI_LINK_TRAIN_NONE
;
2353 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2354 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2359 /* Ironlake workaround, enable clock pointer after FDI enable*/
2360 if (HAS_PCH_IBX(dev
)) {
2361 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2363 FDI_RX_PHASE_SYNC_POINTER_EN
);
2366 reg
= FDI_RX_IIR(pipe
);
2367 for (tries
= 0; tries
< 5; tries
++) {
2368 temp
= I915_READ(reg
);
2369 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2371 if ((temp
& FDI_RX_BIT_LOCK
)) {
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
2373 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2378 DRM_ERROR("FDI train 1 fail!\n");
2381 reg
= FDI_TX_CTL(pipe
);
2382 temp
= I915_READ(reg
);
2383 temp
&= ~FDI_LINK_TRAIN_NONE
;
2384 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2385 I915_WRITE(reg
, temp
);
2387 reg
= FDI_RX_CTL(pipe
);
2388 temp
= I915_READ(reg
);
2389 temp
&= ~FDI_LINK_TRAIN_NONE
;
2390 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2391 I915_WRITE(reg
, temp
);
2396 reg
= FDI_RX_IIR(pipe
);
2397 for (tries
= 0; tries
< 5; tries
++) {
2398 temp
= I915_READ(reg
);
2399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2401 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2402 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2403 DRM_DEBUG_KMS("FDI train 2 done.\n");
2408 DRM_ERROR("FDI train 2 fail!\n");
2410 DRM_DEBUG_KMS("FDI train done\n");
2414 static const int snb_b_fdi_train_param
[] = {
2415 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2416 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2417 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2418 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2421 /* The FDI link training functions for SNB/Cougarpoint. */
2422 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2424 struct drm_device
*dev
= crtc
->dev
;
2425 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2426 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2427 int pipe
= intel_crtc
->pipe
;
2428 u32 reg
, temp
, i
, retry
;
2430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2432 reg
= FDI_RX_IMR(pipe
);
2433 temp
= I915_READ(reg
);
2434 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2435 temp
&= ~FDI_RX_BIT_LOCK
;
2436 I915_WRITE(reg
, temp
);
2441 /* enable CPU FDI TX and PCH FDI RX */
2442 reg
= FDI_TX_CTL(pipe
);
2443 temp
= I915_READ(reg
);
2445 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2446 temp
&= ~FDI_LINK_TRAIN_NONE
;
2447 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2448 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2450 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2451 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2453 reg
= FDI_RX_CTL(pipe
);
2454 temp
= I915_READ(reg
);
2455 if (HAS_PCH_CPT(dev
)) {
2456 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2457 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2459 temp
&= ~FDI_LINK_TRAIN_NONE
;
2460 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2462 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2467 if (HAS_PCH_CPT(dev
))
2468 cpt_phase_pointer_enable(dev
, pipe
);
2470 for (i
= 0; i
< 4; i
++) {
2471 reg
= FDI_TX_CTL(pipe
);
2472 temp
= I915_READ(reg
);
2473 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2474 temp
|= snb_b_fdi_train_param
[i
];
2475 I915_WRITE(reg
, temp
);
2480 for (retry
= 0; retry
< 5; retry
++) {
2481 reg
= FDI_RX_IIR(pipe
);
2482 temp
= I915_READ(reg
);
2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2484 if (temp
& FDI_RX_BIT_LOCK
) {
2485 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2486 DRM_DEBUG_KMS("FDI train 1 done.\n");
2495 DRM_ERROR("FDI train 1 fail!\n");
2498 reg
= FDI_TX_CTL(pipe
);
2499 temp
= I915_READ(reg
);
2500 temp
&= ~FDI_LINK_TRAIN_NONE
;
2501 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2503 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2505 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2507 I915_WRITE(reg
, temp
);
2509 reg
= FDI_RX_CTL(pipe
);
2510 temp
= I915_READ(reg
);
2511 if (HAS_PCH_CPT(dev
)) {
2512 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2513 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2515 temp
&= ~FDI_LINK_TRAIN_NONE
;
2516 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2518 I915_WRITE(reg
, temp
);
2523 for (i
= 0; i
< 4; i
++) {
2524 reg
= FDI_TX_CTL(pipe
);
2525 temp
= I915_READ(reg
);
2526 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2527 temp
|= snb_b_fdi_train_param
[i
];
2528 I915_WRITE(reg
, temp
);
2533 for (retry
= 0; retry
< 5; retry
++) {
2534 reg
= FDI_RX_IIR(pipe
);
2535 temp
= I915_READ(reg
);
2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2537 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2538 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2539 DRM_DEBUG_KMS("FDI train 2 done.\n");
2548 DRM_ERROR("FDI train 2 fail!\n");
2550 DRM_DEBUG_KMS("FDI train done.\n");
2553 /* Manual link training for Ivy Bridge A0 parts */
2554 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2556 struct drm_device
*dev
= crtc
->dev
;
2557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2558 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2559 int pipe
= intel_crtc
->pipe
;
2562 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2564 reg
= FDI_RX_IMR(pipe
);
2565 temp
= I915_READ(reg
);
2566 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2567 temp
&= ~FDI_RX_BIT_LOCK
;
2568 I915_WRITE(reg
, temp
);
2573 /* enable CPU FDI TX and PCH FDI RX */
2574 reg
= FDI_TX_CTL(pipe
);
2575 temp
= I915_READ(reg
);
2577 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2578 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2579 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2580 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2581 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2582 temp
|= FDI_COMPOSITE_SYNC
;
2583 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2585 reg
= FDI_RX_CTL(pipe
);
2586 temp
= I915_READ(reg
);
2587 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2588 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2589 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2590 temp
|= FDI_COMPOSITE_SYNC
;
2591 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2596 if (HAS_PCH_CPT(dev
))
2597 cpt_phase_pointer_enable(dev
, pipe
);
2599 for (i
= 0; i
< 4; i
++) {
2600 reg
= FDI_TX_CTL(pipe
);
2601 temp
= I915_READ(reg
);
2602 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2603 temp
|= snb_b_fdi_train_param
[i
];
2604 I915_WRITE(reg
, temp
);
2609 reg
= FDI_RX_IIR(pipe
);
2610 temp
= I915_READ(reg
);
2611 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2613 if (temp
& FDI_RX_BIT_LOCK
||
2614 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2615 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2616 DRM_DEBUG_KMS("FDI train 1 done.\n");
2621 DRM_ERROR("FDI train 1 fail!\n");
2624 reg
= FDI_TX_CTL(pipe
);
2625 temp
= I915_READ(reg
);
2626 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2627 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2628 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2629 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2630 I915_WRITE(reg
, temp
);
2632 reg
= FDI_RX_CTL(pipe
);
2633 temp
= I915_READ(reg
);
2634 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2635 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2636 I915_WRITE(reg
, temp
);
2641 for (i
= 0; i
< 4; i
++) {
2642 reg
= FDI_TX_CTL(pipe
);
2643 temp
= I915_READ(reg
);
2644 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2645 temp
|= snb_b_fdi_train_param
[i
];
2646 I915_WRITE(reg
, temp
);
2651 reg
= FDI_RX_IIR(pipe
);
2652 temp
= I915_READ(reg
);
2653 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2655 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2656 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2657 DRM_DEBUG_KMS("FDI train 2 done.\n");
2662 DRM_ERROR("FDI train 2 fail!\n");
2664 DRM_DEBUG_KMS("FDI train done.\n");
2667 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2669 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2671 int pipe
= intel_crtc
->pipe
;
2674 /* Write the TU size bits so error detection works */
2675 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2676 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2678 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2679 reg
= FDI_RX_CTL(pipe
);
2680 temp
= I915_READ(reg
);
2681 temp
&= ~((0x7 << 19) | (0x7 << 16));
2682 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2683 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2684 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2689 /* Switch from Rawclk to PCDclk */
2690 temp
= I915_READ(reg
);
2691 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2696 /* On Haswell, the PLL configuration for ports and pipes is handled
2697 * separately, as part of DDI setup */
2698 if (!IS_HASWELL(dev
)) {
2699 /* Enable CPU FDI TX PLL, always on for Ironlake */
2700 reg
= FDI_TX_CTL(pipe
);
2701 temp
= I915_READ(reg
);
2702 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2703 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2711 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2713 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2715 int pipe
= intel_crtc
->pipe
;
2718 /* Switch from PCDclk to Rawclk */
2719 reg
= FDI_RX_CTL(pipe
);
2720 temp
= I915_READ(reg
);
2721 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2723 /* Disable CPU FDI TX PLL */
2724 reg
= FDI_TX_CTL(pipe
);
2725 temp
= I915_READ(reg
);
2726 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2731 reg
= FDI_RX_CTL(pipe
);
2732 temp
= I915_READ(reg
);
2733 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2735 /* Wait for the clocks to turn off. */
2740 static void cpt_phase_pointer_disable(struct drm_device
*dev
, int pipe
)
2742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2743 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2745 flags
&= ~(FDI_PHASE_SYNC_EN(pipe
));
2746 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to disable... */
2747 flags
&= ~(FDI_PHASE_SYNC_OVR(pipe
));
2748 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to lock */
2749 POSTING_READ(SOUTH_CHICKEN1
);
2751 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2753 struct drm_device
*dev
= crtc
->dev
;
2754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2755 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2756 int pipe
= intel_crtc
->pipe
;
2759 /* disable CPU FDI tx and PCH FDI rx */
2760 reg
= FDI_TX_CTL(pipe
);
2761 temp
= I915_READ(reg
);
2762 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2765 reg
= FDI_RX_CTL(pipe
);
2766 temp
= I915_READ(reg
);
2767 temp
&= ~(0x7 << 16);
2768 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2769 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2774 /* Ironlake workaround, disable clock pointer after downing FDI */
2775 if (HAS_PCH_IBX(dev
)) {
2776 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2777 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2778 I915_READ(FDI_RX_CHICKEN(pipe
) &
2779 ~FDI_RX_PHASE_SYNC_POINTER_EN
));
2780 } else if (HAS_PCH_CPT(dev
)) {
2781 cpt_phase_pointer_disable(dev
, pipe
);
2784 /* still set train pattern 1 */
2785 reg
= FDI_TX_CTL(pipe
);
2786 temp
= I915_READ(reg
);
2787 temp
&= ~FDI_LINK_TRAIN_NONE
;
2788 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2789 I915_WRITE(reg
, temp
);
2791 reg
= FDI_RX_CTL(pipe
);
2792 temp
= I915_READ(reg
);
2793 if (HAS_PCH_CPT(dev
)) {
2794 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2795 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2797 temp
&= ~FDI_LINK_TRAIN_NONE
;
2798 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2800 /* BPC in FDI rx is consistent with that in PIPECONF */
2801 temp
&= ~(0x07 << 16);
2802 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2803 I915_WRITE(reg
, temp
);
2809 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2811 struct drm_device
*dev
= crtc
->dev
;
2813 if (crtc
->fb
== NULL
)
2816 mutex_lock(&dev
->struct_mutex
);
2817 intel_finish_fb(crtc
->fb
);
2818 mutex_unlock(&dev
->struct_mutex
);
2821 static bool intel_crtc_driving_pch(struct drm_crtc
*crtc
)
2823 struct drm_device
*dev
= crtc
->dev
;
2824 struct intel_encoder
*intel_encoder
;
2827 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2828 * must be driven by its own crtc; no sharing is possible.
2830 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
2832 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2833 * CPU handles all others */
2834 if (IS_HASWELL(dev
)) {
2835 /* It is still unclear how this will work on PPT, so throw up a warning */
2836 WARN_ON(!HAS_PCH_LPT(dev
));
2838 if (intel_encoder
->type
== INTEL_OUTPUT_ANALOG
) {
2839 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2842 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2843 intel_encoder
->type
);
2848 switch (intel_encoder
->type
) {
2849 case INTEL_OUTPUT_EDP
:
2850 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
2859 /* Program iCLKIP clock to the desired frequency */
2860 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2862 struct drm_device
*dev
= crtc
->dev
;
2863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2864 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2867 /* It is necessary to ungate the pixclk gate prior to programming
2868 * the divisors, and gate it back when it is done.
2870 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2872 /* Disable SSCCTL */
2873 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2874 intel_sbi_read(dev_priv
, SBI_SSCCTL6
) |
2875 SBI_SSCCTL_DISABLE
);
2877 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2878 if (crtc
->mode
.clock
== 20000) {
2883 /* The iCLK virtual clock root frequency is in MHz,
2884 * but the crtc->mode.clock in in KHz. To get the divisors,
2885 * it is necessary to divide one by another, so we
2886 * convert the virtual clock precision to KHz here for higher
2889 u32 iclk_virtual_root_freq
= 172800 * 1000;
2890 u32 iclk_pi_range
= 64;
2891 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2893 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2894 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2895 pi_value
= desired_divisor
% iclk_pi_range
;
2898 divsel
= msb_divisor_value
- 2;
2899 phaseinc
= pi_value
;
2902 /* This should not happen with any sane values */
2903 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2904 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2905 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2906 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2908 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2915 /* Program SSCDIVINTPHASE6 */
2916 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
);
2917 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2918 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2919 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2920 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2921 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2922 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2924 intel_sbi_write(dev_priv
,
2925 SBI_SSCDIVINTPHASE6
,
2928 /* Program SSCAUXDIV */
2929 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
);
2930 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2931 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2932 intel_sbi_write(dev_priv
,
2937 /* Enable modulator and associated divider */
2938 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
);
2939 temp
&= ~SBI_SSCCTL_DISABLE
;
2940 intel_sbi_write(dev_priv
,
2944 /* Wait for initialization time */
2947 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2951 * Enable PCH resources required for PCH ports:
2953 * - FDI training & RX/TX
2954 * - update transcoder timings
2955 * - DP transcoding bits
2958 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2960 struct drm_device
*dev
= crtc
->dev
;
2961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2962 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2963 int pipe
= intel_crtc
->pipe
;
2966 assert_transcoder_disabled(dev_priv
, pipe
);
2968 /* For PCH output, training FDI link */
2969 dev_priv
->display
.fdi_link_train(crtc
);
2971 intel_enable_pch_pll(intel_crtc
);
2973 if (HAS_PCH_LPT(dev
)) {
2974 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2975 lpt_program_iclkip(crtc
);
2976 } else if (HAS_PCH_CPT(dev
)) {
2979 temp
= I915_READ(PCH_DPLL_SEL
);
2983 temp
|= TRANSA_DPLL_ENABLE
;
2984 sel
= TRANSA_DPLLB_SEL
;
2987 temp
|= TRANSB_DPLL_ENABLE
;
2988 sel
= TRANSB_DPLLB_SEL
;
2991 temp
|= TRANSC_DPLL_ENABLE
;
2992 sel
= TRANSC_DPLLB_SEL
;
2995 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
2999 I915_WRITE(PCH_DPLL_SEL
, temp
);
3002 /* set transcoder timing, panel must allow it */
3003 assert_panel_unlocked(dev_priv
, pipe
);
3004 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3005 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3006 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3008 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3009 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3010 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3011 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3013 if (!IS_HASWELL(dev
))
3014 intel_fdi_normal_train(crtc
);
3016 /* For PCH DP, enable TRANS_DP_CTL */
3017 if (HAS_PCH_CPT(dev
) &&
3018 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3019 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3020 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) >> 5;
3021 reg
= TRANS_DP_CTL(pipe
);
3022 temp
= I915_READ(reg
);
3023 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3024 TRANS_DP_SYNC_MASK
|
3026 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3027 TRANS_DP_ENH_FRAMING
);
3028 temp
|= bpc
<< 9; /* same format but at 11:9 */
3030 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3031 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3032 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3033 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3035 switch (intel_trans_dp_port_sel(crtc
)) {
3037 temp
|= TRANS_DP_PORT_SEL_B
;
3040 temp
|= TRANS_DP_PORT_SEL_C
;
3043 temp
|= TRANS_DP_PORT_SEL_D
;
3046 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3047 temp
|= TRANS_DP_PORT_SEL_B
;
3051 I915_WRITE(reg
, temp
);
3054 intel_enable_transcoder(dev_priv
, pipe
);
3057 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3059 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3064 if (pll
->refcount
== 0) {
3065 WARN(1, "bad PCH PLL refcount\n");
3070 intel_crtc
->pch_pll
= NULL
;
3073 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3075 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3076 struct intel_pch_pll
*pll
;
3079 pll
= intel_crtc
->pch_pll
;
3081 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3082 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3086 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3087 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3088 i
= intel_crtc
->pipe
;
3089 pll
= &dev_priv
->pch_plls
[i
];
3091 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3092 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3097 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3098 pll
= &dev_priv
->pch_plls
[i
];
3100 /* Only want to check enabled timings first */
3101 if (pll
->refcount
== 0)
3104 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3105 fp
== I915_READ(pll
->fp0_reg
)) {
3106 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3107 intel_crtc
->base
.base
.id
,
3108 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3114 /* Ok no matching timings, maybe there's a free one? */
3115 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3116 pll
= &dev_priv
->pch_plls
[i
];
3117 if (pll
->refcount
== 0) {
3118 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3119 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3127 intel_crtc
->pch_pll
= pll
;
3129 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3130 prepare
: /* separate function? */
3131 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3133 /* Wait for the clocks to stabilize before rewriting the regs */
3134 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3135 POSTING_READ(pll
->pll_reg
);
3138 I915_WRITE(pll
->fp0_reg
, fp
);
3139 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3144 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3147 int dslreg
= PIPEDSL(pipe
), tc2reg
= TRANS_CHICKEN2(pipe
);
3150 temp
= I915_READ(dslreg
);
3152 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3153 /* Without this, mode sets may fail silently on FDI */
3154 I915_WRITE(tc2reg
, TRANS_AUTOTRAIN_GEN_STALL_DIS
);
3156 I915_WRITE(tc2reg
, 0);
3157 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3158 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3162 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3164 struct drm_device
*dev
= crtc
->dev
;
3165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3166 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3167 struct intel_encoder
*encoder
;
3168 int pipe
= intel_crtc
->pipe
;
3169 int plane
= intel_crtc
->plane
;
3173 WARN_ON(!crtc
->enabled
);
3175 if (intel_crtc
->active
)
3178 intel_crtc
->active
= true;
3179 intel_update_watermarks(dev
);
3181 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3182 temp
= I915_READ(PCH_LVDS
);
3183 if ((temp
& LVDS_PORT_EN
) == 0)
3184 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3187 is_pch_port
= intel_crtc_driving_pch(crtc
);
3190 ironlake_fdi_pll_enable(intel_crtc
);
3192 assert_fdi_tx_disabled(dev_priv
, pipe
);
3193 assert_fdi_rx_disabled(dev_priv
, pipe
);
3196 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3197 if (encoder
->pre_enable
)
3198 encoder
->pre_enable(encoder
);
3200 /* Enable panel fitting for LVDS */
3201 if (dev_priv
->pch_pf_size
&&
3202 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
3203 /* Force use of hard-coded filter coefficients
3204 * as some pre-programmed values are broken,
3207 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3208 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3209 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3213 * On ILK+ LUT must be loaded before the pipe is running but with
3216 intel_crtc_load_lut(crtc
);
3218 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3219 intel_enable_plane(dev_priv
, plane
, pipe
);
3222 ironlake_pch_enable(crtc
);
3224 mutex_lock(&dev
->struct_mutex
);
3225 intel_update_fbc(dev
);
3226 mutex_unlock(&dev
->struct_mutex
);
3228 intel_crtc_update_cursor(crtc
, true);
3230 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3231 encoder
->enable(encoder
);
3233 if (HAS_PCH_CPT(dev
))
3234 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3237 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3239 struct drm_device
*dev
= crtc
->dev
;
3240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3241 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3242 struct intel_encoder
*encoder
;
3243 int pipe
= intel_crtc
->pipe
;
3244 int plane
= intel_crtc
->plane
;
3248 if (!intel_crtc
->active
)
3251 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3252 encoder
->disable(encoder
);
3254 intel_crtc_wait_for_pending_flips(crtc
);
3255 drm_vblank_off(dev
, pipe
);
3256 intel_crtc_update_cursor(crtc
, false);
3258 intel_disable_plane(dev_priv
, plane
, pipe
);
3260 if (dev_priv
->cfb_plane
== plane
)
3261 intel_disable_fbc(dev
);
3263 intel_disable_pipe(dev_priv
, pipe
);
3266 I915_WRITE(PF_CTL(pipe
), 0);
3267 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3269 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3270 if (encoder
->post_disable
)
3271 encoder
->post_disable(encoder
);
3273 ironlake_fdi_disable(crtc
);
3275 intel_disable_transcoder(dev_priv
, pipe
);
3277 if (HAS_PCH_CPT(dev
)) {
3278 /* disable TRANS_DP_CTL */
3279 reg
= TRANS_DP_CTL(pipe
);
3280 temp
= I915_READ(reg
);
3281 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3282 temp
|= TRANS_DP_PORT_SEL_NONE
;
3283 I915_WRITE(reg
, temp
);
3285 /* disable DPLL_SEL */
3286 temp
= I915_READ(PCH_DPLL_SEL
);
3289 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3292 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3295 /* C shares PLL A or B */
3296 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3301 I915_WRITE(PCH_DPLL_SEL
, temp
);
3304 /* disable PCH DPLL */
3305 intel_disable_pch_pll(intel_crtc
);
3307 ironlake_fdi_pll_disable(intel_crtc
);
3309 intel_crtc
->active
= false;
3310 intel_update_watermarks(dev
);
3312 mutex_lock(&dev
->struct_mutex
);
3313 intel_update_fbc(dev
);
3314 mutex_unlock(&dev
->struct_mutex
);
3317 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3319 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3320 intel_put_pch_pll(intel_crtc
);
3323 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3325 if (!enable
&& intel_crtc
->overlay
) {
3326 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3329 mutex_lock(&dev
->struct_mutex
);
3330 dev_priv
->mm
.interruptible
= false;
3331 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3332 dev_priv
->mm
.interruptible
= true;
3333 mutex_unlock(&dev
->struct_mutex
);
3336 /* Let userspace switch the overlay on again. In most cases userspace
3337 * has to recompute where to put it anyway.
3341 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3343 struct drm_device
*dev
= crtc
->dev
;
3344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3345 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3346 struct intel_encoder
*encoder
;
3347 int pipe
= intel_crtc
->pipe
;
3348 int plane
= intel_crtc
->plane
;
3350 WARN_ON(!crtc
->enabled
);
3352 if (intel_crtc
->active
)
3355 intel_crtc
->active
= true;
3356 intel_update_watermarks(dev
);
3358 intel_enable_pll(dev_priv
, pipe
);
3359 intel_enable_pipe(dev_priv
, pipe
, false);
3360 intel_enable_plane(dev_priv
, plane
, pipe
);
3362 intel_crtc_load_lut(crtc
);
3363 intel_update_fbc(dev
);
3365 /* Give the overlay scaler a chance to enable if it's on this pipe */
3366 intel_crtc_dpms_overlay(intel_crtc
, true);
3367 intel_crtc_update_cursor(crtc
, true);
3369 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3370 encoder
->enable(encoder
);
3373 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3375 struct drm_device
*dev
= crtc
->dev
;
3376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3377 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3378 struct intel_encoder
*encoder
;
3379 int pipe
= intel_crtc
->pipe
;
3380 int plane
= intel_crtc
->plane
;
3383 if (!intel_crtc
->active
)
3386 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3387 encoder
->disable(encoder
);
3389 /* Give the overlay scaler a chance to disable if it's on this pipe */
3390 intel_crtc_wait_for_pending_flips(crtc
);
3391 drm_vblank_off(dev
, pipe
);
3392 intel_crtc_dpms_overlay(intel_crtc
, false);
3393 intel_crtc_update_cursor(crtc
, false);
3395 if (dev_priv
->cfb_plane
== plane
)
3396 intel_disable_fbc(dev
);
3398 intel_disable_plane(dev_priv
, plane
, pipe
);
3399 intel_disable_pipe(dev_priv
, pipe
);
3400 intel_disable_pll(dev_priv
, pipe
);
3402 intel_crtc
->active
= false;
3403 intel_update_fbc(dev
);
3404 intel_update_watermarks(dev
);
3407 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3411 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3414 struct drm_device
*dev
= crtc
->dev
;
3415 struct drm_i915_master_private
*master_priv
;
3416 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3417 int pipe
= intel_crtc
->pipe
;
3419 if (!dev
->primary
->master
)
3422 master_priv
= dev
->primary
->master
->driver_priv
;
3423 if (!master_priv
->sarea_priv
)
3428 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3429 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3432 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3433 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3436 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3442 * Sets the power management mode of the pipe and plane.
3444 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3446 struct drm_device
*dev
= crtc
->dev
;
3447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3448 struct intel_encoder
*intel_encoder
;
3449 bool enable
= false;
3451 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3452 enable
|= intel_encoder
->connectors_active
;
3455 dev_priv
->display
.crtc_enable(crtc
);
3457 dev_priv
->display
.crtc_disable(crtc
);
3459 intel_crtc_update_sarea(crtc
, enable
);
3462 static void intel_crtc_noop(struct drm_crtc
*crtc
)
3466 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3468 struct drm_device
*dev
= crtc
->dev
;
3469 struct drm_connector
*connector
;
3470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3472 /* crtc should still be enabled when we disable it. */
3473 WARN_ON(!crtc
->enabled
);
3475 dev_priv
->display
.crtc_disable(crtc
);
3476 intel_crtc_update_sarea(crtc
, false);
3477 dev_priv
->display
.off(crtc
);
3479 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3480 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3483 mutex_lock(&dev
->struct_mutex
);
3484 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3485 mutex_unlock(&dev
->struct_mutex
);
3489 /* Update computed state. */
3490 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3491 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3494 if (connector
->encoder
->crtc
!= crtc
)
3497 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3498 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3502 void intel_modeset_disable(struct drm_device
*dev
)
3504 struct drm_crtc
*crtc
;
3506 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3508 intel_crtc_disable(crtc
);
3512 void intel_encoder_noop(struct drm_encoder
*encoder
)
3516 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3518 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3520 drm_encoder_cleanup(encoder
);
3521 kfree(intel_encoder
);
3524 /* Simple dpms helper for encodres with just one connector, no cloning and only
3525 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3526 * state of the entire output pipe. */
3527 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3529 if (mode
== DRM_MODE_DPMS_ON
) {
3530 encoder
->connectors_active
= true;
3532 intel_crtc_update_dpms(encoder
->base
.crtc
);
3534 encoder
->connectors_active
= false;
3536 intel_crtc_update_dpms(encoder
->base
.crtc
);
3540 /* Cross check the actual hw state with our own modeset state tracking (and it's
3541 * internal consistency). */
3542 static void intel_connector_check_state(struct intel_connector
*connector
)
3544 if (connector
->get_hw_state(connector
)) {
3545 struct intel_encoder
*encoder
= connector
->encoder
;
3546 struct drm_crtc
*crtc
;
3547 bool encoder_enabled
;
3550 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3551 connector
->base
.base
.id
,
3552 drm_get_connector_name(&connector
->base
));
3554 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3555 "wrong connector dpms state\n");
3556 WARN(connector
->base
.encoder
!= &encoder
->base
,
3557 "active connector not linked to encoder\n");
3558 WARN(!encoder
->connectors_active
,
3559 "encoder->connectors_active not set\n");
3561 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3562 WARN(!encoder_enabled
, "encoder not enabled\n");
3563 if (WARN_ON(!encoder
->base
.crtc
))
3566 crtc
= encoder
->base
.crtc
;
3568 WARN(!crtc
->enabled
, "crtc not enabled\n");
3569 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3570 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3571 "encoder active on the wrong pipe\n");
3575 /* Even simpler default implementation, if there's really no special case to
3577 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3579 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3581 /* All the simple cases only support two dpms states. */
3582 if (mode
!= DRM_MODE_DPMS_ON
)
3583 mode
= DRM_MODE_DPMS_OFF
;
3585 if (mode
== connector
->dpms
)
3588 connector
->dpms
= mode
;
3590 /* Only need to change hw state when actually enabled */
3591 if (encoder
->base
.crtc
)
3592 intel_encoder_dpms(encoder
, mode
);
3594 WARN_ON(encoder
->connectors_active
!= false);
3596 intel_modeset_check_state(connector
->dev
);
3599 /* Simple connector->get_hw_state implementation for encoders that support only
3600 * one connector and no cloning and hence the encoder state determines the state
3601 * of the connector. */
3602 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3605 struct intel_encoder
*encoder
= connector
->encoder
;
3607 return encoder
->get_hw_state(encoder
, &pipe
);
3610 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3611 const struct drm_display_mode
*mode
,
3612 struct drm_display_mode
*adjusted_mode
)
3614 struct drm_device
*dev
= crtc
->dev
;
3616 if (HAS_PCH_SPLIT(dev
)) {
3617 /* FDI link clock is fixed at 2.7G */
3618 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3622 /* All interlaced capable intel hw wants timings in frames. Note though
3623 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3624 * timings, so we need to be careful not to clobber these.*/
3625 if (!(adjusted_mode
->private_flags
& INTEL_MODE_CRTC_TIMINGS_SET
))
3626 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3628 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3629 * with a hsync front porch of 0.
3631 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
3632 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
3638 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3640 return 400000; /* FIXME */
3643 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3648 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3653 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3658 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3662 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3664 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3667 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3668 case GC_DISPLAY_CLOCK_333_MHZ
:
3671 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3677 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3682 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3685 /* Assume that the hardware is in the high speed state. This
3686 * should be the default.
3688 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3689 case GC_CLOCK_133_200
:
3690 case GC_CLOCK_100_200
:
3692 case GC_CLOCK_166_250
:
3694 case GC_CLOCK_100_133
:
3698 /* Shouldn't happen */
3702 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3716 fdi_reduce_ratio(u32
*num
, u32
*den
)
3718 while (*num
> 0xffffff || *den
> 0xffffff) {
3725 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
3726 int link_clock
, struct fdi_m_n
*m_n
)
3728 m_n
->tu
= 64; /* default size */
3730 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3731 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3732 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3733 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3735 m_n
->link_m
= pixel_clock
;
3736 m_n
->link_n
= link_clock
;
3737 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3740 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
3742 if (i915_panel_use_ssc
>= 0)
3743 return i915_panel_use_ssc
!= 0;
3744 return dev_priv
->lvds_use_ssc
3745 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
3749 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3750 * @crtc: CRTC structure
3751 * @mode: requested mode
3753 * A pipe may be connected to one or more outputs. Based on the depth of the
3754 * attached framebuffer, choose a good color depth to use on the pipe.
3756 * If possible, match the pipe depth to the fb depth. In some cases, this
3757 * isn't ideal, because the connected output supports a lesser or restricted
3758 * set of depths. Resolve that here:
3759 * LVDS typically supports only 6bpc, so clamp down in that case
3760 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3761 * Displays may support a restricted set as well, check EDID and clamp as
3763 * DP may want to dither down to 6bpc to fit larger modes
3766 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3767 * true if they don't match).
3769 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
3770 struct drm_framebuffer
*fb
,
3771 unsigned int *pipe_bpp
,
3772 struct drm_display_mode
*mode
)
3774 struct drm_device
*dev
= crtc
->dev
;
3775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3776 struct drm_connector
*connector
;
3777 struct intel_encoder
*intel_encoder
;
3778 unsigned int display_bpc
= UINT_MAX
, bpc
;
3780 /* Walk the encoders & connectors on this crtc, get min bpc */
3781 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
3783 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
3784 unsigned int lvds_bpc
;
3786 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
3792 if (lvds_bpc
< display_bpc
) {
3793 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
3794 display_bpc
= lvds_bpc
;
3799 /* Not one of the known troublemakers, check the EDID */
3800 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
3802 if (connector
->encoder
!= &intel_encoder
->base
)
3805 /* Don't use an invalid EDID bpc value */
3806 if (connector
->display_info
.bpc
&&
3807 connector
->display_info
.bpc
< display_bpc
) {
3808 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
3809 display_bpc
= connector
->display_info
.bpc
;
3814 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3815 * through, clamp it down. (Note: >12bpc will be caught below.)
3817 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
3818 if (display_bpc
> 8 && display_bpc
< 12) {
3819 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3822 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3828 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
3829 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3834 * We could just drive the pipe at the highest bpc all the time and
3835 * enable dithering as needed, but that costs bandwidth. So choose
3836 * the minimum value that expresses the full color range of the fb but
3837 * also stays within the max display bpc discovered above.
3840 switch (fb
->depth
) {
3842 bpc
= 8; /* since we go through a colormap */
3846 bpc
= 6; /* min is 18bpp */
3858 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3859 bpc
= min((unsigned int)8, display_bpc
);
3863 display_bpc
= min(display_bpc
, bpc
);
3865 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3868 *pipe_bpp
= display_bpc
* 3;
3870 return display_bpc
!= bpc
;
3873 static int vlv_get_refclk(struct drm_crtc
*crtc
)
3875 struct drm_device
*dev
= crtc
->dev
;
3876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3877 int refclk
= 27000; /* for DP & HDMI */
3879 return 100000; /* only one validated so far */
3881 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
3883 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3884 if (intel_panel_use_ssc(dev_priv
))
3888 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3895 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
3897 struct drm_device
*dev
= crtc
->dev
;
3898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3901 if (IS_VALLEYVIEW(dev
)) {
3902 refclk
= vlv_get_refclk(crtc
);
3903 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3904 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
3905 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3906 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3908 } else if (!IS_GEN2(dev
)) {
3917 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
3918 intel_clock_t
*clock
)
3920 /* SDVO TV has fixed PLL values depend on its clock range,
3921 this mirrors vbios setting. */
3922 if (adjusted_mode
->clock
>= 100000
3923 && adjusted_mode
->clock
< 140500) {
3929 } else if (adjusted_mode
->clock
>= 140500
3930 && adjusted_mode
->clock
<= 200000) {
3939 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
3940 intel_clock_t
*clock
,
3941 intel_clock_t
*reduced_clock
)
3943 struct drm_device
*dev
= crtc
->dev
;
3944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3945 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3946 int pipe
= intel_crtc
->pipe
;
3949 if (IS_PINEVIEW(dev
)) {
3950 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
3952 fp2
= (1 << reduced_clock
->n
) << 16 |
3953 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
3955 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
3957 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
3961 I915_WRITE(FP0(pipe
), fp
);
3963 intel_crtc
->lowfreq_avail
= false;
3964 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3965 reduced_clock
&& i915_powersave
) {
3966 I915_WRITE(FP1(pipe
), fp2
);
3967 intel_crtc
->lowfreq_avail
= true;
3969 I915_WRITE(FP1(pipe
), fp
);
3973 static void intel_update_lvds(struct drm_crtc
*crtc
, intel_clock_t
*clock
,
3974 struct drm_display_mode
*adjusted_mode
)
3976 struct drm_device
*dev
= crtc
->dev
;
3977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3978 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3979 int pipe
= intel_crtc
->pipe
;
3982 temp
= I915_READ(LVDS
);
3983 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
3985 temp
|= LVDS_PIPEB_SELECT
;
3987 temp
&= ~LVDS_PIPEB_SELECT
;
3989 /* set the corresponsding LVDS_BORDER bit */
3990 temp
|= dev_priv
->lvds_border_bits
;
3991 /* Set the B0-B3 data pairs corresponding to whether we're going to
3992 * set the DPLLs for dual-channel mode or not.
3995 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
3997 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
3999 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4000 * appropriately here, but we need to look more thoroughly into how
4001 * panels behave in the two modes.
4003 /* set the dithering flag on LVDS as needed */
4004 if (INTEL_INFO(dev
)->gen
>= 4) {
4005 if (dev_priv
->lvds_dither
)
4006 temp
|= LVDS_ENABLE_DITHER
;
4008 temp
&= ~LVDS_ENABLE_DITHER
;
4010 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
4011 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
4012 temp
|= LVDS_HSYNC_POLARITY
;
4013 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
4014 temp
|= LVDS_VSYNC_POLARITY
;
4015 I915_WRITE(LVDS
, temp
);
4018 static void vlv_update_pll(struct drm_crtc
*crtc
,
4019 struct drm_display_mode
*mode
,
4020 struct drm_display_mode
*adjusted_mode
,
4021 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4024 struct drm_device
*dev
= crtc
->dev
;
4025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4026 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4027 int pipe
= intel_crtc
->pipe
;
4028 u32 dpll
, mdiv
, pdiv
;
4029 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4033 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4034 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4036 dpll
= DPLL_VGA_MODE_DIS
;
4037 dpll
|= DPLL_EXT_BUFFER_ENABLE_VLV
;
4038 dpll
|= DPLL_REFA_CLK_ENABLE_VLV
;
4039 dpll
|= DPLL_INTEGRATED_CLOCK_VLV
;
4041 I915_WRITE(DPLL(pipe
), dpll
);
4042 POSTING_READ(DPLL(pipe
));
4051 * In Valleyview PLL and program lane counter registers are exposed
4052 * through DPIO interface
4054 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4055 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4056 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4057 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
4058 mdiv
|= (1 << DPIO_K_SHIFT
);
4059 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4060 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4062 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4064 pdiv
= (1 << DPIO_REFSEL_OVERRIDE
) | (5 << DPIO_PLL_MODESEL_SHIFT
) |
4065 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4066 (7 << DPIO_PLL_REFCLK_SEL_SHIFT
) | (8 << DPIO_DRIVER_CTL_SHIFT
) |
4067 (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4068 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4070 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x005f003b);
4072 dpll
|= DPLL_VCO_ENABLE
;
4073 I915_WRITE(DPLL(pipe
), dpll
);
4074 POSTING_READ(DPLL(pipe
));
4075 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4076 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4078 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x620);
4080 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4081 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4083 I915_WRITE(DPLL(pipe
), dpll
);
4085 /* Wait for the clocks to stabilize. */
4086 POSTING_READ(DPLL(pipe
));
4091 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4093 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4097 I915_WRITE(DPLL_MD(pipe
), temp
);
4098 POSTING_READ(DPLL_MD(pipe
));
4100 /* Now program lane control registers */
4101 if(intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)
4102 || intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
4107 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL1
, temp
);
4109 if(intel_pipe_has_type(crtc
,INTEL_OUTPUT_EDP
))
4114 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL2
, temp
);
4118 static void i9xx_update_pll(struct drm_crtc
*crtc
,
4119 struct drm_display_mode
*mode
,
4120 struct drm_display_mode
*adjusted_mode
,
4121 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4124 struct drm_device
*dev
= crtc
->dev
;
4125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4126 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4127 int pipe
= intel_crtc
->pipe
;
4131 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4133 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4134 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4136 dpll
= DPLL_VGA_MODE_DIS
;
4138 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4139 dpll
|= DPLLB_MODE_LVDS
;
4141 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4143 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4144 if (pixel_multiplier
> 1) {
4145 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4146 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4148 dpll
|= DPLL_DVO_HIGH_SPEED
;
4150 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4151 dpll
|= DPLL_DVO_HIGH_SPEED
;
4153 /* compute bitmask from p1 value */
4154 if (IS_PINEVIEW(dev
))
4155 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4157 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4158 if (IS_G4X(dev
) && reduced_clock
)
4159 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4161 switch (clock
->p2
) {
4163 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4166 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4169 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4172 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4175 if (INTEL_INFO(dev
)->gen
>= 4)
4176 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4178 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4179 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4180 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4181 /* XXX: just matching BIOS for now */
4182 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4184 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4185 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4186 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4188 dpll
|= PLL_REF_INPUT_DREFCLK
;
4190 dpll
|= DPLL_VCO_ENABLE
;
4191 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4192 POSTING_READ(DPLL(pipe
));
4195 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4196 * This is an exception to the general rule that mode_set doesn't turn
4199 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4200 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4202 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4203 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4205 I915_WRITE(DPLL(pipe
), dpll
);
4207 /* Wait for the clocks to stabilize. */
4208 POSTING_READ(DPLL(pipe
));
4211 if (INTEL_INFO(dev
)->gen
>= 4) {
4214 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4216 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4220 I915_WRITE(DPLL_MD(pipe
), temp
);
4222 /* The pixel multiplier can only be updated once the
4223 * DPLL is enabled and the clocks are stable.
4225 * So write it again.
4227 I915_WRITE(DPLL(pipe
), dpll
);
4231 static void i8xx_update_pll(struct drm_crtc
*crtc
,
4232 struct drm_display_mode
*adjusted_mode
,
4233 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4236 struct drm_device
*dev
= crtc
->dev
;
4237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4238 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4239 int pipe
= intel_crtc
->pipe
;
4242 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4244 dpll
= DPLL_VGA_MODE_DIS
;
4246 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4247 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4250 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4252 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4254 dpll
|= PLL_P2_DIVIDE_BY_4
;
4257 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4258 /* XXX: just matching BIOS for now */
4259 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4261 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4262 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4263 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4265 dpll
|= PLL_REF_INPUT_DREFCLK
;
4267 dpll
|= DPLL_VCO_ENABLE
;
4268 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4269 POSTING_READ(DPLL(pipe
));
4272 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4273 * This is an exception to the general rule that mode_set doesn't turn
4276 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4277 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4279 I915_WRITE(DPLL(pipe
), dpll
);
4281 /* Wait for the clocks to stabilize. */
4282 POSTING_READ(DPLL(pipe
));
4285 /* The pixel multiplier can only be updated once the
4286 * DPLL is enabled and the clocks are stable.
4288 * So write it again.
4290 I915_WRITE(DPLL(pipe
), dpll
);
4293 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4294 struct drm_display_mode
*mode
,
4295 struct drm_display_mode
*adjusted_mode
,
4297 struct drm_framebuffer
*fb
)
4299 struct drm_device
*dev
= crtc
->dev
;
4300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4301 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4302 int pipe
= intel_crtc
->pipe
;
4303 int plane
= intel_crtc
->plane
;
4304 int refclk
, num_connectors
= 0;
4305 intel_clock_t clock
, reduced_clock
;
4306 u32 dspcntr
, pipeconf
, vsyncshift
;
4307 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4308 bool is_lvds
= false, is_tv
= false, is_dp
= false;
4309 struct intel_encoder
*encoder
;
4310 const intel_limit_t
*limit
;
4313 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4314 switch (encoder
->type
) {
4315 case INTEL_OUTPUT_LVDS
:
4318 case INTEL_OUTPUT_SDVO
:
4319 case INTEL_OUTPUT_HDMI
:
4321 if (encoder
->needs_tv_clock
)
4324 case INTEL_OUTPUT_TVOUT
:
4327 case INTEL_OUTPUT_DISPLAYPORT
:
4335 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4338 * Returns a set of divisors for the desired target clock with the given
4339 * refclk, or FALSE. The returned values represent the clock equation:
4340 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4342 limit
= intel_limit(crtc
, refclk
);
4343 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4346 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4350 /* Ensure that the cursor is valid for the new mode before changing... */
4351 intel_crtc_update_cursor(crtc
, true);
4353 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4355 * Ensure we match the reduced clock's P to the target clock.
4356 * If the clocks don't match, we can't switch the display clock
4357 * by using the FP0/FP1. In such case we will disable the LVDS
4358 * downclock feature.
4360 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4361 dev_priv
->lvds_downclock
,
4367 if (is_sdvo
&& is_tv
)
4368 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4371 i8xx_update_pll(crtc
, adjusted_mode
, &clock
,
4372 has_reduced_clock
? &reduced_clock
: NULL
,
4374 else if (IS_VALLEYVIEW(dev
))
4375 vlv_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4376 has_reduced_clock
? &reduced_clock
: NULL
,
4379 i9xx_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4380 has_reduced_clock
? &reduced_clock
: NULL
,
4383 /* setup pipeconf */
4384 pipeconf
= I915_READ(PIPECONF(pipe
));
4386 /* Set up the display plane register */
4387 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4390 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4392 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4394 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4395 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4398 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4402 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4403 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4405 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4408 /* default to 8bpc */
4409 pipeconf
&= ~(PIPECONF_BPP_MASK
| PIPECONF_DITHER_EN
);
4411 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4412 pipeconf
|= PIPECONF_BPP_6
|
4413 PIPECONF_DITHER_EN
|
4414 PIPECONF_DITHER_TYPE_SP
;
4418 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4419 drm_mode_debug_printmodeline(mode
);
4421 if (HAS_PIPE_CXSR(dev
)) {
4422 if (intel_crtc
->lowfreq_avail
) {
4423 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4424 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4426 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4427 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4431 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4432 if (!IS_GEN2(dev
) &&
4433 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4434 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4435 /* the chip adds 2 halflines automatically */
4436 adjusted_mode
->crtc_vtotal
-= 1;
4437 adjusted_mode
->crtc_vblank_end
-= 1;
4438 vsyncshift
= adjusted_mode
->crtc_hsync_start
4439 - adjusted_mode
->crtc_htotal
/2;
4441 pipeconf
|= PIPECONF_PROGRESSIVE
;
4446 I915_WRITE(VSYNCSHIFT(pipe
), vsyncshift
);
4448 I915_WRITE(HTOTAL(pipe
),
4449 (adjusted_mode
->crtc_hdisplay
- 1) |
4450 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4451 I915_WRITE(HBLANK(pipe
),
4452 (adjusted_mode
->crtc_hblank_start
- 1) |
4453 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4454 I915_WRITE(HSYNC(pipe
),
4455 (adjusted_mode
->crtc_hsync_start
- 1) |
4456 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4458 I915_WRITE(VTOTAL(pipe
),
4459 (adjusted_mode
->crtc_vdisplay
- 1) |
4460 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4461 I915_WRITE(VBLANK(pipe
),
4462 (adjusted_mode
->crtc_vblank_start
- 1) |
4463 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4464 I915_WRITE(VSYNC(pipe
),
4465 (adjusted_mode
->crtc_vsync_start
- 1) |
4466 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4468 /* pipesrc and dspsize control the size that is scaled from,
4469 * which should always be the user's requested size.
4471 I915_WRITE(DSPSIZE(plane
),
4472 ((mode
->vdisplay
- 1) << 16) |
4473 (mode
->hdisplay
- 1));
4474 I915_WRITE(DSPPOS(plane
), 0);
4475 I915_WRITE(PIPESRC(pipe
),
4476 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4478 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4479 POSTING_READ(PIPECONF(pipe
));
4480 intel_enable_pipe(dev_priv
, pipe
, false);
4482 intel_wait_for_vblank(dev
, pipe
);
4484 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4485 POSTING_READ(DSPCNTR(plane
));
4487 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4489 intel_update_watermarks(dev
);
4495 * Initialize reference clocks when the driver loads
4497 void ironlake_init_pch_refclk(struct drm_device
*dev
)
4499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4500 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4501 struct intel_encoder
*encoder
;
4503 bool has_lvds
= false;
4504 bool has_cpu_edp
= false;
4505 bool has_pch_edp
= false;
4506 bool has_panel
= false;
4507 bool has_ck505
= false;
4508 bool can_ssc
= false;
4510 /* We need to take the global config into account */
4511 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4513 switch (encoder
->type
) {
4514 case INTEL_OUTPUT_LVDS
:
4518 case INTEL_OUTPUT_EDP
:
4520 if (intel_encoder_is_pch_edp(&encoder
->base
))
4528 if (HAS_PCH_IBX(dev
)) {
4529 has_ck505
= dev_priv
->display_clock_mode
;
4530 can_ssc
= has_ck505
;
4536 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4537 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4540 /* Ironlake: try to setup display ref clock before DPLL
4541 * enabling. This is only under driver's control after
4542 * PCH B stepping, previous chipset stepping should be
4543 * ignoring this setting.
4545 temp
= I915_READ(PCH_DREF_CONTROL
);
4546 /* Always enable nonspread source */
4547 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4550 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
4552 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4555 temp
&= ~DREF_SSC_SOURCE_MASK
;
4556 temp
|= DREF_SSC_SOURCE_ENABLE
;
4558 /* SSC must be turned on before enabling the CPU output */
4559 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4560 DRM_DEBUG_KMS("Using SSC on panel\n");
4561 temp
|= DREF_SSC1_ENABLE
;
4563 temp
&= ~DREF_SSC1_ENABLE
;
4565 /* Get SSC going before enabling the outputs */
4566 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4567 POSTING_READ(PCH_DREF_CONTROL
);
4570 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4572 /* Enable CPU source on CPU attached eDP */
4574 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4575 DRM_DEBUG_KMS("Using SSC on eDP\n");
4576 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4579 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4581 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4583 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4584 POSTING_READ(PCH_DREF_CONTROL
);
4587 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4589 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4591 /* Turn off CPU output */
4592 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4594 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4595 POSTING_READ(PCH_DREF_CONTROL
);
4598 /* Turn off the SSC source */
4599 temp
&= ~DREF_SSC_SOURCE_MASK
;
4600 temp
|= DREF_SSC_SOURCE_DISABLE
;
4603 temp
&= ~ DREF_SSC1_ENABLE
;
4605 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4606 POSTING_READ(PCH_DREF_CONTROL
);
4611 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
4613 struct drm_device
*dev
= crtc
->dev
;
4614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4615 struct intel_encoder
*encoder
;
4616 struct intel_encoder
*edp_encoder
= NULL
;
4617 int num_connectors
= 0;
4618 bool is_lvds
= false;
4620 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4621 switch (encoder
->type
) {
4622 case INTEL_OUTPUT_LVDS
:
4625 case INTEL_OUTPUT_EDP
:
4626 edp_encoder
= encoder
;
4632 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4633 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4634 dev_priv
->lvds_ssc_freq
);
4635 return dev_priv
->lvds_ssc_freq
* 1000;
4641 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
,
4642 struct drm_display_mode
*adjusted_mode
,
4645 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
4646 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4647 int pipe
= intel_crtc
->pipe
;
4650 val
= I915_READ(PIPECONF(pipe
));
4652 val
&= ~PIPE_BPC_MASK
;
4653 switch (intel_crtc
->bpp
) {
4667 /* Case prevented by intel_choose_pipe_bpp_dither. */
4671 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
4673 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
4675 val
&= ~PIPECONF_INTERLACE_MASK
;
4676 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
4677 val
|= PIPECONF_INTERLACED_ILK
;
4679 val
|= PIPECONF_PROGRESSIVE
;
4681 I915_WRITE(PIPECONF(pipe
), val
);
4682 POSTING_READ(PIPECONF(pipe
));
4685 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
4686 struct drm_display_mode
*adjusted_mode
,
4687 intel_clock_t
*clock
,
4688 bool *has_reduced_clock
,
4689 intel_clock_t
*reduced_clock
)
4691 struct drm_device
*dev
= crtc
->dev
;
4692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4693 struct intel_encoder
*intel_encoder
;
4695 const intel_limit_t
*limit
;
4696 bool ret
, is_sdvo
= false, is_tv
= false, is_lvds
= false;
4698 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4699 switch (intel_encoder
->type
) {
4700 case INTEL_OUTPUT_LVDS
:
4703 case INTEL_OUTPUT_SDVO
:
4704 case INTEL_OUTPUT_HDMI
:
4706 if (intel_encoder
->needs_tv_clock
)
4709 case INTEL_OUTPUT_TVOUT
:
4715 refclk
= ironlake_get_refclk(crtc
);
4718 * Returns a set of divisors for the desired target clock with the given
4719 * refclk, or FALSE. The returned values represent the clock equation:
4720 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4722 limit
= intel_limit(crtc
, refclk
);
4723 ret
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4728 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4730 * Ensure we match the reduced clock's P to the target clock.
4731 * If the clocks don't match, we can't switch the display clock
4732 * by using the FP0/FP1. In such case we will disable the LVDS
4733 * downclock feature.
4735 *has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4736 dev_priv
->lvds_downclock
,
4742 if (is_sdvo
&& is_tv
)
4743 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, clock
);
4748 static void ironlake_set_m_n(struct drm_crtc
*crtc
,
4749 struct drm_display_mode
*mode
,
4750 struct drm_display_mode
*adjusted_mode
)
4752 struct drm_device
*dev
= crtc
->dev
;
4753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4754 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4755 enum pipe pipe
= intel_crtc
->pipe
;
4756 struct intel_encoder
*intel_encoder
, *edp_encoder
= NULL
;
4757 struct fdi_m_n m_n
= {0};
4758 int target_clock
, pixel_multiplier
, lane
, link_bw
;
4759 bool is_dp
= false, is_cpu_edp
= false;
4761 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4762 switch (intel_encoder
->type
) {
4763 case INTEL_OUTPUT_DISPLAYPORT
:
4766 case INTEL_OUTPUT_EDP
:
4768 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
4770 edp_encoder
= intel_encoder
;
4776 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4778 /* CPU eDP doesn't require FDI link, so just set DP M/N
4779 according to current link config */
4781 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
4783 /* FDI is a binary signal running at ~2.7GHz, encoding
4784 * each output octet as 10 bits. The actual frequency
4785 * is stored as a divider into a 100MHz clock, and the
4786 * mode pixel clock is stored in units of 1KHz.
4787 * Hence the bw of each lane in terms of the mode signal
4790 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4793 /* [e]DP over FDI requires target mode clock instead of link clock. */
4795 target_clock
= intel_edp_target_clock(edp_encoder
, mode
);
4797 target_clock
= mode
->clock
;
4799 target_clock
= adjusted_mode
->clock
;
4803 * Account for spread spectrum to avoid
4804 * oversubscribing the link. Max center spread
4805 * is 2.5%; use 5% for safety's sake.
4807 u32 bps
= target_clock
* intel_crtc
->bpp
* 21 / 20;
4808 lane
= bps
/ (link_bw
* 8) + 1;
4811 intel_crtc
->fdi_lanes
= lane
;
4813 if (pixel_multiplier
> 1)
4814 link_bw
*= pixel_multiplier
;
4815 ironlake_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
,
4818 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
4819 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
4820 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
4821 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
4824 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
4825 struct drm_display_mode
*adjusted_mode
,
4826 intel_clock_t
*clock
, u32 fp
)
4828 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4829 struct drm_device
*dev
= crtc
->dev
;
4830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4831 struct intel_encoder
*intel_encoder
;
4833 int factor
, pixel_multiplier
, num_connectors
= 0;
4834 bool is_lvds
= false, is_sdvo
= false, is_tv
= false;
4835 bool is_dp
= false, is_cpu_edp
= false;
4837 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4838 switch (intel_encoder
->type
) {
4839 case INTEL_OUTPUT_LVDS
:
4842 case INTEL_OUTPUT_SDVO
:
4843 case INTEL_OUTPUT_HDMI
:
4845 if (intel_encoder
->needs_tv_clock
)
4848 case INTEL_OUTPUT_TVOUT
:
4851 case INTEL_OUTPUT_DISPLAYPORT
:
4854 case INTEL_OUTPUT_EDP
:
4856 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
4864 /* Enable autotuning of the PLL clock (if permissible) */
4867 if ((intel_panel_use_ssc(dev_priv
) &&
4868 dev_priv
->lvds_ssc_freq
== 100) ||
4869 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
4871 } else if (is_sdvo
&& is_tv
)
4874 if (clock
->m
< factor
* clock
->n
)
4880 dpll
|= DPLLB_MODE_LVDS
;
4882 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4884 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4885 if (pixel_multiplier
> 1) {
4886 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
4888 dpll
|= DPLL_DVO_HIGH_SPEED
;
4890 if (is_dp
&& !is_cpu_edp
)
4891 dpll
|= DPLL_DVO_HIGH_SPEED
;
4893 /* compute bitmask from p1 value */
4894 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4896 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4898 switch (clock
->p2
) {
4900 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4903 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4906 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4909 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4913 if (is_sdvo
&& is_tv
)
4914 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4916 /* XXX: just matching BIOS for now */
4917 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4919 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4920 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4922 dpll
|= PLL_REF_INPUT_DREFCLK
;
4927 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
4928 struct drm_display_mode
*mode
,
4929 struct drm_display_mode
*adjusted_mode
,
4931 struct drm_framebuffer
*fb
)
4933 struct drm_device
*dev
= crtc
->dev
;
4934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4935 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4936 int pipe
= intel_crtc
->pipe
;
4937 int plane
= intel_crtc
->plane
;
4938 int num_connectors
= 0;
4939 intel_clock_t clock
, reduced_clock
;
4940 u32 dpll
, fp
= 0, fp2
= 0;
4941 bool ok
, has_reduced_clock
= false;
4942 bool is_lvds
= false, is_dp
= false, is_cpu_edp
= false;
4943 struct intel_encoder
*encoder
;
4948 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4949 switch (encoder
->type
) {
4950 case INTEL_OUTPUT_LVDS
:
4953 case INTEL_OUTPUT_DISPLAYPORT
:
4956 case INTEL_OUTPUT_EDP
:
4958 if (!intel_encoder_is_pch_edp(&encoder
->base
))
4966 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
4967 &has_reduced_clock
, &reduced_clock
);
4969 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4973 /* Ensure that the cursor is valid for the new mode before changing... */
4974 intel_crtc_update_cursor(crtc
, true);
4976 /* determine panel color depth */
4977 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &intel_crtc
->bpp
, mode
);
4978 if (is_lvds
&& dev_priv
->lvds_dither
)
4981 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
4982 if (has_reduced_clock
)
4983 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
4986 dpll
= ironlake_compute_dpll(intel_crtc
, adjusted_mode
, &clock
, fp
);
4988 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
4989 drm_mode_debug_printmodeline(mode
);
4991 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4992 * pre-Haswell/LPT generation */
4993 if (HAS_PCH_LPT(dev
)) {
4994 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4996 } else if (!is_cpu_edp
) {
4997 struct intel_pch_pll
*pll
;
4999 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5001 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5006 intel_put_pch_pll(intel_crtc
);
5008 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5009 * This is an exception to the general rule that mode_set doesn't turn
5013 temp
= I915_READ(PCH_LVDS
);
5014 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
5015 if (HAS_PCH_CPT(dev
)) {
5016 temp
&= ~PORT_TRANS_SEL_MASK
;
5017 temp
|= PORT_TRANS_SEL_CPT(pipe
);
5020 temp
|= LVDS_PIPEB_SELECT
;
5022 temp
&= ~LVDS_PIPEB_SELECT
;
5025 /* set the corresponsding LVDS_BORDER bit */
5026 temp
|= dev_priv
->lvds_border_bits
;
5027 /* Set the B0-B3 data pairs corresponding to whether we're going to
5028 * set the DPLLs for dual-channel mode or not.
5031 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
5033 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
5035 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5036 * appropriately here, but we need to look more thoroughly into how
5037 * panels behave in the two modes.
5039 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
5040 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
5041 temp
|= LVDS_HSYNC_POLARITY
;
5042 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
5043 temp
|= LVDS_VSYNC_POLARITY
;
5044 I915_WRITE(PCH_LVDS
, temp
);
5047 if (is_dp
&& !is_cpu_edp
) {
5048 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5050 /* For non-DP output, clear any trans DP clock recovery setting.*/
5051 I915_WRITE(TRANSDATA_M1(pipe
), 0);
5052 I915_WRITE(TRANSDATA_N1(pipe
), 0);
5053 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
5054 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
5057 if (intel_crtc
->pch_pll
) {
5058 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5060 /* Wait for the clocks to stabilize. */
5061 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5064 /* The pixel multiplier can only be updated once the
5065 * DPLL is enabled and the clocks are stable.
5067 * So write it again.
5069 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5072 intel_crtc
->lowfreq_avail
= false;
5073 if (intel_crtc
->pch_pll
) {
5074 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5075 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5076 intel_crtc
->lowfreq_avail
= true;
5078 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5082 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5083 /* the chip adds 2 halflines automatically */
5084 adjusted_mode
->crtc_vtotal
-= 1;
5085 adjusted_mode
->crtc_vblank_end
-= 1;
5086 I915_WRITE(VSYNCSHIFT(pipe
),
5087 adjusted_mode
->crtc_hsync_start
5088 - adjusted_mode
->crtc_htotal
/2);
5090 I915_WRITE(VSYNCSHIFT(pipe
), 0);
5093 I915_WRITE(HTOTAL(pipe
),
5094 (adjusted_mode
->crtc_hdisplay
- 1) |
5095 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5096 I915_WRITE(HBLANK(pipe
),
5097 (adjusted_mode
->crtc_hblank_start
- 1) |
5098 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5099 I915_WRITE(HSYNC(pipe
),
5100 (adjusted_mode
->crtc_hsync_start
- 1) |
5101 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5103 I915_WRITE(VTOTAL(pipe
),
5104 (adjusted_mode
->crtc_vdisplay
- 1) |
5105 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
5106 I915_WRITE(VBLANK(pipe
),
5107 (adjusted_mode
->crtc_vblank_start
- 1) |
5108 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
5109 I915_WRITE(VSYNC(pipe
),
5110 (adjusted_mode
->crtc_vsync_start
- 1) |
5111 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5113 /* pipesrc controls the size that is scaled from, which should
5114 * always be the user's requested size.
5116 I915_WRITE(PIPESRC(pipe
),
5117 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
5119 ironlake_set_m_n(crtc
, mode
, adjusted_mode
);
5122 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
5124 ironlake_set_pipeconf(crtc
, adjusted_mode
, dither
);
5126 intel_wait_for_vblank(dev
, pipe
);
5128 /* Set up the display plane register */
5129 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5130 POSTING_READ(DSPCNTR(plane
));
5132 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5134 intel_update_watermarks(dev
);
5136 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5141 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5142 struct drm_display_mode
*mode
,
5143 struct drm_display_mode
*adjusted_mode
,
5145 struct drm_framebuffer
*fb
)
5147 struct drm_device
*dev
= crtc
->dev
;
5148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5149 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5150 int pipe
= intel_crtc
->pipe
;
5153 drm_vblank_pre_modeset(dev
, pipe
);
5155 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
5157 drm_vblank_post_modeset(dev
, pipe
);
5162 static bool intel_eld_uptodate(struct drm_connector
*connector
,
5163 int reg_eldv
, uint32_t bits_eldv
,
5164 int reg_elda
, uint32_t bits_elda
,
5167 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5168 uint8_t *eld
= connector
->eld
;
5171 i
= I915_READ(reg_eldv
);
5180 i
= I915_READ(reg_elda
);
5182 I915_WRITE(reg_elda
, i
);
5184 for (i
= 0; i
< eld
[2]; i
++)
5185 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5191 static void g4x_write_eld(struct drm_connector
*connector
,
5192 struct drm_crtc
*crtc
)
5194 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5195 uint8_t *eld
= connector
->eld
;
5200 i
= I915_READ(G4X_AUD_VID_DID
);
5202 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5203 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5205 eldv
= G4X_ELDV_DEVCTG
;
5207 if (intel_eld_uptodate(connector
,
5208 G4X_AUD_CNTL_ST
, eldv
,
5209 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5210 G4X_HDMIW_HDMIEDID
))
5213 i
= I915_READ(G4X_AUD_CNTL_ST
);
5214 i
&= ~(eldv
| G4X_ELD_ADDR
);
5215 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5216 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5221 len
= min_t(uint8_t, eld
[2], len
);
5222 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5223 for (i
= 0; i
< len
; i
++)
5224 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5226 i
= I915_READ(G4X_AUD_CNTL_ST
);
5228 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5231 static void haswell_write_eld(struct drm_connector
*connector
,
5232 struct drm_crtc
*crtc
)
5234 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5235 uint8_t *eld
= connector
->eld
;
5236 struct drm_device
*dev
= crtc
->dev
;
5240 int pipe
= to_intel_crtc(crtc
)->pipe
;
5243 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
5244 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
5245 int aud_config
= HSW_AUD_CFG(pipe
);
5246 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
5249 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5251 /* Audio output enable */
5252 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5253 tmp
= I915_READ(aud_cntrl_st2
);
5254 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
5255 I915_WRITE(aud_cntrl_st2
, tmp
);
5257 /* Wait for 1 vertical blank */
5258 intel_wait_for_vblank(dev
, pipe
);
5260 /* Set ELD valid state */
5261 tmp
= I915_READ(aud_cntrl_st2
);
5262 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
5263 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
5264 I915_WRITE(aud_cntrl_st2
, tmp
);
5265 tmp
= I915_READ(aud_cntrl_st2
);
5266 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
5268 /* Enable HDMI mode */
5269 tmp
= I915_READ(aud_config
);
5270 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
5271 /* clear N_programing_enable and N_value_index */
5272 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
5273 I915_WRITE(aud_config
, tmp
);
5275 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5277 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
5279 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5280 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5281 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5282 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5284 I915_WRITE(aud_config
, 0);
5286 if (intel_eld_uptodate(connector
,
5287 aud_cntrl_st2
, eldv
,
5288 aud_cntl_st
, IBX_ELD_ADDRESS
,
5292 i
= I915_READ(aud_cntrl_st2
);
5294 I915_WRITE(aud_cntrl_st2
, i
);
5299 i
= I915_READ(aud_cntl_st
);
5300 i
&= ~IBX_ELD_ADDRESS
;
5301 I915_WRITE(aud_cntl_st
, i
);
5302 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
5303 DRM_DEBUG_DRIVER("port num:%d\n", i
);
5305 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5306 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5307 for (i
= 0; i
< len
; i
++)
5308 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5310 i
= I915_READ(aud_cntrl_st2
);
5312 I915_WRITE(aud_cntrl_st2
, i
);
5316 static void ironlake_write_eld(struct drm_connector
*connector
,
5317 struct drm_crtc
*crtc
)
5319 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5320 uint8_t *eld
= connector
->eld
;
5328 int pipe
= to_intel_crtc(crtc
)->pipe
;
5330 if (HAS_PCH_IBX(connector
->dev
)) {
5331 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
5332 aud_config
= IBX_AUD_CFG(pipe
);
5333 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
5334 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
5336 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
5337 aud_config
= CPT_AUD_CFG(pipe
);
5338 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
5339 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
5342 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5344 i
= I915_READ(aud_cntl_st
);
5345 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
5347 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5348 /* operate blindly on all ports */
5349 eldv
= IBX_ELD_VALIDB
;
5350 eldv
|= IBX_ELD_VALIDB
<< 4;
5351 eldv
|= IBX_ELD_VALIDB
<< 8;
5353 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
5354 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
5357 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5358 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5359 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5360 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5362 I915_WRITE(aud_config
, 0);
5364 if (intel_eld_uptodate(connector
,
5365 aud_cntrl_st2
, eldv
,
5366 aud_cntl_st
, IBX_ELD_ADDRESS
,
5370 i
= I915_READ(aud_cntrl_st2
);
5372 I915_WRITE(aud_cntrl_st2
, i
);
5377 i
= I915_READ(aud_cntl_st
);
5378 i
&= ~IBX_ELD_ADDRESS
;
5379 I915_WRITE(aud_cntl_st
, i
);
5381 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5382 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5383 for (i
= 0; i
< len
; i
++)
5384 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5386 i
= I915_READ(aud_cntrl_st2
);
5388 I915_WRITE(aud_cntrl_st2
, i
);
5391 void intel_write_eld(struct drm_encoder
*encoder
,
5392 struct drm_display_mode
*mode
)
5394 struct drm_crtc
*crtc
= encoder
->crtc
;
5395 struct drm_connector
*connector
;
5396 struct drm_device
*dev
= encoder
->dev
;
5397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5399 connector
= drm_select_eld(encoder
, mode
);
5403 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5405 drm_get_connector_name(connector
),
5406 connector
->encoder
->base
.id
,
5407 drm_get_encoder_name(connector
->encoder
));
5409 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
5411 if (dev_priv
->display
.write_eld
)
5412 dev_priv
->display
.write_eld(connector
, crtc
);
5415 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5416 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
5418 struct drm_device
*dev
= crtc
->dev
;
5419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5420 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5421 int palreg
= PALETTE(intel_crtc
->pipe
);
5424 /* The clocks have to be on to load the palette. */
5425 if (!crtc
->enabled
|| !intel_crtc
->active
)
5428 /* use legacy palette for Ironlake */
5429 if (HAS_PCH_SPLIT(dev
))
5430 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
5432 for (i
= 0; i
< 256; i
++) {
5433 I915_WRITE(palreg
+ 4 * i
,
5434 (intel_crtc
->lut_r
[i
] << 16) |
5435 (intel_crtc
->lut_g
[i
] << 8) |
5436 intel_crtc
->lut_b
[i
]);
5440 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5442 struct drm_device
*dev
= crtc
->dev
;
5443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5444 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5445 bool visible
= base
!= 0;
5448 if (intel_crtc
->cursor_visible
== visible
)
5451 cntl
= I915_READ(_CURACNTR
);
5453 /* On these chipsets we can only modify the base whilst
5454 * the cursor is disabled.
5456 I915_WRITE(_CURABASE
, base
);
5458 cntl
&= ~(CURSOR_FORMAT_MASK
);
5459 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5460 cntl
|= CURSOR_ENABLE
|
5461 CURSOR_GAMMA_ENABLE
|
5464 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
5465 I915_WRITE(_CURACNTR
, cntl
);
5467 intel_crtc
->cursor_visible
= visible
;
5470 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5472 struct drm_device
*dev
= crtc
->dev
;
5473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5474 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5475 int pipe
= intel_crtc
->pipe
;
5476 bool visible
= base
!= 0;
5478 if (intel_crtc
->cursor_visible
!= visible
) {
5479 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
5481 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
5482 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5483 cntl
|= pipe
<< 28; /* Connect to correct pipe */
5485 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5486 cntl
|= CURSOR_MODE_DISABLE
;
5488 I915_WRITE(CURCNTR(pipe
), cntl
);
5490 intel_crtc
->cursor_visible
= visible
;
5492 /* and commit changes on next vblank */
5493 I915_WRITE(CURBASE(pipe
), base
);
5496 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5498 struct drm_device
*dev
= crtc
->dev
;
5499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5500 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5501 int pipe
= intel_crtc
->pipe
;
5502 bool visible
= base
!= 0;
5504 if (intel_crtc
->cursor_visible
!= visible
) {
5505 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
5507 cntl
&= ~CURSOR_MODE
;
5508 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5510 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5511 cntl
|= CURSOR_MODE_DISABLE
;
5513 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
5515 intel_crtc
->cursor_visible
= visible
;
5517 /* and commit changes on next vblank */
5518 I915_WRITE(CURBASE_IVB(pipe
), base
);
5521 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5522 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
5525 struct drm_device
*dev
= crtc
->dev
;
5526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5527 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5528 int pipe
= intel_crtc
->pipe
;
5529 int x
= intel_crtc
->cursor_x
;
5530 int y
= intel_crtc
->cursor_y
;
5536 if (on
&& crtc
->enabled
&& crtc
->fb
) {
5537 base
= intel_crtc
->cursor_addr
;
5538 if (x
> (int) crtc
->fb
->width
)
5541 if (y
> (int) crtc
->fb
->height
)
5547 if (x
+ intel_crtc
->cursor_width
< 0)
5550 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
5553 pos
|= x
<< CURSOR_X_SHIFT
;
5556 if (y
+ intel_crtc
->cursor_height
< 0)
5559 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
5562 pos
|= y
<< CURSOR_Y_SHIFT
;
5564 visible
= base
!= 0;
5565 if (!visible
&& !intel_crtc
->cursor_visible
)
5568 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
5569 I915_WRITE(CURPOS_IVB(pipe
), pos
);
5570 ivb_update_cursor(crtc
, base
);
5572 I915_WRITE(CURPOS(pipe
), pos
);
5573 if (IS_845G(dev
) || IS_I865G(dev
))
5574 i845_update_cursor(crtc
, base
);
5576 i9xx_update_cursor(crtc
, base
);
5580 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
5581 struct drm_file
*file
,
5583 uint32_t width
, uint32_t height
)
5585 struct drm_device
*dev
= crtc
->dev
;
5586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5587 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5588 struct drm_i915_gem_object
*obj
;
5592 /* if we want to turn off the cursor ignore width and height */
5594 DRM_DEBUG_KMS("cursor off\n");
5597 mutex_lock(&dev
->struct_mutex
);
5601 /* Currently we only support 64x64 cursors */
5602 if (width
!= 64 || height
!= 64) {
5603 DRM_ERROR("we currently only support 64x64 cursors\n");
5607 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
5608 if (&obj
->base
== NULL
)
5611 if (obj
->base
.size
< width
* height
* 4) {
5612 DRM_ERROR("buffer is to small\n");
5617 /* we only need to pin inside GTT if cursor is non-phy */
5618 mutex_lock(&dev
->struct_mutex
);
5619 if (!dev_priv
->info
->cursor_needs_physical
) {
5620 if (obj
->tiling_mode
) {
5621 DRM_ERROR("cursor cannot be tiled\n");
5626 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
5628 DRM_ERROR("failed to move cursor bo into the GTT\n");
5632 ret
= i915_gem_object_put_fence(obj
);
5634 DRM_ERROR("failed to release fence for cursor");
5638 addr
= obj
->gtt_offset
;
5640 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
5641 ret
= i915_gem_attach_phys_object(dev
, obj
,
5642 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
5645 DRM_ERROR("failed to attach phys object\n");
5648 addr
= obj
->phys_obj
->handle
->busaddr
;
5652 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
5655 if (intel_crtc
->cursor_bo
) {
5656 if (dev_priv
->info
->cursor_needs_physical
) {
5657 if (intel_crtc
->cursor_bo
!= obj
)
5658 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
5660 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
5661 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
5664 mutex_unlock(&dev
->struct_mutex
);
5666 intel_crtc
->cursor_addr
= addr
;
5667 intel_crtc
->cursor_bo
= obj
;
5668 intel_crtc
->cursor_width
= width
;
5669 intel_crtc
->cursor_height
= height
;
5671 intel_crtc_update_cursor(crtc
, true);
5675 i915_gem_object_unpin(obj
);
5677 mutex_unlock(&dev
->struct_mutex
);
5679 drm_gem_object_unreference_unlocked(&obj
->base
);
5683 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
5685 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5687 intel_crtc
->cursor_x
= x
;
5688 intel_crtc
->cursor_y
= y
;
5690 intel_crtc_update_cursor(crtc
, true);
5695 /** Sets the color ramps on behalf of RandR */
5696 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
5697 u16 blue
, int regno
)
5699 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5701 intel_crtc
->lut_r
[regno
] = red
>> 8;
5702 intel_crtc
->lut_g
[regno
] = green
>> 8;
5703 intel_crtc
->lut_b
[regno
] = blue
>> 8;
5706 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5707 u16
*blue
, int regno
)
5709 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5711 *red
= intel_crtc
->lut_r
[regno
] << 8;
5712 *green
= intel_crtc
->lut_g
[regno
] << 8;
5713 *blue
= intel_crtc
->lut_b
[regno
] << 8;
5716 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5717 u16
*blue
, uint32_t start
, uint32_t size
)
5719 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
5720 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5722 for (i
= start
; i
< end
; i
++) {
5723 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
5724 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
5725 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
5728 intel_crtc_load_lut(crtc
);
5732 * Get a pipe with a simple mode set on it for doing load-based monitor
5735 * It will be up to the load-detect code to adjust the pipe as appropriate for
5736 * its requirements. The pipe will be connected to no other encoders.
5738 * Currently this code will only succeed if there is a pipe with no encoders
5739 * configured for it. In the future, it could choose to temporarily disable
5740 * some outputs to free up a pipe for its use.
5742 * \return crtc, or NULL if no pipes are available.
5745 /* VESA 640x480x72Hz mode to set on the pipe */
5746 static struct drm_display_mode load_detect_mode
= {
5747 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
5748 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
5751 static struct drm_framebuffer
*
5752 intel_framebuffer_create(struct drm_device
*dev
,
5753 struct drm_mode_fb_cmd2
*mode_cmd
,
5754 struct drm_i915_gem_object
*obj
)
5756 struct intel_framebuffer
*intel_fb
;
5759 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
5761 drm_gem_object_unreference_unlocked(&obj
->base
);
5762 return ERR_PTR(-ENOMEM
);
5765 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
5767 drm_gem_object_unreference_unlocked(&obj
->base
);
5769 return ERR_PTR(ret
);
5772 return &intel_fb
->base
;
5776 intel_framebuffer_pitch_for_width(int width
, int bpp
)
5778 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
5779 return ALIGN(pitch
, 64);
5783 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
5785 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
5786 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
5789 static struct drm_framebuffer
*
5790 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
5791 struct drm_display_mode
*mode
,
5794 struct drm_i915_gem_object
*obj
;
5795 struct drm_mode_fb_cmd2 mode_cmd
;
5797 obj
= i915_gem_alloc_object(dev
,
5798 intel_framebuffer_size_for_mode(mode
, bpp
));
5800 return ERR_PTR(-ENOMEM
);
5802 mode_cmd
.width
= mode
->hdisplay
;
5803 mode_cmd
.height
= mode
->vdisplay
;
5804 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
5806 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
5808 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
5811 static struct drm_framebuffer
*
5812 mode_fits_in_fbdev(struct drm_device
*dev
,
5813 struct drm_display_mode
*mode
)
5815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5816 struct drm_i915_gem_object
*obj
;
5817 struct drm_framebuffer
*fb
;
5819 if (dev_priv
->fbdev
== NULL
)
5822 obj
= dev_priv
->fbdev
->ifb
.obj
;
5826 fb
= &dev_priv
->fbdev
->ifb
.base
;
5827 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
5828 fb
->bits_per_pixel
))
5831 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
5837 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
5838 struct drm_display_mode
*mode
,
5839 struct intel_load_detect_pipe
*old
)
5841 struct intel_crtc
*intel_crtc
;
5842 struct intel_encoder
*intel_encoder
=
5843 intel_attached_encoder(connector
);
5844 struct drm_crtc
*possible_crtc
;
5845 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5846 struct drm_crtc
*crtc
= NULL
;
5847 struct drm_device
*dev
= encoder
->dev
;
5848 struct drm_framebuffer
*fb
;
5851 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5852 connector
->base
.id
, drm_get_connector_name(connector
),
5853 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5856 * Algorithm gets a little messy:
5858 * - if the connector already has an assigned crtc, use it (but make
5859 * sure it's on first)
5861 * - try to find the first unused crtc that can drive this connector,
5862 * and use that if we find one
5865 /* See if we already have a CRTC for this connector */
5866 if (encoder
->crtc
) {
5867 crtc
= encoder
->crtc
;
5869 old
->dpms_mode
= connector
->dpms
;
5870 old
->load_detect_temp
= false;
5872 /* Make sure the crtc and connector are running */
5873 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
5874 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
5879 /* Find an unused one (if possible) */
5880 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
5882 if (!(encoder
->possible_crtcs
& (1 << i
)))
5884 if (!possible_crtc
->enabled
) {
5885 crtc
= possible_crtc
;
5891 * If we didn't find an unused CRTC, don't use any.
5894 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5898 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
5899 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
5901 intel_crtc
= to_intel_crtc(crtc
);
5902 old
->dpms_mode
= connector
->dpms
;
5903 old
->load_detect_temp
= true;
5904 old
->release_fb
= NULL
;
5907 mode
= &load_detect_mode
;
5909 /* We need a framebuffer large enough to accommodate all accesses
5910 * that the plane may generate whilst we perform load detection.
5911 * We can not rely on the fbcon either being present (we get called
5912 * during its initialisation to detect all boot displays, or it may
5913 * not even exist) or that it is large enough to satisfy the
5916 fb
= mode_fits_in_fbdev(dev
, mode
);
5918 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5919 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
5920 old
->release_fb
= fb
;
5922 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5924 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5928 if (!intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
5929 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5930 if (old
->release_fb
)
5931 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5935 /* let the connector get through one full cycle before testing */
5936 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
5940 connector
->encoder
= NULL
;
5941 encoder
->crtc
= NULL
;
5945 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
5946 struct intel_load_detect_pipe
*old
)
5948 struct intel_encoder
*intel_encoder
=
5949 intel_attached_encoder(connector
);
5950 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5952 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5953 connector
->base
.id
, drm_get_connector_name(connector
),
5954 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5956 if (old
->load_detect_temp
) {
5957 struct drm_crtc
*crtc
= encoder
->crtc
;
5959 to_intel_connector(connector
)->new_encoder
= NULL
;
5960 intel_encoder
->new_crtc
= NULL
;
5961 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
5963 if (old
->release_fb
)
5964 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5969 /* Switch crtc and encoder back off if necessary */
5970 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
5971 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
5974 /* Returns the clock of the currently programmed mode of the given pipe. */
5975 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
5977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5978 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5979 int pipe
= intel_crtc
->pipe
;
5980 u32 dpll
= I915_READ(DPLL(pipe
));
5982 intel_clock_t clock
;
5984 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
5985 fp
= I915_READ(FP0(pipe
));
5987 fp
= I915_READ(FP1(pipe
));
5989 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
5990 if (IS_PINEVIEW(dev
)) {
5991 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
5992 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5994 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
5995 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5998 if (!IS_GEN2(dev
)) {
5999 if (IS_PINEVIEW(dev
))
6000 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6001 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6003 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6004 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6006 switch (dpll
& DPLL_MODE_MASK
) {
6007 case DPLLB_MODE_DAC_SERIAL
:
6008 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6011 case DPLLB_MODE_LVDS
:
6012 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6016 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6017 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6021 /* XXX: Handle the 100Mhz refclk */
6022 intel_clock(dev
, 96000, &clock
);
6024 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6027 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6028 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6031 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6032 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6033 /* XXX: might not be 66MHz */
6034 intel_clock(dev
, 66000, &clock
);
6036 intel_clock(dev
, 48000, &clock
);
6038 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6041 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6042 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6044 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6049 intel_clock(dev
, 48000, &clock
);
6053 /* XXX: It would be nice to validate the clocks, but we can't reuse
6054 * i830PllIsValid() because it relies on the xf86_config connector
6055 * configuration being accurate, which it isn't necessarily.
6061 /** Returns the currently programmed mode of the given pipe. */
6062 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6063 struct drm_crtc
*crtc
)
6065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6066 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6067 int pipe
= intel_crtc
->pipe
;
6068 struct drm_display_mode
*mode
;
6069 int htot
= I915_READ(HTOTAL(pipe
));
6070 int hsync
= I915_READ(HSYNC(pipe
));
6071 int vtot
= I915_READ(VTOTAL(pipe
));
6072 int vsync
= I915_READ(VSYNC(pipe
));
6074 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6078 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6079 mode
->hdisplay
= (htot
& 0xffff) + 1;
6080 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6081 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6082 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6083 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6084 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6085 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6086 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6088 drm_mode_set_name(mode
);
6093 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6095 struct drm_device
*dev
= crtc
->dev
;
6096 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6097 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6098 int pipe
= intel_crtc
->pipe
;
6099 int dpll_reg
= DPLL(pipe
);
6102 if (HAS_PCH_SPLIT(dev
))
6105 if (!dev_priv
->lvds_downclock_avail
)
6108 dpll
= I915_READ(dpll_reg
);
6109 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6110 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6112 assert_panel_unlocked(dev_priv
, pipe
);
6114 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6115 I915_WRITE(dpll_reg
, dpll
);
6116 intel_wait_for_vblank(dev
, pipe
);
6118 dpll
= I915_READ(dpll_reg
);
6119 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6120 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6124 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
6126 struct drm_device
*dev
= crtc
->dev
;
6127 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6128 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6130 if (HAS_PCH_SPLIT(dev
))
6133 if (!dev_priv
->lvds_downclock_avail
)
6137 * Since this is called by a timer, we should never get here in
6140 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
6141 int pipe
= intel_crtc
->pipe
;
6142 int dpll_reg
= DPLL(pipe
);
6145 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6147 assert_panel_unlocked(dev_priv
, pipe
);
6149 dpll
= I915_READ(dpll_reg
);
6150 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
6151 I915_WRITE(dpll_reg
, dpll
);
6152 intel_wait_for_vblank(dev
, pipe
);
6153 dpll
= I915_READ(dpll_reg
);
6154 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
6155 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6160 void intel_mark_busy(struct drm_device
*dev
)
6162 i915_update_gfx_val(dev
->dev_private
);
6165 void intel_mark_idle(struct drm_device
*dev
)
6169 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
)
6171 struct drm_device
*dev
= obj
->base
.dev
;
6172 struct drm_crtc
*crtc
;
6174 if (!i915_powersave
)
6177 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6181 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6182 intel_increase_pllclock(crtc
);
6186 void intel_mark_fb_idle(struct drm_i915_gem_object
*obj
)
6188 struct drm_device
*dev
= obj
->base
.dev
;
6189 struct drm_crtc
*crtc
;
6191 if (!i915_powersave
)
6194 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6198 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6199 intel_decrease_pllclock(crtc
);
6203 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6205 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6206 struct drm_device
*dev
= crtc
->dev
;
6207 struct intel_unpin_work
*work
;
6208 unsigned long flags
;
6210 spin_lock_irqsave(&dev
->event_lock
, flags
);
6211 work
= intel_crtc
->unpin_work
;
6212 intel_crtc
->unpin_work
= NULL
;
6213 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6216 cancel_work_sync(&work
->work
);
6220 drm_crtc_cleanup(crtc
);
6225 static void intel_unpin_work_fn(struct work_struct
*__work
)
6227 struct intel_unpin_work
*work
=
6228 container_of(__work
, struct intel_unpin_work
, work
);
6230 mutex_lock(&work
->dev
->struct_mutex
);
6231 intel_unpin_fb_obj(work
->old_fb_obj
);
6232 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6233 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6235 intel_update_fbc(work
->dev
);
6236 mutex_unlock(&work
->dev
->struct_mutex
);
6240 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6241 struct drm_crtc
*crtc
)
6243 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6244 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6245 struct intel_unpin_work
*work
;
6246 struct drm_i915_gem_object
*obj
;
6247 struct drm_pending_vblank_event
*e
;
6248 struct timeval tnow
, tvbl
;
6249 unsigned long flags
;
6251 /* Ignore early vblank irqs */
6252 if (intel_crtc
== NULL
)
6255 do_gettimeofday(&tnow
);
6257 spin_lock_irqsave(&dev
->event_lock
, flags
);
6258 work
= intel_crtc
->unpin_work
;
6259 if (work
== NULL
|| !work
->pending
) {
6260 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6264 intel_crtc
->unpin_work
= NULL
;
6268 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
6270 /* Called before vblank count and timestamps have
6271 * been updated for the vblank interval of flip
6272 * completion? Need to increment vblank count and
6273 * add one videorefresh duration to returned timestamp
6274 * to account for this. We assume this happened if we
6275 * get called over 0.9 frame durations after the last
6276 * timestamped vblank.
6278 * This calculation can not be used with vrefresh rates
6279 * below 5Hz (10Hz to be on the safe side) without
6280 * promoting to 64 integers.
6282 if (10 * (timeval_to_ns(&tnow
) - timeval_to_ns(&tvbl
)) >
6283 9 * crtc
->framedur_ns
) {
6284 e
->event
.sequence
++;
6285 tvbl
= ns_to_timeval(timeval_to_ns(&tvbl
) +
6289 e
->event
.tv_sec
= tvbl
.tv_sec
;
6290 e
->event
.tv_usec
= tvbl
.tv_usec
;
6292 list_add_tail(&e
->base
.link
,
6293 &e
->base
.file_priv
->event_list
);
6294 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
6297 drm_vblank_put(dev
, intel_crtc
->pipe
);
6299 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6301 obj
= work
->old_fb_obj
;
6303 atomic_clear_mask(1 << intel_crtc
->plane
,
6304 &obj
->pending_flip
.counter
);
6305 if (atomic_read(&obj
->pending_flip
) == 0)
6306 wake_up(&dev_priv
->pending_flip_queue
);
6308 schedule_work(&work
->work
);
6310 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
6313 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
6315 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6316 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
6318 do_intel_finish_page_flip(dev
, crtc
);
6321 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
6323 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6324 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
6326 do_intel_finish_page_flip(dev
, crtc
);
6329 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
6331 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6332 struct intel_crtc
*intel_crtc
=
6333 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
6334 unsigned long flags
;
6336 spin_lock_irqsave(&dev
->event_lock
, flags
);
6337 if (intel_crtc
->unpin_work
) {
6338 if ((++intel_crtc
->unpin_work
->pending
) > 1)
6339 DRM_ERROR("Prepared flip multiple times\n");
6341 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6343 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6346 static int intel_gen2_queue_flip(struct drm_device
*dev
,
6347 struct drm_crtc
*crtc
,
6348 struct drm_framebuffer
*fb
,
6349 struct drm_i915_gem_object
*obj
)
6351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6352 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6354 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6357 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6361 ret
= intel_ring_begin(ring
, 6);
6365 /* Can't queue multiple flips, so wait for the previous
6366 * one to finish before executing the next.
6368 if (intel_crtc
->plane
)
6369 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6371 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6372 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6373 intel_ring_emit(ring
, MI_NOOP
);
6374 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6375 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6376 intel_ring_emit(ring
, fb
->pitches
[0]);
6377 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6378 intel_ring_emit(ring
, 0); /* aux display base address, unused */
6379 intel_ring_advance(ring
);
6383 intel_unpin_fb_obj(obj
);
6388 static int intel_gen3_queue_flip(struct drm_device
*dev
,
6389 struct drm_crtc
*crtc
,
6390 struct drm_framebuffer
*fb
,
6391 struct drm_i915_gem_object
*obj
)
6393 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6394 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6396 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6399 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6403 ret
= intel_ring_begin(ring
, 6);
6407 if (intel_crtc
->plane
)
6408 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6410 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6411 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6412 intel_ring_emit(ring
, MI_NOOP
);
6413 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
6414 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6415 intel_ring_emit(ring
, fb
->pitches
[0]);
6416 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6417 intel_ring_emit(ring
, MI_NOOP
);
6419 intel_ring_advance(ring
);
6423 intel_unpin_fb_obj(obj
);
6428 static int intel_gen4_queue_flip(struct drm_device
*dev
,
6429 struct drm_crtc
*crtc
,
6430 struct drm_framebuffer
*fb
,
6431 struct drm_i915_gem_object
*obj
)
6433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6434 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6435 uint32_t pf
, pipesrc
;
6436 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6439 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6443 ret
= intel_ring_begin(ring
, 4);
6447 /* i965+ uses the linear or tiled offsets from the
6448 * Display Registers (which do not change across a page-flip)
6449 * so we need only reprogram the base address.
6451 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6452 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6453 intel_ring_emit(ring
, fb
->pitches
[0]);
6454 intel_ring_emit(ring
,
6455 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
6458 /* XXX Enabling the panel-fitter across page-flip is so far
6459 * untested on non-native modes, so ignore it for now.
6460 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6463 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6464 intel_ring_emit(ring
, pf
| pipesrc
);
6465 intel_ring_advance(ring
);
6469 intel_unpin_fb_obj(obj
);
6474 static int intel_gen6_queue_flip(struct drm_device
*dev
,
6475 struct drm_crtc
*crtc
,
6476 struct drm_framebuffer
*fb
,
6477 struct drm_i915_gem_object
*obj
)
6479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6480 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6481 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6482 uint32_t pf
, pipesrc
;
6485 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6489 ret
= intel_ring_begin(ring
, 4);
6493 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6494 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6495 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
6496 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6498 /* Contrary to the suggestions in the documentation,
6499 * "Enable Panel Fitter" does not seem to be required when page
6500 * flipping with a non-native mode, and worse causes a normal
6502 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6505 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6506 intel_ring_emit(ring
, pf
| pipesrc
);
6507 intel_ring_advance(ring
);
6511 intel_unpin_fb_obj(obj
);
6517 * On gen7 we currently use the blit ring because (in early silicon at least)
6518 * the render ring doesn't give us interrpts for page flip completion, which
6519 * means clients will hang after the first flip is queued. Fortunately the
6520 * blit ring generates interrupts properly, so use it instead.
6522 static int intel_gen7_queue_flip(struct drm_device
*dev
,
6523 struct drm_crtc
*crtc
,
6524 struct drm_framebuffer
*fb
,
6525 struct drm_i915_gem_object
*obj
)
6527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6528 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6529 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
6530 uint32_t plane_bit
= 0;
6533 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6537 switch(intel_crtc
->plane
) {
6539 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
6542 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
6545 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
6548 WARN_ONCE(1, "unknown plane in flip command\n");
6553 ret
= intel_ring_begin(ring
, 4);
6557 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
6558 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
6559 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6560 intel_ring_emit(ring
, (MI_NOOP
));
6561 intel_ring_advance(ring
);
6565 intel_unpin_fb_obj(obj
);
6570 static int intel_default_queue_flip(struct drm_device
*dev
,
6571 struct drm_crtc
*crtc
,
6572 struct drm_framebuffer
*fb
,
6573 struct drm_i915_gem_object
*obj
)
6578 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
6579 struct drm_framebuffer
*fb
,
6580 struct drm_pending_vblank_event
*event
)
6582 struct drm_device
*dev
= crtc
->dev
;
6583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6584 struct intel_framebuffer
*intel_fb
;
6585 struct drm_i915_gem_object
*obj
;
6586 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6587 struct intel_unpin_work
*work
;
6588 unsigned long flags
;
6591 /* Can't change pixel format via MI display flips. */
6592 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
6596 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6597 * Note that pitch changes could also affect these register.
6599 if (INTEL_INFO(dev
)->gen
> 3 &&
6600 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
6601 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
6604 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
6608 work
->event
= event
;
6609 work
->dev
= crtc
->dev
;
6610 intel_fb
= to_intel_framebuffer(crtc
->fb
);
6611 work
->old_fb_obj
= intel_fb
->obj
;
6612 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
6614 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
6618 /* We borrow the event spin lock for protecting unpin_work */
6619 spin_lock_irqsave(&dev
->event_lock
, flags
);
6620 if (intel_crtc
->unpin_work
) {
6621 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6623 drm_vblank_put(dev
, intel_crtc
->pipe
);
6625 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6628 intel_crtc
->unpin_work
= work
;
6629 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6631 intel_fb
= to_intel_framebuffer(fb
);
6632 obj
= intel_fb
->obj
;
6634 ret
= i915_mutex_lock_interruptible(dev
);
6638 /* Reference the objects for the scheduled work. */
6639 drm_gem_object_reference(&work
->old_fb_obj
->base
);
6640 drm_gem_object_reference(&obj
->base
);
6644 work
->pending_flip_obj
= obj
;
6646 work
->enable_stall_check
= true;
6648 /* Block clients from rendering to the new back buffer until
6649 * the flip occurs and the object is no longer visible.
6651 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6653 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
6655 goto cleanup_pending
;
6657 intel_disable_fbc(dev
);
6658 intel_mark_fb_busy(obj
);
6659 mutex_unlock(&dev
->struct_mutex
);
6661 trace_i915_flip_request(intel_crtc
->plane
, obj
);
6666 atomic_sub(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6667 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6668 drm_gem_object_unreference(&obj
->base
);
6669 mutex_unlock(&dev
->struct_mutex
);
6672 spin_lock_irqsave(&dev
->event_lock
, flags
);
6673 intel_crtc
->unpin_work
= NULL
;
6674 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6676 drm_vblank_put(dev
, intel_crtc
->pipe
);
6683 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
6684 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
6685 .load_lut
= intel_crtc_load_lut
,
6686 .disable
= intel_crtc_noop
,
6689 bool intel_encoder_check_is_cloned(struct intel_encoder
*encoder
)
6691 struct intel_encoder
*other_encoder
;
6692 struct drm_crtc
*crtc
= &encoder
->new_crtc
->base
;
6697 list_for_each_entry(other_encoder
,
6698 &crtc
->dev
->mode_config
.encoder_list
,
6701 if (&other_encoder
->new_crtc
->base
!= crtc
||
6702 encoder
== other_encoder
)
6711 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
6712 struct drm_crtc
*crtc
)
6714 struct drm_device
*dev
;
6715 struct drm_crtc
*tmp
;
6718 WARN(!crtc
, "checking null crtc?\n");
6722 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
6728 if (encoder
->possible_crtcs
& crtc_mask
)
6734 * intel_modeset_update_staged_output_state
6736 * Updates the staged output configuration state, e.g. after we've read out the
6739 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
6741 struct intel_encoder
*encoder
;
6742 struct intel_connector
*connector
;
6744 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
6746 connector
->new_encoder
=
6747 to_intel_encoder(connector
->base
.encoder
);
6750 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
6753 to_intel_crtc(encoder
->base
.crtc
);
6758 * intel_modeset_commit_output_state
6760 * This function copies the stage display pipe configuration to the real one.
6762 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
6764 struct intel_encoder
*encoder
;
6765 struct intel_connector
*connector
;
6767 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
6769 connector
->base
.encoder
= &connector
->new_encoder
->base
;
6772 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
6774 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
6778 static struct drm_display_mode
*
6779 intel_modeset_adjusted_mode(struct drm_crtc
*crtc
,
6780 struct drm_display_mode
*mode
)
6782 struct drm_device
*dev
= crtc
->dev
;
6783 struct drm_display_mode
*adjusted_mode
;
6784 struct drm_encoder_helper_funcs
*encoder_funcs
;
6785 struct intel_encoder
*encoder
;
6787 adjusted_mode
= drm_mode_duplicate(dev
, mode
);
6789 return ERR_PTR(-ENOMEM
);
6791 /* Pass our mode to the connectors and the CRTC to give them a chance to
6792 * adjust it according to limitations or connector properties, and also
6793 * a chance to reject the mode entirely.
6795 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
6798 if (&encoder
->new_crtc
->base
!= crtc
)
6800 encoder_funcs
= encoder
->base
.helper_private
;
6801 if (!(encoder_funcs
->mode_fixup(&encoder
->base
, mode
,
6803 DRM_DEBUG_KMS("Encoder fixup failed\n");
6808 if (!(intel_crtc_mode_fixup(crtc
, mode
, adjusted_mode
))) {
6809 DRM_DEBUG_KMS("CRTC fixup failed\n");
6812 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
6814 return adjusted_mode
;
6816 drm_mode_destroy(dev
, adjusted_mode
);
6817 return ERR_PTR(-EINVAL
);
6820 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
6821 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6823 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
6824 unsigned *prepare_pipes
, unsigned *disable_pipes
)
6826 struct intel_crtc
*intel_crtc
;
6827 struct drm_device
*dev
= crtc
->dev
;
6828 struct intel_encoder
*encoder
;
6829 struct intel_connector
*connector
;
6830 struct drm_crtc
*tmp_crtc
;
6832 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
6834 /* Check which crtcs have changed outputs connected to them, these need
6835 * to be part of the prepare_pipes mask. We don't (yet) support global
6836 * modeset across multiple crtcs, so modeset_pipes will only have one
6837 * bit set at most. */
6838 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
6840 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
6843 if (connector
->base
.encoder
) {
6844 tmp_crtc
= connector
->base
.encoder
->crtc
;
6846 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
6849 if (connector
->new_encoder
)
6851 1 << connector
->new_encoder
->new_crtc
->pipe
;
6854 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
6856 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
6859 if (encoder
->base
.crtc
) {
6860 tmp_crtc
= encoder
->base
.crtc
;
6862 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
6865 if (encoder
->new_crtc
)
6866 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
6869 /* Check for any pipes that will be fully disabled ... */
6870 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
6874 /* Don't try to disable disabled crtcs. */
6875 if (!intel_crtc
->base
.enabled
)
6878 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
6880 if (encoder
->new_crtc
== intel_crtc
)
6885 *disable_pipes
|= 1 << intel_crtc
->pipe
;
6889 /* set_mode is also used to update properties on life display pipes. */
6890 intel_crtc
= to_intel_crtc(crtc
);
6892 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
6894 /* We only support modeset on one single crtc, hence we need to do that
6895 * only for the passed in crtc iff we change anything else than just
6898 * This is actually not true, to be fully compatible with the old crtc
6899 * helper we automatically disable _any_ output (i.e. doesn't need to be
6900 * connected to the crtc we're modesetting on) if it's disconnected.
6901 * Which is a rather nutty api (since changed the output configuration
6902 * without userspace's explicit request can lead to confusion), but
6903 * alas. Hence we currently need to modeset on all pipes we prepare. */
6905 *modeset_pipes
= *prepare_pipes
;
6907 /* ... and mask these out. */
6908 *modeset_pipes
&= ~(*disable_pipes
);
6909 *prepare_pipes
&= ~(*disable_pipes
);
6912 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
6914 struct drm_encoder
*encoder
;
6915 struct drm_device
*dev
= crtc
->dev
;
6917 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
6918 if (encoder
->crtc
== crtc
)
6925 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
6927 struct intel_encoder
*intel_encoder
;
6928 struct intel_crtc
*intel_crtc
;
6929 struct drm_connector
*connector
;
6931 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
6933 if (!intel_encoder
->base
.crtc
)
6936 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
6938 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
6939 intel_encoder
->connectors_active
= false;
6942 intel_modeset_commit_output_state(dev
);
6944 /* Update computed state. */
6945 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
6947 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
6950 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
6951 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
6954 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
6956 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
6957 struct drm_property
*dpms_property
=
6958 dev
->mode_config
.dpms_property
;
6960 connector
->dpms
= DRM_MODE_DPMS_ON
;
6961 drm_connector_property_set_value(connector
,
6965 intel_encoder
= to_intel_encoder(connector
->encoder
);
6966 intel_encoder
->connectors_active
= true;
6972 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6973 list_for_each_entry((intel_crtc), \
6974 &(dev)->mode_config.crtc_list, \
6976 if (mask & (1 <<(intel_crtc)->pipe)) \
6979 intel_modeset_check_state(struct drm_device
*dev
)
6981 struct intel_crtc
*crtc
;
6982 struct intel_encoder
*encoder
;
6983 struct intel_connector
*connector
;
6985 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
6987 /* This also checks the encoder/connector hw state with the
6988 * ->get_hw_state callbacks. */
6989 intel_connector_check_state(connector
);
6991 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
6992 "connector's staged encoder doesn't match current encoder\n");
6995 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
6997 bool enabled
= false;
6998 bool active
= false;
6999 enum pipe pipe
, tracked_pipe
;
7001 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7002 encoder
->base
.base
.id
,
7003 drm_get_encoder_name(&encoder
->base
));
7005 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
7006 "encoder's stage crtc doesn't match current crtc\n");
7007 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
7008 "encoder's active_connectors set, but no crtc\n");
7010 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7012 if (connector
->base
.encoder
!= &encoder
->base
)
7015 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
7018 WARN(!!encoder
->base
.crtc
!= enabled
,
7019 "encoder's enabled state mismatch "
7020 "(expected %i, found %i)\n",
7021 !!encoder
->base
.crtc
, enabled
);
7022 WARN(active
&& !encoder
->base
.crtc
,
7023 "active encoder with no crtc\n");
7025 WARN(encoder
->connectors_active
!= active
,
7026 "encoder's computed active state doesn't match tracked active state "
7027 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
7029 active
= encoder
->get_hw_state(encoder
, &pipe
);
7030 WARN(active
!= encoder
->connectors_active
,
7031 "encoder's hw state doesn't match sw tracking "
7032 "(expected %i, found %i)\n",
7033 encoder
->connectors_active
, active
);
7035 if (!encoder
->base
.crtc
)
7038 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
7039 WARN(active
&& pipe
!= tracked_pipe
,
7040 "active encoder's pipe doesn't match"
7041 "(expected %i, found %i)\n",
7042 tracked_pipe
, pipe
);
7046 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
7048 bool enabled
= false;
7049 bool active
= false;
7051 DRM_DEBUG_KMS("[CRTC:%d]\n",
7052 crtc
->base
.base
.id
);
7054 WARN(crtc
->active
&& !crtc
->base
.enabled
,
7055 "active crtc, but not enabled in sw tracking\n");
7057 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7059 if (encoder
->base
.crtc
!= &crtc
->base
)
7062 if (encoder
->connectors_active
)
7065 WARN(active
!= crtc
->active
,
7066 "crtc's computed active state doesn't match tracked active state "
7067 "(expected %i, found %i)\n", active
, crtc
->active
);
7068 WARN(enabled
!= crtc
->base
.enabled
,
7069 "crtc's computed enabled state doesn't match tracked enabled state "
7070 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
7072 assert_pipe(dev
->dev_private
, crtc
->pipe
, crtc
->active
);
7076 bool intel_set_mode(struct drm_crtc
*crtc
,
7077 struct drm_display_mode
*mode
,
7078 int x
, int y
, struct drm_framebuffer
*fb
)
7080 struct drm_device
*dev
= crtc
->dev
;
7081 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7082 struct drm_display_mode
*adjusted_mode
, saved_mode
, saved_hwmode
;
7083 struct drm_encoder_helper_funcs
*encoder_funcs
;
7084 struct drm_encoder
*encoder
;
7085 struct intel_crtc
*intel_crtc
;
7086 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
7089 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
7090 &prepare_pipes
, &disable_pipes
);
7092 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7093 modeset_pipes
, prepare_pipes
, disable_pipes
);
7095 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
7096 intel_crtc_disable(&intel_crtc
->base
);
7098 saved_hwmode
= crtc
->hwmode
;
7099 saved_mode
= crtc
->mode
;
7101 /* Hack: Because we don't (yet) support global modeset on multiple
7102 * crtcs, we don't keep track of the new mode for more than one crtc.
7103 * Hence simply check whether any bit is set in modeset_pipes in all the
7104 * pieces of code that are not yet converted to deal with mutliple crtcs
7105 * changing their mode at the same time. */
7106 adjusted_mode
= NULL
;
7107 if (modeset_pipes
) {
7108 adjusted_mode
= intel_modeset_adjusted_mode(crtc
, mode
);
7109 if (IS_ERR(adjusted_mode
)) {
7114 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
7115 if (intel_crtc
->base
.enabled
)
7116 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
7119 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7120 * to set it here already despite that we pass it down the callchain.
7125 /* Only after disabling all output pipelines that will be changed can we
7126 * update the the output configuration. */
7127 intel_modeset_update_state(dev
, prepare_pipes
);
7129 /* Set up the DPLL and any encoders state that needs to adjust or depend
7132 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
7133 ret
= !intel_crtc_mode_set(&intel_crtc
->base
,
7134 mode
, adjusted_mode
,
7139 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
7141 if (encoder
->crtc
!= &intel_crtc
->base
)
7144 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7145 encoder
->base
.id
, drm_get_encoder_name(encoder
),
7146 mode
->base
.id
, mode
->name
);
7147 encoder_funcs
= encoder
->helper_private
;
7148 encoder_funcs
->mode_set(encoder
, mode
, adjusted_mode
);
7152 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7153 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
7154 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
7156 if (modeset_pipes
) {
7157 /* Store real post-adjustment hardware mode. */
7158 crtc
->hwmode
= *adjusted_mode
;
7160 /* Calculate and store various constants which
7161 * are later needed by vblank and swap-completion
7162 * timestamping. They are derived from true hwmode.
7164 drm_calc_timestamping_constants(crtc
);
7167 /* FIXME: add subpixel order */
7169 drm_mode_destroy(dev
, adjusted_mode
);
7170 if (!ret
&& crtc
->enabled
) {
7171 crtc
->hwmode
= saved_hwmode
;
7172 crtc
->mode
= saved_mode
;
7174 intel_modeset_check_state(dev
);
7180 #undef for_each_intel_crtc_masked
7182 static void intel_set_config_free(struct intel_set_config
*config
)
7187 kfree(config
->save_connector_encoders
);
7188 kfree(config
->save_encoder_crtcs
);
7192 static int intel_set_config_save_state(struct drm_device
*dev
,
7193 struct intel_set_config
*config
)
7195 struct drm_encoder
*encoder
;
7196 struct drm_connector
*connector
;
7199 config
->save_encoder_crtcs
=
7200 kcalloc(dev
->mode_config
.num_encoder
,
7201 sizeof(struct drm_crtc
*), GFP_KERNEL
);
7202 if (!config
->save_encoder_crtcs
)
7205 config
->save_connector_encoders
=
7206 kcalloc(dev
->mode_config
.num_connector
,
7207 sizeof(struct drm_encoder
*), GFP_KERNEL
);
7208 if (!config
->save_connector_encoders
)
7211 /* Copy data. Note that driver private data is not affected.
7212 * Should anything bad happen only the expected state is
7213 * restored, not the drivers personal bookkeeping.
7216 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
7217 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
7221 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7222 config
->save_connector_encoders
[count
++] = connector
->encoder
;
7228 static void intel_set_config_restore_state(struct drm_device
*dev
,
7229 struct intel_set_config
*config
)
7231 struct intel_encoder
*encoder
;
7232 struct intel_connector
*connector
;
7236 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
7238 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
7242 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
7243 connector
->new_encoder
=
7244 to_intel_encoder(config
->save_connector_encoders
[count
++]);
7249 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
7250 struct intel_set_config
*config
)
7253 /* We should be able to check here if the fb has the same properties
7254 * and then just flip_or_move it */
7255 if (set
->crtc
->fb
!= set
->fb
) {
7256 /* If we have no fb then treat it as a full mode set */
7257 if (set
->crtc
->fb
== NULL
) {
7258 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7259 config
->mode_changed
= true;
7260 } else if (set
->fb
== NULL
) {
7261 config
->mode_changed
= true;
7262 } else if (set
->fb
->depth
!= set
->crtc
->fb
->depth
) {
7263 config
->mode_changed
= true;
7264 } else if (set
->fb
->bits_per_pixel
!=
7265 set
->crtc
->fb
->bits_per_pixel
) {
7266 config
->mode_changed
= true;
7268 config
->fb_changed
= true;
7271 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
7272 config
->fb_changed
= true;
7274 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
7275 DRM_DEBUG_KMS("modes are different, full mode set\n");
7276 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
7277 drm_mode_debug_printmodeline(set
->mode
);
7278 config
->mode_changed
= true;
7283 intel_modeset_stage_output_state(struct drm_device
*dev
,
7284 struct drm_mode_set
*set
,
7285 struct intel_set_config
*config
)
7287 struct drm_crtc
*new_crtc
;
7288 struct intel_connector
*connector
;
7289 struct intel_encoder
*encoder
;
7292 /* The upper layers ensure that we either disabl a crtc or have a list
7293 * of connectors. For paranoia, double-check this. */
7294 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
7295 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
7298 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7300 /* Otherwise traverse passed in connector list and get encoders
7302 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
7303 if (set
->connectors
[ro
] == &connector
->base
) {
7304 connector
->new_encoder
= connector
->encoder
;
7309 /* If we disable the crtc, disable all its connectors. Also, if
7310 * the connector is on the changing crtc but not on the new
7311 * connector list, disable it. */
7312 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
7313 connector
->base
.encoder
&&
7314 connector
->base
.encoder
->crtc
== set
->crtc
) {
7315 connector
->new_encoder
= NULL
;
7317 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7318 connector
->base
.base
.id
,
7319 drm_get_connector_name(&connector
->base
));
7323 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
7324 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7325 config
->mode_changed
= true;
7328 /* Disable all disconnected encoders. */
7329 if (connector
->base
.status
== connector_status_disconnected
)
7330 connector
->new_encoder
= NULL
;
7332 /* connector->new_encoder is now updated for all connectors. */
7334 /* Update crtc of enabled connectors. */
7336 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7338 if (!connector
->new_encoder
)
7341 new_crtc
= connector
->new_encoder
->base
.crtc
;
7343 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
7344 if (set
->connectors
[ro
] == &connector
->base
)
7345 new_crtc
= set
->crtc
;
7348 /* Make sure the new CRTC will work with the encoder */
7349 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
7353 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
7355 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7356 connector
->base
.base
.id
,
7357 drm_get_connector_name(&connector
->base
),
7361 /* Check for any encoders that needs to be disabled. */
7362 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7364 list_for_each_entry(connector
,
7365 &dev
->mode_config
.connector_list
,
7367 if (connector
->new_encoder
== encoder
) {
7368 WARN_ON(!connector
->new_encoder
->new_crtc
);
7373 encoder
->new_crtc
= NULL
;
7375 /* Only now check for crtc changes so we don't miss encoders
7376 * that will be disabled. */
7377 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
7378 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7379 config
->mode_changed
= true;
7382 /* Now we've also updated encoder->new_crtc for all encoders. */
7387 static int intel_crtc_set_config(struct drm_mode_set
*set
)
7389 struct drm_device
*dev
;
7390 struct drm_mode_set save_set
;
7391 struct intel_set_config
*config
;
7396 BUG_ON(!set
->crtc
->helper_private
);
7401 /* The fb helper likes to play gross jokes with ->mode_set_config.
7402 * Unfortunately the crtc helper doesn't do much at all for this case,
7403 * so we have to cope with this madness until the fb helper is fixed up. */
7404 if (set
->fb
&& set
->num_connectors
== 0)
7408 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7409 set
->crtc
->base
.id
, set
->fb
->base
.id
,
7410 (int)set
->num_connectors
, set
->x
, set
->y
);
7412 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
7415 dev
= set
->crtc
->dev
;
7418 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
7422 ret
= intel_set_config_save_state(dev
, config
);
7426 save_set
.crtc
= set
->crtc
;
7427 save_set
.mode
= &set
->crtc
->mode
;
7428 save_set
.x
= set
->crtc
->x
;
7429 save_set
.y
= set
->crtc
->y
;
7430 save_set
.fb
= set
->crtc
->fb
;
7432 /* Compute whether we need a full modeset, only an fb base update or no
7433 * change at all. In the future we might also check whether only the
7434 * mode changed, e.g. for LVDS where we only change the panel fitter in
7436 intel_set_config_compute_mode_changes(set
, config
);
7438 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
7442 if (config
->mode_changed
) {
7444 DRM_DEBUG_KMS("attempting to set mode from"
7446 drm_mode_debug_printmodeline(set
->mode
);
7449 if (!intel_set_mode(set
->crtc
, set
->mode
,
7450 set
->x
, set
->y
, set
->fb
)) {
7451 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7452 set
->crtc
->base
.id
);
7456 } else if (config
->fb_changed
) {
7457 ret
= intel_pipe_set_base(set
->crtc
,
7458 set
->x
, set
->y
, set
->fb
);
7461 intel_set_config_free(config
);
7466 intel_set_config_restore_state(dev
, config
);
7468 /* Try to restore the config */
7469 if (config
->mode_changed
&&
7470 !intel_set_mode(save_set
.crtc
, save_set
.mode
,
7471 save_set
.x
, save_set
.y
, save_set
.fb
))
7472 DRM_ERROR("failed to restore config after modeset failure\n");
7475 intel_set_config_free(config
);
7479 static const struct drm_crtc_funcs intel_crtc_funcs
= {
7480 .cursor_set
= intel_crtc_cursor_set
,
7481 .cursor_move
= intel_crtc_cursor_move
,
7482 .gamma_set
= intel_crtc_gamma_set
,
7483 .set_config
= intel_crtc_set_config
,
7484 .destroy
= intel_crtc_destroy
,
7485 .page_flip
= intel_crtc_page_flip
,
7488 static void intel_pch_pll_init(struct drm_device
*dev
)
7490 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7493 if (dev_priv
->num_pch_pll
== 0) {
7494 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7498 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
7499 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
7500 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
7501 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
7505 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
7507 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7508 struct intel_crtc
*intel_crtc
;
7511 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
7512 if (intel_crtc
== NULL
)
7515 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
7517 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
7518 for (i
= 0; i
< 256; i
++) {
7519 intel_crtc
->lut_r
[i
] = i
;
7520 intel_crtc
->lut_g
[i
] = i
;
7521 intel_crtc
->lut_b
[i
] = i
;
7524 /* Swap pipes & planes for FBC on pre-965 */
7525 intel_crtc
->pipe
= pipe
;
7526 intel_crtc
->plane
= pipe
;
7527 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
7528 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7529 intel_crtc
->plane
= !pipe
;
7532 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
7533 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
7534 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
7535 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
7537 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
7539 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
7542 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
7543 struct drm_file
*file
)
7545 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
7546 struct drm_mode_object
*drmmode_obj
;
7547 struct intel_crtc
*crtc
;
7549 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
7552 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
7553 DRM_MODE_OBJECT_CRTC
);
7556 DRM_ERROR("no such CRTC id\n");
7560 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
7561 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
7566 static int intel_encoder_clones(struct intel_encoder
*encoder
)
7568 struct drm_device
*dev
= encoder
->base
.dev
;
7569 struct intel_encoder
*source_encoder
;
7573 list_for_each_entry(source_encoder
,
7574 &dev
->mode_config
.encoder_list
, base
.head
) {
7576 if (encoder
== source_encoder
)
7577 index_mask
|= (1 << entry
);
7579 /* Intel hw has only one MUX where enocoders could be cloned. */
7580 if (encoder
->cloneable
&& source_encoder
->cloneable
)
7581 index_mask
|= (1 << entry
);
7589 static bool has_edp_a(struct drm_device
*dev
)
7591 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7593 if (!IS_MOBILE(dev
))
7596 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
7600 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
7606 static void intel_setup_outputs(struct drm_device
*dev
)
7608 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7609 struct intel_encoder
*encoder
;
7610 bool dpd_is_edp
= false;
7613 has_lvds
= intel_lvds_init(dev
);
7614 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
7615 /* disable the panel fitter on everything but LVDS */
7616 I915_WRITE(PFIT_CONTROL
, 0);
7619 if (HAS_PCH_SPLIT(dev
)) {
7620 dpd_is_edp
= intel_dpd_is_edp(dev
);
7623 intel_dp_init(dev
, DP_A
, PORT_A
);
7625 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
7626 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
7629 intel_crt_init(dev
);
7631 if (IS_HASWELL(dev
)) {
7634 /* Haswell uses DDI functions to detect digital outputs */
7635 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
7636 /* DDI A only supports eDP */
7638 intel_ddi_init(dev
, PORT_A
);
7640 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7642 found
= I915_READ(SFUSE_STRAP
);
7644 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
7645 intel_ddi_init(dev
, PORT_B
);
7646 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
7647 intel_ddi_init(dev
, PORT_C
);
7648 if (found
& SFUSE_STRAP_DDID_DETECTED
)
7649 intel_ddi_init(dev
, PORT_D
);
7650 } else if (HAS_PCH_SPLIT(dev
)) {
7653 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
7654 /* PCH SDVOB multiplex with HDMIB */
7655 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
7657 intel_hdmi_init(dev
, HDMIB
, PORT_B
);
7658 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
7659 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
7662 if (I915_READ(HDMIC
) & PORT_DETECTED
)
7663 intel_hdmi_init(dev
, HDMIC
, PORT_C
);
7665 if (!dpd_is_edp
&& I915_READ(HDMID
) & PORT_DETECTED
)
7666 intel_hdmi_init(dev
, HDMID
, PORT_D
);
7668 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
7669 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
7671 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
7672 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
7673 } else if (IS_VALLEYVIEW(dev
)) {
7676 if (I915_READ(SDVOB
) & PORT_DETECTED
) {
7677 /* SDVOB multiplex with HDMIB */
7678 found
= intel_sdvo_init(dev
, SDVOB
, true);
7680 intel_hdmi_init(dev
, SDVOB
, PORT_B
);
7681 if (!found
&& (I915_READ(DP_B
) & DP_DETECTED
))
7682 intel_dp_init(dev
, DP_B
, PORT_B
);
7685 if (I915_READ(SDVOC
) & PORT_DETECTED
)
7686 intel_hdmi_init(dev
, SDVOC
, PORT_C
);
7688 /* Shares lanes with HDMI on SDVOC */
7689 if (I915_READ(DP_C
) & DP_DETECTED
)
7690 intel_dp_init(dev
, DP_C
, PORT_C
);
7691 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
7694 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
7695 DRM_DEBUG_KMS("probing SDVOB\n");
7696 found
= intel_sdvo_init(dev
, SDVOB
, true);
7697 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
7698 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7699 intel_hdmi_init(dev
, SDVOB
, PORT_B
);
7702 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
7703 DRM_DEBUG_KMS("probing DP_B\n");
7704 intel_dp_init(dev
, DP_B
, PORT_B
);
7708 /* Before G4X SDVOC doesn't have its own detect register */
7710 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
7711 DRM_DEBUG_KMS("probing SDVOC\n");
7712 found
= intel_sdvo_init(dev
, SDVOC
, false);
7715 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
7717 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
7718 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7719 intel_hdmi_init(dev
, SDVOC
, PORT_C
);
7721 if (SUPPORTS_INTEGRATED_DP(dev
)) {
7722 DRM_DEBUG_KMS("probing DP_C\n");
7723 intel_dp_init(dev
, DP_C
, PORT_C
);
7727 if (SUPPORTS_INTEGRATED_DP(dev
) &&
7728 (I915_READ(DP_D
) & DP_DETECTED
)) {
7729 DRM_DEBUG_KMS("probing DP_D\n");
7730 intel_dp_init(dev
, DP_D
, PORT_D
);
7732 } else if (IS_GEN2(dev
))
7733 intel_dvo_init(dev
);
7735 if (SUPPORTS_TV(dev
))
7738 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
7739 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
7740 encoder
->base
.possible_clones
=
7741 intel_encoder_clones(encoder
);
7744 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
7745 ironlake_init_pch_refclk(dev
);
7748 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
7750 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
7752 drm_framebuffer_cleanup(fb
);
7753 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
7758 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
7759 struct drm_file
*file
,
7760 unsigned int *handle
)
7762 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
7763 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
7765 return drm_gem_handle_create(file
, &obj
->base
, handle
);
7768 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
7769 .destroy
= intel_user_framebuffer_destroy
,
7770 .create_handle
= intel_user_framebuffer_create_handle
,
7773 int intel_framebuffer_init(struct drm_device
*dev
,
7774 struct intel_framebuffer
*intel_fb
,
7775 struct drm_mode_fb_cmd2
*mode_cmd
,
7776 struct drm_i915_gem_object
*obj
)
7780 if (obj
->tiling_mode
== I915_TILING_Y
)
7783 if (mode_cmd
->pitches
[0] & 63)
7786 switch (mode_cmd
->pixel_format
) {
7787 case DRM_FORMAT_RGB332
:
7788 case DRM_FORMAT_RGB565
:
7789 case DRM_FORMAT_XRGB8888
:
7790 case DRM_FORMAT_XBGR8888
:
7791 case DRM_FORMAT_ARGB8888
:
7792 case DRM_FORMAT_XRGB2101010
:
7793 case DRM_FORMAT_ARGB2101010
:
7794 /* RGB formats are common across chipsets */
7796 case DRM_FORMAT_YUYV
:
7797 case DRM_FORMAT_UYVY
:
7798 case DRM_FORMAT_YVYU
:
7799 case DRM_FORMAT_VYUY
:
7802 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7803 mode_cmd
->pixel_format
);
7807 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
7809 DRM_ERROR("framebuffer init failed %d\n", ret
);
7813 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
7814 intel_fb
->obj
= obj
;
7818 static struct drm_framebuffer
*
7819 intel_user_framebuffer_create(struct drm_device
*dev
,
7820 struct drm_file
*filp
,
7821 struct drm_mode_fb_cmd2
*mode_cmd
)
7823 struct drm_i915_gem_object
*obj
;
7825 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
7826 mode_cmd
->handles
[0]));
7827 if (&obj
->base
== NULL
)
7828 return ERR_PTR(-ENOENT
);
7830 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
7833 static const struct drm_mode_config_funcs intel_mode_funcs
= {
7834 .fb_create
= intel_user_framebuffer_create
,
7835 .output_poll_changed
= intel_fb_output_poll_changed
,
7838 /* Set up chip specific display functions */
7839 static void intel_init_display(struct drm_device
*dev
)
7841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7843 /* We always want a DPMS function */
7844 if (HAS_PCH_SPLIT(dev
)) {
7845 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
7846 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
7847 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
7848 dev_priv
->display
.off
= ironlake_crtc_off
;
7849 dev_priv
->display
.update_plane
= ironlake_update_plane
;
7851 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
7852 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
7853 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
7854 dev_priv
->display
.off
= i9xx_crtc_off
;
7855 dev_priv
->display
.update_plane
= i9xx_update_plane
;
7858 /* Returns the core display clock speed */
7859 if (IS_VALLEYVIEW(dev
))
7860 dev_priv
->display
.get_display_clock_speed
=
7861 valleyview_get_display_clock_speed
;
7862 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
7863 dev_priv
->display
.get_display_clock_speed
=
7864 i945_get_display_clock_speed
;
7865 else if (IS_I915G(dev
))
7866 dev_priv
->display
.get_display_clock_speed
=
7867 i915_get_display_clock_speed
;
7868 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
7869 dev_priv
->display
.get_display_clock_speed
=
7870 i9xx_misc_get_display_clock_speed
;
7871 else if (IS_I915GM(dev
))
7872 dev_priv
->display
.get_display_clock_speed
=
7873 i915gm_get_display_clock_speed
;
7874 else if (IS_I865G(dev
))
7875 dev_priv
->display
.get_display_clock_speed
=
7876 i865_get_display_clock_speed
;
7877 else if (IS_I85X(dev
))
7878 dev_priv
->display
.get_display_clock_speed
=
7879 i855_get_display_clock_speed
;
7881 dev_priv
->display
.get_display_clock_speed
=
7882 i830_get_display_clock_speed
;
7884 if (HAS_PCH_SPLIT(dev
)) {
7886 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
7887 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7888 } else if (IS_GEN6(dev
)) {
7889 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
7890 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7891 } else if (IS_IVYBRIDGE(dev
)) {
7892 /* FIXME: detect B0+ stepping and use auto training */
7893 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
7894 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7895 } else if (IS_HASWELL(dev
)) {
7896 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
7897 dev_priv
->display
.write_eld
= haswell_write_eld
;
7899 dev_priv
->display
.update_wm
= NULL
;
7900 } else if (IS_G4X(dev
)) {
7901 dev_priv
->display
.write_eld
= g4x_write_eld
;
7904 /* Default just returns -ENODEV to indicate unsupported */
7905 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
7907 switch (INTEL_INFO(dev
)->gen
) {
7909 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
7913 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
7918 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
7922 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
7925 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
7931 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7932 * resume, or other times. This quirk makes sure that's the case for
7935 static void quirk_pipea_force(struct drm_device
*dev
)
7937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7939 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
7940 DRM_INFO("applying pipe a force quirk\n");
7944 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7946 static void quirk_ssc_force_disable(struct drm_device
*dev
)
7948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7949 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
7950 DRM_INFO("applying lvds SSC disable quirk\n");
7954 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7957 static void quirk_invert_brightness(struct drm_device
*dev
)
7959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7960 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
7961 DRM_INFO("applying inverted panel brightness quirk\n");
7964 struct intel_quirk
{
7966 int subsystem_vendor
;
7967 int subsystem_device
;
7968 void (*hook
)(struct drm_device
*dev
);
7971 static struct intel_quirk intel_quirks
[] = {
7972 /* HP Mini needs pipe A force quirk (LP: #322104) */
7973 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
7975 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7976 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
7978 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7979 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
7981 /* 855 & before need to leave pipe A & dpll A up */
7982 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7983 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7984 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7986 /* Lenovo U160 cannot use SSC on LVDS */
7987 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
7989 /* Sony Vaio Y cannot use SSC on LVDS */
7990 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
7992 /* Acer Aspire 5734Z must invert backlight brightness */
7993 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
7996 static void intel_init_quirks(struct drm_device
*dev
)
7998 struct pci_dev
*d
= dev
->pdev
;
8001 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
8002 struct intel_quirk
*q
= &intel_quirks
[i
];
8004 if (d
->device
== q
->device
&&
8005 (d
->subsystem_vendor
== q
->subsystem_vendor
||
8006 q
->subsystem_vendor
== PCI_ANY_ID
) &&
8007 (d
->subsystem_device
== q
->subsystem_device
||
8008 q
->subsystem_device
== PCI_ANY_ID
))
8013 /* Disable the VGA plane that we never use */
8014 static void i915_disable_vga(struct drm_device
*dev
)
8016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8020 if (HAS_PCH_SPLIT(dev
))
8021 vga_reg
= CPU_VGACNTRL
;
8025 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8026 outb(SR01
, VGA_SR_INDEX
);
8027 sr1
= inb(VGA_SR_DATA
);
8028 outb(sr1
| 1<<5, VGA_SR_DATA
);
8029 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8032 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
8033 POSTING_READ(vga_reg
);
8036 void intel_modeset_init_hw(struct drm_device
*dev
)
8038 /* We attempt to init the necessary power wells early in the initialization
8039 * time, so the subsystems that expect power to be enabled can work.
8041 intel_init_power_wells(dev
);
8043 intel_prepare_ddi(dev
);
8045 intel_init_clock_gating(dev
);
8047 mutex_lock(&dev
->struct_mutex
);
8048 intel_enable_gt_powersave(dev
);
8049 mutex_unlock(&dev
->struct_mutex
);
8052 void intel_modeset_init(struct drm_device
*dev
)
8054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8057 drm_mode_config_init(dev
);
8059 dev
->mode_config
.min_width
= 0;
8060 dev
->mode_config
.min_height
= 0;
8062 dev
->mode_config
.preferred_depth
= 24;
8063 dev
->mode_config
.prefer_shadow
= 1;
8065 dev
->mode_config
.funcs
= &intel_mode_funcs
;
8067 intel_init_quirks(dev
);
8071 intel_init_display(dev
);
8074 dev
->mode_config
.max_width
= 2048;
8075 dev
->mode_config
.max_height
= 2048;
8076 } else if (IS_GEN3(dev
)) {
8077 dev
->mode_config
.max_width
= 4096;
8078 dev
->mode_config
.max_height
= 4096;
8080 dev
->mode_config
.max_width
= 8192;
8081 dev
->mode_config
.max_height
= 8192;
8083 dev
->mode_config
.fb_base
= dev_priv
->mm
.gtt_base_addr
;
8085 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8086 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
8088 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
8089 intel_crtc_init(dev
, i
);
8090 ret
= intel_plane_init(dev
, i
);
8092 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
8095 intel_pch_pll_init(dev
);
8097 /* Just disable it once at startup */
8098 i915_disable_vga(dev
);
8099 intel_setup_outputs(dev
);
8103 intel_connector_break_all_links(struct intel_connector
*connector
)
8105 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8106 connector
->base
.encoder
= NULL
;
8107 connector
->encoder
->connectors_active
= false;
8108 connector
->encoder
->base
.crtc
= NULL
;
8111 static void intel_enable_pipe_a(struct drm_device
*dev
)
8113 struct intel_connector
*connector
;
8114 struct drm_connector
*crt
= NULL
;
8115 struct intel_load_detect_pipe load_detect_temp
;
8117 /* We can't just switch on the pipe A, we need to set things up with a
8118 * proper mode and output configuration. As a gross hack, enable pipe A
8119 * by enabling the load detect pipe once. */
8120 list_for_each_entry(connector
,
8121 &dev
->mode_config
.connector_list
,
8123 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
8124 crt
= &connector
->base
;
8132 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
8133 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
8138 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
8140 struct drm_device
*dev
= crtc
->base
.dev
;
8141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8144 /* Clear any frame start delays used for debugging left by the BIOS */
8145 reg
= PIPECONF(crtc
->pipe
);
8146 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
8148 /* We need to sanitize the plane -> pipe mapping first because this will
8149 * disable the crtc (and hence change the state) if it is wrong. */
8150 if (!HAS_PCH_SPLIT(dev
)) {
8151 struct intel_connector
*connector
;
8154 reg
= DSPCNTR(crtc
->plane
);
8155 val
= I915_READ(reg
);
8157 if ((val
& DISPLAY_PLANE_ENABLE
) == 0 &&
8158 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
8161 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8162 crtc
->base
.base
.id
);
8164 /* Pipe has the wrong plane attached and the plane is active.
8165 * Temporarily change the plane mapping and disable everything
8167 plane
= crtc
->plane
;
8168 crtc
->plane
= !plane
;
8169 dev_priv
->display
.crtc_disable(&crtc
->base
);
8170 crtc
->plane
= plane
;
8172 /* ... and break all links. */
8173 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8175 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
8178 intel_connector_break_all_links(connector
);
8181 WARN_ON(crtc
->active
);
8182 crtc
->base
.enabled
= false;
8186 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
8187 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
8188 /* BIOS forgot to enable pipe A, this mostly happens after
8189 * resume. Force-enable the pipe to fix this, the update_dpms
8190 * call below we restore the pipe to the right state, but leave
8191 * the required bits on. */
8192 intel_enable_pipe_a(dev
);
8195 /* Adjust the state of the output pipe according to whether we
8196 * have active connectors/encoders. */
8197 intel_crtc_update_dpms(&crtc
->base
);
8199 if (crtc
->active
!= crtc
->base
.enabled
) {
8200 struct intel_encoder
*encoder
;
8202 /* This can happen either due to bugs in the get_hw_state
8203 * functions or because the pipe is force-enabled due to the
8205 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8207 crtc
->base
.enabled
? "enabled" : "disabled",
8208 crtc
->active
? "enabled" : "disabled");
8210 crtc
->base
.enabled
= crtc
->active
;
8212 /* Because we only establish the connector -> encoder ->
8213 * crtc links if something is active, this means the
8214 * crtc is now deactivated. Break the links. connector
8215 * -> encoder links are only establish when things are
8216 * actually up, hence no need to break them. */
8217 WARN_ON(crtc
->active
);
8219 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
8220 WARN_ON(encoder
->connectors_active
);
8221 encoder
->base
.crtc
= NULL
;
8226 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
8228 struct intel_connector
*connector
;
8229 struct drm_device
*dev
= encoder
->base
.dev
;
8231 /* We need to check both for a crtc link (meaning that the
8232 * encoder is active and trying to read from a pipe) and the
8233 * pipe itself being active. */
8234 bool has_active_crtc
= encoder
->base
.crtc
&&
8235 to_intel_crtc(encoder
->base
.crtc
)->active
;
8237 if (encoder
->connectors_active
&& !has_active_crtc
) {
8238 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8239 encoder
->base
.base
.id
,
8240 drm_get_encoder_name(&encoder
->base
));
8242 /* Connector is active, but has no active pipe. This is
8243 * fallout from our resume register restoring. Disable
8244 * the encoder manually again. */
8245 if (encoder
->base
.crtc
) {
8246 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8247 encoder
->base
.base
.id
,
8248 drm_get_encoder_name(&encoder
->base
));
8249 encoder
->disable(encoder
);
8252 /* Inconsistent output/port/pipe state happens presumably due to
8253 * a bug in one of the get_hw_state functions. Or someplace else
8254 * in our code, like the register restore mess on resume. Clamp
8255 * things to off as a safer default. */
8256 list_for_each_entry(connector
,
8257 &dev
->mode_config
.connector_list
,
8259 if (connector
->encoder
!= encoder
)
8262 intel_connector_break_all_links(connector
);
8265 /* Enabled encoders without active connectors will be fixed in
8266 * the crtc fixup. */
8269 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8270 * and i915 state tracking structures. */
8271 void intel_modeset_setup_hw_state(struct drm_device
*dev
)
8273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8276 struct intel_crtc
*crtc
;
8277 struct intel_encoder
*encoder
;
8278 struct intel_connector
*connector
;
8280 for_each_pipe(pipe
) {
8281 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
8283 tmp
= I915_READ(PIPECONF(pipe
));
8284 if (tmp
& PIPECONF_ENABLE
)
8285 crtc
->active
= true;
8287 crtc
->active
= false;
8289 crtc
->base
.enabled
= crtc
->active
;
8291 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8293 crtc
->active
? "enabled" : "disabled");
8296 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8300 if (encoder
->get_hw_state(encoder
, &pipe
)) {
8301 encoder
->base
.crtc
=
8302 dev_priv
->pipe_to_crtc_mapping
[pipe
];
8304 encoder
->base
.crtc
= NULL
;
8307 encoder
->connectors_active
= false;
8308 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8309 encoder
->base
.base
.id
,
8310 drm_get_encoder_name(&encoder
->base
),
8311 encoder
->base
.crtc
? "enabled" : "disabled",
8315 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8317 if (connector
->get_hw_state(connector
)) {
8318 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
8319 connector
->encoder
->connectors_active
= true;
8320 connector
->base
.encoder
= &connector
->encoder
->base
;
8322 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8323 connector
->base
.encoder
= NULL
;
8325 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8326 connector
->base
.base
.id
,
8327 drm_get_connector_name(&connector
->base
),
8328 connector
->base
.encoder
? "enabled" : "disabled");
8331 /* HW state is read out, now we need to sanitize this mess. */
8332 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8334 intel_sanitize_encoder(encoder
);
8337 for_each_pipe(pipe
) {
8338 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
8339 intel_sanitize_crtc(crtc
);
8342 intel_modeset_update_staged_output_state(dev
);
8344 intel_modeset_check_state(dev
);
8347 void intel_modeset_gem_init(struct drm_device
*dev
)
8349 intel_modeset_init_hw(dev
);
8351 intel_setup_overlay(dev
);
8353 intel_modeset_setup_hw_state(dev
);
8356 void intel_modeset_cleanup(struct drm_device
*dev
)
8358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8359 struct drm_crtc
*crtc
;
8360 struct intel_crtc
*intel_crtc
;
8362 drm_kms_helper_poll_fini(dev
);
8363 mutex_lock(&dev
->struct_mutex
);
8365 intel_unregister_dsm_handler();
8368 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
8369 /* Skip inactive CRTCs */
8373 intel_crtc
= to_intel_crtc(crtc
);
8374 intel_increase_pllclock(crtc
);
8377 intel_disable_fbc(dev
);
8379 intel_disable_gt_powersave(dev
);
8381 ironlake_teardown_rc6(dev
);
8383 if (IS_VALLEYVIEW(dev
))
8386 mutex_unlock(&dev
->struct_mutex
);
8388 /* Disable the irq before mode object teardown, for the irq might
8389 * enqueue unpin/hotplug work. */
8390 drm_irq_uninstall(dev
);
8391 cancel_work_sync(&dev_priv
->hotplug_work
);
8392 cancel_work_sync(&dev_priv
->rps
.work
);
8394 /* flush any delayed tasks or pending work */
8395 flush_scheduled_work();
8397 drm_mode_config_cleanup(dev
);
8401 * Return which encoder is currently attached for connector.
8403 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
8405 return &intel_attached_encoder(connector
)->base
;
8408 void intel_connector_attach_encoder(struct intel_connector
*connector
,
8409 struct intel_encoder
*encoder
)
8411 connector
->encoder
= encoder
;
8412 drm_mode_connector_attach_encoder(&connector
->base
,
8417 * set vga decode state - true == enable VGA decode
8419 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
8421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8424 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
8426 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
8428 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
8429 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
8433 #ifdef CONFIG_DEBUG_FS
8434 #include <linux/seq_file.h>
8436 struct intel_display_error_state
{
8437 struct intel_cursor_error_state
{
8442 } cursor
[I915_MAX_PIPES
];
8444 struct intel_pipe_error_state
{
8454 } pipe
[I915_MAX_PIPES
];
8456 struct intel_plane_error_state
{
8464 } plane
[I915_MAX_PIPES
];
8467 struct intel_display_error_state
*
8468 intel_display_capture_error_state(struct drm_device
*dev
)
8470 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8471 struct intel_display_error_state
*error
;
8474 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
8479 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
8480 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
8481 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
8483 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
8484 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
8485 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
8486 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
8487 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
8488 if (INTEL_INFO(dev
)->gen
>= 4) {
8489 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
8490 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
8493 error
->pipe
[i
].conf
= I915_READ(PIPECONF(i
));
8494 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
8495 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(i
));
8496 error
->pipe
[i
].hblank
= I915_READ(HBLANK(i
));
8497 error
->pipe
[i
].hsync
= I915_READ(HSYNC(i
));
8498 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(i
));
8499 error
->pipe
[i
].vblank
= I915_READ(VBLANK(i
));
8500 error
->pipe
[i
].vsync
= I915_READ(VSYNC(i
));
8507 intel_display_print_error_state(struct seq_file
*m
,
8508 struct drm_device
*dev
,
8509 struct intel_display_error_state
*error
)
8511 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8514 seq_printf(m
, "Num Pipes: %d\n", dev_priv
->num_pipe
);
8516 seq_printf(m
, "Pipe [%d]:\n", i
);
8517 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
8518 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
8519 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
8520 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
8521 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
8522 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
8523 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
8524 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
8526 seq_printf(m
, "Plane [%d]:\n", i
);
8527 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
8528 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
8529 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
8530 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
8531 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
8532 if (INTEL_INFO(dev
)->gen
>= 4) {
8533 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
8534 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
8537 seq_printf(m
, "Cursor [%d]:\n", i
);
8538 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
8539 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
8540 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);