2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
34 #include "intel_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
40 #include "drm_crtc_helper.h"
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
45 static void intel_update_watermarks(struct drm_device
*dev
);
46 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
47 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t
;
73 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
75 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
76 int, int, intel_clock_t
*);
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
90 #define I8XX_M2_MAX 16
92 #define I8XX_P_MAX 128
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
253 /* We have parameter ranges for different type of outputs. */
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
332 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
333 int target
, int refclk
, intel_clock_t
*best_clock
);
335 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
336 int target
, int refclk
, intel_clock_t
*best_clock
);
339 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
340 int target
, int refclk
, intel_clock_t
*best_clock
);
342 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
343 int target
, int refclk
, intel_clock_t
*best_clock
);
345 static inline u32
/* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device
*dev
)
348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
349 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
352 static const intel_limit_t intel_limits_i8xx_dvo
= {
353 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
354 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
355 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
356 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
357 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
358 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
359 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
360 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
361 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
362 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
363 .find_pll
= intel_find_best_PLL
,
366 static const intel_limit_t intel_limits_i8xx_lvds
= {
367 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
368 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
369 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
370 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
371 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
372 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
373 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
374 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
375 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
376 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
377 .find_pll
= intel_find_best_PLL
,
380 static const intel_limit_t intel_limits_i9xx_sdvo
= {
381 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
382 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
383 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
384 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
385 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
386 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
387 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
388 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
389 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
390 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
391 .find_pll
= intel_find_best_PLL
,
394 static const intel_limit_t intel_limits_i9xx_lvds
= {
395 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
396 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
397 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
398 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
399 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
400 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
401 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
402 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
403 /* The single-channel range is 25-112Mhz, and dual-channel
404 * is 80-224Mhz. Prefer single channel as much as possible.
406 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
407 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
408 .find_pll
= intel_find_best_PLL
,
411 /* below parameter and function is for G4X Chipset Family*/
412 static const intel_limit_t intel_limits_g4x_sdvo
= {
413 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
414 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
415 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
416 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
417 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
418 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
419 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
420 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
421 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
422 .p2_slow
= G4X_P2_SDVO_SLOW
,
423 .p2_fast
= G4X_P2_SDVO_FAST
425 .find_pll
= intel_g4x_find_best_PLL
,
428 static const intel_limit_t intel_limits_g4x_hdmi
= {
429 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
430 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
431 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
432 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
433 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
434 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
435 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
436 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
437 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
438 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
439 .p2_fast
= G4X_P2_HDMI_DAC_FAST
441 .find_pll
= intel_g4x_find_best_PLL
,
444 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
445 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
446 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
447 .vco
= { .min
= G4X_VCO_MIN
,
448 .max
= G4X_VCO_MAX
},
449 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
450 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
451 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
452 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
453 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
454 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
455 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
456 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
457 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
458 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
459 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
460 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
461 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
462 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
463 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
465 .find_pll
= intel_g4x_find_best_PLL
,
468 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
469 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
470 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
471 .vco
= { .min
= G4X_VCO_MIN
,
472 .max
= G4X_VCO_MAX
},
473 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
474 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
475 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
476 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
477 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
478 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
479 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
480 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
481 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
482 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
483 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
484 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
485 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
486 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
487 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
489 .find_pll
= intel_g4x_find_best_PLL
,
492 static const intel_limit_t intel_limits_g4x_display_port
= {
493 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
494 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
495 .vco
= { .min
= G4X_VCO_MIN
,
497 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
498 .max
= G4X_N_DISPLAY_PORT_MAX
},
499 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
500 .max
= G4X_M_DISPLAY_PORT_MAX
},
501 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
502 .max
= G4X_M1_DISPLAY_PORT_MAX
},
503 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
504 .max
= G4X_M2_DISPLAY_PORT_MAX
},
505 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
506 .max
= G4X_P_DISPLAY_PORT_MAX
},
507 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
508 .max
= G4X_P1_DISPLAY_PORT_MAX
},
509 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
510 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
511 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
512 .find_pll
= intel_find_pll_g4x_dp
,
515 static const intel_limit_t intel_limits_pineview_sdvo
= {
516 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
517 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
518 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
519 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
520 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
521 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
522 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
523 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
524 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
525 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
526 .find_pll
= intel_find_best_PLL
,
529 static const intel_limit_t intel_limits_pineview_lvds
= {
530 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
531 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
532 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
533 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
534 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
535 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
536 .p
= { .min
= PINEVIEW_P_LVDS_MIN
, .max
= PINEVIEW_P_LVDS_MAX
},
537 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
538 /* Pineview only supports single-channel mode. */
539 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
540 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
541 .find_pll
= intel_find_best_PLL
,
544 static const intel_limit_t intel_limits_ironlake_dac
= {
545 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
546 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
547 .n
= { .min
= IRONLAKE_DAC_N_MIN
, .max
= IRONLAKE_DAC_N_MAX
},
548 .m
= { .min
= IRONLAKE_DAC_M_MIN
, .max
= IRONLAKE_DAC_M_MAX
},
549 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
550 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
551 .p
= { .min
= IRONLAKE_DAC_P_MIN
, .max
= IRONLAKE_DAC_P_MAX
},
552 .p1
= { .min
= IRONLAKE_DAC_P1_MIN
, .max
= IRONLAKE_DAC_P1_MAX
},
553 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
554 .p2_slow
= IRONLAKE_DAC_P2_SLOW
,
555 .p2_fast
= IRONLAKE_DAC_P2_FAST
},
556 .find_pll
= intel_g4x_find_best_PLL
,
559 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
560 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
561 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
562 .n
= { .min
= IRONLAKE_LVDS_S_N_MIN
, .max
= IRONLAKE_LVDS_S_N_MAX
},
563 .m
= { .min
= IRONLAKE_LVDS_S_M_MIN
, .max
= IRONLAKE_LVDS_S_M_MAX
},
564 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
565 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
566 .p
= { .min
= IRONLAKE_LVDS_S_P_MIN
, .max
= IRONLAKE_LVDS_S_P_MAX
},
567 .p1
= { .min
= IRONLAKE_LVDS_S_P1_MIN
, .max
= IRONLAKE_LVDS_S_P1_MAX
},
568 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
569 .p2_slow
= IRONLAKE_LVDS_S_P2_SLOW
,
570 .p2_fast
= IRONLAKE_LVDS_S_P2_FAST
},
571 .find_pll
= intel_g4x_find_best_PLL
,
574 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
575 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
576 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
577 .n
= { .min
= IRONLAKE_LVDS_D_N_MIN
, .max
= IRONLAKE_LVDS_D_N_MAX
},
578 .m
= { .min
= IRONLAKE_LVDS_D_M_MIN
, .max
= IRONLAKE_LVDS_D_M_MAX
},
579 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
580 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
581 .p
= { .min
= IRONLAKE_LVDS_D_P_MIN
, .max
= IRONLAKE_LVDS_D_P_MAX
},
582 .p1
= { .min
= IRONLAKE_LVDS_D_P1_MIN
, .max
= IRONLAKE_LVDS_D_P1_MAX
},
583 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
584 .p2_slow
= IRONLAKE_LVDS_D_P2_SLOW
,
585 .p2_fast
= IRONLAKE_LVDS_D_P2_FAST
},
586 .find_pll
= intel_g4x_find_best_PLL
,
589 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
590 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
591 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
592 .n
= { .min
= IRONLAKE_LVDS_S_SSC_N_MIN
, .max
= IRONLAKE_LVDS_S_SSC_N_MAX
},
593 .m
= { .min
= IRONLAKE_LVDS_S_SSC_M_MIN
, .max
= IRONLAKE_LVDS_S_SSC_M_MAX
},
594 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
595 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
596 .p
= { .min
= IRONLAKE_LVDS_S_SSC_P_MIN
, .max
= IRONLAKE_LVDS_S_SSC_P_MAX
},
597 .p1
= { .min
= IRONLAKE_LVDS_S_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_S_SSC_P1_MAX
},
598 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
599 .p2_slow
= IRONLAKE_LVDS_S_SSC_P2_SLOW
,
600 .p2_fast
= IRONLAKE_LVDS_S_SSC_P2_FAST
},
601 .find_pll
= intel_g4x_find_best_PLL
,
604 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
605 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
606 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
607 .n
= { .min
= IRONLAKE_LVDS_D_SSC_N_MIN
, .max
= IRONLAKE_LVDS_D_SSC_N_MAX
},
608 .m
= { .min
= IRONLAKE_LVDS_D_SSC_M_MIN
, .max
= IRONLAKE_LVDS_D_SSC_M_MAX
},
609 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
610 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
611 .p
= { .min
= IRONLAKE_LVDS_D_SSC_P_MIN
, .max
= IRONLAKE_LVDS_D_SSC_P_MAX
},
612 .p1
= { .min
= IRONLAKE_LVDS_D_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_D_SSC_P1_MAX
},
613 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
614 .p2_slow
= IRONLAKE_LVDS_D_SSC_P2_SLOW
,
615 .p2_fast
= IRONLAKE_LVDS_D_SSC_P2_FAST
},
616 .find_pll
= intel_g4x_find_best_PLL
,
619 static const intel_limit_t intel_limits_ironlake_display_port
= {
620 .dot
= { .min
= IRONLAKE_DOT_MIN
,
621 .max
= IRONLAKE_DOT_MAX
},
622 .vco
= { .min
= IRONLAKE_VCO_MIN
,
623 .max
= IRONLAKE_VCO_MAX
},
624 .n
= { .min
= IRONLAKE_DP_N_MIN
,
625 .max
= IRONLAKE_DP_N_MAX
},
626 .m
= { .min
= IRONLAKE_DP_M_MIN
,
627 .max
= IRONLAKE_DP_M_MAX
},
628 .m1
= { .min
= IRONLAKE_M1_MIN
,
629 .max
= IRONLAKE_M1_MAX
},
630 .m2
= { .min
= IRONLAKE_M2_MIN
,
631 .max
= IRONLAKE_M2_MAX
},
632 .p
= { .min
= IRONLAKE_DP_P_MIN
,
633 .max
= IRONLAKE_DP_P_MAX
},
634 .p1
= { .min
= IRONLAKE_DP_P1_MIN
,
635 .max
= IRONLAKE_DP_P1_MAX
},
636 .p2
= { .dot_limit
= IRONLAKE_DP_P2_LIMIT
,
637 .p2_slow
= IRONLAKE_DP_P2_SLOW
,
638 .p2_fast
= IRONLAKE_DP_P2_FAST
},
639 .find_pll
= intel_find_pll_ironlake_dp
,
642 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
)
644 struct drm_device
*dev
= crtc
->dev
;
645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
646 const intel_limit_t
*limit
;
649 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
650 if (dev_priv
->lvds_use_ssc
&& dev_priv
->lvds_ssc_freq
== 100)
653 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
654 LVDS_CLKB_POWER_UP
) {
655 /* LVDS dual channel */
657 limit
= &intel_limits_ironlake_dual_lvds_100m
;
659 limit
= &intel_limits_ironlake_dual_lvds
;
662 limit
= &intel_limits_ironlake_single_lvds_100m
;
664 limit
= &intel_limits_ironlake_single_lvds
;
666 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
668 limit
= &intel_limits_ironlake_display_port
;
670 limit
= &intel_limits_ironlake_dac
;
675 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
677 struct drm_device
*dev
= crtc
->dev
;
678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
679 const intel_limit_t
*limit
;
681 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
682 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
684 /* LVDS with dual channel */
685 limit
= &intel_limits_g4x_dual_channel_lvds
;
687 /* LVDS with dual channel */
688 limit
= &intel_limits_g4x_single_channel_lvds
;
689 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
690 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
691 limit
= &intel_limits_g4x_hdmi
;
692 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
693 limit
= &intel_limits_g4x_sdvo
;
694 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
695 limit
= &intel_limits_g4x_display_port
;
696 } else /* The option is for other outputs */
697 limit
= &intel_limits_i9xx_sdvo
;
702 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
704 struct drm_device
*dev
= crtc
->dev
;
705 const intel_limit_t
*limit
;
707 if (HAS_PCH_SPLIT(dev
))
708 limit
= intel_ironlake_limit(crtc
);
709 else if (IS_G4X(dev
)) {
710 limit
= intel_g4x_limit(crtc
);
711 } else if (IS_PINEVIEW(dev
)) {
712 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
713 limit
= &intel_limits_pineview_lvds
;
715 limit
= &intel_limits_pineview_sdvo
;
716 } else if (!IS_GEN2(dev
)) {
717 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
718 limit
= &intel_limits_i9xx_lvds
;
720 limit
= &intel_limits_i9xx_sdvo
;
722 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
723 limit
= &intel_limits_i8xx_lvds
;
725 limit
= &intel_limits_i8xx_dvo
;
730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
731 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
733 clock
->m
= clock
->m2
+ 2;
734 clock
->p
= clock
->p1
* clock
->p2
;
735 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
736 clock
->dot
= clock
->vco
/ clock
->p
;
739 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
741 if (IS_PINEVIEW(dev
)) {
742 pineview_clock(refclk
, clock
);
745 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
746 clock
->p
= clock
->p1
* clock
->p2
;
747 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
748 clock
->dot
= clock
->vco
/ clock
->p
;
752 * Returns whether any output on the specified pipe is of the specified type
754 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
756 struct drm_device
*dev
= crtc
->dev
;
757 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
758 struct intel_encoder
*encoder
;
760 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
761 if (encoder
->base
.crtc
== crtc
&& encoder
->type
== type
)
767 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
773 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
775 const intel_limit_t
*limit
= intel_limit (crtc
);
776 struct drm_device
*dev
= crtc
->dev
;
778 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
779 INTELPllInvalid ("p1 out of range\n");
780 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
781 INTELPllInvalid ("p out of range\n");
782 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
783 INTELPllInvalid ("m2 out of range\n");
784 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
785 INTELPllInvalid ("m1 out of range\n");
786 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
787 INTELPllInvalid ("m1 <= m2\n");
788 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
789 INTELPllInvalid ("m out of range\n");
790 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
791 INTELPllInvalid ("n out of range\n");
792 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
793 INTELPllInvalid ("vco out of range\n");
794 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
795 * connector, etc., rather than just a single range.
797 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
798 INTELPllInvalid ("dot out of range\n");
804 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
805 int target
, int refclk
, intel_clock_t
*best_clock
)
808 struct drm_device
*dev
= crtc
->dev
;
809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
813 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
814 (I915_READ(LVDS
)) != 0) {
816 * For LVDS, if the panel is on, just rely on its current
817 * settings for dual-channel. We haven't figured out how to
818 * reliably set up different single/dual channel state, if we
821 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
823 clock
.p2
= limit
->p2
.p2_fast
;
825 clock
.p2
= limit
->p2
.p2_slow
;
827 if (target
< limit
->p2
.dot_limit
)
828 clock
.p2
= limit
->p2
.p2_slow
;
830 clock
.p2
= limit
->p2
.p2_fast
;
833 memset (best_clock
, 0, sizeof (*best_clock
));
835 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
837 for (clock
.m2
= limit
->m2
.min
;
838 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
839 /* m1 is always 0 in Pineview */
840 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
842 for (clock
.n
= limit
->n
.min
;
843 clock
.n
<= limit
->n
.max
; clock
.n
++) {
844 for (clock
.p1
= limit
->p1
.min
;
845 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
848 intel_clock(dev
, refclk
, &clock
);
850 if (!intel_PLL_is_valid(crtc
, &clock
))
853 this_err
= abs(clock
.dot
- target
);
854 if (this_err
< err
) {
863 return (err
!= target
);
867 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
868 int target
, int refclk
, intel_clock_t
*best_clock
)
870 struct drm_device
*dev
= crtc
->dev
;
871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
875 /* approximately equals target * 0.00585 */
876 int err_most
= (target
>> 8) + (target
>> 9);
879 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
882 if (HAS_PCH_SPLIT(dev
))
886 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
888 clock
.p2
= limit
->p2
.p2_fast
;
890 clock
.p2
= limit
->p2
.p2_slow
;
892 if (target
< limit
->p2
.dot_limit
)
893 clock
.p2
= limit
->p2
.p2_slow
;
895 clock
.p2
= limit
->p2
.p2_fast
;
898 memset(best_clock
, 0, sizeof(*best_clock
));
899 max_n
= limit
->n
.max
;
900 /* based on hardware requirement, prefer smaller n to precision */
901 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
902 /* based on hardware requirement, prefere larger m1,m2 */
903 for (clock
.m1
= limit
->m1
.max
;
904 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
905 for (clock
.m2
= limit
->m2
.max
;
906 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
907 for (clock
.p1
= limit
->p1
.max
;
908 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
911 intel_clock(dev
, refclk
, &clock
);
912 if (!intel_PLL_is_valid(crtc
, &clock
))
914 this_err
= abs(clock
.dot
- target
) ;
915 if (this_err
< err_most
) {
929 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
930 int target
, int refclk
, intel_clock_t
*best_clock
)
932 struct drm_device
*dev
= crtc
->dev
;
935 /* return directly when it is eDP */
939 if (target
< 200000) {
952 intel_clock(dev
, refclk
, &clock
);
953 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
957 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
959 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
960 int target
, int refclk
, intel_clock_t
*best_clock
)
963 if (target
< 200000) {
976 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
977 clock
.p
= (clock
.p1
* clock
.p2
);
978 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
980 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
985 * intel_wait_for_vblank - wait for vblank on a given pipe
987 * @pipe: pipe to wait for
989 * Wait for vblank to occur on a given pipe. Needed for various bits of
992 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
995 int pipestat_reg
= (pipe
== 0 ? PIPEASTAT
: PIPEBSTAT
);
997 /* Clear existing vblank status. Note this will clear any other
998 * sticky status fields as well.
1000 * This races with i915_driver_irq_handler() with the result
1001 * that either function could miss a vblank event. Here it is not
1002 * fatal, as we will either wait upon the next vblank interrupt or
1003 * timeout. Generally speaking intel_wait_for_vblank() is only
1004 * called during modeset at which time the GPU should be idle and
1005 * should *not* be performing page flips and thus not waiting on
1007 * Currently, the result of us stealing a vblank from the irq
1008 * handler is that a single frame will be skipped during swapbuffers.
1010 I915_WRITE(pipestat_reg
,
1011 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
1013 /* Wait for vblank interrupt bit to set */
1014 if (wait_for(I915_READ(pipestat_reg
) &
1015 PIPE_VBLANK_INTERRUPT_STATUS
,
1017 DRM_DEBUG_KMS("vblank wait timed out\n");
1021 * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1023 * @pipe: pipe to wait for
1025 * After disabling a pipe, we can't wait for vblank in the usual way,
1026 * spinning on the vblank interrupt status bit, since we won't actually
1027 * see an interrupt when the pipe is disabled.
1029 * So this function waits for the display line value to settle (it
1030 * usually ends up stopping at the start of the next frame).
1032 void intel_wait_for_vblank_off(struct drm_device
*dev
, int pipe
)
1034 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1035 int pipedsl_reg
= (pipe
== 0 ? PIPEADSL
: PIPEBDSL
);
1036 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1037 u32 last_line
, line
;
1039 /* Wait for the display line to settle */
1040 line
= I915_READ(pipedsl_reg
) & DSL_LINEMASK
;
1044 line
= I915_READ(pipedsl_reg
) & DSL_LINEMASK
;
1045 } while (line
!= last_line
&& time_after(timeout
, jiffies
));
1047 if (line
!= last_line
)
1048 DRM_DEBUG_KMS("vblank wait timed out\n");
1051 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1053 struct drm_device
*dev
= crtc
->dev
;
1054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1055 struct drm_framebuffer
*fb
= crtc
->fb
;
1056 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1057 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1058 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1060 u32 fbc_ctl
, fbc_ctl2
;
1062 if (fb
->pitch
== dev_priv
->cfb_pitch
&&
1063 obj_priv
->fence_reg
== dev_priv
->cfb_fence
&&
1064 intel_crtc
->plane
== dev_priv
->cfb_plane
&&
1065 I915_READ(FBC_CONTROL
) & FBC_CTL_EN
)
1068 i8xx_disable_fbc(dev
);
1070 dev_priv
->cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
1072 if (fb
->pitch
< dev_priv
->cfb_pitch
)
1073 dev_priv
->cfb_pitch
= fb
->pitch
;
1075 /* FBC_CTL wants 64B units */
1076 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1077 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1078 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1079 plane
= dev_priv
->cfb_plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1081 /* Clear old tags */
1082 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1083 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1086 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| plane
;
1087 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1088 fbc_ctl2
|= FBC_CTL_CPU_FENCE
;
1089 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1090 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1093 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1095 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
1096 fbc_ctl
|= (dev_priv
->cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1097 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1098 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1099 fbc_ctl
|= dev_priv
->cfb_fence
;
1100 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1102 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1103 dev_priv
->cfb_pitch
, crtc
->y
, dev_priv
->cfb_plane
);
1106 void i8xx_disable_fbc(struct drm_device
*dev
)
1108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1111 /* Disable compression */
1112 fbc_ctl
= I915_READ(FBC_CONTROL
);
1113 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
1116 fbc_ctl
&= ~FBC_CTL_EN
;
1117 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1119 /* Wait for compressing bit to clear */
1120 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
1121 DRM_DEBUG_KMS("FBC idle timed out\n");
1125 DRM_DEBUG_KMS("disabled FBC\n");
1128 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
1130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1132 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1135 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1137 struct drm_device
*dev
= crtc
->dev
;
1138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1139 struct drm_framebuffer
*fb
= crtc
->fb
;
1140 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1141 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1142 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1143 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1144 unsigned long stall_watermark
= 200;
1147 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1148 if (dpfc_ctl
& DPFC_CTL_EN
) {
1149 if (dev_priv
->cfb_pitch
== dev_priv
->cfb_pitch
/ 64 - 1 &&
1150 dev_priv
->cfb_fence
== obj_priv
->fence_reg
&&
1151 dev_priv
->cfb_plane
== intel_crtc
->plane
&&
1152 dev_priv
->cfb_y
== crtc
->y
)
1155 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
& ~DPFC_CTL_EN
);
1156 POSTING_READ(DPFC_CONTROL
);
1157 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1160 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1161 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1162 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1163 dev_priv
->cfb_y
= crtc
->y
;
1165 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1166 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1167 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
;
1168 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1170 I915_WRITE(DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1173 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1174 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1175 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1176 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1179 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1181 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1184 void g4x_disable_fbc(struct drm_device
*dev
)
1186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1189 /* Disable compression */
1190 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1191 if (dpfc_ctl
& DPFC_CTL_EN
) {
1192 dpfc_ctl
&= ~DPFC_CTL_EN
;
1193 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1195 DRM_DEBUG_KMS("disabled FBC\n");
1199 static bool g4x_fbc_enabled(struct drm_device
*dev
)
1201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1203 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1206 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1208 struct drm_device
*dev
= crtc
->dev
;
1209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1210 struct drm_framebuffer
*fb
= crtc
->fb
;
1211 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1212 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1213 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1214 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1215 unsigned long stall_watermark
= 200;
1218 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1219 if (dpfc_ctl
& DPFC_CTL_EN
) {
1220 if (dev_priv
->cfb_pitch
== dev_priv
->cfb_pitch
/ 64 - 1 &&
1221 dev_priv
->cfb_fence
== obj_priv
->fence_reg
&&
1222 dev_priv
->cfb_plane
== intel_crtc
->plane
&&
1223 dev_priv
->cfb_offset
== obj_priv
->gtt_offset
&&
1224 dev_priv
->cfb_y
== crtc
->y
)
1227 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
& ~DPFC_CTL_EN
);
1228 POSTING_READ(ILK_DPFC_CONTROL
);
1229 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1232 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1233 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1234 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1235 dev_priv
->cfb_offset
= obj_priv
->gtt_offset
;
1236 dev_priv
->cfb_y
= crtc
->y
;
1238 dpfc_ctl
&= DPFC_RESERVED
;
1239 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
1240 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1241 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
);
1242 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1244 I915_WRITE(ILK_DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1247 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1248 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1249 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1250 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
1251 I915_WRITE(ILK_FBC_RT_BASE
, obj_priv
->gtt_offset
| ILK_FBC_RT_VALID
);
1253 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
1255 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1258 void ironlake_disable_fbc(struct drm_device
*dev
)
1260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1263 /* Disable compression */
1264 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1265 if (dpfc_ctl
& DPFC_CTL_EN
) {
1266 dpfc_ctl
&= ~DPFC_CTL_EN
;
1267 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
1269 DRM_DEBUG_KMS("disabled FBC\n");
1273 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
1275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1277 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
1280 bool intel_fbc_enabled(struct drm_device
*dev
)
1282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1284 if (!dev_priv
->display
.fbc_enabled
)
1287 return dev_priv
->display
.fbc_enabled(dev
);
1290 void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1292 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1294 if (!dev_priv
->display
.enable_fbc
)
1297 dev_priv
->display
.enable_fbc(crtc
, interval
);
1300 void intel_disable_fbc(struct drm_device
*dev
)
1302 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1304 if (!dev_priv
->display
.disable_fbc
)
1307 dev_priv
->display
.disable_fbc(dev
);
1311 * intel_update_fbc - enable/disable FBC as needed
1312 * @dev: the drm_device
1314 * Set up the framebuffer compression hardware at mode set time. We
1315 * enable it if possible:
1316 * - plane A only (on pre-965)
1317 * - no pixel mulitply/line duplication
1318 * - no alpha buffer discard
1320 * - framebuffer <= 2048 in width, 1536 in height
1322 * We can't assume that any compression will take place (worst case),
1323 * so the compressed buffer has to be the same size as the uncompressed
1324 * one. It also must reside (along with the line length buffer) in
1327 * We need to enable/disable FBC on a global basis.
1329 static void intel_update_fbc(struct drm_device
*dev
)
1331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1332 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
1333 struct intel_crtc
*intel_crtc
;
1334 struct drm_framebuffer
*fb
;
1335 struct intel_framebuffer
*intel_fb
;
1336 struct drm_i915_gem_object
*obj_priv
;
1338 DRM_DEBUG_KMS("\n");
1340 if (!i915_powersave
)
1343 if (!I915_HAS_FBC(dev
))
1347 * If FBC is already on, we just have to verify that we can
1348 * keep it that way...
1349 * Need to disable if:
1350 * - more than one pipe is active
1351 * - changing FBC params (stride, fence, mode)
1352 * - new fb is too large to fit in compressed buffer
1353 * - going to an unsupported config (interlace, pixel multiply, etc.)
1355 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1356 if (tmp_crtc
->enabled
) {
1358 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1359 dev_priv
->no_fbc_reason
= FBC_MULTIPLE_PIPES
;
1366 if (!crtc
|| crtc
->fb
== NULL
) {
1367 DRM_DEBUG_KMS("no output, disabling\n");
1368 dev_priv
->no_fbc_reason
= FBC_NO_OUTPUT
;
1372 intel_crtc
= to_intel_crtc(crtc
);
1374 intel_fb
= to_intel_framebuffer(fb
);
1375 obj_priv
= to_intel_bo(intel_fb
->obj
);
1377 if (intel_fb
->obj
->size
> dev_priv
->cfb_size
) {
1378 DRM_DEBUG_KMS("framebuffer too large, disabling "
1380 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1383 if ((crtc
->mode
.flags
& DRM_MODE_FLAG_INTERLACE
) ||
1384 (crtc
->mode
.flags
& DRM_MODE_FLAG_DBLSCAN
)) {
1385 DRM_DEBUG_KMS("mode incompatible with compression, "
1387 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
1390 if ((crtc
->mode
.hdisplay
> 2048) ||
1391 (crtc
->mode
.vdisplay
> 1536)) {
1392 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1393 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
1396 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && intel_crtc
->plane
!= 0) {
1397 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1398 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
1401 if (obj_priv
->tiling_mode
!= I915_TILING_X
) {
1402 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1403 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
1407 /* If the kernel debugger is active, always disable compression */
1408 if (in_dbg_master())
1411 intel_enable_fbc(crtc
, 500);
1415 /* Multiple disables should be harmless */
1416 if (intel_fbc_enabled(dev
)) {
1417 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1418 intel_disable_fbc(dev
);
1423 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1424 struct drm_gem_object
*obj
,
1427 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1431 switch (obj_priv
->tiling_mode
) {
1432 case I915_TILING_NONE
:
1433 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1434 alignment
= 128 * 1024;
1435 else if (INTEL_INFO(dev
)->gen
>= 4)
1436 alignment
= 4 * 1024;
1438 alignment
= 64 * 1024;
1441 /* pin() will align the object as required by fence */
1445 /* FIXME: Is this true? */
1446 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1452 ret
= i915_gem_object_pin(obj
, alignment
);
1456 ret
= i915_gem_object_set_to_display_plane(obj
, pipelined
);
1460 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1461 * fence, whereas 965+ only requires a fence if using
1462 * framebuffer compression. For simplicity, we always install
1463 * a fence as the cost is not that onerous.
1465 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
1466 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1467 ret
= i915_gem_object_get_fence_reg(obj
, false);
1475 i915_gem_object_unpin(obj
);
1479 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1481 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1484 struct drm_device
*dev
= crtc
->dev
;
1485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1486 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1487 struct intel_framebuffer
*intel_fb
;
1488 struct drm_i915_gem_object
*obj_priv
;
1489 struct drm_gem_object
*obj
;
1490 int plane
= intel_crtc
->plane
;
1491 unsigned long Start
, Offset
;
1500 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1504 intel_fb
= to_intel_framebuffer(fb
);
1505 obj
= intel_fb
->obj
;
1506 obj_priv
= to_intel_bo(obj
);
1508 reg
= DSPCNTR(plane
);
1509 dspcntr
= I915_READ(reg
);
1510 /* Mask out pixel format bits in case we change it */
1511 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1512 switch (fb
->bits_per_pixel
) {
1514 dspcntr
|= DISPPLANE_8BPP
;
1517 if (fb
->depth
== 15)
1518 dspcntr
|= DISPPLANE_15_16BPP
;
1520 dspcntr
|= DISPPLANE_16BPP
;
1524 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1527 DRM_ERROR("Unknown color depth\n");
1530 if (INTEL_INFO(dev
)->gen
>= 4) {
1531 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1532 dspcntr
|= DISPPLANE_TILED
;
1534 dspcntr
&= ~DISPPLANE_TILED
;
1537 if (HAS_PCH_SPLIT(dev
))
1539 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1541 I915_WRITE(reg
, dspcntr
);
1543 Start
= obj_priv
->gtt_offset
;
1544 Offset
= y
* fb
->pitch
+ x
* (fb
->bits_per_pixel
/ 8);
1546 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1547 Start
, Offset
, x
, y
, fb
->pitch
);
1548 I915_WRITE(DSPSTRIDE(plane
), fb
->pitch
);
1549 if (INTEL_INFO(dev
)->gen
>= 4) {
1550 I915_WRITE(DSPSURF(plane
), Start
);
1551 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
1552 I915_WRITE(DSPADDR(plane
), Offset
);
1554 I915_WRITE(DSPADDR(plane
), Start
+ Offset
);
1557 intel_update_fbc(dev
);
1558 intel_increase_pllclock(crtc
);
1564 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1565 struct drm_framebuffer
*old_fb
)
1567 struct drm_device
*dev
= crtc
->dev
;
1568 struct drm_i915_master_private
*master_priv
;
1569 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1574 DRM_DEBUG_KMS("No FB bound\n");
1578 switch (intel_crtc
->plane
) {
1586 mutex_lock(&dev
->struct_mutex
);
1587 ret
= intel_pin_and_fence_fb_obj(dev
,
1588 to_intel_framebuffer(crtc
->fb
)->obj
,
1591 mutex_unlock(&dev
->struct_mutex
);
1596 struct drm_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
1597 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1599 if (atomic_read(&obj_priv
->pending_flip
)) {
1600 ret
= i915_gem_wait_for_pending_flip(dev
, &obj
, 1);
1602 i915_gem_object_unpin(to_intel_framebuffer(crtc
->fb
)->obj
);
1603 mutex_unlock(&dev
->struct_mutex
);
1609 ret
= intel_pipe_set_base_atomic(crtc
, crtc
->fb
, x
, y
);
1611 i915_gem_object_unpin(to_intel_framebuffer(crtc
->fb
)->obj
);
1612 mutex_unlock(&dev
->struct_mutex
);
1617 i915_gem_object_unpin(to_intel_framebuffer(old_fb
)->obj
);
1619 mutex_unlock(&dev
->struct_mutex
);
1621 if (!dev
->primary
->master
)
1624 master_priv
= dev
->primary
->master
->driver_priv
;
1625 if (!master_priv
->sarea_priv
)
1628 if (intel_crtc
->pipe
) {
1629 master_priv
->sarea_priv
->pipeB_x
= x
;
1630 master_priv
->sarea_priv
->pipeB_y
= y
;
1632 master_priv
->sarea_priv
->pipeA_x
= x
;
1633 master_priv
->sarea_priv
->pipeA_y
= y
;
1639 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
1641 struct drm_device
*dev
= crtc
->dev
;
1642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1645 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
1646 dpa_ctl
= I915_READ(DP_A
);
1647 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1649 if (clock
< 200000) {
1651 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1652 /* workaround for 160Mhz:
1653 1) program 0x4600c bits 15:0 = 0x8124
1654 2) program 0x46010 bit 0 = 1
1655 3) program 0x46034 bit 24 = 1
1656 4) program 0x64000 bit 14 = 1
1658 temp
= I915_READ(0x4600c);
1660 I915_WRITE(0x4600c, temp
| 0x8124);
1662 temp
= I915_READ(0x46010);
1663 I915_WRITE(0x46010, temp
| 1);
1665 temp
= I915_READ(0x46034);
1666 I915_WRITE(0x46034, temp
| (1 << 24));
1668 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1670 I915_WRITE(DP_A
, dpa_ctl
);
1676 /* The FDI link training functions for ILK/Ibexpeak. */
1677 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
1679 struct drm_device
*dev
= crtc
->dev
;
1680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1681 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1682 int pipe
= intel_crtc
->pipe
;
1683 u32 reg
, temp
, tries
;
1685 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1687 reg
= FDI_RX_IMR(pipe
);
1688 temp
= I915_READ(reg
);
1689 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1690 temp
&= ~FDI_RX_BIT_LOCK
;
1691 I915_WRITE(reg
, temp
);
1695 /* enable CPU FDI TX and PCH FDI RX */
1696 reg
= FDI_TX_CTL(pipe
);
1697 temp
= I915_READ(reg
);
1699 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1700 temp
&= ~FDI_LINK_TRAIN_NONE
;
1701 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1702 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
1704 reg
= FDI_RX_CTL(pipe
);
1705 temp
= I915_READ(reg
);
1706 temp
&= ~FDI_LINK_TRAIN_NONE
;
1707 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1708 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
1713 reg
= FDI_RX_IIR(pipe
);
1714 for (tries
= 0; tries
< 5; tries
++) {
1715 temp
= I915_READ(reg
);
1716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1718 if ((temp
& FDI_RX_BIT_LOCK
)) {
1719 DRM_DEBUG_KMS("FDI train 1 done.\n");
1720 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
1725 DRM_ERROR("FDI train 1 fail!\n");
1728 reg
= FDI_TX_CTL(pipe
);
1729 temp
= I915_READ(reg
);
1730 temp
&= ~FDI_LINK_TRAIN_NONE
;
1731 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1732 I915_WRITE(reg
, temp
);
1734 reg
= FDI_RX_CTL(pipe
);
1735 temp
= I915_READ(reg
);
1736 temp
&= ~FDI_LINK_TRAIN_NONE
;
1737 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1738 I915_WRITE(reg
, temp
);
1743 reg
= FDI_RX_IIR(pipe
);
1744 for (tries
= 0; tries
< 5; tries
++) {
1745 temp
= I915_READ(reg
);
1746 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1748 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1749 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
1750 DRM_DEBUG_KMS("FDI train 2 done.\n");
1755 DRM_ERROR("FDI train 2 fail!\n");
1757 DRM_DEBUG_KMS("FDI train done\n");
1760 static const int const snb_b_fdi_train_param
[] = {
1761 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
1762 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
1763 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
1764 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
1767 /* The FDI link training functions for SNB/Cougarpoint. */
1768 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
1770 struct drm_device
*dev
= crtc
->dev
;
1771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1772 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1773 int pipe
= intel_crtc
->pipe
;
1776 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1778 reg
= FDI_RX_IMR(pipe
);
1779 temp
= I915_READ(reg
);
1780 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1781 temp
&= ~FDI_RX_BIT_LOCK
;
1782 I915_WRITE(reg
, temp
);
1787 /* enable CPU FDI TX and PCH FDI RX */
1788 reg
= FDI_TX_CTL(pipe
);
1789 temp
= I915_READ(reg
);
1791 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1792 temp
&= ~FDI_LINK_TRAIN_NONE
;
1793 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1794 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1796 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1797 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
1799 reg
= FDI_RX_CTL(pipe
);
1800 temp
= I915_READ(reg
);
1801 if (HAS_PCH_CPT(dev
)) {
1802 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1803 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
1805 temp
&= ~FDI_LINK_TRAIN_NONE
;
1806 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1808 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
1813 for (i
= 0; i
< 4; i
++ ) {
1814 reg
= FDI_TX_CTL(pipe
);
1815 temp
= I915_READ(reg
);
1816 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1817 temp
|= snb_b_fdi_train_param
[i
];
1818 I915_WRITE(reg
, temp
);
1823 reg
= FDI_RX_IIR(pipe
);
1824 temp
= I915_READ(reg
);
1825 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1827 if (temp
& FDI_RX_BIT_LOCK
) {
1828 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
1829 DRM_DEBUG_KMS("FDI train 1 done.\n");
1834 DRM_ERROR("FDI train 1 fail!\n");
1837 reg
= FDI_TX_CTL(pipe
);
1838 temp
= I915_READ(reg
);
1839 temp
&= ~FDI_LINK_TRAIN_NONE
;
1840 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1842 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1844 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1846 I915_WRITE(reg
, temp
);
1848 reg
= FDI_RX_CTL(pipe
);
1849 temp
= I915_READ(reg
);
1850 if (HAS_PCH_CPT(dev
)) {
1851 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1852 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
1854 temp
&= ~FDI_LINK_TRAIN_NONE
;
1855 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1857 I915_WRITE(reg
, temp
);
1862 for (i
= 0; i
< 4; i
++ ) {
1863 reg
= FDI_TX_CTL(pipe
);
1864 temp
= I915_READ(reg
);
1865 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1866 temp
|= snb_b_fdi_train_param
[i
];
1867 I915_WRITE(reg
, temp
);
1872 reg
= FDI_RX_IIR(pipe
);
1873 temp
= I915_READ(reg
);
1874 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1876 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1877 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
1878 DRM_DEBUG_KMS("FDI train 2 done.\n");
1883 DRM_ERROR("FDI train 2 fail!\n");
1885 DRM_DEBUG_KMS("FDI train done.\n");
1888 static void ironlake_fdi_enable(struct drm_crtc
*crtc
)
1890 struct drm_device
*dev
= crtc
->dev
;
1891 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1892 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1893 int pipe
= intel_crtc
->pipe
;
1896 /* Write the TU size bits so error detection works */
1897 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
1898 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
1900 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1901 reg
= FDI_RX_CTL(pipe
);
1902 temp
= I915_READ(reg
);
1903 temp
&= ~((0x7 << 19) | (0x7 << 16));
1904 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1905 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
1906 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
1911 /* Switch from Rawclk to PCDclk */
1912 temp
= I915_READ(reg
);
1913 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
1918 /* Enable CPU FDI TX PLL, always on for Ironlake */
1919 reg
= FDI_TX_CTL(pipe
);
1920 temp
= I915_READ(reg
);
1921 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
1922 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
1929 static void intel_flush_display_plane(struct drm_device
*dev
,
1932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1933 u32 reg
= DSPADDR(plane
);
1934 I915_WRITE(reg
, I915_READ(reg
));
1938 * When we disable a pipe, we need to clear any pending scanline wait events
1939 * to avoid hanging the ring, which we assume we are waiting on.
1941 static void intel_clear_scanline_wait(struct drm_device
*dev
)
1943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1947 /* Can't break the hang on i8xx */
1950 tmp
= I915_READ(PRB0_CTL
);
1951 if (tmp
& RING_WAIT
) {
1952 I915_WRITE(PRB0_CTL
, tmp
);
1953 POSTING_READ(PRB0_CTL
);
1957 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
1959 struct drm_device
*dev
= crtc
->dev
;
1960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1961 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1962 int pipe
= intel_crtc
->pipe
;
1963 int plane
= intel_crtc
->plane
;
1966 if (intel_crtc
->active
)
1969 intel_crtc
->active
= true;
1970 intel_update_watermarks(dev
);
1972 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1973 temp
= I915_READ(PCH_LVDS
);
1974 if ((temp
& LVDS_PORT_EN
) == 0)
1975 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
1978 ironlake_fdi_enable(crtc
);
1980 /* Enable panel fitting for LVDS */
1981 if (dev_priv
->pch_pf_size
&&
1982 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)
1983 || HAS_eDP
|| intel_pch_has_edp(crtc
))) {
1984 /* Force use of hard-coded filter coefficients
1985 * as some pre-programmed values are broken,
1988 I915_WRITE(pipe
? PFB_CTL_1
: PFA_CTL_1
,
1989 PF_ENABLE
| PF_FILTER_MED_3x3
);
1990 I915_WRITE(pipe
? PFB_WIN_POS
: PFA_WIN_POS
,
1991 dev_priv
->pch_pf_pos
);
1992 I915_WRITE(pipe
? PFB_WIN_SZ
: PFA_WIN_SZ
,
1993 dev_priv
->pch_pf_size
);
1996 /* Enable CPU pipe */
1997 reg
= PIPECONF(pipe
);
1998 temp
= I915_READ(reg
);
1999 if ((temp
& PIPECONF_ENABLE
) == 0) {
2000 I915_WRITE(reg
, temp
| PIPECONF_ENABLE
);
2005 /* configure and enable CPU plane */
2006 reg
= DSPCNTR(plane
);
2007 temp
= I915_READ(reg
);
2008 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
2009 I915_WRITE(reg
, temp
| DISPLAY_PLANE_ENABLE
);
2010 intel_flush_display_plane(dev
, plane
);
2013 /* For PCH output, training FDI link */
2015 gen6_fdi_link_train(crtc
);
2017 ironlake_fdi_link_train(crtc
);
2019 /* enable PCH DPLL */
2020 reg
= PCH_DPLL(pipe
);
2021 temp
= I915_READ(reg
);
2022 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
2023 I915_WRITE(reg
, temp
| DPLL_VCO_ENABLE
);
2028 if (HAS_PCH_CPT(dev
)) {
2029 /* Be sure PCH DPLL SEL is set */
2030 temp
= I915_READ(PCH_DPLL_SEL
);
2031 if (pipe
== 0 && (temp
& TRANSA_DPLL_ENABLE
) == 0)
2032 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
2033 else if (pipe
== 1 && (temp
& TRANSB_DPLL_ENABLE
) == 0)
2034 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2035 I915_WRITE(PCH_DPLL_SEL
, temp
);
2038 /* set transcoder timing */
2039 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
2040 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
2041 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
2043 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
2044 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
2045 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
2047 /* enable normal train */
2048 reg
= FDI_TX_CTL(pipe
);
2049 temp
= I915_READ(reg
);
2050 temp
&= ~FDI_LINK_TRAIN_NONE
;
2051 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2052 I915_WRITE(reg
, temp
);
2054 reg
= FDI_RX_CTL(pipe
);
2055 temp
= I915_READ(reg
);
2056 if (HAS_PCH_CPT(dev
)) {
2057 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2058 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2060 temp
&= ~FDI_LINK_TRAIN_NONE
;
2061 temp
|= FDI_LINK_TRAIN_NONE
;
2063 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2065 /* wait one idle pattern time */
2069 /* For PCH DP, enable TRANS_DP_CTL */
2070 if (HAS_PCH_CPT(dev
) &&
2071 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
2072 reg
= TRANS_DP_CTL(pipe
);
2073 temp
= I915_READ(reg
);
2074 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
2075 TRANS_DP_SYNC_MASK
);
2076 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
2077 TRANS_DP_ENH_FRAMING
);
2079 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
2080 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
2081 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
2082 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
2084 switch (intel_trans_dp_port_sel(crtc
)) {
2086 temp
|= TRANS_DP_PORT_SEL_B
;
2089 temp
|= TRANS_DP_PORT_SEL_C
;
2092 temp
|= TRANS_DP_PORT_SEL_D
;
2095 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2096 temp
|= TRANS_DP_PORT_SEL_B
;
2100 I915_WRITE(reg
, temp
);
2103 /* enable PCH transcoder */
2104 reg
= TRANSCONF(pipe
);
2105 temp
= I915_READ(reg
);
2107 * make the BPC in transcoder be consistent with
2108 * that in pipeconf reg.
2110 temp
&= ~PIPE_BPC_MASK
;
2111 temp
|= I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
;
2112 I915_WRITE(reg
, temp
| TRANS_ENABLE
);
2113 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
2114 DRM_ERROR("failed to enable transcoder\n");
2116 intel_crtc_load_lut(crtc
);
2117 intel_update_fbc(dev
);
2118 intel_crtc_update_cursor(crtc
, true);
2121 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
2123 struct drm_device
*dev
= crtc
->dev
;
2124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2125 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2126 int pipe
= intel_crtc
->pipe
;
2127 int plane
= intel_crtc
->plane
;
2130 if (!intel_crtc
->active
)
2133 drm_vblank_off(dev
, pipe
);
2134 intel_crtc_update_cursor(crtc
, false);
2136 /* Disable display plane */
2137 reg
= DSPCNTR(plane
);
2138 temp
= I915_READ(reg
);
2139 if (temp
& DISPLAY_PLANE_ENABLE
) {
2140 I915_WRITE(reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2141 intel_flush_display_plane(dev
, plane
);
2144 if (dev_priv
->cfb_plane
== plane
&&
2145 dev_priv
->display
.disable_fbc
)
2146 dev_priv
->display
.disable_fbc(dev
);
2148 /* disable cpu pipe, disable after all planes disabled */
2149 reg
= PIPECONF(pipe
);
2150 temp
= I915_READ(reg
);
2151 if (temp
& PIPECONF_ENABLE
) {
2152 I915_WRITE(reg
, temp
& ~PIPECONF_ENABLE
);
2153 /* wait for cpu pipe off, pipe state */
2154 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0, 50))
2155 DRM_ERROR("failed to turn off cpu pipe\n");
2159 I915_WRITE(pipe
? PFB_CTL_1
: PFA_CTL_1
, 0);
2160 I915_WRITE(pipe
? PFB_WIN_SZ
: PFA_WIN_SZ
, 0);
2162 /* disable CPU FDI tx and PCH FDI rx */
2163 reg
= FDI_TX_CTL(pipe
);
2164 temp
= I915_READ(reg
);
2165 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2168 reg
= FDI_RX_CTL(pipe
);
2169 temp
= I915_READ(reg
);
2170 temp
&= ~(0x7 << 16);
2171 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2172 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2177 /* still set train pattern 1 */
2178 reg
= FDI_TX_CTL(pipe
);
2179 temp
= I915_READ(reg
);
2180 temp
&= ~FDI_LINK_TRAIN_NONE
;
2181 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2182 I915_WRITE(reg
, temp
);
2184 reg
= FDI_RX_CTL(pipe
);
2185 temp
= I915_READ(reg
);
2186 if (HAS_PCH_CPT(dev
)) {
2187 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2188 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2190 temp
&= ~FDI_LINK_TRAIN_NONE
;
2191 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2193 /* BPC in FDI rx is consistent with that in PIPECONF */
2194 temp
&= ~(0x07 << 16);
2195 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2196 I915_WRITE(reg
, temp
);
2201 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
2202 temp
= I915_READ(PCH_LVDS
);
2203 if (temp
& LVDS_PORT_EN
) {
2204 I915_WRITE(PCH_LVDS
, temp
& ~LVDS_PORT_EN
);
2205 POSTING_READ(PCH_LVDS
);
2210 /* disable PCH transcoder */
2211 reg
= TRANSCONF(plane
);
2212 temp
= I915_READ(reg
);
2213 if (temp
& TRANS_ENABLE
) {
2214 I915_WRITE(reg
, temp
& ~TRANS_ENABLE
);
2215 /* wait for PCH transcoder off, transcoder state */
2216 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2217 DRM_ERROR("failed to disable transcoder\n");
2220 if (HAS_PCH_CPT(dev
)) {
2221 /* disable TRANS_DP_CTL */
2222 reg
= TRANS_DP_CTL(pipe
);
2223 temp
= I915_READ(reg
);
2224 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
2225 I915_WRITE(reg
, temp
);
2227 /* disable DPLL_SEL */
2228 temp
= I915_READ(PCH_DPLL_SEL
);
2230 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
2232 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2233 I915_WRITE(PCH_DPLL_SEL
, temp
);
2236 /* disable PCH DPLL */
2237 reg
= PCH_DPLL(pipe
);
2238 temp
= I915_READ(reg
);
2239 I915_WRITE(reg
, temp
& ~DPLL_VCO_ENABLE
);
2241 /* Switch from PCDclk to Rawclk */
2242 reg
= FDI_RX_CTL(pipe
);
2243 temp
= I915_READ(reg
);
2244 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2246 /* Disable CPU FDI TX PLL */
2247 reg
= FDI_TX_CTL(pipe
);
2248 temp
= I915_READ(reg
);
2249 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2254 reg
= FDI_RX_CTL(pipe
);
2255 temp
= I915_READ(reg
);
2256 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2258 /* Wait for the clocks to turn off. */
2262 intel_crtc
->active
= false;
2263 intel_update_watermarks(dev
);
2264 intel_update_fbc(dev
);
2265 intel_clear_scanline_wait(dev
);
2268 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2270 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2271 int pipe
= intel_crtc
->pipe
;
2272 int plane
= intel_crtc
->plane
;
2274 /* XXX: When our outputs are all unaware of DPMS modes other than off
2275 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2278 case DRM_MODE_DPMS_ON
:
2279 case DRM_MODE_DPMS_STANDBY
:
2280 case DRM_MODE_DPMS_SUSPEND
:
2281 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe
, plane
);
2282 ironlake_crtc_enable(crtc
);
2285 case DRM_MODE_DPMS_OFF
:
2286 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe
, plane
);
2287 ironlake_crtc_disable(crtc
);
2292 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
2294 if (!enable
&& intel_crtc
->overlay
) {
2295 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2297 mutex_lock(&dev
->struct_mutex
);
2298 (void) intel_overlay_switch_off(intel_crtc
->overlay
, false);
2299 mutex_unlock(&dev
->struct_mutex
);
2302 /* Let userspace switch the overlay on again. In most cases userspace
2303 * has to recompute where to put it anyway.
2307 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
2309 struct drm_device
*dev
= crtc
->dev
;
2310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2311 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2312 int pipe
= intel_crtc
->pipe
;
2313 int plane
= intel_crtc
->plane
;
2316 if (intel_crtc
->active
)
2319 intel_crtc
->active
= true;
2320 intel_update_watermarks(dev
);
2322 /* Enable the DPLL */
2324 temp
= I915_READ(reg
);
2325 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
2326 I915_WRITE(reg
, temp
);
2328 /* Wait for the clocks to stabilize. */
2332 I915_WRITE(reg
, temp
| DPLL_VCO_ENABLE
);
2334 /* Wait for the clocks to stabilize. */
2338 I915_WRITE(reg
, temp
| DPLL_VCO_ENABLE
);
2340 /* Wait for the clocks to stabilize. */
2345 /* Enable the pipe */
2346 reg
= PIPECONF(pipe
);
2347 temp
= I915_READ(reg
);
2348 if ((temp
& PIPECONF_ENABLE
) == 0)
2349 I915_WRITE(reg
, temp
| PIPECONF_ENABLE
);
2351 /* Enable the plane */
2352 reg
= DSPCNTR(plane
);
2353 temp
= I915_READ(reg
);
2354 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
2355 I915_WRITE(reg
, temp
| DISPLAY_PLANE_ENABLE
);
2356 intel_flush_display_plane(dev
, plane
);
2359 intel_crtc_load_lut(crtc
);
2360 intel_update_fbc(dev
);
2362 /* Give the overlay scaler a chance to enable if it's on this pipe */
2363 intel_crtc_dpms_overlay(intel_crtc
, true);
2364 intel_crtc_update_cursor(crtc
, true);
2367 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
2369 struct drm_device
*dev
= crtc
->dev
;
2370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2371 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2372 int pipe
= intel_crtc
->pipe
;
2373 int plane
= intel_crtc
->plane
;
2376 if (!intel_crtc
->active
)
2379 /* Give the overlay scaler a chance to disable if it's on this pipe */
2380 intel_crtc_dpms_overlay(intel_crtc
, false);
2381 intel_crtc_update_cursor(crtc
, false);
2382 drm_vblank_off(dev
, pipe
);
2384 if (dev_priv
->cfb_plane
== plane
&&
2385 dev_priv
->display
.disable_fbc
)
2386 dev_priv
->display
.disable_fbc(dev
);
2388 /* Disable display plane */
2389 reg
= DSPCNTR(plane
);
2390 temp
= I915_READ(reg
);
2391 if (temp
& DISPLAY_PLANE_ENABLE
) {
2392 I915_WRITE(reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2393 /* Flush the plane changes */
2394 intel_flush_display_plane(dev
, plane
);
2396 /* Wait for vblank for the disable to take effect */
2398 intel_wait_for_vblank_off(dev
, pipe
);
2401 /* Don't disable pipe A or pipe A PLLs if needed */
2402 if (pipe
== 0 && (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
2405 /* Next, disable display pipes */
2406 reg
= PIPECONF(pipe
);
2407 temp
= I915_READ(reg
);
2408 if (temp
& PIPECONF_ENABLE
) {
2409 I915_WRITE(reg
, temp
& ~PIPECONF_ENABLE
);
2411 /* Wait for vblank for the disable to take effect. */
2413 intel_wait_for_vblank_off(dev
, pipe
);
2417 temp
= I915_READ(reg
);
2418 if (temp
& DPLL_VCO_ENABLE
) {
2419 I915_WRITE(reg
, temp
& ~DPLL_VCO_ENABLE
);
2421 /* Wait for the clocks to turn off. */
2427 intel_crtc
->active
= false;
2428 intel_update_fbc(dev
);
2429 intel_update_watermarks(dev
);
2430 intel_clear_scanline_wait(dev
);
2433 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2435 /* XXX: When our outputs are all unaware of DPMS modes other than off
2436 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2439 case DRM_MODE_DPMS_ON
:
2440 case DRM_MODE_DPMS_STANDBY
:
2441 case DRM_MODE_DPMS_SUSPEND
:
2442 i9xx_crtc_enable(crtc
);
2444 case DRM_MODE_DPMS_OFF
:
2445 i9xx_crtc_disable(crtc
);
2451 * Sets the power management mode of the pipe and plane.
2453 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2455 struct drm_device
*dev
= crtc
->dev
;
2456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2457 struct drm_i915_master_private
*master_priv
;
2458 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2459 int pipe
= intel_crtc
->pipe
;
2462 if (intel_crtc
->dpms_mode
== mode
)
2465 intel_crtc
->dpms_mode
= mode
;
2467 dev_priv
->display
.dpms(crtc
, mode
);
2469 if (!dev
->primary
->master
)
2472 master_priv
= dev
->primary
->master
->driver_priv
;
2473 if (!master_priv
->sarea_priv
)
2476 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
2480 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2481 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2484 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2485 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2488 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
2493 static void intel_crtc_disable(struct drm_crtc
*crtc
)
2495 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2496 struct drm_device
*dev
= crtc
->dev
;
2498 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
2501 mutex_lock(&dev
->struct_mutex
);
2502 i915_gem_object_unpin(to_intel_framebuffer(crtc
->fb
)->obj
);
2503 mutex_unlock(&dev
->struct_mutex
);
2507 /* Prepare for a mode set.
2509 * Note we could be a lot smarter here. We need to figure out which outputs
2510 * will be enabled, which disabled (in short, how the config will changes)
2511 * and perform the minimum necessary steps to accomplish that, e.g. updating
2512 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2513 * panel fitting is in the proper state, etc.
2515 static void i9xx_crtc_prepare(struct drm_crtc
*crtc
)
2517 i9xx_crtc_disable(crtc
);
2520 static void i9xx_crtc_commit(struct drm_crtc
*crtc
)
2522 i9xx_crtc_enable(crtc
);
2525 static void ironlake_crtc_prepare(struct drm_crtc
*crtc
)
2527 ironlake_crtc_disable(crtc
);
2530 static void ironlake_crtc_commit(struct drm_crtc
*crtc
)
2532 ironlake_crtc_enable(crtc
);
2535 void intel_encoder_prepare (struct drm_encoder
*encoder
)
2537 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2538 /* lvds has its own version of prepare see intel_lvds_prepare */
2539 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
2542 void intel_encoder_commit (struct drm_encoder
*encoder
)
2544 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2545 /* lvds has its own version of commit see intel_lvds_commit */
2546 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
2549 void intel_encoder_destroy(struct drm_encoder
*encoder
)
2551 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
2553 drm_encoder_cleanup(encoder
);
2554 kfree(intel_encoder
);
2557 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
2558 struct drm_display_mode
*mode
,
2559 struct drm_display_mode
*adjusted_mode
)
2561 struct drm_device
*dev
= crtc
->dev
;
2563 if (HAS_PCH_SPLIT(dev
)) {
2564 /* FDI link clock is fixed at 2.7G */
2565 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
2569 /* XXX some encoders set the crtcinfo, others don't.
2570 * Obviously we need some form of conflict resolution here...
2572 if (adjusted_mode
->crtc_htotal
== 0)
2573 drm_mode_set_crtcinfo(adjusted_mode
, 0);
2578 static int i945_get_display_clock_speed(struct drm_device
*dev
)
2583 static int i915_get_display_clock_speed(struct drm_device
*dev
)
2588 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
2593 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
2597 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
2599 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
2602 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
2603 case GC_DISPLAY_CLOCK_333_MHZ
:
2606 case GC_DISPLAY_CLOCK_190_200_MHZ
:
2612 static int i865_get_display_clock_speed(struct drm_device
*dev
)
2617 static int i855_get_display_clock_speed(struct drm_device
*dev
)
2620 /* Assume that the hardware is in the high speed state. This
2621 * should be the default.
2623 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
2624 case GC_CLOCK_133_200
:
2625 case GC_CLOCK_100_200
:
2627 case GC_CLOCK_166_250
:
2629 case GC_CLOCK_100_133
:
2633 /* Shouldn't happen */
2637 static int i830_get_display_clock_speed(struct drm_device
*dev
)
2651 fdi_reduce_ratio(u32
*num
, u32
*den
)
2653 while (*num
> 0xffffff || *den
> 0xffffff) {
2659 #define DATA_N 0x800000
2660 #define LINK_N 0x80000
2663 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
2664 int link_clock
, struct fdi_m_n
*m_n
)
2668 m_n
->tu
= 64; /* default size */
2670 temp
= (u64
) DATA_N
* pixel_clock
;
2671 temp
= div_u64(temp
, link_clock
);
2672 m_n
->gmch_m
= div_u64(temp
* bits_per_pixel
, nlanes
);
2673 m_n
->gmch_m
>>= 3; /* convert to bytes_per_pixel */
2674 m_n
->gmch_n
= DATA_N
;
2675 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
2677 temp
= (u64
) LINK_N
* pixel_clock
;
2678 m_n
->link_m
= div_u64(temp
, link_clock
);
2679 m_n
->link_n
= LINK_N
;
2680 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
2684 struct intel_watermark_params
{
2685 unsigned long fifo_size
;
2686 unsigned long max_wm
;
2687 unsigned long default_wm
;
2688 unsigned long guard_size
;
2689 unsigned long cacheline_size
;
2692 /* Pineview has different values for various configs */
2693 static struct intel_watermark_params pineview_display_wm
= {
2694 PINEVIEW_DISPLAY_FIFO
,
2698 PINEVIEW_FIFO_LINE_SIZE
2700 static struct intel_watermark_params pineview_display_hplloff_wm
= {
2701 PINEVIEW_DISPLAY_FIFO
,
2703 PINEVIEW_DFT_HPLLOFF_WM
,
2705 PINEVIEW_FIFO_LINE_SIZE
2707 static struct intel_watermark_params pineview_cursor_wm
= {
2708 PINEVIEW_CURSOR_FIFO
,
2709 PINEVIEW_CURSOR_MAX_WM
,
2710 PINEVIEW_CURSOR_DFT_WM
,
2711 PINEVIEW_CURSOR_GUARD_WM
,
2712 PINEVIEW_FIFO_LINE_SIZE
,
2714 static struct intel_watermark_params pineview_cursor_hplloff_wm
= {
2715 PINEVIEW_CURSOR_FIFO
,
2716 PINEVIEW_CURSOR_MAX_WM
,
2717 PINEVIEW_CURSOR_DFT_WM
,
2718 PINEVIEW_CURSOR_GUARD_WM
,
2719 PINEVIEW_FIFO_LINE_SIZE
2721 static struct intel_watermark_params g4x_wm_info
= {
2728 static struct intel_watermark_params g4x_cursor_wm_info
= {
2735 static struct intel_watermark_params i965_cursor_wm_info
= {
2740 I915_FIFO_LINE_SIZE
,
2742 static struct intel_watermark_params i945_wm_info
= {
2749 static struct intel_watermark_params i915_wm_info
= {
2756 static struct intel_watermark_params i855_wm_info
= {
2763 static struct intel_watermark_params i830_wm_info
= {
2771 static struct intel_watermark_params ironlake_display_wm_info
= {
2779 static struct intel_watermark_params ironlake_cursor_wm_info
= {
2787 static struct intel_watermark_params ironlake_display_srwm_info
= {
2788 ILK_DISPLAY_SR_FIFO
,
2789 ILK_DISPLAY_MAX_SRWM
,
2790 ILK_DISPLAY_DFT_SRWM
,
2795 static struct intel_watermark_params ironlake_cursor_srwm_info
= {
2797 ILK_CURSOR_MAX_SRWM
,
2798 ILK_CURSOR_DFT_SRWM
,
2804 * intel_calculate_wm - calculate watermark level
2805 * @clock_in_khz: pixel clock
2806 * @wm: chip FIFO params
2807 * @pixel_size: display pixel size
2808 * @latency_ns: memory latency for the platform
2810 * Calculate the watermark level (the level at which the display plane will
2811 * start fetching from memory again). Each chip has a different display
2812 * FIFO size and allocation, so the caller needs to figure that out and pass
2813 * in the correct intel_watermark_params structure.
2815 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2816 * on the pixel size. When it reaches the watermark level, it'll start
2817 * fetching FIFO line sized based chunks from memory until the FIFO fills
2818 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2819 * will occur, and a display engine hang could result.
2821 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
2822 struct intel_watermark_params
*wm
,
2824 unsigned long latency_ns
)
2826 long entries_required
, wm_size
;
2829 * Note: we need to make sure we don't overflow for various clock &
2831 * clocks go from a few thousand to several hundred thousand.
2832 * latency is usually a few thousand
2834 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
2836 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
2838 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required
);
2840 wm_size
= wm
->fifo_size
- (entries_required
+ wm
->guard_size
);
2842 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
2844 /* Don't promote wm_size to unsigned... */
2845 if (wm_size
> (long)wm
->max_wm
)
2846 wm_size
= wm
->max_wm
;
2848 wm_size
= wm
->default_wm
;
2852 struct cxsr_latency
{
2855 unsigned long fsb_freq
;
2856 unsigned long mem_freq
;
2857 unsigned long display_sr
;
2858 unsigned long display_hpll_disable
;
2859 unsigned long cursor_sr
;
2860 unsigned long cursor_hpll_disable
;
2863 static const struct cxsr_latency cxsr_latency_table
[] = {
2864 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2865 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2866 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2867 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2868 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2870 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2871 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2872 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2873 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2874 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2876 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2877 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2878 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2879 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2880 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2882 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2883 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2884 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2885 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2886 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2888 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2889 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2890 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2891 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2892 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2894 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2895 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2896 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2897 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2898 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2901 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
2906 const struct cxsr_latency
*latency
;
2909 if (fsb
== 0 || mem
== 0)
2912 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
2913 latency
= &cxsr_latency_table
[i
];
2914 if (is_desktop
== latency
->is_desktop
&&
2915 is_ddr3
== latency
->is_ddr3
&&
2916 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
2920 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2925 static void pineview_disable_cxsr(struct drm_device
*dev
)
2927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2929 /* deactivate cxsr */
2930 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
2934 * Latency for FIFO fetches is dependent on several factors:
2935 * - memory configuration (speed, channels)
2937 * - current MCH state
2938 * It can be fairly high in some situations, so here we assume a fairly
2939 * pessimal value. It's a tradeoff between extra memory fetches (if we
2940 * set this value too high, the FIFO will fetch frequently to stay full)
2941 * and power consumption (set it too low to save power and we might see
2942 * FIFO underruns and display "flicker").
2944 * A value of 5us seems to be a good balance; safe for very low end
2945 * platforms but not overly aggressive on lower latency configs.
2947 static const int latency_ns
= 5000;
2949 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
2951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2952 uint32_t dsparb
= I915_READ(DSPARB
);
2955 size
= dsparb
& 0x7f;
2957 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
2959 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2960 plane
? "B" : "A", size
);
2965 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
2967 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2968 uint32_t dsparb
= I915_READ(DSPARB
);
2971 size
= dsparb
& 0x1ff;
2973 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
2974 size
>>= 1; /* Convert to cachelines */
2976 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2977 plane
? "B" : "A", size
);
2982 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
2984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2985 uint32_t dsparb
= I915_READ(DSPARB
);
2988 size
= dsparb
& 0x7f;
2989 size
>>= 2; /* Convert to cachelines */
2991 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2998 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
3000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3001 uint32_t dsparb
= I915_READ(DSPARB
);
3004 size
= dsparb
& 0x7f;
3005 size
>>= 1; /* Convert to cachelines */
3007 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3008 plane
? "B" : "A", size
);
3013 static void pineview_update_wm(struct drm_device
*dev
, int planea_clock
,
3014 int planeb_clock
, int sr_hdisplay
, int unused
,
3017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3018 const struct cxsr_latency
*latency
;
3023 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
3024 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
3026 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3027 pineview_disable_cxsr(dev
);
3031 if (!planea_clock
|| !planeb_clock
) {
3032 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3035 wm
= intel_calculate_wm(sr_clock
, &pineview_display_wm
,
3036 pixel_size
, latency
->display_sr
);
3037 reg
= I915_READ(DSPFW1
);
3038 reg
&= ~DSPFW_SR_MASK
;
3039 reg
|= wm
<< DSPFW_SR_SHIFT
;
3040 I915_WRITE(DSPFW1
, reg
);
3041 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
3044 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_wm
,
3045 pixel_size
, latency
->cursor_sr
);
3046 reg
= I915_READ(DSPFW3
);
3047 reg
&= ~DSPFW_CURSOR_SR_MASK
;
3048 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
3049 I915_WRITE(DSPFW3
, reg
);
3051 /* Display HPLL off SR */
3052 wm
= intel_calculate_wm(sr_clock
, &pineview_display_hplloff_wm
,
3053 pixel_size
, latency
->display_hpll_disable
);
3054 reg
= I915_READ(DSPFW3
);
3055 reg
&= ~DSPFW_HPLL_SR_MASK
;
3056 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
3057 I915_WRITE(DSPFW3
, reg
);
3059 /* cursor HPLL off SR */
3060 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_hplloff_wm
,
3061 pixel_size
, latency
->cursor_hpll_disable
);
3062 reg
= I915_READ(DSPFW3
);
3063 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
3064 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
3065 I915_WRITE(DSPFW3
, reg
);
3066 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
3070 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
3071 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3073 pineview_disable_cxsr(dev
);
3074 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3078 static void g4x_update_wm(struct drm_device
*dev
, int planea_clock
,
3079 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3083 int total_size
, cacheline_size
;
3084 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
, cursor_sr
;
3085 struct intel_watermark_params planea_params
, planeb_params
;
3086 unsigned long line_time_us
;
3087 int sr_clock
, sr_entries
= 0, entries_required
;
3089 /* Create copies of the base settings for each pipe */
3090 planea_params
= planeb_params
= g4x_wm_info
;
3092 /* Grab a couple of global values before we overwrite them */
3093 total_size
= planea_params
.fifo_size
;
3094 cacheline_size
= planea_params
.cacheline_size
;
3097 * Note: we need to make sure we don't overflow for various clock &
3099 * clocks go from a few thousand to several hundred thousand.
3100 * latency is usually a few thousand
3102 entries_required
= ((planea_clock
/ 1000) * pixel_size
* latency_ns
) /
3104 entries_required
= DIV_ROUND_UP(entries_required
, G4X_FIFO_LINE_SIZE
);
3105 planea_wm
= entries_required
+ planea_params
.guard_size
;
3107 entries_required
= ((planeb_clock
/ 1000) * pixel_size
* latency_ns
) /
3109 entries_required
= DIV_ROUND_UP(entries_required
, G4X_FIFO_LINE_SIZE
);
3110 planeb_wm
= entries_required
+ planeb_params
.guard_size
;
3112 cursora_wm
= cursorb_wm
= 16;
3115 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3117 /* Calc sr entries for one plane configs */
3118 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
3119 /* self-refresh has much higher latency */
3120 static const int sr_latency_ns
= 12000;
3122 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3123 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3125 /* Use ns/us then divide to preserve precision */
3126 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3127 pixel_size
* sr_hdisplay
;
3128 sr_entries
= DIV_ROUND_UP(sr_entries
, cacheline_size
);
3130 entries_required
= (((sr_latency_ns
/ line_time_us
) +
3131 1000) / 1000) * pixel_size
* 64;
3132 entries_required
= DIV_ROUND_UP(entries_required
,
3133 g4x_cursor_wm_info
.cacheline_size
);
3134 cursor_sr
= entries_required
+ g4x_cursor_wm_info
.guard_size
;
3136 if (cursor_sr
> g4x_cursor_wm_info
.max_wm
)
3137 cursor_sr
= g4x_cursor_wm_info
.max_wm
;
3138 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3139 "cursor %d\n", sr_entries
, cursor_sr
);
3141 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3143 /* Turn off self refresh if both pipes are enabled */
3144 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3148 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3149 planea_wm
, planeb_wm
, sr_entries
);
3154 I915_WRITE(DSPFW1
, (sr_entries
<< DSPFW_SR_SHIFT
) |
3155 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
3156 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) | planea_wm
);
3157 I915_WRITE(DSPFW2
, (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
3158 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
3159 /* HPLL off in SR has some issues on G4x... disable it */
3160 I915_WRITE(DSPFW3
, (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
3161 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3164 static void i965_update_wm(struct drm_device
*dev
, int planea_clock
,
3165 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3169 unsigned long line_time_us
;
3170 int sr_clock
, sr_entries
, srwm
= 1;
3173 /* Calc sr entries for one plane configs */
3174 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
3175 /* self-refresh has much higher latency */
3176 static const int sr_latency_ns
= 12000;
3178 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3179 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3181 /* Use ns/us then divide to preserve precision */
3182 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3183 pixel_size
* sr_hdisplay
;
3184 sr_entries
= DIV_ROUND_UP(sr_entries
, I915_FIFO_LINE_SIZE
);
3185 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
3186 srwm
= I965_FIFO_SIZE
- sr_entries
;
3191 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3193 sr_entries
= DIV_ROUND_UP(sr_entries
,
3194 i965_cursor_wm_info
.cacheline_size
);
3195 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
3196 (sr_entries
+ i965_cursor_wm_info
.guard_size
);
3198 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
3199 cursor_sr
= i965_cursor_wm_info
.max_wm
;
3201 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3202 "cursor %d\n", srwm
, cursor_sr
);
3204 if (IS_CRESTLINE(dev
))
3205 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3207 /* Turn off self refresh if both pipes are enabled */
3208 if (IS_CRESTLINE(dev
))
3209 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3213 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3216 /* 965 has limitations... */
3217 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) | (8 << 16) | (8 << 8) |
3219 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
3220 /* update cursor SR watermark */
3221 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3224 static void i9xx_update_wm(struct drm_device
*dev
, int planea_clock
,
3225 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3231 int total_size
, cacheline_size
, cwm
, srwm
= 1;
3232 int planea_wm
, planeb_wm
;
3233 struct intel_watermark_params planea_params
, planeb_params
;
3234 unsigned long line_time_us
;
3235 int sr_clock
, sr_entries
= 0;
3237 /* Create copies of the base settings for each pipe */
3238 if (IS_CRESTLINE(dev
) || IS_I945GM(dev
))
3239 planea_params
= planeb_params
= i945_wm_info
;
3240 else if (!IS_GEN2(dev
))
3241 planea_params
= planeb_params
= i915_wm_info
;
3243 planea_params
= planeb_params
= i855_wm_info
;
3245 /* Grab a couple of global values before we overwrite them */
3246 total_size
= planea_params
.fifo_size
;
3247 cacheline_size
= planea_params
.cacheline_size
;
3249 /* Update per-plane FIFO sizes */
3250 planea_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3251 planeb_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
3253 planea_wm
= intel_calculate_wm(planea_clock
, &planea_params
,
3254 pixel_size
, latency_ns
);
3255 planeb_wm
= intel_calculate_wm(planeb_clock
, &planeb_params
,
3256 pixel_size
, latency_ns
);
3257 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3260 * Overlay gets an aggressive default since video jitter is bad.
3264 /* Calc sr entries for one plane configs */
3265 if (HAS_FW_BLC(dev
) && sr_hdisplay
&&
3266 (!planea_clock
|| !planeb_clock
)) {
3267 /* self-refresh has much higher latency */
3268 static const int sr_latency_ns
= 6000;
3270 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3271 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3273 /* Use ns/us then divide to preserve precision */
3274 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3275 pixel_size
* sr_hdisplay
;
3276 sr_entries
= DIV_ROUND_UP(sr_entries
, cacheline_size
);
3277 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries
);
3278 srwm
= total_size
- sr_entries
;
3282 if (IS_I945G(dev
) || IS_I945GM(dev
))
3283 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
3284 else if (IS_I915GM(dev
)) {
3285 /* 915M has a smaller SRWM field */
3286 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
3287 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
3290 /* Turn off self refresh if both pipes are enabled */
3291 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
3292 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3294 } else if (IS_I915GM(dev
)) {
3295 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
3299 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3300 planea_wm
, planeb_wm
, cwm
, srwm
);
3302 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
3303 fwater_hi
= (cwm
& 0x1f);
3305 /* Set request length to 8 cachelines per fetch */
3306 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
3307 fwater_hi
= fwater_hi
| (1 << 8);
3309 I915_WRITE(FW_BLC
, fwater_lo
);
3310 I915_WRITE(FW_BLC2
, fwater_hi
);
3313 static void i830_update_wm(struct drm_device
*dev
, int planea_clock
, int unused
,
3314 int unused2
, int unused3
, int pixel_size
)
3316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3317 uint32_t fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
3320 i830_wm_info
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3322 planea_wm
= intel_calculate_wm(planea_clock
, &i830_wm_info
,
3323 pixel_size
, latency_ns
);
3324 fwater_lo
|= (3<<8) | planea_wm
;
3326 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
3328 I915_WRITE(FW_BLC
, fwater_lo
);
3331 #define ILK_LP0_PLANE_LATENCY 700
3332 #define ILK_LP0_CURSOR_LATENCY 1300
3334 static bool ironlake_compute_wm0(struct drm_device
*dev
,
3339 struct drm_crtc
*crtc
;
3340 int htotal
, hdisplay
, clock
, pixel_size
= 0;
3341 int line_time_us
, line_count
, entries
;
3343 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
3344 if (crtc
->fb
== NULL
|| !crtc
->enabled
)
3347 htotal
= crtc
->mode
.htotal
;
3348 hdisplay
= crtc
->mode
.hdisplay
;
3349 clock
= crtc
->mode
.clock
;
3350 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3352 /* Use the small buffer method to calculate plane watermark */
3353 entries
= ((clock
* pixel_size
/ 1000) * ILK_LP0_PLANE_LATENCY
) / 1000;
3354 entries
= DIV_ROUND_UP(entries
,
3355 ironlake_display_wm_info
.cacheline_size
);
3356 *plane_wm
= entries
+ ironlake_display_wm_info
.guard_size
;
3357 if (*plane_wm
> (int)ironlake_display_wm_info
.max_wm
)
3358 *plane_wm
= ironlake_display_wm_info
.max_wm
;
3360 /* Use the large buffer method to calculate cursor watermark */
3361 line_time_us
= ((htotal
* 1000) / clock
);
3362 line_count
= (ILK_LP0_CURSOR_LATENCY
/ line_time_us
+ 1000) / 1000;
3363 entries
= line_count
* 64 * pixel_size
;
3364 entries
= DIV_ROUND_UP(entries
,
3365 ironlake_cursor_wm_info
.cacheline_size
);
3366 *cursor_wm
= entries
+ ironlake_cursor_wm_info
.guard_size
;
3367 if (*cursor_wm
> ironlake_cursor_wm_info
.max_wm
)
3368 *cursor_wm
= ironlake_cursor_wm_info
.max_wm
;
3373 static void ironlake_update_wm(struct drm_device
*dev
,
3374 int planea_clock
, int planeb_clock
,
3375 int sr_hdisplay
, int sr_htotal
,
3378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3379 int plane_wm
, cursor_wm
, enabled
;
3383 if (ironlake_compute_wm0(dev
, 0, &plane_wm
, &cursor_wm
)) {
3384 I915_WRITE(WM0_PIPEA_ILK
,
3385 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
3386 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3387 " plane %d, " "cursor: %d\n",
3388 plane_wm
, cursor_wm
);
3392 if (ironlake_compute_wm0(dev
, 1, &plane_wm
, &cursor_wm
)) {
3393 I915_WRITE(WM0_PIPEB_ILK
,
3394 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
3395 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3396 " plane %d, cursor: %d\n",
3397 plane_wm
, cursor_wm
);
3402 * Calculate and update the self-refresh watermark only when one
3403 * display plane is used.
3406 if (enabled
== 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3407 unsigned long line_time_us
;
3408 int small
, large
, plane_fbc
;
3409 int sr_clock
, entries
;
3410 int line_count
, line_size
;
3411 /* Read the self-refresh latency. The unit is 0.5us */
3412 int ilk_sr_latency
= I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
;
3414 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3415 line_time_us
= (sr_htotal
* 1000) / sr_clock
;
3417 /* Use ns/us then divide to preserve precision */
3418 line_count
= ((ilk_sr_latency
* 500) / line_time_us
+ 1000)
3420 line_size
= sr_hdisplay
* pixel_size
;
3422 /* Use the minimum of the small and large buffer method for primary */
3423 small
= ((sr_clock
* pixel_size
/ 1000) * (ilk_sr_latency
* 500)) / 1000;
3424 large
= line_count
* line_size
;
3426 entries
= DIV_ROUND_UP(min(small
, large
),
3427 ironlake_display_srwm_info
.cacheline_size
);
3429 plane_fbc
= entries
* 64;
3430 plane_fbc
= DIV_ROUND_UP(plane_fbc
, line_size
);
3432 plane_wm
= entries
+ ironlake_display_srwm_info
.guard_size
;
3433 if (plane_wm
> (int)ironlake_display_srwm_info
.max_wm
)
3434 plane_wm
= ironlake_display_srwm_info
.max_wm
;
3436 /* calculate the self-refresh watermark for display cursor */
3437 entries
= line_count
* pixel_size
* 64;
3438 entries
= DIV_ROUND_UP(entries
,
3439 ironlake_cursor_srwm_info
.cacheline_size
);
3441 cursor_wm
= entries
+ ironlake_cursor_srwm_info
.guard_size
;
3442 if (cursor_wm
> (int)ironlake_cursor_srwm_info
.max_wm
)
3443 cursor_wm
= ironlake_cursor_srwm_info
.max_wm
;
3445 /* configure watermark and enable self-refresh */
3446 tmp
= (WM1_LP_SR_EN
|
3447 (ilk_sr_latency
<< WM1_LP_LATENCY_SHIFT
) |
3448 (plane_fbc
<< WM1_LP_FBC_SHIFT
) |
3449 (plane_wm
<< WM1_LP_SR_SHIFT
) |
3451 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3452 " cursor %d\n", plane_wm
, plane_fbc
, cursor_wm
);
3454 I915_WRITE(WM1_LP_ILK
, tmp
);
3455 /* XXX setup WM2 and WM3 */
3459 * intel_update_watermarks - update FIFO watermark values based on current modes
3461 * Calculate watermark values for the various WM regs based on current mode
3462 * and plane configuration.
3464 * There are several cases to deal with here:
3465 * - normal (i.e. non-self-refresh)
3466 * - self-refresh (SR) mode
3467 * - lines are large relative to FIFO size (buffer can hold up to 2)
3468 * - lines are small relative to FIFO size (buffer can hold more than 2
3469 * lines), so need to account for TLB latency
3471 * The normal calculation is:
3472 * watermark = dotclock * bytes per pixel * latency
3473 * where latency is platform & configuration dependent (we assume pessimal
3476 * The SR calculation is:
3477 * watermark = (trunc(latency/line time)+1) * surface width *
3480 * line time = htotal / dotclock
3481 * surface width = hdisplay for normal plane and 64 for cursor
3482 * and latency is assumed to be high, as above.
3484 * The final value programmed to the register should always be rounded up,
3485 * and include an extra 2 entries to account for clock crossings.
3487 * We don't use the sprite, so we can ignore that. And on Crestline we have
3488 * to set the non-SR watermarks to 8.
3490 static void intel_update_watermarks(struct drm_device
*dev
)
3492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3493 struct drm_crtc
*crtc
;
3494 int sr_hdisplay
= 0;
3495 unsigned long planea_clock
= 0, planeb_clock
= 0, sr_clock
= 0;
3496 int enabled
= 0, pixel_size
= 0;
3499 if (!dev_priv
->display
.update_wm
)
3502 /* Get the clock config from both planes */
3503 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3504 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3505 if (intel_crtc
->active
) {
3507 if (intel_crtc
->plane
== 0) {
3508 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3509 intel_crtc
->pipe
, crtc
->mode
.clock
);
3510 planea_clock
= crtc
->mode
.clock
;
3512 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3513 intel_crtc
->pipe
, crtc
->mode
.clock
);
3514 planeb_clock
= crtc
->mode
.clock
;
3516 sr_hdisplay
= crtc
->mode
.hdisplay
;
3517 sr_clock
= crtc
->mode
.clock
;
3518 sr_htotal
= crtc
->mode
.htotal
;
3520 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3522 pixel_size
= 4; /* by default */
3529 dev_priv
->display
.update_wm(dev
, planea_clock
, planeb_clock
,
3530 sr_hdisplay
, sr_htotal
, pixel_size
);
3533 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
3534 struct drm_display_mode
*mode
,
3535 struct drm_display_mode
*adjusted_mode
,
3537 struct drm_framebuffer
*old_fb
)
3539 struct drm_device
*dev
= crtc
->dev
;
3540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3541 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3542 int pipe
= intel_crtc
->pipe
;
3543 int plane
= intel_crtc
->plane
;
3544 u32 fp_reg
, dpll_reg
;
3545 int refclk
, num_connectors
= 0;
3546 intel_clock_t clock
, reduced_clock
;
3547 u32 dpll
, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
3548 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
3549 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
3550 struct intel_encoder
*has_edp_encoder
= NULL
;
3551 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3552 struct intel_encoder
*encoder
;
3553 const intel_limit_t
*limit
;
3555 struct fdi_m_n m_n
= {0};
3559 drm_vblank_pre_modeset(dev
, pipe
);
3561 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
3562 if (encoder
->base
.crtc
!= crtc
)
3565 switch (encoder
->type
) {
3566 case INTEL_OUTPUT_LVDS
:
3569 case INTEL_OUTPUT_SDVO
:
3570 case INTEL_OUTPUT_HDMI
:
3572 if (encoder
->needs_tv_clock
)
3575 case INTEL_OUTPUT_DVO
:
3578 case INTEL_OUTPUT_TVOUT
:
3581 case INTEL_OUTPUT_ANALOG
:
3584 case INTEL_OUTPUT_DISPLAYPORT
:
3587 case INTEL_OUTPUT_EDP
:
3588 has_edp_encoder
= encoder
;
3595 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2) {
3596 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3597 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3599 } else if (!IS_GEN2(dev
)) {
3601 if (HAS_PCH_SPLIT(dev
))
3602 refclk
= 120000; /* 120Mhz refclk */
3608 * Returns a set of divisors for the desired target clock with the given
3609 * refclk, or FALSE. The returned values represent the clock equation:
3610 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3612 limit
= intel_limit(crtc
);
3613 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
3615 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3616 drm_vblank_post_modeset(dev
, pipe
);
3620 /* Ensure that the cursor is valid for the new mode before changing... */
3621 intel_crtc_update_cursor(crtc
, true);
3623 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
3624 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
3625 dev_priv
->lvds_downclock
,
3628 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
3630 * If the different P is found, it means that we can't
3631 * switch the display clock by using the FP0/FP1.
3632 * In such case we will disable the LVDS downclock
3635 DRM_DEBUG_KMS("Different P is found for "
3636 "LVDS clock/downclock\n");
3637 has_reduced_clock
= 0;
3640 /* SDVO TV has fixed PLL values depend on its clock range,
3641 this mirrors vbios setting. */
3642 if (is_sdvo
&& is_tv
) {
3643 if (adjusted_mode
->clock
>= 100000
3644 && adjusted_mode
->clock
< 140500) {
3650 } else if (adjusted_mode
->clock
>= 140500
3651 && adjusted_mode
->clock
<= 200000) {
3661 if (HAS_PCH_SPLIT(dev
)) {
3662 int lane
= 0, link_bw
, bpp
;
3663 /* eDP doesn't require FDI link, so just set DP M/N
3664 according to current link config */
3665 if (has_edp_encoder
) {
3666 target_clock
= mode
->clock
;
3667 intel_edp_link_config(has_edp_encoder
,
3670 /* DP over FDI requires target mode clock
3671 instead of link clock */
3673 target_clock
= mode
->clock
;
3675 target_clock
= adjusted_mode
->clock
;
3677 /* FDI is a binary signal running at ~2.7GHz, encoding
3678 * each output octet as 10 bits. The actual frequency
3679 * is stored as a divider into a 100MHz clock, and the
3680 * mode pixel clock is stored in units of 1KHz.
3681 * Hence the bw of each lane in terms of the mode signal
3684 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
3687 /* determine panel color depth */
3688 temp
= I915_READ(PIPECONF(pipe
));
3689 temp
&= ~PIPE_BPC_MASK
;
3691 /* the BPC will be 6 if it is 18-bit LVDS panel */
3692 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
3696 } else if (has_edp_encoder
|| (is_dp
&& intel_pch_has_edp(crtc
))) {
3697 switch (dev_priv
->edp_bpp
/3) {
3713 I915_WRITE(PIPECONF(pipe
), temp
);
3715 switch (temp
& PIPE_BPC_MASK
) {
3729 DRM_ERROR("unknown pipe bpc value\n");
3735 * Account for spread spectrum to avoid
3736 * oversubscribing the link. Max center spread
3737 * is 2.5%; use 5% for safety's sake.
3739 u32 bps
= target_clock
* bpp
* 21 / 20;
3740 lane
= bps
/ (link_bw
* 8) + 1;
3743 intel_crtc
->fdi_lanes
= lane
;
3745 ironlake_compute_m_n(bpp
, lane
, target_clock
, link_bw
, &m_n
);
3748 /* Ironlake: try to setup display ref clock before DPLL
3749 * enabling. This is only under driver's control after
3750 * PCH B stepping, previous chipset stepping should be
3751 * ignoring this setting.
3753 if (HAS_PCH_SPLIT(dev
)) {
3754 temp
= I915_READ(PCH_DREF_CONTROL
);
3755 /* Always enable nonspread source */
3756 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
3757 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
3758 temp
&= ~DREF_SSC_SOURCE_MASK
;
3759 temp
|= DREF_SSC_SOURCE_ENABLE
;
3760 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3762 POSTING_READ(PCH_DREF_CONTROL
);
3765 if (has_edp_encoder
) {
3766 if (dev_priv
->lvds_use_ssc
) {
3767 temp
|= DREF_SSC1_ENABLE
;
3768 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3770 POSTING_READ(PCH_DREF_CONTROL
);
3773 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
3774 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
3776 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
3778 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3782 if (IS_PINEVIEW(dev
)) {
3783 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
3784 if (has_reduced_clock
)
3785 fp2
= (1 << reduced_clock
.n
) << 16 |
3786 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
3788 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
3789 if (has_reduced_clock
)
3790 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
3795 if (!HAS_PCH_SPLIT(dev
))
3796 dpll
= DPLL_VGA_MODE_DIS
;
3798 if (!IS_GEN2(dev
)) {
3800 dpll
|= DPLLB_MODE_LVDS
;
3802 dpll
|= DPLLB_MODE_DAC_SERIAL
;
3804 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
3805 if (pixel_multiplier
> 1) {
3806 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3807 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
3808 else if (HAS_PCH_SPLIT(dev
))
3809 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
3811 dpll
|= DPLL_DVO_HIGH_SPEED
;
3814 dpll
|= DPLL_DVO_HIGH_SPEED
;
3816 /* compute bitmask from p1 value */
3817 if (IS_PINEVIEW(dev
))
3818 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
3820 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3822 if (HAS_PCH_SPLIT(dev
))
3823 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3824 if (IS_G4X(dev
) && has_reduced_clock
)
3825 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3829 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
3832 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
3835 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
3838 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
3841 if (INTEL_INFO(dev
)->gen
>= 4 && !HAS_PCH_SPLIT(dev
))
3842 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
3845 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3848 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
3850 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3852 dpll
|= PLL_P2_DIVIDE_BY_4
;
3856 if (is_sdvo
&& is_tv
)
3857 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
3859 /* XXX: just matching BIOS for now */
3860 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3862 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2)
3863 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
3865 dpll
|= PLL_REF_INPUT_DREFCLK
;
3867 /* setup pipeconf */
3868 pipeconf
= I915_READ(PIPECONF(pipe
));
3870 /* Set up the display plane register */
3871 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3873 /* Ironlake's plane is forced to pipe, bit 24 is to
3874 enable color space conversion */
3875 if (!HAS_PCH_SPLIT(dev
)) {
3877 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
3879 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
3882 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
3883 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3886 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3890 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
3891 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
3893 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
3896 dspcntr
|= DISPLAY_PLANE_ENABLE
;
3897 pipeconf
|= PIPECONF_ENABLE
;
3898 dpll
|= DPLL_VCO_ENABLE
;
3900 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
3901 drm_mode_debug_printmodeline(mode
);
3903 /* assign to Ironlake registers */
3904 if (HAS_PCH_SPLIT(dev
)) {
3905 fp_reg
= PCH_FP0(pipe
);
3906 dpll_reg
= PCH_DPLL(pipe
);
3909 dpll_reg
= DPLL(pipe
);
3912 if (!has_edp_encoder
) {
3913 I915_WRITE(fp_reg
, fp
);
3914 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3916 POSTING_READ(dpll_reg
);
3920 /* enable transcoder DPLL */
3921 if (HAS_PCH_CPT(dev
)) {
3922 temp
= I915_READ(PCH_DPLL_SEL
);
3924 temp
|= TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
;
3926 temp
|= TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
;
3927 I915_WRITE(PCH_DPLL_SEL
, temp
);
3929 POSTING_READ(PCH_DPLL_SEL
);
3933 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3934 * This is an exception to the general rule that mode_set doesn't turn
3939 if (HAS_PCH_SPLIT(dev
))
3942 temp
= I915_READ(reg
);
3943 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
3945 if (HAS_PCH_CPT(dev
))
3946 temp
|= PORT_TRANS_B_SEL_CPT
;
3948 temp
|= LVDS_PIPEB_SELECT
;
3950 if (HAS_PCH_CPT(dev
))
3951 temp
&= ~PORT_TRANS_SEL_MASK
;
3953 temp
&= ~LVDS_PIPEB_SELECT
;
3955 /* set the corresponsding LVDS_BORDER bit */
3956 temp
|= dev_priv
->lvds_border_bits
;
3957 /* Set the B0-B3 data pairs corresponding to whether we're going to
3958 * set the DPLLs for dual-channel mode or not.
3961 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
3963 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
3965 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3966 * appropriately here, but we need to look more thoroughly into how
3967 * panels behave in the two modes.
3969 /* set the dithering flag on non-PCH LVDS as needed */
3970 if (INTEL_INFO(dev
)->gen
>= 4 && !HAS_PCH_SPLIT(dev
)) {
3971 if (dev_priv
->lvds_dither
)
3972 temp
|= LVDS_ENABLE_DITHER
;
3974 temp
&= ~LVDS_ENABLE_DITHER
;
3976 I915_WRITE(reg
, temp
);
3979 /* set the dithering flag and clear for anything other than a panel. */
3980 if (HAS_PCH_SPLIT(dev
)) {
3981 pipeconf
&= ~PIPECONF_DITHER_EN
;
3982 pipeconf
&= ~PIPECONF_DITHER_TYPE_MASK
;
3983 if (dev_priv
->lvds_dither
&& (is_lvds
|| has_edp_encoder
)) {
3984 pipeconf
|= PIPECONF_DITHER_EN
;
3985 pipeconf
|= PIPECONF_DITHER_TYPE_ST1
;
3990 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
3991 else if (HAS_PCH_SPLIT(dev
)) {
3992 /* For non-DP output, clear any trans DP clock recovery setting.*/
3994 I915_WRITE(TRANSA_DATA_M1
, 0);
3995 I915_WRITE(TRANSA_DATA_N1
, 0);
3996 I915_WRITE(TRANSA_DP_LINK_M1
, 0);
3997 I915_WRITE(TRANSA_DP_LINK_N1
, 0);
3999 I915_WRITE(TRANSB_DATA_M1
, 0);
4000 I915_WRITE(TRANSB_DATA_N1
, 0);
4001 I915_WRITE(TRANSB_DP_LINK_M1
, 0);
4002 I915_WRITE(TRANSB_DP_LINK_N1
, 0);
4006 if (!has_edp_encoder
) {
4007 I915_WRITE(fp_reg
, fp
);
4008 I915_WRITE(dpll_reg
, dpll
);
4010 /* Wait for the clocks to stabilize. */
4011 POSTING_READ(dpll_reg
);
4014 if (INTEL_INFO(dev
)->gen
>= 4 && !HAS_PCH_SPLIT(dev
)) {
4017 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4019 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4023 I915_WRITE(DPLL_MD(pipe
), temp
);
4025 /* write it again -- the BIOS does, after all */
4026 I915_WRITE(dpll_reg
, dpll
);
4029 /* Wait for the clocks to stabilize. */
4030 POSTING_READ(dpll_reg
);
4034 intel_crtc
->lowfreq_avail
= false;
4035 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
4036 I915_WRITE(fp_reg
+ 4, fp2
);
4037 intel_crtc
->lowfreq_avail
= true;
4038 if (HAS_PIPE_CXSR(dev
)) {
4039 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4040 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4043 I915_WRITE(fp_reg
+ 4, fp
);
4044 if (HAS_PIPE_CXSR(dev
)) {
4045 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4046 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4050 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4051 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4052 /* the chip adds 2 halflines automatically */
4053 adjusted_mode
->crtc_vdisplay
-= 1;
4054 adjusted_mode
->crtc_vtotal
-= 1;
4055 adjusted_mode
->crtc_vblank_start
-= 1;
4056 adjusted_mode
->crtc_vblank_end
-= 1;
4057 adjusted_mode
->crtc_vsync_end
-= 1;
4058 adjusted_mode
->crtc_vsync_start
-= 1;
4060 pipeconf
&= ~PIPECONF_INTERLACE_W_FIELD_INDICATION
; /* progressive */
4062 I915_WRITE(HTOTAL(pipe
),
4063 (adjusted_mode
->crtc_hdisplay
- 1) |
4064 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4065 I915_WRITE(HBLANK(pipe
),
4066 (adjusted_mode
->crtc_hblank_start
- 1) |
4067 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4068 I915_WRITE(HSYNC(pipe
),
4069 (adjusted_mode
->crtc_hsync_start
- 1) |
4070 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4072 I915_WRITE(VTOTAL(pipe
),
4073 (adjusted_mode
->crtc_vdisplay
- 1) |
4074 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4075 I915_WRITE(VBLANK(pipe
),
4076 (adjusted_mode
->crtc_vblank_start
- 1) |
4077 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4078 I915_WRITE(VSYNC(pipe
),
4079 (adjusted_mode
->crtc_vsync_start
- 1) |
4080 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4082 /* pipesrc and dspsize control the size that is scaled from,
4083 * which should always be the user's requested size.
4085 if (!HAS_PCH_SPLIT(dev
)) {
4086 I915_WRITE(DSPSIZE(plane
),
4087 ((mode
->vdisplay
- 1) << 16) |
4088 (mode
->hdisplay
- 1));
4089 I915_WRITE(DSPPOS(plane
), 0);
4091 I915_WRITE(PIPESRC(pipe
),
4092 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4094 if (HAS_PCH_SPLIT(dev
)) {
4095 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
4096 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
4097 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
4098 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
4100 if (has_edp_encoder
) {
4101 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
4103 /* enable FDI RX PLL too */
4104 reg
= FDI_RX_CTL(pipe
);
4105 temp
= I915_READ(reg
);
4106 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
4111 /* enable FDI TX PLL too */
4112 reg
= FDI_TX_CTL(pipe
);
4113 temp
= I915_READ(reg
);
4114 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
4116 /* enable FDI RX PCDCLK */
4117 reg
= FDI_RX_CTL(pipe
);
4118 temp
= I915_READ(reg
);
4119 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
4126 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4127 POSTING_READ(PIPECONF(pipe
));
4129 intel_wait_for_vblank(dev
, pipe
);
4131 if (IS_IRONLAKE(dev
)) {
4132 /* enable address swizzle for tiling buffer */
4133 temp
= I915_READ(DISP_ARB_CTL
);
4134 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
4137 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4139 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4141 intel_update_watermarks(dev
);
4143 drm_vblank_post_modeset(dev
, pipe
);
4148 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4149 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4151 struct drm_device
*dev
= crtc
->dev
;
4152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4153 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4154 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
4157 /* The clocks have to be on to load the palette. */
4161 /* use legacy palette for Ironlake */
4162 if (HAS_PCH_SPLIT(dev
))
4163 palreg
= (intel_crtc
->pipe
== 0) ? LGC_PALETTE_A
:
4166 for (i
= 0; i
< 256; i
++) {
4167 I915_WRITE(palreg
+ 4 * i
,
4168 (intel_crtc
->lut_r
[i
] << 16) |
4169 (intel_crtc
->lut_g
[i
] << 8) |
4170 intel_crtc
->lut_b
[i
]);
4174 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
4176 struct drm_device
*dev
= crtc
->dev
;
4177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4178 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4179 bool visible
= base
!= 0;
4182 if (intel_crtc
->cursor_visible
== visible
)
4185 cntl
= I915_READ(CURACNTR
);
4187 /* On these chipsets we can only modify the base whilst
4188 * the cursor is disabled.
4190 I915_WRITE(CURABASE
, base
);
4192 cntl
&= ~(CURSOR_FORMAT_MASK
);
4193 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4194 cntl
|= CURSOR_ENABLE
|
4195 CURSOR_GAMMA_ENABLE
|
4198 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
4199 I915_WRITE(CURACNTR
, cntl
);
4201 intel_crtc
->cursor_visible
= visible
;
4204 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
4206 struct drm_device
*dev
= crtc
->dev
;
4207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4208 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4209 int pipe
= intel_crtc
->pipe
;
4210 bool visible
= base
!= 0;
4212 if (intel_crtc
->cursor_visible
!= visible
) {
4213 uint32_t cntl
= I915_READ(pipe
== 0 ? CURACNTR
: CURBCNTR
);
4215 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
4216 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
4217 cntl
|= pipe
<< 28; /* Connect to correct pipe */
4219 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
4220 cntl
|= CURSOR_MODE_DISABLE
;
4222 I915_WRITE(pipe
== 0 ? CURACNTR
: CURBCNTR
, cntl
);
4224 intel_crtc
->cursor_visible
= visible
;
4226 /* and commit changes on next vblank */
4227 I915_WRITE(pipe
== 0 ? CURABASE
: CURBBASE
, base
);
4230 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4231 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
4234 struct drm_device
*dev
= crtc
->dev
;
4235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4236 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4237 int pipe
= intel_crtc
->pipe
;
4238 int x
= intel_crtc
->cursor_x
;
4239 int y
= intel_crtc
->cursor_y
;
4245 if (on
&& crtc
->enabled
&& crtc
->fb
) {
4246 base
= intel_crtc
->cursor_addr
;
4247 if (x
> (int) crtc
->fb
->width
)
4250 if (y
> (int) crtc
->fb
->height
)
4256 if (x
+ intel_crtc
->cursor_width
< 0)
4259 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
4262 pos
|= x
<< CURSOR_X_SHIFT
;
4265 if (y
+ intel_crtc
->cursor_height
< 0)
4268 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
4271 pos
|= y
<< CURSOR_Y_SHIFT
;
4273 visible
= base
!= 0;
4274 if (!visible
&& !intel_crtc
->cursor_visible
)
4277 I915_WRITE(pipe
== 0 ? CURAPOS
: CURBPOS
, pos
);
4278 if (IS_845G(dev
) || IS_I865G(dev
))
4279 i845_update_cursor(crtc
, base
);
4281 i9xx_update_cursor(crtc
, base
);
4284 intel_mark_busy(dev
, to_intel_framebuffer(crtc
->fb
)->obj
);
4287 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
4288 struct drm_file
*file_priv
,
4290 uint32_t width
, uint32_t height
)
4292 struct drm_device
*dev
= crtc
->dev
;
4293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4294 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4295 struct drm_gem_object
*bo
;
4296 struct drm_i915_gem_object
*obj_priv
;
4300 DRM_DEBUG_KMS("\n");
4302 /* if we want to turn off the cursor ignore width and height */
4304 DRM_DEBUG_KMS("cursor off\n");
4307 mutex_lock(&dev
->struct_mutex
);
4311 /* Currently we only support 64x64 cursors */
4312 if (width
!= 64 || height
!= 64) {
4313 DRM_ERROR("we currently only support 64x64 cursors\n");
4317 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
4321 obj_priv
= to_intel_bo(bo
);
4323 if (bo
->size
< width
* height
* 4) {
4324 DRM_ERROR("buffer is to small\n");
4329 /* we only need to pin inside GTT if cursor is non-phy */
4330 mutex_lock(&dev
->struct_mutex
);
4331 if (!dev_priv
->info
->cursor_needs_physical
) {
4332 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
4334 DRM_ERROR("failed to pin cursor bo\n");
4338 ret
= i915_gem_object_set_to_gtt_domain(bo
, 0);
4340 DRM_ERROR("failed to move cursor bo into the GTT\n");
4344 addr
= obj_priv
->gtt_offset
;
4346 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
4347 ret
= i915_gem_attach_phys_object(dev
, bo
,
4348 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
4351 DRM_ERROR("failed to attach phys object\n");
4354 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
4358 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
4361 if (intel_crtc
->cursor_bo
) {
4362 if (dev_priv
->info
->cursor_needs_physical
) {
4363 if (intel_crtc
->cursor_bo
!= bo
)
4364 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
4366 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
4367 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
4370 mutex_unlock(&dev
->struct_mutex
);
4372 intel_crtc
->cursor_addr
= addr
;
4373 intel_crtc
->cursor_bo
= bo
;
4374 intel_crtc
->cursor_width
= width
;
4375 intel_crtc
->cursor_height
= height
;
4377 intel_crtc_update_cursor(crtc
, true);
4381 i915_gem_object_unpin(bo
);
4383 mutex_unlock(&dev
->struct_mutex
);
4385 drm_gem_object_unreference_unlocked(bo
);
4389 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
4391 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4393 intel_crtc
->cursor_x
= x
;
4394 intel_crtc
->cursor_y
= y
;
4396 intel_crtc_update_cursor(crtc
, true);
4401 /** Sets the color ramps on behalf of RandR */
4402 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
4403 u16 blue
, int regno
)
4405 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4407 intel_crtc
->lut_r
[regno
] = red
>> 8;
4408 intel_crtc
->lut_g
[regno
] = green
>> 8;
4409 intel_crtc
->lut_b
[regno
] = blue
>> 8;
4412 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4413 u16
*blue
, int regno
)
4415 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4417 *red
= intel_crtc
->lut_r
[regno
] << 8;
4418 *green
= intel_crtc
->lut_g
[regno
] << 8;
4419 *blue
= intel_crtc
->lut_b
[regno
] << 8;
4422 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4423 u16
*blue
, uint32_t start
, uint32_t size
)
4425 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
4426 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4428 for (i
= start
; i
< end
; i
++) {
4429 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
4430 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
4431 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
4434 intel_crtc_load_lut(crtc
);
4438 * Get a pipe with a simple mode set on it for doing load-based monitor
4441 * It will be up to the load-detect code to adjust the pipe as appropriate for
4442 * its requirements. The pipe will be connected to no other encoders.
4444 * Currently this code will only succeed if there is a pipe with no encoders
4445 * configured for it. In the future, it could choose to temporarily disable
4446 * some outputs to free up a pipe for its use.
4448 * \return crtc, or NULL if no pipes are available.
4451 /* VESA 640x480x72Hz mode to set on the pipe */
4452 static struct drm_display_mode load_detect_mode
= {
4453 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
4454 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
4457 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4458 struct drm_connector
*connector
,
4459 struct drm_display_mode
*mode
,
4462 struct intel_crtc
*intel_crtc
;
4463 struct drm_crtc
*possible_crtc
;
4464 struct drm_crtc
*supported_crtc
=NULL
;
4465 struct drm_encoder
*encoder
= &intel_encoder
->base
;
4466 struct drm_crtc
*crtc
= NULL
;
4467 struct drm_device
*dev
= encoder
->dev
;
4468 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4469 struct drm_crtc_helper_funcs
*crtc_funcs
;
4473 * Algorithm gets a little messy:
4474 * - if the connector already has an assigned crtc, use it (but make
4475 * sure it's on first)
4476 * - try to find the first unused crtc that can drive this connector,
4477 * and use that if we find one
4478 * - if there are no unused crtcs available, try to use the first
4479 * one we found that supports the connector
4482 /* See if we already have a CRTC for this connector */
4483 if (encoder
->crtc
) {
4484 crtc
= encoder
->crtc
;
4485 /* Make sure the crtc and connector are running */
4486 intel_crtc
= to_intel_crtc(crtc
);
4487 *dpms_mode
= intel_crtc
->dpms_mode
;
4488 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4489 crtc_funcs
= crtc
->helper_private
;
4490 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4491 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
4496 /* Find an unused one (if possible) */
4497 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
4499 if (!(encoder
->possible_crtcs
& (1 << i
)))
4501 if (!possible_crtc
->enabled
) {
4502 crtc
= possible_crtc
;
4505 if (!supported_crtc
)
4506 supported_crtc
= possible_crtc
;
4510 * If we didn't find an unused CRTC, don't use any.
4516 encoder
->crtc
= crtc
;
4517 connector
->encoder
= encoder
;
4518 intel_encoder
->load_detect_temp
= true;
4520 intel_crtc
= to_intel_crtc(crtc
);
4521 *dpms_mode
= intel_crtc
->dpms_mode
;
4523 if (!crtc
->enabled
) {
4525 mode
= &load_detect_mode
;
4526 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
4528 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4529 crtc_funcs
= crtc
->helper_private
;
4530 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4533 /* Add this connector to the crtc */
4534 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
4535 encoder_funcs
->commit(encoder
);
4537 /* let the connector get through one full cycle before testing */
4538 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4543 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4544 struct drm_connector
*connector
, int dpms_mode
)
4546 struct drm_encoder
*encoder
= &intel_encoder
->base
;
4547 struct drm_device
*dev
= encoder
->dev
;
4548 struct drm_crtc
*crtc
= encoder
->crtc
;
4549 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4550 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
4552 if (intel_encoder
->load_detect_temp
) {
4553 encoder
->crtc
= NULL
;
4554 connector
->encoder
= NULL
;
4555 intel_encoder
->load_detect_temp
= false;
4556 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
4557 drm_helper_disable_unused_functions(dev
);
4560 /* Switch crtc and encoder back off if necessary */
4561 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
4562 if (encoder
->crtc
== crtc
)
4563 encoder_funcs
->dpms(encoder
, dpms_mode
);
4564 crtc_funcs
->dpms(crtc
, dpms_mode
);
4568 /* Returns the clock of the currently programmed mode of the given pipe. */
4569 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
4571 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4572 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4573 int pipe
= intel_crtc
->pipe
;
4574 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
4576 intel_clock_t clock
;
4578 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
4579 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
4581 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
4583 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
4584 if (IS_PINEVIEW(dev
)) {
4585 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
4586 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4588 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
4589 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4592 if (!IS_GEN2(dev
)) {
4593 if (IS_PINEVIEW(dev
))
4594 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
4595 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
4597 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
4598 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4600 switch (dpll
& DPLL_MODE_MASK
) {
4601 case DPLLB_MODE_DAC_SERIAL
:
4602 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
4605 case DPLLB_MODE_LVDS
:
4606 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
4610 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4611 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
4615 /* XXX: Handle the 100Mhz refclk */
4616 intel_clock(dev
, 96000, &clock
);
4618 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
4621 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
4622 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4625 if ((dpll
& PLL_REF_INPUT_MASK
) ==
4626 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
4627 /* XXX: might not be 66MHz */
4628 intel_clock(dev
, 66000, &clock
);
4630 intel_clock(dev
, 48000, &clock
);
4632 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
4635 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
4636 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
4638 if (dpll
& PLL_P2_DIVIDE_BY_4
)
4643 intel_clock(dev
, 48000, &clock
);
4647 /* XXX: It would be nice to validate the clocks, but we can't reuse
4648 * i830PllIsValid() because it relies on the xf86_config connector
4649 * configuration being accurate, which it isn't necessarily.
4655 /** Returns the currently programmed mode of the given pipe. */
4656 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
4657 struct drm_crtc
*crtc
)
4659 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4660 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4661 int pipe
= intel_crtc
->pipe
;
4662 struct drm_display_mode
*mode
;
4663 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
4664 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
4665 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
4666 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
4668 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
4672 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
4673 mode
->hdisplay
= (htot
& 0xffff) + 1;
4674 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
4675 mode
->hsync_start
= (hsync
& 0xffff) + 1;
4676 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
4677 mode
->vdisplay
= (vtot
& 0xffff) + 1;
4678 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
4679 mode
->vsync_start
= (vsync
& 0xffff) + 1;
4680 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
4682 drm_mode_set_name(mode
);
4683 drm_mode_set_crtcinfo(mode
, 0);
4688 #define GPU_IDLE_TIMEOUT 500 /* ms */
4690 /* When this timer fires, we've been idle for awhile */
4691 static void intel_gpu_idle_timer(unsigned long arg
)
4693 struct drm_device
*dev
= (struct drm_device
*)arg
;
4694 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4696 dev_priv
->busy
= false;
4698 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4701 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4703 static void intel_crtc_idle_timer(unsigned long arg
)
4705 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
4706 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4707 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
4709 intel_crtc
->busy
= false;
4711 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4714 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
4716 struct drm_device
*dev
= crtc
->dev
;
4717 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4718 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4719 int pipe
= intel_crtc
->pipe
;
4720 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4721 int dpll
= I915_READ(dpll_reg
);
4723 if (HAS_PCH_SPLIT(dev
))
4726 if (!dev_priv
->lvds_downclock_avail
)
4729 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
4730 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4732 /* Unlock panel regs */
4733 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) |
4736 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
4737 I915_WRITE(dpll_reg
, dpll
);
4738 dpll
= I915_READ(dpll_reg
);
4739 intel_wait_for_vblank(dev
, pipe
);
4740 dpll
= I915_READ(dpll_reg
);
4741 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
4742 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4744 /* ...and lock them again */
4745 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4748 /* Schedule downclock */
4749 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4750 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4753 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
4755 struct drm_device
*dev
= crtc
->dev
;
4756 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4757 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4758 int pipe
= intel_crtc
->pipe
;
4759 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4760 int dpll
= I915_READ(dpll_reg
);
4762 if (HAS_PCH_SPLIT(dev
))
4765 if (!dev_priv
->lvds_downclock_avail
)
4769 * Since this is called by a timer, we should never get here in
4772 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
4773 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4775 /* Unlock panel regs */
4776 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) |
4779 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
4780 I915_WRITE(dpll_reg
, dpll
);
4781 dpll
= I915_READ(dpll_reg
);
4782 intel_wait_for_vblank(dev
, pipe
);
4783 dpll
= I915_READ(dpll_reg
);
4784 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
4785 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4787 /* ...and lock them again */
4788 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4794 * intel_idle_update - adjust clocks for idleness
4795 * @work: work struct
4797 * Either the GPU or display (or both) went idle. Check the busy status
4798 * here and adjust the CRTC and GPU clocks as necessary.
4800 static void intel_idle_update(struct work_struct
*work
)
4802 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
4804 struct drm_device
*dev
= dev_priv
->dev
;
4805 struct drm_crtc
*crtc
;
4806 struct intel_crtc
*intel_crtc
;
4809 if (!i915_powersave
)
4812 mutex_lock(&dev
->struct_mutex
);
4814 i915_update_gfx_val(dev_priv
);
4816 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4817 /* Skip inactive CRTCs */
4822 intel_crtc
= to_intel_crtc(crtc
);
4823 if (!intel_crtc
->busy
)
4824 intel_decrease_pllclock(crtc
);
4827 if ((enabled
== 1) && (IS_I945G(dev
) || IS_I945GM(dev
))) {
4828 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4829 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
4832 mutex_unlock(&dev
->struct_mutex
);
4836 * intel_mark_busy - mark the GPU and possibly the display busy
4838 * @obj: object we're operating on
4840 * Callers can use this function to indicate that the GPU is busy processing
4841 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4842 * buffer), we'll also mark the display as busy, so we know to increase its
4845 void intel_mark_busy(struct drm_device
*dev
, struct drm_gem_object
*obj
)
4847 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4848 struct drm_crtc
*crtc
= NULL
;
4849 struct intel_framebuffer
*intel_fb
;
4850 struct intel_crtc
*intel_crtc
;
4852 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4855 if (!dev_priv
->busy
) {
4856 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4859 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4860 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4861 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4862 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4864 dev_priv
->busy
= true;
4866 mod_timer(&dev_priv
->idle_timer
, jiffies
+
4867 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
4869 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4873 intel_crtc
= to_intel_crtc(crtc
);
4874 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4875 if (intel_fb
->obj
== obj
) {
4876 if (!intel_crtc
->busy
) {
4877 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4880 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4881 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4882 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4883 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4885 /* Non-busy -> busy, upclock */
4886 intel_increase_pllclock(crtc
);
4887 intel_crtc
->busy
= true;
4889 /* Busy -> busy, put off timer */
4890 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4891 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4897 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
4899 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4900 struct drm_device
*dev
= crtc
->dev
;
4901 struct intel_unpin_work
*work
;
4902 unsigned long flags
;
4904 spin_lock_irqsave(&dev
->event_lock
, flags
);
4905 work
= intel_crtc
->unpin_work
;
4906 intel_crtc
->unpin_work
= NULL
;
4907 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4910 cancel_work_sync(&work
->work
);
4914 drm_crtc_cleanup(crtc
);
4919 static void intel_unpin_work_fn(struct work_struct
*__work
)
4921 struct intel_unpin_work
*work
=
4922 container_of(__work
, struct intel_unpin_work
, work
);
4924 mutex_lock(&work
->dev
->struct_mutex
);
4925 i915_gem_object_unpin(work
->old_fb_obj
);
4926 drm_gem_object_unreference(work
->pending_flip_obj
);
4927 drm_gem_object_unreference(work
->old_fb_obj
);
4928 mutex_unlock(&work
->dev
->struct_mutex
);
4932 static void do_intel_finish_page_flip(struct drm_device
*dev
,
4933 struct drm_crtc
*crtc
)
4935 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4936 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4937 struct intel_unpin_work
*work
;
4938 struct drm_i915_gem_object
*obj_priv
;
4939 struct drm_pending_vblank_event
*e
;
4941 unsigned long flags
;
4943 /* Ignore early vblank irqs */
4944 if (intel_crtc
== NULL
)
4947 spin_lock_irqsave(&dev
->event_lock
, flags
);
4948 work
= intel_crtc
->unpin_work
;
4949 if (work
== NULL
|| !work
->pending
) {
4950 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4954 intel_crtc
->unpin_work
= NULL
;
4955 drm_vblank_put(dev
, intel_crtc
->pipe
);
4959 do_gettimeofday(&now
);
4960 e
->event
.sequence
= drm_vblank_count(dev
, intel_crtc
->pipe
);
4961 e
->event
.tv_sec
= now
.tv_sec
;
4962 e
->event
.tv_usec
= now
.tv_usec
;
4963 list_add_tail(&e
->base
.link
,
4964 &e
->base
.file_priv
->event_list
);
4965 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
4968 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4970 obj_priv
= to_intel_bo(work
->pending_flip_obj
);
4972 /* Initial scanout buffer will have a 0 pending flip count */
4973 if ((atomic_read(&obj_priv
->pending_flip
) == 0) ||
4974 atomic_dec_and_test(&obj_priv
->pending_flip
))
4975 DRM_WAKEUP(&dev_priv
->pending_flip_queue
);
4976 schedule_work(&work
->work
);
4978 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
4981 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
4983 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4984 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
4986 do_intel_finish_page_flip(dev
, crtc
);
4989 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
4991 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4992 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
4994 do_intel_finish_page_flip(dev
, crtc
);
4997 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
4999 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5000 struct intel_crtc
*intel_crtc
=
5001 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
5002 unsigned long flags
;
5004 spin_lock_irqsave(&dev
->event_lock
, flags
);
5005 if (intel_crtc
->unpin_work
) {
5006 if ((++intel_crtc
->unpin_work
->pending
) > 1)
5007 DRM_ERROR("Prepared flip multiple times\n");
5009 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5011 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5014 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
5015 struct drm_framebuffer
*fb
,
5016 struct drm_pending_vblank_event
*event
)
5018 struct drm_device
*dev
= crtc
->dev
;
5019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5020 struct intel_framebuffer
*intel_fb
;
5021 struct drm_i915_gem_object
*obj_priv
;
5022 struct drm_gem_object
*obj
;
5023 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5024 struct intel_unpin_work
*work
;
5025 unsigned long flags
, offset
;
5026 int pipe
= intel_crtc
->pipe
;
5030 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
5034 work
->event
= event
;
5035 work
->dev
= crtc
->dev
;
5036 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5037 work
->old_fb_obj
= intel_fb
->obj
;
5038 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
5040 /* We borrow the event spin lock for protecting unpin_work */
5041 spin_lock_irqsave(&dev
->event_lock
, flags
);
5042 if (intel_crtc
->unpin_work
) {
5043 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5046 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5049 intel_crtc
->unpin_work
= work
;
5050 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5052 intel_fb
= to_intel_framebuffer(fb
);
5053 obj
= intel_fb
->obj
;
5055 mutex_lock(&dev
->struct_mutex
);
5056 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, true);
5060 /* Reference the objects for the scheduled work. */
5061 drm_gem_object_reference(work
->old_fb_obj
);
5062 drm_gem_object_reference(obj
);
5066 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
5070 obj_priv
= to_intel_bo(obj
);
5071 atomic_inc(&obj_priv
->pending_flip
);
5072 work
->pending_flip_obj
= obj
;
5074 if (IS_GEN3(dev
) || IS_GEN2(dev
)) {
5077 /* Can't queue multiple flips, so wait for the previous
5078 * one to finish before executing the next.
5081 if (intel_crtc
->plane
)
5082 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
5084 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
5085 OUT_RING(MI_WAIT_FOR_EVENT
| flip_mask
);
5090 work
->enable_stall_check
= true;
5092 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5093 offset
= crtc
->y
* fb
->pitch
+ crtc
->x
* fb
->bits_per_pixel
/8;
5096 switch(INTEL_INFO(dev
)->gen
) {
5098 OUT_RING(MI_DISPLAY_FLIP
|
5099 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5100 OUT_RING(fb
->pitch
);
5101 OUT_RING(obj_priv
->gtt_offset
+ offset
);
5106 OUT_RING(MI_DISPLAY_FLIP_I915
|
5107 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5108 OUT_RING(fb
->pitch
);
5109 OUT_RING(obj_priv
->gtt_offset
+ offset
);
5115 /* i965+ uses the linear or tiled offsets from the
5116 * Display Registers (which do not change across a page-flip)
5117 * so we need only reprogram the base address.
5119 OUT_RING(MI_DISPLAY_FLIP
|
5120 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5121 OUT_RING(fb
->pitch
);
5122 OUT_RING(obj_priv
->gtt_offset
| obj_priv
->tiling_mode
);
5124 /* XXX Enabling the panel-fitter across page-flip is so far
5125 * untested on non-native modes, so ignore it for now.
5126 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5129 pipesrc
= I915_READ(pipe
== 0 ? PIPEASRC
: PIPEBSRC
) & 0x0fff0fff;
5130 OUT_RING(pf
| pipesrc
);
5134 OUT_RING(MI_DISPLAY_FLIP
|
5135 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5136 OUT_RING(fb
->pitch
| obj_priv
->tiling_mode
);
5137 OUT_RING(obj_priv
->gtt_offset
);
5139 pf
= I915_READ(pipe
== 0 ? PFA_CTL_1
: PFB_CTL_1
) & PF_ENABLE
;
5140 pipesrc
= I915_READ(pipe
== 0 ? PIPEASRC
: PIPEBSRC
) & 0x0fff0fff;
5141 OUT_RING(pf
| pipesrc
);
5146 mutex_unlock(&dev
->struct_mutex
);
5148 trace_i915_flip_request(intel_crtc
->plane
, obj
);
5153 drm_gem_object_unreference(work
->old_fb_obj
);
5154 drm_gem_object_unreference(obj
);
5156 mutex_unlock(&dev
->struct_mutex
);
5158 spin_lock_irqsave(&dev
->event_lock
, flags
);
5159 intel_crtc
->unpin_work
= NULL
;
5160 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5167 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
5168 .dpms
= intel_crtc_dpms
,
5169 .mode_fixup
= intel_crtc_mode_fixup
,
5170 .mode_set
= intel_crtc_mode_set
,
5171 .mode_set_base
= intel_pipe_set_base
,
5172 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
5173 .load_lut
= intel_crtc_load_lut
,
5174 .disable
= intel_crtc_disable
,
5177 static const struct drm_crtc_funcs intel_crtc_funcs
= {
5178 .cursor_set
= intel_crtc_cursor_set
,
5179 .cursor_move
= intel_crtc_cursor_move
,
5180 .gamma_set
= intel_crtc_gamma_set
,
5181 .set_config
= drm_crtc_helper_set_config
,
5182 .destroy
= intel_crtc_destroy
,
5183 .page_flip
= intel_crtc_page_flip
,
5187 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
5189 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5190 struct intel_crtc
*intel_crtc
;
5193 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
5194 if (intel_crtc
== NULL
)
5197 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
5199 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
5200 for (i
= 0; i
< 256; i
++) {
5201 intel_crtc
->lut_r
[i
] = i
;
5202 intel_crtc
->lut_g
[i
] = i
;
5203 intel_crtc
->lut_b
[i
] = i
;
5206 /* Swap pipes & planes for FBC on pre-965 */
5207 intel_crtc
->pipe
= pipe
;
5208 intel_crtc
->plane
= pipe
;
5209 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
5210 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5211 intel_crtc
->plane
= !pipe
;
5214 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
5215 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
5216 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
5217 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
5219 intel_crtc
->cursor_addr
= 0;
5220 intel_crtc
->dpms_mode
= -1;
5221 intel_crtc
->active
= true; /* force the pipe off on setup_init_config */
5223 if (HAS_PCH_SPLIT(dev
)) {
5224 intel_helper_funcs
.prepare
= ironlake_crtc_prepare
;
5225 intel_helper_funcs
.commit
= ironlake_crtc_commit
;
5227 intel_helper_funcs
.prepare
= i9xx_crtc_prepare
;
5228 intel_helper_funcs
.commit
= i9xx_crtc_commit
;
5231 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
5233 intel_crtc
->busy
= false;
5235 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
5236 (unsigned long)intel_crtc
);
5239 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
5240 struct drm_file
*file_priv
)
5242 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5243 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
5244 struct drm_mode_object
*drmmode_obj
;
5245 struct intel_crtc
*crtc
;
5248 DRM_ERROR("called with no initialization\n");
5252 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
5253 DRM_MODE_OBJECT_CRTC
);
5256 DRM_ERROR("no such CRTC id\n");
5260 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
5261 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
5266 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
5268 struct intel_encoder
*encoder
;
5272 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
5273 if (type_mask
& encoder
->clone_mask
)
5274 index_mask
|= (1 << entry
);
5281 static void intel_setup_outputs(struct drm_device
*dev
)
5283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5284 struct intel_encoder
*encoder
;
5285 bool dpd_is_edp
= false;
5287 if (IS_MOBILE(dev
) && !IS_I830(dev
))
5288 intel_lvds_init(dev
);
5290 if (HAS_PCH_SPLIT(dev
)) {
5291 dpd_is_edp
= intel_dpd_is_edp(dev
);
5293 if (IS_MOBILE(dev
) && (I915_READ(DP_A
) & DP_DETECTED
))
5294 intel_dp_init(dev
, DP_A
);
5296 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
5297 intel_dp_init(dev
, PCH_DP_D
);
5300 intel_crt_init(dev
);
5302 if (HAS_PCH_SPLIT(dev
)) {
5305 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
5306 /* PCH SDVOB multiplex with HDMIB */
5307 found
= intel_sdvo_init(dev
, PCH_SDVOB
);
5309 intel_hdmi_init(dev
, HDMIB
);
5310 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
5311 intel_dp_init(dev
, PCH_DP_B
);
5314 if (I915_READ(HDMIC
) & PORT_DETECTED
)
5315 intel_hdmi_init(dev
, HDMIC
);
5317 if (I915_READ(HDMID
) & PORT_DETECTED
)
5318 intel_hdmi_init(dev
, HDMID
);
5320 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
5321 intel_dp_init(dev
, PCH_DP_C
);
5323 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
5324 intel_dp_init(dev
, PCH_DP_D
);
5326 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
5329 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
5330 DRM_DEBUG_KMS("probing SDVOB\n");
5331 found
= intel_sdvo_init(dev
, SDVOB
);
5332 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
5333 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5334 intel_hdmi_init(dev
, SDVOB
);
5337 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
5338 DRM_DEBUG_KMS("probing DP_B\n");
5339 intel_dp_init(dev
, DP_B
);
5343 /* Before G4X SDVOC doesn't have its own detect register */
5345 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
5346 DRM_DEBUG_KMS("probing SDVOC\n");
5347 found
= intel_sdvo_init(dev
, SDVOC
);
5350 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
5352 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
5353 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5354 intel_hdmi_init(dev
, SDVOC
);
5356 if (SUPPORTS_INTEGRATED_DP(dev
)) {
5357 DRM_DEBUG_KMS("probing DP_C\n");
5358 intel_dp_init(dev
, DP_C
);
5362 if (SUPPORTS_INTEGRATED_DP(dev
) &&
5363 (I915_READ(DP_D
) & DP_DETECTED
)) {
5364 DRM_DEBUG_KMS("probing DP_D\n");
5365 intel_dp_init(dev
, DP_D
);
5367 } else if (IS_GEN2(dev
))
5368 intel_dvo_init(dev
);
5370 if (SUPPORTS_TV(dev
))
5373 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
5374 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
5375 encoder
->base
.possible_clones
=
5376 intel_encoder_clones(dev
, encoder
->clone_mask
);
5380 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
5382 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
5384 drm_framebuffer_cleanup(fb
);
5385 drm_gem_object_unreference_unlocked(intel_fb
->obj
);
5390 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
5391 struct drm_file
*file_priv
,
5392 unsigned int *handle
)
5394 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
5395 struct drm_gem_object
*object
= intel_fb
->obj
;
5397 return drm_gem_handle_create(file_priv
, object
, handle
);
5400 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
5401 .destroy
= intel_user_framebuffer_destroy
,
5402 .create_handle
= intel_user_framebuffer_create_handle
,
5405 int intel_framebuffer_init(struct drm_device
*dev
,
5406 struct intel_framebuffer
*intel_fb
,
5407 struct drm_mode_fb_cmd
*mode_cmd
,
5408 struct drm_gem_object
*obj
)
5410 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
5413 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
5416 if (mode_cmd
->pitch
& 63)
5419 switch (mode_cmd
->bpp
) {
5429 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
5431 DRM_ERROR("framebuffer init failed %d\n", ret
);
5435 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
5436 intel_fb
->obj
= obj
;
5440 static struct drm_framebuffer
*
5441 intel_user_framebuffer_create(struct drm_device
*dev
,
5442 struct drm_file
*filp
,
5443 struct drm_mode_fb_cmd
*mode_cmd
)
5445 struct drm_gem_object
*obj
;
5446 struct intel_framebuffer
*intel_fb
;
5449 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
5451 return ERR_PTR(-ENOENT
);
5453 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
5455 return ERR_PTR(-ENOMEM
);
5457 ret
= intel_framebuffer_init(dev
, intel_fb
,
5460 drm_gem_object_unreference_unlocked(obj
);
5462 return ERR_PTR(ret
);
5465 return &intel_fb
->base
;
5468 static const struct drm_mode_config_funcs intel_mode_funcs
= {
5469 .fb_create
= intel_user_framebuffer_create
,
5470 .output_poll_changed
= intel_fb_output_poll_changed
,
5473 static struct drm_gem_object
*
5474 intel_alloc_context_page(struct drm_device
*dev
)
5476 struct drm_gem_object
*ctx
;
5479 ctx
= i915_gem_alloc_object(dev
, 4096);
5481 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5485 mutex_lock(&dev
->struct_mutex
);
5486 ret
= i915_gem_object_pin(ctx
, 4096);
5488 DRM_ERROR("failed to pin power context: %d\n", ret
);
5492 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
5494 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
5497 mutex_unlock(&dev
->struct_mutex
);
5502 i915_gem_object_unpin(ctx
);
5504 drm_gem_object_unreference(ctx
);
5505 mutex_unlock(&dev
->struct_mutex
);
5509 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
5511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5514 rgvswctl
= I915_READ16(MEMSWCTL
);
5515 if (rgvswctl
& MEMCTL_CMD_STS
) {
5516 DRM_DEBUG("gpu busy, RCS change rejected\n");
5517 return false; /* still busy with another command */
5520 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
5521 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
5522 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5523 POSTING_READ16(MEMSWCTL
);
5525 rgvswctl
|= MEMCTL_CMD_STS
;
5526 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5531 void ironlake_enable_drps(struct drm_device
*dev
)
5533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5534 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
5535 u8 fmax
, fmin
, fstart
, vstart
;
5537 /* Enable temp reporting */
5538 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
5539 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
5541 /* 100ms RC evaluation intervals */
5542 I915_WRITE(RCUPEI
, 100000);
5543 I915_WRITE(RCDNEI
, 100000);
5545 /* Set max/min thresholds to 90ms and 80ms respectively */
5546 I915_WRITE(RCBMAXAVG
, 90000);
5547 I915_WRITE(RCBMINAVG
, 80000);
5549 I915_WRITE(MEMIHYST
, 1);
5551 /* Set up min, max, and cur for interrupt handling */
5552 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
5553 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
5554 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
5555 MEMMODE_FSTART_SHIFT
;
5558 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
5561 dev_priv
->fmax
= fstart
; /* IPS callback will increase this */
5562 dev_priv
->fstart
= fstart
;
5564 dev_priv
->max_delay
= fmax
;
5565 dev_priv
->min_delay
= fmin
;
5566 dev_priv
->cur_delay
= fstart
;
5568 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax
, fmin
,
5571 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
5574 * Interrupts will be enabled in ironlake_irq_postinstall
5577 I915_WRITE(VIDSTART
, vstart
);
5578 POSTING_READ(VIDSTART
);
5580 rgvmodectl
|= MEMMODE_SWMODE_EN
;
5581 I915_WRITE(MEMMODECTL
, rgvmodectl
);
5583 if (wait_for((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
5584 DRM_ERROR("stuck trying to change perf mode\n");
5587 ironlake_set_drps(dev
, fstart
);
5589 dev_priv
->last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
5591 dev_priv
->last_time1
= jiffies_to_msecs(jiffies
);
5592 dev_priv
->last_count2
= I915_READ(0x112f4);
5593 getrawmonotonic(&dev_priv
->last_time2
);
5596 void ironlake_disable_drps(struct drm_device
*dev
)
5598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5599 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
5601 /* Ack interrupts, disable EFC interrupt */
5602 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
5603 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
5604 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
5605 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
5606 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
5608 /* Go back to the starting frequency */
5609 ironlake_set_drps(dev
, dev_priv
->fstart
);
5611 rgvswctl
|= MEMCTL_CMD_STS
;
5612 I915_WRITE(MEMSWCTL
, rgvswctl
);
5617 static unsigned long intel_pxfreq(u32 vidfreq
)
5620 int div
= (vidfreq
& 0x3f0000) >> 16;
5621 int post
= (vidfreq
& 0x3000) >> 12;
5622 int pre
= (vidfreq
& 0x7);
5627 freq
= ((div
* 133333) / ((1<<post
) * pre
));
5632 void intel_init_emon(struct drm_device
*dev
)
5634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5639 /* Disable to program */
5643 /* Program energy weights for various events */
5644 I915_WRITE(SDEW
, 0x15040d00);
5645 I915_WRITE(CSIEW0
, 0x007f0000);
5646 I915_WRITE(CSIEW1
, 0x1e220004);
5647 I915_WRITE(CSIEW2
, 0x04000004);
5649 for (i
= 0; i
< 5; i
++)
5650 I915_WRITE(PEW
+ (i
* 4), 0);
5651 for (i
= 0; i
< 3; i
++)
5652 I915_WRITE(DEW
+ (i
* 4), 0);
5654 /* Program P-state weights to account for frequency power adjustment */
5655 for (i
= 0; i
< 16; i
++) {
5656 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
5657 unsigned long freq
= intel_pxfreq(pxvidfreq
);
5658 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
5663 val
*= (freq
/ 1000);
5665 val
/= (127*127*900);
5667 DRM_ERROR("bad pxval: %ld\n", val
);
5670 /* Render standby states get 0 weight */
5674 for (i
= 0; i
< 4; i
++) {
5675 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
5676 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
5677 I915_WRITE(PXW
+ (i
* 4), val
);
5680 /* Adjust magic regs to magic values (more experimental results) */
5681 I915_WRITE(OGW0
, 0);
5682 I915_WRITE(OGW1
, 0);
5683 I915_WRITE(EG0
, 0x00007f00);
5684 I915_WRITE(EG1
, 0x0000000e);
5685 I915_WRITE(EG2
, 0x000e0000);
5686 I915_WRITE(EG3
, 0x68000300);
5687 I915_WRITE(EG4
, 0x42000000);
5688 I915_WRITE(EG5
, 0x00140031);
5692 for (i
= 0; i
< 8; i
++)
5693 I915_WRITE(PXWL
+ (i
* 4), 0);
5695 /* Enable PMON + select events */
5696 I915_WRITE(ECR
, 0x80000019);
5698 lcfuse
= I915_READ(LCFUSE02
);
5700 dev_priv
->corr
= (lcfuse
& LCFUSE_HIV_MASK
);
5703 void intel_init_clock_gating(struct drm_device
*dev
)
5705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5708 * Disable clock gating reported to work incorrectly according to the
5709 * specs, but enable as much else as we can.
5711 if (HAS_PCH_SPLIT(dev
)) {
5712 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
5714 if (IS_IRONLAKE(dev
)) {
5715 /* Required for FBC */
5716 dspclk_gate
|= DPFDUNIT_CLOCK_GATE_DISABLE
;
5717 /* Required for CxSR */
5718 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
5720 I915_WRITE(PCH_3DCGDIS0
,
5721 MARIUNIT_CLOCK_GATE_DISABLE
|
5722 SVSMUNIT_CLOCK_GATE_DISABLE
);
5725 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
5728 * According to the spec the following bits should be set in
5729 * order to enable memory self-refresh
5730 * The bit 22/21 of 0x42004
5731 * The bit 5 of 0x42020
5732 * The bit 15 of 0x45000
5734 if (IS_IRONLAKE(dev
)) {
5735 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5736 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5737 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5738 I915_WRITE(ILK_DSPCLK_GATE
,
5739 (I915_READ(ILK_DSPCLK_GATE
) |
5740 ILK_DPARB_CLK_GATE
));
5741 I915_WRITE(DISP_ARB_CTL
,
5742 (I915_READ(DISP_ARB_CTL
) |
5744 I915_WRITE(WM3_LP_ILK
, 0);
5745 I915_WRITE(WM2_LP_ILK
, 0);
5746 I915_WRITE(WM1_LP_ILK
, 0);
5749 * Based on the document from hardware guys the following bits
5750 * should be set unconditionally in order to enable FBC.
5751 * The bit 22 of 0x42000
5752 * The bit 22 of 0x42004
5753 * The bit 7,8,9 of 0x42020.
5755 if (IS_IRONLAKE_M(dev
)) {
5756 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5757 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5759 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5760 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5762 I915_WRITE(ILK_DSPCLK_GATE
,
5763 I915_READ(ILK_DSPCLK_GATE
) |
5769 } else if (IS_G4X(dev
)) {
5770 uint32_t dspclk_gate
;
5771 I915_WRITE(RENCLK_GATE_D1
, 0);
5772 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5773 GS_UNIT_CLOCK_GATE_DISABLE
|
5774 CL_UNIT_CLOCK_GATE_DISABLE
);
5775 I915_WRITE(RAMCLK_GATE_D
, 0);
5776 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5777 OVRUNIT_CLOCK_GATE_DISABLE
|
5778 OVCUNIT_CLOCK_GATE_DISABLE
;
5780 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5781 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5782 } else if (IS_CRESTLINE(dev
)) {
5783 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5784 I915_WRITE(RENCLK_GATE_D2
, 0);
5785 I915_WRITE(DSPCLK_GATE_D
, 0);
5786 I915_WRITE(RAMCLK_GATE_D
, 0);
5787 I915_WRITE16(DEUC
, 0);
5788 } else if (IS_BROADWATER(dev
)) {
5789 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5790 I965_RCC_CLOCK_GATE_DISABLE
|
5791 I965_RCPB_CLOCK_GATE_DISABLE
|
5792 I965_ISC_CLOCK_GATE_DISABLE
|
5793 I965_FBC_CLOCK_GATE_DISABLE
);
5794 I915_WRITE(RENCLK_GATE_D2
, 0);
5795 } else if (IS_GEN3(dev
)) {
5796 u32 dstate
= I915_READ(D_STATE
);
5798 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5799 DSTATE_DOT_CLOCK_GATING
;
5800 I915_WRITE(D_STATE
, dstate
);
5801 } else if (IS_I85X(dev
) || IS_I865G(dev
)) {
5802 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5803 } else if (IS_I830(dev
)) {
5804 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5808 * GPU can automatically power down the render unit if given a page
5811 if (IS_IRONLAKE_M(dev
)) {
5812 if (dev_priv
->renderctx
== NULL
)
5813 dev_priv
->renderctx
= intel_alloc_context_page(dev
);
5814 if (dev_priv
->renderctx
) {
5815 struct drm_i915_gem_object
*obj_priv
;
5816 obj_priv
= to_intel_bo(dev_priv
->renderctx
);
5819 OUT_RING(MI_SET_CONTEXT
);
5820 OUT_RING(obj_priv
->gtt_offset
|
5822 MI_SAVE_EXT_STATE_EN
|
5823 MI_RESTORE_EXT_STATE_EN
|
5824 MI_RESTORE_INHIBIT
);
5830 DRM_DEBUG_KMS("Failed to allocate render context."
5834 if (I915_HAS_RC6(dev
) && drm_core_check_feature(dev
, DRIVER_MODESET
)) {
5835 struct drm_i915_gem_object
*obj_priv
= NULL
;
5837 if (dev_priv
->pwrctx
) {
5838 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
5840 struct drm_gem_object
*pwrctx
;
5842 pwrctx
= intel_alloc_context_page(dev
);
5844 dev_priv
->pwrctx
= pwrctx
;
5845 obj_priv
= to_intel_bo(pwrctx
);
5850 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
| PWRCTX_EN
);
5851 I915_WRITE(MCHBAR_RENDER_STANDBY
,
5852 I915_READ(MCHBAR_RENDER_STANDBY
) & ~RCX_SW_EXIT
);
5857 /* Set up chip specific display functions */
5858 static void intel_init_display(struct drm_device
*dev
)
5860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5862 /* We always want a DPMS function */
5863 if (HAS_PCH_SPLIT(dev
))
5864 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
5866 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
5868 if (I915_HAS_FBC(dev
)) {
5869 if (IS_IRONLAKE_M(dev
)) {
5870 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
5871 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
5872 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
5873 } else if (IS_GM45(dev
)) {
5874 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
5875 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
5876 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
5877 } else if (IS_CRESTLINE(dev
)) {
5878 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
5879 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
5880 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
5882 /* 855GM needs testing */
5885 /* Returns the core display clock speed */
5886 if (IS_I945G(dev
) || (IS_G33(dev
) && ! IS_PINEVIEW_M(dev
)))
5887 dev_priv
->display
.get_display_clock_speed
=
5888 i945_get_display_clock_speed
;
5889 else if (IS_I915G(dev
))
5890 dev_priv
->display
.get_display_clock_speed
=
5891 i915_get_display_clock_speed
;
5892 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
5893 dev_priv
->display
.get_display_clock_speed
=
5894 i9xx_misc_get_display_clock_speed
;
5895 else if (IS_I915GM(dev
))
5896 dev_priv
->display
.get_display_clock_speed
=
5897 i915gm_get_display_clock_speed
;
5898 else if (IS_I865G(dev
))
5899 dev_priv
->display
.get_display_clock_speed
=
5900 i865_get_display_clock_speed
;
5901 else if (IS_I85X(dev
))
5902 dev_priv
->display
.get_display_clock_speed
=
5903 i855_get_display_clock_speed
;
5905 dev_priv
->display
.get_display_clock_speed
=
5906 i830_get_display_clock_speed
;
5908 /* For FIFO watermark updates */
5909 if (HAS_PCH_SPLIT(dev
)) {
5910 if (IS_IRONLAKE(dev
)) {
5911 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
5912 dev_priv
->display
.update_wm
= ironlake_update_wm
;
5914 DRM_DEBUG_KMS("Failed to get proper latency. "
5916 dev_priv
->display
.update_wm
= NULL
;
5919 dev_priv
->display
.update_wm
= NULL
;
5920 } else if (IS_PINEVIEW(dev
)) {
5921 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
5924 dev_priv
->mem_freq
)) {
5925 DRM_INFO("failed to find known CxSR latency "
5926 "(found ddr%s fsb freq %d, mem freq %d), "
5928 (dev_priv
->is_ddr3
== 1) ? "3": "2",
5929 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
5930 /* Disable CxSR and never update its watermark again */
5931 pineview_disable_cxsr(dev
);
5932 dev_priv
->display
.update_wm
= NULL
;
5934 dev_priv
->display
.update_wm
= pineview_update_wm
;
5935 } else if (IS_G4X(dev
))
5936 dev_priv
->display
.update_wm
= g4x_update_wm
;
5937 else if (IS_GEN4(dev
))
5938 dev_priv
->display
.update_wm
= i965_update_wm
;
5939 else if (IS_GEN3(dev
)) {
5940 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5941 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
5942 } else if (IS_I85X(dev
)) {
5943 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5944 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
5946 dev_priv
->display
.update_wm
= i830_update_wm
;
5948 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
5950 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
5955 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5956 * resume, or other times. This quirk makes sure that's the case for
5959 static void quirk_pipea_force (struct drm_device
*dev
)
5961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5963 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
5964 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5967 struct intel_quirk
{
5969 int subsystem_vendor
;
5970 int subsystem_device
;
5971 void (*hook
)(struct drm_device
*dev
);
5974 struct intel_quirk intel_quirks
[] = {
5975 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5976 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force
},
5977 /* HP Mini needs pipe A force quirk (LP: #322104) */
5978 { 0x27ae,0x103c, 0x361a, quirk_pipea_force
},
5980 /* Thinkpad R31 needs pipe A force quirk */
5981 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
5982 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5983 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
5985 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5986 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
5987 /* ThinkPad X40 needs pipe A force quirk */
5989 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5990 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
5992 /* 855 & before need to leave pipe A & dpll A up */
5993 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
5994 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
5997 static void intel_init_quirks(struct drm_device
*dev
)
5999 struct pci_dev
*d
= dev
->pdev
;
6002 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
6003 struct intel_quirk
*q
= &intel_quirks
[i
];
6005 if (d
->device
== q
->device
&&
6006 (d
->subsystem_vendor
== q
->subsystem_vendor
||
6007 q
->subsystem_vendor
== PCI_ANY_ID
) &&
6008 (d
->subsystem_device
== q
->subsystem_device
||
6009 q
->subsystem_device
== PCI_ANY_ID
))
6014 /* Disable the VGA plane that we never use */
6015 static void i915_disable_vga(struct drm_device
*dev
)
6017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6021 if (HAS_PCH_SPLIT(dev
))
6022 vga_reg
= CPU_VGACNTRL
;
6026 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6027 outb(1, VGA_SR_INDEX
);
6028 sr1
= inb(VGA_SR_DATA
);
6029 outb(sr1
| 1<<5, VGA_SR_DATA
);
6030 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6033 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
6034 POSTING_READ(vga_reg
);
6037 void intel_modeset_init(struct drm_device
*dev
)
6039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6042 drm_mode_config_init(dev
);
6044 dev
->mode_config
.min_width
= 0;
6045 dev
->mode_config
.min_height
= 0;
6047 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
6049 intel_init_quirks(dev
);
6051 intel_init_display(dev
);
6054 dev
->mode_config
.max_width
= 2048;
6055 dev
->mode_config
.max_height
= 2048;
6056 } else if (IS_GEN3(dev
)) {
6057 dev
->mode_config
.max_width
= 4096;
6058 dev
->mode_config
.max_height
= 4096;
6060 dev
->mode_config
.max_width
= 8192;
6061 dev
->mode_config
.max_height
= 8192;
6064 /* set memory base */
6066 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
6068 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
6070 if (IS_MOBILE(dev
) || !IS_GEN2(dev
))
6071 dev_priv
->num_pipe
= 2;
6073 dev_priv
->num_pipe
= 1;
6074 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6075 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
6077 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
6078 intel_crtc_init(dev
, i
);
6081 intel_setup_outputs(dev
);
6083 intel_init_clock_gating(dev
);
6085 /* Just disable it once at startup */
6086 i915_disable_vga(dev
);
6088 if (IS_IRONLAKE_M(dev
)) {
6089 ironlake_enable_drps(dev
);
6090 intel_init_emon(dev
);
6093 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
6094 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
6095 (unsigned long)dev
);
6097 intel_setup_overlay(dev
);
6100 void intel_modeset_cleanup(struct drm_device
*dev
)
6102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6103 struct drm_crtc
*crtc
;
6104 struct intel_crtc
*intel_crtc
;
6106 mutex_lock(&dev
->struct_mutex
);
6108 drm_kms_helper_poll_fini(dev
);
6109 intel_fbdev_fini(dev
);
6111 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6112 /* Skip inactive CRTCs */
6116 intel_crtc
= to_intel_crtc(crtc
);
6117 intel_increase_pllclock(crtc
);
6120 if (dev_priv
->display
.disable_fbc
)
6121 dev_priv
->display
.disable_fbc(dev
);
6123 if (dev_priv
->renderctx
) {
6124 struct drm_i915_gem_object
*obj_priv
;
6126 obj_priv
= to_intel_bo(dev_priv
->renderctx
);
6127 I915_WRITE(CCID
, obj_priv
->gtt_offset
&~ CCID_EN
);
6129 i915_gem_object_unpin(dev_priv
->renderctx
);
6130 drm_gem_object_unreference(dev_priv
->renderctx
);
6133 if (dev_priv
->pwrctx
) {
6134 struct drm_i915_gem_object
*obj_priv
;
6136 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
6137 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
&~ PWRCTX_EN
);
6139 i915_gem_object_unpin(dev_priv
->pwrctx
);
6140 drm_gem_object_unreference(dev_priv
->pwrctx
);
6143 if (IS_IRONLAKE_M(dev
))
6144 ironlake_disable_drps(dev
);
6146 mutex_unlock(&dev
->struct_mutex
);
6148 /* Disable the irq before mode object teardown, for the irq might
6149 * enqueue unpin/hotplug work. */
6150 drm_irq_uninstall(dev
);
6151 cancel_work_sync(&dev_priv
->hotplug_work
);
6153 /* Shut off idle work before the crtcs get freed. */
6154 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6155 intel_crtc
= to_intel_crtc(crtc
);
6156 del_timer_sync(&intel_crtc
->idle_timer
);
6158 del_timer_sync(&dev_priv
->idle_timer
);
6159 cancel_work_sync(&dev_priv
->idle_work
);
6161 drm_mode_config_cleanup(dev
);
6165 * Return which encoder is currently attached for connector.
6167 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
6169 return &intel_attached_encoder(connector
)->base
;
6172 void intel_connector_attach_encoder(struct intel_connector
*connector
,
6173 struct intel_encoder
*encoder
)
6175 connector
->encoder
= encoder
;
6176 drm_mode_connector_attach_encoder(&connector
->base
,
6181 * set vga decode state - true == enable VGA decode
6183 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
6185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6188 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
6190 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
6192 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
6193 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);