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drm/i915: Drop the 64k linear scanout alignment on gen2/3
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_set_mode(struct drm_atomic_state *state);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void chv_prepare_pll(struct intel_crtc *crtc,
105 const struct intel_crtc_state *pipe_config);
106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
112 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
113 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
114
115 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
116 {
117 if (!connector->mst_port)
118 return connector->encoder;
119 else
120 return &connector->mst_port->mst_encoders[pipe]->base;
121 }
122
123 typedef struct {
124 int min, max;
125 } intel_range_t;
126
127 typedef struct {
128 int dot_limit;
129 int p2_slow, p2_fast;
130 } intel_p2_t;
131
132 typedef struct intel_limit intel_limit_t;
133 struct intel_limit {
134 intel_range_t dot, vco, n, m, m1, m2, p, p1;
135 intel_p2_t p2;
136 };
137
138 int
139 intel_pch_rawclk(struct drm_device *dev)
140 {
141 struct drm_i915_private *dev_priv = dev->dev_private;
142
143 WARN_ON(!HAS_PCH_SPLIT(dev));
144
145 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
146 }
147
148 static inline u32 /* units of 100MHz */
149 intel_fdi_link_freq(struct drm_device *dev)
150 {
151 if (IS_GEN5(dev)) {
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
154 } else
155 return 27;
156 }
157
158 static const intel_limit_t intel_limits_i8xx_dac = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 2 },
169 };
170
171 static const intel_limit_t intel_limits_i8xx_dvo = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 2, .max = 33 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 4, .p2_fast = 4 },
182 };
183
184 static const intel_limit_t intel_limits_i8xx_lvds = {
185 .dot = { .min = 25000, .max = 350000 },
186 .vco = { .min = 908000, .max = 1512000 },
187 .n = { .min = 2, .max = 16 },
188 .m = { .min = 96, .max = 140 },
189 .m1 = { .min = 18, .max = 26 },
190 .m2 = { .min = 6, .max = 16 },
191 .p = { .min = 4, .max = 128 },
192 .p1 = { .min = 1, .max = 6 },
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 14, .p2_fast = 7 },
195 };
196
197 static const intel_limit_t intel_limits_i9xx_sdvo = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 200000,
207 .p2_slow = 10, .p2_fast = 5 },
208 };
209
210 static const intel_limit_t intel_limits_i9xx_lvds = {
211 .dot = { .min = 20000, .max = 400000 },
212 .vco = { .min = 1400000, .max = 2800000 },
213 .n = { .min = 1, .max = 6 },
214 .m = { .min = 70, .max = 120 },
215 .m1 = { .min = 8, .max = 18 },
216 .m2 = { .min = 3, .max = 7 },
217 .p = { .min = 7, .max = 98 },
218 .p1 = { .min = 1, .max = 8 },
219 .p2 = { .dot_limit = 112000,
220 .p2_slow = 14, .p2_fast = 7 },
221 };
222
223
224 static const intel_limit_t intel_limits_g4x_sdvo = {
225 .dot = { .min = 25000, .max = 270000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 4 },
228 .m = { .min = 104, .max = 138 },
229 .m1 = { .min = 17, .max = 23 },
230 .m2 = { .min = 5, .max = 11 },
231 .p = { .min = 10, .max = 30 },
232 .p1 = { .min = 1, .max = 3},
233 .p2 = { .dot_limit = 270000,
234 .p2_slow = 10,
235 .p2_fast = 10
236 },
237 };
238
239 static const intel_limit_t intel_limits_g4x_hdmi = {
240 .dot = { .min = 22000, .max = 400000 },
241 .vco = { .min = 1750000, .max = 3500000},
242 .n = { .min = 1, .max = 4 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 16, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8},
248 .p2 = { .dot_limit = 165000,
249 .p2_slow = 10, .p2_fast = 5 },
250 };
251
252 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
253 .dot = { .min = 20000, .max = 115000 },
254 .vco = { .min = 1750000, .max = 3500000 },
255 .n = { .min = 1, .max = 3 },
256 .m = { .min = 104, .max = 138 },
257 .m1 = { .min = 17, .max = 23 },
258 .m2 = { .min = 5, .max = 11 },
259 .p = { .min = 28, .max = 112 },
260 .p1 = { .min = 2, .max = 8 },
261 .p2 = { .dot_limit = 0,
262 .p2_slow = 14, .p2_fast = 14
263 },
264 };
265
266 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
267 .dot = { .min = 80000, .max = 224000 },
268 .vco = { .min = 1750000, .max = 3500000 },
269 .n = { .min = 1, .max = 3 },
270 .m = { .min = 104, .max = 138 },
271 .m1 = { .min = 17, .max = 23 },
272 .m2 = { .min = 5, .max = 11 },
273 .p = { .min = 14, .max = 42 },
274 .p1 = { .min = 2, .max = 6 },
275 .p2 = { .dot_limit = 0,
276 .p2_slow = 7, .p2_fast = 7
277 },
278 };
279
280 static const intel_limit_t intel_limits_pineview_sdvo = {
281 .dot = { .min = 20000, .max = 400000},
282 .vco = { .min = 1700000, .max = 3500000 },
283 /* Pineview's Ncounter is a ring counter */
284 .n = { .min = 3, .max = 6 },
285 .m = { .min = 2, .max = 256 },
286 /* Pineview only has one combined m divider, which we treat as m2. */
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 200000,
292 .p2_slow = 10, .p2_fast = 5 },
293 };
294
295 static const intel_limit_t intel_limits_pineview_lvds = {
296 .dot = { .min = 20000, .max = 400000 },
297 .vco = { .min = 1700000, .max = 3500000 },
298 .n = { .min = 3, .max = 6 },
299 .m = { .min = 2, .max = 256 },
300 .m1 = { .min = 0, .max = 0 },
301 .m2 = { .min = 0, .max = 254 },
302 .p = { .min = 7, .max = 112 },
303 .p1 = { .min = 1, .max = 8 },
304 .p2 = { .dot_limit = 112000,
305 .p2_slow = 14, .p2_fast = 14 },
306 };
307
308 /* Ironlake / Sandybridge
309 *
310 * We calculate clock using (register_value + 2) for N/M1/M2, so here
311 * the range value for them is (actual_value - 2).
312 */
313 static const intel_limit_t intel_limits_ironlake_dac = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 5 },
317 .m = { .min = 79, .max = 127 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 5, .max = 80 },
321 .p1 = { .min = 1, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 10, .p2_fast = 5 },
324 };
325
326 static const intel_limit_t intel_limits_ironlake_single_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 118 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 28, .max = 112 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 14, .p2_fast = 14 },
337 };
338
339 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 127 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 56 },
347 .p1 = { .min = 2, .max = 8 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 };
351
352 /* LVDS 100mhz refclk limits. */
353 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 28, .max = 112 },
361 .p1 = { .min = 2, .max = 8 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 14, .p2_fast = 14 },
364 };
365
366 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
367 .dot = { .min = 25000, .max = 350000 },
368 .vco = { .min = 1760000, .max = 3510000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 79, .max = 126 },
371 .m1 = { .min = 12, .max = 22 },
372 .m2 = { .min = 5, .max = 9 },
373 .p = { .min = 14, .max = 42 },
374 .p1 = { .min = 2, .max = 6 },
375 .p2 = { .dot_limit = 225000,
376 .p2_slow = 7, .p2_fast = 7 },
377 };
378
379 static const intel_limit_t intel_limits_vlv = {
380 /*
381 * These are the data rate limits (measured in fast clocks)
382 * since those are the strictest limits we have. The fast
383 * clock and actual rate limits are more relaxed, so checking
384 * them would make no difference.
385 */
386 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
387 .vco = { .min = 4000000, .max = 6000000 },
388 .n = { .min = 1, .max = 7 },
389 .m1 = { .min = 2, .max = 3 },
390 .m2 = { .min = 11, .max = 156 },
391 .p1 = { .min = 2, .max = 3 },
392 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
393 };
394
395 static const intel_limit_t intel_limits_chv = {
396 /*
397 * These are the data rate limits (measured in fast clocks)
398 * since those are the strictest limits we have. The fast
399 * clock and actual rate limits are more relaxed, so checking
400 * them would make no difference.
401 */
402 .dot = { .min = 25000 * 5, .max = 540000 * 5},
403 .vco = { .min = 4800000, .max = 6480000 },
404 .n = { .min = 1, .max = 1 },
405 .m1 = { .min = 2, .max = 2 },
406 .m2 = { .min = 24 << 22, .max = 175 << 22 },
407 .p1 = { .min = 2, .max = 4 },
408 .p2 = { .p2_slow = 1, .p2_fast = 14 },
409 };
410
411 static const intel_limit_t intel_limits_bxt = {
412 /* FIXME: find real dot limits */
413 .dot = { .min = 0, .max = INT_MAX },
414 .vco = { .min = 4800000, .max = 6480000 },
415 .n = { .min = 1, .max = 1 },
416 .m1 = { .min = 2, .max = 2 },
417 /* FIXME: find real m2 limits */
418 .m2 = { .min = 2 << 22, .max = 255 << 22 },
419 .p1 = { .min = 2, .max = 4 },
420 .p2 = { .p2_slow = 1, .p2_fast = 20 },
421 };
422
423 static void vlv_clock(int refclk, intel_clock_t *clock)
424 {
425 clock->m = clock->m1 * clock->m2;
426 clock->p = clock->p1 * clock->p2;
427 if (WARN_ON(clock->n == 0 || clock->p == 0))
428 return;
429 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
430 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
431 }
432
433 static bool
434 needs_modeset(struct drm_crtc_state *state)
435 {
436 return state->mode_changed || state->active_changed;
437 }
438
439 /**
440 * Returns whether any output on the specified pipe is of the specified type
441 */
442 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
443 {
444 struct drm_device *dev = crtc->base.dev;
445 struct intel_encoder *encoder;
446
447 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
448 if (encoder->type == type)
449 return true;
450
451 return false;
452 }
453
454 /**
455 * Returns whether any output on the specified pipe will have the specified
456 * type after a staged modeset is complete, i.e., the same as
457 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
458 * encoder->crtc.
459 */
460 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
461 int type)
462 {
463 struct drm_atomic_state *state = crtc_state->base.state;
464 struct drm_connector *connector;
465 struct drm_connector_state *connector_state;
466 struct intel_encoder *encoder;
467 int i, num_connectors = 0;
468
469 for_each_connector_in_state(state, connector, connector_state, i) {
470 if (connector_state->crtc != crtc_state->base.crtc)
471 continue;
472
473 num_connectors++;
474
475 encoder = to_intel_encoder(connector_state->best_encoder);
476 if (encoder->type == type)
477 return true;
478 }
479
480 WARN_ON(num_connectors == 0);
481
482 return false;
483 }
484
485 static const intel_limit_t *
486 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
487 {
488 struct drm_device *dev = crtc_state->base.crtc->dev;
489 const intel_limit_t *limit;
490
491 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
492 if (intel_is_dual_link_lvds(dev)) {
493 if (refclk == 100000)
494 limit = &intel_limits_ironlake_dual_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_dual_lvds;
497 } else {
498 if (refclk == 100000)
499 limit = &intel_limits_ironlake_single_lvds_100m;
500 else
501 limit = &intel_limits_ironlake_single_lvds;
502 }
503 } else
504 limit = &intel_limits_ironlake_dac;
505
506 return limit;
507 }
508
509 static const intel_limit_t *
510 intel_g4x_limit(struct intel_crtc_state *crtc_state)
511 {
512 struct drm_device *dev = crtc_state->base.crtc->dev;
513 const intel_limit_t *limit;
514
515 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
516 if (intel_is_dual_link_lvds(dev))
517 limit = &intel_limits_g4x_dual_channel_lvds;
518 else
519 limit = &intel_limits_g4x_single_channel_lvds;
520 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
521 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
522 limit = &intel_limits_g4x_hdmi;
523 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
524 limit = &intel_limits_g4x_sdvo;
525 } else /* The option is for other outputs */
526 limit = &intel_limits_i9xx_sdvo;
527
528 return limit;
529 }
530
531 static const intel_limit_t *
532 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
533 {
534 struct drm_device *dev = crtc_state->base.crtc->dev;
535 const intel_limit_t *limit;
536
537 if (IS_BROXTON(dev))
538 limit = &intel_limits_bxt;
539 else if (HAS_PCH_SPLIT(dev))
540 limit = intel_ironlake_limit(crtc_state, refclk);
541 else if (IS_G4X(dev)) {
542 limit = intel_g4x_limit(crtc_state);
543 } else if (IS_PINEVIEW(dev)) {
544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
545 limit = &intel_limits_pineview_lvds;
546 else
547 limit = &intel_limits_pineview_sdvo;
548 } else if (IS_CHERRYVIEW(dev)) {
549 limit = &intel_limits_chv;
550 } else if (IS_VALLEYVIEW(dev)) {
551 limit = &intel_limits_vlv;
552 } else if (!IS_GEN2(dev)) {
553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
554 limit = &intel_limits_i9xx_lvds;
555 else
556 limit = &intel_limits_i9xx_sdvo;
557 } else {
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
559 limit = &intel_limits_i8xx_lvds;
560 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
561 limit = &intel_limits_i8xx_dvo;
562 else
563 limit = &intel_limits_i8xx_dac;
564 }
565 return limit;
566 }
567
568 /* m1 is reserved as 0 in Pineview, n is a ring counter */
569 static void pineview_clock(int refclk, intel_clock_t *clock)
570 {
571 clock->m = clock->m2 + 2;
572 clock->p = clock->p1 * clock->p2;
573 if (WARN_ON(clock->n == 0 || clock->p == 0))
574 return;
575 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
576 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
577 }
578
579 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
580 {
581 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
582 }
583
584 static void i9xx_clock(int refclk, intel_clock_t *clock)
585 {
586 clock->m = i9xx_dpll_compute_m(clock);
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
589 return;
590 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
591 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
592 }
593
594 static void chv_clock(int refclk, intel_clock_t *clock)
595 {
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
599 return;
600 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
601 clock->n << 22);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
603 }
604
605 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
606 /**
607 * Returns whether the given set of divisors are valid for a given refclk with
608 * the given connectors.
609 */
610
611 static bool intel_PLL_is_valid(struct drm_device *dev,
612 const intel_limit_t *limit,
613 const intel_clock_t *clock)
614 {
615 if (clock->n < limit->n.min || limit->n.max < clock->n)
616 INTELPllInvalid("n out of range\n");
617 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
618 INTELPllInvalid("p1 out of range\n");
619 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
620 INTELPllInvalid("m2 out of range\n");
621 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
622 INTELPllInvalid("m1 out of range\n");
623
624 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
625 if (clock->m1 <= clock->m2)
626 INTELPllInvalid("m1 <= m2\n");
627
628 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
629 if (clock->p < limit->p.min || limit->p.max < clock->p)
630 INTELPllInvalid("p out of range\n");
631 if (clock->m < limit->m.min || limit->m.max < clock->m)
632 INTELPllInvalid("m out of range\n");
633 }
634
635 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
636 INTELPllInvalid("vco out of range\n");
637 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
638 * connector, etc., rather than just a single range.
639 */
640 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
641 INTELPllInvalid("dot out of range\n");
642
643 return true;
644 }
645
646 static bool
647 i9xx_find_best_dpll(const intel_limit_t *limit,
648 struct intel_crtc_state *crtc_state,
649 int target, int refclk, intel_clock_t *match_clock,
650 intel_clock_t *best_clock)
651 {
652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
653 struct drm_device *dev = crtc->base.dev;
654 intel_clock_t clock;
655 int err = target;
656
657 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
658 /*
659 * For LVDS just rely on its current settings for dual-channel.
660 * We haven't figured out how to reliably set up different
661 * single/dual channel state, if we even can.
662 */
663 if (intel_is_dual_link_lvds(dev))
664 clock.p2 = limit->p2.p2_fast;
665 else
666 clock.p2 = limit->p2.p2_slow;
667 } else {
668 if (target < limit->p2.dot_limit)
669 clock.p2 = limit->p2.p2_slow;
670 else
671 clock.p2 = limit->p2.p2_fast;
672 }
673
674 memset(best_clock, 0, sizeof(*best_clock));
675
676 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
677 clock.m1++) {
678 for (clock.m2 = limit->m2.min;
679 clock.m2 <= limit->m2.max; clock.m2++) {
680 if (clock.m2 >= clock.m1)
681 break;
682 for (clock.n = limit->n.min;
683 clock.n <= limit->n.max; clock.n++) {
684 for (clock.p1 = limit->p1.min;
685 clock.p1 <= limit->p1.max; clock.p1++) {
686 int this_err;
687
688 i9xx_clock(refclk, &clock);
689 if (!intel_PLL_is_valid(dev, limit,
690 &clock))
691 continue;
692 if (match_clock &&
693 clock.p != match_clock->p)
694 continue;
695
696 this_err = abs(clock.dot - target);
697 if (this_err < err) {
698 *best_clock = clock;
699 err = this_err;
700 }
701 }
702 }
703 }
704 }
705
706 return (err != target);
707 }
708
709 static bool
710 pnv_find_best_dpll(const intel_limit_t *limit,
711 struct intel_crtc_state *crtc_state,
712 int target, int refclk, intel_clock_t *match_clock,
713 intel_clock_t *best_clock)
714 {
715 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
716 struct drm_device *dev = crtc->base.dev;
717 intel_clock_t clock;
718 int err = target;
719
720 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
721 /*
722 * For LVDS just rely on its current settings for dual-channel.
723 * We haven't figured out how to reliably set up different
724 * single/dual channel state, if we even can.
725 */
726 if (intel_is_dual_link_lvds(dev))
727 clock.p2 = limit->p2.p2_fast;
728 else
729 clock.p2 = limit->p2.p2_slow;
730 } else {
731 if (target < limit->p2.dot_limit)
732 clock.p2 = limit->p2.p2_slow;
733 else
734 clock.p2 = limit->p2.p2_fast;
735 }
736
737 memset(best_clock, 0, sizeof(*best_clock));
738
739 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
740 clock.m1++) {
741 for (clock.m2 = limit->m2.min;
742 clock.m2 <= limit->m2.max; clock.m2++) {
743 for (clock.n = limit->n.min;
744 clock.n <= limit->n.max; clock.n++) {
745 for (clock.p1 = limit->p1.min;
746 clock.p1 <= limit->p1.max; clock.p1++) {
747 int this_err;
748
749 pineview_clock(refclk, &clock);
750 if (!intel_PLL_is_valid(dev, limit,
751 &clock))
752 continue;
753 if (match_clock &&
754 clock.p != match_clock->p)
755 continue;
756
757 this_err = abs(clock.dot - target);
758 if (this_err < err) {
759 *best_clock = clock;
760 err = this_err;
761 }
762 }
763 }
764 }
765 }
766
767 return (err != target);
768 }
769
770 static bool
771 g4x_find_best_dpll(const intel_limit_t *limit,
772 struct intel_crtc_state *crtc_state,
773 int target, int refclk, intel_clock_t *match_clock,
774 intel_clock_t *best_clock)
775 {
776 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
777 struct drm_device *dev = crtc->base.dev;
778 intel_clock_t clock;
779 int max_n;
780 bool found;
781 /* approximately equals target * 0.00585 */
782 int err_most = (target >> 8) + (target >> 9);
783 found = false;
784
785 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
786 if (intel_is_dual_link_lvds(dev))
787 clock.p2 = limit->p2.p2_fast;
788 else
789 clock.p2 = limit->p2.p2_slow;
790 } else {
791 if (target < limit->p2.dot_limit)
792 clock.p2 = limit->p2.p2_slow;
793 else
794 clock.p2 = limit->p2.p2_fast;
795 }
796
797 memset(best_clock, 0, sizeof(*best_clock));
798 max_n = limit->n.max;
799 /* based on hardware requirement, prefer smaller n to precision */
800 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
801 /* based on hardware requirement, prefere larger m1,m2 */
802 for (clock.m1 = limit->m1.max;
803 clock.m1 >= limit->m1.min; clock.m1--) {
804 for (clock.m2 = limit->m2.max;
805 clock.m2 >= limit->m2.min; clock.m2--) {
806 for (clock.p1 = limit->p1.max;
807 clock.p1 >= limit->p1.min; clock.p1--) {
808 int this_err;
809
810 i9xx_clock(refclk, &clock);
811 if (!intel_PLL_is_valid(dev, limit,
812 &clock))
813 continue;
814
815 this_err = abs(clock.dot - target);
816 if (this_err < err_most) {
817 *best_clock = clock;
818 err_most = this_err;
819 max_n = clock.n;
820 found = true;
821 }
822 }
823 }
824 }
825 }
826 return found;
827 }
828
829 /*
830 * Check if the calculated PLL configuration is more optimal compared to the
831 * best configuration and error found so far. Return the calculated error.
832 */
833 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
834 const intel_clock_t *calculated_clock,
835 const intel_clock_t *best_clock,
836 unsigned int best_error_ppm,
837 unsigned int *error_ppm)
838 {
839 /*
840 * For CHV ignore the error and consider only the P value.
841 * Prefer a bigger P value based on HW requirements.
842 */
843 if (IS_CHERRYVIEW(dev)) {
844 *error_ppm = 0;
845
846 return calculated_clock->p > best_clock->p;
847 }
848
849 if (WARN_ON_ONCE(!target_freq))
850 return false;
851
852 *error_ppm = div_u64(1000000ULL *
853 abs(target_freq - calculated_clock->dot),
854 target_freq);
855 /*
856 * Prefer a better P value over a better (smaller) error if the error
857 * is small. Ensure this preference for future configurations too by
858 * setting the error to 0.
859 */
860 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
861 *error_ppm = 0;
862
863 return true;
864 }
865
866 return *error_ppm + 10 < best_error_ppm;
867 }
868
869 static bool
870 vlv_find_best_dpll(const intel_limit_t *limit,
871 struct intel_crtc_state *crtc_state,
872 int target, int refclk, intel_clock_t *match_clock,
873 intel_clock_t *best_clock)
874 {
875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
876 struct drm_device *dev = crtc->base.dev;
877 intel_clock_t clock;
878 unsigned int bestppm = 1000000;
879 /* min update 19.2 MHz */
880 int max_n = min(limit->n.max, refclk / 19200);
881 bool found = false;
882
883 target *= 5; /* fast clock */
884
885 memset(best_clock, 0, sizeof(*best_clock));
886
887 /* based on hardware requirement, prefer smaller n to precision */
888 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
889 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
890 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
891 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
892 clock.p = clock.p1 * clock.p2;
893 /* based on hardware requirement, prefer bigger m1,m2 values */
894 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
895 unsigned int ppm;
896
897 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
898 refclk * clock.m1);
899
900 vlv_clock(refclk, &clock);
901
902 if (!intel_PLL_is_valid(dev, limit,
903 &clock))
904 continue;
905
906 if (!vlv_PLL_is_optimal(dev, target,
907 &clock,
908 best_clock,
909 bestppm, &ppm))
910 continue;
911
912 *best_clock = clock;
913 bestppm = ppm;
914 found = true;
915 }
916 }
917 }
918 }
919
920 return found;
921 }
922
923 static bool
924 chv_find_best_dpll(const intel_limit_t *limit,
925 struct intel_crtc_state *crtc_state,
926 int target, int refclk, intel_clock_t *match_clock,
927 intel_clock_t *best_clock)
928 {
929 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
930 struct drm_device *dev = crtc->base.dev;
931 unsigned int best_error_ppm;
932 intel_clock_t clock;
933 uint64_t m2;
934 int found = false;
935
936 memset(best_clock, 0, sizeof(*best_clock));
937 best_error_ppm = 1000000;
938
939 /*
940 * Based on hardware doc, the n always set to 1, and m1 always
941 * set to 2. If requires to support 200Mhz refclk, we need to
942 * revisit this because n may not 1 anymore.
943 */
944 clock.n = 1, clock.m1 = 2;
945 target *= 5; /* fast clock */
946
947 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
948 for (clock.p2 = limit->p2.p2_fast;
949 clock.p2 >= limit->p2.p2_slow;
950 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
951 unsigned int error_ppm;
952
953 clock.p = clock.p1 * clock.p2;
954
955 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
956 clock.n) << 22, refclk * clock.m1);
957
958 if (m2 > INT_MAX/clock.m1)
959 continue;
960
961 clock.m2 = m2;
962
963 chv_clock(refclk, &clock);
964
965 if (!intel_PLL_is_valid(dev, limit, &clock))
966 continue;
967
968 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
969 best_error_ppm, &error_ppm))
970 continue;
971
972 *best_clock = clock;
973 best_error_ppm = error_ppm;
974 found = true;
975 }
976 }
977
978 return found;
979 }
980
981 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
982 intel_clock_t *best_clock)
983 {
984 int refclk = i9xx_get_refclk(crtc_state, 0);
985
986 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
987 target_clock, refclk, NULL, best_clock);
988 }
989
990 bool intel_crtc_active(struct drm_crtc *crtc)
991 {
992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
993
994 /* Be paranoid as we can arrive here with only partial
995 * state retrieved from the hardware during setup.
996 *
997 * We can ditch the adjusted_mode.crtc_clock check as soon
998 * as Haswell has gained clock readout/fastboot support.
999 *
1000 * We can ditch the crtc->primary->fb check as soon as we can
1001 * properly reconstruct framebuffers.
1002 *
1003 * FIXME: The intel_crtc->active here should be switched to
1004 * crtc->state->active once we have proper CRTC states wired up
1005 * for atomic.
1006 */
1007 return intel_crtc->active && crtc->primary->state->fb &&
1008 intel_crtc->config->base.adjusted_mode.crtc_clock;
1009 }
1010
1011 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1012 enum pipe pipe)
1013 {
1014 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1016
1017 return intel_crtc->config->cpu_transcoder;
1018 }
1019
1020 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1021 {
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023 u32 reg = PIPEDSL(pipe);
1024 u32 line1, line2;
1025 u32 line_mask;
1026
1027 if (IS_GEN2(dev))
1028 line_mask = DSL_LINEMASK_GEN2;
1029 else
1030 line_mask = DSL_LINEMASK_GEN3;
1031
1032 line1 = I915_READ(reg) & line_mask;
1033 mdelay(5);
1034 line2 = I915_READ(reg) & line_mask;
1035
1036 return line1 == line2;
1037 }
1038
1039 /*
1040 * intel_wait_for_pipe_off - wait for pipe to turn off
1041 * @crtc: crtc whose pipe to wait for
1042 *
1043 * After disabling a pipe, we can't wait for vblank in the usual way,
1044 * spinning on the vblank interrupt status bit, since we won't actually
1045 * see an interrupt when the pipe is disabled.
1046 *
1047 * On Gen4 and above:
1048 * wait for the pipe register state bit to turn off
1049 *
1050 * Otherwise:
1051 * wait for the display line value to settle (it usually
1052 * ends up stopping at the start of the next frame).
1053 *
1054 */
1055 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1056 {
1057 struct drm_device *dev = crtc->base.dev;
1058 struct drm_i915_private *dev_priv = dev->dev_private;
1059 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1060 enum pipe pipe = crtc->pipe;
1061
1062 if (INTEL_INFO(dev)->gen >= 4) {
1063 int reg = PIPECONF(cpu_transcoder);
1064
1065 /* Wait for the Pipe State to go off */
1066 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1067 100))
1068 WARN(1, "pipe_off wait timed out\n");
1069 } else {
1070 /* Wait for the display line to settle */
1071 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1072 WARN(1, "pipe_off wait timed out\n");
1073 }
1074 }
1075
1076 /*
1077 * ibx_digital_port_connected - is the specified port connected?
1078 * @dev_priv: i915 private structure
1079 * @port: the port to test
1080 *
1081 * Returns true if @port is connected, false otherwise.
1082 */
1083 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1084 struct intel_digital_port *port)
1085 {
1086 u32 bit;
1087
1088 if (HAS_PCH_IBX(dev_priv->dev)) {
1089 switch (port->port) {
1090 case PORT_B:
1091 bit = SDE_PORTB_HOTPLUG;
1092 break;
1093 case PORT_C:
1094 bit = SDE_PORTC_HOTPLUG;
1095 break;
1096 case PORT_D:
1097 bit = SDE_PORTD_HOTPLUG;
1098 break;
1099 default:
1100 return true;
1101 }
1102 } else {
1103 switch (port->port) {
1104 case PORT_B:
1105 bit = SDE_PORTB_HOTPLUG_CPT;
1106 break;
1107 case PORT_C:
1108 bit = SDE_PORTC_HOTPLUG_CPT;
1109 break;
1110 case PORT_D:
1111 bit = SDE_PORTD_HOTPLUG_CPT;
1112 break;
1113 default:
1114 return true;
1115 }
1116 }
1117
1118 return I915_READ(SDEISR) & bit;
1119 }
1120
1121 static const char *state_string(bool enabled)
1122 {
1123 return enabled ? "on" : "off";
1124 }
1125
1126 /* Only for pre-ILK configs */
1127 void assert_pll(struct drm_i915_private *dev_priv,
1128 enum pipe pipe, bool state)
1129 {
1130 int reg;
1131 u32 val;
1132 bool cur_state;
1133
1134 reg = DPLL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & DPLL_VCO_ENABLE);
1137 I915_STATE_WARN(cur_state != state,
1138 "PLL state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140 }
1141
1142 /* XXX: the dsi pll is shared between MIPI DSI ports */
1143 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1144 {
1145 u32 val;
1146 bool cur_state;
1147
1148 mutex_lock(&dev_priv->sb_lock);
1149 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1150 mutex_unlock(&dev_priv->sb_lock);
1151
1152 cur_state = val & DSI_PLL_VCO_EN;
1153 I915_STATE_WARN(cur_state != state,
1154 "DSI PLL state assertion failure (expected %s, current %s)\n",
1155 state_string(state), state_string(cur_state));
1156 }
1157 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1158 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1159
1160 struct intel_shared_dpll *
1161 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1162 {
1163 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1164
1165 if (crtc->config->shared_dpll < 0)
1166 return NULL;
1167
1168 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1169 }
1170
1171 /* For ILK+ */
1172 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1173 struct intel_shared_dpll *pll,
1174 bool state)
1175 {
1176 bool cur_state;
1177 struct intel_dpll_hw_state hw_state;
1178
1179 if (WARN (!pll,
1180 "asserting DPLL %s with no DPLL\n", state_string(state)))
1181 return;
1182
1183 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1184 I915_STATE_WARN(cur_state != state,
1185 "%s assertion failure (expected %s, current %s)\n",
1186 pll->name, state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, bool state)
1191 {
1192 int reg;
1193 u32 val;
1194 bool cur_state;
1195 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1196 pipe);
1197
1198 if (HAS_DDI(dev_priv->dev)) {
1199 /* DDI does not have a specific FDI_TX register */
1200 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1203 } else {
1204 reg = FDI_TX_CTL(pipe);
1205 val = I915_READ(reg);
1206 cur_state = !!(val & FDI_TX_ENABLE);
1207 }
1208 I915_STATE_WARN(cur_state != state,
1209 "FDI TX state assertion failure (expected %s, current %s)\n",
1210 state_string(state), state_string(cur_state));
1211 }
1212 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1213 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1214
1215 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1216 enum pipe pipe, bool state)
1217 {
1218 int reg;
1219 u32 val;
1220 bool cur_state;
1221
1222 reg = FDI_RX_CTL(pipe);
1223 val = I915_READ(reg);
1224 cur_state = !!(val & FDI_RX_ENABLE);
1225 I915_STATE_WARN(cur_state != state,
1226 "FDI RX state assertion failure (expected %s, current %s)\n",
1227 state_string(state), state_string(cur_state));
1228 }
1229 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1230 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1231
1232 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234 {
1235 int reg;
1236 u32 val;
1237
1238 /* ILK FDI PLL is always enabled */
1239 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1240 return;
1241
1242 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1243 if (HAS_DDI(dev_priv->dev))
1244 return;
1245
1246 reg = FDI_TX_CTL(pipe);
1247 val = I915_READ(reg);
1248 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1249 }
1250
1251 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, bool state)
1253 {
1254 int reg;
1255 u32 val;
1256 bool cur_state;
1257
1258 reg = FDI_RX_CTL(pipe);
1259 val = I915_READ(reg);
1260 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1261 I915_STATE_WARN(cur_state != state,
1262 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1263 state_string(state), state_string(cur_state));
1264 }
1265
1266 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1267 enum pipe pipe)
1268 {
1269 struct drm_device *dev = dev_priv->dev;
1270 int pp_reg;
1271 u32 val;
1272 enum pipe panel_pipe = PIPE_A;
1273 bool locked = true;
1274
1275 if (WARN_ON(HAS_DDI(dev)))
1276 return;
1277
1278 if (HAS_PCH_SPLIT(dev)) {
1279 u32 port_sel;
1280
1281 pp_reg = PCH_PP_CONTROL;
1282 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1283
1284 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1285 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 /* XXX: else fix for eDP */
1288 } else if (IS_VALLEYVIEW(dev)) {
1289 /* presumably write lock depends on pipe, not port select */
1290 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1291 panel_pipe = pipe;
1292 } else {
1293 pp_reg = PP_CONTROL;
1294 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1295 panel_pipe = PIPE_B;
1296 }
1297
1298 val = I915_READ(pp_reg);
1299 if (!(val & PANEL_POWER_ON) ||
1300 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1301 locked = false;
1302
1303 I915_STATE_WARN(panel_pipe == pipe && locked,
1304 "panel assertion failure, pipe %c regs locked\n",
1305 pipe_name(pipe));
1306 }
1307
1308 static void assert_cursor(struct drm_i915_private *dev_priv,
1309 enum pipe pipe, bool state)
1310 {
1311 struct drm_device *dev = dev_priv->dev;
1312 bool cur_state;
1313
1314 if (IS_845G(dev) || IS_I865G(dev))
1315 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1316 else
1317 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1318
1319 I915_STATE_WARN(cur_state != state,
1320 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1321 pipe_name(pipe), state_string(state), state_string(cur_state));
1322 }
1323 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1324 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1325
1326 void assert_pipe(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328 {
1329 int reg;
1330 u32 val;
1331 bool cur_state;
1332 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1333 pipe);
1334
1335 /* if we need the pipe quirk it must be always on */
1336 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1337 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1338 state = true;
1339
1340 if (!intel_display_power_is_enabled(dev_priv,
1341 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1342 cur_state = false;
1343 } else {
1344 reg = PIPECONF(cpu_transcoder);
1345 val = I915_READ(reg);
1346 cur_state = !!(val & PIPECONF_ENABLE);
1347 }
1348
1349 I915_STATE_WARN(cur_state != state,
1350 "pipe %c assertion failure (expected %s, current %s)\n",
1351 pipe_name(pipe), state_string(state), state_string(cur_state));
1352 }
1353
1354 static void assert_plane(struct drm_i915_private *dev_priv,
1355 enum plane plane, bool state)
1356 {
1357 int reg;
1358 u32 val;
1359 bool cur_state;
1360
1361 reg = DSPCNTR(plane);
1362 val = I915_READ(reg);
1363 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1364 I915_STATE_WARN(cur_state != state,
1365 "plane %c assertion failure (expected %s, current %s)\n",
1366 plane_name(plane), state_string(state), state_string(cur_state));
1367 }
1368
1369 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1370 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1371
1372 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe)
1374 {
1375 struct drm_device *dev = dev_priv->dev;
1376 int reg, i;
1377 u32 val;
1378 int cur_pipe;
1379
1380 /* Primary planes are fixed to pipes on gen4+ */
1381 if (INTEL_INFO(dev)->gen >= 4) {
1382 reg = DSPCNTR(pipe);
1383 val = I915_READ(reg);
1384 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1385 "plane %c assertion failure, should be disabled but not\n",
1386 plane_name(pipe));
1387 return;
1388 }
1389
1390 /* Need to check both planes against the pipe */
1391 for_each_pipe(dev_priv, i) {
1392 reg = DSPCNTR(i);
1393 val = I915_READ(reg);
1394 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1395 DISPPLANE_SEL_PIPE_SHIFT;
1396 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1397 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1398 plane_name(i), pipe_name(pipe));
1399 }
1400 }
1401
1402 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1403 enum pipe pipe)
1404 {
1405 struct drm_device *dev = dev_priv->dev;
1406 int reg, sprite;
1407 u32 val;
1408
1409 if (INTEL_INFO(dev)->gen >= 9) {
1410 for_each_sprite(dev_priv, pipe, sprite) {
1411 val = I915_READ(PLANE_CTL(pipe, sprite));
1412 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1413 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1414 sprite, pipe_name(pipe));
1415 }
1416 } else if (IS_VALLEYVIEW(dev)) {
1417 for_each_sprite(dev_priv, pipe, sprite) {
1418 reg = SPCNTR(pipe, sprite);
1419 val = I915_READ(reg);
1420 I915_STATE_WARN(val & SP_ENABLE,
1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1422 sprite_name(pipe, sprite), pipe_name(pipe));
1423 }
1424 } else if (INTEL_INFO(dev)->gen >= 7) {
1425 reg = SPRCTL(pipe);
1426 val = I915_READ(reg);
1427 I915_STATE_WARN(val & SPRITE_ENABLE,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 plane_name(pipe), pipe_name(pipe));
1430 } else if (INTEL_INFO(dev)->gen >= 5) {
1431 reg = DVSCNTR(pipe);
1432 val = I915_READ(reg);
1433 I915_STATE_WARN(val & DVS_ENABLE,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe), pipe_name(pipe));
1436 }
1437 }
1438
1439 static void assert_vblank_disabled(struct drm_crtc *crtc)
1440 {
1441 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1442 drm_crtc_vblank_put(crtc);
1443 }
1444
1445 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1446 {
1447 u32 val;
1448 bool enabled;
1449
1450 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1451
1452 val = I915_READ(PCH_DREF_CONTROL);
1453 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1454 DREF_SUPERSPREAD_SOURCE_MASK));
1455 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1456 }
1457
1458 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1459 enum pipe pipe)
1460 {
1461 int reg;
1462 u32 val;
1463 bool enabled;
1464
1465 reg = PCH_TRANSCONF(pipe);
1466 val = I915_READ(reg);
1467 enabled = !!(val & TRANS_ENABLE);
1468 I915_STATE_WARN(enabled,
1469 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1470 pipe_name(pipe));
1471 }
1472
1473 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, u32 port_sel, u32 val)
1475 {
1476 if ((val & DP_PORT_EN) == 0)
1477 return false;
1478
1479 if (HAS_PCH_CPT(dev_priv->dev)) {
1480 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1481 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1482 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1483 return false;
1484 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1485 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1486 return false;
1487 } else {
1488 if ((val & DP_PIPE_MASK) != (pipe << 30))
1489 return false;
1490 }
1491 return true;
1492 }
1493
1494 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, u32 val)
1496 {
1497 if ((val & SDVO_ENABLE) == 0)
1498 return false;
1499
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
1501 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1502 return false;
1503 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1504 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1505 return false;
1506 } else {
1507 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1508 return false;
1509 }
1510 return true;
1511 }
1512
1513 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1514 enum pipe pipe, u32 val)
1515 {
1516 if ((val & LVDS_PORT_EN) == 0)
1517 return false;
1518
1519 if (HAS_PCH_CPT(dev_priv->dev)) {
1520 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1521 return false;
1522 } else {
1523 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1524 return false;
1525 }
1526 return true;
1527 }
1528
1529 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1530 enum pipe pipe, u32 val)
1531 {
1532 if ((val & ADPA_DAC_ENABLE) == 0)
1533 return false;
1534 if (HAS_PCH_CPT(dev_priv->dev)) {
1535 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1536 return false;
1537 } else {
1538 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1539 return false;
1540 }
1541 return true;
1542 }
1543
1544 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1545 enum pipe pipe, int reg, u32 port_sel)
1546 {
1547 u32 val = I915_READ(reg);
1548 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1549 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1550 reg, pipe_name(pipe));
1551
1552 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1553 && (val & DP_PIPEB_SELECT),
1554 "IBX PCH dp port still using transcoder B\n");
1555 }
1556
1557 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1558 enum pipe pipe, int reg)
1559 {
1560 u32 val = I915_READ(reg);
1561 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1562 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1563 reg, pipe_name(pipe));
1564
1565 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1566 && (val & SDVO_PIPE_B_SELECT),
1567 "IBX PCH hdmi port still using transcoder B\n");
1568 }
1569
1570 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1571 enum pipe pipe)
1572 {
1573 int reg;
1574 u32 val;
1575
1576 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1577 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1579
1580 reg = PCH_ADPA;
1581 val = I915_READ(reg);
1582 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1583 "PCH VGA enabled on transcoder %c, should be disabled\n",
1584 pipe_name(pipe));
1585
1586 reg = PCH_LVDS;
1587 val = I915_READ(reg);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590 pipe_name(pipe));
1591
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void intel_init_dpio(struct drm_device *dev)
1598 {
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601 if (!IS_VALLEYVIEW(dev))
1602 return;
1603
1604 /*
1605 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1606 * CHV x1 PHY (DP/HDMI D)
1607 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1608 */
1609 if (IS_CHERRYVIEW(dev)) {
1610 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1611 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1612 } else {
1613 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1614 }
1615 }
1616
1617 static void vlv_enable_pll(struct intel_crtc *crtc,
1618 const struct intel_crtc_state *pipe_config)
1619 {
1620 struct drm_device *dev = crtc->base.dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 int reg = DPLL(crtc->pipe);
1623 u32 dpll = pipe_config->dpll_hw_state.dpll;
1624
1625 assert_pipe_disabled(dev_priv, crtc->pipe);
1626
1627 /* No really, not for ILK+ */
1628 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1629
1630 /* PLL is protected by panel, make sure we can write it */
1631 if (IS_MOBILE(dev_priv->dev))
1632 assert_panel_unlocked(dev_priv, crtc->pipe);
1633
1634 I915_WRITE(reg, dpll);
1635 POSTING_READ(reg);
1636 udelay(150);
1637
1638 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1639 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1640
1641 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1642 POSTING_READ(DPLL_MD(crtc->pipe));
1643
1644 /* We do this three times for luck */
1645 I915_WRITE(reg, dpll);
1646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg, dpll);
1649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
1651 I915_WRITE(reg, dpll);
1652 POSTING_READ(reg);
1653 udelay(150); /* wait for warmup */
1654 }
1655
1656 static void chv_enable_pll(struct intel_crtc *crtc,
1657 const struct intel_crtc_state *pipe_config)
1658 {
1659 struct drm_device *dev = crtc->base.dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 int pipe = crtc->pipe;
1662 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1663 u32 tmp;
1664
1665 assert_pipe_disabled(dev_priv, crtc->pipe);
1666
1667 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1668
1669 mutex_lock(&dev_priv->sb_lock);
1670
1671 /* Enable back the 10bit clock to display controller */
1672 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1673 tmp |= DPIO_DCLKP_EN;
1674 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1675
1676 mutex_unlock(&dev_priv->sb_lock);
1677
1678 /*
1679 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1680 */
1681 udelay(1);
1682
1683 /* Enable PLL */
1684 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1685
1686 /* Check PLL is locked */
1687 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1688 DRM_ERROR("PLL %d failed to lock\n", pipe);
1689
1690 /* not sure when this should be written */
1691 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1692 POSTING_READ(DPLL_MD(pipe));
1693 }
1694
1695 static int intel_num_dvo_pipes(struct drm_device *dev)
1696 {
1697 struct intel_crtc *crtc;
1698 int count = 0;
1699
1700 for_each_intel_crtc(dev, crtc)
1701 count += crtc->base.state->active &&
1702 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1703
1704 return count;
1705 }
1706
1707 static void i9xx_enable_pll(struct intel_crtc *crtc)
1708 {
1709 struct drm_device *dev = crtc->base.dev;
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 int reg = DPLL(crtc->pipe);
1712 u32 dpll = crtc->config->dpll_hw_state.dpll;
1713
1714 assert_pipe_disabled(dev_priv, crtc->pipe);
1715
1716 /* No really, not for ILK+ */
1717 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1718
1719 /* PLL is protected by panel, make sure we can write it */
1720 if (IS_MOBILE(dev) && !IS_I830(dev))
1721 assert_panel_unlocked(dev_priv, crtc->pipe);
1722
1723 /* Enable DVO 2x clock on both PLLs if necessary */
1724 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1725 /*
1726 * It appears to be important that we don't enable this
1727 * for the current pipe before otherwise configuring the
1728 * PLL. No idea how this should be handled if multiple
1729 * DVO outputs are enabled simultaneosly.
1730 */
1731 dpll |= DPLL_DVO_2X_MODE;
1732 I915_WRITE(DPLL(!crtc->pipe),
1733 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1734 }
1735
1736 /* Wait for the clocks to stabilize. */
1737 POSTING_READ(reg);
1738 udelay(150);
1739
1740 if (INTEL_INFO(dev)->gen >= 4) {
1741 I915_WRITE(DPLL_MD(crtc->pipe),
1742 crtc->config->dpll_hw_state.dpll_md);
1743 } else {
1744 /* The pixel multiplier can only be updated once the
1745 * DPLL is enabled and the clocks are stable.
1746 *
1747 * So write it again.
1748 */
1749 I915_WRITE(reg, dpll);
1750 }
1751
1752 /* We do this three times for luck */
1753 I915_WRITE(reg, dpll);
1754 POSTING_READ(reg);
1755 udelay(150); /* wait for warmup */
1756 I915_WRITE(reg, dpll);
1757 POSTING_READ(reg);
1758 udelay(150); /* wait for warmup */
1759 I915_WRITE(reg, dpll);
1760 POSTING_READ(reg);
1761 udelay(150); /* wait for warmup */
1762 }
1763
1764 /**
1765 * i9xx_disable_pll - disable a PLL
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe PLL to disable
1768 *
1769 * Disable the PLL for @pipe, making sure the pipe is off first.
1770 *
1771 * Note! This is for pre-ILK only.
1772 */
1773 static void i9xx_disable_pll(struct intel_crtc *crtc)
1774 {
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 enum pipe pipe = crtc->pipe;
1778
1779 /* Disable DVO 2x clock on both PLLs if necessary */
1780 if (IS_I830(dev) &&
1781 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1782 !intel_num_dvo_pipes(dev)) {
1783 I915_WRITE(DPLL(PIPE_B),
1784 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1785 I915_WRITE(DPLL(PIPE_A),
1786 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1787 }
1788
1789 /* Don't disable pipe or pipe PLLs if needed */
1790 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1791 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1792 return;
1793
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv, pipe);
1796
1797 I915_WRITE(DPLL(pipe), 0);
1798 POSTING_READ(DPLL(pipe));
1799 }
1800
1801 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1802 {
1803 u32 val = 0;
1804
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1807
1808 /*
1809 * Leave integrated clock source and reference clock enabled for pipe B.
1810 * The latter is needed for VGA hotplug / manual detection.
1811 */
1812 if (pipe == PIPE_B)
1813 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1814 I915_WRITE(DPLL(pipe), val);
1815 POSTING_READ(DPLL(pipe));
1816
1817 }
1818
1819 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1820 {
1821 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1822 u32 val;
1823
1824 /* Make sure the pipe isn't still relying on us */
1825 assert_pipe_disabled(dev_priv, pipe);
1826
1827 /* Set PLL en = 0 */
1828 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1829 if (pipe != PIPE_A)
1830 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1831 I915_WRITE(DPLL(pipe), val);
1832 POSTING_READ(DPLL(pipe));
1833
1834 mutex_lock(&dev_priv->sb_lock);
1835
1836 /* Disable 10bit clock to display controller */
1837 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1838 val &= ~DPIO_DCLKP_EN;
1839 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1840
1841 /* disable left/right clock distribution */
1842 if (pipe != PIPE_B) {
1843 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1844 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1845 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1846 } else {
1847 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1848 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1849 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1850 }
1851
1852 mutex_unlock(&dev_priv->sb_lock);
1853 }
1854
1855 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1856 struct intel_digital_port *dport,
1857 unsigned int expected_mask)
1858 {
1859 u32 port_mask;
1860 int dpll_reg;
1861
1862 switch (dport->port) {
1863 case PORT_B:
1864 port_mask = DPLL_PORTB_READY_MASK;
1865 dpll_reg = DPLL(0);
1866 break;
1867 case PORT_C:
1868 port_mask = DPLL_PORTC_READY_MASK;
1869 dpll_reg = DPLL(0);
1870 expected_mask <<= 4;
1871 break;
1872 case PORT_D:
1873 port_mask = DPLL_PORTD_READY_MASK;
1874 dpll_reg = DPIO_PHY_STATUS;
1875 break;
1876 default:
1877 BUG();
1878 }
1879
1880 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1881 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1882 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1883 }
1884
1885 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1886 {
1887 struct drm_device *dev = crtc->base.dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1890
1891 if (WARN_ON(pll == NULL))
1892 return;
1893
1894 WARN_ON(!pll->config.crtc_mask);
1895 if (pll->active == 0) {
1896 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1897 WARN_ON(pll->on);
1898 assert_shared_dpll_disabled(dev_priv, pll);
1899
1900 pll->mode_set(dev_priv, pll);
1901 }
1902 }
1903
1904 /**
1905 * intel_enable_shared_dpll - enable PCH PLL
1906 * @dev_priv: i915 private structure
1907 * @pipe: pipe PLL to enable
1908 *
1909 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1910 * drives the transcoder clock.
1911 */
1912 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1913 {
1914 struct drm_device *dev = crtc->base.dev;
1915 struct drm_i915_private *dev_priv = dev->dev_private;
1916 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1917
1918 if (WARN_ON(pll == NULL))
1919 return;
1920
1921 if (WARN_ON(pll->config.crtc_mask == 0))
1922 return;
1923
1924 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1925 pll->name, pll->active, pll->on,
1926 crtc->base.base.id);
1927
1928 if (pll->active++) {
1929 WARN_ON(!pll->on);
1930 assert_shared_dpll_enabled(dev_priv, pll);
1931 return;
1932 }
1933 WARN_ON(pll->on);
1934
1935 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1936
1937 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1938 pll->enable(dev_priv, pll);
1939 pll->on = true;
1940 }
1941
1942 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1943 {
1944 struct drm_device *dev = crtc->base.dev;
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1947
1948 /* PCH only available on ILK+ */
1949 BUG_ON(INTEL_INFO(dev)->gen < 5);
1950 if (WARN_ON(pll == NULL))
1951 return;
1952
1953 if (WARN_ON(pll->config.crtc_mask == 0))
1954 return;
1955
1956 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1957 pll->name, pll->active, pll->on,
1958 crtc->base.base.id);
1959
1960 if (WARN_ON(pll->active == 0)) {
1961 assert_shared_dpll_disabled(dev_priv, pll);
1962 return;
1963 }
1964
1965 assert_shared_dpll_enabled(dev_priv, pll);
1966 WARN_ON(!pll->on);
1967 if (--pll->active)
1968 return;
1969
1970 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1971 pll->disable(dev_priv, pll);
1972 pll->on = false;
1973
1974 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1975 }
1976
1977 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1978 enum pipe pipe)
1979 {
1980 struct drm_device *dev = dev_priv->dev;
1981 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983 uint32_t reg, val, pipeconf_val;
1984
1985 /* PCH only available on ILK+ */
1986 BUG_ON(!HAS_PCH_SPLIT(dev));
1987
1988 /* Make sure PCH DPLL is enabled */
1989 assert_shared_dpll_enabled(dev_priv,
1990 intel_crtc_to_shared_dpll(intel_crtc));
1991
1992 /* FDI must be feeding us bits for PCH ports */
1993 assert_fdi_tx_enabled(dev_priv, pipe);
1994 assert_fdi_rx_enabled(dev_priv, pipe);
1995
1996 if (HAS_PCH_CPT(dev)) {
1997 /* Workaround: Set the timing override bit before enabling the
1998 * pch transcoder. */
1999 reg = TRANS_CHICKEN2(pipe);
2000 val = I915_READ(reg);
2001 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2002 I915_WRITE(reg, val);
2003 }
2004
2005 reg = PCH_TRANSCONF(pipe);
2006 val = I915_READ(reg);
2007 pipeconf_val = I915_READ(PIPECONF(pipe));
2008
2009 if (HAS_PCH_IBX(dev_priv->dev)) {
2010 /*
2011 * Make the BPC in transcoder be consistent with
2012 * that in pipeconf reg. For HDMI we must use 8bpc
2013 * here for both 8bpc and 12bpc.
2014 */
2015 val &= ~PIPECONF_BPC_MASK;
2016 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2017 val |= PIPECONF_8BPC;
2018 else
2019 val |= pipeconf_val & PIPECONF_BPC_MASK;
2020 }
2021
2022 val &= ~TRANS_INTERLACE_MASK;
2023 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2024 if (HAS_PCH_IBX(dev_priv->dev) &&
2025 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2026 val |= TRANS_LEGACY_INTERLACED_ILK;
2027 else
2028 val |= TRANS_INTERLACED;
2029 else
2030 val |= TRANS_PROGRESSIVE;
2031
2032 I915_WRITE(reg, val | TRANS_ENABLE);
2033 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2034 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2035 }
2036
2037 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2038 enum transcoder cpu_transcoder)
2039 {
2040 u32 val, pipeconf_val;
2041
2042 /* PCH only available on ILK+ */
2043 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2044
2045 /* FDI must be feeding us bits for PCH ports */
2046 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2047 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2048
2049 /* Workaround: set timing override bit. */
2050 val = I915_READ(_TRANSA_CHICKEN2);
2051 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2052 I915_WRITE(_TRANSA_CHICKEN2, val);
2053
2054 val = TRANS_ENABLE;
2055 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2056
2057 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2058 PIPECONF_INTERLACED_ILK)
2059 val |= TRANS_INTERLACED;
2060 else
2061 val |= TRANS_PROGRESSIVE;
2062
2063 I915_WRITE(LPT_TRANSCONF, val);
2064 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2065 DRM_ERROR("Failed to enable PCH transcoder\n");
2066 }
2067
2068 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2069 enum pipe pipe)
2070 {
2071 struct drm_device *dev = dev_priv->dev;
2072 uint32_t reg, val;
2073
2074 /* FDI relies on the transcoder */
2075 assert_fdi_tx_disabled(dev_priv, pipe);
2076 assert_fdi_rx_disabled(dev_priv, pipe);
2077
2078 /* Ports must be off as well */
2079 assert_pch_ports_disabled(dev_priv, pipe);
2080
2081 reg = PCH_TRANSCONF(pipe);
2082 val = I915_READ(reg);
2083 val &= ~TRANS_ENABLE;
2084 I915_WRITE(reg, val);
2085 /* wait for PCH transcoder off, transcoder state */
2086 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2087 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2088
2089 if (!HAS_PCH_IBX(dev)) {
2090 /* Workaround: Clear the timing override chicken bit again. */
2091 reg = TRANS_CHICKEN2(pipe);
2092 val = I915_READ(reg);
2093 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094 I915_WRITE(reg, val);
2095 }
2096 }
2097
2098 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2099 {
2100 u32 val;
2101
2102 val = I915_READ(LPT_TRANSCONF);
2103 val &= ~TRANS_ENABLE;
2104 I915_WRITE(LPT_TRANSCONF, val);
2105 /* wait for PCH transcoder off, transcoder state */
2106 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2107 DRM_ERROR("Failed to disable PCH transcoder\n");
2108
2109 /* Workaround: clear timing override bit. */
2110 val = I915_READ(_TRANSA_CHICKEN2);
2111 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2112 I915_WRITE(_TRANSA_CHICKEN2, val);
2113 }
2114
2115 /**
2116 * intel_enable_pipe - enable a pipe, asserting requirements
2117 * @crtc: crtc responsible for the pipe
2118 *
2119 * Enable @crtc's pipe, making sure that various hardware specific requirements
2120 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2121 */
2122 static void intel_enable_pipe(struct intel_crtc *crtc)
2123 {
2124 struct drm_device *dev = crtc->base.dev;
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126 enum pipe pipe = crtc->pipe;
2127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2128 pipe);
2129 enum pipe pch_transcoder;
2130 int reg;
2131 u32 val;
2132
2133 assert_planes_disabled(dev_priv, pipe);
2134 assert_cursor_disabled(dev_priv, pipe);
2135 assert_sprites_disabled(dev_priv, pipe);
2136
2137 if (HAS_PCH_LPT(dev_priv->dev))
2138 pch_transcoder = TRANSCODER_A;
2139 else
2140 pch_transcoder = pipe;
2141
2142 /*
2143 * A pipe without a PLL won't actually be able to drive bits from
2144 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2145 * need the check.
2146 */
2147 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2148 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2149 assert_dsi_pll_enabled(dev_priv);
2150 else
2151 assert_pll_enabled(dev_priv, pipe);
2152 else {
2153 if (crtc->config->has_pch_encoder) {
2154 /* if driving the PCH, we need FDI enabled */
2155 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2156 assert_fdi_tx_pll_enabled(dev_priv,
2157 (enum pipe) cpu_transcoder);
2158 }
2159 /* FIXME: assert CPU port conditions for SNB+ */
2160 }
2161
2162 reg = PIPECONF(cpu_transcoder);
2163 val = I915_READ(reg);
2164 if (val & PIPECONF_ENABLE) {
2165 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2166 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2167 return;
2168 }
2169
2170 I915_WRITE(reg, val | PIPECONF_ENABLE);
2171 POSTING_READ(reg);
2172 }
2173
2174 /**
2175 * intel_disable_pipe - disable a pipe, asserting requirements
2176 * @crtc: crtc whose pipes is to be disabled
2177 *
2178 * Disable the pipe of @crtc, making sure that various hardware
2179 * specific requirements are met, if applicable, e.g. plane
2180 * disabled, panel fitter off, etc.
2181 *
2182 * Will wait until the pipe has shut down before returning.
2183 */
2184 static void intel_disable_pipe(struct intel_crtc *crtc)
2185 {
2186 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2187 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2188 enum pipe pipe = crtc->pipe;
2189 int reg;
2190 u32 val;
2191
2192 /*
2193 * Make sure planes won't keep trying to pump pixels to us,
2194 * or we might hang the display.
2195 */
2196 assert_planes_disabled(dev_priv, pipe);
2197 assert_cursor_disabled(dev_priv, pipe);
2198 assert_sprites_disabled(dev_priv, pipe);
2199
2200 reg = PIPECONF(cpu_transcoder);
2201 val = I915_READ(reg);
2202 if ((val & PIPECONF_ENABLE) == 0)
2203 return;
2204
2205 /*
2206 * Double wide has implications for planes
2207 * so best keep it disabled when not needed.
2208 */
2209 if (crtc->config->double_wide)
2210 val &= ~PIPECONF_DOUBLE_WIDE;
2211
2212 /* Don't disable pipe or pipe PLLs if needed */
2213 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2214 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2215 val &= ~PIPECONF_ENABLE;
2216
2217 I915_WRITE(reg, val);
2218 if ((val & PIPECONF_ENABLE) == 0)
2219 intel_wait_for_pipe_off(crtc);
2220 }
2221
2222 /**
2223 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2224 * @plane: plane to be enabled
2225 * @crtc: crtc for the plane
2226 *
2227 * Enable @plane on @crtc, making sure that the pipe is running first.
2228 */
2229 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2230 struct drm_crtc *crtc)
2231 {
2232 struct drm_device *dev = plane->dev;
2233 struct drm_i915_private *dev_priv = dev->dev_private;
2234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2235
2236 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2237 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2238 to_intel_plane_state(plane->state)->visible = true;
2239
2240 dev_priv->display.update_primary_plane(crtc, plane->fb,
2241 crtc->x, crtc->y);
2242 }
2243
2244 static bool need_vtd_wa(struct drm_device *dev)
2245 {
2246 #ifdef CONFIG_INTEL_IOMMU
2247 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2248 return true;
2249 #endif
2250 return false;
2251 }
2252
2253 unsigned int
2254 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2255 uint64_t fb_format_modifier)
2256 {
2257 unsigned int tile_height;
2258 uint32_t pixel_bytes;
2259
2260 switch (fb_format_modifier) {
2261 case DRM_FORMAT_MOD_NONE:
2262 tile_height = 1;
2263 break;
2264 case I915_FORMAT_MOD_X_TILED:
2265 tile_height = IS_GEN2(dev) ? 16 : 8;
2266 break;
2267 case I915_FORMAT_MOD_Y_TILED:
2268 tile_height = 32;
2269 break;
2270 case I915_FORMAT_MOD_Yf_TILED:
2271 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2272 switch (pixel_bytes) {
2273 default:
2274 case 1:
2275 tile_height = 64;
2276 break;
2277 case 2:
2278 case 4:
2279 tile_height = 32;
2280 break;
2281 case 8:
2282 tile_height = 16;
2283 break;
2284 case 16:
2285 WARN_ONCE(1,
2286 "128-bit pixels are not supported for display!");
2287 tile_height = 16;
2288 break;
2289 }
2290 break;
2291 default:
2292 MISSING_CASE(fb_format_modifier);
2293 tile_height = 1;
2294 break;
2295 }
2296
2297 return tile_height;
2298 }
2299
2300 unsigned int
2301 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2302 uint32_t pixel_format, uint64_t fb_format_modifier)
2303 {
2304 return ALIGN(height, intel_tile_height(dev, pixel_format,
2305 fb_format_modifier));
2306 }
2307
2308 static int
2309 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2310 const struct drm_plane_state *plane_state)
2311 {
2312 struct intel_rotation_info *info = &view->rotation_info;
2313
2314 *view = i915_ggtt_view_normal;
2315
2316 if (!plane_state)
2317 return 0;
2318
2319 if (!intel_rotation_90_or_270(plane_state->rotation))
2320 return 0;
2321
2322 *view = i915_ggtt_view_rotated;
2323
2324 info->height = fb->height;
2325 info->pixel_format = fb->pixel_format;
2326 info->pitch = fb->pitches[0];
2327 info->fb_modifier = fb->modifier[0];
2328
2329 return 0;
2330 }
2331
2332 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2333 {
2334 if (INTEL_INFO(dev_priv)->gen >= 9)
2335 return 256 * 1024;
2336 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2337 IS_VALLEYVIEW(dev_priv))
2338 return 128 * 1024;
2339 else if (INTEL_INFO(dev_priv)->gen >= 4)
2340 return 4 * 1024;
2341 else
2342 return 0;
2343 }
2344
2345 int
2346 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2347 struct drm_framebuffer *fb,
2348 const struct drm_plane_state *plane_state,
2349 struct intel_engine_cs *pipelined)
2350 {
2351 struct drm_device *dev = fb->dev;
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2354 struct i915_ggtt_view view;
2355 u32 alignment;
2356 int ret;
2357
2358 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2359
2360 switch (fb->modifier[0]) {
2361 case DRM_FORMAT_MOD_NONE:
2362 alignment = intel_linear_alignment(dev_priv);
2363 break;
2364 case I915_FORMAT_MOD_X_TILED:
2365 if (INTEL_INFO(dev)->gen >= 9)
2366 alignment = 256 * 1024;
2367 else {
2368 /* pin() will align the object as required by fence */
2369 alignment = 0;
2370 }
2371 break;
2372 case I915_FORMAT_MOD_Y_TILED:
2373 case I915_FORMAT_MOD_Yf_TILED:
2374 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2375 "Y tiling bo slipped through, driver bug!\n"))
2376 return -EINVAL;
2377 alignment = 1 * 1024 * 1024;
2378 break;
2379 default:
2380 MISSING_CASE(fb->modifier[0]);
2381 return -EINVAL;
2382 }
2383
2384 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2385 if (ret)
2386 return ret;
2387
2388 /* Note that the w/a also requires 64 PTE of padding following the
2389 * bo. We currently fill all unused PTE with the shadow page and so
2390 * we should always have valid PTE following the scanout preventing
2391 * the VT-d warning.
2392 */
2393 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2394 alignment = 256 * 1024;
2395
2396 /*
2397 * Global gtt pte registers are special registers which actually forward
2398 * writes to a chunk of system memory. Which means that there is no risk
2399 * that the register values disappear as soon as we call
2400 * intel_runtime_pm_put(), so it is correct to wrap only the
2401 * pin/unpin/fence and not more.
2402 */
2403 intel_runtime_pm_get(dev_priv);
2404
2405 dev_priv->mm.interruptible = false;
2406 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2407 &view);
2408 if (ret)
2409 goto err_interruptible;
2410
2411 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2412 * fence, whereas 965+ only requires a fence if using
2413 * framebuffer compression. For simplicity, we always install
2414 * a fence as the cost is not that onerous.
2415 */
2416 ret = i915_gem_object_get_fence(obj);
2417 if (ret)
2418 goto err_unpin;
2419
2420 i915_gem_object_pin_fence(obj);
2421
2422 dev_priv->mm.interruptible = true;
2423 intel_runtime_pm_put(dev_priv);
2424 return 0;
2425
2426 err_unpin:
2427 i915_gem_object_unpin_from_display_plane(obj, &view);
2428 err_interruptible:
2429 dev_priv->mm.interruptible = true;
2430 intel_runtime_pm_put(dev_priv);
2431 return ret;
2432 }
2433
2434 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2435 const struct drm_plane_state *plane_state)
2436 {
2437 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2438 struct i915_ggtt_view view;
2439 int ret;
2440
2441 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2442
2443 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2444 WARN_ONCE(ret, "Couldn't get view from plane state!");
2445
2446 i915_gem_object_unpin_fence(obj);
2447 i915_gem_object_unpin_from_display_plane(obj, &view);
2448 }
2449
2450 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2451 * is assumed to be a power-of-two. */
2452 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2453 int *x, int *y,
2454 unsigned int tiling_mode,
2455 unsigned int cpp,
2456 unsigned int pitch)
2457 {
2458 if (tiling_mode != I915_TILING_NONE) {
2459 unsigned int tile_rows, tiles;
2460
2461 tile_rows = *y / 8;
2462 *y %= 8;
2463
2464 tiles = *x / (512/cpp);
2465 *x %= 512/cpp;
2466
2467 return tile_rows * pitch * 8 + tiles * 4096;
2468 } else {
2469 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2470 unsigned int offset;
2471
2472 offset = *y * pitch + *x * cpp;
2473 *y = (offset & alignment) / pitch;
2474 *x = ((offset & alignment) - *y * pitch) / cpp;
2475 return offset & ~alignment;
2476 }
2477 }
2478
2479 static int i9xx_format_to_fourcc(int format)
2480 {
2481 switch (format) {
2482 case DISPPLANE_8BPP:
2483 return DRM_FORMAT_C8;
2484 case DISPPLANE_BGRX555:
2485 return DRM_FORMAT_XRGB1555;
2486 case DISPPLANE_BGRX565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case DISPPLANE_BGRX888:
2490 return DRM_FORMAT_XRGB8888;
2491 case DISPPLANE_RGBX888:
2492 return DRM_FORMAT_XBGR8888;
2493 case DISPPLANE_BGRX101010:
2494 return DRM_FORMAT_XRGB2101010;
2495 case DISPPLANE_RGBX101010:
2496 return DRM_FORMAT_XBGR2101010;
2497 }
2498 }
2499
2500 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2501 {
2502 switch (format) {
2503 case PLANE_CTL_FORMAT_RGB_565:
2504 return DRM_FORMAT_RGB565;
2505 default:
2506 case PLANE_CTL_FORMAT_XRGB_8888:
2507 if (rgb_order) {
2508 if (alpha)
2509 return DRM_FORMAT_ABGR8888;
2510 else
2511 return DRM_FORMAT_XBGR8888;
2512 } else {
2513 if (alpha)
2514 return DRM_FORMAT_ARGB8888;
2515 else
2516 return DRM_FORMAT_XRGB8888;
2517 }
2518 case PLANE_CTL_FORMAT_XRGB_2101010:
2519 if (rgb_order)
2520 return DRM_FORMAT_XBGR2101010;
2521 else
2522 return DRM_FORMAT_XRGB2101010;
2523 }
2524 }
2525
2526 static bool
2527 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2528 struct intel_initial_plane_config *plane_config)
2529 {
2530 struct drm_device *dev = crtc->base.dev;
2531 struct drm_i915_gem_object *obj = NULL;
2532 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2533 struct drm_framebuffer *fb = &plane_config->fb->base;
2534 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2535 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2536 PAGE_SIZE);
2537
2538 size_aligned -= base_aligned;
2539
2540 if (plane_config->size == 0)
2541 return false;
2542
2543 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2544 base_aligned,
2545 base_aligned,
2546 size_aligned);
2547 if (!obj)
2548 return false;
2549
2550 obj->tiling_mode = plane_config->tiling;
2551 if (obj->tiling_mode == I915_TILING_X)
2552 obj->stride = fb->pitches[0];
2553
2554 mode_cmd.pixel_format = fb->pixel_format;
2555 mode_cmd.width = fb->width;
2556 mode_cmd.height = fb->height;
2557 mode_cmd.pitches[0] = fb->pitches[0];
2558 mode_cmd.modifier[0] = fb->modifier[0];
2559 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2560
2561 mutex_lock(&dev->struct_mutex);
2562 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2563 &mode_cmd, obj)) {
2564 DRM_DEBUG_KMS("intel fb init failed\n");
2565 goto out_unref_obj;
2566 }
2567 mutex_unlock(&dev->struct_mutex);
2568
2569 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2570 return true;
2571
2572 out_unref_obj:
2573 drm_gem_object_unreference(&obj->base);
2574 mutex_unlock(&dev->struct_mutex);
2575 return false;
2576 }
2577
2578 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2579 static void
2580 update_state_fb(struct drm_plane *plane)
2581 {
2582 if (plane->fb == plane->state->fb)
2583 return;
2584
2585 if (plane->state->fb)
2586 drm_framebuffer_unreference(plane->state->fb);
2587 plane->state->fb = plane->fb;
2588 if (plane->state->fb)
2589 drm_framebuffer_reference(plane->state->fb);
2590 }
2591
2592 static void
2593 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2594 struct intel_initial_plane_config *plane_config)
2595 {
2596 struct drm_device *dev = intel_crtc->base.dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct drm_crtc *c;
2599 struct intel_crtc *i;
2600 struct drm_i915_gem_object *obj;
2601 struct drm_plane *primary = intel_crtc->base.primary;
2602 struct drm_framebuffer *fb;
2603
2604 if (!plane_config->fb)
2605 return;
2606
2607 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2608 fb = &plane_config->fb->base;
2609 goto valid_fb;
2610 }
2611
2612 kfree(plane_config->fb);
2613
2614 /*
2615 * Failed to alloc the obj, check to see if we should share
2616 * an fb with another CRTC instead
2617 */
2618 for_each_crtc(dev, c) {
2619 i = to_intel_crtc(c);
2620
2621 if (c == &intel_crtc->base)
2622 continue;
2623
2624 if (!i->active)
2625 continue;
2626
2627 fb = c->primary->fb;
2628 if (!fb)
2629 continue;
2630
2631 obj = intel_fb_obj(fb);
2632 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2633 drm_framebuffer_reference(fb);
2634 goto valid_fb;
2635 }
2636 }
2637
2638 return;
2639
2640 valid_fb:
2641 obj = intel_fb_obj(fb);
2642 if (obj->tiling_mode != I915_TILING_NONE)
2643 dev_priv->preserve_bios_swizzle = true;
2644
2645 primary->fb = fb;
2646 primary->crtc = primary->state->crtc = &intel_crtc->base;
2647 update_state_fb(primary);
2648 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2649 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2650 }
2651
2652 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2653 struct drm_framebuffer *fb,
2654 int x, int y)
2655 {
2656 struct drm_device *dev = crtc->dev;
2657 struct drm_i915_private *dev_priv = dev->dev_private;
2658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2659 struct drm_plane *primary = crtc->primary;
2660 bool visible = to_intel_plane_state(primary->state)->visible;
2661 struct drm_i915_gem_object *obj;
2662 int plane = intel_crtc->plane;
2663 unsigned long linear_offset;
2664 u32 dspcntr;
2665 u32 reg = DSPCNTR(plane);
2666 int pixel_size;
2667
2668 if (!visible || !fb) {
2669 I915_WRITE(reg, 0);
2670 if (INTEL_INFO(dev)->gen >= 4)
2671 I915_WRITE(DSPSURF(plane), 0);
2672 else
2673 I915_WRITE(DSPADDR(plane), 0);
2674 POSTING_READ(reg);
2675 return;
2676 }
2677
2678 obj = intel_fb_obj(fb);
2679 if (WARN_ON(obj == NULL))
2680 return;
2681
2682 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2683
2684 dspcntr = DISPPLANE_GAMMA_ENABLE;
2685
2686 dspcntr |= DISPLAY_PLANE_ENABLE;
2687
2688 if (INTEL_INFO(dev)->gen < 4) {
2689 if (intel_crtc->pipe == PIPE_B)
2690 dspcntr |= DISPPLANE_SEL_PIPE_B;
2691
2692 /* pipesrc and dspsize control the size that is scaled from,
2693 * which should always be the user's requested size.
2694 */
2695 I915_WRITE(DSPSIZE(plane),
2696 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2697 (intel_crtc->config->pipe_src_w - 1));
2698 I915_WRITE(DSPPOS(plane), 0);
2699 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2700 I915_WRITE(PRIMSIZE(plane),
2701 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2702 (intel_crtc->config->pipe_src_w - 1));
2703 I915_WRITE(PRIMPOS(plane), 0);
2704 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2705 }
2706
2707 switch (fb->pixel_format) {
2708 case DRM_FORMAT_C8:
2709 dspcntr |= DISPPLANE_8BPP;
2710 break;
2711 case DRM_FORMAT_XRGB1555:
2712 dspcntr |= DISPPLANE_BGRX555;
2713 break;
2714 case DRM_FORMAT_RGB565:
2715 dspcntr |= DISPPLANE_BGRX565;
2716 break;
2717 case DRM_FORMAT_XRGB8888:
2718 dspcntr |= DISPPLANE_BGRX888;
2719 break;
2720 case DRM_FORMAT_XBGR8888:
2721 dspcntr |= DISPPLANE_RGBX888;
2722 break;
2723 case DRM_FORMAT_XRGB2101010:
2724 dspcntr |= DISPPLANE_BGRX101010;
2725 break;
2726 case DRM_FORMAT_XBGR2101010:
2727 dspcntr |= DISPPLANE_RGBX101010;
2728 break;
2729 default:
2730 BUG();
2731 }
2732
2733 if (INTEL_INFO(dev)->gen >= 4 &&
2734 obj->tiling_mode != I915_TILING_NONE)
2735 dspcntr |= DISPPLANE_TILED;
2736
2737 if (IS_G4X(dev))
2738 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2739
2740 linear_offset = y * fb->pitches[0] + x * pixel_size;
2741
2742 if (INTEL_INFO(dev)->gen >= 4) {
2743 intel_crtc->dspaddr_offset =
2744 intel_gen4_compute_page_offset(dev_priv,
2745 &x, &y, obj->tiling_mode,
2746 pixel_size,
2747 fb->pitches[0]);
2748 linear_offset -= intel_crtc->dspaddr_offset;
2749 } else {
2750 intel_crtc->dspaddr_offset = linear_offset;
2751 }
2752
2753 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2754 dspcntr |= DISPPLANE_ROTATE_180;
2755
2756 x += (intel_crtc->config->pipe_src_w - 1);
2757 y += (intel_crtc->config->pipe_src_h - 1);
2758
2759 /* Finding the last pixel of the last line of the display
2760 data and adding to linear_offset*/
2761 linear_offset +=
2762 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2763 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2764 }
2765
2766 I915_WRITE(reg, dspcntr);
2767
2768 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2769 if (INTEL_INFO(dev)->gen >= 4) {
2770 I915_WRITE(DSPSURF(plane),
2771 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2772 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2773 I915_WRITE(DSPLINOFF(plane), linear_offset);
2774 } else
2775 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2776 POSTING_READ(reg);
2777 }
2778
2779 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2780 struct drm_framebuffer *fb,
2781 int x, int y)
2782 {
2783 struct drm_device *dev = crtc->dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2786 struct drm_plane *primary = crtc->primary;
2787 bool visible = to_intel_plane_state(primary->state)->visible;
2788 struct drm_i915_gem_object *obj;
2789 int plane = intel_crtc->plane;
2790 unsigned long linear_offset;
2791 u32 dspcntr;
2792 u32 reg = DSPCNTR(plane);
2793 int pixel_size;
2794
2795 if (!visible || !fb) {
2796 I915_WRITE(reg, 0);
2797 I915_WRITE(DSPSURF(plane), 0);
2798 POSTING_READ(reg);
2799 return;
2800 }
2801
2802 obj = intel_fb_obj(fb);
2803 if (WARN_ON(obj == NULL))
2804 return;
2805
2806 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2807
2808 dspcntr = DISPPLANE_GAMMA_ENABLE;
2809
2810 dspcntr |= DISPLAY_PLANE_ENABLE;
2811
2812 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2813 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2814
2815 switch (fb->pixel_format) {
2816 case DRM_FORMAT_C8:
2817 dspcntr |= DISPPLANE_8BPP;
2818 break;
2819 case DRM_FORMAT_RGB565:
2820 dspcntr |= DISPPLANE_BGRX565;
2821 break;
2822 case DRM_FORMAT_XRGB8888:
2823 dspcntr |= DISPPLANE_BGRX888;
2824 break;
2825 case DRM_FORMAT_XBGR8888:
2826 dspcntr |= DISPPLANE_RGBX888;
2827 break;
2828 case DRM_FORMAT_XRGB2101010:
2829 dspcntr |= DISPPLANE_BGRX101010;
2830 break;
2831 case DRM_FORMAT_XBGR2101010:
2832 dspcntr |= DISPPLANE_RGBX101010;
2833 break;
2834 default:
2835 BUG();
2836 }
2837
2838 if (obj->tiling_mode != I915_TILING_NONE)
2839 dspcntr |= DISPPLANE_TILED;
2840
2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2842 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2843
2844 linear_offset = y * fb->pitches[0] + x * pixel_size;
2845 intel_crtc->dspaddr_offset =
2846 intel_gen4_compute_page_offset(dev_priv,
2847 &x, &y, obj->tiling_mode,
2848 pixel_size,
2849 fb->pitches[0]);
2850 linear_offset -= intel_crtc->dspaddr_offset;
2851 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2852 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2855 x += (intel_crtc->config->pipe_src_w - 1);
2856 y += (intel_crtc->config->pipe_src_h - 1);
2857
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2860 linear_offset +=
2861 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2863 }
2864 }
2865
2866 I915_WRITE(reg, dspcntr);
2867
2868 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2869 I915_WRITE(DSPSURF(plane),
2870 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2871 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2872 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873 } else {
2874 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876 }
2877 POSTING_READ(reg);
2878 }
2879
2880 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2881 uint32_t pixel_format)
2882 {
2883 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2884
2885 /*
2886 * The stride is either expressed as a multiple of 64 bytes
2887 * chunks for linear buffers or in number of tiles for tiled
2888 * buffers.
2889 */
2890 switch (fb_modifier) {
2891 case DRM_FORMAT_MOD_NONE:
2892 return 64;
2893 case I915_FORMAT_MOD_X_TILED:
2894 if (INTEL_INFO(dev)->gen == 2)
2895 return 128;
2896 return 512;
2897 case I915_FORMAT_MOD_Y_TILED:
2898 /* No need to check for old gens and Y tiling since this is
2899 * about the display engine and those will be blocked before
2900 * we get here.
2901 */
2902 return 128;
2903 case I915_FORMAT_MOD_Yf_TILED:
2904 if (bits_per_pixel == 8)
2905 return 64;
2906 else
2907 return 128;
2908 default:
2909 MISSING_CASE(fb_modifier);
2910 return 64;
2911 }
2912 }
2913
2914 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2915 struct drm_i915_gem_object *obj)
2916 {
2917 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2918
2919 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2920 view = &i915_ggtt_view_rotated;
2921
2922 return i915_gem_obj_ggtt_offset_view(obj, view);
2923 }
2924
2925 /*
2926 * This function detaches (aka. unbinds) unused scalers in hardware
2927 */
2928 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2929 {
2930 struct drm_device *dev;
2931 struct drm_i915_private *dev_priv;
2932 struct intel_crtc_scaler_state *scaler_state;
2933 int i;
2934
2935 if (!intel_crtc || !intel_crtc->config)
2936 return;
2937
2938 dev = intel_crtc->base.dev;
2939 dev_priv = dev->dev_private;
2940 scaler_state = &intel_crtc->config->scaler_state;
2941
2942 /* loop through and disable scalers that aren't in use */
2943 for (i = 0; i < intel_crtc->num_scalers; i++) {
2944 if (!scaler_state->scalers[i].in_use) {
2945 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2946 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2947 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2948 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2949 intel_crtc->base.base.id, intel_crtc->pipe, i);
2950 }
2951 }
2952 }
2953
2954 u32 skl_plane_ctl_format(uint32_t pixel_format)
2955 {
2956 switch (pixel_format) {
2957 case DRM_FORMAT_C8:
2958 return PLANE_CTL_FORMAT_INDEXED;
2959 case DRM_FORMAT_RGB565:
2960 return PLANE_CTL_FORMAT_RGB_565;
2961 case DRM_FORMAT_XBGR8888:
2962 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2963 case DRM_FORMAT_XRGB8888:
2964 return PLANE_CTL_FORMAT_XRGB_8888;
2965 /*
2966 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2967 * to be already pre-multiplied. We need to add a knob (or a different
2968 * DRM_FORMAT) for user-space to configure that.
2969 */
2970 case DRM_FORMAT_ABGR8888:
2971 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2972 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2973 case DRM_FORMAT_ARGB8888:
2974 return PLANE_CTL_FORMAT_XRGB_8888 |
2975 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2976 case DRM_FORMAT_XRGB2101010:
2977 return PLANE_CTL_FORMAT_XRGB_2101010;
2978 case DRM_FORMAT_XBGR2101010:
2979 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2980 case DRM_FORMAT_YUYV:
2981 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2982 case DRM_FORMAT_YVYU:
2983 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2984 case DRM_FORMAT_UYVY:
2985 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2986 case DRM_FORMAT_VYUY:
2987 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2988 default:
2989 MISSING_CASE(pixel_format);
2990 }
2991
2992 return 0;
2993 }
2994
2995 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2996 {
2997 switch (fb_modifier) {
2998 case DRM_FORMAT_MOD_NONE:
2999 break;
3000 case I915_FORMAT_MOD_X_TILED:
3001 return PLANE_CTL_TILED_X;
3002 case I915_FORMAT_MOD_Y_TILED:
3003 return PLANE_CTL_TILED_Y;
3004 case I915_FORMAT_MOD_Yf_TILED:
3005 return PLANE_CTL_TILED_YF;
3006 default:
3007 MISSING_CASE(fb_modifier);
3008 }
3009
3010 return 0;
3011 }
3012
3013 u32 skl_plane_ctl_rotation(unsigned int rotation)
3014 {
3015 switch (rotation) {
3016 case BIT(DRM_ROTATE_0):
3017 break;
3018 /*
3019 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3020 * while i915 HW rotation is clockwise, thats why this swapping.
3021 */
3022 case BIT(DRM_ROTATE_90):
3023 return PLANE_CTL_ROTATE_270;
3024 case BIT(DRM_ROTATE_180):
3025 return PLANE_CTL_ROTATE_180;
3026 case BIT(DRM_ROTATE_270):
3027 return PLANE_CTL_ROTATE_90;
3028 default:
3029 MISSING_CASE(rotation);
3030 }
3031
3032 return 0;
3033 }
3034
3035 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3036 struct drm_framebuffer *fb,
3037 int x, int y)
3038 {
3039 struct drm_device *dev = crtc->dev;
3040 struct drm_i915_private *dev_priv = dev->dev_private;
3041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3042 struct drm_plane *plane = crtc->primary;
3043 bool visible = to_intel_plane_state(plane->state)->visible;
3044 struct drm_i915_gem_object *obj;
3045 int pipe = intel_crtc->pipe;
3046 u32 plane_ctl, stride_div, stride;
3047 u32 tile_height, plane_offset, plane_size;
3048 unsigned int rotation;
3049 int x_offset, y_offset;
3050 unsigned long surf_addr;
3051 struct intel_crtc_state *crtc_state = intel_crtc->config;
3052 struct intel_plane_state *plane_state;
3053 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3054 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3055 int scaler_id = -1;
3056
3057 plane_state = to_intel_plane_state(plane->state);
3058
3059 if (!visible || !fb) {
3060 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3061 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3062 POSTING_READ(PLANE_CTL(pipe, 0));
3063 return;
3064 }
3065
3066 plane_ctl = PLANE_CTL_ENABLE |
3067 PLANE_CTL_PIPE_GAMMA_ENABLE |
3068 PLANE_CTL_PIPE_CSC_ENABLE;
3069
3070 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3071 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3072 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3073
3074 rotation = plane->state->rotation;
3075 plane_ctl |= skl_plane_ctl_rotation(rotation);
3076
3077 obj = intel_fb_obj(fb);
3078 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3079 fb->pixel_format);
3080 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3081
3082 /*
3083 * FIXME: intel_plane_state->src, dst aren't set when transitional
3084 * update_plane helpers are called from legacy paths.
3085 * Once full atomic crtc is available, below check can be avoided.
3086 */
3087 if (drm_rect_width(&plane_state->src)) {
3088 scaler_id = plane_state->scaler_id;
3089 src_x = plane_state->src.x1 >> 16;
3090 src_y = plane_state->src.y1 >> 16;
3091 src_w = drm_rect_width(&plane_state->src) >> 16;
3092 src_h = drm_rect_height(&plane_state->src) >> 16;
3093 dst_x = plane_state->dst.x1;
3094 dst_y = plane_state->dst.y1;
3095 dst_w = drm_rect_width(&plane_state->dst);
3096 dst_h = drm_rect_height(&plane_state->dst);
3097
3098 WARN_ON(x != src_x || y != src_y);
3099 } else {
3100 src_w = intel_crtc->config->pipe_src_w;
3101 src_h = intel_crtc->config->pipe_src_h;
3102 }
3103
3104 if (intel_rotation_90_or_270(rotation)) {
3105 /* stride = Surface height in tiles */
3106 tile_height = intel_tile_height(dev, fb->pixel_format,
3107 fb->modifier[0]);
3108 stride = DIV_ROUND_UP(fb->height, tile_height);
3109 x_offset = stride * tile_height - y - src_h;
3110 y_offset = x;
3111 plane_size = (src_w - 1) << 16 | (src_h - 1);
3112 } else {
3113 stride = fb->pitches[0] / stride_div;
3114 x_offset = x;
3115 y_offset = y;
3116 plane_size = (src_h - 1) << 16 | (src_w - 1);
3117 }
3118 plane_offset = y_offset << 16 | x_offset;
3119
3120 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3121 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3122 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3123 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3124
3125 if (scaler_id >= 0) {
3126 uint32_t ps_ctrl = 0;
3127
3128 WARN_ON(!dst_w || !dst_h);
3129 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3130 crtc_state->scaler_state.scalers[scaler_id].mode;
3131 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3132 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3133 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3134 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3135 I915_WRITE(PLANE_POS(pipe, 0), 0);
3136 } else {
3137 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3138 }
3139
3140 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3141
3142 POSTING_READ(PLANE_SURF(pipe, 0));
3143 }
3144
3145 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3146 static int
3147 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3148 int x, int y, enum mode_set_atomic state)
3149 {
3150 struct drm_device *dev = crtc->dev;
3151 struct drm_i915_private *dev_priv = dev->dev_private;
3152
3153 if (dev_priv->display.disable_fbc)
3154 dev_priv->display.disable_fbc(dev);
3155
3156 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3157
3158 return 0;
3159 }
3160
3161 static void intel_complete_page_flips(struct drm_device *dev)
3162 {
3163 struct drm_crtc *crtc;
3164
3165 for_each_crtc(dev, crtc) {
3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167 enum plane plane = intel_crtc->plane;
3168
3169 intel_prepare_page_flip(dev, plane);
3170 intel_finish_page_flip_plane(dev, plane);
3171 }
3172 }
3173
3174 static void intel_update_primary_planes(struct drm_device *dev)
3175 {
3176 struct drm_i915_private *dev_priv = dev->dev_private;
3177 struct drm_crtc *crtc;
3178
3179 for_each_crtc(dev, crtc) {
3180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3181
3182 drm_modeset_lock(&crtc->mutex, NULL);
3183 /*
3184 * FIXME: Once we have proper support for primary planes (and
3185 * disabling them without disabling the entire crtc) allow again
3186 * a NULL crtc->primary->fb.
3187 */
3188 if (intel_crtc->active && crtc->primary->fb)
3189 dev_priv->display.update_primary_plane(crtc,
3190 crtc->primary->fb,
3191 crtc->x,
3192 crtc->y);
3193 drm_modeset_unlock(&crtc->mutex);
3194 }
3195 }
3196
3197 void intel_prepare_reset(struct drm_device *dev)
3198 {
3199 /* no reset support for gen2 */
3200 if (IS_GEN2(dev))
3201 return;
3202
3203 /* reset doesn't touch the display */
3204 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3205 return;
3206
3207 drm_modeset_lock_all(dev);
3208 /*
3209 * Disabling the crtcs gracefully seems nicer. Also the
3210 * g33 docs say we should at least disable all the planes.
3211 */
3212 intel_display_suspend(dev);
3213 }
3214
3215 void intel_finish_reset(struct drm_device *dev)
3216 {
3217 struct drm_i915_private *dev_priv = to_i915(dev);
3218
3219 /*
3220 * Flips in the rings will be nuked by the reset,
3221 * so complete all pending flips so that user space
3222 * will get its events and not get stuck.
3223 */
3224 intel_complete_page_flips(dev);
3225
3226 /* no reset support for gen2 */
3227 if (IS_GEN2(dev))
3228 return;
3229
3230 /* reset doesn't touch the display */
3231 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3232 /*
3233 * Flips in the rings have been nuked by the reset,
3234 * so update the base address of all primary
3235 * planes to the the last fb to make sure we're
3236 * showing the correct fb after a reset.
3237 */
3238 intel_update_primary_planes(dev);
3239 return;
3240 }
3241
3242 /*
3243 * The display has been reset as well,
3244 * so need a full re-initialization.
3245 */
3246 intel_runtime_pm_disable_interrupts(dev_priv);
3247 intel_runtime_pm_enable_interrupts(dev_priv);
3248
3249 intel_modeset_init_hw(dev);
3250
3251 spin_lock_irq(&dev_priv->irq_lock);
3252 if (dev_priv->display.hpd_irq_setup)
3253 dev_priv->display.hpd_irq_setup(dev);
3254 spin_unlock_irq(&dev_priv->irq_lock);
3255
3256 intel_modeset_setup_hw_state(dev, true);
3257
3258 intel_hpd_init(dev_priv);
3259
3260 drm_modeset_unlock_all(dev);
3261 }
3262
3263 static void
3264 intel_finish_fb(struct drm_framebuffer *old_fb)
3265 {
3266 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3267 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3268 bool was_interruptible = dev_priv->mm.interruptible;
3269 int ret;
3270
3271 /* Big Hammer, we also need to ensure that any pending
3272 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3273 * current scanout is retired before unpinning the old
3274 * framebuffer. Note that we rely on userspace rendering
3275 * into the buffer attached to the pipe they are waiting
3276 * on. If not, userspace generates a GPU hang with IPEHR
3277 * point to the MI_WAIT_FOR_EVENT.
3278 *
3279 * This should only fail upon a hung GPU, in which case we
3280 * can safely continue.
3281 */
3282 dev_priv->mm.interruptible = false;
3283 ret = i915_gem_object_wait_rendering(obj, true);
3284 dev_priv->mm.interruptible = was_interruptible;
3285
3286 WARN_ON(ret);
3287 }
3288
3289 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3290 {
3291 struct drm_device *dev = crtc->dev;
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3294 bool pending;
3295
3296 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3297 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3298 return false;
3299
3300 spin_lock_irq(&dev->event_lock);
3301 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3302 spin_unlock_irq(&dev->event_lock);
3303
3304 return pending;
3305 }
3306
3307 static void intel_update_pipe_size(struct intel_crtc *crtc)
3308 {
3309 struct drm_device *dev = crtc->base.dev;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311 const struct drm_display_mode *adjusted_mode;
3312
3313 if (!i915.fastboot)
3314 return;
3315
3316 /*
3317 * Update pipe size and adjust fitter if needed: the reason for this is
3318 * that in compute_mode_changes we check the native mode (not the pfit
3319 * mode) to see if we can flip rather than do a full mode set. In the
3320 * fastboot case, we'll flip, but if we don't update the pipesrc and
3321 * pfit state, we'll end up with a big fb scanned out into the wrong
3322 * sized surface.
3323 *
3324 * To fix this properly, we need to hoist the checks up into
3325 * compute_mode_changes (or above), check the actual pfit state and
3326 * whether the platform allows pfit disable with pipe active, and only
3327 * then update the pipesrc and pfit state, even on the flip path.
3328 */
3329
3330 adjusted_mode = &crtc->config->base.adjusted_mode;
3331
3332 I915_WRITE(PIPESRC(crtc->pipe),
3333 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3334 (adjusted_mode->crtc_vdisplay - 1));
3335 if (!crtc->config->pch_pfit.enabled &&
3336 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3337 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3338 I915_WRITE(PF_CTL(crtc->pipe), 0);
3339 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3340 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3341 }
3342 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3343 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3344 }
3345
3346 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3347 {
3348 struct drm_device *dev = crtc->dev;
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351 int pipe = intel_crtc->pipe;
3352 u32 reg, temp;
3353
3354 /* enable normal train */
3355 reg = FDI_TX_CTL(pipe);
3356 temp = I915_READ(reg);
3357 if (IS_IVYBRIDGE(dev)) {
3358 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3359 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3360 } else {
3361 temp &= ~FDI_LINK_TRAIN_NONE;
3362 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3363 }
3364 I915_WRITE(reg, temp);
3365
3366 reg = FDI_RX_CTL(pipe);
3367 temp = I915_READ(reg);
3368 if (HAS_PCH_CPT(dev)) {
3369 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3370 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3371 } else {
3372 temp &= ~FDI_LINK_TRAIN_NONE;
3373 temp |= FDI_LINK_TRAIN_NONE;
3374 }
3375 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3376
3377 /* wait one idle pattern time */
3378 POSTING_READ(reg);
3379 udelay(1000);
3380
3381 /* IVB wants error correction enabled */
3382 if (IS_IVYBRIDGE(dev))
3383 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3384 FDI_FE_ERRC_ENABLE);
3385 }
3386
3387 /* The FDI link training functions for ILK/Ibexpeak. */
3388 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3389 {
3390 struct drm_device *dev = crtc->dev;
3391 struct drm_i915_private *dev_priv = dev->dev_private;
3392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3393 int pipe = intel_crtc->pipe;
3394 u32 reg, temp, tries;
3395
3396 /* FDI needs bits from pipe first */
3397 assert_pipe_enabled(dev_priv, pipe);
3398
3399 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3400 for train result */
3401 reg = FDI_RX_IMR(pipe);
3402 temp = I915_READ(reg);
3403 temp &= ~FDI_RX_SYMBOL_LOCK;
3404 temp &= ~FDI_RX_BIT_LOCK;
3405 I915_WRITE(reg, temp);
3406 I915_READ(reg);
3407 udelay(150);
3408
3409 /* enable CPU FDI TX and PCH FDI RX */
3410 reg = FDI_TX_CTL(pipe);
3411 temp = I915_READ(reg);
3412 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3413 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3414 temp &= ~FDI_LINK_TRAIN_NONE;
3415 temp |= FDI_LINK_TRAIN_PATTERN_1;
3416 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3417
3418 reg = FDI_RX_CTL(pipe);
3419 temp = I915_READ(reg);
3420 temp &= ~FDI_LINK_TRAIN_NONE;
3421 temp |= FDI_LINK_TRAIN_PATTERN_1;
3422 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3423
3424 POSTING_READ(reg);
3425 udelay(150);
3426
3427 /* Ironlake workaround, enable clock pointer after FDI enable*/
3428 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3429 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3430 FDI_RX_PHASE_SYNC_POINTER_EN);
3431
3432 reg = FDI_RX_IIR(pipe);
3433 for (tries = 0; tries < 5; tries++) {
3434 temp = I915_READ(reg);
3435 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3436
3437 if ((temp & FDI_RX_BIT_LOCK)) {
3438 DRM_DEBUG_KMS("FDI train 1 done.\n");
3439 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3440 break;
3441 }
3442 }
3443 if (tries == 5)
3444 DRM_ERROR("FDI train 1 fail!\n");
3445
3446 /* Train 2 */
3447 reg = FDI_TX_CTL(pipe);
3448 temp = I915_READ(reg);
3449 temp &= ~FDI_LINK_TRAIN_NONE;
3450 temp |= FDI_LINK_TRAIN_PATTERN_2;
3451 I915_WRITE(reg, temp);
3452
3453 reg = FDI_RX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_2;
3457 I915_WRITE(reg, temp);
3458
3459 POSTING_READ(reg);
3460 udelay(150);
3461
3462 reg = FDI_RX_IIR(pipe);
3463 for (tries = 0; tries < 5; tries++) {
3464 temp = I915_READ(reg);
3465 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3466
3467 if (temp & FDI_RX_SYMBOL_LOCK) {
3468 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3469 DRM_DEBUG_KMS("FDI train 2 done.\n");
3470 break;
3471 }
3472 }
3473 if (tries == 5)
3474 DRM_ERROR("FDI train 2 fail!\n");
3475
3476 DRM_DEBUG_KMS("FDI train done\n");
3477
3478 }
3479
3480 static const int snb_b_fdi_train_param[] = {
3481 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3482 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3483 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3484 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3485 };
3486
3487 /* The FDI link training functions for SNB/Cougarpoint. */
3488 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3489 {
3490 struct drm_device *dev = crtc->dev;
3491 struct drm_i915_private *dev_priv = dev->dev_private;
3492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3493 int pipe = intel_crtc->pipe;
3494 u32 reg, temp, i, retry;
3495
3496 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3497 for train result */
3498 reg = FDI_RX_IMR(pipe);
3499 temp = I915_READ(reg);
3500 temp &= ~FDI_RX_SYMBOL_LOCK;
3501 temp &= ~FDI_RX_BIT_LOCK;
3502 I915_WRITE(reg, temp);
3503
3504 POSTING_READ(reg);
3505 udelay(150);
3506
3507 /* enable CPU FDI TX and PCH FDI RX */
3508 reg = FDI_TX_CTL(pipe);
3509 temp = I915_READ(reg);
3510 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3511 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3512 temp &= ~FDI_LINK_TRAIN_NONE;
3513 temp |= FDI_LINK_TRAIN_PATTERN_1;
3514 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3515 /* SNB-B */
3516 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3517 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3518
3519 I915_WRITE(FDI_RX_MISC(pipe),
3520 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3521
3522 reg = FDI_RX_CTL(pipe);
3523 temp = I915_READ(reg);
3524 if (HAS_PCH_CPT(dev)) {
3525 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3526 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3527 } else {
3528 temp &= ~FDI_LINK_TRAIN_NONE;
3529 temp |= FDI_LINK_TRAIN_PATTERN_1;
3530 }
3531 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3532
3533 POSTING_READ(reg);
3534 udelay(150);
3535
3536 for (i = 0; i < 4; i++) {
3537 reg = FDI_TX_CTL(pipe);
3538 temp = I915_READ(reg);
3539 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3540 temp |= snb_b_fdi_train_param[i];
3541 I915_WRITE(reg, temp);
3542
3543 POSTING_READ(reg);
3544 udelay(500);
3545
3546 for (retry = 0; retry < 5; retry++) {
3547 reg = FDI_RX_IIR(pipe);
3548 temp = I915_READ(reg);
3549 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3550 if (temp & FDI_RX_BIT_LOCK) {
3551 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3552 DRM_DEBUG_KMS("FDI train 1 done.\n");
3553 break;
3554 }
3555 udelay(50);
3556 }
3557 if (retry < 5)
3558 break;
3559 }
3560 if (i == 4)
3561 DRM_ERROR("FDI train 1 fail!\n");
3562
3563 /* Train 2 */
3564 reg = FDI_TX_CTL(pipe);
3565 temp = I915_READ(reg);
3566 temp &= ~FDI_LINK_TRAIN_NONE;
3567 temp |= FDI_LINK_TRAIN_PATTERN_2;
3568 if (IS_GEN6(dev)) {
3569 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3570 /* SNB-B */
3571 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3572 }
3573 I915_WRITE(reg, temp);
3574
3575 reg = FDI_RX_CTL(pipe);
3576 temp = I915_READ(reg);
3577 if (HAS_PCH_CPT(dev)) {
3578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3579 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3580 } else {
3581 temp &= ~FDI_LINK_TRAIN_NONE;
3582 temp |= FDI_LINK_TRAIN_PATTERN_2;
3583 }
3584 I915_WRITE(reg, temp);
3585
3586 POSTING_READ(reg);
3587 udelay(150);
3588
3589 for (i = 0; i < 4; i++) {
3590 reg = FDI_TX_CTL(pipe);
3591 temp = I915_READ(reg);
3592 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3593 temp |= snb_b_fdi_train_param[i];
3594 I915_WRITE(reg, temp);
3595
3596 POSTING_READ(reg);
3597 udelay(500);
3598
3599 for (retry = 0; retry < 5; retry++) {
3600 reg = FDI_RX_IIR(pipe);
3601 temp = I915_READ(reg);
3602 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603 if (temp & FDI_RX_SYMBOL_LOCK) {
3604 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3605 DRM_DEBUG_KMS("FDI train 2 done.\n");
3606 break;
3607 }
3608 udelay(50);
3609 }
3610 if (retry < 5)
3611 break;
3612 }
3613 if (i == 4)
3614 DRM_ERROR("FDI train 2 fail!\n");
3615
3616 DRM_DEBUG_KMS("FDI train done.\n");
3617 }
3618
3619 /* Manual link training for Ivy Bridge A0 parts */
3620 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3621 {
3622 struct drm_device *dev = crtc->dev;
3623 struct drm_i915_private *dev_priv = dev->dev_private;
3624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3625 int pipe = intel_crtc->pipe;
3626 u32 reg, temp, i, j;
3627
3628 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3629 for train result */
3630 reg = FDI_RX_IMR(pipe);
3631 temp = I915_READ(reg);
3632 temp &= ~FDI_RX_SYMBOL_LOCK;
3633 temp &= ~FDI_RX_BIT_LOCK;
3634 I915_WRITE(reg, temp);
3635
3636 POSTING_READ(reg);
3637 udelay(150);
3638
3639 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3640 I915_READ(FDI_RX_IIR(pipe)));
3641
3642 /* Try each vswing and preemphasis setting twice before moving on */
3643 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3644 /* disable first in case we need to retry */
3645 reg = FDI_TX_CTL(pipe);
3646 temp = I915_READ(reg);
3647 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3648 temp &= ~FDI_TX_ENABLE;
3649 I915_WRITE(reg, temp);
3650
3651 reg = FDI_RX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 temp &= ~FDI_LINK_TRAIN_AUTO;
3654 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3655 temp &= ~FDI_RX_ENABLE;
3656 I915_WRITE(reg, temp);
3657
3658 /* enable CPU FDI TX and PCH FDI RX */
3659 reg = FDI_TX_CTL(pipe);
3660 temp = I915_READ(reg);
3661 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3662 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3663 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3664 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3665 temp |= snb_b_fdi_train_param[j/2];
3666 temp |= FDI_COMPOSITE_SYNC;
3667 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3668
3669 I915_WRITE(FDI_RX_MISC(pipe),
3670 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3671
3672 reg = FDI_RX_CTL(pipe);
3673 temp = I915_READ(reg);
3674 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3675 temp |= FDI_COMPOSITE_SYNC;
3676 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3677
3678 POSTING_READ(reg);
3679 udelay(1); /* should be 0.5us */
3680
3681 for (i = 0; i < 4; i++) {
3682 reg = FDI_RX_IIR(pipe);
3683 temp = I915_READ(reg);
3684 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3685
3686 if (temp & FDI_RX_BIT_LOCK ||
3687 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3688 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3689 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3690 i);
3691 break;
3692 }
3693 udelay(1); /* should be 0.5us */
3694 }
3695 if (i == 4) {
3696 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3697 continue;
3698 }
3699
3700 /* Train 2 */
3701 reg = FDI_TX_CTL(pipe);
3702 temp = I915_READ(reg);
3703 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3704 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3705 I915_WRITE(reg, temp);
3706
3707 reg = FDI_RX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3710 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3711 I915_WRITE(reg, temp);
3712
3713 POSTING_READ(reg);
3714 udelay(2); /* should be 1.5us */
3715
3716 for (i = 0; i < 4; i++) {
3717 reg = FDI_RX_IIR(pipe);
3718 temp = I915_READ(reg);
3719 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3720
3721 if (temp & FDI_RX_SYMBOL_LOCK ||
3722 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3723 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3724 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3725 i);
3726 goto train_done;
3727 }
3728 udelay(2); /* should be 1.5us */
3729 }
3730 if (i == 4)
3731 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3732 }
3733
3734 train_done:
3735 DRM_DEBUG_KMS("FDI train done.\n");
3736 }
3737
3738 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3739 {
3740 struct drm_device *dev = intel_crtc->base.dev;
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 int pipe = intel_crtc->pipe;
3743 u32 reg, temp;
3744
3745
3746 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3747 reg = FDI_RX_CTL(pipe);
3748 temp = I915_READ(reg);
3749 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3750 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3751 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3752 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3753
3754 POSTING_READ(reg);
3755 udelay(200);
3756
3757 /* Switch from Rawclk to PCDclk */
3758 temp = I915_READ(reg);
3759 I915_WRITE(reg, temp | FDI_PCDCLK);
3760
3761 POSTING_READ(reg);
3762 udelay(200);
3763
3764 /* Enable CPU FDI TX PLL, always on for Ironlake */
3765 reg = FDI_TX_CTL(pipe);
3766 temp = I915_READ(reg);
3767 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3768 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3769
3770 POSTING_READ(reg);
3771 udelay(100);
3772 }
3773 }
3774
3775 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3776 {
3777 struct drm_device *dev = intel_crtc->base.dev;
3778 struct drm_i915_private *dev_priv = dev->dev_private;
3779 int pipe = intel_crtc->pipe;
3780 u32 reg, temp;
3781
3782 /* Switch from PCDclk to Rawclk */
3783 reg = FDI_RX_CTL(pipe);
3784 temp = I915_READ(reg);
3785 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3786
3787 /* Disable CPU FDI TX PLL */
3788 reg = FDI_TX_CTL(pipe);
3789 temp = I915_READ(reg);
3790 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3791
3792 POSTING_READ(reg);
3793 udelay(100);
3794
3795 reg = FDI_RX_CTL(pipe);
3796 temp = I915_READ(reg);
3797 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3798
3799 /* Wait for the clocks to turn off. */
3800 POSTING_READ(reg);
3801 udelay(100);
3802 }
3803
3804 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3805 {
3806 struct drm_device *dev = crtc->dev;
3807 struct drm_i915_private *dev_priv = dev->dev_private;
3808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3809 int pipe = intel_crtc->pipe;
3810 u32 reg, temp;
3811
3812 /* disable CPU FDI tx and PCH FDI rx */
3813 reg = FDI_TX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3816 POSTING_READ(reg);
3817
3818 reg = FDI_RX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 temp &= ~(0x7 << 16);
3821 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3822 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3823
3824 POSTING_READ(reg);
3825 udelay(100);
3826
3827 /* Ironlake workaround, disable clock pointer after downing FDI */
3828 if (HAS_PCH_IBX(dev))
3829 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3830
3831 /* still set train pattern 1 */
3832 reg = FDI_TX_CTL(pipe);
3833 temp = I915_READ(reg);
3834 temp &= ~FDI_LINK_TRAIN_NONE;
3835 temp |= FDI_LINK_TRAIN_PATTERN_1;
3836 I915_WRITE(reg, temp);
3837
3838 reg = FDI_RX_CTL(pipe);
3839 temp = I915_READ(reg);
3840 if (HAS_PCH_CPT(dev)) {
3841 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3842 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3843 } else {
3844 temp &= ~FDI_LINK_TRAIN_NONE;
3845 temp |= FDI_LINK_TRAIN_PATTERN_1;
3846 }
3847 /* BPC in FDI rx is consistent with that in PIPECONF */
3848 temp &= ~(0x07 << 16);
3849 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3850 I915_WRITE(reg, temp);
3851
3852 POSTING_READ(reg);
3853 udelay(100);
3854 }
3855
3856 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3857 {
3858 struct intel_crtc *crtc;
3859
3860 /* Note that we don't need to be called with mode_config.lock here
3861 * as our list of CRTC objects is static for the lifetime of the
3862 * device and so cannot disappear as we iterate. Similarly, we can
3863 * happily treat the predicates as racy, atomic checks as userspace
3864 * cannot claim and pin a new fb without at least acquring the
3865 * struct_mutex and so serialising with us.
3866 */
3867 for_each_intel_crtc(dev, crtc) {
3868 if (atomic_read(&crtc->unpin_work_count) == 0)
3869 continue;
3870
3871 if (crtc->unpin_work)
3872 intel_wait_for_vblank(dev, crtc->pipe);
3873
3874 return true;
3875 }
3876
3877 return false;
3878 }
3879
3880 static void page_flip_completed(struct intel_crtc *intel_crtc)
3881 {
3882 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3883 struct intel_unpin_work *work = intel_crtc->unpin_work;
3884
3885 /* ensure that the unpin work is consistent wrt ->pending. */
3886 smp_rmb();
3887 intel_crtc->unpin_work = NULL;
3888
3889 if (work->event)
3890 drm_send_vblank_event(intel_crtc->base.dev,
3891 intel_crtc->pipe,
3892 work->event);
3893
3894 drm_crtc_vblank_put(&intel_crtc->base);
3895
3896 wake_up_all(&dev_priv->pending_flip_queue);
3897 queue_work(dev_priv->wq, &work->work);
3898
3899 trace_i915_flip_complete(intel_crtc->plane,
3900 work->pending_flip_obj);
3901 }
3902
3903 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3904 {
3905 struct drm_device *dev = crtc->dev;
3906 struct drm_i915_private *dev_priv = dev->dev_private;
3907
3908 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3909 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3910 !intel_crtc_has_pending_flip(crtc),
3911 60*HZ) == 0)) {
3912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3913
3914 spin_lock_irq(&dev->event_lock);
3915 if (intel_crtc->unpin_work) {
3916 WARN_ONCE(1, "Removing stuck page flip\n");
3917 page_flip_completed(intel_crtc);
3918 }
3919 spin_unlock_irq(&dev->event_lock);
3920 }
3921
3922 if (crtc->primary->fb) {
3923 mutex_lock(&dev->struct_mutex);
3924 intel_finish_fb(crtc->primary->fb);
3925 mutex_unlock(&dev->struct_mutex);
3926 }
3927 }
3928
3929 /* Program iCLKIP clock to the desired frequency */
3930 static void lpt_program_iclkip(struct drm_crtc *crtc)
3931 {
3932 struct drm_device *dev = crtc->dev;
3933 struct drm_i915_private *dev_priv = dev->dev_private;
3934 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3935 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3936 u32 temp;
3937
3938 mutex_lock(&dev_priv->sb_lock);
3939
3940 /* It is necessary to ungate the pixclk gate prior to programming
3941 * the divisors, and gate it back when it is done.
3942 */
3943 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3944
3945 /* Disable SSCCTL */
3946 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3947 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3948 SBI_SSCCTL_DISABLE,
3949 SBI_ICLK);
3950
3951 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3952 if (clock == 20000) {
3953 auxdiv = 1;
3954 divsel = 0x41;
3955 phaseinc = 0x20;
3956 } else {
3957 /* The iCLK virtual clock root frequency is in MHz,
3958 * but the adjusted_mode->crtc_clock in in KHz. To get the
3959 * divisors, it is necessary to divide one by another, so we
3960 * convert the virtual clock precision to KHz here for higher
3961 * precision.
3962 */
3963 u32 iclk_virtual_root_freq = 172800 * 1000;
3964 u32 iclk_pi_range = 64;
3965 u32 desired_divisor, msb_divisor_value, pi_value;
3966
3967 desired_divisor = (iclk_virtual_root_freq / clock);
3968 msb_divisor_value = desired_divisor / iclk_pi_range;
3969 pi_value = desired_divisor % iclk_pi_range;
3970
3971 auxdiv = 0;
3972 divsel = msb_divisor_value - 2;
3973 phaseinc = pi_value;
3974 }
3975
3976 /* This should not happen with any sane values */
3977 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3978 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3979 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3980 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3981
3982 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3983 clock,
3984 auxdiv,
3985 divsel,
3986 phasedir,
3987 phaseinc);
3988
3989 /* Program SSCDIVINTPHASE6 */
3990 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3991 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3992 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3993 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3994 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3995 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3996 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3997 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3998
3999 /* Program SSCAUXDIV */
4000 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4001 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4002 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4003 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4004
4005 /* Enable modulator and associated divider */
4006 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4007 temp &= ~SBI_SSCCTL_DISABLE;
4008 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4009
4010 /* Wait for initialization time */
4011 udelay(24);
4012
4013 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4014
4015 mutex_unlock(&dev_priv->sb_lock);
4016 }
4017
4018 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4019 enum pipe pch_transcoder)
4020 {
4021 struct drm_device *dev = crtc->base.dev;
4022 struct drm_i915_private *dev_priv = dev->dev_private;
4023 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4024
4025 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4026 I915_READ(HTOTAL(cpu_transcoder)));
4027 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4028 I915_READ(HBLANK(cpu_transcoder)));
4029 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4030 I915_READ(HSYNC(cpu_transcoder)));
4031
4032 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4033 I915_READ(VTOTAL(cpu_transcoder)));
4034 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4035 I915_READ(VBLANK(cpu_transcoder)));
4036 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4037 I915_READ(VSYNC(cpu_transcoder)));
4038 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4039 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4040 }
4041
4042 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4043 {
4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 uint32_t temp;
4046
4047 temp = I915_READ(SOUTH_CHICKEN1);
4048 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4049 return;
4050
4051 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4052 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4053
4054 temp &= ~FDI_BC_BIFURCATION_SELECT;
4055 if (enable)
4056 temp |= FDI_BC_BIFURCATION_SELECT;
4057
4058 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4059 I915_WRITE(SOUTH_CHICKEN1, temp);
4060 POSTING_READ(SOUTH_CHICKEN1);
4061 }
4062
4063 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4064 {
4065 struct drm_device *dev = intel_crtc->base.dev;
4066
4067 switch (intel_crtc->pipe) {
4068 case PIPE_A:
4069 break;
4070 case PIPE_B:
4071 if (intel_crtc->config->fdi_lanes > 2)
4072 cpt_set_fdi_bc_bifurcation(dev, false);
4073 else
4074 cpt_set_fdi_bc_bifurcation(dev, true);
4075
4076 break;
4077 case PIPE_C:
4078 cpt_set_fdi_bc_bifurcation(dev, true);
4079
4080 break;
4081 default:
4082 BUG();
4083 }
4084 }
4085
4086 /*
4087 * Enable PCH resources required for PCH ports:
4088 * - PCH PLLs
4089 * - FDI training & RX/TX
4090 * - update transcoder timings
4091 * - DP transcoding bits
4092 * - transcoder
4093 */
4094 static void ironlake_pch_enable(struct drm_crtc *crtc)
4095 {
4096 struct drm_device *dev = crtc->dev;
4097 struct drm_i915_private *dev_priv = dev->dev_private;
4098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4099 int pipe = intel_crtc->pipe;
4100 u32 reg, temp;
4101
4102 assert_pch_transcoder_disabled(dev_priv, pipe);
4103
4104 if (IS_IVYBRIDGE(dev))
4105 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4106
4107 /* Write the TU size bits before fdi link training, so that error
4108 * detection works. */
4109 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4110 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4111
4112 /* For PCH output, training FDI link */
4113 dev_priv->display.fdi_link_train(crtc);
4114
4115 /* We need to program the right clock selection before writing the pixel
4116 * mutliplier into the DPLL. */
4117 if (HAS_PCH_CPT(dev)) {
4118 u32 sel;
4119
4120 temp = I915_READ(PCH_DPLL_SEL);
4121 temp |= TRANS_DPLL_ENABLE(pipe);
4122 sel = TRANS_DPLLB_SEL(pipe);
4123 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4124 temp |= sel;
4125 else
4126 temp &= ~sel;
4127 I915_WRITE(PCH_DPLL_SEL, temp);
4128 }
4129
4130 /* XXX: pch pll's can be enabled any time before we enable the PCH
4131 * transcoder, and we actually should do this to not upset any PCH
4132 * transcoder that already use the clock when we share it.
4133 *
4134 * Note that enable_shared_dpll tries to do the right thing, but
4135 * get_shared_dpll unconditionally resets the pll - we need that to have
4136 * the right LVDS enable sequence. */
4137 intel_enable_shared_dpll(intel_crtc);
4138
4139 /* set transcoder timing, panel must allow it */
4140 assert_panel_unlocked(dev_priv, pipe);
4141 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4142
4143 intel_fdi_normal_train(crtc);
4144
4145 /* For PCH DP, enable TRANS_DP_CTL */
4146 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4147 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4148 reg = TRANS_DP_CTL(pipe);
4149 temp = I915_READ(reg);
4150 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4151 TRANS_DP_SYNC_MASK |
4152 TRANS_DP_BPC_MASK);
4153 temp |= TRANS_DP_OUTPUT_ENABLE;
4154 temp |= bpc << 9; /* same format but at 11:9 */
4155
4156 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4157 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4158 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4159 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4160
4161 switch (intel_trans_dp_port_sel(crtc)) {
4162 case PCH_DP_B:
4163 temp |= TRANS_DP_PORT_SEL_B;
4164 break;
4165 case PCH_DP_C:
4166 temp |= TRANS_DP_PORT_SEL_C;
4167 break;
4168 case PCH_DP_D:
4169 temp |= TRANS_DP_PORT_SEL_D;
4170 break;
4171 default:
4172 BUG();
4173 }
4174
4175 I915_WRITE(reg, temp);
4176 }
4177
4178 ironlake_enable_pch_transcoder(dev_priv, pipe);
4179 }
4180
4181 static void lpt_pch_enable(struct drm_crtc *crtc)
4182 {
4183 struct drm_device *dev = crtc->dev;
4184 struct drm_i915_private *dev_priv = dev->dev_private;
4185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4186 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4187
4188 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4189
4190 lpt_program_iclkip(crtc);
4191
4192 /* Set transcoder timing. */
4193 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4194
4195 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4196 }
4197
4198 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4199 struct intel_crtc_state *crtc_state)
4200 {
4201 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4202 struct intel_shared_dpll *pll;
4203 struct intel_shared_dpll_config *shared_dpll;
4204 enum intel_dpll_id i;
4205
4206 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4207
4208 if (HAS_PCH_IBX(dev_priv->dev)) {
4209 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4210 i = (enum intel_dpll_id) crtc->pipe;
4211 pll = &dev_priv->shared_dplls[i];
4212
4213 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4214 crtc->base.base.id, pll->name);
4215
4216 WARN_ON(shared_dpll[i].crtc_mask);
4217
4218 goto found;
4219 }
4220
4221 if (IS_BROXTON(dev_priv->dev)) {
4222 /* PLL is attached to port in bxt */
4223 struct intel_encoder *encoder;
4224 struct intel_digital_port *intel_dig_port;
4225
4226 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4227 if (WARN_ON(!encoder))
4228 return NULL;
4229
4230 intel_dig_port = enc_to_dig_port(&encoder->base);
4231 /* 1:1 mapping between ports and PLLs */
4232 i = (enum intel_dpll_id)intel_dig_port->port;
4233 pll = &dev_priv->shared_dplls[i];
4234 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4235 crtc->base.base.id, pll->name);
4236 WARN_ON(shared_dpll[i].crtc_mask);
4237
4238 goto found;
4239 }
4240
4241 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4242 pll = &dev_priv->shared_dplls[i];
4243
4244 /* Only want to check enabled timings first */
4245 if (shared_dpll[i].crtc_mask == 0)
4246 continue;
4247
4248 if (memcmp(&crtc_state->dpll_hw_state,
4249 &shared_dpll[i].hw_state,
4250 sizeof(crtc_state->dpll_hw_state)) == 0) {
4251 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4252 crtc->base.base.id, pll->name,
4253 shared_dpll[i].crtc_mask,
4254 pll->active);
4255 goto found;
4256 }
4257 }
4258
4259 /* Ok no matching timings, maybe there's a free one? */
4260 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4261 pll = &dev_priv->shared_dplls[i];
4262 if (shared_dpll[i].crtc_mask == 0) {
4263 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4264 crtc->base.base.id, pll->name);
4265 goto found;
4266 }
4267 }
4268
4269 return NULL;
4270
4271 found:
4272 if (shared_dpll[i].crtc_mask == 0)
4273 shared_dpll[i].hw_state =
4274 crtc_state->dpll_hw_state;
4275
4276 crtc_state->shared_dpll = i;
4277 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4278 pipe_name(crtc->pipe));
4279
4280 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4281
4282 return pll;
4283 }
4284
4285 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4286 {
4287 struct drm_i915_private *dev_priv = to_i915(state->dev);
4288 struct intel_shared_dpll_config *shared_dpll;
4289 struct intel_shared_dpll *pll;
4290 enum intel_dpll_id i;
4291
4292 if (!to_intel_atomic_state(state)->dpll_set)
4293 return;
4294
4295 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4296 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4297 pll = &dev_priv->shared_dplls[i];
4298 pll->config = shared_dpll[i];
4299 }
4300 }
4301
4302 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4303 {
4304 struct drm_i915_private *dev_priv = dev->dev_private;
4305 int dslreg = PIPEDSL(pipe);
4306 u32 temp;
4307
4308 temp = I915_READ(dslreg);
4309 udelay(500);
4310 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4311 if (wait_for(I915_READ(dslreg) != temp, 5))
4312 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4313 }
4314 }
4315
4316 /**
4317 * skl_update_scaler_users - Stages update to crtc's scaler state
4318 * @intel_crtc: crtc
4319 * @crtc_state: crtc_state
4320 * @plane: plane (NULL indicates crtc is requesting update)
4321 * @plane_state: plane's state
4322 * @force_detach: request unconditional detachment of scaler
4323 *
4324 * This function updates scaler state for requested plane or crtc.
4325 * To request scaler usage update for a plane, caller shall pass plane pointer.
4326 * To request scaler usage update for crtc, caller shall pass plane pointer
4327 * as NULL.
4328 *
4329 * Return
4330 * 0 - scaler_usage updated successfully
4331 * error - requested scaling cannot be supported or other error condition
4332 */
4333 int
4334 skl_update_scaler_users(
4335 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4336 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4337 int force_detach)
4338 {
4339 int need_scaling;
4340 int idx;
4341 int src_w, src_h, dst_w, dst_h;
4342 int *scaler_id;
4343 struct drm_framebuffer *fb;
4344 struct intel_crtc_scaler_state *scaler_state;
4345 unsigned int rotation;
4346
4347 if (!intel_crtc || !crtc_state)
4348 return 0;
4349
4350 scaler_state = &crtc_state->scaler_state;
4351
4352 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4353 fb = intel_plane ? plane_state->base.fb : NULL;
4354
4355 if (intel_plane) {
4356 src_w = drm_rect_width(&plane_state->src) >> 16;
4357 src_h = drm_rect_height(&plane_state->src) >> 16;
4358 dst_w = drm_rect_width(&plane_state->dst);
4359 dst_h = drm_rect_height(&plane_state->dst);
4360 scaler_id = &plane_state->scaler_id;
4361 rotation = plane_state->base.rotation;
4362 } else {
4363 struct drm_display_mode *adjusted_mode =
4364 &crtc_state->base.adjusted_mode;
4365 src_w = crtc_state->pipe_src_w;
4366 src_h = crtc_state->pipe_src_h;
4367 dst_w = adjusted_mode->hdisplay;
4368 dst_h = adjusted_mode->vdisplay;
4369 scaler_id = &scaler_state->scaler_id;
4370 rotation = DRM_ROTATE_0;
4371 }
4372
4373 need_scaling = intel_rotation_90_or_270(rotation) ?
4374 (src_h != dst_w || src_w != dst_h):
4375 (src_w != dst_w || src_h != dst_h);
4376
4377 /*
4378 * if plane is being disabled or scaler is no more required or force detach
4379 * - free scaler binded to this plane/crtc
4380 * - in order to do this, update crtc->scaler_usage
4381 *
4382 * Here scaler state in crtc_state is set free so that
4383 * scaler can be assigned to other user. Actual register
4384 * update to free the scaler is done in plane/panel-fit programming.
4385 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4386 */
4387 if (force_detach || !need_scaling || (intel_plane &&
4388 (!fb || !plane_state->visible))) {
4389 if (*scaler_id >= 0) {
4390 scaler_state->scaler_users &= ~(1 << idx);
4391 scaler_state->scalers[*scaler_id].in_use = 0;
4392
4393 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4394 "crtc_state = %p scaler_users = 0x%x\n",
4395 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4396 intel_plane ? intel_plane->base.base.id :
4397 intel_crtc->base.base.id, crtc_state,
4398 scaler_state->scaler_users);
4399 *scaler_id = -1;
4400 }
4401 return 0;
4402 }
4403
4404 /* range checks */
4405 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4406 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4407
4408 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4409 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4410 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4411 "size is out of scaler range\n",
4412 intel_plane ? "PLANE" : "CRTC",
4413 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4414 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4415 return -EINVAL;
4416 }
4417
4418 /* check colorkey */
4419 if (WARN_ON(intel_plane &&
4420 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4421 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4422 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
4423 return -EINVAL;
4424 }
4425
4426 /* Check src format */
4427 if (intel_plane) {
4428 switch (fb->pixel_format) {
4429 case DRM_FORMAT_RGB565:
4430 case DRM_FORMAT_XBGR8888:
4431 case DRM_FORMAT_XRGB8888:
4432 case DRM_FORMAT_ABGR8888:
4433 case DRM_FORMAT_ARGB8888:
4434 case DRM_FORMAT_XRGB2101010:
4435 case DRM_FORMAT_XBGR2101010:
4436 case DRM_FORMAT_YUYV:
4437 case DRM_FORMAT_YVYU:
4438 case DRM_FORMAT_UYVY:
4439 case DRM_FORMAT_VYUY:
4440 break;
4441 default:
4442 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4443 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4444 return -EINVAL;
4445 }
4446 }
4447
4448 /* mark this plane as a scaler user in crtc_state */
4449 scaler_state->scaler_users |= (1 << idx);
4450 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4451 "crtc_state = %p scaler_users = 0x%x\n",
4452 intel_plane ? "PLANE" : "CRTC",
4453 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4454 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4455 return 0;
4456 }
4457
4458 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4459 {
4460 struct drm_device *dev = crtc->base.dev;
4461 struct drm_i915_private *dev_priv = dev->dev_private;
4462 int pipe = crtc->pipe;
4463 struct intel_crtc_scaler_state *scaler_state =
4464 &crtc->config->scaler_state;
4465
4466 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4467
4468 /* To update pfit, first update scaler state */
4469 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4470 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4471 skl_detach_scalers(crtc);
4472 if (!enable)
4473 return;
4474
4475 if (crtc->config->pch_pfit.enabled) {
4476 int id;
4477
4478 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4479 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4480 return;
4481 }
4482
4483 id = scaler_state->scaler_id;
4484 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4485 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4486 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4487 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4488
4489 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4490 }
4491 }
4492
4493 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4494 {
4495 struct drm_device *dev = crtc->base.dev;
4496 struct drm_i915_private *dev_priv = dev->dev_private;
4497 int pipe = crtc->pipe;
4498
4499 if (crtc->config->pch_pfit.enabled) {
4500 /* Force use of hard-coded filter coefficients
4501 * as some pre-programmed values are broken,
4502 * e.g. x201.
4503 */
4504 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4505 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4506 PF_PIPE_SEL_IVB(pipe));
4507 else
4508 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4509 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4510 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4511 }
4512 }
4513
4514 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4515 {
4516 struct drm_device *dev = crtc->dev;
4517 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4518 struct drm_plane *plane;
4519 struct intel_plane *intel_plane;
4520
4521 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4522 intel_plane = to_intel_plane(plane);
4523 if (intel_plane->pipe == pipe)
4524 intel_plane_restore(&intel_plane->base);
4525 }
4526 }
4527
4528 void hsw_enable_ips(struct intel_crtc *crtc)
4529 {
4530 struct drm_device *dev = crtc->base.dev;
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4532
4533 if (!crtc->config->ips_enabled)
4534 return;
4535
4536 /* We can only enable IPS after we enable a plane and wait for a vblank */
4537 intel_wait_for_vblank(dev, crtc->pipe);
4538
4539 assert_plane_enabled(dev_priv, crtc->plane);
4540 if (IS_BROADWELL(dev)) {
4541 mutex_lock(&dev_priv->rps.hw_lock);
4542 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4543 mutex_unlock(&dev_priv->rps.hw_lock);
4544 /* Quoting Art Runyan: "its not safe to expect any particular
4545 * value in IPS_CTL bit 31 after enabling IPS through the
4546 * mailbox." Moreover, the mailbox may return a bogus state,
4547 * so we need to just enable it and continue on.
4548 */
4549 } else {
4550 I915_WRITE(IPS_CTL, IPS_ENABLE);
4551 /* The bit only becomes 1 in the next vblank, so this wait here
4552 * is essentially intel_wait_for_vblank. If we don't have this
4553 * and don't wait for vblanks until the end of crtc_enable, then
4554 * the HW state readout code will complain that the expected
4555 * IPS_CTL value is not the one we read. */
4556 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4557 DRM_ERROR("Timed out waiting for IPS enable\n");
4558 }
4559 }
4560
4561 void hsw_disable_ips(struct intel_crtc *crtc)
4562 {
4563 struct drm_device *dev = crtc->base.dev;
4564 struct drm_i915_private *dev_priv = dev->dev_private;
4565
4566 if (!crtc->config->ips_enabled)
4567 return;
4568
4569 assert_plane_enabled(dev_priv, crtc->plane);
4570 if (IS_BROADWELL(dev)) {
4571 mutex_lock(&dev_priv->rps.hw_lock);
4572 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4573 mutex_unlock(&dev_priv->rps.hw_lock);
4574 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4575 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4576 DRM_ERROR("Timed out waiting for IPS disable\n");
4577 } else {
4578 I915_WRITE(IPS_CTL, 0);
4579 POSTING_READ(IPS_CTL);
4580 }
4581
4582 /* We need to wait for a vblank before we can disable the plane. */
4583 intel_wait_for_vblank(dev, crtc->pipe);
4584 }
4585
4586 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4587 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4588 {
4589 struct drm_device *dev = crtc->dev;
4590 struct drm_i915_private *dev_priv = dev->dev_private;
4591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4592 enum pipe pipe = intel_crtc->pipe;
4593 int palreg = PALETTE(pipe);
4594 int i;
4595 bool reenable_ips = false;
4596
4597 /* The clocks have to be on to load the palette. */
4598 if (!crtc->state->active)
4599 return;
4600
4601 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4602 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4603 assert_dsi_pll_enabled(dev_priv);
4604 else
4605 assert_pll_enabled(dev_priv, pipe);
4606 }
4607
4608 /* use legacy palette for Ironlake */
4609 if (!HAS_GMCH_DISPLAY(dev))
4610 palreg = LGC_PALETTE(pipe);
4611
4612 /* Workaround : Do not read or write the pipe palette/gamma data while
4613 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4614 */
4615 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4616 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4617 GAMMA_MODE_MODE_SPLIT)) {
4618 hsw_disable_ips(intel_crtc);
4619 reenable_ips = true;
4620 }
4621
4622 for (i = 0; i < 256; i++) {
4623 I915_WRITE(palreg + 4 * i,
4624 (intel_crtc->lut_r[i] << 16) |
4625 (intel_crtc->lut_g[i] << 8) |
4626 intel_crtc->lut_b[i]);
4627 }
4628
4629 if (reenable_ips)
4630 hsw_enable_ips(intel_crtc);
4631 }
4632
4633 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4634 {
4635 if (intel_crtc->overlay) {
4636 struct drm_device *dev = intel_crtc->base.dev;
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638
4639 mutex_lock(&dev->struct_mutex);
4640 dev_priv->mm.interruptible = false;
4641 (void) intel_overlay_switch_off(intel_crtc->overlay);
4642 dev_priv->mm.interruptible = true;
4643 mutex_unlock(&dev->struct_mutex);
4644 }
4645
4646 /* Let userspace switch the overlay on again. In most cases userspace
4647 * has to recompute where to put it anyway.
4648 */
4649 }
4650
4651 /**
4652 * intel_post_enable_primary - Perform operations after enabling primary plane
4653 * @crtc: the CRTC whose primary plane was just enabled
4654 *
4655 * Performs potentially sleeping operations that must be done after the primary
4656 * plane is enabled, such as updating FBC and IPS. Note that this may be
4657 * called due to an explicit primary plane update, or due to an implicit
4658 * re-enable that is caused when a sprite plane is updated to no longer
4659 * completely hide the primary plane.
4660 */
4661 static void
4662 intel_post_enable_primary(struct drm_crtc *crtc)
4663 {
4664 struct drm_device *dev = crtc->dev;
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4667 int pipe = intel_crtc->pipe;
4668
4669 /*
4670 * BDW signals flip done immediately if the plane
4671 * is disabled, even if the plane enable is already
4672 * armed to occur at the next vblank :(
4673 */
4674 if (IS_BROADWELL(dev))
4675 intel_wait_for_vblank(dev, pipe);
4676
4677 /*
4678 * FIXME IPS should be fine as long as one plane is
4679 * enabled, but in practice it seems to have problems
4680 * when going from primary only to sprite only and vice
4681 * versa.
4682 */
4683 hsw_enable_ips(intel_crtc);
4684
4685 mutex_lock(&dev->struct_mutex);
4686 intel_fbc_update(dev);
4687 mutex_unlock(&dev->struct_mutex);
4688
4689 /*
4690 * Gen2 reports pipe underruns whenever all planes are disabled.
4691 * So don't enable underrun reporting before at least some planes
4692 * are enabled.
4693 * FIXME: Need to fix the logic to work when we turn off all planes
4694 * but leave the pipe running.
4695 */
4696 if (IS_GEN2(dev))
4697 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4698
4699 /* Underruns don't raise interrupts, so check manually. */
4700 if (HAS_GMCH_DISPLAY(dev))
4701 i9xx_check_fifo_underruns(dev_priv);
4702 }
4703
4704 /**
4705 * intel_pre_disable_primary - Perform operations before disabling primary plane
4706 * @crtc: the CRTC whose primary plane is to be disabled
4707 *
4708 * Performs potentially sleeping operations that must be done before the
4709 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4710 * be called due to an explicit primary plane update, or due to an implicit
4711 * disable that is caused when a sprite plane completely hides the primary
4712 * plane.
4713 */
4714 static void
4715 intel_pre_disable_primary(struct drm_crtc *crtc)
4716 {
4717 struct drm_device *dev = crtc->dev;
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4720 int pipe = intel_crtc->pipe;
4721
4722 /*
4723 * Gen2 reports pipe underruns whenever all planes are disabled.
4724 * So diasble underrun reporting before all the planes get disabled.
4725 * FIXME: Need to fix the logic to work when we turn off all planes
4726 * but leave the pipe running.
4727 */
4728 if (IS_GEN2(dev))
4729 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4730
4731 /*
4732 * Vblank time updates from the shadow to live plane control register
4733 * are blocked if the memory self-refresh mode is active at that
4734 * moment. So to make sure the plane gets truly disabled, disable
4735 * first the self-refresh mode. The self-refresh enable bit in turn
4736 * will be checked/applied by the HW only at the next frame start
4737 * event which is after the vblank start event, so we need to have a
4738 * wait-for-vblank between disabling the plane and the pipe.
4739 */
4740 if (HAS_GMCH_DISPLAY(dev))
4741 intel_set_memory_cxsr(dev_priv, false);
4742
4743 mutex_lock(&dev->struct_mutex);
4744 if (dev_priv->fbc.crtc == intel_crtc)
4745 intel_fbc_disable(dev);
4746 mutex_unlock(&dev->struct_mutex);
4747
4748 /*
4749 * FIXME IPS should be fine as long as one plane is
4750 * enabled, but in practice it seems to have problems
4751 * when going from primary only to sprite only and vice
4752 * versa.
4753 */
4754 hsw_disable_ips(intel_crtc);
4755 }
4756
4757 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4758 {
4759 struct drm_device *dev = crtc->dev;
4760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4761 int pipe = intel_crtc->pipe;
4762
4763 intel_enable_primary_hw_plane(crtc->primary, crtc);
4764 intel_enable_sprite_planes(crtc);
4765 if (to_intel_plane_state(crtc->cursor->state)->visible)
4766 intel_crtc_update_cursor(crtc, true);
4767
4768 intel_post_enable_primary(crtc);
4769
4770 /*
4771 * FIXME: Once we grow proper nuclear flip support out of this we need
4772 * to compute the mask of flip planes precisely. For the time being
4773 * consider this a flip to a NULL plane.
4774 */
4775 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4776 }
4777
4778 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4779 {
4780 struct drm_device *dev = crtc->dev;
4781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4782 struct intel_plane *intel_plane;
4783 int pipe = intel_crtc->pipe;
4784
4785 intel_crtc_wait_for_pending_flips(crtc);
4786
4787 intel_pre_disable_primary(crtc);
4788
4789 intel_crtc_dpms_overlay_disable(intel_crtc);
4790 for_each_intel_plane(dev, intel_plane) {
4791 if (intel_plane->pipe == pipe) {
4792 struct drm_crtc *from = intel_plane->base.crtc;
4793
4794 intel_plane->disable_plane(&intel_plane->base,
4795 from ?: crtc, true);
4796 }
4797 }
4798
4799 /*
4800 * FIXME: Once we grow proper nuclear flip support out of this we need
4801 * to compute the mask of flip planes precisely. For the time being
4802 * consider this a flip to a NULL plane.
4803 */
4804 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4805 }
4806
4807 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4808 {
4809 struct drm_device *dev = crtc->dev;
4810 struct drm_i915_private *dev_priv = dev->dev_private;
4811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4812 struct intel_encoder *encoder;
4813 int pipe = intel_crtc->pipe;
4814
4815 if (WARN_ON(intel_crtc->active))
4816 return;
4817
4818 if (intel_crtc->config->has_pch_encoder)
4819 intel_prepare_shared_dpll(intel_crtc);
4820
4821 if (intel_crtc->config->has_dp_encoder)
4822 intel_dp_set_m_n(intel_crtc, M1_N1);
4823
4824 intel_set_pipe_timings(intel_crtc);
4825
4826 if (intel_crtc->config->has_pch_encoder) {
4827 intel_cpu_transcoder_set_m_n(intel_crtc,
4828 &intel_crtc->config->fdi_m_n, NULL);
4829 }
4830
4831 ironlake_set_pipeconf(crtc);
4832
4833 intel_crtc->active = true;
4834
4835 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4836 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4837
4838 for_each_encoder_on_crtc(dev, crtc, encoder)
4839 if (encoder->pre_enable)
4840 encoder->pre_enable(encoder);
4841
4842 if (intel_crtc->config->has_pch_encoder) {
4843 /* Note: FDI PLL enabling _must_ be done before we enable the
4844 * cpu pipes, hence this is separate from all the other fdi/pch
4845 * enabling. */
4846 ironlake_fdi_pll_enable(intel_crtc);
4847 } else {
4848 assert_fdi_tx_disabled(dev_priv, pipe);
4849 assert_fdi_rx_disabled(dev_priv, pipe);
4850 }
4851
4852 ironlake_pfit_enable(intel_crtc);
4853
4854 /*
4855 * On ILK+ LUT must be loaded before the pipe is running but with
4856 * clocks enabled
4857 */
4858 intel_crtc_load_lut(crtc);
4859
4860 intel_update_watermarks(crtc);
4861 intel_enable_pipe(intel_crtc);
4862
4863 if (intel_crtc->config->has_pch_encoder)
4864 ironlake_pch_enable(crtc);
4865
4866 assert_vblank_disabled(crtc);
4867 drm_crtc_vblank_on(crtc);
4868
4869 for_each_encoder_on_crtc(dev, crtc, encoder)
4870 encoder->enable(encoder);
4871
4872 if (HAS_PCH_CPT(dev))
4873 cpt_verify_modeset(dev, intel_crtc->pipe);
4874 }
4875
4876 /* IPS only exists on ULT machines and is tied to pipe A. */
4877 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4878 {
4879 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4880 }
4881
4882 static void haswell_crtc_enable(struct drm_crtc *crtc)
4883 {
4884 struct drm_device *dev = crtc->dev;
4885 struct drm_i915_private *dev_priv = dev->dev_private;
4886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4887 struct intel_encoder *encoder;
4888 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4889 struct intel_crtc_state *pipe_config =
4890 to_intel_crtc_state(crtc->state);
4891
4892 if (WARN_ON(intel_crtc->active))
4893 return;
4894
4895 if (intel_crtc_to_shared_dpll(intel_crtc))
4896 intel_enable_shared_dpll(intel_crtc);
4897
4898 if (intel_crtc->config->has_dp_encoder)
4899 intel_dp_set_m_n(intel_crtc, M1_N1);
4900
4901 intel_set_pipe_timings(intel_crtc);
4902
4903 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4904 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4905 intel_crtc->config->pixel_multiplier - 1);
4906 }
4907
4908 if (intel_crtc->config->has_pch_encoder) {
4909 intel_cpu_transcoder_set_m_n(intel_crtc,
4910 &intel_crtc->config->fdi_m_n, NULL);
4911 }
4912
4913 haswell_set_pipeconf(crtc);
4914
4915 intel_set_pipe_csc(crtc);
4916
4917 intel_crtc->active = true;
4918
4919 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4920 for_each_encoder_on_crtc(dev, crtc, encoder)
4921 if (encoder->pre_enable)
4922 encoder->pre_enable(encoder);
4923
4924 if (intel_crtc->config->has_pch_encoder) {
4925 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4926 true);
4927 dev_priv->display.fdi_link_train(crtc);
4928 }
4929
4930 intel_ddi_enable_pipe_clock(intel_crtc);
4931
4932 if (INTEL_INFO(dev)->gen == 9)
4933 skylake_pfit_update(intel_crtc, 1);
4934 else if (INTEL_INFO(dev)->gen < 9)
4935 ironlake_pfit_enable(intel_crtc);
4936 else
4937 MISSING_CASE(INTEL_INFO(dev)->gen);
4938
4939 /*
4940 * On ILK+ LUT must be loaded before the pipe is running but with
4941 * clocks enabled
4942 */
4943 intel_crtc_load_lut(crtc);
4944
4945 intel_ddi_set_pipe_settings(crtc);
4946 intel_ddi_enable_transcoder_func(crtc);
4947
4948 intel_update_watermarks(crtc);
4949 intel_enable_pipe(intel_crtc);
4950
4951 if (intel_crtc->config->has_pch_encoder)
4952 lpt_pch_enable(crtc);
4953
4954 if (intel_crtc->config->dp_encoder_is_mst)
4955 intel_ddi_set_vc_payload_alloc(crtc, true);
4956
4957 assert_vblank_disabled(crtc);
4958 drm_crtc_vblank_on(crtc);
4959
4960 for_each_encoder_on_crtc(dev, crtc, encoder) {
4961 encoder->enable(encoder);
4962 intel_opregion_notify_encoder(encoder, true);
4963 }
4964
4965 /* If we change the relative order between pipe/planes enabling, we need
4966 * to change the workaround. */
4967 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4968 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4969 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4970 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4971 }
4972 }
4973
4974 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4975 {
4976 struct drm_device *dev = crtc->base.dev;
4977 struct drm_i915_private *dev_priv = dev->dev_private;
4978 int pipe = crtc->pipe;
4979
4980 /* To avoid upsetting the power well on haswell only disable the pfit if
4981 * it's in use. The hw state code will make sure we get this right. */
4982 if (crtc->config->pch_pfit.enabled) {
4983 I915_WRITE(PF_CTL(pipe), 0);
4984 I915_WRITE(PF_WIN_POS(pipe), 0);
4985 I915_WRITE(PF_WIN_SZ(pipe), 0);
4986 }
4987 }
4988
4989 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4990 {
4991 struct drm_device *dev = crtc->dev;
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4994 struct intel_encoder *encoder;
4995 int pipe = intel_crtc->pipe;
4996 u32 reg, temp;
4997
4998 if (WARN_ON(!intel_crtc->active))
4999 return;
5000
5001 for_each_encoder_on_crtc(dev, crtc, encoder)
5002 encoder->disable(encoder);
5003
5004 drm_crtc_vblank_off(crtc);
5005 assert_vblank_disabled(crtc);
5006
5007 if (intel_crtc->config->has_pch_encoder)
5008 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5009
5010 intel_disable_pipe(intel_crtc);
5011
5012 ironlake_pfit_disable(intel_crtc);
5013
5014 if (intel_crtc->config->has_pch_encoder)
5015 ironlake_fdi_disable(crtc);
5016
5017 for_each_encoder_on_crtc(dev, crtc, encoder)
5018 if (encoder->post_disable)
5019 encoder->post_disable(encoder);
5020
5021 if (intel_crtc->config->has_pch_encoder) {
5022 ironlake_disable_pch_transcoder(dev_priv, pipe);
5023
5024 if (HAS_PCH_CPT(dev)) {
5025 /* disable TRANS_DP_CTL */
5026 reg = TRANS_DP_CTL(pipe);
5027 temp = I915_READ(reg);
5028 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5029 TRANS_DP_PORT_SEL_MASK);
5030 temp |= TRANS_DP_PORT_SEL_NONE;
5031 I915_WRITE(reg, temp);
5032
5033 /* disable DPLL_SEL */
5034 temp = I915_READ(PCH_DPLL_SEL);
5035 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5036 I915_WRITE(PCH_DPLL_SEL, temp);
5037 }
5038
5039 /* disable PCH DPLL */
5040 intel_disable_shared_dpll(intel_crtc);
5041
5042 ironlake_fdi_pll_disable(intel_crtc);
5043 }
5044
5045 intel_crtc->active = false;
5046 intel_update_watermarks(crtc);
5047
5048 mutex_lock(&dev->struct_mutex);
5049 intel_fbc_update(dev);
5050 mutex_unlock(&dev->struct_mutex);
5051 }
5052
5053 static void haswell_crtc_disable(struct drm_crtc *crtc)
5054 {
5055 struct drm_device *dev = crtc->dev;
5056 struct drm_i915_private *dev_priv = dev->dev_private;
5057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5058 struct intel_encoder *encoder;
5059 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5060
5061 if (WARN_ON(!intel_crtc->active))
5062 return;
5063
5064 for_each_encoder_on_crtc(dev, crtc, encoder) {
5065 intel_opregion_notify_encoder(encoder, false);
5066 encoder->disable(encoder);
5067 }
5068
5069 drm_crtc_vblank_off(crtc);
5070 assert_vblank_disabled(crtc);
5071
5072 if (intel_crtc->config->has_pch_encoder)
5073 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5074 false);
5075 intel_disable_pipe(intel_crtc);
5076
5077 if (intel_crtc->config->dp_encoder_is_mst)
5078 intel_ddi_set_vc_payload_alloc(crtc, false);
5079
5080 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5081
5082 if (INTEL_INFO(dev)->gen == 9)
5083 skylake_pfit_update(intel_crtc, 0);
5084 else if (INTEL_INFO(dev)->gen < 9)
5085 ironlake_pfit_disable(intel_crtc);
5086 else
5087 MISSING_CASE(INTEL_INFO(dev)->gen);
5088
5089 intel_ddi_disable_pipe_clock(intel_crtc);
5090
5091 if (intel_crtc->config->has_pch_encoder) {
5092 lpt_disable_pch_transcoder(dev_priv);
5093 intel_ddi_fdi_disable(crtc);
5094 }
5095
5096 for_each_encoder_on_crtc(dev, crtc, encoder)
5097 if (encoder->post_disable)
5098 encoder->post_disable(encoder);
5099
5100 intel_crtc->active = false;
5101 intel_update_watermarks(crtc);
5102
5103 mutex_lock(&dev->struct_mutex);
5104 intel_fbc_update(dev);
5105 mutex_unlock(&dev->struct_mutex);
5106
5107 if (intel_crtc_to_shared_dpll(intel_crtc))
5108 intel_disable_shared_dpll(intel_crtc);
5109 }
5110
5111 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5112 {
5113 struct drm_device *dev = crtc->base.dev;
5114 struct drm_i915_private *dev_priv = dev->dev_private;
5115 struct intel_crtc_state *pipe_config = crtc->config;
5116
5117 if (!pipe_config->gmch_pfit.control)
5118 return;
5119
5120 /*
5121 * The panel fitter should only be adjusted whilst the pipe is disabled,
5122 * according to register description and PRM.
5123 */
5124 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5125 assert_pipe_disabled(dev_priv, crtc->pipe);
5126
5127 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5128 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5129
5130 /* Border color in case we don't scale up to the full screen. Black by
5131 * default, change to something else for debugging. */
5132 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5133 }
5134
5135 static enum intel_display_power_domain port_to_power_domain(enum port port)
5136 {
5137 switch (port) {
5138 case PORT_A:
5139 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5140 case PORT_B:
5141 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5142 case PORT_C:
5143 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5144 case PORT_D:
5145 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5146 default:
5147 WARN_ON_ONCE(1);
5148 return POWER_DOMAIN_PORT_OTHER;
5149 }
5150 }
5151
5152 #define for_each_power_domain(domain, mask) \
5153 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5154 if ((1 << (domain)) & (mask))
5155
5156 enum intel_display_power_domain
5157 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5158 {
5159 struct drm_device *dev = intel_encoder->base.dev;
5160 struct intel_digital_port *intel_dig_port;
5161
5162 switch (intel_encoder->type) {
5163 case INTEL_OUTPUT_UNKNOWN:
5164 /* Only DDI platforms should ever use this output type */
5165 WARN_ON_ONCE(!HAS_DDI(dev));
5166 case INTEL_OUTPUT_DISPLAYPORT:
5167 case INTEL_OUTPUT_HDMI:
5168 case INTEL_OUTPUT_EDP:
5169 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5170 return port_to_power_domain(intel_dig_port->port);
5171 case INTEL_OUTPUT_DP_MST:
5172 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5173 return port_to_power_domain(intel_dig_port->port);
5174 case INTEL_OUTPUT_ANALOG:
5175 return POWER_DOMAIN_PORT_CRT;
5176 case INTEL_OUTPUT_DSI:
5177 return POWER_DOMAIN_PORT_DSI;
5178 default:
5179 return POWER_DOMAIN_PORT_OTHER;
5180 }
5181 }
5182
5183 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5184 {
5185 struct drm_device *dev = crtc->dev;
5186 struct intel_encoder *intel_encoder;
5187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5188 enum pipe pipe = intel_crtc->pipe;
5189 unsigned long mask;
5190 enum transcoder transcoder;
5191
5192 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5193
5194 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5195 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5196 if (intel_crtc->config->pch_pfit.enabled ||
5197 intel_crtc->config->pch_pfit.force_thru)
5198 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5199
5200 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5201 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5202
5203 return mask;
5204 }
5205
5206 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5207 {
5208 struct drm_device *dev = state->dev;
5209 struct drm_i915_private *dev_priv = dev->dev_private;
5210 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5211 struct intel_crtc *crtc;
5212
5213 /*
5214 * First get all needed power domains, then put all unneeded, to avoid
5215 * any unnecessary toggling of the power wells.
5216 */
5217 for_each_intel_crtc(dev, crtc) {
5218 enum intel_display_power_domain domain;
5219
5220 if (!crtc->base.state->enable)
5221 continue;
5222
5223 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5224
5225 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5226 intel_display_power_get(dev_priv, domain);
5227 }
5228
5229 if (dev_priv->display.modeset_global_resources)
5230 dev_priv->display.modeset_global_resources(state);
5231
5232 for_each_intel_crtc(dev, crtc) {
5233 enum intel_display_power_domain domain;
5234
5235 for_each_power_domain(domain, crtc->enabled_power_domains)
5236 intel_display_power_put(dev_priv, domain);
5237
5238 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5239 }
5240
5241 intel_display_set_init_power(dev_priv, false);
5242 }
5243
5244 static void intel_update_max_cdclk(struct drm_device *dev)
5245 {
5246 struct drm_i915_private *dev_priv = dev->dev_private;
5247
5248 if (IS_SKYLAKE(dev)) {
5249 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5250
5251 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5252 dev_priv->max_cdclk_freq = 675000;
5253 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5254 dev_priv->max_cdclk_freq = 540000;
5255 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5256 dev_priv->max_cdclk_freq = 450000;
5257 else
5258 dev_priv->max_cdclk_freq = 337500;
5259 } else if (IS_BROADWELL(dev)) {
5260 /*
5261 * FIXME with extra cooling we can allow
5262 * 540 MHz for ULX and 675 Mhz for ULT.
5263 * How can we know if extra cooling is
5264 * available? PCI ID, VTB, something else?
5265 */
5266 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5267 dev_priv->max_cdclk_freq = 450000;
5268 else if (IS_BDW_ULX(dev))
5269 dev_priv->max_cdclk_freq = 450000;
5270 else if (IS_BDW_ULT(dev))
5271 dev_priv->max_cdclk_freq = 540000;
5272 else
5273 dev_priv->max_cdclk_freq = 675000;
5274 } else if (IS_VALLEYVIEW(dev)) {
5275 dev_priv->max_cdclk_freq = 400000;
5276 } else {
5277 /* otherwise assume cdclk is fixed */
5278 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5279 }
5280
5281 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5282 dev_priv->max_cdclk_freq);
5283 }
5284
5285 static void intel_update_cdclk(struct drm_device *dev)
5286 {
5287 struct drm_i915_private *dev_priv = dev->dev_private;
5288
5289 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5290 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5291 dev_priv->cdclk_freq);
5292
5293 /*
5294 * Program the gmbus_freq based on the cdclk frequency.
5295 * BSpec erroneously claims we should aim for 4MHz, but
5296 * in fact 1MHz is the correct frequency.
5297 */
5298 if (IS_VALLEYVIEW(dev)) {
5299 /*
5300 * Program the gmbus_freq based on the cdclk frequency.
5301 * BSpec erroneously claims we should aim for 4MHz, but
5302 * in fact 1MHz is the correct frequency.
5303 */
5304 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5305 }
5306
5307 if (dev_priv->max_cdclk_freq == 0)
5308 intel_update_max_cdclk(dev);
5309 }
5310
5311 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5312 {
5313 struct drm_i915_private *dev_priv = dev->dev_private;
5314 uint32_t divider;
5315 uint32_t ratio;
5316 uint32_t current_freq;
5317 int ret;
5318
5319 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5320 switch (frequency) {
5321 case 144000:
5322 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5323 ratio = BXT_DE_PLL_RATIO(60);
5324 break;
5325 case 288000:
5326 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5327 ratio = BXT_DE_PLL_RATIO(60);
5328 break;
5329 case 384000:
5330 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5331 ratio = BXT_DE_PLL_RATIO(60);
5332 break;
5333 case 576000:
5334 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5335 ratio = BXT_DE_PLL_RATIO(60);
5336 break;
5337 case 624000:
5338 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5339 ratio = BXT_DE_PLL_RATIO(65);
5340 break;
5341 case 19200:
5342 /*
5343 * Bypass frequency with DE PLL disabled. Init ratio, divider
5344 * to suppress GCC warning.
5345 */
5346 ratio = 0;
5347 divider = 0;
5348 break;
5349 default:
5350 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5351
5352 return;
5353 }
5354
5355 mutex_lock(&dev_priv->rps.hw_lock);
5356 /* Inform power controller of upcoming frequency change */
5357 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5358 0x80000000);
5359 mutex_unlock(&dev_priv->rps.hw_lock);
5360
5361 if (ret) {
5362 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5363 ret, frequency);
5364 return;
5365 }
5366
5367 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5368 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5369 current_freq = current_freq * 500 + 1000;
5370
5371 /*
5372 * DE PLL has to be disabled when
5373 * - setting to 19.2MHz (bypass, PLL isn't used)
5374 * - before setting to 624MHz (PLL needs toggling)
5375 * - before setting to any frequency from 624MHz (PLL needs toggling)
5376 */
5377 if (frequency == 19200 || frequency == 624000 ||
5378 current_freq == 624000) {
5379 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5380 /* Timeout 200us */
5381 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5382 1))
5383 DRM_ERROR("timout waiting for DE PLL unlock\n");
5384 }
5385
5386 if (frequency != 19200) {
5387 uint32_t val;
5388
5389 val = I915_READ(BXT_DE_PLL_CTL);
5390 val &= ~BXT_DE_PLL_RATIO_MASK;
5391 val |= ratio;
5392 I915_WRITE(BXT_DE_PLL_CTL, val);
5393
5394 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5395 /* Timeout 200us */
5396 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5397 DRM_ERROR("timeout waiting for DE PLL lock\n");
5398
5399 val = I915_READ(CDCLK_CTL);
5400 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5401 val |= divider;
5402 /*
5403 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5404 * enable otherwise.
5405 */
5406 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5407 if (frequency >= 500000)
5408 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5409
5410 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5411 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5412 val |= (frequency - 1000) / 500;
5413 I915_WRITE(CDCLK_CTL, val);
5414 }
5415
5416 mutex_lock(&dev_priv->rps.hw_lock);
5417 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5418 DIV_ROUND_UP(frequency, 25000));
5419 mutex_unlock(&dev_priv->rps.hw_lock);
5420
5421 if (ret) {
5422 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5423 ret, frequency);
5424 return;
5425 }
5426
5427 intel_update_cdclk(dev);
5428 }
5429
5430 void broxton_init_cdclk(struct drm_device *dev)
5431 {
5432 struct drm_i915_private *dev_priv = dev->dev_private;
5433 uint32_t val;
5434
5435 /*
5436 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5437 * or else the reset will hang because there is no PCH to respond.
5438 * Move the handshake programming to initialization sequence.
5439 * Previously was left up to BIOS.
5440 */
5441 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5442 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5443 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5444
5445 /* Enable PG1 for cdclk */
5446 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5447
5448 /* check if cd clock is enabled */
5449 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5450 DRM_DEBUG_KMS("Display already initialized\n");
5451 return;
5452 }
5453
5454 /*
5455 * FIXME:
5456 * - The initial CDCLK needs to be read from VBT.
5457 * Need to make this change after VBT has changes for BXT.
5458 * - check if setting the max (or any) cdclk freq is really necessary
5459 * here, it belongs to modeset time
5460 */
5461 broxton_set_cdclk(dev, 624000);
5462
5463 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5464 POSTING_READ(DBUF_CTL);
5465
5466 udelay(10);
5467
5468 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5469 DRM_ERROR("DBuf power enable timeout!\n");
5470 }
5471
5472 void broxton_uninit_cdclk(struct drm_device *dev)
5473 {
5474 struct drm_i915_private *dev_priv = dev->dev_private;
5475
5476 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5477 POSTING_READ(DBUF_CTL);
5478
5479 udelay(10);
5480
5481 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5482 DRM_ERROR("DBuf power disable timeout!\n");
5483
5484 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5485 broxton_set_cdclk(dev, 19200);
5486
5487 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5488 }
5489
5490 static const struct skl_cdclk_entry {
5491 unsigned int freq;
5492 unsigned int vco;
5493 } skl_cdclk_frequencies[] = {
5494 { .freq = 308570, .vco = 8640 },
5495 { .freq = 337500, .vco = 8100 },
5496 { .freq = 432000, .vco = 8640 },
5497 { .freq = 450000, .vco = 8100 },
5498 { .freq = 540000, .vco = 8100 },
5499 { .freq = 617140, .vco = 8640 },
5500 { .freq = 675000, .vco = 8100 },
5501 };
5502
5503 static unsigned int skl_cdclk_decimal(unsigned int freq)
5504 {
5505 return (freq - 1000) / 500;
5506 }
5507
5508 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5509 {
5510 unsigned int i;
5511
5512 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5513 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5514
5515 if (e->freq == freq)
5516 return e->vco;
5517 }
5518
5519 return 8100;
5520 }
5521
5522 static void
5523 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5524 {
5525 unsigned int min_freq;
5526 u32 val;
5527
5528 /* select the minimum CDCLK before enabling DPLL 0 */
5529 val = I915_READ(CDCLK_CTL);
5530 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5531 val |= CDCLK_FREQ_337_308;
5532
5533 if (required_vco == 8640)
5534 min_freq = 308570;
5535 else
5536 min_freq = 337500;
5537
5538 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5539
5540 I915_WRITE(CDCLK_CTL, val);
5541 POSTING_READ(CDCLK_CTL);
5542
5543 /*
5544 * We always enable DPLL0 with the lowest link rate possible, but still
5545 * taking into account the VCO required to operate the eDP panel at the
5546 * desired frequency. The usual DP link rates operate with a VCO of
5547 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5548 * The modeset code is responsible for the selection of the exact link
5549 * rate later on, with the constraint of choosing a frequency that
5550 * works with required_vco.
5551 */
5552 val = I915_READ(DPLL_CTRL1);
5553
5554 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5555 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5556 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5557 if (required_vco == 8640)
5558 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5559 SKL_DPLL0);
5560 else
5561 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5562 SKL_DPLL0);
5563
5564 I915_WRITE(DPLL_CTRL1, val);
5565 POSTING_READ(DPLL_CTRL1);
5566
5567 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5568
5569 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5570 DRM_ERROR("DPLL0 not locked\n");
5571 }
5572
5573 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5574 {
5575 int ret;
5576 u32 val;
5577
5578 /* inform PCU we want to change CDCLK */
5579 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5580 mutex_lock(&dev_priv->rps.hw_lock);
5581 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5582 mutex_unlock(&dev_priv->rps.hw_lock);
5583
5584 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5585 }
5586
5587 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5588 {
5589 unsigned int i;
5590
5591 for (i = 0; i < 15; i++) {
5592 if (skl_cdclk_pcu_ready(dev_priv))
5593 return true;
5594 udelay(10);
5595 }
5596
5597 return false;
5598 }
5599
5600 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5601 {
5602 struct drm_device *dev = dev_priv->dev;
5603 u32 freq_select, pcu_ack;
5604
5605 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5606
5607 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5608 DRM_ERROR("failed to inform PCU about cdclk change\n");
5609 return;
5610 }
5611
5612 /* set CDCLK_CTL */
5613 switch(freq) {
5614 case 450000:
5615 case 432000:
5616 freq_select = CDCLK_FREQ_450_432;
5617 pcu_ack = 1;
5618 break;
5619 case 540000:
5620 freq_select = CDCLK_FREQ_540;
5621 pcu_ack = 2;
5622 break;
5623 case 308570:
5624 case 337500:
5625 default:
5626 freq_select = CDCLK_FREQ_337_308;
5627 pcu_ack = 0;
5628 break;
5629 case 617140:
5630 case 675000:
5631 freq_select = CDCLK_FREQ_675_617;
5632 pcu_ack = 3;
5633 break;
5634 }
5635
5636 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5637 POSTING_READ(CDCLK_CTL);
5638
5639 /* inform PCU of the change */
5640 mutex_lock(&dev_priv->rps.hw_lock);
5641 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5642 mutex_unlock(&dev_priv->rps.hw_lock);
5643
5644 intel_update_cdclk(dev);
5645 }
5646
5647 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5648 {
5649 /* disable DBUF power */
5650 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5651 POSTING_READ(DBUF_CTL);
5652
5653 udelay(10);
5654
5655 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5656 DRM_ERROR("DBuf power disable timeout\n");
5657
5658 /* disable DPLL0 */
5659 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5660 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5661 DRM_ERROR("Couldn't disable DPLL0\n");
5662
5663 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5664 }
5665
5666 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5667 {
5668 u32 val;
5669 unsigned int required_vco;
5670
5671 /* enable PCH reset handshake */
5672 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5673 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5674
5675 /* enable PG1 and Misc I/O */
5676 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5677
5678 /* DPLL0 already enabed !? */
5679 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5680 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5681 return;
5682 }
5683
5684 /* enable DPLL0 */
5685 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5686 skl_dpll0_enable(dev_priv, required_vco);
5687
5688 /* set CDCLK to the frequency the BIOS chose */
5689 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5690
5691 /* enable DBUF power */
5692 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5693 POSTING_READ(DBUF_CTL);
5694
5695 udelay(10);
5696
5697 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5698 DRM_ERROR("DBuf power enable timeout\n");
5699 }
5700
5701 /* returns HPLL frequency in kHz */
5702 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5703 {
5704 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5705
5706 /* Obtain SKU information */
5707 mutex_lock(&dev_priv->sb_lock);
5708 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5709 CCK_FUSE_HPLL_FREQ_MASK;
5710 mutex_unlock(&dev_priv->sb_lock);
5711
5712 return vco_freq[hpll_freq] * 1000;
5713 }
5714
5715 /* Adjust CDclk dividers to allow high res or save power if possible */
5716 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5717 {
5718 struct drm_i915_private *dev_priv = dev->dev_private;
5719 u32 val, cmd;
5720
5721 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5722 != dev_priv->cdclk_freq);
5723
5724 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5725 cmd = 2;
5726 else if (cdclk == 266667)
5727 cmd = 1;
5728 else
5729 cmd = 0;
5730
5731 mutex_lock(&dev_priv->rps.hw_lock);
5732 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5733 val &= ~DSPFREQGUAR_MASK;
5734 val |= (cmd << DSPFREQGUAR_SHIFT);
5735 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5736 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5737 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5738 50)) {
5739 DRM_ERROR("timed out waiting for CDclk change\n");
5740 }
5741 mutex_unlock(&dev_priv->rps.hw_lock);
5742
5743 mutex_lock(&dev_priv->sb_lock);
5744
5745 if (cdclk == 400000) {
5746 u32 divider;
5747
5748 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5749
5750 /* adjust cdclk divider */
5751 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5752 val &= ~DISPLAY_FREQUENCY_VALUES;
5753 val |= divider;
5754 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5755
5756 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5757 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5758 50))
5759 DRM_ERROR("timed out waiting for CDclk change\n");
5760 }
5761
5762 /* adjust self-refresh exit latency value */
5763 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5764 val &= ~0x7f;
5765
5766 /*
5767 * For high bandwidth configs, we set a higher latency in the bunit
5768 * so that the core display fetch happens in time to avoid underruns.
5769 */
5770 if (cdclk == 400000)
5771 val |= 4500 / 250; /* 4.5 usec */
5772 else
5773 val |= 3000 / 250; /* 3.0 usec */
5774 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5775
5776 mutex_unlock(&dev_priv->sb_lock);
5777
5778 intel_update_cdclk(dev);
5779 }
5780
5781 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5782 {
5783 struct drm_i915_private *dev_priv = dev->dev_private;
5784 u32 val, cmd;
5785
5786 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5787 != dev_priv->cdclk_freq);
5788
5789 switch (cdclk) {
5790 case 333333:
5791 case 320000:
5792 case 266667:
5793 case 200000:
5794 break;
5795 default:
5796 MISSING_CASE(cdclk);
5797 return;
5798 }
5799
5800 /*
5801 * Specs are full of misinformation, but testing on actual
5802 * hardware has shown that we just need to write the desired
5803 * CCK divider into the Punit register.
5804 */
5805 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5806
5807 mutex_lock(&dev_priv->rps.hw_lock);
5808 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5809 val &= ~DSPFREQGUAR_MASK_CHV;
5810 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5811 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5812 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5813 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5814 50)) {
5815 DRM_ERROR("timed out waiting for CDclk change\n");
5816 }
5817 mutex_unlock(&dev_priv->rps.hw_lock);
5818
5819 intel_update_cdclk(dev);
5820 }
5821
5822 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5823 int max_pixclk)
5824 {
5825 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5826 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5827
5828 /*
5829 * Really only a few cases to deal with, as only 4 CDclks are supported:
5830 * 200MHz
5831 * 267MHz
5832 * 320/333MHz (depends on HPLL freq)
5833 * 400MHz (VLV only)
5834 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5835 * of the lower bin and adjust if needed.
5836 *
5837 * We seem to get an unstable or solid color picture at 200MHz.
5838 * Not sure what's wrong. For now use 200MHz only when all pipes
5839 * are off.
5840 */
5841 if (!IS_CHERRYVIEW(dev_priv) &&
5842 max_pixclk > freq_320*limit/100)
5843 return 400000;
5844 else if (max_pixclk > 266667*limit/100)
5845 return freq_320;
5846 else if (max_pixclk > 0)
5847 return 266667;
5848 else
5849 return 200000;
5850 }
5851
5852 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5853 int max_pixclk)
5854 {
5855 /*
5856 * FIXME:
5857 * - remove the guardband, it's not needed on BXT
5858 * - set 19.2MHz bypass frequency if there are no active pipes
5859 */
5860 if (max_pixclk > 576000*9/10)
5861 return 624000;
5862 else if (max_pixclk > 384000*9/10)
5863 return 576000;
5864 else if (max_pixclk > 288000*9/10)
5865 return 384000;
5866 else if (max_pixclk > 144000*9/10)
5867 return 288000;
5868 else
5869 return 144000;
5870 }
5871
5872 /* Compute the max pixel clock for new configuration. Uses atomic state if
5873 * that's non-NULL, look at current state otherwise. */
5874 static int intel_mode_max_pixclk(struct drm_device *dev,
5875 struct drm_atomic_state *state)
5876 {
5877 struct intel_crtc *intel_crtc;
5878 struct intel_crtc_state *crtc_state;
5879 int max_pixclk = 0;
5880
5881 for_each_intel_crtc(dev, intel_crtc) {
5882 if (state)
5883 crtc_state =
5884 intel_atomic_get_crtc_state(state, intel_crtc);
5885 else
5886 crtc_state = intel_crtc->config;
5887 if (IS_ERR(crtc_state))
5888 return PTR_ERR(crtc_state);
5889
5890 if (!crtc_state->base.enable)
5891 continue;
5892
5893 max_pixclk = max(max_pixclk,
5894 crtc_state->base.adjusted_mode.crtc_clock);
5895 }
5896
5897 return max_pixclk;
5898 }
5899
5900 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5901 {
5902 struct drm_i915_private *dev_priv = to_i915(state->dev);
5903 struct drm_crtc *crtc;
5904 struct drm_crtc_state *crtc_state;
5905 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5906 int cdclk, ret = 0;
5907
5908 if (max_pixclk < 0)
5909 return max_pixclk;
5910
5911 if (IS_VALLEYVIEW(dev_priv))
5912 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5913 else
5914 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5915
5916 if (cdclk == dev_priv->cdclk_freq)
5917 return 0;
5918
5919 /* add all active pipes to the state */
5920 for_each_crtc(state->dev, crtc) {
5921 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5922 if (IS_ERR(crtc_state))
5923 return PTR_ERR(crtc_state);
5924
5925 if (!crtc_state->active || needs_modeset(crtc_state))
5926 continue;
5927
5928 crtc_state->mode_changed = true;
5929
5930 ret = drm_atomic_add_affected_connectors(state, crtc);
5931 if (ret)
5932 break;
5933
5934 ret = drm_atomic_add_affected_planes(state, crtc);
5935 if (ret)
5936 break;
5937 }
5938
5939 return ret;
5940 }
5941
5942 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5943 {
5944 unsigned int credits, default_credits;
5945
5946 if (IS_CHERRYVIEW(dev_priv))
5947 default_credits = PFI_CREDIT(12);
5948 else
5949 default_credits = PFI_CREDIT(8);
5950
5951 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5952 /* CHV suggested value is 31 or 63 */
5953 if (IS_CHERRYVIEW(dev_priv))
5954 credits = PFI_CREDIT_63;
5955 else
5956 credits = PFI_CREDIT(15);
5957 } else {
5958 credits = default_credits;
5959 }
5960
5961 /*
5962 * WA - write default credits before re-programming
5963 * FIXME: should we also set the resend bit here?
5964 */
5965 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5966 default_credits);
5967
5968 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5969 credits | PFI_CREDIT_RESEND);
5970
5971 /*
5972 * FIXME is this guaranteed to clear
5973 * immediately or should we poll for it?
5974 */
5975 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5976 }
5977
5978 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
5979 {
5980 struct drm_device *dev = old_state->dev;
5981 struct drm_i915_private *dev_priv = dev->dev_private;
5982 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
5983 int req_cdclk;
5984
5985 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5986 * never fail. */
5987 if (WARN_ON(max_pixclk < 0))
5988 return;
5989
5990 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5991
5992 if (req_cdclk != dev_priv->cdclk_freq) {
5993 /*
5994 * FIXME: We can end up here with all power domains off, yet
5995 * with a CDCLK frequency other than the minimum. To account
5996 * for this take the PIPE-A power domain, which covers the HW
5997 * blocks needed for the following programming. This can be
5998 * removed once it's guaranteed that we get here either with
5999 * the minimum CDCLK set, or the required power domains
6000 * enabled.
6001 */
6002 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6003
6004 if (IS_CHERRYVIEW(dev))
6005 cherryview_set_cdclk(dev, req_cdclk);
6006 else
6007 valleyview_set_cdclk(dev, req_cdclk);
6008
6009 vlv_program_pfi_credits(dev_priv);
6010
6011 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6012 }
6013 }
6014
6015 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6016 {
6017 struct drm_device *dev = crtc->dev;
6018 struct drm_i915_private *dev_priv = to_i915(dev);
6019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6020 struct intel_encoder *encoder;
6021 int pipe = intel_crtc->pipe;
6022 bool is_dsi;
6023
6024 if (WARN_ON(intel_crtc->active))
6025 return;
6026
6027 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6028
6029 if (!is_dsi) {
6030 if (IS_CHERRYVIEW(dev))
6031 chv_prepare_pll(intel_crtc, intel_crtc->config);
6032 else
6033 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6034 }
6035
6036 if (intel_crtc->config->has_dp_encoder)
6037 intel_dp_set_m_n(intel_crtc, M1_N1);
6038
6039 intel_set_pipe_timings(intel_crtc);
6040
6041 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6042 struct drm_i915_private *dev_priv = dev->dev_private;
6043
6044 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6045 I915_WRITE(CHV_CANVAS(pipe), 0);
6046 }
6047
6048 i9xx_set_pipeconf(intel_crtc);
6049
6050 intel_crtc->active = true;
6051
6052 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6053
6054 for_each_encoder_on_crtc(dev, crtc, encoder)
6055 if (encoder->pre_pll_enable)
6056 encoder->pre_pll_enable(encoder);
6057
6058 if (!is_dsi) {
6059 if (IS_CHERRYVIEW(dev))
6060 chv_enable_pll(intel_crtc, intel_crtc->config);
6061 else
6062 vlv_enable_pll(intel_crtc, intel_crtc->config);
6063 }
6064
6065 for_each_encoder_on_crtc(dev, crtc, encoder)
6066 if (encoder->pre_enable)
6067 encoder->pre_enable(encoder);
6068
6069 i9xx_pfit_enable(intel_crtc);
6070
6071 intel_crtc_load_lut(crtc);
6072
6073 intel_update_watermarks(crtc);
6074 intel_enable_pipe(intel_crtc);
6075
6076 assert_vblank_disabled(crtc);
6077 drm_crtc_vblank_on(crtc);
6078
6079 for_each_encoder_on_crtc(dev, crtc, encoder)
6080 encoder->enable(encoder);
6081 }
6082
6083 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6084 {
6085 struct drm_device *dev = crtc->base.dev;
6086 struct drm_i915_private *dev_priv = dev->dev_private;
6087
6088 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6089 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6090 }
6091
6092 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6093 {
6094 struct drm_device *dev = crtc->dev;
6095 struct drm_i915_private *dev_priv = to_i915(dev);
6096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6097 struct intel_encoder *encoder;
6098 int pipe = intel_crtc->pipe;
6099
6100 if (WARN_ON(intel_crtc->active))
6101 return;
6102
6103 i9xx_set_pll_dividers(intel_crtc);
6104
6105 if (intel_crtc->config->has_dp_encoder)
6106 intel_dp_set_m_n(intel_crtc, M1_N1);
6107
6108 intel_set_pipe_timings(intel_crtc);
6109
6110 i9xx_set_pipeconf(intel_crtc);
6111
6112 intel_crtc->active = true;
6113
6114 if (!IS_GEN2(dev))
6115 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6116
6117 for_each_encoder_on_crtc(dev, crtc, encoder)
6118 if (encoder->pre_enable)
6119 encoder->pre_enable(encoder);
6120
6121 i9xx_enable_pll(intel_crtc);
6122
6123 i9xx_pfit_enable(intel_crtc);
6124
6125 intel_crtc_load_lut(crtc);
6126
6127 intel_update_watermarks(crtc);
6128 intel_enable_pipe(intel_crtc);
6129
6130 assert_vblank_disabled(crtc);
6131 drm_crtc_vblank_on(crtc);
6132
6133 for_each_encoder_on_crtc(dev, crtc, encoder)
6134 encoder->enable(encoder);
6135 }
6136
6137 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6138 {
6139 struct drm_device *dev = crtc->base.dev;
6140 struct drm_i915_private *dev_priv = dev->dev_private;
6141
6142 if (!crtc->config->gmch_pfit.control)
6143 return;
6144
6145 assert_pipe_disabled(dev_priv, crtc->pipe);
6146
6147 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6148 I915_READ(PFIT_CONTROL));
6149 I915_WRITE(PFIT_CONTROL, 0);
6150 }
6151
6152 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6153 {
6154 struct drm_device *dev = crtc->dev;
6155 struct drm_i915_private *dev_priv = dev->dev_private;
6156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6157 struct intel_encoder *encoder;
6158 int pipe = intel_crtc->pipe;
6159
6160 if (WARN_ON(!intel_crtc->active))
6161 return;
6162
6163 /*
6164 * On gen2 planes are double buffered but the pipe isn't, so we must
6165 * wait for planes to fully turn off before disabling the pipe.
6166 * We also need to wait on all gmch platforms because of the
6167 * self-refresh mode constraint explained above.
6168 */
6169 intel_wait_for_vblank(dev, pipe);
6170
6171 for_each_encoder_on_crtc(dev, crtc, encoder)
6172 encoder->disable(encoder);
6173
6174 drm_crtc_vblank_off(crtc);
6175 assert_vblank_disabled(crtc);
6176
6177 intel_disable_pipe(intel_crtc);
6178
6179 i9xx_pfit_disable(intel_crtc);
6180
6181 for_each_encoder_on_crtc(dev, crtc, encoder)
6182 if (encoder->post_disable)
6183 encoder->post_disable(encoder);
6184
6185 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6186 if (IS_CHERRYVIEW(dev))
6187 chv_disable_pll(dev_priv, pipe);
6188 else if (IS_VALLEYVIEW(dev))
6189 vlv_disable_pll(dev_priv, pipe);
6190 else
6191 i9xx_disable_pll(intel_crtc);
6192 }
6193
6194 if (!IS_GEN2(dev))
6195 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6196
6197 intel_crtc->active = false;
6198 intel_update_watermarks(crtc);
6199
6200 mutex_lock(&dev->struct_mutex);
6201 intel_fbc_update(dev);
6202 mutex_unlock(&dev->struct_mutex);
6203 }
6204
6205 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6206 {
6207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6208 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6209 enum intel_display_power_domain domain;
6210 unsigned long domains;
6211
6212 if (!intel_crtc->active)
6213 return;
6214
6215 intel_crtc_disable_planes(crtc);
6216 dev_priv->display.crtc_disable(crtc);
6217
6218 domains = intel_crtc->enabled_power_domains;
6219 for_each_power_domain(domain, domains)
6220 intel_display_power_put(dev_priv, domain);
6221 intel_crtc->enabled_power_domains = 0;
6222 }
6223
6224 /*
6225 * turn all crtc's off, but do not adjust state
6226 * This has to be paired with a call to intel_modeset_setup_hw_state.
6227 */
6228 void intel_display_suspend(struct drm_device *dev)
6229 {
6230 struct drm_crtc *crtc;
6231
6232 for_each_crtc(dev, crtc)
6233 intel_crtc_disable_noatomic(crtc);
6234 }
6235
6236 /* Master function to enable/disable CRTC and corresponding power wells */
6237 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6238 {
6239 struct drm_device *dev = crtc->dev;
6240 struct drm_mode_config *config = &dev->mode_config;
6241 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6243 struct intel_crtc_state *pipe_config;
6244 struct drm_atomic_state *state;
6245 int ret;
6246
6247 if (enable == intel_crtc->active)
6248 return 0;
6249
6250 if (enable && !crtc->state->enable)
6251 return 0;
6252
6253 /* this function should be called with drm_modeset_lock_all for now */
6254 if (WARN_ON(!ctx))
6255 return -EIO;
6256 lockdep_assert_held(&ctx->ww_ctx);
6257
6258 state = drm_atomic_state_alloc(dev);
6259 if (WARN_ON(!state))
6260 return -ENOMEM;
6261
6262 state->acquire_ctx = ctx;
6263 state->allow_modeset = true;
6264
6265 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6266 if (IS_ERR(pipe_config)) {
6267 ret = PTR_ERR(pipe_config);
6268 goto err;
6269 }
6270 pipe_config->base.active = enable;
6271
6272 ret = intel_set_mode(state);
6273 if (!ret)
6274 return ret;
6275
6276 err:
6277 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6278 drm_atomic_state_free(state);
6279 return ret;
6280 }
6281
6282 /**
6283 * Sets the power management mode of the pipe and plane.
6284 */
6285 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6286 {
6287 struct drm_device *dev = crtc->dev;
6288 struct intel_encoder *intel_encoder;
6289 bool enable = false;
6290
6291 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6292 enable |= intel_encoder->connectors_active;
6293
6294 intel_crtc_control(crtc, enable);
6295 }
6296
6297 void intel_encoder_destroy(struct drm_encoder *encoder)
6298 {
6299 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6300
6301 drm_encoder_cleanup(encoder);
6302 kfree(intel_encoder);
6303 }
6304
6305 /* Simple dpms helper for encoders with just one connector, no cloning and only
6306 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6307 * state of the entire output pipe. */
6308 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6309 {
6310 if (mode == DRM_MODE_DPMS_ON) {
6311 encoder->connectors_active = true;
6312
6313 intel_crtc_update_dpms(encoder->base.crtc);
6314 } else {
6315 encoder->connectors_active = false;
6316
6317 intel_crtc_update_dpms(encoder->base.crtc);
6318 }
6319 }
6320
6321 /* Cross check the actual hw state with our own modeset state tracking (and it's
6322 * internal consistency). */
6323 static void intel_connector_check_state(struct intel_connector *connector)
6324 {
6325 if (connector->get_hw_state(connector)) {
6326 struct intel_encoder *encoder = connector->encoder;
6327 struct drm_crtc *crtc;
6328 bool encoder_enabled;
6329 enum pipe pipe;
6330
6331 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6332 connector->base.base.id,
6333 connector->base.name);
6334
6335 /* there is no real hw state for MST connectors */
6336 if (connector->mst_port)
6337 return;
6338
6339 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6340 "wrong connector dpms state\n");
6341 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6342 "active connector not linked to encoder\n");
6343
6344 if (encoder) {
6345 I915_STATE_WARN(!encoder->connectors_active,
6346 "encoder->connectors_active not set\n");
6347
6348 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6349 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6350 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6351 return;
6352
6353 crtc = encoder->base.crtc;
6354
6355 I915_STATE_WARN(!crtc->state->enable,
6356 "crtc not enabled\n");
6357 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6358 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6359 "encoder active on the wrong pipe\n");
6360 }
6361 }
6362 }
6363
6364 int intel_connector_init(struct intel_connector *connector)
6365 {
6366 struct drm_connector_state *connector_state;
6367
6368 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6369 if (!connector_state)
6370 return -ENOMEM;
6371
6372 connector->base.state = connector_state;
6373 return 0;
6374 }
6375
6376 struct intel_connector *intel_connector_alloc(void)
6377 {
6378 struct intel_connector *connector;
6379
6380 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6381 if (!connector)
6382 return NULL;
6383
6384 if (intel_connector_init(connector) < 0) {
6385 kfree(connector);
6386 return NULL;
6387 }
6388
6389 return connector;
6390 }
6391
6392 /* Even simpler default implementation, if there's really no special case to
6393 * consider. */
6394 void intel_connector_dpms(struct drm_connector *connector, int mode)
6395 {
6396 /* All the simple cases only support two dpms states. */
6397 if (mode != DRM_MODE_DPMS_ON)
6398 mode = DRM_MODE_DPMS_OFF;
6399
6400 if (mode == connector->dpms)
6401 return;
6402
6403 connector->dpms = mode;
6404
6405 /* Only need to change hw state when actually enabled */
6406 if (connector->encoder)
6407 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6408
6409 intel_modeset_check_state(connector->dev);
6410 }
6411
6412 /* Simple connector->get_hw_state implementation for encoders that support only
6413 * one connector and no cloning and hence the encoder state determines the state
6414 * of the connector. */
6415 bool intel_connector_get_hw_state(struct intel_connector *connector)
6416 {
6417 enum pipe pipe = 0;
6418 struct intel_encoder *encoder = connector->encoder;
6419
6420 return encoder->get_hw_state(encoder, &pipe);
6421 }
6422
6423 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6424 {
6425 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6426 return crtc_state->fdi_lanes;
6427
6428 return 0;
6429 }
6430
6431 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6432 struct intel_crtc_state *pipe_config)
6433 {
6434 struct drm_atomic_state *state = pipe_config->base.state;
6435 struct intel_crtc *other_crtc;
6436 struct intel_crtc_state *other_crtc_state;
6437
6438 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6439 pipe_name(pipe), pipe_config->fdi_lanes);
6440 if (pipe_config->fdi_lanes > 4) {
6441 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6442 pipe_name(pipe), pipe_config->fdi_lanes);
6443 return -EINVAL;
6444 }
6445
6446 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6447 if (pipe_config->fdi_lanes > 2) {
6448 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6449 pipe_config->fdi_lanes);
6450 return -EINVAL;
6451 } else {
6452 return 0;
6453 }
6454 }
6455
6456 if (INTEL_INFO(dev)->num_pipes == 2)
6457 return 0;
6458
6459 /* Ivybridge 3 pipe is really complicated */
6460 switch (pipe) {
6461 case PIPE_A:
6462 return 0;
6463 case PIPE_B:
6464 if (pipe_config->fdi_lanes <= 2)
6465 return 0;
6466
6467 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6468 other_crtc_state =
6469 intel_atomic_get_crtc_state(state, other_crtc);
6470 if (IS_ERR(other_crtc_state))
6471 return PTR_ERR(other_crtc_state);
6472
6473 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6474 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6475 pipe_name(pipe), pipe_config->fdi_lanes);
6476 return -EINVAL;
6477 }
6478 return 0;
6479 case PIPE_C:
6480 if (pipe_config->fdi_lanes > 2) {
6481 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6482 pipe_name(pipe), pipe_config->fdi_lanes);
6483 return -EINVAL;
6484 }
6485
6486 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6487 other_crtc_state =
6488 intel_atomic_get_crtc_state(state, other_crtc);
6489 if (IS_ERR(other_crtc_state))
6490 return PTR_ERR(other_crtc_state);
6491
6492 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6493 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6494 return -EINVAL;
6495 }
6496 return 0;
6497 default:
6498 BUG();
6499 }
6500 }
6501
6502 #define RETRY 1
6503 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6504 struct intel_crtc_state *pipe_config)
6505 {
6506 struct drm_device *dev = intel_crtc->base.dev;
6507 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6508 int lane, link_bw, fdi_dotclock, ret;
6509 bool needs_recompute = false;
6510
6511 retry:
6512 /* FDI is a binary signal running at ~2.7GHz, encoding
6513 * each output octet as 10 bits. The actual frequency
6514 * is stored as a divider into a 100MHz clock, and the
6515 * mode pixel clock is stored in units of 1KHz.
6516 * Hence the bw of each lane in terms of the mode signal
6517 * is:
6518 */
6519 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6520
6521 fdi_dotclock = adjusted_mode->crtc_clock;
6522
6523 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6524 pipe_config->pipe_bpp);
6525
6526 pipe_config->fdi_lanes = lane;
6527
6528 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6529 link_bw, &pipe_config->fdi_m_n);
6530
6531 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6532 intel_crtc->pipe, pipe_config);
6533 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6534 pipe_config->pipe_bpp -= 2*3;
6535 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6536 pipe_config->pipe_bpp);
6537 needs_recompute = true;
6538 pipe_config->bw_constrained = true;
6539
6540 goto retry;
6541 }
6542
6543 if (needs_recompute)
6544 return RETRY;
6545
6546 return ret;
6547 }
6548
6549 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6550 struct intel_crtc_state *pipe_config)
6551 {
6552 if (pipe_config->pipe_bpp > 24)
6553 return false;
6554
6555 /* HSW can handle pixel rate up to cdclk? */
6556 if (IS_HASWELL(dev_priv->dev))
6557 return true;
6558
6559 /*
6560 * We compare against max which means we must take
6561 * the increased cdclk requirement into account when
6562 * calculating the new cdclk.
6563 *
6564 * Should measure whether using a lower cdclk w/o IPS
6565 */
6566 return ilk_pipe_pixel_rate(pipe_config) <=
6567 dev_priv->max_cdclk_freq * 95 / 100;
6568 }
6569
6570 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6571 struct intel_crtc_state *pipe_config)
6572 {
6573 struct drm_device *dev = crtc->base.dev;
6574 struct drm_i915_private *dev_priv = dev->dev_private;
6575
6576 pipe_config->ips_enabled = i915.enable_ips &&
6577 hsw_crtc_supports_ips(crtc) &&
6578 pipe_config_supports_ips(dev_priv, pipe_config);
6579 }
6580
6581 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6582 struct intel_crtc_state *pipe_config)
6583 {
6584 struct drm_device *dev = crtc->base.dev;
6585 struct drm_i915_private *dev_priv = dev->dev_private;
6586 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6587 int ret;
6588
6589 /* FIXME should check pixel clock limits on all platforms */
6590 if (INTEL_INFO(dev)->gen < 4) {
6591 int clock_limit = dev_priv->max_cdclk_freq;
6592
6593 /*
6594 * Enable pixel doubling when the dot clock
6595 * is > 90% of the (display) core speed.
6596 *
6597 * GDG double wide on either pipe,
6598 * otherwise pipe A only.
6599 */
6600 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6601 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6602 clock_limit *= 2;
6603 pipe_config->double_wide = true;
6604 }
6605
6606 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6607 return -EINVAL;
6608 }
6609
6610 /*
6611 * Pipe horizontal size must be even in:
6612 * - DVO ganged mode
6613 * - LVDS dual channel mode
6614 * - Double wide pipe
6615 */
6616 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6617 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6618 pipe_config->pipe_src_w &= ~1;
6619
6620 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6621 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6622 */
6623 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6624 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6625 return -EINVAL;
6626
6627 if (HAS_IPS(dev))
6628 hsw_compute_ips_config(crtc, pipe_config);
6629
6630 if (pipe_config->has_pch_encoder)
6631 return ironlake_fdi_compute_config(crtc, pipe_config);
6632
6633 /* FIXME: remove below call once atomic mode set is place and all crtc
6634 * related checks called from atomic_crtc_check function */
6635 ret = 0;
6636 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6637 crtc, pipe_config->base.state);
6638 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6639
6640 return ret;
6641 }
6642
6643 static int skylake_get_display_clock_speed(struct drm_device *dev)
6644 {
6645 struct drm_i915_private *dev_priv = to_i915(dev);
6646 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6647 uint32_t cdctl = I915_READ(CDCLK_CTL);
6648 uint32_t linkrate;
6649
6650 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6651 return 24000; /* 24MHz is the cd freq with NSSC ref */
6652
6653 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6654 return 540000;
6655
6656 linkrate = (I915_READ(DPLL_CTRL1) &
6657 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6658
6659 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6660 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6661 /* vco 8640 */
6662 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6663 case CDCLK_FREQ_450_432:
6664 return 432000;
6665 case CDCLK_FREQ_337_308:
6666 return 308570;
6667 case CDCLK_FREQ_675_617:
6668 return 617140;
6669 default:
6670 WARN(1, "Unknown cd freq selection\n");
6671 }
6672 } else {
6673 /* vco 8100 */
6674 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6675 case CDCLK_FREQ_450_432:
6676 return 450000;
6677 case CDCLK_FREQ_337_308:
6678 return 337500;
6679 case CDCLK_FREQ_675_617:
6680 return 675000;
6681 default:
6682 WARN(1, "Unknown cd freq selection\n");
6683 }
6684 }
6685
6686 /* error case, do as if DPLL0 isn't enabled */
6687 return 24000;
6688 }
6689
6690 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6691 {
6692 struct drm_i915_private *dev_priv = dev->dev_private;
6693 uint32_t lcpll = I915_READ(LCPLL_CTL);
6694 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6695
6696 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6697 return 800000;
6698 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6699 return 450000;
6700 else if (freq == LCPLL_CLK_FREQ_450)
6701 return 450000;
6702 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6703 return 540000;
6704 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6705 return 337500;
6706 else
6707 return 675000;
6708 }
6709
6710 static int haswell_get_display_clock_speed(struct drm_device *dev)
6711 {
6712 struct drm_i915_private *dev_priv = dev->dev_private;
6713 uint32_t lcpll = I915_READ(LCPLL_CTL);
6714 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6715
6716 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6717 return 800000;
6718 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6719 return 450000;
6720 else if (freq == LCPLL_CLK_FREQ_450)
6721 return 450000;
6722 else if (IS_HSW_ULT(dev))
6723 return 337500;
6724 else
6725 return 540000;
6726 }
6727
6728 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6729 {
6730 struct drm_i915_private *dev_priv = dev->dev_private;
6731 u32 val;
6732 int divider;
6733
6734 if (dev_priv->hpll_freq == 0)
6735 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6736
6737 mutex_lock(&dev_priv->sb_lock);
6738 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6739 mutex_unlock(&dev_priv->sb_lock);
6740
6741 divider = val & DISPLAY_FREQUENCY_VALUES;
6742
6743 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6744 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6745 "cdclk change in progress\n");
6746
6747 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6748 }
6749
6750 static int ilk_get_display_clock_speed(struct drm_device *dev)
6751 {
6752 return 450000;
6753 }
6754
6755 static int i945_get_display_clock_speed(struct drm_device *dev)
6756 {
6757 return 400000;
6758 }
6759
6760 static int i915_get_display_clock_speed(struct drm_device *dev)
6761 {
6762 return 333333;
6763 }
6764
6765 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6766 {
6767 return 200000;
6768 }
6769
6770 static int pnv_get_display_clock_speed(struct drm_device *dev)
6771 {
6772 u16 gcfgc = 0;
6773
6774 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6775
6776 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6777 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6778 return 266667;
6779 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6780 return 333333;
6781 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6782 return 444444;
6783 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6784 return 200000;
6785 default:
6786 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6787 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6788 return 133333;
6789 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6790 return 166667;
6791 }
6792 }
6793
6794 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6795 {
6796 u16 gcfgc = 0;
6797
6798 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6799
6800 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6801 return 133333;
6802 else {
6803 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6804 case GC_DISPLAY_CLOCK_333_MHZ:
6805 return 333333;
6806 default:
6807 case GC_DISPLAY_CLOCK_190_200_MHZ:
6808 return 190000;
6809 }
6810 }
6811 }
6812
6813 static int i865_get_display_clock_speed(struct drm_device *dev)
6814 {
6815 return 266667;
6816 }
6817
6818 static int i85x_get_display_clock_speed(struct drm_device *dev)
6819 {
6820 u16 hpllcc = 0;
6821
6822 /*
6823 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6824 * encoding is different :(
6825 * FIXME is this the right way to detect 852GM/852GMV?
6826 */
6827 if (dev->pdev->revision == 0x1)
6828 return 133333;
6829
6830 pci_bus_read_config_word(dev->pdev->bus,
6831 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6832
6833 /* Assume that the hardware is in the high speed state. This
6834 * should be the default.
6835 */
6836 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6837 case GC_CLOCK_133_200:
6838 case GC_CLOCK_133_200_2:
6839 case GC_CLOCK_100_200:
6840 return 200000;
6841 case GC_CLOCK_166_250:
6842 return 250000;
6843 case GC_CLOCK_100_133:
6844 return 133333;
6845 case GC_CLOCK_133_266:
6846 case GC_CLOCK_133_266_2:
6847 case GC_CLOCK_166_266:
6848 return 266667;
6849 }
6850
6851 /* Shouldn't happen */
6852 return 0;
6853 }
6854
6855 static int i830_get_display_clock_speed(struct drm_device *dev)
6856 {
6857 return 133333;
6858 }
6859
6860 static unsigned int intel_hpll_vco(struct drm_device *dev)
6861 {
6862 struct drm_i915_private *dev_priv = dev->dev_private;
6863 static const unsigned int blb_vco[8] = {
6864 [0] = 3200000,
6865 [1] = 4000000,
6866 [2] = 5333333,
6867 [3] = 4800000,
6868 [4] = 6400000,
6869 };
6870 static const unsigned int pnv_vco[8] = {
6871 [0] = 3200000,
6872 [1] = 4000000,
6873 [2] = 5333333,
6874 [3] = 4800000,
6875 [4] = 2666667,
6876 };
6877 static const unsigned int cl_vco[8] = {
6878 [0] = 3200000,
6879 [1] = 4000000,
6880 [2] = 5333333,
6881 [3] = 6400000,
6882 [4] = 3333333,
6883 [5] = 3566667,
6884 [6] = 4266667,
6885 };
6886 static const unsigned int elk_vco[8] = {
6887 [0] = 3200000,
6888 [1] = 4000000,
6889 [2] = 5333333,
6890 [3] = 4800000,
6891 };
6892 static const unsigned int ctg_vco[8] = {
6893 [0] = 3200000,
6894 [1] = 4000000,
6895 [2] = 5333333,
6896 [3] = 6400000,
6897 [4] = 2666667,
6898 [5] = 4266667,
6899 };
6900 const unsigned int *vco_table;
6901 unsigned int vco;
6902 uint8_t tmp = 0;
6903
6904 /* FIXME other chipsets? */
6905 if (IS_GM45(dev))
6906 vco_table = ctg_vco;
6907 else if (IS_G4X(dev))
6908 vco_table = elk_vco;
6909 else if (IS_CRESTLINE(dev))
6910 vco_table = cl_vco;
6911 else if (IS_PINEVIEW(dev))
6912 vco_table = pnv_vco;
6913 else if (IS_G33(dev))
6914 vco_table = blb_vco;
6915 else
6916 return 0;
6917
6918 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6919
6920 vco = vco_table[tmp & 0x7];
6921 if (vco == 0)
6922 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6923 else
6924 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6925
6926 return vco;
6927 }
6928
6929 static int gm45_get_display_clock_speed(struct drm_device *dev)
6930 {
6931 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6932 uint16_t tmp = 0;
6933
6934 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6935
6936 cdclk_sel = (tmp >> 12) & 0x1;
6937
6938 switch (vco) {
6939 case 2666667:
6940 case 4000000:
6941 case 5333333:
6942 return cdclk_sel ? 333333 : 222222;
6943 case 3200000:
6944 return cdclk_sel ? 320000 : 228571;
6945 default:
6946 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6947 return 222222;
6948 }
6949 }
6950
6951 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6952 {
6953 static const uint8_t div_3200[] = { 16, 10, 8 };
6954 static const uint8_t div_4000[] = { 20, 12, 10 };
6955 static const uint8_t div_5333[] = { 24, 16, 14 };
6956 const uint8_t *div_table;
6957 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6958 uint16_t tmp = 0;
6959
6960 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6961
6962 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6963
6964 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6965 goto fail;
6966
6967 switch (vco) {
6968 case 3200000:
6969 div_table = div_3200;
6970 break;
6971 case 4000000:
6972 div_table = div_4000;
6973 break;
6974 case 5333333:
6975 div_table = div_5333;
6976 break;
6977 default:
6978 goto fail;
6979 }
6980
6981 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6982
6983 fail:
6984 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6985 return 200000;
6986 }
6987
6988 static int g33_get_display_clock_speed(struct drm_device *dev)
6989 {
6990 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6991 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6992 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6993 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6994 const uint8_t *div_table;
6995 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6996 uint16_t tmp = 0;
6997
6998 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6999
7000 cdclk_sel = (tmp >> 4) & 0x7;
7001
7002 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7003 goto fail;
7004
7005 switch (vco) {
7006 case 3200000:
7007 div_table = div_3200;
7008 break;
7009 case 4000000:
7010 div_table = div_4000;
7011 break;
7012 case 4800000:
7013 div_table = div_4800;
7014 break;
7015 case 5333333:
7016 div_table = div_5333;
7017 break;
7018 default:
7019 goto fail;
7020 }
7021
7022 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7023
7024 fail:
7025 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7026 return 190476;
7027 }
7028
7029 static void
7030 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7031 {
7032 while (*num > DATA_LINK_M_N_MASK ||
7033 *den > DATA_LINK_M_N_MASK) {
7034 *num >>= 1;
7035 *den >>= 1;
7036 }
7037 }
7038
7039 static void compute_m_n(unsigned int m, unsigned int n,
7040 uint32_t *ret_m, uint32_t *ret_n)
7041 {
7042 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7043 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7044 intel_reduce_m_n_ratio(ret_m, ret_n);
7045 }
7046
7047 void
7048 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7049 int pixel_clock, int link_clock,
7050 struct intel_link_m_n *m_n)
7051 {
7052 m_n->tu = 64;
7053
7054 compute_m_n(bits_per_pixel * pixel_clock,
7055 link_clock * nlanes * 8,
7056 &m_n->gmch_m, &m_n->gmch_n);
7057
7058 compute_m_n(pixel_clock, link_clock,
7059 &m_n->link_m, &m_n->link_n);
7060 }
7061
7062 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7063 {
7064 if (i915.panel_use_ssc >= 0)
7065 return i915.panel_use_ssc != 0;
7066 return dev_priv->vbt.lvds_use_ssc
7067 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7068 }
7069
7070 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7071 int num_connectors)
7072 {
7073 struct drm_device *dev = crtc_state->base.crtc->dev;
7074 struct drm_i915_private *dev_priv = dev->dev_private;
7075 int refclk;
7076
7077 WARN_ON(!crtc_state->base.state);
7078
7079 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7080 refclk = 100000;
7081 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7082 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7083 refclk = dev_priv->vbt.lvds_ssc_freq;
7084 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7085 } else if (!IS_GEN2(dev)) {
7086 refclk = 96000;
7087 } else {
7088 refclk = 48000;
7089 }
7090
7091 return refclk;
7092 }
7093
7094 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7095 {
7096 return (1 << dpll->n) << 16 | dpll->m2;
7097 }
7098
7099 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7100 {
7101 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7102 }
7103
7104 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7105 struct intel_crtc_state *crtc_state,
7106 intel_clock_t *reduced_clock)
7107 {
7108 struct drm_device *dev = crtc->base.dev;
7109 u32 fp, fp2 = 0;
7110
7111 if (IS_PINEVIEW(dev)) {
7112 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7113 if (reduced_clock)
7114 fp2 = pnv_dpll_compute_fp(reduced_clock);
7115 } else {
7116 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7117 if (reduced_clock)
7118 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7119 }
7120
7121 crtc_state->dpll_hw_state.fp0 = fp;
7122
7123 crtc->lowfreq_avail = false;
7124 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7125 reduced_clock) {
7126 crtc_state->dpll_hw_state.fp1 = fp2;
7127 crtc->lowfreq_avail = true;
7128 } else {
7129 crtc_state->dpll_hw_state.fp1 = fp;
7130 }
7131 }
7132
7133 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7134 pipe)
7135 {
7136 u32 reg_val;
7137
7138 /*
7139 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7140 * and set it to a reasonable value instead.
7141 */
7142 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7143 reg_val &= 0xffffff00;
7144 reg_val |= 0x00000030;
7145 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7146
7147 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7148 reg_val &= 0x8cffffff;
7149 reg_val = 0x8c000000;
7150 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7151
7152 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7153 reg_val &= 0xffffff00;
7154 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7155
7156 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7157 reg_val &= 0x00ffffff;
7158 reg_val |= 0xb0000000;
7159 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7160 }
7161
7162 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7163 struct intel_link_m_n *m_n)
7164 {
7165 struct drm_device *dev = crtc->base.dev;
7166 struct drm_i915_private *dev_priv = dev->dev_private;
7167 int pipe = crtc->pipe;
7168
7169 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7170 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7171 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7172 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7173 }
7174
7175 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7176 struct intel_link_m_n *m_n,
7177 struct intel_link_m_n *m2_n2)
7178 {
7179 struct drm_device *dev = crtc->base.dev;
7180 struct drm_i915_private *dev_priv = dev->dev_private;
7181 int pipe = crtc->pipe;
7182 enum transcoder transcoder = crtc->config->cpu_transcoder;
7183
7184 if (INTEL_INFO(dev)->gen >= 5) {
7185 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7186 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7187 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7188 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7189 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7190 * for gen < 8) and if DRRS is supported (to make sure the
7191 * registers are not unnecessarily accessed).
7192 */
7193 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7194 crtc->config->has_drrs) {
7195 I915_WRITE(PIPE_DATA_M2(transcoder),
7196 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7197 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7198 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7199 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7200 }
7201 } else {
7202 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7203 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7204 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7205 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7206 }
7207 }
7208
7209 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7210 {
7211 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7212
7213 if (m_n == M1_N1) {
7214 dp_m_n = &crtc->config->dp_m_n;
7215 dp_m2_n2 = &crtc->config->dp_m2_n2;
7216 } else if (m_n == M2_N2) {
7217
7218 /*
7219 * M2_N2 registers are not supported. Hence m2_n2 divider value
7220 * needs to be programmed into M1_N1.
7221 */
7222 dp_m_n = &crtc->config->dp_m2_n2;
7223 } else {
7224 DRM_ERROR("Unsupported divider value\n");
7225 return;
7226 }
7227
7228 if (crtc->config->has_pch_encoder)
7229 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7230 else
7231 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7232 }
7233
7234 static void vlv_update_pll(struct intel_crtc *crtc,
7235 struct intel_crtc_state *pipe_config)
7236 {
7237 u32 dpll, dpll_md;
7238
7239 /*
7240 * Enable DPIO clock input. We should never disable the reference
7241 * clock for pipe B, since VGA hotplug / manual detection depends
7242 * on it.
7243 */
7244 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7245 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7246 /* We should never disable this, set it here for state tracking */
7247 if (crtc->pipe == PIPE_B)
7248 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7249 dpll |= DPLL_VCO_ENABLE;
7250 pipe_config->dpll_hw_state.dpll = dpll;
7251
7252 dpll_md = (pipe_config->pixel_multiplier - 1)
7253 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7254 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7255 }
7256
7257 static void vlv_prepare_pll(struct intel_crtc *crtc,
7258 const struct intel_crtc_state *pipe_config)
7259 {
7260 struct drm_device *dev = crtc->base.dev;
7261 struct drm_i915_private *dev_priv = dev->dev_private;
7262 int pipe = crtc->pipe;
7263 u32 mdiv;
7264 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7265 u32 coreclk, reg_val;
7266
7267 mutex_lock(&dev_priv->sb_lock);
7268
7269 bestn = pipe_config->dpll.n;
7270 bestm1 = pipe_config->dpll.m1;
7271 bestm2 = pipe_config->dpll.m2;
7272 bestp1 = pipe_config->dpll.p1;
7273 bestp2 = pipe_config->dpll.p2;
7274
7275 /* See eDP HDMI DPIO driver vbios notes doc */
7276
7277 /* PLL B needs special handling */
7278 if (pipe == PIPE_B)
7279 vlv_pllb_recal_opamp(dev_priv, pipe);
7280
7281 /* Set up Tx target for periodic Rcomp update */
7282 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7283
7284 /* Disable target IRef on PLL */
7285 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7286 reg_val &= 0x00ffffff;
7287 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7288
7289 /* Disable fast lock */
7290 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7291
7292 /* Set idtafcrecal before PLL is enabled */
7293 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7294 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7295 mdiv |= ((bestn << DPIO_N_SHIFT));
7296 mdiv |= (1 << DPIO_K_SHIFT);
7297
7298 /*
7299 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7300 * but we don't support that).
7301 * Note: don't use the DAC post divider as it seems unstable.
7302 */
7303 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7304 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7305
7306 mdiv |= DPIO_ENABLE_CALIBRATION;
7307 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7308
7309 /* Set HBR and RBR LPF coefficients */
7310 if (pipe_config->port_clock == 162000 ||
7311 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7312 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7313 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7314 0x009f0003);
7315 else
7316 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7317 0x00d0000f);
7318
7319 if (pipe_config->has_dp_encoder) {
7320 /* Use SSC source */
7321 if (pipe == PIPE_A)
7322 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7323 0x0df40000);
7324 else
7325 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7326 0x0df70000);
7327 } else { /* HDMI or VGA */
7328 /* Use bend source */
7329 if (pipe == PIPE_A)
7330 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7331 0x0df70000);
7332 else
7333 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7334 0x0df40000);
7335 }
7336
7337 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7338 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7339 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7340 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7341 coreclk |= 0x01000000;
7342 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7343
7344 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7345 mutex_unlock(&dev_priv->sb_lock);
7346 }
7347
7348 static void chv_update_pll(struct intel_crtc *crtc,
7349 struct intel_crtc_state *pipe_config)
7350 {
7351 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7352 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7353 DPLL_VCO_ENABLE;
7354 if (crtc->pipe != PIPE_A)
7355 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7356
7357 pipe_config->dpll_hw_state.dpll_md =
7358 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7359 }
7360
7361 static void chv_prepare_pll(struct intel_crtc *crtc,
7362 const struct intel_crtc_state *pipe_config)
7363 {
7364 struct drm_device *dev = crtc->base.dev;
7365 struct drm_i915_private *dev_priv = dev->dev_private;
7366 int pipe = crtc->pipe;
7367 int dpll_reg = DPLL(crtc->pipe);
7368 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7369 u32 loopfilter, tribuf_calcntr;
7370 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7371 u32 dpio_val;
7372 int vco;
7373
7374 bestn = pipe_config->dpll.n;
7375 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7376 bestm1 = pipe_config->dpll.m1;
7377 bestm2 = pipe_config->dpll.m2 >> 22;
7378 bestp1 = pipe_config->dpll.p1;
7379 bestp2 = pipe_config->dpll.p2;
7380 vco = pipe_config->dpll.vco;
7381 dpio_val = 0;
7382 loopfilter = 0;
7383
7384 /*
7385 * Enable Refclk and SSC
7386 */
7387 I915_WRITE(dpll_reg,
7388 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7389
7390 mutex_lock(&dev_priv->sb_lock);
7391
7392 /* p1 and p2 divider */
7393 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7394 5 << DPIO_CHV_S1_DIV_SHIFT |
7395 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7396 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7397 1 << DPIO_CHV_K_DIV_SHIFT);
7398
7399 /* Feedback post-divider - m2 */
7400 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7401
7402 /* Feedback refclk divider - n and m1 */
7403 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7404 DPIO_CHV_M1_DIV_BY_2 |
7405 1 << DPIO_CHV_N_DIV_SHIFT);
7406
7407 /* M2 fraction division */
7408 if (bestm2_frac)
7409 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7410
7411 /* M2 fraction division enable */
7412 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7413 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7414 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7415 if (bestm2_frac)
7416 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7417 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7418
7419 /* Program digital lock detect threshold */
7420 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7421 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7422 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7423 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7424 if (!bestm2_frac)
7425 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7426 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7427
7428 /* Loop filter */
7429 if (vco == 5400000) {
7430 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7431 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7432 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7433 tribuf_calcntr = 0x9;
7434 } else if (vco <= 6200000) {
7435 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7436 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7437 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7438 tribuf_calcntr = 0x9;
7439 } else if (vco <= 6480000) {
7440 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7441 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7442 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7443 tribuf_calcntr = 0x8;
7444 } else {
7445 /* Not supported. Apply the same limits as in the max case */
7446 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7447 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7448 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7449 tribuf_calcntr = 0;
7450 }
7451 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7452
7453 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7454 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7455 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7456 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7457
7458 /* AFC Recal */
7459 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7460 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7461 DPIO_AFC_RECAL);
7462
7463 mutex_unlock(&dev_priv->sb_lock);
7464 }
7465
7466 /**
7467 * vlv_force_pll_on - forcibly enable just the PLL
7468 * @dev_priv: i915 private structure
7469 * @pipe: pipe PLL to enable
7470 * @dpll: PLL configuration
7471 *
7472 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7473 * in cases where we need the PLL enabled even when @pipe is not going to
7474 * be enabled.
7475 */
7476 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7477 const struct dpll *dpll)
7478 {
7479 struct intel_crtc *crtc =
7480 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7481 struct intel_crtc_state pipe_config = {
7482 .base.crtc = &crtc->base,
7483 .pixel_multiplier = 1,
7484 .dpll = *dpll,
7485 };
7486
7487 if (IS_CHERRYVIEW(dev)) {
7488 chv_update_pll(crtc, &pipe_config);
7489 chv_prepare_pll(crtc, &pipe_config);
7490 chv_enable_pll(crtc, &pipe_config);
7491 } else {
7492 vlv_update_pll(crtc, &pipe_config);
7493 vlv_prepare_pll(crtc, &pipe_config);
7494 vlv_enable_pll(crtc, &pipe_config);
7495 }
7496 }
7497
7498 /**
7499 * vlv_force_pll_off - forcibly disable just the PLL
7500 * @dev_priv: i915 private structure
7501 * @pipe: pipe PLL to disable
7502 *
7503 * Disable the PLL for @pipe. To be used in cases where we need
7504 * the PLL enabled even when @pipe is not going to be enabled.
7505 */
7506 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7507 {
7508 if (IS_CHERRYVIEW(dev))
7509 chv_disable_pll(to_i915(dev), pipe);
7510 else
7511 vlv_disable_pll(to_i915(dev), pipe);
7512 }
7513
7514 static void i9xx_update_pll(struct intel_crtc *crtc,
7515 struct intel_crtc_state *crtc_state,
7516 intel_clock_t *reduced_clock,
7517 int num_connectors)
7518 {
7519 struct drm_device *dev = crtc->base.dev;
7520 struct drm_i915_private *dev_priv = dev->dev_private;
7521 u32 dpll;
7522 bool is_sdvo;
7523 struct dpll *clock = &crtc_state->dpll;
7524
7525 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7526
7527 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7528 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7529
7530 dpll = DPLL_VGA_MODE_DIS;
7531
7532 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7533 dpll |= DPLLB_MODE_LVDS;
7534 else
7535 dpll |= DPLLB_MODE_DAC_SERIAL;
7536
7537 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7538 dpll |= (crtc_state->pixel_multiplier - 1)
7539 << SDVO_MULTIPLIER_SHIFT_HIRES;
7540 }
7541
7542 if (is_sdvo)
7543 dpll |= DPLL_SDVO_HIGH_SPEED;
7544
7545 if (crtc_state->has_dp_encoder)
7546 dpll |= DPLL_SDVO_HIGH_SPEED;
7547
7548 /* compute bitmask from p1 value */
7549 if (IS_PINEVIEW(dev))
7550 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7551 else {
7552 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7553 if (IS_G4X(dev) && reduced_clock)
7554 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7555 }
7556 switch (clock->p2) {
7557 case 5:
7558 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7559 break;
7560 case 7:
7561 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7562 break;
7563 case 10:
7564 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7565 break;
7566 case 14:
7567 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7568 break;
7569 }
7570 if (INTEL_INFO(dev)->gen >= 4)
7571 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7572
7573 if (crtc_state->sdvo_tv_clock)
7574 dpll |= PLL_REF_INPUT_TVCLKINBC;
7575 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7576 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7577 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7578 else
7579 dpll |= PLL_REF_INPUT_DREFCLK;
7580
7581 dpll |= DPLL_VCO_ENABLE;
7582 crtc_state->dpll_hw_state.dpll = dpll;
7583
7584 if (INTEL_INFO(dev)->gen >= 4) {
7585 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7586 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7587 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7588 }
7589 }
7590
7591 static void i8xx_update_pll(struct intel_crtc *crtc,
7592 struct intel_crtc_state *crtc_state,
7593 intel_clock_t *reduced_clock,
7594 int num_connectors)
7595 {
7596 struct drm_device *dev = crtc->base.dev;
7597 struct drm_i915_private *dev_priv = dev->dev_private;
7598 u32 dpll;
7599 struct dpll *clock = &crtc_state->dpll;
7600
7601 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7602
7603 dpll = DPLL_VGA_MODE_DIS;
7604
7605 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7606 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7607 } else {
7608 if (clock->p1 == 2)
7609 dpll |= PLL_P1_DIVIDE_BY_TWO;
7610 else
7611 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7612 if (clock->p2 == 4)
7613 dpll |= PLL_P2_DIVIDE_BY_4;
7614 }
7615
7616 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7617 dpll |= DPLL_DVO_2X_MODE;
7618
7619 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7620 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7621 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7622 else
7623 dpll |= PLL_REF_INPUT_DREFCLK;
7624
7625 dpll |= DPLL_VCO_ENABLE;
7626 crtc_state->dpll_hw_state.dpll = dpll;
7627 }
7628
7629 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7630 {
7631 struct drm_device *dev = intel_crtc->base.dev;
7632 struct drm_i915_private *dev_priv = dev->dev_private;
7633 enum pipe pipe = intel_crtc->pipe;
7634 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7635 struct drm_display_mode *adjusted_mode =
7636 &intel_crtc->config->base.adjusted_mode;
7637 uint32_t crtc_vtotal, crtc_vblank_end;
7638 int vsyncshift = 0;
7639
7640 /* We need to be careful not to changed the adjusted mode, for otherwise
7641 * the hw state checker will get angry at the mismatch. */
7642 crtc_vtotal = adjusted_mode->crtc_vtotal;
7643 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7644
7645 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7646 /* the chip adds 2 halflines automatically */
7647 crtc_vtotal -= 1;
7648 crtc_vblank_end -= 1;
7649
7650 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7651 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7652 else
7653 vsyncshift = adjusted_mode->crtc_hsync_start -
7654 adjusted_mode->crtc_htotal / 2;
7655 if (vsyncshift < 0)
7656 vsyncshift += adjusted_mode->crtc_htotal;
7657 }
7658
7659 if (INTEL_INFO(dev)->gen > 3)
7660 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7661
7662 I915_WRITE(HTOTAL(cpu_transcoder),
7663 (adjusted_mode->crtc_hdisplay - 1) |
7664 ((adjusted_mode->crtc_htotal - 1) << 16));
7665 I915_WRITE(HBLANK(cpu_transcoder),
7666 (adjusted_mode->crtc_hblank_start - 1) |
7667 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7668 I915_WRITE(HSYNC(cpu_transcoder),
7669 (adjusted_mode->crtc_hsync_start - 1) |
7670 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7671
7672 I915_WRITE(VTOTAL(cpu_transcoder),
7673 (adjusted_mode->crtc_vdisplay - 1) |
7674 ((crtc_vtotal - 1) << 16));
7675 I915_WRITE(VBLANK(cpu_transcoder),
7676 (adjusted_mode->crtc_vblank_start - 1) |
7677 ((crtc_vblank_end - 1) << 16));
7678 I915_WRITE(VSYNC(cpu_transcoder),
7679 (adjusted_mode->crtc_vsync_start - 1) |
7680 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7681
7682 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7683 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7684 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7685 * bits. */
7686 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7687 (pipe == PIPE_B || pipe == PIPE_C))
7688 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7689
7690 /* pipesrc controls the size that is scaled from, which should
7691 * always be the user's requested size.
7692 */
7693 I915_WRITE(PIPESRC(pipe),
7694 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7695 (intel_crtc->config->pipe_src_h - 1));
7696 }
7697
7698 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7699 struct intel_crtc_state *pipe_config)
7700 {
7701 struct drm_device *dev = crtc->base.dev;
7702 struct drm_i915_private *dev_priv = dev->dev_private;
7703 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7704 uint32_t tmp;
7705
7706 tmp = I915_READ(HTOTAL(cpu_transcoder));
7707 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7708 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7709 tmp = I915_READ(HBLANK(cpu_transcoder));
7710 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7711 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7712 tmp = I915_READ(HSYNC(cpu_transcoder));
7713 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7714 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7715
7716 tmp = I915_READ(VTOTAL(cpu_transcoder));
7717 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7718 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7719 tmp = I915_READ(VBLANK(cpu_transcoder));
7720 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7721 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7722 tmp = I915_READ(VSYNC(cpu_transcoder));
7723 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7724 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7725
7726 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7727 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7728 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7729 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7730 }
7731
7732 tmp = I915_READ(PIPESRC(crtc->pipe));
7733 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7734 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7735
7736 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7737 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7738 }
7739
7740 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7741 struct intel_crtc_state *pipe_config)
7742 {
7743 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7744 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7745 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7746 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7747
7748 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7749 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7750 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7751 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7752
7753 mode->flags = pipe_config->base.adjusted_mode.flags;
7754
7755 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7756 mode->flags |= pipe_config->base.adjusted_mode.flags;
7757 }
7758
7759 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7760 {
7761 struct drm_device *dev = intel_crtc->base.dev;
7762 struct drm_i915_private *dev_priv = dev->dev_private;
7763 uint32_t pipeconf;
7764
7765 pipeconf = 0;
7766
7767 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7768 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7769 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7770
7771 if (intel_crtc->config->double_wide)
7772 pipeconf |= PIPECONF_DOUBLE_WIDE;
7773
7774 /* only g4x and later have fancy bpc/dither controls */
7775 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7776 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7777 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7778 pipeconf |= PIPECONF_DITHER_EN |
7779 PIPECONF_DITHER_TYPE_SP;
7780
7781 switch (intel_crtc->config->pipe_bpp) {
7782 case 18:
7783 pipeconf |= PIPECONF_6BPC;
7784 break;
7785 case 24:
7786 pipeconf |= PIPECONF_8BPC;
7787 break;
7788 case 30:
7789 pipeconf |= PIPECONF_10BPC;
7790 break;
7791 default:
7792 /* Case prevented by intel_choose_pipe_bpp_dither. */
7793 BUG();
7794 }
7795 }
7796
7797 if (HAS_PIPE_CXSR(dev)) {
7798 if (intel_crtc->lowfreq_avail) {
7799 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7800 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7801 } else {
7802 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7803 }
7804 }
7805
7806 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7807 if (INTEL_INFO(dev)->gen < 4 ||
7808 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7809 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7810 else
7811 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7812 } else
7813 pipeconf |= PIPECONF_PROGRESSIVE;
7814
7815 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7816 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7817
7818 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7819 POSTING_READ(PIPECONF(intel_crtc->pipe));
7820 }
7821
7822 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7823 struct intel_crtc_state *crtc_state)
7824 {
7825 struct drm_device *dev = crtc->base.dev;
7826 struct drm_i915_private *dev_priv = dev->dev_private;
7827 int refclk, num_connectors = 0;
7828 intel_clock_t clock, reduced_clock;
7829 bool ok, has_reduced_clock = false;
7830 bool is_lvds = false, is_dsi = false;
7831 struct intel_encoder *encoder;
7832 const intel_limit_t *limit;
7833 struct drm_atomic_state *state = crtc_state->base.state;
7834 struct drm_connector *connector;
7835 struct drm_connector_state *connector_state;
7836 int i;
7837
7838 memset(&crtc_state->dpll_hw_state, 0,
7839 sizeof(crtc_state->dpll_hw_state));
7840
7841 for_each_connector_in_state(state, connector, connector_state, i) {
7842 if (connector_state->crtc != &crtc->base)
7843 continue;
7844
7845 encoder = to_intel_encoder(connector_state->best_encoder);
7846
7847 switch (encoder->type) {
7848 case INTEL_OUTPUT_LVDS:
7849 is_lvds = true;
7850 break;
7851 case INTEL_OUTPUT_DSI:
7852 is_dsi = true;
7853 break;
7854 default:
7855 break;
7856 }
7857
7858 num_connectors++;
7859 }
7860
7861 if (is_dsi)
7862 return 0;
7863
7864 if (!crtc_state->clock_set) {
7865 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7866
7867 /*
7868 * Returns a set of divisors for the desired target clock with
7869 * the given refclk, or FALSE. The returned values represent
7870 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7871 * 2) / p1 / p2.
7872 */
7873 limit = intel_limit(crtc_state, refclk);
7874 ok = dev_priv->display.find_dpll(limit, crtc_state,
7875 crtc_state->port_clock,
7876 refclk, NULL, &clock);
7877 if (!ok) {
7878 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7879 return -EINVAL;
7880 }
7881
7882 if (is_lvds && dev_priv->lvds_downclock_avail) {
7883 /*
7884 * Ensure we match the reduced clock's P to the target
7885 * clock. If the clocks don't match, we can't switch
7886 * the display clock by using the FP0/FP1. In such case
7887 * we will disable the LVDS downclock feature.
7888 */
7889 has_reduced_clock =
7890 dev_priv->display.find_dpll(limit, crtc_state,
7891 dev_priv->lvds_downclock,
7892 refclk, &clock,
7893 &reduced_clock);
7894 }
7895 /* Compat-code for transition, will disappear. */
7896 crtc_state->dpll.n = clock.n;
7897 crtc_state->dpll.m1 = clock.m1;
7898 crtc_state->dpll.m2 = clock.m2;
7899 crtc_state->dpll.p1 = clock.p1;
7900 crtc_state->dpll.p2 = clock.p2;
7901 }
7902
7903 if (IS_GEN2(dev)) {
7904 i8xx_update_pll(crtc, crtc_state,
7905 has_reduced_clock ? &reduced_clock : NULL,
7906 num_connectors);
7907 } else if (IS_CHERRYVIEW(dev)) {
7908 chv_update_pll(crtc, crtc_state);
7909 } else if (IS_VALLEYVIEW(dev)) {
7910 vlv_update_pll(crtc, crtc_state);
7911 } else {
7912 i9xx_update_pll(crtc, crtc_state,
7913 has_reduced_clock ? &reduced_clock : NULL,
7914 num_connectors);
7915 }
7916
7917 return 0;
7918 }
7919
7920 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7921 struct intel_crtc_state *pipe_config)
7922 {
7923 struct drm_device *dev = crtc->base.dev;
7924 struct drm_i915_private *dev_priv = dev->dev_private;
7925 uint32_t tmp;
7926
7927 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7928 return;
7929
7930 tmp = I915_READ(PFIT_CONTROL);
7931 if (!(tmp & PFIT_ENABLE))
7932 return;
7933
7934 /* Check whether the pfit is attached to our pipe. */
7935 if (INTEL_INFO(dev)->gen < 4) {
7936 if (crtc->pipe != PIPE_B)
7937 return;
7938 } else {
7939 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7940 return;
7941 }
7942
7943 pipe_config->gmch_pfit.control = tmp;
7944 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7945 if (INTEL_INFO(dev)->gen < 5)
7946 pipe_config->gmch_pfit.lvds_border_bits =
7947 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7948 }
7949
7950 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7951 struct intel_crtc_state *pipe_config)
7952 {
7953 struct drm_device *dev = crtc->base.dev;
7954 struct drm_i915_private *dev_priv = dev->dev_private;
7955 int pipe = pipe_config->cpu_transcoder;
7956 intel_clock_t clock;
7957 u32 mdiv;
7958 int refclk = 100000;
7959
7960 /* In case of MIPI DPLL will not even be used */
7961 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7962 return;
7963
7964 mutex_lock(&dev_priv->sb_lock);
7965 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7966 mutex_unlock(&dev_priv->sb_lock);
7967
7968 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7969 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7970 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7971 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7972 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7973
7974 vlv_clock(refclk, &clock);
7975
7976 /* clock.dot is the fast clock */
7977 pipe_config->port_clock = clock.dot / 5;
7978 }
7979
7980 static void
7981 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7982 struct intel_initial_plane_config *plane_config)
7983 {
7984 struct drm_device *dev = crtc->base.dev;
7985 struct drm_i915_private *dev_priv = dev->dev_private;
7986 u32 val, base, offset;
7987 int pipe = crtc->pipe, plane = crtc->plane;
7988 int fourcc, pixel_format;
7989 unsigned int aligned_height;
7990 struct drm_framebuffer *fb;
7991 struct intel_framebuffer *intel_fb;
7992
7993 val = I915_READ(DSPCNTR(plane));
7994 if (!(val & DISPLAY_PLANE_ENABLE))
7995 return;
7996
7997 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7998 if (!intel_fb) {
7999 DRM_DEBUG_KMS("failed to alloc fb\n");
8000 return;
8001 }
8002
8003 fb = &intel_fb->base;
8004
8005 if (INTEL_INFO(dev)->gen >= 4) {
8006 if (val & DISPPLANE_TILED) {
8007 plane_config->tiling = I915_TILING_X;
8008 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8009 }
8010 }
8011
8012 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8013 fourcc = i9xx_format_to_fourcc(pixel_format);
8014 fb->pixel_format = fourcc;
8015 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8016
8017 if (INTEL_INFO(dev)->gen >= 4) {
8018 if (plane_config->tiling)
8019 offset = I915_READ(DSPTILEOFF(plane));
8020 else
8021 offset = I915_READ(DSPLINOFF(plane));
8022 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8023 } else {
8024 base = I915_READ(DSPADDR(plane));
8025 }
8026 plane_config->base = base;
8027
8028 val = I915_READ(PIPESRC(pipe));
8029 fb->width = ((val >> 16) & 0xfff) + 1;
8030 fb->height = ((val >> 0) & 0xfff) + 1;
8031
8032 val = I915_READ(DSPSTRIDE(pipe));
8033 fb->pitches[0] = val & 0xffffffc0;
8034
8035 aligned_height = intel_fb_align_height(dev, fb->height,
8036 fb->pixel_format,
8037 fb->modifier[0]);
8038
8039 plane_config->size = fb->pitches[0] * aligned_height;
8040
8041 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8042 pipe_name(pipe), plane, fb->width, fb->height,
8043 fb->bits_per_pixel, base, fb->pitches[0],
8044 plane_config->size);
8045
8046 plane_config->fb = intel_fb;
8047 }
8048
8049 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8050 struct intel_crtc_state *pipe_config)
8051 {
8052 struct drm_device *dev = crtc->base.dev;
8053 struct drm_i915_private *dev_priv = dev->dev_private;
8054 int pipe = pipe_config->cpu_transcoder;
8055 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8056 intel_clock_t clock;
8057 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8058 int refclk = 100000;
8059
8060 mutex_lock(&dev_priv->sb_lock);
8061 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8062 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8063 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8064 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8065 mutex_unlock(&dev_priv->sb_lock);
8066
8067 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8068 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8069 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8070 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8071 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8072
8073 chv_clock(refclk, &clock);
8074
8075 /* clock.dot is the fast clock */
8076 pipe_config->port_clock = clock.dot / 5;
8077 }
8078
8079 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8080 struct intel_crtc_state *pipe_config)
8081 {
8082 struct drm_device *dev = crtc->base.dev;
8083 struct drm_i915_private *dev_priv = dev->dev_private;
8084 uint32_t tmp;
8085
8086 if (!intel_display_power_is_enabled(dev_priv,
8087 POWER_DOMAIN_PIPE(crtc->pipe)))
8088 return false;
8089
8090 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8091 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8092
8093 tmp = I915_READ(PIPECONF(crtc->pipe));
8094 if (!(tmp & PIPECONF_ENABLE))
8095 return false;
8096
8097 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8098 switch (tmp & PIPECONF_BPC_MASK) {
8099 case PIPECONF_6BPC:
8100 pipe_config->pipe_bpp = 18;
8101 break;
8102 case PIPECONF_8BPC:
8103 pipe_config->pipe_bpp = 24;
8104 break;
8105 case PIPECONF_10BPC:
8106 pipe_config->pipe_bpp = 30;
8107 break;
8108 default:
8109 break;
8110 }
8111 }
8112
8113 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8114 pipe_config->limited_color_range = true;
8115
8116 if (INTEL_INFO(dev)->gen < 4)
8117 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8118
8119 intel_get_pipe_timings(crtc, pipe_config);
8120
8121 i9xx_get_pfit_config(crtc, pipe_config);
8122
8123 if (INTEL_INFO(dev)->gen >= 4) {
8124 tmp = I915_READ(DPLL_MD(crtc->pipe));
8125 pipe_config->pixel_multiplier =
8126 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8127 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8128 pipe_config->dpll_hw_state.dpll_md = tmp;
8129 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8130 tmp = I915_READ(DPLL(crtc->pipe));
8131 pipe_config->pixel_multiplier =
8132 ((tmp & SDVO_MULTIPLIER_MASK)
8133 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8134 } else {
8135 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8136 * port and will be fixed up in the encoder->get_config
8137 * function. */
8138 pipe_config->pixel_multiplier = 1;
8139 }
8140 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8141 if (!IS_VALLEYVIEW(dev)) {
8142 /*
8143 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8144 * on 830. Filter it out here so that we don't
8145 * report errors due to that.
8146 */
8147 if (IS_I830(dev))
8148 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8149
8150 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8151 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8152 } else {
8153 /* Mask out read-only status bits. */
8154 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8155 DPLL_PORTC_READY_MASK |
8156 DPLL_PORTB_READY_MASK);
8157 }
8158
8159 if (IS_CHERRYVIEW(dev))
8160 chv_crtc_clock_get(crtc, pipe_config);
8161 else if (IS_VALLEYVIEW(dev))
8162 vlv_crtc_clock_get(crtc, pipe_config);
8163 else
8164 i9xx_crtc_clock_get(crtc, pipe_config);
8165
8166 return true;
8167 }
8168
8169 static void ironlake_init_pch_refclk(struct drm_device *dev)
8170 {
8171 struct drm_i915_private *dev_priv = dev->dev_private;
8172 struct intel_encoder *encoder;
8173 u32 val, final;
8174 bool has_lvds = false;
8175 bool has_cpu_edp = false;
8176 bool has_panel = false;
8177 bool has_ck505 = false;
8178 bool can_ssc = false;
8179
8180 /* We need to take the global config into account */
8181 for_each_intel_encoder(dev, encoder) {
8182 switch (encoder->type) {
8183 case INTEL_OUTPUT_LVDS:
8184 has_panel = true;
8185 has_lvds = true;
8186 break;
8187 case INTEL_OUTPUT_EDP:
8188 has_panel = true;
8189 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8190 has_cpu_edp = true;
8191 break;
8192 default:
8193 break;
8194 }
8195 }
8196
8197 if (HAS_PCH_IBX(dev)) {
8198 has_ck505 = dev_priv->vbt.display_clock_mode;
8199 can_ssc = has_ck505;
8200 } else {
8201 has_ck505 = false;
8202 can_ssc = true;
8203 }
8204
8205 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8206 has_panel, has_lvds, has_ck505);
8207
8208 /* Ironlake: try to setup display ref clock before DPLL
8209 * enabling. This is only under driver's control after
8210 * PCH B stepping, previous chipset stepping should be
8211 * ignoring this setting.
8212 */
8213 val = I915_READ(PCH_DREF_CONTROL);
8214
8215 /* As we must carefully and slowly disable/enable each source in turn,
8216 * compute the final state we want first and check if we need to
8217 * make any changes at all.
8218 */
8219 final = val;
8220 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8221 if (has_ck505)
8222 final |= DREF_NONSPREAD_CK505_ENABLE;
8223 else
8224 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8225
8226 final &= ~DREF_SSC_SOURCE_MASK;
8227 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8228 final &= ~DREF_SSC1_ENABLE;
8229
8230 if (has_panel) {
8231 final |= DREF_SSC_SOURCE_ENABLE;
8232
8233 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8234 final |= DREF_SSC1_ENABLE;
8235
8236 if (has_cpu_edp) {
8237 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8238 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8239 else
8240 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8241 } else
8242 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8243 } else {
8244 final |= DREF_SSC_SOURCE_DISABLE;
8245 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8246 }
8247
8248 if (final == val)
8249 return;
8250
8251 /* Always enable nonspread source */
8252 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8253
8254 if (has_ck505)
8255 val |= DREF_NONSPREAD_CK505_ENABLE;
8256 else
8257 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8258
8259 if (has_panel) {
8260 val &= ~DREF_SSC_SOURCE_MASK;
8261 val |= DREF_SSC_SOURCE_ENABLE;
8262
8263 /* SSC must be turned on before enabling the CPU output */
8264 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8265 DRM_DEBUG_KMS("Using SSC on panel\n");
8266 val |= DREF_SSC1_ENABLE;
8267 } else
8268 val &= ~DREF_SSC1_ENABLE;
8269
8270 /* Get SSC going before enabling the outputs */
8271 I915_WRITE(PCH_DREF_CONTROL, val);
8272 POSTING_READ(PCH_DREF_CONTROL);
8273 udelay(200);
8274
8275 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8276
8277 /* Enable CPU source on CPU attached eDP */
8278 if (has_cpu_edp) {
8279 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8280 DRM_DEBUG_KMS("Using SSC on eDP\n");
8281 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8282 } else
8283 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8284 } else
8285 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8286
8287 I915_WRITE(PCH_DREF_CONTROL, val);
8288 POSTING_READ(PCH_DREF_CONTROL);
8289 udelay(200);
8290 } else {
8291 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8292
8293 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8294
8295 /* Turn off CPU output */
8296 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8297
8298 I915_WRITE(PCH_DREF_CONTROL, val);
8299 POSTING_READ(PCH_DREF_CONTROL);
8300 udelay(200);
8301
8302 /* Turn off the SSC source */
8303 val &= ~DREF_SSC_SOURCE_MASK;
8304 val |= DREF_SSC_SOURCE_DISABLE;
8305
8306 /* Turn off SSC1 */
8307 val &= ~DREF_SSC1_ENABLE;
8308
8309 I915_WRITE(PCH_DREF_CONTROL, val);
8310 POSTING_READ(PCH_DREF_CONTROL);
8311 udelay(200);
8312 }
8313
8314 BUG_ON(val != final);
8315 }
8316
8317 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8318 {
8319 uint32_t tmp;
8320
8321 tmp = I915_READ(SOUTH_CHICKEN2);
8322 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8323 I915_WRITE(SOUTH_CHICKEN2, tmp);
8324
8325 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8326 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8327 DRM_ERROR("FDI mPHY reset assert timeout\n");
8328
8329 tmp = I915_READ(SOUTH_CHICKEN2);
8330 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8331 I915_WRITE(SOUTH_CHICKEN2, tmp);
8332
8333 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8334 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8335 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8336 }
8337
8338 /* WaMPhyProgramming:hsw */
8339 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8340 {
8341 uint32_t tmp;
8342
8343 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8344 tmp &= ~(0xFF << 24);
8345 tmp |= (0x12 << 24);
8346 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8347
8348 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8349 tmp |= (1 << 11);
8350 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8351
8352 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8353 tmp |= (1 << 11);
8354 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8355
8356 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8357 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8358 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8359
8360 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8361 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8362 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8363
8364 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8365 tmp &= ~(7 << 13);
8366 tmp |= (5 << 13);
8367 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8368
8369 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8370 tmp &= ~(7 << 13);
8371 tmp |= (5 << 13);
8372 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8373
8374 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8375 tmp &= ~0xFF;
8376 tmp |= 0x1C;
8377 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8378
8379 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8380 tmp &= ~0xFF;
8381 tmp |= 0x1C;
8382 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8383
8384 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8385 tmp &= ~(0xFF << 16);
8386 tmp |= (0x1C << 16);
8387 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8388
8389 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8390 tmp &= ~(0xFF << 16);
8391 tmp |= (0x1C << 16);
8392 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8393
8394 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8395 tmp |= (1 << 27);
8396 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8397
8398 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8399 tmp |= (1 << 27);
8400 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8401
8402 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8403 tmp &= ~(0xF << 28);
8404 tmp |= (4 << 28);
8405 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8406
8407 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8408 tmp &= ~(0xF << 28);
8409 tmp |= (4 << 28);
8410 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8411 }
8412
8413 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8414 * Programming" based on the parameters passed:
8415 * - Sequence to enable CLKOUT_DP
8416 * - Sequence to enable CLKOUT_DP without spread
8417 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8418 */
8419 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8420 bool with_fdi)
8421 {
8422 struct drm_i915_private *dev_priv = dev->dev_private;
8423 uint32_t reg, tmp;
8424
8425 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8426 with_spread = true;
8427 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8428 with_fdi, "LP PCH doesn't have FDI\n"))
8429 with_fdi = false;
8430
8431 mutex_lock(&dev_priv->sb_lock);
8432
8433 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8434 tmp &= ~SBI_SSCCTL_DISABLE;
8435 tmp |= SBI_SSCCTL_PATHALT;
8436 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8437
8438 udelay(24);
8439
8440 if (with_spread) {
8441 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8442 tmp &= ~SBI_SSCCTL_PATHALT;
8443 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8444
8445 if (with_fdi) {
8446 lpt_reset_fdi_mphy(dev_priv);
8447 lpt_program_fdi_mphy(dev_priv);
8448 }
8449 }
8450
8451 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8452 SBI_GEN0 : SBI_DBUFF0;
8453 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8454 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8455 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8456
8457 mutex_unlock(&dev_priv->sb_lock);
8458 }
8459
8460 /* Sequence to disable CLKOUT_DP */
8461 static void lpt_disable_clkout_dp(struct drm_device *dev)
8462 {
8463 struct drm_i915_private *dev_priv = dev->dev_private;
8464 uint32_t reg, tmp;
8465
8466 mutex_lock(&dev_priv->sb_lock);
8467
8468 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8469 SBI_GEN0 : SBI_DBUFF0;
8470 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8471 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8472 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8473
8474 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8475 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8476 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8477 tmp |= SBI_SSCCTL_PATHALT;
8478 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8479 udelay(32);
8480 }
8481 tmp |= SBI_SSCCTL_DISABLE;
8482 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8483 }
8484
8485 mutex_unlock(&dev_priv->sb_lock);
8486 }
8487
8488 static void lpt_init_pch_refclk(struct drm_device *dev)
8489 {
8490 struct intel_encoder *encoder;
8491 bool has_vga = false;
8492
8493 for_each_intel_encoder(dev, encoder) {
8494 switch (encoder->type) {
8495 case INTEL_OUTPUT_ANALOG:
8496 has_vga = true;
8497 break;
8498 default:
8499 break;
8500 }
8501 }
8502
8503 if (has_vga)
8504 lpt_enable_clkout_dp(dev, true, true);
8505 else
8506 lpt_disable_clkout_dp(dev);
8507 }
8508
8509 /*
8510 * Initialize reference clocks when the driver loads
8511 */
8512 void intel_init_pch_refclk(struct drm_device *dev)
8513 {
8514 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8515 ironlake_init_pch_refclk(dev);
8516 else if (HAS_PCH_LPT(dev))
8517 lpt_init_pch_refclk(dev);
8518 }
8519
8520 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8521 {
8522 struct drm_device *dev = crtc_state->base.crtc->dev;
8523 struct drm_i915_private *dev_priv = dev->dev_private;
8524 struct drm_atomic_state *state = crtc_state->base.state;
8525 struct drm_connector *connector;
8526 struct drm_connector_state *connector_state;
8527 struct intel_encoder *encoder;
8528 int num_connectors = 0, i;
8529 bool is_lvds = false;
8530
8531 for_each_connector_in_state(state, connector, connector_state, i) {
8532 if (connector_state->crtc != crtc_state->base.crtc)
8533 continue;
8534
8535 encoder = to_intel_encoder(connector_state->best_encoder);
8536
8537 switch (encoder->type) {
8538 case INTEL_OUTPUT_LVDS:
8539 is_lvds = true;
8540 break;
8541 default:
8542 break;
8543 }
8544 num_connectors++;
8545 }
8546
8547 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8548 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8549 dev_priv->vbt.lvds_ssc_freq);
8550 return dev_priv->vbt.lvds_ssc_freq;
8551 }
8552
8553 return 120000;
8554 }
8555
8556 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8557 {
8558 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8560 int pipe = intel_crtc->pipe;
8561 uint32_t val;
8562
8563 val = 0;
8564
8565 switch (intel_crtc->config->pipe_bpp) {
8566 case 18:
8567 val |= PIPECONF_6BPC;
8568 break;
8569 case 24:
8570 val |= PIPECONF_8BPC;
8571 break;
8572 case 30:
8573 val |= PIPECONF_10BPC;
8574 break;
8575 case 36:
8576 val |= PIPECONF_12BPC;
8577 break;
8578 default:
8579 /* Case prevented by intel_choose_pipe_bpp_dither. */
8580 BUG();
8581 }
8582
8583 if (intel_crtc->config->dither)
8584 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8585
8586 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8587 val |= PIPECONF_INTERLACED_ILK;
8588 else
8589 val |= PIPECONF_PROGRESSIVE;
8590
8591 if (intel_crtc->config->limited_color_range)
8592 val |= PIPECONF_COLOR_RANGE_SELECT;
8593
8594 I915_WRITE(PIPECONF(pipe), val);
8595 POSTING_READ(PIPECONF(pipe));
8596 }
8597
8598 /*
8599 * Set up the pipe CSC unit.
8600 *
8601 * Currently only full range RGB to limited range RGB conversion
8602 * is supported, but eventually this should handle various
8603 * RGB<->YCbCr scenarios as well.
8604 */
8605 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8606 {
8607 struct drm_device *dev = crtc->dev;
8608 struct drm_i915_private *dev_priv = dev->dev_private;
8609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8610 int pipe = intel_crtc->pipe;
8611 uint16_t coeff = 0x7800; /* 1.0 */
8612
8613 /*
8614 * TODO: Check what kind of values actually come out of the pipe
8615 * with these coeff/postoff values and adjust to get the best
8616 * accuracy. Perhaps we even need to take the bpc value into
8617 * consideration.
8618 */
8619
8620 if (intel_crtc->config->limited_color_range)
8621 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8622
8623 /*
8624 * GY/GU and RY/RU should be the other way around according
8625 * to BSpec, but reality doesn't agree. Just set them up in
8626 * a way that results in the correct picture.
8627 */
8628 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8629 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8630
8631 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8632 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8633
8634 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8635 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8636
8637 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8638 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8639 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8640
8641 if (INTEL_INFO(dev)->gen > 6) {
8642 uint16_t postoff = 0;
8643
8644 if (intel_crtc->config->limited_color_range)
8645 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8646
8647 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8648 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8649 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8650
8651 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8652 } else {
8653 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8654
8655 if (intel_crtc->config->limited_color_range)
8656 mode |= CSC_BLACK_SCREEN_OFFSET;
8657
8658 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8659 }
8660 }
8661
8662 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8663 {
8664 struct drm_device *dev = crtc->dev;
8665 struct drm_i915_private *dev_priv = dev->dev_private;
8666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8667 enum pipe pipe = intel_crtc->pipe;
8668 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8669 uint32_t val;
8670
8671 val = 0;
8672
8673 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8674 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8675
8676 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8677 val |= PIPECONF_INTERLACED_ILK;
8678 else
8679 val |= PIPECONF_PROGRESSIVE;
8680
8681 I915_WRITE(PIPECONF(cpu_transcoder), val);
8682 POSTING_READ(PIPECONF(cpu_transcoder));
8683
8684 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8685 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8686
8687 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8688 val = 0;
8689
8690 switch (intel_crtc->config->pipe_bpp) {
8691 case 18:
8692 val |= PIPEMISC_DITHER_6_BPC;
8693 break;
8694 case 24:
8695 val |= PIPEMISC_DITHER_8_BPC;
8696 break;
8697 case 30:
8698 val |= PIPEMISC_DITHER_10_BPC;
8699 break;
8700 case 36:
8701 val |= PIPEMISC_DITHER_12_BPC;
8702 break;
8703 default:
8704 /* Case prevented by pipe_config_set_bpp. */
8705 BUG();
8706 }
8707
8708 if (intel_crtc->config->dither)
8709 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8710
8711 I915_WRITE(PIPEMISC(pipe), val);
8712 }
8713 }
8714
8715 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8716 struct intel_crtc_state *crtc_state,
8717 intel_clock_t *clock,
8718 bool *has_reduced_clock,
8719 intel_clock_t *reduced_clock)
8720 {
8721 struct drm_device *dev = crtc->dev;
8722 struct drm_i915_private *dev_priv = dev->dev_private;
8723 int refclk;
8724 const intel_limit_t *limit;
8725 bool ret, is_lvds = false;
8726
8727 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8728
8729 refclk = ironlake_get_refclk(crtc_state);
8730
8731 /*
8732 * Returns a set of divisors for the desired target clock with the given
8733 * refclk, or FALSE. The returned values represent the clock equation:
8734 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8735 */
8736 limit = intel_limit(crtc_state, refclk);
8737 ret = dev_priv->display.find_dpll(limit, crtc_state,
8738 crtc_state->port_clock,
8739 refclk, NULL, clock);
8740 if (!ret)
8741 return false;
8742
8743 if (is_lvds && dev_priv->lvds_downclock_avail) {
8744 /*
8745 * Ensure we match the reduced clock's P to the target clock.
8746 * If the clocks don't match, we can't switch the display clock
8747 * by using the FP0/FP1. In such case we will disable the LVDS
8748 * downclock feature.
8749 */
8750 *has_reduced_clock =
8751 dev_priv->display.find_dpll(limit, crtc_state,
8752 dev_priv->lvds_downclock,
8753 refclk, clock,
8754 reduced_clock);
8755 }
8756
8757 return true;
8758 }
8759
8760 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8761 {
8762 /*
8763 * Account for spread spectrum to avoid
8764 * oversubscribing the link. Max center spread
8765 * is 2.5%; use 5% for safety's sake.
8766 */
8767 u32 bps = target_clock * bpp * 21 / 20;
8768 return DIV_ROUND_UP(bps, link_bw * 8);
8769 }
8770
8771 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8772 {
8773 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8774 }
8775
8776 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8777 struct intel_crtc_state *crtc_state,
8778 u32 *fp,
8779 intel_clock_t *reduced_clock, u32 *fp2)
8780 {
8781 struct drm_crtc *crtc = &intel_crtc->base;
8782 struct drm_device *dev = crtc->dev;
8783 struct drm_i915_private *dev_priv = dev->dev_private;
8784 struct drm_atomic_state *state = crtc_state->base.state;
8785 struct drm_connector *connector;
8786 struct drm_connector_state *connector_state;
8787 struct intel_encoder *encoder;
8788 uint32_t dpll;
8789 int factor, num_connectors = 0, i;
8790 bool is_lvds = false, is_sdvo = false;
8791
8792 for_each_connector_in_state(state, connector, connector_state, i) {
8793 if (connector_state->crtc != crtc_state->base.crtc)
8794 continue;
8795
8796 encoder = to_intel_encoder(connector_state->best_encoder);
8797
8798 switch (encoder->type) {
8799 case INTEL_OUTPUT_LVDS:
8800 is_lvds = true;
8801 break;
8802 case INTEL_OUTPUT_SDVO:
8803 case INTEL_OUTPUT_HDMI:
8804 is_sdvo = true;
8805 break;
8806 default:
8807 break;
8808 }
8809
8810 num_connectors++;
8811 }
8812
8813 /* Enable autotuning of the PLL clock (if permissible) */
8814 factor = 21;
8815 if (is_lvds) {
8816 if ((intel_panel_use_ssc(dev_priv) &&
8817 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8818 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8819 factor = 25;
8820 } else if (crtc_state->sdvo_tv_clock)
8821 factor = 20;
8822
8823 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8824 *fp |= FP_CB_TUNE;
8825
8826 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8827 *fp2 |= FP_CB_TUNE;
8828
8829 dpll = 0;
8830
8831 if (is_lvds)
8832 dpll |= DPLLB_MODE_LVDS;
8833 else
8834 dpll |= DPLLB_MODE_DAC_SERIAL;
8835
8836 dpll |= (crtc_state->pixel_multiplier - 1)
8837 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8838
8839 if (is_sdvo)
8840 dpll |= DPLL_SDVO_HIGH_SPEED;
8841 if (crtc_state->has_dp_encoder)
8842 dpll |= DPLL_SDVO_HIGH_SPEED;
8843
8844 /* compute bitmask from p1 value */
8845 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8846 /* also FPA1 */
8847 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8848
8849 switch (crtc_state->dpll.p2) {
8850 case 5:
8851 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8852 break;
8853 case 7:
8854 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8855 break;
8856 case 10:
8857 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8858 break;
8859 case 14:
8860 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8861 break;
8862 }
8863
8864 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8865 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8866 else
8867 dpll |= PLL_REF_INPUT_DREFCLK;
8868
8869 return dpll | DPLL_VCO_ENABLE;
8870 }
8871
8872 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8873 struct intel_crtc_state *crtc_state)
8874 {
8875 struct drm_device *dev = crtc->base.dev;
8876 intel_clock_t clock, reduced_clock;
8877 u32 dpll = 0, fp = 0, fp2 = 0;
8878 bool ok, has_reduced_clock = false;
8879 bool is_lvds = false;
8880 struct intel_shared_dpll *pll;
8881
8882 memset(&crtc_state->dpll_hw_state, 0,
8883 sizeof(crtc_state->dpll_hw_state));
8884
8885 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8886
8887 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8888 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8889
8890 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8891 &has_reduced_clock, &reduced_clock);
8892 if (!ok && !crtc_state->clock_set) {
8893 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8894 return -EINVAL;
8895 }
8896 /* Compat-code for transition, will disappear. */
8897 if (!crtc_state->clock_set) {
8898 crtc_state->dpll.n = clock.n;
8899 crtc_state->dpll.m1 = clock.m1;
8900 crtc_state->dpll.m2 = clock.m2;
8901 crtc_state->dpll.p1 = clock.p1;
8902 crtc_state->dpll.p2 = clock.p2;
8903 }
8904
8905 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8906 if (crtc_state->has_pch_encoder) {
8907 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8908 if (has_reduced_clock)
8909 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8910
8911 dpll = ironlake_compute_dpll(crtc, crtc_state,
8912 &fp, &reduced_clock,
8913 has_reduced_clock ? &fp2 : NULL);
8914
8915 crtc_state->dpll_hw_state.dpll = dpll;
8916 crtc_state->dpll_hw_state.fp0 = fp;
8917 if (has_reduced_clock)
8918 crtc_state->dpll_hw_state.fp1 = fp2;
8919 else
8920 crtc_state->dpll_hw_state.fp1 = fp;
8921
8922 pll = intel_get_shared_dpll(crtc, crtc_state);
8923 if (pll == NULL) {
8924 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8925 pipe_name(crtc->pipe));
8926 return -EINVAL;
8927 }
8928 }
8929
8930 if (is_lvds && has_reduced_clock)
8931 crtc->lowfreq_avail = true;
8932 else
8933 crtc->lowfreq_avail = false;
8934
8935 return 0;
8936 }
8937
8938 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8939 struct intel_link_m_n *m_n)
8940 {
8941 struct drm_device *dev = crtc->base.dev;
8942 struct drm_i915_private *dev_priv = dev->dev_private;
8943 enum pipe pipe = crtc->pipe;
8944
8945 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8946 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8947 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8948 & ~TU_SIZE_MASK;
8949 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8950 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8951 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8952 }
8953
8954 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8955 enum transcoder transcoder,
8956 struct intel_link_m_n *m_n,
8957 struct intel_link_m_n *m2_n2)
8958 {
8959 struct drm_device *dev = crtc->base.dev;
8960 struct drm_i915_private *dev_priv = dev->dev_private;
8961 enum pipe pipe = crtc->pipe;
8962
8963 if (INTEL_INFO(dev)->gen >= 5) {
8964 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8965 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8966 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8967 & ~TU_SIZE_MASK;
8968 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8969 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8970 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8971 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8972 * gen < 8) and if DRRS is supported (to make sure the
8973 * registers are not unnecessarily read).
8974 */
8975 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8976 crtc->config->has_drrs) {
8977 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8978 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8979 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8980 & ~TU_SIZE_MASK;
8981 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8982 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8983 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8984 }
8985 } else {
8986 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8987 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8988 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8989 & ~TU_SIZE_MASK;
8990 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8991 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8992 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8993 }
8994 }
8995
8996 void intel_dp_get_m_n(struct intel_crtc *crtc,
8997 struct intel_crtc_state *pipe_config)
8998 {
8999 if (pipe_config->has_pch_encoder)
9000 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9001 else
9002 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9003 &pipe_config->dp_m_n,
9004 &pipe_config->dp_m2_n2);
9005 }
9006
9007 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9008 struct intel_crtc_state *pipe_config)
9009 {
9010 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9011 &pipe_config->fdi_m_n, NULL);
9012 }
9013
9014 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9015 struct intel_crtc_state *pipe_config)
9016 {
9017 struct drm_device *dev = crtc->base.dev;
9018 struct drm_i915_private *dev_priv = dev->dev_private;
9019 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9020 uint32_t ps_ctrl = 0;
9021 int id = -1;
9022 int i;
9023
9024 /* find scaler attached to this pipe */
9025 for (i = 0; i < crtc->num_scalers; i++) {
9026 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9027 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9028 id = i;
9029 pipe_config->pch_pfit.enabled = true;
9030 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9031 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9032 break;
9033 }
9034 }
9035
9036 scaler_state->scaler_id = id;
9037 if (id >= 0) {
9038 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9039 } else {
9040 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9041 }
9042 }
9043
9044 static void
9045 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9046 struct intel_initial_plane_config *plane_config)
9047 {
9048 struct drm_device *dev = crtc->base.dev;
9049 struct drm_i915_private *dev_priv = dev->dev_private;
9050 u32 val, base, offset, stride_mult, tiling;
9051 int pipe = crtc->pipe;
9052 int fourcc, pixel_format;
9053 unsigned int aligned_height;
9054 struct drm_framebuffer *fb;
9055 struct intel_framebuffer *intel_fb;
9056
9057 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9058 if (!intel_fb) {
9059 DRM_DEBUG_KMS("failed to alloc fb\n");
9060 return;
9061 }
9062
9063 fb = &intel_fb->base;
9064
9065 val = I915_READ(PLANE_CTL(pipe, 0));
9066 if (!(val & PLANE_CTL_ENABLE))
9067 goto error;
9068
9069 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9070 fourcc = skl_format_to_fourcc(pixel_format,
9071 val & PLANE_CTL_ORDER_RGBX,
9072 val & PLANE_CTL_ALPHA_MASK);
9073 fb->pixel_format = fourcc;
9074 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9075
9076 tiling = val & PLANE_CTL_TILED_MASK;
9077 switch (tiling) {
9078 case PLANE_CTL_TILED_LINEAR:
9079 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9080 break;
9081 case PLANE_CTL_TILED_X:
9082 plane_config->tiling = I915_TILING_X;
9083 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9084 break;
9085 case PLANE_CTL_TILED_Y:
9086 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9087 break;
9088 case PLANE_CTL_TILED_YF:
9089 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9090 break;
9091 default:
9092 MISSING_CASE(tiling);
9093 goto error;
9094 }
9095
9096 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9097 plane_config->base = base;
9098
9099 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9100
9101 val = I915_READ(PLANE_SIZE(pipe, 0));
9102 fb->height = ((val >> 16) & 0xfff) + 1;
9103 fb->width = ((val >> 0) & 0x1fff) + 1;
9104
9105 val = I915_READ(PLANE_STRIDE(pipe, 0));
9106 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9107 fb->pixel_format);
9108 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9109
9110 aligned_height = intel_fb_align_height(dev, fb->height,
9111 fb->pixel_format,
9112 fb->modifier[0]);
9113
9114 plane_config->size = fb->pitches[0] * aligned_height;
9115
9116 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9117 pipe_name(pipe), fb->width, fb->height,
9118 fb->bits_per_pixel, base, fb->pitches[0],
9119 plane_config->size);
9120
9121 plane_config->fb = intel_fb;
9122 return;
9123
9124 error:
9125 kfree(fb);
9126 }
9127
9128 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9129 struct intel_crtc_state *pipe_config)
9130 {
9131 struct drm_device *dev = crtc->base.dev;
9132 struct drm_i915_private *dev_priv = dev->dev_private;
9133 uint32_t tmp;
9134
9135 tmp = I915_READ(PF_CTL(crtc->pipe));
9136
9137 if (tmp & PF_ENABLE) {
9138 pipe_config->pch_pfit.enabled = true;
9139 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9140 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9141
9142 /* We currently do not free assignements of panel fitters on
9143 * ivb/hsw (since we don't use the higher upscaling modes which
9144 * differentiates them) so just WARN about this case for now. */
9145 if (IS_GEN7(dev)) {
9146 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9147 PF_PIPE_SEL_IVB(crtc->pipe));
9148 }
9149 }
9150 }
9151
9152 static void
9153 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9154 struct intel_initial_plane_config *plane_config)
9155 {
9156 struct drm_device *dev = crtc->base.dev;
9157 struct drm_i915_private *dev_priv = dev->dev_private;
9158 u32 val, base, offset;
9159 int pipe = crtc->pipe;
9160 int fourcc, pixel_format;
9161 unsigned int aligned_height;
9162 struct drm_framebuffer *fb;
9163 struct intel_framebuffer *intel_fb;
9164
9165 val = I915_READ(DSPCNTR(pipe));
9166 if (!(val & DISPLAY_PLANE_ENABLE))
9167 return;
9168
9169 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9170 if (!intel_fb) {
9171 DRM_DEBUG_KMS("failed to alloc fb\n");
9172 return;
9173 }
9174
9175 fb = &intel_fb->base;
9176
9177 if (INTEL_INFO(dev)->gen >= 4) {
9178 if (val & DISPPLANE_TILED) {
9179 plane_config->tiling = I915_TILING_X;
9180 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9181 }
9182 }
9183
9184 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9185 fourcc = i9xx_format_to_fourcc(pixel_format);
9186 fb->pixel_format = fourcc;
9187 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9188
9189 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9190 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9191 offset = I915_READ(DSPOFFSET(pipe));
9192 } else {
9193 if (plane_config->tiling)
9194 offset = I915_READ(DSPTILEOFF(pipe));
9195 else
9196 offset = I915_READ(DSPLINOFF(pipe));
9197 }
9198 plane_config->base = base;
9199
9200 val = I915_READ(PIPESRC(pipe));
9201 fb->width = ((val >> 16) & 0xfff) + 1;
9202 fb->height = ((val >> 0) & 0xfff) + 1;
9203
9204 val = I915_READ(DSPSTRIDE(pipe));
9205 fb->pitches[0] = val & 0xffffffc0;
9206
9207 aligned_height = intel_fb_align_height(dev, fb->height,
9208 fb->pixel_format,
9209 fb->modifier[0]);
9210
9211 plane_config->size = fb->pitches[0] * aligned_height;
9212
9213 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9214 pipe_name(pipe), fb->width, fb->height,
9215 fb->bits_per_pixel, base, fb->pitches[0],
9216 plane_config->size);
9217
9218 plane_config->fb = intel_fb;
9219 }
9220
9221 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9222 struct intel_crtc_state *pipe_config)
9223 {
9224 struct drm_device *dev = crtc->base.dev;
9225 struct drm_i915_private *dev_priv = dev->dev_private;
9226 uint32_t tmp;
9227
9228 if (!intel_display_power_is_enabled(dev_priv,
9229 POWER_DOMAIN_PIPE(crtc->pipe)))
9230 return false;
9231
9232 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9233 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9234
9235 tmp = I915_READ(PIPECONF(crtc->pipe));
9236 if (!(tmp & PIPECONF_ENABLE))
9237 return false;
9238
9239 switch (tmp & PIPECONF_BPC_MASK) {
9240 case PIPECONF_6BPC:
9241 pipe_config->pipe_bpp = 18;
9242 break;
9243 case PIPECONF_8BPC:
9244 pipe_config->pipe_bpp = 24;
9245 break;
9246 case PIPECONF_10BPC:
9247 pipe_config->pipe_bpp = 30;
9248 break;
9249 case PIPECONF_12BPC:
9250 pipe_config->pipe_bpp = 36;
9251 break;
9252 default:
9253 break;
9254 }
9255
9256 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9257 pipe_config->limited_color_range = true;
9258
9259 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9260 struct intel_shared_dpll *pll;
9261
9262 pipe_config->has_pch_encoder = true;
9263
9264 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9265 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9266 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9267
9268 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9269
9270 if (HAS_PCH_IBX(dev_priv->dev)) {
9271 pipe_config->shared_dpll =
9272 (enum intel_dpll_id) crtc->pipe;
9273 } else {
9274 tmp = I915_READ(PCH_DPLL_SEL);
9275 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9276 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9277 else
9278 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9279 }
9280
9281 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9282
9283 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9284 &pipe_config->dpll_hw_state));
9285
9286 tmp = pipe_config->dpll_hw_state.dpll;
9287 pipe_config->pixel_multiplier =
9288 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9289 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9290
9291 ironlake_pch_clock_get(crtc, pipe_config);
9292 } else {
9293 pipe_config->pixel_multiplier = 1;
9294 }
9295
9296 intel_get_pipe_timings(crtc, pipe_config);
9297
9298 ironlake_get_pfit_config(crtc, pipe_config);
9299
9300 return true;
9301 }
9302
9303 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9304 {
9305 struct drm_device *dev = dev_priv->dev;
9306 struct intel_crtc *crtc;
9307
9308 for_each_intel_crtc(dev, crtc)
9309 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9310 pipe_name(crtc->pipe));
9311
9312 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9313 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9314 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9315 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9316 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9317 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9318 "CPU PWM1 enabled\n");
9319 if (IS_HASWELL(dev))
9320 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9321 "CPU PWM2 enabled\n");
9322 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9323 "PCH PWM1 enabled\n");
9324 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9325 "Utility pin enabled\n");
9326 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9327
9328 /*
9329 * In theory we can still leave IRQs enabled, as long as only the HPD
9330 * interrupts remain enabled. We used to check for that, but since it's
9331 * gen-specific and since we only disable LCPLL after we fully disable
9332 * the interrupts, the check below should be enough.
9333 */
9334 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9335 }
9336
9337 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9338 {
9339 struct drm_device *dev = dev_priv->dev;
9340
9341 if (IS_HASWELL(dev))
9342 return I915_READ(D_COMP_HSW);
9343 else
9344 return I915_READ(D_COMP_BDW);
9345 }
9346
9347 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9348 {
9349 struct drm_device *dev = dev_priv->dev;
9350
9351 if (IS_HASWELL(dev)) {
9352 mutex_lock(&dev_priv->rps.hw_lock);
9353 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9354 val))
9355 DRM_ERROR("Failed to write to D_COMP\n");
9356 mutex_unlock(&dev_priv->rps.hw_lock);
9357 } else {
9358 I915_WRITE(D_COMP_BDW, val);
9359 POSTING_READ(D_COMP_BDW);
9360 }
9361 }
9362
9363 /*
9364 * This function implements pieces of two sequences from BSpec:
9365 * - Sequence for display software to disable LCPLL
9366 * - Sequence for display software to allow package C8+
9367 * The steps implemented here are just the steps that actually touch the LCPLL
9368 * register. Callers should take care of disabling all the display engine
9369 * functions, doing the mode unset, fixing interrupts, etc.
9370 */
9371 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9372 bool switch_to_fclk, bool allow_power_down)
9373 {
9374 uint32_t val;
9375
9376 assert_can_disable_lcpll(dev_priv);
9377
9378 val = I915_READ(LCPLL_CTL);
9379
9380 if (switch_to_fclk) {
9381 val |= LCPLL_CD_SOURCE_FCLK;
9382 I915_WRITE(LCPLL_CTL, val);
9383
9384 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9385 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9386 DRM_ERROR("Switching to FCLK failed\n");
9387
9388 val = I915_READ(LCPLL_CTL);
9389 }
9390
9391 val |= LCPLL_PLL_DISABLE;
9392 I915_WRITE(LCPLL_CTL, val);
9393 POSTING_READ(LCPLL_CTL);
9394
9395 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9396 DRM_ERROR("LCPLL still locked\n");
9397
9398 val = hsw_read_dcomp(dev_priv);
9399 val |= D_COMP_COMP_DISABLE;
9400 hsw_write_dcomp(dev_priv, val);
9401 ndelay(100);
9402
9403 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9404 1))
9405 DRM_ERROR("D_COMP RCOMP still in progress\n");
9406
9407 if (allow_power_down) {
9408 val = I915_READ(LCPLL_CTL);
9409 val |= LCPLL_POWER_DOWN_ALLOW;
9410 I915_WRITE(LCPLL_CTL, val);
9411 POSTING_READ(LCPLL_CTL);
9412 }
9413 }
9414
9415 /*
9416 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9417 * source.
9418 */
9419 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9420 {
9421 uint32_t val;
9422
9423 val = I915_READ(LCPLL_CTL);
9424
9425 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9426 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9427 return;
9428
9429 /*
9430 * Make sure we're not on PC8 state before disabling PC8, otherwise
9431 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9432 */
9433 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9434
9435 if (val & LCPLL_POWER_DOWN_ALLOW) {
9436 val &= ~LCPLL_POWER_DOWN_ALLOW;
9437 I915_WRITE(LCPLL_CTL, val);
9438 POSTING_READ(LCPLL_CTL);
9439 }
9440
9441 val = hsw_read_dcomp(dev_priv);
9442 val |= D_COMP_COMP_FORCE;
9443 val &= ~D_COMP_COMP_DISABLE;
9444 hsw_write_dcomp(dev_priv, val);
9445
9446 val = I915_READ(LCPLL_CTL);
9447 val &= ~LCPLL_PLL_DISABLE;
9448 I915_WRITE(LCPLL_CTL, val);
9449
9450 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9451 DRM_ERROR("LCPLL not locked yet\n");
9452
9453 if (val & LCPLL_CD_SOURCE_FCLK) {
9454 val = I915_READ(LCPLL_CTL);
9455 val &= ~LCPLL_CD_SOURCE_FCLK;
9456 I915_WRITE(LCPLL_CTL, val);
9457
9458 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9459 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9460 DRM_ERROR("Switching back to LCPLL failed\n");
9461 }
9462
9463 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9464 intel_update_cdclk(dev_priv->dev);
9465 }
9466
9467 /*
9468 * Package states C8 and deeper are really deep PC states that can only be
9469 * reached when all the devices on the system allow it, so even if the graphics
9470 * device allows PC8+, it doesn't mean the system will actually get to these
9471 * states. Our driver only allows PC8+ when going into runtime PM.
9472 *
9473 * The requirements for PC8+ are that all the outputs are disabled, the power
9474 * well is disabled and most interrupts are disabled, and these are also
9475 * requirements for runtime PM. When these conditions are met, we manually do
9476 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9477 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9478 * hang the machine.
9479 *
9480 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9481 * the state of some registers, so when we come back from PC8+ we need to
9482 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9483 * need to take care of the registers kept by RC6. Notice that this happens even
9484 * if we don't put the device in PCI D3 state (which is what currently happens
9485 * because of the runtime PM support).
9486 *
9487 * For more, read "Display Sequences for Package C8" on the hardware
9488 * documentation.
9489 */
9490 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9491 {
9492 struct drm_device *dev = dev_priv->dev;
9493 uint32_t val;
9494
9495 DRM_DEBUG_KMS("Enabling package C8+\n");
9496
9497 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9498 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9499 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9500 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9501 }
9502
9503 lpt_disable_clkout_dp(dev);
9504 hsw_disable_lcpll(dev_priv, true, true);
9505 }
9506
9507 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9508 {
9509 struct drm_device *dev = dev_priv->dev;
9510 uint32_t val;
9511
9512 DRM_DEBUG_KMS("Disabling package C8+\n");
9513
9514 hsw_restore_lcpll(dev_priv);
9515 lpt_init_pch_refclk(dev);
9516
9517 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9518 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9519 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9520 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9521 }
9522
9523 intel_prepare_ddi(dev);
9524 }
9525
9526 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9527 {
9528 struct drm_device *dev = old_state->dev;
9529 struct drm_i915_private *dev_priv = dev->dev_private;
9530 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9531 int req_cdclk;
9532
9533 /* see the comment in valleyview_modeset_global_resources */
9534 if (WARN_ON(max_pixclk < 0))
9535 return;
9536
9537 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9538
9539 if (req_cdclk != dev_priv->cdclk_freq)
9540 broxton_set_cdclk(dev, req_cdclk);
9541 }
9542
9543 /* compute the max rate for new configuration */
9544 static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9545 {
9546 struct drm_device *dev = dev_priv->dev;
9547 struct intel_crtc *intel_crtc;
9548 struct drm_crtc *crtc;
9549 int max_pixel_rate = 0;
9550 int pixel_rate;
9551
9552 for_each_crtc(dev, crtc) {
9553 if (!crtc->state->enable)
9554 continue;
9555
9556 intel_crtc = to_intel_crtc(crtc);
9557 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9558
9559 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9560 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9561 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9562
9563 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9564 }
9565
9566 return max_pixel_rate;
9567 }
9568
9569 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9570 {
9571 struct drm_i915_private *dev_priv = dev->dev_private;
9572 uint32_t val, data;
9573 int ret;
9574
9575 if (WARN((I915_READ(LCPLL_CTL) &
9576 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9577 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9578 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9579 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9580 "trying to change cdclk frequency with cdclk not enabled\n"))
9581 return;
9582
9583 mutex_lock(&dev_priv->rps.hw_lock);
9584 ret = sandybridge_pcode_write(dev_priv,
9585 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9586 mutex_unlock(&dev_priv->rps.hw_lock);
9587 if (ret) {
9588 DRM_ERROR("failed to inform pcode about cdclk change\n");
9589 return;
9590 }
9591
9592 val = I915_READ(LCPLL_CTL);
9593 val |= LCPLL_CD_SOURCE_FCLK;
9594 I915_WRITE(LCPLL_CTL, val);
9595
9596 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9597 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9598 DRM_ERROR("Switching to FCLK failed\n");
9599
9600 val = I915_READ(LCPLL_CTL);
9601 val &= ~LCPLL_CLK_FREQ_MASK;
9602
9603 switch (cdclk) {
9604 case 450000:
9605 val |= LCPLL_CLK_FREQ_450;
9606 data = 0;
9607 break;
9608 case 540000:
9609 val |= LCPLL_CLK_FREQ_54O_BDW;
9610 data = 1;
9611 break;
9612 case 337500:
9613 val |= LCPLL_CLK_FREQ_337_5_BDW;
9614 data = 2;
9615 break;
9616 case 675000:
9617 val |= LCPLL_CLK_FREQ_675_BDW;
9618 data = 3;
9619 break;
9620 default:
9621 WARN(1, "invalid cdclk frequency\n");
9622 return;
9623 }
9624
9625 I915_WRITE(LCPLL_CTL, val);
9626
9627 val = I915_READ(LCPLL_CTL);
9628 val &= ~LCPLL_CD_SOURCE_FCLK;
9629 I915_WRITE(LCPLL_CTL, val);
9630
9631 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9632 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9633 DRM_ERROR("Switching back to LCPLL failed\n");
9634
9635 mutex_lock(&dev_priv->rps.hw_lock);
9636 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9637 mutex_unlock(&dev_priv->rps.hw_lock);
9638
9639 intel_update_cdclk(dev);
9640
9641 WARN(cdclk != dev_priv->cdclk_freq,
9642 "cdclk requested %d kHz but got %d kHz\n",
9643 cdclk, dev_priv->cdclk_freq);
9644 }
9645
9646 static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9647 int max_pixel_rate)
9648 {
9649 int cdclk;
9650
9651 /*
9652 * FIXME should also account for plane ratio
9653 * once 64bpp pixel formats are supported.
9654 */
9655 if (max_pixel_rate > 540000)
9656 cdclk = 675000;
9657 else if (max_pixel_rate > 450000)
9658 cdclk = 540000;
9659 else if (max_pixel_rate > 337500)
9660 cdclk = 450000;
9661 else
9662 cdclk = 337500;
9663
9664 /*
9665 * FIXME move the cdclk caclulation to
9666 * compute_config() so we can fail gracegully.
9667 */
9668 if (cdclk > dev_priv->max_cdclk_freq) {
9669 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9670 cdclk, dev_priv->max_cdclk_freq);
9671 cdclk = dev_priv->max_cdclk_freq;
9672 }
9673
9674 return cdclk;
9675 }
9676
9677 static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9678 {
9679 struct drm_i915_private *dev_priv = to_i915(state->dev);
9680 struct drm_crtc *crtc;
9681 struct drm_crtc_state *crtc_state;
9682 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9683 int cdclk, i;
9684
9685 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9686
9687 if (cdclk == dev_priv->cdclk_freq)
9688 return 0;
9689
9690 /* add all active pipes to the state */
9691 for_each_crtc(state->dev, crtc) {
9692 if (!crtc->state->enable)
9693 continue;
9694
9695 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9696 if (IS_ERR(crtc_state))
9697 return PTR_ERR(crtc_state);
9698 }
9699
9700 /* disable/enable all currently active pipes while we change cdclk */
9701 for_each_crtc_in_state(state, crtc, crtc_state, i)
9702 if (crtc_state->enable)
9703 crtc_state->mode_changed = true;
9704
9705 return 0;
9706 }
9707
9708 static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9709 {
9710 struct drm_device *dev = state->dev;
9711 struct drm_i915_private *dev_priv = dev->dev_private;
9712 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9713 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9714
9715 if (req_cdclk != dev_priv->cdclk_freq)
9716 broadwell_set_cdclk(dev, req_cdclk);
9717 }
9718
9719 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9720 struct intel_crtc_state *crtc_state)
9721 {
9722 if (!intel_ddi_pll_select(crtc, crtc_state))
9723 return -EINVAL;
9724
9725 crtc->lowfreq_avail = false;
9726
9727 return 0;
9728 }
9729
9730 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9731 enum port port,
9732 struct intel_crtc_state *pipe_config)
9733 {
9734 switch (port) {
9735 case PORT_A:
9736 pipe_config->ddi_pll_sel = SKL_DPLL0;
9737 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9738 break;
9739 case PORT_B:
9740 pipe_config->ddi_pll_sel = SKL_DPLL1;
9741 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9742 break;
9743 case PORT_C:
9744 pipe_config->ddi_pll_sel = SKL_DPLL2;
9745 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9746 break;
9747 default:
9748 DRM_ERROR("Incorrect port type\n");
9749 }
9750 }
9751
9752 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9753 enum port port,
9754 struct intel_crtc_state *pipe_config)
9755 {
9756 u32 temp, dpll_ctl1;
9757
9758 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9759 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9760
9761 switch (pipe_config->ddi_pll_sel) {
9762 case SKL_DPLL0:
9763 /*
9764 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9765 * of the shared DPLL framework and thus needs to be read out
9766 * separately
9767 */
9768 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9769 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9770 break;
9771 case SKL_DPLL1:
9772 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9773 break;
9774 case SKL_DPLL2:
9775 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9776 break;
9777 case SKL_DPLL3:
9778 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9779 break;
9780 }
9781 }
9782
9783 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9784 enum port port,
9785 struct intel_crtc_state *pipe_config)
9786 {
9787 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9788
9789 switch (pipe_config->ddi_pll_sel) {
9790 case PORT_CLK_SEL_WRPLL1:
9791 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9792 break;
9793 case PORT_CLK_SEL_WRPLL2:
9794 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9795 break;
9796 }
9797 }
9798
9799 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9800 struct intel_crtc_state *pipe_config)
9801 {
9802 struct drm_device *dev = crtc->base.dev;
9803 struct drm_i915_private *dev_priv = dev->dev_private;
9804 struct intel_shared_dpll *pll;
9805 enum port port;
9806 uint32_t tmp;
9807
9808 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9809
9810 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9811
9812 if (IS_SKYLAKE(dev))
9813 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9814 else if (IS_BROXTON(dev))
9815 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9816 else
9817 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9818
9819 if (pipe_config->shared_dpll >= 0) {
9820 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9821
9822 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9823 &pipe_config->dpll_hw_state));
9824 }
9825
9826 /*
9827 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9828 * DDI E. So just check whether this pipe is wired to DDI E and whether
9829 * the PCH transcoder is on.
9830 */
9831 if (INTEL_INFO(dev)->gen < 9 &&
9832 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9833 pipe_config->has_pch_encoder = true;
9834
9835 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9836 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9837 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9838
9839 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9840 }
9841 }
9842
9843 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9844 struct intel_crtc_state *pipe_config)
9845 {
9846 struct drm_device *dev = crtc->base.dev;
9847 struct drm_i915_private *dev_priv = dev->dev_private;
9848 enum intel_display_power_domain pfit_domain;
9849 uint32_t tmp;
9850
9851 if (!intel_display_power_is_enabled(dev_priv,
9852 POWER_DOMAIN_PIPE(crtc->pipe)))
9853 return false;
9854
9855 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9856 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9857
9858 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9859 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9860 enum pipe trans_edp_pipe;
9861 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9862 default:
9863 WARN(1, "unknown pipe linked to edp transcoder\n");
9864 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9865 case TRANS_DDI_EDP_INPUT_A_ON:
9866 trans_edp_pipe = PIPE_A;
9867 break;
9868 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9869 trans_edp_pipe = PIPE_B;
9870 break;
9871 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9872 trans_edp_pipe = PIPE_C;
9873 break;
9874 }
9875
9876 if (trans_edp_pipe == crtc->pipe)
9877 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9878 }
9879
9880 if (!intel_display_power_is_enabled(dev_priv,
9881 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9882 return false;
9883
9884 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9885 if (!(tmp & PIPECONF_ENABLE))
9886 return false;
9887
9888 haswell_get_ddi_port_state(crtc, pipe_config);
9889
9890 intel_get_pipe_timings(crtc, pipe_config);
9891
9892 if (INTEL_INFO(dev)->gen >= 9) {
9893 skl_init_scalers(dev, crtc, pipe_config);
9894 }
9895
9896 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9897
9898 if (INTEL_INFO(dev)->gen >= 9) {
9899 pipe_config->scaler_state.scaler_id = -1;
9900 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9901 }
9902
9903 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9904 if (INTEL_INFO(dev)->gen == 9)
9905 skylake_get_pfit_config(crtc, pipe_config);
9906 else if (INTEL_INFO(dev)->gen < 9)
9907 ironlake_get_pfit_config(crtc, pipe_config);
9908 else
9909 MISSING_CASE(INTEL_INFO(dev)->gen);
9910 }
9911
9912 if (IS_HASWELL(dev))
9913 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9914 (I915_READ(IPS_CTL) & IPS_ENABLE);
9915
9916 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9917 pipe_config->pixel_multiplier =
9918 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9919 } else {
9920 pipe_config->pixel_multiplier = 1;
9921 }
9922
9923 return true;
9924 }
9925
9926 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9927 {
9928 struct drm_device *dev = crtc->dev;
9929 struct drm_i915_private *dev_priv = dev->dev_private;
9930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9931 uint32_t cntl = 0, size = 0;
9932
9933 if (base) {
9934 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9935 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9936 unsigned int stride = roundup_pow_of_two(width) * 4;
9937
9938 switch (stride) {
9939 default:
9940 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9941 width, stride);
9942 stride = 256;
9943 /* fallthrough */
9944 case 256:
9945 case 512:
9946 case 1024:
9947 case 2048:
9948 break;
9949 }
9950
9951 cntl |= CURSOR_ENABLE |
9952 CURSOR_GAMMA_ENABLE |
9953 CURSOR_FORMAT_ARGB |
9954 CURSOR_STRIDE(stride);
9955
9956 size = (height << 12) | width;
9957 }
9958
9959 if (intel_crtc->cursor_cntl != 0 &&
9960 (intel_crtc->cursor_base != base ||
9961 intel_crtc->cursor_size != size ||
9962 intel_crtc->cursor_cntl != cntl)) {
9963 /* On these chipsets we can only modify the base/size/stride
9964 * whilst the cursor is disabled.
9965 */
9966 I915_WRITE(_CURACNTR, 0);
9967 POSTING_READ(_CURACNTR);
9968 intel_crtc->cursor_cntl = 0;
9969 }
9970
9971 if (intel_crtc->cursor_base != base) {
9972 I915_WRITE(_CURABASE, base);
9973 intel_crtc->cursor_base = base;
9974 }
9975
9976 if (intel_crtc->cursor_size != size) {
9977 I915_WRITE(CURSIZE, size);
9978 intel_crtc->cursor_size = size;
9979 }
9980
9981 if (intel_crtc->cursor_cntl != cntl) {
9982 I915_WRITE(_CURACNTR, cntl);
9983 POSTING_READ(_CURACNTR);
9984 intel_crtc->cursor_cntl = cntl;
9985 }
9986 }
9987
9988 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9989 {
9990 struct drm_device *dev = crtc->dev;
9991 struct drm_i915_private *dev_priv = dev->dev_private;
9992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9993 int pipe = intel_crtc->pipe;
9994 uint32_t cntl;
9995
9996 cntl = 0;
9997 if (base) {
9998 cntl = MCURSOR_GAMMA_ENABLE;
9999 switch (intel_crtc->base.cursor->state->crtc_w) {
10000 case 64:
10001 cntl |= CURSOR_MODE_64_ARGB_AX;
10002 break;
10003 case 128:
10004 cntl |= CURSOR_MODE_128_ARGB_AX;
10005 break;
10006 case 256:
10007 cntl |= CURSOR_MODE_256_ARGB_AX;
10008 break;
10009 default:
10010 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10011 return;
10012 }
10013 cntl |= pipe << 28; /* Connect to correct pipe */
10014
10015 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10016 cntl |= CURSOR_PIPE_CSC_ENABLE;
10017 }
10018
10019 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10020 cntl |= CURSOR_ROTATE_180;
10021
10022 if (intel_crtc->cursor_cntl != cntl) {
10023 I915_WRITE(CURCNTR(pipe), cntl);
10024 POSTING_READ(CURCNTR(pipe));
10025 intel_crtc->cursor_cntl = cntl;
10026 }
10027
10028 /* and commit changes on next vblank */
10029 I915_WRITE(CURBASE(pipe), base);
10030 POSTING_READ(CURBASE(pipe));
10031
10032 intel_crtc->cursor_base = base;
10033 }
10034
10035 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10036 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10037 bool on)
10038 {
10039 struct drm_device *dev = crtc->dev;
10040 struct drm_i915_private *dev_priv = dev->dev_private;
10041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10042 int pipe = intel_crtc->pipe;
10043 int x = crtc->cursor_x;
10044 int y = crtc->cursor_y;
10045 u32 base = 0, pos = 0;
10046
10047 if (on)
10048 base = intel_crtc->cursor_addr;
10049
10050 if (x >= intel_crtc->config->pipe_src_w)
10051 base = 0;
10052
10053 if (y >= intel_crtc->config->pipe_src_h)
10054 base = 0;
10055
10056 if (x < 0) {
10057 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10058 base = 0;
10059
10060 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10061 x = -x;
10062 }
10063 pos |= x << CURSOR_X_SHIFT;
10064
10065 if (y < 0) {
10066 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10067 base = 0;
10068
10069 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10070 y = -y;
10071 }
10072 pos |= y << CURSOR_Y_SHIFT;
10073
10074 if (base == 0 && intel_crtc->cursor_base == 0)
10075 return;
10076
10077 I915_WRITE(CURPOS(pipe), pos);
10078
10079 /* ILK+ do this automagically */
10080 if (HAS_GMCH_DISPLAY(dev) &&
10081 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10082 base += (intel_crtc->base.cursor->state->crtc_h *
10083 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10084 }
10085
10086 if (IS_845G(dev) || IS_I865G(dev))
10087 i845_update_cursor(crtc, base);
10088 else
10089 i9xx_update_cursor(crtc, base);
10090 }
10091
10092 static bool cursor_size_ok(struct drm_device *dev,
10093 uint32_t width, uint32_t height)
10094 {
10095 if (width == 0 || height == 0)
10096 return false;
10097
10098 /*
10099 * 845g/865g are special in that they are only limited by
10100 * the width of their cursors, the height is arbitrary up to
10101 * the precision of the register. Everything else requires
10102 * square cursors, limited to a few power-of-two sizes.
10103 */
10104 if (IS_845G(dev) || IS_I865G(dev)) {
10105 if ((width & 63) != 0)
10106 return false;
10107
10108 if (width > (IS_845G(dev) ? 64 : 512))
10109 return false;
10110
10111 if (height > 1023)
10112 return false;
10113 } else {
10114 switch (width | height) {
10115 case 256:
10116 case 128:
10117 if (IS_GEN2(dev))
10118 return false;
10119 case 64:
10120 break;
10121 default:
10122 return false;
10123 }
10124 }
10125
10126 return true;
10127 }
10128
10129 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10130 u16 *blue, uint32_t start, uint32_t size)
10131 {
10132 int end = (start + size > 256) ? 256 : start + size, i;
10133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10134
10135 for (i = start; i < end; i++) {
10136 intel_crtc->lut_r[i] = red[i] >> 8;
10137 intel_crtc->lut_g[i] = green[i] >> 8;
10138 intel_crtc->lut_b[i] = blue[i] >> 8;
10139 }
10140
10141 intel_crtc_load_lut(crtc);
10142 }
10143
10144 /* VESA 640x480x72Hz mode to set on the pipe */
10145 static struct drm_display_mode load_detect_mode = {
10146 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10147 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10148 };
10149
10150 struct drm_framebuffer *
10151 __intel_framebuffer_create(struct drm_device *dev,
10152 struct drm_mode_fb_cmd2 *mode_cmd,
10153 struct drm_i915_gem_object *obj)
10154 {
10155 struct intel_framebuffer *intel_fb;
10156 int ret;
10157
10158 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10159 if (!intel_fb) {
10160 drm_gem_object_unreference(&obj->base);
10161 return ERR_PTR(-ENOMEM);
10162 }
10163
10164 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10165 if (ret)
10166 goto err;
10167
10168 return &intel_fb->base;
10169 err:
10170 drm_gem_object_unreference(&obj->base);
10171 kfree(intel_fb);
10172
10173 return ERR_PTR(ret);
10174 }
10175
10176 static struct drm_framebuffer *
10177 intel_framebuffer_create(struct drm_device *dev,
10178 struct drm_mode_fb_cmd2 *mode_cmd,
10179 struct drm_i915_gem_object *obj)
10180 {
10181 struct drm_framebuffer *fb;
10182 int ret;
10183
10184 ret = i915_mutex_lock_interruptible(dev);
10185 if (ret)
10186 return ERR_PTR(ret);
10187 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10188 mutex_unlock(&dev->struct_mutex);
10189
10190 return fb;
10191 }
10192
10193 static u32
10194 intel_framebuffer_pitch_for_width(int width, int bpp)
10195 {
10196 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10197 return ALIGN(pitch, 64);
10198 }
10199
10200 static u32
10201 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10202 {
10203 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10204 return PAGE_ALIGN(pitch * mode->vdisplay);
10205 }
10206
10207 static struct drm_framebuffer *
10208 intel_framebuffer_create_for_mode(struct drm_device *dev,
10209 struct drm_display_mode *mode,
10210 int depth, int bpp)
10211 {
10212 struct drm_i915_gem_object *obj;
10213 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10214
10215 obj = i915_gem_alloc_object(dev,
10216 intel_framebuffer_size_for_mode(mode, bpp));
10217 if (obj == NULL)
10218 return ERR_PTR(-ENOMEM);
10219
10220 mode_cmd.width = mode->hdisplay;
10221 mode_cmd.height = mode->vdisplay;
10222 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10223 bpp);
10224 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10225
10226 return intel_framebuffer_create(dev, &mode_cmd, obj);
10227 }
10228
10229 static struct drm_framebuffer *
10230 mode_fits_in_fbdev(struct drm_device *dev,
10231 struct drm_display_mode *mode)
10232 {
10233 #ifdef CONFIG_DRM_I915_FBDEV
10234 struct drm_i915_private *dev_priv = dev->dev_private;
10235 struct drm_i915_gem_object *obj;
10236 struct drm_framebuffer *fb;
10237
10238 if (!dev_priv->fbdev)
10239 return NULL;
10240
10241 if (!dev_priv->fbdev->fb)
10242 return NULL;
10243
10244 obj = dev_priv->fbdev->fb->obj;
10245 BUG_ON(!obj);
10246
10247 fb = &dev_priv->fbdev->fb->base;
10248 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10249 fb->bits_per_pixel))
10250 return NULL;
10251
10252 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10253 return NULL;
10254
10255 return fb;
10256 #else
10257 return NULL;
10258 #endif
10259 }
10260
10261 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10262 struct drm_crtc *crtc,
10263 struct drm_display_mode *mode,
10264 struct drm_framebuffer *fb,
10265 int x, int y)
10266 {
10267 struct drm_plane_state *plane_state;
10268 int hdisplay, vdisplay;
10269 int ret;
10270
10271 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10272 if (IS_ERR(plane_state))
10273 return PTR_ERR(plane_state);
10274
10275 if (mode)
10276 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10277 else
10278 hdisplay = vdisplay = 0;
10279
10280 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10281 if (ret)
10282 return ret;
10283 drm_atomic_set_fb_for_plane(plane_state, fb);
10284 plane_state->crtc_x = 0;
10285 plane_state->crtc_y = 0;
10286 plane_state->crtc_w = hdisplay;
10287 plane_state->crtc_h = vdisplay;
10288 plane_state->src_x = x << 16;
10289 plane_state->src_y = y << 16;
10290 plane_state->src_w = hdisplay << 16;
10291 plane_state->src_h = vdisplay << 16;
10292
10293 return 0;
10294 }
10295
10296 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10297 struct drm_display_mode *mode,
10298 struct intel_load_detect_pipe *old,
10299 struct drm_modeset_acquire_ctx *ctx)
10300 {
10301 struct intel_crtc *intel_crtc;
10302 struct intel_encoder *intel_encoder =
10303 intel_attached_encoder(connector);
10304 struct drm_crtc *possible_crtc;
10305 struct drm_encoder *encoder = &intel_encoder->base;
10306 struct drm_crtc *crtc = NULL;
10307 struct drm_device *dev = encoder->dev;
10308 struct drm_framebuffer *fb;
10309 struct drm_mode_config *config = &dev->mode_config;
10310 struct drm_atomic_state *state = NULL;
10311 struct drm_connector_state *connector_state;
10312 struct intel_crtc_state *crtc_state;
10313 int ret, i = -1;
10314
10315 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10316 connector->base.id, connector->name,
10317 encoder->base.id, encoder->name);
10318
10319 retry:
10320 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10321 if (ret)
10322 goto fail_unlock;
10323
10324 /*
10325 * Algorithm gets a little messy:
10326 *
10327 * - if the connector already has an assigned crtc, use it (but make
10328 * sure it's on first)
10329 *
10330 * - try to find the first unused crtc that can drive this connector,
10331 * and use that if we find one
10332 */
10333
10334 /* See if we already have a CRTC for this connector */
10335 if (encoder->crtc) {
10336 crtc = encoder->crtc;
10337
10338 ret = drm_modeset_lock(&crtc->mutex, ctx);
10339 if (ret)
10340 goto fail_unlock;
10341 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10342 if (ret)
10343 goto fail_unlock;
10344
10345 old->dpms_mode = connector->dpms;
10346 old->load_detect_temp = false;
10347
10348 /* Make sure the crtc and connector are running */
10349 if (connector->dpms != DRM_MODE_DPMS_ON)
10350 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10351
10352 return true;
10353 }
10354
10355 /* Find an unused one (if possible) */
10356 for_each_crtc(dev, possible_crtc) {
10357 i++;
10358 if (!(encoder->possible_crtcs & (1 << i)))
10359 continue;
10360 if (possible_crtc->state->enable)
10361 continue;
10362 /* This can occur when applying the pipe A quirk on resume. */
10363 if (to_intel_crtc(possible_crtc)->new_enabled)
10364 continue;
10365
10366 crtc = possible_crtc;
10367 break;
10368 }
10369
10370 /*
10371 * If we didn't find an unused CRTC, don't use any.
10372 */
10373 if (!crtc) {
10374 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10375 goto fail_unlock;
10376 }
10377
10378 ret = drm_modeset_lock(&crtc->mutex, ctx);
10379 if (ret)
10380 goto fail_unlock;
10381 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10382 if (ret)
10383 goto fail_unlock;
10384 intel_encoder->new_crtc = to_intel_crtc(crtc);
10385 to_intel_connector(connector)->new_encoder = intel_encoder;
10386
10387 intel_crtc = to_intel_crtc(crtc);
10388 intel_crtc->new_enabled = true;
10389 old->dpms_mode = connector->dpms;
10390 old->load_detect_temp = true;
10391 old->release_fb = NULL;
10392
10393 state = drm_atomic_state_alloc(dev);
10394 if (!state)
10395 return false;
10396
10397 state->acquire_ctx = ctx;
10398
10399 connector_state = drm_atomic_get_connector_state(state, connector);
10400 if (IS_ERR(connector_state)) {
10401 ret = PTR_ERR(connector_state);
10402 goto fail;
10403 }
10404
10405 connector_state->crtc = crtc;
10406 connector_state->best_encoder = &intel_encoder->base;
10407
10408 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10409 if (IS_ERR(crtc_state)) {
10410 ret = PTR_ERR(crtc_state);
10411 goto fail;
10412 }
10413
10414 crtc_state->base.active = crtc_state->base.enable = true;
10415
10416 if (!mode)
10417 mode = &load_detect_mode;
10418
10419 /* We need a framebuffer large enough to accommodate all accesses
10420 * that the plane may generate whilst we perform load detection.
10421 * We can not rely on the fbcon either being present (we get called
10422 * during its initialisation to detect all boot displays, or it may
10423 * not even exist) or that it is large enough to satisfy the
10424 * requested mode.
10425 */
10426 fb = mode_fits_in_fbdev(dev, mode);
10427 if (fb == NULL) {
10428 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10429 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10430 old->release_fb = fb;
10431 } else
10432 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10433 if (IS_ERR(fb)) {
10434 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10435 goto fail;
10436 }
10437
10438 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10439 if (ret)
10440 goto fail;
10441
10442 drm_mode_copy(&crtc_state->base.mode, mode);
10443
10444 if (intel_set_mode(state)) {
10445 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10446 if (old->release_fb)
10447 old->release_fb->funcs->destroy(old->release_fb);
10448 goto fail;
10449 }
10450 crtc->primary->crtc = crtc;
10451
10452 /* let the connector get through one full cycle before testing */
10453 intel_wait_for_vblank(dev, intel_crtc->pipe);
10454 return true;
10455
10456 fail:
10457 intel_crtc->new_enabled = crtc->state->enable;
10458 fail_unlock:
10459 drm_atomic_state_free(state);
10460 state = NULL;
10461
10462 if (ret == -EDEADLK) {
10463 drm_modeset_backoff(ctx);
10464 goto retry;
10465 }
10466
10467 return false;
10468 }
10469
10470 void intel_release_load_detect_pipe(struct drm_connector *connector,
10471 struct intel_load_detect_pipe *old,
10472 struct drm_modeset_acquire_ctx *ctx)
10473 {
10474 struct drm_device *dev = connector->dev;
10475 struct intel_encoder *intel_encoder =
10476 intel_attached_encoder(connector);
10477 struct drm_encoder *encoder = &intel_encoder->base;
10478 struct drm_crtc *crtc = encoder->crtc;
10479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10480 struct drm_atomic_state *state;
10481 struct drm_connector_state *connector_state;
10482 struct intel_crtc_state *crtc_state;
10483 int ret;
10484
10485 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10486 connector->base.id, connector->name,
10487 encoder->base.id, encoder->name);
10488
10489 if (old->load_detect_temp) {
10490 state = drm_atomic_state_alloc(dev);
10491 if (!state)
10492 goto fail;
10493
10494 state->acquire_ctx = ctx;
10495
10496 connector_state = drm_atomic_get_connector_state(state, connector);
10497 if (IS_ERR(connector_state))
10498 goto fail;
10499
10500 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10501 if (IS_ERR(crtc_state))
10502 goto fail;
10503
10504 to_intel_connector(connector)->new_encoder = NULL;
10505 intel_encoder->new_crtc = NULL;
10506 intel_crtc->new_enabled = false;
10507
10508 connector_state->best_encoder = NULL;
10509 connector_state->crtc = NULL;
10510
10511 crtc_state->base.enable = crtc_state->base.active = false;
10512
10513 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10514 0, 0);
10515 if (ret)
10516 goto fail;
10517
10518 ret = intel_set_mode(state);
10519 if (ret)
10520 goto fail;
10521
10522 if (old->release_fb) {
10523 drm_framebuffer_unregister_private(old->release_fb);
10524 drm_framebuffer_unreference(old->release_fb);
10525 }
10526
10527 return;
10528 }
10529
10530 /* Switch crtc and encoder back off if necessary */
10531 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10532 connector->funcs->dpms(connector, old->dpms_mode);
10533
10534 return;
10535 fail:
10536 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10537 drm_atomic_state_free(state);
10538 }
10539
10540 static int i9xx_pll_refclk(struct drm_device *dev,
10541 const struct intel_crtc_state *pipe_config)
10542 {
10543 struct drm_i915_private *dev_priv = dev->dev_private;
10544 u32 dpll = pipe_config->dpll_hw_state.dpll;
10545
10546 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10547 return dev_priv->vbt.lvds_ssc_freq;
10548 else if (HAS_PCH_SPLIT(dev))
10549 return 120000;
10550 else if (!IS_GEN2(dev))
10551 return 96000;
10552 else
10553 return 48000;
10554 }
10555
10556 /* Returns the clock of the currently programmed mode of the given pipe. */
10557 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10558 struct intel_crtc_state *pipe_config)
10559 {
10560 struct drm_device *dev = crtc->base.dev;
10561 struct drm_i915_private *dev_priv = dev->dev_private;
10562 int pipe = pipe_config->cpu_transcoder;
10563 u32 dpll = pipe_config->dpll_hw_state.dpll;
10564 u32 fp;
10565 intel_clock_t clock;
10566 int refclk = i9xx_pll_refclk(dev, pipe_config);
10567
10568 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10569 fp = pipe_config->dpll_hw_state.fp0;
10570 else
10571 fp = pipe_config->dpll_hw_state.fp1;
10572
10573 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10574 if (IS_PINEVIEW(dev)) {
10575 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10576 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10577 } else {
10578 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10579 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10580 }
10581
10582 if (!IS_GEN2(dev)) {
10583 if (IS_PINEVIEW(dev))
10584 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10585 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10586 else
10587 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10588 DPLL_FPA01_P1_POST_DIV_SHIFT);
10589
10590 switch (dpll & DPLL_MODE_MASK) {
10591 case DPLLB_MODE_DAC_SERIAL:
10592 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10593 5 : 10;
10594 break;
10595 case DPLLB_MODE_LVDS:
10596 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10597 7 : 14;
10598 break;
10599 default:
10600 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10601 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10602 return;
10603 }
10604
10605 if (IS_PINEVIEW(dev))
10606 pineview_clock(refclk, &clock);
10607 else
10608 i9xx_clock(refclk, &clock);
10609 } else {
10610 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10611 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10612
10613 if (is_lvds) {
10614 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10615 DPLL_FPA01_P1_POST_DIV_SHIFT);
10616
10617 if (lvds & LVDS_CLKB_POWER_UP)
10618 clock.p2 = 7;
10619 else
10620 clock.p2 = 14;
10621 } else {
10622 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10623 clock.p1 = 2;
10624 else {
10625 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10626 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10627 }
10628 if (dpll & PLL_P2_DIVIDE_BY_4)
10629 clock.p2 = 4;
10630 else
10631 clock.p2 = 2;
10632 }
10633
10634 i9xx_clock(refclk, &clock);
10635 }
10636
10637 /*
10638 * This value includes pixel_multiplier. We will use
10639 * port_clock to compute adjusted_mode.crtc_clock in the
10640 * encoder's get_config() function.
10641 */
10642 pipe_config->port_clock = clock.dot;
10643 }
10644
10645 int intel_dotclock_calculate(int link_freq,
10646 const struct intel_link_m_n *m_n)
10647 {
10648 /*
10649 * The calculation for the data clock is:
10650 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10651 * But we want to avoid losing precison if possible, so:
10652 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10653 *
10654 * and the link clock is simpler:
10655 * link_clock = (m * link_clock) / n
10656 */
10657
10658 if (!m_n->link_n)
10659 return 0;
10660
10661 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10662 }
10663
10664 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10665 struct intel_crtc_state *pipe_config)
10666 {
10667 struct drm_device *dev = crtc->base.dev;
10668
10669 /* read out port_clock from the DPLL */
10670 i9xx_crtc_clock_get(crtc, pipe_config);
10671
10672 /*
10673 * This value does not include pixel_multiplier.
10674 * We will check that port_clock and adjusted_mode.crtc_clock
10675 * agree once we know their relationship in the encoder's
10676 * get_config() function.
10677 */
10678 pipe_config->base.adjusted_mode.crtc_clock =
10679 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10680 &pipe_config->fdi_m_n);
10681 }
10682
10683 /** Returns the currently programmed mode of the given pipe. */
10684 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10685 struct drm_crtc *crtc)
10686 {
10687 struct drm_i915_private *dev_priv = dev->dev_private;
10688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10689 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10690 struct drm_display_mode *mode;
10691 struct intel_crtc_state pipe_config;
10692 int htot = I915_READ(HTOTAL(cpu_transcoder));
10693 int hsync = I915_READ(HSYNC(cpu_transcoder));
10694 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10695 int vsync = I915_READ(VSYNC(cpu_transcoder));
10696 enum pipe pipe = intel_crtc->pipe;
10697
10698 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10699 if (!mode)
10700 return NULL;
10701
10702 /*
10703 * Construct a pipe_config sufficient for getting the clock info
10704 * back out of crtc_clock_get.
10705 *
10706 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10707 * to use a real value here instead.
10708 */
10709 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10710 pipe_config.pixel_multiplier = 1;
10711 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10712 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10713 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10714 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10715
10716 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10717 mode->hdisplay = (htot & 0xffff) + 1;
10718 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10719 mode->hsync_start = (hsync & 0xffff) + 1;
10720 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10721 mode->vdisplay = (vtot & 0xffff) + 1;
10722 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10723 mode->vsync_start = (vsync & 0xffff) + 1;
10724 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10725
10726 drm_mode_set_name(mode);
10727
10728 return mode;
10729 }
10730
10731 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10732 {
10733 struct drm_device *dev = crtc->dev;
10734 struct drm_i915_private *dev_priv = dev->dev_private;
10735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10736
10737 if (!HAS_GMCH_DISPLAY(dev))
10738 return;
10739
10740 if (!dev_priv->lvds_downclock_avail)
10741 return;
10742
10743 /*
10744 * Since this is called by a timer, we should never get here in
10745 * the manual case.
10746 */
10747 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10748 int pipe = intel_crtc->pipe;
10749 int dpll_reg = DPLL(pipe);
10750 int dpll;
10751
10752 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10753
10754 assert_panel_unlocked(dev_priv, pipe);
10755
10756 dpll = I915_READ(dpll_reg);
10757 dpll |= DISPLAY_RATE_SELECT_FPA1;
10758 I915_WRITE(dpll_reg, dpll);
10759 intel_wait_for_vblank(dev, pipe);
10760 dpll = I915_READ(dpll_reg);
10761 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10762 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10763 }
10764
10765 }
10766
10767 void intel_mark_busy(struct drm_device *dev)
10768 {
10769 struct drm_i915_private *dev_priv = dev->dev_private;
10770
10771 if (dev_priv->mm.busy)
10772 return;
10773
10774 intel_runtime_pm_get(dev_priv);
10775 i915_update_gfx_val(dev_priv);
10776 if (INTEL_INFO(dev)->gen >= 6)
10777 gen6_rps_busy(dev_priv);
10778 dev_priv->mm.busy = true;
10779 }
10780
10781 void intel_mark_idle(struct drm_device *dev)
10782 {
10783 struct drm_i915_private *dev_priv = dev->dev_private;
10784 struct drm_crtc *crtc;
10785
10786 if (!dev_priv->mm.busy)
10787 return;
10788
10789 dev_priv->mm.busy = false;
10790
10791 for_each_crtc(dev, crtc) {
10792 if (!crtc->primary->fb)
10793 continue;
10794
10795 intel_decrease_pllclock(crtc);
10796 }
10797
10798 if (INTEL_INFO(dev)->gen >= 6)
10799 gen6_rps_idle(dev->dev_private);
10800
10801 intel_runtime_pm_put(dev_priv);
10802 }
10803
10804 static void intel_crtc_destroy(struct drm_crtc *crtc)
10805 {
10806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10807 struct drm_device *dev = crtc->dev;
10808 struct intel_unpin_work *work;
10809
10810 spin_lock_irq(&dev->event_lock);
10811 work = intel_crtc->unpin_work;
10812 intel_crtc->unpin_work = NULL;
10813 spin_unlock_irq(&dev->event_lock);
10814
10815 if (work) {
10816 cancel_work_sync(&work->work);
10817 kfree(work);
10818 }
10819
10820 drm_crtc_cleanup(crtc);
10821
10822 kfree(intel_crtc);
10823 }
10824
10825 static void intel_unpin_work_fn(struct work_struct *__work)
10826 {
10827 struct intel_unpin_work *work =
10828 container_of(__work, struct intel_unpin_work, work);
10829 struct drm_device *dev = work->crtc->dev;
10830 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10831
10832 mutex_lock(&dev->struct_mutex);
10833 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10834 drm_gem_object_unreference(&work->pending_flip_obj->base);
10835
10836 intel_fbc_update(dev);
10837
10838 if (work->flip_queued_req)
10839 i915_gem_request_assign(&work->flip_queued_req, NULL);
10840 mutex_unlock(&dev->struct_mutex);
10841
10842 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10843 drm_framebuffer_unreference(work->old_fb);
10844
10845 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10846 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10847
10848 kfree(work);
10849 }
10850
10851 static void do_intel_finish_page_flip(struct drm_device *dev,
10852 struct drm_crtc *crtc)
10853 {
10854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10855 struct intel_unpin_work *work;
10856 unsigned long flags;
10857
10858 /* Ignore early vblank irqs */
10859 if (intel_crtc == NULL)
10860 return;
10861
10862 /*
10863 * This is called both by irq handlers and the reset code (to complete
10864 * lost pageflips) so needs the full irqsave spinlocks.
10865 */
10866 spin_lock_irqsave(&dev->event_lock, flags);
10867 work = intel_crtc->unpin_work;
10868
10869 /* Ensure we don't miss a work->pending update ... */
10870 smp_rmb();
10871
10872 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10873 spin_unlock_irqrestore(&dev->event_lock, flags);
10874 return;
10875 }
10876
10877 page_flip_completed(intel_crtc);
10878
10879 spin_unlock_irqrestore(&dev->event_lock, flags);
10880 }
10881
10882 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10883 {
10884 struct drm_i915_private *dev_priv = dev->dev_private;
10885 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10886
10887 do_intel_finish_page_flip(dev, crtc);
10888 }
10889
10890 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10891 {
10892 struct drm_i915_private *dev_priv = dev->dev_private;
10893 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10894
10895 do_intel_finish_page_flip(dev, crtc);
10896 }
10897
10898 /* Is 'a' after or equal to 'b'? */
10899 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10900 {
10901 return !((a - b) & 0x80000000);
10902 }
10903
10904 static bool page_flip_finished(struct intel_crtc *crtc)
10905 {
10906 struct drm_device *dev = crtc->base.dev;
10907 struct drm_i915_private *dev_priv = dev->dev_private;
10908
10909 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10910 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10911 return true;
10912
10913 /*
10914 * The relevant registers doen't exist on pre-ctg.
10915 * As the flip done interrupt doesn't trigger for mmio
10916 * flips on gmch platforms, a flip count check isn't
10917 * really needed there. But since ctg has the registers,
10918 * include it in the check anyway.
10919 */
10920 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10921 return true;
10922
10923 /*
10924 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10925 * used the same base address. In that case the mmio flip might
10926 * have completed, but the CS hasn't even executed the flip yet.
10927 *
10928 * A flip count check isn't enough as the CS might have updated
10929 * the base address just after start of vblank, but before we
10930 * managed to process the interrupt. This means we'd complete the
10931 * CS flip too soon.
10932 *
10933 * Combining both checks should get us a good enough result. It may
10934 * still happen that the CS flip has been executed, but has not
10935 * yet actually completed. But in case the base address is the same
10936 * anyway, we don't really care.
10937 */
10938 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10939 crtc->unpin_work->gtt_offset &&
10940 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10941 crtc->unpin_work->flip_count);
10942 }
10943
10944 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10945 {
10946 struct drm_i915_private *dev_priv = dev->dev_private;
10947 struct intel_crtc *intel_crtc =
10948 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10949 unsigned long flags;
10950
10951
10952 /*
10953 * This is called both by irq handlers and the reset code (to complete
10954 * lost pageflips) so needs the full irqsave spinlocks.
10955 *
10956 * NB: An MMIO update of the plane base pointer will also
10957 * generate a page-flip completion irq, i.e. every modeset
10958 * is also accompanied by a spurious intel_prepare_page_flip().
10959 */
10960 spin_lock_irqsave(&dev->event_lock, flags);
10961 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10962 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10963 spin_unlock_irqrestore(&dev->event_lock, flags);
10964 }
10965
10966 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10967 {
10968 /* Ensure that the work item is consistent when activating it ... */
10969 smp_wmb();
10970 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10971 /* and that it is marked active as soon as the irq could fire. */
10972 smp_wmb();
10973 }
10974
10975 static int intel_gen2_queue_flip(struct drm_device *dev,
10976 struct drm_crtc *crtc,
10977 struct drm_framebuffer *fb,
10978 struct drm_i915_gem_object *obj,
10979 struct intel_engine_cs *ring,
10980 uint32_t flags)
10981 {
10982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10983 u32 flip_mask;
10984 int ret;
10985
10986 ret = intel_ring_begin(ring, 6);
10987 if (ret)
10988 return ret;
10989
10990 /* Can't queue multiple flips, so wait for the previous
10991 * one to finish before executing the next.
10992 */
10993 if (intel_crtc->plane)
10994 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10995 else
10996 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10997 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10998 intel_ring_emit(ring, MI_NOOP);
10999 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11000 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11001 intel_ring_emit(ring, fb->pitches[0]);
11002 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11003 intel_ring_emit(ring, 0); /* aux display base address, unused */
11004
11005 intel_mark_page_flip_active(intel_crtc);
11006 __intel_ring_advance(ring);
11007 return 0;
11008 }
11009
11010 static int intel_gen3_queue_flip(struct drm_device *dev,
11011 struct drm_crtc *crtc,
11012 struct drm_framebuffer *fb,
11013 struct drm_i915_gem_object *obj,
11014 struct intel_engine_cs *ring,
11015 uint32_t flags)
11016 {
11017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11018 u32 flip_mask;
11019 int ret;
11020
11021 ret = intel_ring_begin(ring, 6);
11022 if (ret)
11023 return ret;
11024
11025 if (intel_crtc->plane)
11026 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11027 else
11028 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11029 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11030 intel_ring_emit(ring, MI_NOOP);
11031 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11032 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11033 intel_ring_emit(ring, fb->pitches[0]);
11034 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11035 intel_ring_emit(ring, MI_NOOP);
11036
11037 intel_mark_page_flip_active(intel_crtc);
11038 __intel_ring_advance(ring);
11039 return 0;
11040 }
11041
11042 static int intel_gen4_queue_flip(struct drm_device *dev,
11043 struct drm_crtc *crtc,
11044 struct drm_framebuffer *fb,
11045 struct drm_i915_gem_object *obj,
11046 struct intel_engine_cs *ring,
11047 uint32_t flags)
11048 {
11049 struct drm_i915_private *dev_priv = dev->dev_private;
11050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11051 uint32_t pf, pipesrc;
11052 int ret;
11053
11054 ret = intel_ring_begin(ring, 4);
11055 if (ret)
11056 return ret;
11057
11058 /* i965+ uses the linear or tiled offsets from the
11059 * Display Registers (which do not change across a page-flip)
11060 * so we need only reprogram the base address.
11061 */
11062 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11063 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11064 intel_ring_emit(ring, fb->pitches[0]);
11065 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11066 obj->tiling_mode);
11067
11068 /* XXX Enabling the panel-fitter across page-flip is so far
11069 * untested on non-native modes, so ignore it for now.
11070 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11071 */
11072 pf = 0;
11073 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11074 intel_ring_emit(ring, pf | pipesrc);
11075
11076 intel_mark_page_flip_active(intel_crtc);
11077 __intel_ring_advance(ring);
11078 return 0;
11079 }
11080
11081 static int intel_gen6_queue_flip(struct drm_device *dev,
11082 struct drm_crtc *crtc,
11083 struct drm_framebuffer *fb,
11084 struct drm_i915_gem_object *obj,
11085 struct intel_engine_cs *ring,
11086 uint32_t flags)
11087 {
11088 struct drm_i915_private *dev_priv = dev->dev_private;
11089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11090 uint32_t pf, pipesrc;
11091 int ret;
11092
11093 ret = intel_ring_begin(ring, 4);
11094 if (ret)
11095 return ret;
11096
11097 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11098 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11099 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11100 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11101
11102 /* Contrary to the suggestions in the documentation,
11103 * "Enable Panel Fitter" does not seem to be required when page
11104 * flipping with a non-native mode, and worse causes a normal
11105 * modeset to fail.
11106 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11107 */
11108 pf = 0;
11109 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11110 intel_ring_emit(ring, pf | pipesrc);
11111
11112 intel_mark_page_flip_active(intel_crtc);
11113 __intel_ring_advance(ring);
11114 return 0;
11115 }
11116
11117 static int intel_gen7_queue_flip(struct drm_device *dev,
11118 struct drm_crtc *crtc,
11119 struct drm_framebuffer *fb,
11120 struct drm_i915_gem_object *obj,
11121 struct intel_engine_cs *ring,
11122 uint32_t flags)
11123 {
11124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11125 uint32_t plane_bit = 0;
11126 int len, ret;
11127
11128 switch (intel_crtc->plane) {
11129 case PLANE_A:
11130 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11131 break;
11132 case PLANE_B:
11133 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11134 break;
11135 case PLANE_C:
11136 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11137 break;
11138 default:
11139 WARN_ONCE(1, "unknown plane in flip command\n");
11140 return -ENODEV;
11141 }
11142
11143 len = 4;
11144 if (ring->id == RCS) {
11145 len += 6;
11146 /*
11147 * On Gen 8, SRM is now taking an extra dword to accommodate
11148 * 48bits addresses, and we need a NOOP for the batch size to
11149 * stay even.
11150 */
11151 if (IS_GEN8(dev))
11152 len += 2;
11153 }
11154
11155 /*
11156 * BSpec MI_DISPLAY_FLIP for IVB:
11157 * "The full packet must be contained within the same cache line."
11158 *
11159 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11160 * cacheline, if we ever start emitting more commands before
11161 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11162 * then do the cacheline alignment, and finally emit the
11163 * MI_DISPLAY_FLIP.
11164 */
11165 ret = intel_ring_cacheline_align(ring);
11166 if (ret)
11167 return ret;
11168
11169 ret = intel_ring_begin(ring, len);
11170 if (ret)
11171 return ret;
11172
11173 /* Unmask the flip-done completion message. Note that the bspec says that
11174 * we should do this for both the BCS and RCS, and that we must not unmask
11175 * more than one flip event at any time (or ensure that one flip message
11176 * can be sent by waiting for flip-done prior to queueing new flips).
11177 * Experimentation says that BCS works despite DERRMR masking all
11178 * flip-done completion events and that unmasking all planes at once
11179 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11180 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11181 */
11182 if (ring->id == RCS) {
11183 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11184 intel_ring_emit(ring, DERRMR);
11185 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11186 DERRMR_PIPEB_PRI_FLIP_DONE |
11187 DERRMR_PIPEC_PRI_FLIP_DONE));
11188 if (IS_GEN8(dev))
11189 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11190 MI_SRM_LRM_GLOBAL_GTT);
11191 else
11192 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11193 MI_SRM_LRM_GLOBAL_GTT);
11194 intel_ring_emit(ring, DERRMR);
11195 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11196 if (IS_GEN8(dev)) {
11197 intel_ring_emit(ring, 0);
11198 intel_ring_emit(ring, MI_NOOP);
11199 }
11200 }
11201
11202 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11203 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11204 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11205 intel_ring_emit(ring, (MI_NOOP));
11206
11207 intel_mark_page_flip_active(intel_crtc);
11208 __intel_ring_advance(ring);
11209 return 0;
11210 }
11211
11212 static bool use_mmio_flip(struct intel_engine_cs *ring,
11213 struct drm_i915_gem_object *obj)
11214 {
11215 /*
11216 * This is not being used for older platforms, because
11217 * non-availability of flip done interrupt forces us to use
11218 * CS flips. Older platforms derive flip done using some clever
11219 * tricks involving the flip_pending status bits and vblank irqs.
11220 * So using MMIO flips there would disrupt this mechanism.
11221 */
11222
11223 if (ring == NULL)
11224 return true;
11225
11226 if (INTEL_INFO(ring->dev)->gen < 5)
11227 return false;
11228
11229 if (i915.use_mmio_flip < 0)
11230 return false;
11231 else if (i915.use_mmio_flip > 0)
11232 return true;
11233 else if (i915.enable_execlists)
11234 return true;
11235 else
11236 return ring != i915_gem_request_get_ring(obj->last_write_req);
11237 }
11238
11239 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11240 {
11241 struct drm_device *dev = intel_crtc->base.dev;
11242 struct drm_i915_private *dev_priv = dev->dev_private;
11243 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11244 const enum pipe pipe = intel_crtc->pipe;
11245 u32 ctl, stride;
11246
11247 ctl = I915_READ(PLANE_CTL(pipe, 0));
11248 ctl &= ~PLANE_CTL_TILED_MASK;
11249 switch (fb->modifier[0]) {
11250 case DRM_FORMAT_MOD_NONE:
11251 break;
11252 case I915_FORMAT_MOD_X_TILED:
11253 ctl |= PLANE_CTL_TILED_X;
11254 break;
11255 case I915_FORMAT_MOD_Y_TILED:
11256 ctl |= PLANE_CTL_TILED_Y;
11257 break;
11258 case I915_FORMAT_MOD_Yf_TILED:
11259 ctl |= PLANE_CTL_TILED_YF;
11260 break;
11261 default:
11262 MISSING_CASE(fb->modifier[0]);
11263 }
11264
11265 /*
11266 * The stride is either expressed as a multiple of 64 bytes chunks for
11267 * linear buffers or in number of tiles for tiled buffers.
11268 */
11269 stride = fb->pitches[0] /
11270 intel_fb_stride_alignment(dev, fb->modifier[0],
11271 fb->pixel_format);
11272
11273 /*
11274 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11275 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11276 */
11277 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11278 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11279
11280 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11281 POSTING_READ(PLANE_SURF(pipe, 0));
11282 }
11283
11284 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11285 {
11286 struct drm_device *dev = intel_crtc->base.dev;
11287 struct drm_i915_private *dev_priv = dev->dev_private;
11288 struct intel_framebuffer *intel_fb =
11289 to_intel_framebuffer(intel_crtc->base.primary->fb);
11290 struct drm_i915_gem_object *obj = intel_fb->obj;
11291 u32 dspcntr;
11292 u32 reg;
11293
11294 reg = DSPCNTR(intel_crtc->plane);
11295 dspcntr = I915_READ(reg);
11296
11297 if (obj->tiling_mode != I915_TILING_NONE)
11298 dspcntr |= DISPPLANE_TILED;
11299 else
11300 dspcntr &= ~DISPPLANE_TILED;
11301
11302 I915_WRITE(reg, dspcntr);
11303
11304 I915_WRITE(DSPSURF(intel_crtc->plane),
11305 intel_crtc->unpin_work->gtt_offset);
11306 POSTING_READ(DSPSURF(intel_crtc->plane));
11307
11308 }
11309
11310 /*
11311 * XXX: This is the temporary way to update the plane registers until we get
11312 * around to using the usual plane update functions for MMIO flips
11313 */
11314 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11315 {
11316 struct drm_device *dev = intel_crtc->base.dev;
11317 bool atomic_update;
11318 u32 start_vbl_count;
11319
11320 intel_mark_page_flip_active(intel_crtc);
11321
11322 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11323
11324 if (INTEL_INFO(dev)->gen >= 9)
11325 skl_do_mmio_flip(intel_crtc);
11326 else
11327 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11328 ilk_do_mmio_flip(intel_crtc);
11329
11330 if (atomic_update)
11331 intel_pipe_update_end(intel_crtc, start_vbl_count);
11332 }
11333
11334 static void intel_mmio_flip_work_func(struct work_struct *work)
11335 {
11336 struct intel_mmio_flip *mmio_flip =
11337 container_of(work, struct intel_mmio_flip, work);
11338
11339 if (mmio_flip->req)
11340 WARN_ON(__i915_wait_request(mmio_flip->req,
11341 mmio_flip->crtc->reset_counter,
11342 false, NULL,
11343 &mmio_flip->i915->rps.mmioflips));
11344
11345 intel_do_mmio_flip(mmio_flip->crtc);
11346
11347 i915_gem_request_unreference__unlocked(mmio_flip->req);
11348 kfree(mmio_flip);
11349 }
11350
11351 static int intel_queue_mmio_flip(struct drm_device *dev,
11352 struct drm_crtc *crtc,
11353 struct drm_framebuffer *fb,
11354 struct drm_i915_gem_object *obj,
11355 struct intel_engine_cs *ring,
11356 uint32_t flags)
11357 {
11358 struct intel_mmio_flip *mmio_flip;
11359
11360 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11361 if (mmio_flip == NULL)
11362 return -ENOMEM;
11363
11364 mmio_flip->i915 = to_i915(dev);
11365 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11366 mmio_flip->crtc = to_intel_crtc(crtc);
11367
11368 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11369 schedule_work(&mmio_flip->work);
11370
11371 return 0;
11372 }
11373
11374 static int intel_default_queue_flip(struct drm_device *dev,
11375 struct drm_crtc *crtc,
11376 struct drm_framebuffer *fb,
11377 struct drm_i915_gem_object *obj,
11378 struct intel_engine_cs *ring,
11379 uint32_t flags)
11380 {
11381 return -ENODEV;
11382 }
11383
11384 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11385 struct drm_crtc *crtc)
11386 {
11387 struct drm_i915_private *dev_priv = dev->dev_private;
11388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11389 struct intel_unpin_work *work = intel_crtc->unpin_work;
11390 u32 addr;
11391
11392 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11393 return true;
11394
11395 if (!work->enable_stall_check)
11396 return false;
11397
11398 if (work->flip_ready_vblank == 0) {
11399 if (work->flip_queued_req &&
11400 !i915_gem_request_completed(work->flip_queued_req, true))
11401 return false;
11402
11403 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11404 }
11405
11406 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11407 return false;
11408
11409 /* Potential stall - if we see that the flip has happened,
11410 * assume a missed interrupt. */
11411 if (INTEL_INFO(dev)->gen >= 4)
11412 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11413 else
11414 addr = I915_READ(DSPADDR(intel_crtc->plane));
11415
11416 /* There is a potential issue here with a false positive after a flip
11417 * to the same address. We could address this by checking for a
11418 * non-incrementing frame counter.
11419 */
11420 return addr == work->gtt_offset;
11421 }
11422
11423 void intel_check_page_flip(struct drm_device *dev, int pipe)
11424 {
11425 struct drm_i915_private *dev_priv = dev->dev_private;
11426 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11428 struct intel_unpin_work *work;
11429
11430 WARN_ON(!in_interrupt());
11431
11432 if (crtc == NULL)
11433 return;
11434
11435 spin_lock(&dev->event_lock);
11436 work = intel_crtc->unpin_work;
11437 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11438 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11439 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11440 page_flip_completed(intel_crtc);
11441 work = NULL;
11442 }
11443 if (work != NULL &&
11444 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11445 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11446 spin_unlock(&dev->event_lock);
11447 }
11448
11449 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11450 struct drm_framebuffer *fb,
11451 struct drm_pending_vblank_event *event,
11452 uint32_t page_flip_flags)
11453 {
11454 struct drm_device *dev = crtc->dev;
11455 struct drm_i915_private *dev_priv = dev->dev_private;
11456 struct drm_framebuffer *old_fb = crtc->primary->fb;
11457 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11459 struct drm_plane *primary = crtc->primary;
11460 enum pipe pipe = intel_crtc->pipe;
11461 struct intel_unpin_work *work;
11462 struct intel_engine_cs *ring;
11463 bool mmio_flip;
11464 int ret;
11465
11466 /*
11467 * drm_mode_page_flip_ioctl() should already catch this, but double
11468 * check to be safe. In the future we may enable pageflipping from
11469 * a disabled primary plane.
11470 */
11471 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11472 return -EBUSY;
11473
11474 /* Can't change pixel format via MI display flips. */
11475 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11476 return -EINVAL;
11477
11478 /*
11479 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11480 * Note that pitch changes could also affect these register.
11481 */
11482 if (INTEL_INFO(dev)->gen > 3 &&
11483 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11484 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11485 return -EINVAL;
11486
11487 if (i915_terminally_wedged(&dev_priv->gpu_error))
11488 goto out_hang;
11489
11490 work = kzalloc(sizeof(*work), GFP_KERNEL);
11491 if (work == NULL)
11492 return -ENOMEM;
11493
11494 work->event = event;
11495 work->crtc = crtc;
11496 work->old_fb = old_fb;
11497 INIT_WORK(&work->work, intel_unpin_work_fn);
11498
11499 ret = drm_crtc_vblank_get(crtc);
11500 if (ret)
11501 goto free_work;
11502
11503 /* We borrow the event spin lock for protecting unpin_work */
11504 spin_lock_irq(&dev->event_lock);
11505 if (intel_crtc->unpin_work) {
11506 /* Before declaring the flip queue wedged, check if
11507 * the hardware completed the operation behind our backs.
11508 */
11509 if (__intel_pageflip_stall_check(dev, crtc)) {
11510 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11511 page_flip_completed(intel_crtc);
11512 } else {
11513 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11514 spin_unlock_irq(&dev->event_lock);
11515
11516 drm_crtc_vblank_put(crtc);
11517 kfree(work);
11518 return -EBUSY;
11519 }
11520 }
11521 intel_crtc->unpin_work = work;
11522 spin_unlock_irq(&dev->event_lock);
11523
11524 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11525 flush_workqueue(dev_priv->wq);
11526
11527 /* Reference the objects for the scheduled work. */
11528 drm_framebuffer_reference(work->old_fb);
11529 drm_gem_object_reference(&obj->base);
11530
11531 crtc->primary->fb = fb;
11532 update_state_fb(crtc->primary);
11533
11534 work->pending_flip_obj = obj;
11535
11536 ret = i915_mutex_lock_interruptible(dev);
11537 if (ret)
11538 goto cleanup;
11539
11540 atomic_inc(&intel_crtc->unpin_work_count);
11541 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11542
11543 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11544 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11545
11546 if (IS_VALLEYVIEW(dev)) {
11547 ring = &dev_priv->ring[BCS];
11548 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11549 /* vlv: DISPLAY_FLIP fails to change tiling */
11550 ring = NULL;
11551 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11552 ring = &dev_priv->ring[BCS];
11553 } else if (INTEL_INFO(dev)->gen >= 7) {
11554 ring = i915_gem_request_get_ring(obj->last_write_req);
11555 if (ring == NULL || ring->id != RCS)
11556 ring = &dev_priv->ring[BCS];
11557 } else {
11558 ring = &dev_priv->ring[RCS];
11559 }
11560
11561 mmio_flip = use_mmio_flip(ring, obj);
11562
11563 /* When using CS flips, we want to emit semaphores between rings.
11564 * However, when using mmio flips we will create a task to do the
11565 * synchronisation, so all we want here is to pin the framebuffer
11566 * into the display plane and skip any waits.
11567 */
11568 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11569 crtc->primary->state,
11570 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11571 if (ret)
11572 goto cleanup_pending;
11573
11574 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11575 + intel_crtc->dspaddr_offset;
11576
11577 if (mmio_flip) {
11578 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11579 page_flip_flags);
11580 if (ret)
11581 goto cleanup_unpin;
11582
11583 i915_gem_request_assign(&work->flip_queued_req,
11584 obj->last_write_req);
11585 } else {
11586 if (obj->last_write_req) {
11587 ret = i915_gem_check_olr(obj->last_write_req);
11588 if (ret)
11589 goto cleanup_unpin;
11590 }
11591
11592 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11593 page_flip_flags);
11594 if (ret)
11595 goto cleanup_unpin;
11596
11597 i915_gem_request_assign(&work->flip_queued_req,
11598 intel_ring_get_request(ring));
11599 }
11600
11601 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11602 work->enable_stall_check = true;
11603
11604 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11605 INTEL_FRONTBUFFER_PRIMARY(pipe));
11606
11607 intel_fbc_disable(dev);
11608 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11609 mutex_unlock(&dev->struct_mutex);
11610
11611 trace_i915_flip_request(intel_crtc->plane, obj);
11612
11613 return 0;
11614
11615 cleanup_unpin:
11616 intel_unpin_fb_obj(fb, crtc->primary->state);
11617 cleanup_pending:
11618 atomic_dec(&intel_crtc->unpin_work_count);
11619 mutex_unlock(&dev->struct_mutex);
11620 cleanup:
11621 crtc->primary->fb = old_fb;
11622 update_state_fb(crtc->primary);
11623
11624 drm_gem_object_unreference_unlocked(&obj->base);
11625 drm_framebuffer_unreference(work->old_fb);
11626
11627 spin_lock_irq(&dev->event_lock);
11628 intel_crtc->unpin_work = NULL;
11629 spin_unlock_irq(&dev->event_lock);
11630
11631 drm_crtc_vblank_put(crtc);
11632 free_work:
11633 kfree(work);
11634
11635 if (ret == -EIO) {
11636 struct drm_atomic_state *state;
11637 struct drm_plane_state *plane_state;
11638
11639 out_hang:
11640 state = drm_atomic_state_alloc(dev);
11641 if (!state)
11642 return -ENOMEM;
11643 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11644
11645 retry:
11646 plane_state = drm_atomic_get_plane_state(state, primary);
11647 ret = PTR_ERR_OR_ZERO(plane_state);
11648 if (!ret) {
11649 drm_atomic_set_fb_for_plane(plane_state, fb);
11650
11651 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11652 if (!ret)
11653 ret = drm_atomic_commit(state);
11654 }
11655
11656 if (ret == -EDEADLK) {
11657 drm_modeset_backoff(state->acquire_ctx);
11658 drm_atomic_state_clear(state);
11659 goto retry;
11660 }
11661
11662 if (ret)
11663 drm_atomic_state_free(state);
11664
11665 if (ret == 0 && event) {
11666 spin_lock_irq(&dev->event_lock);
11667 drm_send_vblank_event(dev, pipe, event);
11668 spin_unlock_irq(&dev->event_lock);
11669 }
11670 }
11671 return ret;
11672 }
11673
11674 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11675 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11676 .load_lut = intel_crtc_load_lut,
11677 .atomic_begin = intel_begin_crtc_commit,
11678 .atomic_flush = intel_finish_crtc_commit,
11679 };
11680
11681 /**
11682 * intel_modeset_update_staged_output_state
11683 *
11684 * Updates the staged output configuration state, e.g. after we've read out the
11685 * current hw state.
11686 */
11687 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11688 {
11689 struct intel_crtc *crtc;
11690 struct intel_encoder *encoder;
11691 struct intel_connector *connector;
11692
11693 for_each_intel_connector(dev, connector) {
11694 connector->new_encoder =
11695 to_intel_encoder(connector->base.encoder);
11696 }
11697
11698 for_each_intel_encoder(dev, encoder) {
11699 encoder->new_crtc =
11700 to_intel_crtc(encoder->base.crtc);
11701 }
11702
11703 for_each_intel_crtc(dev, crtc) {
11704 crtc->new_enabled = crtc->base.state->enable;
11705 }
11706 }
11707
11708 /* Transitional helper to copy current connector/encoder state to
11709 * connector->state. This is needed so that code that is partially
11710 * converted to atomic does the right thing.
11711 */
11712 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11713 {
11714 struct intel_connector *connector;
11715
11716 for_each_intel_connector(dev, connector) {
11717 if (connector->base.encoder) {
11718 connector->base.state->best_encoder =
11719 connector->base.encoder;
11720 connector->base.state->crtc =
11721 connector->base.encoder->crtc;
11722 } else {
11723 connector->base.state->best_encoder = NULL;
11724 connector->base.state->crtc = NULL;
11725 }
11726 }
11727 }
11728
11729 static void
11730 connected_sink_compute_bpp(struct intel_connector *connector,
11731 struct intel_crtc_state *pipe_config)
11732 {
11733 int bpp = pipe_config->pipe_bpp;
11734
11735 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11736 connector->base.base.id,
11737 connector->base.name);
11738
11739 /* Don't use an invalid EDID bpc value */
11740 if (connector->base.display_info.bpc &&
11741 connector->base.display_info.bpc * 3 < bpp) {
11742 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11743 bpp, connector->base.display_info.bpc*3);
11744 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11745 }
11746
11747 /* Clamp bpp to 8 on screens without EDID 1.4 */
11748 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11749 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11750 bpp);
11751 pipe_config->pipe_bpp = 24;
11752 }
11753 }
11754
11755 static int
11756 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11757 struct intel_crtc_state *pipe_config)
11758 {
11759 struct drm_device *dev = crtc->base.dev;
11760 struct drm_atomic_state *state;
11761 struct drm_connector *connector;
11762 struct drm_connector_state *connector_state;
11763 int bpp, i;
11764
11765 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11766 bpp = 10*3;
11767 else if (INTEL_INFO(dev)->gen >= 5)
11768 bpp = 12*3;
11769 else
11770 bpp = 8*3;
11771
11772
11773 pipe_config->pipe_bpp = bpp;
11774
11775 state = pipe_config->base.state;
11776
11777 /* Clamp display bpp to EDID value */
11778 for_each_connector_in_state(state, connector, connector_state, i) {
11779 if (connector_state->crtc != &crtc->base)
11780 continue;
11781
11782 connected_sink_compute_bpp(to_intel_connector(connector),
11783 pipe_config);
11784 }
11785
11786 return bpp;
11787 }
11788
11789 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11790 {
11791 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11792 "type: 0x%x flags: 0x%x\n",
11793 mode->crtc_clock,
11794 mode->crtc_hdisplay, mode->crtc_hsync_start,
11795 mode->crtc_hsync_end, mode->crtc_htotal,
11796 mode->crtc_vdisplay, mode->crtc_vsync_start,
11797 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11798 }
11799
11800 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11801 struct intel_crtc_state *pipe_config,
11802 const char *context)
11803 {
11804 struct drm_device *dev = crtc->base.dev;
11805 struct drm_plane *plane;
11806 struct intel_plane *intel_plane;
11807 struct intel_plane_state *state;
11808 struct drm_framebuffer *fb;
11809
11810 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11811 context, pipe_config, pipe_name(crtc->pipe));
11812
11813 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11814 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11815 pipe_config->pipe_bpp, pipe_config->dither);
11816 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11817 pipe_config->has_pch_encoder,
11818 pipe_config->fdi_lanes,
11819 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11820 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11821 pipe_config->fdi_m_n.tu);
11822 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11823 pipe_config->has_dp_encoder,
11824 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11825 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11826 pipe_config->dp_m_n.tu);
11827
11828 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11829 pipe_config->has_dp_encoder,
11830 pipe_config->dp_m2_n2.gmch_m,
11831 pipe_config->dp_m2_n2.gmch_n,
11832 pipe_config->dp_m2_n2.link_m,
11833 pipe_config->dp_m2_n2.link_n,
11834 pipe_config->dp_m2_n2.tu);
11835
11836 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11837 pipe_config->has_audio,
11838 pipe_config->has_infoframe);
11839
11840 DRM_DEBUG_KMS("requested mode:\n");
11841 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11842 DRM_DEBUG_KMS("adjusted mode:\n");
11843 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11844 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11845 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11846 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11847 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11848 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11849 crtc->num_scalers,
11850 pipe_config->scaler_state.scaler_users,
11851 pipe_config->scaler_state.scaler_id);
11852 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11853 pipe_config->gmch_pfit.control,
11854 pipe_config->gmch_pfit.pgm_ratios,
11855 pipe_config->gmch_pfit.lvds_border_bits);
11856 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11857 pipe_config->pch_pfit.pos,
11858 pipe_config->pch_pfit.size,
11859 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11860 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11861 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11862
11863 if (IS_BROXTON(dev)) {
11864 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11865 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11866 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11867 pipe_config->ddi_pll_sel,
11868 pipe_config->dpll_hw_state.ebb0,
11869 pipe_config->dpll_hw_state.pll0,
11870 pipe_config->dpll_hw_state.pll1,
11871 pipe_config->dpll_hw_state.pll2,
11872 pipe_config->dpll_hw_state.pll3,
11873 pipe_config->dpll_hw_state.pll6,
11874 pipe_config->dpll_hw_state.pll8,
11875 pipe_config->dpll_hw_state.pcsdw12);
11876 } else if (IS_SKYLAKE(dev)) {
11877 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11878 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11879 pipe_config->ddi_pll_sel,
11880 pipe_config->dpll_hw_state.ctrl1,
11881 pipe_config->dpll_hw_state.cfgcr1,
11882 pipe_config->dpll_hw_state.cfgcr2);
11883 } else if (HAS_DDI(dev)) {
11884 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11885 pipe_config->ddi_pll_sel,
11886 pipe_config->dpll_hw_state.wrpll);
11887 } else {
11888 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11889 "fp0: 0x%x, fp1: 0x%x\n",
11890 pipe_config->dpll_hw_state.dpll,
11891 pipe_config->dpll_hw_state.dpll_md,
11892 pipe_config->dpll_hw_state.fp0,
11893 pipe_config->dpll_hw_state.fp1);
11894 }
11895
11896 DRM_DEBUG_KMS("planes on this crtc\n");
11897 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11898 intel_plane = to_intel_plane(plane);
11899 if (intel_plane->pipe != crtc->pipe)
11900 continue;
11901
11902 state = to_intel_plane_state(plane->state);
11903 fb = state->base.fb;
11904 if (!fb) {
11905 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11906 "disabled, scaler_id = %d\n",
11907 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11908 plane->base.id, intel_plane->pipe,
11909 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11910 drm_plane_index(plane), state->scaler_id);
11911 continue;
11912 }
11913
11914 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11915 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11916 plane->base.id, intel_plane->pipe,
11917 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11918 drm_plane_index(plane));
11919 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11920 fb->base.id, fb->width, fb->height, fb->pixel_format);
11921 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11922 state->scaler_id,
11923 state->src.x1 >> 16, state->src.y1 >> 16,
11924 drm_rect_width(&state->src) >> 16,
11925 drm_rect_height(&state->src) >> 16,
11926 state->dst.x1, state->dst.y1,
11927 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11928 }
11929 }
11930
11931 static bool encoders_cloneable(const struct intel_encoder *a,
11932 const struct intel_encoder *b)
11933 {
11934 /* masks could be asymmetric, so check both ways */
11935 return a == b || (a->cloneable & (1 << b->type) &&
11936 b->cloneable & (1 << a->type));
11937 }
11938
11939 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11940 struct intel_crtc *crtc,
11941 struct intel_encoder *encoder)
11942 {
11943 struct intel_encoder *source_encoder;
11944 struct drm_connector *connector;
11945 struct drm_connector_state *connector_state;
11946 int i;
11947
11948 for_each_connector_in_state(state, connector, connector_state, i) {
11949 if (connector_state->crtc != &crtc->base)
11950 continue;
11951
11952 source_encoder =
11953 to_intel_encoder(connector_state->best_encoder);
11954 if (!encoders_cloneable(encoder, source_encoder))
11955 return false;
11956 }
11957
11958 return true;
11959 }
11960
11961 static bool check_encoder_cloning(struct drm_atomic_state *state,
11962 struct intel_crtc *crtc)
11963 {
11964 struct intel_encoder *encoder;
11965 struct drm_connector *connector;
11966 struct drm_connector_state *connector_state;
11967 int i;
11968
11969 for_each_connector_in_state(state, connector, connector_state, i) {
11970 if (connector_state->crtc != &crtc->base)
11971 continue;
11972
11973 encoder = to_intel_encoder(connector_state->best_encoder);
11974 if (!check_single_encoder_cloning(state, crtc, encoder))
11975 return false;
11976 }
11977
11978 return true;
11979 }
11980
11981 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11982 {
11983 struct drm_device *dev = state->dev;
11984 struct intel_encoder *encoder;
11985 struct drm_connector *connector;
11986 struct drm_connector_state *connector_state;
11987 unsigned int used_ports = 0;
11988 int i;
11989
11990 /*
11991 * Walk the connector list instead of the encoder
11992 * list to detect the problem on ddi platforms
11993 * where there's just one encoder per digital port.
11994 */
11995 for_each_connector_in_state(state, connector, connector_state, i) {
11996 if (!connector_state->best_encoder)
11997 continue;
11998
11999 encoder = to_intel_encoder(connector_state->best_encoder);
12000
12001 WARN_ON(!connector_state->crtc);
12002
12003 switch (encoder->type) {
12004 unsigned int port_mask;
12005 case INTEL_OUTPUT_UNKNOWN:
12006 if (WARN_ON(!HAS_DDI(dev)))
12007 break;
12008 case INTEL_OUTPUT_DISPLAYPORT:
12009 case INTEL_OUTPUT_HDMI:
12010 case INTEL_OUTPUT_EDP:
12011 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12012
12013 /* the same port mustn't appear more than once */
12014 if (used_ports & port_mask)
12015 return false;
12016
12017 used_ports |= port_mask;
12018 default:
12019 break;
12020 }
12021 }
12022
12023 return true;
12024 }
12025
12026 static void
12027 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12028 {
12029 struct drm_crtc_state tmp_state;
12030 struct intel_crtc_scaler_state scaler_state;
12031 struct intel_dpll_hw_state dpll_hw_state;
12032 enum intel_dpll_id shared_dpll;
12033 uint32_t ddi_pll_sel;
12034
12035 /* FIXME: before the switch to atomic started, a new pipe_config was
12036 * kzalloc'd. Code that depends on any field being zero should be
12037 * fixed, so that the crtc_state can be safely duplicated. For now,
12038 * only fields that are know to not cause problems are preserved. */
12039
12040 tmp_state = crtc_state->base;
12041 scaler_state = crtc_state->scaler_state;
12042 shared_dpll = crtc_state->shared_dpll;
12043 dpll_hw_state = crtc_state->dpll_hw_state;
12044 ddi_pll_sel = crtc_state->ddi_pll_sel;
12045
12046 memset(crtc_state, 0, sizeof *crtc_state);
12047
12048 crtc_state->base = tmp_state;
12049 crtc_state->scaler_state = scaler_state;
12050 crtc_state->shared_dpll = shared_dpll;
12051 crtc_state->dpll_hw_state = dpll_hw_state;
12052 crtc_state->ddi_pll_sel = ddi_pll_sel;
12053 }
12054
12055 static int
12056 intel_modeset_pipe_config(struct drm_crtc *crtc,
12057 struct drm_atomic_state *state)
12058 {
12059 struct drm_crtc_state *crtc_state;
12060 struct intel_crtc_state *pipe_config;
12061 struct intel_encoder *encoder;
12062 struct drm_connector *connector;
12063 struct drm_connector_state *connector_state;
12064 int base_bpp, ret = -EINVAL;
12065 int i;
12066 bool retry = true;
12067
12068 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
12069 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12070 return -EINVAL;
12071 }
12072
12073 if (!check_digital_port_conflicts(state)) {
12074 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12075 return -EINVAL;
12076 }
12077
12078 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12079 if (WARN_ON(!crtc_state))
12080 return -EINVAL;
12081
12082 pipe_config = to_intel_crtc_state(crtc_state);
12083
12084 /*
12085 * XXX: Add all connectors to make the crtc state match the encoders.
12086 */
12087 if (!needs_modeset(&pipe_config->base)) {
12088 ret = drm_atomic_add_affected_connectors(state, crtc);
12089 if (ret)
12090 return ret;
12091 }
12092
12093 clear_intel_crtc_state(pipe_config);
12094
12095 pipe_config->cpu_transcoder =
12096 (enum transcoder) to_intel_crtc(crtc)->pipe;
12097
12098 /*
12099 * Sanitize sync polarity flags based on requested ones. If neither
12100 * positive or negative polarity is requested, treat this as meaning
12101 * negative polarity.
12102 */
12103 if (!(pipe_config->base.adjusted_mode.flags &
12104 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12105 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12106
12107 if (!(pipe_config->base.adjusted_mode.flags &
12108 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12109 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12110
12111 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12112 * plane pixel format and any sink constraints into account. Returns the
12113 * source plane bpp so that dithering can be selected on mismatches
12114 * after encoders and crtc also have had their say. */
12115 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12116 pipe_config);
12117 if (base_bpp < 0)
12118 goto fail;
12119
12120 /*
12121 * Determine the real pipe dimensions. Note that stereo modes can
12122 * increase the actual pipe size due to the frame doubling and
12123 * insertion of additional space for blanks between the frame. This
12124 * is stored in the crtc timings. We use the requested mode to do this
12125 * computation to clearly distinguish it from the adjusted mode, which
12126 * can be changed by the connectors in the below retry loop.
12127 */
12128 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12129 &pipe_config->pipe_src_w,
12130 &pipe_config->pipe_src_h);
12131
12132 encoder_retry:
12133 /* Ensure the port clock defaults are reset when retrying. */
12134 pipe_config->port_clock = 0;
12135 pipe_config->pixel_multiplier = 1;
12136
12137 /* Fill in default crtc timings, allow encoders to overwrite them. */
12138 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12139 CRTC_STEREO_DOUBLE);
12140
12141 /* Pass our mode to the connectors and the CRTC to give them a chance to
12142 * adjust it according to limitations or connector properties, and also
12143 * a chance to reject the mode entirely.
12144 */
12145 for_each_connector_in_state(state, connector, connector_state, i) {
12146 if (connector_state->crtc != crtc)
12147 continue;
12148
12149 encoder = to_intel_encoder(connector_state->best_encoder);
12150
12151 if (!(encoder->compute_config(encoder, pipe_config))) {
12152 DRM_DEBUG_KMS("Encoder config failure\n");
12153 goto fail;
12154 }
12155 }
12156
12157 /* Set default port clock if not overwritten by the encoder. Needs to be
12158 * done afterwards in case the encoder adjusts the mode. */
12159 if (!pipe_config->port_clock)
12160 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12161 * pipe_config->pixel_multiplier;
12162
12163 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12164 if (ret < 0) {
12165 DRM_DEBUG_KMS("CRTC fixup failed\n");
12166 goto fail;
12167 }
12168
12169 if (ret == RETRY) {
12170 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12171 ret = -EINVAL;
12172 goto fail;
12173 }
12174
12175 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12176 retry = false;
12177 goto encoder_retry;
12178 }
12179
12180 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12181 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12182 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12183
12184 /* Check if we need to force a modeset */
12185 if (pipe_config->has_audio !=
12186 to_intel_crtc_state(crtc->state)->has_audio) {
12187 pipe_config->base.mode_changed = true;
12188 ret = drm_atomic_add_affected_planes(state, crtc);
12189 }
12190
12191 /*
12192 * Note we have an issue here with infoframes: current code
12193 * only updates them on the full mode set path per hw
12194 * requirements. So here we should be checking for any
12195 * required changes and forcing a mode set.
12196 */
12197 fail:
12198 return ret;
12199 }
12200
12201 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12202 {
12203 struct drm_encoder *encoder;
12204 struct drm_device *dev = crtc->dev;
12205
12206 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12207 if (encoder->crtc == crtc)
12208 return true;
12209
12210 return false;
12211 }
12212
12213 static void
12214 intel_modeset_update_state(struct drm_atomic_state *state)
12215 {
12216 struct drm_device *dev = state->dev;
12217 struct intel_encoder *intel_encoder;
12218 struct drm_crtc *crtc;
12219 struct drm_crtc_state *crtc_state;
12220 struct drm_connector *connector;
12221
12222 intel_shared_dpll_commit(state);
12223
12224 for_each_intel_encoder(dev, intel_encoder) {
12225 if (!intel_encoder->base.crtc)
12226 continue;
12227
12228 crtc = intel_encoder->base.crtc;
12229 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12230 if (!crtc_state || !needs_modeset(crtc->state))
12231 continue;
12232
12233 intel_encoder->connectors_active = false;
12234 }
12235
12236 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12237 intel_modeset_update_staged_output_state(state->dev);
12238
12239 /* Double check state. */
12240 for_each_crtc(dev, crtc) {
12241 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12242
12243 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12244
12245 /* Update hwmode for vblank functions */
12246 if (crtc->state->active)
12247 crtc->hwmode = crtc->state->adjusted_mode;
12248 else
12249 crtc->hwmode.crtc_clock = 0;
12250 }
12251
12252 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12253 if (!connector->encoder || !connector->encoder->crtc)
12254 continue;
12255
12256 crtc = connector->encoder->crtc;
12257 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12258 if (!crtc_state || !needs_modeset(crtc->state))
12259 continue;
12260
12261 if (crtc->state->active) {
12262 struct drm_property *dpms_property =
12263 dev->mode_config.dpms_property;
12264
12265 connector->dpms = DRM_MODE_DPMS_ON;
12266 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12267
12268 intel_encoder = to_intel_encoder(connector->encoder);
12269 intel_encoder->connectors_active = true;
12270 } else
12271 connector->dpms = DRM_MODE_DPMS_OFF;
12272 }
12273 }
12274
12275 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12276 {
12277 int diff;
12278
12279 if (clock1 == clock2)
12280 return true;
12281
12282 if (!clock1 || !clock2)
12283 return false;
12284
12285 diff = abs(clock1 - clock2);
12286
12287 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12288 return true;
12289
12290 return false;
12291 }
12292
12293 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12294 list_for_each_entry((intel_crtc), \
12295 &(dev)->mode_config.crtc_list, \
12296 base.head) \
12297 if (mask & (1 <<(intel_crtc)->pipe))
12298
12299 static bool
12300 intel_pipe_config_compare(struct drm_device *dev,
12301 struct intel_crtc_state *current_config,
12302 struct intel_crtc_state *pipe_config)
12303 {
12304 #define PIPE_CONF_CHECK_X(name) \
12305 if (current_config->name != pipe_config->name) { \
12306 DRM_ERROR("mismatch in " #name " " \
12307 "(expected 0x%08x, found 0x%08x)\n", \
12308 current_config->name, \
12309 pipe_config->name); \
12310 return false; \
12311 }
12312
12313 #define PIPE_CONF_CHECK_I(name) \
12314 if (current_config->name != pipe_config->name) { \
12315 DRM_ERROR("mismatch in " #name " " \
12316 "(expected %i, found %i)\n", \
12317 current_config->name, \
12318 pipe_config->name); \
12319 return false; \
12320 }
12321
12322 /* This is required for BDW+ where there is only one set of registers for
12323 * switching between high and low RR.
12324 * This macro can be used whenever a comparison has to be made between one
12325 * hw state and multiple sw state variables.
12326 */
12327 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12328 if ((current_config->name != pipe_config->name) && \
12329 (current_config->alt_name != pipe_config->name)) { \
12330 DRM_ERROR("mismatch in " #name " " \
12331 "(expected %i or %i, found %i)\n", \
12332 current_config->name, \
12333 current_config->alt_name, \
12334 pipe_config->name); \
12335 return false; \
12336 }
12337
12338 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12339 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12340 DRM_ERROR("mismatch in " #name "(" #mask ") " \
12341 "(expected %i, found %i)\n", \
12342 current_config->name & (mask), \
12343 pipe_config->name & (mask)); \
12344 return false; \
12345 }
12346
12347 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12348 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12349 DRM_ERROR("mismatch in " #name " " \
12350 "(expected %i, found %i)\n", \
12351 current_config->name, \
12352 pipe_config->name); \
12353 return false; \
12354 }
12355
12356 #define PIPE_CONF_QUIRK(quirk) \
12357 ((current_config->quirks | pipe_config->quirks) & (quirk))
12358
12359 PIPE_CONF_CHECK_I(cpu_transcoder);
12360
12361 PIPE_CONF_CHECK_I(has_pch_encoder);
12362 PIPE_CONF_CHECK_I(fdi_lanes);
12363 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12364 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12365 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12366 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12367 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12368
12369 PIPE_CONF_CHECK_I(has_dp_encoder);
12370
12371 if (INTEL_INFO(dev)->gen < 8) {
12372 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12373 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12374 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12375 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12376 PIPE_CONF_CHECK_I(dp_m_n.tu);
12377
12378 if (current_config->has_drrs) {
12379 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12380 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12381 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12382 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12383 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12384 }
12385 } else {
12386 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12387 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12388 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12389 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12390 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12391 }
12392
12393 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12394 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12395 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12396 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12397 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12398 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12399
12400 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12401 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12402 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12403 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12404 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12405 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12406
12407 PIPE_CONF_CHECK_I(pixel_multiplier);
12408 PIPE_CONF_CHECK_I(has_hdmi_sink);
12409 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12410 IS_VALLEYVIEW(dev))
12411 PIPE_CONF_CHECK_I(limited_color_range);
12412 PIPE_CONF_CHECK_I(has_infoframe);
12413
12414 PIPE_CONF_CHECK_I(has_audio);
12415
12416 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12417 DRM_MODE_FLAG_INTERLACE);
12418
12419 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12420 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12421 DRM_MODE_FLAG_PHSYNC);
12422 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12423 DRM_MODE_FLAG_NHSYNC);
12424 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12425 DRM_MODE_FLAG_PVSYNC);
12426 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12427 DRM_MODE_FLAG_NVSYNC);
12428 }
12429
12430 PIPE_CONF_CHECK_I(pipe_src_w);
12431 PIPE_CONF_CHECK_I(pipe_src_h);
12432
12433 /*
12434 * FIXME: BIOS likes to set up a cloned config with lvds+external
12435 * screen. Since we don't yet re-compute the pipe config when moving
12436 * just the lvds port away to another pipe the sw tracking won't match.
12437 *
12438 * Proper atomic modesets with recomputed global state will fix this.
12439 * Until then just don't check gmch state for inherited modes.
12440 */
12441 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12442 PIPE_CONF_CHECK_I(gmch_pfit.control);
12443 /* pfit ratios are autocomputed by the hw on gen4+ */
12444 if (INTEL_INFO(dev)->gen < 4)
12445 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12446 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12447 }
12448
12449 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12450 if (current_config->pch_pfit.enabled) {
12451 PIPE_CONF_CHECK_I(pch_pfit.pos);
12452 PIPE_CONF_CHECK_I(pch_pfit.size);
12453 }
12454
12455 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12456
12457 /* BDW+ don't expose a synchronous way to read the state */
12458 if (IS_HASWELL(dev))
12459 PIPE_CONF_CHECK_I(ips_enabled);
12460
12461 PIPE_CONF_CHECK_I(double_wide);
12462
12463 PIPE_CONF_CHECK_X(ddi_pll_sel);
12464
12465 PIPE_CONF_CHECK_I(shared_dpll);
12466 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12467 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12468 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12469 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12470 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12471 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12472 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12473 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12474
12475 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12476 PIPE_CONF_CHECK_I(pipe_bpp);
12477
12478 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12479 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12480
12481 #undef PIPE_CONF_CHECK_X
12482 #undef PIPE_CONF_CHECK_I
12483 #undef PIPE_CONF_CHECK_I_ALT
12484 #undef PIPE_CONF_CHECK_FLAGS
12485 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12486 #undef PIPE_CONF_QUIRK
12487
12488 return true;
12489 }
12490
12491 static void check_wm_state(struct drm_device *dev)
12492 {
12493 struct drm_i915_private *dev_priv = dev->dev_private;
12494 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12495 struct intel_crtc *intel_crtc;
12496 int plane;
12497
12498 if (INTEL_INFO(dev)->gen < 9)
12499 return;
12500
12501 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12502 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12503
12504 for_each_intel_crtc(dev, intel_crtc) {
12505 struct skl_ddb_entry *hw_entry, *sw_entry;
12506 const enum pipe pipe = intel_crtc->pipe;
12507
12508 if (!intel_crtc->active)
12509 continue;
12510
12511 /* planes */
12512 for_each_plane(dev_priv, pipe, plane) {
12513 hw_entry = &hw_ddb.plane[pipe][plane];
12514 sw_entry = &sw_ddb->plane[pipe][plane];
12515
12516 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12517 continue;
12518
12519 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12520 "(expected (%u,%u), found (%u,%u))\n",
12521 pipe_name(pipe), plane + 1,
12522 sw_entry->start, sw_entry->end,
12523 hw_entry->start, hw_entry->end);
12524 }
12525
12526 /* cursor */
12527 hw_entry = &hw_ddb.cursor[pipe];
12528 sw_entry = &sw_ddb->cursor[pipe];
12529
12530 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12531 continue;
12532
12533 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12534 "(expected (%u,%u), found (%u,%u))\n",
12535 pipe_name(pipe),
12536 sw_entry->start, sw_entry->end,
12537 hw_entry->start, hw_entry->end);
12538 }
12539 }
12540
12541 static void
12542 check_connector_state(struct drm_device *dev)
12543 {
12544 struct intel_connector *connector;
12545
12546 for_each_intel_connector(dev, connector) {
12547 /* This also checks the encoder/connector hw state with the
12548 * ->get_hw_state callbacks. */
12549 intel_connector_check_state(connector);
12550
12551 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12552 "connector's staged encoder doesn't match current encoder\n");
12553 }
12554 }
12555
12556 static void
12557 check_encoder_state(struct drm_device *dev)
12558 {
12559 struct intel_encoder *encoder;
12560 struct intel_connector *connector;
12561
12562 for_each_intel_encoder(dev, encoder) {
12563 bool enabled = false;
12564 bool active = false;
12565 enum pipe pipe, tracked_pipe;
12566
12567 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12568 encoder->base.base.id,
12569 encoder->base.name);
12570
12571 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12572 "encoder's stage crtc doesn't match current crtc\n");
12573 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12574 "encoder's active_connectors set, but no crtc\n");
12575
12576 for_each_intel_connector(dev, connector) {
12577 if (connector->base.encoder != &encoder->base)
12578 continue;
12579 enabled = true;
12580 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12581 active = true;
12582 }
12583 /*
12584 * for MST connectors if we unplug the connector is gone
12585 * away but the encoder is still connected to a crtc
12586 * until a modeset happens in response to the hotplug.
12587 */
12588 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12589 continue;
12590
12591 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12592 "encoder's enabled state mismatch "
12593 "(expected %i, found %i)\n",
12594 !!encoder->base.crtc, enabled);
12595 I915_STATE_WARN(active && !encoder->base.crtc,
12596 "active encoder with no crtc\n");
12597
12598 I915_STATE_WARN(encoder->connectors_active != active,
12599 "encoder's computed active state doesn't match tracked active state "
12600 "(expected %i, found %i)\n", active, encoder->connectors_active);
12601
12602 active = encoder->get_hw_state(encoder, &pipe);
12603 I915_STATE_WARN(active != encoder->connectors_active,
12604 "encoder's hw state doesn't match sw tracking "
12605 "(expected %i, found %i)\n",
12606 encoder->connectors_active, active);
12607
12608 if (!encoder->base.crtc)
12609 continue;
12610
12611 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12612 I915_STATE_WARN(active && pipe != tracked_pipe,
12613 "active encoder's pipe doesn't match"
12614 "(expected %i, found %i)\n",
12615 tracked_pipe, pipe);
12616
12617 }
12618 }
12619
12620 static void
12621 check_crtc_state(struct drm_device *dev)
12622 {
12623 struct drm_i915_private *dev_priv = dev->dev_private;
12624 struct intel_crtc *crtc;
12625 struct intel_encoder *encoder;
12626 struct intel_crtc_state pipe_config;
12627
12628 for_each_intel_crtc(dev, crtc) {
12629 bool enabled = false;
12630 bool active = false;
12631
12632 memset(&pipe_config, 0, sizeof(pipe_config));
12633
12634 DRM_DEBUG_KMS("[CRTC:%d]\n",
12635 crtc->base.base.id);
12636
12637 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12638 "active crtc, but not enabled in sw tracking\n");
12639
12640 for_each_intel_encoder(dev, encoder) {
12641 if (encoder->base.crtc != &crtc->base)
12642 continue;
12643 enabled = true;
12644 if (encoder->connectors_active)
12645 active = true;
12646 }
12647
12648 I915_STATE_WARN(active != crtc->active,
12649 "crtc's computed active state doesn't match tracked active state "
12650 "(expected %i, found %i)\n", active, crtc->active);
12651 I915_STATE_WARN(enabled != crtc->base.state->enable,
12652 "crtc's computed enabled state doesn't match tracked enabled state "
12653 "(expected %i, found %i)\n", enabled,
12654 crtc->base.state->enable);
12655
12656 active = dev_priv->display.get_pipe_config(crtc,
12657 &pipe_config);
12658
12659 /* hw state is inconsistent with the pipe quirk */
12660 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12661 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12662 active = crtc->active;
12663
12664 for_each_intel_encoder(dev, encoder) {
12665 enum pipe pipe;
12666 if (encoder->base.crtc != &crtc->base)
12667 continue;
12668 if (encoder->get_hw_state(encoder, &pipe))
12669 encoder->get_config(encoder, &pipe_config);
12670 }
12671
12672 I915_STATE_WARN(crtc->active != active,
12673 "crtc active state doesn't match with hw state "
12674 "(expected %i, found %i)\n", crtc->active, active);
12675
12676 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12677 "transitional active state does not match atomic hw state "
12678 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12679
12680 if (active &&
12681 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12682 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12683 intel_dump_pipe_config(crtc, &pipe_config,
12684 "[hw state]");
12685 intel_dump_pipe_config(crtc, crtc->config,
12686 "[sw state]");
12687 }
12688 }
12689 }
12690
12691 static void
12692 check_shared_dpll_state(struct drm_device *dev)
12693 {
12694 struct drm_i915_private *dev_priv = dev->dev_private;
12695 struct intel_crtc *crtc;
12696 struct intel_dpll_hw_state dpll_hw_state;
12697 int i;
12698
12699 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12700 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12701 int enabled_crtcs = 0, active_crtcs = 0;
12702 bool active;
12703
12704 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12705
12706 DRM_DEBUG_KMS("%s\n", pll->name);
12707
12708 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12709
12710 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12711 "more active pll users than references: %i vs %i\n",
12712 pll->active, hweight32(pll->config.crtc_mask));
12713 I915_STATE_WARN(pll->active && !pll->on,
12714 "pll in active use but not on in sw tracking\n");
12715 I915_STATE_WARN(pll->on && !pll->active,
12716 "pll in on but not on in use in sw tracking\n");
12717 I915_STATE_WARN(pll->on != active,
12718 "pll on state mismatch (expected %i, found %i)\n",
12719 pll->on, active);
12720
12721 for_each_intel_crtc(dev, crtc) {
12722 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12723 enabled_crtcs++;
12724 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12725 active_crtcs++;
12726 }
12727 I915_STATE_WARN(pll->active != active_crtcs,
12728 "pll active crtcs mismatch (expected %i, found %i)\n",
12729 pll->active, active_crtcs);
12730 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12731 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12732 hweight32(pll->config.crtc_mask), enabled_crtcs);
12733
12734 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12735 sizeof(dpll_hw_state)),
12736 "pll hw state mismatch\n");
12737 }
12738 }
12739
12740 void
12741 intel_modeset_check_state(struct drm_device *dev)
12742 {
12743 check_wm_state(dev);
12744 check_connector_state(dev);
12745 check_encoder_state(dev);
12746 check_crtc_state(dev);
12747 check_shared_dpll_state(dev);
12748 }
12749
12750 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12751 int dotclock)
12752 {
12753 /*
12754 * FDI already provided one idea for the dotclock.
12755 * Yell if the encoder disagrees.
12756 */
12757 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12758 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12759 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12760 }
12761
12762 static void update_scanline_offset(struct intel_crtc *crtc)
12763 {
12764 struct drm_device *dev = crtc->base.dev;
12765
12766 /*
12767 * The scanline counter increments at the leading edge of hsync.
12768 *
12769 * On most platforms it starts counting from vtotal-1 on the
12770 * first active line. That means the scanline counter value is
12771 * always one less than what we would expect. Ie. just after
12772 * start of vblank, which also occurs at start of hsync (on the
12773 * last active line), the scanline counter will read vblank_start-1.
12774 *
12775 * On gen2 the scanline counter starts counting from 1 instead
12776 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12777 * to keep the value positive), instead of adding one.
12778 *
12779 * On HSW+ the behaviour of the scanline counter depends on the output
12780 * type. For DP ports it behaves like most other platforms, but on HDMI
12781 * there's an extra 1 line difference. So we need to add two instead of
12782 * one to the value.
12783 */
12784 if (IS_GEN2(dev)) {
12785 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12786 int vtotal;
12787
12788 vtotal = mode->crtc_vtotal;
12789 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12790 vtotal /= 2;
12791
12792 crtc->scanline_offset = vtotal - 1;
12793 } else if (HAS_DDI(dev) &&
12794 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12795 crtc->scanline_offset = 2;
12796 } else
12797 crtc->scanline_offset = 1;
12798 }
12799
12800 static int intel_modeset_setup_plls(struct drm_atomic_state *state)
12801 {
12802 struct drm_device *dev = state->dev;
12803 struct drm_i915_private *dev_priv = to_i915(dev);
12804 unsigned clear_pipes = 0;
12805 struct intel_crtc *intel_crtc;
12806 struct intel_crtc_state *intel_crtc_state;
12807 struct drm_crtc *crtc;
12808 struct drm_crtc_state *crtc_state;
12809 int ret = 0;
12810 int i;
12811
12812 if (!dev_priv->display.crtc_compute_clock)
12813 return 0;
12814
12815 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12816 intel_crtc = to_intel_crtc(crtc);
12817 intel_crtc_state = to_intel_crtc_state(crtc_state);
12818
12819 if (needs_modeset(crtc_state)) {
12820 clear_pipes |= 1 << intel_crtc->pipe;
12821 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12822 }
12823 }
12824
12825 if (clear_pipes) {
12826 struct intel_shared_dpll_config *shared_dpll =
12827 intel_atomic_get_shared_dpll_state(state);
12828
12829 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12830 shared_dpll[i].crtc_mask &= ~clear_pipes;
12831 }
12832
12833 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12834 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12835 continue;
12836
12837 intel_crtc = to_intel_crtc(crtc);
12838 intel_crtc_state = to_intel_crtc_state(crtc_state);
12839
12840 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12841 intel_crtc_state);
12842 if (ret)
12843 return ret;
12844 }
12845
12846 return ret;
12847 }
12848
12849 /*
12850 * This implements the workaround described in the "notes" section of the mode
12851 * set sequence documentation. When going from no pipes or single pipe to
12852 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12853 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12854 */
12855 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12856 {
12857 struct drm_crtc_state *crtc_state;
12858 struct intel_crtc *intel_crtc;
12859 struct drm_crtc *crtc;
12860 struct intel_crtc_state *first_crtc_state = NULL;
12861 struct intel_crtc_state *other_crtc_state = NULL;
12862 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12863 int i;
12864
12865 /* look at all crtc's that are going to be enabled in during modeset */
12866 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12867 intel_crtc = to_intel_crtc(crtc);
12868
12869 if (!crtc_state->active || !needs_modeset(crtc_state))
12870 continue;
12871
12872 if (first_crtc_state) {
12873 other_crtc_state = to_intel_crtc_state(crtc_state);
12874 break;
12875 } else {
12876 first_crtc_state = to_intel_crtc_state(crtc_state);
12877 first_pipe = intel_crtc->pipe;
12878 }
12879 }
12880
12881 /* No workaround needed? */
12882 if (!first_crtc_state)
12883 return 0;
12884
12885 /* w/a possibly needed, check how many crtc's are already enabled. */
12886 for_each_intel_crtc(state->dev, intel_crtc) {
12887 struct intel_crtc_state *pipe_config;
12888
12889 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12890 if (IS_ERR(pipe_config))
12891 return PTR_ERR(pipe_config);
12892
12893 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12894
12895 if (!pipe_config->base.active ||
12896 needs_modeset(&pipe_config->base))
12897 continue;
12898
12899 /* 2 or more enabled crtcs means no need for w/a */
12900 if (enabled_pipe != INVALID_PIPE)
12901 return 0;
12902
12903 enabled_pipe = intel_crtc->pipe;
12904 }
12905
12906 if (enabled_pipe != INVALID_PIPE)
12907 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12908 else if (other_crtc_state)
12909 other_crtc_state->hsw_workaround_pipe = first_pipe;
12910
12911 return 0;
12912 }
12913
12914 /* Code that should eventually be part of atomic_check() */
12915 static int intel_modeset_checks(struct drm_atomic_state *state)
12916 {
12917 struct drm_device *dev = state->dev;
12918 int ret;
12919
12920 /*
12921 * See if the config requires any additional preparation, e.g.
12922 * to adjust global state with pipes off. We need to do this
12923 * here so we can get the modeset_pipe updated config for the new
12924 * mode set on this crtc. For other crtcs we need to use the
12925 * adjusted_mode bits in the crtc directly.
12926 */
12927 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
12928 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
12929 ret = valleyview_modeset_global_pipes(state);
12930 else
12931 ret = broadwell_modeset_global_pipes(state);
12932
12933 if (ret)
12934 return ret;
12935 }
12936
12937 ret = intel_modeset_setup_plls(state);
12938 if (ret)
12939 return ret;
12940
12941 if (IS_HASWELL(dev))
12942 ret = haswell_mode_set_planes_workaround(state);
12943
12944 return ret;
12945 }
12946
12947 static int
12948 intel_modeset_compute_config(struct drm_atomic_state *state)
12949 {
12950 struct drm_crtc *crtc;
12951 struct drm_crtc_state *crtc_state;
12952 int ret, i;
12953
12954 ret = drm_atomic_helper_check_modeset(state->dev, state);
12955 if (ret)
12956 return ret;
12957
12958 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12959 if (!crtc_state->enable &&
12960 WARN_ON(crtc_state->active))
12961 crtc_state->active = false;
12962
12963 if (!crtc_state->enable)
12964 continue;
12965
12966 ret = intel_modeset_pipe_config(crtc, state);
12967 if (ret)
12968 return ret;
12969
12970 intel_dump_pipe_config(to_intel_crtc(crtc),
12971 to_intel_crtc_state(crtc_state),
12972 "[modeset]");
12973 }
12974
12975 ret = intel_modeset_checks(state);
12976 if (ret)
12977 return ret;
12978
12979 return drm_atomic_helper_check_planes(state->dev, state);
12980 }
12981
12982 static int __intel_set_mode(struct drm_atomic_state *state)
12983 {
12984 struct drm_device *dev = state->dev;
12985 struct drm_i915_private *dev_priv = dev->dev_private;
12986 struct drm_crtc *crtc;
12987 struct drm_crtc_state *crtc_state;
12988 int ret = 0;
12989 int i;
12990
12991 ret = drm_atomic_helper_prepare_planes(dev, state);
12992 if (ret)
12993 return ret;
12994
12995 drm_atomic_helper_swap_state(dev, state);
12996
12997 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12998 if (!needs_modeset(crtc->state) || !crtc_state->active)
12999 continue;
13000
13001 intel_crtc_disable_planes(crtc);
13002 dev_priv->display.crtc_disable(crtc);
13003 }
13004
13005 /* Only after disabling all output pipelines that will be changed can we
13006 * update the the output configuration. */
13007 intel_modeset_update_state(state);
13008
13009 /* The state has been swaped above, so state actually contains the
13010 * old state now. */
13011
13012 modeset_update_crtc_power_domains(state);
13013
13014 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13015 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13016 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13017
13018 if (!needs_modeset(crtc->state) || !crtc->state->active)
13019 continue;
13020
13021 update_scanline_offset(to_intel_crtc(crtc));
13022
13023 dev_priv->display.crtc_enable(crtc);
13024 intel_crtc_enable_planes(crtc);
13025 }
13026
13027 /* FIXME: add subpixel order */
13028
13029 drm_atomic_helper_cleanup_planes(dev, state);
13030
13031 drm_atomic_state_free(state);
13032
13033 return 0;
13034 }
13035
13036 static int intel_set_mode_checked(struct drm_atomic_state *state)
13037 {
13038 struct drm_device *dev = state->dev;
13039 int ret;
13040
13041 ret = __intel_set_mode(state);
13042 if (ret == 0)
13043 intel_modeset_check_state(dev);
13044
13045 return ret;
13046 }
13047
13048 static int intel_set_mode(struct drm_atomic_state *state)
13049 {
13050 int ret;
13051
13052 ret = intel_modeset_compute_config(state);
13053 if (ret)
13054 return ret;
13055
13056 return intel_set_mode_checked(state);
13057 }
13058
13059 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13060 {
13061 struct drm_device *dev = crtc->dev;
13062 struct drm_atomic_state *state;
13063 struct intel_crtc *intel_crtc;
13064 struct intel_encoder *encoder;
13065 struct intel_connector *connector;
13066 struct drm_connector_state *connector_state;
13067 struct intel_crtc_state *crtc_state;
13068 int ret;
13069
13070 state = drm_atomic_state_alloc(dev);
13071 if (!state) {
13072 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13073 crtc->base.id);
13074 return;
13075 }
13076
13077 state->acquire_ctx = dev->mode_config.acquire_ctx;
13078
13079 /* The force restore path in the HW readout code relies on the staged
13080 * config still keeping the user requested config while the actual
13081 * state has been overwritten by the configuration read from HW. We
13082 * need to copy the staged config to the atomic state, otherwise the
13083 * mode set will just reapply the state the HW is already in. */
13084 for_each_intel_encoder(dev, encoder) {
13085 if (&encoder->new_crtc->base != crtc)
13086 continue;
13087
13088 for_each_intel_connector(dev, connector) {
13089 if (connector->new_encoder != encoder)
13090 continue;
13091
13092 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13093 if (IS_ERR(connector_state)) {
13094 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13095 connector->base.base.id,
13096 connector->base.name,
13097 PTR_ERR(connector_state));
13098 continue;
13099 }
13100
13101 connector_state->crtc = crtc;
13102 connector_state->best_encoder = &encoder->base;
13103 }
13104 }
13105
13106 for_each_intel_crtc(dev, intel_crtc) {
13107 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13108 continue;
13109
13110 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13111 if (IS_ERR(crtc_state)) {
13112 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13113 intel_crtc->base.base.id,
13114 PTR_ERR(crtc_state));
13115 continue;
13116 }
13117
13118 crtc_state->base.active = crtc_state->base.enable =
13119 intel_crtc->new_enabled;
13120
13121 if (&intel_crtc->base == crtc)
13122 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13123 }
13124
13125 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13126 crtc->primary->fb, crtc->x, crtc->y);
13127
13128 ret = intel_set_mode(state);
13129 if (ret)
13130 drm_atomic_state_free(state);
13131 }
13132
13133 #undef for_each_intel_crtc_masked
13134
13135 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13136 struct drm_mode_set *set)
13137 {
13138 int ro;
13139
13140 for (ro = 0; ro < set->num_connectors; ro++)
13141 if (set->connectors[ro] == &connector->base)
13142 return true;
13143
13144 return false;
13145 }
13146
13147 static int
13148 intel_modeset_stage_output_state(struct drm_device *dev,
13149 struct drm_mode_set *set,
13150 struct drm_atomic_state *state)
13151 {
13152 struct intel_connector *connector;
13153 struct drm_connector *drm_connector;
13154 struct drm_connector_state *connector_state;
13155 struct drm_crtc *crtc;
13156 struct drm_crtc_state *crtc_state;
13157 int i, ret;
13158
13159 /* The upper layers ensure that we either disable a crtc or have a list
13160 * of connectors. For paranoia, double-check this. */
13161 WARN_ON(!set->fb && (set->num_connectors != 0));
13162 WARN_ON(set->fb && (set->num_connectors == 0));
13163
13164 for_each_intel_connector(dev, connector) {
13165 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13166
13167 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13168 continue;
13169
13170 connector_state =
13171 drm_atomic_get_connector_state(state, &connector->base);
13172 if (IS_ERR(connector_state))
13173 return PTR_ERR(connector_state);
13174
13175 if (in_mode_set) {
13176 int pipe = to_intel_crtc(set->crtc)->pipe;
13177 connector_state->best_encoder =
13178 &intel_find_encoder(connector, pipe)->base;
13179 }
13180
13181 if (connector->base.state->crtc != set->crtc)
13182 continue;
13183
13184 /* If we disable the crtc, disable all its connectors. Also, if
13185 * the connector is on the changing crtc but not on the new
13186 * connector list, disable it. */
13187 if (!set->fb || !in_mode_set) {
13188 connector_state->best_encoder = NULL;
13189
13190 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13191 connector->base.base.id,
13192 connector->base.name);
13193 }
13194 }
13195 /* connector->new_encoder is now updated for all connectors. */
13196
13197 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13198 connector = to_intel_connector(drm_connector);
13199
13200 if (!connector_state->best_encoder) {
13201 ret = drm_atomic_set_crtc_for_connector(connector_state,
13202 NULL);
13203 if (ret)
13204 return ret;
13205
13206 continue;
13207 }
13208
13209 if (intel_connector_in_mode_set(connector, set)) {
13210 struct drm_crtc *crtc = connector->base.state->crtc;
13211
13212 /* If this connector was in a previous crtc, add it
13213 * to the state. We might need to disable it. */
13214 if (crtc) {
13215 crtc_state =
13216 drm_atomic_get_crtc_state(state, crtc);
13217 if (IS_ERR(crtc_state))
13218 return PTR_ERR(crtc_state);
13219 }
13220
13221 ret = drm_atomic_set_crtc_for_connector(connector_state,
13222 set->crtc);
13223 if (ret)
13224 return ret;
13225 }
13226
13227 /* Make sure the new CRTC will work with the encoder */
13228 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13229 connector_state->crtc)) {
13230 return -EINVAL;
13231 }
13232
13233 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13234 connector->base.base.id,
13235 connector->base.name,
13236 connector_state->crtc->base.id);
13237
13238 if (connector_state->best_encoder != &connector->encoder->base)
13239 connector->encoder =
13240 to_intel_encoder(connector_state->best_encoder);
13241 }
13242
13243 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13244 bool has_connectors;
13245
13246 ret = drm_atomic_add_affected_connectors(state, crtc);
13247 if (ret)
13248 return ret;
13249
13250 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13251 if (has_connectors != crtc_state->enable)
13252 crtc_state->enable =
13253 crtc_state->active = has_connectors;
13254 }
13255
13256 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13257 set->fb, set->x, set->y);
13258 if (ret)
13259 return ret;
13260
13261 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13262 if (IS_ERR(crtc_state))
13263 return PTR_ERR(crtc_state);
13264
13265 if (set->mode)
13266 drm_mode_copy(&crtc_state->mode, set->mode);
13267
13268 if (set->num_connectors)
13269 crtc_state->active = true;
13270
13271 return 0;
13272 }
13273
13274 static int intel_crtc_set_config(struct drm_mode_set *set)
13275 {
13276 struct drm_device *dev;
13277 struct drm_atomic_state *state = NULL;
13278 int ret;
13279
13280 BUG_ON(!set);
13281 BUG_ON(!set->crtc);
13282 BUG_ON(!set->crtc->helper_private);
13283
13284 /* Enforce sane interface api - has been abused by the fb helper. */
13285 BUG_ON(!set->mode && set->fb);
13286 BUG_ON(set->fb && set->num_connectors == 0);
13287
13288 if (set->fb) {
13289 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13290 set->crtc->base.id, set->fb->base.id,
13291 (int)set->num_connectors, set->x, set->y);
13292 } else {
13293 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13294 }
13295
13296 dev = set->crtc->dev;
13297
13298 state = drm_atomic_state_alloc(dev);
13299 if (!state)
13300 return -ENOMEM;
13301
13302 state->acquire_ctx = dev->mode_config.acquire_ctx;
13303
13304 ret = intel_modeset_stage_output_state(dev, set, state);
13305 if (ret)
13306 goto out;
13307
13308 ret = intel_modeset_compute_config(state);
13309 if (ret)
13310 goto out;
13311
13312 intel_update_pipe_size(to_intel_crtc(set->crtc));
13313
13314 ret = intel_set_mode_checked(state);
13315 if (ret) {
13316 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13317 set->crtc->base.id, ret);
13318 }
13319
13320 out:
13321 if (ret)
13322 drm_atomic_state_free(state);
13323 return ret;
13324 }
13325
13326 static const struct drm_crtc_funcs intel_crtc_funcs = {
13327 .gamma_set = intel_crtc_gamma_set,
13328 .set_config = intel_crtc_set_config,
13329 .destroy = intel_crtc_destroy,
13330 .page_flip = intel_crtc_page_flip,
13331 .atomic_duplicate_state = intel_crtc_duplicate_state,
13332 .atomic_destroy_state = intel_crtc_destroy_state,
13333 };
13334
13335 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13336 struct intel_shared_dpll *pll,
13337 struct intel_dpll_hw_state *hw_state)
13338 {
13339 uint32_t val;
13340
13341 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13342 return false;
13343
13344 val = I915_READ(PCH_DPLL(pll->id));
13345 hw_state->dpll = val;
13346 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13347 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13348
13349 return val & DPLL_VCO_ENABLE;
13350 }
13351
13352 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13353 struct intel_shared_dpll *pll)
13354 {
13355 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13356 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13357 }
13358
13359 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13360 struct intel_shared_dpll *pll)
13361 {
13362 /* PCH refclock must be enabled first */
13363 ibx_assert_pch_refclk_enabled(dev_priv);
13364
13365 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13366
13367 /* Wait for the clocks to stabilize. */
13368 POSTING_READ(PCH_DPLL(pll->id));
13369 udelay(150);
13370
13371 /* The pixel multiplier can only be updated once the
13372 * DPLL is enabled and the clocks are stable.
13373 *
13374 * So write it again.
13375 */
13376 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13377 POSTING_READ(PCH_DPLL(pll->id));
13378 udelay(200);
13379 }
13380
13381 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13382 struct intel_shared_dpll *pll)
13383 {
13384 struct drm_device *dev = dev_priv->dev;
13385 struct intel_crtc *crtc;
13386
13387 /* Make sure no transcoder isn't still depending on us. */
13388 for_each_intel_crtc(dev, crtc) {
13389 if (intel_crtc_to_shared_dpll(crtc) == pll)
13390 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13391 }
13392
13393 I915_WRITE(PCH_DPLL(pll->id), 0);
13394 POSTING_READ(PCH_DPLL(pll->id));
13395 udelay(200);
13396 }
13397
13398 static char *ibx_pch_dpll_names[] = {
13399 "PCH DPLL A",
13400 "PCH DPLL B",
13401 };
13402
13403 static void ibx_pch_dpll_init(struct drm_device *dev)
13404 {
13405 struct drm_i915_private *dev_priv = dev->dev_private;
13406 int i;
13407
13408 dev_priv->num_shared_dpll = 2;
13409
13410 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13411 dev_priv->shared_dplls[i].id = i;
13412 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13413 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13414 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13415 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13416 dev_priv->shared_dplls[i].get_hw_state =
13417 ibx_pch_dpll_get_hw_state;
13418 }
13419 }
13420
13421 static void intel_shared_dpll_init(struct drm_device *dev)
13422 {
13423 struct drm_i915_private *dev_priv = dev->dev_private;
13424
13425 intel_update_cdclk(dev);
13426
13427 if (HAS_DDI(dev))
13428 intel_ddi_pll_init(dev);
13429 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13430 ibx_pch_dpll_init(dev);
13431 else
13432 dev_priv->num_shared_dpll = 0;
13433
13434 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13435 }
13436
13437 /**
13438 * intel_wm_need_update - Check whether watermarks need updating
13439 * @plane: drm plane
13440 * @state: new plane state
13441 *
13442 * Check current plane state versus the new one to determine whether
13443 * watermarks need to be recalculated.
13444 *
13445 * Returns true or false.
13446 */
13447 bool intel_wm_need_update(struct drm_plane *plane,
13448 struct drm_plane_state *state)
13449 {
13450 /* Update watermarks on tiling changes. */
13451 if (!plane->state->fb || !state->fb ||
13452 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13453 plane->state->rotation != state->rotation)
13454 return true;
13455
13456 return false;
13457 }
13458
13459 /**
13460 * intel_prepare_plane_fb - Prepare fb for usage on plane
13461 * @plane: drm plane to prepare for
13462 * @fb: framebuffer to prepare for presentation
13463 *
13464 * Prepares a framebuffer for usage on a display plane. Generally this
13465 * involves pinning the underlying object and updating the frontbuffer tracking
13466 * bits. Some older platforms need special physical address handling for
13467 * cursor planes.
13468 *
13469 * Returns 0 on success, negative error code on failure.
13470 */
13471 int
13472 intel_prepare_plane_fb(struct drm_plane *plane,
13473 struct drm_framebuffer *fb,
13474 const struct drm_plane_state *new_state)
13475 {
13476 struct drm_device *dev = plane->dev;
13477 struct intel_plane *intel_plane = to_intel_plane(plane);
13478 enum pipe pipe = intel_plane->pipe;
13479 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13480 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13481 unsigned frontbuffer_bits = 0;
13482 int ret = 0;
13483
13484 if (!obj)
13485 return 0;
13486
13487 switch (plane->type) {
13488 case DRM_PLANE_TYPE_PRIMARY:
13489 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13490 break;
13491 case DRM_PLANE_TYPE_CURSOR:
13492 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13493 break;
13494 case DRM_PLANE_TYPE_OVERLAY:
13495 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13496 break;
13497 }
13498
13499 mutex_lock(&dev->struct_mutex);
13500
13501 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13502 INTEL_INFO(dev)->cursor_needs_physical) {
13503 int align = IS_I830(dev) ? 16 * 1024 : 256;
13504 ret = i915_gem_object_attach_phys(obj, align);
13505 if (ret)
13506 DRM_DEBUG_KMS("failed to attach phys object\n");
13507 } else {
13508 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13509 }
13510
13511 if (ret == 0)
13512 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13513
13514 mutex_unlock(&dev->struct_mutex);
13515
13516 return ret;
13517 }
13518
13519 /**
13520 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13521 * @plane: drm plane to clean up for
13522 * @fb: old framebuffer that was on plane
13523 *
13524 * Cleans up a framebuffer that has just been removed from a plane.
13525 */
13526 void
13527 intel_cleanup_plane_fb(struct drm_plane *plane,
13528 struct drm_framebuffer *fb,
13529 const struct drm_plane_state *old_state)
13530 {
13531 struct drm_device *dev = plane->dev;
13532 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13533
13534 if (WARN_ON(!obj))
13535 return;
13536
13537 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13538 !INTEL_INFO(dev)->cursor_needs_physical) {
13539 mutex_lock(&dev->struct_mutex);
13540 intel_unpin_fb_obj(fb, old_state);
13541 mutex_unlock(&dev->struct_mutex);
13542 }
13543 }
13544
13545 int
13546 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13547 {
13548 int max_scale;
13549 struct drm_device *dev;
13550 struct drm_i915_private *dev_priv;
13551 int crtc_clock, cdclk;
13552
13553 if (!intel_crtc || !crtc_state)
13554 return DRM_PLANE_HELPER_NO_SCALING;
13555
13556 dev = intel_crtc->base.dev;
13557 dev_priv = dev->dev_private;
13558 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13559 cdclk = dev_priv->display.get_display_clock_speed(dev);
13560
13561 if (!crtc_clock || !cdclk)
13562 return DRM_PLANE_HELPER_NO_SCALING;
13563
13564 /*
13565 * skl max scale is lower of:
13566 * close to 3 but not 3, -1 is for that purpose
13567 * or
13568 * cdclk/crtc_clock
13569 */
13570 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13571
13572 return max_scale;
13573 }
13574
13575 static int
13576 intel_check_primary_plane(struct drm_plane *plane,
13577 struct intel_plane_state *state)
13578 {
13579 struct drm_device *dev = plane->dev;
13580 struct drm_i915_private *dev_priv = dev->dev_private;
13581 struct drm_crtc *crtc = state->base.crtc;
13582 struct intel_crtc *intel_crtc;
13583 struct intel_crtc_state *crtc_state;
13584 struct drm_framebuffer *fb = state->base.fb;
13585 struct drm_rect *dest = &state->dst;
13586 struct drm_rect *src = &state->src;
13587 const struct drm_rect *clip = &state->clip;
13588 bool can_position = false;
13589 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13590 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13591 int ret;
13592
13593 crtc = crtc ? crtc : plane->crtc;
13594 intel_crtc = to_intel_crtc(crtc);
13595 crtc_state = state->base.state ?
13596 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13597
13598 if (INTEL_INFO(dev)->gen >= 9) {
13599 /* use scaler when colorkey is not required */
13600 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13601 min_scale = 1;
13602 max_scale = skl_max_scale(intel_crtc, crtc_state);
13603 }
13604 can_position = true;
13605 }
13606
13607 ret = drm_plane_helper_check_update(plane, crtc, fb,
13608 src, dest, clip,
13609 min_scale,
13610 max_scale,
13611 can_position, true,
13612 &state->visible);
13613 if (ret)
13614 return ret;
13615
13616 if (intel_crtc->active) {
13617 struct intel_plane_state *old_state =
13618 to_intel_plane_state(plane->state);
13619
13620 intel_crtc->atomic.wait_for_flips = true;
13621
13622 /*
13623 * FBC does not work on some platforms for rotated
13624 * planes, so disable it when rotation is not 0 and
13625 * update it when rotation is set back to 0.
13626 *
13627 * FIXME: This is redundant with the fbc update done in
13628 * the primary plane enable function except that that
13629 * one is done too late. We eventually need to unify
13630 * this.
13631 */
13632 if (state->visible &&
13633 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13634 dev_priv->fbc.crtc == intel_crtc &&
13635 state->base.rotation != BIT(DRM_ROTATE_0)) {
13636 intel_crtc->atomic.disable_fbc = true;
13637 }
13638
13639 if (state->visible && !old_state->visible) {
13640 /*
13641 * BDW signals flip done immediately if the plane
13642 * is disabled, even if the plane enable is already
13643 * armed to occur at the next vblank :(
13644 */
13645 if (IS_BROADWELL(dev))
13646 intel_crtc->atomic.wait_vblank = true;
13647
13648 if (crtc_state && !needs_modeset(&crtc_state->base))
13649 intel_crtc->atomic.post_enable_primary = true;
13650 }
13651
13652 if (!state->visible && old_state->visible &&
13653 crtc_state && !needs_modeset(&crtc_state->base))
13654 intel_crtc->atomic.pre_disable_primary = true;
13655
13656 intel_crtc->atomic.fb_bits |=
13657 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13658
13659 intel_crtc->atomic.update_fbc = true;
13660
13661 if (intel_wm_need_update(plane, &state->base))
13662 intel_crtc->atomic.update_wm = true;
13663 }
13664
13665 if (INTEL_INFO(dev)->gen >= 9) {
13666 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13667 to_intel_plane(plane), state, 0);
13668 if (ret)
13669 return ret;
13670 }
13671
13672 return 0;
13673 }
13674
13675 static void
13676 intel_commit_primary_plane(struct drm_plane *plane,
13677 struct intel_plane_state *state)
13678 {
13679 struct drm_crtc *crtc = state->base.crtc;
13680 struct drm_framebuffer *fb = state->base.fb;
13681 struct drm_device *dev = plane->dev;
13682 struct drm_i915_private *dev_priv = dev->dev_private;
13683 struct intel_crtc *intel_crtc;
13684 struct drm_rect *src = &state->src;
13685
13686 crtc = crtc ? crtc : plane->crtc;
13687 intel_crtc = to_intel_crtc(crtc);
13688
13689 plane->fb = fb;
13690 crtc->x = src->x1 >> 16;
13691 crtc->y = src->y1 >> 16;
13692
13693 if (intel_crtc->active) {
13694 if (state->visible)
13695 /* FIXME: kill this fastboot hack */
13696 intel_update_pipe_size(intel_crtc);
13697
13698 dev_priv->display.update_primary_plane(crtc, plane->fb,
13699 crtc->x, crtc->y);
13700 }
13701 }
13702
13703 static void
13704 intel_disable_primary_plane(struct drm_plane *plane,
13705 struct drm_crtc *crtc,
13706 bool force)
13707 {
13708 struct drm_device *dev = plane->dev;
13709 struct drm_i915_private *dev_priv = dev->dev_private;
13710
13711 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13712 }
13713
13714 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13715 {
13716 struct drm_device *dev = crtc->dev;
13717 struct drm_i915_private *dev_priv = dev->dev_private;
13718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13719 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
13720 struct intel_plane *intel_plane;
13721 struct drm_plane *p;
13722 unsigned fb_bits = 0;
13723
13724 /* Track fb's for any planes being disabled */
13725 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13726 intel_plane = to_intel_plane(p);
13727
13728 if (intel_crtc->atomic.disabled_planes &
13729 (1 << drm_plane_index(p))) {
13730 switch (p->type) {
13731 case DRM_PLANE_TYPE_PRIMARY:
13732 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13733 break;
13734 case DRM_PLANE_TYPE_CURSOR:
13735 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13736 break;
13737 case DRM_PLANE_TYPE_OVERLAY:
13738 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13739 break;
13740 }
13741
13742 mutex_lock(&dev->struct_mutex);
13743 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13744 mutex_unlock(&dev->struct_mutex);
13745 }
13746 }
13747
13748 if (intel_crtc->atomic.wait_for_flips)
13749 intel_crtc_wait_for_pending_flips(crtc);
13750
13751 if (intel_crtc->atomic.disable_fbc)
13752 intel_fbc_disable(dev);
13753
13754 if (intel_crtc->atomic.pre_disable_primary)
13755 intel_pre_disable_primary(crtc);
13756
13757 if (intel_crtc->atomic.update_wm)
13758 intel_update_watermarks(crtc);
13759
13760 intel_runtime_pm_get(dev_priv);
13761
13762 /* Perform vblank evasion around commit operation */
13763 if (crtc_state->active && !needs_modeset(crtc_state))
13764 intel_crtc->atomic.evade =
13765 intel_pipe_update_start(intel_crtc,
13766 &intel_crtc->atomic.start_vbl_count);
13767 }
13768
13769 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13770 {
13771 struct drm_device *dev = crtc->dev;
13772 struct drm_i915_private *dev_priv = dev->dev_private;
13773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13774 struct drm_plane *p;
13775
13776 if (intel_crtc->atomic.evade)
13777 intel_pipe_update_end(intel_crtc,
13778 intel_crtc->atomic.start_vbl_count);
13779
13780 intel_runtime_pm_put(dev_priv);
13781
13782 if (intel_crtc->atomic.wait_vblank && intel_crtc->active)
13783 intel_wait_for_vblank(dev, intel_crtc->pipe);
13784
13785 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13786
13787 if (intel_crtc->atomic.update_fbc) {
13788 mutex_lock(&dev->struct_mutex);
13789 intel_fbc_update(dev);
13790 mutex_unlock(&dev->struct_mutex);
13791 }
13792
13793 if (intel_crtc->atomic.post_enable_primary)
13794 intel_post_enable_primary(crtc);
13795
13796 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13797 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13798 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13799 false, false);
13800
13801 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13802 }
13803
13804 /**
13805 * intel_plane_destroy - destroy a plane
13806 * @plane: plane to destroy
13807 *
13808 * Common destruction function for all types of planes (primary, cursor,
13809 * sprite).
13810 */
13811 void intel_plane_destroy(struct drm_plane *plane)
13812 {
13813 struct intel_plane *intel_plane = to_intel_plane(plane);
13814 drm_plane_cleanup(plane);
13815 kfree(intel_plane);
13816 }
13817
13818 const struct drm_plane_funcs intel_plane_funcs = {
13819 .update_plane = drm_atomic_helper_update_plane,
13820 .disable_plane = drm_atomic_helper_disable_plane,
13821 .destroy = intel_plane_destroy,
13822 .set_property = drm_atomic_helper_plane_set_property,
13823 .atomic_get_property = intel_plane_atomic_get_property,
13824 .atomic_set_property = intel_plane_atomic_set_property,
13825 .atomic_duplicate_state = intel_plane_duplicate_state,
13826 .atomic_destroy_state = intel_plane_destroy_state,
13827
13828 };
13829
13830 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13831 int pipe)
13832 {
13833 struct intel_plane *primary;
13834 struct intel_plane_state *state;
13835 const uint32_t *intel_primary_formats;
13836 int num_formats;
13837
13838 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13839 if (primary == NULL)
13840 return NULL;
13841
13842 state = intel_create_plane_state(&primary->base);
13843 if (!state) {
13844 kfree(primary);
13845 return NULL;
13846 }
13847 primary->base.state = &state->base;
13848
13849 primary->can_scale = false;
13850 primary->max_downscale = 1;
13851 if (INTEL_INFO(dev)->gen >= 9) {
13852 primary->can_scale = true;
13853 state->scaler_id = -1;
13854 }
13855 primary->pipe = pipe;
13856 primary->plane = pipe;
13857 primary->check_plane = intel_check_primary_plane;
13858 primary->commit_plane = intel_commit_primary_plane;
13859 primary->disable_plane = intel_disable_primary_plane;
13860 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13861 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13862 primary->plane = !pipe;
13863
13864 if (INTEL_INFO(dev)->gen >= 9) {
13865 intel_primary_formats = skl_primary_formats;
13866 num_formats = ARRAY_SIZE(skl_primary_formats);
13867 } else if (INTEL_INFO(dev)->gen >= 4) {
13868 intel_primary_formats = i965_primary_formats;
13869 num_formats = ARRAY_SIZE(i965_primary_formats);
13870 } else {
13871 intel_primary_formats = i8xx_primary_formats;
13872 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13873 }
13874
13875 drm_universal_plane_init(dev, &primary->base, 0,
13876 &intel_plane_funcs,
13877 intel_primary_formats, num_formats,
13878 DRM_PLANE_TYPE_PRIMARY);
13879
13880 if (INTEL_INFO(dev)->gen >= 4)
13881 intel_create_rotation_property(dev, primary);
13882
13883 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13884
13885 return &primary->base;
13886 }
13887
13888 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13889 {
13890 if (!dev->mode_config.rotation_property) {
13891 unsigned long flags = BIT(DRM_ROTATE_0) |
13892 BIT(DRM_ROTATE_180);
13893
13894 if (INTEL_INFO(dev)->gen >= 9)
13895 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13896
13897 dev->mode_config.rotation_property =
13898 drm_mode_create_rotation_property(dev, flags);
13899 }
13900 if (dev->mode_config.rotation_property)
13901 drm_object_attach_property(&plane->base.base,
13902 dev->mode_config.rotation_property,
13903 plane->base.state->rotation);
13904 }
13905
13906 static int
13907 intel_check_cursor_plane(struct drm_plane *plane,
13908 struct intel_plane_state *state)
13909 {
13910 struct drm_crtc *crtc = state->base.crtc;
13911 struct drm_device *dev = plane->dev;
13912 struct drm_framebuffer *fb = state->base.fb;
13913 struct drm_rect *dest = &state->dst;
13914 struct drm_rect *src = &state->src;
13915 const struct drm_rect *clip = &state->clip;
13916 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13917 struct intel_crtc *intel_crtc;
13918 unsigned stride;
13919 int ret;
13920
13921 crtc = crtc ? crtc : plane->crtc;
13922 intel_crtc = to_intel_crtc(crtc);
13923
13924 ret = drm_plane_helper_check_update(plane, crtc, fb,
13925 src, dest, clip,
13926 DRM_PLANE_HELPER_NO_SCALING,
13927 DRM_PLANE_HELPER_NO_SCALING,
13928 true, true, &state->visible);
13929 if (ret)
13930 return ret;
13931
13932
13933 /* if we want to turn off the cursor ignore width and height */
13934 if (!obj)
13935 goto finish;
13936
13937 /* Check for which cursor types we support */
13938 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13939 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13940 state->base.crtc_w, state->base.crtc_h);
13941 return -EINVAL;
13942 }
13943
13944 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13945 if (obj->base.size < stride * state->base.crtc_h) {
13946 DRM_DEBUG_KMS("buffer is too small\n");
13947 return -ENOMEM;
13948 }
13949
13950 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13951 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13952 ret = -EINVAL;
13953 }
13954
13955 finish:
13956 if (intel_crtc->active) {
13957 if (plane->state->crtc_w != state->base.crtc_w)
13958 intel_crtc->atomic.update_wm = true;
13959
13960 intel_crtc->atomic.fb_bits |=
13961 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13962 }
13963
13964 return ret;
13965 }
13966
13967 static void
13968 intel_disable_cursor_plane(struct drm_plane *plane,
13969 struct drm_crtc *crtc,
13970 bool force)
13971 {
13972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13973
13974 if (!force) {
13975 plane->fb = NULL;
13976 intel_crtc->cursor_bo = NULL;
13977 intel_crtc->cursor_addr = 0;
13978 }
13979
13980 intel_crtc_update_cursor(crtc, false);
13981 }
13982
13983 static void
13984 intel_commit_cursor_plane(struct drm_plane *plane,
13985 struct intel_plane_state *state)
13986 {
13987 struct drm_crtc *crtc = state->base.crtc;
13988 struct drm_device *dev = plane->dev;
13989 struct intel_crtc *intel_crtc;
13990 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13991 uint32_t addr;
13992
13993 crtc = crtc ? crtc : plane->crtc;
13994 intel_crtc = to_intel_crtc(crtc);
13995
13996 plane->fb = state->base.fb;
13997 crtc->cursor_x = state->base.crtc_x;
13998 crtc->cursor_y = state->base.crtc_y;
13999
14000 if (intel_crtc->cursor_bo == obj)
14001 goto update;
14002
14003 if (!obj)
14004 addr = 0;
14005 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14006 addr = i915_gem_obj_ggtt_offset(obj);
14007 else
14008 addr = obj->phys_handle->busaddr;
14009
14010 intel_crtc->cursor_addr = addr;
14011 intel_crtc->cursor_bo = obj;
14012 update:
14013
14014 if (intel_crtc->active)
14015 intel_crtc_update_cursor(crtc, state->visible);
14016 }
14017
14018 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14019 int pipe)
14020 {
14021 struct intel_plane *cursor;
14022 struct intel_plane_state *state;
14023
14024 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14025 if (cursor == NULL)
14026 return NULL;
14027
14028 state = intel_create_plane_state(&cursor->base);
14029 if (!state) {
14030 kfree(cursor);
14031 return NULL;
14032 }
14033 cursor->base.state = &state->base;
14034
14035 cursor->can_scale = false;
14036 cursor->max_downscale = 1;
14037 cursor->pipe = pipe;
14038 cursor->plane = pipe;
14039 cursor->check_plane = intel_check_cursor_plane;
14040 cursor->commit_plane = intel_commit_cursor_plane;
14041 cursor->disable_plane = intel_disable_cursor_plane;
14042
14043 drm_universal_plane_init(dev, &cursor->base, 0,
14044 &intel_plane_funcs,
14045 intel_cursor_formats,
14046 ARRAY_SIZE(intel_cursor_formats),
14047 DRM_PLANE_TYPE_CURSOR);
14048
14049 if (INTEL_INFO(dev)->gen >= 4) {
14050 if (!dev->mode_config.rotation_property)
14051 dev->mode_config.rotation_property =
14052 drm_mode_create_rotation_property(dev,
14053 BIT(DRM_ROTATE_0) |
14054 BIT(DRM_ROTATE_180));
14055 if (dev->mode_config.rotation_property)
14056 drm_object_attach_property(&cursor->base.base,
14057 dev->mode_config.rotation_property,
14058 state->base.rotation);
14059 }
14060
14061 if (INTEL_INFO(dev)->gen >=9)
14062 state->scaler_id = -1;
14063
14064 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14065
14066 return &cursor->base;
14067 }
14068
14069 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14070 struct intel_crtc_state *crtc_state)
14071 {
14072 int i;
14073 struct intel_scaler *intel_scaler;
14074 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14075
14076 for (i = 0; i < intel_crtc->num_scalers; i++) {
14077 intel_scaler = &scaler_state->scalers[i];
14078 intel_scaler->in_use = 0;
14079 intel_scaler->id = i;
14080
14081 intel_scaler->mode = PS_SCALER_MODE_DYN;
14082 }
14083
14084 scaler_state->scaler_id = -1;
14085 }
14086
14087 static void intel_crtc_init(struct drm_device *dev, int pipe)
14088 {
14089 struct drm_i915_private *dev_priv = dev->dev_private;
14090 struct intel_crtc *intel_crtc;
14091 struct intel_crtc_state *crtc_state = NULL;
14092 struct drm_plane *primary = NULL;
14093 struct drm_plane *cursor = NULL;
14094 int i, ret;
14095
14096 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14097 if (intel_crtc == NULL)
14098 return;
14099
14100 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14101 if (!crtc_state)
14102 goto fail;
14103 intel_crtc->config = crtc_state;
14104 intel_crtc->base.state = &crtc_state->base;
14105 crtc_state->base.crtc = &intel_crtc->base;
14106
14107 /* initialize shared scalers */
14108 if (INTEL_INFO(dev)->gen >= 9) {
14109 if (pipe == PIPE_C)
14110 intel_crtc->num_scalers = 1;
14111 else
14112 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14113
14114 skl_init_scalers(dev, intel_crtc, crtc_state);
14115 }
14116
14117 primary = intel_primary_plane_create(dev, pipe);
14118 if (!primary)
14119 goto fail;
14120
14121 cursor = intel_cursor_plane_create(dev, pipe);
14122 if (!cursor)
14123 goto fail;
14124
14125 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14126 cursor, &intel_crtc_funcs);
14127 if (ret)
14128 goto fail;
14129
14130 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14131 for (i = 0; i < 256; i++) {
14132 intel_crtc->lut_r[i] = i;
14133 intel_crtc->lut_g[i] = i;
14134 intel_crtc->lut_b[i] = i;
14135 }
14136
14137 /*
14138 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14139 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14140 */
14141 intel_crtc->pipe = pipe;
14142 intel_crtc->plane = pipe;
14143 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14144 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14145 intel_crtc->plane = !pipe;
14146 }
14147
14148 intel_crtc->cursor_base = ~0;
14149 intel_crtc->cursor_cntl = ~0;
14150 intel_crtc->cursor_size = ~0;
14151
14152 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14153 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14154 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14155 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14156
14157 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14158
14159 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14160 return;
14161
14162 fail:
14163 if (primary)
14164 drm_plane_cleanup(primary);
14165 if (cursor)
14166 drm_plane_cleanup(cursor);
14167 kfree(crtc_state);
14168 kfree(intel_crtc);
14169 }
14170
14171 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14172 {
14173 struct drm_encoder *encoder = connector->base.encoder;
14174 struct drm_device *dev = connector->base.dev;
14175
14176 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14177
14178 if (!encoder || WARN_ON(!encoder->crtc))
14179 return INVALID_PIPE;
14180
14181 return to_intel_crtc(encoder->crtc)->pipe;
14182 }
14183
14184 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14185 struct drm_file *file)
14186 {
14187 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14188 struct drm_crtc *drmmode_crtc;
14189 struct intel_crtc *crtc;
14190
14191 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14192
14193 if (!drmmode_crtc) {
14194 DRM_ERROR("no such CRTC id\n");
14195 return -ENOENT;
14196 }
14197
14198 crtc = to_intel_crtc(drmmode_crtc);
14199 pipe_from_crtc_id->pipe = crtc->pipe;
14200
14201 return 0;
14202 }
14203
14204 static int intel_encoder_clones(struct intel_encoder *encoder)
14205 {
14206 struct drm_device *dev = encoder->base.dev;
14207 struct intel_encoder *source_encoder;
14208 int index_mask = 0;
14209 int entry = 0;
14210
14211 for_each_intel_encoder(dev, source_encoder) {
14212 if (encoders_cloneable(encoder, source_encoder))
14213 index_mask |= (1 << entry);
14214
14215 entry++;
14216 }
14217
14218 return index_mask;
14219 }
14220
14221 static bool has_edp_a(struct drm_device *dev)
14222 {
14223 struct drm_i915_private *dev_priv = dev->dev_private;
14224
14225 if (!IS_MOBILE(dev))
14226 return false;
14227
14228 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14229 return false;
14230
14231 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14232 return false;
14233
14234 return true;
14235 }
14236
14237 static bool intel_crt_present(struct drm_device *dev)
14238 {
14239 struct drm_i915_private *dev_priv = dev->dev_private;
14240
14241 if (INTEL_INFO(dev)->gen >= 9)
14242 return false;
14243
14244 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14245 return false;
14246
14247 if (IS_CHERRYVIEW(dev))
14248 return false;
14249
14250 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14251 return false;
14252
14253 return true;
14254 }
14255
14256 static void intel_setup_outputs(struct drm_device *dev)
14257 {
14258 struct drm_i915_private *dev_priv = dev->dev_private;
14259 struct intel_encoder *encoder;
14260 bool dpd_is_edp = false;
14261
14262 intel_lvds_init(dev);
14263
14264 if (intel_crt_present(dev))
14265 intel_crt_init(dev);
14266
14267 if (IS_BROXTON(dev)) {
14268 /*
14269 * FIXME: Broxton doesn't support port detection via the
14270 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14271 * detect the ports.
14272 */
14273 intel_ddi_init(dev, PORT_A);
14274 intel_ddi_init(dev, PORT_B);
14275 intel_ddi_init(dev, PORT_C);
14276 } else if (HAS_DDI(dev)) {
14277 int found;
14278
14279 /*
14280 * Haswell uses DDI functions to detect digital outputs.
14281 * On SKL pre-D0 the strap isn't connected, so we assume
14282 * it's there.
14283 */
14284 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14285 /* WaIgnoreDDIAStrap: skl */
14286 if (found ||
14287 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14288 intel_ddi_init(dev, PORT_A);
14289
14290 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14291 * register */
14292 found = I915_READ(SFUSE_STRAP);
14293
14294 if (found & SFUSE_STRAP_DDIB_DETECTED)
14295 intel_ddi_init(dev, PORT_B);
14296 if (found & SFUSE_STRAP_DDIC_DETECTED)
14297 intel_ddi_init(dev, PORT_C);
14298 if (found & SFUSE_STRAP_DDID_DETECTED)
14299 intel_ddi_init(dev, PORT_D);
14300 } else if (HAS_PCH_SPLIT(dev)) {
14301 int found;
14302 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14303
14304 if (has_edp_a(dev))
14305 intel_dp_init(dev, DP_A, PORT_A);
14306
14307 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14308 /* PCH SDVOB multiplex with HDMIB */
14309 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14310 if (!found)
14311 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14312 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14313 intel_dp_init(dev, PCH_DP_B, PORT_B);
14314 }
14315
14316 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14317 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14318
14319 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14320 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14321
14322 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14323 intel_dp_init(dev, PCH_DP_C, PORT_C);
14324
14325 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14326 intel_dp_init(dev, PCH_DP_D, PORT_D);
14327 } else if (IS_VALLEYVIEW(dev)) {
14328 /*
14329 * The DP_DETECTED bit is the latched state of the DDC
14330 * SDA pin at boot. However since eDP doesn't require DDC
14331 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14332 * eDP ports may have been muxed to an alternate function.
14333 * Thus we can't rely on the DP_DETECTED bit alone to detect
14334 * eDP ports. Consult the VBT as well as DP_DETECTED to
14335 * detect eDP ports.
14336 */
14337 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14338 !intel_dp_is_edp(dev, PORT_B))
14339 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14340 PORT_B);
14341 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14342 intel_dp_is_edp(dev, PORT_B))
14343 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14344
14345 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14346 !intel_dp_is_edp(dev, PORT_C))
14347 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14348 PORT_C);
14349 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14350 intel_dp_is_edp(dev, PORT_C))
14351 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14352
14353 if (IS_CHERRYVIEW(dev)) {
14354 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14355 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14356 PORT_D);
14357 /* eDP not supported on port D, so don't check VBT */
14358 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14359 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14360 }
14361
14362 intel_dsi_init(dev);
14363 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14364 bool found = false;
14365
14366 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14367 DRM_DEBUG_KMS("probing SDVOB\n");
14368 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14369 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14370 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14371 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14372 }
14373
14374 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14375 intel_dp_init(dev, DP_B, PORT_B);
14376 }
14377
14378 /* Before G4X SDVOC doesn't have its own detect register */
14379
14380 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14381 DRM_DEBUG_KMS("probing SDVOC\n");
14382 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14383 }
14384
14385 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14386
14387 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14388 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14389 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14390 }
14391 if (SUPPORTS_INTEGRATED_DP(dev))
14392 intel_dp_init(dev, DP_C, PORT_C);
14393 }
14394
14395 if (SUPPORTS_INTEGRATED_DP(dev) &&
14396 (I915_READ(DP_D) & DP_DETECTED))
14397 intel_dp_init(dev, DP_D, PORT_D);
14398 } else if (IS_GEN2(dev))
14399 intel_dvo_init(dev);
14400
14401 if (SUPPORTS_TV(dev))
14402 intel_tv_init(dev);
14403
14404 intel_psr_init(dev);
14405
14406 for_each_intel_encoder(dev, encoder) {
14407 encoder->base.possible_crtcs = encoder->crtc_mask;
14408 encoder->base.possible_clones =
14409 intel_encoder_clones(encoder);
14410 }
14411
14412 intel_init_pch_refclk(dev);
14413
14414 drm_helper_move_panel_connectors_to_head(dev);
14415 }
14416
14417 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14418 {
14419 struct drm_device *dev = fb->dev;
14420 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14421
14422 drm_framebuffer_cleanup(fb);
14423 mutex_lock(&dev->struct_mutex);
14424 WARN_ON(!intel_fb->obj->framebuffer_references--);
14425 drm_gem_object_unreference(&intel_fb->obj->base);
14426 mutex_unlock(&dev->struct_mutex);
14427 kfree(intel_fb);
14428 }
14429
14430 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14431 struct drm_file *file,
14432 unsigned int *handle)
14433 {
14434 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14435 struct drm_i915_gem_object *obj = intel_fb->obj;
14436
14437 return drm_gem_handle_create(file, &obj->base, handle);
14438 }
14439
14440 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14441 .destroy = intel_user_framebuffer_destroy,
14442 .create_handle = intel_user_framebuffer_create_handle,
14443 };
14444
14445 static
14446 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14447 uint32_t pixel_format)
14448 {
14449 u32 gen = INTEL_INFO(dev)->gen;
14450
14451 if (gen >= 9) {
14452 /* "The stride in bytes must not exceed the of the size of 8K
14453 * pixels and 32K bytes."
14454 */
14455 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14456 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14457 return 32*1024;
14458 } else if (gen >= 4) {
14459 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14460 return 16*1024;
14461 else
14462 return 32*1024;
14463 } else if (gen >= 3) {
14464 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14465 return 8*1024;
14466 else
14467 return 16*1024;
14468 } else {
14469 /* XXX DSPC is limited to 4k tiled */
14470 return 8*1024;
14471 }
14472 }
14473
14474 static int intel_framebuffer_init(struct drm_device *dev,
14475 struct intel_framebuffer *intel_fb,
14476 struct drm_mode_fb_cmd2 *mode_cmd,
14477 struct drm_i915_gem_object *obj)
14478 {
14479 unsigned int aligned_height;
14480 int ret;
14481 u32 pitch_limit, stride_alignment;
14482
14483 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14484
14485 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14486 /* Enforce that fb modifier and tiling mode match, but only for
14487 * X-tiled. This is needed for FBC. */
14488 if (!!(obj->tiling_mode == I915_TILING_X) !=
14489 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14490 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14491 return -EINVAL;
14492 }
14493 } else {
14494 if (obj->tiling_mode == I915_TILING_X)
14495 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14496 else if (obj->tiling_mode == I915_TILING_Y) {
14497 DRM_DEBUG("No Y tiling for legacy addfb\n");
14498 return -EINVAL;
14499 }
14500 }
14501
14502 /* Passed in modifier sanity checking. */
14503 switch (mode_cmd->modifier[0]) {
14504 case I915_FORMAT_MOD_Y_TILED:
14505 case I915_FORMAT_MOD_Yf_TILED:
14506 if (INTEL_INFO(dev)->gen < 9) {
14507 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14508 mode_cmd->modifier[0]);
14509 return -EINVAL;
14510 }
14511 case DRM_FORMAT_MOD_NONE:
14512 case I915_FORMAT_MOD_X_TILED:
14513 break;
14514 default:
14515 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14516 mode_cmd->modifier[0]);
14517 return -EINVAL;
14518 }
14519
14520 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14521 mode_cmd->pixel_format);
14522 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14523 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14524 mode_cmd->pitches[0], stride_alignment);
14525 return -EINVAL;
14526 }
14527
14528 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14529 mode_cmd->pixel_format);
14530 if (mode_cmd->pitches[0] > pitch_limit) {
14531 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14532 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14533 "tiled" : "linear",
14534 mode_cmd->pitches[0], pitch_limit);
14535 return -EINVAL;
14536 }
14537
14538 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14539 mode_cmd->pitches[0] != obj->stride) {
14540 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14541 mode_cmd->pitches[0], obj->stride);
14542 return -EINVAL;
14543 }
14544
14545 /* Reject formats not supported by any plane early. */
14546 switch (mode_cmd->pixel_format) {
14547 case DRM_FORMAT_C8:
14548 case DRM_FORMAT_RGB565:
14549 case DRM_FORMAT_XRGB8888:
14550 case DRM_FORMAT_ARGB8888:
14551 break;
14552 case DRM_FORMAT_XRGB1555:
14553 if (INTEL_INFO(dev)->gen > 3) {
14554 DRM_DEBUG("unsupported pixel format: %s\n",
14555 drm_get_format_name(mode_cmd->pixel_format));
14556 return -EINVAL;
14557 }
14558 break;
14559 case DRM_FORMAT_ABGR8888:
14560 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14561 DRM_DEBUG("unsupported pixel format: %s\n",
14562 drm_get_format_name(mode_cmd->pixel_format));
14563 return -EINVAL;
14564 }
14565 break;
14566 case DRM_FORMAT_XBGR8888:
14567 case DRM_FORMAT_XRGB2101010:
14568 case DRM_FORMAT_XBGR2101010:
14569 if (INTEL_INFO(dev)->gen < 4) {
14570 DRM_DEBUG("unsupported pixel format: %s\n",
14571 drm_get_format_name(mode_cmd->pixel_format));
14572 return -EINVAL;
14573 }
14574 break;
14575 case DRM_FORMAT_ABGR2101010:
14576 if (!IS_VALLEYVIEW(dev)) {
14577 DRM_DEBUG("unsupported pixel format: %s\n",
14578 drm_get_format_name(mode_cmd->pixel_format));
14579 return -EINVAL;
14580 }
14581 break;
14582 case DRM_FORMAT_YUYV:
14583 case DRM_FORMAT_UYVY:
14584 case DRM_FORMAT_YVYU:
14585 case DRM_FORMAT_VYUY:
14586 if (INTEL_INFO(dev)->gen < 5) {
14587 DRM_DEBUG("unsupported pixel format: %s\n",
14588 drm_get_format_name(mode_cmd->pixel_format));
14589 return -EINVAL;
14590 }
14591 break;
14592 default:
14593 DRM_DEBUG("unsupported pixel format: %s\n",
14594 drm_get_format_name(mode_cmd->pixel_format));
14595 return -EINVAL;
14596 }
14597
14598 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14599 if (mode_cmd->offsets[0] != 0)
14600 return -EINVAL;
14601
14602 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14603 mode_cmd->pixel_format,
14604 mode_cmd->modifier[0]);
14605 /* FIXME drm helper for size checks (especially planar formats)? */
14606 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14607 return -EINVAL;
14608
14609 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14610 intel_fb->obj = obj;
14611 intel_fb->obj->framebuffer_references++;
14612
14613 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14614 if (ret) {
14615 DRM_ERROR("framebuffer init failed %d\n", ret);
14616 return ret;
14617 }
14618
14619 return 0;
14620 }
14621
14622 static struct drm_framebuffer *
14623 intel_user_framebuffer_create(struct drm_device *dev,
14624 struct drm_file *filp,
14625 struct drm_mode_fb_cmd2 *mode_cmd)
14626 {
14627 struct drm_i915_gem_object *obj;
14628
14629 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14630 mode_cmd->handles[0]));
14631 if (&obj->base == NULL)
14632 return ERR_PTR(-ENOENT);
14633
14634 return intel_framebuffer_create(dev, mode_cmd, obj);
14635 }
14636
14637 #ifndef CONFIG_DRM_I915_FBDEV
14638 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14639 {
14640 }
14641 #endif
14642
14643 static const struct drm_mode_config_funcs intel_mode_funcs = {
14644 .fb_create = intel_user_framebuffer_create,
14645 .output_poll_changed = intel_fbdev_output_poll_changed,
14646 .atomic_check = intel_atomic_check,
14647 .atomic_commit = intel_atomic_commit,
14648 .atomic_state_alloc = intel_atomic_state_alloc,
14649 .atomic_state_clear = intel_atomic_state_clear,
14650 };
14651
14652 /* Set up chip specific display functions */
14653 static void intel_init_display(struct drm_device *dev)
14654 {
14655 struct drm_i915_private *dev_priv = dev->dev_private;
14656
14657 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14658 dev_priv->display.find_dpll = g4x_find_best_dpll;
14659 else if (IS_CHERRYVIEW(dev))
14660 dev_priv->display.find_dpll = chv_find_best_dpll;
14661 else if (IS_VALLEYVIEW(dev))
14662 dev_priv->display.find_dpll = vlv_find_best_dpll;
14663 else if (IS_PINEVIEW(dev))
14664 dev_priv->display.find_dpll = pnv_find_best_dpll;
14665 else
14666 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14667
14668 if (INTEL_INFO(dev)->gen >= 9) {
14669 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14670 dev_priv->display.get_initial_plane_config =
14671 skylake_get_initial_plane_config;
14672 dev_priv->display.crtc_compute_clock =
14673 haswell_crtc_compute_clock;
14674 dev_priv->display.crtc_enable = haswell_crtc_enable;
14675 dev_priv->display.crtc_disable = haswell_crtc_disable;
14676 dev_priv->display.update_primary_plane =
14677 skylake_update_primary_plane;
14678 } else if (HAS_DDI(dev)) {
14679 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14680 dev_priv->display.get_initial_plane_config =
14681 ironlake_get_initial_plane_config;
14682 dev_priv->display.crtc_compute_clock =
14683 haswell_crtc_compute_clock;
14684 dev_priv->display.crtc_enable = haswell_crtc_enable;
14685 dev_priv->display.crtc_disable = haswell_crtc_disable;
14686 dev_priv->display.update_primary_plane =
14687 ironlake_update_primary_plane;
14688 } else if (HAS_PCH_SPLIT(dev)) {
14689 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14690 dev_priv->display.get_initial_plane_config =
14691 ironlake_get_initial_plane_config;
14692 dev_priv->display.crtc_compute_clock =
14693 ironlake_crtc_compute_clock;
14694 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14695 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14696 dev_priv->display.update_primary_plane =
14697 ironlake_update_primary_plane;
14698 } else if (IS_VALLEYVIEW(dev)) {
14699 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14700 dev_priv->display.get_initial_plane_config =
14701 i9xx_get_initial_plane_config;
14702 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14703 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14704 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14705 dev_priv->display.update_primary_plane =
14706 i9xx_update_primary_plane;
14707 } else {
14708 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14709 dev_priv->display.get_initial_plane_config =
14710 i9xx_get_initial_plane_config;
14711 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14712 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14713 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14714 dev_priv->display.update_primary_plane =
14715 i9xx_update_primary_plane;
14716 }
14717
14718 /* Returns the core display clock speed */
14719 if (IS_SKYLAKE(dev))
14720 dev_priv->display.get_display_clock_speed =
14721 skylake_get_display_clock_speed;
14722 else if (IS_BROADWELL(dev))
14723 dev_priv->display.get_display_clock_speed =
14724 broadwell_get_display_clock_speed;
14725 else if (IS_HASWELL(dev))
14726 dev_priv->display.get_display_clock_speed =
14727 haswell_get_display_clock_speed;
14728 else if (IS_VALLEYVIEW(dev))
14729 dev_priv->display.get_display_clock_speed =
14730 valleyview_get_display_clock_speed;
14731 else if (IS_GEN5(dev))
14732 dev_priv->display.get_display_clock_speed =
14733 ilk_get_display_clock_speed;
14734 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14735 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14736 dev_priv->display.get_display_clock_speed =
14737 i945_get_display_clock_speed;
14738 else if (IS_GM45(dev))
14739 dev_priv->display.get_display_clock_speed =
14740 gm45_get_display_clock_speed;
14741 else if (IS_CRESTLINE(dev))
14742 dev_priv->display.get_display_clock_speed =
14743 i965gm_get_display_clock_speed;
14744 else if (IS_PINEVIEW(dev))
14745 dev_priv->display.get_display_clock_speed =
14746 pnv_get_display_clock_speed;
14747 else if (IS_G33(dev) || IS_G4X(dev))
14748 dev_priv->display.get_display_clock_speed =
14749 g33_get_display_clock_speed;
14750 else if (IS_I915G(dev))
14751 dev_priv->display.get_display_clock_speed =
14752 i915_get_display_clock_speed;
14753 else if (IS_I945GM(dev) || IS_845G(dev))
14754 dev_priv->display.get_display_clock_speed =
14755 i9xx_misc_get_display_clock_speed;
14756 else if (IS_PINEVIEW(dev))
14757 dev_priv->display.get_display_clock_speed =
14758 pnv_get_display_clock_speed;
14759 else if (IS_I915GM(dev))
14760 dev_priv->display.get_display_clock_speed =
14761 i915gm_get_display_clock_speed;
14762 else if (IS_I865G(dev))
14763 dev_priv->display.get_display_clock_speed =
14764 i865_get_display_clock_speed;
14765 else if (IS_I85X(dev))
14766 dev_priv->display.get_display_clock_speed =
14767 i85x_get_display_clock_speed;
14768 else { /* 830 */
14769 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14770 dev_priv->display.get_display_clock_speed =
14771 i830_get_display_clock_speed;
14772 }
14773
14774 if (IS_GEN5(dev)) {
14775 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14776 } else if (IS_GEN6(dev)) {
14777 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14778 } else if (IS_IVYBRIDGE(dev)) {
14779 /* FIXME: detect B0+ stepping and use auto training */
14780 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14781 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14782 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14783 if (IS_BROADWELL(dev))
14784 dev_priv->display.modeset_global_resources =
14785 broadwell_modeset_global_resources;
14786 } else if (IS_VALLEYVIEW(dev)) {
14787 dev_priv->display.modeset_global_resources =
14788 valleyview_modeset_global_resources;
14789 } else if (IS_BROXTON(dev)) {
14790 dev_priv->display.modeset_global_resources =
14791 broxton_modeset_global_resources;
14792 }
14793
14794 switch (INTEL_INFO(dev)->gen) {
14795 case 2:
14796 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14797 break;
14798
14799 case 3:
14800 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14801 break;
14802
14803 case 4:
14804 case 5:
14805 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14806 break;
14807
14808 case 6:
14809 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14810 break;
14811 case 7:
14812 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14813 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14814 break;
14815 case 9:
14816 /* Drop through - unsupported since execlist only. */
14817 default:
14818 /* Default just returns -ENODEV to indicate unsupported */
14819 dev_priv->display.queue_flip = intel_default_queue_flip;
14820 }
14821
14822 intel_panel_init_backlight_funcs(dev);
14823
14824 mutex_init(&dev_priv->pps_mutex);
14825 }
14826
14827 /*
14828 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14829 * resume, or other times. This quirk makes sure that's the case for
14830 * affected systems.
14831 */
14832 static void quirk_pipea_force(struct drm_device *dev)
14833 {
14834 struct drm_i915_private *dev_priv = dev->dev_private;
14835
14836 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14837 DRM_INFO("applying pipe a force quirk\n");
14838 }
14839
14840 static void quirk_pipeb_force(struct drm_device *dev)
14841 {
14842 struct drm_i915_private *dev_priv = dev->dev_private;
14843
14844 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14845 DRM_INFO("applying pipe b force quirk\n");
14846 }
14847
14848 /*
14849 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14850 */
14851 static void quirk_ssc_force_disable(struct drm_device *dev)
14852 {
14853 struct drm_i915_private *dev_priv = dev->dev_private;
14854 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14855 DRM_INFO("applying lvds SSC disable quirk\n");
14856 }
14857
14858 /*
14859 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14860 * brightness value
14861 */
14862 static void quirk_invert_brightness(struct drm_device *dev)
14863 {
14864 struct drm_i915_private *dev_priv = dev->dev_private;
14865 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14866 DRM_INFO("applying inverted panel brightness quirk\n");
14867 }
14868
14869 /* Some VBT's incorrectly indicate no backlight is present */
14870 static void quirk_backlight_present(struct drm_device *dev)
14871 {
14872 struct drm_i915_private *dev_priv = dev->dev_private;
14873 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14874 DRM_INFO("applying backlight present quirk\n");
14875 }
14876
14877 struct intel_quirk {
14878 int device;
14879 int subsystem_vendor;
14880 int subsystem_device;
14881 void (*hook)(struct drm_device *dev);
14882 };
14883
14884 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14885 struct intel_dmi_quirk {
14886 void (*hook)(struct drm_device *dev);
14887 const struct dmi_system_id (*dmi_id_list)[];
14888 };
14889
14890 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14891 {
14892 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14893 return 1;
14894 }
14895
14896 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14897 {
14898 .dmi_id_list = &(const struct dmi_system_id[]) {
14899 {
14900 .callback = intel_dmi_reverse_brightness,
14901 .ident = "NCR Corporation",
14902 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14903 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14904 },
14905 },
14906 { } /* terminating entry */
14907 },
14908 .hook = quirk_invert_brightness,
14909 },
14910 };
14911
14912 static struct intel_quirk intel_quirks[] = {
14913 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14914 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14915
14916 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14917 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14918
14919 /* 830 needs to leave pipe A & dpll A up */
14920 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14921
14922 /* 830 needs to leave pipe B & dpll B up */
14923 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14924
14925 /* Lenovo U160 cannot use SSC on LVDS */
14926 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14927
14928 /* Sony Vaio Y cannot use SSC on LVDS */
14929 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14930
14931 /* Acer Aspire 5734Z must invert backlight brightness */
14932 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14933
14934 /* Acer/eMachines G725 */
14935 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14936
14937 /* Acer/eMachines e725 */
14938 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14939
14940 /* Acer/Packard Bell NCL20 */
14941 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14942
14943 /* Acer Aspire 4736Z */
14944 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14945
14946 /* Acer Aspire 5336 */
14947 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14948
14949 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14950 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14951
14952 /* Acer C720 Chromebook (Core i3 4005U) */
14953 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14954
14955 /* Apple Macbook 2,1 (Core 2 T7400) */
14956 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14957
14958 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14959 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14960
14961 /* HP Chromebook 14 (Celeron 2955U) */
14962 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14963
14964 /* Dell Chromebook 11 */
14965 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14966 };
14967
14968 static void intel_init_quirks(struct drm_device *dev)
14969 {
14970 struct pci_dev *d = dev->pdev;
14971 int i;
14972
14973 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14974 struct intel_quirk *q = &intel_quirks[i];
14975
14976 if (d->device == q->device &&
14977 (d->subsystem_vendor == q->subsystem_vendor ||
14978 q->subsystem_vendor == PCI_ANY_ID) &&
14979 (d->subsystem_device == q->subsystem_device ||
14980 q->subsystem_device == PCI_ANY_ID))
14981 q->hook(dev);
14982 }
14983 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14984 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14985 intel_dmi_quirks[i].hook(dev);
14986 }
14987 }
14988
14989 /* Disable the VGA plane that we never use */
14990 static void i915_disable_vga(struct drm_device *dev)
14991 {
14992 struct drm_i915_private *dev_priv = dev->dev_private;
14993 u8 sr1;
14994 u32 vga_reg = i915_vgacntrl_reg(dev);
14995
14996 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14997 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14998 outb(SR01, VGA_SR_INDEX);
14999 sr1 = inb(VGA_SR_DATA);
15000 outb(sr1 | 1<<5, VGA_SR_DATA);
15001 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15002 udelay(300);
15003
15004 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15005 POSTING_READ(vga_reg);
15006 }
15007
15008 void intel_modeset_init_hw(struct drm_device *dev)
15009 {
15010 intel_update_cdclk(dev);
15011 intel_prepare_ddi(dev);
15012 intel_init_clock_gating(dev);
15013 intel_enable_gt_powersave(dev);
15014 }
15015
15016 void intel_modeset_init(struct drm_device *dev)
15017 {
15018 struct drm_i915_private *dev_priv = dev->dev_private;
15019 int sprite, ret;
15020 enum pipe pipe;
15021 struct intel_crtc *crtc;
15022
15023 drm_mode_config_init(dev);
15024
15025 dev->mode_config.min_width = 0;
15026 dev->mode_config.min_height = 0;
15027
15028 dev->mode_config.preferred_depth = 24;
15029 dev->mode_config.prefer_shadow = 1;
15030
15031 dev->mode_config.allow_fb_modifiers = true;
15032
15033 dev->mode_config.funcs = &intel_mode_funcs;
15034
15035 intel_init_quirks(dev);
15036
15037 intel_init_pm(dev);
15038
15039 if (INTEL_INFO(dev)->num_pipes == 0)
15040 return;
15041
15042 intel_init_display(dev);
15043 intel_init_audio(dev);
15044
15045 if (IS_GEN2(dev)) {
15046 dev->mode_config.max_width = 2048;
15047 dev->mode_config.max_height = 2048;
15048 } else if (IS_GEN3(dev)) {
15049 dev->mode_config.max_width = 4096;
15050 dev->mode_config.max_height = 4096;
15051 } else {
15052 dev->mode_config.max_width = 8192;
15053 dev->mode_config.max_height = 8192;
15054 }
15055
15056 if (IS_845G(dev) || IS_I865G(dev)) {
15057 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15058 dev->mode_config.cursor_height = 1023;
15059 } else if (IS_GEN2(dev)) {
15060 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15061 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15062 } else {
15063 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15064 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15065 }
15066
15067 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15068
15069 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15070 INTEL_INFO(dev)->num_pipes,
15071 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15072
15073 for_each_pipe(dev_priv, pipe) {
15074 intel_crtc_init(dev, pipe);
15075 for_each_sprite(dev_priv, pipe, sprite) {
15076 ret = intel_plane_init(dev, pipe, sprite);
15077 if (ret)
15078 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15079 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15080 }
15081 }
15082
15083 intel_init_dpio(dev);
15084
15085 intel_shared_dpll_init(dev);
15086
15087 /* Just disable it once at startup */
15088 i915_disable_vga(dev);
15089 intel_setup_outputs(dev);
15090
15091 /* Just in case the BIOS is doing something questionable. */
15092 intel_fbc_disable(dev);
15093
15094 drm_modeset_lock_all(dev);
15095 intel_modeset_setup_hw_state(dev, false);
15096 drm_modeset_unlock_all(dev);
15097
15098 for_each_intel_crtc(dev, crtc) {
15099 if (!crtc->active)
15100 continue;
15101
15102 /*
15103 * Note that reserving the BIOS fb up front prevents us
15104 * from stuffing other stolen allocations like the ring
15105 * on top. This prevents some ugliness at boot time, and
15106 * can even allow for smooth boot transitions if the BIOS
15107 * fb is large enough for the active pipe configuration.
15108 */
15109 if (dev_priv->display.get_initial_plane_config) {
15110 dev_priv->display.get_initial_plane_config(crtc,
15111 &crtc->plane_config);
15112 /*
15113 * If the fb is shared between multiple heads, we'll
15114 * just get the first one.
15115 */
15116 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15117 }
15118 }
15119 }
15120
15121 static void intel_enable_pipe_a(struct drm_device *dev)
15122 {
15123 struct intel_connector *connector;
15124 struct drm_connector *crt = NULL;
15125 struct intel_load_detect_pipe load_detect_temp;
15126 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15127
15128 /* We can't just switch on the pipe A, we need to set things up with a
15129 * proper mode and output configuration. As a gross hack, enable pipe A
15130 * by enabling the load detect pipe once. */
15131 for_each_intel_connector(dev, connector) {
15132 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15133 crt = &connector->base;
15134 break;
15135 }
15136 }
15137
15138 if (!crt)
15139 return;
15140
15141 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15142 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15143 }
15144
15145 static bool
15146 intel_check_plane_mapping(struct intel_crtc *crtc)
15147 {
15148 struct drm_device *dev = crtc->base.dev;
15149 struct drm_i915_private *dev_priv = dev->dev_private;
15150 u32 reg, val;
15151
15152 if (INTEL_INFO(dev)->num_pipes == 1)
15153 return true;
15154
15155 reg = DSPCNTR(!crtc->plane);
15156 val = I915_READ(reg);
15157
15158 if ((val & DISPLAY_PLANE_ENABLE) &&
15159 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15160 return false;
15161
15162 return true;
15163 }
15164
15165 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15166 {
15167 struct drm_device *dev = crtc->base.dev;
15168 struct drm_i915_private *dev_priv = dev->dev_private;
15169 struct intel_encoder *encoder;
15170 u32 reg;
15171 bool enable;
15172
15173 /* Clear any frame start delays used for debugging left by the BIOS */
15174 reg = PIPECONF(crtc->config->cpu_transcoder);
15175 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15176
15177 /* restore vblank interrupts to correct state */
15178 drm_crtc_vblank_reset(&crtc->base);
15179 if (crtc->active) {
15180 update_scanline_offset(crtc);
15181 drm_crtc_vblank_on(&crtc->base);
15182 }
15183
15184 /* We need to sanitize the plane -> pipe mapping first because this will
15185 * disable the crtc (and hence change the state) if it is wrong. Note
15186 * that gen4+ has a fixed plane -> pipe mapping. */
15187 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15188 bool plane;
15189
15190 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15191 crtc->base.base.id);
15192
15193 /* Pipe has the wrong plane attached and the plane is active.
15194 * Temporarily change the plane mapping and disable everything
15195 * ... */
15196 plane = crtc->plane;
15197 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15198 crtc->plane = !plane;
15199 intel_crtc_disable_noatomic(&crtc->base);
15200 crtc->plane = plane;
15201 }
15202
15203 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15204 crtc->pipe == PIPE_A && !crtc->active) {
15205 /* BIOS forgot to enable pipe A, this mostly happens after
15206 * resume. Force-enable the pipe to fix this, the update_dpms
15207 * call below we restore the pipe to the right state, but leave
15208 * the required bits on. */
15209 intel_enable_pipe_a(dev);
15210 }
15211
15212 /* Adjust the state of the output pipe according to whether we
15213 * have active connectors/encoders. */
15214 enable = false;
15215 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15216 enable |= encoder->connectors_active;
15217
15218 if (!enable)
15219 intel_crtc_disable_noatomic(&crtc->base);
15220
15221 if (crtc->active != crtc->base.state->active) {
15222
15223 /* This can happen either due to bugs in the get_hw_state
15224 * functions or because of calls to intel_crtc_disable_noatomic,
15225 * or because the pipe is force-enabled due to the
15226 * pipe A quirk. */
15227 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15228 crtc->base.base.id,
15229 crtc->base.state->enable ? "enabled" : "disabled",
15230 crtc->active ? "enabled" : "disabled");
15231
15232 crtc->base.state->enable = crtc->active;
15233 crtc->base.state->active = crtc->active;
15234 crtc->base.enabled = crtc->active;
15235
15236 /* Because we only establish the connector -> encoder ->
15237 * crtc links if something is active, this means the
15238 * crtc is now deactivated. Break the links. connector
15239 * -> encoder links are only establish when things are
15240 * actually up, hence no need to break them. */
15241 WARN_ON(crtc->active);
15242
15243 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15244 WARN_ON(encoder->connectors_active);
15245 encoder->base.crtc = NULL;
15246 }
15247 }
15248
15249 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15250 /*
15251 * We start out with underrun reporting disabled to avoid races.
15252 * For correct bookkeeping mark this on active crtcs.
15253 *
15254 * Also on gmch platforms we dont have any hardware bits to
15255 * disable the underrun reporting. Which means we need to start
15256 * out with underrun reporting disabled also on inactive pipes,
15257 * since otherwise we'll complain about the garbage we read when
15258 * e.g. coming up after runtime pm.
15259 *
15260 * No protection against concurrent access is required - at
15261 * worst a fifo underrun happens which also sets this to false.
15262 */
15263 crtc->cpu_fifo_underrun_disabled = true;
15264 crtc->pch_fifo_underrun_disabled = true;
15265 }
15266 }
15267
15268 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15269 {
15270 struct intel_connector *connector;
15271 struct drm_device *dev = encoder->base.dev;
15272
15273 /* We need to check both for a crtc link (meaning that the
15274 * encoder is active and trying to read from a pipe) and the
15275 * pipe itself being active. */
15276 bool has_active_crtc = encoder->base.crtc &&
15277 to_intel_crtc(encoder->base.crtc)->active;
15278
15279 if (encoder->connectors_active && !has_active_crtc) {
15280 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15281 encoder->base.base.id,
15282 encoder->base.name);
15283
15284 /* Connector is active, but has no active pipe. This is
15285 * fallout from our resume register restoring. Disable
15286 * the encoder manually again. */
15287 if (encoder->base.crtc) {
15288 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15289 encoder->base.base.id,
15290 encoder->base.name);
15291 encoder->disable(encoder);
15292 if (encoder->post_disable)
15293 encoder->post_disable(encoder);
15294 }
15295 encoder->base.crtc = NULL;
15296 encoder->connectors_active = false;
15297
15298 /* Inconsistent output/port/pipe state happens presumably due to
15299 * a bug in one of the get_hw_state functions. Or someplace else
15300 * in our code, like the register restore mess on resume. Clamp
15301 * things to off as a safer default. */
15302 for_each_intel_connector(dev, connector) {
15303 if (connector->encoder != encoder)
15304 continue;
15305 connector->base.dpms = DRM_MODE_DPMS_OFF;
15306 connector->base.encoder = NULL;
15307 }
15308 }
15309 /* Enabled encoders without active connectors will be fixed in
15310 * the crtc fixup. */
15311 }
15312
15313 void i915_redisable_vga_power_on(struct drm_device *dev)
15314 {
15315 struct drm_i915_private *dev_priv = dev->dev_private;
15316 u32 vga_reg = i915_vgacntrl_reg(dev);
15317
15318 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15319 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15320 i915_disable_vga(dev);
15321 }
15322 }
15323
15324 void i915_redisable_vga(struct drm_device *dev)
15325 {
15326 struct drm_i915_private *dev_priv = dev->dev_private;
15327
15328 /* This function can be called both from intel_modeset_setup_hw_state or
15329 * at a very early point in our resume sequence, where the power well
15330 * structures are not yet restored. Since this function is at a very
15331 * paranoid "someone might have enabled VGA while we were not looking"
15332 * level, just check if the power well is enabled instead of trying to
15333 * follow the "don't touch the power well if we don't need it" policy
15334 * the rest of the driver uses. */
15335 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15336 return;
15337
15338 i915_redisable_vga_power_on(dev);
15339 }
15340
15341 static bool primary_get_hw_state(struct intel_crtc *crtc)
15342 {
15343 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15344
15345 if (!crtc->active)
15346 return false;
15347
15348 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15349 }
15350
15351 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15352 {
15353 struct drm_i915_private *dev_priv = dev->dev_private;
15354 enum pipe pipe;
15355 struct intel_crtc *crtc;
15356 struct intel_encoder *encoder;
15357 struct intel_connector *connector;
15358 int i;
15359
15360 for_each_intel_crtc(dev, crtc) {
15361 struct drm_plane *primary = crtc->base.primary;
15362 struct intel_plane_state *plane_state;
15363
15364 memset(crtc->config, 0, sizeof(*crtc->config));
15365 crtc->config->base.crtc = &crtc->base;
15366
15367 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15368
15369 crtc->active = dev_priv->display.get_pipe_config(crtc,
15370 crtc->config);
15371
15372 crtc->base.state->enable = crtc->active;
15373 crtc->base.state->active = crtc->active;
15374 crtc->base.enabled = crtc->active;
15375 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15376
15377 plane_state = to_intel_plane_state(primary->state);
15378 plane_state->visible = primary_get_hw_state(crtc);
15379
15380 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15381 crtc->base.base.id,
15382 crtc->active ? "enabled" : "disabled");
15383 }
15384
15385 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15386 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15387
15388 pll->on = pll->get_hw_state(dev_priv, pll,
15389 &pll->config.hw_state);
15390 pll->active = 0;
15391 pll->config.crtc_mask = 0;
15392 for_each_intel_crtc(dev, crtc) {
15393 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15394 pll->active++;
15395 pll->config.crtc_mask |= 1 << crtc->pipe;
15396 }
15397 }
15398
15399 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15400 pll->name, pll->config.crtc_mask, pll->on);
15401
15402 if (pll->config.crtc_mask)
15403 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15404 }
15405
15406 for_each_intel_encoder(dev, encoder) {
15407 pipe = 0;
15408
15409 if (encoder->get_hw_state(encoder, &pipe)) {
15410 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15411 encoder->base.crtc = &crtc->base;
15412 encoder->get_config(encoder, crtc->config);
15413 } else {
15414 encoder->base.crtc = NULL;
15415 }
15416
15417 encoder->connectors_active = false;
15418 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15419 encoder->base.base.id,
15420 encoder->base.name,
15421 encoder->base.crtc ? "enabled" : "disabled",
15422 pipe_name(pipe));
15423 }
15424
15425 for_each_intel_connector(dev, connector) {
15426 if (connector->get_hw_state(connector)) {
15427 connector->base.dpms = DRM_MODE_DPMS_ON;
15428 connector->encoder->connectors_active = true;
15429 connector->base.encoder = &connector->encoder->base;
15430 } else {
15431 connector->base.dpms = DRM_MODE_DPMS_OFF;
15432 connector->base.encoder = NULL;
15433 }
15434 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15435 connector->base.base.id,
15436 connector->base.name,
15437 connector->base.encoder ? "enabled" : "disabled");
15438 }
15439 }
15440
15441 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15442 * and i915 state tracking structures. */
15443 void intel_modeset_setup_hw_state(struct drm_device *dev,
15444 bool force_restore)
15445 {
15446 struct drm_i915_private *dev_priv = dev->dev_private;
15447 enum pipe pipe;
15448 struct intel_crtc *crtc;
15449 struct intel_encoder *encoder;
15450 int i;
15451
15452 intel_modeset_readout_hw_state(dev);
15453
15454 /*
15455 * Now that we have the config, copy it to each CRTC struct
15456 * Note that this could go away if we move to using crtc_config
15457 * checking everywhere.
15458 */
15459 for_each_intel_crtc(dev, crtc) {
15460 if (crtc->active && i915.fastboot) {
15461 intel_mode_from_pipe_config(&crtc->base.mode,
15462 crtc->config);
15463 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15464 crtc->base.base.id);
15465 drm_mode_debug_printmodeline(&crtc->base.mode);
15466 }
15467 }
15468
15469 /* HW state is read out, now we need to sanitize this mess. */
15470 for_each_intel_encoder(dev, encoder) {
15471 intel_sanitize_encoder(encoder);
15472 }
15473
15474 for_each_pipe(dev_priv, pipe) {
15475 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15476 intel_sanitize_crtc(crtc);
15477 intel_dump_pipe_config(crtc, crtc->config,
15478 "[setup_hw_state]");
15479 }
15480
15481 intel_modeset_update_connector_atomic_state(dev);
15482
15483 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15484 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15485
15486 if (!pll->on || pll->active)
15487 continue;
15488
15489 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15490
15491 pll->disable(dev_priv, pll);
15492 pll->on = false;
15493 }
15494
15495 if (IS_GEN9(dev))
15496 skl_wm_get_hw_state(dev);
15497 else if (HAS_PCH_SPLIT(dev))
15498 ilk_wm_get_hw_state(dev);
15499
15500 if (force_restore) {
15501 i915_redisable_vga(dev);
15502
15503 /*
15504 * We need to use raw interfaces for restoring state to avoid
15505 * checking (bogus) intermediate states.
15506 */
15507 for_each_pipe(dev_priv, pipe) {
15508 struct drm_crtc *crtc =
15509 dev_priv->pipe_to_crtc_mapping[pipe];
15510
15511 intel_crtc_restore_mode(crtc);
15512 }
15513 } else {
15514 intel_modeset_update_staged_output_state(dev);
15515 }
15516
15517 intel_modeset_check_state(dev);
15518 }
15519
15520 void intel_modeset_gem_init(struct drm_device *dev)
15521 {
15522 struct drm_i915_private *dev_priv = dev->dev_private;
15523 struct drm_crtc *c;
15524 struct drm_i915_gem_object *obj;
15525 int ret;
15526
15527 mutex_lock(&dev->struct_mutex);
15528 intel_init_gt_powersave(dev);
15529 mutex_unlock(&dev->struct_mutex);
15530
15531 /*
15532 * There may be no VBT; and if the BIOS enabled SSC we can
15533 * just keep using it to avoid unnecessary flicker. Whereas if the
15534 * BIOS isn't using it, don't assume it will work even if the VBT
15535 * indicates as much.
15536 */
15537 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15538 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15539 DREF_SSC1_ENABLE);
15540
15541 intel_modeset_init_hw(dev);
15542
15543 intel_setup_overlay(dev);
15544
15545 /*
15546 * Make sure any fbs we allocated at startup are properly
15547 * pinned & fenced. When we do the allocation it's too early
15548 * for this.
15549 */
15550 for_each_crtc(dev, c) {
15551 obj = intel_fb_obj(c->primary->fb);
15552 if (obj == NULL)
15553 continue;
15554
15555 mutex_lock(&dev->struct_mutex);
15556 ret = intel_pin_and_fence_fb_obj(c->primary,
15557 c->primary->fb,
15558 c->primary->state,
15559 NULL);
15560 mutex_unlock(&dev->struct_mutex);
15561 if (ret) {
15562 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15563 to_intel_crtc(c)->pipe);
15564 drm_framebuffer_unreference(c->primary->fb);
15565 c->primary->fb = NULL;
15566 c->primary->crtc = c->primary->state->crtc = NULL;
15567 update_state_fb(c->primary);
15568 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15569 }
15570 }
15571
15572 intel_backlight_register(dev);
15573 }
15574
15575 void intel_connector_unregister(struct intel_connector *intel_connector)
15576 {
15577 struct drm_connector *connector = &intel_connector->base;
15578
15579 intel_panel_destroy_backlight(connector);
15580 drm_connector_unregister(connector);
15581 }
15582
15583 void intel_modeset_cleanup(struct drm_device *dev)
15584 {
15585 struct drm_i915_private *dev_priv = dev->dev_private;
15586 struct drm_connector *connector;
15587
15588 intel_disable_gt_powersave(dev);
15589
15590 intel_backlight_unregister(dev);
15591
15592 /*
15593 * Interrupts and polling as the first thing to avoid creating havoc.
15594 * Too much stuff here (turning of connectors, ...) would
15595 * experience fancy races otherwise.
15596 */
15597 intel_irq_uninstall(dev_priv);
15598
15599 /*
15600 * Due to the hpd irq storm handling the hotplug work can re-arm the
15601 * poll handlers. Hence disable polling after hpd handling is shut down.
15602 */
15603 drm_kms_helper_poll_fini(dev);
15604
15605 mutex_lock(&dev->struct_mutex);
15606
15607 intel_unregister_dsm_handler();
15608
15609 intel_fbc_disable(dev);
15610
15611 mutex_unlock(&dev->struct_mutex);
15612
15613 /* flush any delayed tasks or pending work */
15614 flush_scheduled_work();
15615
15616 /* destroy the backlight and sysfs files before encoders/connectors */
15617 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15618 struct intel_connector *intel_connector;
15619
15620 intel_connector = to_intel_connector(connector);
15621 intel_connector->unregister(intel_connector);
15622 }
15623
15624 drm_mode_config_cleanup(dev);
15625
15626 intel_cleanup_overlay(dev);
15627
15628 mutex_lock(&dev->struct_mutex);
15629 intel_cleanup_gt_powersave(dev);
15630 mutex_unlock(&dev->struct_mutex);
15631 }
15632
15633 /*
15634 * Return which encoder is currently attached for connector.
15635 */
15636 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15637 {
15638 return &intel_attached_encoder(connector)->base;
15639 }
15640
15641 void intel_connector_attach_encoder(struct intel_connector *connector,
15642 struct intel_encoder *encoder)
15643 {
15644 connector->encoder = encoder;
15645 drm_mode_connector_attach_encoder(&connector->base,
15646 &encoder->base);
15647 }
15648
15649 /*
15650 * set vga decode state - true == enable VGA decode
15651 */
15652 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15653 {
15654 struct drm_i915_private *dev_priv = dev->dev_private;
15655 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15656 u16 gmch_ctrl;
15657
15658 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15659 DRM_ERROR("failed to read control word\n");
15660 return -EIO;
15661 }
15662
15663 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15664 return 0;
15665
15666 if (state)
15667 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15668 else
15669 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15670
15671 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15672 DRM_ERROR("failed to write control word\n");
15673 return -EIO;
15674 }
15675
15676 return 0;
15677 }
15678
15679 struct intel_display_error_state {
15680
15681 u32 power_well_driver;
15682
15683 int num_transcoders;
15684
15685 struct intel_cursor_error_state {
15686 u32 control;
15687 u32 position;
15688 u32 base;
15689 u32 size;
15690 } cursor[I915_MAX_PIPES];
15691
15692 struct intel_pipe_error_state {
15693 bool power_domain_on;
15694 u32 source;
15695 u32 stat;
15696 } pipe[I915_MAX_PIPES];
15697
15698 struct intel_plane_error_state {
15699 u32 control;
15700 u32 stride;
15701 u32 size;
15702 u32 pos;
15703 u32 addr;
15704 u32 surface;
15705 u32 tile_offset;
15706 } plane[I915_MAX_PIPES];
15707
15708 struct intel_transcoder_error_state {
15709 bool power_domain_on;
15710 enum transcoder cpu_transcoder;
15711
15712 u32 conf;
15713
15714 u32 htotal;
15715 u32 hblank;
15716 u32 hsync;
15717 u32 vtotal;
15718 u32 vblank;
15719 u32 vsync;
15720 } transcoder[4];
15721 };
15722
15723 struct intel_display_error_state *
15724 intel_display_capture_error_state(struct drm_device *dev)
15725 {
15726 struct drm_i915_private *dev_priv = dev->dev_private;
15727 struct intel_display_error_state *error;
15728 int transcoders[] = {
15729 TRANSCODER_A,
15730 TRANSCODER_B,
15731 TRANSCODER_C,
15732 TRANSCODER_EDP,
15733 };
15734 int i;
15735
15736 if (INTEL_INFO(dev)->num_pipes == 0)
15737 return NULL;
15738
15739 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15740 if (error == NULL)
15741 return NULL;
15742
15743 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15744 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15745
15746 for_each_pipe(dev_priv, i) {
15747 error->pipe[i].power_domain_on =
15748 __intel_display_power_is_enabled(dev_priv,
15749 POWER_DOMAIN_PIPE(i));
15750 if (!error->pipe[i].power_domain_on)
15751 continue;
15752
15753 error->cursor[i].control = I915_READ(CURCNTR(i));
15754 error->cursor[i].position = I915_READ(CURPOS(i));
15755 error->cursor[i].base = I915_READ(CURBASE(i));
15756
15757 error->plane[i].control = I915_READ(DSPCNTR(i));
15758 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15759 if (INTEL_INFO(dev)->gen <= 3) {
15760 error->plane[i].size = I915_READ(DSPSIZE(i));
15761 error->plane[i].pos = I915_READ(DSPPOS(i));
15762 }
15763 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15764 error->plane[i].addr = I915_READ(DSPADDR(i));
15765 if (INTEL_INFO(dev)->gen >= 4) {
15766 error->plane[i].surface = I915_READ(DSPSURF(i));
15767 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15768 }
15769
15770 error->pipe[i].source = I915_READ(PIPESRC(i));
15771
15772 if (HAS_GMCH_DISPLAY(dev))
15773 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15774 }
15775
15776 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15777 if (HAS_DDI(dev_priv->dev))
15778 error->num_transcoders++; /* Account for eDP. */
15779
15780 for (i = 0; i < error->num_transcoders; i++) {
15781 enum transcoder cpu_transcoder = transcoders[i];
15782
15783 error->transcoder[i].power_domain_on =
15784 __intel_display_power_is_enabled(dev_priv,
15785 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15786 if (!error->transcoder[i].power_domain_on)
15787 continue;
15788
15789 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15790
15791 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15792 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15793 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15794 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15795 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15796 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15797 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15798 }
15799
15800 return error;
15801 }
15802
15803 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15804
15805 void
15806 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15807 struct drm_device *dev,
15808 struct intel_display_error_state *error)
15809 {
15810 struct drm_i915_private *dev_priv = dev->dev_private;
15811 int i;
15812
15813 if (!error)
15814 return;
15815
15816 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15817 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15818 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15819 error->power_well_driver);
15820 for_each_pipe(dev_priv, i) {
15821 err_printf(m, "Pipe [%d]:\n", i);
15822 err_printf(m, " Power: %s\n",
15823 error->pipe[i].power_domain_on ? "on" : "off");
15824 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15825 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15826
15827 err_printf(m, "Plane [%d]:\n", i);
15828 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15829 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15830 if (INTEL_INFO(dev)->gen <= 3) {
15831 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15832 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15833 }
15834 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15835 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15836 if (INTEL_INFO(dev)->gen >= 4) {
15837 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15838 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15839 }
15840
15841 err_printf(m, "Cursor [%d]:\n", i);
15842 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15843 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15844 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15845 }
15846
15847 for (i = 0; i < error->num_transcoders; i++) {
15848 err_printf(m, "CPU transcoder: %c\n",
15849 transcoder_name(error->transcoder[i].cpu_transcoder));
15850 err_printf(m, " Power: %s\n",
15851 error->transcoder[i].power_domain_on ? "on" : "off");
15852 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15853 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15854 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15855 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15856 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15857 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15858 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15859 }
15860 }
15861
15862 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15863 {
15864 struct intel_crtc *crtc;
15865
15866 for_each_intel_crtc(dev, crtc) {
15867 struct intel_unpin_work *work;
15868
15869 spin_lock_irq(&dev->event_lock);
15870
15871 work = crtc->unpin_work;
15872
15873 if (work && work->event &&
15874 work->event->base.file_priv == file) {
15875 kfree(work->event);
15876 work->event = NULL;
15877 }
15878
15879 spin_unlock_irq(&dev->event_lock);
15880 }
15881 }
Linux kernel - Deliverables
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