2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats
[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats
[] = {
62 DRM_FORMAT_XRGB2101010
,
63 DRM_FORMAT_XBGR2101010
,
66 static const uint32_t skl_primary_formats
[] = {
73 DRM_FORMAT_XRGB2101010
,
74 DRM_FORMAT_XBGR2101010
,
78 static const uint32_t intel_cursor_formats
[] = {
82 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
84 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
85 struct intel_crtc_state
*pipe_config
);
86 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
87 struct intel_crtc_state
*pipe_config
);
89 static int intel_set_mode(struct drm_crtc
*crtc
,
90 struct drm_atomic_state
*state
);
91 static int intel_framebuffer_init(struct drm_device
*dev
,
92 struct intel_framebuffer
*ifb
,
93 struct drm_mode_fb_cmd2
*mode_cmd
,
94 struct drm_i915_gem_object
*obj
);
95 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
96 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
98 struct intel_link_m_n
*m_n
,
99 struct intel_link_m_n
*m2_n2
);
100 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
101 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
102 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
103 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
104 const struct intel_crtc_state
*pipe_config
);
105 static void chv_prepare_pll(struct intel_crtc
*crtc
,
106 const struct intel_crtc_state
*pipe_config
);
107 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
);
108 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
);
109 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
110 struct intel_crtc_state
*crtc_state
);
111 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
113 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
);
114 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
);
116 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
118 if (!connector
->mst_port
)
119 return connector
->encoder
;
121 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
130 int p2_slow
, p2_fast
;
133 typedef struct intel_limit intel_limit_t
;
135 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
140 intel_pch_rawclk(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
144 WARN_ON(!HAS_PCH_SPLIT(dev
));
146 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
149 static inline u32
/* units of 100MHz */
150 intel_fdi_link_freq(struct drm_device
*dev
)
153 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
154 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
159 static const intel_limit_t intel_limits_i8xx_dac
= {
160 .dot
= { .min
= 25000, .max
= 350000 },
161 .vco
= { .min
= 908000, .max
= 1512000 },
162 .n
= { .min
= 2, .max
= 16 },
163 .m
= { .min
= 96, .max
= 140 },
164 .m1
= { .min
= 18, .max
= 26 },
165 .m2
= { .min
= 6, .max
= 16 },
166 .p
= { .min
= 4, .max
= 128 },
167 .p1
= { .min
= 2, .max
= 33 },
168 .p2
= { .dot_limit
= 165000,
169 .p2_slow
= 4, .p2_fast
= 2 },
172 static const intel_limit_t intel_limits_i8xx_dvo
= {
173 .dot
= { .min
= 25000, .max
= 350000 },
174 .vco
= { .min
= 908000, .max
= 1512000 },
175 .n
= { .min
= 2, .max
= 16 },
176 .m
= { .min
= 96, .max
= 140 },
177 .m1
= { .min
= 18, .max
= 26 },
178 .m2
= { .min
= 6, .max
= 16 },
179 .p
= { .min
= 4, .max
= 128 },
180 .p1
= { .min
= 2, .max
= 33 },
181 .p2
= { .dot_limit
= 165000,
182 .p2_slow
= 4, .p2_fast
= 4 },
185 static const intel_limit_t intel_limits_i8xx_lvds
= {
186 .dot
= { .min
= 25000, .max
= 350000 },
187 .vco
= { .min
= 908000, .max
= 1512000 },
188 .n
= { .min
= 2, .max
= 16 },
189 .m
= { .min
= 96, .max
= 140 },
190 .m1
= { .min
= 18, .max
= 26 },
191 .m2
= { .min
= 6, .max
= 16 },
192 .p
= { .min
= 4, .max
= 128 },
193 .p1
= { .min
= 1, .max
= 6 },
194 .p2
= { .dot_limit
= 165000,
195 .p2_slow
= 14, .p2_fast
= 7 },
198 static const intel_limit_t intel_limits_i9xx_sdvo
= {
199 .dot
= { .min
= 20000, .max
= 400000 },
200 .vco
= { .min
= 1400000, .max
= 2800000 },
201 .n
= { .min
= 1, .max
= 6 },
202 .m
= { .min
= 70, .max
= 120 },
203 .m1
= { .min
= 8, .max
= 18 },
204 .m2
= { .min
= 3, .max
= 7 },
205 .p
= { .min
= 5, .max
= 80 },
206 .p1
= { .min
= 1, .max
= 8 },
207 .p2
= { .dot_limit
= 200000,
208 .p2_slow
= 10, .p2_fast
= 5 },
211 static const intel_limit_t intel_limits_i9xx_lvds
= {
212 .dot
= { .min
= 20000, .max
= 400000 },
213 .vco
= { .min
= 1400000, .max
= 2800000 },
214 .n
= { .min
= 1, .max
= 6 },
215 .m
= { .min
= 70, .max
= 120 },
216 .m1
= { .min
= 8, .max
= 18 },
217 .m2
= { .min
= 3, .max
= 7 },
218 .p
= { .min
= 7, .max
= 98 },
219 .p1
= { .min
= 1, .max
= 8 },
220 .p2
= { .dot_limit
= 112000,
221 .p2_slow
= 14, .p2_fast
= 7 },
225 static const intel_limit_t intel_limits_g4x_sdvo
= {
226 .dot
= { .min
= 25000, .max
= 270000 },
227 .vco
= { .min
= 1750000, .max
= 3500000},
228 .n
= { .min
= 1, .max
= 4 },
229 .m
= { .min
= 104, .max
= 138 },
230 .m1
= { .min
= 17, .max
= 23 },
231 .m2
= { .min
= 5, .max
= 11 },
232 .p
= { .min
= 10, .max
= 30 },
233 .p1
= { .min
= 1, .max
= 3},
234 .p2
= { .dot_limit
= 270000,
240 static const intel_limit_t intel_limits_g4x_hdmi
= {
241 .dot
= { .min
= 22000, .max
= 400000 },
242 .vco
= { .min
= 1750000, .max
= 3500000},
243 .n
= { .min
= 1, .max
= 4 },
244 .m
= { .min
= 104, .max
= 138 },
245 .m1
= { .min
= 16, .max
= 23 },
246 .m2
= { .min
= 5, .max
= 11 },
247 .p
= { .min
= 5, .max
= 80 },
248 .p1
= { .min
= 1, .max
= 8},
249 .p2
= { .dot_limit
= 165000,
250 .p2_slow
= 10, .p2_fast
= 5 },
253 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
254 .dot
= { .min
= 20000, .max
= 115000 },
255 .vco
= { .min
= 1750000, .max
= 3500000 },
256 .n
= { .min
= 1, .max
= 3 },
257 .m
= { .min
= 104, .max
= 138 },
258 .m1
= { .min
= 17, .max
= 23 },
259 .m2
= { .min
= 5, .max
= 11 },
260 .p
= { .min
= 28, .max
= 112 },
261 .p1
= { .min
= 2, .max
= 8 },
262 .p2
= { .dot_limit
= 0,
263 .p2_slow
= 14, .p2_fast
= 14
267 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
268 .dot
= { .min
= 80000, .max
= 224000 },
269 .vco
= { .min
= 1750000, .max
= 3500000 },
270 .n
= { .min
= 1, .max
= 3 },
271 .m
= { .min
= 104, .max
= 138 },
272 .m1
= { .min
= 17, .max
= 23 },
273 .m2
= { .min
= 5, .max
= 11 },
274 .p
= { .min
= 14, .max
= 42 },
275 .p1
= { .min
= 2, .max
= 6 },
276 .p2
= { .dot_limit
= 0,
277 .p2_slow
= 7, .p2_fast
= 7
281 static const intel_limit_t intel_limits_pineview_sdvo
= {
282 .dot
= { .min
= 20000, .max
= 400000},
283 .vco
= { .min
= 1700000, .max
= 3500000 },
284 /* Pineview's Ncounter is a ring counter */
285 .n
= { .min
= 3, .max
= 6 },
286 .m
= { .min
= 2, .max
= 256 },
287 /* Pineview only has one combined m divider, which we treat as m2. */
288 .m1
= { .min
= 0, .max
= 0 },
289 .m2
= { .min
= 0, .max
= 254 },
290 .p
= { .min
= 5, .max
= 80 },
291 .p1
= { .min
= 1, .max
= 8 },
292 .p2
= { .dot_limit
= 200000,
293 .p2_slow
= 10, .p2_fast
= 5 },
296 static const intel_limit_t intel_limits_pineview_lvds
= {
297 .dot
= { .min
= 20000, .max
= 400000 },
298 .vco
= { .min
= 1700000, .max
= 3500000 },
299 .n
= { .min
= 3, .max
= 6 },
300 .m
= { .min
= 2, .max
= 256 },
301 .m1
= { .min
= 0, .max
= 0 },
302 .m2
= { .min
= 0, .max
= 254 },
303 .p
= { .min
= 7, .max
= 112 },
304 .p1
= { .min
= 1, .max
= 8 },
305 .p2
= { .dot_limit
= 112000,
306 .p2_slow
= 14, .p2_fast
= 14 },
309 /* Ironlake / Sandybridge
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
314 static const intel_limit_t intel_limits_ironlake_dac
= {
315 .dot
= { .min
= 25000, .max
= 350000 },
316 .vco
= { .min
= 1760000, .max
= 3510000 },
317 .n
= { .min
= 1, .max
= 5 },
318 .m
= { .min
= 79, .max
= 127 },
319 .m1
= { .min
= 12, .max
= 22 },
320 .m2
= { .min
= 5, .max
= 9 },
321 .p
= { .min
= 5, .max
= 80 },
322 .p1
= { .min
= 1, .max
= 8 },
323 .p2
= { .dot_limit
= 225000,
324 .p2_slow
= 10, .p2_fast
= 5 },
327 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
328 .dot
= { .min
= 25000, .max
= 350000 },
329 .vco
= { .min
= 1760000, .max
= 3510000 },
330 .n
= { .min
= 1, .max
= 3 },
331 .m
= { .min
= 79, .max
= 118 },
332 .m1
= { .min
= 12, .max
= 22 },
333 .m2
= { .min
= 5, .max
= 9 },
334 .p
= { .min
= 28, .max
= 112 },
335 .p1
= { .min
= 2, .max
= 8 },
336 .p2
= { .dot_limit
= 225000,
337 .p2_slow
= 14, .p2_fast
= 14 },
340 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
341 .dot
= { .min
= 25000, .max
= 350000 },
342 .vco
= { .min
= 1760000, .max
= 3510000 },
343 .n
= { .min
= 1, .max
= 3 },
344 .m
= { .min
= 79, .max
= 127 },
345 .m1
= { .min
= 12, .max
= 22 },
346 .m2
= { .min
= 5, .max
= 9 },
347 .p
= { .min
= 14, .max
= 56 },
348 .p1
= { .min
= 2, .max
= 8 },
349 .p2
= { .dot_limit
= 225000,
350 .p2_slow
= 7, .p2_fast
= 7 },
353 /* LVDS 100mhz refclk limits. */
354 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
355 .dot
= { .min
= 25000, .max
= 350000 },
356 .vco
= { .min
= 1760000, .max
= 3510000 },
357 .n
= { .min
= 1, .max
= 2 },
358 .m
= { .min
= 79, .max
= 126 },
359 .m1
= { .min
= 12, .max
= 22 },
360 .m2
= { .min
= 5, .max
= 9 },
361 .p
= { .min
= 28, .max
= 112 },
362 .p1
= { .min
= 2, .max
= 8 },
363 .p2
= { .dot_limit
= 225000,
364 .p2_slow
= 14, .p2_fast
= 14 },
367 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
368 .dot
= { .min
= 25000, .max
= 350000 },
369 .vco
= { .min
= 1760000, .max
= 3510000 },
370 .n
= { .min
= 1, .max
= 3 },
371 .m
= { .min
= 79, .max
= 126 },
372 .m1
= { .min
= 12, .max
= 22 },
373 .m2
= { .min
= 5, .max
= 9 },
374 .p
= { .min
= 14, .max
= 42 },
375 .p1
= { .min
= 2, .max
= 6 },
376 .p2
= { .dot_limit
= 225000,
377 .p2_slow
= 7, .p2_fast
= 7 },
380 static const intel_limit_t intel_limits_vlv
= {
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
387 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
388 .vco
= { .min
= 4000000, .max
= 6000000 },
389 .n
= { .min
= 1, .max
= 7 },
390 .m1
= { .min
= 2, .max
= 3 },
391 .m2
= { .min
= 11, .max
= 156 },
392 .p1
= { .min
= 2, .max
= 3 },
393 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
396 static const intel_limit_t intel_limits_chv
= {
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
403 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
404 .vco
= { .min
= 4800000, .max
= 6480000 },
405 .n
= { .min
= 1, .max
= 1 },
406 .m1
= { .min
= 2, .max
= 2 },
407 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
408 .p1
= { .min
= 2, .max
= 4 },
409 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
412 static const intel_limit_t intel_limits_bxt
= {
413 /* FIXME: find real dot limits */
414 .dot
= { .min
= 0, .max
= INT_MAX
},
415 .vco
= { .min
= 4800000, .max
= 6480000 },
416 .n
= { .min
= 1, .max
= 1 },
417 .m1
= { .min
= 2, .max
= 2 },
418 /* FIXME: find real m2 limits */
419 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
420 .p1
= { .min
= 2, .max
= 4 },
421 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
424 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
426 clock
->m
= clock
->m1
* clock
->m2
;
427 clock
->p
= clock
->p1
* clock
->p2
;
428 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
430 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
431 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
435 * Returns whether any output on the specified pipe is of the specified type
437 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
439 struct drm_device
*dev
= crtc
->base
.dev
;
440 struct intel_encoder
*encoder
;
442 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
443 if (encoder
->type
== type
)
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
455 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
458 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
459 struct drm_connector
*connector
;
460 struct drm_connector_state
*connector_state
;
461 struct intel_encoder
*encoder
;
462 int i
, num_connectors
= 0;
464 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
465 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
470 encoder
= to_intel_encoder(connector_state
->best_encoder
);
471 if (encoder
->type
== type
)
475 WARN_ON(num_connectors
== 0);
480 static const intel_limit_t
*
481 intel_ironlake_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
483 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
484 const intel_limit_t
*limit
;
486 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
487 if (intel_is_dual_link_lvds(dev
)) {
488 if (refclk
== 100000)
489 limit
= &intel_limits_ironlake_dual_lvds_100m
;
491 limit
= &intel_limits_ironlake_dual_lvds
;
493 if (refclk
== 100000)
494 limit
= &intel_limits_ironlake_single_lvds_100m
;
496 limit
= &intel_limits_ironlake_single_lvds
;
499 limit
= &intel_limits_ironlake_dac
;
504 static const intel_limit_t
*
505 intel_g4x_limit(struct intel_crtc_state
*crtc_state
)
507 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
508 const intel_limit_t
*limit
;
510 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
511 if (intel_is_dual_link_lvds(dev
))
512 limit
= &intel_limits_g4x_dual_channel_lvds
;
514 limit
= &intel_limits_g4x_single_channel_lvds
;
515 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
516 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
517 limit
= &intel_limits_g4x_hdmi
;
518 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
519 limit
= &intel_limits_g4x_sdvo
;
520 } else /* The option is for other outputs */
521 limit
= &intel_limits_i9xx_sdvo
;
526 static const intel_limit_t
*
527 intel_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
529 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
530 const intel_limit_t
*limit
;
533 limit
= &intel_limits_bxt
;
534 else if (HAS_PCH_SPLIT(dev
))
535 limit
= intel_ironlake_limit(crtc_state
, refclk
);
536 else if (IS_G4X(dev
)) {
537 limit
= intel_g4x_limit(crtc_state
);
538 } else if (IS_PINEVIEW(dev
)) {
539 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
540 limit
= &intel_limits_pineview_lvds
;
542 limit
= &intel_limits_pineview_sdvo
;
543 } else if (IS_CHERRYVIEW(dev
)) {
544 limit
= &intel_limits_chv
;
545 } else if (IS_VALLEYVIEW(dev
)) {
546 limit
= &intel_limits_vlv
;
547 } else if (!IS_GEN2(dev
)) {
548 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
549 limit
= &intel_limits_i9xx_lvds
;
551 limit
= &intel_limits_i9xx_sdvo
;
553 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
554 limit
= &intel_limits_i8xx_lvds
;
555 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
556 limit
= &intel_limits_i8xx_dvo
;
558 limit
= &intel_limits_i8xx_dac
;
563 /* m1 is reserved as 0 in Pineview, n is a ring counter */
564 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
566 clock
->m
= clock
->m2
+ 2;
567 clock
->p
= clock
->p1
* clock
->p2
;
568 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
570 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
571 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
574 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
576 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
579 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
581 clock
->m
= i9xx_dpll_compute_m(clock
);
582 clock
->p
= clock
->p1
* clock
->p2
;
583 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
585 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
586 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
589 static void chv_clock(int refclk
, intel_clock_t
*clock
)
591 clock
->m
= clock
->m1
* clock
->m2
;
592 clock
->p
= clock
->p1
* clock
->p2
;
593 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
595 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
597 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
600 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
606 static bool intel_PLL_is_valid(struct drm_device
*dev
,
607 const intel_limit_t
*limit
,
608 const intel_clock_t
*clock
)
610 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
611 INTELPllInvalid("n out of range\n");
612 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
613 INTELPllInvalid("p1 out of range\n");
614 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
615 INTELPllInvalid("m2 out of range\n");
616 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
617 INTELPllInvalid("m1 out of range\n");
619 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
))
620 if (clock
->m1
<= clock
->m2
)
621 INTELPllInvalid("m1 <= m2\n");
623 if (!IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
)) {
624 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
625 INTELPllInvalid("p out of range\n");
626 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
627 INTELPllInvalid("m out of range\n");
630 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
631 INTELPllInvalid("vco out of range\n");
632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
635 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
636 INTELPllInvalid("dot out of range\n");
642 i9xx_find_best_dpll(const intel_limit_t
*limit
,
643 struct intel_crtc_state
*crtc_state
,
644 int target
, int refclk
, intel_clock_t
*match_clock
,
645 intel_clock_t
*best_clock
)
647 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
648 struct drm_device
*dev
= crtc
->base
.dev
;
652 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
658 if (intel_is_dual_link_lvds(dev
))
659 clock
.p2
= limit
->p2
.p2_fast
;
661 clock
.p2
= limit
->p2
.p2_slow
;
663 if (target
< limit
->p2
.dot_limit
)
664 clock
.p2
= limit
->p2
.p2_slow
;
666 clock
.p2
= limit
->p2
.p2_fast
;
669 memset(best_clock
, 0, sizeof(*best_clock
));
671 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
673 for (clock
.m2
= limit
->m2
.min
;
674 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
675 if (clock
.m2
>= clock
.m1
)
677 for (clock
.n
= limit
->n
.min
;
678 clock
.n
<= limit
->n
.max
; clock
.n
++) {
679 for (clock
.p1
= limit
->p1
.min
;
680 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
683 i9xx_clock(refclk
, &clock
);
684 if (!intel_PLL_is_valid(dev
, limit
,
688 clock
.p
!= match_clock
->p
)
691 this_err
= abs(clock
.dot
- target
);
692 if (this_err
< err
) {
701 return (err
!= target
);
705 pnv_find_best_dpll(const intel_limit_t
*limit
,
706 struct intel_crtc_state
*crtc_state
,
707 int target
, int refclk
, intel_clock_t
*match_clock
,
708 intel_clock_t
*best_clock
)
710 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
711 struct drm_device
*dev
= crtc
->base
.dev
;
715 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
721 if (intel_is_dual_link_lvds(dev
))
722 clock
.p2
= limit
->p2
.p2_fast
;
724 clock
.p2
= limit
->p2
.p2_slow
;
726 if (target
< limit
->p2
.dot_limit
)
727 clock
.p2
= limit
->p2
.p2_slow
;
729 clock
.p2
= limit
->p2
.p2_fast
;
732 memset(best_clock
, 0, sizeof(*best_clock
));
734 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
736 for (clock
.m2
= limit
->m2
.min
;
737 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
738 for (clock
.n
= limit
->n
.min
;
739 clock
.n
<= limit
->n
.max
; clock
.n
++) {
740 for (clock
.p1
= limit
->p1
.min
;
741 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
744 pineview_clock(refclk
, &clock
);
745 if (!intel_PLL_is_valid(dev
, limit
,
749 clock
.p
!= match_clock
->p
)
752 this_err
= abs(clock
.dot
- target
);
753 if (this_err
< err
) {
762 return (err
!= target
);
766 g4x_find_best_dpll(const intel_limit_t
*limit
,
767 struct intel_crtc_state
*crtc_state
,
768 int target
, int refclk
, intel_clock_t
*match_clock
,
769 intel_clock_t
*best_clock
)
771 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
772 struct drm_device
*dev
= crtc
->base
.dev
;
776 /* approximately equals target * 0.00585 */
777 int err_most
= (target
>> 8) + (target
>> 9);
780 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
781 if (intel_is_dual_link_lvds(dev
))
782 clock
.p2
= limit
->p2
.p2_fast
;
784 clock
.p2
= limit
->p2
.p2_slow
;
786 if (target
< limit
->p2
.dot_limit
)
787 clock
.p2
= limit
->p2
.p2_slow
;
789 clock
.p2
= limit
->p2
.p2_fast
;
792 memset(best_clock
, 0, sizeof(*best_clock
));
793 max_n
= limit
->n
.max
;
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
796 /* based on hardware requirement, prefere larger m1,m2 */
797 for (clock
.m1
= limit
->m1
.max
;
798 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
799 for (clock
.m2
= limit
->m2
.max
;
800 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
801 for (clock
.p1
= limit
->p1
.max
;
802 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
805 i9xx_clock(refclk
, &clock
);
806 if (!intel_PLL_is_valid(dev
, limit
,
810 this_err
= abs(clock
.dot
- target
);
811 if (this_err
< err_most
) {
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
828 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
829 const intel_clock_t
*calculated_clock
,
830 const intel_clock_t
*best_clock
,
831 unsigned int best_error_ppm
,
832 unsigned int *error_ppm
)
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
838 if (IS_CHERRYVIEW(dev
)) {
841 return calculated_clock
->p
> best_clock
->p
;
844 if (WARN_ON_ONCE(!target_freq
))
847 *error_ppm
= div_u64(1000000ULL *
848 abs(target_freq
- calculated_clock
->dot
),
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
855 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
861 return *error_ppm
+ 10 < best_error_ppm
;
865 vlv_find_best_dpll(const intel_limit_t
*limit
,
866 struct intel_crtc_state
*crtc_state
,
867 int target
, int refclk
, intel_clock_t
*match_clock
,
868 intel_clock_t
*best_clock
)
870 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
871 struct drm_device
*dev
= crtc
->base
.dev
;
873 unsigned int bestppm
= 1000000;
874 /* min update 19.2 MHz */
875 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
878 target
*= 5; /* fast clock */
880 memset(best_clock
, 0, sizeof(*best_clock
));
882 /* based on hardware requirement, prefer smaller n to precision */
883 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
884 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
885 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
886 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
887 clock
.p
= clock
.p1
* clock
.p2
;
888 /* based on hardware requirement, prefer bigger m1,m2 values */
889 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
892 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
895 vlv_clock(refclk
, &clock
);
897 if (!intel_PLL_is_valid(dev
, limit
,
901 if (!vlv_PLL_is_optimal(dev
, target
,
919 chv_find_best_dpll(const intel_limit_t
*limit
,
920 struct intel_crtc_state
*crtc_state
,
921 int target
, int refclk
, intel_clock_t
*match_clock
,
922 intel_clock_t
*best_clock
)
924 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
925 struct drm_device
*dev
= crtc
->base
.dev
;
926 unsigned int best_error_ppm
;
931 memset(best_clock
, 0, sizeof(*best_clock
));
932 best_error_ppm
= 1000000;
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
939 clock
.n
= 1, clock
.m1
= 2;
940 target
*= 5; /* fast clock */
942 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
943 for (clock
.p2
= limit
->p2
.p2_fast
;
944 clock
.p2
>= limit
->p2
.p2_slow
;
945 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
946 unsigned int error_ppm
;
948 clock
.p
= clock
.p1
* clock
.p2
;
950 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
951 clock
.n
) << 22, refclk
* clock
.m1
);
953 if (m2
> INT_MAX
/clock
.m1
)
958 chv_clock(refclk
, &clock
);
960 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
963 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
964 best_error_ppm
, &error_ppm
))
968 best_error_ppm
= error_ppm
;
976 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
977 intel_clock_t
*best_clock
)
979 int refclk
= i9xx_get_refclk(crtc_state
, 0);
981 return chv_find_best_dpll(intel_limit(crtc_state
, refclk
), crtc_state
,
982 target_clock
, refclk
, NULL
, best_clock
);
985 bool intel_crtc_active(struct drm_crtc
*crtc
)
987 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
992 * We can ditch the adjusted_mode.crtc_clock check as soon
993 * as Haswell has gained clock readout/fastboot support.
995 * We can ditch the crtc->primary->fb check as soon as we can
996 * properly reconstruct framebuffers.
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1002 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
1003 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1006 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1009 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1010 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1012 return intel_crtc
->config
->cpu_transcoder
;
1015 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1018 u32 reg
= PIPEDSL(pipe
);
1023 line_mask
= DSL_LINEMASK_GEN2
;
1025 line_mask
= DSL_LINEMASK_GEN3
;
1027 line1
= I915_READ(reg
) & line_mask
;
1029 line2
= I915_READ(reg
) & line_mask
;
1031 return line1
== line2
;
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
1036 * @crtc: crtc whose pipe to wait for
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
1050 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1052 struct drm_device
*dev
= crtc
->base
.dev
;
1053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1054 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1055 enum pipe pipe
= crtc
->pipe
;
1057 if (INTEL_INFO(dev
)->gen
>= 4) {
1058 int reg
= PIPECONF(cpu_transcoder
);
1060 /* Wait for the Pipe State to go off */
1061 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1063 WARN(1, "pipe_off wait timed out\n");
1065 /* Wait for the display line to settle */
1066 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1067 WARN(1, "pipe_off wait timed out\n");
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1076 * Returns true if @port is connected, false otherwise.
1078 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1079 struct intel_digital_port
*port
)
1083 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1084 switch (port
->port
) {
1086 bit
= SDE_PORTB_HOTPLUG
;
1089 bit
= SDE_PORTC_HOTPLUG
;
1092 bit
= SDE_PORTD_HOTPLUG
;
1098 switch (port
->port
) {
1100 bit
= SDE_PORTB_HOTPLUG_CPT
;
1103 bit
= SDE_PORTC_HOTPLUG_CPT
;
1106 bit
= SDE_PORTD_HOTPLUG_CPT
;
1113 return I915_READ(SDEISR
) & bit
;
1116 static const char *state_string(bool enabled
)
1118 return enabled
? "on" : "off";
1121 /* Only for pre-ILK configs */
1122 void assert_pll(struct drm_i915_private
*dev_priv
,
1123 enum pipe pipe
, bool state
)
1130 val
= I915_READ(reg
);
1131 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1132 I915_STATE_WARN(cur_state
!= state
,
1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state
), state_string(cur_state
));
1137 /* XXX: the dsi pll is shared between MIPI DSI ports */
1138 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1143 mutex_lock(&dev_priv
->sb_lock
);
1144 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1145 mutex_unlock(&dev_priv
->sb_lock
);
1147 cur_state
= val
& DSI_PLL_VCO_EN
;
1148 I915_STATE_WARN(cur_state
!= state
,
1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state
), state_string(cur_state
));
1152 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1155 struct intel_shared_dpll
*
1156 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1158 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1160 if (crtc
->config
->shared_dpll
< 0)
1163 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1167 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1168 struct intel_shared_dpll
*pll
,
1172 struct intel_dpll_hw_state hw_state
;
1175 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1178 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1179 I915_STATE_WARN(cur_state
!= state
,
1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll
->name
, state_string(state
), state_string(cur_state
));
1184 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1185 enum pipe pipe
, bool state
)
1190 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1193 if (HAS_DDI(dev_priv
->dev
)) {
1194 /* DDI does not have a specific FDI_TX register */
1195 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1196 val
= I915_READ(reg
);
1197 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1199 reg
= FDI_TX_CTL(pipe
);
1200 val
= I915_READ(reg
);
1201 cur_state
= !!(val
& FDI_TX_ENABLE
);
1203 I915_STATE_WARN(cur_state
!= state
,
1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state
), state_string(cur_state
));
1207 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1210 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1211 enum pipe pipe
, bool state
)
1217 reg
= FDI_RX_CTL(pipe
);
1218 val
= I915_READ(reg
);
1219 cur_state
= !!(val
& FDI_RX_ENABLE
);
1220 I915_STATE_WARN(cur_state
!= state
,
1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state
), state_string(cur_state
));
1224 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1227 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1233 /* ILK FDI PLL is always enabled */
1234 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1238 if (HAS_DDI(dev_priv
->dev
))
1241 reg
= FDI_TX_CTL(pipe
);
1242 val
= I915_READ(reg
);
1243 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1246 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1247 enum pipe pipe
, bool state
)
1253 reg
= FDI_RX_CTL(pipe
);
1254 val
= I915_READ(reg
);
1255 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1256 I915_STATE_WARN(cur_state
!= state
,
1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state
), state_string(cur_state
));
1261 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1264 struct drm_device
*dev
= dev_priv
->dev
;
1267 enum pipe panel_pipe
= PIPE_A
;
1270 if (WARN_ON(HAS_DDI(dev
)))
1273 if (HAS_PCH_SPLIT(dev
)) {
1276 pp_reg
= PCH_PP_CONTROL
;
1277 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1279 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1280 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1281 panel_pipe
= PIPE_B
;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev
)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1288 pp_reg
= PP_CONTROL
;
1289 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1290 panel_pipe
= PIPE_B
;
1293 val
= I915_READ(pp_reg
);
1294 if (!(val
& PANEL_POWER_ON
) ||
1295 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1298 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1299 "panel assertion failure, pipe %c regs locked\n",
1303 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1304 enum pipe pipe
, bool state
)
1306 struct drm_device
*dev
= dev_priv
->dev
;
1309 if (IS_845G(dev
) || IS_I865G(dev
))
1310 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1312 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1314 I915_STATE_WARN(cur_state
!= state
,
1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1318 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1321 void assert_pipe(struct drm_i915_private
*dev_priv
,
1322 enum pipe pipe
, bool state
)
1327 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1332 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1335 if (!intel_display_power_is_enabled(dev_priv
,
1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1339 reg
= PIPECONF(cpu_transcoder
);
1340 val
= I915_READ(reg
);
1341 cur_state
= !!(val
& PIPECONF_ENABLE
);
1344 I915_STATE_WARN(cur_state
!= state
,
1345 "pipe %c assertion failure (expected %s, current %s)\n",
1346 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1349 static void assert_plane(struct drm_i915_private
*dev_priv
,
1350 enum plane plane
, bool state
)
1356 reg
= DSPCNTR(plane
);
1357 val
= I915_READ(reg
);
1358 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1359 I915_STATE_WARN(cur_state
!= state
,
1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane
), state_string(state
), state_string(cur_state
));
1364 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1367 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1370 struct drm_device
*dev
= dev_priv
->dev
;
1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev
)->gen
>= 4) {
1377 reg
= DSPCNTR(pipe
);
1378 val
= I915_READ(reg
);
1379 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1380 "plane %c assertion failure, should be disabled but not\n",
1385 /* Need to check both planes against the pipe */
1386 for_each_pipe(dev_priv
, i
) {
1388 val
= I915_READ(reg
);
1389 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1390 DISPPLANE_SEL_PIPE_SHIFT
;
1391 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i
), pipe_name(pipe
));
1397 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1400 struct drm_device
*dev
= dev_priv
->dev
;
1404 if (INTEL_INFO(dev
)->gen
>= 9) {
1405 for_each_sprite(dev_priv
, pipe
, sprite
) {
1406 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1407 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite
, pipe_name(pipe
));
1411 } else if (IS_VALLEYVIEW(dev
)) {
1412 for_each_sprite(dev_priv
, pipe
, sprite
) {
1413 reg
= SPCNTR(pipe
, sprite
);
1414 val
= I915_READ(reg
);
1415 I915_STATE_WARN(val
& SP_ENABLE
,
1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1419 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1421 val
= I915_READ(reg
);
1422 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1424 plane_name(pipe
), pipe_name(pipe
));
1425 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1426 reg
= DVSCNTR(pipe
);
1427 val
= I915_READ(reg
);
1428 I915_STATE_WARN(val
& DVS_ENABLE
,
1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1430 plane_name(pipe
), pipe_name(pipe
));
1434 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1437 drm_crtc_vblank_put(crtc
);
1440 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1447 val
= I915_READ(PCH_DREF_CONTROL
);
1448 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1449 DREF_SUPERSPREAD_SOURCE_MASK
));
1450 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1453 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1460 reg
= PCH_TRANSCONF(pipe
);
1461 val
= I915_READ(reg
);
1462 enabled
= !!(val
& TRANS_ENABLE
);
1463 I915_STATE_WARN(enabled
,
1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1468 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1469 enum pipe pipe
, u32 port_sel
, u32 val
)
1471 if ((val
& DP_PORT_EN
) == 0)
1474 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1475 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1476 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1477 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1479 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1480 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1483 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1489 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1490 enum pipe pipe
, u32 val
)
1492 if ((val
& SDVO_ENABLE
) == 0)
1495 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1496 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1498 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1499 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1502 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1508 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1509 enum pipe pipe
, u32 val
)
1511 if ((val
& LVDS_PORT_EN
) == 0)
1514 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1515 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1518 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1524 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1525 enum pipe pipe
, u32 val
)
1527 if ((val
& ADPA_DAC_ENABLE
) == 0)
1529 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1530 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1533 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1539 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1540 enum pipe pipe
, int reg
, u32 port_sel
)
1542 u32 val
= I915_READ(reg
);
1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1545 reg
, pipe_name(pipe
));
1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1548 && (val
& DP_PIPEB_SELECT
),
1549 "IBX PCH dp port still using transcoder B\n");
1552 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1553 enum pipe pipe
, int reg
)
1555 u32 val
= I915_READ(reg
);
1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1558 reg
, pipe_name(pipe
));
1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1561 && (val
& SDVO_PIPE_B_SELECT
),
1562 "IBX PCH hdmi port still using transcoder B\n");
1565 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1571 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1572 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1573 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1576 val
= I915_READ(reg
);
1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
1582 val
= I915_READ(reg
);
1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1587 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1588 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1589 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1592 static void intel_init_dpio(struct drm_device
*dev
)
1594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1596 if (!IS_VALLEYVIEW(dev
))
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1604 if (IS_CHERRYVIEW(dev
)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1612 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1613 const struct intel_crtc_state
*pipe_config
)
1615 struct drm_device
*dev
= crtc
->base
.dev
;
1616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1617 int reg
= DPLL(crtc
->pipe
);
1618 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1620 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1625 /* PLL is protected by panel, make sure we can write it */
1626 if (IS_MOBILE(dev_priv
->dev
))
1627 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1629 I915_WRITE(reg
, dpll
);
1633 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1636 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1637 POSTING_READ(DPLL_MD(crtc
->pipe
));
1639 /* We do this three times for luck */
1640 I915_WRITE(reg
, dpll
);
1642 udelay(150); /* wait for warmup */
1643 I915_WRITE(reg
, dpll
);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg
, dpll
);
1648 udelay(150); /* wait for warmup */
1651 static void chv_enable_pll(struct intel_crtc
*crtc
,
1652 const struct intel_crtc_state
*pipe_config
)
1654 struct drm_device
*dev
= crtc
->base
.dev
;
1655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1656 int pipe
= crtc
->pipe
;
1657 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1660 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1664 mutex_lock(&dev_priv
->sb_lock
);
1666 /* Enable back the 10bit clock to display controller */
1667 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1668 tmp
|= DPIO_DCLKP_EN
;
1669 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1671 mutex_unlock(&dev_priv
->sb_lock
);
1674 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1679 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1681 /* Check PLL is locked */
1682 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1683 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1685 /* not sure when this should be written */
1686 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1687 POSTING_READ(DPLL_MD(pipe
));
1690 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1692 struct intel_crtc
*crtc
;
1695 for_each_intel_crtc(dev
, crtc
)
1696 count
+= crtc
->active
&&
1697 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1702 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1704 struct drm_device
*dev
= crtc
->base
.dev
;
1705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1706 int reg
= DPLL(crtc
->pipe
);
1707 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1709 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1711 /* No really, not for ILK+ */
1712 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1714 /* PLL is protected by panel, make sure we can write it */
1715 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1716 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1726 dpll
|= DPLL_DVO_2X_MODE
;
1727 I915_WRITE(DPLL(!crtc
->pipe
),
1728 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1731 /* Wait for the clocks to stabilize. */
1735 if (INTEL_INFO(dev
)->gen
>= 4) {
1736 I915_WRITE(DPLL_MD(crtc
->pipe
),
1737 crtc
->config
->dpll_hw_state
.dpll_md
);
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1742 * So write it again.
1744 I915_WRITE(reg
, dpll
);
1747 /* We do this three times for luck */
1748 I915_WRITE(reg
, dpll
);
1750 udelay(150); /* wait for warmup */
1751 I915_WRITE(reg
, dpll
);
1753 udelay(150); /* wait for warmup */
1754 I915_WRITE(reg
, dpll
);
1756 udelay(150); /* wait for warmup */
1760 * i9xx_disable_pll - disable a PLL
1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1766 * Note! This is for pre-ILK only.
1768 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1770 struct drm_device
*dev
= crtc
->base
.dev
;
1771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1772 enum pipe pipe
= crtc
->pipe
;
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1776 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1777 intel_num_dvo_pipes(dev
) == 1) {
1778 I915_WRITE(DPLL(PIPE_B
),
1779 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1780 I915_WRITE(DPLL(PIPE_A
),
1781 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1786 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv
, pipe
);
1792 I915_WRITE(DPLL(pipe
), 0);
1793 POSTING_READ(DPLL(pipe
));
1796 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv
, pipe
);
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1808 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1809 I915_WRITE(DPLL(pipe
), val
);
1810 POSTING_READ(DPLL(pipe
));
1814 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1816 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv
, pipe
);
1822 /* Set PLL en = 0 */
1823 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1825 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1826 I915_WRITE(DPLL(pipe
), val
);
1827 POSTING_READ(DPLL(pipe
));
1829 mutex_lock(&dev_priv
->sb_lock
);
1831 /* Disable 10bit clock to display controller */
1832 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1833 val
&= ~DPIO_DCLKP_EN
;
1834 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1836 /* disable left/right clock distribution */
1837 if (pipe
!= PIPE_B
) {
1838 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1839 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1840 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1842 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1843 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1844 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1847 mutex_unlock(&dev_priv
->sb_lock
);
1850 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1851 struct intel_digital_port
*dport
,
1852 unsigned int expected_mask
)
1857 switch (dport
->port
) {
1859 port_mask
= DPLL_PORTB_READY_MASK
;
1863 port_mask
= DPLL_PORTC_READY_MASK
;
1865 expected_mask
<<= 4;
1868 port_mask
= DPLL_PORTD_READY_MASK
;
1869 dpll_reg
= DPIO_PHY_STATUS
;
1875 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == expected_mask
, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1880 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1882 struct drm_device
*dev
= crtc
->base
.dev
;
1883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1884 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1886 if (WARN_ON(pll
== NULL
))
1889 WARN_ON(!pll
->config
.crtc_mask
);
1890 if (pll
->active
== 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1893 assert_shared_dpll_disabled(dev_priv
, pll
);
1895 pll
->mode_set(dev_priv
, pll
);
1900 * intel_enable_shared_dpll - enable PCH PLL
1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1907 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1909 struct drm_device
*dev
= crtc
->base
.dev
;
1910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1911 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1913 if (WARN_ON(pll
== NULL
))
1916 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1920 pll
->name
, pll
->active
, pll
->on
,
1921 crtc
->base
.base
.id
);
1923 if (pll
->active
++) {
1925 assert_shared_dpll_enabled(dev_priv
, pll
);
1930 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1932 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1933 pll
->enable(dev_priv
, pll
);
1937 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1939 struct drm_device
*dev
= crtc
->base
.dev
;
1940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1941 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1943 /* PCH only available on ILK+ */
1944 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1945 if (WARN_ON(pll
== NULL
))
1948 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll
->name
, pll
->active
, pll
->on
,
1953 crtc
->base
.base
.id
);
1955 if (WARN_ON(pll
->active
== 0)) {
1956 assert_shared_dpll_disabled(dev_priv
, pll
);
1960 assert_shared_dpll_enabled(dev_priv
, pll
);
1965 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1966 pll
->disable(dev_priv
, pll
);
1969 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1972 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1975 struct drm_device
*dev
= dev_priv
->dev
;
1976 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1977 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1978 uint32_t reg
, val
, pipeconf_val
;
1980 /* PCH only available on ILK+ */
1981 BUG_ON(!HAS_PCH_SPLIT(dev
));
1983 /* Make sure PCH DPLL is enabled */
1984 assert_shared_dpll_enabled(dev_priv
,
1985 intel_crtc_to_shared_dpll(intel_crtc
));
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv
, pipe
);
1989 assert_fdi_rx_enabled(dev_priv
, pipe
);
1991 if (HAS_PCH_CPT(dev
)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg
= TRANS_CHICKEN2(pipe
);
1995 val
= I915_READ(reg
);
1996 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1997 I915_WRITE(reg
, val
);
2000 reg
= PCH_TRANSCONF(pipe
);
2001 val
= I915_READ(reg
);
2002 pipeconf_val
= I915_READ(PIPECONF(pipe
));
2004 if (HAS_PCH_IBX(dev_priv
->dev
)) {
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2009 val
&= ~PIPECONF_BPC_MASK
;
2010 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
2013 val
&= ~TRANS_INTERLACE_MASK
;
2014 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
2015 if (HAS_PCH_IBX(dev_priv
->dev
) &&
2016 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
2017 val
|= TRANS_LEGACY_INTERLACED_ILK
;
2019 val
|= TRANS_INTERLACED
;
2021 val
|= TRANS_PROGRESSIVE
;
2023 I915_WRITE(reg
, val
| TRANS_ENABLE
);
2024 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
2028 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2029 enum transcoder cpu_transcoder
)
2031 u32 val
, pipeconf_val
;
2033 /* PCH only available on ILK+ */
2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
2036 /* FDI must be feeding us bits for PCH ports */
2037 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
2038 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
2040 /* Workaround: set timing override bit. */
2041 val
= I915_READ(_TRANSA_CHICKEN2
);
2042 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
2043 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2046 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
2048 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
2049 PIPECONF_INTERLACED_ILK
)
2050 val
|= TRANS_INTERLACED
;
2052 val
|= TRANS_PROGRESSIVE
;
2054 I915_WRITE(LPT_TRANSCONF
, val
);
2055 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
2056 DRM_ERROR("Failed to enable PCH transcoder\n");
2059 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2062 struct drm_device
*dev
= dev_priv
->dev
;
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv
, pipe
);
2067 assert_fdi_rx_disabled(dev_priv
, pipe
);
2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv
, pipe
);
2072 reg
= PCH_TRANSCONF(pipe
);
2073 val
= I915_READ(reg
);
2074 val
&= ~TRANS_ENABLE
;
2075 I915_WRITE(reg
, val
);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
2080 if (!HAS_PCH_IBX(dev
)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg
= TRANS_CHICKEN2(pipe
);
2083 val
= I915_READ(reg
);
2084 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2085 I915_WRITE(reg
, val
);
2089 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
2093 val
= I915_READ(LPT_TRANSCONF
);
2094 val
&= ~TRANS_ENABLE
;
2095 I915_WRITE(LPT_TRANSCONF
, val
);
2096 /* wait for PCH transcoder off, transcoder state */
2097 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
2098 DRM_ERROR("Failed to disable PCH transcoder\n");
2100 /* Workaround: clear timing override bit. */
2101 val
= I915_READ(_TRANSA_CHICKEN2
);
2102 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2103 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2107 * intel_enable_pipe - enable a pipe, asserting requirements
2108 * @crtc: crtc responsible for the pipe
2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2113 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2115 struct drm_device
*dev
= crtc
->base
.dev
;
2116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2117 enum pipe pipe
= crtc
->pipe
;
2118 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2120 enum pipe pch_transcoder
;
2124 assert_planes_disabled(dev_priv
, pipe
);
2125 assert_cursor_disabled(dev_priv
, pipe
);
2126 assert_sprites_disabled(dev_priv
, pipe
);
2128 if (HAS_PCH_LPT(dev_priv
->dev
))
2129 pch_transcoder
= TRANSCODER_A
;
2131 pch_transcoder
= pipe
;
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2138 if (HAS_GMCH_DISPLAY(dev_priv
->dev
))
2139 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2140 assert_dsi_pll_enabled(dev_priv
);
2142 assert_pll_enabled(dev_priv
, pipe
);
2144 if (crtc
->config
->has_pch_encoder
) {
2145 /* if driving the PCH, we need FDI enabled */
2146 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2147 assert_fdi_tx_pll_enabled(dev_priv
,
2148 (enum pipe
) cpu_transcoder
);
2150 /* FIXME: assert CPU port conditions for SNB+ */
2153 reg
= PIPECONF(cpu_transcoder
);
2154 val
= I915_READ(reg
);
2155 if (val
& PIPECONF_ENABLE
) {
2156 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2157 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2161 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2166 * intel_disable_pipe - disable a pipe, asserting requirements
2167 * @crtc: crtc whose pipes is to be disabled
2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
2173 * Will wait until the pipe has shut down before returning.
2175 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2177 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2178 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2179 enum pipe pipe
= crtc
->pipe
;
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2187 assert_planes_disabled(dev_priv
, pipe
);
2188 assert_cursor_disabled(dev_priv
, pipe
);
2189 assert_sprites_disabled(dev_priv
, pipe
);
2191 reg
= PIPECONF(cpu_transcoder
);
2192 val
= I915_READ(reg
);
2193 if ((val
& PIPECONF_ENABLE
) == 0)
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2200 if (crtc
->config
->double_wide
)
2201 val
&= ~PIPECONF_DOUBLE_WIDE
;
2203 /* Don't disable pipe or pipe PLLs if needed */
2204 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2205 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2206 val
&= ~PIPECONF_ENABLE
;
2208 I915_WRITE(reg
, val
);
2209 if ((val
& PIPECONF_ENABLE
) == 0)
2210 intel_wait_for_pipe_off(crtc
);
2214 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2215 * @plane: plane to be enabled
2216 * @crtc: crtc for the plane
2218 * Enable @plane on @crtc, making sure that the pipe is running first.
2220 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2221 struct drm_crtc
*crtc
)
2223 struct drm_device
*dev
= plane
->dev
;
2224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2225 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2227 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2228 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2229 to_intel_plane_state(plane
->state
)->visible
= true;
2231 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2235 static bool need_vtd_wa(struct drm_device
*dev
)
2237 #ifdef CONFIG_INTEL_IOMMU
2238 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2245 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
2246 uint64_t fb_format_modifier
)
2248 unsigned int tile_height
;
2249 uint32_t pixel_bytes
;
2251 switch (fb_format_modifier
) {
2252 case DRM_FORMAT_MOD_NONE
:
2255 case I915_FORMAT_MOD_X_TILED
:
2256 tile_height
= IS_GEN2(dev
) ? 16 : 8;
2258 case I915_FORMAT_MOD_Y_TILED
:
2261 case I915_FORMAT_MOD_Yf_TILED
:
2262 pixel_bytes
= drm_format_plane_cpp(pixel_format
, 0);
2263 switch (pixel_bytes
) {
2277 "128-bit pixels are not supported for display!");
2283 MISSING_CASE(fb_format_modifier
);
2292 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2293 uint32_t pixel_format
, uint64_t fb_format_modifier
)
2295 return ALIGN(height
, intel_tile_height(dev
, pixel_format
,
2296 fb_format_modifier
));
2300 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
, struct drm_framebuffer
*fb
,
2301 const struct drm_plane_state
*plane_state
)
2303 struct intel_rotation_info
*info
= &view
->rotation_info
;
2305 *view
= i915_ggtt_view_normal
;
2310 if (!intel_rotation_90_or_270(plane_state
->rotation
))
2313 *view
= i915_ggtt_view_rotated
;
2315 info
->height
= fb
->height
;
2316 info
->pixel_format
= fb
->pixel_format
;
2317 info
->pitch
= fb
->pitches
[0];
2318 info
->fb_modifier
= fb
->modifier
[0];
2324 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2325 struct drm_framebuffer
*fb
,
2326 const struct drm_plane_state
*plane_state
,
2327 struct intel_engine_cs
*pipelined
)
2329 struct drm_device
*dev
= fb
->dev
;
2330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2331 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2332 struct i915_ggtt_view view
;
2336 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2338 switch (fb
->modifier
[0]) {
2339 case DRM_FORMAT_MOD_NONE
:
2340 if (INTEL_INFO(dev
)->gen
>= 9)
2341 alignment
= 256 * 1024;
2342 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2343 alignment
= 128 * 1024;
2344 else if (INTEL_INFO(dev
)->gen
>= 4)
2345 alignment
= 4 * 1024;
2347 alignment
= 64 * 1024;
2349 case I915_FORMAT_MOD_X_TILED
:
2350 if (INTEL_INFO(dev
)->gen
>= 9)
2351 alignment
= 256 * 1024;
2353 /* pin() will align the object as required by fence */
2357 case I915_FORMAT_MOD_Y_TILED
:
2358 case I915_FORMAT_MOD_Yf_TILED
:
2359 if (WARN_ONCE(INTEL_INFO(dev
)->gen
< 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2362 alignment
= 1 * 1024 * 1024;
2365 MISSING_CASE(fb
->modifier
[0]);
2369 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2378 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2379 alignment
= 256 * 1024;
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2388 intel_runtime_pm_get(dev_priv
);
2390 dev_priv
->mm
.interruptible
= false;
2391 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
,
2394 goto err_interruptible
;
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2401 ret
= i915_gem_object_get_fence(obj
);
2405 i915_gem_object_pin_fence(obj
);
2407 dev_priv
->mm
.interruptible
= true;
2408 intel_runtime_pm_put(dev_priv
);
2412 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2414 dev_priv
->mm
.interruptible
= true;
2415 intel_runtime_pm_put(dev_priv
);
2419 static void intel_unpin_fb_obj(struct drm_framebuffer
*fb
,
2420 const struct drm_plane_state
*plane_state
)
2422 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2423 struct i915_ggtt_view view
;
2426 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2428 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2429 WARN_ONCE(ret
, "Couldn't get view from plane state!");
2431 i915_gem_object_unpin_fence(obj
);
2432 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2435 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2436 * is assumed to be a power-of-two. */
2437 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2438 unsigned int tiling_mode
,
2442 if (tiling_mode
!= I915_TILING_NONE
) {
2443 unsigned int tile_rows
, tiles
;
2448 tiles
= *x
/ (512/cpp
);
2451 return tile_rows
* pitch
* 8 + tiles
* 4096;
2453 unsigned int offset
;
2455 offset
= *y
* pitch
+ *x
* cpp
;
2457 *x
= (offset
& 4095) / cpp
;
2458 return offset
& -4096;
2462 static int i9xx_format_to_fourcc(int format
)
2465 case DISPPLANE_8BPP
:
2466 return DRM_FORMAT_C8
;
2467 case DISPPLANE_BGRX555
:
2468 return DRM_FORMAT_XRGB1555
;
2469 case DISPPLANE_BGRX565
:
2470 return DRM_FORMAT_RGB565
;
2472 case DISPPLANE_BGRX888
:
2473 return DRM_FORMAT_XRGB8888
;
2474 case DISPPLANE_RGBX888
:
2475 return DRM_FORMAT_XBGR8888
;
2476 case DISPPLANE_BGRX101010
:
2477 return DRM_FORMAT_XRGB2101010
;
2478 case DISPPLANE_RGBX101010
:
2479 return DRM_FORMAT_XBGR2101010
;
2483 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2486 case PLANE_CTL_FORMAT_RGB_565
:
2487 return DRM_FORMAT_RGB565
;
2489 case PLANE_CTL_FORMAT_XRGB_8888
:
2492 return DRM_FORMAT_ABGR8888
;
2494 return DRM_FORMAT_XBGR8888
;
2497 return DRM_FORMAT_ARGB8888
;
2499 return DRM_FORMAT_XRGB8888
;
2501 case PLANE_CTL_FORMAT_XRGB_2101010
:
2503 return DRM_FORMAT_XBGR2101010
;
2505 return DRM_FORMAT_XRGB2101010
;
2510 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2511 struct intel_initial_plane_config
*plane_config
)
2513 struct drm_device
*dev
= crtc
->base
.dev
;
2514 struct drm_i915_gem_object
*obj
= NULL
;
2515 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2516 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2517 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2518 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2521 size_aligned
-= base_aligned
;
2523 if (plane_config
->size
== 0)
2526 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2533 obj
->tiling_mode
= plane_config
->tiling
;
2534 if (obj
->tiling_mode
== I915_TILING_X
)
2535 obj
->stride
= fb
->pitches
[0];
2537 mode_cmd
.pixel_format
= fb
->pixel_format
;
2538 mode_cmd
.width
= fb
->width
;
2539 mode_cmd
.height
= fb
->height
;
2540 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2541 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2542 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2544 mutex_lock(&dev
->struct_mutex
);
2545 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2547 DRM_DEBUG_KMS("intel fb init failed\n");
2550 mutex_unlock(&dev
->struct_mutex
);
2552 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2556 drm_gem_object_unreference(&obj
->base
);
2557 mutex_unlock(&dev
->struct_mutex
);
2561 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2563 update_state_fb(struct drm_plane
*plane
)
2565 if (plane
->fb
== plane
->state
->fb
)
2568 if (plane
->state
->fb
)
2569 drm_framebuffer_unreference(plane
->state
->fb
);
2570 plane
->state
->fb
= plane
->fb
;
2571 if (plane
->state
->fb
)
2572 drm_framebuffer_reference(plane
->state
->fb
);
2576 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2577 struct intel_initial_plane_config
*plane_config
)
2579 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2582 struct intel_crtc
*i
;
2583 struct drm_i915_gem_object
*obj
;
2584 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2585 struct drm_framebuffer
*fb
;
2587 if (!plane_config
->fb
)
2590 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2591 fb
= &plane_config
->fb
->base
;
2595 kfree(plane_config
->fb
);
2598 * Failed to alloc the obj, check to see if we should share
2599 * an fb with another CRTC instead
2601 for_each_crtc(dev
, c
) {
2602 i
= to_intel_crtc(c
);
2604 if (c
== &intel_crtc
->base
)
2610 fb
= c
->primary
->fb
;
2614 obj
= intel_fb_obj(fb
);
2615 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2616 drm_framebuffer_reference(fb
);
2624 obj
= intel_fb_obj(fb
);
2625 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2626 dev_priv
->preserve_bios_swizzle
= true;
2629 primary
->state
->crtc
= &intel_crtc
->base
;
2630 primary
->crtc
= &intel_crtc
->base
;
2631 update_state_fb(primary
);
2632 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2635 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2636 struct drm_framebuffer
*fb
,
2639 struct drm_device
*dev
= crtc
->dev
;
2640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2641 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2642 struct drm_plane
*primary
= crtc
->primary
;
2643 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2644 struct drm_i915_gem_object
*obj
;
2645 int plane
= intel_crtc
->plane
;
2646 unsigned long linear_offset
;
2648 u32 reg
= DSPCNTR(plane
);
2651 if (!visible
|| !fb
) {
2653 if (INTEL_INFO(dev
)->gen
>= 4)
2654 I915_WRITE(DSPSURF(plane
), 0);
2656 I915_WRITE(DSPADDR(plane
), 0);
2661 obj
= intel_fb_obj(fb
);
2662 if (WARN_ON(obj
== NULL
))
2665 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2667 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2669 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2671 if (INTEL_INFO(dev
)->gen
< 4) {
2672 if (intel_crtc
->pipe
== PIPE_B
)
2673 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2678 I915_WRITE(DSPSIZE(plane
),
2679 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2680 (intel_crtc
->config
->pipe_src_w
- 1));
2681 I915_WRITE(DSPPOS(plane
), 0);
2682 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2683 I915_WRITE(PRIMSIZE(plane
),
2684 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2685 (intel_crtc
->config
->pipe_src_w
- 1));
2686 I915_WRITE(PRIMPOS(plane
), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2690 switch (fb
->pixel_format
) {
2692 dspcntr
|= DISPPLANE_8BPP
;
2694 case DRM_FORMAT_XRGB1555
:
2695 dspcntr
|= DISPPLANE_BGRX555
;
2697 case DRM_FORMAT_RGB565
:
2698 dspcntr
|= DISPPLANE_BGRX565
;
2700 case DRM_FORMAT_XRGB8888
:
2701 dspcntr
|= DISPPLANE_BGRX888
;
2703 case DRM_FORMAT_XBGR8888
:
2704 dspcntr
|= DISPPLANE_RGBX888
;
2706 case DRM_FORMAT_XRGB2101010
:
2707 dspcntr
|= DISPPLANE_BGRX101010
;
2709 case DRM_FORMAT_XBGR2101010
:
2710 dspcntr
|= DISPPLANE_RGBX101010
;
2716 if (INTEL_INFO(dev
)->gen
>= 4 &&
2717 obj
->tiling_mode
!= I915_TILING_NONE
)
2718 dspcntr
|= DISPPLANE_TILED
;
2721 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2723 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2725 if (INTEL_INFO(dev
)->gen
>= 4) {
2726 intel_crtc
->dspaddr_offset
=
2727 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2730 linear_offset
-= intel_crtc
->dspaddr_offset
;
2732 intel_crtc
->dspaddr_offset
= linear_offset
;
2735 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2736 dspcntr
|= DISPPLANE_ROTATE_180
;
2738 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2739 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2741 /* Finding the last pixel of the last line of the display
2742 data and adding to linear_offset*/
2744 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2745 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2748 I915_WRITE(reg
, dspcntr
);
2750 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2751 if (INTEL_INFO(dev
)->gen
>= 4) {
2752 I915_WRITE(DSPSURF(plane
),
2753 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2754 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2755 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2757 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2761 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2762 struct drm_framebuffer
*fb
,
2765 struct drm_device
*dev
= crtc
->dev
;
2766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2767 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2768 struct drm_plane
*primary
= crtc
->primary
;
2769 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2770 struct drm_i915_gem_object
*obj
;
2771 int plane
= intel_crtc
->plane
;
2772 unsigned long linear_offset
;
2774 u32 reg
= DSPCNTR(plane
);
2777 if (!visible
|| !fb
) {
2779 I915_WRITE(DSPSURF(plane
), 0);
2784 obj
= intel_fb_obj(fb
);
2785 if (WARN_ON(obj
== NULL
))
2788 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2790 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2792 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2794 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2795 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2797 switch (fb
->pixel_format
) {
2799 dspcntr
|= DISPPLANE_8BPP
;
2801 case DRM_FORMAT_RGB565
:
2802 dspcntr
|= DISPPLANE_BGRX565
;
2804 case DRM_FORMAT_XRGB8888
:
2805 dspcntr
|= DISPPLANE_BGRX888
;
2807 case DRM_FORMAT_XBGR8888
:
2808 dspcntr
|= DISPPLANE_RGBX888
;
2810 case DRM_FORMAT_XRGB2101010
:
2811 dspcntr
|= DISPPLANE_BGRX101010
;
2813 case DRM_FORMAT_XBGR2101010
:
2814 dspcntr
|= DISPPLANE_RGBX101010
;
2820 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2821 dspcntr
|= DISPPLANE_TILED
;
2823 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2824 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2826 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2827 intel_crtc
->dspaddr_offset
=
2828 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2831 linear_offset
-= intel_crtc
->dspaddr_offset
;
2832 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2833 dspcntr
|= DISPPLANE_ROTATE_180
;
2835 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2836 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2837 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2839 /* Finding the last pixel of the last line of the display
2840 data and adding to linear_offset*/
2842 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2843 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2847 I915_WRITE(reg
, dspcntr
);
2849 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2850 I915_WRITE(DSPSURF(plane
),
2851 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2852 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2853 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2855 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2856 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2861 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
2862 uint32_t pixel_format
)
2864 u32 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2867 * The stride is either expressed as a multiple of 64 bytes
2868 * chunks for linear buffers or in number of tiles for tiled
2871 switch (fb_modifier
) {
2872 case DRM_FORMAT_MOD_NONE
:
2874 case I915_FORMAT_MOD_X_TILED
:
2875 if (INTEL_INFO(dev
)->gen
== 2)
2878 case I915_FORMAT_MOD_Y_TILED
:
2879 /* No need to check for old gens and Y tiling since this is
2880 * about the display engine and those will be blocked before
2884 case I915_FORMAT_MOD_Yf_TILED
:
2885 if (bits_per_pixel
== 8)
2890 MISSING_CASE(fb_modifier
);
2895 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2896 struct drm_i915_gem_object
*obj
)
2898 const struct i915_ggtt_view
*view
= &i915_ggtt_view_normal
;
2900 if (intel_rotation_90_or_270(intel_plane
->base
.state
->rotation
))
2901 view
= &i915_ggtt_view_rotated
;
2903 return i915_gem_obj_ggtt_offset_view(obj
, view
);
2907 * This function detaches (aka. unbinds) unused scalers in hardware
2909 void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2911 struct drm_device
*dev
;
2912 struct drm_i915_private
*dev_priv
;
2913 struct intel_crtc_scaler_state
*scaler_state
;
2916 if (!intel_crtc
|| !intel_crtc
->config
)
2919 dev
= intel_crtc
->base
.dev
;
2920 dev_priv
= dev
->dev_private
;
2921 scaler_state
= &intel_crtc
->config
->scaler_state
;
2923 /* loop through and disable scalers that aren't in use */
2924 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2925 if (!scaler_state
->scalers
[i
].in_use
) {
2926 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, i
), 0);
2927 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, i
), 0);
2928 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, i
), 0);
2929 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2930 intel_crtc
->base
.base
.id
, intel_crtc
->pipe
, i
);
2935 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2937 switch (pixel_format
) {
2939 return PLANE_CTL_FORMAT_INDEXED
;
2940 case DRM_FORMAT_RGB565
:
2941 return PLANE_CTL_FORMAT_RGB_565
;
2942 case DRM_FORMAT_XBGR8888
:
2943 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2944 case DRM_FORMAT_XRGB8888
:
2945 return PLANE_CTL_FORMAT_XRGB_8888
;
2947 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2948 * to be already pre-multiplied. We need to add a knob (or a different
2949 * DRM_FORMAT) for user-space to configure that.
2951 case DRM_FORMAT_ABGR8888
:
2952 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
2953 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2954 case DRM_FORMAT_ARGB8888
:
2955 return PLANE_CTL_FORMAT_XRGB_8888
|
2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2957 case DRM_FORMAT_XRGB2101010
:
2958 return PLANE_CTL_FORMAT_XRGB_2101010
;
2959 case DRM_FORMAT_XBGR2101010
:
2960 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
2961 case DRM_FORMAT_YUYV
:
2962 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
2963 case DRM_FORMAT_YVYU
:
2964 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
2965 case DRM_FORMAT_UYVY
:
2966 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
2967 case DRM_FORMAT_VYUY
:
2968 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
2970 MISSING_CASE(pixel_format
);
2976 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
2978 switch (fb_modifier
) {
2979 case DRM_FORMAT_MOD_NONE
:
2981 case I915_FORMAT_MOD_X_TILED
:
2982 return PLANE_CTL_TILED_X
;
2983 case I915_FORMAT_MOD_Y_TILED
:
2984 return PLANE_CTL_TILED_Y
;
2985 case I915_FORMAT_MOD_Yf_TILED
:
2986 return PLANE_CTL_TILED_YF
;
2988 MISSING_CASE(fb_modifier
);
2994 u32
skl_plane_ctl_rotation(unsigned int rotation
)
2997 case BIT(DRM_ROTATE_0
):
3000 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3001 * while i915 HW rotation is clockwise, thats why this swapping.
3003 case BIT(DRM_ROTATE_90
):
3004 return PLANE_CTL_ROTATE_270
;
3005 case BIT(DRM_ROTATE_180
):
3006 return PLANE_CTL_ROTATE_180
;
3007 case BIT(DRM_ROTATE_270
):
3008 return PLANE_CTL_ROTATE_90
;
3010 MISSING_CASE(rotation
);
3016 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
3017 struct drm_framebuffer
*fb
,
3020 struct drm_device
*dev
= crtc
->dev
;
3021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3022 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3023 struct drm_plane
*plane
= crtc
->primary
;
3024 bool visible
= to_intel_plane_state(plane
->state
)->visible
;
3025 struct drm_i915_gem_object
*obj
;
3026 int pipe
= intel_crtc
->pipe
;
3027 u32 plane_ctl
, stride_div
, stride
;
3028 u32 tile_height
, plane_offset
, plane_size
;
3029 unsigned int rotation
;
3030 int x_offset
, y_offset
;
3031 unsigned long surf_addr
;
3032 struct intel_crtc_state
*crtc_state
= intel_crtc
->config
;
3033 struct intel_plane_state
*plane_state
;
3034 int src_x
= 0, src_y
= 0, src_w
= 0, src_h
= 0;
3035 int dst_x
= 0, dst_y
= 0, dst_w
= 0, dst_h
= 0;
3038 plane_state
= to_intel_plane_state(plane
->state
);
3040 if (!visible
|| !fb
) {
3041 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3042 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3043 POSTING_READ(PLANE_CTL(pipe
, 0));
3047 plane_ctl
= PLANE_CTL_ENABLE
|
3048 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3049 PLANE_CTL_PIPE_CSC_ENABLE
;
3051 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3052 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3053 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3055 rotation
= plane
->state
->rotation
;
3056 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3058 obj
= intel_fb_obj(fb
);
3059 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
3061 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
);
3064 * FIXME: intel_plane_state->src, dst aren't set when transitional
3065 * update_plane helpers are called from legacy paths.
3066 * Once full atomic crtc is available, below check can be avoided.
3068 if (drm_rect_width(&plane_state
->src
)) {
3069 scaler_id
= plane_state
->scaler_id
;
3070 src_x
= plane_state
->src
.x1
>> 16;
3071 src_y
= plane_state
->src
.y1
>> 16;
3072 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3073 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3074 dst_x
= plane_state
->dst
.x1
;
3075 dst_y
= plane_state
->dst
.y1
;
3076 dst_w
= drm_rect_width(&plane_state
->dst
);
3077 dst_h
= drm_rect_height(&plane_state
->dst
);
3079 WARN_ON(x
!= src_x
|| y
!= src_y
);
3081 src_w
= intel_crtc
->config
->pipe_src_w
;
3082 src_h
= intel_crtc
->config
->pipe_src_h
;
3085 if (intel_rotation_90_or_270(rotation
)) {
3086 /* stride = Surface height in tiles */
3087 tile_height
= intel_tile_height(dev
, fb
->pixel_format
,
3089 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3090 x_offset
= stride
* tile_height
- y
- src_h
;
3092 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3094 stride
= fb
->pitches
[0] / stride_div
;
3097 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3099 plane_offset
= y_offset
<< 16 | x_offset
;
3101 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3102 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3103 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3104 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3106 if (scaler_id
>= 0) {
3107 uint32_t ps_ctrl
= 0;
3109 WARN_ON(!dst_w
|| !dst_h
);
3110 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3111 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3112 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3113 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3114 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3115 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3116 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3118 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3121 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3123 POSTING_READ(PLANE_SURF(pipe
, 0));
3126 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3128 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3129 int x
, int y
, enum mode_set_atomic state
)
3131 struct drm_device
*dev
= crtc
->dev
;
3132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3134 if (dev_priv
->display
.disable_fbc
)
3135 dev_priv
->display
.disable_fbc(dev
);
3137 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
3142 static void intel_complete_page_flips(struct drm_device
*dev
)
3144 struct drm_crtc
*crtc
;
3146 for_each_crtc(dev
, crtc
) {
3147 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3148 enum plane plane
= intel_crtc
->plane
;
3150 intel_prepare_page_flip(dev
, plane
);
3151 intel_finish_page_flip_plane(dev
, plane
);
3155 static void intel_update_primary_planes(struct drm_device
*dev
)
3157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3158 struct drm_crtc
*crtc
;
3160 for_each_crtc(dev
, crtc
) {
3161 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3163 drm_modeset_lock(&crtc
->mutex
, NULL
);
3165 * FIXME: Once we have proper support for primary planes (and
3166 * disabling them without disabling the entire crtc) allow again
3167 * a NULL crtc->primary->fb.
3169 if (intel_crtc
->active
&& crtc
->primary
->fb
)
3170 dev_priv
->display
.update_primary_plane(crtc
,
3174 drm_modeset_unlock(&crtc
->mutex
);
3178 void intel_crtc_reset(struct intel_crtc
*crtc
)
3180 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3185 intel_crtc_disable_planes(&crtc
->base
);
3186 dev_priv
->display
.crtc_disable(&crtc
->base
);
3187 dev_priv
->display
.crtc_enable(&crtc
->base
);
3188 intel_crtc_enable_planes(&crtc
->base
);
3191 void intel_prepare_reset(struct drm_device
*dev
)
3193 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3194 struct intel_crtc
*crtc
;
3196 /* no reset support for gen2 */
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
3204 drm_modeset_lock_all(dev
);
3207 * Disabling the crtcs gracefully seems nicer. Also the
3208 * g33 docs say we should at least disable all the planes.
3210 for_each_intel_crtc(dev
, crtc
) {
3214 intel_crtc_disable_planes(&crtc
->base
);
3215 dev_priv
->display
.crtc_disable(&crtc
->base
);
3219 void intel_finish_reset(struct drm_device
*dev
)
3221 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3224 * Flips in the rings will be nuked by the reset,
3225 * so complete all pending flips so that user space
3226 * will get its events and not get stuck.
3228 intel_complete_page_flips(dev
);
3230 /* no reset support for gen2 */
3234 /* reset doesn't touch the display */
3235 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3237 * Flips in the rings have been nuked by the reset,
3238 * so update the base address of all primary
3239 * planes to the the last fb to make sure we're
3240 * showing the correct fb after a reset.
3242 intel_update_primary_planes(dev
);
3247 * The display has been reset as well,
3248 * so need a full re-initialization.
3250 intel_runtime_pm_disable_interrupts(dev_priv
);
3251 intel_runtime_pm_enable_interrupts(dev_priv
);
3253 intel_modeset_init_hw(dev
);
3255 spin_lock_irq(&dev_priv
->irq_lock
);
3256 if (dev_priv
->display
.hpd_irq_setup
)
3257 dev_priv
->display
.hpd_irq_setup(dev
);
3258 spin_unlock_irq(&dev_priv
->irq_lock
);
3260 intel_modeset_setup_hw_state(dev
, true);
3262 intel_hpd_init(dev_priv
);
3264 drm_modeset_unlock_all(dev
);
3268 intel_finish_fb(struct drm_framebuffer
*old_fb
)
3270 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
3271 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3272 bool was_interruptible
= dev_priv
->mm
.interruptible
;
3275 /* Big Hammer, we also need to ensure that any pending
3276 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3277 * current scanout is retired before unpinning the old
3278 * framebuffer. Note that we rely on userspace rendering
3279 * into the buffer attached to the pipe they are waiting
3280 * on. If not, userspace generates a GPU hang with IPEHR
3281 * point to the MI_WAIT_FOR_EVENT.
3283 * This should only fail upon a hung GPU, in which case we
3284 * can safely continue.
3286 dev_priv
->mm
.interruptible
= false;
3287 ret
= i915_gem_object_wait_rendering(obj
, true);
3288 dev_priv
->mm
.interruptible
= was_interruptible
;
3293 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3295 struct drm_device
*dev
= crtc
->dev
;
3296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3297 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3300 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3301 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3304 spin_lock_irq(&dev
->event_lock
);
3305 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3306 spin_unlock_irq(&dev
->event_lock
);
3311 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
3313 struct drm_device
*dev
= crtc
->base
.dev
;
3314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3315 const struct drm_display_mode
*adjusted_mode
;
3321 * Update pipe size and adjust fitter if needed: the reason for this is
3322 * that in compute_mode_changes we check the native mode (not the pfit
3323 * mode) to see if we can flip rather than do a full mode set. In the
3324 * fastboot case, we'll flip, but if we don't update the pipesrc and
3325 * pfit state, we'll end up with a big fb scanned out into the wrong
3328 * To fix this properly, we need to hoist the checks up into
3329 * compute_mode_changes (or above), check the actual pfit state and
3330 * whether the platform allows pfit disable with pipe active, and only
3331 * then update the pipesrc and pfit state, even on the flip path.
3334 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
3336 I915_WRITE(PIPESRC(crtc
->pipe
),
3337 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
3338 (adjusted_mode
->crtc_vdisplay
- 1));
3339 if (!crtc
->config
->pch_pfit
.enabled
&&
3340 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3341 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3342 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
3343 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
3344 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
3346 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
3347 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
3350 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3352 struct drm_device
*dev
= crtc
->dev
;
3353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3354 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3355 int pipe
= intel_crtc
->pipe
;
3358 /* enable normal train */
3359 reg
= FDI_TX_CTL(pipe
);
3360 temp
= I915_READ(reg
);
3361 if (IS_IVYBRIDGE(dev
)) {
3362 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3363 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3365 temp
&= ~FDI_LINK_TRAIN_NONE
;
3366 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3368 I915_WRITE(reg
, temp
);
3370 reg
= FDI_RX_CTL(pipe
);
3371 temp
= I915_READ(reg
);
3372 if (HAS_PCH_CPT(dev
)) {
3373 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3374 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3376 temp
&= ~FDI_LINK_TRAIN_NONE
;
3377 temp
|= FDI_LINK_TRAIN_NONE
;
3379 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3381 /* wait one idle pattern time */
3385 /* IVB wants error correction enabled */
3386 if (IS_IVYBRIDGE(dev
))
3387 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3388 FDI_FE_ERRC_ENABLE
);
3391 /* The FDI link training functions for ILK/Ibexpeak. */
3392 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3394 struct drm_device
*dev
= crtc
->dev
;
3395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3396 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3397 int pipe
= intel_crtc
->pipe
;
3398 u32 reg
, temp
, tries
;
3400 /* FDI needs bits from pipe first */
3401 assert_pipe_enabled(dev_priv
, pipe
);
3403 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3405 reg
= FDI_RX_IMR(pipe
);
3406 temp
= I915_READ(reg
);
3407 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3408 temp
&= ~FDI_RX_BIT_LOCK
;
3409 I915_WRITE(reg
, temp
);
3413 /* enable CPU FDI TX and PCH FDI RX */
3414 reg
= FDI_TX_CTL(pipe
);
3415 temp
= I915_READ(reg
);
3416 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3417 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3418 temp
&= ~FDI_LINK_TRAIN_NONE
;
3419 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3420 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3422 reg
= FDI_RX_CTL(pipe
);
3423 temp
= I915_READ(reg
);
3424 temp
&= ~FDI_LINK_TRAIN_NONE
;
3425 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3426 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3431 /* Ironlake workaround, enable clock pointer after FDI enable*/
3432 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3433 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3434 FDI_RX_PHASE_SYNC_POINTER_EN
);
3436 reg
= FDI_RX_IIR(pipe
);
3437 for (tries
= 0; tries
< 5; tries
++) {
3438 temp
= I915_READ(reg
);
3439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3441 if ((temp
& FDI_RX_BIT_LOCK
)) {
3442 DRM_DEBUG_KMS("FDI train 1 done.\n");
3443 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3448 DRM_ERROR("FDI train 1 fail!\n");
3451 reg
= FDI_TX_CTL(pipe
);
3452 temp
= I915_READ(reg
);
3453 temp
&= ~FDI_LINK_TRAIN_NONE
;
3454 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3455 I915_WRITE(reg
, temp
);
3457 reg
= FDI_RX_CTL(pipe
);
3458 temp
= I915_READ(reg
);
3459 temp
&= ~FDI_LINK_TRAIN_NONE
;
3460 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3461 I915_WRITE(reg
, temp
);
3466 reg
= FDI_RX_IIR(pipe
);
3467 for (tries
= 0; tries
< 5; tries
++) {
3468 temp
= I915_READ(reg
);
3469 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3471 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3472 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3473 DRM_DEBUG_KMS("FDI train 2 done.\n");
3478 DRM_ERROR("FDI train 2 fail!\n");
3480 DRM_DEBUG_KMS("FDI train done\n");
3484 static const int snb_b_fdi_train_param
[] = {
3485 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3486 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3487 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3488 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3491 /* The FDI link training functions for SNB/Cougarpoint. */
3492 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3494 struct drm_device
*dev
= crtc
->dev
;
3495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3496 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3497 int pipe
= intel_crtc
->pipe
;
3498 u32 reg
, temp
, i
, retry
;
3500 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3502 reg
= FDI_RX_IMR(pipe
);
3503 temp
= I915_READ(reg
);
3504 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3505 temp
&= ~FDI_RX_BIT_LOCK
;
3506 I915_WRITE(reg
, temp
);
3511 /* enable CPU FDI TX and PCH FDI RX */
3512 reg
= FDI_TX_CTL(pipe
);
3513 temp
= I915_READ(reg
);
3514 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3515 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3516 temp
&= ~FDI_LINK_TRAIN_NONE
;
3517 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3518 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3520 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3521 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3523 I915_WRITE(FDI_RX_MISC(pipe
),
3524 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3526 reg
= FDI_RX_CTL(pipe
);
3527 temp
= I915_READ(reg
);
3528 if (HAS_PCH_CPT(dev
)) {
3529 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3530 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3532 temp
&= ~FDI_LINK_TRAIN_NONE
;
3533 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3535 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3540 for (i
= 0; i
< 4; i
++) {
3541 reg
= FDI_TX_CTL(pipe
);
3542 temp
= I915_READ(reg
);
3543 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3544 temp
|= snb_b_fdi_train_param
[i
];
3545 I915_WRITE(reg
, temp
);
3550 for (retry
= 0; retry
< 5; retry
++) {
3551 reg
= FDI_RX_IIR(pipe
);
3552 temp
= I915_READ(reg
);
3553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3554 if (temp
& FDI_RX_BIT_LOCK
) {
3555 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3556 DRM_DEBUG_KMS("FDI train 1 done.\n");
3565 DRM_ERROR("FDI train 1 fail!\n");
3568 reg
= FDI_TX_CTL(pipe
);
3569 temp
= I915_READ(reg
);
3570 temp
&= ~FDI_LINK_TRAIN_NONE
;
3571 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3573 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3575 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3577 I915_WRITE(reg
, temp
);
3579 reg
= FDI_RX_CTL(pipe
);
3580 temp
= I915_READ(reg
);
3581 if (HAS_PCH_CPT(dev
)) {
3582 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3583 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3585 temp
&= ~FDI_LINK_TRAIN_NONE
;
3586 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3588 I915_WRITE(reg
, temp
);
3593 for (i
= 0; i
< 4; i
++) {
3594 reg
= FDI_TX_CTL(pipe
);
3595 temp
= I915_READ(reg
);
3596 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3597 temp
|= snb_b_fdi_train_param
[i
];
3598 I915_WRITE(reg
, temp
);
3603 for (retry
= 0; retry
< 5; retry
++) {
3604 reg
= FDI_RX_IIR(pipe
);
3605 temp
= I915_READ(reg
);
3606 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3607 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3608 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3609 DRM_DEBUG_KMS("FDI train 2 done.\n");
3618 DRM_ERROR("FDI train 2 fail!\n");
3620 DRM_DEBUG_KMS("FDI train done.\n");
3623 /* Manual link training for Ivy Bridge A0 parts */
3624 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3626 struct drm_device
*dev
= crtc
->dev
;
3627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3628 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3629 int pipe
= intel_crtc
->pipe
;
3630 u32 reg
, temp
, i
, j
;
3632 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3634 reg
= FDI_RX_IMR(pipe
);
3635 temp
= I915_READ(reg
);
3636 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3637 temp
&= ~FDI_RX_BIT_LOCK
;
3638 I915_WRITE(reg
, temp
);
3643 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3644 I915_READ(FDI_RX_IIR(pipe
)));
3646 /* Try each vswing and preemphasis setting twice before moving on */
3647 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3648 /* disable first in case we need to retry */
3649 reg
= FDI_TX_CTL(pipe
);
3650 temp
= I915_READ(reg
);
3651 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3652 temp
&= ~FDI_TX_ENABLE
;
3653 I915_WRITE(reg
, temp
);
3655 reg
= FDI_RX_CTL(pipe
);
3656 temp
= I915_READ(reg
);
3657 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3658 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3659 temp
&= ~FDI_RX_ENABLE
;
3660 I915_WRITE(reg
, temp
);
3662 /* enable CPU FDI TX and PCH FDI RX */
3663 reg
= FDI_TX_CTL(pipe
);
3664 temp
= I915_READ(reg
);
3665 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3666 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3667 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3668 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3669 temp
|= snb_b_fdi_train_param
[j
/2];
3670 temp
|= FDI_COMPOSITE_SYNC
;
3671 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3673 I915_WRITE(FDI_RX_MISC(pipe
),
3674 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3676 reg
= FDI_RX_CTL(pipe
);
3677 temp
= I915_READ(reg
);
3678 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3679 temp
|= FDI_COMPOSITE_SYNC
;
3680 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3683 udelay(1); /* should be 0.5us */
3685 for (i
= 0; i
< 4; i
++) {
3686 reg
= FDI_RX_IIR(pipe
);
3687 temp
= I915_READ(reg
);
3688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3690 if (temp
& FDI_RX_BIT_LOCK
||
3691 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3692 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3693 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3697 udelay(1); /* should be 0.5us */
3700 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3705 reg
= FDI_TX_CTL(pipe
);
3706 temp
= I915_READ(reg
);
3707 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3708 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3709 I915_WRITE(reg
, temp
);
3711 reg
= FDI_RX_CTL(pipe
);
3712 temp
= I915_READ(reg
);
3713 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3714 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3715 I915_WRITE(reg
, temp
);
3718 udelay(2); /* should be 1.5us */
3720 for (i
= 0; i
< 4; i
++) {
3721 reg
= FDI_RX_IIR(pipe
);
3722 temp
= I915_READ(reg
);
3723 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3725 if (temp
& FDI_RX_SYMBOL_LOCK
||
3726 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3727 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3728 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3732 udelay(2); /* should be 1.5us */
3735 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3739 DRM_DEBUG_KMS("FDI train done.\n");
3742 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3744 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3746 int pipe
= intel_crtc
->pipe
;
3750 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3751 reg
= FDI_RX_CTL(pipe
);
3752 temp
= I915_READ(reg
);
3753 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3754 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3755 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3756 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3761 /* Switch from Rawclk to PCDclk */
3762 temp
= I915_READ(reg
);
3763 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3768 /* Enable CPU FDI TX PLL, always on for Ironlake */
3769 reg
= FDI_TX_CTL(pipe
);
3770 temp
= I915_READ(reg
);
3771 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3772 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3779 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3781 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3783 int pipe
= intel_crtc
->pipe
;
3786 /* Switch from PCDclk to Rawclk */
3787 reg
= FDI_RX_CTL(pipe
);
3788 temp
= I915_READ(reg
);
3789 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3791 /* Disable CPU FDI TX PLL */
3792 reg
= FDI_TX_CTL(pipe
);
3793 temp
= I915_READ(reg
);
3794 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3799 reg
= FDI_RX_CTL(pipe
);
3800 temp
= I915_READ(reg
);
3801 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3803 /* Wait for the clocks to turn off. */
3808 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3810 struct drm_device
*dev
= crtc
->dev
;
3811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3812 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3813 int pipe
= intel_crtc
->pipe
;
3816 /* disable CPU FDI tx and PCH FDI rx */
3817 reg
= FDI_TX_CTL(pipe
);
3818 temp
= I915_READ(reg
);
3819 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3822 reg
= FDI_RX_CTL(pipe
);
3823 temp
= I915_READ(reg
);
3824 temp
&= ~(0x7 << 16);
3825 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3826 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3831 /* Ironlake workaround, disable clock pointer after downing FDI */
3832 if (HAS_PCH_IBX(dev
))
3833 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3835 /* still set train pattern 1 */
3836 reg
= FDI_TX_CTL(pipe
);
3837 temp
= I915_READ(reg
);
3838 temp
&= ~FDI_LINK_TRAIN_NONE
;
3839 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3840 I915_WRITE(reg
, temp
);
3842 reg
= FDI_RX_CTL(pipe
);
3843 temp
= I915_READ(reg
);
3844 if (HAS_PCH_CPT(dev
)) {
3845 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3846 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3848 temp
&= ~FDI_LINK_TRAIN_NONE
;
3849 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3851 /* BPC in FDI rx is consistent with that in PIPECONF */
3852 temp
&= ~(0x07 << 16);
3853 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3854 I915_WRITE(reg
, temp
);
3860 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3862 struct intel_crtc
*crtc
;
3864 /* Note that we don't need to be called with mode_config.lock here
3865 * as our list of CRTC objects is static for the lifetime of the
3866 * device and so cannot disappear as we iterate. Similarly, we can
3867 * happily treat the predicates as racy, atomic checks as userspace
3868 * cannot claim and pin a new fb without at least acquring the
3869 * struct_mutex and so serialising with us.
3871 for_each_intel_crtc(dev
, crtc
) {
3872 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3875 if (crtc
->unpin_work
)
3876 intel_wait_for_vblank(dev
, crtc
->pipe
);
3884 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3886 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3887 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3889 /* ensure that the unpin work is consistent wrt ->pending. */
3891 intel_crtc
->unpin_work
= NULL
;
3894 drm_send_vblank_event(intel_crtc
->base
.dev
,
3898 drm_crtc_vblank_put(&intel_crtc
->base
);
3900 wake_up_all(&dev_priv
->pending_flip_queue
);
3901 queue_work(dev_priv
->wq
, &work
->work
);
3903 trace_i915_flip_complete(intel_crtc
->plane
,
3904 work
->pending_flip_obj
);
3907 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3909 struct drm_device
*dev
= crtc
->dev
;
3910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3912 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3913 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3914 !intel_crtc_has_pending_flip(crtc
),
3916 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3918 spin_lock_irq(&dev
->event_lock
);
3919 if (intel_crtc
->unpin_work
) {
3920 WARN_ONCE(1, "Removing stuck page flip\n");
3921 page_flip_completed(intel_crtc
);
3923 spin_unlock_irq(&dev
->event_lock
);
3926 if (crtc
->primary
->fb
) {
3927 mutex_lock(&dev
->struct_mutex
);
3928 intel_finish_fb(crtc
->primary
->fb
);
3929 mutex_unlock(&dev
->struct_mutex
);
3933 /* Program iCLKIP clock to the desired frequency */
3934 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3936 struct drm_device
*dev
= crtc
->dev
;
3937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3938 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3939 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3942 mutex_lock(&dev_priv
->sb_lock
);
3944 /* It is necessary to ungate the pixclk gate prior to programming
3945 * the divisors, and gate it back when it is done.
3947 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3949 /* Disable SSCCTL */
3950 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3951 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3955 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3956 if (clock
== 20000) {
3961 /* The iCLK virtual clock root frequency is in MHz,
3962 * but the adjusted_mode->crtc_clock in in KHz. To get the
3963 * divisors, it is necessary to divide one by another, so we
3964 * convert the virtual clock precision to KHz here for higher
3967 u32 iclk_virtual_root_freq
= 172800 * 1000;
3968 u32 iclk_pi_range
= 64;
3969 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3971 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3972 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3973 pi_value
= desired_divisor
% iclk_pi_range
;
3976 divsel
= msb_divisor_value
- 2;
3977 phaseinc
= pi_value
;
3980 /* This should not happen with any sane values */
3981 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3982 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3984 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3986 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3993 /* Program SSCDIVINTPHASE6 */
3994 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3995 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3996 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3997 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3998 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3999 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4000 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4001 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4003 /* Program SSCAUXDIV */
4004 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4005 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4006 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4007 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4009 /* Enable modulator and associated divider */
4010 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4011 temp
&= ~SBI_SSCCTL_DISABLE
;
4012 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4014 /* Wait for initialization time */
4017 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4019 mutex_unlock(&dev_priv
->sb_lock
);
4022 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
4023 enum pipe pch_transcoder
)
4025 struct drm_device
*dev
= crtc
->base
.dev
;
4026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4027 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4029 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4030 I915_READ(HTOTAL(cpu_transcoder
)));
4031 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4032 I915_READ(HBLANK(cpu_transcoder
)));
4033 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4034 I915_READ(HSYNC(cpu_transcoder
)));
4036 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4037 I915_READ(VTOTAL(cpu_transcoder
)));
4038 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4039 I915_READ(VBLANK(cpu_transcoder
)));
4040 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4041 I915_READ(VSYNC(cpu_transcoder
)));
4042 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4043 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4046 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4051 temp
= I915_READ(SOUTH_CHICKEN1
);
4052 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4056 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4058 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4060 temp
|= FDI_BC_BIFURCATION_SELECT
;
4062 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4063 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4064 POSTING_READ(SOUTH_CHICKEN1
);
4067 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4069 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4071 switch (intel_crtc
->pipe
) {
4075 if (intel_crtc
->config
->fdi_lanes
> 2)
4076 cpt_set_fdi_bc_bifurcation(dev
, false);
4078 cpt_set_fdi_bc_bifurcation(dev
, true);
4082 cpt_set_fdi_bc_bifurcation(dev
, true);
4091 * Enable PCH resources required for PCH ports:
4093 * - FDI training & RX/TX
4094 * - update transcoder timings
4095 * - DP transcoding bits
4098 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4100 struct drm_device
*dev
= crtc
->dev
;
4101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4102 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4103 int pipe
= intel_crtc
->pipe
;
4106 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4108 if (IS_IVYBRIDGE(dev
))
4109 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4111 /* Write the TU size bits before fdi link training, so that error
4112 * detection works. */
4113 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4114 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4116 /* For PCH output, training FDI link */
4117 dev_priv
->display
.fdi_link_train(crtc
);
4119 /* We need to program the right clock selection before writing the pixel
4120 * mutliplier into the DPLL. */
4121 if (HAS_PCH_CPT(dev
)) {
4124 temp
= I915_READ(PCH_DPLL_SEL
);
4125 temp
|= TRANS_DPLL_ENABLE(pipe
);
4126 sel
= TRANS_DPLLB_SEL(pipe
);
4127 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
4131 I915_WRITE(PCH_DPLL_SEL
, temp
);
4134 /* XXX: pch pll's can be enabled any time before we enable the PCH
4135 * transcoder, and we actually should do this to not upset any PCH
4136 * transcoder that already use the clock when we share it.
4138 * Note that enable_shared_dpll tries to do the right thing, but
4139 * get_shared_dpll unconditionally resets the pll - we need that to have
4140 * the right LVDS enable sequence. */
4141 intel_enable_shared_dpll(intel_crtc
);
4143 /* set transcoder timing, panel must allow it */
4144 assert_panel_unlocked(dev_priv
, pipe
);
4145 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4147 intel_fdi_normal_train(crtc
);
4149 /* For PCH DP, enable TRANS_DP_CTL */
4150 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4151 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4152 reg
= TRANS_DP_CTL(pipe
);
4153 temp
= I915_READ(reg
);
4154 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4155 TRANS_DP_SYNC_MASK
|
4157 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4158 temp
|= bpc
<< 9; /* same format but at 11:9 */
4160 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
4161 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4162 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
4163 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4165 switch (intel_trans_dp_port_sel(crtc
)) {
4167 temp
|= TRANS_DP_PORT_SEL_B
;
4170 temp
|= TRANS_DP_PORT_SEL_C
;
4173 temp
|= TRANS_DP_PORT_SEL_D
;
4179 I915_WRITE(reg
, temp
);
4182 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4185 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4187 struct drm_device
*dev
= crtc
->dev
;
4188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4189 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4190 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4192 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4194 lpt_program_iclkip(crtc
);
4196 /* Set transcoder timing. */
4197 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4199 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4202 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
4204 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
4209 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
4210 WARN(1, "bad %s crtc mask\n", pll
->name
);
4214 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
4215 if (pll
->config
.crtc_mask
== 0) {
4217 WARN_ON(pll
->active
);
4220 crtc
->config
->shared_dpll
= DPLL_ID_PRIVATE
;
4223 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
4224 struct intel_crtc_state
*crtc_state
)
4226 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
4227 struct intel_shared_dpll
*pll
;
4228 enum intel_dpll_id i
;
4230 if (HAS_PCH_IBX(dev_priv
->dev
)) {
4231 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4232 i
= (enum intel_dpll_id
) crtc
->pipe
;
4233 pll
= &dev_priv
->shared_dplls
[i
];
4235 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236 crtc
->base
.base
.id
, pll
->name
);
4238 WARN_ON(pll
->new_config
->crtc_mask
);
4243 if (IS_BROXTON(dev_priv
->dev
)) {
4244 /* PLL is attached to port in bxt */
4245 struct intel_encoder
*encoder
;
4246 struct intel_digital_port
*intel_dig_port
;
4248 encoder
= intel_ddi_get_crtc_new_encoder(crtc_state
);
4249 if (WARN_ON(!encoder
))
4252 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
4253 /* 1:1 mapping between ports and PLLs */
4254 i
= (enum intel_dpll_id
)intel_dig_port
->port
;
4255 pll
= &dev_priv
->shared_dplls
[i
];
4256 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4257 crtc
->base
.base
.id
, pll
->name
);
4258 WARN_ON(pll
->new_config
->crtc_mask
);
4263 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4264 pll
= &dev_priv
->shared_dplls
[i
];
4266 /* Only want to check enabled timings first */
4267 if (pll
->new_config
->crtc_mask
== 0)
4270 if (memcmp(&crtc_state
->dpll_hw_state
,
4271 &pll
->new_config
->hw_state
,
4272 sizeof(pll
->new_config
->hw_state
)) == 0) {
4273 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4274 crtc
->base
.base
.id
, pll
->name
,
4275 pll
->new_config
->crtc_mask
,
4281 /* Ok no matching timings, maybe there's a free one? */
4282 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4283 pll
= &dev_priv
->shared_dplls
[i
];
4284 if (pll
->new_config
->crtc_mask
== 0) {
4285 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4286 crtc
->base
.base
.id
, pll
->name
);
4294 if (pll
->new_config
->crtc_mask
== 0)
4295 pll
->new_config
->hw_state
= crtc_state
->dpll_hw_state
;
4297 crtc_state
->shared_dpll
= i
;
4298 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
4299 pipe_name(crtc
->pipe
));
4301 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
4307 * intel_shared_dpll_start_config - start a new PLL staged config
4308 * @dev_priv: DRM device
4309 * @clear_pipes: mask of pipes that will have their PLLs freed
4311 * Starts a new PLL staged config, copying the current config but
4312 * releasing the references of pipes specified in clear_pipes.
4314 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
4315 unsigned clear_pipes
)
4317 struct intel_shared_dpll
*pll
;
4318 enum intel_dpll_id i
;
4320 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4321 pll
= &dev_priv
->shared_dplls
[i
];
4323 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
4325 if (!pll
->new_config
)
4328 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
4335 pll
= &dev_priv
->shared_dplls
[i
];
4336 kfree(pll
->new_config
);
4337 pll
->new_config
= NULL
;
4343 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
4345 struct intel_shared_dpll
*pll
;
4346 enum intel_dpll_id i
;
4348 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4349 pll
= &dev_priv
->shared_dplls
[i
];
4351 WARN_ON(pll
->new_config
== &pll
->config
);
4353 pll
->config
= *pll
->new_config
;
4354 kfree(pll
->new_config
);
4355 pll
->new_config
= NULL
;
4359 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
4361 struct intel_shared_dpll
*pll
;
4362 enum intel_dpll_id i
;
4364 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4365 pll
= &dev_priv
->shared_dplls
[i
];
4367 WARN_ON(pll
->new_config
== &pll
->config
);
4369 kfree(pll
->new_config
);
4370 pll
->new_config
= NULL
;
4374 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4377 int dslreg
= PIPEDSL(pipe
);
4380 temp
= I915_READ(dslreg
);
4382 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4383 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4384 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4389 * skl_update_scaler_users - Stages update to crtc's scaler state
4391 * @crtc_state: crtc_state
4392 * @plane: plane (NULL indicates crtc is requesting update)
4393 * @plane_state: plane's state
4394 * @force_detach: request unconditional detachment of scaler
4396 * This function updates scaler state for requested plane or crtc.
4397 * To request scaler usage update for a plane, caller shall pass plane pointer.
4398 * To request scaler usage update for crtc, caller shall pass plane pointer
4402 * 0 - scaler_usage updated successfully
4403 * error - requested scaling cannot be supported or other error condition
4406 skl_update_scaler_users(
4407 struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
,
4408 struct intel_plane
*intel_plane
, struct intel_plane_state
*plane_state
,
4413 int src_w
, src_h
, dst_w
, dst_h
;
4415 struct drm_framebuffer
*fb
;
4416 struct intel_crtc_scaler_state
*scaler_state
;
4417 unsigned int rotation
;
4419 if (!intel_crtc
|| !crtc_state
)
4422 scaler_state
= &crtc_state
->scaler_state
;
4424 idx
= intel_plane
? drm_plane_index(&intel_plane
->base
) : SKL_CRTC_INDEX
;
4425 fb
= intel_plane
? plane_state
->base
.fb
: NULL
;
4428 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
4429 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
4430 dst_w
= drm_rect_width(&plane_state
->dst
);
4431 dst_h
= drm_rect_height(&plane_state
->dst
);
4432 scaler_id
= &plane_state
->scaler_id
;
4433 rotation
= plane_state
->base
.rotation
;
4435 struct drm_display_mode
*adjusted_mode
=
4436 &crtc_state
->base
.adjusted_mode
;
4437 src_w
= crtc_state
->pipe_src_w
;
4438 src_h
= crtc_state
->pipe_src_h
;
4439 dst_w
= adjusted_mode
->hdisplay
;
4440 dst_h
= adjusted_mode
->vdisplay
;
4441 scaler_id
= &scaler_state
->scaler_id
;
4442 rotation
= DRM_ROTATE_0
;
4445 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4446 (src_h
!= dst_w
|| src_w
!= dst_h
):
4447 (src_w
!= dst_w
|| src_h
!= dst_h
);
4450 * if plane is being disabled or scaler is no more required or force detach
4451 * - free scaler binded to this plane/crtc
4452 * - in order to do this, update crtc->scaler_usage
4454 * Here scaler state in crtc_state is set free so that
4455 * scaler can be assigned to other user. Actual register
4456 * update to free the scaler is done in plane/panel-fit programming.
4457 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4459 if (force_detach
|| !need_scaling
|| (intel_plane
&&
4460 (!fb
|| !plane_state
->visible
))) {
4461 if (*scaler_id
>= 0) {
4462 scaler_state
->scaler_users
&= ~(1 << idx
);
4463 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4465 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4466 "crtc_state = %p scaler_users = 0x%x\n",
4467 intel_crtc
->pipe
, *scaler_id
, intel_plane
? "PLANE" : "CRTC",
4468 intel_plane
? intel_plane
->base
.base
.id
:
4469 intel_crtc
->base
.base
.id
, crtc_state
,
4470 scaler_state
->scaler_users
);
4477 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4478 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4480 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4481 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4482 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4483 "size is out of scaler range\n",
4484 intel_plane
? "PLANE" : "CRTC",
4485 intel_plane
? intel_plane
->base
.base
.id
: intel_crtc
->base
.base
.id
,
4486 intel_crtc
->pipe
, idx
, src_w
, src_h
, dst_w
, dst_h
);
4490 /* check colorkey */
4491 if (WARN_ON(intel_plane
&&
4492 intel_plane
->ckey
.flags
!= I915_SET_COLORKEY_NONE
)) {
4493 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4494 intel_plane
->base
.base
.id
, src_w
, src_h
, dst_w
, dst_h
);
4498 /* Check src format */
4500 switch (fb
->pixel_format
) {
4501 case DRM_FORMAT_RGB565
:
4502 case DRM_FORMAT_XBGR8888
:
4503 case DRM_FORMAT_XRGB8888
:
4504 case DRM_FORMAT_ABGR8888
:
4505 case DRM_FORMAT_ARGB8888
:
4506 case DRM_FORMAT_XRGB2101010
:
4507 case DRM_FORMAT_XBGR2101010
:
4508 case DRM_FORMAT_YUYV
:
4509 case DRM_FORMAT_YVYU
:
4510 case DRM_FORMAT_UYVY
:
4511 case DRM_FORMAT_VYUY
:
4514 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4515 intel_plane
->base
.base
.id
, fb
->base
.id
, fb
->pixel_format
);
4520 /* mark this plane as a scaler user in crtc_state */
4521 scaler_state
->scaler_users
|= (1 << idx
);
4522 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4523 "crtc_state = %p scaler_users = 0x%x\n",
4524 intel_plane
? "PLANE" : "CRTC",
4525 intel_plane
? intel_plane
->base
.base
.id
: intel_crtc
->base
.base
.id
,
4526 src_w
, src_h
, dst_w
, dst_h
, crtc_state
, scaler_state
->scaler_users
);
4530 static void skylake_pfit_update(struct intel_crtc
*crtc
, int enable
)
4532 struct drm_device
*dev
= crtc
->base
.dev
;
4533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4534 int pipe
= crtc
->pipe
;
4535 struct intel_crtc_scaler_state
*scaler_state
=
4536 &crtc
->config
->scaler_state
;
4538 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4540 /* To update pfit, first update scaler state */
4541 skl_update_scaler_users(crtc
, crtc
->config
, NULL
, NULL
, !enable
);
4542 intel_atomic_setup_scalers(crtc
->base
.dev
, crtc
, crtc
->config
);
4543 skl_detach_scalers(crtc
);
4547 if (crtc
->config
->pch_pfit
.enabled
) {
4550 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4551 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4555 id
= scaler_state
->scaler_id
;
4556 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4557 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4558 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4559 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4561 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4565 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4567 struct drm_device
*dev
= crtc
->base
.dev
;
4568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4569 int pipe
= crtc
->pipe
;
4571 if (crtc
->config
->pch_pfit
.enabled
) {
4572 /* Force use of hard-coded filter coefficients
4573 * as some pre-programmed values are broken,
4576 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4577 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4578 PF_PIPE_SEL_IVB(pipe
));
4580 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4581 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4582 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4586 static void intel_enable_sprite_planes(struct drm_crtc
*crtc
)
4588 struct drm_device
*dev
= crtc
->dev
;
4589 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4590 struct drm_plane
*plane
;
4591 struct intel_plane
*intel_plane
;
4593 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4594 intel_plane
= to_intel_plane(plane
);
4595 if (intel_plane
->pipe
== pipe
)
4596 intel_plane_restore(&intel_plane
->base
);
4600 void hsw_enable_ips(struct intel_crtc
*crtc
)
4602 struct drm_device
*dev
= crtc
->base
.dev
;
4603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4605 if (!crtc
->config
->ips_enabled
)
4608 /* We can only enable IPS after we enable a plane and wait for a vblank */
4609 intel_wait_for_vblank(dev
, crtc
->pipe
);
4611 assert_plane_enabled(dev_priv
, crtc
->plane
);
4612 if (IS_BROADWELL(dev
)) {
4613 mutex_lock(&dev_priv
->rps
.hw_lock
);
4614 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4615 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4616 /* Quoting Art Runyan: "its not safe to expect any particular
4617 * value in IPS_CTL bit 31 after enabling IPS through the
4618 * mailbox." Moreover, the mailbox may return a bogus state,
4619 * so we need to just enable it and continue on.
4622 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4623 /* The bit only becomes 1 in the next vblank, so this wait here
4624 * is essentially intel_wait_for_vblank. If we don't have this
4625 * and don't wait for vblanks until the end of crtc_enable, then
4626 * the HW state readout code will complain that the expected
4627 * IPS_CTL value is not the one we read. */
4628 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4629 DRM_ERROR("Timed out waiting for IPS enable\n");
4633 void hsw_disable_ips(struct intel_crtc
*crtc
)
4635 struct drm_device
*dev
= crtc
->base
.dev
;
4636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4638 if (!crtc
->config
->ips_enabled
)
4641 assert_plane_enabled(dev_priv
, crtc
->plane
);
4642 if (IS_BROADWELL(dev
)) {
4643 mutex_lock(&dev_priv
->rps
.hw_lock
);
4644 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4645 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4646 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4647 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4648 DRM_ERROR("Timed out waiting for IPS disable\n");
4650 I915_WRITE(IPS_CTL
, 0);
4651 POSTING_READ(IPS_CTL
);
4654 /* We need to wait for a vblank before we can disable the plane. */
4655 intel_wait_for_vblank(dev
, crtc
->pipe
);
4658 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4659 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4661 struct drm_device
*dev
= crtc
->dev
;
4662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4663 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4664 enum pipe pipe
= intel_crtc
->pipe
;
4665 int palreg
= PALETTE(pipe
);
4667 bool reenable_ips
= false;
4669 /* The clocks have to be on to load the palette. */
4670 if (!crtc
->state
->enable
|| !intel_crtc
->active
)
4673 if (HAS_GMCH_DISPLAY(dev_priv
->dev
)) {
4674 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4675 assert_dsi_pll_enabled(dev_priv
);
4677 assert_pll_enabled(dev_priv
, pipe
);
4680 /* use legacy palette for Ironlake */
4681 if (!HAS_GMCH_DISPLAY(dev
))
4682 palreg
= LGC_PALETTE(pipe
);
4684 /* Workaround : Do not read or write the pipe palette/gamma data while
4685 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4687 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4688 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4689 GAMMA_MODE_MODE_SPLIT
)) {
4690 hsw_disable_ips(intel_crtc
);
4691 reenable_ips
= true;
4694 for (i
= 0; i
< 256; i
++) {
4695 I915_WRITE(palreg
+ 4 * i
,
4696 (intel_crtc
->lut_r
[i
] << 16) |
4697 (intel_crtc
->lut_g
[i
] << 8) |
4698 intel_crtc
->lut_b
[i
]);
4702 hsw_enable_ips(intel_crtc
);
4705 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4707 if (intel_crtc
->overlay
) {
4708 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4711 mutex_lock(&dev
->struct_mutex
);
4712 dev_priv
->mm
.interruptible
= false;
4713 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4714 dev_priv
->mm
.interruptible
= true;
4715 mutex_unlock(&dev
->struct_mutex
);
4718 /* Let userspace switch the overlay on again. In most cases userspace
4719 * has to recompute where to put it anyway.
4724 * intel_post_enable_primary - Perform operations after enabling primary plane
4725 * @crtc: the CRTC whose primary plane was just enabled
4727 * Performs potentially sleeping operations that must be done after the primary
4728 * plane is enabled, such as updating FBC and IPS. Note that this may be
4729 * called due to an explicit primary plane update, or due to an implicit
4730 * re-enable that is caused when a sprite plane is updated to no longer
4731 * completely hide the primary plane.
4734 intel_post_enable_primary(struct drm_crtc
*crtc
)
4736 struct drm_device
*dev
= crtc
->dev
;
4737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4738 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4739 int pipe
= intel_crtc
->pipe
;
4742 * BDW signals flip done immediately if the plane
4743 * is disabled, even if the plane enable is already
4744 * armed to occur at the next vblank :(
4746 if (IS_BROADWELL(dev
))
4747 intel_wait_for_vblank(dev
, pipe
);
4750 * FIXME IPS should be fine as long as one plane is
4751 * enabled, but in practice it seems to have problems
4752 * when going from primary only to sprite only and vice
4755 hsw_enable_ips(intel_crtc
);
4757 mutex_lock(&dev
->struct_mutex
);
4758 intel_fbc_update(dev
);
4759 mutex_unlock(&dev
->struct_mutex
);
4762 * Gen2 reports pipe underruns whenever all planes are disabled.
4763 * So don't enable underrun reporting before at least some planes
4765 * FIXME: Need to fix the logic to work when we turn off all planes
4766 * but leave the pipe running.
4769 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4771 /* Underruns don't raise interrupts, so check manually. */
4772 if (HAS_GMCH_DISPLAY(dev
))
4773 i9xx_check_fifo_underruns(dev_priv
);
4777 * intel_pre_disable_primary - Perform operations before disabling primary plane
4778 * @crtc: the CRTC whose primary plane is to be disabled
4780 * Performs potentially sleeping operations that must be done before the
4781 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4782 * be called due to an explicit primary plane update, or due to an implicit
4783 * disable that is caused when a sprite plane completely hides the primary
4787 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4789 struct drm_device
*dev
= crtc
->dev
;
4790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4791 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4792 int pipe
= intel_crtc
->pipe
;
4795 * Gen2 reports pipe underruns whenever all planes are disabled.
4796 * So diasble underrun reporting before all the planes get disabled.
4797 * FIXME: Need to fix the logic to work when we turn off all planes
4798 * but leave the pipe running.
4801 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4804 * Vblank time updates from the shadow to live plane control register
4805 * are blocked if the memory self-refresh mode is active at that
4806 * moment. So to make sure the plane gets truly disabled, disable
4807 * first the self-refresh mode. The self-refresh enable bit in turn
4808 * will be checked/applied by the HW only at the next frame start
4809 * event which is after the vblank start event, so we need to have a
4810 * wait-for-vblank between disabling the plane and the pipe.
4812 if (HAS_GMCH_DISPLAY(dev
))
4813 intel_set_memory_cxsr(dev_priv
, false);
4815 mutex_lock(&dev
->struct_mutex
);
4816 if (dev_priv
->fbc
.crtc
== intel_crtc
)
4817 intel_fbc_disable(dev
);
4818 mutex_unlock(&dev
->struct_mutex
);
4821 * FIXME IPS should be fine as long as one plane is
4822 * enabled, but in practice it seems to have problems
4823 * when going from primary only to sprite only and vice
4826 hsw_disable_ips(intel_crtc
);
4829 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4831 struct drm_device
*dev
= crtc
->dev
;
4832 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4833 int pipe
= intel_crtc
->pipe
;
4835 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4836 intel_enable_sprite_planes(crtc
);
4837 intel_crtc_update_cursor(crtc
, true);
4839 intel_post_enable_primary(crtc
);
4842 * FIXME: Once we grow proper nuclear flip support out of this we need
4843 * to compute the mask of flip planes precisely. For the time being
4844 * consider this a flip to a NULL plane.
4846 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4849 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4851 struct drm_device
*dev
= crtc
->dev
;
4852 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4853 struct intel_plane
*intel_plane
;
4854 int pipe
= intel_crtc
->pipe
;
4856 intel_crtc_wait_for_pending_flips(crtc
);
4858 intel_pre_disable_primary(crtc
);
4860 intel_crtc_dpms_overlay_disable(intel_crtc
);
4861 for_each_intel_plane(dev
, intel_plane
) {
4862 if (intel_plane
->pipe
== pipe
) {
4863 struct drm_crtc
*from
= intel_plane
->base
.crtc
;
4865 intel_plane
->disable_plane(&intel_plane
->base
,
4866 from
?: crtc
, true);
4871 * FIXME: Once we grow proper nuclear flip support out of this we need
4872 * to compute the mask of flip planes precisely. For the time being
4873 * consider this a flip to a NULL plane.
4875 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4878 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4880 struct drm_device
*dev
= crtc
->dev
;
4881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4882 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4883 struct intel_encoder
*encoder
;
4884 int pipe
= intel_crtc
->pipe
;
4886 WARN_ON(!crtc
->state
->enable
);
4888 if (intel_crtc
->active
)
4891 if (intel_crtc
->config
->has_pch_encoder
)
4892 intel_prepare_shared_dpll(intel_crtc
);
4894 if (intel_crtc
->config
->has_dp_encoder
)
4895 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4897 intel_set_pipe_timings(intel_crtc
);
4899 if (intel_crtc
->config
->has_pch_encoder
) {
4900 intel_cpu_transcoder_set_m_n(intel_crtc
,
4901 &intel_crtc
->config
->fdi_m_n
, NULL
);
4904 ironlake_set_pipeconf(crtc
);
4906 intel_crtc
->active
= true;
4908 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4909 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4911 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4912 if (encoder
->pre_enable
)
4913 encoder
->pre_enable(encoder
);
4915 if (intel_crtc
->config
->has_pch_encoder
) {
4916 /* Note: FDI PLL enabling _must_ be done before we enable the
4917 * cpu pipes, hence this is separate from all the other fdi/pch
4919 ironlake_fdi_pll_enable(intel_crtc
);
4921 assert_fdi_tx_disabled(dev_priv
, pipe
);
4922 assert_fdi_rx_disabled(dev_priv
, pipe
);
4925 ironlake_pfit_enable(intel_crtc
);
4928 * On ILK+ LUT must be loaded before the pipe is running but with
4931 intel_crtc_load_lut(crtc
);
4933 intel_update_watermarks(crtc
);
4934 intel_enable_pipe(intel_crtc
);
4936 if (intel_crtc
->config
->has_pch_encoder
)
4937 ironlake_pch_enable(crtc
);
4939 assert_vblank_disabled(crtc
);
4940 drm_crtc_vblank_on(crtc
);
4942 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4943 encoder
->enable(encoder
);
4945 if (HAS_PCH_CPT(dev
))
4946 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4949 /* IPS only exists on ULT machines and is tied to pipe A. */
4950 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4952 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4956 * This implements the workaround described in the "notes" section of the mode
4957 * set sequence documentation. When going from no pipes or single pipe to
4958 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4959 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4961 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4963 struct drm_device
*dev
= crtc
->base
.dev
;
4964 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4966 /* We want to get the other_active_crtc only if there's only 1 other
4968 for_each_intel_crtc(dev
, crtc_it
) {
4969 if (!crtc_it
->active
|| crtc_it
== crtc
)
4972 if (other_active_crtc
)
4975 other_active_crtc
= crtc_it
;
4977 if (!other_active_crtc
)
4980 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4981 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4984 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4986 struct drm_device
*dev
= crtc
->dev
;
4987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4988 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4989 struct intel_encoder
*encoder
;
4990 int pipe
= intel_crtc
->pipe
;
4992 WARN_ON(!crtc
->state
->enable
);
4994 if (intel_crtc
->active
)
4997 if (intel_crtc_to_shared_dpll(intel_crtc
))
4998 intel_enable_shared_dpll(intel_crtc
);
5000 if (intel_crtc
->config
->has_dp_encoder
)
5001 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5003 intel_set_pipe_timings(intel_crtc
);
5005 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
5006 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
5007 intel_crtc
->config
->pixel_multiplier
- 1);
5010 if (intel_crtc
->config
->has_pch_encoder
) {
5011 intel_cpu_transcoder_set_m_n(intel_crtc
,
5012 &intel_crtc
->config
->fdi_m_n
, NULL
);
5015 haswell_set_pipeconf(crtc
);
5017 intel_set_pipe_csc(crtc
);
5019 intel_crtc
->active
= true;
5021 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5022 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5023 if (encoder
->pre_enable
)
5024 encoder
->pre_enable(encoder
);
5026 if (intel_crtc
->config
->has_pch_encoder
) {
5027 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5029 dev_priv
->display
.fdi_link_train(crtc
);
5032 intel_ddi_enable_pipe_clock(intel_crtc
);
5034 if (INTEL_INFO(dev
)->gen
== 9)
5035 skylake_pfit_update(intel_crtc
, 1);
5036 else if (INTEL_INFO(dev
)->gen
< 9)
5037 ironlake_pfit_enable(intel_crtc
);
5039 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5042 * On ILK+ LUT must be loaded before the pipe is running but with
5045 intel_crtc_load_lut(crtc
);
5047 intel_ddi_set_pipe_settings(crtc
);
5048 intel_ddi_enable_transcoder_func(crtc
);
5050 intel_update_watermarks(crtc
);
5051 intel_enable_pipe(intel_crtc
);
5053 if (intel_crtc
->config
->has_pch_encoder
)
5054 lpt_pch_enable(crtc
);
5056 if (intel_crtc
->config
->dp_encoder_is_mst
)
5057 intel_ddi_set_vc_payload_alloc(crtc
, true);
5059 assert_vblank_disabled(crtc
);
5060 drm_crtc_vblank_on(crtc
);
5062 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5063 encoder
->enable(encoder
);
5064 intel_opregion_notify_encoder(encoder
, true);
5067 /* If we change the relative order between pipe/planes enabling, we need
5068 * to change the workaround. */
5069 haswell_mode_set_planes_workaround(intel_crtc
);
5072 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
5074 struct drm_device
*dev
= crtc
->base
.dev
;
5075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5076 int pipe
= crtc
->pipe
;
5078 /* To avoid upsetting the power well on haswell only disable the pfit if
5079 * it's in use. The hw state code will make sure we get this right. */
5080 if (crtc
->config
->pch_pfit
.enabled
) {
5081 I915_WRITE(PF_CTL(pipe
), 0);
5082 I915_WRITE(PF_WIN_POS(pipe
), 0);
5083 I915_WRITE(PF_WIN_SZ(pipe
), 0);
5087 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
5089 struct drm_device
*dev
= crtc
->dev
;
5090 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5091 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5092 struct intel_encoder
*encoder
;
5093 int pipe
= intel_crtc
->pipe
;
5096 if (!intel_crtc
->active
)
5099 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5100 encoder
->disable(encoder
);
5102 drm_crtc_vblank_off(crtc
);
5103 assert_vblank_disabled(crtc
);
5105 if (intel_crtc
->config
->has_pch_encoder
)
5106 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5108 intel_disable_pipe(intel_crtc
);
5110 ironlake_pfit_disable(intel_crtc
);
5112 if (intel_crtc
->config
->has_pch_encoder
)
5113 ironlake_fdi_disable(crtc
);
5115 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5116 if (encoder
->post_disable
)
5117 encoder
->post_disable(encoder
);
5119 if (intel_crtc
->config
->has_pch_encoder
) {
5120 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5122 if (HAS_PCH_CPT(dev
)) {
5123 /* disable TRANS_DP_CTL */
5124 reg
= TRANS_DP_CTL(pipe
);
5125 temp
= I915_READ(reg
);
5126 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5127 TRANS_DP_PORT_SEL_MASK
);
5128 temp
|= TRANS_DP_PORT_SEL_NONE
;
5129 I915_WRITE(reg
, temp
);
5131 /* disable DPLL_SEL */
5132 temp
= I915_READ(PCH_DPLL_SEL
);
5133 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5134 I915_WRITE(PCH_DPLL_SEL
, temp
);
5137 /* disable PCH DPLL */
5138 intel_disable_shared_dpll(intel_crtc
);
5140 ironlake_fdi_pll_disable(intel_crtc
);
5143 intel_crtc
->active
= false;
5144 intel_update_watermarks(crtc
);
5146 mutex_lock(&dev
->struct_mutex
);
5147 intel_fbc_update(dev
);
5148 mutex_unlock(&dev
->struct_mutex
);
5151 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5153 struct drm_device
*dev
= crtc
->dev
;
5154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5155 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5156 struct intel_encoder
*encoder
;
5157 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5159 if (!intel_crtc
->active
)
5162 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5163 intel_opregion_notify_encoder(encoder
, false);
5164 encoder
->disable(encoder
);
5167 drm_crtc_vblank_off(crtc
);
5168 assert_vblank_disabled(crtc
);
5170 if (intel_crtc
->config
->has_pch_encoder
)
5171 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5173 intel_disable_pipe(intel_crtc
);
5175 if (intel_crtc
->config
->dp_encoder_is_mst
)
5176 intel_ddi_set_vc_payload_alloc(crtc
, false);
5178 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5180 if (INTEL_INFO(dev
)->gen
== 9)
5181 skylake_pfit_update(intel_crtc
, 0);
5182 else if (INTEL_INFO(dev
)->gen
< 9)
5183 ironlake_pfit_disable(intel_crtc
);
5185 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5187 intel_ddi_disable_pipe_clock(intel_crtc
);
5189 if (intel_crtc
->config
->has_pch_encoder
) {
5190 lpt_disable_pch_transcoder(dev_priv
);
5191 intel_ddi_fdi_disable(crtc
);
5194 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5195 if (encoder
->post_disable
)
5196 encoder
->post_disable(encoder
);
5198 intel_crtc
->active
= false;
5199 intel_update_watermarks(crtc
);
5201 mutex_lock(&dev
->struct_mutex
);
5202 intel_fbc_update(dev
);
5203 mutex_unlock(&dev
->struct_mutex
);
5205 if (intel_crtc_to_shared_dpll(intel_crtc
))
5206 intel_disable_shared_dpll(intel_crtc
);
5209 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
5211 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5212 intel_put_shared_dpll(intel_crtc
);
5216 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5218 struct drm_device
*dev
= crtc
->base
.dev
;
5219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5220 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5222 if (!pipe_config
->gmch_pfit
.control
)
5226 * The panel fitter should only be adjusted whilst the pipe is disabled,
5227 * according to register description and PRM.
5229 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5230 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5232 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5233 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5235 /* Border color in case we don't scale up to the full screen. Black by
5236 * default, change to something else for debugging. */
5237 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5240 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5244 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
5246 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
5248 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
5250 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
5253 return POWER_DOMAIN_PORT_OTHER
;
5257 #define for_each_power_domain(domain, mask) \
5258 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5259 if ((1 << (domain)) & (mask))
5261 enum intel_display_power_domain
5262 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5264 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5265 struct intel_digital_port
*intel_dig_port
;
5267 switch (intel_encoder
->type
) {
5268 case INTEL_OUTPUT_UNKNOWN
:
5269 /* Only DDI platforms should ever use this output type */
5270 WARN_ON_ONCE(!HAS_DDI(dev
));
5271 case INTEL_OUTPUT_DISPLAYPORT
:
5272 case INTEL_OUTPUT_HDMI
:
5273 case INTEL_OUTPUT_EDP
:
5274 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5275 return port_to_power_domain(intel_dig_port
->port
);
5276 case INTEL_OUTPUT_DP_MST
:
5277 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5278 return port_to_power_domain(intel_dig_port
->port
);
5279 case INTEL_OUTPUT_ANALOG
:
5280 return POWER_DOMAIN_PORT_CRT
;
5281 case INTEL_OUTPUT_DSI
:
5282 return POWER_DOMAIN_PORT_DSI
;
5284 return POWER_DOMAIN_PORT_OTHER
;
5288 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
5290 struct drm_device
*dev
= crtc
->dev
;
5291 struct intel_encoder
*intel_encoder
;
5292 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5293 enum pipe pipe
= intel_crtc
->pipe
;
5295 enum transcoder transcoder
;
5297 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
5299 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5300 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5301 if (intel_crtc
->config
->pch_pfit
.enabled
||
5302 intel_crtc
->config
->pch_pfit
.force_thru
)
5303 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5305 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5306 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5311 static void modeset_update_crtc_power_domains(struct drm_atomic_state
*state
)
5313 struct drm_device
*dev
= state
->dev
;
5314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5315 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
5316 struct intel_crtc
*crtc
;
5319 * First get all needed power domains, then put all unneeded, to avoid
5320 * any unnecessary toggling of the power wells.
5322 for_each_intel_crtc(dev
, crtc
) {
5323 enum intel_display_power_domain domain
;
5325 if (!crtc
->base
.state
->enable
)
5328 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
5330 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
5331 intel_display_power_get(dev_priv
, domain
);
5334 if (dev_priv
->display
.modeset_global_resources
)
5335 dev_priv
->display
.modeset_global_resources(state
);
5337 for_each_intel_crtc(dev
, crtc
) {
5338 enum intel_display_power_domain domain
;
5340 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
5341 intel_display_power_put(dev_priv
, domain
);
5343 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
5346 intel_display_set_init_power(dev_priv
, false);
5349 static void intel_update_max_cdclk(struct drm_device
*dev
)
5351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5353 if (IS_SKYLAKE(dev
)) {
5354 u32 limit
= I915_READ(SKL_DFSM
) & SKL_DFSM_CDCLK_LIMIT_MASK
;
5356 if (limit
== SKL_DFSM_CDCLK_LIMIT_675
)
5357 dev_priv
->max_cdclk_freq
= 675000;
5358 else if (limit
== SKL_DFSM_CDCLK_LIMIT_540
)
5359 dev_priv
->max_cdclk_freq
= 540000;
5360 else if (limit
== SKL_DFSM_CDCLK_LIMIT_450
)
5361 dev_priv
->max_cdclk_freq
= 450000;
5363 dev_priv
->max_cdclk_freq
= 337500;
5364 } else if (IS_BROADWELL(dev
)) {
5366 * FIXME with extra cooling we can allow
5367 * 540 MHz for ULX and 675 Mhz for ULT.
5368 * How can we know if extra cooling is
5369 * available? PCI ID, VTB, something else?
5371 if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5372 dev_priv
->max_cdclk_freq
= 450000;
5373 else if (IS_BDW_ULX(dev
))
5374 dev_priv
->max_cdclk_freq
= 450000;
5375 else if (IS_BDW_ULT(dev
))
5376 dev_priv
->max_cdclk_freq
= 540000;
5378 dev_priv
->max_cdclk_freq
= 675000;
5379 } else if (IS_VALLEYVIEW(dev
)) {
5380 dev_priv
->max_cdclk_freq
= 400000;
5382 /* otherwise assume cdclk is fixed */
5383 dev_priv
->max_cdclk_freq
= dev_priv
->cdclk_freq
;
5386 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5387 dev_priv
->max_cdclk_freq
);
5390 static void intel_update_cdclk(struct drm_device
*dev
)
5392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5394 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5395 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5396 dev_priv
->cdclk_freq
);
5399 * Program the gmbus_freq based on the cdclk frequency.
5400 * BSpec erroneously claims we should aim for 4MHz, but
5401 * in fact 1MHz is the correct frequency.
5403 if (IS_VALLEYVIEW(dev
)) {
5405 * Program the gmbus_freq based on the cdclk frequency.
5406 * BSpec erroneously claims we should aim for 4MHz, but
5407 * in fact 1MHz is the correct frequency.
5409 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5412 if (dev_priv
->max_cdclk_freq
== 0)
5413 intel_update_max_cdclk(dev
);
5416 static void broxton_set_cdclk(struct drm_device
*dev
, int frequency
)
5418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5421 uint32_t current_freq
;
5424 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5425 switch (frequency
) {
5427 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5428 ratio
= BXT_DE_PLL_RATIO(60);
5431 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5432 ratio
= BXT_DE_PLL_RATIO(60);
5435 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5436 ratio
= BXT_DE_PLL_RATIO(60);
5439 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5440 ratio
= BXT_DE_PLL_RATIO(60);
5443 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5444 ratio
= BXT_DE_PLL_RATIO(65);
5448 * Bypass frequency with DE PLL disabled. Init ratio, divider
5449 * to suppress GCC warning.
5455 DRM_ERROR("unsupported CDCLK freq %d", frequency
);
5460 mutex_lock(&dev_priv
->rps
.hw_lock
);
5461 /* Inform power controller of upcoming frequency change */
5462 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5464 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5467 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5472 current_freq
= I915_READ(CDCLK_CTL
) & CDCLK_FREQ_DECIMAL_MASK
;
5473 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5474 current_freq
= current_freq
* 500 + 1000;
5477 * DE PLL has to be disabled when
5478 * - setting to 19.2MHz (bypass, PLL isn't used)
5479 * - before setting to 624MHz (PLL needs toggling)
5480 * - before setting to any frequency from 624MHz (PLL needs toggling)
5482 if (frequency
== 19200 || frequency
== 624000 ||
5483 current_freq
== 624000) {
5484 I915_WRITE(BXT_DE_PLL_ENABLE
, ~BXT_DE_PLL_PLL_ENABLE
);
5486 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
),
5488 DRM_ERROR("timout waiting for DE PLL unlock\n");
5491 if (frequency
!= 19200) {
5494 val
= I915_READ(BXT_DE_PLL_CTL
);
5495 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5497 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5499 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5501 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
, 1))
5502 DRM_ERROR("timeout waiting for DE PLL lock\n");
5504 val
= I915_READ(CDCLK_CTL
);
5505 val
&= ~BXT_CDCLK_CD2X_DIV_SEL_MASK
;
5508 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5511 val
&= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5512 if (frequency
>= 500000)
5513 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5515 val
&= ~CDCLK_FREQ_DECIMAL_MASK
;
5516 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5517 val
|= (frequency
- 1000) / 500;
5518 I915_WRITE(CDCLK_CTL
, val
);
5521 mutex_lock(&dev_priv
->rps
.hw_lock
);
5522 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5523 DIV_ROUND_UP(frequency
, 25000));
5524 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5527 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5532 dev_priv
->cdclk_freq
= frequency
;
5535 void broxton_init_cdclk(struct drm_device
*dev
)
5537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5541 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5542 * or else the reset will hang because there is no PCH to respond.
5543 * Move the handshake programming to initialization sequence.
5544 * Previously was left up to BIOS.
5546 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5547 val
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5548 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
);
5550 /* Enable PG1 for cdclk */
5551 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5553 /* check if cd clock is enabled */
5554 if (I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_PLL_ENABLE
) {
5555 DRM_DEBUG_KMS("Display already initialized\n");
5561 * - The initial CDCLK needs to be read from VBT.
5562 * Need to make this change after VBT has changes for BXT.
5563 * - check if setting the max (or any) cdclk freq is really necessary
5564 * here, it belongs to modeset time
5566 broxton_set_cdclk(dev
, 624000);
5568 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5569 POSTING_READ(DBUF_CTL
);
5573 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5574 DRM_ERROR("DBuf power enable timeout!\n");
5577 void broxton_uninit_cdclk(struct drm_device
*dev
)
5579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5581 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5582 POSTING_READ(DBUF_CTL
);
5586 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5587 DRM_ERROR("DBuf power disable timeout!\n");
5589 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5590 broxton_set_cdclk(dev
, 19200);
5592 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5595 static const struct skl_cdclk_entry
{
5598 } skl_cdclk_frequencies
[] = {
5599 { .freq
= 308570, .vco
= 8640 },
5600 { .freq
= 337500, .vco
= 8100 },
5601 { .freq
= 432000, .vco
= 8640 },
5602 { .freq
= 450000, .vco
= 8100 },
5603 { .freq
= 540000, .vco
= 8100 },
5604 { .freq
= 617140, .vco
= 8640 },
5605 { .freq
= 675000, .vco
= 8100 },
5608 static unsigned int skl_cdclk_decimal(unsigned int freq
)
5610 return (freq
- 1000) / 500;
5613 static unsigned int skl_cdclk_get_vco(unsigned int freq
)
5617 for (i
= 0; i
< ARRAY_SIZE(skl_cdclk_frequencies
); i
++) {
5618 const struct skl_cdclk_entry
*e
= &skl_cdclk_frequencies
[i
];
5620 if (e
->freq
== freq
)
5628 skl_dpll0_enable(struct drm_i915_private
*dev_priv
, unsigned int required_vco
)
5630 unsigned int min_freq
;
5633 /* select the minimum CDCLK before enabling DPLL 0 */
5634 val
= I915_READ(CDCLK_CTL
);
5635 val
&= ~CDCLK_FREQ_SEL_MASK
| ~CDCLK_FREQ_DECIMAL_MASK
;
5636 val
|= CDCLK_FREQ_337_308
;
5638 if (required_vco
== 8640)
5643 val
= CDCLK_FREQ_337_308
| skl_cdclk_decimal(min_freq
);
5645 I915_WRITE(CDCLK_CTL
, val
);
5646 POSTING_READ(CDCLK_CTL
);
5649 * We always enable DPLL0 with the lowest link rate possible, but still
5650 * taking into account the VCO required to operate the eDP panel at the
5651 * desired frequency. The usual DP link rates operate with a VCO of
5652 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5653 * The modeset code is responsible for the selection of the exact link
5654 * rate later on, with the constraint of choosing a frequency that
5655 * works with required_vco.
5657 val
= I915_READ(DPLL_CTRL1
);
5659 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
5660 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5661 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
5662 if (required_vco
== 8640)
5663 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
5666 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
5669 I915_WRITE(DPLL_CTRL1
, val
);
5670 POSTING_READ(DPLL_CTRL1
);
5672 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
5674 if (wait_for(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
, 5))
5675 DRM_ERROR("DPLL0 not locked\n");
5678 static bool skl_cdclk_pcu_ready(struct drm_i915_private
*dev_priv
)
5683 /* inform PCU we want to change CDCLK */
5684 val
= SKL_CDCLK_PREPARE_FOR_CHANGE
;
5685 mutex_lock(&dev_priv
->rps
.hw_lock
);
5686 ret
= sandybridge_pcode_read(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, &val
);
5687 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5689 return ret
== 0 && (val
& SKL_CDCLK_READY_FOR_CHANGE
);
5692 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private
*dev_priv
)
5696 for (i
= 0; i
< 15; i
++) {
5697 if (skl_cdclk_pcu_ready(dev_priv
))
5705 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
, unsigned int freq
)
5707 struct drm_device
*dev
= dev_priv
->dev
;
5708 u32 freq_select
, pcu_ack
;
5710 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq
);
5712 if (!skl_cdclk_wait_for_pcu_ready(dev_priv
)) {
5713 DRM_ERROR("failed to inform PCU about cdclk change\n");
5721 freq_select
= CDCLK_FREQ_450_432
;
5725 freq_select
= CDCLK_FREQ_540
;
5731 freq_select
= CDCLK_FREQ_337_308
;
5736 freq_select
= CDCLK_FREQ_675_617
;
5741 I915_WRITE(CDCLK_CTL
, freq_select
| skl_cdclk_decimal(freq
));
5742 POSTING_READ(CDCLK_CTL
);
5744 /* inform PCU of the change */
5745 mutex_lock(&dev_priv
->rps
.hw_lock
);
5746 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
5747 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5749 intel_update_cdclk(dev
);
5752 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5754 /* disable DBUF power */
5755 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5756 POSTING_READ(DBUF_CTL
);
5760 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5761 DRM_ERROR("DBuf power disable timeout\n");
5764 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) & ~LCPLL_PLL_ENABLE
);
5765 if (wait_for(!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
), 1))
5766 DRM_ERROR("Couldn't disable DPLL0\n");
5768 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5771 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
5774 unsigned int required_vco
;
5776 /* enable PCH reset handshake */
5777 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5778 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
| RESET_PCH_HANDSHAKE_ENABLE
);
5780 /* enable PG1 and Misc I/O */
5781 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5783 /* DPLL0 already enabed !? */
5784 if (I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
) {
5785 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5790 required_vco
= skl_cdclk_get_vco(dev_priv
->skl_boot_cdclk
);
5791 skl_dpll0_enable(dev_priv
, required_vco
);
5793 /* set CDCLK to the frequency the BIOS chose */
5794 skl_set_cdclk(dev_priv
, dev_priv
->skl_boot_cdclk
);
5796 /* enable DBUF power */
5797 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5798 POSTING_READ(DBUF_CTL
);
5802 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5803 DRM_ERROR("DBuf power enable timeout\n");
5806 /* returns HPLL frequency in kHz */
5807 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
5809 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
5811 /* Obtain SKU information */
5812 mutex_lock(&dev_priv
->sb_lock
);
5813 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
5814 CCK_FUSE_HPLL_FREQ_MASK
;
5815 mutex_unlock(&dev_priv
->sb_lock
);
5817 return vco_freq
[hpll_freq
] * 1000;
5820 /* Adjust CDclk dividers to allow high res or save power if possible */
5821 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5826 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5827 != dev_priv
->cdclk_freq
);
5829 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5831 else if (cdclk
== 266667)
5836 mutex_lock(&dev_priv
->rps
.hw_lock
);
5837 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5838 val
&= ~DSPFREQGUAR_MASK
;
5839 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5840 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5841 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5842 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5844 DRM_ERROR("timed out waiting for CDclk change\n");
5846 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5848 mutex_lock(&dev_priv
->sb_lock
);
5850 if (cdclk
== 400000) {
5853 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5855 /* adjust cdclk divider */
5856 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5857 val
&= ~DISPLAY_FREQUENCY_VALUES
;
5859 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5861 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5862 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5864 DRM_ERROR("timed out waiting for CDclk change\n");
5867 /* adjust self-refresh exit latency value */
5868 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5872 * For high bandwidth configs, we set a higher latency in the bunit
5873 * so that the core display fetch happens in time to avoid underruns.
5875 if (cdclk
== 400000)
5876 val
|= 4500 / 250; /* 4.5 usec */
5878 val
|= 3000 / 250; /* 3.0 usec */
5879 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5881 mutex_unlock(&dev_priv
->sb_lock
);
5883 intel_update_cdclk(dev
);
5886 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5888 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5891 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5892 != dev_priv
->cdclk_freq
);
5901 MISSING_CASE(cdclk
);
5906 * Specs are full of misinformation, but testing on actual
5907 * hardware has shown that we just need to write the desired
5908 * CCK divider into the Punit register.
5910 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5912 mutex_lock(&dev_priv
->rps
.hw_lock
);
5913 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5914 val
&= ~DSPFREQGUAR_MASK_CHV
;
5915 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5916 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5917 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5918 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5920 DRM_ERROR("timed out waiting for CDclk change\n");
5922 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5924 intel_update_cdclk(dev
);
5927 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5930 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5931 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5934 * Really only a few cases to deal with, as only 4 CDclks are supported:
5937 * 320/333MHz (depends on HPLL freq)
5939 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5940 * of the lower bin and adjust if needed.
5942 * We seem to get an unstable or solid color picture at 200MHz.
5943 * Not sure what's wrong. For now use 200MHz only when all pipes
5946 if (!IS_CHERRYVIEW(dev_priv
) &&
5947 max_pixclk
> freq_320
*limit
/100)
5949 else if (max_pixclk
> 266667*limit
/100)
5951 else if (max_pixclk
> 0)
5957 static int broxton_calc_cdclk(struct drm_i915_private
*dev_priv
,
5962 * - remove the guardband, it's not needed on BXT
5963 * - set 19.2MHz bypass frequency if there are no active pipes
5965 if (max_pixclk
> 576000*9/10)
5967 else if (max_pixclk
> 384000*9/10)
5969 else if (max_pixclk
> 288000*9/10)
5971 else if (max_pixclk
> 144000*9/10)
5977 /* Compute the max pixel clock for new configuration. Uses atomic state if
5978 * that's non-NULL, look at current state otherwise. */
5979 static int intel_mode_max_pixclk(struct drm_device
*dev
,
5980 struct drm_atomic_state
*state
)
5982 struct intel_crtc
*intel_crtc
;
5983 struct intel_crtc_state
*crtc_state
;
5986 for_each_intel_crtc(dev
, intel_crtc
) {
5989 intel_atomic_get_crtc_state(state
, intel_crtc
);
5991 crtc_state
= intel_crtc
->config
;
5992 if (IS_ERR(crtc_state
))
5993 return PTR_ERR(crtc_state
);
5995 if (!crtc_state
->base
.enable
)
5998 max_pixclk
= max(max_pixclk
,
5999 crtc_state
->base
.adjusted_mode
.crtc_clock
);
6005 static int valleyview_modeset_global_pipes(struct drm_atomic_state
*state
)
6007 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
6008 struct drm_crtc
*crtc
;
6009 struct drm_crtc_state
*crtc_state
;
6010 int max_pixclk
= intel_mode_max_pixclk(state
->dev
, state
);
6016 if (IS_VALLEYVIEW(dev_priv
))
6017 cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
6019 cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
6021 if (cdclk
== dev_priv
->cdclk_freq
)
6024 /* add all active pipes to the state */
6025 for_each_crtc(state
->dev
, crtc
) {
6026 if (!crtc
->state
->enable
)
6029 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
6030 if (IS_ERR(crtc_state
))
6031 return PTR_ERR(crtc_state
);
6034 /* disable/enable all currently active pipes while we change cdclk */
6035 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
6036 if (crtc_state
->enable
)
6037 crtc_state
->mode_changed
= true;
6042 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
6044 unsigned int credits
, default_credits
;
6046 if (IS_CHERRYVIEW(dev_priv
))
6047 default_credits
= PFI_CREDIT(12);
6049 default_credits
= PFI_CREDIT(8);
6051 if (DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 1000) >= dev_priv
->rps
.cz_freq
) {
6052 /* CHV suggested value is 31 or 63 */
6053 if (IS_CHERRYVIEW(dev_priv
))
6054 credits
= PFI_CREDIT_31
;
6056 credits
= PFI_CREDIT(15);
6058 credits
= default_credits
;
6062 * WA - write default credits before re-programming
6063 * FIXME: should we also set the resend bit here?
6065 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6068 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6069 credits
| PFI_CREDIT_RESEND
);
6072 * FIXME is this guaranteed to clear
6073 * immediately or should we poll for it?
6075 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
6078 static void valleyview_modeset_global_resources(struct drm_atomic_state
*old_state
)
6080 struct drm_device
*dev
= old_state
->dev
;
6081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6082 int max_pixclk
= intel_mode_max_pixclk(dev
, NULL
);
6085 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6087 if (WARN_ON(max_pixclk
< 0))
6090 req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
6092 if (req_cdclk
!= dev_priv
->cdclk_freq
) {
6094 * FIXME: We can end up here with all power domains off, yet
6095 * with a CDCLK frequency other than the minimum. To account
6096 * for this take the PIPE-A power domain, which covers the HW
6097 * blocks needed for the following programming. This can be
6098 * removed once it's guaranteed that we get here either with
6099 * the minimum CDCLK set, or the required power domains
6102 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
6104 if (IS_CHERRYVIEW(dev
))
6105 cherryview_set_cdclk(dev
, req_cdclk
);
6107 valleyview_set_cdclk(dev
, req_cdclk
);
6109 vlv_program_pfi_credits(dev_priv
);
6111 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
6115 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
6117 struct drm_device
*dev
= crtc
->dev
;
6118 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6119 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6120 struct intel_encoder
*encoder
;
6121 int pipe
= intel_crtc
->pipe
;
6124 WARN_ON(!crtc
->state
->enable
);
6126 if (intel_crtc
->active
)
6129 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
6132 if (IS_CHERRYVIEW(dev
))
6133 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6135 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6138 if (intel_crtc
->config
->has_dp_encoder
)
6139 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6141 intel_set_pipe_timings(intel_crtc
);
6143 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
6144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6146 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6147 I915_WRITE(CHV_CANVAS(pipe
), 0);
6150 i9xx_set_pipeconf(intel_crtc
);
6152 intel_crtc
->active
= true;
6154 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6156 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6157 if (encoder
->pre_pll_enable
)
6158 encoder
->pre_pll_enable(encoder
);
6161 if (IS_CHERRYVIEW(dev
))
6162 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
6164 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
6167 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6168 if (encoder
->pre_enable
)
6169 encoder
->pre_enable(encoder
);
6171 i9xx_pfit_enable(intel_crtc
);
6173 intel_crtc_load_lut(crtc
);
6175 intel_update_watermarks(crtc
);
6176 intel_enable_pipe(intel_crtc
);
6178 assert_vblank_disabled(crtc
);
6179 drm_crtc_vblank_on(crtc
);
6181 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6182 encoder
->enable(encoder
);
6185 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
6187 struct drm_device
*dev
= crtc
->base
.dev
;
6188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6190 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
6191 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
6194 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
6196 struct drm_device
*dev
= crtc
->dev
;
6197 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6198 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6199 struct intel_encoder
*encoder
;
6200 int pipe
= intel_crtc
->pipe
;
6202 WARN_ON(!crtc
->state
->enable
);
6204 if (intel_crtc
->active
)
6207 i9xx_set_pll_dividers(intel_crtc
);
6209 if (intel_crtc
->config
->has_dp_encoder
)
6210 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6212 intel_set_pipe_timings(intel_crtc
);
6214 i9xx_set_pipeconf(intel_crtc
);
6216 intel_crtc
->active
= true;
6219 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6221 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6222 if (encoder
->pre_enable
)
6223 encoder
->pre_enable(encoder
);
6225 i9xx_enable_pll(intel_crtc
);
6227 i9xx_pfit_enable(intel_crtc
);
6229 intel_crtc_load_lut(crtc
);
6231 intel_update_watermarks(crtc
);
6232 intel_enable_pipe(intel_crtc
);
6234 assert_vblank_disabled(crtc
);
6235 drm_crtc_vblank_on(crtc
);
6237 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6238 encoder
->enable(encoder
);
6241 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6243 struct drm_device
*dev
= crtc
->base
.dev
;
6244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6246 if (!crtc
->config
->gmch_pfit
.control
)
6249 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6251 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6252 I915_READ(PFIT_CONTROL
));
6253 I915_WRITE(PFIT_CONTROL
, 0);
6256 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6258 struct drm_device
*dev
= crtc
->dev
;
6259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6260 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6261 struct intel_encoder
*encoder
;
6262 int pipe
= intel_crtc
->pipe
;
6264 if (!intel_crtc
->active
)
6268 * On gen2 planes are double buffered but the pipe isn't, so we must
6269 * wait for planes to fully turn off before disabling the pipe.
6270 * We also need to wait on all gmch platforms because of the
6271 * self-refresh mode constraint explained above.
6273 intel_wait_for_vblank(dev
, pipe
);
6275 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6276 encoder
->disable(encoder
);
6278 drm_crtc_vblank_off(crtc
);
6279 assert_vblank_disabled(crtc
);
6281 intel_disable_pipe(intel_crtc
);
6283 i9xx_pfit_disable(intel_crtc
);
6285 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6286 if (encoder
->post_disable
)
6287 encoder
->post_disable(encoder
);
6289 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
6290 if (IS_CHERRYVIEW(dev
))
6291 chv_disable_pll(dev_priv
, pipe
);
6292 else if (IS_VALLEYVIEW(dev
))
6293 vlv_disable_pll(dev_priv
, pipe
);
6295 i9xx_disable_pll(intel_crtc
);
6299 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6301 intel_crtc
->active
= false;
6302 intel_update_watermarks(crtc
);
6304 mutex_lock(&dev
->struct_mutex
);
6305 intel_fbc_update(dev
);
6306 mutex_unlock(&dev
->struct_mutex
);
6309 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
6313 /* Master function to enable/disable CRTC and corresponding power wells */
6314 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
6316 struct drm_device
*dev
= crtc
->dev
;
6317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6318 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6319 enum intel_display_power_domain domain
;
6320 unsigned long domains
;
6323 if (!intel_crtc
->active
) {
6324 domains
= get_crtc_power_domains(crtc
);
6325 for_each_power_domain(domain
, domains
)
6326 intel_display_power_get(dev_priv
, domain
);
6327 intel_crtc
->enabled_power_domains
= domains
;
6329 dev_priv
->display
.crtc_enable(crtc
);
6330 intel_crtc_enable_planes(crtc
);
6333 if (intel_crtc
->active
) {
6334 intel_crtc_disable_planes(crtc
);
6335 dev_priv
->display
.crtc_disable(crtc
);
6337 domains
= intel_crtc
->enabled_power_domains
;
6338 for_each_power_domain(domain
, domains
)
6339 intel_display_power_put(dev_priv
, domain
);
6340 intel_crtc
->enabled_power_domains
= 0;
6346 * Sets the power management mode of the pipe and plane.
6348 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
6350 struct drm_device
*dev
= crtc
->dev
;
6351 struct intel_encoder
*intel_encoder
;
6352 bool enable
= false;
6354 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
6355 enable
|= intel_encoder
->connectors_active
;
6357 intel_crtc_control(crtc
, enable
);
6359 crtc
->state
->active
= enable
;
6362 static void intel_crtc_disable(struct drm_crtc
*crtc
)
6364 struct drm_device
*dev
= crtc
->dev
;
6365 struct drm_connector
*connector
;
6366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6368 /* crtc should still be enabled when we disable it. */
6369 WARN_ON(!crtc
->state
->enable
);
6371 intel_crtc_disable_planes(crtc
);
6372 dev_priv
->display
.crtc_disable(crtc
);
6373 dev_priv
->display
.off(crtc
);
6375 drm_plane_helper_disable(crtc
->primary
);
6377 /* Update computed state. */
6378 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
6379 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
6382 if (connector
->encoder
->crtc
!= crtc
)
6385 connector
->dpms
= DRM_MODE_DPMS_OFF
;
6386 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
6390 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6392 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6394 drm_encoder_cleanup(encoder
);
6395 kfree(intel_encoder
);
6398 /* Simple dpms helper for encoders with just one connector, no cloning and only
6399 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6400 * state of the entire output pipe. */
6401 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
6403 if (mode
== DRM_MODE_DPMS_ON
) {
6404 encoder
->connectors_active
= true;
6406 intel_crtc_update_dpms(encoder
->base
.crtc
);
6408 encoder
->connectors_active
= false;
6410 intel_crtc_update_dpms(encoder
->base
.crtc
);
6414 /* Cross check the actual hw state with our own modeset state tracking (and it's
6415 * internal consistency). */
6416 static void intel_connector_check_state(struct intel_connector
*connector
)
6418 if (connector
->get_hw_state(connector
)) {
6419 struct intel_encoder
*encoder
= connector
->encoder
;
6420 struct drm_crtc
*crtc
;
6421 bool encoder_enabled
;
6424 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6425 connector
->base
.base
.id
,
6426 connector
->base
.name
);
6428 /* there is no real hw state for MST connectors */
6429 if (connector
->mst_port
)
6432 I915_STATE_WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
6433 "wrong connector dpms state\n");
6434 I915_STATE_WARN(connector
->base
.encoder
!= &encoder
->base
,
6435 "active connector not linked to encoder\n");
6438 I915_STATE_WARN(!encoder
->connectors_active
,
6439 "encoder->connectors_active not set\n");
6441 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
6442 I915_STATE_WARN(!encoder_enabled
, "encoder not enabled\n");
6443 if (I915_STATE_WARN_ON(!encoder
->base
.crtc
))
6446 crtc
= encoder
->base
.crtc
;
6448 I915_STATE_WARN(!crtc
->state
->enable
,
6449 "crtc not enabled\n");
6450 I915_STATE_WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
6451 I915_STATE_WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
6452 "encoder active on the wrong pipe\n");
6457 int intel_connector_init(struct intel_connector
*connector
)
6459 struct drm_connector_state
*connector_state
;
6461 connector_state
= kzalloc(sizeof *connector_state
, GFP_KERNEL
);
6462 if (!connector_state
)
6465 connector
->base
.state
= connector_state
;
6469 struct intel_connector
*intel_connector_alloc(void)
6471 struct intel_connector
*connector
;
6473 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6477 if (intel_connector_init(connector
) < 0) {
6485 /* Even simpler default implementation, if there's really no special case to
6487 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
6489 /* All the simple cases only support two dpms states. */
6490 if (mode
!= DRM_MODE_DPMS_ON
)
6491 mode
= DRM_MODE_DPMS_OFF
;
6493 if (mode
== connector
->dpms
)
6496 connector
->dpms
= mode
;
6498 /* Only need to change hw state when actually enabled */
6499 if (connector
->encoder
)
6500 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
6502 intel_modeset_check_state(connector
->dev
);
6505 /* Simple connector->get_hw_state implementation for encoders that support only
6506 * one connector and no cloning and hence the encoder state determines the state
6507 * of the connector. */
6508 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6511 struct intel_encoder
*encoder
= connector
->encoder
;
6513 return encoder
->get_hw_state(encoder
, &pipe
);
6516 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6518 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6519 return crtc_state
->fdi_lanes
;
6524 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6525 struct intel_crtc_state
*pipe_config
)
6527 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6528 struct intel_crtc
*other_crtc
;
6529 struct intel_crtc_state
*other_crtc_state
;
6531 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6532 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6533 if (pipe_config
->fdi_lanes
> 4) {
6534 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6535 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6539 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6540 if (pipe_config
->fdi_lanes
> 2) {
6541 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6542 pipe_config
->fdi_lanes
);
6549 if (INTEL_INFO(dev
)->num_pipes
== 2)
6552 /* Ivybridge 3 pipe is really complicated */
6557 if (pipe_config
->fdi_lanes
<= 2)
6560 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6562 intel_atomic_get_crtc_state(state
, other_crtc
);
6563 if (IS_ERR(other_crtc_state
))
6564 return PTR_ERR(other_crtc_state
);
6566 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6567 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6568 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6573 if (pipe_config
->fdi_lanes
> 2) {
6574 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6575 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6579 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6581 intel_atomic_get_crtc_state(state
, other_crtc
);
6582 if (IS_ERR(other_crtc_state
))
6583 return PTR_ERR(other_crtc_state
);
6585 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6586 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6596 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6597 struct intel_crtc_state
*pipe_config
)
6599 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6600 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6601 int lane
, link_bw
, fdi_dotclock
, ret
;
6602 bool needs_recompute
= false;
6605 /* FDI is a binary signal running at ~2.7GHz, encoding
6606 * each output octet as 10 bits. The actual frequency
6607 * is stored as a divider into a 100MHz clock, and the
6608 * mode pixel clock is stored in units of 1KHz.
6609 * Hence the bw of each lane in terms of the mode signal
6612 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
6614 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6616 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6617 pipe_config
->pipe_bpp
);
6619 pipe_config
->fdi_lanes
= lane
;
6621 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6622 link_bw
, &pipe_config
->fdi_m_n
);
6624 ret
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
6625 intel_crtc
->pipe
, pipe_config
);
6626 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6627 pipe_config
->pipe_bpp
-= 2*3;
6628 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6629 pipe_config
->pipe_bpp
);
6630 needs_recompute
= true;
6631 pipe_config
->bw_constrained
= true;
6636 if (needs_recompute
)
6642 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
6643 struct intel_crtc_state
*pipe_config
)
6645 if (pipe_config
->pipe_bpp
> 24)
6648 /* HSW can handle pixel rate up to cdclk? */
6649 if (IS_HASWELL(dev_priv
->dev
))
6653 * We compare against max which means we must take
6654 * the increased cdclk requirement into account when
6655 * calculating the new cdclk.
6657 * Should measure whether using a lower cdclk w/o IPS
6659 return ilk_pipe_pixel_rate(pipe_config
) <=
6660 dev_priv
->max_cdclk_freq
* 95 / 100;
6663 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6664 struct intel_crtc_state
*pipe_config
)
6666 struct drm_device
*dev
= crtc
->base
.dev
;
6667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6669 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6670 hsw_crtc_supports_ips(crtc
) &&
6671 pipe_config_supports_ips(dev_priv
, pipe_config
);
6674 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6675 struct intel_crtc_state
*pipe_config
)
6677 struct drm_device
*dev
= crtc
->base
.dev
;
6678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6679 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6682 /* FIXME should check pixel clock limits on all platforms */
6683 if (INTEL_INFO(dev
)->gen
< 4) {
6684 int clock_limit
= dev_priv
->max_cdclk_freq
;
6687 * Enable pixel doubling when the dot clock
6688 * is > 90% of the (display) core speed.
6690 * GDG double wide on either pipe,
6691 * otherwise pipe A only.
6693 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
6694 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
6696 pipe_config
->double_wide
= true;
6699 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
6704 * Pipe horizontal size must be even in:
6706 * - LVDS dual channel mode
6707 * - Double wide pipe
6709 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6710 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6711 pipe_config
->pipe_src_w
&= ~1;
6713 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6714 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6716 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6717 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
6721 hsw_compute_ips_config(crtc
, pipe_config
);
6723 if (pipe_config
->has_pch_encoder
)
6724 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6726 /* FIXME: remove below call once atomic mode set is place and all crtc
6727 * related checks called from atomic_crtc_check function */
6729 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6730 crtc
, pipe_config
->base
.state
);
6731 ret
= intel_atomic_setup_scalers(dev
, crtc
, pipe_config
);
6736 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6739 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
6740 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6743 if (!(lcpll1
& LCPLL_PLL_ENABLE
))
6744 return 24000; /* 24MHz is the cd freq with NSSC ref */
6746 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
6749 linkrate
= (I915_READ(DPLL_CTRL1
) &
6750 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
6752 if (linkrate
== DPLL_CTRL1_LINK_RATE_2160
||
6753 linkrate
== DPLL_CTRL1_LINK_RATE_1080
) {
6755 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6756 case CDCLK_FREQ_450_432
:
6758 case CDCLK_FREQ_337_308
:
6760 case CDCLK_FREQ_675_617
:
6763 WARN(1, "Unknown cd freq selection\n");
6767 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6768 case CDCLK_FREQ_450_432
:
6770 case CDCLK_FREQ_337_308
:
6772 case CDCLK_FREQ_675_617
:
6775 WARN(1, "Unknown cd freq selection\n");
6779 /* error case, do as if DPLL0 isn't enabled */
6783 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6786 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6787 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6789 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6791 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6793 else if (freq
== LCPLL_CLK_FREQ_450
)
6795 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6797 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6803 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6806 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6807 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6809 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6811 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6813 else if (freq
== LCPLL_CLK_FREQ_450
)
6815 else if (IS_HSW_ULT(dev
))
6821 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6827 if (dev_priv
->hpll_freq
== 0)
6828 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
6830 mutex_lock(&dev_priv
->sb_lock
);
6831 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
6832 mutex_unlock(&dev_priv
->sb_lock
);
6834 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
6836 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
6837 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
6838 "cdclk change in progress\n");
6840 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
6843 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6848 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6853 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6858 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6863 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6867 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6869 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6870 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6872 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6874 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6876 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6879 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6880 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6882 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6887 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6891 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6893 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6896 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6897 case GC_DISPLAY_CLOCK_333_MHZ
:
6900 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6906 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6911 static int i85x_get_display_clock_speed(struct drm_device
*dev
)
6916 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6917 * encoding is different :(
6918 * FIXME is this the right way to detect 852GM/852GMV?
6920 if (dev
->pdev
->revision
== 0x1)
6923 pci_bus_read_config_word(dev
->pdev
->bus
,
6924 PCI_DEVFN(0, 3), HPLLCC
, &hpllcc
);
6926 /* Assume that the hardware is in the high speed state. This
6927 * should be the default.
6929 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6930 case GC_CLOCK_133_200
:
6931 case GC_CLOCK_133_200_2
:
6932 case GC_CLOCK_100_200
:
6934 case GC_CLOCK_166_250
:
6936 case GC_CLOCK_100_133
:
6938 case GC_CLOCK_133_266
:
6939 case GC_CLOCK_133_266_2
:
6940 case GC_CLOCK_166_266
:
6944 /* Shouldn't happen */
6948 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6953 static unsigned int intel_hpll_vco(struct drm_device
*dev
)
6955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6956 static const unsigned int blb_vco
[8] = {
6963 static const unsigned int pnv_vco
[8] = {
6970 static const unsigned int cl_vco
[8] = {
6979 static const unsigned int elk_vco
[8] = {
6985 static const unsigned int ctg_vco
[8] = {
6993 const unsigned int *vco_table
;
6997 /* FIXME other chipsets? */
6999 vco_table
= ctg_vco
;
7000 else if (IS_G4X(dev
))
7001 vco_table
= elk_vco
;
7002 else if (IS_CRESTLINE(dev
))
7004 else if (IS_PINEVIEW(dev
))
7005 vco_table
= pnv_vco
;
7006 else if (IS_G33(dev
))
7007 vco_table
= blb_vco
;
7011 tmp
= I915_READ(IS_MOBILE(dev
) ? HPLLVCO_MOBILE
: HPLLVCO
);
7013 vco
= vco_table
[tmp
& 0x7];
7015 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp
);
7017 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco
);
7022 static int gm45_get_display_clock_speed(struct drm_device
*dev
)
7024 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7027 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7029 cdclk_sel
= (tmp
>> 12) & 0x1;
7035 return cdclk_sel
? 333333 : 222222;
7037 return cdclk_sel
? 320000 : 228571;
7039 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco
, tmp
);
7044 static int i965gm_get_display_clock_speed(struct drm_device
*dev
)
7046 static const uint8_t div_3200
[] = { 16, 10, 8 };
7047 static const uint8_t div_4000
[] = { 20, 12, 10 };
7048 static const uint8_t div_5333
[] = { 24, 16, 14 };
7049 const uint8_t *div_table
;
7050 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7053 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7055 cdclk_sel
= ((tmp
>> 8) & 0x1f) - 1;
7057 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7062 div_table
= div_3200
;
7065 div_table
= div_4000
;
7068 div_table
= div_5333
;
7074 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7077 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco
, tmp
);
7081 static int g33_get_display_clock_speed(struct drm_device
*dev
)
7083 static const uint8_t div_3200
[] = { 12, 10, 8, 7, 5, 16 };
7084 static const uint8_t div_4000
[] = { 14, 12, 10, 8, 6, 20 };
7085 static const uint8_t div_4800
[] = { 20, 14, 12, 10, 8, 24 };
7086 static const uint8_t div_5333
[] = { 20, 16, 12, 12, 8, 28 };
7087 const uint8_t *div_table
;
7088 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7091 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7093 cdclk_sel
= (tmp
>> 4) & 0x7;
7095 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7100 div_table
= div_3200
;
7103 div_table
= div_4000
;
7106 div_table
= div_4800
;
7109 div_table
= div_5333
;
7115 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7118 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco
, tmp
);
7123 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
7125 while (*num
> DATA_LINK_M_N_MASK
||
7126 *den
> DATA_LINK_M_N_MASK
) {
7132 static void compute_m_n(unsigned int m
, unsigned int n
,
7133 uint32_t *ret_m
, uint32_t *ret_n
)
7135 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7136 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
7137 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7141 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
7142 int pixel_clock
, int link_clock
,
7143 struct intel_link_m_n
*m_n
)
7147 compute_m_n(bits_per_pixel
* pixel_clock
,
7148 link_clock
* nlanes
* 8,
7149 &m_n
->gmch_m
, &m_n
->gmch_n
);
7151 compute_m_n(pixel_clock
, link_clock
,
7152 &m_n
->link_m
, &m_n
->link_n
);
7155 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7157 if (i915
.panel_use_ssc
>= 0)
7158 return i915
.panel_use_ssc
!= 0;
7159 return dev_priv
->vbt
.lvds_use_ssc
7160 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7163 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
7166 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
7167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7170 WARN_ON(!crtc_state
->base
.state
);
7172 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
7174 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7175 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7176 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7177 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7178 } else if (!IS_GEN2(dev
)) {
7187 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
7189 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7192 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
7194 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7197 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7198 struct intel_crtc_state
*crtc_state
,
7199 intel_clock_t
*reduced_clock
)
7201 struct drm_device
*dev
= crtc
->base
.dev
;
7204 if (IS_PINEVIEW(dev
)) {
7205 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7207 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7209 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7211 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7214 crtc_state
->dpll_hw_state
.fp0
= fp
;
7216 crtc
->lowfreq_avail
= false;
7217 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7219 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7220 crtc
->lowfreq_avail
= true;
7222 crtc_state
->dpll_hw_state
.fp1
= fp
;
7226 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7232 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7233 * and set it to a reasonable value instead.
7235 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7236 reg_val
&= 0xffffff00;
7237 reg_val
|= 0x00000030;
7238 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7240 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7241 reg_val
&= 0x8cffffff;
7242 reg_val
= 0x8c000000;
7243 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7245 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7246 reg_val
&= 0xffffff00;
7247 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7249 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7250 reg_val
&= 0x00ffffff;
7251 reg_val
|= 0xb0000000;
7252 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7255 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
7256 struct intel_link_m_n
*m_n
)
7258 struct drm_device
*dev
= crtc
->base
.dev
;
7259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7260 int pipe
= crtc
->pipe
;
7262 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7263 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7264 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7265 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7268 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
7269 struct intel_link_m_n
*m_n
,
7270 struct intel_link_m_n
*m2_n2
)
7272 struct drm_device
*dev
= crtc
->base
.dev
;
7273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7274 int pipe
= crtc
->pipe
;
7275 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
7277 if (INTEL_INFO(dev
)->gen
>= 5) {
7278 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7279 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7280 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7281 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7282 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7283 * for gen < 8) and if DRRS is supported (to make sure the
7284 * registers are not unnecessarily accessed).
7286 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
7287 crtc
->config
->has_drrs
) {
7288 I915_WRITE(PIPE_DATA_M2(transcoder
),
7289 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7290 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7291 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7292 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7295 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7296 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7297 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7298 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7302 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
7304 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7307 dp_m_n
= &crtc
->config
->dp_m_n
;
7308 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
7309 } else if (m_n
== M2_N2
) {
7312 * M2_N2 registers are not supported. Hence m2_n2 divider value
7313 * needs to be programmed into M1_N1.
7315 dp_m_n
= &crtc
->config
->dp_m2_n2
;
7317 DRM_ERROR("Unsupported divider value\n");
7321 if (crtc
->config
->has_pch_encoder
)
7322 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
7324 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
7327 static void vlv_update_pll(struct intel_crtc
*crtc
,
7328 struct intel_crtc_state
*pipe_config
)
7333 * Enable DPIO clock input. We should never disable the reference
7334 * clock for pipe B, since VGA hotplug / manual detection depends
7337 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
7338 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
7339 /* We should never disable this, set it here for state tracking */
7340 if (crtc
->pipe
== PIPE_B
)
7341 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7342 dpll
|= DPLL_VCO_ENABLE
;
7343 pipe_config
->dpll_hw_state
.dpll
= dpll
;
7345 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
7346 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7347 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
7350 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7351 const struct intel_crtc_state
*pipe_config
)
7353 struct drm_device
*dev
= crtc
->base
.dev
;
7354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7355 int pipe
= crtc
->pipe
;
7357 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7358 u32 coreclk
, reg_val
;
7360 mutex_lock(&dev_priv
->sb_lock
);
7362 bestn
= pipe_config
->dpll
.n
;
7363 bestm1
= pipe_config
->dpll
.m1
;
7364 bestm2
= pipe_config
->dpll
.m2
;
7365 bestp1
= pipe_config
->dpll
.p1
;
7366 bestp2
= pipe_config
->dpll
.p2
;
7368 /* See eDP HDMI DPIO driver vbios notes doc */
7370 /* PLL B needs special handling */
7372 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7374 /* Set up Tx target for periodic Rcomp update */
7375 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7377 /* Disable target IRef on PLL */
7378 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7379 reg_val
&= 0x00ffffff;
7380 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7382 /* Disable fast lock */
7383 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7385 /* Set idtafcrecal before PLL is enabled */
7386 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7387 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7388 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7389 mdiv
|= (1 << DPIO_K_SHIFT
);
7392 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7393 * but we don't support that).
7394 * Note: don't use the DAC post divider as it seems unstable.
7396 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7397 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7399 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7400 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7402 /* Set HBR and RBR LPF coefficients */
7403 if (pipe_config
->port_clock
== 162000 ||
7404 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
7405 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
7406 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7409 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7412 if (pipe_config
->has_dp_encoder
) {
7413 /* Use SSC source */
7415 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7418 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7420 } else { /* HDMI or VGA */
7421 /* Use bend source */
7423 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7426 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7430 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7431 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7432 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
7433 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
7434 coreclk
|= 0x01000000;
7435 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7437 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7438 mutex_unlock(&dev_priv
->sb_lock
);
7441 static void chv_update_pll(struct intel_crtc
*crtc
,
7442 struct intel_crtc_state
*pipe_config
)
7444 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
7445 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
7447 if (crtc
->pipe
!= PIPE_A
)
7448 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7450 pipe_config
->dpll_hw_state
.dpll_md
=
7451 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7454 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7455 const struct intel_crtc_state
*pipe_config
)
7457 struct drm_device
*dev
= crtc
->base
.dev
;
7458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7459 int pipe
= crtc
->pipe
;
7460 int dpll_reg
= DPLL(crtc
->pipe
);
7461 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7462 u32 loopfilter
, tribuf_calcntr
;
7463 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7467 bestn
= pipe_config
->dpll
.n
;
7468 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7469 bestm1
= pipe_config
->dpll
.m1
;
7470 bestm2
= pipe_config
->dpll
.m2
>> 22;
7471 bestp1
= pipe_config
->dpll
.p1
;
7472 bestp2
= pipe_config
->dpll
.p2
;
7473 vco
= pipe_config
->dpll
.vco
;
7478 * Enable Refclk and SSC
7480 I915_WRITE(dpll_reg
,
7481 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7483 mutex_lock(&dev_priv
->sb_lock
);
7485 /* p1 and p2 divider */
7486 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7487 5 << DPIO_CHV_S1_DIV_SHIFT
|
7488 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7489 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7490 1 << DPIO_CHV_K_DIV_SHIFT
);
7492 /* Feedback post-divider - m2 */
7493 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7495 /* Feedback refclk divider - n and m1 */
7496 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7497 DPIO_CHV_M1_DIV_BY_2
|
7498 1 << DPIO_CHV_N_DIV_SHIFT
);
7500 /* M2 fraction division */
7502 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7504 /* M2 fraction division enable */
7505 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7506 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7507 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7509 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7510 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7512 /* Program digital lock detect threshold */
7513 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7514 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7515 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7516 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7518 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7519 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7522 if (vco
== 5400000) {
7523 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7524 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7525 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7526 tribuf_calcntr
= 0x9;
7527 } else if (vco
<= 6200000) {
7528 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7529 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7530 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7531 tribuf_calcntr
= 0x9;
7532 } else if (vco
<= 6480000) {
7533 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7534 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7535 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7536 tribuf_calcntr
= 0x8;
7538 /* Not supported. Apply the same limits as in the max case */
7539 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7540 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7541 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7544 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7546 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7547 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7548 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7549 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7552 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7553 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7556 mutex_unlock(&dev_priv
->sb_lock
);
7560 * vlv_force_pll_on - forcibly enable just the PLL
7561 * @dev_priv: i915 private structure
7562 * @pipe: pipe PLL to enable
7563 * @dpll: PLL configuration
7565 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7566 * in cases where we need the PLL enabled even when @pipe is not going to
7569 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7570 const struct dpll
*dpll
)
7572 struct intel_crtc
*crtc
=
7573 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7574 struct intel_crtc_state pipe_config
= {
7575 .base
.crtc
= &crtc
->base
,
7576 .pixel_multiplier
= 1,
7580 if (IS_CHERRYVIEW(dev
)) {
7581 chv_update_pll(crtc
, &pipe_config
);
7582 chv_prepare_pll(crtc
, &pipe_config
);
7583 chv_enable_pll(crtc
, &pipe_config
);
7585 vlv_update_pll(crtc
, &pipe_config
);
7586 vlv_prepare_pll(crtc
, &pipe_config
);
7587 vlv_enable_pll(crtc
, &pipe_config
);
7592 * vlv_force_pll_off - forcibly disable just the PLL
7593 * @dev_priv: i915 private structure
7594 * @pipe: pipe PLL to disable
7596 * Disable the PLL for @pipe. To be used in cases where we need
7597 * the PLL enabled even when @pipe is not going to be enabled.
7599 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7601 if (IS_CHERRYVIEW(dev
))
7602 chv_disable_pll(to_i915(dev
), pipe
);
7604 vlv_disable_pll(to_i915(dev
), pipe
);
7607 static void i9xx_update_pll(struct intel_crtc
*crtc
,
7608 struct intel_crtc_state
*crtc_state
,
7609 intel_clock_t
*reduced_clock
,
7612 struct drm_device
*dev
= crtc
->base
.dev
;
7613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7616 struct dpll
*clock
= &crtc_state
->dpll
;
7618 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7620 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7621 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
7623 dpll
= DPLL_VGA_MODE_DIS
;
7625 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7626 dpll
|= DPLLB_MODE_LVDS
;
7628 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7630 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7631 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7632 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7636 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7638 if (crtc_state
->has_dp_encoder
)
7639 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7641 /* compute bitmask from p1 value */
7642 if (IS_PINEVIEW(dev
))
7643 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7645 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7646 if (IS_G4X(dev
) && reduced_clock
)
7647 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7649 switch (clock
->p2
) {
7651 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7654 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7657 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7660 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7663 if (INTEL_INFO(dev
)->gen
>= 4)
7664 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7666 if (crtc_state
->sdvo_tv_clock
)
7667 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7668 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7669 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7670 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7672 dpll
|= PLL_REF_INPUT_DREFCLK
;
7674 dpll
|= DPLL_VCO_ENABLE
;
7675 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7677 if (INTEL_INFO(dev
)->gen
>= 4) {
7678 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7679 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7680 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7684 static void i8xx_update_pll(struct intel_crtc
*crtc
,
7685 struct intel_crtc_state
*crtc_state
,
7686 intel_clock_t
*reduced_clock
,
7689 struct drm_device
*dev
= crtc
->base
.dev
;
7690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7692 struct dpll
*clock
= &crtc_state
->dpll
;
7694 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7696 dpll
= DPLL_VGA_MODE_DIS
;
7698 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7699 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7702 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7704 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7706 dpll
|= PLL_P2_DIVIDE_BY_4
;
7709 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
7710 dpll
|= DPLL_DVO_2X_MODE
;
7712 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7713 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7714 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7716 dpll
|= PLL_REF_INPUT_DREFCLK
;
7718 dpll
|= DPLL_VCO_ENABLE
;
7719 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7722 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7724 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7726 enum pipe pipe
= intel_crtc
->pipe
;
7727 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7728 struct drm_display_mode
*adjusted_mode
=
7729 &intel_crtc
->config
->base
.adjusted_mode
;
7730 uint32_t crtc_vtotal
, crtc_vblank_end
;
7733 /* We need to be careful not to changed the adjusted mode, for otherwise
7734 * the hw state checker will get angry at the mismatch. */
7735 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7736 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7738 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7739 /* the chip adds 2 halflines automatically */
7741 crtc_vblank_end
-= 1;
7743 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7744 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7746 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7747 adjusted_mode
->crtc_htotal
/ 2;
7749 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7752 if (INTEL_INFO(dev
)->gen
> 3)
7753 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7755 I915_WRITE(HTOTAL(cpu_transcoder
),
7756 (adjusted_mode
->crtc_hdisplay
- 1) |
7757 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7758 I915_WRITE(HBLANK(cpu_transcoder
),
7759 (adjusted_mode
->crtc_hblank_start
- 1) |
7760 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7761 I915_WRITE(HSYNC(cpu_transcoder
),
7762 (adjusted_mode
->crtc_hsync_start
- 1) |
7763 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7765 I915_WRITE(VTOTAL(cpu_transcoder
),
7766 (adjusted_mode
->crtc_vdisplay
- 1) |
7767 ((crtc_vtotal
- 1) << 16));
7768 I915_WRITE(VBLANK(cpu_transcoder
),
7769 (adjusted_mode
->crtc_vblank_start
- 1) |
7770 ((crtc_vblank_end
- 1) << 16));
7771 I915_WRITE(VSYNC(cpu_transcoder
),
7772 (adjusted_mode
->crtc_vsync_start
- 1) |
7773 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7775 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7776 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7777 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7779 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7780 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7781 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7783 /* pipesrc controls the size that is scaled from, which should
7784 * always be the user's requested size.
7786 I915_WRITE(PIPESRC(pipe
),
7787 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7788 (intel_crtc
->config
->pipe_src_h
- 1));
7791 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7792 struct intel_crtc_state
*pipe_config
)
7794 struct drm_device
*dev
= crtc
->base
.dev
;
7795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7796 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7799 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7800 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7801 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7802 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7803 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7804 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7805 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7806 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7807 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7809 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7810 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7811 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7812 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7813 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7814 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7815 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7816 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7817 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7819 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7820 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7821 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7822 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7825 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7826 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7827 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7829 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7830 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7833 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7834 struct intel_crtc_state
*pipe_config
)
7836 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7837 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7838 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7839 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7841 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7842 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7843 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7844 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7846 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7848 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7849 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7852 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7854 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7860 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7861 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7862 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7864 if (intel_crtc
->config
->double_wide
)
7865 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7867 /* only g4x and later have fancy bpc/dither controls */
7868 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7869 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7870 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7871 pipeconf
|= PIPECONF_DITHER_EN
|
7872 PIPECONF_DITHER_TYPE_SP
;
7874 switch (intel_crtc
->config
->pipe_bpp
) {
7876 pipeconf
|= PIPECONF_6BPC
;
7879 pipeconf
|= PIPECONF_8BPC
;
7882 pipeconf
|= PIPECONF_10BPC
;
7885 /* Case prevented by intel_choose_pipe_bpp_dither. */
7890 if (HAS_PIPE_CXSR(dev
)) {
7891 if (intel_crtc
->lowfreq_avail
) {
7892 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7893 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7895 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7899 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7900 if (INTEL_INFO(dev
)->gen
< 4 ||
7901 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7902 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7904 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7906 pipeconf
|= PIPECONF_PROGRESSIVE
;
7908 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
7909 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7911 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7912 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7915 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7916 struct intel_crtc_state
*crtc_state
)
7918 struct drm_device
*dev
= crtc
->base
.dev
;
7919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7920 int refclk
, num_connectors
= 0;
7921 intel_clock_t clock
, reduced_clock
;
7922 bool ok
, has_reduced_clock
= false;
7923 bool is_lvds
= false, is_dsi
= false;
7924 struct intel_encoder
*encoder
;
7925 const intel_limit_t
*limit
;
7926 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7927 struct drm_connector
*connector
;
7928 struct drm_connector_state
*connector_state
;
7931 memset(&crtc_state
->dpll_hw_state
, 0,
7932 sizeof(crtc_state
->dpll_hw_state
));
7934 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
7935 if (connector_state
->crtc
!= &crtc
->base
)
7938 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7940 switch (encoder
->type
) {
7941 case INTEL_OUTPUT_LVDS
:
7944 case INTEL_OUTPUT_DSI
:
7957 if (!crtc_state
->clock_set
) {
7958 refclk
= i9xx_get_refclk(crtc_state
, num_connectors
);
7961 * Returns a set of divisors for the desired target clock with
7962 * the given refclk, or FALSE. The returned values represent
7963 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7966 limit
= intel_limit(crtc_state
, refclk
);
7967 ok
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
7968 crtc_state
->port_clock
,
7969 refclk
, NULL
, &clock
);
7971 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7975 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7977 * Ensure we match the reduced clock's P to the target
7978 * clock. If the clocks don't match, we can't switch
7979 * the display clock by using the FP0/FP1. In such case
7980 * we will disable the LVDS downclock feature.
7983 dev_priv
->display
.find_dpll(limit
, crtc_state
,
7984 dev_priv
->lvds_downclock
,
7988 /* Compat-code for transition, will disappear. */
7989 crtc_state
->dpll
.n
= clock
.n
;
7990 crtc_state
->dpll
.m1
= clock
.m1
;
7991 crtc_state
->dpll
.m2
= clock
.m2
;
7992 crtc_state
->dpll
.p1
= clock
.p1
;
7993 crtc_state
->dpll
.p2
= clock
.p2
;
7997 i8xx_update_pll(crtc
, crtc_state
,
7998 has_reduced_clock
? &reduced_clock
: NULL
,
8000 } else if (IS_CHERRYVIEW(dev
)) {
8001 chv_update_pll(crtc
, crtc_state
);
8002 } else if (IS_VALLEYVIEW(dev
)) {
8003 vlv_update_pll(crtc
, crtc_state
);
8005 i9xx_update_pll(crtc
, crtc_state
,
8006 has_reduced_clock
? &reduced_clock
: NULL
,
8013 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
8014 struct intel_crtc_state
*pipe_config
)
8016 struct drm_device
*dev
= crtc
->base
.dev
;
8017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8020 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
8023 tmp
= I915_READ(PFIT_CONTROL
);
8024 if (!(tmp
& PFIT_ENABLE
))
8027 /* Check whether the pfit is attached to our pipe. */
8028 if (INTEL_INFO(dev
)->gen
< 4) {
8029 if (crtc
->pipe
!= PIPE_B
)
8032 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
8036 pipe_config
->gmch_pfit
.control
= tmp
;
8037 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
8038 if (INTEL_INFO(dev
)->gen
< 5)
8039 pipe_config
->gmch_pfit
.lvds_border_bits
=
8040 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
8043 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
8044 struct intel_crtc_state
*pipe_config
)
8046 struct drm_device
*dev
= crtc
->base
.dev
;
8047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8048 int pipe
= pipe_config
->cpu_transcoder
;
8049 intel_clock_t clock
;
8051 int refclk
= 100000;
8053 /* In case of MIPI DPLL will not even be used */
8054 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
8057 mutex_lock(&dev_priv
->sb_lock
);
8058 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8059 mutex_unlock(&dev_priv
->sb_lock
);
8061 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8062 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8063 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8064 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8065 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8067 vlv_clock(refclk
, &clock
);
8069 /* clock.dot is the fast clock */
8070 pipe_config
->port_clock
= clock
.dot
/ 5;
8074 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8075 struct intel_initial_plane_config
*plane_config
)
8077 struct drm_device
*dev
= crtc
->base
.dev
;
8078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8079 u32 val
, base
, offset
;
8080 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
8081 int fourcc
, pixel_format
;
8082 unsigned int aligned_height
;
8083 struct drm_framebuffer
*fb
;
8084 struct intel_framebuffer
*intel_fb
;
8086 val
= I915_READ(DSPCNTR(plane
));
8087 if (!(val
& DISPLAY_PLANE_ENABLE
))
8090 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8092 DRM_DEBUG_KMS("failed to alloc fb\n");
8096 fb
= &intel_fb
->base
;
8098 if (INTEL_INFO(dev
)->gen
>= 4) {
8099 if (val
& DISPPLANE_TILED
) {
8100 plane_config
->tiling
= I915_TILING_X
;
8101 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8105 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8106 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8107 fb
->pixel_format
= fourcc
;
8108 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8110 if (INTEL_INFO(dev
)->gen
>= 4) {
8111 if (plane_config
->tiling
)
8112 offset
= I915_READ(DSPTILEOFF(plane
));
8114 offset
= I915_READ(DSPLINOFF(plane
));
8115 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
8117 base
= I915_READ(DSPADDR(plane
));
8119 plane_config
->base
= base
;
8121 val
= I915_READ(PIPESRC(pipe
));
8122 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8123 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8125 val
= I915_READ(DSPSTRIDE(pipe
));
8126 fb
->pitches
[0] = val
& 0xffffffc0;
8128 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8132 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8134 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8135 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
8136 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8137 plane_config
->size
);
8139 plane_config
->fb
= intel_fb
;
8142 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8143 struct intel_crtc_state
*pipe_config
)
8145 struct drm_device
*dev
= crtc
->base
.dev
;
8146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8147 int pipe
= pipe_config
->cpu_transcoder
;
8148 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8149 intel_clock_t clock
;
8150 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
8151 int refclk
= 100000;
8153 mutex_lock(&dev_priv
->sb_lock
);
8154 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8155 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8156 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8157 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8158 mutex_unlock(&dev_priv
->sb_lock
);
8160 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8161 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
8162 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8163 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8164 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8166 chv_clock(refclk
, &clock
);
8168 /* clock.dot is the fast clock */
8169 pipe_config
->port_clock
= clock
.dot
/ 5;
8172 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8173 struct intel_crtc_state
*pipe_config
)
8175 struct drm_device
*dev
= crtc
->base
.dev
;
8176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8179 if (!intel_display_power_is_enabled(dev_priv
,
8180 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8183 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8184 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8186 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8187 if (!(tmp
& PIPECONF_ENABLE
))
8190 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
8191 switch (tmp
& PIPECONF_BPC_MASK
) {
8193 pipe_config
->pipe_bpp
= 18;
8196 pipe_config
->pipe_bpp
= 24;
8198 case PIPECONF_10BPC
:
8199 pipe_config
->pipe_bpp
= 30;
8206 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8207 pipe_config
->limited_color_range
= true;
8209 if (INTEL_INFO(dev
)->gen
< 4)
8210 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8212 intel_get_pipe_timings(crtc
, pipe_config
);
8214 i9xx_get_pfit_config(crtc
, pipe_config
);
8216 if (INTEL_INFO(dev
)->gen
>= 4) {
8217 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8218 pipe_config
->pixel_multiplier
=
8219 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8220 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8221 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8222 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
8223 tmp
= I915_READ(DPLL(crtc
->pipe
));
8224 pipe_config
->pixel_multiplier
=
8225 ((tmp
& SDVO_MULTIPLIER_MASK
)
8226 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8228 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8229 * port and will be fixed up in the encoder->get_config
8231 pipe_config
->pixel_multiplier
= 1;
8233 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8234 if (!IS_VALLEYVIEW(dev
)) {
8236 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8237 * on 830. Filter it out here so that we don't
8238 * report errors due to that.
8241 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
8243 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8244 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8246 /* Mask out read-only status bits. */
8247 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8248 DPLL_PORTC_READY_MASK
|
8249 DPLL_PORTB_READY_MASK
);
8252 if (IS_CHERRYVIEW(dev
))
8253 chv_crtc_clock_get(crtc
, pipe_config
);
8254 else if (IS_VALLEYVIEW(dev
))
8255 vlv_crtc_clock_get(crtc
, pipe_config
);
8257 i9xx_crtc_clock_get(crtc
, pipe_config
);
8262 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
8264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8265 struct intel_encoder
*encoder
;
8267 bool has_lvds
= false;
8268 bool has_cpu_edp
= false;
8269 bool has_panel
= false;
8270 bool has_ck505
= false;
8271 bool can_ssc
= false;
8273 /* We need to take the global config into account */
8274 for_each_intel_encoder(dev
, encoder
) {
8275 switch (encoder
->type
) {
8276 case INTEL_OUTPUT_LVDS
:
8280 case INTEL_OUTPUT_EDP
:
8282 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
8290 if (HAS_PCH_IBX(dev
)) {
8291 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8292 can_ssc
= has_ck505
;
8298 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8299 has_panel
, has_lvds
, has_ck505
);
8301 /* Ironlake: try to setup display ref clock before DPLL
8302 * enabling. This is only under driver's control after
8303 * PCH B stepping, previous chipset stepping should be
8304 * ignoring this setting.
8306 val
= I915_READ(PCH_DREF_CONTROL
);
8308 /* As we must carefully and slowly disable/enable each source in turn,
8309 * compute the final state we want first and check if we need to
8310 * make any changes at all.
8313 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8315 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8317 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8319 final
&= ~DREF_SSC_SOURCE_MASK
;
8320 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8321 final
&= ~DREF_SSC1_ENABLE
;
8324 final
|= DREF_SSC_SOURCE_ENABLE
;
8326 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8327 final
|= DREF_SSC1_ENABLE
;
8330 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8331 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8333 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8335 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8337 final
|= DREF_SSC_SOURCE_DISABLE
;
8338 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8344 /* Always enable nonspread source */
8345 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8348 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8350 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8353 val
&= ~DREF_SSC_SOURCE_MASK
;
8354 val
|= DREF_SSC_SOURCE_ENABLE
;
8356 /* SSC must be turned on before enabling the CPU output */
8357 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8358 DRM_DEBUG_KMS("Using SSC on panel\n");
8359 val
|= DREF_SSC1_ENABLE
;
8361 val
&= ~DREF_SSC1_ENABLE
;
8363 /* Get SSC going before enabling the outputs */
8364 I915_WRITE(PCH_DREF_CONTROL
, val
);
8365 POSTING_READ(PCH_DREF_CONTROL
);
8368 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8370 /* Enable CPU source on CPU attached eDP */
8372 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8373 DRM_DEBUG_KMS("Using SSC on eDP\n");
8374 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8376 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8378 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8380 I915_WRITE(PCH_DREF_CONTROL
, val
);
8381 POSTING_READ(PCH_DREF_CONTROL
);
8384 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8386 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8388 /* Turn off CPU output */
8389 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8391 I915_WRITE(PCH_DREF_CONTROL
, val
);
8392 POSTING_READ(PCH_DREF_CONTROL
);
8395 /* Turn off the SSC source */
8396 val
&= ~DREF_SSC_SOURCE_MASK
;
8397 val
|= DREF_SSC_SOURCE_DISABLE
;
8400 val
&= ~DREF_SSC1_ENABLE
;
8402 I915_WRITE(PCH_DREF_CONTROL
, val
);
8403 POSTING_READ(PCH_DREF_CONTROL
);
8407 BUG_ON(val
!= final
);
8410 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8414 tmp
= I915_READ(SOUTH_CHICKEN2
);
8415 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8416 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8418 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
8419 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8420 DRM_ERROR("FDI mPHY reset assert timeout\n");
8422 tmp
= I915_READ(SOUTH_CHICKEN2
);
8423 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8424 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8426 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
8427 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8428 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8431 /* WaMPhyProgramming:hsw */
8432 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8436 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8437 tmp
&= ~(0xFF << 24);
8438 tmp
|= (0x12 << 24);
8439 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8441 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8443 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8445 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8447 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8449 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8450 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8451 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8453 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8454 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8455 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8457 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8460 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8462 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8465 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8467 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8470 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8472 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8475 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8477 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8478 tmp
&= ~(0xFF << 16);
8479 tmp
|= (0x1C << 16);
8480 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8482 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8483 tmp
&= ~(0xFF << 16);
8484 tmp
|= (0x1C << 16);
8485 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8487 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8489 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8491 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8493 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8495 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8496 tmp
&= ~(0xF << 28);
8498 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8500 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8501 tmp
&= ~(0xF << 28);
8503 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8506 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8507 * Programming" based on the parameters passed:
8508 * - Sequence to enable CLKOUT_DP
8509 * - Sequence to enable CLKOUT_DP without spread
8510 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8512 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8518 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8520 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
8521 with_fdi
, "LP PCH doesn't have FDI\n"))
8524 mutex_lock(&dev_priv
->sb_lock
);
8526 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8527 tmp
&= ~SBI_SSCCTL_DISABLE
;
8528 tmp
|= SBI_SSCCTL_PATHALT
;
8529 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8534 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8535 tmp
&= ~SBI_SSCCTL_PATHALT
;
8536 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8539 lpt_reset_fdi_mphy(dev_priv
);
8540 lpt_program_fdi_mphy(dev_priv
);
8544 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8545 SBI_GEN0
: SBI_DBUFF0
;
8546 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8547 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8548 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8550 mutex_unlock(&dev_priv
->sb_lock
);
8553 /* Sequence to disable CLKOUT_DP */
8554 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8559 mutex_lock(&dev_priv
->sb_lock
);
8561 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8562 SBI_GEN0
: SBI_DBUFF0
;
8563 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8564 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8565 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8567 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8568 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8569 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8570 tmp
|= SBI_SSCCTL_PATHALT
;
8571 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8574 tmp
|= SBI_SSCCTL_DISABLE
;
8575 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8578 mutex_unlock(&dev_priv
->sb_lock
);
8581 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8583 struct intel_encoder
*encoder
;
8584 bool has_vga
= false;
8586 for_each_intel_encoder(dev
, encoder
) {
8587 switch (encoder
->type
) {
8588 case INTEL_OUTPUT_ANALOG
:
8597 lpt_enable_clkout_dp(dev
, true, true);
8599 lpt_disable_clkout_dp(dev
);
8603 * Initialize reference clocks when the driver loads
8605 void intel_init_pch_refclk(struct drm_device
*dev
)
8607 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8608 ironlake_init_pch_refclk(dev
);
8609 else if (HAS_PCH_LPT(dev
))
8610 lpt_init_pch_refclk(dev
);
8613 static int ironlake_get_refclk(struct intel_crtc_state
*crtc_state
)
8615 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
8616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8617 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8618 struct drm_connector
*connector
;
8619 struct drm_connector_state
*connector_state
;
8620 struct intel_encoder
*encoder
;
8621 int num_connectors
= 0, i
;
8622 bool is_lvds
= false;
8624 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8625 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8628 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8630 switch (encoder
->type
) {
8631 case INTEL_OUTPUT_LVDS
:
8640 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
8641 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8642 dev_priv
->vbt
.lvds_ssc_freq
);
8643 return dev_priv
->vbt
.lvds_ssc_freq
;
8649 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8651 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8652 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8653 int pipe
= intel_crtc
->pipe
;
8658 switch (intel_crtc
->config
->pipe_bpp
) {
8660 val
|= PIPECONF_6BPC
;
8663 val
|= PIPECONF_8BPC
;
8666 val
|= PIPECONF_10BPC
;
8669 val
|= PIPECONF_12BPC
;
8672 /* Case prevented by intel_choose_pipe_bpp_dither. */
8676 if (intel_crtc
->config
->dither
)
8677 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8679 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8680 val
|= PIPECONF_INTERLACED_ILK
;
8682 val
|= PIPECONF_PROGRESSIVE
;
8684 if (intel_crtc
->config
->limited_color_range
)
8685 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8687 I915_WRITE(PIPECONF(pipe
), val
);
8688 POSTING_READ(PIPECONF(pipe
));
8692 * Set up the pipe CSC unit.
8694 * Currently only full range RGB to limited range RGB conversion
8695 * is supported, but eventually this should handle various
8696 * RGB<->YCbCr scenarios as well.
8698 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
8700 struct drm_device
*dev
= crtc
->dev
;
8701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8702 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8703 int pipe
= intel_crtc
->pipe
;
8704 uint16_t coeff
= 0x7800; /* 1.0 */
8707 * TODO: Check what kind of values actually come out of the pipe
8708 * with these coeff/postoff values and adjust to get the best
8709 * accuracy. Perhaps we even need to take the bpc value into
8713 if (intel_crtc
->config
->limited_color_range
)
8714 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8717 * GY/GU and RY/RU should be the other way around according
8718 * to BSpec, but reality doesn't agree. Just set them up in
8719 * a way that results in the correct picture.
8721 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
8722 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
8724 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
8725 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
8727 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
8728 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
8730 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
8731 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
8732 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
8734 if (INTEL_INFO(dev
)->gen
> 6) {
8735 uint16_t postoff
= 0;
8737 if (intel_crtc
->config
->limited_color_range
)
8738 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
8740 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
8741 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
8742 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
8744 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
8746 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
8748 if (intel_crtc
->config
->limited_color_range
)
8749 mode
|= CSC_BLACK_SCREEN_OFFSET
;
8751 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
8755 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8757 struct drm_device
*dev
= crtc
->dev
;
8758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8759 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8760 enum pipe pipe
= intel_crtc
->pipe
;
8761 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8766 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
8767 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8769 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8770 val
|= PIPECONF_INTERLACED_ILK
;
8772 val
|= PIPECONF_PROGRESSIVE
;
8774 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8775 POSTING_READ(PIPECONF(cpu_transcoder
));
8777 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
8778 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
8780 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
8783 switch (intel_crtc
->config
->pipe_bpp
) {
8785 val
|= PIPEMISC_DITHER_6_BPC
;
8788 val
|= PIPEMISC_DITHER_8_BPC
;
8791 val
|= PIPEMISC_DITHER_10_BPC
;
8794 val
|= PIPEMISC_DITHER_12_BPC
;
8797 /* Case prevented by pipe_config_set_bpp. */
8801 if (intel_crtc
->config
->dither
)
8802 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8804 I915_WRITE(PIPEMISC(pipe
), val
);
8808 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
8809 struct intel_crtc_state
*crtc_state
,
8810 intel_clock_t
*clock
,
8811 bool *has_reduced_clock
,
8812 intel_clock_t
*reduced_clock
)
8814 struct drm_device
*dev
= crtc
->dev
;
8815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8817 const intel_limit_t
*limit
;
8818 bool ret
, is_lvds
= false;
8820 is_lvds
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
);
8822 refclk
= ironlake_get_refclk(crtc_state
);
8825 * Returns a set of divisors for the desired target clock with the given
8826 * refclk, or FALSE. The returned values represent the clock equation:
8827 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8829 limit
= intel_limit(crtc_state
, refclk
);
8830 ret
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
8831 crtc_state
->port_clock
,
8832 refclk
, NULL
, clock
);
8836 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
8838 * Ensure we match the reduced clock's P to the target clock.
8839 * If the clocks don't match, we can't switch the display clock
8840 * by using the FP0/FP1. In such case we will disable the LVDS
8841 * downclock feature.
8843 *has_reduced_clock
=
8844 dev_priv
->display
.find_dpll(limit
, crtc_state
,
8845 dev_priv
->lvds_downclock
,
8853 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8856 * Account for spread spectrum to avoid
8857 * oversubscribing the link. Max center spread
8858 * is 2.5%; use 5% for safety's sake.
8860 u32 bps
= target_clock
* bpp
* 21 / 20;
8861 return DIV_ROUND_UP(bps
, link_bw
* 8);
8864 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8866 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8869 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8870 struct intel_crtc_state
*crtc_state
,
8872 intel_clock_t
*reduced_clock
, u32
*fp2
)
8874 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8875 struct drm_device
*dev
= crtc
->dev
;
8876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8877 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8878 struct drm_connector
*connector
;
8879 struct drm_connector_state
*connector_state
;
8880 struct intel_encoder
*encoder
;
8882 int factor
, num_connectors
= 0, i
;
8883 bool is_lvds
= false, is_sdvo
= false;
8885 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8886 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8889 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8891 switch (encoder
->type
) {
8892 case INTEL_OUTPUT_LVDS
:
8895 case INTEL_OUTPUT_SDVO
:
8896 case INTEL_OUTPUT_HDMI
:
8906 /* Enable autotuning of the PLL clock (if permissible) */
8909 if ((intel_panel_use_ssc(dev_priv
) &&
8910 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8911 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8913 } else if (crtc_state
->sdvo_tv_clock
)
8916 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8919 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
8925 dpll
|= DPLLB_MODE_LVDS
;
8927 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8929 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8930 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8933 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8934 if (crtc_state
->has_dp_encoder
)
8935 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8937 /* compute bitmask from p1 value */
8938 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8940 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8942 switch (crtc_state
->dpll
.p2
) {
8944 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8947 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8950 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8953 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8957 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
8958 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8960 dpll
|= PLL_REF_INPUT_DREFCLK
;
8962 return dpll
| DPLL_VCO_ENABLE
;
8965 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8966 struct intel_crtc_state
*crtc_state
)
8968 struct drm_device
*dev
= crtc
->base
.dev
;
8969 intel_clock_t clock
, reduced_clock
;
8970 u32 dpll
= 0, fp
= 0, fp2
= 0;
8971 bool ok
, has_reduced_clock
= false;
8972 bool is_lvds
= false;
8973 struct intel_shared_dpll
*pll
;
8975 memset(&crtc_state
->dpll_hw_state
, 0,
8976 sizeof(crtc_state
->dpll_hw_state
));
8978 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
8980 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
8981 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
8983 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
8984 &has_reduced_clock
, &reduced_clock
);
8985 if (!ok
&& !crtc_state
->clock_set
) {
8986 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8989 /* Compat-code for transition, will disappear. */
8990 if (!crtc_state
->clock_set
) {
8991 crtc_state
->dpll
.n
= clock
.n
;
8992 crtc_state
->dpll
.m1
= clock
.m1
;
8993 crtc_state
->dpll
.m2
= clock
.m2
;
8994 crtc_state
->dpll
.p1
= clock
.p1
;
8995 crtc_state
->dpll
.p2
= clock
.p2
;
8998 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8999 if (crtc_state
->has_pch_encoder
) {
9000 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
9001 if (has_reduced_clock
)
9002 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
9004 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
9005 &fp
, &reduced_clock
,
9006 has_reduced_clock
? &fp2
: NULL
);
9008 crtc_state
->dpll_hw_state
.dpll
= dpll
;
9009 crtc_state
->dpll_hw_state
.fp0
= fp
;
9010 if (has_reduced_clock
)
9011 crtc_state
->dpll_hw_state
.fp1
= fp2
;
9013 crtc_state
->dpll_hw_state
.fp1
= fp
;
9015 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
9017 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9018 pipe_name(crtc
->pipe
));
9023 if (is_lvds
&& has_reduced_clock
)
9024 crtc
->lowfreq_avail
= true;
9026 crtc
->lowfreq_avail
= false;
9031 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
9032 struct intel_link_m_n
*m_n
)
9034 struct drm_device
*dev
= crtc
->base
.dev
;
9035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9036 enum pipe pipe
= crtc
->pipe
;
9038 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
9039 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
9040 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
9042 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
9043 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
9044 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9047 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
9048 enum transcoder transcoder
,
9049 struct intel_link_m_n
*m_n
,
9050 struct intel_link_m_n
*m2_n2
)
9052 struct drm_device
*dev
= crtc
->base
.dev
;
9053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9054 enum pipe pipe
= crtc
->pipe
;
9056 if (INTEL_INFO(dev
)->gen
>= 5) {
9057 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
9058 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
9059 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
9061 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
9062 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
9063 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9064 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9065 * gen < 8) and if DRRS is supported (to make sure the
9066 * registers are not unnecessarily read).
9068 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
9069 crtc
->config
->has_drrs
) {
9070 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
9071 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
9072 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
9074 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
9075 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
9076 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9079 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
9080 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
9081 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
9083 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
9084 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
9085 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9089 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
9090 struct intel_crtc_state
*pipe_config
)
9092 if (pipe_config
->has_pch_encoder
)
9093 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
9095 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9096 &pipe_config
->dp_m_n
,
9097 &pipe_config
->dp_m2_n2
);
9100 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9101 struct intel_crtc_state
*pipe_config
)
9103 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9104 &pipe_config
->fdi_m_n
, NULL
);
9107 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9108 struct intel_crtc_state
*pipe_config
)
9110 struct drm_device
*dev
= crtc
->base
.dev
;
9111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9112 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9113 uint32_t ps_ctrl
= 0;
9117 /* find scaler attached to this pipe */
9118 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9119 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9120 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9122 pipe_config
->pch_pfit
.enabled
= true;
9123 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9124 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9129 scaler_state
->scaler_id
= id
;
9131 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9133 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9138 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9139 struct intel_initial_plane_config
*plane_config
)
9141 struct drm_device
*dev
= crtc
->base
.dev
;
9142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9143 u32 val
, base
, offset
, stride_mult
, tiling
;
9144 int pipe
= crtc
->pipe
;
9145 int fourcc
, pixel_format
;
9146 unsigned int aligned_height
;
9147 struct drm_framebuffer
*fb
;
9148 struct intel_framebuffer
*intel_fb
;
9150 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9152 DRM_DEBUG_KMS("failed to alloc fb\n");
9156 fb
= &intel_fb
->base
;
9158 val
= I915_READ(PLANE_CTL(pipe
, 0));
9159 if (!(val
& PLANE_CTL_ENABLE
))
9162 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9163 fourcc
= skl_format_to_fourcc(pixel_format
,
9164 val
& PLANE_CTL_ORDER_RGBX
,
9165 val
& PLANE_CTL_ALPHA_MASK
);
9166 fb
->pixel_format
= fourcc
;
9167 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9169 tiling
= val
& PLANE_CTL_TILED_MASK
;
9171 case PLANE_CTL_TILED_LINEAR
:
9172 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
9174 case PLANE_CTL_TILED_X
:
9175 plane_config
->tiling
= I915_TILING_X
;
9176 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9178 case PLANE_CTL_TILED_Y
:
9179 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
9181 case PLANE_CTL_TILED_YF
:
9182 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
9185 MISSING_CASE(tiling
);
9189 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
9190 plane_config
->base
= base
;
9192 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
9194 val
= I915_READ(PLANE_SIZE(pipe
, 0));
9195 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9196 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9198 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
9199 stride_mult
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
9201 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9203 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9207 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9209 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9210 pipe_name(pipe
), fb
->width
, fb
->height
,
9211 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9212 plane_config
->size
);
9214 plane_config
->fb
= intel_fb
;
9221 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9222 struct intel_crtc_state
*pipe_config
)
9224 struct drm_device
*dev
= crtc
->base
.dev
;
9225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9228 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9230 if (tmp
& PF_ENABLE
) {
9231 pipe_config
->pch_pfit
.enabled
= true;
9232 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9233 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9235 /* We currently do not free assignements of panel fitters on
9236 * ivb/hsw (since we don't use the higher upscaling modes which
9237 * differentiates them) so just WARN about this case for now. */
9239 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9240 PF_PIPE_SEL_IVB(crtc
->pipe
));
9246 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
9247 struct intel_initial_plane_config
*plane_config
)
9249 struct drm_device
*dev
= crtc
->base
.dev
;
9250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9251 u32 val
, base
, offset
;
9252 int pipe
= crtc
->pipe
;
9253 int fourcc
, pixel_format
;
9254 unsigned int aligned_height
;
9255 struct drm_framebuffer
*fb
;
9256 struct intel_framebuffer
*intel_fb
;
9258 val
= I915_READ(DSPCNTR(pipe
));
9259 if (!(val
& DISPLAY_PLANE_ENABLE
))
9262 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9264 DRM_DEBUG_KMS("failed to alloc fb\n");
9268 fb
= &intel_fb
->base
;
9270 if (INTEL_INFO(dev
)->gen
>= 4) {
9271 if (val
& DISPPLANE_TILED
) {
9272 plane_config
->tiling
= I915_TILING_X
;
9273 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9277 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
9278 fourcc
= i9xx_format_to_fourcc(pixel_format
);
9279 fb
->pixel_format
= fourcc
;
9280 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9282 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
9283 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
9284 offset
= I915_READ(DSPOFFSET(pipe
));
9286 if (plane_config
->tiling
)
9287 offset
= I915_READ(DSPTILEOFF(pipe
));
9289 offset
= I915_READ(DSPLINOFF(pipe
));
9291 plane_config
->base
= base
;
9293 val
= I915_READ(PIPESRC(pipe
));
9294 fb
->width
= ((val
>> 16) & 0xfff) + 1;
9295 fb
->height
= ((val
>> 0) & 0xfff) + 1;
9297 val
= I915_READ(DSPSTRIDE(pipe
));
9298 fb
->pitches
[0] = val
& 0xffffffc0;
9300 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9304 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9306 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9307 pipe_name(pipe
), fb
->width
, fb
->height
,
9308 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9309 plane_config
->size
);
9311 plane_config
->fb
= intel_fb
;
9314 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9315 struct intel_crtc_state
*pipe_config
)
9317 struct drm_device
*dev
= crtc
->base
.dev
;
9318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9321 if (!intel_display_power_is_enabled(dev_priv
,
9322 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9325 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9326 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9328 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9329 if (!(tmp
& PIPECONF_ENABLE
))
9332 switch (tmp
& PIPECONF_BPC_MASK
) {
9334 pipe_config
->pipe_bpp
= 18;
9337 pipe_config
->pipe_bpp
= 24;
9339 case PIPECONF_10BPC
:
9340 pipe_config
->pipe_bpp
= 30;
9342 case PIPECONF_12BPC
:
9343 pipe_config
->pipe_bpp
= 36;
9349 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9350 pipe_config
->limited_color_range
= true;
9352 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9353 struct intel_shared_dpll
*pll
;
9355 pipe_config
->has_pch_encoder
= true;
9357 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9358 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9359 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9361 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9363 if (HAS_PCH_IBX(dev_priv
->dev
)) {
9364 pipe_config
->shared_dpll
=
9365 (enum intel_dpll_id
) crtc
->pipe
;
9367 tmp
= I915_READ(PCH_DPLL_SEL
);
9368 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9369 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
9371 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
9374 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9376 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9377 &pipe_config
->dpll_hw_state
));
9379 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9380 pipe_config
->pixel_multiplier
=
9381 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9382 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9384 ironlake_pch_clock_get(crtc
, pipe_config
);
9386 pipe_config
->pixel_multiplier
= 1;
9389 intel_get_pipe_timings(crtc
, pipe_config
);
9391 ironlake_get_pfit_config(crtc
, pipe_config
);
9396 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
9398 struct drm_device
*dev
= dev_priv
->dev
;
9399 struct intel_crtc
*crtc
;
9401 for_each_intel_crtc(dev
, crtc
)
9402 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
9403 pipe_name(crtc
->pipe
));
9405 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
9406 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
9407 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
9408 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
9409 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
9410 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
9411 "CPU PWM1 enabled\n");
9412 if (IS_HASWELL(dev
))
9413 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
9414 "CPU PWM2 enabled\n");
9415 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
9416 "PCH PWM1 enabled\n");
9417 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
9418 "Utility pin enabled\n");
9419 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
9422 * In theory we can still leave IRQs enabled, as long as only the HPD
9423 * interrupts remain enabled. We used to check for that, but since it's
9424 * gen-specific and since we only disable LCPLL after we fully disable
9425 * the interrupts, the check below should be enough.
9427 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
9430 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
9432 struct drm_device
*dev
= dev_priv
->dev
;
9434 if (IS_HASWELL(dev
))
9435 return I915_READ(D_COMP_HSW
);
9437 return I915_READ(D_COMP_BDW
);
9440 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
9442 struct drm_device
*dev
= dev_priv
->dev
;
9444 if (IS_HASWELL(dev
)) {
9445 mutex_lock(&dev_priv
->rps
.hw_lock
);
9446 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
9448 DRM_ERROR("Failed to write to D_COMP\n");
9449 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9451 I915_WRITE(D_COMP_BDW
, val
);
9452 POSTING_READ(D_COMP_BDW
);
9457 * This function implements pieces of two sequences from BSpec:
9458 * - Sequence for display software to disable LCPLL
9459 * - Sequence for display software to allow package C8+
9460 * The steps implemented here are just the steps that actually touch the LCPLL
9461 * register. Callers should take care of disabling all the display engine
9462 * functions, doing the mode unset, fixing interrupts, etc.
9464 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9465 bool switch_to_fclk
, bool allow_power_down
)
9469 assert_can_disable_lcpll(dev_priv
);
9471 val
= I915_READ(LCPLL_CTL
);
9473 if (switch_to_fclk
) {
9474 val
|= LCPLL_CD_SOURCE_FCLK
;
9475 I915_WRITE(LCPLL_CTL
, val
);
9477 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9478 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9479 DRM_ERROR("Switching to FCLK failed\n");
9481 val
= I915_READ(LCPLL_CTL
);
9484 val
|= LCPLL_PLL_DISABLE
;
9485 I915_WRITE(LCPLL_CTL
, val
);
9486 POSTING_READ(LCPLL_CTL
);
9488 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
9489 DRM_ERROR("LCPLL still locked\n");
9491 val
= hsw_read_dcomp(dev_priv
);
9492 val
|= D_COMP_COMP_DISABLE
;
9493 hsw_write_dcomp(dev_priv
, val
);
9496 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9498 DRM_ERROR("D_COMP RCOMP still in progress\n");
9500 if (allow_power_down
) {
9501 val
= I915_READ(LCPLL_CTL
);
9502 val
|= LCPLL_POWER_DOWN_ALLOW
;
9503 I915_WRITE(LCPLL_CTL
, val
);
9504 POSTING_READ(LCPLL_CTL
);
9509 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9512 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9516 val
= I915_READ(LCPLL_CTL
);
9518 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9519 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9523 * Make sure we're not on PC8 state before disabling PC8, otherwise
9524 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9526 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9528 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9529 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9530 I915_WRITE(LCPLL_CTL
, val
);
9531 POSTING_READ(LCPLL_CTL
);
9534 val
= hsw_read_dcomp(dev_priv
);
9535 val
|= D_COMP_COMP_FORCE
;
9536 val
&= ~D_COMP_COMP_DISABLE
;
9537 hsw_write_dcomp(dev_priv
, val
);
9539 val
= I915_READ(LCPLL_CTL
);
9540 val
&= ~LCPLL_PLL_DISABLE
;
9541 I915_WRITE(LCPLL_CTL
, val
);
9543 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
9544 DRM_ERROR("LCPLL not locked yet\n");
9546 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9547 val
= I915_READ(LCPLL_CTL
);
9548 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9549 I915_WRITE(LCPLL_CTL
, val
);
9551 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9552 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9553 DRM_ERROR("Switching back to LCPLL failed\n");
9556 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9557 intel_update_cdclk(dev_priv
->dev
);
9561 * Package states C8 and deeper are really deep PC states that can only be
9562 * reached when all the devices on the system allow it, so even if the graphics
9563 * device allows PC8+, it doesn't mean the system will actually get to these
9564 * states. Our driver only allows PC8+ when going into runtime PM.
9566 * The requirements for PC8+ are that all the outputs are disabled, the power
9567 * well is disabled and most interrupts are disabled, and these are also
9568 * requirements for runtime PM. When these conditions are met, we manually do
9569 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9570 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9573 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9574 * the state of some registers, so when we come back from PC8+ we need to
9575 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9576 * need to take care of the registers kept by RC6. Notice that this happens even
9577 * if we don't put the device in PCI D3 state (which is what currently happens
9578 * because of the runtime PM support).
9580 * For more, read "Display Sequences for Package C8" on the hardware
9583 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9585 struct drm_device
*dev
= dev_priv
->dev
;
9588 DRM_DEBUG_KMS("Enabling package C8+\n");
9590 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9591 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9592 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9593 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9596 lpt_disable_clkout_dp(dev
);
9597 hsw_disable_lcpll(dev_priv
, true, true);
9600 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9602 struct drm_device
*dev
= dev_priv
->dev
;
9605 DRM_DEBUG_KMS("Disabling package C8+\n");
9607 hsw_restore_lcpll(dev_priv
);
9608 lpt_init_pch_refclk(dev
);
9610 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9611 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9612 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9613 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9616 intel_prepare_ddi(dev
);
9619 static void broxton_modeset_global_resources(struct drm_atomic_state
*old_state
)
9621 struct drm_device
*dev
= old_state
->dev
;
9622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9623 int max_pixclk
= intel_mode_max_pixclk(dev
, NULL
);
9626 /* see the comment in valleyview_modeset_global_resources */
9627 if (WARN_ON(max_pixclk
< 0))
9630 req_cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
9632 if (req_cdclk
!= dev_priv
->cdclk_freq
)
9633 broxton_set_cdclk(dev
, req_cdclk
);
9636 /* compute the max rate for new configuration */
9637 static int ilk_max_pixel_rate(struct drm_i915_private
*dev_priv
)
9639 struct drm_device
*dev
= dev_priv
->dev
;
9640 struct intel_crtc
*intel_crtc
;
9641 struct drm_crtc
*crtc
;
9642 int max_pixel_rate
= 0;
9645 for_each_crtc(dev
, crtc
) {
9646 if (!crtc
->state
->enable
)
9649 intel_crtc
= to_intel_crtc(crtc
);
9650 pixel_rate
= ilk_pipe_pixel_rate(intel_crtc
->config
);
9652 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9653 if (IS_BROADWELL(dev
) && intel_crtc
->config
->ips_enabled
)
9654 pixel_rate
= DIV_ROUND_UP(pixel_rate
* 100, 95);
9656 max_pixel_rate
= max(max_pixel_rate
, pixel_rate
);
9659 return max_pixel_rate
;
9662 static void broadwell_set_cdclk(struct drm_device
*dev
, int cdclk
)
9664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9668 if (WARN((I915_READ(LCPLL_CTL
) &
9669 (LCPLL_PLL_DISABLE
| LCPLL_PLL_LOCK
|
9670 LCPLL_CD_CLOCK_DISABLE
| LCPLL_ROOT_CD_CLOCK_DISABLE
|
9671 LCPLL_CD2X_CLOCK_DISABLE
| LCPLL_POWER_DOWN_ALLOW
|
9672 LCPLL_CD_SOURCE_FCLK
)) != LCPLL_PLL_LOCK
,
9673 "trying to change cdclk frequency with cdclk not enabled\n"))
9676 mutex_lock(&dev_priv
->rps
.hw_lock
);
9677 ret
= sandybridge_pcode_write(dev_priv
,
9678 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
, 0x0);
9679 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9681 DRM_ERROR("failed to inform pcode about cdclk change\n");
9685 val
= I915_READ(LCPLL_CTL
);
9686 val
|= LCPLL_CD_SOURCE_FCLK
;
9687 I915_WRITE(LCPLL_CTL
, val
);
9689 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9690 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9691 DRM_ERROR("Switching to FCLK failed\n");
9693 val
= I915_READ(LCPLL_CTL
);
9694 val
&= ~LCPLL_CLK_FREQ_MASK
;
9698 val
|= LCPLL_CLK_FREQ_450
;
9702 val
|= LCPLL_CLK_FREQ_54O_BDW
;
9706 val
|= LCPLL_CLK_FREQ_337_5_BDW
;
9710 val
|= LCPLL_CLK_FREQ_675_BDW
;
9714 WARN(1, "invalid cdclk frequency\n");
9718 I915_WRITE(LCPLL_CTL
, val
);
9720 val
= I915_READ(LCPLL_CTL
);
9721 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9722 I915_WRITE(LCPLL_CTL
, val
);
9724 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9725 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9726 DRM_ERROR("Switching back to LCPLL failed\n");
9728 mutex_lock(&dev_priv
->rps
.hw_lock
);
9729 sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
, data
);
9730 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9732 intel_update_cdclk(dev
);
9734 WARN(cdclk
!= dev_priv
->cdclk_freq
,
9735 "cdclk requested %d kHz but got %d kHz\n",
9736 cdclk
, dev_priv
->cdclk_freq
);
9739 static int broadwell_calc_cdclk(struct drm_i915_private
*dev_priv
,
9745 * FIXME should also account for plane ratio
9746 * once 64bpp pixel formats are supported.
9748 if (max_pixel_rate
> 540000)
9750 else if (max_pixel_rate
> 450000)
9752 else if (max_pixel_rate
> 337500)
9758 * FIXME move the cdclk caclulation to
9759 * compute_config() so we can fail gracegully.
9761 if (cdclk
> dev_priv
->max_cdclk_freq
) {
9762 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9763 cdclk
, dev_priv
->max_cdclk_freq
);
9764 cdclk
= dev_priv
->max_cdclk_freq
;
9770 static int broadwell_modeset_global_pipes(struct drm_atomic_state
*state
)
9772 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9773 struct drm_crtc
*crtc
;
9774 struct drm_crtc_state
*crtc_state
;
9775 int max_pixclk
= ilk_max_pixel_rate(dev_priv
);
9778 cdclk
= broadwell_calc_cdclk(dev_priv
, max_pixclk
);
9780 if (cdclk
== dev_priv
->cdclk_freq
)
9783 /* add all active pipes to the state */
9784 for_each_crtc(state
->dev
, crtc
) {
9785 if (!crtc
->state
->enable
)
9788 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
9789 if (IS_ERR(crtc_state
))
9790 return PTR_ERR(crtc_state
);
9793 /* disable/enable all currently active pipes while we change cdclk */
9794 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
9795 if (crtc_state
->enable
)
9796 crtc_state
->mode_changed
= true;
9801 static void broadwell_modeset_global_resources(struct drm_atomic_state
*state
)
9803 struct drm_device
*dev
= state
->dev
;
9804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9805 int max_pixel_rate
= ilk_max_pixel_rate(dev_priv
);
9806 int req_cdclk
= broadwell_calc_cdclk(dev_priv
, max_pixel_rate
);
9808 if (req_cdclk
!= dev_priv
->cdclk_freq
)
9809 broadwell_set_cdclk(dev
, req_cdclk
);
9812 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9813 struct intel_crtc_state
*crtc_state
)
9815 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9818 crtc
->lowfreq_avail
= false;
9823 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9825 struct intel_crtc_state
*pipe_config
)
9829 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9830 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9833 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9834 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9837 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9838 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9841 DRM_ERROR("Incorrect port type\n");
9845 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9847 struct intel_crtc_state
*pipe_config
)
9849 u32 temp
, dpll_ctl1
;
9851 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9852 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9854 switch (pipe_config
->ddi_pll_sel
) {
9857 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9858 * of the shared DPLL framework and thus needs to be read out
9861 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
9862 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
9865 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9868 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9871 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9876 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9878 struct intel_crtc_state
*pipe_config
)
9880 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9882 switch (pipe_config
->ddi_pll_sel
) {
9883 case PORT_CLK_SEL_WRPLL1
:
9884 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
9886 case PORT_CLK_SEL_WRPLL2
:
9887 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
9892 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9893 struct intel_crtc_state
*pipe_config
)
9895 struct drm_device
*dev
= crtc
->base
.dev
;
9896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9897 struct intel_shared_dpll
*pll
;
9901 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9903 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9905 if (IS_SKYLAKE(dev
))
9906 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9907 else if (IS_BROXTON(dev
))
9908 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9910 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9912 if (pipe_config
->shared_dpll
>= 0) {
9913 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9915 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9916 &pipe_config
->dpll_hw_state
));
9920 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9921 * DDI E. So just check whether this pipe is wired to DDI E and whether
9922 * the PCH transcoder is on.
9924 if (INTEL_INFO(dev
)->gen
< 9 &&
9925 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9926 pipe_config
->has_pch_encoder
= true;
9928 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9929 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9930 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9932 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9936 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9937 struct intel_crtc_state
*pipe_config
)
9939 struct drm_device
*dev
= crtc
->base
.dev
;
9940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9941 enum intel_display_power_domain pfit_domain
;
9944 if (!intel_display_power_is_enabled(dev_priv
,
9945 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9948 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9949 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9951 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9952 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9953 enum pipe trans_edp_pipe
;
9954 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9956 WARN(1, "unknown pipe linked to edp transcoder\n");
9957 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9958 case TRANS_DDI_EDP_INPUT_A_ON
:
9959 trans_edp_pipe
= PIPE_A
;
9961 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9962 trans_edp_pipe
= PIPE_B
;
9964 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9965 trans_edp_pipe
= PIPE_C
;
9969 if (trans_edp_pipe
== crtc
->pipe
)
9970 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9973 if (!intel_display_power_is_enabled(dev_priv
,
9974 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
9977 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9978 if (!(tmp
& PIPECONF_ENABLE
))
9981 haswell_get_ddi_port_state(crtc
, pipe_config
);
9983 intel_get_pipe_timings(crtc
, pipe_config
);
9985 if (INTEL_INFO(dev
)->gen
>= 9) {
9986 skl_init_scalers(dev
, crtc
, pipe_config
);
9989 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
9991 if (INTEL_INFO(dev
)->gen
>= 9) {
9992 pipe_config
->scaler_state
.scaler_id
= -1;
9993 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9996 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
9997 if (INTEL_INFO(dev
)->gen
== 9)
9998 skylake_get_pfit_config(crtc
, pipe_config
);
9999 else if (INTEL_INFO(dev
)->gen
< 9)
10000 ironlake_get_pfit_config(crtc
, pipe_config
);
10002 MISSING_CASE(INTEL_INFO(dev
)->gen
);
10005 if (IS_HASWELL(dev
))
10006 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
10007 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
10009 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
10010 pipe_config
->pixel_multiplier
=
10011 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
10013 pipe_config
->pixel_multiplier
= 1;
10019 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
10021 struct drm_device
*dev
= crtc
->dev
;
10022 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10023 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10024 uint32_t cntl
= 0, size
= 0;
10027 unsigned int width
= intel_crtc
->base
.cursor
->state
->crtc_w
;
10028 unsigned int height
= intel_crtc
->base
.cursor
->state
->crtc_h
;
10029 unsigned int stride
= roundup_pow_of_two(width
) * 4;
10033 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10044 cntl
|= CURSOR_ENABLE
|
10045 CURSOR_GAMMA_ENABLE
|
10046 CURSOR_FORMAT_ARGB
|
10047 CURSOR_STRIDE(stride
);
10049 size
= (height
<< 12) | width
;
10052 if (intel_crtc
->cursor_cntl
!= 0 &&
10053 (intel_crtc
->cursor_base
!= base
||
10054 intel_crtc
->cursor_size
!= size
||
10055 intel_crtc
->cursor_cntl
!= cntl
)) {
10056 /* On these chipsets we can only modify the base/size/stride
10057 * whilst the cursor is disabled.
10059 I915_WRITE(_CURACNTR
, 0);
10060 POSTING_READ(_CURACNTR
);
10061 intel_crtc
->cursor_cntl
= 0;
10064 if (intel_crtc
->cursor_base
!= base
) {
10065 I915_WRITE(_CURABASE
, base
);
10066 intel_crtc
->cursor_base
= base
;
10069 if (intel_crtc
->cursor_size
!= size
) {
10070 I915_WRITE(CURSIZE
, size
);
10071 intel_crtc
->cursor_size
= size
;
10074 if (intel_crtc
->cursor_cntl
!= cntl
) {
10075 I915_WRITE(_CURACNTR
, cntl
);
10076 POSTING_READ(_CURACNTR
);
10077 intel_crtc
->cursor_cntl
= cntl
;
10081 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
10083 struct drm_device
*dev
= crtc
->dev
;
10084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10085 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10086 int pipe
= intel_crtc
->pipe
;
10091 cntl
= MCURSOR_GAMMA_ENABLE
;
10092 switch (intel_crtc
->base
.cursor
->state
->crtc_w
) {
10094 cntl
|= CURSOR_MODE_64_ARGB_AX
;
10097 cntl
|= CURSOR_MODE_128_ARGB_AX
;
10100 cntl
|= CURSOR_MODE_256_ARGB_AX
;
10103 MISSING_CASE(intel_crtc
->base
.cursor
->state
->crtc_w
);
10106 cntl
|= pipe
<< 28; /* Connect to correct pipe */
10108 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
10109 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
10112 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
10113 cntl
|= CURSOR_ROTATE_180
;
10115 if (intel_crtc
->cursor_cntl
!= cntl
) {
10116 I915_WRITE(CURCNTR(pipe
), cntl
);
10117 POSTING_READ(CURCNTR(pipe
));
10118 intel_crtc
->cursor_cntl
= cntl
;
10121 /* and commit changes on next vblank */
10122 I915_WRITE(CURBASE(pipe
), base
);
10123 POSTING_READ(CURBASE(pipe
));
10125 intel_crtc
->cursor_base
= base
;
10128 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10129 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
10132 struct drm_device
*dev
= crtc
->dev
;
10133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10134 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10135 int pipe
= intel_crtc
->pipe
;
10136 int x
= crtc
->cursor_x
;
10137 int y
= crtc
->cursor_y
;
10138 u32 base
= 0, pos
= 0;
10141 base
= intel_crtc
->cursor_addr
;
10143 if (x
>= intel_crtc
->config
->pipe_src_w
)
10146 if (y
>= intel_crtc
->config
->pipe_src_h
)
10150 if (x
+ intel_crtc
->base
.cursor
->state
->crtc_w
<= 0)
10153 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10156 pos
|= x
<< CURSOR_X_SHIFT
;
10159 if (y
+ intel_crtc
->base
.cursor
->state
->crtc_h
<= 0)
10162 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10165 pos
|= y
<< CURSOR_Y_SHIFT
;
10167 if (base
== 0 && intel_crtc
->cursor_base
== 0)
10170 I915_WRITE(CURPOS(pipe
), pos
);
10172 /* ILK+ do this automagically */
10173 if (HAS_GMCH_DISPLAY(dev
) &&
10174 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
10175 base
+= (intel_crtc
->base
.cursor
->state
->crtc_h
*
10176 intel_crtc
->base
.cursor
->state
->crtc_w
- 1) * 4;
10179 if (IS_845G(dev
) || IS_I865G(dev
))
10180 i845_update_cursor(crtc
, base
);
10182 i9xx_update_cursor(crtc
, base
);
10185 static bool cursor_size_ok(struct drm_device
*dev
,
10186 uint32_t width
, uint32_t height
)
10188 if (width
== 0 || height
== 0)
10192 * 845g/865g are special in that they are only limited by
10193 * the width of their cursors, the height is arbitrary up to
10194 * the precision of the register. Everything else requires
10195 * square cursors, limited to a few power-of-two sizes.
10197 if (IS_845G(dev
) || IS_I865G(dev
)) {
10198 if ((width
& 63) != 0)
10201 if (width
> (IS_845G(dev
) ? 64 : 512))
10207 switch (width
| height
) {
10222 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
10223 u16
*blue
, uint32_t start
, uint32_t size
)
10225 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
10226 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10228 for (i
= start
; i
< end
; i
++) {
10229 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
10230 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
10231 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
10234 intel_crtc_load_lut(crtc
);
10237 /* VESA 640x480x72Hz mode to set on the pipe */
10238 static struct drm_display_mode load_detect_mode
= {
10239 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10240 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10243 struct drm_framebuffer
*
10244 __intel_framebuffer_create(struct drm_device
*dev
,
10245 struct drm_mode_fb_cmd2
*mode_cmd
,
10246 struct drm_i915_gem_object
*obj
)
10248 struct intel_framebuffer
*intel_fb
;
10251 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10253 drm_gem_object_unreference(&obj
->base
);
10254 return ERR_PTR(-ENOMEM
);
10257 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
10261 return &intel_fb
->base
;
10263 drm_gem_object_unreference(&obj
->base
);
10266 return ERR_PTR(ret
);
10269 static struct drm_framebuffer
*
10270 intel_framebuffer_create(struct drm_device
*dev
,
10271 struct drm_mode_fb_cmd2
*mode_cmd
,
10272 struct drm_i915_gem_object
*obj
)
10274 struct drm_framebuffer
*fb
;
10277 ret
= i915_mutex_lock_interruptible(dev
);
10279 return ERR_PTR(ret
);
10280 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
10281 mutex_unlock(&dev
->struct_mutex
);
10287 intel_framebuffer_pitch_for_width(int width
, int bpp
)
10289 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
10290 return ALIGN(pitch
, 64);
10294 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
10296 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
10297 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
10300 static struct drm_framebuffer
*
10301 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
10302 struct drm_display_mode
*mode
,
10303 int depth
, int bpp
)
10305 struct drm_i915_gem_object
*obj
;
10306 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
10308 obj
= i915_gem_alloc_object(dev
,
10309 intel_framebuffer_size_for_mode(mode
, bpp
));
10311 return ERR_PTR(-ENOMEM
);
10313 mode_cmd
.width
= mode
->hdisplay
;
10314 mode_cmd
.height
= mode
->vdisplay
;
10315 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
10317 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
10319 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
10322 static struct drm_framebuffer
*
10323 mode_fits_in_fbdev(struct drm_device
*dev
,
10324 struct drm_display_mode
*mode
)
10326 #ifdef CONFIG_DRM_I915_FBDEV
10327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10328 struct drm_i915_gem_object
*obj
;
10329 struct drm_framebuffer
*fb
;
10331 if (!dev_priv
->fbdev
)
10334 if (!dev_priv
->fbdev
->fb
)
10337 obj
= dev_priv
->fbdev
->fb
->obj
;
10340 fb
= &dev_priv
->fbdev
->fb
->base
;
10341 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
10342 fb
->bits_per_pixel
))
10345 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
10354 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
10355 struct drm_crtc
*crtc
,
10356 struct drm_display_mode
*mode
,
10357 struct drm_framebuffer
*fb
,
10360 struct drm_plane_state
*plane_state
;
10361 int hdisplay
, vdisplay
;
10364 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
10365 if (IS_ERR(plane_state
))
10366 return PTR_ERR(plane_state
);
10369 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
10371 hdisplay
= vdisplay
= 0;
10373 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
10376 drm_atomic_set_fb_for_plane(plane_state
, fb
);
10377 plane_state
->crtc_x
= 0;
10378 plane_state
->crtc_y
= 0;
10379 plane_state
->crtc_w
= hdisplay
;
10380 plane_state
->crtc_h
= vdisplay
;
10381 plane_state
->src_x
= x
<< 16;
10382 plane_state
->src_y
= y
<< 16;
10383 plane_state
->src_w
= hdisplay
<< 16;
10384 plane_state
->src_h
= vdisplay
<< 16;
10389 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
10390 struct drm_display_mode
*mode
,
10391 struct intel_load_detect_pipe
*old
,
10392 struct drm_modeset_acquire_ctx
*ctx
)
10394 struct intel_crtc
*intel_crtc
;
10395 struct intel_encoder
*intel_encoder
=
10396 intel_attached_encoder(connector
);
10397 struct drm_crtc
*possible_crtc
;
10398 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10399 struct drm_crtc
*crtc
= NULL
;
10400 struct drm_device
*dev
= encoder
->dev
;
10401 struct drm_framebuffer
*fb
;
10402 struct drm_mode_config
*config
= &dev
->mode_config
;
10403 struct drm_atomic_state
*state
= NULL
;
10404 struct drm_connector_state
*connector_state
;
10405 struct intel_crtc_state
*crtc_state
;
10408 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10409 connector
->base
.id
, connector
->name
,
10410 encoder
->base
.id
, encoder
->name
);
10413 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
10418 * Algorithm gets a little messy:
10420 * - if the connector already has an assigned crtc, use it (but make
10421 * sure it's on first)
10423 * - try to find the first unused crtc that can drive this connector,
10424 * and use that if we find one
10427 /* See if we already have a CRTC for this connector */
10428 if (encoder
->crtc
) {
10429 crtc
= encoder
->crtc
;
10431 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10434 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10438 old
->dpms_mode
= connector
->dpms
;
10439 old
->load_detect_temp
= false;
10441 /* Make sure the crtc and connector are running */
10442 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
10443 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
10448 /* Find an unused one (if possible) */
10449 for_each_crtc(dev
, possible_crtc
) {
10451 if (!(encoder
->possible_crtcs
& (1 << i
)))
10453 if (possible_crtc
->state
->enable
)
10455 /* This can occur when applying the pipe A quirk on resume. */
10456 if (to_intel_crtc(possible_crtc
)->new_enabled
)
10459 crtc
= possible_crtc
;
10464 * If we didn't find an unused CRTC, don't use any.
10467 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10471 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10474 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10477 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
10478 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
10480 intel_crtc
= to_intel_crtc(crtc
);
10481 intel_crtc
->new_enabled
= true;
10482 old
->dpms_mode
= connector
->dpms
;
10483 old
->load_detect_temp
= true;
10484 old
->release_fb
= NULL
;
10486 state
= drm_atomic_state_alloc(dev
);
10490 state
->acquire_ctx
= ctx
;
10492 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10493 if (IS_ERR(connector_state
)) {
10494 ret
= PTR_ERR(connector_state
);
10498 connector_state
->crtc
= crtc
;
10499 connector_state
->best_encoder
= &intel_encoder
->base
;
10501 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10502 if (IS_ERR(crtc_state
)) {
10503 ret
= PTR_ERR(crtc_state
);
10507 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10510 mode
= &load_detect_mode
;
10512 /* We need a framebuffer large enough to accommodate all accesses
10513 * that the plane may generate whilst we perform load detection.
10514 * We can not rely on the fbcon either being present (we get called
10515 * during its initialisation to detect all boot displays, or it may
10516 * not even exist) or that it is large enough to satisfy the
10519 fb
= mode_fits_in_fbdev(dev
, mode
);
10521 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10522 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
10523 old
->release_fb
= fb
;
10525 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10527 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10531 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
10535 drm_mode_copy(&crtc_state
->base
.mode
, mode
);
10537 if (intel_set_mode(crtc
, state
)) {
10538 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10539 if (old
->release_fb
)
10540 old
->release_fb
->funcs
->destroy(old
->release_fb
);
10543 crtc
->primary
->crtc
= crtc
;
10545 /* let the connector get through one full cycle before testing */
10546 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
10550 intel_crtc
->new_enabled
= crtc
->state
->enable
;
10552 drm_atomic_state_free(state
);
10555 if (ret
== -EDEADLK
) {
10556 drm_modeset_backoff(ctx
);
10563 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10564 struct intel_load_detect_pipe
*old
,
10565 struct drm_modeset_acquire_ctx
*ctx
)
10567 struct drm_device
*dev
= connector
->dev
;
10568 struct intel_encoder
*intel_encoder
=
10569 intel_attached_encoder(connector
);
10570 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10571 struct drm_crtc
*crtc
= encoder
->crtc
;
10572 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10573 struct drm_atomic_state
*state
;
10574 struct drm_connector_state
*connector_state
;
10575 struct intel_crtc_state
*crtc_state
;
10578 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10579 connector
->base
.id
, connector
->name
,
10580 encoder
->base
.id
, encoder
->name
);
10582 if (old
->load_detect_temp
) {
10583 state
= drm_atomic_state_alloc(dev
);
10587 state
->acquire_ctx
= ctx
;
10589 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10590 if (IS_ERR(connector_state
))
10593 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10594 if (IS_ERR(crtc_state
))
10597 to_intel_connector(connector
)->new_encoder
= NULL
;
10598 intel_encoder
->new_crtc
= NULL
;
10599 intel_crtc
->new_enabled
= false;
10601 connector_state
->best_encoder
= NULL
;
10602 connector_state
->crtc
= NULL
;
10604 crtc_state
->base
.enable
= crtc_state
->base
.active
= false;
10606 ret
= intel_modeset_setup_plane_state(state
, crtc
, NULL
, NULL
,
10611 ret
= intel_set_mode(crtc
, state
);
10615 if (old
->release_fb
) {
10616 drm_framebuffer_unregister_private(old
->release_fb
);
10617 drm_framebuffer_unreference(old
->release_fb
);
10623 /* Switch crtc and encoder back off if necessary */
10624 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
10625 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
10629 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10630 drm_atomic_state_free(state
);
10633 static int i9xx_pll_refclk(struct drm_device
*dev
,
10634 const struct intel_crtc_state
*pipe_config
)
10636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10637 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10639 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10640 return dev_priv
->vbt
.lvds_ssc_freq
;
10641 else if (HAS_PCH_SPLIT(dev
))
10643 else if (!IS_GEN2(dev
))
10649 /* Returns the clock of the currently programmed mode of the given pipe. */
10650 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10651 struct intel_crtc_state
*pipe_config
)
10653 struct drm_device
*dev
= crtc
->base
.dev
;
10654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10655 int pipe
= pipe_config
->cpu_transcoder
;
10656 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10658 intel_clock_t clock
;
10659 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10661 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10662 fp
= pipe_config
->dpll_hw_state
.fp0
;
10664 fp
= pipe_config
->dpll_hw_state
.fp1
;
10666 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10667 if (IS_PINEVIEW(dev
)) {
10668 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10669 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10671 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10672 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10675 if (!IS_GEN2(dev
)) {
10676 if (IS_PINEVIEW(dev
))
10677 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10678 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10680 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10681 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10683 switch (dpll
& DPLL_MODE_MASK
) {
10684 case DPLLB_MODE_DAC_SERIAL
:
10685 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10688 case DPLLB_MODE_LVDS
:
10689 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10693 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10694 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10698 if (IS_PINEVIEW(dev
))
10699 pineview_clock(refclk
, &clock
);
10701 i9xx_clock(refclk
, &clock
);
10703 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10704 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10707 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10708 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10710 if (lvds
& LVDS_CLKB_POWER_UP
)
10715 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10718 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10719 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10721 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10727 i9xx_clock(refclk
, &clock
);
10731 * This value includes pixel_multiplier. We will use
10732 * port_clock to compute adjusted_mode.crtc_clock in the
10733 * encoder's get_config() function.
10735 pipe_config
->port_clock
= clock
.dot
;
10738 int intel_dotclock_calculate(int link_freq
,
10739 const struct intel_link_m_n
*m_n
)
10742 * The calculation for the data clock is:
10743 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10744 * But we want to avoid losing precison if possible, so:
10745 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10747 * and the link clock is simpler:
10748 * link_clock = (m * link_clock) / n
10754 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10757 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10758 struct intel_crtc_state
*pipe_config
)
10760 struct drm_device
*dev
= crtc
->base
.dev
;
10762 /* read out port_clock from the DPLL */
10763 i9xx_crtc_clock_get(crtc
, pipe_config
);
10766 * This value does not include pixel_multiplier.
10767 * We will check that port_clock and adjusted_mode.crtc_clock
10768 * agree once we know their relationship in the encoder's
10769 * get_config() function.
10771 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10772 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
10773 &pipe_config
->fdi_m_n
);
10776 /** Returns the currently programmed mode of the given pipe. */
10777 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10778 struct drm_crtc
*crtc
)
10780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10781 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10782 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10783 struct drm_display_mode
*mode
;
10784 struct intel_crtc_state pipe_config
;
10785 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10786 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10787 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10788 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10789 enum pipe pipe
= intel_crtc
->pipe
;
10791 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10796 * Construct a pipe_config sufficient for getting the clock info
10797 * back out of crtc_clock_get.
10799 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10800 * to use a real value here instead.
10802 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
10803 pipe_config
.pixel_multiplier
= 1;
10804 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10805 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10806 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10807 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
10809 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
10810 mode
->hdisplay
= (htot
& 0xffff) + 1;
10811 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10812 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10813 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10814 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10815 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10816 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10817 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10819 drm_mode_set_name(mode
);
10824 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
10826 struct drm_device
*dev
= crtc
->dev
;
10827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10828 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10830 if (!HAS_GMCH_DISPLAY(dev
))
10833 if (!dev_priv
->lvds_downclock_avail
)
10837 * Since this is called by a timer, we should never get here in
10840 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
10841 int pipe
= intel_crtc
->pipe
;
10842 int dpll_reg
= DPLL(pipe
);
10845 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10847 assert_panel_unlocked(dev_priv
, pipe
);
10849 dpll
= I915_READ(dpll_reg
);
10850 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
10851 I915_WRITE(dpll_reg
, dpll
);
10852 intel_wait_for_vblank(dev
, pipe
);
10853 dpll
= I915_READ(dpll_reg
);
10854 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
10855 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10860 void intel_mark_busy(struct drm_device
*dev
)
10862 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10864 if (dev_priv
->mm
.busy
)
10867 intel_runtime_pm_get(dev_priv
);
10868 i915_update_gfx_val(dev_priv
);
10869 if (INTEL_INFO(dev
)->gen
>= 6)
10870 gen6_rps_busy(dev_priv
);
10871 dev_priv
->mm
.busy
= true;
10874 void intel_mark_idle(struct drm_device
*dev
)
10876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10877 struct drm_crtc
*crtc
;
10879 if (!dev_priv
->mm
.busy
)
10882 dev_priv
->mm
.busy
= false;
10884 for_each_crtc(dev
, crtc
) {
10885 if (!crtc
->primary
->fb
)
10888 intel_decrease_pllclock(crtc
);
10891 if (INTEL_INFO(dev
)->gen
>= 6)
10892 gen6_rps_idle(dev
->dev_private
);
10894 intel_runtime_pm_put(dev_priv
);
10897 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10899 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10900 struct drm_device
*dev
= crtc
->dev
;
10901 struct intel_unpin_work
*work
;
10903 spin_lock_irq(&dev
->event_lock
);
10904 work
= intel_crtc
->unpin_work
;
10905 intel_crtc
->unpin_work
= NULL
;
10906 spin_unlock_irq(&dev
->event_lock
);
10909 cancel_work_sync(&work
->work
);
10913 drm_crtc_cleanup(crtc
);
10918 static void intel_unpin_work_fn(struct work_struct
*__work
)
10920 struct intel_unpin_work
*work
=
10921 container_of(__work
, struct intel_unpin_work
, work
);
10922 struct drm_device
*dev
= work
->crtc
->dev
;
10923 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
10925 mutex_lock(&dev
->struct_mutex
);
10926 intel_unpin_fb_obj(work
->old_fb
, work
->crtc
->primary
->state
);
10927 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10929 intel_fbc_update(dev
);
10931 if (work
->flip_queued_req
)
10932 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10933 mutex_unlock(&dev
->struct_mutex
);
10935 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
10936 drm_framebuffer_unreference(work
->old_fb
);
10938 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
10939 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
10944 static void do_intel_finish_page_flip(struct drm_device
*dev
,
10945 struct drm_crtc
*crtc
)
10947 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10948 struct intel_unpin_work
*work
;
10949 unsigned long flags
;
10951 /* Ignore early vblank irqs */
10952 if (intel_crtc
== NULL
)
10956 * This is called both by irq handlers and the reset code (to complete
10957 * lost pageflips) so needs the full irqsave spinlocks.
10959 spin_lock_irqsave(&dev
->event_lock
, flags
);
10960 work
= intel_crtc
->unpin_work
;
10962 /* Ensure we don't miss a work->pending update ... */
10965 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
10966 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10970 page_flip_completed(intel_crtc
);
10972 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10975 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
10977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10978 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10980 do_intel_finish_page_flip(dev
, crtc
);
10983 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
10985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10986 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
10988 do_intel_finish_page_flip(dev
, crtc
);
10991 /* Is 'a' after or equal to 'b'? */
10992 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10994 return !((a
- b
) & 0x80000000);
10997 static bool page_flip_finished(struct intel_crtc
*crtc
)
10999 struct drm_device
*dev
= crtc
->base
.dev
;
11000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11002 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
11003 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
11007 * The relevant registers doen't exist on pre-ctg.
11008 * As the flip done interrupt doesn't trigger for mmio
11009 * flips on gmch platforms, a flip count check isn't
11010 * really needed there. But since ctg has the registers,
11011 * include it in the check anyway.
11013 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
11017 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11018 * used the same base address. In that case the mmio flip might
11019 * have completed, but the CS hasn't even executed the flip yet.
11021 * A flip count check isn't enough as the CS might have updated
11022 * the base address just after start of vblank, but before we
11023 * managed to process the interrupt. This means we'd complete the
11024 * CS flip too soon.
11026 * Combining both checks should get us a good enough result. It may
11027 * still happen that the CS flip has been executed, but has not
11028 * yet actually completed. But in case the base address is the same
11029 * anyway, we don't really care.
11031 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
11032 crtc
->unpin_work
->gtt_offset
&&
11033 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
11034 crtc
->unpin_work
->flip_count
);
11037 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
11039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11040 struct intel_crtc
*intel_crtc
=
11041 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
11042 unsigned long flags
;
11046 * This is called both by irq handlers and the reset code (to complete
11047 * lost pageflips) so needs the full irqsave spinlocks.
11049 * NB: An MMIO update of the plane base pointer will also
11050 * generate a page-flip completion irq, i.e. every modeset
11051 * is also accompanied by a spurious intel_prepare_page_flip().
11053 spin_lock_irqsave(&dev
->event_lock
, flags
);
11054 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
11055 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
11056 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
11059 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
11061 /* Ensure that the work item is consistent when activating it ... */
11063 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
11064 /* and that it is marked active as soon as the irq could fire. */
11068 static int intel_gen2_queue_flip(struct drm_device
*dev
,
11069 struct drm_crtc
*crtc
,
11070 struct drm_framebuffer
*fb
,
11071 struct drm_i915_gem_object
*obj
,
11072 struct intel_engine_cs
*ring
,
11075 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11079 ret
= intel_ring_begin(ring
, 6);
11083 /* Can't queue multiple flips, so wait for the previous
11084 * one to finish before executing the next.
11086 if (intel_crtc
->plane
)
11087 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11089 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11090 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
11091 intel_ring_emit(ring
, MI_NOOP
);
11092 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
11093 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11094 intel_ring_emit(ring
, fb
->pitches
[0]);
11095 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
11096 intel_ring_emit(ring
, 0); /* aux display base address, unused */
11098 intel_mark_page_flip_active(intel_crtc
);
11099 __intel_ring_advance(ring
);
11103 static int intel_gen3_queue_flip(struct drm_device
*dev
,
11104 struct drm_crtc
*crtc
,
11105 struct drm_framebuffer
*fb
,
11106 struct drm_i915_gem_object
*obj
,
11107 struct intel_engine_cs
*ring
,
11110 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11114 ret
= intel_ring_begin(ring
, 6);
11118 if (intel_crtc
->plane
)
11119 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11121 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11122 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
11123 intel_ring_emit(ring
, MI_NOOP
);
11124 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
11125 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11126 intel_ring_emit(ring
, fb
->pitches
[0]);
11127 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
11128 intel_ring_emit(ring
, MI_NOOP
);
11130 intel_mark_page_flip_active(intel_crtc
);
11131 __intel_ring_advance(ring
);
11135 static int intel_gen4_queue_flip(struct drm_device
*dev
,
11136 struct drm_crtc
*crtc
,
11137 struct drm_framebuffer
*fb
,
11138 struct drm_i915_gem_object
*obj
,
11139 struct intel_engine_cs
*ring
,
11142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11143 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11144 uint32_t pf
, pipesrc
;
11147 ret
= intel_ring_begin(ring
, 4);
11151 /* i965+ uses the linear or tiled offsets from the
11152 * Display Registers (which do not change across a page-flip)
11153 * so we need only reprogram the base address.
11155 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
11156 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11157 intel_ring_emit(ring
, fb
->pitches
[0]);
11158 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
11161 /* XXX Enabling the panel-fitter across page-flip is so far
11162 * untested on non-native modes, so ignore it for now.
11163 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11166 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11167 intel_ring_emit(ring
, pf
| pipesrc
);
11169 intel_mark_page_flip_active(intel_crtc
);
11170 __intel_ring_advance(ring
);
11174 static int intel_gen6_queue_flip(struct drm_device
*dev
,
11175 struct drm_crtc
*crtc
,
11176 struct drm_framebuffer
*fb
,
11177 struct drm_i915_gem_object
*obj
,
11178 struct intel_engine_cs
*ring
,
11181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11182 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11183 uint32_t pf
, pipesrc
;
11186 ret
= intel_ring_begin(ring
, 4);
11190 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
11191 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11192 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
11193 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
11195 /* Contrary to the suggestions in the documentation,
11196 * "Enable Panel Fitter" does not seem to be required when page
11197 * flipping with a non-native mode, and worse causes a normal
11199 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11202 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11203 intel_ring_emit(ring
, pf
| pipesrc
);
11205 intel_mark_page_flip_active(intel_crtc
);
11206 __intel_ring_advance(ring
);
11210 static int intel_gen7_queue_flip(struct drm_device
*dev
,
11211 struct drm_crtc
*crtc
,
11212 struct drm_framebuffer
*fb
,
11213 struct drm_i915_gem_object
*obj
,
11214 struct intel_engine_cs
*ring
,
11217 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11218 uint32_t plane_bit
= 0;
11221 switch (intel_crtc
->plane
) {
11223 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
11226 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
11229 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
11232 WARN_ONCE(1, "unknown plane in flip command\n");
11237 if (ring
->id
== RCS
) {
11240 * On Gen 8, SRM is now taking an extra dword to accommodate
11241 * 48bits addresses, and we need a NOOP for the batch size to
11249 * BSpec MI_DISPLAY_FLIP for IVB:
11250 * "The full packet must be contained within the same cache line."
11252 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11253 * cacheline, if we ever start emitting more commands before
11254 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11255 * then do the cacheline alignment, and finally emit the
11258 ret
= intel_ring_cacheline_align(ring
);
11262 ret
= intel_ring_begin(ring
, len
);
11266 /* Unmask the flip-done completion message. Note that the bspec says that
11267 * we should do this for both the BCS and RCS, and that we must not unmask
11268 * more than one flip event at any time (or ensure that one flip message
11269 * can be sent by waiting for flip-done prior to queueing new flips).
11270 * Experimentation says that BCS works despite DERRMR masking all
11271 * flip-done completion events and that unmasking all planes at once
11272 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11273 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11275 if (ring
->id
== RCS
) {
11276 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
11277 intel_ring_emit(ring
, DERRMR
);
11278 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
11279 DERRMR_PIPEB_PRI_FLIP_DONE
|
11280 DERRMR_PIPEC_PRI_FLIP_DONE
));
11282 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
11283 MI_SRM_LRM_GLOBAL_GTT
);
11285 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
11286 MI_SRM_LRM_GLOBAL_GTT
);
11287 intel_ring_emit(ring
, DERRMR
);
11288 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
11289 if (IS_GEN8(dev
)) {
11290 intel_ring_emit(ring
, 0);
11291 intel_ring_emit(ring
, MI_NOOP
);
11295 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
11296 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
11297 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
11298 intel_ring_emit(ring
, (MI_NOOP
));
11300 intel_mark_page_flip_active(intel_crtc
);
11301 __intel_ring_advance(ring
);
11305 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
11306 struct drm_i915_gem_object
*obj
)
11309 * This is not being used for older platforms, because
11310 * non-availability of flip done interrupt forces us to use
11311 * CS flips. Older platforms derive flip done using some clever
11312 * tricks involving the flip_pending status bits and vblank irqs.
11313 * So using MMIO flips there would disrupt this mechanism.
11319 if (INTEL_INFO(ring
->dev
)->gen
< 5)
11322 if (i915
.use_mmio_flip
< 0)
11324 else if (i915
.use_mmio_flip
> 0)
11326 else if (i915
.enable_execlists
)
11329 return ring
!= i915_gem_request_get_ring(obj
->last_write_req
);
11332 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
11334 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11336 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
11337 const enum pipe pipe
= intel_crtc
->pipe
;
11340 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
11341 ctl
&= ~PLANE_CTL_TILED_MASK
;
11342 switch (fb
->modifier
[0]) {
11343 case DRM_FORMAT_MOD_NONE
:
11345 case I915_FORMAT_MOD_X_TILED
:
11346 ctl
|= PLANE_CTL_TILED_X
;
11348 case I915_FORMAT_MOD_Y_TILED
:
11349 ctl
|= PLANE_CTL_TILED_Y
;
11351 case I915_FORMAT_MOD_Yf_TILED
:
11352 ctl
|= PLANE_CTL_TILED_YF
;
11355 MISSING_CASE(fb
->modifier
[0]);
11359 * The stride is either expressed as a multiple of 64 bytes chunks for
11360 * linear buffers or in number of tiles for tiled buffers.
11362 stride
= fb
->pitches
[0] /
11363 intel_fb_stride_alignment(dev
, fb
->modifier
[0],
11367 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11368 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11370 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
11371 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
11373 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
11374 POSTING_READ(PLANE_SURF(pipe
, 0));
11377 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
11379 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11381 struct intel_framebuffer
*intel_fb
=
11382 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
11383 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11387 reg
= DSPCNTR(intel_crtc
->plane
);
11388 dspcntr
= I915_READ(reg
);
11390 if (obj
->tiling_mode
!= I915_TILING_NONE
)
11391 dspcntr
|= DISPPLANE_TILED
;
11393 dspcntr
&= ~DISPPLANE_TILED
;
11395 I915_WRITE(reg
, dspcntr
);
11397 I915_WRITE(DSPSURF(intel_crtc
->plane
),
11398 intel_crtc
->unpin_work
->gtt_offset
);
11399 POSTING_READ(DSPSURF(intel_crtc
->plane
));
11404 * XXX: This is the temporary way to update the plane registers until we get
11405 * around to using the usual plane update functions for MMIO flips
11407 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
11409 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11410 bool atomic_update
;
11411 u32 start_vbl_count
;
11413 intel_mark_page_flip_active(intel_crtc
);
11415 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
11417 if (INTEL_INFO(dev
)->gen
>= 9)
11418 skl_do_mmio_flip(intel_crtc
);
11420 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11421 ilk_do_mmio_flip(intel_crtc
);
11424 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
11427 static void intel_mmio_flip_work_func(struct work_struct
*work
)
11429 struct intel_mmio_flip
*mmio_flip
=
11430 container_of(work
, struct intel_mmio_flip
, work
);
11432 if (mmio_flip
->req
)
11433 WARN_ON(__i915_wait_request(mmio_flip
->req
,
11434 mmio_flip
->crtc
->reset_counter
,
11436 &mmio_flip
->i915
->rps
.mmioflips
));
11438 intel_do_mmio_flip(mmio_flip
->crtc
);
11440 i915_gem_request_unreference__unlocked(mmio_flip
->req
);
11444 static int intel_queue_mmio_flip(struct drm_device
*dev
,
11445 struct drm_crtc
*crtc
,
11446 struct drm_framebuffer
*fb
,
11447 struct drm_i915_gem_object
*obj
,
11448 struct intel_engine_cs
*ring
,
11451 struct intel_mmio_flip
*mmio_flip
;
11453 mmio_flip
= kmalloc(sizeof(*mmio_flip
), GFP_KERNEL
);
11454 if (mmio_flip
== NULL
)
11457 mmio_flip
->i915
= to_i915(dev
);
11458 mmio_flip
->req
= i915_gem_request_reference(obj
->last_write_req
);
11459 mmio_flip
->crtc
= to_intel_crtc(crtc
);
11461 INIT_WORK(&mmio_flip
->work
, intel_mmio_flip_work_func
);
11462 schedule_work(&mmio_flip
->work
);
11467 static int intel_default_queue_flip(struct drm_device
*dev
,
11468 struct drm_crtc
*crtc
,
11469 struct drm_framebuffer
*fb
,
11470 struct drm_i915_gem_object
*obj
,
11471 struct intel_engine_cs
*ring
,
11477 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
11478 struct drm_crtc
*crtc
)
11480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11481 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11482 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
11485 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
11488 if (!work
->enable_stall_check
)
11491 if (work
->flip_ready_vblank
== 0) {
11492 if (work
->flip_queued_req
&&
11493 !i915_gem_request_completed(work
->flip_queued_req
, true))
11496 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
11499 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
11502 /* Potential stall - if we see that the flip has happened,
11503 * assume a missed interrupt. */
11504 if (INTEL_INFO(dev
)->gen
>= 4)
11505 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
11507 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
11509 /* There is a potential issue here with a false positive after a flip
11510 * to the same address. We could address this by checking for a
11511 * non-incrementing frame counter.
11513 return addr
== work
->gtt_offset
;
11516 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
11518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11519 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11520 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11521 struct intel_unpin_work
*work
;
11523 WARN_ON(!in_interrupt());
11528 spin_lock(&dev
->event_lock
);
11529 work
= intel_crtc
->unpin_work
;
11530 if (work
!= NULL
&& __intel_pageflip_stall_check(dev
, crtc
)) {
11531 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11532 work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
11533 page_flip_completed(intel_crtc
);
11536 if (work
!= NULL
&&
11537 drm_vblank_count(dev
, pipe
) - work
->flip_queued_vblank
> 1)
11538 intel_queue_rps_boost_for_request(dev
, work
->flip_queued_req
);
11539 spin_unlock(&dev
->event_lock
);
11542 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
11543 struct drm_framebuffer
*fb
,
11544 struct drm_pending_vblank_event
*event
,
11545 uint32_t page_flip_flags
)
11547 struct drm_device
*dev
= crtc
->dev
;
11548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11549 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11550 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11551 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11552 struct drm_plane
*primary
= crtc
->primary
;
11553 enum pipe pipe
= intel_crtc
->pipe
;
11554 struct intel_unpin_work
*work
;
11555 struct intel_engine_cs
*ring
;
11560 * drm_mode_page_flip_ioctl() should already catch this, but double
11561 * check to be safe. In the future we may enable pageflipping from
11562 * a disabled primary plane.
11564 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
11567 /* Can't change pixel format via MI display flips. */
11568 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
11572 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11573 * Note that pitch changes could also affect these register.
11575 if (INTEL_INFO(dev
)->gen
> 3 &&
11576 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
11577 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
11580 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
11583 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
11587 work
->event
= event
;
11589 work
->old_fb
= old_fb
;
11590 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
11592 ret
= drm_crtc_vblank_get(crtc
);
11596 /* We borrow the event spin lock for protecting unpin_work */
11597 spin_lock_irq(&dev
->event_lock
);
11598 if (intel_crtc
->unpin_work
) {
11599 /* Before declaring the flip queue wedged, check if
11600 * the hardware completed the operation behind our backs.
11602 if (__intel_pageflip_stall_check(dev
, crtc
)) {
11603 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11604 page_flip_completed(intel_crtc
);
11606 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11607 spin_unlock_irq(&dev
->event_lock
);
11609 drm_crtc_vblank_put(crtc
);
11614 intel_crtc
->unpin_work
= work
;
11615 spin_unlock_irq(&dev
->event_lock
);
11617 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
11618 flush_workqueue(dev_priv
->wq
);
11620 /* Reference the objects for the scheduled work. */
11621 drm_framebuffer_reference(work
->old_fb
);
11622 drm_gem_object_reference(&obj
->base
);
11624 crtc
->primary
->fb
= fb
;
11625 update_state_fb(crtc
->primary
);
11627 work
->pending_flip_obj
= obj
;
11629 ret
= i915_mutex_lock_interruptible(dev
);
11633 atomic_inc(&intel_crtc
->unpin_work_count
);
11634 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
11636 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
11637 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
11639 if (IS_VALLEYVIEW(dev
)) {
11640 ring
= &dev_priv
->ring
[BCS
];
11641 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
11642 /* vlv: DISPLAY_FLIP fails to change tiling */
11644 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
11645 ring
= &dev_priv
->ring
[BCS
];
11646 } else if (INTEL_INFO(dev
)->gen
>= 7) {
11647 ring
= i915_gem_request_get_ring(obj
->last_write_req
);
11648 if (ring
== NULL
|| ring
->id
!= RCS
)
11649 ring
= &dev_priv
->ring
[BCS
];
11651 ring
= &dev_priv
->ring
[RCS
];
11654 mmio_flip
= use_mmio_flip(ring
, obj
);
11656 /* When using CS flips, we want to emit semaphores between rings.
11657 * However, when using mmio flips we will create a task to do the
11658 * synchronisation, so all we want here is to pin the framebuffer
11659 * into the display plane and skip any waits.
11661 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
,
11662 crtc
->primary
->state
,
11663 mmio_flip
? i915_gem_request_get_ring(obj
->last_write_req
) : ring
);
11665 goto cleanup_pending
;
11667 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
), obj
)
11668 + intel_crtc
->dspaddr_offset
;
11671 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
11674 goto cleanup_unpin
;
11676 i915_gem_request_assign(&work
->flip_queued_req
,
11677 obj
->last_write_req
);
11679 if (obj
->last_write_req
) {
11680 ret
= i915_gem_check_olr(obj
->last_write_req
);
11682 goto cleanup_unpin
;
11685 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
11688 goto cleanup_unpin
;
11690 i915_gem_request_assign(&work
->flip_queued_req
,
11691 intel_ring_get_request(ring
));
11694 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
11695 work
->enable_stall_check
= true;
11697 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
11698 INTEL_FRONTBUFFER_PRIMARY(pipe
));
11700 intel_fbc_disable(dev
);
11701 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
11702 mutex_unlock(&dev
->struct_mutex
);
11704 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11709 intel_unpin_fb_obj(fb
, crtc
->primary
->state
);
11711 atomic_dec(&intel_crtc
->unpin_work_count
);
11712 mutex_unlock(&dev
->struct_mutex
);
11714 crtc
->primary
->fb
= old_fb
;
11715 update_state_fb(crtc
->primary
);
11717 drm_gem_object_unreference_unlocked(&obj
->base
);
11718 drm_framebuffer_unreference(work
->old_fb
);
11720 spin_lock_irq(&dev
->event_lock
);
11721 intel_crtc
->unpin_work
= NULL
;
11722 spin_unlock_irq(&dev
->event_lock
);
11724 drm_crtc_vblank_put(crtc
);
11730 ret
= intel_plane_restore(primary
);
11731 if (ret
== 0 && event
) {
11732 spin_lock_irq(&dev
->event_lock
);
11733 drm_send_vblank_event(dev
, pipe
, event
);
11734 spin_unlock_irq(&dev
->event_lock
);
11740 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11741 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
11742 .load_lut
= intel_crtc_load_lut
,
11743 .atomic_begin
= intel_begin_crtc_commit
,
11744 .atomic_flush
= intel_finish_crtc_commit
,
11748 * intel_modeset_update_staged_output_state
11750 * Updates the staged output configuration state, e.g. after we've read out the
11751 * current hw state.
11753 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
11755 struct intel_crtc
*crtc
;
11756 struct intel_encoder
*encoder
;
11757 struct intel_connector
*connector
;
11759 for_each_intel_connector(dev
, connector
) {
11760 connector
->new_encoder
=
11761 to_intel_encoder(connector
->base
.encoder
);
11764 for_each_intel_encoder(dev
, encoder
) {
11765 encoder
->new_crtc
=
11766 to_intel_crtc(encoder
->base
.crtc
);
11769 for_each_intel_crtc(dev
, crtc
) {
11770 crtc
->new_enabled
= crtc
->base
.state
->enable
;
11774 /* Transitional helper to copy current connector/encoder state to
11775 * connector->state. This is needed so that code that is partially
11776 * converted to atomic does the right thing.
11778 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11780 struct intel_connector
*connector
;
11782 for_each_intel_connector(dev
, connector
) {
11783 if (connector
->base
.encoder
) {
11784 connector
->base
.state
->best_encoder
=
11785 connector
->base
.encoder
;
11786 connector
->base
.state
->crtc
=
11787 connector
->base
.encoder
->crtc
;
11789 connector
->base
.state
->best_encoder
= NULL
;
11790 connector
->base
.state
->crtc
= NULL
;
11795 /* Fixup legacy state after an atomic state swap.
11797 static void intel_modeset_fixup_state(struct drm_atomic_state
*state
)
11799 struct intel_crtc
*crtc
;
11800 struct intel_encoder
*encoder
;
11801 struct intel_connector
*connector
;
11803 for_each_intel_connector(state
->dev
, connector
) {
11804 connector
->base
.encoder
= connector
->base
.state
->best_encoder
;
11805 if (connector
->base
.encoder
)
11806 connector
->base
.encoder
->crtc
=
11807 connector
->base
.state
->crtc
;
11810 /* Update crtc of disabled encoders */
11811 for_each_intel_encoder(state
->dev
, encoder
) {
11812 int num_connectors
= 0;
11814 for_each_intel_connector(state
->dev
, connector
)
11815 if (connector
->base
.encoder
== &encoder
->base
)
11818 if (num_connectors
== 0)
11819 encoder
->base
.crtc
= NULL
;
11822 for_each_intel_crtc(state
->dev
, crtc
) {
11823 crtc
->base
.enabled
= crtc
->base
.state
->enable
;
11824 crtc
->config
= to_intel_crtc_state(crtc
->base
.state
);
11827 /* Copy the new configuration to the staged state, to keep the few
11828 * pieces of code that haven't been converted yet happy */
11829 intel_modeset_update_staged_output_state(state
->dev
);
11833 connected_sink_compute_bpp(struct intel_connector
*connector
,
11834 struct intel_crtc_state
*pipe_config
)
11836 int bpp
= pipe_config
->pipe_bpp
;
11838 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11839 connector
->base
.base
.id
,
11840 connector
->base
.name
);
11842 /* Don't use an invalid EDID bpc value */
11843 if (connector
->base
.display_info
.bpc
&&
11844 connector
->base
.display_info
.bpc
* 3 < bpp
) {
11845 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11846 bpp
, connector
->base
.display_info
.bpc
*3);
11847 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
11850 /* Clamp bpp to 8 on screens without EDID 1.4 */
11851 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
11852 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11854 pipe_config
->pipe_bpp
= 24;
11859 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
11860 struct intel_crtc_state
*pipe_config
)
11862 struct drm_device
*dev
= crtc
->base
.dev
;
11863 struct drm_atomic_state
*state
;
11864 struct drm_connector
*connector
;
11865 struct drm_connector_state
*connector_state
;
11868 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)))
11870 else if (INTEL_INFO(dev
)->gen
>= 5)
11876 pipe_config
->pipe_bpp
= bpp
;
11878 state
= pipe_config
->base
.state
;
11880 /* Clamp display bpp to EDID value */
11881 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11882 if (connector_state
->crtc
!= &crtc
->base
)
11885 connected_sink_compute_bpp(to_intel_connector(connector
),
11892 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
11894 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11895 "type: 0x%x flags: 0x%x\n",
11897 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
11898 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
11899 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
11900 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
11903 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
11904 struct intel_crtc_state
*pipe_config
,
11905 const char *context
)
11907 struct drm_device
*dev
= crtc
->base
.dev
;
11908 struct drm_plane
*plane
;
11909 struct intel_plane
*intel_plane
;
11910 struct intel_plane_state
*state
;
11911 struct drm_framebuffer
*fb
;
11913 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc
->base
.base
.id
,
11914 context
, pipe_config
, pipe_name(crtc
->pipe
));
11916 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
11917 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11918 pipe_config
->pipe_bpp
, pipe_config
->dither
);
11919 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11920 pipe_config
->has_pch_encoder
,
11921 pipe_config
->fdi_lanes
,
11922 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
11923 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
11924 pipe_config
->fdi_m_n
.tu
);
11925 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11926 pipe_config
->has_dp_encoder
,
11927 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
11928 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
11929 pipe_config
->dp_m_n
.tu
);
11931 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11932 pipe_config
->has_dp_encoder
,
11933 pipe_config
->dp_m2_n2
.gmch_m
,
11934 pipe_config
->dp_m2_n2
.gmch_n
,
11935 pipe_config
->dp_m2_n2
.link_m
,
11936 pipe_config
->dp_m2_n2
.link_n
,
11937 pipe_config
->dp_m2_n2
.tu
);
11939 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11940 pipe_config
->has_audio
,
11941 pipe_config
->has_infoframe
);
11943 DRM_DEBUG_KMS("requested mode:\n");
11944 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
11945 DRM_DEBUG_KMS("adjusted mode:\n");
11946 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
11947 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
11948 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
11949 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11950 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
11951 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11953 pipe_config
->scaler_state
.scaler_users
,
11954 pipe_config
->scaler_state
.scaler_id
);
11955 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11956 pipe_config
->gmch_pfit
.control
,
11957 pipe_config
->gmch_pfit
.pgm_ratios
,
11958 pipe_config
->gmch_pfit
.lvds_border_bits
);
11959 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11960 pipe_config
->pch_pfit
.pos
,
11961 pipe_config
->pch_pfit
.size
,
11962 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
11963 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
11964 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
11966 if (IS_BROXTON(dev
)) {
11967 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11968 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11969 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11970 pipe_config
->ddi_pll_sel
,
11971 pipe_config
->dpll_hw_state
.ebb0
,
11972 pipe_config
->dpll_hw_state
.pll0
,
11973 pipe_config
->dpll_hw_state
.pll1
,
11974 pipe_config
->dpll_hw_state
.pll2
,
11975 pipe_config
->dpll_hw_state
.pll3
,
11976 pipe_config
->dpll_hw_state
.pll6
,
11977 pipe_config
->dpll_hw_state
.pll8
,
11978 pipe_config
->dpll_hw_state
.pcsdw12
);
11979 } else if (IS_SKYLAKE(dev
)) {
11980 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11981 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11982 pipe_config
->ddi_pll_sel
,
11983 pipe_config
->dpll_hw_state
.ctrl1
,
11984 pipe_config
->dpll_hw_state
.cfgcr1
,
11985 pipe_config
->dpll_hw_state
.cfgcr2
);
11986 } else if (HAS_DDI(dev
)) {
11987 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11988 pipe_config
->ddi_pll_sel
,
11989 pipe_config
->dpll_hw_state
.wrpll
);
11991 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11992 "fp0: 0x%x, fp1: 0x%x\n",
11993 pipe_config
->dpll_hw_state
.dpll
,
11994 pipe_config
->dpll_hw_state
.dpll_md
,
11995 pipe_config
->dpll_hw_state
.fp0
,
11996 pipe_config
->dpll_hw_state
.fp1
);
11999 DRM_DEBUG_KMS("planes on this crtc\n");
12000 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
12001 intel_plane
= to_intel_plane(plane
);
12002 if (intel_plane
->pipe
!= crtc
->pipe
)
12005 state
= to_intel_plane_state(plane
->state
);
12006 fb
= state
->base
.fb
;
12008 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12009 "disabled, scaler_id = %d\n",
12010 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12011 plane
->base
.id
, intel_plane
->pipe
,
12012 (crtc
->base
.primary
== plane
) ? 0 : intel_plane
->plane
+ 1,
12013 drm_plane_index(plane
), state
->scaler_id
);
12017 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12018 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12019 plane
->base
.id
, intel_plane
->pipe
,
12020 crtc
->base
.primary
== plane
? 0 : intel_plane
->plane
+ 1,
12021 drm_plane_index(plane
));
12022 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12023 fb
->base
.id
, fb
->width
, fb
->height
, fb
->pixel_format
);
12024 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12026 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
12027 drm_rect_width(&state
->src
) >> 16,
12028 drm_rect_height(&state
->src
) >> 16,
12029 state
->dst
.x1
, state
->dst
.y1
,
12030 drm_rect_width(&state
->dst
), drm_rect_height(&state
->dst
));
12034 static bool encoders_cloneable(const struct intel_encoder
*a
,
12035 const struct intel_encoder
*b
)
12037 /* masks could be asymmetric, so check both ways */
12038 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
12039 b
->cloneable
& (1 << a
->type
));
12042 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
12043 struct intel_crtc
*crtc
,
12044 struct intel_encoder
*encoder
)
12046 struct intel_encoder
*source_encoder
;
12047 struct drm_connector
*connector
;
12048 struct drm_connector_state
*connector_state
;
12051 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12052 if (connector_state
->crtc
!= &crtc
->base
)
12056 to_intel_encoder(connector_state
->best_encoder
);
12057 if (!encoders_cloneable(encoder
, source_encoder
))
12064 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
12065 struct intel_crtc
*crtc
)
12067 struct intel_encoder
*encoder
;
12068 struct drm_connector
*connector
;
12069 struct drm_connector_state
*connector_state
;
12072 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12073 if (connector_state
->crtc
!= &crtc
->base
)
12076 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12077 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
12084 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
12086 struct drm_device
*dev
= state
->dev
;
12087 struct intel_encoder
*encoder
;
12088 struct drm_connector
*connector
;
12089 struct drm_connector_state
*connector_state
;
12090 unsigned int used_ports
= 0;
12094 * Walk the connector list instead of the encoder
12095 * list to detect the problem on ddi platforms
12096 * where there's just one encoder per digital port.
12098 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12099 if (!connector_state
->best_encoder
)
12102 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12104 WARN_ON(!connector_state
->crtc
);
12106 switch (encoder
->type
) {
12107 unsigned int port_mask
;
12108 case INTEL_OUTPUT_UNKNOWN
:
12109 if (WARN_ON(!HAS_DDI(dev
)))
12111 case INTEL_OUTPUT_DISPLAYPORT
:
12112 case INTEL_OUTPUT_HDMI
:
12113 case INTEL_OUTPUT_EDP
:
12114 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
12116 /* the same port mustn't appear more than once */
12117 if (used_ports
& port_mask
)
12120 used_ports
|= port_mask
;
12130 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
12132 struct drm_crtc_state tmp_state
;
12133 struct intel_crtc_scaler_state scaler_state
;
12134 struct intel_dpll_hw_state dpll_hw_state
;
12135 enum intel_dpll_id shared_dpll
;
12136 uint32_t ddi_pll_sel
;
12138 /* FIXME: before the switch to atomic started, a new pipe_config was
12139 * kzalloc'd. Code that depends on any field being zero should be
12140 * fixed, so that the crtc_state can be safely duplicated. For now,
12141 * only fields that are know to not cause problems are preserved. */
12143 tmp_state
= crtc_state
->base
;
12144 scaler_state
= crtc_state
->scaler_state
;
12145 shared_dpll
= crtc_state
->shared_dpll
;
12146 dpll_hw_state
= crtc_state
->dpll_hw_state
;
12147 ddi_pll_sel
= crtc_state
->ddi_pll_sel
;
12149 memset(crtc_state
, 0, sizeof *crtc_state
);
12151 crtc_state
->base
= tmp_state
;
12152 crtc_state
->scaler_state
= scaler_state
;
12153 crtc_state
->shared_dpll
= shared_dpll
;
12154 crtc_state
->dpll_hw_state
= dpll_hw_state
;
12155 crtc_state
->ddi_pll_sel
= ddi_pll_sel
;
12159 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
12160 struct drm_atomic_state
*state
,
12161 struct intel_crtc_state
*pipe_config
)
12163 struct intel_encoder
*encoder
;
12164 struct drm_connector
*connector
;
12165 struct drm_connector_state
*connector_state
;
12166 int base_bpp
, ret
= -EINVAL
;
12170 if (!check_encoder_cloning(state
, to_intel_crtc(crtc
))) {
12171 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12175 if (!check_digital_port_conflicts(state
)) {
12176 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12180 clear_intel_crtc_state(pipe_config
);
12182 pipe_config
->cpu_transcoder
=
12183 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
12186 * Sanitize sync polarity flags based on requested ones. If neither
12187 * positive or negative polarity is requested, treat this as meaning
12188 * negative polarity.
12190 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12191 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
12192 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
12194 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12195 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
12196 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
12198 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12199 * plane pixel format and any sink constraints into account. Returns the
12200 * source plane bpp so that dithering can be selected on mismatches
12201 * after encoders and crtc also have had their say. */
12202 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
12208 * Determine the real pipe dimensions. Note that stereo modes can
12209 * increase the actual pipe size due to the frame doubling and
12210 * insertion of additional space for blanks between the frame. This
12211 * is stored in the crtc timings. We use the requested mode to do this
12212 * computation to clearly distinguish it from the adjusted mode, which
12213 * can be changed by the connectors in the below retry loop.
12215 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
12216 &pipe_config
->pipe_src_w
,
12217 &pipe_config
->pipe_src_h
);
12220 /* Ensure the port clock defaults are reset when retrying. */
12221 pipe_config
->port_clock
= 0;
12222 pipe_config
->pixel_multiplier
= 1;
12224 /* Fill in default crtc timings, allow encoders to overwrite them. */
12225 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
12226 CRTC_STEREO_DOUBLE
);
12228 /* Pass our mode to the connectors and the CRTC to give them a chance to
12229 * adjust it according to limitations or connector properties, and also
12230 * a chance to reject the mode entirely.
12232 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12233 if (connector_state
->crtc
!= crtc
)
12236 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12238 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
12239 DRM_DEBUG_KMS("Encoder config failure\n");
12244 /* Set default port clock if not overwritten by the encoder. Needs to be
12245 * done afterwards in case the encoder adjusts the mode. */
12246 if (!pipe_config
->port_clock
)
12247 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
12248 * pipe_config
->pixel_multiplier
;
12250 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
12252 DRM_DEBUG_KMS("CRTC fixup failed\n");
12256 if (ret
== RETRY
) {
12257 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
12262 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12264 goto encoder_retry
;
12267 pipe_config
->dither
= pipe_config
->pipe_bpp
!= base_bpp
;
12268 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12269 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
12276 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
12278 struct drm_encoder
*encoder
;
12279 struct drm_device
*dev
= crtc
->dev
;
12281 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
12282 if (encoder
->crtc
== crtc
)
12289 needs_modeset(struct drm_crtc_state
*state
)
12291 return state
->mode_changed
|| state
->active_changed
;
12295 intel_modeset_update_state(struct drm_atomic_state
*state
)
12297 struct drm_device
*dev
= state
->dev
;
12298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12299 struct intel_encoder
*intel_encoder
;
12300 struct drm_crtc
*crtc
;
12301 struct drm_crtc_state
*crtc_state
;
12302 struct drm_connector
*connector
;
12305 intel_shared_dpll_commit(dev_priv
);
12307 for_each_intel_encoder(dev
, intel_encoder
) {
12308 if (!intel_encoder
->base
.crtc
)
12311 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12312 if (crtc
!= intel_encoder
->base
.crtc
)
12315 if (crtc_state
->enable
&& needs_modeset(crtc_state
))
12316 intel_encoder
->connectors_active
= false;
12322 drm_atomic_helper_swap_state(state
->dev
, state
);
12323 intel_modeset_fixup_state(state
);
12325 /* Double check state. */
12326 for_each_crtc(dev
, crtc
) {
12327 WARN_ON(crtc
->state
->enable
!= intel_crtc_in_use(crtc
));
12330 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
12331 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
12334 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12335 if (crtc
!= connector
->encoder
->crtc
)
12338 if (crtc
->state
->enable
&& needs_modeset(crtc
->state
)) {
12339 struct drm_property
*dpms_property
=
12340 dev
->mode_config
.dpms_property
;
12342 connector
->dpms
= DRM_MODE_DPMS_ON
;
12343 drm_object_property_set_value(&connector
->base
,
12347 intel_encoder
= to_intel_encoder(connector
->encoder
);
12348 intel_encoder
->connectors_active
= true;
12357 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
12361 if (clock1
== clock2
)
12364 if (!clock1
|| !clock2
)
12367 diff
= abs(clock1
- clock2
);
12369 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
12375 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12376 list_for_each_entry((intel_crtc), \
12377 &(dev)->mode_config.crtc_list, \
12379 if (mask & (1 <<(intel_crtc)->pipe))
12382 intel_pipe_config_compare(struct drm_device
*dev
,
12383 struct intel_crtc_state
*current_config
,
12384 struct intel_crtc_state
*pipe_config
)
12386 #define PIPE_CONF_CHECK_X(name) \
12387 if (current_config->name != pipe_config->name) { \
12388 DRM_ERROR("mismatch in " #name " " \
12389 "(expected 0x%08x, found 0x%08x)\n", \
12390 current_config->name, \
12391 pipe_config->name); \
12395 #define PIPE_CONF_CHECK_I(name) \
12396 if (current_config->name != pipe_config->name) { \
12397 DRM_ERROR("mismatch in " #name " " \
12398 "(expected %i, found %i)\n", \
12399 current_config->name, \
12400 pipe_config->name); \
12404 /* This is required for BDW+ where there is only one set of registers for
12405 * switching between high and low RR.
12406 * This macro can be used whenever a comparison has to be made between one
12407 * hw state and multiple sw state variables.
12409 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12410 if ((current_config->name != pipe_config->name) && \
12411 (current_config->alt_name != pipe_config->name)) { \
12412 DRM_ERROR("mismatch in " #name " " \
12413 "(expected %i or %i, found %i)\n", \
12414 current_config->name, \
12415 current_config->alt_name, \
12416 pipe_config->name); \
12420 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12421 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12422 DRM_ERROR("mismatch in " #name "(" #mask ") " \
12423 "(expected %i, found %i)\n", \
12424 current_config->name & (mask), \
12425 pipe_config->name & (mask)); \
12429 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12430 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12431 DRM_ERROR("mismatch in " #name " " \
12432 "(expected %i, found %i)\n", \
12433 current_config->name, \
12434 pipe_config->name); \
12438 #define PIPE_CONF_QUIRK(quirk) \
12439 ((current_config->quirks | pipe_config->quirks) & (quirk))
12441 PIPE_CONF_CHECK_I(cpu_transcoder
);
12443 PIPE_CONF_CHECK_I(has_pch_encoder
);
12444 PIPE_CONF_CHECK_I(fdi_lanes
);
12445 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
12446 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
12447 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
12448 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
12449 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
12451 PIPE_CONF_CHECK_I(has_dp_encoder
);
12453 if (INTEL_INFO(dev
)->gen
< 8) {
12454 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
12455 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
12456 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
12457 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
12458 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
12460 if (current_config
->has_drrs
) {
12461 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
12462 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
12463 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
12464 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
12465 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
12468 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
12469 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
12470 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
12471 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
12472 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
12475 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12476 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12477 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12478 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12479 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12480 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12482 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12483 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12484 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12485 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12486 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12487 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12489 PIPE_CONF_CHECK_I(pixel_multiplier
);
12490 PIPE_CONF_CHECK_I(has_hdmi_sink
);
12491 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
12492 IS_VALLEYVIEW(dev
))
12493 PIPE_CONF_CHECK_I(limited_color_range
);
12494 PIPE_CONF_CHECK_I(has_infoframe
);
12496 PIPE_CONF_CHECK_I(has_audio
);
12498 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12499 DRM_MODE_FLAG_INTERLACE
);
12501 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12502 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12503 DRM_MODE_FLAG_PHSYNC
);
12504 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12505 DRM_MODE_FLAG_NHSYNC
);
12506 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12507 DRM_MODE_FLAG_PVSYNC
);
12508 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12509 DRM_MODE_FLAG_NVSYNC
);
12512 PIPE_CONF_CHECK_I(pipe_src_w
);
12513 PIPE_CONF_CHECK_I(pipe_src_h
);
12516 * FIXME: BIOS likes to set up a cloned config with lvds+external
12517 * screen. Since we don't yet re-compute the pipe config when moving
12518 * just the lvds port away to another pipe the sw tracking won't match.
12520 * Proper atomic modesets with recomputed global state will fix this.
12521 * Until then just don't check gmch state for inherited modes.
12523 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
12524 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
12525 /* pfit ratios are autocomputed by the hw on gen4+ */
12526 if (INTEL_INFO(dev
)->gen
< 4)
12527 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
12528 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
12531 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
12532 if (current_config
->pch_pfit
.enabled
) {
12533 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
12534 PIPE_CONF_CHECK_I(pch_pfit
.size
);
12537 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12539 /* BDW+ don't expose a synchronous way to read the state */
12540 if (IS_HASWELL(dev
))
12541 PIPE_CONF_CHECK_I(ips_enabled
);
12543 PIPE_CONF_CHECK_I(double_wide
);
12545 PIPE_CONF_CHECK_X(ddi_pll_sel
);
12547 PIPE_CONF_CHECK_I(shared_dpll
);
12548 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12549 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12550 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12551 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12552 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12553 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12554 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12555 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12557 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
12558 PIPE_CONF_CHECK_I(pipe_bpp
);
12560 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12561 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12563 #undef PIPE_CONF_CHECK_X
12564 #undef PIPE_CONF_CHECK_I
12565 #undef PIPE_CONF_CHECK_I_ALT
12566 #undef PIPE_CONF_CHECK_FLAGS
12567 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12568 #undef PIPE_CONF_QUIRK
12573 static void check_wm_state(struct drm_device
*dev
)
12575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12576 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
12577 struct intel_crtc
*intel_crtc
;
12580 if (INTEL_INFO(dev
)->gen
< 9)
12583 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
12584 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12586 for_each_intel_crtc(dev
, intel_crtc
) {
12587 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
12588 const enum pipe pipe
= intel_crtc
->pipe
;
12590 if (!intel_crtc
->active
)
12594 for_each_plane(dev_priv
, pipe
, plane
) {
12595 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
12596 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
12598 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12601 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12602 "(expected (%u,%u), found (%u,%u))\n",
12603 pipe_name(pipe
), plane
+ 1,
12604 sw_entry
->start
, sw_entry
->end
,
12605 hw_entry
->start
, hw_entry
->end
);
12609 hw_entry
= &hw_ddb
.cursor
[pipe
];
12610 sw_entry
= &sw_ddb
->cursor
[pipe
];
12612 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12615 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12616 "(expected (%u,%u), found (%u,%u))\n",
12618 sw_entry
->start
, sw_entry
->end
,
12619 hw_entry
->start
, hw_entry
->end
);
12624 check_connector_state(struct drm_device
*dev
)
12626 struct intel_connector
*connector
;
12628 for_each_intel_connector(dev
, connector
) {
12629 /* This also checks the encoder/connector hw state with the
12630 * ->get_hw_state callbacks. */
12631 intel_connector_check_state(connector
);
12633 I915_STATE_WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
12634 "connector's staged encoder doesn't match current encoder\n");
12639 check_encoder_state(struct drm_device
*dev
)
12641 struct intel_encoder
*encoder
;
12642 struct intel_connector
*connector
;
12644 for_each_intel_encoder(dev
, encoder
) {
12645 bool enabled
= false;
12646 bool active
= false;
12647 enum pipe pipe
, tracked_pipe
;
12649 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12650 encoder
->base
.base
.id
,
12651 encoder
->base
.name
);
12653 I915_STATE_WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
12654 "encoder's stage crtc doesn't match current crtc\n");
12655 I915_STATE_WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
12656 "encoder's active_connectors set, but no crtc\n");
12658 for_each_intel_connector(dev
, connector
) {
12659 if (connector
->base
.encoder
!= &encoder
->base
)
12662 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
12666 * for MST connectors if we unplug the connector is gone
12667 * away but the encoder is still connected to a crtc
12668 * until a modeset happens in response to the hotplug.
12670 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
12673 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12674 "encoder's enabled state mismatch "
12675 "(expected %i, found %i)\n",
12676 !!encoder
->base
.crtc
, enabled
);
12677 I915_STATE_WARN(active
&& !encoder
->base
.crtc
,
12678 "active encoder with no crtc\n");
12680 I915_STATE_WARN(encoder
->connectors_active
!= active
,
12681 "encoder's computed active state doesn't match tracked active state "
12682 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
12684 active
= encoder
->get_hw_state(encoder
, &pipe
);
12685 I915_STATE_WARN(active
!= encoder
->connectors_active
,
12686 "encoder's hw state doesn't match sw tracking "
12687 "(expected %i, found %i)\n",
12688 encoder
->connectors_active
, active
);
12690 if (!encoder
->base
.crtc
)
12693 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
12694 I915_STATE_WARN(active
&& pipe
!= tracked_pipe
,
12695 "active encoder's pipe doesn't match"
12696 "(expected %i, found %i)\n",
12697 tracked_pipe
, pipe
);
12703 check_crtc_state(struct drm_device
*dev
)
12705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12706 struct intel_crtc
*crtc
;
12707 struct intel_encoder
*encoder
;
12708 struct intel_crtc_state pipe_config
;
12710 for_each_intel_crtc(dev
, crtc
) {
12711 bool enabled
= false;
12712 bool active
= false;
12714 memset(&pipe_config
, 0, sizeof(pipe_config
));
12716 DRM_DEBUG_KMS("[CRTC:%d]\n",
12717 crtc
->base
.base
.id
);
12719 I915_STATE_WARN(crtc
->active
&& !crtc
->base
.state
->enable
,
12720 "active crtc, but not enabled in sw tracking\n");
12722 for_each_intel_encoder(dev
, encoder
) {
12723 if (encoder
->base
.crtc
!= &crtc
->base
)
12726 if (encoder
->connectors_active
)
12730 I915_STATE_WARN(active
!= crtc
->active
,
12731 "crtc's computed active state doesn't match tracked active state "
12732 "(expected %i, found %i)\n", active
, crtc
->active
);
12733 I915_STATE_WARN(enabled
!= crtc
->base
.state
->enable
,
12734 "crtc's computed enabled state doesn't match tracked enabled state "
12735 "(expected %i, found %i)\n", enabled
,
12736 crtc
->base
.state
->enable
);
12738 active
= dev_priv
->display
.get_pipe_config(crtc
,
12741 /* hw state is inconsistent with the pipe quirk */
12742 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
12743 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
12744 active
= crtc
->active
;
12746 for_each_intel_encoder(dev
, encoder
) {
12748 if (encoder
->base
.crtc
!= &crtc
->base
)
12750 if (encoder
->get_hw_state(encoder
, &pipe
))
12751 encoder
->get_config(encoder
, &pipe_config
);
12754 I915_STATE_WARN(crtc
->active
!= active
,
12755 "crtc active state doesn't match with hw state "
12756 "(expected %i, found %i)\n", crtc
->active
, active
);
12759 !intel_pipe_config_compare(dev
, crtc
->config
, &pipe_config
)) {
12760 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12761 intel_dump_pipe_config(crtc
, &pipe_config
,
12763 intel_dump_pipe_config(crtc
, crtc
->config
,
12770 check_shared_dpll_state(struct drm_device
*dev
)
12772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12773 struct intel_crtc
*crtc
;
12774 struct intel_dpll_hw_state dpll_hw_state
;
12777 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12778 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12779 int enabled_crtcs
= 0, active_crtcs
= 0;
12782 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12784 DRM_DEBUG_KMS("%s\n", pll
->name
);
12786 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12788 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
12789 "more active pll users than references: %i vs %i\n",
12790 pll
->active
, hweight32(pll
->config
.crtc_mask
));
12791 I915_STATE_WARN(pll
->active
&& !pll
->on
,
12792 "pll in active use but not on in sw tracking\n");
12793 I915_STATE_WARN(pll
->on
&& !pll
->active
,
12794 "pll in on but not on in use in sw tracking\n");
12795 I915_STATE_WARN(pll
->on
!= active
,
12796 "pll on state mismatch (expected %i, found %i)\n",
12799 for_each_intel_crtc(dev
, crtc
) {
12800 if (crtc
->base
.state
->enable
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12802 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12805 I915_STATE_WARN(pll
->active
!= active_crtcs
,
12806 "pll active crtcs mismatch (expected %i, found %i)\n",
12807 pll
->active
, active_crtcs
);
12808 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
12809 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12810 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
12812 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
12813 sizeof(dpll_hw_state
)),
12814 "pll hw state mismatch\n");
12819 intel_modeset_check_state(struct drm_device
*dev
)
12821 check_wm_state(dev
);
12822 check_connector_state(dev
);
12823 check_encoder_state(dev
);
12824 check_crtc_state(dev
);
12825 check_shared_dpll_state(dev
);
12828 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
12832 * FDI already provided one idea for the dotclock.
12833 * Yell if the encoder disagrees.
12835 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
12836 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12837 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
12840 static void update_scanline_offset(struct intel_crtc
*crtc
)
12842 struct drm_device
*dev
= crtc
->base
.dev
;
12845 * The scanline counter increments at the leading edge of hsync.
12847 * On most platforms it starts counting from vtotal-1 on the
12848 * first active line. That means the scanline counter value is
12849 * always one less than what we would expect. Ie. just after
12850 * start of vblank, which also occurs at start of hsync (on the
12851 * last active line), the scanline counter will read vblank_start-1.
12853 * On gen2 the scanline counter starts counting from 1 instead
12854 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12855 * to keep the value positive), instead of adding one.
12857 * On HSW+ the behaviour of the scanline counter depends on the output
12858 * type. For DP ports it behaves like most other platforms, but on HDMI
12859 * there's an extra 1 line difference. So we need to add two instead of
12860 * one to the value.
12862 if (IS_GEN2(dev
)) {
12863 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
12866 vtotal
= mode
->crtc_vtotal
;
12867 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
12870 crtc
->scanline_offset
= vtotal
- 1;
12871 } else if (HAS_DDI(dev
) &&
12872 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
12873 crtc
->scanline_offset
= 2;
12875 crtc
->scanline_offset
= 1;
12878 static struct intel_crtc_state
*
12879 intel_modeset_compute_config(struct drm_crtc
*crtc
,
12880 struct drm_atomic_state
*state
)
12882 struct intel_crtc_state
*pipe_config
;
12885 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12887 return ERR_PTR(ret
);
12889 ret
= drm_atomic_helper_check_modeset(state
->dev
, state
);
12891 return ERR_PTR(ret
);
12894 * Note this needs changes when we start tracking multiple modes
12895 * and crtcs. At that point we'll need to compute the whole config
12896 * (i.e. one pipe_config for each crtc) rather than just the one
12899 pipe_config
= intel_atomic_get_crtc_state(state
, to_intel_crtc(crtc
));
12900 if (IS_ERR(pipe_config
))
12901 return pipe_config
;
12903 if (!pipe_config
->base
.enable
)
12904 return pipe_config
;
12906 ret
= intel_modeset_pipe_config(crtc
, state
, pipe_config
);
12908 return ERR_PTR(ret
);
12910 /* Check things that can only be changed through modeset */
12911 if (pipe_config
->has_audio
!=
12912 to_intel_crtc(crtc
)->config
->has_audio
)
12913 pipe_config
->base
.mode_changed
= true;
12916 * Note we have an issue here with infoframes: current code
12917 * only updates them on the full mode set path per hw
12918 * requirements. So here we should be checking for any
12919 * required changes and forcing a mode set.
12922 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,"[modeset]");
12924 ret
= drm_atomic_helper_check_planes(state
->dev
, state
);
12926 return ERR_PTR(ret
);
12928 return pipe_config
;
12931 static int __intel_set_mode_setup_plls(struct drm_atomic_state
*state
)
12933 struct drm_device
*dev
= state
->dev
;
12934 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12935 unsigned clear_pipes
= 0;
12936 struct intel_crtc
*intel_crtc
;
12937 struct intel_crtc_state
*intel_crtc_state
;
12938 struct drm_crtc
*crtc
;
12939 struct drm_crtc_state
*crtc_state
;
12943 if (!dev_priv
->display
.crtc_compute_clock
)
12946 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12947 intel_crtc
= to_intel_crtc(crtc
);
12948 intel_crtc_state
= to_intel_crtc_state(crtc_state
);
12950 if (needs_modeset(crtc_state
)) {
12951 clear_pipes
|= 1 << intel_crtc
->pipe
;
12952 intel_crtc_state
->shared_dpll
= DPLL_ID_PRIVATE
;
12956 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
12960 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12961 if (!needs_modeset(crtc_state
) || !crtc_state
->enable
)
12964 intel_crtc
= to_intel_crtc(crtc
);
12965 intel_crtc_state
= to_intel_crtc_state(crtc_state
);
12967 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
12970 intel_shared_dpll_abort_config(dev_priv
);
12979 /* Code that should eventually be part of atomic_check() */
12980 static int __intel_set_mode_checks(struct drm_atomic_state
*state
)
12982 struct drm_device
*dev
= state
->dev
;
12986 * See if the config requires any additional preparation, e.g.
12987 * to adjust global state with pipes off. We need to do this
12988 * here so we can get the modeset_pipe updated config for the new
12989 * mode set on this crtc. For other crtcs we need to use the
12990 * adjusted_mode bits in the crtc directly.
12992 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
) || IS_BROADWELL(dev
)) {
12993 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
))
12994 ret
= valleyview_modeset_global_pipes(state
);
12996 ret
= broadwell_modeset_global_pipes(state
);
13002 ret
= __intel_set_mode_setup_plls(state
);
13009 static int __intel_set_mode(struct drm_crtc
*modeset_crtc
,
13010 struct intel_crtc_state
*pipe_config
)
13012 struct drm_device
*dev
= modeset_crtc
->dev
;
13013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13014 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
13015 struct drm_crtc
*crtc
;
13016 struct drm_crtc_state
*crtc_state
;
13020 ret
= __intel_set_mode_checks(state
);
13024 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
13028 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13029 if (!needs_modeset(crtc_state
))
13032 if (!crtc_state
->enable
) {
13033 intel_crtc_disable(crtc
);
13034 } else if (crtc
->state
->enable
) {
13035 intel_crtc_disable_planes(crtc
);
13036 dev_priv
->display
.crtc_disable(crtc
);
13040 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
13041 * to set it here already despite that we pass it down the callchain.
13043 * Note we'll need to fix this up when we start tracking multiple
13044 * pipes; here we assume a single modeset_pipe and only track the
13045 * single crtc and mode.
13047 if (pipe_config
->base
.enable
&& needs_modeset(&pipe_config
->base
)) {
13048 modeset_crtc
->mode
= pipe_config
->base
.mode
;
13051 * Calculate and store various constants which
13052 * are later needed by vblank and swap-completion
13053 * timestamping. They are derived from true hwmode.
13055 drm_calc_timestamping_constants(modeset_crtc
,
13056 &pipe_config
->base
.adjusted_mode
);
13059 /* Only after disabling all output pipelines that will be changed can we
13060 * update the the output configuration. */
13061 intel_modeset_update_state(state
);
13063 /* The state has been swaped above, so state actually contains the
13064 * old state now. */
13066 modeset_update_crtc_power_domains(state
);
13068 drm_atomic_helper_commit_planes(dev
, state
);
13070 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13071 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13072 if (!needs_modeset(crtc
->state
) || !crtc
->state
->enable
)
13075 update_scanline_offset(to_intel_crtc(crtc
));
13077 dev_priv
->display
.crtc_enable(crtc
);
13078 intel_crtc_enable_planes(crtc
);
13081 /* FIXME: add subpixel order */
13083 drm_atomic_helper_cleanup_planes(dev
, state
);
13085 drm_atomic_state_free(state
);
13090 static int intel_set_mode_with_config(struct drm_crtc
*crtc
,
13091 struct intel_crtc_state
*pipe_config
)
13095 ret
= __intel_set_mode(crtc
, pipe_config
);
13098 intel_modeset_check_state(crtc
->dev
);
13103 static int intel_set_mode(struct drm_crtc
*crtc
,
13104 struct drm_atomic_state
*state
)
13106 struct intel_crtc_state
*pipe_config
;
13109 pipe_config
= intel_modeset_compute_config(crtc
, state
);
13110 if (IS_ERR(pipe_config
)) {
13111 ret
= PTR_ERR(pipe_config
);
13115 ret
= intel_set_mode_with_config(crtc
, pipe_config
);
13123 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
13125 struct drm_device
*dev
= crtc
->dev
;
13126 struct drm_atomic_state
*state
;
13127 struct intel_crtc
*intel_crtc
;
13128 struct intel_encoder
*encoder
;
13129 struct intel_connector
*connector
;
13130 struct drm_connector_state
*connector_state
;
13131 struct intel_crtc_state
*crtc_state
;
13134 state
= drm_atomic_state_alloc(dev
);
13136 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13141 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
13143 /* The force restore path in the HW readout code relies on the staged
13144 * config still keeping the user requested config while the actual
13145 * state has been overwritten by the configuration read from HW. We
13146 * need to copy the staged config to the atomic state, otherwise the
13147 * mode set will just reapply the state the HW is already in. */
13148 for_each_intel_encoder(dev
, encoder
) {
13149 if (&encoder
->new_crtc
->base
!= crtc
)
13152 for_each_intel_connector(dev
, connector
) {
13153 if (connector
->new_encoder
!= encoder
)
13156 connector_state
= drm_atomic_get_connector_state(state
, &connector
->base
);
13157 if (IS_ERR(connector_state
)) {
13158 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13159 connector
->base
.base
.id
,
13160 connector
->base
.name
,
13161 PTR_ERR(connector_state
));
13165 connector_state
->crtc
= crtc
;
13166 connector_state
->best_encoder
= &encoder
->base
;
13170 for_each_intel_crtc(dev
, intel_crtc
) {
13171 if (intel_crtc
->new_enabled
== intel_crtc
->base
.enabled
)
13174 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
13175 if (IS_ERR(crtc_state
)) {
13176 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13177 intel_crtc
->base
.base
.id
,
13178 PTR_ERR(crtc_state
));
13182 crtc_state
->base
.active
= crtc_state
->base
.enable
=
13183 intel_crtc
->new_enabled
;
13185 if (&intel_crtc
->base
== crtc
)
13186 drm_mode_copy(&crtc_state
->base
.mode
, &crtc
->mode
);
13189 intel_modeset_setup_plane_state(state
, crtc
, &crtc
->mode
,
13190 crtc
->primary
->fb
, crtc
->x
, crtc
->y
);
13192 ret
= intel_set_mode(crtc
, state
);
13194 drm_atomic_state_free(state
);
13197 #undef for_each_intel_crtc_masked
13199 static bool intel_connector_in_mode_set(struct intel_connector
*connector
,
13200 struct drm_mode_set
*set
)
13204 for (ro
= 0; ro
< set
->num_connectors
; ro
++)
13205 if (set
->connectors
[ro
] == &connector
->base
)
13212 intel_modeset_stage_output_state(struct drm_device
*dev
,
13213 struct drm_mode_set
*set
,
13214 struct drm_atomic_state
*state
)
13216 struct intel_connector
*connector
;
13217 struct drm_connector
*drm_connector
;
13218 struct drm_connector_state
*connector_state
;
13219 struct drm_crtc
*crtc
;
13220 struct drm_crtc_state
*crtc_state
;
13223 /* The upper layers ensure that we either disable a crtc or have a list
13224 * of connectors. For paranoia, double-check this. */
13225 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
13226 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
13228 for_each_intel_connector(dev
, connector
) {
13229 bool in_mode_set
= intel_connector_in_mode_set(connector
, set
);
13231 if (!in_mode_set
&& connector
->base
.state
->crtc
!= set
->crtc
)
13235 drm_atomic_get_connector_state(state
, &connector
->base
);
13236 if (IS_ERR(connector_state
))
13237 return PTR_ERR(connector_state
);
13240 int pipe
= to_intel_crtc(set
->crtc
)->pipe
;
13241 connector_state
->best_encoder
=
13242 &intel_find_encoder(connector
, pipe
)->base
;
13245 if (connector
->base
.state
->crtc
!= set
->crtc
)
13248 /* If we disable the crtc, disable all its connectors. Also, if
13249 * the connector is on the changing crtc but not on the new
13250 * connector list, disable it. */
13251 if (!set
->fb
|| !in_mode_set
) {
13252 connector_state
->best_encoder
= NULL
;
13254 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13255 connector
->base
.base
.id
,
13256 connector
->base
.name
);
13259 /* connector->new_encoder is now updated for all connectors. */
13261 for_each_connector_in_state(state
, drm_connector
, connector_state
, i
) {
13262 connector
= to_intel_connector(drm_connector
);
13264 if (!connector_state
->best_encoder
) {
13265 ret
= drm_atomic_set_crtc_for_connector(connector_state
,
13273 if (intel_connector_in_mode_set(connector
, set
)) {
13274 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
13276 /* If this connector was in a previous crtc, add it
13277 * to the state. We might need to disable it. */
13280 drm_atomic_get_crtc_state(state
, crtc
);
13281 if (IS_ERR(crtc_state
))
13282 return PTR_ERR(crtc_state
);
13285 ret
= drm_atomic_set_crtc_for_connector(connector_state
,
13291 /* Make sure the new CRTC will work with the encoder */
13292 if (!drm_encoder_crtc_ok(connector_state
->best_encoder
,
13293 connector_state
->crtc
)) {
13297 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13298 connector
->base
.base
.id
,
13299 connector
->base
.name
,
13300 connector_state
->crtc
->base
.id
);
13302 if (connector_state
->best_encoder
!= &connector
->encoder
->base
)
13303 connector
->encoder
=
13304 to_intel_encoder(connector_state
->best_encoder
);
13307 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13308 bool has_connectors
;
13310 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13314 has_connectors
= !!drm_atomic_connectors_for_crtc(state
, crtc
);
13315 if (has_connectors
!= crtc_state
->enable
)
13316 crtc_state
->enable
=
13317 crtc_state
->active
= has_connectors
;
13320 ret
= intel_modeset_setup_plane_state(state
, set
->crtc
, set
->mode
,
13321 set
->fb
, set
->x
, set
->y
);
13325 crtc_state
= drm_atomic_get_crtc_state(state
, set
->crtc
);
13326 if (IS_ERR(crtc_state
))
13327 return PTR_ERR(crtc_state
);
13330 drm_mode_copy(&crtc_state
->mode
, set
->mode
);
13332 if (set
->num_connectors
)
13333 crtc_state
->active
= true;
13338 static bool primary_plane_visible(struct drm_crtc
*crtc
)
13340 struct intel_plane_state
*plane_state
=
13341 to_intel_plane_state(crtc
->primary
->state
);
13343 return plane_state
->visible
;
13346 static int intel_crtc_set_config(struct drm_mode_set
*set
)
13348 struct drm_device
*dev
;
13349 struct drm_atomic_state
*state
= NULL
;
13350 struct intel_crtc_state
*pipe_config
;
13351 bool primary_plane_was_visible
;
13355 BUG_ON(!set
->crtc
);
13356 BUG_ON(!set
->crtc
->helper_private
);
13358 /* Enforce sane interface api - has been abused by the fb helper. */
13359 BUG_ON(!set
->mode
&& set
->fb
);
13360 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
13363 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13364 set
->crtc
->base
.id
, set
->fb
->base
.id
,
13365 (int)set
->num_connectors
, set
->x
, set
->y
);
13367 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
13370 dev
= set
->crtc
->dev
;
13372 state
= drm_atomic_state_alloc(dev
);
13376 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
13378 ret
= intel_modeset_stage_output_state(dev
, set
, state
);
13382 pipe_config
= intel_modeset_compute_config(set
->crtc
, state
);
13383 if (IS_ERR(pipe_config
)) {
13384 ret
= PTR_ERR(pipe_config
);
13388 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
13390 primary_plane_was_visible
= primary_plane_visible(set
->crtc
);
13392 ret
= intel_set_mode_with_config(set
->crtc
, pipe_config
);
13395 pipe_config
->base
.enable
&&
13396 pipe_config
->base
.planes_changed
&&
13397 !needs_modeset(&pipe_config
->base
)) {
13398 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
13401 * We need to make sure the primary plane is re-enabled if it
13402 * has previously been turned off.
13404 if (ret
== 0 && !primary_plane_was_visible
&&
13405 primary_plane_visible(set
->crtc
)) {
13406 WARN_ON(!intel_crtc
->active
);
13407 intel_post_enable_primary(set
->crtc
);
13411 * In the fastboot case this may be our only check of the
13412 * state after boot. It would be better to only do it on
13413 * the first update, but we don't have a nice way of doing that
13414 * (and really, set_config isn't used much for high freq page
13415 * flipping, so increasing its cost here shouldn't be a big
13418 if (i915
.fastboot
&& ret
== 0)
13419 intel_modeset_check_state(set
->crtc
->dev
);
13423 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13424 set
->crtc
->base
.id
, ret
);
13429 drm_atomic_state_free(state
);
13433 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13434 .gamma_set
= intel_crtc_gamma_set
,
13435 .set_config
= intel_crtc_set_config
,
13436 .destroy
= intel_crtc_destroy
,
13437 .page_flip
= intel_crtc_page_flip
,
13438 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13439 .atomic_destroy_state
= intel_crtc_destroy_state
,
13442 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
13443 struct intel_shared_dpll
*pll
,
13444 struct intel_dpll_hw_state
*hw_state
)
13448 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
13451 val
= I915_READ(PCH_DPLL(pll
->id
));
13452 hw_state
->dpll
= val
;
13453 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
13454 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
13456 return val
& DPLL_VCO_ENABLE
;
13459 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
13460 struct intel_shared_dpll
*pll
)
13462 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
13463 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
13466 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
13467 struct intel_shared_dpll
*pll
)
13469 /* PCH refclock must be enabled first */
13470 ibx_assert_pch_refclk_enabled(dev_priv
);
13472 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13474 /* Wait for the clocks to stabilize. */
13475 POSTING_READ(PCH_DPLL(pll
->id
));
13478 /* The pixel multiplier can only be updated once the
13479 * DPLL is enabled and the clocks are stable.
13481 * So write it again.
13483 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13484 POSTING_READ(PCH_DPLL(pll
->id
));
13488 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
13489 struct intel_shared_dpll
*pll
)
13491 struct drm_device
*dev
= dev_priv
->dev
;
13492 struct intel_crtc
*crtc
;
13494 /* Make sure no transcoder isn't still depending on us. */
13495 for_each_intel_crtc(dev
, crtc
) {
13496 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
13497 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
13500 I915_WRITE(PCH_DPLL(pll
->id
), 0);
13501 POSTING_READ(PCH_DPLL(pll
->id
));
13505 static char *ibx_pch_dpll_names
[] = {
13510 static void ibx_pch_dpll_init(struct drm_device
*dev
)
13512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13515 dev_priv
->num_shared_dpll
= 2;
13517 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13518 dev_priv
->shared_dplls
[i
].id
= i
;
13519 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
13520 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
13521 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
13522 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
13523 dev_priv
->shared_dplls
[i
].get_hw_state
=
13524 ibx_pch_dpll_get_hw_state
;
13528 static void intel_shared_dpll_init(struct drm_device
*dev
)
13530 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13532 intel_update_cdclk(dev
);
13535 intel_ddi_pll_init(dev
);
13536 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
13537 ibx_pch_dpll_init(dev
);
13539 dev_priv
->num_shared_dpll
= 0;
13541 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
13545 * intel_wm_need_update - Check whether watermarks need updating
13546 * @plane: drm plane
13547 * @state: new plane state
13549 * Check current plane state versus the new one to determine whether
13550 * watermarks need to be recalculated.
13552 * Returns true or false.
13554 bool intel_wm_need_update(struct drm_plane
*plane
,
13555 struct drm_plane_state
*state
)
13557 /* Update watermarks on tiling changes. */
13558 if (!plane
->state
->fb
|| !state
->fb
||
13559 plane
->state
->fb
->modifier
[0] != state
->fb
->modifier
[0] ||
13560 plane
->state
->rotation
!= state
->rotation
)
13567 * intel_prepare_plane_fb - Prepare fb for usage on plane
13568 * @plane: drm plane to prepare for
13569 * @fb: framebuffer to prepare for presentation
13571 * Prepares a framebuffer for usage on a display plane. Generally this
13572 * involves pinning the underlying object and updating the frontbuffer tracking
13573 * bits. Some older platforms need special physical address handling for
13576 * Returns 0 on success, negative error code on failure.
13579 intel_prepare_plane_fb(struct drm_plane
*plane
,
13580 struct drm_framebuffer
*fb
,
13581 const struct drm_plane_state
*new_state
)
13583 struct drm_device
*dev
= plane
->dev
;
13584 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13585 enum pipe pipe
= intel_plane
->pipe
;
13586 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13587 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
13588 unsigned frontbuffer_bits
= 0;
13594 switch (plane
->type
) {
13595 case DRM_PLANE_TYPE_PRIMARY
:
13596 frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
13598 case DRM_PLANE_TYPE_CURSOR
:
13599 frontbuffer_bits
= INTEL_FRONTBUFFER_CURSOR(pipe
);
13601 case DRM_PLANE_TYPE_OVERLAY
:
13602 frontbuffer_bits
= INTEL_FRONTBUFFER_SPRITE(pipe
);
13606 mutex_lock(&dev
->struct_mutex
);
13608 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
13609 INTEL_INFO(dev
)->cursor_needs_physical
) {
13610 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
13611 ret
= i915_gem_object_attach_phys(obj
, align
);
13613 DRM_DEBUG_KMS("failed to attach phys object\n");
13615 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, new_state
, NULL
);
13619 i915_gem_track_fb(old_obj
, obj
, frontbuffer_bits
);
13621 mutex_unlock(&dev
->struct_mutex
);
13627 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13628 * @plane: drm plane to clean up for
13629 * @fb: old framebuffer that was on plane
13631 * Cleans up a framebuffer that has just been removed from a plane.
13634 intel_cleanup_plane_fb(struct drm_plane
*plane
,
13635 struct drm_framebuffer
*fb
,
13636 const struct drm_plane_state
*old_state
)
13638 struct drm_device
*dev
= plane
->dev
;
13639 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13644 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
13645 !INTEL_INFO(dev
)->cursor_needs_physical
) {
13646 mutex_lock(&dev
->struct_mutex
);
13647 intel_unpin_fb_obj(fb
, old_state
);
13648 mutex_unlock(&dev
->struct_mutex
);
13653 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
13656 struct drm_device
*dev
;
13657 struct drm_i915_private
*dev_priv
;
13658 int crtc_clock
, cdclk
;
13660 if (!intel_crtc
|| !crtc_state
)
13661 return DRM_PLANE_HELPER_NO_SCALING
;
13663 dev
= intel_crtc
->base
.dev
;
13664 dev_priv
= dev
->dev_private
;
13665 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
13666 cdclk
= dev_priv
->display
.get_display_clock_speed(dev
);
13668 if (!crtc_clock
|| !cdclk
)
13669 return DRM_PLANE_HELPER_NO_SCALING
;
13672 * skl max scale is lower of:
13673 * close to 3 but not 3, -1 is for that purpose
13677 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
13683 intel_check_primary_plane(struct drm_plane
*plane
,
13684 struct intel_plane_state
*state
)
13686 struct drm_device
*dev
= plane
->dev
;
13687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13688 struct drm_crtc
*crtc
= state
->base
.crtc
;
13689 struct intel_crtc
*intel_crtc
;
13690 struct intel_crtc_state
*crtc_state
;
13691 struct drm_framebuffer
*fb
= state
->base
.fb
;
13692 struct drm_rect
*dest
= &state
->dst
;
13693 struct drm_rect
*src
= &state
->src
;
13694 const struct drm_rect
*clip
= &state
->clip
;
13695 bool can_position
= false;
13696 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13697 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13700 crtc
= crtc
? crtc
: plane
->crtc
;
13701 intel_crtc
= to_intel_crtc(crtc
);
13702 crtc_state
= state
->base
.state
?
13703 intel_atomic_get_crtc_state(state
->base
.state
, intel_crtc
) : NULL
;
13705 if (INTEL_INFO(dev
)->gen
>= 9) {
13706 /* use scaler when colorkey is not required */
13707 if (to_intel_plane(plane
)->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
13709 max_scale
= skl_max_scale(intel_crtc
, crtc_state
);
13711 can_position
= true;
13714 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
13718 can_position
, true,
13723 if (intel_crtc
->active
) {
13724 struct intel_plane_state
*old_state
=
13725 to_intel_plane_state(plane
->state
);
13727 intel_crtc
->atomic
.wait_for_flips
= true;
13730 * FBC does not work on some platforms for rotated
13731 * planes, so disable it when rotation is not 0 and
13732 * update it when rotation is set back to 0.
13734 * FIXME: This is redundant with the fbc update done in
13735 * the primary plane enable function except that that
13736 * one is done too late. We eventually need to unify
13739 if (state
->visible
&&
13740 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
13741 dev_priv
->fbc
.crtc
== intel_crtc
&&
13742 state
->base
.rotation
!= BIT(DRM_ROTATE_0
)) {
13743 intel_crtc
->atomic
.disable_fbc
= true;
13746 if (state
->visible
&& !old_state
->visible
) {
13748 * BDW signals flip done immediately if the plane
13749 * is disabled, even if the plane enable is already
13750 * armed to occur at the next vblank :(
13752 if (IS_BROADWELL(dev
))
13753 intel_crtc
->atomic
.wait_vblank
= true;
13756 intel_crtc
->atomic
.fb_bits
|=
13757 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
13759 intel_crtc
->atomic
.update_fbc
= true;
13761 if (intel_wm_need_update(plane
, &state
->base
))
13762 intel_crtc
->atomic
.update_wm
= true;
13765 if (INTEL_INFO(dev
)->gen
>= 9) {
13766 ret
= skl_update_scaler_users(intel_crtc
, crtc_state
,
13767 to_intel_plane(plane
), state
, 0);
13776 intel_commit_primary_plane(struct drm_plane
*plane
,
13777 struct intel_plane_state
*state
)
13779 struct drm_crtc
*crtc
= state
->base
.crtc
;
13780 struct drm_framebuffer
*fb
= state
->base
.fb
;
13781 struct drm_device
*dev
= plane
->dev
;
13782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13783 struct intel_crtc
*intel_crtc
;
13784 struct drm_rect
*src
= &state
->src
;
13786 crtc
= crtc
? crtc
: plane
->crtc
;
13787 intel_crtc
= to_intel_crtc(crtc
);
13790 crtc
->x
= src
->x1
>> 16;
13791 crtc
->y
= src
->y1
>> 16;
13793 if (intel_crtc
->active
) {
13794 if (state
->visible
)
13795 /* FIXME: kill this fastboot hack */
13796 intel_update_pipe_size(intel_crtc
);
13798 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
13804 intel_disable_primary_plane(struct drm_plane
*plane
,
13805 struct drm_crtc
*crtc
,
13808 struct drm_device
*dev
= plane
->dev
;
13809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13811 dev_priv
->display
.update_primary_plane(crtc
, NULL
, 0, 0);
13814 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
)
13816 struct drm_device
*dev
= crtc
->dev
;
13817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13818 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13819 struct intel_plane
*intel_plane
;
13820 struct drm_plane
*p
;
13821 unsigned fb_bits
= 0;
13823 /* Track fb's for any planes being disabled */
13824 list_for_each_entry(p
, &dev
->mode_config
.plane_list
, head
) {
13825 intel_plane
= to_intel_plane(p
);
13827 if (intel_crtc
->atomic
.disabled_planes
&
13828 (1 << drm_plane_index(p
))) {
13830 case DRM_PLANE_TYPE_PRIMARY
:
13831 fb_bits
= INTEL_FRONTBUFFER_PRIMARY(intel_plane
->pipe
);
13833 case DRM_PLANE_TYPE_CURSOR
:
13834 fb_bits
= INTEL_FRONTBUFFER_CURSOR(intel_plane
->pipe
);
13836 case DRM_PLANE_TYPE_OVERLAY
:
13837 fb_bits
= INTEL_FRONTBUFFER_SPRITE(intel_plane
->pipe
);
13841 mutex_lock(&dev
->struct_mutex
);
13842 i915_gem_track_fb(intel_fb_obj(p
->fb
), NULL
, fb_bits
);
13843 mutex_unlock(&dev
->struct_mutex
);
13847 if (intel_crtc
->atomic
.wait_for_flips
)
13848 intel_crtc_wait_for_pending_flips(crtc
);
13850 if (intel_crtc
->atomic
.disable_fbc
)
13851 intel_fbc_disable(dev
);
13853 if (intel_crtc
->atomic
.pre_disable_primary
)
13854 intel_pre_disable_primary(crtc
);
13856 if (intel_crtc
->atomic
.update_wm
)
13857 intel_update_watermarks(crtc
);
13859 intel_runtime_pm_get(dev_priv
);
13861 /* Perform vblank evasion around commit operation */
13862 if (intel_crtc
->active
)
13863 intel_crtc
->atomic
.evade
=
13864 intel_pipe_update_start(intel_crtc
,
13865 &intel_crtc
->atomic
.start_vbl_count
);
13868 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
)
13870 struct drm_device
*dev
= crtc
->dev
;
13871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13872 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13873 struct drm_plane
*p
;
13875 if (intel_crtc
->atomic
.evade
)
13876 intel_pipe_update_end(intel_crtc
,
13877 intel_crtc
->atomic
.start_vbl_count
);
13879 intel_runtime_pm_put(dev_priv
);
13881 if (intel_crtc
->atomic
.wait_vblank
)
13882 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
13884 intel_frontbuffer_flip(dev
, intel_crtc
->atomic
.fb_bits
);
13886 if (intel_crtc
->atomic
.update_fbc
) {
13887 mutex_lock(&dev
->struct_mutex
);
13888 intel_fbc_update(dev
);
13889 mutex_unlock(&dev
->struct_mutex
);
13892 if (intel_crtc
->atomic
.post_enable_primary
)
13893 intel_post_enable_primary(crtc
);
13895 drm_for_each_legacy_plane(p
, &dev
->mode_config
.plane_list
)
13896 if (intel_crtc
->atomic
.update_sprite_watermarks
& drm_plane_index(p
))
13897 intel_update_sprite_watermarks(p
, crtc
, 0, 0, 0,
13900 memset(&intel_crtc
->atomic
, 0, sizeof(intel_crtc
->atomic
));
13904 * intel_plane_destroy - destroy a plane
13905 * @plane: plane to destroy
13907 * Common destruction function for all types of planes (primary, cursor,
13910 void intel_plane_destroy(struct drm_plane
*plane
)
13912 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13913 drm_plane_cleanup(plane
);
13914 kfree(intel_plane
);
13917 const struct drm_plane_funcs intel_plane_funcs
= {
13918 .update_plane
= drm_atomic_helper_update_plane
,
13919 .disable_plane
= drm_atomic_helper_disable_plane
,
13920 .destroy
= intel_plane_destroy
,
13921 .set_property
= drm_atomic_helper_plane_set_property
,
13922 .atomic_get_property
= intel_plane_atomic_get_property
,
13923 .atomic_set_property
= intel_plane_atomic_set_property
,
13924 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13925 .atomic_destroy_state
= intel_plane_destroy_state
,
13929 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
13932 struct intel_plane
*primary
;
13933 struct intel_plane_state
*state
;
13934 const uint32_t *intel_primary_formats
;
13937 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
13938 if (primary
== NULL
)
13941 state
= intel_create_plane_state(&primary
->base
);
13946 primary
->base
.state
= &state
->base
;
13948 primary
->can_scale
= false;
13949 primary
->max_downscale
= 1;
13950 if (INTEL_INFO(dev
)->gen
>= 9) {
13951 primary
->can_scale
= true;
13952 state
->scaler_id
= -1;
13954 primary
->pipe
= pipe
;
13955 primary
->plane
= pipe
;
13956 primary
->check_plane
= intel_check_primary_plane
;
13957 primary
->commit_plane
= intel_commit_primary_plane
;
13958 primary
->disable_plane
= intel_disable_primary_plane
;
13959 primary
->ckey
.flags
= I915_SET_COLORKEY_NONE
;
13960 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
13961 primary
->plane
= !pipe
;
13963 if (INTEL_INFO(dev
)->gen
>= 9) {
13964 intel_primary_formats
= skl_primary_formats
;
13965 num_formats
= ARRAY_SIZE(skl_primary_formats
);
13966 } else if (INTEL_INFO(dev
)->gen
>= 4) {
13967 intel_primary_formats
= i965_primary_formats
;
13968 num_formats
= ARRAY_SIZE(i965_primary_formats
);
13970 intel_primary_formats
= i8xx_primary_formats
;
13971 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
13974 drm_universal_plane_init(dev
, &primary
->base
, 0,
13975 &intel_plane_funcs
,
13976 intel_primary_formats
, num_formats
,
13977 DRM_PLANE_TYPE_PRIMARY
);
13979 if (INTEL_INFO(dev
)->gen
>= 4)
13980 intel_create_rotation_property(dev
, primary
);
13982 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
13984 return &primary
->base
;
13987 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
13989 if (!dev
->mode_config
.rotation_property
) {
13990 unsigned long flags
= BIT(DRM_ROTATE_0
) |
13991 BIT(DRM_ROTATE_180
);
13993 if (INTEL_INFO(dev
)->gen
>= 9)
13994 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
13996 dev
->mode_config
.rotation_property
=
13997 drm_mode_create_rotation_property(dev
, flags
);
13999 if (dev
->mode_config
.rotation_property
)
14000 drm_object_attach_property(&plane
->base
.base
,
14001 dev
->mode_config
.rotation_property
,
14002 plane
->base
.state
->rotation
);
14006 intel_check_cursor_plane(struct drm_plane
*plane
,
14007 struct intel_plane_state
*state
)
14009 struct drm_crtc
*crtc
= state
->base
.crtc
;
14010 struct drm_device
*dev
= plane
->dev
;
14011 struct drm_framebuffer
*fb
= state
->base
.fb
;
14012 struct drm_rect
*dest
= &state
->dst
;
14013 struct drm_rect
*src
= &state
->src
;
14014 const struct drm_rect
*clip
= &state
->clip
;
14015 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
14016 struct intel_crtc
*intel_crtc
;
14020 crtc
= crtc
? crtc
: plane
->crtc
;
14021 intel_crtc
= to_intel_crtc(crtc
);
14023 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
14025 DRM_PLANE_HELPER_NO_SCALING
,
14026 DRM_PLANE_HELPER_NO_SCALING
,
14027 true, true, &state
->visible
);
14032 /* if we want to turn off the cursor ignore width and height */
14036 /* Check for which cursor types we support */
14037 if (!cursor_size_ok(dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
14038 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14039 state
->base
.crtc_w
, state
->base
.crtc_h
);
14043 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
14044 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
14045 DRM_DEBUG_KMS("buffer is too small\n");
14049 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
14050 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14055 if (intel_crtc
->active
) {
14056 if (plane
->state
->crtc_w
!= state
->base
.crtc_w
)
14057 intel_crtc
->atomic
.update_wm
= true;
14059 intel_crtc
->atomic
.fb_bits
|=
14060 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
);
14067 intel_disable_cursor_plane(struct drm_plane
*plane
,
14068 struct drm_crtc
*crtc
,
14071 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14075 intel_crtc
->cursor_bo
= NULL
;
14076 intel_crtc
->cursor_addr
= 0;
14079 intel_crtc_update_cursor(crtc
, false);
14083 intel_commit_cursor_plane(struct drm_plane
*plane
,
14084 struct intel_plane_state
*state
)
14086 struct drm_crtc
*crtc
= state
->base
.crtc
;
14087 struct drm_device
*dev
= plane
->dev
;
14088 struct intel_crtc
*intel_crtc
;
14089 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
14092 crtc
= crtc
? crtc
: plane
->crtc
;
14093 intel_crtc
= to_intel_crtc(crtc
);
14095 plane
->fb
= state
->base
.fb
;
14096 crtc
->cursor_x
= state
->base
.crtc_x
;
14097 crtc
->cursor_y
= state
->base
.crtc_y
;
14099 if (intel_crtc
->cursor_bo
== obj
)
14104 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
14105 addr
= i915_gem_obj_ggtt_offset(obj
);
14107 addr
= obj
->phys_handle
->busaddr
;
14109 intel_crtc
->cursor_addr
= addr
;
14110 intel_crtc
->cursor_bo
= obj
;
14113 if (intel_crtc
->active
)
14114 intel_crtc_update_cursor(crtc
, state
->visible
);
14117 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
14120 struct intel_plane
*cursor
;
14121 struct intel_plane_state
*state
;
14123 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
14124 if (cursor
== NULL
)
14127 state
= intel_create_plane_state(&cursor
->base
);
14132 cursor
->base
.state
= &state
->base
;
14134 cursor
->can_scale
= false;
14135 cursor
->max_downscale
= 1;
14136 cursor
->pipe
= pipe
;
14137 cursor
->plane
= pipe
;
14138 cursor
->check_plane
= intel_check_cursor_plane
;
14139 cursor
->commit_plane
= intel_commit_cursor_plane
;
14140 cursor
->disable_plane
= intel_disable_cursor_plane
;
14142 drm_universal_plane_init(dev
, &cursor
->base
, 0,
14143 &intel_plane_funcs
,
14144 intel_cursor_formats
,
14145 ARRAY_SIZE(intel_cursor_formats
),
14146 DRM_PLANE_TYPE_CURSOR
);
14148 if (INTEL_INFO(dev
)->gen
>= 4) {
14149 if (!dev
->mode_config
.rotation_property
)
14150 dev
->mode_config
.rotation_property
=
14151 drm_mode_create_rotation_property(dev
,
14152 BIT(DRM_ROTATE_0
) |
14153 BIT(DRM_ROTATE_180
));
14154 if (dev
->mode_config
.rotation_property
)
14155 drm_object_attach_property(&cursor
->base
.base
,
14156 dev
->mode_config
.rotation_property
,
14157 state
->base
.rotation
);
14160 if (INTEL_INFO(dev
)->gen
>=9)
14161 state
->scaler_id
= -1;
14163 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
14165 return &cursor
->base
;
14168 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
14169 struct intel_crtc_state
*crtc_state
)
14172 struct intel_scaler
*intel_scaler
;
14173 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
14175 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
14176 intel_scaler
= &scaler_state
->scalers
[i
];
14177 intel_scaler
->in_use
= 0;
14178 intel_scaler
->id
= i
;
14180 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
14183 scaler_state
->scaler_id
= -1;
14186 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
14188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14189 struct intel_crtc
*intel_crtc
;
14190 struct intel_crtc_state
*crtc_state
= NULL
;
14191 struct drm_plane
*primary
= NULL
;
14192 struct drm_plane
*cursor
= NULL
;
14195 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
14196 if (intel_crtc
== NULL
)
14199 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
14202 intel_crtc
->config
= crtc_state
;
14203 intel_crtc
->base
.state
= &crtc_state
->base
;
14204 crtc_state
->base
.crtc
= &intel_crtc
->base
;
14206 /* initialize shared scalers */
14207 if (INTEL_INFO(dev
)->gen
>= 9) {
14208 if (pipe
== PIPE_C
)
14209 intel_crtc
->num_scalers
= 1;
14211 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
14213 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
14216 primary
= intel_primary_plane_create(dev
, pipe
);
14220 cursor
= intel_cursor_plane_create(dev
, pipe
);
14224 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
14225 cursor
, &intel_crtc_funcs
);
14229 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
14230 for (i
= 0; i
< 256; i
++) {
14231 intel_crtc
->lut_r
[i
] = i
;
14232 intel_crtc
->lut_g
[i
] = i
;
14233 intel_crtc
->lut_b
[i
] = i
;
14237 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14238 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14240 intel_crtc
->pipe
= pipe
;
14241 intel_crtc
->plane
= pipe
;
14242 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
14243 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14244 intel_crtc
->plane
= !pipe
;
14247 intel_crtc
->cursor_base
= ~0;
14248 intel_crtc
->cursor_cntl
= ~0;
14249 intel_crtc
->cursor_size
= ~0;
14251 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
14252 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
14253 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
14254 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
14256 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
14258 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
14263 drm_plane_cleanup(primary
);
14265 drm_plane_cleanup(cursor
);
14270 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
14272 struct drm_encoder
*encoder
= connector
->base
.encoder
;
14273 struct drm_device
*dev
= connector
->base
.dev
;
14275 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
14277 if (!encoder
|| WARN_ON(!encoder
->crtc
))
14278 return INVALID_PIPE
;
14280 return to_intel_crtc(encoder
->crtc
)->pipe
;
14283 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
14284 struct drm_file
*file
)
14286 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
14287 struct drm_crtc
*drmmode_crtc
;
14288 struct intel_crtc
*crtc
;
14290 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
14292 if (!drmmode_crtc
) {
14293 DRM_ERROR("no such CRTC id\n");
14297 crtc
= to_intel_crtc(drmmode_crtc
);
14298 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
14303 static int intel_encoder_clones(struct intel_encoder
*encoder
)
14305 struct drm_device
*dev
= encoder
->base
.dev
;
14306 struct intel_encoder
*source_encoder
;
14307 int index_mask
= 0;
14310 for_each_intel_encoder(dev
, source_encoder
) {
14311 if (encoders_cloneable(encoder
, source_encoder
))
14312 index_mask
|= (1 << entry
);
14320 static bool has_edp_a(struct drm_device
*dev
)
14322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14324 if (!IS_MOBILE(dev
))
14327 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
14330 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
14336 static bool intel_crt_present(struct drm_device
*dev
)
14338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14340 if (INTEL_INFO(dev
)->gen
>= 9)
14343 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
14346 if (IS_CHERRYVIEW(dev
))
14349 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
14355 static void intel_setup_outputs(struct drm_device
*dev
)
14357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14358 struct intel_encoder
*encoder
;
14359 bool dpd_is_edp
= false;
14361 intel_lvds_init(dev
);
14363 if (intel_crt_present(dev
))
14364 intel_crt_init(dev
);
14366 if (IS_BROXTON(dev
)) {
14368 * FIXME: Broxton doesn't support port detection via the
14369 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14370 * detect the ports.
14372 intel_ddi_init(dev
, PORT_A
);
14373 intel_ddi_init(dev
, PORT_B
);
14374 intel_ddi_init(dev
, PORT_C
);
14375 } else if (HAS_DDI(dev
)) {
14379 * Haswell uses DDI functions to detect digital outputs.
14380 * On SKL pre-D0 the strap isn't connected, so we assume
14383 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
14384 /* WaIgnoreDDIAStrap: skl */
14386 (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) < SKL_REVID_D0
))
14387 intel_ddi_init(dev
, PORT_A
);
14389 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14391 found
= I915_READ(SFUSE_STRAP
);
14393 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
14394 intel_ddi_init(dev
, PORT_B
);
14395 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
14396 intel_ddi_init(dev
, PORT_C
);
14397 if (found
& SFUSE_STRAP_DDID_DETECTED
)
14398 intel_ddi_init(dev
, PORT_D
);
14399 } else if (HAS_PCH_SPLIT(dev
)) {
14401 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
14403 if (has_edp_a(dev
))
14404 intel_dp_init(dev
, DP_A
, PORT_A
);
14406 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
14407 /* PCH SDVOB multiplex with HDMIB */
14408 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
14410 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
14411 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
14412 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
14415 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
14416 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
14418 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
14419 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
14421 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
14422 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
14424 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
14425 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
14426 } else if (IS_VALLEYVIEW(dev
)) {
14428 * The DP_DETECTED bit is the latched state of the DDC
14429 * SDA pin at boot. However since eDP doesn't require DDC
14430 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14431 * eDP ports may have been muxed to an alternate function.
14432 * Thus we can't rely on the DP_DETECTED bit alone to detect
14433 * eDP ports. Consult the VBT as well as DP_DETECTED to
14434 * detect eDP ports.
14436 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
14437 !intel_dp_is_edp(dev
, PORT_B
))
14438 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
14440 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
14441 intel_dp_is_edp(dev
, PORT_B
))
14442 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
14444 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
14445 !intel_dp_is_edp(dev
, PORT_C
))
14446 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
14448 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
14449 intel_dp_is_edp(dev
, PORT_C
))
14450 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
14452 if (IS_CHERRYVIEW(dev
)) {
14453 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
14454 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
14456 /* eDP not supported on port D, so don't check VBT */
14457 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
14458 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
14461 intel_dsi_init(dev
);
14462 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
14463 bool found
= false;
14465 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14466 DRM_DEBUG_KMS("probing SDVOB\n");
14467 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
14468 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
14469 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14470 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
14473 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
14474 intel_dp_init(dev
, DP_B
, PORT_B
);
14477 /* Before G4X SDVOC doesn't have its own detect register */
14479 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14480 DRM_DEBUG_KMS("probing SDVOC\n");
14481 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
14484 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14486 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
14487 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14488 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
14490 if (SUPPORTS_INTEGRATED_DP(dev
))
14491 intel_dp_init(dev
, DP_C
, PORT_C
);
14494 if (SUPPORTS_INTEGRATED_DP(dev
) &&
14495 (I915_READ(DP_D
) & DP_DETECTED
))
14496 intel_dp_init(dev
, DP_D
, PORT_D
);
14497 } else if (IS_GEN2(dev
))
14498 intel_dvo_init(dev
);
14500 if (SUPPORTS_TV(dev
))
14501 intel_tv_init(dev
);
14503 intel_psr_init(dev
);
14505 for_each_intel_encoder(dev
, encoder
) {
14506 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
14507 encoder
->base
.possible_clones
=
14508 intel_encoder_clones(encoder
);
14511 intel_init_pch_refclk(dev
);
14513 drm_helper_move_panel_connectors_to_head(dev
);
14516 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
14518 struct drm_device
*dev
= fb
->dev
;
14519 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14521 drm_framebuffer_cleanup(fb
);
14522 mutex_lock(&dev
->struct_mutex
);
14523 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
14524 drm_gem_object_unreference(&intel_fb
->obj
->base
);
14525 mutex_unlock(&dev
->struct_mutex
);
14529 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
14530 struct drm_file
*file
,
14531 unsigned int *handle
)
14533 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14534 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14536 return drm_gem_handle_create(file
, &obj
->base
, handle
);
14539 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
14540 .destroy
= intel_user_framebuffer_destroy
,
14541 .create_handle
= intel_user_framebuffer_create_handle
,
14545 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
14546 uint32_t pixel_format
)
14548 u32 gen
= INTEL_INFO(dev
)->gen
;
14551 /* "The stride in bytes must not exceed the of the size of 8K
14552 * pixels and 32K bytes."
14554 return min(8192*drm_format_plane_cpp(pixel_format
, 0), 32768);
14555 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
14557 } else if (gen
>= 4) {
14558 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14562 } else if (gen
>= 3) {
14563 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14568 /* XXX DSPC is limited to 4k tiled */
14573 static int intel_framebuffer_init(struct drm_device
*dev
,
14574 struct intel_framebuffer
*intel_fb
,
14575 struct drm_mode_fb_cmd2
*mode_cmd
,
14576 struct drm_i915_gem_object
*obj
)
14578 unsigned int aligned_height
;
14580 u32 pitch_limit
, stride_alignment
;
14582 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
14584 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
14585 /* Enforce that fb modifier and tiling mode match, but only for
14586 * X-tiled. This is needed for FBC. */
14587 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
14588 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
14589 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14593 if (obj
->tiling_mode
== I915_TILING_X
)
14594 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
14595 else if (obj
->tiling_mode
== I915_TILING_Y
) {
14596 DRM_DEBUG("No Y tiling for legacy addfb\n");
14601 /* Passed in modifier sanity checking. */
14602 switch (mode_cmd
->modifier
[0]) {
14603 case I915_FORMAT_MOD_Y_TILED
:
14604 case I915_FORMAT_MOD_Yf_TILED
:
14605 if (INTEL_INFO(dev
)->gen
< 9) {
14606 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14607 mode_cmd
->modifier
[0]);
14610 case DRM_FORMAT_MOD_NONE
:
14611 case I915_FORMAT_MOD_X_TILED
:
14614 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14615 mode_cmd
->modifier
[0]);
14619 stride_alignment
= intel_fb_stride_alignment(dev
, mode_cmd
->modifier
[0],
14620 mode_cmd
->pixel_format
);
14621 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
14622 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14623 mode_cmd
->pitches
[0], stride_alignment
);
14627 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
14628 mode_cmd
->pixel_format
);
14629 if (mode_cmd
->pitches
[0] > pitch_limit
) {
14630 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14631 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
14632 "tiled" : "linear",
14633 mode_cmd
->pitches
[0], pitch_limit
);
14637 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
14638 mode_cmd
->pitches
[0] != obj
->stride
) {
14639 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14640 mode_cmd
->pitches
[0], obj
->stride
);
14644 /* Reject formats not supported by any plane early. */
14645 switch (mode_cmd
->pixel_format
) {
14646 case DRM_FORMAT_C8
:
14647 case DRM_FORMAT_RGB565
:
14648 case DRM_FORMAT_XRGB8888
:
14649 case DRM_FORMAT_ARGB8888
:
14651 case DRM_FORMAT_XRGB1555
:
14652 if (INTEL_INFO(dev
)->gen
> 3) {
14653 DRM_DEBUG("unsupported pixel format: %s\n",
14654 drm_get_format_name(mode_cmd
->pixel_format
));
14658 case DRM_FORMAT_ABGR8888
:
14659 if (!IS_VALLEYVIEW(dev
) && INTEL_INFO(dev
)->gen
< 9) {
14660 DRM_DEBUG("unsupported pixel format: %s\n",
14661 drm_get_format_name(mode_cmd
->pixel_format
));
14665 case DRM_FORMAT_XBGR8888
:
14666 case DRM_FORMAT_XRGB2101010
:
14667 case DRM_FORMAT_XBGR2101010
:
14668 if (INTEL_INFO(dev
)->gen
< 4) {
14669 DRM_DEBUG("unsupported pixel format: %s\n",
14670 drm_get_format_name(mode_cmd
->pixel_format
));
14674 case DRM_FORMAT_ABGR2101010
:
14675 if (!IS_VALLEYVIEW(dev
)) {
14676 DRM_DEBUG("unsupported pixel format: %s\n",
14677 drm_get_format_name(mode_cmd
->pixel_format
));
14681 case DRM_FORMAT_YUYV
:
14682 case DRM_FORMAT_UYVY
:
14683 case DRM_FORMAT_YVYU
:
14684 case DRM_FORMAT_VYUY
:
14685 if (INTEL_INFO(dev
)->gen
< 5) {
14686 DRM_DEBUG("unsupported pixel format: %s\n",
14687 drm_get_format_name(mode_cmd
->pixel_format
));
14692 DRM_DEBUG("unsupported pixel format: %s\n",
14693 drm_get_format_name(mode_cmd
->pixel_format
));
14697 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14698 if (mode_cmd
->offsets
[0] != 0)
14701 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
14702 mode_cmd
->pixel_format
,
14703 mode_cmd
->modifier
[0]);
14704 /* FIXME drm helper for size checks (especially planar formats)? */
14705 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
14708 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
14709 intel_fb
->obj
= obj
;
14710 intel_fb
->obj
->framebuffer_references
++;
14712 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
14714 DRM_ERROR("framebuffer init failed %d\n", ret
);
14721 static struct drm_framebuffer
*
14722 intel_user_framebuffer_create(struct drm_device
*dev
,
14723 struct drm_file
*filp
,
14724 struct drm_mode_fb_cmd2
*mode_cmd
)
14726 struct drm_i915_gem_object
*obj
;
14728 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
14729 mode_cmd
->handles
[0]));
14730 if (&obj
->base
== NULL
)
14731 return ERR_PTR(-ENOENT
);
14733 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
14736 #ifndef CONFIG_DRM_I915_FBDEV
14737 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
14742 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14743 .fb_create
= intel_user_framebuffer_create
,
14744 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14745 .atomic_check
= intel_atomic_check
,
14746 .atomic_commit
= intel_atomic_commit
,
14749 /* Set up chip specific display functions */
14750 static void intel_init_display(struct drm_device
*dev
)
14752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14754 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
14755 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
14756 else if (IS_CHERRYVIEW(dev
))
14757 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
14758 else if (IS_VALLEYVIEW(dev
))
14759 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
14760 else if (IS_PINEVIEW(dev
))
14761 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
14763 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
14765 if (INTEL_INFO(dev
)->gen
>= 9) {
14766 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14767 dev_priv
->display
.get_initial_plane_config
=
14768 skylake_get_initial_plane_config
;
14769 dev_priv
->display
.crtc_compute_clock
=
14770 haswell_crtc_compute_clock
;
14771 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14772 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14773 dev_priv
->display
.off
= ironlake_crtc_off
;
14774 dev_priv
->display
.update_primary_plane
=
14775 skylake_update_primary_plane
;
14776 } else if (HAS_DDI(dev
)) {
14777 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14778 dev_priv
->display
.get_initial_plane_config
=
14779 ironlake_get_initial_plane_config
;
14780 dev_priv
->display
.crtc_compute_clock
=
14781 haswell_crtc_compute_clock
;
14782 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14783 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14784 dev_priv
->display
.off
= ironlake_crtc_off
;
14785 dev_priv
->display
.update_primary_plane
=
14786 ironlake_update_primary_plane
;
14787 } else if (HAS_PCH_SPLIT(dev
)) {
14788 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14789 dev_priv
->display
.get_initial_plane_config
=
14790 ironlake_get_initial_plane_config
;
14791 dev_priv
->display
.crtc_compute_clock
=
14792 ironlake_crtc_compute_clock
;
14793 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14794 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14795 dev_priv
->display
.off
= ironlake_crtc_off
;
14796 dev_priv
->display
.update_primary_plane
=
14797 ironlake_update_primary_plane
;
14798 } else if (IS_VALLEYVIEW(dev
)) {
14799 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14800 dev_priv
->display
.get_initial_plane_config
=
14801 i9xx_get_initial_plane_config
;
14802 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14803 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14804 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14805 dev_priv
->display
.off
= i9xx_crtc_off
;
14806 dev_priv
->display
.update_primary_plane
=
14807 i9xx_update_primary_plane
;
14809 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14810 dev_priv
->display
.get_initial_plane_config
=
14811 i9xx_get_initial_plane_config
;
14812 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14813 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14814 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14815 dev_priv
->display
.off
= i9xx_crtc_off
;
14816 dev_priv
->display
.update_primary_plane
=
14817 i9xx_update_primary_plane
;
14820 /* Returns the core display clock speed */
14821 if (IS_SKYLAKE(dev
))
14822 dev_priv
->display
.get_display_clock_speed
=
14823 skylake_get_display_clock_speed
;
14824 else if (IS_BROADWELL(dev
))
14825 dev_priv
->display
.get_display_clock_speed
=
14826 broadwell_get_display_clock_speed
;
14827 else if (IS_HASWELL(dev
))
14828 dev_priv
->display
.get_display_clock_speed
=
14829 haswell_get_display_clock_speed
;
14830 else if (IS_VALLEYVIEW(dev
))
14831 dev_priv
->display
.get_display_clock_speed
=
14832 valleyview_get_display_clock_speed
;
14833 else if (IS_GEN5(dev
))
14834 dev_priv
->display
.get_display_clock_speed
=
14835 ilk_get_display_clock_speed
;
14836 else if (IS_I945G(dev
) || IS_BROADWATER(dev
) ||
14837 IS_GEN6(dev
) || IS_IVYBRIDGE(dev
))
14838 dev_priv
->display
.get_display_clock_speed
=
14839 i945_get_display_clock_speed
;
14840 else if (IS_GM45(dev
))
14841 dev_priv
->display
.get_display_clock_speed
=
14842 gm45_get_display_clock_speed
;
14843 else if (IS_CRESTLINE(dev
))
14844 dev_priv
->display
.get_display_clock_speed
=
14845 i965gm_get_display_clock_speed
;
14846 else if (IS_PINEVIEW(dev
))
14847 dev_priv
->display
.get_display_clock_speed
=
14848 pnv_get_display_clock_speed
;
14849 else if (IS_G33(dev
) || IS_G4X(dev
))
14850 dev_priv
->display
.get_display_clock_speed
=
14851 g33_get_display_clock_speed
;
14852 else if (IS_I915G(dev
))
14853 dev_priv
->display
.get_display_clock_speed
=
14854 i915_get_display_clock_speed
;
14855 else if (IS_I945GM(dev
) || IS_845G(dev
))
14856 dev_priv
->display
.get_display_clock_speed
=
14857 i9xx_misc_get_display_clock_speed
;
14858 else if (IS_PINEVIEW(dev
))
14859 dev_priv
->display
.get_display_clock_speed
=
14860 pnv_get_display_clock_speed
;
14861 else if (IS_I915GM(dev
))
14862 dev_priv
->display
.get_display_clock_speed
=
14863 i915gm_get_display_clock_speed
;
14864 else if (IS_I865G(dev
))
14865 dev_priv
->display
.get_display_clock_speed
=
14866 i865_get_display_clock_speed
;
14867 else if (IS_I85X(dev
))
14868 dev_priv
->display
.get_display_clock_speed
=
14869 i85x_get_display_clock_speed
;
14871 WARN(!IS_I830(dev
), "Unknown platform. Assuming 133 MHz CDCLK\n");
14872 dev_priv
->display
.get_display_clock_speed
=
14873 i830_get_display_clock_speed
;
14876 if (IS_GEN5(dev
)) {
14877 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
14878 } else if (IS_GEN6(dev
)) {
14879 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
14880 } else if (IS_IVYBRIDGE(dev
)) {
14881 /* FIXME: detect B0+ stepping and use auto training */
14882 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
14883 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
14884 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
14885 if (IS_BROADWELL(dev
))
14886 dev_priv
->display
.modeset_global_resources
=
14887 broadwell_modeset_global_resources
;
14888 } else if (IS_VALLEYVIEW(dev
)) {
14889 dev_priv
->display
.modeset_global_resources
=
14890 valleyview_modeset_global_resources
;
14891 } else if (IS_BROXTON(dev
)) {
14892 dev_priv
->display
.modeset_global_resources
=
14893 broxton_modeset_global_resources
;
14896 switch (INTEL_INFO(dev
)->gen
) {
14898 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
14902 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
14907 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
14911 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
14914 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14915 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
14918 /* Drop through - unsupported since execlist only. */
14920 /* Default just returns -ENODEV to indicate unsupported */
14921 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
14924 intel_panel_init_backlight_funcs(dev
);
14926 mutex_init(&dev_priv
->pps_mutex
);
14930 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14931 * resume, or other times. This quirk makes sure that's the case for
14932 * affected systems.
14934 static void quirk_pipea_force(struct drm_device
*dev
)
14936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14938 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
14939 DRM_INFO("applying pipe a force quirk\n");
14942 static void quirk_pipeb_force(struct drm_device
*dev
)
14944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14946 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
14947 DRM_INFO("applying pipe b force quirk\n");
14951 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14953 static void quirk_ssc_force_disable(struct drm_device
*dev
)
14955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14956 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
14957 DRM_INFO("applying lvds SSC disable quirk\n");
14961 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14964 static void quirk_invert_brightness(struct drm_device
*dev
)
14966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14967 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
14968 DRM_INFO("applying inverted panel brightness quirk\n");
14971 /* Some VBT's incorrectly indicate no backlight is present */
14972 static void quirk_backlight_present(struct drm_device
*dev
)
14974 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14975 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
14976 DRM_INFO("applying backlight present quirk\n");
14979 struct intel_quirk
{
14981 int subsystem_vendor
;
14982 int subsystem_device
;
14983 void (*hook
)(struct drm_device
*dev
);
14986 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14987 struct intel_dmi_quirk
{
14988 void (*hook
)(struct drm_device
*dev
);
14989 const struct dmi_system_id (*dmi_id_list
)[];
14992 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
14994 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
14998 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
15000 .dmi_id_list
= &(const struct dmi_system_id
[]) {
15002 .callback
= intel_dmi_reverse_brightness
,
15003 .ident
= "NCR Corporation",
15004 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
15005 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
15008 { } /* terminating entry */
15010 .hook
= quirk_invert_brightness
,
15014 static struct intel_quirk intel_quirks
[] = {
15015 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15016 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
15018 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15019 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
15021 /* 830 needs to leave pipe A & dpll A up */
15022 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
15024 /* 830 needs to leave pipe B & dpll B up */
15025 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
15027 /* Lenovo U160 cannot use SSC on LVDS */
15028 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
15030 /* Sony Vaio Y cannot use SSC on LVDS */
15031 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
15033 /* Acer Aspire 5734Z must invert backlight brightness */
15034 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
15036 /* Acer/eMachines G725 */
15037 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
15039 /* Acer/eMachines e725 */
15040 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
15042 /* Acer/Packard Bell NCL20 */
15043 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
15045 /* Acer Aspire 4736Z */
15046 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
15048 /* Acer Aspire 5336 */
15049 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
15051 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15052 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
15054 /* Acer C720 Chromebook (Core i3 4005U) */
15055 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
15057 /* Apple Macbook 2,1 (Core 2 T7400) */
15058 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
15060 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15061 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
15063 /* HP Chromebook 14 (Celeron 2955U) */
15064 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
15066 /* Dell Chromebook 11 */
15067 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
15070 static void intel_init_quirks(struct drm_device
*dev
)
15072 struct pci_dev
*d
= dev
->pdev
;
15075 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
15076 struct intel_quirk
*q
= &intel_quirks
[i
];
15078 if (d
->device
== q
->device
&&
15079 (d
->subsystem_vendor
== q
->subsystem_vendor
||
15080 q
->subsystem_vendor
== PCI_ANY_ID
) &&
15081 (d
->subsystem_device
== q
->subsystem_device
||
15082 q
->subsystem_device
== PCI_ANY_ID
))
15085 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
15086 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
15087 intel_dmi_quirks
[i
].hook(dev
);
15091 /* Disable the VGA plane that we never use */
15092 static void i915_disable_vga(struct drm_device
*dev
)
15094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15096 u32 vga_reg
= i915_vgacntrl_reg(dev
);
15098 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15099 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15100 outb(SR01
, VGA_SR_INDEX
);
15101 sr1
= inb(VGA_SR_DATA
);
15102 outb(sr1
| 1<<5, VGA_SR_DATA
);
15103 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15106 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
15107 POSTING_READ(vga_reg
);
15110 void intel_modeset_init_hw(struct drm_device
*dev
)
15112 intel_update_cdclk(dev
);
15113 intel_prepare_ddi(dev
);
15114 intel_init_clock_gating(dev
);
15115 intel_enable_gt_powersave(dev
);
15118 void intel_modeset_init(struct drm_device
*dev
)
15120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15123 struct intel_crtc
*crtc
;
15125 drm_mode_config_init(dev
);
15127 dev
->mode_config
.min_width
= 0;
15128 dev
->mode_config
.min_height
= 0;
15130 dev
->mode_config
.preferred_depth
= 24;
15131 dev
->mode_config
.prefer_shadow
= 1;
15133 dev
->mode_config
.allow_fb_modifiers
= true;
15135 dev
->mode_config
.funcs
= &intel_mode_funcs
;
15137 intel_init_quirks(dev
);
15139 intel_init_pm(dev
);
15141 if (INTEL_INFO(dev
)->num_pipes
== 0)
15144 intel_init_display(dev
);
15145 intel_init_audio(dev
);
15147 if (IS_GEN2(dev
)) {
15148 dev
->mode_config
.max_width
= 2048;
15149 dev
->mode_config
.max_height
= 2048;
15150 } else if (IS_GEN3(dev
)) {
15151 dev
->mode_config
.max_width
= 4096;
15152 dev
->mode_config
.max_height
= 4096;
15154 dev
->mode_config
.max_width
= 8192;
15155 dev
->mode_config
.max_height
= 8192;
15158 if (IS_845G(dev
) || IS_I865G(dev
)) {
15159 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
15160 dev
->mode_config
.cursor_height
= 1023;
15161 } else if (IS_GEN2(dev
)) {
15162 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
15163 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
15165 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
15166 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
15169 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
15171 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15172 INTEL_INFO(dev
)->num_pipes
,
15173 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
15175 for_each_pipe(dev_priv
, pipe
) {
15176 intel_crtc_init(dev
, pipe
);
15177 for_each_sprite(dev_priv
, pipe
, sprite
) {
15178 ret
= intel_plane_init(dev
, pipe
, sprite
);
15180 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15181 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
15185 intel_init_dpio(dev
);
15187 intel_shared_dpll_init(dev
);
15189 /* Just disable it once at startup */
15190 i915_disable_vga(dev
);
15191 intel_setup_outputs(dev
);
15193 /* Just in case the BIOS is doing something questionable. */
15194 intel_fbc_disable(dev
);
15196 drm_modeset_lock_all(dev
);
15197 intel_modeset_setup_hw_state(dev
, false);
15198 drm_modeset_unlock_all(dev
);
15200 for_each_intel_crtc(dev
, crtc
) {
15205 * Note that reserving the BIOS fb up front prevents us
15206 * from stuffing other stolen allocations like the ring
15207 * on top. This prevents some ugliness at boot time, and
15208 * can even allow for smooth boot transitions if the BIOS
15209 * fb is large enough for the active pipe configuration.
15211 if (dev_priv
->display
.get_initial_plane_config
) {
15212 dev_priv
->display
.get_initial_plane_config(crtc
,
15213 &crtc
->plane_config
);
15215 * If the fb is shared between multiple heads, we'll
15216 * just get the first one.
15218 intel_find_initial_plane_obj(crtc
, &crtc
->plane_config
);
15223 static void intel_enable_pipe_a(struct drm_device
*dev
)
15225 struct intel_connector
*connector
;
15226 struct drm_connector
*crt
= NULL
;
15227 struct intel_load_detect_pipe load_detect_temp
;
15228 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
15230 /* We can't just switch on the pipe A, we need to set things up with a
15231 * proper mode and output configuration. As a gross hack, enable pipe A
15232 * by enabling the load detect pipe once. */
15233 for_each_intel_connector(dev
, connector
) {
15234 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
15235 crt
= &connector
->base
;
15243 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
15244 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
15248 intel_check_plane_mapping(struct intel_crtc
*crtc
)
15250 struct drm_device
*dev
= crtc
->base
.dev
;
15251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15254 if (INTEL_INFO(dev
)->num_pipes
== 1)
15257 reg
= DSPCNTR(!crtc
->plane
);
15258 val
= I915_READ(reg
);
15260 if ((val
& DISPLAY_PLANE_ENABLE
) &&
15261 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
15267 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
15269 struct drm_device
*dev
= crtc
->base
.dev
;
15270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15273 /* Clear any frame start delays used for debugging left by the BIOS */
15274 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
15275 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
15277 /* restore vblank interrupts to correct state */
15278 drm_crtc_vblank_reset(&crtc
->base
);
15279 if (crtc
->active
) {
15280 update_scanline_offset(crtc
);
15281 drm_crtc_vblank_on(&crtc
->base
);
15284 /* We need to sanitize the plane -> pipe mapping first because this will
15285 * disable the crtc (and hence change the state) if it is wrong. Note
15286 * that gen4+ has a fixed plane -> pipe mapping. */
15287 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
15288 struct intel_connector
*connector
;
15291 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15292 crtc
->base
.base
.id
);
15294 /* Pipe has the wrong plane attached and the plane is active.
15295 * Temporarily change the plane mapping and disable everything
15297 plane
= crtc
->plane
;
15298 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
15299 crtc
->plane
= !plane
;
15300 intel_crtc_disable_planes(&crtc
->base
);
15301 dev_priv
->display
.crtc_disable(&crtc
->base
);
15302 crtc
->plane
= plane
;
15304 /* ... and break all links. */
15305 for_each_intel_connector(dev
, connector
) {
15306 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
15309 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15310 connector
->base
.encoder
= NULL
;
15312 /* multiple connectors may have the same encoder:
15313 * handle them and break crtc link separately */
15314 for_each_intel_connector(dev
, connector
)
15315 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
15316 connector
->encoder
->base
.crtc
= NULL
;
15317 connector
->encoder
->connectors_active
= false;
15320 WARN_ON(crtc
->active
);
15321 crtc
->base
.state
->enable
= false;
15322 crtc
->base
.state
->active
= false;
15323 crtc
->base
.enabled
= false;
15326 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
15327 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
15328 /* BIOS forgot to enable pipe A, this mostly happens after
15329 * resume. Force-enable the pipe to fix this, the update_dpms
15330 * call below we restore the pipe to the right state, but leave
15331 * the required bits on. */
15332 intel_enable_pipe_a(dev
);
15335 /* Adjust the state of the output pipe according to whether we
15336 * have active connectors/encoders. */
15337 intel_crtc_update_dpms(&crtc
->base
);
15339 if (crtc
->active
!= crtc
->base
.state
->enable
) {
15340 struct intel_encoder
*encoder
;
15342 /* This can happen either due to bugs in the get_hw_state
15343 * functions or because the pipe is force-enabled due to the
15345 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15346 crtc
->base
.base
.id
,
15347 crtc
->base
.state
->enable
? "enabled" : "disabled",
15348 crtc
->active
? "enabled" : "disabled");
15350 crtc
->base
.state
->enable
= crtc
->active
;
15351 crtc
->base
.state
->active
= crtc
->active
;
15352 crtc
->base
.enabled
= crtc
->active
;
15354 /* Because we only establish the connector -> encoder ->
15355 * crtc links if something is active, this means the
15356 * crtc is now deactivated. Break the links. connector
15357 * -> encoder links are only establish when things are
15358 * actually up, hence no need to break them. */
15359 WARN_ON(crtc
->active
);
15361 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
15362 WARN_ON(encoder
->connectors_active
);
15363 encoder
->base
.crtc
= NULL
;
15367 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
15369 * We start out with underrun reporting disabled to avoid races.
15370 * For correct bookkeeping mark this on active crtcs.
15372 * Also on gmch platforms we dont have any hardware bits to
15373 * disable the underrun reporting. Which means we need to start
15374 * out with underrun reporting disabled also on inactive pipes,
15375 * since otherwise we'll complain about the garbage we read when
15376 * e.g. coming up after runtime pm.
15378 * No protection against concurrent access is required - at
15379 * worst a fifo underrun happens which also sets this to false.
15381 crtc
->cpu_fifo_underrun_disabled
= true;
15382 crtc
->pch_fifo_underrun_disabled
= true;
15386 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
15388 struct intel_connector
*connector
;
15389 struct drm_device
*dev
= encoder
->base
.dev
;
15391 /* We need to check both for a crtc link (meaning that the
15392 * encoder is active and trying to read from a pipe) and the
15393 * pipe itself being active. */
15394 bool has_active_crtc
= encoder
->base
.crtc
&&
15395 to_intel_crtc(encoder
->base
.crtc
)->active
;
15397 if (encoder
->connectors_active
&& !has_active_crtc
) {
15398 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15399 encoder
->base
.base
.id
,
15400 encoder
->base
.name
);
15402 /* Connector is active, but has no active pipe. This is
15403 * fallout from our resume register restoring. Disable
15404 * the encoder manually again. */
15405 if (encoder
->base
.crtc
) {
15406 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15407 encoder
->base
.base
.id
,
15408 encoder
->base
.name
);
15409 encoder
->disable(encoder
);
15410 if (encoder
->post_disable
)
15411 encoder
->post_disable(encoder
);
15413 encoder
->base
.crtc
= NULL
;
15414 encoder
->connectors_active
= false;
15416 /* Inconsistent output/port/pipe state happens presumably due to
15417 * a bug in one of the get_hw_state functions. Or someplace else
15418 * in our code, like the register restore mess on resume. Clamp
15419 * things to off as a safer default. */
15420 for_each_intel_connector(dev
, connector
) {
15421 if (connector
->encoder
!= encoder
)
15423 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15424 connector
->base
.encoder
= NULL
;
15427 /* Enabled encoders without active connectors will be fixed in
15428 * the crtc fixup. */
15431 void i915_redisable_vga_power_on(struct drm_device
*dev
)
15433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15434 u32 vga_reg
= i915_vgacntrl_reg(dev
);
15436 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
15437 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15438 i915_disable_vga(dev
);
15442 void i915_redisable_vga(struct drm_device
*dev
)
15444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15446 /* This function can be called both from intel_modeset_setup_hw_state or
15447 * at a very early point in our resume sequence, where the power well
15448 * structures are not yet restored. Since this function is at a very
15449 * paranoid "someone might have enabled VGA while we were not looking"
15450 * level, just check if the power well is enabled instead of trying to
15451 * follow the "don't touch the power well if we don't need it" policy
15452 * the rest of the driver uses. */
15453 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
15456 i915_redisable_vga_power_on(dev
);
15459 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
15461 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
15466 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
15469 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
15471 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15473 struct intel_crtc
*crtc
;
15474 struct intel_encoder
*encoder
;
15475 struct intel_connector
*connector
;
15478 for_each_intel_crtc(dev
, crtc
) {
15479 struct drm_plane
*primary
= crtc
->base
.primary
;
15480 struct intel_plane_state
*plane_state
;
15482 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
15484 crtc
->config
->quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
15486 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
15489 crtc
->base
.state
->enable
= crtc
->active
;
15490 crtc
->base
.state
->active
= crtc
->active
;
15491 crtc
->base
.enabled
= crtc
->active
;
15493 plane_state
= to_intel_plane_state(primary
->state
);
15494 plane_state
->visible
= primary_get_hw_state(crtc
);
15496 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15497 crtc
->base
.base
.id
,
15498 crtc
->active
? "enabled" : "disabled");
15501 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15502 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15504 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
15505 &pll
->config
.hw_state
);
15507 pll
->config
.crtc_mask
= 0;
15508 for_each_intel_crtc(dev
, crtc
) {
15509 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
15511 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
15515 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15516 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
15518 if (pll
->config
.crtc_mask
)
15519 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
15522 for_each_intel_encoder(dev
, encoder
) {
15525 if (encoder
->get_hw_state(encoder
, &pipe
)) {
15526 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15527 encoder
->base
.crtc
= &crtc
->base
;
15528 encoder
->get_config(encoder
, crtc
->config
);
15530 encoder
->base
.crtc
= NULL
;
15533 encoder
->connectors_active
= false;
15534 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15535 encoder
->base
.base
.id
,
15536 encoder
->base
.name
,
15537 encoder
->base
.crtc
? "enabled" : "disabled",
15541 for_each_intel_connector(dev
, connector
) {
15542 if (connector
->get_hw_state(connector
)) {
15543 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
15544 connector
->encoder
->connectors_active
= true;
15545 connector
->base
.encoder
= &connector
->encoder
->base
;
15547 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15548 connector
->base
.encoder
= NULL
;
15550 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15551 connector
->base
.base
.id
,
15552 connector
->base
.name
,
15553 connector
->base
.encoder
? "enabled" : "disabled");
15557 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15558 * and i915 state tracking structures. */
15559 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
15560 bool force_restore
)
15562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15564 struct intel_crtc
*crtc
;
15565 struct intel_encoder
*encoder
;
15568 intel_modeset_readout_hw_state(dev
);
15571 * Now that we have the config, copy it to each CRTC struct
15572 * Note that this could go away if we move to using crtc_config
15573 * checking everywhere.
15575 for_each_intel_crtc(dev
, crtc
) {
15576 if (crtc
->active
&& i915
.fastboot
) {
15577 intel_mode_from_pipe_config(&crtc
->base
.mode
,
15579 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15580 crtc
->base
.base
.id
);
15581 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
15585 /* HW state is read out, now we need to sanitize this mess. */
15586 for_each_intel_encoder(dev
, encoder
) {
15587 intel_sanitize_encoder(encoder
);
15590 for_each_pipe(dev_priv
, pipe
) {
15591 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15592 intel_sanitize_crtc(crtc
);
15593 intel_dump_pipe_config(crtc
, crtc
->config
,
15594 "[setup_hw_state]");
15597 intel_modeset_update_connector_atomic_state(dev
);
15599 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15600 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15602 if (!pll
->on
|| pll
->active
)
15605 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
15607 pll
->disable(dev_priv
, pll
);
15612 skl_wm_get_hw_state(dev
);
15613 else if (HAS_PCH_SPLIT(dev
))
15614 ilk_wm_get_hw_state(dev
);
15616 if (force_restore
) {
15617 i915_redisable_vga(dev
);
15620 * We need to use raw interfaces for restoring state to avoid
15621 * checking (bogus) intermediate states.
15623 for_each_pipe(dev_priv
, pipe
) {
15624 struct drm_crtc
*crtc
=
15625 dev_priv
->pipe_to_crtc_mapping
[pipe
];
15627 intel_crtc_restore_mode(crtc
);
15630 intel_modeset_update_staged_output_state(dev
);
15633 intel_modeset_check_state(dev
);
15636 void intel_modeset_gem_init(struct drm_device
*dev
)
15638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15639 struct drm_crtc
*c
;
15640 struct drm_i915_gem_object
*obj
;
15643 mutex_lock(&dev
->struct_mutex
);
15644 intel_init_gt_powersave(dev
);
15645 mutex_unlock(&dev
->struct_mutex
);
15648 * There may be no VBT; and if the BIOS enabled SSC we can
15649 * just keep using it to avoid unnecessary flicker. Whereas if the
15650 * BIOS isn't using it, don't assume it will work even if the VBT
15651 * indicates as much.
15653 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
15654 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15657 intel_modeset_init_hw(dev
);
15659 intel_setup_overlay(dev
);
15662 * Make sure any fbs we allocated at startup are properly
15663 * pinned & fenced. When we do the allocation it's too early
15666 for_each_crtc(dev
, c
) {
15667 obj
= intel_fb_obj(c
->primary
->fb
);
15671 mutex_lock(&dev
->struct_mutex
);
15672 ret
= intel_pin_and_fence_fb_obj(c
->primary
,
15676 mutex_unlock(&dev
->struct_mutex
);
15678 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15679 to_intel_crtc(c
)->pipe
);
15680 drm_framebuffer_unreference(c
->primary
->fb
);
15681 c
->primary
->fb
= NULL
;
15682 update_state_fb(c
->primary
);
15686 intel_backlight_register(dev
);
15689 void intel_connector_unregister(struct intel_connector
*intel_connector
)
15691 struct drm_connector
*connector
= &intel_connector
->base
;
15693 intel_panel_destroy_backlight(connector
);
15694 drm_connector_unregister(connector
);
15697 void intel_modeset_cleanup(struct drm_device
*dev
)
15699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15700 struct drm_connector
*connector
;
15702 intel_disable_gt_powersave(dev
);
15704 intel_backlight_unregister(dev
);
15707 * Interrupts and polling as the first thing to avoid creating havoc.
15708 * Too much stuff here (turning of connectors, ...) would
15709 * experience fancy races otherwise.
15711 intel_irq_uninstall(dev_priv
);
15714 * Due to the hpd irq storm handling the hotplug work can re-arm the
15715 * poll handlers. Hence disable polling after hpd handling is shut down.
15717 drm_kms_helper_poll_fini(dev
);
15719 mutex_lock(&dev
->struct_mutex
);
15721 intel_unregister_dsm_handler();
15723 intel_fbc_disable(dev
);
15725 mutex_unlock(&dev
->struct_mutex
);
15727 /* flush any delayed tasks or pending work */
15728 flush_scheduled_work();
15730 /* destroy the backlight and sysfs files before encoders/connectors */
15731 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
15732 struct intel_connector
*intel_connector
;
15734 intel_connector
= to_intel_connector(connector
);
15735 intel_connector
->unregister(intel_connector
);
15738 drm_mode_config_cleanup(dev
);
15740 intel_cleanup_overlay(dev
);
15742 mutex_lock(&dev
->struct_mutex
);
15743 intel_cleanup_gt_powersave(dev
);
15744 mutex_unlock(&dev
->struct_mutex
);
15748 * Return which encoder is currently attached for connector.
15750 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
15752 return &intel_attached_encoder(connector
)->base
;
15755 void intel_connector_attach_encoder(struct intel_connector
*connector
,
15756 struct intel_encoder
*encoder
)
15758 connector
->encoder
= encoder
;
15759 drm_mode_connector_attach_encoder(&connector
->base
,
15764 * set vga decode state - true == enable VGA decode
15766 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
15768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15769 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
15772 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
15773 DRM_ERROR("failed to read control word\n");
15777 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
15781 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
15783 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
15785 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
15786 DRM_ERROR("failed to write control word\n");
15793 struct intel_display_error_state
{
15795 u32 power_well_driver
;
15797 int num_transcoders
;
15799 struct intel_cursor_error_state
{
15804 } cursor
[I915_MAX_PIPES
];
15806 struct intel_pipe_error_state
{
15807 bool power_domain_on
;
15810 } pipe
[I915_MAX_PIPES
];
15812 struct intel_plane_error_state
{
15820 } plane
[I915_MAX_PIPES
];
15822 struct intel_transcoder_error_state
{
15823 bool power_domain_on
;
15824 enum transcoder cpu_transcoder
;
15837 struct intel_display_error_state
*
15838 intel_display_capture_error_state(struct drm_device
*dev
)
15840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15841 struct intel_display_error_state
*error
;
15842 int transcoders
[] = {
15850 if (INTEL_INFO(dev
)->num_pipes
== 0)
15853 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
15857 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15858 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
15860 for_each_pipe(dev_priv
, i
) {
15861 error
->pipe
[i
].power_domain_on
=
15862 __intel_display_power_is_enabled(dev_priv
,
15863 POWER_DOMAIN_PIPE(i
));
15864 if (!error
->pipe
[i
].power_domain_on
)
15867 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
15868 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
15869 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
15871 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
15872 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
15873 if (INTEL_INFO(dev
)->gen
<= 3) {
15874 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
15875 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
15877 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15878 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
15879 if (INTEL_INFO(dev
)->gen
>= 4) {
15880 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
15881 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
15884 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
15886 if (HAS_GMCH_DISPLAY(dev
))
15887 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
15890 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
15891 if (HAS_DDI(dev_priv
->dev
))
15892 error
->num_transcoders
++; /* Account for eDP. */
15894 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15895 enum transcoder cpu_transcoder
= transcoders
[i
];
15897 error
->transcoder
[i
].power_domain_on
=
15898 __intel_display_power_is_enabled(dev_priv
,
15899 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
15900 if (!error
->transcoder
[i
].power_domain_on
)
15903 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
15905 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
15906 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
15907 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
15908 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
15909 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
15910 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
15911 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
15917 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15920 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
15921 struct drm_device
*dev
,
15922 struct intel_display_error_state
*error
)
15924 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15930 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
15931 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15932 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
15933 error
->power_well_driver
);
15934 for_each_pipe(dev_priv
, i
) {
15935 err_printf(m
, "Pipe [%d]:\n", i
);
15936 err_printf(m
, " Power: %s\n",
15937 error
->pipe
[i
].power_domain_on
? "on" : "off");
15938 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
15939 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
15941 err_printf(m
, "Plane [%d]:\n", i
);
15942 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
15943 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
15944 if (INTEL_INFO(dev
)->gen
<= 3) {
15945 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
15946 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
15948 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15949 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
15950 if (INTEL_INFO(dev
)->gen
>= 4) {
15951 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
15952 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
15955 err_printf(m
, "Cursor [%d]:\n", i
);
15956 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
15957 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
15958 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
15961 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15962 err_printf(m
, "CPU transcoder: %c\n",
15963 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
15964 err_printf(m
, " Power: %s\n",
15965 error
->transcoder
[i
].power_domain_on
? "on" : "off");
15966 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
15967 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
15968 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
15969 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
15970 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
15971 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
15972 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
15976 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
15978 struct intel_crtc
*crtc
;
15980 for_each_intel_crtc(dev
, crtc
) {
15981 struct intel_unpin_work
*work
;
15983 spin_lock_irq(&dev
->event_lock
);
15985 work
= crtc
->unpin_work
;
15987 if (work
&& work
->event
&&
15988 work
->event
->base
.file_priv
== file
) {
15989 kfree(work
->event
);
15990 work
->event
= NULL
;
15993 spin_unlock_irq(&dev
->event_lock
);