projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'virtio-gpu-drm-next' of git://git.kraxel.org/linux into drm-next
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_set_mode(struct drm_crtc *crtc,
90 struct drm_atomic_state *state);
91 static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
100 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
101 static void haswell_set_pipeconf(struct drm_crtc *crtc);
102 static void intel_set_pipe_csc(struct drm_crtc *crtc);
103 static void vlv_prepare_pll(struct intel_crtc *crtc,
104 const struct intel_crtc_state *pipe_config);
105 static void chv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
109 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
111 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
113 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
115
116 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117 {
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122 }
123
124 typedef struct {
125 int min, max;
126 } intel_range_t;
127
128 typedef struct {
129 int dot_limit;
130 int p2_slow, p2_fast;
131 } intel_p2_t;
132
133 typedef struct intel_limit intel_limit_t;
134 struct intel_limit {
135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
137 };
138
139 int
140 intel_pch_rawclk(struct drm_device *dev)
141 {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147 }
148
149 static inline u32 /* units of 100MHz */
150 intel_fdi_link_freq(struct drm_device *dev)
151 {
152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
157 }
158
159 static const intel_limit_t intel_limits_i8xx_dac = {
160 .dot = { .min = 25000, .max = 350000 },
161 .vco = { .min = 908000, .max = 1512000 },
162 .n = { .min = 2, .max = 16 },
163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
170 };
171
172 static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
174 .vco = { .min = 908000, .max = 1512000 },
175 .n = { .min = 2, .max = 16 },
176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183 };
184
185 static const intel_limit_t intel_limits_i8xx_lvds = {
186 .dot = { .min = 25000, .max = 350000 },
187 .vco = { .min = 908000, .max = 1512000 },
188 .n = { .min = 2, .max = 16 },
189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
196 };
197
198 static const intel_limit_t intel_limits_i9xx_sdvo = {
199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
209 };
210
211 static const intel_limit_t intel_limits_i9xx_lvds = {
212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
222 };
223
224
225 static const intel_limit_t intel_limits_g4x_sdvo = {
226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
237 },
238 };
239
240 static const intel_limit_t intel_limits_g4x_hdmi = {
241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
251 };
252
253 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
264 },
265 };
266
267 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
278 },
279 };
280
281 static const intel_limit_t intel_limits_pineview_sdvo = {
282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
284 /* Pineview's Ncounter is a ring counter */
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 /* Pineview only has one combined m divider, which we treat as m2. */
288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
294 };
295
296 static const intel_limit_t intel_limits_pineview_lvds = {
297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
307 };
308
309 /* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
314 static const intel_limit_t intel_limits_ironlake_dac = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
325 };
326
327 static const intel_limit_t intel_limits_ironlake_single_lvds = {
328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
338 };
339
340 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
351 };
352
353 /* LVDS 100mhz refclk limits. */
354 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
362 .p1 = { .min = 2, .max = 8 },
363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
365 };
366
367 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
375 .p1 = { .min = 2, .max = 6 },
376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
378 };
379
380 static const intel_limit_t intel_limits_vlv = {
381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
388 .vco = { .min = 4000000, .max = 6000000 },
389 .n = { .min = 1, .max = 7 },
390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
392 .p1 = { .min = 2, .max = 3 },
393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
394 };
395
396 static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
404 .vco = { .min = 4800000, .max = 6480000 },
405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410 };
411
412 static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422 };
423
424 static void vlv_clock(int refclk, intel_clock_t *clock)
425 {
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
432 }
433
434 /**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
437 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
438 {
439 struct drm_device *dev = crtc->base.dev;
440 struct intel_encoder *encoder;
441
442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
443 if (encoder->type == type)
444 return true;
445
446 return false;
447 }
448
449 /**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
455 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
457 {
458 struct drm_atomic_state *state = crtc_state->base.state;
459 struct drm_connector *connector;
460 struct drm_connector_state *connector_state;
461 struct intel_encoder *encoder;
462 int i, num_connectors = 0;
463
464 for_each_connector_in_state(state, connector, connector_state, i) {
465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
469
470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
472 return true;
473 }
474
475 WARN_ON(num_connectors == 0);
476
477 return false;
478 }
479
480 static const intel_limit_t *
481 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
482 {
483 struct drm_device *dev = crtc_state->base.crtc->dev;
484 const intel_limit_t *limit;
485
486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
487 if (intel_is_dual_link_lvds(dev)) {
488 if (refclk == 100000)
489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
493 if (refclk == 100000)
494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
498 } else
499 limit = &intel_limits_ironlake_dac;
500
501 return limit;
502 }
503
504 static const intel_limit_t *
505 intel_g4x_limit(struct intel_crtc_state *crtc_state)
506 {
507 struct drm_device *dev = crtc_state->base.crtc->dev;
508 const intel_limit_t *limit;
509
510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
511 if (intel_is_dual_link_lvds(dev))
512 limit = &intel_limits_g4x_dual_channel_lvds;
513 else
514 limit = &intel_limits_g4x_single_channel_lvds;
515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
517 limit = &intel_limits_g4x_hdmi;
518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
519 limit = &intel_limits_g4x_sdvo;
520 } else /* The option is for other outputs */
521 limit = &intel_limits_i9xx_sdvo;
522
523 return limit;
524 }
525
526 static const intel_limit_t *
527 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
528 {
529 struct drm_device *dev = crtc_state->base.crtc->dev;
530 const intel_limit_t *limit;
531
532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
535 limit = intel_ironlake_limit(crtc_state, refclk);
536 else if (IS_G4X(dev)) {
537 limit = intel_g4x_limit(crtc_state);
538 } else if (IS_PINEVIEW(dev)) {
539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
540 limit = &intel_limits_pineview_lvds;
541 else
542 limit = &intel_limits_pineview_sdvo;
543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
545 } else if (IS_VALLEYVIEW(dev)) {
546 limit = &intel_limits_vlv;
547 } else if (!IS_GEN2(dev)) {
548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
552 } else {
553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
554 limit = &intel_limits_i8xx_lvds;
555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
556 limit = &intel_limits_i8xx_dvo;
557 else
558 limit = &intel_limits_i8xx_dac;
559 }
560 return limit;
561 }
562
563 /* m1 is reserved as 0 in Pineview, n is a ring counter */
564 static void pineview_clock(int refclk, intel_clock_t *clock)
565 {
566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
572 }
573
574 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575 {
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577 }
578
579 static void i9xx_clock(int refclk, intel_clock_t *clock)
580 {
581 clock->m = i9xx_dpll_compute_m(clock);
582 clock->p = clock->p1 * clock->p2;
583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
587 }
588
589 static void chv_clock(int refclk, intel_clock_t *clock)
590 {
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598 }
599
600 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
601 /**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
606 static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
609 {
610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
613 INTELPllInvalid("p1 out of range\n");
614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
615 INTELPllInvalid("m2 out of range\n");
616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
617 INTELPllInvalid("m1 out of range\n");
618
619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
631 INTELPllInvalid("vco out of range\n");
632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
636 INTELPllInvalid("dot out of range\n");
637
638 return true;
639 }
640
641 static bool
642 i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
646 {
647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
648 struct drm_device *dev = crtc->base.dev;
649 intel_clock_t clock;
650 int err = target;
651
652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
653 /*
654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
657 */
658 if (intel_is_dual_link_lvds(dev))
659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
669 memset(best_clock, 0, sizeof(*best_clock));
670
671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
675 if (clock.m2 >= clock.m1)
676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
681 int this_err;
682
683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702 }
703
704 static bool
705 pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
709 {
710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
711 struct drm_device *dev = crtc->base.dev;
712 intel_clock_t clock;
713 int err = target;
714
715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
716 /*
717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
720 */
721 if (intel_is_dual_link_lvds(dev))
722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733
734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
742 int this_err;
743
744 pineview_clock(refclk, &clock);
745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
747 continue;
748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763 }
764
765 static bool
766 g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
770 {
771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
772 struct drm_device *dev = crtc->base.dev;
773 intel_clock_t clock;
774 int max_n;
775 bool found;
776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
778 found = false;
779
780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
781 if (intel_is_dual_link_lvds(dev))
782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 /* based on hardware requirement, prefere larger m1,m2 */
797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
805 i9xx_clock(refclk, &clock);
806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
808 continue;
809
810 this_err = abs(clock.dot - target);
811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
821 return found;
822 }
823
824 /*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833 {
834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862 }
863
864 static bool
865 vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
869 {
870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
871 struct drm_device *dev = crtc->base.dev;
872 intel_clock_t clock;
873 unsigned int bestppm = 1000000;
874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
876 bool found = false;
877
878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
881
882 /* based on hardware requirement, prefer smaller n to precision */
883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
887 clock.p = clock.p1 * clock.p2;
888 /* based on hardware requirement, prefer bigger m1,m2 values */
889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
890 unsigned int ppm;
891
892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
896
897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
899 continue;
900
901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
906
907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
910 }
911 }
912 }
913 }
914
915 return found;
916 }
917
918 static bool
919 chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923 {
924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
925 struct drm_device *dev = crtc->base.dev;
926 unsigned int best_error_ppm;
927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
932 best_error_ppm = 1000000;
933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
946 unsigned int error_ppm;
947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
970 }
971 }
972
973 return found;
974 }
975
976 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978 {
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983 }
984
985 bool intel_crtc_active(struct drm_crtc *crtc)
986 {
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
992 * We can ditch the adjusted_mode.crtc_clock check as soon
993 * as Haswell has gained clock readout/fastboot support.
994 *
995 * We can ditch the crtc->primary->fb check as soon as we can
996 * properly reconstruct framebuffers.
997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
1001 */
1002 return intel_crtc->active && crtc->primary->state->fb &&
1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
1004 }
1005
1006 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008 {
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
1012 return intel_crtc->config->cpu_transcoder;
1013 }
1014
1015 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016 {
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032 }
1033
1034 /*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
1036 * @crtc: crtc whose pipe to wait for
1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
1048 *
1049 */
1050 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1051 {
1052 struct drm_device *dev = crtc->base.dev;
1053 struct drm_i915_private *dev_priv = dev->dev_private;
1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1055 enum pipe pipe = crtc->pipe;
1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
1058 int reg = PIPECONF(cpu_transcoder);
1059
1060 /* Wait for the Pipe State to go off */
1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
1063 WARN(1, "pipe_off wait timed out\n");
1064 } else {
1065 /* Wait for the display line to settle */
1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1067 WARN(1, "pipe_off wait timed out\n");
1068 }
1069 }
1070
1071 /*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080 {
1081 u32 bit;
1082
1083 if (HAS_PCH_IBX(dev_priv->dev)) {
1084 switch (port->port) {
1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
1098 switch (port->port) {
1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114 }
1115
1116 static const char *state_string(bool enabled)
1117 {
1118 return enabled ? "on" : "off";
1119 }
1120
1121 /* Only for pre-ILK configs */
1122 void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
1124 {
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
1132 I915_STATE_WARN(cur_state != state,
1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135 }
1136
1137 /* XXX: the dsi pll is shared between MIPI DSI ports */
1138 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139 {
1140 u32 val;
1141 bool cur_state;
1142
1143 mutex_lock(&dev_priv->sb_lock);
1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1145 mutex_unlock(&dev_priv->sb_lock);
1146
1147 cur_state = val & DSI_PLL_VCO_EN;
1148 I915_STATE_WARN(cur_state != state,
1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151 }
1152 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
1155 struct intel_shared_dpll *
1156 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157 {
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
1160 if (crtc->config->shared_dpll < 0)
1161 return NULL;
1162
1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1164 }
1165
1166 /* For ILK+ */
1167 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
1170 {
1171 bool cur_state;
1172 struct intel_dpll_hw_state hw_state;
1173
1174 if (WARN (!pll,
1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
1176 return;
1177
1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1179 I915_STATE_WARN(cur_state != state,
1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
1182 }
1183
1184 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186 {
1187 int reg;
1188 u32 val;
1189 bool cur_state;
1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
1192
1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
1203 I915_STATE_WARN(cur_state != state,
1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206 }
1207 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212 {
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
1220 I915_STATE_WARN(cur_state != state,
1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223 }
1224 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229 {
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1235 return;
1236
1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1238 if (HAS_DDI(dev_priv->dev))
1239 return;
1240
1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1244 }
1245
1246 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
1248 {
1249 int reg;
1250 u32 val;
1251 bool cur_state;
1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1256 I915_STATE_WARN(cur_state != state,
1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
1259 }
1260
1261 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
1263 {
1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
1268 bool locked = true;
1269
1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
1276 pp_reg = PCH_PP_CONTROL;
1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
1287 } else {
1288 pp_reg = PP_CONTROL;
1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1296 locked = false;
1297
1298 I915_STATE_WARN(panel_pipe == pipe && locked,
1299 "panel assertion failure, pipe %c regs locked\n",
1300 pipe_name(pipe));
1301 }
1302
1303 static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305 {
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
1309 if (IS_845G(dev) || IS_I865G(dev))
1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1311 else
1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1313
1314 I915_STATE_WARN(cur_state != state,
1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317 }
1318 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
1321 void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
1323 {
1324 int reg;
1325 u32 val;
1326 bool cur_state;
1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
1329
1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1333 state = true;
1334
1335 if (!intel_display_power_is_enabled(dev_priv,
1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
1344 I915_STATE_WARN(cur_state != state,
1345 "pipe %c assertion failure (expected %s, current %s)\n",
1346 pipe_name(pipe), state_string(state), state_string(cur_state));
1347 }
1348
1349 static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
1351 {
1352 int reg;
1353 u32 val;
1354 bool cur_state;
1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1359 I915_STATE_WARN(cur_state != state,
1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
1362 }
1363
1364 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
1367 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369 {
1370 struct drm_device *dev = dev_priv->dev;
1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
1382 return;
1383 }
1384
1385 /* Need to check both planes against the pipe */
1386 for_each_pipe(dev_priv, i) {
1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
1394 }
1395 }
1396
1397 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399 {
1400 struct drm_device *dev = dev_priv->dev;
1401 int reg, sprite;
1402 u32 val;
1403
1404 if (INTEL_INFO(dev)->gen >= 9) {
1405 for_each_sprite(dev_priv, pipe, sprite) {
1406 val = I915_READ(PLANE_CTL(pipe, sprite));
1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
1412 for_each_sprite(dev_priv, pipe, sprite) {
1413 reg = SPCNTR(pipe, sprite);
1414 val = I915_READ(reg);
1415 I915_STATE_WARN(val & SP_ENABLE,
1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417 sprite_name(pipe, sprite), pipe_name(pipe));
1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
1421 val = I915_READ(reg);
1422 I915_STATE_WARN(val & SPRITE_ENABLE,
1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
1427 val = I915_READ(reg);
1428 I915_STATE_WARN(val & DVS_ENABLE,
1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1430 plane_name(pipe), pipe_name(pipe));
1431 }
1432 }
1433
1434 static void assert_vblank_disabled(struct drm_crtc *crtc)
1435 {
1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1437 drm_crtc_vblank_put(crtc);
1438 }
1439
1440 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1441 {
1442 u32 val;
1443 bool enabled;
1444
1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1446
1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1451 }
1452
1453 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
1455 {
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
1460 reg = PCH_TRANSCONF(pipe);
1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
1463 I915_STATE_WARN(enabled,
1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
1466 }
1467
1468 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
1470 {
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487 }
1488
1489 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491 {
1492 if ((val & SDVO_ENABLE) == 0)
1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1497 return false;
1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1501 } else {
1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1503 return false;
1504 }
1505 return true;
1506 }
1507
1508 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510 {
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522 }
1523
1524 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526 {
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537 }
1538
1539 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1540 enum pipe pipe, int reg, u32 port_sel)
1541 {
1542 u32 val = I915_READ(reg);
1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1545 reg, pipe_name(pipe));
1546
1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1548 && (val & DP_PIPEB_SELECT),
1549 "IBX PCH dp port still using transcoder B\n");
1550 }
1551
1552 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554 {
1555 u32 val = I915_READ(reg);
1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1558 reg, pipe_name(pipe));
1559
1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1561 && (val & SDVO_PIPE_B_SELECT),
1562 "IBX PCH hdmi port still using transcoder B\n");
1563 }
1564
1565 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567 {
1568 int reg;
1569 u32 val;
1570
1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
1579 pipe_name(pipe));
1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1585 pipe_name(pipe));
1586
1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1590 }
1591
1592 static void intel_init_dpio(struct drm_device *dev)
1593 {
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
1610 }
1611
1612 static void vlv_enable_pll(struct intel_crtc *crtc,
1613 const struct intel_crtc_state *pipe_config)
1614 {
1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
1619
1620 assert_pipe_disabled(dev_priv, crtc->pipe);
1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
1626 if (IS_MOBILE(dev_priv->dev))
1627 assert_panel_unlocked(dev_priv, crtc->pipe);
1628
1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1637 POSTING_READ(DPLL_MD(crtc->pipe));
1638
1639 /* We do this three times for luck */
1640 I915_WRITE(reg, dpll);
1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
1643 I915_WRITE(reg, dpll);
1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 }
1650
1651 static void chv_enable_pll(struct intel_crtc *crtc,
1652 const struct intel_crtc_state *pipe_config)
1653 {
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
1664 mutex_lock(&dev_priv->sb_lock);
1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
1671 mutex_unlock(&dev_priv->sb_lock);
1672
1673 /*
1674 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1675 */
1676 udelay(1);
1677
1678 /* Enable PLL */
1679 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1680
1681 /* Check PLL is locked */
1682 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1683 DRM_ERROR("PLL %d failed to lock\n", pipe);
1684
1685 /* not sure when this should be written */
1686 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1687 POSTING_READ(DPLL_MD(pipe));
1688 }
1689
1690 static int intel_num_dvo_pipes(struct drm_device *dev)
1691 {
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1698
1699 return count;
1700 }
1701
1702 static void i9xx_enable_pll(struct intel_crtc *crtc)
1703 {
1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
1708
1709 assert_pipe_disabled(dev_priv, crtc->pipe);
1710
1711 /* No really, not for ILK+ */
1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1713
1714 /* PLL is protected by panel, make sure we can write it */
1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
1717
1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
1737 crtc->config->dpll_hw_state.dpll_md);
1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
1746
1747 /* We do this three times for luck */
1748 I915_WRITE(reg, dpll);
1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
1751 I915_WRITE(reg, dpll);
1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
1754 I915_WRITE(reg, dpll);
1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757 }
1758
1759 /**
1760 * i9xx_disable_pll - disable a PLL
1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1768 static void i9xx_disable_pll(struct intel_crtc *crtc)
1769 {
1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
1794 }
1795
1796 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797 {
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
1807 if (pipe == PIPE_B)
1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
1811
1812 }
1813
1814 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815 {
1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1817 u32 val;
1818
1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
1821
1822 /* Set PLL en = 0 */
1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
1828
1829 mutex_lock(&dev_priv->sb_lock);
1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
1847 mutex_unlock(&dev_priv->sb_lock);
1848 }
1849
1850 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
1853 {
1854 u32 port_mask;
1855 int dpll_reg;
1856
1857 switch (dport->port) {
1858 case PORT_B:
1859 port_mask = DPLL_PORTB_READY_MASK;
1860 dpll_reg = DPLL(0);
1861 break;
1862 case PORT_C:
1863 port_mask = DPLL_PORTC_READY_MASK;
1864 dpll_reg = DPLL(0);
1865 expected_mask <<= 4;
1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
1870 break;
1871 default:
1872 BUG();
1873 }
1874
1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1878 }
1879
1880 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881 {
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
1886 if (WARN_ON(pll == NULL))
1887 return;
1888
1889 WARN_ON(!pll->config.crtc_mask);
1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897 }
1898
1899 /**
1900 * intel_enable_shared_dpll - enable PCH PLL
1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
1907 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1908 {
1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1912
1913 if (WARN_ON(pll == NULL))
1914 return;
1915
1916 if (WARN_ON(pll->config.crtc_mask == 0))
1917 return;
1918
1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1920 pll->name, pll->active, pll->on,
1921 crtc->base.base.id);
1922
1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
1925 assert_shared_dpll_enabled(dev_priv, pll);
1926 return;
1927 }
1928 WARN_ON(pll->on);
1929
1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1933 pll->enable(dev_priv, pll);
1934 pll->on = true;
1935 }
1936
1937 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1938 {
1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1942
1943 /* PCH only available on ILK+ */
1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
1945 if (WARN_ON(pll == NULL))
1946 return;
1947
1948 if (WARN_ON(pll->config.crtc_mask == 0))
1949 return;
1950
1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
1953 crtc->base.base.id);
1954
1955 if (WARN_ON(pll->active == 0)) {
1956 assert_shared_dpll_disabled(dev_priv, pll);
1957 return;
1958 }
1959
1960 assert_shared_dpll_enabled(dev_priv, pll);
1961 WARN_ON(!pll->on);
1962 if (--pll->active)
1963 return;
1964
1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1966 pll->disable(dev_priv, pll);
1967 pll->on = false;
1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1970 }
1971
1972 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
1974 {
1975 struct drm_device *dev = dev_priv->dev;
1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978 uint32_t reg, val, pipeconf_val;
1979
1980 /* PCH only available on ILK+ */
1981 BUG_ON(!HAS_PCH_SPLIT(dev));
1982
1983 /* Make sure PCH DPLL is enabled */
1984 assert_shared_dpll_enabled(dev_priv,
1985 intel_crtc_to_shared_dpll(intel_crtc));
1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
1998 }
1999
2000 reg = PCH_TRANSCONF(pipe);
2001 val = I915_READ(reg);
2002 pipeconf_val = I915_READ(PIPECONF(pipe));
2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
2011 }
2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2015 if (HAS_PCH_IBX(dev_priv->dev) &&
2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2026 }
2027
2028 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2029 enum transcoder cpu_transcoder)
2030 {
2031 u32 val, pipeconf_val;
2032
2033 /* PCH only available on ILK+ */
2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2035
2036 /* FDI must be feeding us bits for PCH ports */
2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2039
2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
2045 val = TRANS_ENABLE;
2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2047
2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
2050 val |= TRANS_INTERLACED;
2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2056 DRM_ERROR("Failed to enable PCH transcoder\n");
2057 }
2058
2059 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
2061 {
2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
2072 reg = PCH_TRANSCONF(pipe);
2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
2087 }
2088
2089 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2090 {
2091 u32 val;
2092
2093 val = I915_READ(LPT_TRANSCONF);
2094 val &= ~TRANS_ENABLE;
2095 I915_WRITE(LPT_TRANSCONF, val);
2096 /* wait for PCH transcoder off, transcoder state */
2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2098 DRM_ERROR("Failed to disable PCH transcoder\n");
2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2103 I915_WRITE(_TRANSA_CHICKEN2, val);
2104 }
2105
2106 /**
2107 * intel_enable_pipe - enable a pipe, asserting requirements
2108 * @crtc: crtc responsible for the pipe
2109 *
2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2112 */
2113 static void intel_enable_pipe(struct intel_crtc *crtc)
2114 {
2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
2120 enum pipe pch_transcoder;
2121 int reg;
2122 u32 val;
2123
2124 assert_planes_disabled(dev_priv, pipe);
2125 assert_cursor_disabled(dev_priv, pipe);
2126 assert_sprites_disabled(dev_priv, pipe);
2127
2128 if (HAS_PCH_LPT(dev_priv->dev))
2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
2143 else {
2144 if (crtc->config->has_pch_encoder) {
2145 /* if driving the PCH, we need FDI enabled */
2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
2152
2153 reg = PIPECONF(cpu_transcoder);
2154 val = I915_READ(reg);
2155 if (val & PIPECONF_ENABLE) {
2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2158 return;
2159 }
2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
2162 POSTING_READ(reg);
2163 }
2164
2165 /**
2166 * intel_disable_pipe - disable a pipe, asserting requirements
2167 * @crtc: crtc whose pipes is to be disabled
2168 *
2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
2175 static void intel_disable_pipe(struct intel_crtc *crtc)
2176 {
2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2179 enum pipe pipe = crtc->pipe;
2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
2188 assert_cursor_disabled(dev_priv, pipe);
2189 assert_sprites_disabled(dev_priv, pipe);
2190
2191 reg = PIPECONF(cpu_transcoder);
2192 val = I915_READ(reg);
2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
2200 if (crtc->config->double_wide)
2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
2211 }
2212
2213 /**
2214 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2215 * @plane: plane to be enabled
2216 * @crtc: crtc for the plane
2217 *
2218 * Enable @plane on @crtc, making sure that the pipe is running first.
2219 */
2220 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2221 struct drm_crtc *crtc)
2222 {
2223 struct drm_device *dev = plane->dev;
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2226
2227 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2228 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2229 to_intel_plane_state(plane->state)->visible = true;
2230
2231 dev_priv->display.update_primary_plane(crtc, plane->fb,
2232 crtc->x, crtc->y);
2233 }
2234
2235 static bool need_vtd_wa(struct drm_device *dev)
2236 {
2237 #ifdef CONFIG_INTEL_IOMMU
2238 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2239 return true;
2240 #endif
2241 return false;
2242 }
2243
2244 unsigned int
2245 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2246 uint64_t fb_format_modifier)
2247 {
2248 unsigned int tile_height;
2249 uint32_t pixel_bytes;
2250
2251 switch (fb_format_modifier) {
2252 case DRM_FORMAT_MOD_NONE:
2253 tile_height = 1;
2254 break;
2255 case I915_FORMAT_MOD_X_TILED:
2256 tile_height = IS_GEN2(dev) ? 16 : 8;
2257 break;
2258 case I915_FORMAT_MOD_Y_TILED:
2259 tile_height = 32;
2260 break;
2261 case I915_FORMAT_MOD_Yf_TILED:
2262 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2263 switch (pixel_bytes) {
2264 default:
2265 case 1:
2266 tile_height = 64;
2267 break;
2268 case 2:
2269 case 4:
2270 tile_height = 32;
2271 break;
2272 case 8:
2273 tile_height = 16;
2274 break;
2275 case 16:
2276 WARN_ONCE(1,
2277 "128-bit pixels are not supported for display!");
2278 tile_height = 16;
2279 break;
2280 }
2281 break;
2282 default:
2283 MISSING_CASE(fb_format_modifier);
2284 tile_height = 1;
2285 break;
2286 }
2287
2288 return tile_height;
2289 }
2290
2291 unsigned int
2292 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2293 uint32_t pixel_format, uint64_t fb_format_modifier)
2294 {
2295 return ALIGN(height, intel_tile_height(dev, pixel_format,
2296 fb_format_modifier));
2297 }
2298
2299 static int
2300 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2301 const struct drm_plane_state *plane_state)
2302 {
2303 struct intel_rotation_info *info = &view->rotation_info;
2304
2305 *view = i915_ggtt_view_normal;
2306
2307 if (!plane_state)
2308 return 0;
2309
2310 if (!intel_rotation_90_or_270(plane_state->rotation))
2311 return 0;
2312
2313 *view = i915_ggtt_view_rotated;
2314
2315 info->height = fb->height;
2316 info->pixel_format = fb->pixel_format;
2317 info->pitch = fb->pitches[0];
2318 info->fb_modifier = fb->modifier[0];
2319
2320 return 0;
2321 }
2322
2323 int
2324 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2325 struct drm_framebuffer *fb,
2326 const struct drm_plane_state *plane_state,
2327 struct intel_engine_cs *pipelined)
2328 {
2329 struct drm_device *dev = fb->dev;
2330 struct drm_i915_private *dev_priv = dev->dev_private;
2331 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2332 struct i915_ggtt_view view;
2333 u32 alignment;
2334 int ret;
2335
2336 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2337
2338 switch (fb->modifier[0]) {
2339 case DRM_FORMAT_MOD_NONE:
2340 if (INTEL_INFO(dev)->gen >= 9)
2341 alignment = 256 * 1024;
2342 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2343 alignment = 128 * 1024;
2344 else if (INTEL_INFO(dev)->gen >= 4)
2345 alignment = 4 * 1024;
2346 else
2347 alignment = 64 * 1024;
2348 break;
2349 case I915_FORMAT_MOD_X_TILED:
2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else {
2353 /* pin() will align the object as required by fence */
2354 alignment = 0;
2355 }
2356 break;
2357 case I915_FORMAT_MOD_Y_TILED:
2358 case I915_FORMAT_MOD_Yf_TILED:
2359 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2361 return -EINVAL;
2362 alignment = 1 * 1024 * 1024;
2363 break;
2364 default:
2365 MISSING_CASE(fb->modifier[0]);
2366 return -EINVAL;
2367 }
2368
2369 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370 if (ret)
2371 return ret;
2372
2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2376 * the VT-d warning.
2377 */
2378 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379 alignment = 256 * 1024;
2380
2381 /*
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2387 */
2388 intel_runtime_pm_get(dev_priv);
2389
2390 dev_priv->mm.interruptible = false;
2391 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2392 &view);
2393 if (ret)
2394 goto err_interruptible;
2395
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2400 */
2401 ret = i915_gem_object_get_fence(obj);
2402 if (ret)
2403 goto err_unpin;
2404
2405 i915_gem_object_pin_fence(obj);
2406
2407 dev_priv->mm.interruptible = true;
2408 intel_runtime_pm_put(dev_priv);
2409 return 0;
2410
2411 err_unpin:
2412 i915_gem_object_unpin_from_display_plane(obj, &view);
2413 err_interruptible:
2414 dev_priv->mm.interruptible = true;
2415 intel_runtime_pm_put(dev_priv);
2416 return ret;
2417 }
2418
2419 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2420 const struct drm_plane_state *plane_state)
2421 {
2422 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2423 struct i915_ggtt_view view;
2424 int ret;
2425
2426 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2427
2428 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2429 WARN_ONCE(ret, "Couldn't get view from plane state!");
2430
2431 i915_gem_object_unpin_fence(obj);
2432 i915_gem_object_unpin_from_display_plane(obj, &view);
2433 }
2434
2435 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2436 * is assumed to be a power-of-two. */
2437 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2438 unsigned int tiling_mode,
2439 unsigned int cpp,
2440 unsigned int pitch)
2441 {
2442 if (tiling_mode != I915_TILING_NONE) {
2443 unsigned int tile_rows, tiles;
2444
2445 tile_rows = *y / 8;
2446 *y %= 8;
2447
2448 tiles = *x / (512/cpp);
2449 *x %= 512/cpp;
2450
2451 return tile_rows * pitch * 8 + tiles * 4096;
2452 } else {
2453 unsigned int offset;
2454
2455 offset = *y * pitch + *x * cpp;
2456 *y = 0;
2457 *x = (offset & 4095) / cpp;
2458 return offset & -4096;
2459 }
2460 }
2461
2462 static int i9xx_format_to_fourcc(int format)
2463 {
2464 switch (format) {
2465 case DISPPLANE_8BPP:
2466 return DRM_FORMAT_C8;
2467 case DISPPLANE_BGRX555:
2468 return DRM_FORMAT_XRGB1555;
2469 case DISPPLANE_BGRX565:
2470 return DRM_FORMAT_RGB565;
2471 default:
2472 case DISPPLANE_BGRX888:
2473 return DRM_FORMAT_XRGB8888;
2474 case DISPPLANE_RGBX888:
2475 return DRM_FORMAT_XBGR8888;
2476 case DISPPLANE_BGRX101010:
2477 return DRM_FORMAT_XRGB2101010;
2478 case DISPPLANE_RGBX101010:
2479 return DRM_FORMAT_XBGR2101010;
2480 }
2481 }
2482
2483 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2484 {
2485 switch (format) {
2486 case PLANE_CTL_FORMAT_RGB_565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case PLANE_CTL_FORMAT_XRGB_8888:
2490 if (rgb_order) {
2491 if (alpha)
2492 return DRM_FORMAT_ABGR8888;
2493 else
2494 return DRM_FORMAT_XBGR8888;
2495 } else {
2496 if (alpha)
2497 return DRM_FORMAT_ARGB8888;
2498 else
2499 return DRM_FORMAT_XRGB8888;
2500 }
2501 case PLANE_CTL_FORMAT_XRGB_2101010:
2502 if (rgb_order)
2503 return DRM_FORMAT_XBGR2101010;
2504 else
2505 return DRM_FORMAT_XRGB2101010;
2506 }
2507 }
2508
2509 static bool
2510 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2511 struct intel_initial_plane_config *plane_config)
2512 {
2513 struct drm_device *dev = crtc->base.dev;
2514 struct drm_i915_gem_object *obj = NULL;
2515 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2516 struct drm_framebuffer *fb = &plane_config->fb->base;
2517 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 PAGE_SIZE);
2520
2521 size_aligned -= base_aligned;
2522
2523 if (plane_config->size == 0)
2524 return false;
2525
2526 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2527 base_aligned,
2528 base_aligned,
2529 size_aligned);
2530 if (!obj)
2531 return false;
2532
2533 obj->tiling_mode = plane_config->tiling;
2534 if (obj->tiling_mode == I915_TILING_X)
2535 obj->stride = fb->pitches[0];
2536
2537 mode_cmd.pixel_format = fb->pixel_format;
2538 mode_cmd.width = fb->width;
2539 mode_cmd.height = fb->height;
2540 mode_cmd.pitches[0] = fb->pitches[0];
2541 mode_cmd.modifier[0] = fb->modifier[0];
2542 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2543
2544 mutex_lock(&dev->struct_mutex);
2545 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2546 &mode_cmd, obj)) {
2547 DRM_DEBUG_KMS("intel fb init failed\n");
2548 goto out_unref_obj;
2549 }
2550 mutex_unlock(&dev->struct_mutex);
2551
2552 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2553 return true;
2554
2555 out_unref_obj:
2556 drm_gem_object_unreference(&obj->base);
2557 mutex_unlock(&dev->struct_mutex);
2558 return false;
2559 }
2560
2561 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2562 static void
2563 update_state_fb(struct drm_plane *plane)
2564 {
2565 if (plane->fb == plane->state->fb)
2566 return;
2567
2568 if (plane->state->fb)
2569 drm_framebuffer_unreference(plane->state->fb);
2570 plane->state->fb = plane->fb;
2571 if (plane->state->fb)
2572 drm_framebuffer_reference(plane->state->fb);
2573 }
2574
2575 static void
2576 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2577 struct intel_initial_plane_config *plane_config)
2578 {
2579 struct drm_device *dev = intel_crtc->base.dev;
2580 struct drm_i915_private *dev_priv = dev->dev_private;
2581 struct drm_crtc *c;
2582 struct intel_crtc *i;
2583 struct drm_i915_gem_object *obj;
2584 struct drm_plane *primary = intel_crtc->base.primary;
2585 struct drm_framebuffer *fb;
2586
2587 if (!plane_config->fb)
2588 return;
2589
2590 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2591 fb = &plane_config->fb->base;
2592 goto valid_fb;
2593 }
2594
2595 kfree(plane_config->fb);
2596
2597 /*
2598 * Failed to alloc the obj, check to see if we should share
2599 * an fb with another CRTC instead
2600 */
2601 for_each_crtc(dev, c) {
2602 i = to_intel_crtc(c);
2603
2604 if (c == &intel_crtc->base)
2605 continue;
2606
2607 if (!i->active)
2608 continue;
2609
2610 fb = c->primary->fb;
2611 if (!fb)
2612 continue;
2613
2614 obj = intel_fb_obj(fb);
2615 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2616 drm_framebuffer_reference(fb);
2617 goto valid_fb;
2618 }
2619 }
2620
2621 return;
2622
2623 valid_fb:
2624 obj = intel_fb_obj(fb);
2625 if (obj->tiling_mode != I915_TILING_NONE)
2626 dev_priv->preserve_bios_swizzle = true;
2627
2628 primary->fb = fb;
2629 primary->state->crtc = &intel_crtc->base;
2630 primary->crtc = &intel_crtc->base;
2631 update_state_fb(primary);
2632 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2633 }
2634
2635 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2636 struct drm_framebuffer *fb,
2637 int x, int y)
2638 {
2639 struct drm_device *dev = crtc->dev;
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2642 struct drm_plane *primary = crtc->primary;
2643 bool visible = to_intel_plane_state(primary->state)->visible;
2644 struct drm_i915_gem_object *obj;
2645 int plane = intel_crtc->plane;
2646 unsigned long linear_offset;
2647 u32 dspcntr;
2648 u32 reg = DSPCNTR(plane);
2649 int pixel_size;
2650
2651 if (!visible || !fb) {
2652 I915_WRITE(reg, 0);
2653 if (INTEL_INFO(dev)->gen >= 4)
2654 I915_WRITE(DSPSURF(plane), 0);
2655 else
2656 I915_WRITE(DSPADDR(plane), 0);
2657 POSTING_READ(reg);
2658 return;
2659 }
2660
2661 obj = intel_fb_obj(fb);
2662 if (WARN_ON(obj == NULL))
2663 return;
2664
2665 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2666
2667 dspcntr = DISPPLANE_GAMMA_ENABLE;
2668
2669 dspcntr |= DISPLAY_PLANE_ENABLE;
2670
2671 if (INTEL_INFO(dev)->gen < 4) {
2672 if (intel_crtc->pipe == PIPE_B)
2673 dspcntr |= DISPPLANE_SEL_PIPE_B;
2674
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2677 */
2678 I915_WRITE(DSPSIZE(plane),
2679 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2680 (intel_crtc->config->pipe_src_w - 1));
2681 I915_WRITE(DSPPOS(plane), 0);
2682 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2683 I915_WRITE(PRIMSIZE(plane),
2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
2686 I915_WRITE(PRIMPOS(plane), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2688 }
2689
2690 switch (fb->pixel_format) {
2691 case DRM_FORMAT_C8:
2692 dspcntr |= DISPPLANE_8BPP;
2693 break;
2694 case DRM_FORMAT_XRGB1555:
2695 dspcntr |= DISPPLANE_BGRX555;
2696 break;
2697 case DRM_FORMAT_RGB565:
2698 dspcntr |= DISPPLANE_BGRX565;
2699 break;
2700 case DRM_FORMAT_XRGB8888:
2701 dspcntr |= DISPPLANE_BGRX888;
2702 break;
2703 case DRM_FORMAT_XBGR8888:
2704 dspcntr |= DISPPLANE_RGBX888;
2705 break;
2706 case DRM_FORMAT_XRGB2101010:
2707 dspcntr |= DISPPLANE_BGRX101010;
2708 break;
2709 case DRM_FORMAT_XBGR2101010:
2710 dspcntr |= DISPPLANE_RGBX101010;
2711 break;
2712 default:
2713 BUG();
2714 }
2715
2716 if (INTEL_INFO(dev)->gen >= 4 &&
2717 obj->tiling_mode != I915_TILING_NONE)
2718 dspcntr |= DISPPLANE_TILED;
2719
2720 if (IS_G4X(dev))
2721 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2722
2723 linear_offset = y * fb->pitches[0] + x * pixel_size;
2724
2725 if (INTEL_INFO(dev)->gen >= 4) {
2726 intel_crtc->dspaddr_offset =
2727 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2728 pixel_size,
2729 fb->pitches[0]);
2730 linear_offset -= intel_crtc->dspaddr_offset;
2731 } else {
2732 intel_crtc->dspaddr_offset = linear_offset;
2733 }
2734
2735 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2736 dspcntr |= DISPPLANE_ROTATE_180;
2737
2738 x += (intel_crtc->config->pipe_src_w - 1);
2739 y += (intel_crtc->config->pipe_src_h - 1);
2740
2741 /* Finding the last pixel of the last line of the display
2742 data and adding to linear_offset*/
2743 linear_offset +=
2744 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2745 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2746 }
2747
2748 I915_WRITE(reg, dspcntr);
2749
2750 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2751 if (INTEL_INFO(dev)->gen >= 4) {
2752 I915_WRITE(DSPSURF(plane),
2753 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2754 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2755 I915_WRITE(DSPLINOFF(plane), linear_offset);
2756 } else
2757 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2758 POSTING_READ(reg);
2759 }
2760
2761 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762 struct drm_framebuffer *fb,
2763 int x, int y)
2764 {
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2768 struct drm_plane *primary = crtc->primary;
2769 bool visible = to_intel_plane_state(primary->state)->visible;
2770 struct drm_i915_gem_object *obj;
2771 int plane = intel_crtc->plane;
2772 unsigned long linear_offset;
2773 u32 dspcntr;
2774 u32 reg = DSPCNTR(plane);
2775 int pixel_size;
2776
2777 if (!visible || !fb) {
2778 I915_WRITE(reg, 0);
2779 I915_WRITE(DSPSURF(plane), 0);
2780 POSTING_READ(reg);
2781 return;
2782 }
2783
2784 obj = intel_fb_obj(fb);
2785 if (WARN_ON(obj == NULL))
2786 return;
2787
2788 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2789
2790 dspcntr = DISPPLANE_GAMMA_ENABLE;
2791
2792 dspcntr |= DISPLAY_PLANE_ENABLE;
2793
2794 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2795 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2796
2797 switch (fb->pixel_format) {
2798 case DRM_FORMAT_C8:
2799 dspcntr |= DISPPLANE_8BPP;
2800 break;
2801 case DRM_FORMAT_RGB565:
2802 dspcntr |= DISPPLANE_BGRX565;
2803 break;
2804 case DRM_FORMAT_XRGB8888:
2805 dspcntr |= DISPPLANE_BGRX888;
2806 break;
2807 case DRM_FORMAT_XBGR8888:
2808 dspcntr |= DISPPLANE_RGBX888;
2809 break;
2810 case DRM_FORMAT_XRGB2101010:
2811 dspcntr |= DISPPLANE_BGRX101010;
2812 break;
2813 case DRM_FORMAT_XBGR2101010:
2814 dspcntr |= DISPPLANE_RGBX101010;
2815 break;
2816 default:
2817 BUG();
2818 }
2819
2820 if (obj->tiling_mode != I915_TILING_NONE)
2821 dspcntr |= DISPPLANE_TILED;
2822
2823 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2824 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2825
2826 linear_offset = y * fb->pitches[0] + x * pixel_size;
2827 intel_crtc->dspaddr_offset =
2828 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2829 pixel_size,
2830 fb->pitches[0]);
2831 linear_offset -= intel_crtc->dspaddr_offset;
2832 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2833 dspcntr |= DISPPLANE_ROTATE_180;
2834
2835 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2836 x += (intel_crtc->config->pipe_src_w - 1);
2837 y += (intel_crtc->config->pipe_src_h - 1);
2838
2839 /* Finding the last pixel of the last line of the display
2840 data and adding to linear_offset*/
2841 linear_offset +=
2842 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2843 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2844 }
2845 }
2846
2847 I915_WRITE(reg, dspcntr);
2848
2849 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2850 I915_WRITE(DSPSURF(plane),
2851 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2853 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2854 } else {
2855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2856 I915_WRITE(DSPLINOFF(plane), linear_offset);
2857 }
2858 POSTING_READ(reg);
2859 }
2860
2861 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2862 uint32_t pixel_format)
2863 {
2864 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2865
2866 /*
2867 * The stride is either expressed as a multiple of 64 bytes
2868 * chunks for linear buffers or in number of tiles for tiled
2869 * buffers.
2870 */
2871 switch (fb_modifier) {
2872 case DRM_FORMAT_MOD_NONE:
2873 return 64;
2874 case I915_FORMAT_MOD_X_TILED:
2875 if (INTEL_INFO(dev)->gen == 2)
2876 return 128;
2877 return 512;
2878 case I915_FORMAT_MOD_Y_TILED:
2879 /* No need to check for old gens and Y tiling since this is
2880 * about the display engine and those will be blocked before
2881 * we get here.
2882 */
2883 return 128;
2884 case I915_FORMAT_MOD_Yf_TILED:
2885 if (bits_per_pixel == 8)
2886 return 64;
2887 else
2888 return 128;
2889 default:
2890 MISSING_CASE(fb_modifier);
2891 return 64;
2892 }
2893 }
2894
2895 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2896 struct drm_i915_gem_object *obj)
2897 {
2898 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2899
2900 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2901 view = &i915_ggtt_view_rotated;
2902
2903 return i915_gem_obj_ggtt_offset_view(obj, view);
2904 }
2905
2906 /*
2907 * This function detaches (aka. unbinds) unused scalers in hardware
2908 */
2909 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2910 {
2911 struct drm_device *dev;
2912 struct drm_i915_private *dev_priv;
2913 struct intel_crtc_scaler_state *scaler_state;
2914 int i;
2915
2916 if (!intel_crtc || !intel_crtc->config)
2917 return;
2918
2919 dev = intel_crtc->base.dev;
2920 dev_priv = dev->dev_private;
2921 scaler_state = &intel_crtc->config->scaler_state;
2922
2923 /* loop through and disable scalers that aren't in use */
2924 for (i = 0; i < intel_crtc->num_scalers; i++) {
2925 if (!scaler_state->scalers[i].in_use) {
2926 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2927 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2928 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2929 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2930 intel_crtc->base.base.id, intel_crtc->pipe, i);
2931 }
2932 }
2933 }
2934
2935 u32 skl_plane_ctl_format(uint32_t pixel_format)
2936 {
2937 switch (pixel_format) {
2938 case DRM_FORMAT_C8:
2939 return PLANE_CTL_FORMAT_INDEXED;
2940 case DRM_FORMAT_RGB565:
2941 return PLANE_CTL_FORMAT_RGB_565;
2942 case DRM_FORMAT_XBGR8888:
2943 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2944 case DRM_FORMAT_XRGB8888:
2945 return PLANE_CTL_FORMAT_XRGB_8888;
2946 /*
2947 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2948 * to be already pre-multiplied. We need to add a knob (or a different
2949 * DRM_FORMAT) for user-space to configure that.
2950 */
2951 case DRM_FORMAT_ABGR8888:
2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2953 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2954 case DRM_FORMAT_ARGB8888:
2955 return PLANE_CTL_FORMAT_XRGB_8888 |
2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2957 case DRM_FORMAT_XRGB2101010:
2958 return PLANE_CTL_FORMAT_XRGB_2101010;
2959 case DRM_FORMAT_XBGR2101010:
2960 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2961 case DRM_FORMAT_YUYV:
2962 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2963 case DRM_FORMAT_YVYU:
2964 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2965 case DRM_FORMAT_UYVY:
2966 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2967 case DRM_FORMAT_VYUY:
2968 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2969 default:
2970 MISSING_CASE(pixel_format);
2971 }
2972
2973 return 0;
2974 }
2975
2976 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2977 {
2978 switch (fb_modifier) {
2979 case DRM_FORMAT_MOD_NONE:
2980 break;
2981 case I915_FORMAT_MOD_X_TILED:
2982 return PLANE_CTL_TILED_X;
2983 case I915_FORMAT_MOD_Y_TILED:
2984 return PLANE_CTL_TILED_Y;
2985 case I915_FORMAT_MOD_Yf_TILED:
2986 return PLANE_CTL_TILED_YF;
2987 default:
2988 MISSING_CASE(fb_modifier);
2989 }
2990
2991 return 0;
2992 }
2993
2994 u32 skl_plane_ctl_rotation(unsigned int rotation)
2995 {
2996 switch (rotation) {
2997 case BIT(DRM_ROTATE_0):
2998 break;
2999 /*
3000 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3001 * while i915 HW rotation is clockwise, thats why this swapping.
3002 */
3003 case BIT(DRM_ROTATE_90):
3004 return PLANE_CTL_ROTATE_270;
3005 case BIT(DRM_ROTATE_180):
3006 return PLANE_CTL_ROTATE_180;
3007 case BIT(DRM_ROTATE_270):
3008 return PLANE_CTL_ROTATE_90;
3009 default:
3010 MISSING_CASE(rotation);
3011 }
3012
3013 return 0;
3014 }
3015
3016 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3017 struct drm_framebuffer *fb,
3018 int x, int y)
3019 {
3020 struct drm_device *dev = crtc->dev;
3021 struct drm_i915_private *dev_priv = dev->dev_private;
3022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3023 struct drm_plane *plane = crtc->primary;
3024 bool visible = to_intel_plane_state(plane->state)->visible;
3025 struct drm_i915_gem_object *obj;
3026 int pipe = intel_crtc->pipe;
3027 u32 plane_ctl, stride_div, stride;
3028 u32 tile_height, plane_offset, plane_size;
3029 unsigned int rotation;
3030 int x_offset, y_offset;
3031 unsigned long surf_addr;
3032 struct intel_crtc_state *crtc_state = intel_crtc->config;
3033 struct intel_plane_state *plane_state;
3034 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3035 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3036 int scaler_id = -1;
3037
3038 plane_state = to_intel_plane_state(plane->state);
3039
3040 if (!visible || !fb) {
3041 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3042 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3043 POSTING_READ(PLANE_CTL(pipe, 0));
3044 return;
3045 }
3046
3047 plane_ctl = PLANE_CTL_ENABLE |
3048 PLANE_CTL_PIPE_GAMMA_ENABLE |
3049 PLANE_CTL_PIPE_CSC_ENABLE;
3050
3051 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3052 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3053 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3054
3055 rotation = plane->state->rotation;
3056 plane_ctl |= skl_plane_ctl_rotation(rotation);
3057
3058 obj = intel_fb_obj(fb);
3059 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3060 fb->pixel_format);
3061 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3062
3063 /*
3064 * FIXME: intel_plane_state->src, dst aren't set when transitional
3065 * update_plane helpers are called from legacy paths.
3066 * Once full atomic crtc is available, below check can be avoided.
3067 */
3068 if (drm_rect_width(&plane_state->src)) {
3069 scaler_id = plane_state->scaler_id;
3070 src_x = plane_state->src.x1 >> 16;
3071 src_y = plane_state->src.y1 >> 16;
3072 src_w = drm_rect_width(&plane_state->src) >> 16;
3073 src_h = drm_rect_height(&plane_state->src) >> 16;
3074 dst_x = plane_state->dst.x1;
3075 dst_y = plane_state->dst.y1;
3076 dst_w = drm_rect_width(&plane_state->dst);
3077 dst_h = drm_rect_height(&plane_state->dst);
3078
3079 WARN_ON(x != src_x || y != src_y);
3080 } else {
3081 src_w = intel_crtc->config->pipe_src_w;
3082 src_h = intel_crtc->config->pipe_src_h;
3083 }
3084
3085 if (intel_rotation_90_or_270(rotation)) {
3086 /* stride = Surface height in tiles */
3087 tile_height = intel_tile_height(dev, fb->pixel_format,
3088 fb->modifier[0]);
3089 stride = DIV_ROUND_UP(fb->height, tile_height);
3090 x_offset = stride * tile_height - y - src_h;
3091 y_offset = x;
3092 plane_size = (src_w - 1) << 16 | (src_h - 1);
3093 } else {
3094 stride = fb->pitches[0] / stride_div;
3095 x_offset = x;
3096 y_offset = y;
3097 plane_size = (src_h - 1) << 16 | (src_w - 1);
3098 }
3099 plane_offset = y_offset << 16 | x_offset;
3100
3101 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3102 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3103 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3104 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3105
3106 if (scaler_id >= 0) {
3107 uint32_t ps_ctrl = 0;
3108
3109 WARN_ON(!dst_w || !dst_h);
3110 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3111 crtc_state->scaler_state.scalers[scaler_id].mode;
3112 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3113 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3114 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3115 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3116 I915_WRITE(PLANE_POS(pipe, 0), 0);
3117 } else {
3118 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3119 }
3120
3121 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3122
3123 POSTING_READ(PLANE_SURF(pipe, 0));
3124 }
3125
3126 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3127 static int
3128 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3129 int x, int y, enum mode_set_atomic state)
3130 {
3131 struct drm_device *dev = crtc->dev;
3132 struct drm_i915_private *dev_priv = dev->dev_private;
3133
3134 if (dev_priv->display.disable_fbc)
3135 dev_priv->display.disable_fbc(dev);
3136
3137 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3138
3139 return 0;
3140 }
3141
3142 static void intel_complete_page_flips(struct drm_device *dev)
3143 {
3144 struct drm_crtc *crtc;
3145
3146 for_each_crtc(dev, crtc) {
3147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3148 enum plane plane = intel_crtc->plane;
3149
3150 intel_prepare_page_flip(dev, plane);
3151 intel_finish_page_flip_plane(dev, plane);
3152 }
3153 }
3154
3155 static void intel_update_primary_planes(struct drm_device *dev)
3156 {
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct drm_crtc *crtc;
3159
3160 for_each_crtc(dev, crtc) {
3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162
3163 drm_modeset_lock(&crtc->mutex, NULL);
3164 /*
3165 * FIXME: Once we have proper support for primary planes (and
3166 * disabling them without disabling the entire crtc) allow again
3167 * a NULL crtc->primary->fb.
3168 */
3169 if (intel_crtc->active && crtc->primary->fb)
3170 dev_priv->display.update_primary_plane(crtc,
3171 crtc->primary->fb,
3172 crtc->x,
3173 crtc->y);
3174 drm_modeset_unlock(&crtc->mutex);
3175 }
3176 }
3177
3178 void intel_crtc_reset(struct intel_crtc *crtc)
3179 {
3180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3181
3182 if (!crtc->active)
3183 return;
3184
3185 intel_crtc_disable_planes(&crtc->base);
3186 dev_priv->display.crtc_disable(&crtc->base);
3187 dev_priv->display.crtc_enable(&crtc->base);
3188 intel_crtc_enable_planes(&crtc->base);
3189 }
3190
3191 void intel_prepare_reset(struct drm_device *dev)
3192 {
3193 struct drm_i915_private *dev_priv = to_i915(dev);
3194 struct intel_crtc *crtc;
3195
3196 /* no reset support for gen2 */
3197 if (IS_GEN2(dev))
3198 return;
3199
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3202 return;
3203
3204 drm_modeset_lock_all(dev);
3205
3206 /*
3207 * Disabling the crtcs gracefully seems nicer. Also the
3208 * g33 docs say we should at least disable all the planes.
3209 */
3210 for_each_intel_crtc(dev, crtc) {
3211 if (!crtc->active)
3212 continue;
3213
3214 intel_crtc_disable_planes(&crtc->base);
3215 dev_priv->display.crtc_disable(&crtc->base);
3216 }
3217 }
3218
3219 void intel_finish_reset(struct drm_device *dev)
3220 {
3221 struct drm_i915_private *dev_priv = to_i915(dev);
3222
3223 /*
3224 * Flips in the rings will be nuked by the reset,
3225 * so complete all pending flips so that user space
3226 * will get its events and not get stuck.
3227 */
3228 intel_complete_page_flips(dev);
3229
3230 /* no reset support for gen2 */
3231 if (IS_GEN2(dev))
3232 return;
3233
3234 /* reset doesn't touch the display */
3235 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3236 /*
3237 * Flips in the rings have been nuked by the reset,
3238 * so update the base address of all primary
3239 * planes to the the last fb to make sure we're
3240 * showing the correct fb after a reset.
3241 */
3242 intel_update_primary_planes(dev);
3243 return;
3244 }
3245
3246 /*
3247 * The display has been reset as well,
3248 * so need a full re-initialization.
3249 */
3250 intel_runtime_pm_disable_interrupts(dev_priv);
3251 intel_runtime_pm_enable_interrupts(dev_priv);
3252
3253 intel_modeset_init_hw(dev);
3254
3255 spin_lock_irq(&dev_priv->irq_lock);
3256 if (dev_priv->display.hpd_irq_setup)
3257 dev_priv->display.hpd_irq_setup(dev);
3258 spin_unlock_irq(&dev_priv->irq_lock);
3259
3260 intel_modeset_setup_hw_state(dev, true);
3261
3262 intel_hpd_init(dev_priv);
3263
3264 drm_modeset_unlock_all(dev);
3265 }
3266
3267 static void
3268 intel_finish_fb(struct drm_framebuffer *old_fb)
3269 {
3270 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3271 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3272 bool was_interruptible = dev_priv->mm.interruptible;
3273 int ret;
3274
3275 /* Big Hammer, we also need to ensure that any pending
3276 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3277 * current scanout is retired before unpinning the old
3278 * framebuffer. Note that we rely on userspace rendering
3279 * into the buffer attached to the pipe they are waiting
3280 * on. If not, userspace generates a GPU hang with IPEHR
3281 * point to the MI_WAIT_FOR_EVENT.
3282 *
3283 * This should only fail upon a hung GPU, in which case we
3284 * can safely continue.
3285 */
3286 dev_priv->mm.interruptible = false;
3287 ret = i915_gem_object_wait_rendering(obj, true);
3288 dev_priv->mm.interruptible = was_interruptible;
3289
3290 WARN_ON(ret);
3291 }
3292
3293 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3294 {
3295 struct drm_device *dev = crtc->dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3298 bool pending;
3299
3300 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3301 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3302 return false;
3303
3304 spin_lock_irq(&dev->event_lock);
3305 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3306 spin_unlock_irq(&dev->event_lock);
3307
3308 return pending;
3309 }
3310
3311 static void intel_update_pipe_size(struct intel_crtc *crtc)
3312 {
3313 struct drm_device *dev = crtc->base.dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315 const struct drm_display_mode *adjusted_mode;
3316
3317 if (!i915.fastboot)
3318 return;
3319
3320 /*
3321 * Update pipe size and adjust fitter if needed: the reason for this is
3322 * that in compute_mode_changes we check the native mode (not the pfit
3323 * mode) to see if we can flip rather than do a full mode set. In the
3324 * fastboot case, we'll flip, but if we don't update the pipesrc and
3325 * pfit state, we'll end up with a big fb scanned out into the wrong
3326 * sized surface.
3327 *
3328 * To fix this properly, we need to hoist the checks up into
3329 * compute_mode_changes (or above), check the actual pfit state and
3330 * whether the platform allows pfit disable with pipe active, and only
3331 * then update the pipesrc and pfit state, even on the flip path.
3332 */
3333
3334 adjusted_mode = &crtc->config->base.adjusted_mode;
3335
3336 I915_WRITE(PIPESRC(crtc->pipe),
3337 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3338 (adjusted_mode->crtc_vdisplay - 1));
3339 if (!crtc->config->pch_pfit.enabled &&
3340 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3341 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3342 I915_WRITE(PF_CTL(crtc->pipe), 0);
3343 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3344 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3345 }
3346 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3347 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3348 }
3349
3350 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3351 {
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355 int pipe = intel_crtc->pipe;
3356 u32 reg, temp;
3357
3358 /* enable normal train */
3359 reg = FDI_TX_CTL(pipe);
3360 temp = I915_READ(reg);
3361 if (IS_IVYBRIDGE(dev)) {
3362 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3363 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3364 } else {
3365 temp &= ~FDI_LINK_TRAIN_NONE;
3366 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3367 }
3368 I915_WRITE(reg, temp);
3369
3370 reg = FDI_RX_CTL(pipe);
3371 temp = I915_READ(reg);
3372 if (HAS_PCH_CPT(dev)) {
3373 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3374 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3375 } else {
3376 temp &= ~FDI_LINK_TRAIN_NONE;
3377 temp |= FDI_LINK_TRAIN_NONE;
3378 }
3379 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3380
3381 /* wait one idle pattern time */
3382 POSTING_READ(reg);
3383 udelay(1000);
3384
3385 /* IVB wants error correction enabled */
3386 if (IS_IVYBRIDGE(dev))
3387 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3388 FDI_FE_ERRC_ENABLE);
3389 }
3390
3391 /* The FDI link training functions for ILK/Ibexpeak. */
3392 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3393 {
3394 struct drm_device *dev = crtc->dev;
3395 struct drm_i915_private *dev_priv = dev->dev_private;
3396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3397 int pipe = intel_crtc->pipe;
3398 u32 reg, temp, tries;
3399
3400 /* FDI needs bits from pipe first */
3401 assert_pipe_enabled(dev_priv, pipe);
3402
3403 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3404 for train result */
3405 reg = FDI_RX_IMR(pipe);
3406 temp = I915_READ(reg);
3407 temp &= ~FDI_RX_SYMBOL_LOCK;
3408 temp &= ~FDI_RX_BIT_LOCK;
3409 I915_WRITE(reg, temp);
3410 I915_READ(reg);
3411 udelay(150);
3412
3413 /* enable CPU FDI TX and PCH FDI RX */
3414 reg = FDI_TX_CTL(pipe);
3415 temp = I915_READ(reg);
3416 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3417 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3418 temp &= ~FDI_LINK_TRAIN_NONE;
3419 temp |= FDI_LINK_TRAIN_PATTERN_1;
3420 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3421
3422 reg = FDI_RX_CTL(pipe);
3423 temp = I915_READ(reg);
3424 temp &= ~FDI_LINK_TRAIN_NONE;
3425 temp |= FDI_LINK_TRAIN_PATTERN_1;
3426 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427
3428 POSTING_READ(reg);
3429 udelay(150);
3430
3431 /* Ironlake workaround, enable clock pointer after FDI enable*/
3432 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3433 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3434 FDI_RX_PHASE_SYNC_POINTER_EN);
3435
3436 reg = FDI_RX_IIR(pipe);
3437 for (tries = 0; tries < 5; tries++) {
3438 temp = I915_READ(reg);
3439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3440
3441 if ((temp & FDI_RX_BIT_LOCK)) {
3442 DRM_DEBUG_KMS("FDI train 1 done.\n");
3443 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3444 break;
3445 }
3446 }
3447 if (tries == 5)
3448 DRM_ERROR("FDI train 1 fail!\n");
3449
3450 /* Train 2 */
3451 reg = FDI_TX_CTL(pipe);
3452 temp = I915_READ(reg);
3453 temp &= ~FDI_LINK_TRAIN_NONE;
3454 temp |= FDI_LINK_TRAIN_PATTERN_2;
3455 I915_WRITE(reg, temp);
3456
3457 reg = FDI_RX_CTL(pipe);
3458 temp = I915_READ(reg);
3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_2;
3461 I915_WRITE(reg, temp);
3462
3463 POSTING_READ(reg);
3464 udelay(150);
3465
3466 reg = FDI_RX_IIR(pipe);
3467 for (tries = 0; tries < 5; tries++) {
3468 temp = I915_READ(reg);
3469 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3470
3471 if (temp & FDI_RX_SYMBOL_LOCK) {
3472 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3473 DRM_DEBUG_KMS("FDI train 2 done.\n");
3474 break;
3475 }
3476 }
3477 if (tries == 5)
3478 DRM_ERROR("FDI train 2 fail!\n");
3479
3480 DRM_DEBUG_KMS("FDI train done\n");
3481
3482 }
3483
3484 static const int snb_b_fdi_train_param[] = {
3485 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3486 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3487 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3488 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3489 };
3490
3491 /* The FDI link training functions for SNB/Cougarpoint. */
3492 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3493 {
3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497 int pipe = intel_crtc->pipe;
3498 u32 reg, temp, i, retry;
3499
3500 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3501 for train result */
3502 reg = FDI_RX_IMR(pipe);
3503 temp = I915_READ(reg);
3504 temp &= ~FDI_RX_SYMBOL_LOCK;
3505 temp &= ~FDI_RX_BIT_LOCK;
3506 I915_WRITE(reg, temp);
3507
3508 POSTING_READ(reg);
3509 udelay(150);
3510
3511 /* enable CPU FDI TX and PCH FDI RX */
3512 reg = FDI_TX_CTL(pipe);
3513 temp = I915_READ(reg);
3514 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3515 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3516 temp &= ~FDI_LINK_TRAIN_NONE;
3517 temp |= FDI_LINK_TRAIN_PATTERN_1;
3518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3519 /* SNB-B */
3520 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3521 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3522
3523 I915_WRITE(FDI_RX_MISC(pipe),
3524 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3525
3526 reg = FDI_RX_CTL(pipe);
3527 temp = I915_READ(reg);
3528 if (HAS_PCH_CPT(dev)) {
3529 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3530 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3531 } else {
3532 temp &= ~FDI_LINK_TRAIN_NONE;
3533 temp |= FDI_LINK_TRAIN_PATTERN_1;
3534 }
3535 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3536
3537 POSTING_READ(reg);
3538 udelay(150);
3539
3540 for (i = 0; i < 4; i++) {
3541 reg = FDI_TX_CTL(pipe);
3542 temp = I915_READ(reg);
3543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3544 temp |= snb_b_fdi_train_param[i];
3545 I915_WRITE(reg, temp);
3546
3547 POSTING_READ(reg);
3548 udelay(500);
3549
3550 for (retry = 0; retry < 5; retry++) {
3551 reg = FDI_RX_IIR(pipe);
3552 temp = I915_READ(reg);
3553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3554 if (temp & FDI_RX_BIT_LOCK) {
3555 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3556 DRM_DEBUG_KMS("FDI train 1 done.\n");
3557 break;
3558 }
3559 udelay(50);
3560 }
3561 if (retry < 5)
3562 break;
3563 }
3564 if (i == 4)
3565 DRM_ERROR("FDI train 1 fail!\n");
3566
3567 /* Train 2 */
3568 reg = FDI_TX_CTL(pipe);
3569 temp = I915_READ(reg);
3570 temp &= ~FDI_LINK_TRAIN_NONE;
3571 temp |= FDI_LINK_TRAIN_PATTERN_2;
3572 if (IS_GEN6(dev)) {
3573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574 /* SNB-B */
3575 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3576 }
3577 I915_WRITE(reg, temp);
3578
3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
3581 if (HAS_PCH_CPT(dev)) {
3582 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3583 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3584 } else {
3585 temp &= ~FDI_LINK_TRAIN_NONE;
3586 temp |= FDI_LINK_TRAIN_PATTERN_2;
3587 }
3588 I915_WRITE(reg, temp);
3589
3590 POSTING_READ(reg);
3591 udelay(150);
3592
3593 for (i = 0; i < 4; i++) {
3594 reg = FDI_TX_CTL(pipe);
3595 temp = I915_READ(reg);
3596 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3597 temp |= snb_b_fdi_train_param[i];
3598 I915_WRITE(reg, temp);
3599
3600 POSTING_READ(reg);
3601 udelay(500);
3602
3603 for (retry = 0; retry < 5; retry++) {
3604 reg = FDI_RX_IIR(pipe);
3605 temp = I915_READ(reg);
3606 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3607 if (temp & FDI_RX_SYMBOL_LOCK) {
3608 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3609 DRM_DEBUG_KMS("FDI train 2 done.\n");
3610 break;
3611 }
3612 udelay(50);
3613 }
3614 if (retry < 5)
3615 break;
3616 }
3617 if (i == 4)
3618 DRM_ERROR("FDI train 2 fail!\n");
3619
3620 DRM_DEBUG_KMS("FDI train done.\n");
3621 }
3622
3623 /* Manual link training for Ivy Bridge A0 parts */
3624 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3625 {
3626 struct drm_device *dev = crtc->dev;
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629 int pipe = intel_crtc->pipe;
3630 u32 reg, temp, i, j;
3631
3632 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3633 for train result */
3634 reg = FDI_RX_IMR(pipe);
3635 temp = I915_READ(reg);
3636 temp &= ~FDI_RX_SYMBOL_LOCK;
3637 temp &= ~FDI_RX_BIT_LOCK;
3638 I915_WRITE(reg, temp);
3639
3640 POSTING_READ(reg);
3641 udelay(150);
3642
3643 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3644 I915_READ(FDI_RX_IIR(pipe)));
3645
3646 /* Try each vswing and preemphasis setting twice before moving on */
3647 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3648 /* disable first in case we need to retry */
3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3652 temp &= ~FDI_TX_ENABLE;
3653 I915_WRITE(reg, temp);
3654
3655 reg = FDI_RX_CTL(pipe);
3656 temp = I915_READ(reg);
3657 temp &= ~FDI_LINK_TRAIN_AUTO;
3658 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3659 temp &= ~FDI_RX_ENABLE;
3660 I915_WRITE(reg, temp);
3661
3662 /* enable CPU FDI TX and PCH FDI RX */
3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3667 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3668 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3669 temp |= snb_b_fdi_train_param[j/2];
3670 temp |= FDI_COMPOSITE_SYNC;
3671 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3672
3673 I915_WRITE(FDI_RX_MISC(pipe),
3674 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3675
3676 reg = FDI_RX_CTL(pipe);
3677 temp = I915_READ(reg);
3678 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3679 temp |= FDI_COMPOSITE_SYNC;
3680 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3681
3682 POSTING_READ(reg);
3683 udelay(1); /* should be 0.5us */
3684
3685 for (i = 0; i < 4; i++) {
3686 reg = FDI_RX_IIR(pipe);
3687 temp = I915_READ(reg);
3688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3689
3690 if (temp & FDI_RX_BIT_LOCK ||
3691 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3692 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3693 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3694 i);
3695 break;
3696 }
3697 udelay(1); /* should be 0.5us */
3698 }
3699 if (i == 4) {
3700 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3701 continue;
3702 }
3703
3704 /* Train 2 */
3705 reg = FDI_TX_CTL(pipe);
3706 temp = I915_READ(reg);
3707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3709 I915_WRITE(reg, temp);
3710
3711 reg = FDI_RX_CTL(pipe);
3712 temp = I915_READ(reg);
3713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3715 I915_WRITE(reg, temp);
3716
3717 POSTING_READ(reg);
3718 udelay(2); /* should be 1.5us */
3719
3720 for (i = 0; i < 4; i++) {
3721 reg = FDI_RX_IIR(pipe);
3722 temp = I915_READ(reg);
3723 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3724
3725 if (temp & FDI_RX_SYMBOL_LOCK ||
3726 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3727 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3728 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3729 i);
3730 goto train_done;
3731 }
3732 udelay(2); /* should be 1.5us */
3733 }
3734 if (i == 4)
3735 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3736 }
3737
3738 train_done:
3739 DRM_DEBUG_KMS("FDI train done.\n");
3740 }
3741
3742 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3743 {
3744 struct drm_device *dev = intel_crtc->base.dev;
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3746 int pipe = intel_crtc->pipe;
3747 u32 reg, temp;
3748
3749
3750 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3751 reg = FDI_RX_CTL(pipe);
3752 temp = I915_READ(reg);
3753 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3754 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3755 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3756 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3757
3758 POSTING_READ(reg);
3759 udelay(200);
3760
3761 /* Switch from Rawclk to PCDclk */
3762 temp = I915_READ(reg);
3763 I915_WRITE(reg, temp | FDI_PCDCLK);
3764
3765 POSTING_READ(reg);
3766 udelay(200);
3767
3768 /* Enable CPU FDI TX PLL, always on for Ironlake */
3769 reg = FDI_TX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3772 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3773
3774 POSTING_READ(reg);
3775 udelay(100);
3776 }
3777 }
3778
3779 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3780 {
3781 struct drm_device *dev = intel_crtc->base.dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 int pipe = intel_crtc->pipe;
3784 u32 reg, temp;
3785
3786 /* Switch from PCDclk to Rawclk */
3787 reg = FDI_RX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3790
3791 /* Disable CPU FDI TX PLL */
3792 reg = FDI_TX_CTL(pipe);
3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3795
3796 POSTING_READ(reg);
3797 udelay(100);
3798
3799 reg = FDI_RX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3802
3803 /* Wait for the clocks to turn off. */
3804 POSTING_READ(reg);
3805 udelay(100);
3806 }
3807
3808 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3809 {
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813 int pipe = intel_crtc->pipe;
3814 u32 reg, temp;
3815
3816 /* disable CPU FDI tx and PCH FDI rx */
3817 reg = FDI_TX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3820 POSTING_READ(reg);
3821
3822 reg = FDI_RX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 temp &= ~(0x7 << 16);
3825 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3826 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3827
3828 POSTING_READ(reg);
3829 udelay(100);
3830
3831 /* Ironlake workaround, disable clock pointer after downing FDI */
3832 if (HAS_PCH_IBX(dev))
3833 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3834
3835 /* still set train pattern 1 */
3836 reg = FDI_TX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~FDI_LINK_TRAIN_NONE;
3839 temp |= FDI_LINK_TRAIN_PATTERN_1;
3840 I915_WRITE(reg, temp);
3841
3842 reg = FDI_RX_CTL(pipe);
3843 temp = I915_READ(reg);
3844 if (HAS_PCH_CPT(dev)) {
3845 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3846 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3847 } else {
3848 temp &= ~FDI_LINK_TRAIN_NONE;
3849 temp |= FDI_LINK_TRAIN_PATTERN_1;
3850 }
3851 /* BPC in FDI rx is consistent with that in PIPECONF */
3852 temp &= ~(0x07 << 16);
3853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3854 I915_WRITE(reg, temp);
3855
3856 POSTING_READ(reg);
3857 udelay(100);
3858 }
3859
3860 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3861 {
3862 struct intel_crtc *crtc;
3863
3864 /* Note that we don't need to be called with mode_config.lock here
3865 * as our list of CRTC objects is static for the lifetime of the
3866 * device and so cannot disappear as we iterate. Similarly, we can
3867 * happily treat the predicates as racy, atomic checks as userspace
3868 * cannot claim and pin a new fb without at least acquring the
3869 * struct_mutex and so serialising with us.
3870 */
3871 for_each_intel_crtc(dev, crtc) {
3872 if (atomic_read(&crtc->unpin_work_count) == 0)
3873 continue;
3874
3875 if (crtc->unpin_work)
3876 intel_wait_for_vblank(dev, crtc->pipe);
3877
3878 return true;
3879 }
3880
3881 return false;
3882 }
3883
3884 static void page_flip_completed(struct intel_crtc *intel_crtc)
3885 {
3886 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3887 struct intel_unpin_work *work = intel_crtc->unpin_work;
3888
3889 /* ensure that the unpin work is consistent wrt ->pending. */
3890 smp_rmb();
3891 intel_crtc->unpin_work = NULL;
3892
3893 if (work->event)
3894 drm_send_vblank_event(intel_crtc->base.dev,
3895 intel_crtc->pipe,
3896 work->event);
3897
3898 drm_crtc_vblank_put(&intel_crtc->base);
3899
3900 wake_up_all(&dev_priv->pending_flip_queue);
3901 queue_work(dev_priv->wq, &work->work);
3902
3903 trace_i915_flip_complete(intel_crtc->plane,
3904 work->pending_flip_obj);
3905 }
3906
3907 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3908 {
3909 struct drm_device *dev = crtc->dev;
3910 struct drm_i915_private *dev_priv = dev->dev_private;
3911
3912 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3913 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3914 !intel_crtc_has_pending_flip(crtc),
3915 60*HZ) == 0)) {
3916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3917
3918 spin_lock_irq(&dev->event_lock);
3919 if (intel_crtc->unpin_work) {
3920 WARN_ONCE(1, "Removing stuck page flip\n");
3921 page_flip_completed(intel_crtc);
3922 }
3923 spin_unlock_irq(&dev->event_lock);
3924 }
3925
3926 if (crtc->primary->fb) {
3927 mutex_lock(&dev->struct_mutex);
3928 intel_finish_fb(crtc->primary->fb);
3929 mutex_unlock(&dev->struct_mutex);
3930 }
3931 }
3932
3933 /* Program iCLKIP clock to the desired frequency */
3934 static void lpt_program_iclkip(struct drm_crtc *crtc)
3935 {
3936 struct drm_device *dev = crtc->dev;
3937 struct drm_i915_private *dev_priv = dev->dev_private;
3938 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3939 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3940 u32 temp;
3941
3942 mutex_lock(&dev_priv->sb_lock);
3943
3944 /* It is necessary to ungate the pixclk gate prior to programming
3945 * the divisors, and gate it back when it is done.
3946 */
3947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3948
3949 /* Disable SSCCTL */
3950 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3951 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3952 SBI_SSCCTL_DISABLE,
3953 SBI_ICLK);
3954
3955 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3956 if (clock == 20000) {
3957 auxdiv = 1;
3958 divsel = 0x41;
3959 phaseinc = 0x20;
3960 } else {
3961 /* The iCLK virtual clock root frequency is in MHz,
3962 * but the adjusted_mode->crtc_clock in in KHz. To get the
3963 * divisors, it is necessary to divide one by another, so we
3964 * convert the virtual clock precision to KHz here for higher
3965 * precision.
3966 */
3967 u32 iclk_virtual_root_freq = 172800 * 1000;
3968 u32 iclk_pi_range = 64;
3969 u32 desired_divisor, msb_divisor_value, pi_value;
3970
3971 desired_divisor = (iclk_virtual_root_freq / clock);
3972 msb_divisor_value = desired_divisor / iclk_pi_range;
3973 pi_value = desired_divisor % iclk_pi_range;
3974
3975 auxdiv = 0;
3976 divsel = msb_divisor_value - 2;
3977 phaseinc = pi_value;
3978 }
3979
3980 /* This should not happen with any sane values */
3981 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3982 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3984 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3985
3986 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3987 clock,
3988 auxdiv,
3989 divsel,
3990 phasedir,
3991 phaseinc);
3992
3993 /* Program SSCDIVINTPHASE6 */
3994 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3995 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3996 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3997 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3998 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3999 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4000 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4001 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4002
4003 /* Program SSCAUXDIV */
4004 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4005 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4006 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4007 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4008
4009 /* Enable modulator and associated divider */
4010 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4011 temp &= ~SBI_SSCCTL_DISABLE;
4012 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4013
4014 /* Wait for initialization time */
4015 udelay(24);
4016
4017 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4018
4019 mutex_unlock(&dev_priv->sb_lock);
4020 }
4021
4022 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4023 enum pipe pch_transcoder)
4024 {
4025 struct drm_device *dev = crtc->base.dev;
4026 struct drm_i915_private *dev_priv = dev->dev_private;
4027 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4028
4029 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4030 I915_READ(HTOTAL(cpu_transcoder)));
4031 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4032 I915_READ(HBLANK(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4034 I915_READ(HSYNC(cpu_transcoder)));
4035
4036 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4037 I915_READ(VTOTAL(cpu_transcoder)));
4038 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4039 I915_READ(VBLANK(cpu_transcoder)));
4040 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4041 I915_READ(VSYNC(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4043 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4044 }
4045
4046 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4047 {
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 uint32_t temp;
4050
4051 temp = I915_READ(SOUTH_CHICKEN1);
4052 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4053 return;
4054
4055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4056 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4057
4058 temp &= ~FDI_BC_BIFURCATION_SELECT;
4059 if (enable)
4060 temp |= FDI_BC_BIFURCATION_SELECT;
4061
4062 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4063 I915_WRITE(SOUTH_CHICKEN1, temp);
4064 POSTING_READ(SOUTH_CHICKEN1);
4065 }
4066
4067 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4068 {
4069 struct drm_device *dev = intel_crtc->base.dev;
4070
4071 switch (intel_crtc->pipe) {
4072 case PIPE_A:
4073 break;
4074 case PIPE_B:
4075 if (intel_crtc->config->fdi_lanes > 2)
4076 cpt_set_fdi_bc_bifurcation(dev, false);
4077 else
4078 cpt_set_fdi_bc_bifurcation(dev, true);
4079
4080 break;
4081 case PIPE_C:
4082 cpt_set_fdi_bc_bifurcation(dev, true);
4083
4084 break;
4085 default:
4086 BUG();
4087 }
4088 }
4089
4090 /*
4091 * Enable PCH resources required for PCH ports:
4092 * - PCH PLLs
4093 * - FDI training & RX/TX
4094 * - update transcoder timings
4095 * - DP transcoding bits
4096 * - transcoder
4097 */
4098 static void ironlake_pch_enable(struct drm_crtc *crtc)
4099 {
4100 struct drm_device *dev = crtc->dev;
4101 struct drm_i915_private *dev_priv = dev->dev_private;
4102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4103 int pipe = intel_crtc->pipe;
4104 u32 reg, temp;
4105
4106 assert_pch_transcoder_disabled(dev_priv, pipe);
4107
4108 if (IS_IVYBRIDGE(dev))
4109 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4110
4111 /* Write the TU size bits before fdi link training, so that error
4112 * detection works. */
4113 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4114 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4115
4116 /* For PCH output, training FDI link */
4117 dev_priv->display.fdi_link_train(crtc);
4118
4119 /* We need to program the right clock selection before writing the pixel
4120 * mutliplier into the DPLL. */
4121 if (HAS_PCH_CPT(dev)) {
4122 u32 sel;
4123
4124 temp = I915_READ(PCH_DPLL_SEL);
4125 temp |= TRANS_DPLL_ENABLE(pipe);
4126 sel = TRANS_DPLLB_SEL(pipe);
4127 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4128 temp |= sel;
4129 else
4130 temp &= ~sel;
4131 I915_WRITE(PCH_DPLL_SEL, temp);
4132 }
4133
4134 /* XXX: pch pll's can be enabled any time before we enable the PCH
4135 * transcoder, and we actually should do this to not upset any PCH
4136 * transcoder that already use the clock when we share it.
4137 *
4138 * Note that enable_shared_dpll tries to do the right thing, but
4139 * get_shared_dpll unconditionally resets the pll - we need that to have
4140 * the right LVDS enable sequence. */
4141 intel_enable_shared_dpll(intel_crtc);
4142
4143 /* set transcoder timing, panel must allow it */
4144 assert_panel_unlocked(dev_priv, pipe);
4145 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4146
4147 intel_fdi_normal_train(crtc);
4148
4149 /* For PCH DP, enable TRANS_DP_CTL */
4150 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4151 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4152 reg = TRANS_DP_CTL(pipe);
4153 temp = I915_READ(reg);
4154 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4155 TRANS_DP_SYNC_MASK |
4156 TRANS_DP_BPC_MASK);
4157 temp |= TRANS_DP_OUTPUT_ENABLE;
4158 temp |= bpc << 9; /* same format but at 11:9 */
4159
4160 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4161 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4162 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4163 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4164
4165 switch (intel_trans_dp_port_sel(crtc)) {
4166 case PCH_DP_B:
4167 temp |= TRANS_DP_PORT_SEL_B;
4168 break;
4169 case PCH_DP_C:
4170 temp |= TRANS_DP_PORT_SEL_C;
4171 break;
4172 case PCH_DP_D:
4173 temp |= TRANS_DP_PORT_SEL_D;
4174 break;
4175 default:
4176 BUG();
4177 }
4178
4179 I915_WRITE(reg, temp);
4180 }
4181
4182 ironlake_enable_pch_transcoder(dev_priv, pipe);
4183 }
4184
4185 static void lpt_pch_enable(struct drm_crtc *crtc)
4186 {
4187 struct drm_device *dev = crtc->dev;
4188 struct drm_i915_private *dev_priv = dev->dev_private;
4189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4190 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4191
4192 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4193
4194 lpt_program_iclkip(crtc);
4195
4196 /* Set transcoder timing. */
4197 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4198
4199 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4200 }
4201
4202 void intel_put_shared_dpll(struct intel_crtc *crtc)
4203 {
4204 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4205
4206 if (pll == NULL)
4207 return;
4208
4209 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4210 WARN(1, "bad %s crtc mask\n", pll->name);
4211 return;
4212 }
4213
4214 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4215 if (pll->config.crtc_mask == 0) {
4216 WARN_ON(pll->on);
4217 WARN_ON(pll->active);
4218 }
4219
4220 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4221 }
4222
4223 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4224 struct intel_crtc_state *crtc_state)
4225 {
4226 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4227 struct intel_shared_dpll *pll;
4228 enum intel_dpll_id i;
4229
4230 if (HAS_PCH_IBX(dev_priv->dev)) {
4231 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4232 i = (enum intel_dpll_id) crtc->pipe;
4233 pll = &dev_priv->shared_dplls[i];
4234
4235 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236 crtc->base.base.id, pll->name);
4237
4238 WARN_ON(pll->new_config->crtc_mask);
4239
4240 goto found;
4241 }
4242
4243 if (IS_BROXTON(dev_priv->dev)) {
4244 /* PLL is attached to port in bxt */
4245 struct intel_encoder *encoder;
4246 struct intel_digital_port *intel_dig_port;
4247
4248 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4249 if (WARN_ON(!encoder))
4250 return NULL;
4251
4252 intel_dig_port = enc_to_dig_port(&encoder->base);
4253 /* 1:1 mapping between ports and PLLs */
4254 i = (enum intel_dpll_id)intel_dig_port->port;
4255 pll = &dev_priv->shared_dplls[i];
4256 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4257 crtc->base.base.id, pll->name);
4258 WARN_ON(pll->new_config->crtc_mask);
4259
4260 goto found;
4261 }
4262
4263 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4264 pll = &dev_priv->shared_dplls[i];
4265
4266 /* Only want to check enabled timings first */
4267 if (pll->new_config->crtc_mask == 0)
4268 continue;
4269
4270 if (memcmp(&crtc_state->dpll_hw_state,
4271 &pll->new_config->hw_state,
4272 sizeof(pll->new_config->hw_state)) == 0) {
4273 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4274 crtc->base.base.id, pll->name,
4275 pll->new_config->crtc_mask,
4276 pll->active);
4277 goto found;
4278 }
4279 }
4280
4281 /* Ok no matching timings, maybe there's a free one? */
4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
4284 if (pll->new_config->crtc_mask == 0) {
4285 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4286 crtc->base.base.id, pll->name);
4287 goto found;
4288 }
4289 }
4290
4291 return NULL;
4292
4293 found:
4294 if (pll->new_config->crtc_mask == 0)
4295 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4296
4297 crtc_state->shared_dpll = i;
4298 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4299 pipe_name(crtc->pipe));
4300
4301 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4302
4303 return pll;
4304 }
4305
4306 /**
4307 * intel_shared_dpll_start_config - start a new PLL staged config
4308 * @dev_priv: DRM device
4309 * @clear_pipes: mask of pipes that will have their PLLs freed
4310 *
4311 * Starts a new PLL staged config, copying the current config but
4312 * releasing the references of pipes specified in clear_pipes.
4313 */
4314 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4315 unsigned clear_pipes)
4316 {
4317 struct intel_shared_dpll *pll;
4318 enum intel_dpll_id i;
4319
4320 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4321 pll = &dev_priv->shared_dplls[i];
4322
4323 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4324 GFP_KERNEL);
4325 if (!pll->new_config)
4326 goto cleanup;
4327
4328 pll->new_config->crtc_mask &= ~clear_pipes;
4329 }
4330
4331 return 0;
4332
4333 cleanup:
4334 while (--i >= 0) {
4335 pll = &dev_priv->shared_dplls[i];
4336 kfree(pll->new_config);
4337 pll->new_config = NULL;
4338 }
4339
4340 return -ENOMEM;
4341 }
4342
4343 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4344 {
4345 struct intel_shared_dpll *pll;
4346 enum intel_dpll_id i;
4347
4348 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4349 pll = &dev_priv->shared_dplls[i];
4350
4351 WARN_ON(pll->new_config == &pll->config);
4352
4353 pll->config = *pll->new_config;
4354 kfree(pll->new_config);
4355 pll->new_config = NULL;
4356 }
4357 }
4358
4359 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4360 {
4361 struct intel_shared_dpll *pll;
4362 enum intel_dpll_id i;
4363
4364 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4365 pll = &dev_priv->shared_dplls[i];
4366
4367 WARN_ON(pll->new_config == &pll->config);
4368
4369 kfree(pll->new_config);
4370 pll->new_config = NULL;
4371 }
4372 }
4373
4374 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4375 {
4376 struct drm_i915_private *dev_priv = dev->dev_private;
4377 int dslreg = PIPEDSL(pipe);
4378 u32 temp;
4379
4380 temp = I915_READ(dslreg);
4381 udelay(500);
4382 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4383 if (wait_for(I915_READ(dslreg) != temp, 5))
4384 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4385 }
4386 }
4387
4388 /**
4389 * skl_update_scaler_users - Stages update to crtc's scaler state
4390 * @intel_crtc: crtc
4391 * @crtc_state: crtc_state
4392 * @plane: plane (NULL indicates crtc is requesting update)
4393 * @plane_state: plane's state
4394 * @force_detach: request unconditional detachment of scaler
4395 *
4396 * This function updates scaler state for requested plane or crtc.
4397 * To request scaler usage update for a plane, caller shall pass plane pointer.
4398 * To request scaler usage update for crtc, caller shall pass plane pointer
4399 * as NULL.
4400 *
4401 * Return
4402 * 0 - scaler_usage updated successfully
4403 * error - requested scaling cannot be supported or other error condition
4404 */
4405 int
4406 skl_update_scaler_users(
4407 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4408 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4409 int force_detach)
4410 {
4411 int need_scaling;
4412 int idx;
4413 int src_w, src_h, dst_w, dst_h;
4414 int *scaler_id;
4415 struct drm_framebuffer *fb;
4416 struct intel_crtc_scaler_state *scaler_state;
4417 unsigned int rotation;
4418
4419 if (!intel_crtc || !crtc_state)
4420 return 0;
4421
4422 scaler_state = &crtc_state->scaler_state;
4423
4424 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4425 fb = intel_plane ? plane_state->base.fb : NULL;
4426
4427 if (intel_plane) {
4428 src_w = drm_rect_width(&plane_state->src) >> 16;
4429 src_h = drm_rect_height(&plane_state->src) >> 16;
4430 dst_w = drm_rect_width(&plane_state->dst);
4431 dst_h = drm_rect_height(&plane_state->dst);
4432 scaler_id = &plane_state->scaler_id;
4433 rotation = plane_state->base.rotation;
4434 } else {
4435 struct drm_display_mode *adjusted_mode =
4436 &crtc_state->base.adjusted_mode;
4437 src_w = crtc_state->pipe_src_w;
4438 src_h = crtc_state->pipe_src_h;
4439 dst_w = adjusted_mode->hdisplay;
4440 dst_h = adjusted_mode->vdisplay;
4441 scaler_id = &scaler_state->scaler_id;
4442 rotation = DRM_ROTATE_0;
4443 }
4444
4445 need_scaling = intel_rotation_90_or_270(rotation) ?
4446 (src_h != dst_w || src_w != dst_h):
4447 (src_w != dst_w || src_h != dst_h);
4448
4449 /*
4450 * if plane is being disabled or scaler is no more required or force detach
4451 * - free scaler binded to this plane/crtc
4452 * - in order to do this, update crtc->scaler_usage
4453 *
4454 * Here scaler state in crtc_state is set free so that
4455 * scaler can be assigned to other user. Actual register
4456 * update to free the scaler is done in plane/panel-fit programming.
4457 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4458 */
4459 if (force_detach || !need_scaling || (intel_plane &&
4460 (!fb || !plane_state->visible))) {
4461 if (*scaler_id >= 0) {
4462 scaler_state->scaler_users &= ~(1 << idx);
4463 scaler_state->scalers[*scaler_id].in_use = 0;
4464
4465 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4466 "crtc_state = %p scaler_users = 0x%x\n",
4467 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4468 intel_plane ? intel_plane->base.base.id :
4469 intel_crtc->base.base.id, crtc_state,
4470 scaler_state->scaler_users);
4471 *scaler_id = -1;
4472 }
4473 return 0;
4474 }
4475
4476 /* range checks */
4477 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4478 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4479
4480 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4481 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4482 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4483 "size is out of scaler range\n",
4484 intel_plane ? "PLANE" : "CRTC",
4485 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4486 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4487 return -EINVAL;
4488 }
4489
4490 /* check colorkey */
4491 if (WARN_ON(intel_plane &&
4492 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4493 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4494 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
4495 return -EINVAL;
4496 }
4497
4498 /* Check src format */
4499 if (intel_plane) {
4500 switch (fb->pixel_format) {
4501 case DRM_FORMAT_RGB565:
4502 case DRM_FORMAT_XBGR8888:
4503 case DRM_FORMAT_XRGB8888:
4504 case DRM_FORMAT_ABGR8888:
4505 case DRM_FORMAT_ARGB8888:
4506 case DRM_FORMAT_XRGB2101010:
4507 case DRM_FORMAT_XBGR2101010:
4508 case DRM_FORMAT_YUYV:
4509 case DRM_FORMAT_YVYU:
4510 case DRM_FORMAT_UYVY:
4511 case DRM_FORMAT_VYUY:
4512 break;
4513 default:
4514 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4515 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4516 return -EINVAL;
4517 }
4518 }
4519
4520 /* mark this plane as a scaler user in crtc_state */
4521 scaler_state->scaler_users |= (1 << idx);
4522 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4523 "crtc_state = %p scaler_users = 0x%x\n",
4524 intel_plane ? "PLANE" : "CRTC",
4525 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4526 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4527 return 0;
4528 }
4529
4530 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4531 {
4532 struct drm_device *dev = crtc->base.dev;
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4534 int pipe = crtc->pipe;
4535 struct intel_crtc_scaler_state *scaler_state =
4536 &crtc->config->scaler_state;
4537
4538 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4539
4540 /* To update pfit, first update scaler state */
4541 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4542 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4543 skl_detach_scalers(crtc);
4544 if (!enable)
4545 return;
4546
4547 if (crtc->config->pch_pfit.enabled) {
4548 int id;
4549
4550 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4551 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4552 return;
4553 }
4554
4555 id = scaler_state->scaler_id;
4556 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4557 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4558 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4559 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4560
4561 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4562 }
4563 }
4564
4565 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4566 {
4567 struct drm_device *dev = crtc->base.dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569 int pipe = crtc->pipe;
4570
4571 if (crtc->config->pch_pfit.enabled) {
4572 /* Force use of hard-coded filter coefficients
4573 * as some pre-programmed values are broken,
4574 * e.g. x201.
4575 */
4576 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4577 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4578 PF_PIPE_SEL_IVB(pipe));
4579 else
4580 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4581 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4582 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4583 }
4584 }
4585
4586 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4587 {
4588 struct drm_device *dev = crtc->dev;
4589 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4590 struct drm_plane *plane;
4591 struct intel_plane *intel_plane;
4592
4593 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4594 intel_plane = to_intel_plane(plane);
4595 if (intel_plane->pipe == pipe)
4596 intel_plane_restore(&intel_plane->base);
4597 }
4598 }
4599
4600 void hsw_enable_ips(struct intel_crtc *crtc)
4601 {
4602 struct drm_device *dev = crtc->base.dev;
4603 struct drm_i915_private *dev_priv = dev->dev_private;
4604
4605 if (!crtc->config->ips_enabled)
4606 return;
4607
4608 /* We can only enable IPS after we enable a plane and wait for a vblank */
4609 intel_wait_for_vblank(dev, crtc->pipe);
4610
4611 assert_plane_enabled(dev_priv, crtc->plane);
4612 if (IS_BROADWELL(dev)) {
4613 mutex_lock(&dev_priv->rps.hw_lock);
4614 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4615 mutex_unlock(&dev_priv->rps.hw_lock);
4616 /* Quoting Art Runyan: "its not safe to expect any particular
4617 * value in IPS_CTL bit 31 after enabling IPS through the
4618 * mailbox." Moreover, the mailbox may return a bogus state,
4619 * so we need to just enable it and continue on.
4620 */
4621 } else {
4622 I915_WRITE(IPS_CTL, IPS_ENABLE);
4623 /* The bit only becomes 1 in the next vblank, so this wait here
4624 * is essentially intel_wait_for_vblank. If we don't have this
4625 * and don't wait for vblanks until the end of crtc_enable, then
4626 * the HW state readout code will complain that the expected
4627 * IPS_CTL value is not the one we read. */
4628 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4629 DRM_ERROR("Timed out waiting for IPS enable\n");
4630 }
4631 }
4632
4633 void hsw_disable_ips(struct intel_crtc *crtc)
4634 {
4635 struct drm_device *dev = crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637
4638 if (!crtc->config->ips_enabled)
4639 return;
4640
4641 assert_plane_enabled(dev_priv, crtc->plane);
4642 if (IS_BROADWELL(dev)) {
4643 mutex_lock(&dev_priv->rps.hw_lock);
4644 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4645 mutex_unlock(&dev_priv->rps.hw_lock);
4646 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4647 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4648 DRM_ERROR("Timed out waiting for IPS disable\n");
4649 } else {
4650 I915_WRITE(IPS_CTL, 0);
4651 POSTING_READ(IPS_CTL);
4652 }
4653
4654 /* We need to wait for a vblank before we can disable the plane. */
4655 intel_wait_for_vblank(dev, crtc->pipe);
4656 }
4657
4658 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4659 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4660 {
4661 struct drm_device *dev = crtc->dev;
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4664 enum pipe pipe = intel_crtc->pipe;
4665 int palreg = PALETTE(pipe);
4666 int i;
4667 bool reenable_ips = false;
4668
4669 /* The clocks have to be on to load the palette. */
4670 if (!crtc->state->enable || !intel_crtc->active)
4671 return;
4672
4673 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4674 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4675 assert_dsi_pll_enabled(dev_priv);
4676 else
4677 assert_pll_enabled(dev_priv, pipe);
4678 }
4679
4680 /* use legacy palette for Ironlake */
4681 if (!HAS_GMCH_DISPLAY(dev))
4682 palreg = LGC_PALETTE(pipe);
4683
4684 /* Workaround : Do not read or write the pipe palette/gamma data while
4685 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4686 */
4687 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4688 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4689 GAMMA_MODE_MODE_SPLIT)) {
4690 hsw_disable_ips(intel_crtc);
4691 reenable_ips = true;
4692 }
4693
4694 for (i = 0; i < 256; i++) {
4695 I915_WRITE(palreg + 4 * i,
4696 (intel_crtc->lut_r[i] << 16) |
4697 (intel_crtc->lut_g[i] << 8) |
4698 intel_crtc->lut_b[i]);
4699 }
4700
4701 if (reenable_ips)
4702 hsw_enable_ips(intel_crtc);
4703 }
4704
4705 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4706 {
4707 if (intel_crtc->overlay) {
4708 struct drm_device *dev = intel_crtc->base.dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710
4711 mutex_lock(&dev->struct_mutex);
4712 dev_priv->mm.interruptible = false;
4713 (void) intel_overlay_switch_off(intel_crtc->overlay);
4714 dev_priv->mm.interruptible = true;
4715 mutex_unlock(&dev->struct_mutex);
4716 }
4717
4718 /* Let userspace switch the overlay on again. In most cases userspace
4719 * has to recompute where to put it anyway.
4720 */
4721 }
4722
4723 /**
4724 * intel_post_enable_primary - Perform operations after enabling primary plane
4725 * @crtc: the CRTC whose primary plane was just enabled
4726 *
4727 * Performs potentially sleeping operations that must be done after the primary
4728 * plane is enabled, such as updating FBC and IPS. Note that this may be
4729 * called due to an explicit primary plane update, or due to an implicit
4730 * re-enable that is caused when a sprite plane is updated to no longer
4731 * completely hide the primary plane.
4732 */
4733 static void
4734 intel_post_enable_primary(struct drm_crtc *crtc)
4735 {
4736 struct drm_device *dev = crtc->dev;
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739 int pipe = intel_crtc->pipe;
4740
4741 /*
4742 * BDW signals flip done immediately if the plane
4743 * is disabled, even if the plane enable is already
4744 * armed to occur at the next vblank :(
4745 */
4746 if (IS_BROADWELL(dev))
4747 intel_wait_for_vblank(dev, pipe);
4748
4749 /*
4750 * FIXME IPS should be fine as long as one plane is
4751 * enabled, but in practice it seems to have problems
4752 * when going from primary only to sprite only and vice
4753 * versa.
4754 */
4755 hsw_enable_ips(intel_crtc);
4756
4757 mutex_lock(&dev->struct_mutex);
4758 intel_fbc_update(dev);
4759 mutex_unlock(&dev->struct_mutex);
4760
4761 /*
4762 * Gen2 reports pipe underruns whenever all planes are disabled.
4763 * So don't enable underrun reporting before at least some planes
4764 * are enabled.
4765 * FIXME: Need to fix the logic to work when we turn off all planes
4766 * but leave the pipe running.
4767 */
4768 if (IS_GEN2(dev))
4769 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4770
4771 /* Underruns don't raise interrupts, so check manually. */
4772 if (HAS_GMCH_DISPLAY(dev))
4773 i9xx_check_fifo_underruns(dev_priv);
4774 }
4775
4776 /**
4777 * intel_pre_disable_primary - Perform operations before disabling primary plane
4778 * @crtc: the CRTC whose primary plane is to be disabled
4779 *
4780 * Performs potentially sleeping operations that must be done before the
4781 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4782 * be called due to an explicit primary plane update, or due to an implicit
4783 * disable that is caused when a sprite plane completely hides the primary
4784 * plane.
4785 */
4786 static void
4787 intel_pre_disable_primary(struct drm_crtc *crtc)
4788 {
4789 struct drm_device *dev = crtc->dev;
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4792 int pipe = intel_crtc->pipe;
4793
4794 /*
4795 * Gen2 reports pipe underruns whenever all planes are disabled.
4796 * So diasble underrun reporting before all the planes get disabled.
4797 * FIXME: Need to fix the logic to work when we turn off all planes
4798 * but leave the pipe running.
4799 */
4800 if (IS_GEN2(dev))
4801 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4802
4803 /*
4804 * Vblank time updates from the shadow to live plane control register
4805 * are blocked if the memory self-refresh mode is active at that
4806 * moment. So to make sure the plane gets truly disabled, disable
4807 * first the self-refresh mode. The self-refresh enable bit in turn
4808 * will be checked/applied by the HW only at the next frame start
4809 * event which is after the vblank start event, so we need to have a
4810 * wait-for-vblank between disabling the plane and the pipe.
4811 */
4812 if (HAS_GMCH_DISPLAY(dev))
4813 intel_set_memory_cxsr(dev_priv, false);
4814
4815 mutex_lock(&dev->struct_mutex);
4816 if (dev_priv->fbc.crtc == intel_crtc)
4817 intel_fbc_disable(dev);
4818 mutex_unlock(&dev->struct_mutex);
4819
4820 /*
4821 * FIXME IPS should be fine as long as one plane is
4822 * enabled, but in practice it seems to have problems
4823 * when going from primary only to sprite only and vice
4824 * versa.
4825 */
4826 hsw_disable_ips(intel_crtc);
4827 }
4828
4829 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4830 {
4831 struct drm_device *dev = crtc->dev;
4832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4833 int pipe = intel_crtc->pipe;
4834
4835 intel_enable_primary_hw_plane(crtc->primary, crtc);
4836 intel_enable_sprite_planes(crtc);
4837 intel_crtc_update_cursor(crtc, true);
4838
4839 intel_post_enable_primary(crtc);
4840
4841 /*
4842 * FIXME: Once we grow proper nuclear flip support out of this we need
4843 * to compute the mask of flip planes precisely. For the time being
4844 * consider this a flip to a NULL plane.
4845 */
4846 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4847 }
4848
4849 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4850 {
4851 struct drm_device *dev = crtc->dev;
4852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4853 struct intel_plane *intel_plane;
4854 int pipe = intel_crtc->pipe;
4855
4856 intel_crtc_wait_for_pending_flips(crtc);
4857
4858 intel_pre_disable_primary(crtc);
4859
4860 intel_crtc_dpms_overlay_disable(intel_crtc);
4861 for_each_intel_plane(dev, intel_plane) {
4862 if (intel_plane->pipe == pipe) {
4863 struct drm_crtc *from = intel_plane->base.crtc;
4864
4865 intel_plane->disable_plane(&intel_plane->base,
4866 from ?: crtc, true);
4867 }
4868 }
4869
4870 /*
4871 * FIXME: Once we grow proper nuclear flip support out of this we need
4872 * to compute the mask of flip planes precisely. For the time being
4873 * consider this a flip to a NULL plane.
4874 */
4875 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4876 }
4877
4878 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4879 {
4880 struct drm_device *dev = crtc->dev;
4881 struct drm_i915_private *dev_priv = dev->dev_private;
4882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4883 struct intel_encoder *encoder;
4884 int pipe = intel_crtc->pipe;
4885
4886 WARN_ON(!crtc->state->enable);
4887
4888 if (intel_crtc->active)
4889 return;
4890
4891 if (intel_crtc->config->has_pch_encoder)
4892 intel_prepare_shared_dpll(intel_crtc);
4893
4894 if (intel_crtc->config->has_dp_encoder)
4895 intel_dp_set_m_n(intel_crtc, M1_N1);
4896
4897 intel_set_pipe_timings(intel_crtc);
4898
4899 if (intel_crtc->config->has_pch_encoder) {
4900 intel_cpu_transcoder_set_m_n(intel_crtc,
4901 &intel_crtc->config->fdi_m_n, NULL);
4902 }
4903
4904 ironlake_set_pipeconf(crtc);
4905
4906 intel_crtc->active = true;
4907
4908 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4909 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4910
4911 for_each_encoder_on_crtc(dev, crtc, encoder)
4912 if (encoder->pre_enable)
4913 encoder->pre_enable(encoder);
4914
4915 if (intel_crtc->config->has_pch_encoder) {
4916 /* Note: FDI PLL enabling _must_ be done before we enable the
4917 * cpu pipes, hence this is separate from all the other fdi/pch
4918 * enabling. */
4919 ironlake_fdi_pll_enable(intel_crtc);
4920 } else {
4921 assert_fdi_tx_disabled(dev_priv, pipe);
4922 assert_fdi_rx_disabled(dev_priv, pipe);
4923 }
4924
4925 ironlake_pfit_enable(intel_crtc);
4926
4927 /*
4928 * On ILK+ LUT must be loaded before the pipe is running but with
4929 * clocks enabled
4930 */
4931 intel_crtc_load_lut(crtc);
4932
4933 intel_update_watermarks(crtc);
4934 intel_enable_pipe(intel_crtc);
4935
4936 if (intel_crtc->config->has_pch_encoder)
4937 ironlake_pch_enable(crtc);
4938
4939 assert_vblank_disabled(crtc);
4940 drm_crtc_vblank_on(crtc);
4941
4942 for_each_encoder_on_crtc(dev, crtc, encoder)
4943 encoder->enable(encoder);
4944
4945 if (HAS_PCH_CPT(dev))
4946 cpt_verify_modeset(dev, intel_crtc->pipe);
4947 }
4948
4949 /* IPS only exists on ULT machines and is tied to pipe A. */
4950 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4951 {
4952 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4953 }
4954
4955 /*
4956 * This implements the workaround described in the "notes" section of the mode
4957 * set sequence documentation. When going from no pipes or single pipe to
4958 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4959 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4960 */
4961 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4962 {
4963 struct drm_device *dev = crtc->base.dev;
4964 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4965
4966 /* We want to get the other_active_crtc only if there's only 1 other
4967 * active crtc. */
4968 for_each_intel_crtc(dev, crtc_it) {
4969 if (!crtc_it->active || crtc_it == crtc)
4970 continue;
4971
4972 if (other_active_crtc)
4973 return;
4974
4975 other_active_crtc = crtc_it;
4976 }
4977 if (!other_active_crtc)
4978 return;
4979
4980 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4981 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4982 }
4983
4984 static void haswell_crtc_enable(struct drm_crtc *crtc)
4985 {
4986 struct drm_device *dev = crtc->dev;
4987 struct drm_i915_private *dev_priv = dev->dev_private;
4988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4989 struct intel_encoder *encoder;
4990 int pipe = intel_crtc->pipe;
4991
4992 WARN_ON(!crtc->state->enable);
4993
4994 if (intel_crtc->active)
4995 return;
4996
4997 if (intel_crtc_to_shared_dpll(intel_crtc))
4998 intel_enable_shared_dpll(intel_crtc);
4999
5000 if (intel_crtc->config->has_dp_encoder)
5001 intel_dp_set_m_n(intel_crtc, M1_N1);
5002
5003 intel_set_pipe_timings(intel_crtc);
5004
5005 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5006 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5007 intel_crtc->config->pixel_multiplier - 1);
5008 }
5009
5010 if (intel_crtc->config->has_pch_encoder) {
5011 intel_cpu_transcoder_set_m_n(intel_crtc,
5012 &intel_crtc->config->fdi_m_n, NULL);
5013 }
5014
5015 haswell_set_pipeconf(crtc);
5016
5017 intel_set_pipe_csc(crtc);
5018
5019 intel_crtc->active = true;
5020
5021 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5022 for_each_encoder_on_crtc(dev, crtc, encoder)
5023 if (encoder->pre_enable)
5024 encoder->pre_enable(encoder);
5025
5026 if (intel_crtc->config->has_pch_encoder) {
5027 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5028 true);
5029 dev_priv->display.fdi_link_train(crtc);
5030 }
5031
5032 intel_ddi_enable_pipe_clock(intel_crtc);
5033
5034 if (INTEL_INFO(dev)->gen == 9)
5035 skylake_pfit_update(intel_crtc, 1);
5036 else if (INTEL_INFO(dev)->gen < 9)
5037 ironlake_pfit_enable(intel_crtc);
5038 else
5039 MISSING_CASE(INTEL_INFO(dev)->gen);
5040
5041 /*
5042 * On ILK+ LUT must be loaded before the pipe is running but with
5043 * clocks enabled
5044 */
5045 intel_crtc_load_lut(crtc);
5046
5047 intel_ddi_set_pipe_settings(crtc);
5048 intel_ddi_enable_transcoder_func(crtc);
5049
5050 intel_update_watermarks(crtc);
5051 intel_enable_pipe(intel_crtc);
5052
5053 if (intel_crtc->config->has_pch_encoder)
5054 lpt_pch_enable(crtc);
5055
5056 if (intel_crtc->config->dp_encoder_is_mst)
5057 intel_ddi_set_vc_payload_alloc(crtc, true);
5058
5059 assert_vblank_disabled(crtc);
5060 drm_crtc_vblank_on(crtc);
5061
5062 for_each_encoder_on_crtc(dev, crtc, encoder) {
5063 encoder->enable(encoder);
5064 intel_opregion_notify_encoder(encoder, true);
5065 }
5066
5067 /* If we change the relative order between pipe/planes enabling, we need
5068 * to change the workaround. */
5069 haswell_mode_set_planes_workaround(intel_crtc);
5070 }
5071
5072 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5073 {
5074 struct drm_device *dev = crtc->base.dev;
5075 struct drm_i915_private *dev_priv = dev->dev_private;
5076 int pipe = crtc->pipe;
5077
5078 /* To avoid upsetting the power well on haswell only disable the pfit if
5079 * it's in use. The hw state code will make sure we get this right. */
5080 if (crtc->config->pch_pfit.enabled) {
5081 I915_WRITE(PF_CTL(pipe), 0);
5082 I915_WRITE(PF_WIN_POS(pipe), 0);
5083 I915_WRITE(PF_WIN_SZ(pipe), 0);
5084 }
5085 }
5086
5087 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5088 {
5089 struct drm_device *dev = crtc->dev;
5090 struct drm_i915_private *dev_priv = dev->dev_private;
5091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5092 struct intel_encoder *encoder;
5093 int pipe = intel_crtc->pipe;
5094 u32 reg, temp;
5095
5096 if (!intel_crtc->active)
5097 return;
5098
5099 for_each_encoder_on_crtc(dev, crtc, encoder)
5100 encoder->disable(encoder);
5101
5102 drm_crtc_vblank_off(crtc);
5103 assert_vblank_disabled(crtc);
5104
5105 if (intel_crtc->config->has_pch_encoder)
5106 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5107
5108 intel_disable_pipe(intel_crtc);
5109
5110 ironlake_pfit_disable(intel_crtc);
5111
5112 if (intel_crtc->config->has_pch_encoder)
5113 ironlake_fdi_disable(crtc);
5114
5115 for_each_encoder_on_crtc(dev, crtc, encoder)
5116 if (encoder->post_disable)
5117 encoder->post_disable(encoder);
5118
5119 if (intel_crtc->config->has_pch_encoder) {
5120 ironlake_disable_pch_transcoder(dev_priv, pipe);
5121
5122 if (HAS_PCH_CPT(dev)) {
5123 /* disable TRANS_DP_CTL */
5124 reg = TRANS_DP_CTL(pipe);
5125 temp = I915_READ(reg);
5126 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5127 TRANS_DP_PORT_SEL_MASK);
5128 temp |= TRANS_DP_PORT_SEL_NONE;
5129 I915_WRITE(reg, temp);
5130
5131 /* disable DPLL_SEL */
5132 temp = I915_READ(PCH_DPLL_SEL);
5133 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5134 I915_WRITE(PCH_DPLL_SEL, temp);
5135 }
5136
5137 /* disable PCH DPLL */
5138 intel_disable_shared_dpll(intel_crtc);
5139
5140 ironlake_fdi_pll_disable(intel_crtc);
5141 }
5142
5143 intel_crtc->active = false;
5144 intel_update_watermarks(crtc);
5145
5146 mutex_lock(&dev->struct_mutex);
5147 intel_fbc_update(dev);
5148 mutex_unlock(&dev->struct_mutex);
5149 }
5150
5151 static void haswell_crtc_disable(struct drm_crtc *crtc)
5152 {
5153 struct drm_device *dev = crtc->dev;
5154 struct drm_i915_private *dev_priv = dev->dev_private;
5155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5156 struct intel_encoder *encoder;
5157 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5158
5159 if (!intel_crtc->active)
5160 return;
5161
5162 for_each_encoder_on_crtc(dev, crtc, encoder) {
5163 intel_opregion_notify_encoder(encoder, false);
5164 encoder->disable(encoder);
5165 }
5166
5167 drm_crtc_vblank_off(crtc);
5168 assert_vblank_disabled(crtc);
5169
5170 if (intel_crtc->config->has_pch_encoder)
5171 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5172 false);
5173 intel_disable_pipe(intel_crtc);
5174
5175 if (intel_crtc->config->dp_encoder_is_mst)
5176 intel_ddi_set_vc_payload_alloc(crtc, false);
5177
5178 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5179
5180 if (INTEL_INFO(dev)->gen == 9)
5181 skylake_pfit_update(intel_crtc, 0);
5182 else if (INTEL_INFO(dev)->gen < 9)
5183 ironlake_pfit_disable(intel_crtc);
5184 else
5185 MISSING_CASE(INTEL_INFO(dev)->gen);
5186
5187 intel_ddi_disable_pipe_clock(intel_crtc);
5188
5189 if (intel_crtc->config->has_pch_encoder) {
5190 lpt_disable_pch_transcoder(dev_priv);
5191 intel_ddi_fdi_disable(crtc);
5192 }
5193
5194 for_each_encoder_on_crtc(dev, crtc, encoder)
5195 if (encoder->post_disable)
5196 encoder->post_disable(encoder);
5197
5198 intel_crtc->active = false;
5199 intel_update_watermarks(crtc);
5200
5201 mutex_lock(&dev->struct_mutex);
5202 intel_fbc_update(dev);
5203 mutex_unlock(&dev->struct_mutex);
5204
5205 if (intel_crtc_to_shared_dpll(intel_crtc))
5206 intel_disable_shared_dpll(intel_crtc);
5207 }
5208
5209 static void ironlake_crtc_off(struct drm_crtc *crtc)
5210 {
5211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5212 intel_put_shared_dpll(intel_crtc);
5213 }
5214
5215
5216 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5217 {
5218 struct drm_device *dev = crtc->base.dev;
5219 struct drm_i915_private *dev_priv = dev->dev_private;
5220 struct intel_crtc_state *pipe_config = crtc->config;
5221
5222 if (!pipe_config->gmch_pfit.control)
5223 return;
5224
5225 /*
5226 * The panel fitter should only be adjusted whilst the pipe is disabled,
5227 * according to register description and PRM.
5228 */
5229 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5230 assert_pipe_disabled(dev_priv, crtc->pipe);
5231
5232 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5233 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5234
5235 /* Border color in case we don't scale up to the full screen. Black by
5236 * default, change to something else for debugging. */
5237 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5238 }
5239
5240 static enum intel_display_power_domain port_to_power_domain(enum port port)
5241 {
5242 switch (port) {
5243 case PORT_A:
5244 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5245 case PORT_B:
5246 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5247 case PORT_C:
5248 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5249 case PORT_D:
5250 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5251 default:
5252 WARN_ON_ONCE(1);
5253 return POWER_DOMAIN_PORT_OTHER;
5254 }
5255 }
5256
5257 #define for_each_power_domain(domain, mask) \
5258 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5259 if ((1 << (domain)) & (mask))
5260
5261 enum intel_display_power_domain
5262 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5263 {
5264 struct drm_device *dev = intel_encoder->base.dev;
5265 struct intel_digital_port *intel_dig_port;
5266
5267 switch (intel_encoder->type) {
5268 case INTEL_OUTPUT_UNKNOWN:
5269 /* Only DDI platforms should ever use this output type */
5270 WARN_ON_ONCE(!HAS_DDI(dev));
5271 case INTEL_OUTPUT_DISPLAYPORT:
5272 case INTEL_OUTPUT_HDMI:
5273 case INTEL_OUTPUT_EDP:
5274 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5275 return port_to_power_domain(intel_dig_port->port);
5276 case INTEL_OUTPUT_DP_MST:
5277 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5278 return port_to_power_domain(intel_dig_port->port);
5279 case INTEL_OUTPUT_ANALOG:
5280 return POWER_DOMAIN_PORT_CRT;
5281 case INTEL_OUTPUT_DSI:
5282 return POWER_DOMAIN_PORT_DSI;
5283 default:
5284 return POWER_DOMAIN_PORT_OTHER;
5285 }
5286 }
5287
5288 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5289 {
5290 struct drm_device *dev = crtc->dev;
5291 struct intel_encoder *intel_encoder;
5292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5293 enum pipe pipe = intel_crtc->pipe;
5294 unsigned long mask;
5295 enum transcoder transcoder;
5296
5297 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5298
5299 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5300 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5301 if (intel_crtc->config->pch_pfit.enabled ||
5302 intel_crtc->config->pch_pfit.force_thru)
5303 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5304
5305 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5306 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5307
5308 return mask;
5309 }
5310
5311 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5312 {
5313 struct drm_device *dev = state->dev;
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5316 struct intel_crtc *crtc;
5317
5318 /*
5319 * First get all needed power domains, then put all unneeded, to avoid
5320 * any unnecessary toggling of the power wells.
5321 */
5322 for_each_intel_crtc(dev, crtc) {
5323 enum intel_display_power_domain domain;
5324
5325 if (!crtc->base.state->enable)
5326 continue;
5327
5328 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5329
5330 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5331 intel_display_power_get(dev_priv, domain);
5332 }
5333
5334 if (dev_priv->display.modeset_global_resources)
5335 dev_priv->display.modeset_global_resources(state);
5336
5337 for_each_intel_crtc(dev, crtc) {
5338 enum intel_display_power_domain domain;
5339
5340 for_each_power_domain(domain, crtc->enabled_power_domains)
5341 intel_display_power_put(dev_priv, domain);
5342
5343 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5344 }
5345
5346 intel_display_set_init_power(dev_priv, false);
5347 }
5348
5349 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5350 {
5351 struct drm_i915_private *dev_priv = dev->dev_private;
5352 uint32_t divider;
5353 uint32_t ratio;
5354 uint32_t current_freq;
5355 int ret;
5356
5357 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5358 switch (frequency) {
5359 case 144000:
5360 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5361 ratio = BXT_DE_PLL_RATIO(60);
5362 break;
5363 case 288000:
5364 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5365 ratio = BXT_DE_PLL_RATIO(60);
5366 break;
5367 case 384000:
5368 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5369 ratio = BXT_DE_PLL_RATIO(60);
5370 break;
5371 case 576000:
5372 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5373 ratio = BXT_DE_PLL_RATIO(60);
5374 break;
5375 case 624000:
5376 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5377 ratio = BXT_DE_PLL_RATIO(65);
5378 break;
5379 case 19200:
5380 /*
5381 * Bypass frequency with DE PLL disabled. Init ratio, divider
5382 * to suppress GCC warning.
5383 */
5384 ratio = 0;
5385 divider = 0;
5386 break;
5387 default:
5388 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5389
5390 return;
5391 }
5392
5393 mutex_lock(&dev_priv->rps.hw_lock);
5394 /* Inform power controller of upcoming frequency change */
5395 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5396 0x80000000);
5397 mutex_unlock(&dev_priv->rps.hw_lock);
5398
5399 if (ret) {
5400 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5401 ret, frequency);
5402 return;
5403 }
5404
5405 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5406 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5407 current_freq = current_freq * 500 + 1000;
5408
5409 /*
5410 * DE PLL has to be disabled when
5411 * - setting to 19.2MHz (bypass, PLL isn't used)
5412 * - before setting to 624MHz (PLL needs toggling)
5413 * - before setting to any frequency from 624MHz (PLL needs toggling)
5414 */
5415 if (frequency == 19200 || frequency == 624000 ||
5416 current_freq == 624000) {
5417 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5418 /* Timeout 200us */
5419 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5420 1))
5421 DRM_ERROR("timout waiting for DE PLL unlock\n");
5422 }
5423
5424 if (frequency != 19200) {
5425 uint32_t val;
5426
5427 val = I915_READ(BXT_DE_PLL_CTL);
5428 val &= ~BXT_DE_PLL_RATIO_MASK;
5429 val |= ratio;
5430 I915_WRITE(BXT_DE_PLL_CTL, val);
5431
5432 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5433 /* Timeout 200us */
5434 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5435 DRM_ERROR("timeout waiting for DE PLL lock\n");
5436
5437 val = I915_READ(CDCLK_CTL);
5438 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5439 val |= divider;
5440 /*
5441 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5442 * enable otherwise.
5443 */
5444 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5445 if (frequency >= 500000)
5446 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5447
5448 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5449 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5450 val |= (frequency - 1000) / 500;
5451 I915_WRITE(CDCLK_CTL, val);
5452 }
5453
5454 mutex_lock(&dev_priv->rps.hw_lock);
5455 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5456 DIV_ROUND_UP(frequency, 25000));
5457 mutex_unlock(&dev_priv->rps.hw_lock);
5458
5459 if (ret) {
5460 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5461 ret, frequency);
5462 return;
5463 }
5464
5465 dev_priv->cdclk_freq = frequency;
5466 }
5467
5468 void broxton_init_cdclk(struct drm_device *dev)
5469 {
5470 struct drm_i915_private *dev_priv = dev->dev_private;
5471 uint32_t val;
5472
5473 /*
5474 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5475 * or else the reset will hang because there is no PCH to respond.
5476 * Move the handshake programming to initialization sequence.
5477 * Previously was left up to BIOS.
5478 */
5479 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5480 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5481 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5482
5483 /* Enable PG1 for cdclk */
5484 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5485
5486 /* check if cd clock is enabled */
5487 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5488 DRM_DEBUG_KMS("Display already initialized\n");
5489 return;
5490 }
5491
5492 /*
5493 * FIXME:
5494 * - The initial CDCLK needs to be read from VBT.
5495 * Need to make this change after VBT has changes for BXT.
5496 * - check if setting the max (or any) cdclk freq is really necessary
5497 * here, it belongs to modeset time
5498 */
5499 broxton_set_cdclk(dev, 624000);
5500
5501 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5502 POSTING_READ(DBUF_CTL);
5503
5504 udelay(10);
5505
5506 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5507 DRM_ERROR("DBuf power enable timeout!\n");
5508 }
5509
5510 void broxton_uninit_cdclk(struct drm_device *dev)
5511 {
5512 struct drm_i915_private *dev_priv = dev->dev_private;
5513
5514 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5515 POSTING_READ(DBUF_CTL);
5516
5517 udelay(10);
5518
5519 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5520 DRM_ERROR("DBuf power disable timeout!\n");
5521
5522 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5523 broxton_set_cdclk(dev, 19200);
5524
5525 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5526 }
5527
5528 static const struct skl_cdclk_entry {
5529 unsigned int freq;
5530 unsigned int vco;
5531 } skl_cdclk_frequencies[] = {
5532 { .freq = 308570, .vco = 8640 },
5533 { .freq = 337500, .vco = 8100 },
5534 { .freq = 432000, .vco = 8640 },
5535 { .freq = 450000, .vco = 8100 },
5536 { .freq = 540000, .vco = 8100 },
5537 { .freq = 617140, .vco = 8640 },
5538 { .freq = 675000, .vco = 8100 },
5539 };
5540
5541 static unsigned int skl_cdclk_decimal(unsigned int freq)
5542 {
5543 return (freq - 1000) / 500;
5544 }
5545
5546 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5547 {
5548 unsigned int i;
5549
5550 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5551 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5552
5553 if (e->freq == freq)
5554 return e->vco;
5555 }
5556
5557 return 8100;
5558 }
5559
5560 static void
5561 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5562 {
5563 unsigned int min_freq;
5564 u32 val;
5565
5566 /* select the minimum CDCLK before enabling DPLL 0 */
5567 val = I915_READ(CDCLK_CTL);
5568 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5569 val |= CDCLK_FREQ_337_308;
5570
5571 if (required_vco == 8640)
5572 min_freq = 308570;
5573 else
5574 min_freq = 337500;
5575
5576 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5577
5578 I915_WRITE(CDCLK_CTL, val);
5579 POSTING_READ(CDCLK_CTL);
5580
5581 /*
5582 * We always enable DPLL0 with the lowest link rate possible, but still
5583 * taking into account the VCO required to operate the eDP panel at the
5584 * desired frequency. The usual DP link rates operate with a VCO of
5585 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5586 * The modeset code is responsible for the selection of the exact link
5587 * rate later on, with the constraint of choosing a frequency that
5588 * works with required_vco.
5589 */
5590 val = I915_READ(DPLL_CTRL1);
5591
5592 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5593 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5594 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5595 if (required_vco == 8640)
5596 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5597 SKL_DPLL0);
5598 else
5599 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5600 SKL_DPLL0);
5601
5602 I915_WRITE(DPLL_CTRL1, val);
5603 POSTING_READ(DPLL_CTRL1);
5604
5605 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5606
5607 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5608 DRM_ERROR("DPLL0 not locked\n");
5609 }
5610
5611 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5612 {
5613 int ret;
5614 u32 val;
5615
5616 /* inform PCU we want to change CDCLK */
5617 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5618 mutex_lock(&dev_priv->rps.hw_lock);
5619 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5620 mutex_unlock(&dev_priv->rps.hw_lock);
5621
5622 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5623 }
5624
5625 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5626 {
5627 unsigned int i;
5628
5629 for (i = 0; i < 15; i++) {
5630 if (skl_cdclk_pcu_ready(dev_priv))
5631 return true;
5632 udelay(10);
5633 }
5634
5635 return false;
5636 }
5637
5638 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5639 {
5640 u32 freq_select, pcu_ack;
5641
5642 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5643
5644 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5645 DRM_ERROR("failed to inform PCU about cdclk change\n");
5646 return;
5647 }
5648
5649 /* set CDCLK_CTL */
5650 switch(freq) {
5651 case 450000:
5652 case 432000:
5653 freq_select = CDCLK_FREQ_450_432;
5654 pcu_ack = 1;
5655 break;
5656 case 540000:
5657 freq_select = CDCLK_FREQ_540;
5658 pcu_ack = 2;
5659 break;
5660 case 308570:
5661 case 337500:
5662 default:
5663 freq_select = CDCLK_FREQ_337_308;
5664 pcu_ack = 0;
5665 break;
5666 case 617140:
5667 case 675000:
5668 freq_select = CDCLK_FREQ_675_617;
5669 pcu_ack = 3;
5670 break;
5671 }
5672
5673 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5674 POSTING_READ(CDCLK_CTL);
5675
5676 /* inform PCU of the change */
5677 mutex_lock(&dev_priv->rps.hw_lock);
5678 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5679 mutex_unlock(&dev_priv->rps.hw_lock);
5680 }
5681
5682 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5683 {
5684 /* disable DBUF power */
5685 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5686 POSTING_READ(DBUF_CTL);
5687
5688 udelay(10);
5689
5690 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5691 DRM_ERROR("DBuf power disable timeout\n");
5692
5693 /* disable DPLL0 */
5694 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5695 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5696 DRM_ERROR("Couldn't disable DPLL0\n");
5697
5698 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5699 }
5700
5701 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5702 {
5703 u32 val;
5704 unsigned int required_vco;
5705
5706 /* enable PCH reset handshake */
5707 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5708 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5709
5710 /* enable PG1 and Misc I/O */
5711 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5712
5713 /* DPLL0 already enabed !? */
5714 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5715 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5716 return;
5717 }
5718
5719 /* enable DPLL0 */
5720 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5721 skl_dpll0_enable(dev_priv, required_vco);
5722
5723 /* set CDCLK to the frequency the BIOS chose */
5724 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5725
5726 /* enable DBUF power */
5727 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5728 POSTING_READ(DBUF_CTL);
5729
5730 udelay(10);
5731
5732 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5733 DRM_ERROR("DBuf power enable timeout\n");
5734 }
5735
5736 /* returns HPLL frequency in kHz */
5737 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5738 {
5739 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5740
5741 /* Obtain SKU information */
5742 mutex_lock(&dev_priv->sb_lock);
5743 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5744 CCK_FUSE_HPLL_FREQ_MASK;
5745 mutex_unlock(&dev_priv->sb_lock);
5746
5747 return vco_freq[hpll_freq] * 1000;
5748 }
5749
5750 static void vlv_update_cdclk(struct drm_device *dev)
5751 {
5752 struct drm_i915_private *dev_priv = dev->dev_private;
5753
5754 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5755 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5756 dev_priv->cdclk_freq);
5757
5758 /*
5759 * Program the gmbus_freq based on the cdclk frequency.
5760 * BSpec erroneously claims we should aim for 4MHz, but
5761 * in fact 1MHz is the correct frequency.
5762 */
5763 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5764 }
5765
5766 /* Adjust CDclk dividers to allow high res or save power if possible */
5767 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5768 {
5769 struct drm_i915_private *dev_priv = dev->dev_private;
5770 u32 val, cmd;
5771
5772 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5773 != dev_priv->cdclk_freq);
5774
5775 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5776 cmd = 2;
5777 else if (cdclk == 266667)
5778 cmd = 1;
5779 else
5780 cmd = 0;
5781
5782 mutex_lock(&dev_priv->rps.hw_lock);
5783 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5784 val &= ~DSPFREQGUAR_MASK;
5785 val |= (cmd << DSPFREQGUAR_SHIFT);
5786 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5787 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5788 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5789 50)) {
5790 DRM_ERROR("timed out waiting for CDclk change\n");
5791 }
5792 mutex_unlock(&dev_priv->rps.hw_lock);
5793
5794 mutex_lock(&dev_priv->sb_lock);
5795
5796 if (cdclk == 400000) {
5797 u32 divider;
5798
5799 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5800
5801 /* adjust cdclk divider */
5802 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5803 val &= ~DISPLAY_FREQUENCY_VALUES;
5804 val |= divider;
5805 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5806
5807 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5808 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5809 50))
5810 DRM_ERROR("timed out waiting for CDclk change\n");
5811 }
5812
5813 /* adjust self-refresh exit latency value */
5814 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5815 val &= ~0x7f;
5816
5817 /*
5818 * For high bandwidth configs, we set a higher latency in the bunit
5819 * so that the core display fetch happens in time to avoid underruns.
5820 */
5821 if (cdclk == 400000)
5822 val |= 4500 / 250; /* 4.5 usec */
5823 else
5824 val |= 3000 / 250; /* 3.0 usec */
5825 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5826
5827 mutex_unlock(&dev_priv->sb_lock);
5828
5829 vlv_update_cdclk(dev);
5830 }
5831
5832 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5833 {
5834 struct drm_i915_private *dev_priv = dev->dev_private;
5835 u32 val, cmd;
5836
5837 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5838 != dev_priv->cdclk_freq);
5839
5840 switch (cdclk) {
5841 case 333333:
5842 case 320000:
5843 case 266667:
5844 case 200000:
5845 break;
5846 default:
5847 MISSING_CASE(cdclk);
5848 return;
5849 }
5850
5851 /*
5852 * Specs are full of misinformation, but testing on actual
5853 * hardware has shown that we just need to write the desired
5854 * CCK divider into the Punit register.
5855 */
5856 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5857
5858 mutex_lock(&dev_priv->rps.hw_lock);
5859 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5860 val &= ~DSPFREQGUAR_MASK_CHV;
5861 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5862 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5863 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5864 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5865 50)) {
5866 DRM_ERROR("timed out waiting for CDclk change\n");
5867 }
5868 mutex_unlock(&dev_priv->rps.hw_lock);
5869
5870 vlv_update_cdclk(dev);
5871 }
5872
5873 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5874 int max_pixclk)
5875 {
5876 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5877 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5878
5879 /*
5880 * Really only a few cases to deal with, as only 4 CDclks are supported:
5881 * 200MHz
5882 * 267MHz
5883 * 320/333MHz (depends on HPLL freq)
5884 * 400MHz (VLV only)
5885 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5886 * of the lower bin and adjust if needed.
5887 *
5888 * We seem to get an unstable or solid color picture at 200MHz.
5889 * Not sure what's wrong. For now use 200MHz only when all pipes
5890 * are off.
5891 */
5892 if (!IS_CHERRYVIEW(dev_priv) &&
5893 max_pixclk > freq_320*limit/100)
5894 return 400000;
5895 else if (max_pixclk > 266667*limit/100)
5896 return freq_320;
5897 else if (max_pixclk > 0)
5898 return 266667;
5899 else
5900 return 200000;
5901 }
5902
5903 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5904 int max_pixclk)
5905 {
5906 /*
5907 * FIXME:
5908 * - remove the guardband, it's not needed on BXT
5909 * - set 19.2MHz bypass frequency if there are no active pipes
5910 */
5911 if (max_pixclk > 576000*9/10)
5912 return 624000;
5913 else if (max_pixclk > 384000*9/10)
5914 return 576000;
5915 else if (max_pixclk > 288000*9/10)
5916 return 384000;
5917 else if (max_pixclk > 144000*9/10)
5918 return 288000;
5919 else
5920 return 144000;
5921 }
5922
5923 /* Compute the max pixel clock for new configuration. Uses atomic state if
5924 * that's non-NULL, look at current state otherwise. */
5925 static int intel_mode_max_pixclk(struct drm_device *dev,
5926 struct drm_atomic_state *state)
5927 {
5928 struct intel_crtc *intel_crtc;
5929 struct intel_crtc_state *crtc_state;
5930 int max_pixclk = 0;
5931
5932 for_each_intel_crtc(dev, intel_crtc) {
5933 if (state)
5934 crtc_state =
5935 intel_atomic_get_crtc_state(state, intel_crtc);
5936 else
5937 crtc_state = intel_crtc->config;
5938 if (IS_ERR(crtc_state))
5939 return PTR_ERR(crtc_state);
5940
5941 if (!crtc_state->base.enable)
5942 continue;
5943
5944 max_pixclk = max(max_pixclk,
5945 crtc_state->base.adjusted_mode.crtc_clock);
5946 }
5947
5948 return max_pixclk;
5949 }
5950
5951 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5952 {
5953 struct drm_i915_private *dev_priv = to_i915(state->dev);
5954 struct drm_crtc *crtc;
5955 struct drm_crtc_state *crtc_state;
5956 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5957 int cdclk, i;
5958
5959 if (max_pixclk < 0)
5960 return max_pixclk;
5961
5962 if (IS_VALLEYVIEW(dev_priv))
5963 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5964 else
5965 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5966
5967 if (cdclk == dev_priv->cdclk_freq)
5968 return 0;
5969
5970 /* add all active pipes to the state */
5971 for_each_crtc(state->dev, crtc) {
5972 if (!crtc->state->enable)
5973 continue;
5974
5975 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5976 if (IS_ERR(crtc_state))
5977 return PTR_ERR(crtc_state);
5978 }
5979
5980 /* disable/enable all currently active pipes while we change cdclk */
5981 for_each_crtc_in_state(state, crtc, crtc_state, i)
5982 if (crtc_state->enable)
5983 crtc_state->mode_changed = true;
5984
5985 return 0;
5986 }
5987
5988 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5989 {
5990 unsigned int credits, default_credits;
5991
5992 if (IS_CHERRYVIEW(dev_priv))
5993 default_credits = PFI_CREDIT(12);
5994 else
5995 default_credits = PFI_CREDIT(8);
5996
5997 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5998 /* CHV suggested value is 31 or 63 */
5999 if (IS_CHERRYVIEW(dev_priv))
6000 credits = PFI_CREDIT_31;
6001 else
6002 credits = PFI_CREDIT(15);
6003 } else {
6004 credits = default_credits;
6005 }
6006
6007 /*
6008 * WA - write default credits before re-programming
6009 * FIXME: should we also set the resend bit here?
6010 */
6011 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6012 default_credits);
6013
6014 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6015 credits | PFI_CREDIT_RESEND);
6016
6017 /*
6018 * FIXME is this guaranteed to clear
6019 * immediately or should we poll for it?
6020 */
6021 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6022 }
6023
6024 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
6025 {
6026 struct drm_device *dev = old_state->dev;
6027 struct drm_i915_private *dev_priv = dev->dev_private;
6028 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
6029 int req_cdclk;
6030
6031 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6032 * never fail. */
6033 if (WARN_ON(max_pixclk < 0))
6034 return;
6035
6036 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
6037
6038 if (req_cdclk != dev_priv->cdclk_freq) {
6039 /*
6040 * FIXME: We can end up here with all power domains off, yet
6041 * with a CDCLK frequency other than the minimum. To account
6042 * for this take the PIPE-A power domain, which covers the HW
6043 * blocks needed for the following programming. This can be
6044 * removed once it's guaranteed that we get here either with
6045 * the minimum CDCLK set, or the required power domains
6046 * enabled.
6047 */
6048 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6049
6050 if (IS_CHERRYVIEW(dev))
6051 cherryview_set_cdclk(dev, req_cdclk);
6052 else
6053 valleyview_set_cdclk(dev, req_cdclk);
6054
6055 vlv_program_pfi_credits(dev_priv);
6056
6057 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6058 }
6059 }
6060
6061 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6062 {
6063 struct drm_device *dev = crtc->dev;
6064 struct drm_i915_private *dev_priv = to_i915(dev);
6065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6066 struct intel_encoder *encoder;
6067 int pipe = intel_crtc->pipe;
6068 bool is_dsi;
6069
6070 WARN_ON(!crtc->state->enable);
6071
6072 if (intel_crtc->active)
6073 return;
6074
6075 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6076
6077 if (!is_dsi) {
6078 if (IS_CHERRYVIEW(dev))
6079 chv_prepare_pll(intel_crtc, intel_crtc->config);
6080 else
6081 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6082 }
6083
6084 if (intel_crtc->config->has_dp_encoder)
6085 intel_dp_set_m_n(intel_crtc, M1_N1);
6086
6087 intel_set_pipe_timings(intel_crtc);
6088
6089 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6090 struct drm_i915_private *dev_priv = dev->dev_private;
6091
6092 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6093 I915_WRITE(CHV_CANVAS(pipe), 0);
6094 }
6095
6096 i9xx_set_pipeconf(intel_crtc);
6097
6098 intel_crtc->active = true;
6099
6100 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6101
6102 for_each_encoder_on_crtc(dev, crtc, encoder)
6103 if (encoder->pre_pll_enable)
6104 encoder->pre_pll_enable(encoder);
6105
6106 if (!is_dsi) {
6107 if (IS_CHERRYVIEW(dev))
6108 chv_enable_pll(intel_crtc, intel_crtc->config);
6109 else
6110 vlv_enable_pll(intel_crtc, intel_crtc->config);
6111 }
6112
6113 for_each_encoder_on_crtc(dev, crtc, encoder)
6114 if (encoder->pre_enable)
6115 encoder->pre_enable(encoder);
6116
6117 i9xx_pfit_enable(intel_crtc);
6118
6119 intel_crtc_load_lut(crtc);
6120
6121 intel_update_watermarks(crtc);
6122 intel_enable_pipe(intel_crtc);
6123
6124 assert_vblank_disabled(crtc);
6125 drm_crtc_vblank_on(crtc);
6126
6127 for_each_encoder_on_crtc(dev, crtc, encoder)
6128 encoder->enable(encoder);
6129 }
6130
6131 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6132 {
6133 struct drm_device *dev = crtc->base.dev;
6134 struct drm_i915_private *dev_priv = dev->dev_private;
6135
6136 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6137 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6138 }
6139
6140 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6141 {
6142 struct drm_device *dev = crtc->dev;
6143 struct drm_i915_private *dev_priv = to_i915(dev);
6144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6145 struct intel_encoder *encoder;
6146 int pipe = intel_crtc->pipe;
6147
6148 WARN_ON(!crtc->state->enable);
6149
6150 if (intel_crtc->active)
6151 return;
6152
6153 i9xx_set_pll_dividers(intel_crtc);
6154
6155 if (intel_crtc->config->has_dp_encoder)
6156 intel_dp_set_m_n(intel_crtc, M1_N1);
6157
6158 intel_set_pipe_timings(intel_crtc);
6159
6160 i9xx_set_pipeconf(intel_crtc);
6161
6162 intel_crtc->active = true;
6163
6164 if (!IS_GEN2(dev))
6165 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6166
6167 for_each_encoder_on_crtc(dev, crtc, encoder)
6168 if (encoder->pre_enable)
6169 encoder->pre_enable(encoder);
6170
6171 i9xx_enable_pll(intel_crtc);
6172
6173 i9xx_pfit_enable(intel_crtc);
6174
6175 intel_crtc_load_lut(crtc);
6176
6177 intel_update_watermarks(crtc);
6178 intel_enable_pipe(intel_crtc);
6179
6180 assert_vblank_disabled(crtc);
6181 drm_crtc_vblank_on(crtc);
6182
6183 for_each_encoder_on_crtc(dev, crtc, encoder)
6184 encoder->enable(encoder);
6185 }
6186
6187 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6188 {
6189 struct drm_device *dev = crtc->base.dev;
6190 struct drm_i915_private *dev_priv = dev->dev_private;
6191
6192 if (!crtc->config->gmch_pfit.control)
6193 return;
6194
6195 assert_pipe_disabled(dev_priv, crtc->pipe);
6196
6197 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6198 I915_READ(PFIT_CONTROL));
6199 I915_WRITE(PFIT_CONTROL, 0);
6200 }
6201
6202 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6203 {
6204 struct drm_device *dev = crtc->dev;
6205 struct drm_i915_private *dev_priv = dev->dev_private;
6206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6207 struct intel_encoder *encoder;
6208 int pipe = intel_crtc->pipe;
6209
6210 if (!intel_crtc->active)
6211 return;
6212
6213 /*
6214 * On gen2 planes are double buffered but the pipe isn't, so we must
6215 * wait for planes to fully turn off before disabling the pipe.
6216 * We also need to wait on all gmch platforms because of the
6217 * self-refresh mode constraint explained above.
6218 */
6219 intel_wait_for_vblank(dev, pipe);
6220
6221 for_each_encoder_on_crtc(dev, crtc, encoder)
6222 encoder->disable(encoder);
6223
6224 drm_crtc_vblank_off(crtc);
6225 assert_vblank_disabled(crtc);
6226
6227 intel_disable_pipe(intel_crtc);
6228
6229 i9xx_pfit_disable(intel_crtc);
6230
6231 for_each_encoder_on_crtc(dev, crtc, encoder)
6232 if (encoder->post_disable)
6233 encoder->post_disable(encoder);
6234
6235 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6236 if (IS_CHERRYVIEW(dev))
6237 chv_disable_pll(dev_priv, pipe);
6238 else if (IS_VALLEYVIEW(dev))
6239 vlv_disable_pll(dev_priv, pipe);
6240 else
6241 i9xx_disable_pll(intel_crtc);
6242 }
6243
6244 if (!IS_GEN2(dev))
6245 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6246
6247 intel_crtc->active = false;
6248 intel_update_watermarks(crtc);
6249
6250 mutex_lock(&dev->struct_mutex);
6251 intel_fbc_update(dev);
6252 mutex_unlock(&dev->struct_mutex);
6253 }
6254
6255 static void i9xx_crtc_off(struct drm_crtc *crtc)
6256 {
6257 }
6258
6259 /* Master function to enable/disable CRTC and corresponding power wells */
6260 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6261 {
6262 struct drm_device *dev = crtc->dev;
6263 struct drm_i915_private *dev_priv = dev->dev_private;
6264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6265 enum intel_display_power_domain domain;
6266 unsigned long domains;
6267
6268 if (enable) {
6269 if (!intel_crtc->active) {
6270 domains = get_crtc_power_domains(crtc);
6271 for_each_power_domain(domain, domains)
6272 intel_display_power_get(dev_priv, domain);
6273 intel_crtc->enabled_power_domains = domains;
6274
6275 dev_priv->display.crtc_enable(crtc);
6276 intel_crtc_enable_planes(crtc);
6277 }
6278 } else {
6279 if (intel_crtc->active) {
6280 intel_crtc_disable_planes(crtc);
6281 dev_priv->display.crtc_disable(crtc);
6282
6283 domains = intel_crtc->enabled_power_domains;
6284 for_each_power_domain(domain, domains)
6285 intel_display_power_put(dev_priv, domain);
6286 intel_crtc->enabled_power_domains = 0;
6287 }
6288 }
6289 }
6290
6291 /**
6292 * Sets the power management mode of the pipe and plane.
6293 */
6294 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6295 {
6296 struct drm_device *dev = crtc->dev;
6297 struct intel_encoder *intel_encoder;
6298 bool enable = false;
6299
6300 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6301 enable |= intel_encoder->connectors_active;
6302
6303 intel_crtc_control(crtc, enable);
6304
6305 crtc->state->active = enable;
6306 }
6307
6308 static void intel_crtc_disable(struct drm_crtc *crtc)
6309 {
6310 struct drm_device *dev = crtc->dev;
6311 struct drm_connector *connector;
6312 struct drm_i915_private *dev_priv = dev->dev_private;
6313
6314 /* crtc should still be enabled when we disable it. */
6315 WARN_ON(!crtc->state->enable);
6316
6317 intel_crtc_disable_planes(crtc);
6318 dev_priv->display.crtc_disable(crtc);
6319 dev_priv->display.off(crtc);
6320
6321 drm_plane_helper_disable(crtc->primary);
6322
6323 /* Update computed state. */
6324 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6325 if (!connector->encoder || !connector->encoder->crtc)
6326 continue;
6327
6328 if (connector->encoder->crtc != crtc)
6329 continue;
6330
6331 connector->dpms = DRM_MODE_DPMS_OFF;
6332 to_intel_encoder(connector->encoder)->connectors_active = false;
6333 }
6334 }
6335
6336 void intel_encoder_destroy(struct drm_encoder *encoder)
6337 {
6338 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6339
6340 drm_encoder_cleanup(encoder);
6341 kfree(intel_encoder);
6342 }
6343
6344 /* Simple dpms helper for encoders with just one connector, no cloning and only
6345 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6346 * state of the entire output pipe. */
6347 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6348 {
6349 if (mode == DRM_MODE_DPMS_ON) {
6350 encoder->connectors_active = true;
6351
6352 intel_crtc_update_dpms(encoder->base.crtc);
6353 } else {
6354 encoder->connectors_active = false;
6355
6356 intel_crtc_update_dpms(encoder->base.crtc);
6357 }
6358 }
6359
6360 /* Cross check the actual hw state with our own modeset state tracking (and it's
6361 * internal consistency). */
6362 static void intel_connector_check_state(struct intel_connector *connector)
6363 {
6364 if (connector->get_hw_state(connector)) {
6365 struct intel_encoder *encoder = connector->encoder;
6366 struct drm_crtc *crtc;
6367 bool encoder_enabled;
6368 enum pipe pipe;
6369
6370 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6371 connector->base.base.id,
6372 connector->base.name);
6373
6374 /* there is no real hw state for MST connectors */
6375 if (connector->mst_port)
6376 return;
6377
6378 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6379 "wrong connector dpms state\n");
6380 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6381 "active connector not linked to encoder\n");
6382
6383 if (encoder) {
6384 I915_STATE_WARN(!encoder->connectors_active,
6385 "encoder->connectors_active not set\n");
6386
6387 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6388 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6389 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6390 return;
6391
6392 crtc = encoder->base.crtc;
6393
6394 I915_STATE_WARN(!crtc->state->enable,
6395 "crtc not enabled\n");
6396 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6397 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6398 "encoder active on the wrong pipe\n");
6399 }
6400 }
6401 }
6402
6403 int intel_connector_init(struct intel_connector *connector)
6404 {
6405 struct drm_connector_state *connector_state;
6406
6407 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6408 if (!connector_state)
6409 return -ENOMEM;
6410
6411 connector->base.state = connector_state;
6412 return 0;
6413 }
6414
6415 struct intel_connector *intel_connector_alloc(void)
6416 {
6417 struct intel_connector *connector;
6418
6419 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6420 if (!connector)
6421 return NULL;
6422
6423 if (intel_connector_init(connector) < 0) {
6424 kfree(connector);
6425 return NULL;
6426 }
6427
6428 return connector;
6429 }
6430
6431 /* Even simpler default implementation, if there's really no special case to
6432 * consider. */
6433 void intel_connector_dpms(struct drm_connector *connector, int mode)
6434 {
6435 /* All the simple cases only support two dpms states. */
6436 if (mode != DRM_MODE_DPMS_ON)
6437 mode = DRM_MODE_DPMS_OFF;
6438
6439 if (mode == connector->dpms)
6440 return;
6441
6442 connector->dpms = mode;
6443
6444 /* Only need to change hw state when actually enabled */
6445 if (connector->encoder)
6446 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6447
6448 intel_modeset_check_state(connector->dev);
6449 }
6450
6451 /* Simple connector->get_hw_state implementation for encoders that support only
6452 * one connector and no cloning and hence the encoder state determines the state
6453 * of the connector. */
6454 bool intel_connector_get_hw_state(struct intel_connector *connector)
6455 {
6456 enum pipe pipe = 0;
6457 struct intel_encoder *encoder = connector->encoder;
6458
6459 return encoder->get_hw_state(encoder, &pipe);
6460 }
6461
6462 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6463 {
6464 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6465 return crtc_state->fdi_lanes;
6466
6467 return 0;
6468 }
6469
6470 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6471 struct intel_crtc_state *pipe_config)
6472 {
6473 struct drm_atomic_state *state = pipe_config->base.state;
6474 struct intel_crtc *other_crtc;
6475 struct intel_crtc_state *other_crtc_state;
6476
6477 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6478 pipe_name(pipe), pipe_config->fdi_lanes);
6479 if (pipe_config->fdi_lanes > 4) {
6480 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6481 pipe_name(pipe), pipe_config->fdi_lanes);
6482 return -EINVAL;
6483 }
6484
6485 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6486 if (pipe_config->fdi_lanes > 2) {
6487 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6488 pipe_config->fdi_lanes);
6489 return -EINVAL;
6490 } else {
6491 return 0;
6492 }
6493 }
6494
6495 if (INTEL_INFO(dev)->num_pipes == 2)
6496 return 0;
6497
6498 /* Ivybridge 3 pipe is really complicated */
6499 switch (pipe) {
6500 case PIPE_A:
6501 return 0;
6502 case PIPE_B:
6503 if (pipe_config->fdi_lanes <= 2)
6504 return 0;
6505
6506 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6507 other_crtc_state =
6508 intel_atomic_get_crtc_state(state, other_crtc);
6509 if (IS_ERR(other_crtc_state))
6510 return PTR_ERR(other_crtc_state);
6511
6512 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6513 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6514 pipe_name(pipe), pipe_config->fdi_lanes);
6515 return -EINVAL;
6516 }
6517 return 0;
6518 case PIPE_C:
6519 if (pipe_config->fdi_lanes > 2) {
6520 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6521 pipe_name(pipe), pipe_config->fdi_lanes);
6522 return -EINVAL;
6523 }
6524
6525 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6526 other_crtc_state =
6527 intel_atomic_get_crtc_state(state, other_crtc);
6528 if (IS_ERR(other_crtc_state))
6529 return PTR_ERR(other_crtc_state);
6530
6531 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6532 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6533 return -EINVAL;
6534 }
6535 return 0;
6536 default:
6537 BUG();
6538 }
6539 }
6540
6541 #define RETRY 1
6542 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6543 struct intel_crtc_state *pipe_config)
6544 {
6545 struct drm_device *dev = intel_crtc->base.dev;
6546 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6547 int lane, link_bw, fdi_dotclock, ret;
6548 bool needs_recompute = false;
6549
6550 retry:
6551 /* FDI is a binary signal running at ~2.7GHz, encoding
6552 * each output octet as 10 bits. The actual frequency
6553 * is stored as a divider into a 100MHz clock, and the
6554 * mode pixel clock is stored in units of 1KHz.
6555 * Hence the bw of each lane in terms of the mode signal
6556 * is:
6557 */
6558 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6559
6560 fdi_dotclock = adjusted_mode->crtc_clock;
6561
6562 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6563 pipe_config->pipe_bpp);
6564
6565 pipe_config->fdi_lanes = lane;
6566
6567 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6568 link_bw, &pipe_config->fdi_m_n);
6569
6570 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6571 intel_crtc->pipe, pipe_config);
6572 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6573 pipe_config->pipe_bpp -= 2*3;
6574 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6575 pipe_config->pipe_bpp);
6576 needs_recompute = true;
6577 pipe_config->bw_constrained = true;
6578
6579 goto retry;
6580 }
6581
6582 if (needs_recompute)
6583 return RETRY;
6584
6585 return ret;
6586 }
6587
6588 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6589 struct intel_crtc_state *pipe_config)
6590 {
6591 pipe_config->ips_enabled = i915.enable_ips &&
6592 hsw_crtc_supports_ips(crtc) &&
6593 pipe_config->pipe_bpp <= 24;
6594 }
6595
6596 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6597 struct intel_crtc_state *pipe_config)
6598 {
6599 struct drm_device *dev = crtc->base.dev;
6600 struct drm_i915_private *dev_priv = dev->dev_private;
6601 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6602 int ret;
6603
6604 /* FIXME should check pixel clock limits on all platforms */
6605 if (INTEL_INFO(dev)->gen < 4) {
6606 int clock_limit =
6607 dev_priv->display.get_display_clock_speed(dev);
6608
6609 /*
6610 * Enable pixel doubling when the dot clock
6611 * is > 90% of the (display) core speed.
6612 *
6613 * GDG double wide on either pipe,
6614 * otherwise pipe A only.
6615 */
6616 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6617 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6618 clock_limit *= 2;
6619 pipe_config->double_wide = true;
6620 }
6621
6622 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6623 return -EINVAL;
6624 }
6625
6626 /*
6627 * Pipe horizontal size must be even in:
6628 * - DVO ganged mode
6629 * - LVDS dual channel mode
6630 * - Double wide pipe
6631 */
6632 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6633 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6634 pipe_config->pipe_src_w &= ~1;
6635
6636 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6637 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6638 */
6639 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6640 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6641 return -EINVAL;
6642
6643 if (HAS_IPS(dev))
6644 hsw_compute_ips_config(crtc, pipe_config);
6645
6646 if (pipe_config->has_pch_encoder)
6647 return ironlake_fdi_compute_config(crtc, pipe_config);
6648
6649 /* FIXME: remove below call once atomic mode set is place and all crtc
6650 * related checks called from atomic_crtc_check function */
6651 ret = 0;
6652 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6653 crtc, pipe_config->base.state);
6654 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6655
6656 return ret;
6657 }
6658
6659 static int skylake_get_display_clock_speed(struct drm_device *dev)
6660 {
6661 struct drm_i915_private *dev_priv = to_i915(dev);
6662 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6663 uint32_t cdctl = I915_READ(CDCLK_CTL);
6664 uint32_t linkrate;
6665
6666 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6667 WARN(1, "LCPLL1 not enabled\n");
6668 return 24000; /* 24MHz is the cd freq with NSSC ref */
6669 }
6670
6671 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6672 return 540000;
6673
6674 linkrate = (I915_READ(DPLL_CTRL1) &
6675 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6676
6677 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6678 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6679 /* vco 8640 */
6680 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6681 case CDCLK_FREQ_450_432:
6682 return 432000;
6683 case CDCLK_FREQ_337_308:
6684 return 308570;
6685 case CDCLK_FREQ_675_617:
6686 return 617140;
6687 default:
6688 WARN(1, "Unknown cd freq selection\n");
6689 }
6690 } else {
6691 /* vco 8100 */
6692 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6693 case CDCLK_FREQ_450_432:
6694 return 450000;
6695 case CDCLK_FREQ_337_308:
6696 return 337500;
6697 case CDCLK_FREQ_675_617:
6698 return 675000;
6699 default:
6700 WARN(1, "Unknown cd freq selection\n");
6701 }
6702 }
6703
6704 /* error case, do as if DPLL0 isn't enabled */
6705 return 24000;
6706 }
6707
6708 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6709 {
6710 struct drm_i915_private *dev_priv = dev->dev_private;
6711 uint32_t lcpll = I915_READ(LCPLL_CTL);
6712 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6713
6714 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6715 return 800000;
6716 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6717 return 450000;
6718 else if (freq == LCPLL_CLK_FREQ_450)
6719 return 450000;
6720 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6721 return 540000;
6722 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6723 return 337500;
6724 else
6725 return 675000;
6726 }
6727
6728 static int haswell_get_display_clock_speed(struct drm_device *dev)
6729 {
6730 struct drm_i915_private *dev_priv = dev->dev_private;
6731 uint32_t lcpll = I915_READ(LCPLL_CTL);
6732 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6733
6734 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6735 return 800000;
6736 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6737 return 450000;
6738 else if (freq == LCPLL_CLK_FREQ_450)
6739 return 450000;
6740 else if (IS_HSW_ULT(dev))
6741 return 337500;
6742 else
6743 return 540000;
6744 }
6745
6746 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6747 {
6748 struct drm_i915_private *dev_priv = dev->dev_private;
6749 u32 val;
6750 int divider;
6751
6752 if (dev_priv->hpll_freq == 0)
6753 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6754
6755 mutex_lock(&dev_priv->sb_lock);
6756 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6757 mutex_unlock(&dev_priv->sb_lock);
6758
6759 divider = val & DISPLAY_FREQUENCY_VALUES;
6760
6761 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6762 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6763 "cdclk change in progress\n");
6764
6765 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6766 }
6767
6768 static int ilk_get_display_clock_speed(struct drm_device *dev)
6769 {
6770 return 450000;
6771 }
6772
6773 static int i945_get_display_clock_speed(struct drm_device *dev)
6774 {
6775 return 400000;
6776 }
6777
6778 static int i915_get_display_clock_speed(struct drm_device *dev)
6779 {
6780 return 333333;
6781 }
6782
6783 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6784 {
6785 return 200000;
6786 }
6787
6788 static int pnv_get_display_clock_speed(struct drm_device *dev)
6789 {
6790 u16 gcfgc = 0;
6791
6792 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6793
6794 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6795 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6796 return 266667;
6797 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6798 return 333333;
6799 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6800 return 444444;
6801 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6802 return 200000;
6803 default:
6804 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6805 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6806 return 133333;
6807 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6808 return 166667;
6809 }
6810 }
6811
6812 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6813 {
6814 u16 gcfgc = 0;
6815
6816 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6817
6818 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6819 return 133333;
6820 else {
6821 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6822 case GC_DISPLAY_CLOCK_333_MHZ:
6823 return 333333;
6824 default:
6825 case GC_DISPLAY_CLOCK_190_200_MHZ:
6826 return 190000;
6827 }
6828 }
6829 }
6830
6831 static int i865_get_display_clock_speed(struct drm_device *dev)
6832 {
6833 return 266667;
6834 }
6835
6836 static int i855_get_display_clock_speed(struct drm_device *dev)
6837 {
6838 u16 hpllcc = 0;
6839 /* Assume that the hardware is in the high speed state. This
6840 * should be the default.
6841 */
6842 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6843 case GC_CLOCK_133_200:
6844 case GC_CLOCK_100_200:
6845 return 200000;
6846 case GC_CLOCK_166_250:
6847 return 250000;
6848 case GC_CLOCK_100_133:
6849 return 133333;
6850 }
6851
6852 /* Shouldn't happen */
6853 return 0;
6854 }
6855
6856 static int i830_get_display_clock_speed(struct drm_device *dev)
6857 {
6858 return 133333;
6859 }
6860
6861 static void
6862 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6863 {
6864 while (*num > DATA_LINK_M_N_MASK ||
6865 *den > DATA_LINK_M_N_MASK) {
6866 *num >>= 1;
6867 *den >>= 1;
6868 }
6869 }
6870
6871 static void compute_m_n(unsigned int m, unsigned int n,
6872 uint32_t *ret_m, uint32_t *ret_n)
6873 {
6874 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6875 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6876 intel_reduce_m_n_ratio(ret_m, ret_n);
6877 }
6878
6879 void
6880 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6881 int pixel_clock, int link_clock,
6882 struct intel_link_m_n *m_n)
6883 {
6884 m_n->tu = 64;
6885
6886 compute_m_n(bits_per_pixel * pixel_clock,
6887 link_clock * nlanes * 8,
6888 &m_n->gmch_m, &m_n->gmch_n);
6889
6890 compute_m_n(pixel_clock, link_clock,
6891 &m_n->link_m, &m_n->link_n);
6892 }
6893
6894 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6895 {
6896 if (i915.panel_use_ssc >= 0)
6897 return i915.panel_use_ssc != 0;
6898 return dev_priv->vbt.lvds_use_ssc
6899 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6900 }
6901
6902 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6903 int num_connectors)
6904 {
6905 struct drm_device *dev = crtc_state->base.crtc->dev;
6906 struct drm_i915_private *dev_priv = dev->dev_private;
6907 int refclk;
6908
6909 WARN_ON(!crtc_state->base.state);
6910
6911 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6912 refclk = 100000;
6913 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6914 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6915 refclk = dev_priv->vbt.lvds_ssc_freq;
6916 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6917 } else if (!IS_GEN2(dev)) {
6918 refclk = 96000;
6919 } else {
6920 refclk = 48000;
6921 }
6922
6923 return refclk;
6924 }
6925
6926 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6927 {
6928 return (1 << dpll->n) << 16 | dpll->m2;
6929 }
6930
6931 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6932 {
6933 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6934 }
6935
6936 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6937 struct intel_crtc_state *crtc_state,
6938 intel_clock_t *reduced_clock)
6939 {
6940 struct drm_device *dev = crtc->base.dev;
6941 u32 fp, fp2 = 0;
6942
6943 if (IS_PINEVIEW(dev)) {
6944 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6945 if (reduced_clock)
6946 fp2 = pnv_dpll_compute_fp(reduced_clock);
6947 } else {
6948 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6949 if (reduced_clock)
6950 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6951 }
6952
6953 crtc_state->dpll_hw_state.fp0 = fp;
6954
6955 crtc->lowfreq_avail = false;
6956 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6957 reduced_clock) {
6958 crtc_state->dpll_hw_state.fp1 = fp2;
6959 crtc->lowfreq_avail = true;
6960 } else {
6961 crtc_state->dpll_hw_state.fp1 = fp;
6962 }
6963 }
6964
6965 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6966 pipe)
6967 {
6968 u32 reg_val;
6969
6970 /*
6971 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6972 * and set it to a reasonable value instead.
6973 */
6974 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6975 reg_val &= 0xffffff00;
6976 reg_val |= 0x00000030;
6977 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6978
6979 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6980 reg_val &= 0x8cffffff;
6981 reg_val = 0x8c000000;
6982 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6983
6984 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6985 reg_val &= 0xffffff00;
6986 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6987
6988 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6989 reg_val &= 0x00ffffff;
6990 reg_val |= 0xb0000000;
6991 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6992 }
6993
6994 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6995 struct intel_link_m_n *m_n)
6996 {
6997 struct drm_device *dev = crtc->base.dev;
6998 struct drm_i915_private *dev_priv = dev->dev_private;
6999 int pipe = crtc->pipe;
7000
7001 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7002 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7003 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7004 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7005 }
7006
7007 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7008 struct intel_link_m_n *m_n,
7009 struct intel_link_m_n *m2_n2)
7010 {
7011 struct drm_device *dev = crtc->base.dev;
7012 struct drm_i915_private *dev_priv = dev->dev_private;
7013 int pipe = crtc->pipe;
7014 enum transcoder transcoder = crtc->config->cpu_transcoder;
7015
7016 if (INTEL_INFO(dev)->gen >= 5) {
7017 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7018 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7019 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7020 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7021 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7022 * for gen < 8) and if DRRS is supported (to make sure the
7023 * registers are not unnecessarily accessed).
7024 */
7025 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7026 crtc->config->has_drrs) {
7027 I915_WRITE(PIPE_DATA_M2(transcoder),
7028 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7029 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7030 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7031 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7032 }
7033 } else {
7034 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7035 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7036 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7037 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7038 }
7039 }
7040
7041 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7042 {
7043 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7044
7045 if (m_n == M1_N1) {
7046 dp_m_n = &crtc->config->dp_m_n;
7047 dp_m2_n2 = &crtc->config->dp_m2_n2;
7048 } else if (m_n == M2_N2) {
7049
7050 /*
7051 * M2_N2 registers are not supported. Hence m2_n2 divider value
7052 * needs to be programmed into M1_N1.
7053 */
7054 dp_m_n = &crtc->config->dp_m2_n2;
7055 } else {
7056 DRM_ERROR("Unsupported divider value\n");
7057 return;
7058 }
7059
7060 if (crtc->config->has_pch_encoder)
7061 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7062 else
7063 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7064 }
7065
7066 static void vlv_update_pll(struct intel_crtc *crtc,
7067 struct intel_crtc_state *pipe_config)
7068 {
7069 u32 dpll, dpll_md;
7070
7071 /*
7072 * Enable DPIO clock input. We should never disable the reference
7073 * clock for pipe B, since VGA hotplug / manual detection depends
7074 * on it.
7075 */
7076 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7077 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7078 /* We should never disable this, set it here for state tracking */
7079 if (crtc->pipe == PIPE_B)
7080 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7081 dpll |= DPLL_VCO_ENABLE;
7082 pipe_config->dpll_hw_state.dpll = dpll;
7083
7084 dpll_md = (pipe_config->pixel_multiplier - 1)
7085 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7086 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7087 }
7088
7089 static void vlv_prepare_pll(struct intel_crtc *crtc,
7090 const struct intel_crtc_state *pipe_config)
7091 {
7092 struct drm_device *dev = crtc->base.dev;
7093 struct drm_i915_private *dev_priv = dev->dev_private;
7094 int pipe = crtc->pipe;
7095 u32 mdiv;
7096 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7097 u32 coreclk, reg_val;
7098
7099 mutex_lock(&dev_priv->sb_lock);
7100
7101 bestn = pipe_config->dpll.n;
7102 bestm1 = pipe_config->dpll.m1;
7103 bestm2 = pipe_config->dpll.m2;
7104 bestp1 = pipe_config->dpll.p1;
7105 bestp2 = pipe_config->dpll.p2;
7106
7107 /* See eDP HDMI DPIO driver vbios notes doc */
7108
7109 /* PLL B needs special handling */
7110 if (pipe == PIPE_B)
7111 vlv_pllb_recal_opamp(dev_priv, pipe);
7112
7113 /* Set up Tx target for periodic Rcomp update */
7114 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7115
7116 /* Disable target IRef on PLL */
7117 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7118 reg_val &= 0x00ffffff;
7119 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7120
7121 /* Disable fast lock */
7122 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7123
7124 /* Set idtafcrecal before PLL is enabled */
7125 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7126 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7127 mdiv |= ((bestn << DPIO_N_SHIFT));
7128 mdiv |= (1 << DPIO_K_SHIFT);
7129
7130 /*
7131 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7132 * but we don't support that).
7133 * Note: don't use the DAC post divider as it seems unstable.
7134 */
7135 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7136 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7137
7138 mdiv |= DPIO_ENABLE_CALIBRATION;
7139 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7140
7141 /* Set HBR and RBR LPF coefficients */
7142 if (pipe_config->port_clock == 162000 ||
7143 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7144 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7145 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7146 0x009f0003);
7147 else
7148 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7149 0x00d0000f);
7150
7151 if (pipe_config->has_dp_encoder) {
7152 /* Use SSC source */
7153 if (pipe == PIPE_A)
7154 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7155 0x0df40000);
7156 else
7157 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7158 0x0df70000);
7159 } else { /* HDMI or VGA */
7160 /* Use bend source */
7161 if (pipe == PIPE_A)
7162 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7163 0x0df70000);
7164 else
7165 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7166 0x0df40000);
7167 }
7168
7169 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7170 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7171 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7172 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7173 coreclk |= 0x01000000;
7174 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7175
7176 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7177 mutex_unlock(&dev_priv->sb_lock);
7178 }
7179
7180 static void chv_update_pll(struct intel_crtc *crtc,
7181 struct intel_crtc_state *pipe_config)
7182 {
7183 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7184 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7185 DPLL_VCO_ENABLE;
7186 if (crtc->pipe != PIPE_A)
7187 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7188
7189 pipe_config->dpll_hw_state.dpll_md =
7190 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7191 }
7192
7193 static void chv_prepare_pll(struct intel_crtc *crtc,
7194 const struct intel_crtc_state *pipe_config)
7195 {
7196 struct drm_device *dev = crtc->base.dev;
7197 struct drm_i915_private *dev_priv = dev->dev_private;
7198 int pipe = crtc->pipe;
7199 int dpll_reg = DPLL(crtc->pipe);
7200 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7201 u32 loopfilter, tribuf_calcntr;
7202 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7203 u32 dpio_val;
7204 int vco;
7205
7206 bestn = pipe_config->dpll.n;
7207 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7208 bestm1 = pipe_config->dpll.m1;
7209 bestm2 = pipe_config->dpll.m2 >> 22;
7210 bestp1 = pipe_config->dpll.p1;
7211 bestp2 = pipe_config->dpll.p2;
7212 vco = pipe_config->dpll.vco;
7213 dpio_val = 0;
7214 loopfilter = 0;
7215
7216 /*
7217 * Enable Refclk and SSC
7218 */
7219 I915_WRITE(dpll_reg,
7220 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7221
7222 mutex_lock(&dev_priv->sb_lock);
7223
7224 /* p1 and p2 divider */
7225 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7226 5 << DPIO_CHV_S1_DIV_SHIFT |
7227 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7228 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7229 1 << DPIO_CHV_K_DIV_SHIFT);
7230
7231 /* Feedback post-divider - m2 */
7232 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7233
7234 /* Feedback refclk divider - n and m1 */
7235 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7236 DPIO_CHV_M1_DIV_BY_2 |
7237 1 << DPIO_CHV_N_DIV_SHIFT);
7238
7239 /* M2 fraction division */
7240 if (bestm2_frac)
7241 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7242
7243 /* M2 fraction division enable */
7244 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7245 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7246 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7247 if (bestm2_frac)
7248 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7249 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7250
7251 /* Program digital lock detect threshold */
7252 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7253 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7254 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7255 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7256 if (!bestm2_frac)
7257 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7258 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7259
7260 /* Loop filter */
7261 if (vco == 5400000) {
7262 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7263 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7264 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7265 tribuf_calcntr = 0x9;
7266 } else if (vco <= 6200000) {
7267 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7268 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7269 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7270 tribuf_calcntr = 0x9;
7271 } else if (vco <= 6480000) {
7272 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7273 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7274 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7275 tribuf_calcntr = 0x8;
7276 } else {
7277 /* Not supported. Apply the same limits as in the max case */
7278 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7279 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7280 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7281 tribuf_calcntr = 0;
7282 }
7283 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7284
7285 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7286 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7287 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7288 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7289
7290 /* AFC Recal */
7291 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7292 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7293 DPIO_AFC_RECAL);
7294
7295 mutex_unlock(&dev_priv->sb_lock);
7296 }
7297
7298 /**
7299 * vlv_force_pll_on - forcibly enable just the PLL
7300 * @dev_priv: i915 private structure
7301 * @pipe: pipe PLL to enable
7302 * @dpll: PLL configuration
7303 *
7304 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7305 * in cases where we need the PLL enabled even when @pipe is not going to
7306 * be enabled.
7307 */
7308 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7309 const struct dpll *dpll)
7310 {
7311 struct intel_crtc *crtc =
7312 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7313 struct intel_crtc_state pipe_config = {
7314 .base.crtc = &crtc->base,
7315 .pixel_multiplier = 1,
7316 .dpll = *dpll,
7317 };
7318
7319 if (IS_CHERRYVIEW(dev)) {
7320 chv_update_pll(crtc, &pipe_config);
7321 chv_prepare_pll(crtc, &pipe_config);
7322 chv_enable_pll(crtc, &pipe_config);
7323 } else {
7324 vlv_update_pll(crtc, &pipe_config);
7325 vlv_prepare_pll(crtc, &pipe_config);
7326 vlv_enable_pll(crtc, &pipe_config);
7327 }
7328 }
7329
7330 /**
7331 * vlv_force_pll_off - forcibly disable just the PLL
7332 * @dev_priv: i915 private structure
7333 * @pipe: pipe PLL to disable
7334 *
7335 * Disable the PLL for @pipe. To be used in cases where we need
7336 * the PLL enabled even when @pipe is not going to be enabled.
7337 */
7338 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7339 {
7340 if (IS_CHERRYVIEW(dev))
7341 chv_disable_pll(to_i915(dev), pipe);
7342 else
7343 vlv_disable_pll(to_i915(dev), pipe);
7344 }
7345
7346 static void i9xx_update_pll(struct intel_crtc *crtc,
7347 struct intel_crtc_state *crtc_state,
7348 intel_clock_t *reduced_clock,
7349 int num_connectors)
7350 {
7351 struct drm_device *dev = crtc->base.dev;
7352 struct drm_i915_private *dev_priv = dev->dev_private;
7353 u32 dpll;
7354 bool is_sdvo;
7355 struct dpll *clock = &crtc_state->dpll;
7356
7357 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7358
7359 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7360 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7361
7362 dpll = DPLL_VGA_MODE_DIS;
7363
7364 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7365 dpll |= DPLLB_MODE_LVDS;
7366 else
7367 dpll |= DPLLB_MODE_DAC_SERIAL;
7368
7369 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7370 dpll |= (crtc_state->pixel_multiplier - 1)
7371 << SDVO_MULTIPLIER_SHIFT_HIRES;
7372 }
7373
7374 if (is_sdvo)
7375 dpll |= DPLL_SDVO_HIGH_SPEED;
7376
7377 if (crtc_state->has_dp_encoder)
7378 dpll |= DPLL_SDVO_HIGH_SPEED;
7379
7380 /* compute bitmask from p1 value */
7381 if (IS_PINEVIEW(dev))
7382 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7383 else {
7384 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7385 if (IS_G4X(dev) && reduced_clock)
7386 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7387 }
7388 switch (clock->p2) {
7389 case 5:
7390 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7391 break;
7392 case 7:
7393 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7394 break;
7395 case 10:
7396 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7397 break;
7398 case 14:
7399 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7400 break;
7401 }
7402 if (INTEL_INFO(dev)->gen >= 4)
7403 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7404
7405 if (crtc_state->sdvo_tv_clock)
7406 dpll |= PLL_REF_INPUT_TVCLKINBC;
7407 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7408 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7409 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7410 else
7411 dpll |= PLL_REF_INPUT_DREFCLK;
7412
7413 dpll |= DPLL_VCO_ENABLE;
7414 crtc_state->dpll_hw_state.dpll = dpll;
7415
7416 if (INTEL_INFO(dev)->gen >= 4) {
7417 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7418 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7419 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7420 }
7421 }
7422
7423 static void i8xx_update_pll(struct intel_crtc *crtc,
7424 struct intel_crtc_state *crtc_state,
7425 intel_clock_t *reduced_clock,
7426 int num_connectors)
7427 {
7428 struct drm_device *dev = crtc->base.dev;
7429 struct drm_i915_private *dev_priv = dev->dev_private;
7430 u32 dpll;
7431 struct dpll *clock = &crtc_state->dpll;
7432
7433 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7434
7435 dpll = DPLL_VGA_MODE_DIS;
7436
7437 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7438 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7439 } else {
7440 if (clock->p1 == 2)
7441 dpll |= PLL_P1_DIVIDE_BY_TWO;
7442 else
7443 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7444 if (clock->p2 == 4)
7445 dpll |= PLL_P2_DIVIDE_BY_4;
7446 }
7447
7448 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7449 dpll |= DPLL_DVO_2X_MODE;
7450
7451 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7452 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7453 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7454 else
7455 dpll |= PLL_REF_INPUT_DREFCLK;
7456
7457 dpll |= DPLL_VCO_ENABLE;
7458 crtc_state->dpll_hw_state.dpll = dpll;
7459 }
7460
7461 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7462 {
7463 struct drm_device *dev = intel_crtc->base.dev;
7464 struct drm_i915_private *dev_priv = dev->dev_private;
7465 enum pipe pipe = intel_crtc->pipe;
7466 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7467 struct drm_display_mode *adjusted_mode =
7468 &intel_crtc->config->base.adjusted_mode;
7469 uint32_t crtc_vtotal, crtc_vblank_end;
7470 int vsyncshift = 0;
7471
7472 /* We need to be careful not to changed the adjusted mode, for otherwise
7473 * the hw state checker will get angry at the mismatch. */
7474 crtc_vtotal = adjusted_mode->crtc_vtotal;
7475 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7476
7477 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7478 /* the chip adds 2 halflines automatically */
7479 crtc_vtotal -= 1;
7480 crtc_vblank_end -= 1;
7481
7482 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7483 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7484 else
7485 vsyncshift = adjusted_mode->crtc_hsync_start -
7486 adjusted_mode->crtc_htotal / 2;
7487 if (vsyncshift < 0)
7488 vsyncshift += adjusted_mode->crtc_htotal;
7489 }
7490
7491 if (INTEL_INFO(dev)->gen > 3)
7492 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7493
7494 I915_WRITE(HTOTAL(cpu_transcoder),
7495 (adjusted_mode->crtc_hdisplay - 1) |
7496 ((adjusted_mode->crtc_htotal - 1) << 16));
7497 I915_WRITE(HBLANK(cpu_transcoder),
7498 (adjusted_mode->crtc_hblank_start - 1) |
7499 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7500 I915_WRITE(HSYNC(cpu_transcoder),
7501 (adjusted_mode->crtc_hsync_start - 1) |
7502 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7503
7504 I915_WRITE(VTOTAL(cpu_transcoder),
7505 (adjusted_mode->crtc_vdisplay - 1) |
7506 ((crtc_vtotal - 1) << 16));
7507 I915_WRITE(VBLANK(cpu_transcoder),
7508 (adjusted_mode->crtc_vblank_start - 1) |
7509 ((crtc_vblank_end - 1) << 16));
7510 I915_WRITE(VSYNC(cpu_transcoder),
7511 (adjusted_mode->crtc_vsync_start - 1) |
7512 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7513
7514 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7515 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7516 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7517 * bits. */
7518 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7519 (pipe == PIPE_B || pipe == PIPE_C))
7520 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7521
7522 /* pipesrc controls the size that is scaled from, which should
7523 * always be the user's requested size.
7524 */
7525 I915_WRITE(PIPESRC(pipe),
7526 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7527 (intel_crtc->config->pipe_src_h - 1));
7528 }
7529
7530 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7531 struct intel_crtc_state *pipe_config)
7532 {
7533 struct drm_device *dev = crtc->base.dev;
7534 struct drm_i915_private *dev_priv = dev->dev_private;
7535 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7536 uint32_t tmp;
7537
7538 tmp = I915_READ(HTOTAL(cpu_transcoder));
7539 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7540 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7541 tmp = I915_READ(HBLANK(cpu_transcoder));
7542 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7543 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7544 tmp = I915_READ(HSYNC(cpu_transcoder));
7545 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7546 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7547
7548 tmp = I915_READ(VTOTAL(cpu_transcoder));
7549 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7550 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7551 tmp = I915_READ(VBLANK(cpu_transcoder));
7552 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7553 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7554 tmp = I915_READ(VSYNC(cpu_transcoder));
7555 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7556 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7557
7558 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7559 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7560 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7561 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7562 }
7563
7564 tmp = I915_READ(PIPESRC(crtc->pipe));
7565 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7566 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7567
7568 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7569 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7570 }
7571
7572 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7573 struct intel_crtc_state *pipe_config)
7574 {
7575 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7576 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7577 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7578 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7579
7580 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7581 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7582 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7583 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7584
7585 mode->flags = pipe_config->base.adjusted_mode.flags;
7586
7587 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7588 mode->flags |= pipe_config->base.adjusted_mode.flags;
7589 }
7590
7591 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7592 {
7593 struct drm_device *dev = intel_crtc->base.dev;
7594 struct drm_i915_private *dev_priv = dev->dev_private;
7595 uint32_t pipeconf;
7596
7597 pipeconf = 0;
7598
7599 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7600 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7601 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7602
7603 if (intel_crtc->config->double_wide)
7604 pipeconf |= PIPECONF_DOUBLE_WIDE;
7605
7606 /* only g4x and later have fancy bpc/dither controls */
7607 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7608 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7609 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7610 pipeconf |= PIPECONF_DITHER_EN |
7611 PIPECONF_DITHER_TYPE_SP;
7612
7613 switch (intel_crtc->config->pipe_bpp) {
7614 case 18:
7615 pipeconf |= PIPECONF_6BPC;
7616 break;
7617 case 24:
7618 pipeconf |= PIPECONF_8BPC;
7619 break;
7620 case 30:
7621 pipeconf |= PIPECONF_10BPC;
7622 break;
7623 default:
7624 /* Case prevented by intel_choose_pipe_bpp_dither. */
7625 BUG();
7626 }
7627 }
7628
7629 if (HAS_PIPE_CXSR(dev)) {
7630 if (intel_crtc->lowfreq_avail) {
7631 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7632 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7633 } else {
7634 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7635 }
7636 }
7637
7638 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7639 if (INTEL_INFO(dev)->gen < 4 ||
7640 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7641 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7642 else
7643 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7644 } else
7645 pipeconf |= PIPECONF_PROGRESSIVE;
7646
7647 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7648 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7649
7650 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7651 POSTING_READ(PIPECONF(intel_crtc->pipe));
7652 }
7653
7654 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7655 struct intel_crtc_state *crtc_state)
7656 {
7657 struct drm_device *dev = crtc->base.dev;
7658 struct drm_i915_private *dev_priv = dev->dev_private;
7659 int refclk, num_connectors = 0;
7660 intel_clock_t clock, reduced_clock;
7661 bool ok, has_reduced_clock = false;
7662 bool is_lvds = false, is_dsi = false;
7663 struct intel_encoder *encoder;
7664 const intel_limit_t *limit;
7665 struct drm_atomic_state *state = crtc_state->base.state;
7666 struct drm_connector *connector;
7667 struct drm_connector_state *connector_state;
7668 int i;
7669
7670 memset(&crtc_state->dpll_hw_state, 0,
7671 sizeof(crtc_state->dpll_hw_state));
7672
7673 for_each_connector_in_state(state, connector, connector_state, i) {
7674 if (connector_state->crtc != &crtc->base)
7675 continue;
7676
7677 encoder = to_intel_encoder(connector_state->best_encoder);
7678
7679 switch (encoder->type) {
7680 case INTEL_OUTPUT_LVDS:
7681 is_lvds = true;
7682 break;
7683 case INTEL_OUTPUT_DSI:
7684 is_dsi = true;
7685 break;
7686 default:
7687 break;
7688 }
7689
7690 num_connectors++;
7691 }
7692
7693 if (is_dsi)
7694 return 0;
7695
7696 if (!crtc_state->clock_set) {
7697 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7698
7699 /*
7700 * Returns a set of divisors for the desired target clock with
7701 * the given refclk, or FALSE. The returned values represent
7702 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7703 * 2) / p1 / p2.
7704 */
7705 limit = intel_limit(crtc_state, refclk);
7706 ok = dev_priv->display.find_dpll(limit, crtc_state,
7707 crtc_state->port_clock,
7708 refclk, NULL, &clock);
7709 if (!ok) {
7710 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7711 return -EINVAL;
7712 }
7713
7714 if (is_lvds && dev_priv->lvds_downclock_avail) {
7715 /*
7716 * Ensure we match the reduced clock's P to the target
7717 * clock. If the clocks don't match, we can't switch
7718 * the display clock by using the FP0/FP1. In such case
7719 * we will disable the LVDS downclock feature.
7720 */
7721 has_reduced_clock =
7722 dev_priv->display.find_dpll(limit, crtc_state,
7723 dev_priv->lvds_downclock,
7724 refclk, &clock,
7725 &reduced_clock);
7726 }
7727 /* Compat-code for transition, will disappear. */
7728 crtc_state->dpll.n = clock.n;
7729 crtc_state->dpll.m1 = clock.m1;
7730 crtc_state->dpll.m2 = clock.m2;
7731 crtc_state->dpll.p1 = clock.p1;
7732 crtc_state->dpll.p2 = clock.p2;
7733 }
7734
7735 if (IS_GEN2(dev)) {
7736 i8xx_update_pll(crtc, crtc_state,
7737 has_reduced_clock ? &reduced_clock : NULL,
7738 num_connectors);
7739 } else if (IS_CHERRYVIEW(dev)) {
7740 chv_update_pll(crtc, crtc_state);
7741 } else if (IS_VALLEYVIEW(dev)) {
7742 vlv_update_pll(crtc, crtc_state);
7743 } else {
7744 i9xx_update_pll(crtc, crtc_state,
7745 has_reduced_clock ? &reduced_clock : NULL,
7746 num_connectors);
7747 }
7748
7749 return 0;
7750 }
7751
7752 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7753 struct intel_crtc_state *pipe_config)
7754 {
7755 struct drm_device *dev = crtc->base.dev;
7756 struct drm_i915_private *dev_priv = dev->dev_private;
7757 uint32_t tmp;
7758
7759 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7760 return;
7761
7762 tmp = I915_READ(PFIT_CONTROL);
7763 if (!(tmp & PFIT_ENABLE))
7764 return;
7765
7766 /* Check whether the pfit is attached to our pipe. */
7767 if (INTEL_INFO(dev)->gen < 4) {
7768 if (crtc->pipe != PIPE_B)
7769 return;
7770 } else {
7771 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7772 return;
7773 }
7774
7775 pipe_config->gmch_pfit.control = tmp;
7776 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7777 if (INTEL_INFO(dev)->gen < 5)
7778 pipe_config->gmch_pfit.lvds_border_bits =
7779 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7780 }
7781
7782 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7783 struct intel_crtc_state *pipe_config)
7784 {
7785 struct drm_device *dev = crtc->base.dev;
7786 struct drm_i915_private *dev_priv = dev->dev_private;
7787 int pipe = pipe_config->cpu_transcoder;
7788 intel_clock_t clock;
7789 u32 mdiv;
7790 int refclk = 100000;
7791
7792 /* In case of MIPI DPLL will not even be used */
7793 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7794 return;
7795
7796 mutex_lock(&dev_priv->sb_lock);
7797 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7798 mutex_unlock(&dev_priv->sb_lock);
7799
7800 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7801 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7802 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7803 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7804 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7805
7806 vlv_clock(refclk, &clock);
7807
7808 /* clock.dot is the fast clock */
7809 pipe_config->port_clock = clock.dot / 5;
7810 }
7811
7812 static void
7813 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7814 struct intel_initial_plane_config *plane_config)
7815 {
7816 struct drm_device *dev = crtc->base.dev;
7817 struct drm_i915_private *dev_priv = dev->dev_private;
7818 u32 val, base, offset;
7819 int pipe = crtc->pipe, plane = crtc->plane;
7820 int fourcc, pixel_format;
7821 unsigned int aligned_height;
7822 struct drm_framebuffer *fb;
7823 struct intel_framebuffer *intel_fb;
7824
7825 val = I915_READ(DSPCNTR(plane));
7826 if (!(val & DISPLAY_PLANE_ENABLE))
7827 return;
7828
7829 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7830 if (!intel_fb) {
7831 DRM_DEBUG_KMS("failed to alloc fb\n");
7832 return;
7833 }
7834
7835 fb = &intel_fb->base;
7836
7837 if (INTEL_INFO(dev)->gen >= 4) {
7838 if (val & DISPPLANE_TILED) {
7839 plane_config->tiling = I915_TILING_X;
7840 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7841 }
7842 }
7843
7844 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7845 fourcc = i9xx_format_to_fourcc(pixel_format);
7846 fb->pixel_format = fourcc;
7847 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7848
7849 if (INTEL_INFO(dev)->gen >= 4) {
7850 if (plane_config->tiling)
7851 offset = I915_READ(DSPTILEOFF(plane));
7852 else
7853 offset = I915_READ(DSPLINOFF(plane));
7854 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7855 } else {
7856 base = I915_READ(DSPADDR(plane));
7857 }
7858 plane_config->base = base;
7859
7860 val = I915_READ(PIPESRC(pipe));
7861 fb->width = ((val >> 16) & 0xfff) + 1;
7862 fb->height = ((val >> 0) & 0xfff) + 1;
7863
7864 val = I915_READ(DSPSTRIDE(pipe));
7865 fb->pitches[0] = val & 0xffffffc0;
7866
7867 aligned_height = intel_fb_align_height(dev, fb->height,
7868 fb->pixel_format,
7869 fb->modifier[0]);
7870
7871 plane_config->size = fb->pitches[0] * aligned_height;
7872
7873 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7874 pipe_name(pipe), plane, fb->width, fb->height,
7875 fb->bits_per_pixel, base, fb->pitches[0],
7876 plane_config->size);
7877
7878 plane_config->fb = intel_fb;
7879 }
7880
7881 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7882 struct intel_crtc_state *pipe_config)
7883 {
7884 struct drm_device *dev = crtc->base.dev;
7885 struct drm_i915_private *dev_priv = dev->dev_private;
7886 int pipe = pipe_config->cpu_transcoder;
7887 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7888 intel_clock_t clock;
7889 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7890 int refclk = 100000;
7891
7892 mutex_lock(&dev_priv->sb_lock);
7893 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7894 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7895 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7896 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7897 mutex_unlock(&dev_priv->sb_lock);
7898
7899 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7900 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7901 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7902 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7903 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7904
7905 chv_clock(refclk, &clock);
7906
7907 /* clock.dot is the fast clock */
7908 pipe_config->port_clock = clock.dot / 5;
7909 }
7910
7911 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7912 struct intel_crtc_state *pipe_config)
7913 {
7914 struct drm_device *dev = crtc->base.dev;
7915 struct drm_i915_private *dev_priv = dev->dev_private;
7916 uint32_t tmp;
7917
7918 if (!intel_display_power_is_enabled(dev_priv,
7919 POWER_DOMAIN_PIPE(crtc->pipe)))
7920 return false;
7921
7922 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7923 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7924
7925 tmp = I915_READ(PIPECONF(crtc->pipe));
7926 if (!(tmp & PIPECONF_ENABLE))
7927 return false;
7928
7929 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7930 switch (tmp & PIPECONF_BPC_MASK) {
7931 case PIPECONF_6BPC:
7932 pipe_config->pipe_bpp = 18;
7933 break;
7934 case PIPECONF_8BPC:
7935 pipe_config->pipe_bpp = 24;
7936 break;
7937 case PIPECONF_10BPC:
7938 pipe_config->pipe_bpp = 30;
7939 break;
7940 default:
7941 break;
7942 }
7943 }
7944
7945 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7946 pipe_config->limited_color_range = true;
7947
7948 if (INTEL_INFO(dev)->gen < 4)
7949 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7950
7951 intel_get_pipe_timings(crtc, pipe_config);
7952
7953 i9xx_get_pfit_config(crtc, pipe_config);
7954
7955 if (INTEL_INFO(dev)->gen >= 4) {
7956 tmp = I915_READ(DPLL_MD(crtc->pipe));
7957 pipe_config->pixel_multiplier =
7958 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7959 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7960 pipe_config->dpll_hw_state.dpll_md = tmp;
7961 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7962 tmp = I915_READ(DPLL(crtc->pipe));
7963 pipe_config->pixel_multiplier =
7964 ((tmp & SDVO_MULTIPLIER_MASK)
7965 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7966 } else {
7967 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7968 * port and will be fixed up in the encoder->get_config
7969 * function. */
7970 pipe_config->pixel_multiplier = 1;
7971 }
7972 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7973 if (!IS_VALLEYVIEW(dev)) {
7974 /*
7975 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7976 * on 830. Filter it out here so that we don't
7977 * report errors due to that.
7978 */
7979 if (IS_I830(dev))
7980 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7981
7982 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7983 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7984 } else {
7985 /* Mask out read-only status bits. */
7986 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7987 DPLL_PORTC_READY_MASK |
7988 DPLL_PORTB_READY_MASK);
7989 }
7990
7991 if (IS_CHERRYVIEW(dev))
7992 chv_crtc_clock_get(crtc, pipe_config);
7993 else if (IS_VALLEYVIEW(dev))
7994 vlv_crtc_clock_get(crtc, pipe_config);
7995 else
7996 i9xx_crtc_clock_get(crtc, pipe_config);
7997
7998 return true;
7999 }
8000
8001 static void ironlake_init_pch_refclk(struct drm_device *dev)
8002 {
8003 struct drm_i915_private *dev_priv = dev->dev_private;
8004 struct intel_encoder *encoder;
8005 u32 val, final;
8006 bool has_lvds = false;
8007 bool has_cpu_edp = false;
8008 bool has_panel = false;
8009 bool has_ck505 = false;
8010 bool can_ssc = false;
8011
8012 /* We need to take the global config into account */
8013 for_each_intel_encoder(dev, encoder) {
8014 switch (encoder->type) {
8015 case INTEL_OUTPUT_LVDS:
8016 has_panel = true;
8017 has_lvds = true;
8018 break;
8019 case INTEL_OUTPUT_EDP:
8020 has_panel = true;
8021 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8022 has_cpu_edp = true;
8023 break;
8024 default:
8025 break;
8026 }
8027 }
8028
8029 if (HAS_PCH_IBX(dev)) {
8030 has_ck505 = dev_priv->vbt.display_clock_mode;
8031 can_ssc = has_ck505;
8032 } else {
8033 has_ck505 = false;
8034 can_ssc = true;
8035 }
8036
8037 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8038 has_panel, has_lvds, has_ck505);
8039
8040 /* Ironlake: try to setup display ref clock before DPLL
8041 * enabling. This is only under driver's control after
8042 * PCH B stepping, previous chipset stepping should be
8043 * ignoring this setting.
8044 */
8045 val = I915_READ(PCH_DREF_CONTROL);
8046
8047 /* As we must carefully and slowly disable/enable each source in turn,
8048 * compute the final state we want first and check if we need to
8049 * make any changes at all.
8050 */
8051 final = val;
8052 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8053 if (has_ck505)
8054 final |= DREF_NONSPREAD_CK505_ENABLE;
8055 else
8056 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8057
8058 final &= ~DREF_SSC_SOURCE_MASK;
8059 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8060 final &= ~DREF_SSC1_ENABLE;
8061
8062 if (has_panel) {
8063 final |= DREF_SSC_SOURCE_ENABLE;
8064
8065 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8066 final |= DREF_SSC1_ENABLE;
8067
8068 if (has_cpu_edp) {
8069 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8070 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8071 else
8072 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8073 } else
8074 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8075 } else {
8076 final |= DREF_SSC_SOURCE_DISABLE;
8077 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8078 }
8079
8080 if (final == val)
8081 return;
8082
8083 /* Always enable nonspread source */
8084 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8085
8086 if (has_ck505)
8087 val |= DREF_NONSPREAD_CK505_ENABLE;
8088 else
8089 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8090
8091 if (has_panel) {
8092 val &= ~DREF_SSC_SOURCE_MASK;
8093 val |= DREF_SSC_SOURCE_ENABLE;
8094
8095 /* SSC must be turned on before enabling the CPU output */
8096 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8097 DRM_DEBUG_KMS("Using SSC on panel\n");
8098 val |= DREF_SSC1_ENABLE;
8099 } else
8100 val &= ~DREF_SSC1_ENABLE;
8101
8102 /* Get SSC going before enabling the outputs */
8103 I915_WRITE(PCH_DREF_CONTROL, val);
8104 POSTING_READ(PCH_DREF_CONTROL);
8105 udelay(200);
8106
8107 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8108
8109 /* Enable CPU source on CPU attached eDP */
8110 if (has_cpu_edp) {
8111 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8112 DRM_DEBUG_KMS("Using SSC on eDP\n");
8113 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8114 } else
8115 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8116 } else
8117 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8118
8119 I915_WRITE(PCH_DREF_CONTROL, val);
8120 POSTING_READ(PCH_DREF_CONTROL);
8121 udelay(200);
8122 } else {
8123 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8124
8125 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8126
8127 /* Turn off CPU output */
8128 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8129
8130 I915_WRITE(PCH_DREF_CONTROL, val);
8131 POSTING_READ(PCH_DREF_CONTROL);
8132 udelay(200);
8133
8134 /* Turn off the SSC source */
8135 val &= ~DREF_SSC_SOURCE_MASK;
8136 val |= DREF_SSC_SOURCE_DISABLE;
8137
8138 /* Turn off SSC1 */
8139 val &= ~DREF_SSC1_ENABLE;
8140
8141 I915_WRITE(PCH_DREF_CONTROL, val);
8142 POSTING_READ(PCH_DREF_CONTROL);
8143 udelay(200);
8144 }
8145
8146 BUG_ON(val != final);
8147 }
8148
8149 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8150 {
8151 uint32_t tmp;
8152
8153 tmp = I915_READ(SOUTH_CHICKEN2);
8154 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8155 I915_WRITE(SOUTH_CHICKEN2, tmp);
8156
8157 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8158 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8159 DRM_ERROR("FDI mPHY reset assert timeout\n");
8160
8161 tmp = I915_READ(SOUTH_CHICKEN2);
8162 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8163 I915_WRITE(SOUTH_CHICKEN2, tmp);
8164
8165 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8166 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8167 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8168 }
8169
8170 /* WaMPhyProgramming:hsw */
8171 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8172 {
8173 uint32_t tmp;
8174
8175 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8176 tmp &= ~(0xFF << 24);
8177 tmp |= (0x12 << 24);
8178 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8179
8180 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8181 tmp |= (1 << 11);
8182 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8183
8184 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8185 tmp |= (1 << 11);
8186 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8187
8188 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8189 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8190 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8191
8192 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8193 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8194 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8195
8196 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8197 tmp &= ~(7 << 13);
8198 tmp |= (5 << 13);
8199 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8200
8201 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8202 tmp &= ~(7 << 13);
8203 tmp |= (5 << 13);
8204 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8205
8206 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8207 tmp &= ~0xFF;
8208 tmp |= 0x1C;
8209 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8210
8211 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8212 tmp &= ~0xFF;
8213 tmp |= 0x1C;
8214 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8215
8216 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8217 tmp &= ~(0xFF << 16);
8218 tmp |= (0x1C << 16);
8219 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8220
8221 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8222 tmp &= ~(0xFF << 16);
8223 tmp |= (0x1C << 16);
8224 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8225
8226 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8227 tmp |= (1 << 27);
8228 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8229
8230 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8231 tmp |= (1 << 27);
8232 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8233
8234 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8235 tmp &= ~(0xF << 28);
8236 tmp |= (4 << 28);
8237 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8238
8239 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8240 tmp &= ~(0xF << 28);
8241 tmp |= (4 << 28);
8242 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8243 }
8244
8245 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8246 * Programming" based on the parameters passed:
8247 * - Sequence to enable CLKOUT_DP
8248 * - Sequence to enable CLKOUT_DP without spread
8249 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8250 */
8251 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8252 bool with_fdi)
8253 {
8254 struct drm_i915_private *dev_priv = dev->dev_private;
8255 uint32_t reg, tmp;
8256
8257 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8258 with_spread = true;
8259 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8260 with_fdi, "LP PCH doesn't have FDI\n"))
8261 with_fdi = false;
8262
8263 mutex_lock(&dev_priv->sb_lock);
8264
8265 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8266 tmp &= ~SBI_SSCCTL_DISABLE;
8267 tmp |= SBI_SSCCTL_PATHALT;
8268 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8269
8270 udelay(24);
8271
8272 if (with_spread) {
8273 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8274 tmp &= ~SBI_SSCCTL_PATHALT;
8275 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8276
8277 if (with_fdi) {
8278 lpt_reset_fdi_mphy(dev_priv);
8279 lpt_program_fdi_mphy(dev_priv);
8280 }
8281 }
8282
8283 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8284 SBI_GEN0 : SBI_DBUFF0;
8285 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8286 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8287 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8288
8289 mutex_unlock(&dev_priv->sb_lock);
8290 }
8291
8292 /* Sequence to disable CLKOUT_DP */
8293 static void lpt_disable_clkout_dp(struct drm_device *dev)
8294 {
8295 struct drm_i915_private *dev_priv = dev->dev_private;
8296 uint32_t reg, tmp;
8297
8298 mutex_lock(&dev_priv->sb_lock);
8299
8300 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8301 SBI_GEN0 : SBI_DBUFF0;
8302 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8303 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8304 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8305
8306 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8307 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8308 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8309 tmp |= SBI_SSCCTL_PATHALT;
8310 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8311 udelay(32);
8312 }
8313 tmp |= SBI_SSCCTL_DISABLE;
8314 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8315 }
8316
8317 mutex_unlock(&dev_priv->sb_lock);
8318 }
8319
8320 static void lpt_init_pch_refclk(struct drm_device *dev)
8321 {
8322 struct intel_encoder *encoder;
8323 bool has_vga = false;
8324
8325 for_each_intel_encoder(dev, encoder) {
8326 switch (encoder->type) {
8327 case INTEL_OUTPUT_ANALOG:
8328 has_vga = true;
8329 break;
8330 default:
8331 break;
8332 }
8333 }
8334
8335 if (has_vga)
8336 lpt_enable_clkout_dp(dev, true, true);
8337 else
8338 lpt_disable_clkout_dp(dev);
8339 }
8340
8341 /*
8342 * Initialize reference clocks when the driver loads
8343 */
8344 void intel_init_pch_refclk(struct drm_device *dev)
8345 {
8346 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8347 ironlake_init_pch_refclk(dev);
8348 else if (HAS_PCH_LPT(dev))
8349 lpt_init_pch_refclk(dev);
8350 }
8351
8352 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8353 {
8354 struct drm_device *dev = crtc_state->base.crtc->dev;
8355 struct drm_i915_private *dev_priv = dev->dev_private;
8356 struct drm_atomic_state *state = crtc_state->base.state;
8357 struct drm_connector *connector;
8358 struct drm_connector_state *connector_state;
8359 struct intel_encoder *encoder;
8360 int num_connectors = 0, i;
8361 bool is_lvds = false;
8362
8363 for_each_connector_in_state(state, connector, connector_state, i) {
8364 if (connector_state->crtc != crtc_state->base.crtc)
8365 continue;
8366
8367 encoder = to_intel_encoder(connector_state->best_encoder);
8368
8369 switch (encoder->type) {
8370 case INTEL_OUTPUT_LVDS:
8371 is_lvds = true;
8372 break;
8373 default:
8374 break;
8375 }
8376 num_connectors++;
8377 }
8378
8379 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8380 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8381 dev_priv->vbt.lvds_ssc_freq);
8382 return dev_priv->vbt.lvds_ssc_freq;
8383 }
8384
8385 return 120000;
8386 }
8387
8388 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8389 {
8390 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8392 int pipe = intel_crtc->pipe;
8393 uint32_t val;
8394
8395 val = 0;
8396
8397 switch (intel_crtc->config->pipe_bpp) {
8398 case 18:
8399 val |= PIPECONF_6BPC;
8400 break;
8401 case 24:
8402 val |= PIPECONF_8BPC;
8403 break;
8404 case 30:
8405 val |= PIPECONF_10BPC;
8406 break;
8407 case 36:
8408 val |= PIPECONF_12BPC;
8409 break;
8410 default:
8411 /* Case prevented by intel_choose_pipe_bpp_dither. */
8412 BUG();
8413 }
8414
8415 if (intel_crtc->config->dither)
8416 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8417
8418 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8419 val |= PIPECONF_INTERLACED_ILK;
8420 else
8421 val |= PIPECONF_PROGRESSIVE;
8422
8423 if (intel_crtc->config->limited_color_range)
8424 val |= PIPECONF_COLOR_RANGE_SELECT;
8425
8426 I915_WRITE(PIPECONF(pipe), val);
8427 POSTING_READ(PIPECONF(pipe));
8428 }
8429
8430 /*
8431 * Set up the pipe CSC unit.
8432 *
8433 * Currently only full range RGB to limited range RGB conversion
8434 * is supported, but eventually this should handle various
8435 * RGB<->YCbCr scenarios as well.
8436 */
8437 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8438 {
8439 struct drm_device *dev = crtc->dev;
8440 struct drm_i915_private *dev_priv = dev->dev_private;
8441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8442 int pipe = intel_crtc->pipe;
8443 uint16_t coeff = 0x7800; /* 1.0 */
8444
8445 /*
8446 * TODO: Check what kind of values actually come out of the pipe
8447 * with these coeff/postoff values and adjust to get the best
8448 * accuracy. Perhaps we even need to take the bpc value into
8449 * consideration.
8450 */
8451
8452 if (intel_crtc->config->limited_color_range)
8453 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8454
8455 /*
8456 * GY/GU and RY/RU should be the other way around according
8457 * to BSpec, but reality doesn't agree. Just set them up in
8458 * a way that results in the correct picture.
8459 */
8460 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8461 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8462
8463 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8464 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8465
8466 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8467 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8468
8469 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8470 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8471 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8472
8473 if (INTEL_INFO(dev)->gen > 6) {
8474 uint16_t postoff = 0;
8475
8476 if (intel_crtc->config->limited_color_range)
8477 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8478
8479 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8480 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8481 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8482
8483 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8484 } else {
8485 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8486
8487 if (intel_crtc->config->limited_color_range)
8488 mode |= CSC_BLACK_SCREEN_OFFSET;
8489
8490 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8491 }
8492 }
8493
8494 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8495 {
8496 struct drm_device *dev = crtc->dev;
8497 struct drm_i915_private *dev_priv = dev->dev_private;
8498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8499 enum pipe pipe = intel_crtc->pipe;
8500 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8501 uint32_t val;
8502
8503 val = 0;
8504
8505 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8506 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8507
8508 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8509 val |= PIPECONF_INTERLACED_ILK;
8510 else
8511 val |= PIPECONF_PROGRESSIVE;
8512
8513 I915_WRITE(PIPECONF(cpu_transcoder), val);
8514 POSTING_READ(PIPECONF(cpu_transcoder));
8515
8516 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8517 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8518
8519 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8520 val = 0;
8521
8522 switch (intel_crtc->config->pipe_bpp) {
8523 case 18:
8524 val |= PIPEMISC_DITHER_6_BPC;
8525 break;
8526 case 24:
8527 val |= PIPEMISC_DITHER_8_BPC;
8528 break;
8529 case 30:
8530 val |= PIPEMISC_DITHER_10_BPC;
8531 break;
8532 case 36:
8533 val |= PIPEMISC_DITHER_12_BPC;
8534 break;
8535 default:
8536 /* Case prevented by pipe_config_set_bpp. */
8537 BUG();
8538 }
8539
8540 if (intel_crtc->config->dither)
8541 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8542
8543 I915_WRITE(PIPEMISC(pipe), val);
8544 }
8545 }
8546
8547 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8548 struct intel_crtc_state *crtc_state,
8549 intel_clock_t *clock,
8550 bool *has_reduced_clock,
8551 intel_clock_t *reduced_clock)
8552 {
8553 struct drm_device *dev = crtc->dev;
8554 struct drm_i915_private *dev_priv = dev->dev_private;
8555 int refclk;
8556 const intel_limit_t *limit;
8557 bool ret, is_lvds = false;
8558
8559 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8560
8561 refclk = ironlake_get_refclk(crtc_state);
8562
8563 /*
8564 * Returns a set of divisors for the desired target clock with the given
8565 * refclk, or FALSE. The returned values represent the clock equation:
8566 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8567 */
8568 limit = intel_limit(crtc_state, refclk);
8569 ret = dev_priv->display.find_dpll(limit, crtc_state,
8570 crtc_state->port_clock,
8571 refclk, NULL, clock);
8572 if (!ret)
8573 return false;
8574
8575 if (is_lvds && dev_priv->lvds_downclock_avail) {
8576 /*
8577 * Ensure we match the reduced clock's P to the target clock.
8578 * If the clocks don't match, we can't switch the display clock
8579 * by using the FP0/FP1. In such case we will disable the LVDS
8580 * downclock feature.
8581 */
8582 *has_reduced_clock =
8583 dev_priv->display.find_dpll(limit, crtc_state,
8584 dev_priv->lvds_downclock,
8585 refclk, clock,
8586 reduced_clock);
8587 }
8588
8589 return true;
8590 }
8591
8592 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8593 {
8594 /*
8595 * Account for spread spectrum to avoid
8596 * oversubscribing the link. Max center spread
8597 * is 2.5%; use 5% for safety's sake.
8598 */
8599 u32 bps = target_clock * bpp * 21 / 20;
8600 return DIV_ROUND_UP(bps, link_bw * 8);
8601 }
8602
8603 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8604 {
8605 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8606 }
8607
8608 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8609 struct intel_crtc_state *crtc_state,
8610 u32 *fp,
8611 intel_clock_t *reduced_clock, u32 *fp2)
8612 {
8613 struct drm_crtc *crtc = &intel_crtc->base;
8614 struct drm_device *dev = crtc->dev;
8615 struct drm_i915_private *dev_priv = dev->dev_private;
8616 struct drm_atomic_state *state = crtc_state->base.state;
8617 struct drm_connector *connector;
8618 struct drm_connector_state *connector_state;
8619 struct intel_encoder *encoder;
8620 uint32_t dpll;
8621 int factor, num_connectors = 0, i;
8622 bool is_lvds = false, is_sdvo = false;
8623
8624 for_each_connector_in_state(state, connector, connector_state, i) {
8625 if (connector_state->crtc != crtc_state->base.crtc)
8626 continue;
8627
8628 encoder = to_intel_encoder(connector_state->best_encoder);
8629
8630 switch (encoder->type) {
8631 case INTEL_OUTPUT_LVDS:
8632 is_lvds = true;
8633 break;
8634 case INTEL_OUTPUT_SDVO:
8635 case INTEL_OUTPUT_HDMI:
8636 is_sdvo = true;
8637 break;
8638 default:
8639 break;
8640 }
8641
8642 num_connectors++;
8643 }
8644
8645 /* Enable autotuning of the PLL clock (if permissible) */
8646 factor = 21;
8647 if (is_lvds) {
8648 if ((intel_panel_use_ssc(dev_priv) &&
8649 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8650 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8651 factor = 25;
8652 } else if (crtc_state->sdvo_tv_clock)
8653 factor = 20;
8654
8655 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8656 *fp |= FP_CB_TUNE;
8657
8658 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8659 *fp2 |= FP_CB_TUNE;
8660
8661 dpll = 0;
8662
8663 if (is_lvds)
8664 dpll |= DPLLB_MODE_LVDS;
8665 else
8666 dpll |= DPLLB_MODE_DAC_SERIAL;
8667
8668 dpll |= (crtc_state->pixel_multiplier - 1)
8669 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8670
8671 if (is_sdvo)
8672 dpll |= DPLL_SDVO_HIGH_SPEED;
8673 if (crtc_state->has_dp_encoder)
8674 dpll |= DPLL_SDVO_HIGH_SPEED;
8675
8676 /* compute bitmask from p1 value */
8677 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8678 /* also FPA1 */
8679 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8680
8681 switch (crtc_state->dpll.p2) {
8682 case 5:
8683 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8684 break;
8685 case 7:
8686 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8687 break;
8688 case 10:
8689 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8690 break;
8691 case 14:
8692 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8693 break;
8694 }
8695
8696 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8697 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8698 else
8699 dpll |= PLL_REF_INPUT_DREFCLK;
8700
8701 return dpll | DPLL_VCO_ENABLE;
8702 }
8703
8704 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8705 struct intel_crtc_state *crtc_state)
8706 {
8707 struct drm_device *dev = crtc->base.dev;
8708 intel_clock_t clock, reduced_clock;
8709 u32 dpll = 0, fp = 0, fp2 = 0;
8710 bool ok, has_reduced_clock = false;
8711 bool is_lvds = false;
8712 struct intel_shared_dpll *pll;
8713
8714 memset(&crtc_state->dpll_hw_state, 0,
8715 sizeof(crtc_state->dpll_hw_state));
8716
8717 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8718
8719 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8720 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8721
8722 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8723 &has_reduced_clock, &reduced_clock);
8724 if (!ok && !crtc_state->clock_set) {
8725 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8726 return -EINVAL;
8727 }
8728 /* Compat-code for transition, will disappear. */
8729 if (!crtc_state->clock_set) {
8730 crtc_state->dpll.n = clock.n;
8731 crtc_state->dpll.m1 = clock.m1;
8732 crtc_state->dpll.m2 = clock.m2;
8733 crtc_state->dpll.p1 = clock.p1;
8734 crtc_state->dpll.p2 = clock.p2;
8735 }
8736
8737 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8738 if (crtc_state->has_pch_encoder) {
8739 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8740 if (has_reduced_clock)
8741 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8742
8743 dpll = ironlake_compute_dpll(crtc, crtc_state,
8744 &fp, &reduced_clock,
8745 has_reduced_clock ? &fp2 : NULL);
8746
8747 crtc_state->dpll_hw_state.dpll = dpll;
8748 crtc_state->dpll_hw_state.fp0 = fp;
8749 if (has_reduced_clock)
8750 crtc_state->dpll_hw_state.fp1 = fp2;
8751 else
8752 crtc_state->dpll_hw_state.fp1 = fp;
8753
8754 pll = intel_get_shared_dpll(crtc, crtc_state);
8755 if (pll == NULL) {
8756 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8757 pipe_name(crtc->pipe));
8758 return -EINVAL;
8759 }
8760 }
8761
8762 if (is_lvds && has_reduced_clock)
8763 crtc->lowfreq_avail = true;
8764 else
8765 crtc->lowfreq_avail = false;
8766
8767 return 0;
8768 }
8769
8770 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8771 struct intel_link_m_n *m_n)
8772 {
8773 struct drm_device *dev = crtc->base.dev;
8774 struct drm_i915_private *dev_priv = dev->dev_private;
8775 enum pipe pipe = crtc->pipe;
8776
8777 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8778 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8779 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8780 & ~TU_SIZE_MASK;
8781 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8782 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8783 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8784 }
8785
8786 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8787 enum transcoder transcoder,
8788 struct intel_link_m_n *m_n,
8789 struct intel_link_m_n *m2_n2)
8790 {
8791 struct drm_device *dev = crtc->base.dev;
8792 struct drm_i915_private *dev_priv = dev->dev_private;
8793 enum pipe pipe = crtc->pipe;
8794
8795 if (INTEL_INFO(dev)->gen >= 5) {
8796 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8797 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8798 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8799 & ~TU_SIZE_MASK;
8800 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8801 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8802 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8803 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8804 * gen < 8) and if DRRS is supported (to make sure the
8805 * registers are not unnecessarily read).
8806 */
8807 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8808 crtc->config->has_drrs) {
8809 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8810 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8811 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8812 & ~TU_SIZE_MASK;
8813 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8814 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8815 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8816 }
8817 } else {
8818 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8819 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8820 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8821 & ~TU_SIZE_MASK;
8822 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8823 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8824 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8825 }
8826 }
8827
8828 void intel_dp_get_m_n(struct intel_crtc *crtc,
8829 struct intel_crtc_state *pipe_config)
8830 {
8831 if (pipe_config->has_pch_encoder)
8832 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8833 else
8834 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8835 &pipe_config->dp_m_n,
8836 &pipe_config->dp_m2_n2);
8837 }
8838
8839 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8840 struct intel_crtc_state *pipe_config)
8841 {
8842 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8843 &pipe_config->fdi_m_n, NULL);
8844 }
8845
8846 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8847 struct intel_crtc_state *pipe_config)
8848 {
8849 struct drm_device *dev = crtc->base.dev;
8850 struct drm_i915_private *dev_priv = dev->dev_private;
8851 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8852 uint32_t ps_ctrl = 0;
8853 int id = -1;
8854 int i;
8855
8856 /* find scaler attached to this pipe */
8857 for (i = 0; i < crtc->num_scalers; i++) {
8858 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8859 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8860 id = i;
8861 pipe_config->pch_pfit.enabled = true;
8862 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8863 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8864 break;
8865 }
8866 }
8867
8868 scaler_state->scaler_id = id;
8869 if (id >= 0) {
8870 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8871 } else {
8872 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8873 }
8874 }
8875
8876 static void
8877 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8878 struct intel_initial_plane_config *plane_config)
8879 {
8880 struct drm_device *dev = crtc->base.dev;
8881 struct drm_i915_private *dev_priv = dev->dev_private;
8882 u32 val, base, offset, stride_mult, tiling;
8883 int pipe = crtc->pipe;
8884 int fourcc, pixel_format;
8885 unsigned int aligned_height;
8886 struct drm_framebuffer *fb;
8887 struct intel_framebuffer *intel_fb;
8888
8889 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8890 if (!intel_fb) {
8891 DRM_DEBUG_KMS("failed to alloc fb\n");
8892 return;
8893 }
8894
8895 fb = &intel_fb->base;
8896
8897 val = I915_READ(PLANE_CTL(pipe, 0));
8898 if (!(val & PLANE_CTL_ENABLE))
8899 goto error;
8900
8901 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8902 fourcc = skl_format_to_fourcc(pixel_format,
8903 val & PLANE_CTL_ORDER_RGBX,
8904 val & PLANE_CTL_ALPHA_MASK);
8905 fb->pixel_format = fourcc;
8906 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8907
8908 tiling = val & PLANE_CTL_TILED_MASK;
8909 switch (tiling) {
8910 case PLANE_CTL_TILED_LINEAR:
8911 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8912 break;
8913 case PLANE_CTL_TILED_X:
8914 plane_config->tiling = I915_TILING_X;
8915 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8916 break;
8917 case PLANE_CTL_TILED_Y:
8918 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8919 break;
8920 case PLANE_CTL_TILED_YF:
8921 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8922 break;
8923 default:
8924 MISSING_CASE(tiling);
8925 goto error;
8926 }
8927
8928 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8929 plane_config->base = base;
8930
8931 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8932
8933 val = I915_READ(PLANE_SIZE(pipe, 0));
8934 fb->height = ((val >> 16) & 0xfff) + 1;
8935 fb->width = ((val >> 0) & 0x1fff) + 1;
8936
8937 val = I915_READ(PLANE_STRIDE(pipe, 0));
8938 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8939 fb->pixel_format);
8940 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8941
8942 aligned_height = intel_fb_align_height(dev, fb->height,
8943 fb->pixel_format,
8944 fb->modifier[0]);
8945
8946 plane_config->size = fb->pitches[0] * aligned_height;
8947
8948 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8949 pipe_name(pipe), fb->width, fb->height,
8950 fb->bits_per_pixel, base, fb->pitches[0],
8951 plane_config->size);
8952
8953 plane_config->fb = intel_fb;
8954 return;
8955
8956 error:
8957 kfree(fb);
8958 }
8959
8960 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8961 struct intel_crtc_state *pipe_config)
8962 {
8963 struct drm_device *dev = crtc->base.dev;
8964 struct drm_i915_private *dev_priv = dev->dev_private;
8965 uint32_t tmp;
8966
8967 tmp = I915_READ(PF_CTL(crtc->pipe));
8968
8969 if (tmp & PF_ENABLE) {
8970 pipe_config->pch_pfit.enabled = true;
8971 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8972 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8973
8974 /* We currently do not free assignements of panel fitters on
8975 * ivb/hsw (since we don't use the higher upscaling modes which
8976 * differentiates them) so just WARN about this case for now. */
8977 if (IS_GEN7(dev)) {
8978 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8979 PF_PIPE_SEL_IVB(crtc->pipe));
8980 }
8981 }
8982 }
8983
8984 static void
8985 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8986 struct intel_initial_plane_config *plane_config)
8987 {
8988 struct drm_device *dev = crtc->base.dev;
8989 struct drm_i915_private *dev_priv = dev->dev_private;
8990 u32 val, base, offset;
8991 int pipe = crtc->pipe;
8992 int fourcc, pixel_format;
8993 unsigned int aligned_height;
8994 struct drm_framebuffer *fb;
8995 struct intel_framebuffer *intel_fb;
8996
8997 val = I915_READ(DSPCNTR(pipe));
8998 if (!(val & DISPLAY_PLANE_ENABLE))
8999 return;
9000
9001 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9002 if (!intel_fb) {
9003 DRM_DEBUG_KMS("failed to alloc fb\n");
9004 return;
9005 }
9006
9007 fb = &intel_fb->base;
9008
9009 if (INTEL_INFO(dev)->gen >= 4) {
9010 if (val & DISPPLANE_TILED) {
9011 plane_config->tiling = I915_TILING_X;
9012 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9013 }
9014 }
9015
9016 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9017 fourcc = i9xx_format_to_fourcc(pixel_format);
9018 fb->pixel_format = fourcc;
9019 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9020
9021 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9022 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9023 offset = I915_READ(DSPOFFSET(pipe));
9024 } else {
9025 if (plane_config->tiling)
9026 offset = I915_READ(DSPTILEOFF(pipe));
9027 else
9028 offset = I915_READ(DSPLINOFF(pipe));
9029 }
9030 plane_config->base = base;
9031
9032 val = I915_READ(PIPESRC(pipe));
9033 fb->width = ((val >> 16) & 0xfff) + 1;
9034 fb->height = ((val >> 0) & 0xfff) + 1;
9035
9036 val = I915_READ(DSPSTRIDE(pipe));
9037 fb->pitches[0] = val & 0xffffffc0;
9038
9039 aligned_height = intel_fb_align_height(dev, fb->height,
9040 fb->pixel_format,
9041 fb->modifier[0]);
9042
9043 plane_config->size = fb->pitches[0] * aligned_height;
9044
9045 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9046 pipe_name(pipe), fb->width, fb->height,
9047 fb->bits_per_pixel, base, fb->pitches[0],
9048 plane_config->size);
9049
9050 plane_config->fb = intel_fb;
9051 }
9052
9053 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9054 struct intel_crtc_state *pipe_config)
9055 {
9056 struct drm_device *dev = crtc->base.dev;
9057 struct drm_i915_private *dev_priv = dev->dev_private;
9058 uint32_t tmp;
9059
9060 if (!intel_display_power_is_enabled(dev_priv,
9061 POWER_DOMAIN_PIPE(crtc->pipe)))
9062 return false;
9063
9064 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9065 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9066
9067 tmp = I915_READ(PIPECONF(crtc->pipe));
9068 if (!(tmp & PIPECONF_ENABLE))
9069 return false;
9070
9071 switch (tmp & PIPECONF_BPC_MASK) {
9072 case PIPECONF_6BPC:
9073 pipe_config->pipe_bpp = 18;
9074 break;
9075 case PIPECONF_8BPC:
9076 pipe_config->pipe_bpp = 24;
9077 break;
9078 case PIPECONF_10BPC:
9079 pipe_config->pipe_bpp = 30;
9080 break;
9081 case PIPECONF_12BPC:
9082 pipe_config->pipe_bpp = 36;
9083 break;
9084 default:
9085 break;
9086 }
9087
9088 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9089 pipe_config->limited_color_range = true;
9090
9091 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9092 struct intel_shared_dpll *pll;
9093
9094 pipe_config->has_pch_encoder = true;
9095
9096 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9097 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9098 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9099
9100 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9101
9102 if (HAS_PCH_IBX(dev_priv->dev)) {
9103 pipe_config->shared_dpll =
9104 (enum intel_dpll_id) crtc->pipe;
9105 } else {
9106 tmp = I915_READ(PCH_DPLL_SEL);
9107 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9108 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9109 else
9110 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9111 }
9112
9113 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9114
9115 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9116 &pipe_config->dpll_hw_state));
9117
9118 tmp = pipe_config->dpll_hw_state.dpll;
9119 pipe_config->pixel_multiplier =
9120 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9121 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9122
9123 ironlake_pch_clock_get(crtc, pipe_config);
9124 } else {
9125 pipe_config->pixel_multiplier = 1;
9126 }
9127
9128 intel_get_pipe_timings(crtc, pipe_config);
9129
9130 ironlake_get_pfit_config(crtc, pipe_config);
9131
9132 return true;
9133 }
9134
9135 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9136 {
9137 struct drm_device *dev = dev_priv->dev;
9138 struct intel_crtc *crtc;
9139
9140 for_each_intel_crtc(dev, crtc)
9141 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9142 pipe_name(crtc->pipe));
9143
9144 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9145 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9146 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9147 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9148 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9149 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9150 "CPU PWM1 enabled\n");
9151 if (IS_HASWELL(dev))
9152 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9153 "CPU PWM2 enabled\n");
9154 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9155 "PCH PWM1 enabled\n");
9156 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9157 "Utility pin enabled\n");
9158 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9159
9160 /*
9161 * In theory we can still leave IRQs enabled, as long as only the HPD
9162 * interrupts remain enabled. We used to check for that, but since it's
9163 * gen-specific and since we only disable LCPLL after we fully disable
9164 * the interrupts, the check below should be enough.
9165 */
9166 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9167 }
9168
9169 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9170 {
9171 struct drm_device *dev = dev_priv->dev;
9172
9173 if (IS_HASWELL(dev))
9174 return I915_READ(D_COMP_HSW);
9175 else
9176 return I915_READ(D_COMP_BDW);
9177 }
9178
9179 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9180 {
9181 struct drm_device *dev = dev_priv->dev;
9182
9183 if (IS_HASWELL(dev)) {
9184 mutex_lock(&dev_priv->rps.hw_lock);
9185 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9186 val))
9187 DRM_ERROR("Failed to write to D_COMP\n");
9188 mutex_unlock(&dev_priv->rps.hw_lock);
9189 } else {
9190 I915_WRITE(D_COMP_BDW, val);
9191 POSTING_READ(D_COMP_BDW);
9192 }
9193 }
9194
9195 /*
9196 * This function implements pieces of two sequences from BSpec:
9197 * - Sequence for display software to disable LCPLL
9198 * - Sequence for display software to allow package C8+
9199 * The steps implemented here are just the steps that actually touch the LCPLL
9200 * register. Callers should take care of disabling all the display engine
9201 * functions, doing the mode unset, fixing interrupts, etc.
9202 */
9203 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9204 bool switch_to_fclk, bool allow_power_down)
9205 {
9206 uint32_t val;
9207
9208 assert_can_disable_lcpll(dev_priv);
9209
9210 val = I915_READ(LCPLL_CTL);
9211
9212 if (switch_to_fclk) {
9213 val |= LCPLL_CD_SOURCE_FCLK;
9214 I915_WRITE(LCPLL_CTL, val);
9215
9216 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9217 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9218 DRM_ERROR("Switching to FCLK failed\n");
9219
9220 val = I915_READ(LCPLL_CTL);
9221 }
9222
9223 val |= LCPLL_PLL_DISABLE;
9224 I915_WRITE(LCPLL_CTL, val);
9225 POSTING_READ(LCPLL_CTL);
9226
9227 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9228 DRM_ERROR("LCPLL still locked\n");
9229
9230 val = hsw_read_dcomp(dev_priv);
9231 val |= D_COMP_COMP_DISABLE;
9232 hsw_write_dcomp(dev_priv, val);
9233 ndelay(100);
9234
9235 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9236 1))
9237 DRM_ERROR("D_COMP RCOMP still in progress\n");
9238
9239 if (allow_power_down) {
9240 val = I915_READ(LCPLL_CTL);
9241 val |= LCPLL_POWER_DOWN_ALLOW;
9242 I915_WRITE(LCPLL_CTL, val);
9243 POSTING_READ(LCPLL_CTL);
9244 }
9245 }
9246
9247 /*
9248 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9249 * source.
9250 */
9251 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9252 {
9253 uint32_t val;
9254
9255 val = I915_READ(LCPLL_CTL);
9256
9257 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9258 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9259 return;
9260
9261 /*
9262 * Make sure we're not on PC8 state before disabling PC8, otherwise
9263 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9264 */
9265 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9266
9267 if (val & LCPLL_POWER_DOWN_ALLOW) {
9268 val &= ~LCPLL_POWER_DOWN_ALLOW;
9269 I915_WRITE(LCPLL_CTL, val);
9270 POSTING_READ(LCPLL_CTL);
9271 }
9272
9273 val = hsw_read_dcomp(dev_priv);
9274 val |= D_COMP_COMP_FORCE;
9275 val &= ~D_COMP_COMP_DISABLE;
9276 hsw_write_dcomp(dev_priv, val);
9277
9278 val = I915_READ(LCPLL_CTL);
9279 val &= ~LCPLL_PLL_DISABLE;
9280 I915_WRITE(LCPLL_CTL, val);
9281
9282 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9283 DRM_ERROR("LCPLL not locked yet\n");
9284
9285 if (val & LCPLL_CD_SOURCE_FCLK) {
9286 val = I915_READ(LCPLL_CTL);
9287 val &= ~LCPLL_CD_SOURCE_FCLK;
9288 I915_WRITE(LCPLL_CTL, val);
9289
9290 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9291 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9292 DRM_ERROR("Switching back to LCPLL failed\n");
9293 }
9294
9295 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9296 }
9297
9298 /*
9299 * Package states C8 and deeper are really deep PC states that can only be
9300 * reached when all the devices on the system allow it, so even if the graphics
9301 * device allows PC8+, it doesn't mean the system will actually get to these
9302 * states. Our driver only allows PC8+ when going into runtime PM.
9303 *
9304 * The requirements for PC8+ are that all the outputs are disabled, the power
9305 * well is disabled and most interrupts are disabled, and these are also
9306 * requirements for runtime PM. When these conditions are met, we manually do
9307 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9308 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9309 * hang the machine.
9310 *
9311 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9312 * the state of some registers, so when we come back from PC8+ we need to
9313 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9314 * need to take care of the registers kept by RC6. Notice that this happens even
9315 * if we don't put the device in PCI D3 state (which is what currently happens
9316 * because of the runtime PM support).
9317 *
9318 * For more, read "Display Sequences for Package C8" on the hardware
9319 * documentation.
9320 */
9321 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9322 {
9323 struct drm_device *dev = dev_priv->dev;
9324 uint32_t val;
9325
9326 DRM_DEBUG_KMS("Enabling package C8+\n");
9327
9328 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9329 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9330 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9331 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9332 }
9333
9334 lpt_disable_clkout_dp(dev);
9335 hsw_disable_lcpll(dev_priv, true, true);
9336 }
9337
9338 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9339 {
9340 struct drm_device *dev = dev_priv->dev;
9341 uint32_t val;
9342
9343 DRM_DEBUG_KMS("Disabling package C8+\n");
9344
9345 hsw_restore_lcpll(dev_priv);
9346 lpt_init_pch_refclk(dev);
9347
9348 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9349 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9350 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9351 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9352 }
9353
9354 intel_prepare_ddi(dev);
9355 }
9356
9357 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9358 {
9359 struct drm_device *dev = old_state->dev;
9360 struct drm_i915_private *dev_priv = dev->dev_private;
9361 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9362 int req_cdclk;
9363
9364 /* see the comment in valleyview_modeset_global_resources */
9365 if (WARN_ON(max_pixclk < 0))
9366 return;
9367
9368 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9369
9370 if (req_cdclk != dev_priv->cdclk_freq)
9371 broxton_set_cdclk(dev, req_cdclk);
9372 }
9373
9374 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9375 struct intel_crtc_state *crtc_state)
9376 {
9377 if (!intel_ddi_pll_select(crtc, crtc_state))
9378 return -EINVAL;
9379
9380 crtc->lowfreq_avail = false;
9381
9382 return 0;
9383 }
9384
9385 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9386 enum port port,
9387 struct intel_crtc_state *pipe_config)
9388 {
9389 switch (port) {
9390 case PORT_A:
9391 pipe_config->ddi_pll_sel = SKL_DPLL0;
9392 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9393 break;
9394 case PORT_B:
9395 pipe_config->ddi_pll_sel = SKL_DPLL1;
9396 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9397 break;
9398 case PORT_C:
9399 pipe_config->ddi_pll_sel = SKL_DPLL2;
9400 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9401 break;
9402 default:
9403 DRM_ERROR("Incorrect port type\n");
9404 }
9405 }
9406
9407 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9408 enum port port,
9409 struct intel_crtc_state *pipe_config)
9410 {
9411 u32 temp, dpll_ctl1;
9412
9413 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9414 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9415
9416 switch (pipe_config->ddi_pll_sel) {
9417 case SKL_DPLL0:
9418 /*
9419 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9420 * of the shared DPLL framework and thus needs to be read out
9421 * separately
9422 */
9423 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9424 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9425 break;
9426 case SKL_DPLL1:
9427 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9428 break;
9429 case SKL_DPLL2:
9430 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9431 break;
9432 case SKL_DPLL3:
9433 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9434 break;
9435 }
9436 }
9437
9438 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9439 enum port port,
9440 struct intel_crtc_state *pipe_config)
9441 {
9442 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9443
9444 switch (pipe_config->ddi_pll_sel) {
9445 case PORT_CLK_SEL_WRPLL1:
9446 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9447 break;
9448 case PORT_CLK_SEL_WRPLL2:
9449 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9450 break;
9451 }
9452 }
9453
9454 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9455 struct intel_crtc_state *pipe_config)
9456 {
9457 struct drm_device *dev = crtc->base.dev;
9458 struct drm_i915_private *dev_priv = dev->dev_private;
9459 struct intel_shared_dpll *pll;
9460 enum port port;
9461 uint32_t tmp;
9462
9463 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9464
9465 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9466
9467 if (IS_SKYLAKE(dev))
9468 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9469 else if (IS_BROXTON(dev))
9470 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9471 else
9472 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9473
9474 if (pipe_config->shared_dpll >= 0) {
9475 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9476
9477 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9478 &pipe_config->dpll_hw_state));
9479 }
9480
9481 /*
9482 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9483 * DDI E. So just check whether this pipe is wired to DDI E and whether
9484 * the PCH transcoder is on.
9485 */
9486 if (INTEL_INFO(dev)->gen < 9 &&
9487 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9488 pipe_config->has_pch_encoder = true;
9489
9490 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9491 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9492 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9493
9494 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9495 }
9496 }
9497
9498 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9499 struct intel_crtc_state *pipe_config)
9500 {
9501 struct drm_device *dev = crtc->base.dev;
9502 struct drm_i915_private *dev_priv = dev->dev_private;
9503 enum intel_display_power_domain pfit_domain;
9504 uint32_t tmp;
9505
9506 if (!intel_display_power_is_enabled(dev_priv,
9507 POWER_DOMAIN_PIPE(crtc->pipe)))
9508 return false;
9509
9510 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9511 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9512
9513 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9514 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9515 enum pipe trans_edp_pipe;
9516 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9517 default:
9518 WARN(1, "unknown pipe linked to edp transcoder\n");
9519 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9520 case TRANS_DDI_EDP_INPUT_A_ON:
9521 trans_edp_pipe = PIPE_A;
9522 break;
9523 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9524 trans_edp_pipe = PIPE_B;
9525 break;
9526 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9527 trans_edp_pipe = PIPE_C;
9528 break;
9529 }
9530
9531 if (trans_edp_pipe == crtc->pipe)
9532 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9533 }
9534
9535 if (!intel_display_power_is_enabled(dev_priv,
9536 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9537 return false;
9538
9539 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9540 if (!(tmp & PIPECONF_ENABLE))
9541 return false;
9542
9543 haswell_get_ddi_port_state(crtc, pipe_config);
9544
9545 intel_get_pipe_timings(crtc, pipe_config);
9546
9547 if (INTEL_INFO(dev)->gen >= 9) {
9548 skl_init_scalers(dev, crtc, pipe_config);
9549 }
9550
9551 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9552
9553 if (INTEL_INFO(dev)->gen >= 9) {
9554 pipe_config->scaler_state.scaler_id = -1;
9555 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9556 }
9557
9558 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9559 if (INTEL_INFO(dev)->gen == 9)
9560 skylake_get_pfit_config(crtc, pipe_config);
9561 else if (INTEL_INFO(dev)->gen < 9)
9562 ironlake_get_pfit_config(crtc, pipe_config);
9563 else
9564 MISSING_CASE(INTEL_INFO(dev)->gen);
9565 }
9566
9567 if (IS_HASWELL(dev))
9568 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9569 (I915_READ(IPS_CTL) & IPS_ENABLE);
9570
9571 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9572 pipe_config->pixel_multiplier =
9573 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9574 } else {
9575 pipe_config->pixel_multiplier = 1;
9576 }
9577
9578 return true;
9579 }
9580
9581 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9582 {
9583 struct drm_device *dev = crtc->dev;
9584 struct drm_i915_private *dev_priv = dev->dev_private;
9585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9586 uint32_t cntl = 0, size = 0;
9587
9588 if (base) {
9589 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9590 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9591 unsigned int stride = roundup_pow_of_two(width) * 4;
9592
9593 switch (stride) {
9594 default:
9595 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9596 width, stride);
9597 stride = 256;
9598 /* fallthrough */
9599 case 256:
9600 case 512:
9601 case 1024:
9602 case 2048:
9603 break;
9604 }
9605
9606 cntl |= CURSOR_ENABLE |
9607 CURSOR_GAMMA_ENABLE |
9608 CURSOR_FORMAT_ARGB |
9609 CURSOR_STRIDE(stride);
9610
9611 size = (height << 12) | width;
9612 }
9613
9614 if (intel_crtc->cursor_cntl != 0 &&
9615 (intel_crtc->cursor_base != base ||
9616 intel_crtc->cursor_size != size ||
9617 intel_crtc->cursor_cntl != cntl)) {
9618 /* On these chipsets we can only modify the base/size/stride
9619 * whilst the cursor is disabled.
9620 */
9621 I915_WRITE(_CURACNTR, 0);
9622 POSTING_READ(_CURACNTR);
9623 intel_crtc->cursor_cntl = 0;
9624 }
9625
9626 if (intel_crtc->cursor_base != base) {
9627 I915_WRITE(_CURABASE, base);
9628 intel_crtc->cursor_base = base;
9629 }
9630
9631 if (intel_crtc->cursor_size != size) {
9632 I915_WRITE(CURSIZE, size);
9633 intel_crtc->cursor_size = size;
9634 }
9635
9636 if (intel_crtc->cursor_cntl != cntl) {
9637 I915_WRITE(_CURACNTR, cntl);
9638 POSTING_READ(_CURACNTR);
9639 intel_crtc->cursor_cntl = cntl;
9640 }
9641 }
9642
9643 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9644 {
9645 struct drm_device *dev = crtc->dev;
9646 struct drm_i915_private *dev_priv = dev->dev_private;
9647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9648 int pipe = intel_crtc->pipe;
9649 uint32_t cntl;
9650
9651 cntl = 0;
9652 if (base) {
9653 cntl = MCURSOR_GAMMA_ENABLE;
9654 switch (intel_crtc->base.cursor->state->crtc_w) {
9655 case 64:
9656 cntl |= CURSOR_MODE_64_ARGB_AX;
9657 break;
9658 case 128:
9659 cntl |= CURSOR_MODE_128_ARGB_AX;
9660 break;
9661 case 256:
9662 cntl |= CURSOR_MODE_256_ARGB_AX;
9663 break;
9664 default:
9665 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9666 return;
9667 }
9668 cntl |= pipe << 28; /* Connect to correct pipe */
9669
9670 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9671 cntl |= CURSOR_PIPE_CSC_ENABLE;
9672 }
9673
9674 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9675 cntl |= CURSOR_ROTATE_180;
9676
9677 if (intel_crtc->cursor_cntl != cntl) {
9678 I915_WRITE(CURCNTR(pipe), cntl);
9679 POSTING_READ(CURCNTR(pipe));
9680 intel_crtc->cursor_cntl = cntl;
9681 }
9682
9683 /* and commit changes on next vblank */
9684 I915_WRITE(CURBASE(pipe), base);
9685 POSTING_READ(CURBASE(pipe));
9686
9687 intel_crtc->cursor_base = base;
9688 }
9689
9690 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9691 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9692 bool on)
9693 {
9694 struct drm_device *dev = crtc->dev;
9695 struct drm_i915_private *dev_priv = dev->dev_private;
9696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9697 int pipe = intel_crtc->pipe;
9698 int x = crtc->cursor_x;
9699 int y = crtc->cursor_y;
9700 u32 base = 0, pos = 0;
9701
9702 if (on)
9703 base = intel_crtc->cursor_addr;
9704
9705 if (x >= intel_crtc->config->pipe_src_w)
9706 base = 0;
9707
9708 if (y >= intel_crtc->config->pipe_src_h)
9709 base = 0;
9710
9711 if (x < 0) {
9712 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9713 base = 0;
9714
9715 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9716 x = -x;
9717 }
9718 pos |= x << CURSOR_X_SHIFT;
9719
9720 if (y < 0) {
9721 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9722 base = 0;
9723
9724 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9725 y = -y;
9726 }
9727 pos |= y << CURSOR_Y_SHIFT;
9728
9729 if (base == 0 && intel_crtc->cursor_base == 0)
9730 return;
9731
9732 I915_WRITE(CURPOS(pipe), pos);
9733
9734 /* ILK+ do this automagically */
9735 if (HAS_GMCH_DISPLAY(dev) &&
9736 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9737 base += (intel_crtc->base.cursor->state->crtc_h *
9738 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9739 }
9740
9741 if (IS_845G(dev) || IS_I865G(dev))
9742 i845_update_cursor(crtc, base);
9743 else
9744 i9xx_update_cursor(crtc, base);
9745 }
9746
9747 static bool cursor_size_ok(struct drm_device *dev,
9748 uint32_t width, uint32_t height)
9749 {
9750 if (width == 0 || height == 0)
9751 return false;
9752
9753 /*
9754 * 845g/865g are special in that they are only limited by
9755 * the width of their cursors, the height is arbitrary up to
9756 * the precision of the register. Everything else requires
9757 * square cursors, limited to a few power-of-two sizes.
9758 */
9759 if (IS_845G(dev) || IS_I865G(dev)) {
9760 if ((width & 63) != 0)
9761 return false;
9762
9763 if (width > (IS_845G(dev) ? 64 : 512))
9764 return false;
9765
9766 if (height > 1023)
9767 return false;
9768 } else {
9769 switch (width | height) {
9770 case 256:
9771 case 128:
9772 if (IS_GEN2(dev))
9773 return false;
9774 case 64:
9775 break;
9776 default:
9777 return false;
9778 }
9779 }
9780
9781 return true;
9782 }
9783
9784 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9785 u16 *blue, uint32_t start, uint32_t size)
9786 {
9787 int end = (start + size > 256) ? 256 : start + size, i;
9788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9789
9790 for (i = start; i < end; i++) {
9791 intel_crtc->lut_r[i] = red[i] >> 8;
9792 intel_crtc->lut_g[i] = green[i] >> 8;
9793 intel_crtc->lut_b[i] = blue[i] >> 8;
9794 }
9795
9796 intel_crtc_load_lut(crtc);
9797 }
9798
9799 /* VESA 640x480x72Hz mode to set on the pipe */
9800 static struct drm_display_mode load_detect_mode = {
9801 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9802 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9803 };
9804
9805 struct drm_framebuffer *
9806 __intel_framebuffer_create(struct drm_device *dev,
9807 struct drm_mode_fb_cmd2 *mode_cmd,
9808 struct drm_i915_gem_object *obj)
9809 {
9810 struct intel_framebuffer *intel_fb;
9811 int ret;
9812
9813 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9814 if (!intel_fb) {
9815 drm_gem_object_unreference(&obj->base);
9816 return ERR_PTR(-ENOMEM);
9817 }
9818
9819 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9820 if (ret)
9821 goto err;
9822
9823 return &intel_fb->base;
9824 err:
9825 drm_gem_object_unreference(&obj->base);
9826 kfree(intel_fb);
9827
9828 return ERR_PTR(ret);
9829 }
9830
9831 static struct drm_framebuffer *
9832 intel_framebuffer_create(struct drm_device *dev,
9833 struct drm_mode_fb_cmd2 *mode_cmd,
9834 struct drm_i915_gem_object *obj)
9835 {
9836 struct drm_framebuffer *fb;
9837 int ret;
9838
9839 ret = i915_mutex_lock_interruptible(dev);
9840 if (ret)
9841 return ERR_PTR(ret);
9842 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9843 mutex_unlock(&dev->struct_mutex);
9844
9845 return fb;
9846 }
9847
9848 static u32
9849 intel_framebuffer_pitch_for_width(int width, int bpp)
9850 {
9851 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9852 return ALIGN(pitch, 64);
9853 }
9854
9855 static u32
9856 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9857 {
9858 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9859 return PAGE_ALIGN(pitch * mode->vdisplay);
9860 }
9861
9862 static struct drm_framebuffer *
9863 intel_framebuffer_create_for_mode(struct drm_device *dev,
9864 struct drm_display_mode *mode,
9865 int depth, int bpp)
9866 {
9867 struct drm_i915_gem_object *obj;
9868 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9869
9870 obj = i915_gem_alloc_object(dev,
9871 intel_framebuffer_size_for_mode(mode, bpp));
9872 if (obj == NULL)
9873 return ERR_PTR(-ENOMEM);
9874
9875 mode_cmd.width = mode->hdisplay;
9876 mode_cmd.height = mode->vdisplay;
9877 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9878 bpp);
9879 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9880
9881 return intel_framebuffer_create(dev, &mode_cmd, obj);
9882 }
9883
9884 static struct drm_framebuffer *
9885 mode_fits_in_fbdev(struct drm_device *dev,
9886 struct drm_display_mode *mode)
9887 {
9888 #ifdef CONFIG_DRM_I915_FBDEV
9889 struct drm_i915_private *dev_priv = dev->dev_private;
9890 struct drm_i915_gem_object *obj;
9891 struct drm_framebuffer *fb;
9892
9893 if (!dev_priv->fbdev)
9894 return NULL;
9895
9896 if (!dev_priv->fbdev->fb)
9897 return NULL;
9898
9899 obj = dev_priv->fbdev->fb->obj;
9900 BUG_ON(!obj);
9901
9902 fb = &dev_priv->fbdev->fb->base;
9903 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9904 fb->bits_per_pixel))
9905 return NULL;
9906
9907 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9908 return NULL;
9909
9910 return fb;
9911 #else
9912 return NULL;
9913 #endif
9914 }
9915
9916 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9917 struct drm_crtc *crtc,
9918 struct drm_display_mode *mode,
9919 struct drm_framebuffer *fb,
9920 int x, int y)
9921 {
9922 struct drm_plane_state *plane_state;
9923 int hdisplay, vdisplay;
9924 int ret;
9925
9926 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9927 if (IS_ERR(plane_state))
9928 return PTR_ERR(plane_state);
9929
9930 if (mode)
9931 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9932 else
9933 hdisplay = vdisplay = 0;
9934
9935 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9936 if (ret)
9937 return ret;
9938 drm_atomic_set_fb_for_plane(plane_state, fb);
9939 plane_state->crtc_x = 0;
9940 plane_state->crtc_y = 0;
9941 plane_state->crtc_w = hdisplay;
9942 plane_state->crtc_h = vdisplay;
9943 plane_state->src_x = x << 16;
9944 plane_state->src_y = y << 16;
9945 plane_state->src_w = hdisplay << 16;
9946 plane_state->src_h = vdisplay << 16;
9947
9948 return 0;
9949 }
9950
9951 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9952 struct drm_display_mode *mode,
9953 struct intel_load_detect_pipe *old,
9954 struct drm_modeset_acquire_ctx *ctx)
9955 {
9956 struct intel_crtc *intel_crtc;
9957 struct intel_encoder *intel_encoder =
9958 intel_attached_encoder(connector);
9959 struct drm_crtc *possible_crtc;
9960 struct drm_encoder *encoder = &intel_encoder->base;
9961 struct drm_crtc *crtc = NULL;
9962 struct drm_device *dev = encoder->dev;
9963 struct drm_framebuffer *fb;
9964 struct drm_mode_config *config = &dev->mode_config;
9965 struct drm_atomic_state *state = NULL;
9966 struct drm_connector_state *connector_state;
9967 struct intel_crtc_state *crtc_state;
9968 int ret, i = -1;
9969
9970 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9971 connector->base.id, connector->name,
9972 encoder->base.id, encoder->name);
9973
9974 retry:
9975 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9976 if (ret)
9977 goto fail_unlock;
9978
9979 /*
9980 * Algorithm gets a little messy:
9981 *
9982 * - if the connector already has an assigned crtc, use it (but make
9983 * sure it's on first)
9984 *
9985 * - try to find the first unused crtc that can drive this connector,
9986 * and use that if we find one
9987 */
9988
9989 /* See if we already have a CRTC for this connector */
9990 if (encoder->crtc) {
9991 crtc = encoder->crtc;
9992
9993 ret = drm_modeset_lock(&crtc->mutex, ctx);
9994 if (ret)
9995 goto fail_unlock;
9996 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9997 if (ret)
9998 goto fail_unlock;
9999
10000 old->dpms_mode = connector->dpms;
10001 old->load_detect_temp = false;
10002
10003 /* Make sure the crtc and connector are running */
10004 if (connector->dpms != DRM_MODE_DPMS_ON)
10005 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10006
10007 return true;
10008 }
10009
10010 /* Find an unused one (if possible) */
10011 for_each_crtc(dev, possible_crtc) {
10012 i++;
10013 if (!(encoder->possible_crtcs & (1 << i)))
10014 continue;
10015 if (possible_crtc->state->enable)
10016 continue;
10017 /* This can occur when applying the pipe A quirk on resume. */
10018 if (to_intel_crtc(possible_crtc)->new_enabled)
10019 continue;
10020
10021 crtc = possible_crtc;
10022 break;
10023 }
10024
10025 /*
10026 * If we didn't find an unused CRTC, don't use any.
10027 */
10028 if (!crtc) {
10029 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10030 goto fail_unlock;
10031 }
10032
10033 ret = drm_modeset_lock(&crtc->mutex, ctx);
10034 if (ret)
10035 goto fail_unlock;
10036 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10037 if (ret)
10038 goto fail_unlock;
10039 intel_encoder->new_crtc = to_intel_crtc(crtc);
10040 to_intel_connector(connector)->new_encoder = intel_encoder;
10041
10042 intel_crtc = to_intel_crtc(crtc);
10043 intel_crtc->new_enabled = true;
10044 old->dpms_mode = connector->dpms;
10045 old->load_detect_temp = true;
10046 old->release_fb = NULL;
10047
10048 state = drm_atomic_state_alloc(dev);
10049 if (!state)
10050 return false;
10051
10052 state->acquire_ctx = ctx;
10053
10054 connector_state = drm_atomic_get_connector_state(state, connector);
10055 if (IS_ERR(connector_state)) {
10056 ret = PTR_ERR(connector_state);
10057 goto fail;
10058 }
10059
10060 connector_state->crtc = crtc;
10061 connector_state->best_encoder = &intel_encoder->base;
10062
10063 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10064 if (IS_ERR(crtc_state)) {
10065 ret = PTR_ERR(crtc_state);
10066 goto fail;
10067 }
10068
10069 crtc_state->base.active = crtc_state->base.enable = true;
10070
10071 if (!mode)
10072 mode = &load_detect_mode;
10073
10074 /* We need a framebuffer large enough to accommodate all accesses
10075 * that the plane may generate whilst we perform load detection.
10076 * We can not rely on the fbcon either being present (we get called
10077 * during its initialisation to detect all boot displays, or it may
10078 * not even exist) or that it is large enough to satisfy the
10079 * requested mode.
10080 */
10081 fb = mode_fits_in_fbdev(dev, mode);
10082 if (fb == NULL) {
10083 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10084 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10085 old->release_fb = fb;
10086 } else
10087 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10088 if (IS_ERR(fb)) {
10089 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10090 goto fail;
10091 }
10092
10093 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10094 if (ret)
10095 goto fail;
10096
10097 drm_mode_copy(&crtc_state->base.mode, mode);
10098
10099 if (intel_set_mode(crtc, state)) {
10100 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10101 if (old->release_fb)
10102 old->release_fb->funcs->destroy(old->release_fb);
10103 goto fail;
10104 }
10105 crtc->primary->crtc = crtc;
10106
10107 /* let the connector get through one full cycle before testing */
10108 intel_wait_for_vblank(dev, intel_crtc->pipe);
10109 return true;
10110
10111 fail:
10112 intel_crtc->new_enabled = crtc->state->enable;
10113 fail_unlock:
10114 drm_atomic_state_free(state);
10115 state = NULL;
10116
10117 if (ret == -EDEADLK) {
10118 drm_modeset_backoff(ctx);
10119 goto retry;
10120 }
10121
10122 return false;
10123 }
10124
10125 void intel_release_load_detect_pipe(struct drm_connector *connector,
10126 struct intel_load_detect_pipe *old,
10127 struct drm_modeset_acquire_ctx *ctx)
10128 {
10129 struct drm_device *dev = connector->dev;
10130 struct intel_encoder *intel_encoder =
10131 intel_attached_encoder(connector);
10132 struct drm_encoder *encoder = &intel_encoder->base;
10133 struct drm_crtc *crtc = encoder->crtc;
10134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10135 struct drm_atomic_state *state;
10136 struct drm_connector_state *connector_state;
10137 struct intel_crtc_state *crtc_state;
10138 int ret;
10139
10140 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10141 connector->base.id, connector->name,
10142 encoder->base.id, encoder->name);
10143
10144 if (old->load_detect_temp) {
10145 state = drm_atomic_state_alloc(dev);
10146 if (!state)
10147 goto fail;
10148
10149 state->acquire_ctx = ctx;
10150
10151 connector_state = drm_atomic_get_connector_state(state, connector);
10152 if (IS_ERR(connector_state))
10153 goto fail;
10154
10155 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10156 if (IS_ERR(crtc_state))
10157 goto fail;
10158
10159 to_intel_connector(connector)->new_encoder = NULL;
10160 intel_encoder->new_crtc = NULL;
10161 intel_crtc->new_enabled = false;
10162
10163 connector_state->best_encoder = NULL;
10164 connector_state->crtc = NULL;
10165
10166 crtc_state->base.enable = crtc_state->base.active = false;
10167
10168 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10169 0, 0);
10170 if (ret)
10171 goto fail;
10172
10173 ret = intel_set_mode(crtc, state);
10174 if (ret)
10175 goto fail;
10176
10177 if (old->release_fb) {
10178 drm_framebuffer_unregister_private(old->release_fb);
10179 drm_framebuffer_unreference(old->release_fb);
10180 }
10181
10182 return;
10183 }
10184
10185 /* Switch crtc and encoder back off if necessary */
10186 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10187 connector->funcs->dpms(connector, old->dpms_mode);
10188
10189 return;
10190 fail:
10191 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10192 drm_atomic_state_free(state);
10193 }
10194
10195 static int i9xx_pll_refclk(struct drm_device *dev,
10196 const struct intel_crtc_state *pipe_config)
10197 {
10198 struct drm_i915_private *dev_priv = dev->dev_private;
10199 u32 dpll = pipe_config->dpll_hw_state.dpll;
10200
10201 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10202 return dev_priv->vbt.lvds_ssc_freq;
10203 else if (HAS_PCH_SPLIT(dev))
10204 return 120000;
10205 else if (!IS_GEN2(dev))
10206 return 96000;
10207 else
10208 return 48000;
10209 }
10210
10211 /* Returns the clock of the currently programmed mode of the given pipe. */
10212 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10213 struct intel_crtc_state *pipe_config)
10214 {
10215 struct drm_device *dev = crtc->base.dev;
10216 struct drm_i915_private *dev_priv = dev->dev_private;
10217 int pipe = pipe_config->cpu_transcoder;
10218 u32 dpll = pipe_config->dpll_hw_state.dpll;
10219 u32 fp;
10220 intel_clock_t clock;
10221 int refclk = i9xx_pll_refclk(dev, pipe_config);
10222
10223 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10224 fp = pipe_config->dpll_hw_state.fp0;
10225 else
10226 fp = pipe_config->dpll_hw_state.fp1;
10227
10228 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10229 if (IS_PINEVIEW(dev)) {
10230 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10231 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10232 } else {
10233 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10234 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10235 }
10236
10237 if (!IS_GEN2(dev)) {
10238 if (IS_PINEVIEW(dev))
10239 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10240 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10241 else
10242 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10243 DPLL_FPA01_P1_POST_DIV_SHIFT);
10244
10245 switch (dpll & DPLL_MODE_MASK) {
10246 case DPLLB_MODE_DAC_SERIAL:
10247 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10248 5 : 10;
10249 break;
10250 case DPLLB_MODE_LVDS:
10251 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10252 7 : 14;
10253 break;
10254 default:
10255 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10256 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10257 return;
10258 }
10259
10260 if (IS_PINEVIEW(dev))
10261 pineview_clock(refclk, &clock);
10262 else
10263 i9xx_clock(refclk, &clock);
10264 } else {
10265 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10266 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10267
10268 if (is_lvds) {
10269 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10270 DPLL_FPA01_P1_POST_DIV_SHIFT);
10271
10272 if (lvds & LVDS_CLKB_POWER_UP)
10273 clock.p2 = 7;
10274 else
10275 clock.p2 = 14;
10276 } else {
10277 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10278 clock.p1 = 2;
10279 else {
10280 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10281 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10282 }
10283 if (dpll & PLL_P2_DIVIDE_BY_4)
10284 clock.p2 = 4;
10285 else
10286 clock.p2 = 2;
10287 }
10288
10289 i9xx_clock(refclk, &clock);
10290 }
10291
10292 /*
10293 * This value includes pixel_multiplier. We will use
10294 * port_clock to compute adjusted_mode.crtc_clock in the
10295 * encoder's get_config() function.
10296 */
10297 pipe_config->port_clock = clock.dot;
10298 }
10299
10300 int intel_dotclock_calculate(int link_freq,
10301 const struct intel_link_m_n *m_n)
10302 {
10303 /*
10304 * The calculation for the data clock is:
10305 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10306 * But we want to avoid losing precison if possible, so:
10307 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10308 *
10309 * and the link clock is simpler:
10310 * link_clock = (m * link_clock) / n
10311 */
10312
10313 if (!m_n->link_n)
10314 return 0;
10315
10316 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10317 }
10318
10319 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10320 struct intel_crtc_state *pipe_config)
10321 {
10322 struct drm_device *dev = crtc->base.dev;
10323
10324 /* read out port_clock from the DPLL */
10325 i9xx_crtc_clock_get(crtc, pipe_config);
10326
10327 /*
10328 * This value does not include pixel_multiplier.
10329 * We will check that port_clock and adjusted_mode.crtc_clock
10330 * agree once we know their relationship in the encoder's
10331 * get_config() function.
10332 */
10333 pipe_config->base.adjusted_mode.crtc_clock =
10334 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10335 &pipe_config->fdi_m_n);
10336 }
10337
10338 /** Returns the currently programmed mode of the given pipe. */
10339 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10340 struct drm_crtc *crtc)
10341 {
10342 struct drm_i915_private *dev_priv = dev->dev_private;
10343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10344 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10345 struct drm_display_mode *mode;
10346 struct intel_crtc_state pipe_config;
10347 int htot = I915_READ(HTOTAL(cpu_transcoder));
10348 int hsync = I915_READ(HSYNC(cpu_transcoder));
10349 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10350 int vsync = I915_READ(VSYNC(cpu_transcoder));
10351 enum pipe pipe = intel_crtc->pipe;
10352
10353 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10354 if (!mode)
10355 return NULL;
10356
10357 /*
10358 * Construct a pipe_config sufficient for getting the clock info
10359 * back out of crtc_clock_get.
10360 *
10361 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10362 * to use a real value here instead.
10363 */
10364 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10365 pipe_config.pixel_multiplier = 1;
10366 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10367 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10368 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10369 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10370
10371 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10372 mode->hdisplay = (htot & 0xffff) + 1;
10373 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10374 mode->hsync_start = (hsync & 0xffff) + 1;
10375 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10376 mode->vdisplay = (vtot & 0xffff) + 1;
10377 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10378 mode->vsync_start = (vsync & 0xffff) + 1;
10379 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10380
10381 drm_mode_set_name(mode);
10382
10383 return mode;
10384 }
10385
10386 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10387 {
10388 struct drm_device *dev = crtc->dev;
10389 struct drm_i915_private *dev_priv = dev->dev_private;
10390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10391
10392 if (!HAS_GMCH_DISPLAY(dev))
10393 return;
10394
10395 if (!dev_priv->lvds_downclock_avail)
10396 return;
10397
10398 /*
10399 * Since this is called by a timer, we should never get here in
10400 * the manual case.
10401 */
10402 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10403 int pipe = intel_crtc->pipe;
10404 int dpll_reg = DPLL(pipe);
10405 int dpll;
10406
10407 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10408
10409 assert_panel_unlocked(dev_priv, pipe);
10410
10411 dpll = I915_READ(dpll_reg);
10412 dpll |= DISPLAY_RATE_SELECT_FPA1;
10413 I915_WRITE(dpll_reg, dpll);
10414 intel_wait_for_vblank(dev, pipe);
10415 dpll = I915_READ(dpll_reg);
10416 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10417 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10418 }
10419
10420 }
10421
10422 void intel_mark_busy(struct drm_device *dev)
10423 {
10424 struct drm_i915_private *dev_priv = dev->dev_private;
10425
10426 if (dev_priv->mm.busy)
10427 return;
10428
10429 intel_runtime_pm_get(dev_priv);
10430 i915_update_gfx_val(dev_priv);
10431 if (INTEL_INFO(dev)->gen >= 6)
10432 gen6_rps_busy(dev_priv);
10433 dev_priv->mm.busy = true;
10434 }
10435
10436 void intel_mark_idle(struct drm_device *dev)
10437 {
10438 struct drm_i915_private *dev_priv = dev->dev_private;
10439 struct drm_crtc *crtc;
10440
10441 if (!dev_priv->mm.busy)
10442 return;
10443
10444 dev_priv->mm.busy = false;
10445
10446 for_each_crtc(dev, crtc) {
10447 if (!crtc->primary->fb)
10448 continue;
10449
10450 intel_decrease_pllclock(crtc);
10451 }
10452
10453 if (INTEL_INFO(dev)->gen >= 6)
10454 gen6_rps_idle(dev->dev_private);
10455
10456 intel_runtime_pm_put(dev_priv);
10457 }
10458
10459 static void intel_crtc_destroy(struct drm_crtc *crtc)
10460 {
10461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10462 struct drm_device *dev = crtc->dev;
10463 struct intel_unpin_work *work;
10464
10465 spin_lock_irq(&dev->event_lock);
10466 work = intel_crtc->unpin_work;
10467 intel_crtc->unpin_work = NULL;
10468 spin_unlock_irq(&dev->event_lock);
10469
10470 if (work) {
10471 cancel_work_sync(&work->work);
10472 kfree(work);
10473 }
10474
10475 drm_crtc_cleanup(crtc);
10476
10477 kfree(intel_crtc);
10478 }
10479
10480 static void intel_unpin_work_fn(struct work_struct *__work)
10481 {
10482 struct intel_unpin_work *work =
10483 container_of(__work, struct intel_unpin_work, work);
10484 struct drm_device *dev = work->crtc->dev;
10485 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10486
10487 mutex_lock(&dev->struct_mutex);
10488 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10489 drm_gem_object_unreference(&work->pending_flip_obj->base);
10490
10491 intel_fbc_update(dev);
10492
10493 if (work->flip_queued_req)
10494 i915_gem_request_assign(&work->flip_queued_req, NULL);
10495 mutex_unlock(&dev->struct_mutex);
10496
10497 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10498 drm_framebuffer_unreference(work->old_fb);
10499
10500 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10501 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10502
10503 kfree(work);
10504 }
10505
10506 static void do_intel_finish_page_flip(struct drm_device *dev,
10507 struct drm_crtc *crtc)
10508 {
10509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10510 struct intel_unpin_work *work;
10511 unsigned long flags;
10512
10513 /* Ignore early vblank irqs */
10514 if (intel_crtc == NULL)
10515 return;
10516
10517 /*
10518 * This is called both by irq handlers and the reset code (to complete
10519 * lost pageflips) so needs the full irqsave spinlocks.
10520 */
10521 spin_lock_irqsave(&dev->event_lock, flags);
10522 work = intel_crtc->unpin_work;
10523
10524 /* Ensure we don't miss a work->pending update ... */
10525 smp_rmb();
10526
10527 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10528 spin_unlock_irqrestore(&dev->event_lock, flags);
10529 return;
10530 }
10531
10532 page_flip_completed(intel_crtc);
10533
10534 spin_unlock_irqrestore(&dev->event_lock, flags);
10535 }
10536
10537 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10538 {
10539 struct drm_i915_private *dev_priv = dev->dev_private;
10540 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10541
10542 do_intel_finish_page_flip(dev, crtc);
10543 }
10544
10545 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10546 {
10547 struct drm_i915_private *dev_priv = dev->dev_private;
10548 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10549
10550 do_intel_finish_page_flip(dev, crtc);
10551 }
10552
10553 /* Is 'a' after or equal to 'b'? */
10554 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10555 {
10556 return !((a - b) & 0x80000000);
10557 }
10558
10559 static bool page_flip_finished(struct intel_crtc *crtc)
10560 {
10561 struct drm_device *dev = crtc->base.dev;
10562 struct drm_i915_private *dev_priv = dev->dev_private;
10563
10564 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10565 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10566 return true;
10567
10568 /*
10569 * The relevant registers doen't exist on pre-ctg.
10570 * As the flip done interrupt doesn't trigger for mmio
10571 * flips on gmch platforms, a flip count check isn't
10572 * really needed there. But since ctg has the registers,
10573 * include it in the check anyway.
10574 */
10575 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10576 return true;
10577
10578 /*
10579 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10580 * used the same base address. In that case the mmio flip might
10581 * have completed, but the CS hasn't even executed the flip yet.
10582 *
10583 * A flip count check isn't enough as the CS might have updated
10584 * the base address just after start of vblank, but before we
10585 * managed to process the interrupt. This means we'd complete the
10586 * CS flip too soon.
10587 *
10588 * Combining both checks should get us a good enough result. It may
10589 * still happen that the CS flip has been executed, but has not
10590 * yet actually completed. But in case the base address is the same
10591 * anyway, we don't really care.
10592 */
10593 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10594 crtc->unpin_work->gtt_offset &&
10595 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10596 crtc->unpin_work->flip_count);
10597 }
10598
10599 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10600 {
10601 struct drm_i915_private *dev_priv = dev->dev_private;
10602 struct intel_crtc *intel_crtc =
10603 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10604 unsigned long flags;
10605
10606
10607 /*
10608 * This is called both by irq handlers and the reset code (to complete
10609 * lost pageflips) so needs the full irqsave spinlocks.
10610 *
10611 * NB: An MMIO update of the plane base pointer will also
10612 * generate a page-flip completion irq, i.e. every modeset
10613 * is also accompanied by a spurious intel_prepare_page_flip().
10614 */
10615 spin_lock_irqsave(&dev->event_lock, flags);
10616 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10617 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10618 spin_unlock_irqrestore(&dev->event_lock, flags);
10619 }
10620
10621 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10622 {
10623 /* Ensure that the work item is consistent when activating it ... */
10624 smp_wmb();
10625 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10626 /* and that it is marked active as soon as the irq could fire. */
10627 smp_wmb();
10628 }
10629
10630 static int intel_gen2_queue_flip(struct drm_device *dev,
10631 struct drm_crtc *crtc,
10632 struct drm_framebuffer *fb,
10633 struct drm_i915_gem_object *obj,
10634 struct intel_engine_cs *ring,
10635 uint32_t flags)
10636 {
10637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10638 u32 flip_mask;
10639 int ret;
10640
10641 ret = intel_ring_begin(ring, 6);
10642 if (ret)
10643 return ret;
10644
10645 /* Can't queue multiple flips, so wait for the previous
10646 * one to finish before executing the next.
10647 */
10648 if (intel_crtc->plane)
10649 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10650 else
10651 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10652 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10653 intel_ring_emit(ring, MI_NOOP);
10654 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10655 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10656 intel_ring_emit(ring, fb->pitches[0]);
10657 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10658 intel_ring_emit(ring, 0); /* aux display base address, unused */
10659
10660 intel_mark_page_flip_active(intel_crtc);
10661 __intel_ring_advance(ring);
10662 return 0;
10663 }
10664
10665 static int intel_gen3_queue_flip(struct drm_device *dev,
10666 struct drm_crtc *crtc,
10667 struct drm_framebuffer *fb,
10668 struct drm_i915_gem_object *obj,
10669 struct intel_engine_cs *ring,
10670 uint32_t flags)
10671 {
10672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10673 u32 flip_mask;
10674 int ret;
10675
10676 ret = intel_ring_begin(ring, 6);
10677 if (ret)
10678 return ret;
10679
10680 if (intel_crtc->plane)
10681 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10682 else
10683 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10684 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10685 intel_ring_emit(ring, MI_NOOP);
10686 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10687 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10688 intel_ring_emit(ring, fb->pitches[0]);
10689 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10690 intel_ring_emit(ring, MI_NOOP);
10691
10692 intel_mark_page_flip_active(intel_crtc);
10693 __intel_ring_advance(ring);
10694 return 0;
10695 }
10696
10697 static int intel_gen4_queue_flip(struct drm_device *dev,
10698 struct drm_crtc *crtc,
10699 struct drm_framebuffer *fb,
10700 struct drm_i915_gem_object *obj,
10701 struct intel_engine_cs *ring,
10702 uint32_t flags)
10703 {
10704 struct drm_i915_private *dev_priv = dev->dev_private;
10705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10706 uint32_t pf, pipesrc;
10707 int ret;
10708
10709 ret = intel_ring_begin(ring, 4);
10710 if (ret)
10711 return ret;
10712
10713 /* i965+ uses the linear or tiled offsets from the
10714 * Display Registers (which do not change across a page-flip)
10715 * so we need only reprogram the base address.
10716 */
10717 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10718 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10719 intel_ring_emit(ring, fb->pitches[0]);
10720 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10721 obj->tiling_mode);
10722
10723 /* XXX Enabling the panel-fitter across page-flip is so far
10724 * untested on non-native modes, so ignore it for now.
10725 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10726 */
10727 pf = 0;
10728 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10729 intel_ring_emit(ring, pf | pipesrc);
10730
10731 intel_mark_page_flip_active(intel_crtc);
10732 __intel_ring_advance(ring);
10733 return 0;
10734 }
10735
10736 static int intel_gen6_queue_flip(struct drm_device *dev,
10737 struct drm_crtc *crtc,
10738 struct drm_framebuffer *fb,
10739 struct drm_i915_gem_object *obj,
10740 struct intel_engine_cs *ring,
10741 uint32_t flags)
10742 {
10743 struct drm_i915_private *dev_priv = dev->dev_private;
10744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10745 uint32_t pf, pipesrc;
10746 int ret;
10747
10748 ret = intel_ring_begin(ring, 4);
10749 if (ret)
10750 return ret;
10751
10752 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10753 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10754 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10755 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10756
10757 /* Contrary to the suggestions in the documentation,
10758 * "Enable Panel Fitter" does not seem to be required when page
10759 * flipping with a non-native mode, and worse causes a normal
10760 * modeset to fail.
10761 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10762 */
10763 pf = 0;
10764 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10765 intel_ring_emit(ring, pf | pipesrc);
10766
10767 intel_mark_page_flip_active(intel_crtc);
10768 __intel_ring_advance(ring);
10769 return 0;
10770 }
10771
10772 static int intel_gen7_queue_flip(struct drm_device *dev,
10773 struct drm_crtc *crtc,
10774 struct drm_framebuffer *fb,
10775 struct drm_i915_gem_object *obj,
10776 struct intel_engine_cs *ring,
10777 uint32_t flags)
10778 {
10779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10780 uint32_t plane_bit = 0;
10781 int len, ret;
10782
10783 switch (intel_crtc->plane) {
10784 case PLANE_A:
10785 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10786 break;
10787 case PLANE_B:
10788 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10789 break;
10790 case PLANE_C:
10791 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10792 break;
10793 default:
10794 WARN_ONCE(1, "unknown plane in flip command\n");
10795 return -ENODEV;
10796 }
10797
10798 len = 4;
10799 if (ring->id == RCS) {
10800 len += 6;
10801 /*
10802 * On Gen 8, SRM is now taking an extra dword to accommodate
10803 * 48bits addresses, and we need a NOOP for the batch size to
10804 * stay even.
10805 */
10806 if (IS_GEN8(dev))
10807 len += 2;
10808 }
10809
10810 /*
10811 * BSpec MI_DISPLAY_FLIP for IVB:
10812 * "The full packet must be contained within the same cache line."
10813 *
10814 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10815 * cacheline, if we ever start emitting more commands before
10816 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10817 * then do the cacheline alignment, and finally emit the
10818 * MI_DISPLAY_FLIP.
10819 */
10820 ret = intel_ring_cacheline_align(ring);
10821 if (ret)
10822 return ret;
10823
10824 ret = intel_ring_begin(ring, len);
10825 if (ret)
10826 return ret;
10827
10828 /* Unmask the flip-done completion message. Note that the bspec says that
10829 * we should do this for both the BCS and RCS, and that we must not unmask
10830 * more than one flip event at any time (or ensure that one flip message
10831 * can be sent by waiting for flip-done prior to queueing new flips).
10832 * Experimentation says that BCS works despite DERRMR masking all
10833 * flip-done completion events and that unmasking all planes at once
10834 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10835 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10836 */
10837 if (ring->id == RCS) {
10838 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10839 intel_ring_emit(ring, DERRMR);
10840 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10841 DERRMR_PIPEB_PRI_FLIP_DONE |
10842 DERRMR_PIPEC_PRI_FLIP_DONE));
10843 if (IS_GEN8(dev))
10844 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10845 MI_SRM_LRM_GLOBAL_GTT);
10846 else
10847 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10848 MI_SRM_LRM_GLOBAL_GTT);
10849 intel_ring_emit(ring, DERRMR);
10850 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10851 if (IS_GEN8(dev)) {
10852 intel_ring_emit(ring, 0);
10853 intel_ring_emit(ring, MI_NOOP);
10854 }
10855 }
10856
10857 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10858 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10859 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10860 intel_ring_emit(ring, (MI_NOOP));
10861
10862 intel_mark_page_flip_active(intel_crtc);
10863 __intel_ring_advance(ring);
10864 return 0;
10865 }
10866
10867 static bool use_mmio_flip(struct intel_engine_cs *ring,
10868 struct drm_i915_gem_object *obj)
10869 {
10870 /*
10871 * This is not being used for older platforms, because
10872 * non-availability of flip done interrupt forces us to use
10873 * CS flips. Older platforms derive flip done using some clever
10874 * tricks involving the flip_pending status bits and vblank irqs.
10875 * So using MMIO flips there would disrupt this mechanism.
10876 */
10877
10878 if (ring == NULL)
10879 return true;
10880
10881 if (INTEL_INFO(ring->dev)->gen < 5)
10882 return false;
10883
10884 if (i915.use_mmio_flip < 0)
10885 return false;
10886 else if (i915.use_mmio_flip > 0)
10887 return true;
10888 else if (i915.enable_execlists)
10889 return true;
10890 else
10891 return ring != i915_gem_request_get_ring(obj->last_write_req);
10892 }
10893
10894 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10895 {
10896 struct drm_device *dev = intel_crtc->base.dev;
10897 struct drm_i915_private *dev_priv = dev->dev_private;
10898 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10899 const enum pipe pipe = intel_crtc->pipe;
10900 u32 ctl, stride;
10901
10902 ctl = I915_READ(PLANE_CTL(pipe, 0));
10903 ctl &= ~PLANE_CTL_TILED_MASK;
10904 switch (fb->modifier[0]) {
10905 case DRM_FORMAT_MOD_NONE:
10906 break;
10907 case I915_FORMAT_MOD_X_TILED:
10908 ctl |= PLANE_CTL_TILED_X;
10909 break;
10910 case I915_FORMAT_MOD_Y_TILED:
10911 ctl |= PLANE_CTL_TILED_Y;
10912 break;
10913 case I915_FORMAT_MOD_Yf_TILED:
10914 ctl |= PLANE_CTL_TILED_YF;
10915 break;
10916 default:
10917 MISSING_CASE(fb->modifier[0]);
10918 }
10919
10920 /*
10921 * The stride is either expressed as a multiple of 64 bytes chunks for
10922 * linear buffers or in number of tiles for tiled buffers.
10923 */
10924 stride = fb->pitches[0] /
10925 intel_fb_stride_alignment(dev, fb->modifier[0],
10926 fb->pixel_format);
10927
10928 /*
10929 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10930 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10931 */
10932 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10933 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10934
10935 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10936 POSTING_READ(PLANE_SURF(pipe, 0));
10937 }
10938
10939 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10940 {
10941 struct drm_device *dev = intel_crtc->base.dev;
10942 struct drm_i915_private *dev_priv = dev->dev_private;
10943 struct intel_framebuffer *intel_fb =
10944 to_intel_framebuffer(intel_crtc->base.primary->fb);
10945 struct drm_i915_gem_object *obj = intel_fb->obj;
10946 u32 dspcntr;
10947 u32 reg;
10948
10949 reg = DSPCNTR(intel_crtc->plane);
10950 dspcntr = I915_READ(reg);
10951
10952 if (obj->tiling_mode != I915_TILING_NONE)
10953 dspcntr |= DISPPLANE_TILED;
10954 else
10955 dspcntr &= ~DISPPLANE_TILED;
10956
10957 I915_WRITE(reg, dspcntr);
10958
10959 I915_WRITE(DSPSURF(intel_crtc->plane),
10960 intel_crtc->unpin_work->gtt_offset);
10961 POSTING_READ(DSPSURF(intel_crtc->plane));
10962
10963 }
10964
10965 /*
10966 * XXX: This is the temporary way to update the plane registers until we get
10967 * around to using the usual plane update functions for MMIO flips
10968 */
10969 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10970 {
10971 struct drm_device *dev = intel_crtc->base.dev;
10972 bool atomic_update;
10973 u32 start_vbl_count;
10974
10975 intel_mark_page_flip_active(intel_crtc);
10976
10977 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10978
10979 if (INTEL_INFO(dev)->gen >= 9)
10980 skl_do_mmio_flip(intel_crtc);
10981 else
10982 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10983 ilk_do_mmio_flip(intel_crtc);
10984
10985 if (atomic_update)
10986 intel_pipe_update_end(intel_crtc, start_vbl_count);
10987 }
10988
10989 static void intel_mmio_flip_work_func(struct work_struct *work)
10990 {
10991 struct intel_mmio_flip *mmio_flip =
10992 container_of(work, struct intel_mmio_flip, work);
10993
10994 if (mmio_flip->req)
10995 WARN_ON(__i915_wait_request(mmio_flip->req,
10996 mmio_flip->crtc->reset_counter,
10997 false, NULL,
10998 &mmio_flip->i915->rps.mmioflips));
10999
11000 intel_do_mmio_flip(mmio_flip->crtc);
11001
11002 i915_gem_request_unreference__unlocked(mmio_flip->req);
11003 kfree(mmio_flip);
11004 }
11005
11006 static int intel_queue_mmio_flip(struct drm_device *dev,
11007 struct drm_crtc *crtc,
11008 struct drm_framebuffer *fb,
11009 struct drm_i915_gem_object *obj,
11010 struct intel_engine_cs *ring,
11011 uint32_t flags)
11012 {
11013 struct intel_mmio_flip *mmio_flip;
11014
11015 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11016 if (mmio_flip == NULL)
11017 return -ENOMEM;
11018
11019 mmio_flip->i915 = to_i915(dev);
11020 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11021 mmio_flip->crtc = to_intel_crtc(crtc);
11022
11023 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11024 schedule_work(&mmio_flip->work);
11025
11026 return 0;
11027 }
11028
11029 static int intel_default_queue_flip(struct drm_device *dev,
11030 struct drm_crtc *crtc,
11031 struct drm_framebuffer *fb,
11032 struct drm_i915_gem_object *obj,
11033 struct intel_engine_cs *ring,
11034 uint32_t flags)
11035 {
11036 return -ENODEV;
11037 }
11038
11039 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11040 struct drm_crtc *crtc)
11041 {
11042 struct drm_i915_private *dev_priv = dev->dev_private;
11043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11044 struct intel_unpin_work *work = intel_crtc->unpin_work;
11045 u32 addr;
11046
11047 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11048 return true;
11049
11050 if (!work->enable_stall_check)
11051 return false;
11052
11053 if (work->flip_ready_vblank == 0) {
11054 if (work->flip_queued_req &&
11055 !i915_gem_request_completed(work->flip_queued_req, true))
11056 return false;
11057
11058 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11059 }
11060
11061 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11062 return false;
11063
11064 /* Potential stall - if we see that the flip has happened,
11065 * assume a missed interrupt. */
11066 if (INTEL_INFO(dev)->gen >= 4)
11067 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11068 else
11069 addr = I915_READ(DSPADDR(intel_crtc->plane));
11070
11071 /* There is a potential issue here with a false positive after a flip
11072 * to the same address. We could address this by checking for a
11073 * non-incrementing frame counter.
11074 */
11075 return addr == work->gtt_offset;
11076 }
11077
11078 void intel_check_page_flip(struct drm_device *dev, int pipe)
11079 {
11080 struct drm_i915_private *dev_priv = dev->dev_private;
11081 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11083 struct intel_unpin_work *work;
11084
11085 WARN_ON(!in_interrupt());
11086
11087 if (crtc == NULL)
11088 return;
11089
11090 spin_lock(&dev->event_lock);
11091 work = intel_crtc->unpin_work;
11092 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11093 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11094 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11095 page_flip_completed(intel_crtc);
11096 work = NULL;
11097 }
11098 if (work != NULL &&
11099 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11100 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11101 spin_unlock(&dev->event_lock);
11102 }
11103
11104 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11105 struct drm_framebuffer *fb,
11106 struct drm_pending_vblank_event *event,
11107 uint32_t page_flip_flags)
11108 {
11109 struct drm_device *dev = crtc->dev;
11110 struct drm_i915_private *dev_priv = dev->dev_private;
11111 struct drm_framebuffer *old_fb = crtc->primary->fb;
11112 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11114 struct drm_plane *primary = crtc->primary;
11115 enum pipe pipe = intel_crtc->pipe;
11116 struct intel_unpin_work *work;
11117 struct intel_engine_cs *ring;
11118 bool mmio_flip;
11119 int ret;
11120
11121 /*
11122 * drm_mode_page_flip_ioctl() should already catch this, but double
11123 * check to be safe. In the future we may enable pageflipping from
11124 * a disabled primary plane.
11125 */
11126 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11127 return -EBUSY;
11128
11129 /* Can't change pixel format via MI display flips. */
11130 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11131 return -EINVAL;
11132
11133 /*
11134 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11135 * Note that pitch changes could also affect these register.
11136 */
11137 if (INTEL_INFO(dev)->gen > 3 &&
11138 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11139 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11140 return -EINVAL;
11141
11142 if (i915_terminally_wedged(&dev_priv->gpu_error))
11143 goto out_hang;
11144
11145 work = kzalloc(sizeof(*work), GFP_KERNEL);
11146 if (work == NULL)
11147 return -ENOMEM;
11148
11149 work->event = event;
11150 work->crtc = crtc;
11151 work->old_fb = old_fb;
11152 INIT_WORK(&work->work, intel_unpin_work_fn);
11153
11154 ret = drm_crtc_vblank_get(crtc);
11155 if (ret)
11156 goto free_work;
11157
11158 /* We borrow the event spin lock for protecting unpin_work */
11159 spin_lock_irq(&dev->event_lock);
11160 if (intel_crtc->unpin_work) {
11161 /* Before declaring the flip queue wedged, check if
11162 * the hardware completed the operation behind our backs.
11163 */
11164 if (__intel_pageflip_stall_check(dev, crtc)) {
11165 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11166 page_flip_completed(intel_crtc);
11167 } else {
11168 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11169 spin_unlock_irq(&dev->event_lock);
11170
11171 drm_crtc_vblank_put(crtc);
11172 kfree(work);
11173 return -EBUSY;
11174 }
11175 }
11176 intel_crtc->unpin_work = work;
11177 spin_unlock_irq(&dev->event_lock);
11178
11179 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11180 flush_workqueue(dev_priv->wq);
11181
11182 /* Reference the objects for the scheduled work. */
11183 drm_framebuffer_reference(work->old_fb);
11184 drm_gem_object_reference(&obj->base);
11185
11186 crtc->primary->fb = fb;
11187 update_state_fb(crtc->primary);
11188
11189 work->pending_flip_obj = obj;
11190
11191 ret = i915_mutex_lock_interruptible(dev);
11192 if (ret)
11193 goto cleanup;
11194
11195 atomic_inc(&intel_crtc->unpin_work_count);
11196 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11197
11198 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11199 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11200
11201 if (IS_VALLEYVIEW(dev)) {
11202 ring = &dev_priv->ring[BCS];
11203 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11204 /* vlv: DISPLAY_FLIP fails to change tiling */
11205 ring = NULL;
11206 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11207 ring = &dev_priv->ring[BCS];
11208 } else if (INTEL_INFO(dev)->gen >= 7) {
11209 ring = i915_gem_request_get_ring(obj->last_write_req);
11210 if (ring == NULL || ring->id != RCS)
11211 ring = &dev_priv->ring[BCS];
11212 } else {
11213 ring = &dev_priv->ring[RCS];
11214 }
11215
11216 mmio_flip = use_mmio_flip(ring, obj);
11217
11218 /* When using CS flips, we want to emit semaphores between rings.
11219 * However, when using mmio flips we will create a task to do the
11220 * synchronisation, so all we want here is to pin the framebuffer
11221 * into the display plane and skip any waits.
11222 */
11223 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11224 crtc->primary->state,
11225 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11226 if (ret)
11227 goto cleanup_pending;
11228
11229 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11230 + intel_crtc->dspaddr_offset;
11231
11232 if (mmio_flip) {
11233 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11234 page_flip_flags);
11235 if (ret)
11236 goto cleanup_unpin;
11237
11238 i915_gem_request_assign(&work->flip_queued_req,
11239 obj->last_write_req);
11240 } else {
11241 if (obj->last_write_req) {
11242 ret = i915_gem_check_olr(obj->last_write_req);
11243 if (ret)
11244 goto cleanup_unpin;
11245 }
11246
11247 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11248 page_flip_flags);
11249 if (ret)
11250 goto cleanup_unpin;
11251
11252 i915_gem_request_assign(&work->flip_queued_req,
11253 intel_ring_get_request(ring));
11254 }
11255
11256 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11257 work->enable_stall_check = true;
11258
11259 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11260 INTEL_FRONTBUFFER_PRIMARY(pipe));
11261
11262 intel_fbc_disable(dev);
11263 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11264 mutex_unlock(&dev->struct_mutex);
11265
11266 trace_i915_flip_request(intel_crtc->plane, obj);
11267
11268 return 0;
11269
11270 cleanup_unpin:
11271 intel_unpin_fb_obj(fb, crtc->primary->state);
11272 cleanup_pending:
11273 atomic_dec(&intel_crtc->unpin_work_count);
11274 mutex_unlock(&dev->struct_mutex);
11275 cleanup:
11276 crtc->primary->fb = old_fb;
11277 update_state_fb(crtc->primary);
11278
11279 drm_gem_object_unreference_unlocked(&obj->base);
11280 drm_framebuffer_unreference(work->old_fb);
11281
11282 spin_lock_irq(&dev->event_lock);
11283 intel_crtc->unpin_work = NULL;
11284 spin_unlock_irq(&dev->event_lock);
11285
11286 drm_crtc_vblank_put(crtc);
11287 free_work:
11288 kfree(work);
11289
11290 if (ret == -EIO) {
11291 out_hang:
11292 ret = intel_plane_restore(primary);
11293 if (ret == 0 && event) {
11294 spin_lock_irq(&dev->event_lock);
11295 drm_send_vblank_event(dev, pipe, event);
11296 spin_unlock_irq(&dev->event_lock);
11297 }
11298 }
11299 return ret;
11300 }
11301
11302 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11303 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11304 .load_lut = intel_crtc_load_lut,
11305 .atomic_begin = intel_begin_crtc_commit,
11306 .atomic_flush = intel_finish_crtc_commit,
11307 };
11308
11309 /**
11310 * intel_modeset_update_staged_output_state
11311 *
11312 * Updates the staged output configuration state, e.g. after we've read out the
11313 * current hw state.
11314 */
11315 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11316 {
11317 struct intel_crtc *crtc;
11318 struct intel_encoder *encoder;
11319 struct intel_connector *connector;
11320
11321 for_each_intel_connector(dev, connector) {
11322 connector->new_encoder =
11323 to_intel_encoder(connector->base.encoder);
11324 }
11325
11326 for_each_intel_encoder(dev, encoder) {
11327 encoder->new_crtc =
11328 to_intel_crtc(encoder->base.crtc);
11329 }
11330
11331 for_each_intel_crtc(dev, crtc) {
11332 crtc->new_enabled = crtc->base.state->enable;
11333 }
11334 }
11335
11336 /* Transitional helper to copy current connector/encoder state to
11337 * connector->state. This is needed so that code that is partially
11338 * converted to atomic does the right thing.
11339 */
11340 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11341 {
11342 struct intel_connector *connector;
11343
11344 for_each_intel_connector(dev, connector) {
11345 if (connector->base.encoder) {
11346 connector->base.state->best_encoder =
11347 connector->base.encoder;
11348 connector->base.state->crtc =
11349 connector->base.encoder->crtc;
11350 } else {
11351 connector->base.state->best_encoder = NULL;
11352 connector->base.state->crtc = NULL;
11353 }
11354 }
11355 }
11356
11357 /* Fixup legacy state after an atomic state swap.
11358 */
11359 static void intel_modeset_fixup_state(struct drm_atomic_state *state)
11360 {
11361 struct intel_crtc *crtc;
11362 struct intel_encoder *encoder;
11363 struct intel_connector *connector;
11364
11365 for_each_intel_connector(state->dev, connector) {
11366 connector->base.encoder = connector->base.state->best_encoder;
11367 if (connector->base.encoder)
11368 connector->base.encoder->crtc =
11369 connector->base.state->crtc;
11370 }
11371
11372 /* Update crtc of disabled encoders */
11373 for_each_intel_encoder(state->dev, encoder) {
11374 int num_connectors = 0;
11375
11376 for_each_intel_connector(state->dev, connector)
11377 if (connector->base.encoder == &encoder->base)
11378 num_connectors++;
11379
11380 if (num_connectors == 0)
11381 encoder->base.crtc = NULL;
11382 }
11383
11384 for_each_intel_crtc(state->dev, crtc) {
11385 crtc->base.enabled = crtc->base.state->enable;
11386 crtc->config = to_intel_crtc_state(crtc->base.state);
11387 }
11388
11389 /* Copy the new configuration to the staged state, to keep the few
11390 * pieces of code that haven't been converted yet happy */
11391 intel_modeset_update_staged_output_state(state->dev);
11392 }
11393
11394 static void
11395 connected_sink_compute_bpp(struct intel_connector *connector,
11396 struct intel_crtc_state *pipe_config)
11397 {
11398 int bpp = pipe_config->pipe_bpp;
11399
11400 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11401 connector->base.base.id,
11402 connector->base.name);
11403
11404 /* Don't use an invalid EDID bpc value */
11405 if (connector->base.display_info.bpc &&
11406 connector->base.display_info.bpc * 3 < bpp) {
11407 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11408 bpp, connector->base.display_info.bpc*3);
11409 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11410 }
11411
11412 /* Clamp bpp to 8 on screens without EDID 1.4 */
11413 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11414 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11415 bpp);
11416 pipe_config->pipe_bpp = 24;
11417 }
11418 }
11419
11420 static int
11421 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11422 struct intel_crtc_state *pipe_config)
11423 {
11424 struct drm_device *dev = crtc->base.dev;
11425 struct drm_atomic_state *state;
11426 struct drm_connector *connector;
11427 struct drm_connector_state *connector_state;
11428 int bpp, i;
11429
11430 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11431 bpp = 10*3;
11432 else if (INTEL_INFO(dev)->gen >= 5)
11433 bpp = 12*3;
11434 else
11435 bpp = 8*3;
11436
11437
11438 pipe_config->pipe_bpp = bpp;
11439
11440 state = pipe_config->base.state;
11441
11442 /* Clamp display bpp to EDID value */
11443 for_each_connector_in_state(state, connector, connector_state, i) {
11444 if (connector_state->crtc != &crtc->base)
11445 continue;
11446
11447 connected_sink_compute_bpp(to_intel_connector(connector),
11448 pipe_config);
11449 }
11450
11451 return bpp;
11452 }
11453
11454 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11455 {
11456 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11457 "type: 0x%x flags: 0x%x\n",
11458 mode->crtc_clock,
11459 mode->crtc_hdisplay, mode->crtc_hsync_start,
11460 mode->crtc_hsync_end, mode->crtc_htotal,
11461 mode->crtc_vdisplay, mode->crtc_vsync_start,
11462 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11463 }
11464
11465 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11466 struct intel_crtc_state *pipe_config,
11467 const char *context)
11468 {
11469 struct drm_device *dev = crtc->base.dev;
11470 struct drm_plane *plane;
11471 struct intel_plane *intel_plane;
11472 struct intel_plane_state *state;
11473 struct drm_framebuffer *fb;
11474
11475 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11476 context, pipe_config, pipe_name(crtc->pipe));
11477
11478 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11479 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11480 pipe_config->pipe_bpp, pipe_config->dither);
11481 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11482 pipe_config->has_pch_encoder,
11483 pipe_config->fdi_lanes,
11484 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11485 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11486 pipe_config->fdi_m_n.tu);
11487 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11488 pipe_config->has_dp_encoder,
11489 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11490 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11491 pipe_config->dp_m_n.tu);
11492
11493 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11494 pipe_config->has_dp_encoder,
11495 pipe_config->dp_m2_n2.gmch_m,
11496 pipe_config->dp_m2_n2.gmch_n,
11497 pipe_config->dp_m2_n2.link_m,
11498 pipe_config->dp_m2_n2.link_n,
11499 pipe_config->dp_m2_n2.tu);
11500
11501 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11502 pipe_config->has_audio,
11503 pipe_config->has_infoframe);
11504
11505 DRM_DEBUG_KMS("requested mode:\n");
11506 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11507 DRM_DEBUG_KMS("adjusted mode:\n");
11508 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11509 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11510 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11511 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11512 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11513 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11514 crtc->num_scalers,
11515 pipe_config->scaler_state.scaler_users,
11516 pipe_config->scaler_state.scaler_id);
11517 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11518 pipe_config->gmch_pfit.control,
11519 pipe_config->gmch_pfit.pgm_ratios,
11520 pipe_config->gmch_pfit.lvds_border_bits);
11521 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11522 pipe_config->pch_pfit.pos,
11523 pipe_config->pch_pfit.size,
11524 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11525 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11526 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11527
11528 if (IS_BROXTON(dev)) {
11529 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11530 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11531 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11532 pipe_config->ddi_pll_sel,
11533 pipe_config->dpll_hw_state.ebb0,
11534 pipe_config->dpll_hw_state.pll0,
11535 pipe_config->dpll_hw_state.pll1,
11536 pipe_config->dpll_hw_state.pll2,
11537 pipe_config->dpll_hw_state.pll3,
11538 pipe_config->dpll_hw_state.pll6,
11539 pipe_config->dpll_hw_state.pll8,
11540 pipe_config->dpll_hw_state.pcsdw12);
11541 } else if (IS_SKYLAKE(dev)) {
11542 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11543 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11544 pipe_config->ddi_pll_sel,
11545 pipe_config->dpll_hw_state.ctrl1,
11546 pipe_config->dpll_hw_state.cfgcr1,
11547 pipe_config->dpll_hw_state.cfgcr2);
11548 } else if (HAS_DDI(dev)) {
11549 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11550 pipe_config->ddi_pll_sel,
11551 pipe_config->dpll_hw_state.wrpll);
11552 } else {
11553 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11554 "fp0: 0x%x, fp1: 0x%x\n",
11555 pipe_config->dpll_hw_state.dpll,
11556 pipe_config->dpll_hw_state.dpll_md,
11557 pipe_config->dpll_hw_state.fp0,
11558 pipe_config->dpll_hw_state.fp1);
11559 }
11560
11561 DRM_DEBUG_KMS("planes on this crtc\n");
11562 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11563 intel_plane = to_intel_plane(plane);
11564 if (intel_plane->pipe != crtc->pipe)
11565 continue;
11566
11567 state = to_intel_plane_state(plane->state);
11568 fb = state->base.fb;
11569 if (!fb) {
11570 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11571 "disabled, scaler_id = %d\n",
11572 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11573 plane->base.id, intel_plane->pipe,
11574 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11575 drm_plane_index(plane), state->scaler_id);
11576 continue;
11577 }
11578
11579 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11580 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11581 plane->base.id, intel_plane->pipe,
11582 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11583 drm_plane_index(plane));
11584 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11585 fb->base.id, fb->width, fb->height, fb->pixel_format);
11586 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11587 state->scaler_id,
11588 state->src.x1 >> 16, state->src.y1 >> 16,
11589 drm_rect_width(&state->src) >> 16,
11590 drm_rect_height(&state->src) >> 16,
11591 state->dst.x1, state->dst.y1,
11592 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11593 }
11594 }
11595
11596 static bool encoders_cloneable(const struct intel_encoder *a,
11597 const struct intel_encoder *b)
11598 {
11599 /* masks could be asymmetric, so check both ways */
11600 return a == b || (a->cloneable & (1 << b->type) &&
11601 b->cloneable & (1 << a->type));
11602 }
11603
11604 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11605 struct intel_crtc *crtc,
11606 struct intel_encoder *encoder)
11607 {
11608 struct intel_encoder *source_encoder;
11609 struct drm_connector *connector;
11610 struct drm_connector_state *connector_state;
11611 int i;
11612
11613 for_each_connector_in_state(state, connector, connector_state, i) {
11614 if (connector_state->crtc != &crtc->base)
11615 continue;
11616
11617 source_encoder =
11618 to_intel_encoder(connector_state->best_encoder);
11619 if (!encoders_cloneable(encoder, source_encoder))
11620 return false;
11621 }
11622
11623 return true;
11624 }
11625
11626 static bool check_encoder_cloning(struct drm_atomic_state *state,
11627 struct intel_crtc *crtc)
11628 {
11629 struct intel_encoder *encoder;
11630 struct drm_connector *connector;
11631 struct drm_connector_state *connector_state;
11632 int i;
11633
11634 for_each_connector_in_state(state, connector, connector_state, i) {
11635 if (connector_state->crtc != &crtc->base)
11636 continue;
11637
11638 encoder = to_intel_encoder(connector_state->best_encoder);
11639 if (!check_single_encoder_cloning(state, crtc, encoder))
11640 return false;
11641 }
11642
11643 return true;
11644 }
11645
11646 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11647 {
11648 struct drm_device *dev = state->dev;
11649 struct intel_encoder *encoder;
11650 struct drm_connector *connector;
11651 struct drm_connector_state *connector_state;
11652 unsigned int used_ports = 0;
11653 int i;
11654
11655 /*
11656 * Walk the connector list instead of the encoder
11657 * list to detect the problem on ddi platforms
11658 * where there's just one encoder per digital port.
11659 */
11660 for_each_connector_in_state(state, connector, connector_state, i) {
11661 if (!connector_state->best_encoder)
11662 continue;
11663
11664 encoder = to_intel_encoder(connector_state->best_encoder);
11665
11666 WARN_ON(!connector_state->crtc);
11667
11668 switch (encoder->type) {
11669 unsigned int port_mask;
11670 case INTEL_OUTPUT_UNKNOWN:
11671 if (WARN_ON(!HAS_DDI(dev)))
11672 break;
11673 case INTEL_OUTPUT_DISPLAYPORT:
11674 case INTEL_OUTPUT_HDMI:
11675 case INTEL_OUTPUT_EDP:
11676 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11677
11678 /* the same port mustn't appear more than once */
11679 if (used_ports & port_mask)
11680 return false;
11681
11682 used_ports |= port_mask;
11683 default:
11684 break;
11685 }
11686 }
11687
11688 return true;
11689 }
11690
11691 static void
11692 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11693 {
11694 struct drm_crtc_state tmp_state;
11695 struct intel_crtc_scaler_state scaler_state;
11696 struct intel_dpll_hw_state dpll_hw_state;
11697 enum intel_dpll_id shared_dpll;
11698 uint32_t ddi_pll_sel;
11699
11700 /* FIXME: before the switch to atomic started, a new pipe_config was
11701 * kzalloc'd. Code that depends on any field being zero should be
11702 * fixed, so that the crtc_state can be safely duplicated. For now,
11703 * only fields that are know to not cause problems are preserved. */
11704
11705 tmp_state = crtc_state->base;
11706 scaler_state = crtc_state->scaler_state;
11707 shared_dpll = crtc_state->shared_dpll;
11708 dpll_hw_state = crtc_state->dpll_hw_state;
11709 ddi_pll_sel = crtc_state->ddi_pll_sel;
11710
11711 memset(crtc_state, 0, sizeof *crtc_state);
11712
11713 crtc_state->base = tmp_state;
11714 crtc_state->scaler_state = scaler_state;
11715 crtc_state->shared_dpll = shared_dpll;
11716 crtc_state->dpll_hw_state = dpll_hw_state;
11717 crtc_state->ddi_pll_sel = ddi_pll_sel;
11718 }
11719
11720 static int
11721 intel_modeset_pipe_config(struct drm_crtc *crtc,
11722 struct drm_atomic_state *state,
11723 struct intel_crtc_state *pipe_config)
11724 {
11725 struct intel_encoder *encoder;
11726 struct drm_connector *connector;
11727 struct drm_connector_state *connector_state;
11728 int base_bpp, ret = -EINVAL;
11729 int i;
11730 bool retry = true;
11731
11732 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11733 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11734 return -EINVAL;
11735 }
11736
11737 if (!check_digital_port_conflicts(state)) {
11738 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11739 return -EINVAL;
11740 }
11741
11742 clear_intel_crtc_state(pipe_config);
11743
11744 pipe_config->cpu_transcoder =
11745 (enum transcoder) to_intel_crtc(crtc)->pipe;
11746
11747 /*
11748 * Sanitize sync polarity flags based on requested ones. If neither
11749 * positive or negative polarity is requested, treat this as meaning
11750 * negative polarity.
11751 */
11752 if (!(pipe_config->base.adjusted_mode.flags &
11753 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11754 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11755
11756 if (!(pipe_config->base.adjusted_mode.flags &
11757 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11758 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11759
11760 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11761 * plane pixel format and any sink constraints into account. Returns the
11762 * source plane bpp so that dithering can be selected on mismatches
11763 * after encoders and crtc also have had their say. */
11764 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11765 pipe_config);
11766 if (base_bpp < 0)
11767 goto fail;
11768
11769 /*
11770 * Determine the real pipe dimensions. Note that stereo modes can
11771 * increase the actual pipe size due to the frame doubling and
11772 * insertion of additional space for blanks between the frame. This
11773 * is stored in the crtc timings. We use the requested mode to do this
11774 * computation to clearly distinguish it from the adjusted mode, which
11775 * can be changed by the connectors in the below retry loop.
11776 */
11777 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11778 &pipe_config->pipe_src_w,
11779 &pipe_config->pipe_src_h);
11780
11781 encoder_retry:
11782 /* Ensure the port clock defaults are reset when retrying. */
11783 pipe_config->port_clock = 0;
11784 pipe_config->pixel_multiplier = 1;
11785
11786 /* Fill in default crtc timings, allow encoders to overwrite them. */
11787 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11788 CRTC_STEREO_DOUBLE);
11789
11790 /* Pass our mode to the connectors and the CRTC to give them a chance to
11791 * adjust it according to limitations or connector properties, and also
11792 * a chance to reject the mode entirely.
11793 */
11794 for_each_connector_in_state(state, connector, connector_state, i) {
11795 if (connector_state->crtc != crtc)
11796 continue;
11797
11798 encoder = to_intel_encoder(connector_state->best_encoder);
11799
11800 if (!(encoder->compute_config(encoder, pipe_config))) {
11801 DRM_DEBUG_KMS("Encoder config failure\n");
11802 goto fail;
11803 }
11804 }
11805
11806 /* Set default port clock if not overwritten by the encoder. Needs to be
11807 * done afterwards in case the encoder adjusts the mode. */
11808 if (!pipe_config->port_clock)
11809 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11810 * pipe_config->pixel_multiplier;
11811
11812 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11813 if (ret < 0) {
11814 DRM_DEBUG_KMS("CRTC fixup failed\n");
11815 goto fail;
11816 }
11817
11818 if (ret == RETRY) {
11819 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11820 ret = -EINVAL;
11821 goto fail;
11822 }
11823
11824 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11825 retry = false;
11826 goto encoder_retry;
11827 }
11828
11829 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11830 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11831 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11832
11833 return 0;
11834 fail:
11835 return ret;
11836 }
11837
11838 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11839 {
11840 struct drm_encoder *encoder;
11841 struct drm_device *dev = crtc->dev;
11842
11843 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11844 if (encoder->crtc == crtc)
11845 return true;
11846
11847 return false;
11848 }
11849
11850 static bool
11851 needs_modeset(struct drm_crtc_state *state)
11852 {
11853 return state->mode_changed || state->active_changed;
11854 }
11855
11856 static void
11857 intel_modeset_update_state(struct drm_atomic_state *state)
11858 {
11859 struct drm_device *dev = state->dev;
11860 struct drm_i915_private *dev_priv = dev->dev_private;
11861 struct intel_encoder *intel_encoder;
11862 struct drm_crtc *crtc;
11863 struct drm_crtc_state *crtc_state;
11864 struct drm_connector *connector;
11865 int i;
11866
11867 intel_shared_dpll_commit(dev_priv);
11868
11869 for_each_intel_encoder(dev, intel_encoder) {
11870 if (!intel_encoder->base.crtc)
11871 continue;
11872
11873 for_each_crtc_in_state(state, crtc, crtc_state, i)
11874 if (crtc == intel_encoder->base.crtc)
11875 break;
11876
11877 if (crtc != intel_encoder->base.crtc)
11878 continue;
11879
11880 if (crtc_state->enable && needs_modeset(crtc_state))
11881 intel_encoder->connectors_active = false;
11882 }
11883
11884 drm_atomic_helper_swap_state(state->dev, state);
11885 intel_modeset_fixup_state(state);
11886
11887 /* Double check state. */
11888 for_each_crtc(dev, crtc) {
11889 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11890 }
11891
11892 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11893 if (!connector->encoder || !connector->encoder->crtc)
11894 continue;
11895
11896 for_each_crtc_in_state(state, crtc, crtc_state, i)
11897 if (crtc == connector->encoder->crtc)
11898 break;
11899
11900 if (crtc != connector->encoder->crtc)
11901 continue;
11902
11903 if (crtc->state->enable && needs_modeset(crtc->state)) {
11904 struct drm_property *dpms_property =
11905 dev->mode_config.dpms_property;
11906
11907 connector->dpms = DRM_MODE_DPMS_ON;
11908 drm_object_property_set_value(&connector->base,
11909 dpms_property,
11910 DRM_MODE_DPMS_ON);
11911
11912 intel_encoder = to_intel_encoder(connector->encoder);
11913 intel_encoder->connectors_active = true;
11914 }
11915 }
11916
11917 }
11918
11919 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11920 {
11921 int diff;
11922
11923 if (clock1 == clock2)
11924 return true;
11925
11926 if (!clock1 || !clock2)
11927 return false;
11928
11929 diff = abs(clock1 - clock2);
11930
11931 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11932 return true;
11933
11934 return false;
11935 }
11936
11937 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11938 list_for_each_entry((intel_crtc), \
11939 &(dev)->mode_config.crtc_list, \
11940 base.head) \
11941 if (mask & (1 <<(intel_crtc)->pipe))
11942
11943 static bool
11944 intel_pipe_config_compare(struct drm_device *dev,
11945 struct intel_crtc_state *current_config,
11946 struct intel_crtc_state *pipe_config)
11947 {
11948 #define PIPE_CONF_CHECK_X(name) \
11949 if (current_config->name != pipe_config->name) { \
11950 DRM_ERROR("mismatch in " #name " " \
11951 "(expected 0x%08x, found 0x%08x)\n", \
11952 current_config->name, \
11953 pipe_config->name); \
11954 return false; \
11955 }
11956
11957 #define PIPE_CONF_CHECK_I(name) \
11958 if (current_config->name != pipe_config->name) { \
11959 DRM_ERROR("mismatch in " #name " " \
11960 "(expected %i, found %i)\n", \
11961 current_config->name, \
11962 pipe_config->name); \
11963 return false; \
11964 }
11965
11966 /* This is required for BDW+ where there is only one set of registers for
11967 * switching between high and low RR.
11968 * This macro can be used whenever a comparison has to be made between one
11969 * hw state and multiple sw state variables.
11970 */
11971 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11972 if ((current_config->name != pipe_config->name) && \
11973 (current_config->alt_name != pipe_config->name)) { \
11974 DRM_ERROR("mismatch in " #name " " \
11975 "(expected %i or %i, found %i)\n", \
11976 current_config->name, \
11977 current_config->alt_name, \
11978 pipe_config->name); \
11979 return false; \
11980 }
11981
11982 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11983 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11984 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11985 "(expected %i, found %i)\n", \
11986 current_config->name & (mask), \
11987 pipe_config->name & (mask)); \
11988 return false; \
11989 }
11990
11991 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11992 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11993 DRM_ERROR("mismatch in " #name " " \
11994 "(expected %i, found %i)\n", \
11995 current_config->name, \
11996 pipe_config->name); \
11997 return false; \
11998 }
11999
12000 #define PIPE_CONF_QUIRK(quirk) \
12001 ((current_config->quirks | pipe_config->quirks) & (quirk))
12002
12003 PIPE_CONF_CHECK_I(cpu_transcoder);
12004
12005 PIPE_CONF_CHECK_I(has_pch_encoder);
12006 PIPE_CONF_CHECK_I(fdi_lanes);
12007 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12008 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12009 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12010 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12011 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12012
12013 PIPE_CONF_CHECK_I(has_dp_encoder);
12014
12015 if (INTEL_INFO(dev)->gen < 8) {
12016 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12017 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12018 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12019 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12020 PIPE_CONF_CHECK_I(dp_m_n.tu);
12021
12022 if (current_config->has_drrs) {
12023 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12024 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12025 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12026 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12027 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12028 }
12029 } else {
12030 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12031 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12032 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12033 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12034 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12035 }
12036
12037 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12038 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12039 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12040 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12041 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12042 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12043
12044 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12045 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12046 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12047 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12048 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12049 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12050
12051 PIPE_CONF_CHECK_I(pixel_multiplier);
12052 PIPE_CONF_CHECK_I(has_hdmi_sink);
12053 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12054 IS_VALLEYVIEW(dev))
12055 PIPE_CONF_CHECK_I(limited_color_range);
12056 PIPE_CONF_CHECK_I(has_infoframe);
12057
12058 PIPE_CONF_CHECK_I(has_audio);
12059
12060 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12061 DRM_MODE_FLAG_INTERLACE);
12062
12063 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12064 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12065 DRM_MODE_FLAG_PHSYNC);
12066 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12067 DRM_MODE_FLAG_NHSYNC);
12068 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12069 DRM_MODE_FLAG_PVSYNC);
12070 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12071 DRM_MODE_FLAG_NVSYNC);
12072 }
12073
12074 PIPE_CONF_CHECK_I(pipe_src_w);
12075 PIPE_CONF_CHECK_I(pipe_src_h);
12076
12077 /*
12078 * FIXME: BIOS likes to set up a cloned config with lvds+external
12079 * screen. Since we don't yet re-compute the pipe config when moving
12080 * just the lvds port away to another pipe the sw tracking won't match.
12081 *
12082 * Proper atomic modesets with recomputed global state will fix this.
12083 * Until then just don't check gmch state for inherited modes.
12084 */
12085 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12086 PIPE_CONF_CHECK_I(gmch_pfit.control);
12087 /* pfit ratios are autocomputed by the hw on gen4+ */
12088 if (INTEL_INFO(dev)->gen < 4)
12089 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12090 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12091 }
12092
12093 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12094 if (current_config->pch_pfit.enabled) {
12095 PIPE_CONF_CHECK_I(pch_pfit.pos);
12096 PIPE_CONF_CHECK_I(pch_pfit.size);
12097 }
12098
12099 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12100
12101 /* BDW+ don't expose a synchronous way to read the state */
12102 if (IS_HASWELL(dev))
12103 PIPE_CONF_CHECK_I(ips_enabled);
12104
12105 PIPE_CONF_CHECK_I(double_wide);
12106
12107 PIPE_CONF_CHECK_X(ddi_pll_sel);
12108
12109 PIPE_CONF_CHECK_I(shared_dpll);
12110 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12111 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12112 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12113 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12114 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12115 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12116 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12117 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12118
12119 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12120 PIPE_CONF_CHECK_I(pipe_bpp);
12121
12122 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12123 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12124
12125 #undef PIPE_CONF_CHECK_X
12126 #undef PIPE_CONF_CHECK_I
12127 #undef PIPE_CONF_CHECK_I_ALT
12128 #undef PIPE_CONF_CHECK_FLAGS
12129 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12130 #undef PIPE_CONF_QUIRK
12131
12132 return true;
12133 }
12134
12135 static void check_wm_state(struct drm_device *dev)
12136 {
12137 struct drm_i915_private *dev_priv = dev->dev_private;
12138 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12139 struct intel_crtc *intel_crtc;
12140 int plane;
12141
12142 if (INTEL_INFO(dev)->gen < 9)
12143 return;
12144
12145 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12146 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12147
12148 for_each_intel_crtc(dev, intel_crtc) {
12149 struct skl_ddb_entry *hw_entry, *sw_entry;
12150 const enum pipe pipe = intel_crtc->pipe;
12151
12152 if (!intel_crtc->active)
12153 continue;
12154
12155 /* planes */
12156 for_each_plane(dev_priv, pipe, plane) {
12157 hw_entry = &hw_ddb.plane[pipe][plane];
12158 sw_entry = &sw_ddb->plane[pipe][plane];
12159
12160 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12161 continue;
12162
12163 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12164 "(expected (%u,%u), found (%u,%u))\n",
12165 pipe_name(pipe), plane + 1,
12166 sw_entry->start, sw_entry->end,
12167 hw_entry->start, hw_entry->end);
12168 }
12169
12170 /* cursor */
12171 hw_entry = &hw_ddb.cursor[pipe];
12172 sw_entry = &sw_ddb->cursor[pipe];
12173
12174 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12175 continue;
12176
12177 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12178 "(expected (%u,%u), found (%u,%u))\n",
12179 pipe_name(pipe),
12180 sw_entry->start, sw_entry->end,
12181 hw_entry->start, hw_entry->end);
12182 }
12183 }
12184
12185 static void
12186 check_connector_state(struct drm_device *dev)
12187 {
12188 struct intel_connector *connector;
12189
12190 for_each_intel_connector(dev, connector) {
12191 /* This also checks the encoder/connector hw state with the
12192 * ->get_hw_state callbacks. */
12193 intel_connector_check_state(connector);
12194
12195 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12196 "connector's staged encoder doesn't match current encoder\n");
12197 }
12198 }
12199
12200 static void
12201 check_encoder_state(struct drm_device *dev)
12202 {
12203 struct intel_encoder *encoder;
12204 struct intel_connector *connector;
12205
12206 for_each_intel_encoder(dev, encoder) {
12207 bool enabled = false;
12208 bool active = false;
12209 enum pipe pipe, tracked_pipe;
12210
12211 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12212 encoder->base.base.id,
12213 encoder->base.name);
12214
12215 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12216 "encoder's stage crtc doesn't match current crtc\n");
12217 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12218 "encoder's active_connectors set, but no crtc\n");
12219
12220 for_each_intel_connector(dev, connector) {
12221 if (connector->base.encoder != &encoder->base)
12222 continue;
12223 enabled = true;
12224 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12225 active = true;
12226 }
12227 /*
12228 * for MST connectors if we unplug the connector is gone
12229 * away but the encoder is still connected to a crtc
12230 * until a modeset happens in response to the hotplug.
12231 */
12232 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12233 continue;
12234
12235 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12236 "encoder's enabled state mismatch "
12237 "(expected %i, found %i)\n",
12238 !!encoder->base.crtc, enabled);
12239 I915_STATE_WARN(active && !encoder->base.crtc,
12240 "active encoder with no crtc\n");
12241
12242 I915_STATE_WARN(encoder->connectors_active != active,
12243 "encoder's computed active state doesn't match tracked active state "
12244 "(expected %i, found %i)\n", active, encoder->connectors_active);
12245
12246 active = encoder->get_hw_state(encoder, &pipe);
12247 I915_STATE_WARN(active != encoder->connectors_active,
12248 "encoder's hw state doesn't match sw tracking "
12249 "(expected %i, found %i)\n",
12250 encoder->connectors_active, active);
12251
12252 if (!encoder->base.crtc)
12253 continue;
12254
12255 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12256 I915_STATE_WARN(active && pipe != tracked_pipe,
12257 "active encoder's pipe doesn't match"
12258 "(expected %i, found %i)\n",
12259 tracked_pipe, pipe);
12260
12261 }
12262 }
12263
12264 static void
12265 check_crtc_state(struct drm_device *dev)
12266 {
12267 struct drm_i915_private *dev_priv = dev->dev_private;
12268 struct intel_crtc *crtc;
12269 struct intel_encoder *encoder;
12270 struct intel_crtc_state pipe_config;
12271
12272 for_each_intel_crtc(dev, crtc) {
12273 bool enabled = false;
12274 bool active = false;
12275
12276 memset(&pipe_config, 0, sizeof(pipe_config));
12277
12278 DRM_DEBUG_KMS("[CRTC:%d]\n",
12279 crtc->base.base.id);
12280
12281 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12282 "active crtc, but not enabled in sw tracking\n");
12283
12284 for_each_intel_encoder(dev, encoder) {
12285 if (encoder->base.crtc != &crtc->base)
12286 continue;
12287 enabled = true;
12288 if (encoder->connectors_active)
12289 active = true;
12290 }
12291
12292 I915_STATE_WARN(active != crtc->active,
12293 "crtc's computed active state doesn't match tracked active state "
12294 "(expected %i, found %i)\n", active, crtc->active);
12295 I915_STATE_WARN(enabled != crtc->base.state->enable,
12296 "crtc's computed enabled state doesn't match tracked enabled state "
12297 "(expected %i, found %i)\n", enabled,
12298 crtc->base.state->enable);
12299
12300 active = dev_priv->display.get_pipe_config(crtc,
12301 &pipe_config);
12302
12303 /* hw state is inconsistent with the pipe quirk */
12304 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12305 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12306 active = crtc->active;
12307
12308 for_each_intel_encoder(dev, encoder) {
12309 enum pipe pipe;
12310 if (encoder->base.crtc != &crtc->base)
12311 continue;
12312 if (encoder->get_hw_state(encoder, &pipe))
12313 encoder->get_config(encoder, &pipe_config);
12314 }
12315
12316 I915_STATE_WARN(crtc->active != active,
12317 "crtc active state doesn't match with hw state "
12318 "(expected %i, found %i)\n", crtc->active, active);
12319
12320 if (active &&
12321 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12322 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12323 intel_dump_pipe_config(crtc, &pipe_config,
12324 "[hw state]");
12325 intel_dump_pipe_config(crtc, crtc->config,
12326 "[sw state]");
12327 }
12328 }
12329 }
12330
12331 static void
12332 check_shared_dpll_state(struct drm_device *dev)
12333 {
12334 struct drm_i915_private *dev_priv = dev->dev_private;
12335 struct intel_crtc *crtc;
12336 struct intel_dpll_hw_state dpll_hw_state;
12337 int i;
12338
12339 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12340 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12341 int enabled_crtcs = 0, active_crtcs = 0;
12342 bool active;
12343
12344 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12345
12346 DRM_DEBUG_KMS("%s\n", pll->name);
12347
12348 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12349
12350 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12351 "more active pll users than references: %i vs %i\n",
12352 pll->active, hweight32(pll->config.crtc_mask));
12353 I915_STATE_WARN(pll->active && !pll->on,
12354 "pll in active use but not on in sw tracking\n");
12355 I915_STATE_WARN(pll->on && !pll->active,
12356 "pll in on but not on in use in sw tracking\n");
12357 I915_STATE_WARN(pll->on != active,
12358 "pll on state mismatch (expected %i, found %i)\n",
12359 pll->on, active);
12360
12361 for_each_intel_crtc(dev, crtc) {
12362 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12363 enabled_crtcs++;
12364 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12365 active_crtcs++;
12366 }
12367 I915_STATE_WARN(pll->active != active_crtcs,
12368 "pll active crtcs mismatch (expected %i, found %i)\n",
12369 pll->active, active_crtcs);
12370 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12371 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12372 hweight32(pll->config.crtc_mask), enabled_crtcs);
12373
12374 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12375 sizeof(dpll_hw_state)),
12376 "pll hw state mismatch\n");
12377 }
12378 }
12379
12380 void
12381 intel_modeset_check_state(struct drm_device *dev)
12382 {
12383 check_wm_state(dev);
12384 check_connector_state(dev);
12385 check_encoder_state(dev);
12386 check_crtc_state(dev);
12387 check_shared_dpll_state(dev);
12388 }
12389
12390 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12391 int dotclock)
12392 {
12393 /*
12394 * FDI already provided one idea for the dotclock.
12395 * Yell if the encoder disagrees.
12396 */
12397 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12398 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12399 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12400 }
12401
12402 static void update_scanline_offset(struct intel_crtc *crtc)
12403 {
12404 struct drm_device *dev = crtc->base.dev;
12405
12406 /*
12407 * The scanline counter increments at the leading edge of hsync.
12408 *
12409 * On most platforms it starts counting from vtotal-1 on the
12410 * first active line. That means the scanline counter value is
12411 * always one less than what we would expect. Ie. just after
12412 * start of vblank, which also occurs at start of hsync (on the
12413 * last active line), the scanline counter will read vblank_start-1.
12414 *
12415 * On gen2 the scanline counter starts counting from 1 instead
12416 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12417 * to keep the value positive), instead of adding one.
12418 *
12419 * On HSW+ the behaviour of the scanline counter depends on the output
12420 * type. For DP ports it behaves like most other platforms, but on HDMI
12421 * there's an extra 1 line difference. So we need to add two instead of
12422 * one to the value.
12423 */
12424 if (IS_GEN2(dev)) {
12425 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12426 int vtotal;
12427
12428 vtotal = mode->crtc_vtotal;
12429 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12430 vtotal /= 2;
12431
12432 crtc->scanline_offset = vtotal - 1;
12433 } else if (HAS_DDI(dev) &&
12434 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12435 crtc->scanline_offset = 2;
12436 } else
12437 crtc->scanline_offset = 1;
12438 }
12439
12440 static struct intel_crtc_state *
12441 intel_modeset_compute_config(struct drm_crtc *crtc,
12442 struct drm_atomic_state *state)
12443 {
12444 struct intel_crtc_state *pipe_config;
12445 int ret = 0;
12446
12447 ret = drm_atomic_add_affected_connectors(state, crtc);
12448 if (ret)
12449 return ERR_PTR(ret);
12450
12451 ret = drm_atomic_helper_check_modeset(state->dev, state);
12452 if (ret)
12453 return ERR_PTR(ret);
12454
12455 /*
12456 * Note this needs changes when we start tracking multiple modes
12457 * and crtcs. At that point we'll need to compute the whole config
12458 * (i.e. one pipe_config for each crtc) rather than just the one
12459 * for this crtc.
12460 */
12461 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12462 if (IS_ERR(pipe_config))
12463 return pipe_config;
12464
12465 if (!pipe_config->base.enable)
12466 return pipe_config;
12467
12468 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12469 if (ret)
12470 return ERR_PTR(ret);
12471
12472 /* Check things that can only be changed through modeset */
12473 if (pipe_config->has_audio !=
12474 to_intel_crtc(crtc)->config->has_audio)
12475 pipe_config->base.mode_changed = true;
12476
12477 /*
12478 * Note we have an issue here with infoframes: current code
12479 * only updates them on the full mode set path per hw
12480 * requirements. So here we should be checking for any
12481 * required changes and forcing a mode set.
12482 */
12483
12484 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12485
12486 ret = drm_atomic_helper_check_planes(state->dev, state);
12487 if (ret)
12488 return ERR_PTR(ret);
12489
12490 return pipe_config;
12491 }
12492
12493 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12494 {
12495 struct drm_device *dev = state->dev;
12496 struct drm_i915_private *dev_priv = to_i915(dev);
12497 unsigned clear_pipes = 0;
12498 struct intel_crtc *intel_crtc;
12499 struct intel_crtc_state *intel_crtc_state;
12500 struct drm_crtc *crtc;
12501 struct drm_crtc_state *crtc_state;
12502 int ret = 0;
12503 int i;
12504
12505 if (!dev_priv->display.crtc_compute_clock)
12506 return 0;
12507
12508 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12509 intel_crtc = to_intel_crtc(crtc);
12510 intel_crtc_state = to_intel_crtc_state(crtc_state);
12511
12512 if (needs_modeset(crtc_state)) {
12513 clear_pipes |= 1 << intel_crtc->pipe;
12514 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12515 }
12516 }
12517
12518 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12519 if (ret)
12520 goto done;
12521
12522 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12523 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12524 continue;
12525
12526 intel_crtc = to_intel_crtc(crtc);
12527 intel_crtc_state = to_intel_crtc_state(crtc_state);
12528
12529 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12530 intel_crtc_state);
12531 if (ret) {
12532 intel_shared_dpll_abort_config(dev_priv);
12533 goto done;
12534 }
12535 }
12536
12537 done:
12538 return ret;
12539 }
12540
12541 /* Code that should eventually be part of atomic_check() */
12542 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12543 {
12544 struct drm_device *dev = state->dev;
12545 int ret;
12546
12547 /*
12548 * See if the config requires any additional preparation, e.g.
12549 * to adjust global state with pipes off. We need to do this
12550 * here so we can get the modeset_pipe updated config for the new
12551 * mode set on this crtc. For other crtcs we need to use the
12552 * adjusted_mode bits in the crtc directly.
12553 */
12554 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12555 ret = valleyview_modeset_global_pipes(state);
12556 if (ret)
12557 return ret;
12558 }
12559
12560 ret = __intel_set_mode_setup_plls(state);
12561 if (ret)
12562 return ret;
12563
12564 return 0;
12565 }
12566
12567 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12568 struct intel_crtc_state *pipe_config)
12569 {
12570 struct drm_device *dev = modeset_crtc->dev;
12571 struct drm_i915_private *dev_priv = dev->dev_private;
12572 struct drm_atomic_state *state = pipe_config->base.state;
12573 struct drm_crtc *crtc;
12574 struct drm_crtc_state *crtc_state;
12575 int ret = 0;
12576 int i;
12577
12578 ret = __intel_set_mode_checks(state);
12579 if (ret < 0)
12580 return ret;
12581
12582 ret = drm_atomic_helper_prepare_planes(dev, state);
12583 if (ret)
12584 return ret;
12585
12586 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12587 if (!needs_modeset(crtc_state))
12588 continue;
12589
12590 if (!crtc_state->enable) {
12591 intel_crtc_disable(crtc);
12592 } else if (crtc->state->enable) {
12593 intel_crtc_disable_planes(crtc);
12594 dev_priv->display.crtc_disable(crtc);
12595 }
12596 }
12597
12598 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12599 * to set it here already despite that we pass it down the callchain.
12600 *
12601 * Note we'll need to fix this up when we start tracking multiple
12602 * pipes; here we assume a single modeset_pipe and only track the
12603 * single crtc and mode.
12604 */
12605 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12606 modeset_crtc->mode = pipe_config->base.mode;
12607
12608 /*
12609 * Calculate and store various constants which
12610 * are later needed by vblank and swap-completion
12611 * timestamping. They are derived from true hwmode.
12612 */
12613 drm_calc_timestamping_constants(modeset_crtc,
12614 &pipe_config->base.adjusted_mode);
12615 }
12616
12617 /* Only after disabling all output pipelines that will be changed can we
12618 * update the the output configuration. */
12619 intel_modeset_update_state(state);
12620
12621 /* The state has been swaped above, so state actually contains the
12622 * old state now. */
12623
12624 modeset_update_crtc_power_domains(state);
12625
12626 drm_atomic_helper_commit_planes(dev, state);
12627
12628 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12629 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12630 if (!needs_modeset(crtc->state) || !crtc->state->enable)
12631 continue;
12632
12633 update_scanline_offset(to_intel_crtc(crtc));
12634
12635 dev_priv->display.crtc_enable(crtc);
12636 intel_crtc_enable_planes(crtc);
12637 }
12638
12639 /* FIXME: add subpixel order */
12640
12641 drm_atomic_helper_cleanup_planes(dev, state);
12642
12643 drm_atomic_state_free(state);
12644
12645 return 0;
12646 }
12647
12648 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12649 struct intel_crtc_state *pipe_config)
12650 {
12651 int ret;
12652
12653 ret = __intel_set_mode(crtc, pipe_config);
12654
12655 if (ret == 0)
12656 intel_modeset_check_state(crtc->dev);
12657
12658 return ret;
12659 }
12660
12661 static int intel_set_mode(struct drm_crtc *crtc,
12662 struct drm_atomic_state *state)
12663 {
12664 struct intel_crtc_state *pipe_config;
12665 int ret = 0;
12666
12667 pipe_config = intel_modeset_compute_config(crtc, state);
12668 if (IS_ERR(pipe_config)) {
12669 ret = PTR_ERR(pipe_config);
12670 goto out;
12671 }
12672
12673 ret = intel_set_mode_with_config(crtc, pipe_config);
12674 if (ret)
12675 goto out;
12676
12677 out:
12678 return ret;
12679 }
12680
12681 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12682 {
12683 struct drm_device *dev = crtc->dev;
12684 struct drm_atomic_state *state;
12685 struct intel_crtc *intel_crtc;
12686 struct intel_encoder *encoder;
12687 struct intel_connector *connector;
12688 struct drm_connector_state *connector_state;
12689 struct intel_crtc_state *crtc_state;
12690 int ret;
12691
12692 state = drm_atomic_state_alloc(dev);
12693 if (!state) {
12694 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12695 crtc->base.id);
12696 return;
12697 }
12698
12699 state->acquire_ctx = dev->mode_config.acquire_ctx;
12700
12701 /* The force restore path in the HW readout code relies on the staged
12702 * config still keeping the user requested config while the actual
12703 * state has been overwritten by the configuration read from HW. We
12704 * need to copy the staged config to the atomic state, otherwise the
12705 * mode set will just reapply the state the HW is already in. */
12706 for_each_intel_encoder(dev, encoder) {
12707 if (&encoder->new_crtc->base != crtc)
12708 continue;
12709
12710 for_each_intel_connector(dev, connector) {
12711 if (connector->new_encoder != encoder)
12712 continue;
12713
12714 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12715 if (IS_ERR(connector_state)) {
12716 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12717 connector->base.base.id,
12718 connector->base.name,
12719 PTR_ERR(connector_state));
12720 continue;
12721 }
12722
12723 connector_state->crtc = crtc;
12724 connector_state->best_encoder = &encoder->base;
12725 }
12726 }
12727
12728 for_each_intel_crtc(dev, intel_crtc) {
12729 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12730 continue;
12731
12732 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12733 if (IS_ERR(crtc_state)) {
12734 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12735 intel_crtc->base.base.id,
12736 PTR_ERR(crtc_state));
12737 continue;
12738 }
12739
12740 crtc_state->base.active = crtc_state->base.enable =
12741 intel_crtc->new_enabled;
12742
12743 if (&intel_crtc->base == crtc)
12744 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12745 }
12746
12747 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12748 crtc->primary->fb, crtc->x, crtc->y);
12749
12750 ret = intel_set_mode(crtc, state);
12751 if (ret)
12752 drm_atomic_state_free(state);
12753 }
12754
12755 #undef for_each_intel_crtc_masked
12756
12757 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12758 struct drm_mode_set *set)
12759 {
12760 int ro;
12761
12762 for (ro = 0; ro < set->num_connectors; ro++)
12763 if (set->connectors[ro] == &connector->base)
12764 return true;
12765
12766 return false;
12767 }
12768
12769 static int
12770 intel_modeset_stage_output_state(struct drm_device *dev,
12771 struct drm_mode_set *set,
12772 struct drm_atomic_state *state)
12773 {
12774 struct intel_connector *connector;
12775 struct drm_connector *drm_connector;
12776 struct drm_connector_state *connector_state;
12777 struct drm_crtc *crtc;
12778 struct drm_crtc_state *crtc_state;
12779 int i, ret;
12780
12781 /* The upper layers ensure that we either disable a crtc or have a list
12782 * of connectors. For paranoia, double-check this. */
12783 WARN_ON(!set->fb && (set->num_connectors != 0));
12784 WARN_ON(set->fb && (set->num_connectors == 0));
12785
12786 for_each_intel_connector(dev, connector) {
12787 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12788
12789 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12790 continue;
12791
12792 connector_state =
12793 drm_atomic_get_connector_state(state, &connector->base);
12794 if (IS_ERR(connector_state))
12795 return PTR_ERR(connector_state);
12796
12797 if (in_mode_set) {
12798 int pipe = to_intel_crtc(set->crtc)->pipe;
12799 connector_state->best_encoder =
12800 &intel_find_encoder(connector, pipe)->base;
12801 }
12802
12803 if (connector->base.state->crtc != set->crtc)
12804 continue;
12805
12806 /* If we disable the crtc, disable all its connectors. Also, if
12807 * the connector is on the changing crtc but not on the new
12808 * connector list, disable it. */
12809 if (!set->fb || !in_mode_set) {
12810 connector_state->best_encoder = NULL;
12811
12812 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12813 connector->base.base.id,
12814 connector->base.name);
12815 }
12816 }
12817 /* connector->new_encoder is now updated for all connectors. */
12818
12819 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12820 connector = to_intel_connector(drm_connector);
12821
12822 if (!connector_state->best_encoder) {
12823 ret = drm_atomic_set_crtc_for_connector(connector_state,
12824 NULL);
12825 if (ret)
12826 return ret;
12827
12828 continue;
12829 }
12830
12831 if (intel_connector_in_mode_set(connector, set)) {
12832 struct drm_crtc *crtc = connector->base.state->crtc;
12833
12834 /* If this connector was in a previous crtc, add it
12835 * to the state. We might need to disable it. */
12836 if (crtc) {
12837 crtc_state =
12838 drm_atomic_get_crtc_state(state, crtc);
12839 if (IS_ERR(crtc_state))
12840 return PTR_ERR(crtc_state);
12841 }
12842
12843 ret = drm_atomic_set_crtc_for_connector(connector_state,
12844 set->crtc);
12845 if (ret)
12846 return ret;
12847 }
12848
12849 /* Make sure the new CRTC will work with the encoder */
12850 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12851 connector_state->crtc)) {
12852 return -EINVAL;
12853 }
12854
12855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12856 connector->base.base.id,
12857 connector->base.name,
12858 connector_state->crtc->base.id);
12859
12860 if (connector_state->best_encoder != &connector->encoder->base)
12861 connector->encoder =
12862 to_intel_encoder(connector_state->best_encoder);
12863 }
12864
12865 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12866 bool has_connectors;
12867
12868 ret = drm_atomic_add_affected_connectors(state, crtc);
12869 if (ret)
12870 return ret;
12871
12872 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12873 if (has_connectors != crtc_state->enable)
12874 crtc_state->enable =
12875 crtc_state->active = has_connectors;
12876 }
12877
12878 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12879 set->fb, set->x, set->y);
12880 if (ret)
12881 return ret;
12882
12883 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12884 if (IS_ERR(crtc_state))
12885 return PTR_ERR(crtc_state);
12886
12887 if (set->mode)
12888 drm_mode_copy(&crtc_state->mode, set->mode);
12889
12890 if (set->num_connectors)
12891 crtc_state->active = true;
12892
12893 return 0;
12894 }
12895
12896 static bool primary_plane_visible(struct drm_crtc *crtc)
12897 {
12898 struct intel_plane_state *plane_state =
12899 to_intel_plane_state(crtc->primary->state);
12900
12901 return plane_state->visible;
12902 }
12903
12904 static int intel_crtc_set_config(struct drm_mode_set *set)
12905 {
12906 struct drm_device *dev;
12907 struct drm_atomic_state *state = NULL;
12908 struct intel_crtc_state *pipe_config;
12909 bool primary_plane_was_visible;
12910 int ret;
12911
12912 BUG_ON(!set);
12913 BUG_ON(!set->crtc);
12914 BUG_ON(!set->crtc->helper_private);
12915
12916 /* Enforce sane interface api - has been abused by the fb helper. */
12917 BUG_ON(!set->mode && set->fb);
12918 BUG_ON(set->fb && set->num_connectors == 0);
12919
12920 if (set->fb) {
12921 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12922 set->crtc->base.id, set->fb->base.id,
12923 (int)set->num_connectors, set->x, set->y);
12924 } else {
12925 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12926 }
12927
12928 dev = set->crtc->dev;
12929
12930 state = drm_atomic_state_alloc(dev);
12931 if (!state)
12932 return -ENOMEM;
12933
12934 state->acquire_ctx = dev->mode_config.acquire_ctx;
12935
12936 ret = intel_modeset_stage_output_state(dev, set, state);
12937 if (ret)
12938 goto out;
12939
12940 pipe_config = intel_modeset_compute_config(set->crtc, state);
12941 if (IS_ERR(pipe_config)) {
12942 ret = PTR_ERR(pipe_config);
12943 goto out;
12944 }
12945
12946 intel_update_pipe_size(to_intel_crtc(set->crtc));
12947
12948 primary_plane_was_visible = primary_plane_visible(set->crtc);
12949
12950 ret = intel_set_mode_with_config(set->crtc, pipe_config);
12951
12952 if (ret == 0 &&
12953 pipe_config->base.enable &&
12954 pipe_config->base.planes_changed &&
12955 !needs_modeset(&pipe_config->base)) {
12956 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12957
12958 /*
12959 * We need to make sure the primary plane is re-enabled if it
12960 * has previously been turned off.
12961 */
12962 if (ret == 0 && !primary_plane_was_visible &&
12963 primary_plane_visible(set->crtc)) {
12964 WARN_ON(!intel_crtc->active);
12965 intel_post_enable_primary(set->crtc);
12966 }
12967
12968 /*
12969 * In the fastboot case this may be our only check of the
12970 * state after boot. It would be better to only do it on
12971 * the first update, but we don't have a nice way of doing that
12972 * (and really, set_config isn't used much for high freq page
12973 * flipping, so increasing its cost here shouldn't be a big
12974 * deal).
12975 */
12976 if (i915.fastboot && ret == 0)
12977 intel_modeset_check_state(set->crtc->dev);
12978 }
12979
12980 if (ret) {
12981 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12982 set->crtc->base.id, ret);
12983 }
12984
12985 out:
12986 if (ret)
12987 drm_atomic_state_free(state);
12988 return ret;
12989 }
12990
12991 static const struct drm_crtc_funcs intel_crtc_funcs = {
12992 .gamma_set = intel_crtc_gamma_set,
12993 .set_config = intel_crtc_set_config,
12994 .destroy = intel_crtc_destroy,
12995 .page_flip = intel_crtc_page_flip,
12996 .atomic_duplicate_state = intel_crtc_duplicate_state,
12997 .atomic_destroy_state = intel_crtc_destroy_state,
12998 };
12999
13000 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13001 struct intel_shared_dpll *pll,
13002 struct intel_dpll_hw_state *hw_state)
13003 {
13004 uint32_t val;
13005
13006 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13007 return false;
13008
13009 val = I915_READ(PCH_DPLL(pll->id));
13010 hw_state->dpll = val;
13011 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13012 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13013
13014 return val & DPLL_VCO_ENABLE;
13015 }
13016
13017 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13018 struct intel_shared_dpll *pll)
13019 {
13020 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13021 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13022 }
13023
13024 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13025 struct intel_shared_dpll *pll)
13026 {
13027 /* PCH refclock must be enabled first */
13028 ibx_assert_pch_refclk_enabled(dev_priv);
13029
13030 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13031
13032 /* Wait for the clocks to stabilize. */
13033 POSTING_READ(PCH_DPLL(pll->id));
13034 udelay(150);
13035
13036 /* The pixel multiplier can only be updated once the
13037 * DPLL is enabled and the clocks are stable.
13038 *
13039 * So write it again.
13040 */
13041 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13042 POSTING_READ(PCH_DPLL(pll->id));
13043 udelay(200);
13044 }
13045
13046 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13047 struct intel_shared_dpll *pll)
13048 {
13049 struct drm_device *dev = dev_priv->dev;
13050 struct intel_crtc *crtc;
13051
13052 /* Make sure no transcoder isn't still depending on us. */
13053 for_each_intel_crtc(dev, crtc) {
13054 if (intel_crtc_to_shared_dpll(crtc) == pll)
13055 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13056 }
13057
13058 I915_WRITE(PCH_DPLL(pll->id), 0);
13059 POSTING_READ(PCH_DPLL(pll->id));
13060 udelay(200);
13061 }
13062
13063 static char *ibx_pch_dpll_names[] = {
13064 "PCH DPLL A",
13065 "PCH DPLL B",
13066 };
13067
13068 static void ibx_pch_dpll_init(struct drm_device *dev)
13069 {
13070 struct drm_i915_private *dev_priv = dev->dev_private;
13071 int i;
13072
13073 dev_priv->num_shared_dpll = 2;
13074
13075 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13076 dev_priv->shared_dplls[i].id = i;
13077 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13078 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13079 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13080 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13081 dev_priv->shared_dplls[i].get_hw_state =
13082 ibx_pch_dpll_get_hw_state;
13083 }
13084 }
13085
13086 static void intel_shared_dpll_init(struct drm_device *dev)
13087 {
13088 struct drm_i915_private *dev_priv = dev->dev_private;
13089
13090 if (HAS_DDI(dev))
13091 intel_ddi_pll_init(dev);
13092 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13093 ibx_pch_dpll_init(dev);
13094 else
13095 dev_priv->num_shared_dpll = 0;
13096
13097 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13098 }
13099
13100 /**
13101 * intel_wm_need_update - Check whether watermarks need updating
13102 * @plane: drm plane
13103 * @state: new plane state
13104 *
13105 * Check current plane state versus the new one to determine whether
13106 * watermarks need to be recalculated.
13107 *
13108 * Returns true or false.
13109 */
13110 bool intel_wm_need_update(struct drm_plane *plane,
13111 struct drm_plane_state *state)
13112 {
13113 /* Update watermarks on tiling changes. */
13114 if (!plane->state->fb || !state->fb ||
13115 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13116 plane->state->rotation != state->rotation)
13117 return true;
13118
13119 return false;
13120 }
13121
13122 /**
13123 * intel_prepare_plane_fb - Prepare fb for usage on plane
13124 * @plane: drm plane to prepare for
13125 * @fb: framebuffer to prepare for presentation
13126 *
13127 * Prepares a framebuffer for usage on a display plane. Generally this
13128 * involves pinning the underlying object and updating the frontbuffer tracking
13129 * bits. Some older platforms need special physical address handling for
13130 * cursor planes.
13131 *
13132 * Returns 0 on success, negative error code on failure.
13133 */
13134 int
13135 intel_prepare_plane_fb(struct drm_plane *plane,
13136 struct drm_framebuffer *fb,
13137 const struct drm_plane_state *new_state)
13138 {
13139 struct drm_device *dev = plane->dev;
13140 struct intel_plane *intel_plane = to_intel_plane(plane);
13141 enum pipe pipe = intel_plane->pipe;
13142 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13143 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13144 unsigned frontbuffer_bits = 0;
13145 int ret = 0;
13146
13147 if (!obj)
13148 return 0;
13149
13150 switch (plane->type) {
13151 case DRM_PLANE_TYPE_PRIMARY:
13152 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13153 break;
13154 case DRM_PLANE_TYPE_CURSOR:
13155 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13156 break;
13157 case DRM_PLANE_TYPE_OVERLAY:
13158 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13159 break;
13160 }
13161
13162 mutex_lock(&dev->struct_mutex);
13163
13164 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13165 INTEL_INFO(dev)->cursor_needs_physical) {
13166 int align = IS_I830(dev) ? 16 * 1024 : 256;
13167 ret = i915_gem_object_attach_phys(obj, align);
13168 if (ret)
13169 DRM_DEBUG_KMS("failed to attach phys object\n");
13170 } else {
13171 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13172 }
13173
13174 if (ret == 0)
13175 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13176
13177 mutex_unlock(&dev->struct_mutex);
13178
13179 return ret;
13180 }
13181
13182 /**
13183 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13184 * @plane: drm plane to clean up for
13185 * @fb: old framebuffer that was on plane
13186 *
13187 * Cleans up a framebuffer that has just been removed from a plane.
13188 */
13189 void
13190 intel_cleanup_plane_fb(struct drm_plane *plane,
13191 struct drm_framebuffer *fb,
13192 const struct drm_plane_state *old_state)
13193 {
13194 struct drm_device *dev = plane->dev;
13195 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13196
13197 if (WARN_ON(!obj))
13198 return;
13199
13200 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13201 !INTEL_INFO(dev)->cursor_needs_physical) {
13202 mutex_lock(&dev->struct_mutex);
13203 intel_unpin_fb_obj(fb, old_state);
13204 mutex_unlock(&dev->struct_mutex);
13205 }
13206 }
13207
13208 int
13209 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13210 {
13211 int max_scale;
13212 struct drm_device *dev;
13213 struct drm_i915_private *dev_priv;
13214 int crtc_clock, cdclk;
13215
13216 if (!intel_crtc || !crtc_state)
13217 return DRM_PLANE_HELPER_NO_SCALING;
13218
13219 dev = intel_crtc->base.dev;
13220 dev_priv = dev->dev_private;
13221 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13222 cdclk = dev_priv->display.get_display_clock_speed(dev);
13223
13224 if (!crtc_clock || !cdclk)
13225 return DRM_PLANE_HELPER_NO_SCALING;
13226
13227 /*
13228 * skl max scale is lower of:
13229 * close to 3 but not 3, -1 is for that purpose
13230 * or
13231 * cdclk/crtc_clock
13232 */
13233 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13234
13235 return max_scale;
13236 }
13237
13238 static int
13239 intel_check_primary_plane(struct drm_plane *plane,
13240 struct intel_plane_state *state)
13241 {
13242 struct drm_device *dev = plane->dev;
13243 struct drm_i915_private *dev_priv = dev->dev_private;
13244 struct drm_crtc *crtc = state->base.crtc;
13245 struct intel_crtc *intel_crtc;
13246 struct intel_crtc_state *crtc_state;
13247 struct drm_framebuffer *fb = state->base.fb;
13248 struct drm_rect *dest = &state->dst;
13249 struct drm_rect *src = &state->src;
13250 const struct drm_rect *clip = &state->clip;
13251 bool can_position = false;
13252 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13253 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13254 int ret;
13255
13256 crtc = crtc ? crtc : plane->crtc;
13257 intel_crtc = to_intel_crtc(crtc);
13258 crtc_state = state->base.state ?
13259 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13260
13261 if (INTEL_INFO(dev)->gen >= 9) {
13262 /* use scaler when colorkey is not required */
13263 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13264 min_scale = 1;
13265 max_scale = skl_max_scale(intel_crtc, crtc_state);
13266 }
13267 can_position = true;
13268 }
13269
13270 ret = drm_plane_helper_check_update(plane, crtc, fb,
13271 src, dest, clip,
13272 min_scale,
13273 max_scale,
13274 can_position, true,
13275 &state->visible);
13276 if (ret)
13277 return ret;
13278
13279 if (intel_crtc->active) {
13280 struct intel_plane_state *old_state =
13281 to_intel_plane_state(plane->state);
13282
13283 intel_crtc->atomic.wait_for_flips = true;
13284
13285 /*
13286 * FBC does not work on some platforms for rotated
13287 * planes, so disable it when rotation is not 0 and
13288 * update it when rotation is set back to 0.
13289 *
13290 * FIXME: This is redundant with the fbc update done in
13291 * the primary plane enable function except that that
13292 * one is done too late. We eventually need to unify
13293 * this.
13294 */
13295 if (state->visible &&
13296 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13297 dev_priv->fbc.crtc == intel_crtc &&
13298 state->base.rotation != BIT(DRM_ROTATE_0)) {
13299 intel_crtc->atomic.disable_fbc = true;
13300 }
13301
13302 if (state->visible && !old_state->visible) {
13303 /*
13304 * BDW signals flip done immediately if the plane
13305 * is disabled, even if the plane enable is already
13306 * armed to occur at the next vblank :(
13307 */
13308 if (IS_BROADWELL(dev))
13309 intel_crtc->atomic.wait_vblank = true;
13310 }
13311
13312 intel_crtc->atomic.fb_bits |=
13313 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13314
13315 intel_crtc->atomic.update_fbc = true;
13316
13317 if (intel_wm_need_update(plane, &state->base))
13318 intel_crtc->atomic.update_wm = true;
13319 }
13320
13321 if (INTEL_INFO(dev)->gen >= 9) {
13322 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13323 to_intel_plane(plane), state, 0);
13324 if (ret)
13325 return ret;
13326 }
13327
13328 return 0;
13329 }
13330
13331 static void
13332 intel_commit_primary_plane(struct drm_plane *plane,
13333 struct intel_plane_state *state)
13334 {
13335 struct drm_crtc *crtc = state->base.crtc;
13336 struct drm_framebuffer *fb = state->base.fb;
13337 struct drm_device *dev = plane->dev;
13338 struct drm_i915_private *dev_priv = dev->dev_private;
13339 struct intel_crtc *intel_crtc;
13340 struct drm_rect *src = &state->src;
13341
13342 crtc = crtc ? crtc : plane->crtc;
13343 intel_crtc = to_intel_crtc(crtc);
13344
13345 plane->fb = fb;
13346 crtc->x = src->x1 >> 16;
13347 crtc->y = src->y1 >> 16;
13348
13349 if (intel_crtc->active) {
13350 if (state->visible)
13351 /* FIXME: kill this fastboot hack */
13352 intel_update_pipe_size(intel_crtc);
13353
13354 dev_priv->display.update_primary_plane(crtc, plane->fb,
13355 crtc->x, crtc->y);
13356 }
13357 }
13358
13359 static void
13360 intel_disable_primary_plane(struct drm_plane *plane,
13361 struct drm_crtc *crtc,
13362 bool force)
13363 {
13364 struct drm_device *dev = plane->dev;
13365 struct drm_i915_private *dev_priv = dev->dev_private;
13366
13367 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13368 }
13369
13370 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13371 {
13372 struct drm_device *dev = crtc->dev;
13373 struct drm_i915_private *dev_priv = dev->dev_private;
13374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13375 struct intel_plane *intel_plane;
13376 struct drm_plane *p;
13377 unsigned fb_bits = 0;
13378
13379 /* Track fb's for any planes being disabled */
13380 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13381 intel_plane = to_intel_plane(p);
13382
13383 if (intel_crtc->atomic.disabled_planes &
13384 (1 << drm_plane_index(p))) {
13385 switch (p->type) {
13386 case DRM_PLANE_TYPE_PRIMARY:
13387 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13388 break;
13389 case DRM_PLANE_TYPE_CURSOR:
13390 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13391 break;
13392 case DRM_PLANE_TYPE_OVERLAY:
13393 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13394 break;
13395 }
13396
13397 mutex_lock(&dev->struct_mutex);
13398 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13399 mutex_unlock(&dev->struct_mutex);
13400 }
13401 }
13402
13403 if (intel_crtc->atomic.wait_for_flips)
13404 intel_crtc_wait_for_pending_flips(crtc);
13405
13406 if (intel_crtc->atomic.disable_fbc)
13407 intel_fbc_disable(dev);
13408
13409 if (intel_crtc->atomic.pre_disable_primary)
13410 intel_pre_disable_primary(crtc);
13411
13412 if (intel_crtc->atomic.update_wm)
13413 intel_update_watermarks(crtc);
13414
13415 intel_runtime_pm_get(dev_priv);
13416
13417 /* Perform vblank evasion around commit operation */
13418 if (intel_crtc->active)
13419 intel_crtc->atomic.evade =
13420 intel_pipe_update_start(intel_crtc,
13421 &intel_crtc->atomic.start_vbl_count);
13422 }
13423
13424 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13425 {
13426 struct drm_device *dev = crtc->dev;
13427 struct drm_i915_private *dev_priv = dev->dev_private;
13428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13429 struct drm_plane *p;
13430
13431 if (intel_crtc->atomic.evade)
13432 intel_pipe_update_end(intel_crtc,
13433 intel_crtc->atomic.start_vbl_count);
13434
13435 intel_runtime_pm_put(dev_priv);
13436
13437 if (intel_crtc->atomic.wait_vblank)
13438 intel_wait_for_vblank(dev, intel_crtc->pipe);
13439
13440 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13441
13442 if (intel_crtc->atomic.update_fbc) {
13443 mutex_lock(&dev->struct_mutex);
13444 intel_fbc_update(dev);
13445 mutex_unlock(&dev->struct_mutex);
13446 }
13447
13448 if (intel_crtc->atomic.post_enable_primary)
13449 intel_post_enable_primary(crtc);
13450
13451 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13452 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13453 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13454 false, false);
13455
13456 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13457 }
13458
13459 /**
13460 * intel_plane_destroy - destroy a plane
13461 * @plane: plane to destroy
13462 *
13463 * Common destruction function for all types of planes (primary, cursor,
13464 * sprite).
13465 */
13466 void intel_plane_destroy(struct drm_plane *plane)
13467 {
13468 struct intel_plane *intel_plane = to_intel_plane(plane);
13469 drm_plane_cleanup(plane);
13470 kfree(intel_plane);
13471 }
13472
13473 const struct drm_plane_funcs intel_plane_funcs = {
13474 .update_plane = drm_atomic_helper_update_plane,
13475 .disable_plane = drm_atomic_helper_disable_plane,
13476 .destroy = intel_plane_destroy,
13477 .set_property = drm_atomic_helper_plane_set_property,
13478 .atomic_get_property = intel_plane_atomic_get_property,
13479 .atomic_set_property = intel_plane_atomic_set_property,
13480 .atomic_duplicate_state = intel_plane_duplicate_state,
13481 .atomic_destroy_state = intel_plane_destroy_state,
13482
13483 };
13484
13485 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13486 int pipe)
13487 {
13488 struct intel_plane *primary;
13489 struct intel_plane_state *state;
13490 const uint32_t *intel_primary_formats;
13491 int num_formats;
13492
13493 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13494 if (primary == NULL)
13495 return NULL;
13496
13497 state = intel_create_plane_state(&primary->base);
13498 if (!state) {
13499 kfree(primary);
13500 return NULL;
13501 }
13502 primary->base.state = &state->base;
13503
13504 primary->can_scale = false;
13505 primary->max_downscale = 1;
13506 if (INTEL_INFO(dev)->gen >= 9) {
13507 primary->can_scale = true;
13508 state->scaler_id = -1;
13509 }
13510 primary->pipe = pipe;
13511 primary->plane = pipe;
13512 primary->check_plane = intel_check_primary_plane;
13513 primary->commit_plane = intel_commit_primary_plane;
13514 primary->disable_plane = intel_disable_primary_plane;
13515 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13516 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13517 primary->plane = !pipe;
13518
13519 if (INTEL_INFO(dev)->gen >= 9) {
13520 intel_primary_formats = skl_primary_formats;
13521 num_formats = ARRAY_SIZE(skl_primary_formats);
13522 } else if (INTEL_INFO(dev)->gen >= 4) {
13523 intel_primary_formats = i965_primary_formats;
13524 num_formats = ARRAY_SIZE(i965_primary_formats);
13525 } else {
13526 intel_primary_formats = i8xx_primary_formats;
13527 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13528 }
13529
13530 drm_universal_plane_init(dev, &primary->base, 0,
13531 &intel_plane_funcs,
13532 intel_primary_formats, num_formats,
13533 DRM_PLANE_TYPE_PRIMARY);
13534
13535 if (INTEL_INFO(dev)->gen >= 4)
13536 intel_create_rotation_property(dev, primary);
13537
13538 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13539
13540 return &primary->base;
13541 }
13542
13543 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13544 {
13545 if (!dev->mode_config.rotation_property) {
13546 unsigned long flags = BIT(DRM_ROTATE_0) |
13547 BIT(DRM_ROTATE_180);
13548
13549 if (INTEL_INFO(dev)->gen >= 9)
13550 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13551
13552 dev->mode_config.rotation_property =
13553 drm_mode_create_rotation_property(dev, flags);
13554 }
13555 if (dev->mode_config.rotation_property)
13556 drm_object_attach_property(&plane->base.base,
13557 dev->mode_config.rotation_property,
13558 plane->base.state->rotation);
13559 }
13560
13561 static int
13562 intel_check_cursor_plane(struct drm_plane *plane,
13563 struct intel_plane_state *state)
13564 {
13565 struct drm_crtc *crtc = state->base.crtc;
13566 struct drm_device *dev = plane->dev;
13567 struct drm_framebuffer *fb = state->base.fb;
13568 struct drm_rect *dest = &state->dst;
13569 struct drm_rect *src = &state->src;
13570 const struct drm_rect *clip = &state->clip;
13571 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13572 struct intel_crtc *intel_crtc;
13573 unsigned stride;
13574 int ret;
13575
13576 crtc = crtc ? crtc : plane->crtc;
13577 intel_crtc = to_intel_crtc(crtc);
13578
13579 ret = drm_plane_helper_check_update(plane, crtc, fb,
13580 src, dest, clip,
13581 DRM_PLANE_HELPER_NO_SCALING,
13582 DRM_PLANE_HELPER_NO_SCALING,
13583 true, true, &state->visible);
13584 if (ret)
13585 return ret;
13586
13587
13588 /* if we want to turn off the cursor ignore width and height */
13589 if (!obj)
13590 goto finish;
13591
13592 /* Check for which cursor types we support */
13593 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13594 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13595 state->base.crtc_w, state->base.crtc_h);
13596 return -EINVAL;
13597 }
13598
13599 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13600 if (obj->base.size < stride * state->base.crtc_h) {
13601 DRM_DEBUG_KMS("buffer is too small\n");
13602 return -ENOMEM;
13603 }
13604
13605 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13606 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13607 ret = -EINVAL;
13608 }
13609
13610 finish:
13611 if (intel_crtc->active) {
13612 if (plane->state->crtc_w != state->base.crtc_w)
13613 intel_crtc->atomic.update_wm = true;
13614
13615 intel_crtc->atomic.fb_bits |=
13616 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13617 }
13618
13619 return ret;
13620 }
13621
13622 static void
13623 intel_disable_cursor_plane(struct drm_plane *plane,
13624 struct drm_crtc *crtc,
13625 bool force)
13626 {
13627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13628
13629 if (!force) {
13630 plane->fb = NULL;
13631 intel_crtc->cursor_bo = NULL;
13632 intel_crtc->cursor_addr = 0;
13633 }
13634
13635 intel_crtc_update_cursor(crtc, false);
13636 }
13637
13638 static void
13639 intel_commit_cursor_plane(struct drm_plane *plane,
13640 struct intel_plane_state *state)
13641 {
13642 struct drm_crtc *crtc = state->base.crtc;
13643 struct drm_device *dev = plane->dev;
13644 struct intel_crtc *intel_crtc;
13645 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13646 uint32_t addr;
13647
13648 crtc = crtc ? crtc : plane->crtc;
13649 intel_crtc = to_intel_crtc(crtc);
13650
13651 plane->fb = state->base.fb;
13652 crtc->cursor_x = state->base.crtc_x;
13653 crtc->cursor_y = state->base.crtc_y;
13654
13655 if (intel_crtc->cursor_bo == obj)
13656 goto update;
13657
13658 if (!obj)
13659 addr = 0;
13660 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13661 addr = i915_gem_obj_ggtt_offset(obj);
13662 else
13663 addr = obj->phys_handle->busaddr;
13664
13665 intel_crtc->cursor_addr = addr;
13666 intel_crtc->cursor_bo = obj;
13667 update:
13668
13669 if (intel_crtc->active)
13670 intel_crtc_update_cursor(crtc, state->visible);
13671 }
13672
13673 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13674 int pipe)
13675 {
13676 struct intel_plane *cursor;
13677 struct intel_plane_state *state;
13678
13679 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13680 if (cursor == NULL)
13681 return NULL;
13682
13683 state = intel_create_plane_state(&cursor->base);
13684 if (!state) {
13685 kfree(cursor);
13686 return NULL;
13687 }
13688 cursor->base.state = &state->base;
13689
13690 cursor->can_scale = false;
13691 cursor->max_downscale = 1;
13692 cursor->pipe = pipe;
13693 cursor->plane = pipe;
13694 cursor->check_plane = intel_check_cursor_plane;
13695 cursor->commit_plane = intel_commit_cursor_plane;
13696 cursor->disable_plane = intel_disable_cursor_plane;
13697
13698 drm_universal_plane_init(dev, &cursor->base, 0,
13699 &intel_plane_funcs,
13700 intel_cursor_formats,
13701 ARRAY_SIZE(intel_cursor_formats),
13702 DRM_PLANE_TYPE_CURSOR);
13703
13704 if (INTEL_INFO(dev)->gen >= 4) {
13705 if (!dev->mode_config.rotation_property)
13706 dev->mode_config.rotation_property =
13707 drm_mode_create_rotation_property(dev,
13708 BIT(DRM_ROTATE_0) |
13709 BIT(DRM_ROTATE_180));
13710 if (dev->mode_config.rotation_property)
13711 drm_object_attach_property(&cursor->base.base,
13712 dev->mode_config.rotation_property,
13713 state->base.rotation);
13714 }
13715
13716 if (INTEL_INFO(dev)->gen >=9)
13717 state->scaler_id = -1;
13718
13719 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13720
13721 return &cursor->base;
13722 }
13723
13724 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13725 struct intel_crtc_state *crtc_state)
13726 {
13727 int i;
13728 struct intel_scaler *intel_scaler;
13729 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13730
13731 for (i = 0; i < intel_crtc->num_scalers; i++) {
13732 intel_scaler = &scaler_state->scalers[i];
13733 intel_scaler->in_use = 0;
13734 intel_scaler->id = i;
13735
13736 intel_scaler->mode = PS_SCALER_MODE_DYN;
13737 }
13738
13739 scaler_state->scaler_id = -1;
13740 }
13741
13742 static void intel_crtc_init(struct drm_device *dev, int pipe)
13743 {
13744 struct drm_i915_private *dev_priv = dev->dev_private;
13745 struct intel_crtc *intel_crtc;
13746 struct intel_crtc_state *crtc_state = NULL;
13747 struct drm_plane *primary = NULL;
13748 struct drm_plane *cursor = NULL;
13749 int i, ret;
13750
13751 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13752 if (intel_crtc == NULL)
13753 return;
13754
13755 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13756 if (!crtc_state)
13757 goto fail;
13758 intel_crtc->config = crtc_state;
13759 intel_crtc->base.state = &crtc_state->base;
13760 crtc_state->base.crtc = &intel_crtc->base;
13761
13762 /* initialize shared scalers */
13763 if (INTEL_INFO(dev)->gen >= 9) {
13764 if (pipe == PIPE_C)
13765 intel_crtc->num_scalers = 1;
13766 else
13767 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13768
13769 skl_init_scalers(dev, intel_crtc, crtc_state);
13770 }
13771
13772 primary = intel_primary_plane_create(dev, pipe);
13773 if (!primary)
13774 goto fail;
13775
13776 cursor = intel_cursor_plane_create(dev, pipe);
13777 if (!cursor)
13778 goto fail;
13779
13780 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13781 cursor, &intel_crtc_funcs);
13782 if (ret)
13783 goto fail;
13784
13785 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13786 for (i = 0; i < 256; i++) {
13787 intel_crtc->lut_r[i] = i;
13788 intel_crtc->lut_g[i] = i;
13789 intel_crtc->lut_b[i] = i;
13790 }
13791
13792 /*
13793 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13794 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13795 */
13796 intel_crtc->pipe = pipe;
13797 intel_crtc->plane = pipe;
13798 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13799 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13800 intel_crtc->plane = !pipe;
13801 }
13802
13803 intel_crtc->cursor_base = ~0;
13804 intel_crtc->cursor_cntl = ~0;
13805 intel_crtc->cursor_size = ~0;
13806
13807 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13808 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13809 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13810 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13811
13812 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13813
13814 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13815 return;
13816
13817 fail:
13818 if (primary)
13819 drm_plane_cleanup(primary);
13820 if (cursor)
13821 drm_plane_cleanup(cursor);
13822 kfree(crtc_state);
13823 kfree(intel_crtc);
13824 }
13825
13826 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13827 {
13828 struct drm_encoder *encoder = connector->base.encoder;
13829 struct drm_device *dev = connector->base.dev;
13830
13831 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13832
13833 if (!encoder || WARN_ON(!encoder->crtc))
13834 return INVALID_PIPE;
13835
13836 return to_intel_crtc(encoder->crtc)->pipe;
13837 }
13838
13839 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13840 struct drm_file *file)
13841 {
13842 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13843 struct drm_crtc *drmmode_crtc;
13844 struct intel_crtc *crtc;
13845
13846 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13847
13848 if (!drmmode_crtc) {
13849 DRM_ERROR("no such CRTC id\n");
13850 return -ENOENT;
13851 }
13852
13853 crtc = to_intel_crtc(drmmode_crtc);
13854 pipe_from_crtc_id->pipe = crtc->pipe;
13855
13856 return 0;
13857 }
13858
13859 static int intel_encoder_clones(struct intel_encoder *encoder)
13860 {
13861 struct drm_device *dev = encoder->base.dev;
13862 struct intel_encoder *source_encoder;
13863 int index_mask = 0;
13864 int entry = 0;
13865
13866 for_each_intel_encoder(dev, source_encoder) {
13867 if (encoders_cloneable(encoder, source_encoder))
13868 index_mask |= (1 << entry);
13869
13870 entry++;
13871 }
13872
13873 return index_mask;
13874 }
13875
13876 static bool has_edp_a(struct drm_device *dev)
13877 {
13878 struct drm_i915_private *dev_priv = dev->dev_private;
13879
13880 if (!IS_MOBILE(dev))
13881 return false;
13882
13883 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13884 return false;
13885
13886 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13887 return false;
13888
13889 return true;
13890 }
13891
13892 static bool intel_crt_present(struct drm_device *dev)
13893 {
13894 struct drm_i915_private *dev_priv = dev->dev_private;
13895
13896 if (INTEL_INFO(dev)->gen >= 9)
13897 return false;
13898
13899 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13900 return false;
13901
13902 if (IS_CHERRYVIEW(dev))
13903 return false;
13904
13905 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13906 return false;
13907
13908 return true;
13909 }
13910
13911 static void intel_setup_outputs(struct drm_device *dev)
13912 {
13913 struct drm_i915_private *dev_priv = dev->dev_private;
13914 struct intel_encoder *encoder;
13915 bool dpd_is_edp = false;
13916
13917 intel_lvds_init(dev);
13918
13919 if (intel_crt_present(dev))
13920 intel_crt_init(dev);
13921
13922 if (IS_BROXTON(dev)) {
13923 /*
13924 * FIXME: Broxton doesn't support port detection via the
13925 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13926 * detect the ports.
13927 */
13928 intel_ddi_init(dev, PORT_A);
13929 intel_ddi_init(dev, PORT_B);
13930 intel_ddi_init(dev, PORT_C);
13931 } else if (HAS_DDI(dev)) {
13932 int found;
13933
13934 /*
13935 * Haswell uses DDI functions to detect digital outputs.
13936 * On SKL pre-D0 the strap isn't connected, so we assume
13937 * it's there.
13938 */
13939 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13940 /* WaIgnoreDDIAStrap: skl */
13941 if (found ||
13942 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13943 intel_ddi_init(dev, PORT_A);
13944
13945 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13946 * register */
13947 found = I915_READ(SFUSE_STRAP);
13948
13949 if (found & SFUSE_STRAP_DDIB_DETECTED)
13950 intel_ddi_init(dev, PORT_B);
13951 if (found & SFUSE_STRAP_DDIC_DETECTED)
13952 intel_ddi_init(dev, PORT_C);
13953 if (found & SFUSE_STRAP_DDID_DETECTED)
13954 intel_ddi_init(dev, PORT_D);
13955 } else if (HAS_PCH_SPLIT(dev)) {
13956 int found;
13957 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13958
13959 if (has_edp_a(dev))
13960 intel_dp_init(dev, DP_A, PORT_A);
13961
13962 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13963 /* PCH SDVOB multiplex with HDMIB */
13964 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13965 if (!found)
13966 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13967 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13968 intel_dp_init(dev, PCH_DP_B, PORT_B);
13969 }
13970
13971 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13972 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13973
13974 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13975 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13976
13977 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13978 intel_dp_init(dev, PCH_DP_C, PORT_C);
13979
13980 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13981 intel_dp_init(dev, PCH_DP_D, PORT_D);
13982 } else if (IS_VALLEYVIEW(dev)) {
13983 /*
13984 * The DP_DETECTED bit is the latched state of the DDC
13985 * SDA pin at boot. However since eDP doesn't require DDC
13986 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13987 * eDP ports may have been muxed to an alternate function.
13988 * Thus we can't rely on the DP_DETECTED bit alone to detect
13989 * eDP ports. Consult the VBT as well as DP_DETECTED to
13990 * detect eDP ports.
13991 */
13992 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13993 !intel_dp_is_edp(dev, PORT_B))
13994 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13995 PORT_B);
13996 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13997 intel_dp_is_edp(dev, PORT_B))
13998 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13999
14000 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14001 !intel_dp_is_edp(dev, PORT_C))
14002 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14003 PORT_C);
14004 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14005 intel_dp_is_edp(dev, PORT_C))
14006 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14007
14008 if (IS_CHERRYVIEW(dev)) {
14009 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14010 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14011 PORT_D);
14012 /* eDP not supported on port D, so don't check VBT */
14013 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14014 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14015 }
14016
14017 intel_dsi_init(dev);
14018 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14019 bool found = false;
14020
14021 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14022 DRM_DEBUG_KMS("probing SDVOB\n");
14023 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14024 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14025 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14026 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14027 }
14028
14029 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14030 intel_dp_init(dev, DP_B, PORT_B);
14031 }
14032
14033 /* Before G4X SDVOC doesn't have its own detect register */
14034
14035 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14036 DRM_DEBUG_KMS("probing SDVOC\n");
14037 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14038 }
14039
14040 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14041
14042 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14043 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14044 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14045 }
14046 if (SUPPORTS_INTEGRATED_DP(dev))
14047 intel_dp_init(dev, DP_C, PORT_C);
14048 }
14049
14050 if (SUPPORTS_INTEGRATED_DP(dev) &&
14051 (I915_READ(DP_D) & DP_DETECTED))
14052 intel_dp_init(dev, DP_D, PORT_D);
14053 } else if (IS_GEN2(dev))
14054 intel_dvo_init(dev);
14055
14056 if (SUPPORTS_TV(dev))
14057 intel_tv_init(dev);
14058
14059 intel_psr_init(dev);
14060
14061 for_each_intel_encoder(dev, encoder) {
14062 encoder->base.possible_crtcs = encoder->crtc_mask;
14063 encoder->base.possible_clones =
14064 intel_encoder_clones(encoder);
14065 }
14066
14067 intel_init_pch_refclk(dev);
14068
14069 drm_helper_move_panel_connectors_to_head(dev);
14070 }
14071
14072 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14073 {
14074 struct drm_device *dev = fb->dev;
14075 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14076
14077 drm_framebuffer_cleanup(fb);
14078 mutex_lock(&dev->struct_mutex);
14079 WARN_ON(!intel_fb->obj->framebuffer_references--);
14080 drm_gem_object_unreference(&intel_fb->obj->base);
14081 mutex_unlock(&dev->struct_mutex);
14082 kfree(intel_fb);
14083 }
14084
14085 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14086 struct drm_file *file,
14087 unsigned int *handle)
14088 {
14089 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14090 struct drm_i915_gem_object *obj = intel_fb->obj;
14091
14092 return drm_gem_handle_create(file, &obj->base, handle);
14093 }
14094
14095 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14096 .destroy = intel_user_framebuffer_destroy,
14097 .create_handle = intel_user_framebuffer_create_handle,
14098 };
14099
14100 static
14101 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14102 uint32_t pixel_format)
14103 {
14104 u32 gen = INTEL_INFO(dev)->gen;
14105
14106 if (gen >= 9) {
14107 /* "The stride in bytes must not exceed the of the size of 8K
14108 * pixels and 32K bytes."
14109 */
14110 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14111 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14112 return 32*1024;
14113 } else if (gen >= 4) {
14114 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14115 return 16*1024;
14116 else
14117 return 32*1024;
14118 } else if (gen >= 3) {
14119 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14120 return 8*1024;
14121 else
14122 return 16*1024;
14123 } else {
14124 /* XXX DSPC is limited to 4k tiled */
14125 return 8*1024;
14126 }
14127 }
14128
14129 static int intel_framebuffer_init(struct drm_device *dev,
14130 struct intel_framebuffer *intel_fb,
14131 struct drm_mode_fb_cmd2 *mode_cmd,
14132 struct drm_i915_gem_object *obj)
14133 {
14134 unsigned int aligned_height;
14135 int ret;
14136 u32 pitch_limit, stride_alignment;
14137
14138 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14139
14140 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14141 /* Enforce that fb modifier and tiling mode match, but only for
14142 * X-tiled. This is needed for FBC. */
14143 if (!!(obj->tiling_mode == I915_TILING_X) !=
14144 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14145 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14146 return -EINVAL;
14147 }
14148 } else {
14149 if (obj->tiling_mode == I915_TILING_X)
14150 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14151 else if (obj->tiling_mode == I915_TILING_Y) {
14152 DRM_DEBUG("No Y tiling for legacy addfb\n");
14153 return -EINVAL;
14154 }
14155 }
14156
14157 /* Passed in modifier sanity checking. */
14158 switch (mode_cmd->modifier[0]) {
14159 case I915_FORMAT_MOD_Y_TILED:
14160 case I915_FORMAT_MOD_Yf_TILED:
14161 if (INTEL_INFO(dev)->gen < 9) {
14162 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14163 mode_cmd->modifier[0]);
14164 return -EINVAL;
14165 }
14166 case DRM_FORMAT_MOD_NONE:
14167 case I915_FORMAT_MOD_X_TILED:
14168 break;
14169 default:
14170 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14171 mode_cmd->modifier[0]);
14172 return -EINVAL;
14173 }
14174
14175 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14176 mode_cmd->pixel_format);
14177 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14178 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14179 mode_cmd->pitches[0], stride_alignment);
14180 return -EINVAL;
14181 }
14182
14183 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14184 mode_cmd->pixel_format);
14185 if (mode_cmd->pitches[0] > pitch_limit) {
14186 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14187 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14188 "tiled" : "linear",
14189 mode_cmd->pitches[0], pitch_limit);
14190 return -EINVAL;
14191 }
14192
14193 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14194 mode_cmd->pitches[0] != obj->stride) {
14195 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14196 mode_cmd->pitches[0], obj->stride);
14197 return -EINVAL;
14198 }
14199
14200 /* Reject formats not supported by any plane early. */
14201 switch (mode_cmd->pixel_format) {
14202 case DRM_FORMAT_C8:
14203 case DRM_FORMAT_RGB565:
14204 case DRM_FORMAT_XRGB8888:
14205 case DRM_FORMAT_ARGB8888:
14206 break;
14207 case DRM_FORMAT_XRGB1555:
14208 if (INTEL_INFO(dev)->gen > 3) {
14209 DRM_DEBUG("unsupported pixel format: %s\n",
14210 drm_get_format_name(mode_cmd->pixel_format));
14211 return -EINVAL;
14212 }
14213 break;
14214 case DRM_FORMAT_ABGR8888:
14215 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14216 DRM_DEBUG("unsupported pixel format: %s\n",
14217 drm_get_format_name(mode_cmd->pixel_format));
14218 return -EINVAL;
14219 }
14220 break;
14221 case DRM_FORMAT_XBGR8888:
14222 case DRM_FORMAT_XRGB2101010:
14223 case DRM_FORMAT_XBGR2101010:
14224 if (INTEL_INFO(dev)->gen < 4) {
14225 DRM_DEBUG("unsupported pixel format: %s\n",
14226 drm_get_format_name(mode_cmd->pixel_format));
14227 return -EINVAL;
14228 }
14229 break;
14230 case DRM_FORMAT_ABGR2101010:
14231 if (!IS_VALLEYVIEW(dev)) {
14232 DRM_DEBUG("unsupported pixel format: %s\n",
14233 drm_get_format_name(mode_cmd->pixel_format));
14234 return -EINVAL;
14235 }
14236 break;
14237 case DRM_FORMAT_YUYV:
14238 case DRM_FORMAT_UYVY:
14239 case DRM_FORMAT_YVYU:
14240 case DRM_FORMAT_VYUY:
14241 if (INTEL_INFO(dev)->gen < 5) {
14242 DRM_DEBUG("unsupported pixel format: %s\n",
14243 drm_get_format_name(mode_cmd->pixel_format));
14244 return -EINVAL;
14245 }
14246 break;
14247 default:
14248 DRM_DEBUG("unsupported pixel format: %s\n",
14249 drm_get_format_name(mode_cmd->pixel_format));
14250 return -EINVAL;
14251 }
14252
14253 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14254 if (mode_cmd->offsets[0] != 0)
14255 return -EINVAL;
14256
14257 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14258 mode_cmd->pixel_format,
14259 mode_cmd->modifier[0]);
14260 /* FIXME drm helper for size checks (especially planar formats)? */
14261 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14262 return -EINVAL;
14263
14264 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14265 intel_fb->obj = obj;
14266 intel_fb->obj->framebuffer_references++;
14267
14268 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14269 if (ret) {
14270 DRM_ERROR("framebuffer init failed %d\n", ret);
14271 return ret;
14272 }
14273
14274 return 0;
14275 }
14276
14277 static struct drm_framebuffer *
14278 intel_user_framebuffer_create(struct drm_device *dev,
14279 struct drm_file *filp,
14280 struct drm_mode_fb_cmd2 *mode_cmd)
14281 {
14282 struct drm_i915_gem_object *obj;
14283
14284 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14285 mode_cmd->handles[0]));
14286 if (&obj->base == NULL)
14287 return ERR_PTR(-ENOENT);
14288
14289 return intel_framebuffer_create(dev, mode_cmd, obj);
14290 }
14291
14292 #ifndef CONFIG_DRM_I915_FBDEV
14293 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14294 {
14295 }
14296 #endif
14297
14298 static const struct drm_mode_config_funcs intel_mode_funcs = {
14299 .fb_create = intel_user_framebuffer_create,
14300 .output_poll_changed = intel_fbdev_output_poll_changed,
14301 .atomic_check = intel_atomic_check,
14302 .atomic_commit = intel_atomic_commit,
14303 };
14304
14305 /* Set up chip specific display functions */
14306 static void intel_init_display(struct drm_device *dev)
14307 {
14308 struct drm_i915_private *dev_priv = dev->dev_private;
14309
14310 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14311 dev_priv->display.find_dpll = g4x_find_best_dpll;
14312 else if (IS_CHERRYVIEW(dev))
14313 dev_priv->display.find_dpll = chv_find_best_dpll;
14314 else if (IS_VALLEYVIEW(dev))
14315 dev_priv->display.find_dpll = vlv_find_best_dpll;
14316 else if (IS_PINEVIEW(dev))
14317 dev_priv->display.find_dpll = pnv_find_best_dpll;
14318 else
14319 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14320
14321 if (INTEL_INFO(dev)->gen >= 9) {
14322 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14323 dev_priv->display.get_initial_plane_config =
14324 skylake_get_initial_plane_config;
14325 dev_priv->display.crtc_compute_clock =
14326 haswell_crtc_compute_clock;
14327 dev_priv->display.crtc_enable = haswell_crtc_enable;
14328 dev_priv->display.crtc_disable = haswell_crtc_disable;
14329 dev_priv->display.off = ironlake_crtc_off;
14330 dev_priv->display.update_primary_plane =
14331 skylake_update_primary_plane;
14332 } else if (HAS_DDI(dev)) {
14333 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14334 dev_priv->display.get_initial_plane_config =
14335 ironlake_get_initial_plane_config;
14336 dev_priv->display.crtc_compute_clock =
14337 haswell_crtc_compute_clock;
14338 dev_priv->display.crtc_enable = haswell_crtc_enable;
14339 dev_priv->display.crtc_disable = haswell_crtc_disable;
14340 dev_priv->display.off = ironlake_crtc_off;
14341 dev_priv->display.update_primary_plane =
14342 ironlake_update_primary_plane;
14343 } else if (HAS_PCH_SPLIT(dev)) {
14344 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14345 dev_priv->display.get_initial_plane_config =
14346 ironlake_get_initial_plane_config;
14347 dev_priv->display.crtc_compute_clock =
14348 ironlake_crtc_compute_clock;
14349 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14350 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14351 dev_priv->display.off = ironlake_crtc_off;
14352 dev_priv->display.update_primary_plane =
14353 ironlake_update_primary_plane;
14354 } else if (IS_VALLEYVIEW(dev)) {
14355 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14356 dev_priv->display.get_initial_plane_config =
14357 i9xx_get_initial_plane_config;
14358 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14359 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14360 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14361 dev_priv->display.off = i9xx_crtc_off;
14362 dev_priv->display.update_primary_plane =
14363 i9xx_update_primary_plane;
14364 } else {
14365 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14366 dev_priv->display.get_initial_plane_config =
14367 i9xx_get_initial_plane_config;
14368 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14369 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14370 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14371 dev_priv->display.off = i9xx_crtc_off;
14372 dev_priv->display.update_primary_plane =
14373 i9xx_update_primary_plane;
14374 }
14375
14376 /* Returns the core display clock speed */
14377 if (IS_SKYLAKE(dev))
14378 dev_priv->display.get_display_clock_speed =
14379 skylake_get_display_clock_speed;
14380 else if (IS_BROADWELL(dev))
14381 dev_priv->display.get_display_clock_speed =
14382 broadwell_get_display_clock_speed;
14383 else if (IS_HASWELL(dev))
14384 dev_priv->display.get_display_clock_speed =
14385 haswell_get_display_clock_speed;
14386 else if (IS_VALLEYVIEW(dev))
14387 dev_priv->display.get_display_clock_speed =
14388 valleyview_get_display_clock_speed;
14389 else if (IS_GEN5(dev))
14390 dev_priv->display.get_display_clock_speed =
14391 ilk_get_display_clock_speed;
14392 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14393 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14394 dev_priv->display.get_display_clock_speed =
14395 i945_get_display_clock_speed;
14396 else if (IS_I915G(dev))
14397 dev_priv->display.get_display_clock_speed =
14398 i915_get_display_clock_speed;
14399 else if (IS_I945GM(dev) || IS_845G(dev))
14400 dev_priv->display.get_display_clock_speed =
14401 i9xx_misc_get_display_clock_speed;
14402 else if (IS_PINEVIEW(dev))
14403 dev_priv->display.get_display_clock_speed =
14404 pnv_get_display_clock_speed;
14405 else if (IS_I915GM(dev))
14406 dev_priv->display.get_display_clock_speed =
14407 i915gm_get_display_clock_speed;
14408 else if (IS_I865G(dev))
14409 dev_priv->display.get_display_clock_speed =
14410 i865_get_display_clock_speed;
14411 else if (IS_I85X(dev))
14412 dev_priv->display.get_display_clock_speed =
14413 i855_get_display_clock_speed;
14414 else /* 852, 830 */
14415 dev_priv->display.get_display_clock_speed =
14416 i830_get_display_clock_speed;
14417
14418 if (IS_GEN5(dev)) {
14419 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14420 } else if (IS_GEN6(dev)) {
14421 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14422 } else if (IS_IVYBRIDGE(dev)) {
14423 /* FIXME: detect B0+ stepping and use auto training */
14424 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14425 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14426 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14427 } else if (IS_VALLEYVIEW(dev)) {
14428 dev_priv->display.modeset_global_resources =
14429 valleyview_modeset_global_resources;
14430 } else if (IS_BROXTON(dev)) {
14431 dev_priv->display.modeset_global_resources =
14432 broxton_modeset_global_resources;
14433 }
14434
14435 switch (INTEL_INFO(dev)->gen) {
14436 case 2:
14437 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14438 break;
14439
14440 case 3:
14441 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14442 break;
14443
14444 case 4:
14445 case 5:
14446 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14447 break;
14448
14449 case 6:
14450 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14451 break;
14452 case 7:
14453 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14454 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14455 break;
14456 case 9:
14457 /* Drop through - unsupported since execlist only. */
14458 default:
14459 /* Default just returns -ENODEV to indicate unsupported */
14460 dev_priv->display.queue_flip = intel_default_queue_flip;
14461 }
14462
14463 intel_panel_init_backlight_funcs(dev);
14464
14465 mutex_init(&dev_priv->pps_mutex);
14466 }
14467
14468 /*
14469 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14470 * resume, or other times. This quirk makes sure that's the case for
14471 * affected systems.
14472 */
14473 static void quirk_pipea_force(struct drm_device *dev)
14474 {
14475 struct drm_i915_private *dev_priv = dev->dev_private;
14476
14477 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14478 DRM_INFO("applying pipe a force quirk\n");
14479 }
14480
14481 static void quirk_pipeb_force(struct drm_device *dev)
14482 {
14483 struct drm_i915_private *dev_priv = dev->dev_private;
14484
14485 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14486 DRM_INFO("applying pipe b force quirk\n");
14487 }
14488
14489 /*
14490 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14491 */
14492 static void quirk_ssc_force_disable(struct drm_device *dev)
14493 {
14494 struct drm_i915_private *dev_priv = dev->dev_private;
14495 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14496 DRM_INFO("applying lvds SSC disable quirk\n");
14497 }
14498
14499 /*
14500 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14501 * brightness value
14502 */
14503 static void quirk_invert_brightness(struct drm_device *dev)
14504 {
14505 struct drm_i915_private *dev_priv = dev->dev_private;
14506 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14507 DRM_INFO("applying inverted panel brightness quirk\n");
14508 }
14509
14510 /* Some VBT's incorrectly indicate no backlight is present */
14511 static void quirk_backlight_present(struct drm_device *dev)
14512 {
14513 struct drm_i915_private *dev_priv = dev->dev_private;
14514 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14515 DRM_INFO("applying backlight present quirk\n");
14516 }
14517
14518 struct intel_quirk {
14519 int device;
14520 int subsystem_vendor;
14521 int subsystem_device;
14522 void (*hook)(struct drm_device *dev);
14523 };
14524
14525 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14526 struct intel_dmi_quirk {
14527 void (*hook)(struct drm_device *dev);
14528 const struct dmi_system_id (*dmi_id_list)[];
14529 };
14530
14531 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14532 {
14533 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14534 return 1;
14535 }
14536
14537 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14538 {
14539 .dmi_id_list = &(const struct dmi_system_id[]) {
14540 {
14541 .callback = intel_dmi_reverse_brightness,
14542 .ident = "NCR Corporation",
14543 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14544 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14545 },
14546 },
14547 { } /* terminating entry */
14548 },
14549 .hook = quirk_invert_brightness,
14550 },
14551 };
14552
14553 static struct intel_quirk intel_quirks[] = {
14554 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14555 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14556
14557 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14558 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14559
14560 /* 830 needs to leave pipe A & dpll A up */
14561 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14562
14563 /* 830 needs to leave pipe B & dpll B up */
14564 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14565
14566 /* Lenovo U160 cannot use SSC on LVDS */
14567 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14568
14569 /* Sony Vaio Y cannot use SSC on LVDS */
14570 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14571
14572 /* Acer Aspire 5734Z must invert backlight brightness */
14573 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14574
14575 /* Acer/eMachines G725 */
14576 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14577
14578 /* Acer/eMachines e725 */
14579 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14580
14581 /* Acer/Packard Bell NCL20 */
14582 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14583
14584 /* Acer Aspire 4736Z */
14585 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14586
14587 /* Acer Aspire 5336 */
14588 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14589
14590 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14591 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14592
14593 /* Acer C720 Chromebook (Core i3 4005U) */
14594 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14595
14596 /* Apple Macbook 2,1 (Core 2 T7400) */
14597 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14598
14599 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14600 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14601
14602 /* HP Chromebook 14 (Celeron 2955U) */
14603 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14604
14605 /* Dell Chromebook 11 */
14606 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14607 };
14608
14609 static void intel_init_quirks(struct drm_device *dev)
14610 {
14611 struct pci_dev *d = dev->pdev;
14612 int i;
14613
14614 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14615 struct intel_quirk *q = &intel_quirks[i];
14616
14617 if (d->device == q->device &&
14618 (d->subsystem_vendor == q->subsystem_vendor ||
14619 q->subsystem_vendor == PCI_ANY_ID) &&
14620 (d->subsystem_device == q->subsystem_device ||
14621 q->subsystem_device == PCI_ANY_ID))
14622 q->hook(dev);
14623 }
14624 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14625 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14626 intel_dmi_quirks[i].hook(dev);
14627 }
14628 }
14629
14630 /* Disable the VGA plane that we never use */
14631 static void i915_disable_vga(struct drm_device *dev)
14632 {
14633 struct drm_i915_private *dev_priv = dev->dev_private;
14634 u8 sr1;
14635 u32 vga_reg = i915_vgacntrl_reg(dev);
14636
14637 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14638 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14639 outb(SR01, VGA_SR_INDEX);
14640 sr1 = inb(VGA_SR_DATA);
14641 outb(sr1 | 1<<5, VGA_SR_DATA);
14642 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14643 udelay(300);
14644
14645 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14646 POSTING_READ(vga_reg);
14647 }
14648
14649 void intel_modeset_init_hw(struct drm_device *dev)
14650 {
14651 intel_prepare_ddi(dev);
14652
14653 if (IS_VALLEYVIEW(dev))
14654 vlv_update_cdclk(dev);
14655
14656 intel_init_clock_gating(dev);
14657
14658 intel_enable_gt_powersave(dev);
14659 }
14660
14661 void intel_modeset_init(struct drm_device *dev)
14662 {
14663 struct drm_i915_private *dev_priv = dev->dev_private;
14664 int sprite, ret;
14665 enum pipe pipe;
14666 struct intel_crtc *crtc;
14667
14668 drm_mode_config_init(dev);
14669
14670 dev->mode_config.min_width = 0;
14671 dev->mode_config.min_height = 0;
14672
14673 dev->mode_config.preferred_depth = 24;
14674 dev->mode_config.prefer_shadow = 1;
14675
14676 dev->mode_config.allow_fb_modifiers = true;
14677
14678 dev->mode_config.funcs = &intel_mode_funcs;
14679
14680 intel_init_quirks(dev);
14681
14682 intel_init_pm(dev);
14683
14684 if (INTEL_INFO(dev)->num_pipes == 0)
14685 return;
14686
14687 intel_init_display(dev);
14688 intel_init_audio(dev);
14689
14690 if (IS_GEN2(dev)) {
14691 dev->mode_config.max_width = 2048;
14692 dev->mode_config.max_height = 2048;
14693 } else if (IS_GEN3(dev)) {
14694 dev->mode_config.max_width = 4096;
14695 dev->mode_config.max_height = 4096;
14696 } else {
14697 dev->mode_config.max_width = 8192;
14698 dev->mode_config.max_height = 8192;
14699 }
14700
14701 if (IS_845G(dev) || IS_I865G(dev)) {
14702 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14703 dev->mode_config.cursor_height = 1023;
14704 } else if (IS_GEN2(dev)) {
14705 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14706 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14707 } else {
14708 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14709 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14710 }
14711
14712 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14713
14714 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14715 INTEL_INFO(dev)->num_pipes,
14716 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14717
14718 for_each_pipe(dev_priv, pipe) {
14719 intel_crtc_init(dev, pipe);
14720 for_each_sprite(dev_priv, pipe, sprite) {
14721 ret = intel_plane_init(dev, pipe, sprite);
14722 if (ret)
14723 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14724 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14725 }
14726 }
14727
14728 intel_init_dpio(dev);
14729
14730 intel_shared_dpll_init(dev);
14731
14732 /* Just disable it once at startup */
14733 i915_disable_vga(dev);
14734 intel_setup_outputs(dev);
14735
14736 /* Just in case the BIOS is doing something questionable. */
14737 intel_fbc_disable(dev);
14738
14739 drm_modeset_lock_all(dev);
14740 intel_modeset_setup_hw_state(dev, false);
14741 drm_modeset_unlock_all(dev);
14742
14743 for_each_intel_crtc(dev, crtc) {
14744 if (!crtc->active)
14745 continue;
14746
14747 /*
14748 * Note that reserving the BIOS fb up front prevents us
14749 * from stuffing other stolen allocations like the ring
14750 * on top. This prevents some ugliness at boot time, and
14751 * can even allow for smooth boot transitions if the BIOS
14752 * fb is large enough for the active pipe configuration.
14753 */
14754 if (dev_priv->display.get_initial_plane_config) {
14755 dev_priv->display.get_initial_plane_config(crtc,
14756 &crtc->plane_config);
14757 /*
14758 * If the fb is shared between multiple heads, we'll
14759 * just get the first one.
14760 */
14761 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14762 }
14763 }
14764 }
14765
14766 static void intel_enable_pipe_a(struct drm_device *dev)
14767 {
14768 struct intel_connector *connector;
14769 struct drm_connector *crt = NULL;
14770 struct intel_load_detect_pipe load_detect_temp;
14771 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14772
14773 /* We can't just switch on the pipe A, we need to set things up with a
14774 * proper mode and output configuration. As a gross hack, enable pipe A
14775 * by enabling the load detect pipe once. */
14776 for_each_intel_connector(dev, connector) {
14777 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14778 crt = &connector->base;
14779 break;
14780 }
14781 }
14782
14783 if (!crt)
14784 return;
14785
14786 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14787 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14788 }
14789
14790 static bool
14791 intel_check_plane_mapping(struct intel_crtc *crtc)
14792 {
14793 struct drm_device *dev = crtc->base.dev;
14794 struct drm_i915_private *dev_priv = dev->dev_private;
14795 u32 reg, val;
14796
14797 if (INTEL_INFO(dev)->num_pipes == 1)
14798 return true;
14799
14800 reg = DSPCNTR(!crtc->plane);
14801 val = I915_READ(reg);
14802
14803 if ((val & DISPLAY_PLANE_ENABLE) &&
14804 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14805 return false;
14806
14807 return true;
14808 }
14809
14810 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14811 {
14812 struct drm_device *dev = crtc->base.dev;
14813 struct drm_i915_private *dev_priv = dev->dev_private;
14814 u32 reg;
14815
14816 /* Clear any frame start delays used for debugging left by the BIOS */
14817 reg = PIPECONF(crtc->config->cpu_transcoder);
14818 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14819
14820 /* restore vblank interrupts to correct state */
14821 drm_crtc_vblank_reset(&crtc->base);
14822 if (crtc->active) {
14823 update_scanline_offset(crtc);
14824 drm_crtc_vblank_on(&crtc->base);
14825 }
14826
14827 /* We need to sanitize the plane -> pipe mapping first because this will
14828 * disable the crtc (and hence change the state) if it is wrong. Note
14829 * that gen4+ has a fixed plane -> pipe mapping. */
14830 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14831 struct intel_connector *connector;
14832 bool plane;
14833
14834 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14835 crtc->base.base.id);
14836
14837 /* Pipe has the wrong plane attached and the plane is active.
14838 * Temporarily change the plane mapping and disable everything
14839 * ... */
14840 plane = crtc->plane;
14841 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14842 crtc->plane = !plane;
14843 intel_crtc_disable_planes(&crtc->base);
14844 dev_priv->display.crtc_disable(&crtc->base);
14845 crtc->plane = plane;
14846
14847 /* ... and break all links. */
14848 for_each_intel_connector(dev, connector) {
14849 if (connector->encoder->base.crtc != &crtc->base)
14850 continue;
14851
14852 connector->base.dpms = DRM_MODE_DPMS_OFF;
14853 connector->base.encoder = NULL;
14854 }
14855 /* multiple connectors may have the same encoder:
14856 * handle them and break crtc link separately */
14857 for_each_intel_connector(dev, connector)
14858 if (connector->encoder->base.crtc == &crtc->base) {
14859 connector->encoder->base.crtc = NULL;
14860 connector->encoder->connectors_active = false;
14861 }
14862
14863 WARN_ON(crtc->active);
14864 crtc->base.state->enable = false;
14865 crtc->base.state->active = false;
14866 crtc->base.enabled = false;
14867 }
14868
14869 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14870 crtc->pipe == PIPE_A && !crtc->active) {
14871 /* BIOS forgot to enable pipe A, this mostly happens after
14872 * resume. Force-enable the pipe to fix this, the update_dpms
14873 * call below we restore the pipe to the right state, but leave
14874 * the required bits on. */
14875 intel_enable_pipe_a(dev);
14876 }
14877
14878 /* Adjust the state of the output pipe according to whether we
14879 * have active connectors/encoders. */
14880 intel_crtc_update_dpms(&crtc->base);
14881
14882 if (crtc->active != crtc->base.state->enable) {
14883 struct intel_encoder *encoder;
14884
14885 /* This can happen either due to bugs in the get_hw_state
14886 * functions or because the pipe is force-enabled due to the
14887 * pipe A quirk. */
14888 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14889 crtc->base.base.id,
14890 crtc->base.state->enable ? "enabled" : "disabled",
14891 crtc->active ? "enabled" : "disabled");
14892
14893 crtc->base.state->enable = crtc->active;
14894 crtc->base.state->active = crtc->active;
14895 crtc->base.enabled = crtc->active;
14896
14897 /* Because we only establish the connector -> encoder ->
14898 * crtc links if something is active, this means the
14899 * crtc is now deactivated. Break the links. connector
14900 * -> encoder links are only establish when things are
14901 * actually up, hence no need to break them. */
14902 WARN_ON(crtc->active);
14903
14904 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14905 WARN_ON(encoder->connectors_active);
14906 encoder->base.crtc = NULL;
14907 }
14908 }
14909
14910 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14911 /*
14912 * We start out with underrun reporting disabled to avoid races.
14913 * For correct bookkeeping mark this on active crtcs.
14914 *
14915 * Also on gmch platforms we dont have any hardware bits to
14916 * disable the underrun reporting. Which means we need to start
14917 * out with underrun reporting disabled also on inactive pipes,
14918 * since otherwise we'll complain about the garbage we read when
14919 * e.g. coming up after runtime pm.
14920 *
14921 * No protection against concurrent access is required - at
14922 * worst a fifo underrun happens which also sets this to false.
14923 */
14924 crtc->cpu_fifo_underrun_disabled = true;
14925 crtc->pch_fifo_underrun_disabled = true;
14926 }
14927 }
14928
14929 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14930 {
14931 struct intel_connector *connector;
14932 struct drm_device *dev = encoder->base.dev;
14933
14934 /* We need to check both for a crtc link (meaning that the
14935 * encoder is active and trying to read from a pipe) and the
14936 * pipe itself being active. */
14937 bool has_active_crtc = encoder->base.crtc &&
14938 to_intel_crtc(encoder->base.crtc)->active;
14939
14940 if (encoder->connectors_active && !has_active_crtc) {
14941 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14942 encoder->base.base.id,
14943 encoder->base.name);
14944
14945 /* Connector is active, but has no active pipe. This is
14946 * fallout from our resume register restoring. Disable
14947 * the encoder manually again. */
14948 if (encoder->base.crtc) {
14949 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14950 encoder->base.base.id,
14951 encoder->base.name);
14952 encoder->disable(encoder);
14953 if (encoder->post_disable)
14954 encoder->post_disable(encoder);
14955 }
14956 encoder->base.crtc = NULL;
14957 encoder->connectors_active = false;
14958
14959 /* Inconsistent output/port/pipe state happens presumably due to
14960 * a bug in one of the get_hw_state functions. Or someplace else
14961 * in our code, like the register restore mess on resume. Clamp
14962 * things to off as a safer default. */
14963 for_each_intel_connector(dev, connector) {
14964 if (connector->encoder != encoder)
14965 continue;
14966 connector->base.dpms = DRM_MODE_DPMS_OFF;
14967 connector->base.encoder = NULL;
14968 }
14969 }
14970 /* Enabled encoders without active connectors will be fixed in
14971 * the crtc fixup. */
14972 }
14973
14974 void i915_redisable_vga_power_on(struct drm_device *dev)
14975 {
14976 struct drm_i915_private *dev_priv = dev->dev_private;
14977 u32 vga_reg = i915_vgacntrl_reg(dev);
14978
14979 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14980 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14981 i915_disable_vga(dev);
14982 }
14983 }
14984
14985 void i915_redisable_vga(struct drm_device *dev)
14986 {
14987 struct drm_i915_private *dev_priv = dev->dev_private;
14988
14989 /* This function can be called both from intel_modeset_setup_hw_state or
14990 * at a very early point in our resume sequence, where the power well
14991 * structures are not yet restored. Since this function is at a very
14992 * paranoid "someone might have enabled VGA while we were not looking"
14993 * level, just check if the power well is enabled instead of trying to
14994 * follow the "don't touch the power well if we don't need it" policy
14995 * the rest of the driver uses. */
14996 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14997 return;
14998
14999 i915_redisable_vga_power_on(dev);
15000 }
15001
15002 static bool primary_get_hw_state(struct intel_crtc *crtc)
15003 {
15004 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15005
15006 if (!crtc->active)
15007 return false;
15008
15009 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15010 }
15011
15012 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15013 {
15014 struct drm_i915_private *dev_priv = dev->dev_private;
15015 enum pipe pipe;
15016 struct intel_crtc *crtc;
15017 struct intel_encoder *encoder;
15018 struct intel_connector *connector;
15019 int i;
15020
15021 for_each_intel_crtc(dev, crtc) {
15022 struct drm_plane *primary = crtc->base.primary;
15023 struct intel_plane_state *plane_state;
15024
15025 memset(crtc->config, 0, sizeof(*crtc->config));
15026
15027 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15028
15029 crtc->active = dev_priv->display.get_pipe_config(crtc,
15030 crtc->config);
15031
15032 crtc->base.state->enable = crtc->active;
15033 crtc->base.state->active = crtc->active;
15034 crtc->base.enabled = crtc->active;
15035
15036 plane_state = to_intel_plane_state(primary->state);
15037 plane_state->visible = primary_get_hw_state(crtc);
15038
15039 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15040 crtc->base.base.id,
15041 crtc->active ? "enabled" : "disabled");
15042 }
15043
15044 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15045 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15046
15047 pll->on = pll->get_hw_state(dev_priv, pll,
15048 &pll->config.hw_state);
15049 pll->active = 0;
15050 pll->config.crtc_mask = 0;
15051 for_each_intel_crtc(dev, crtc) {
15052 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15053 pll->active++;
15054 pll->config.crtc_mask |= 1 << crtc->pipe;
15055 }
15056 }
15057
15058 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15059 pll->name, pll->config.crtc_mask, pll->on);
15060
15061 if (pll->config.crtc_mask)
15062 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15063 }
15064
15065 for_each_intel_encoder(dev, encoder) {
15066 pipe = 0;
15067
15068 if (encoder->get_hw_state(encoder, &pipe)) {
15069 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15070 encoder->base.crtc = &crtc->base;
15071 encoder->get_config(encoder, crtc->config);
15072 } else {
15073 encoder->base.crtc = NULL;
15074 }
15075
15076 encoder->connectors_active = false;
15077 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15078 encoder->base.base.id,
15079 encoder->base.name,
15080 encoder->base.crtc ? "enabled" : "disabled",
15081 pipe_name(pipe));
15082 }
15083
15084 for_each_intel_connector(dev, connector) {
15085 if (connector->get_hw_state(connector)) {
15086 connector->base.dpms = DRM_MODE_DPMS_ON;
15087 connector->encoder->connectors_active = true;
15088 connector->base.encoder = &connector->encoder->base;
15089 } else {
15090 connector->base.dpms = DRM_MODE_DPMS_OFF;
15091 connector->base.encoder = NULL;
15092 }
15093 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15094 connector->base.base.id,
15095 connector->base.name,
15096 connector->base.encoder ? "enabled" : "disabled");
15097 }
15098 }
15099
15100 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15101 * and i915 state tracking structures. */
15102 void intel_modeset_setup_hw_state(struct drm_device *dev,
15103 bool force_restore)
15104 {
15105 struct drm_i915_private *dev_priv = dev->dev_private;
15106 enum pipe pipe;
15107 struct intel_crtc *crtc;
15108 struct intel_encoder *encoder;
15109 int i;
15110
15111 intel_modeset_readout_hw_state(dev);
15112
15113 /*
15114 * Now that we have the config, copy it to each CRTC struct
15115 * Note that this could go away if we move to using crtc_config
15116 * checking everywhere.
15117 */
15118 for_each_intel_crtc(dev, crtc) {
15119 if (crtc->active && i915.fastboot) {
15120 intel_mode_from_pipe_config(&crtc->base.mode,
15121 crtc->config);
15122 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15123 crtc->base.base.id);
15124 drm_mode_debug_printmodeline(&crtc->base.mode);
15125 }
15126 }
15127
15128 /* HW state is read out, now we need to sanitize this mess. */
15129 for_each_intel_encoder(dev, encoder) {
15130 intel_sanitize_encoder(encoder);
15131 }
15132
15133 for_each_pipe(dev_priv, pipe) {
15134 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15135 intel_sanitize_crtc(crtc);
15136 intel_dump_pipe_config(crtc, crtc->config,
15137 "[setup_hw_state]");
15138 }
15139
15140 intel_modeset_update_connector_atomic_state(dev);
15141
15142 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15143 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15144
15145 if (!pll->on || pll->active)
15146 continue;
15147
15148 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15149
15150 pll->disable(dev_priv, pll);
15151 pll->on = false;
15152 }
15153
15154 if (IS_GEN9(dev))
15155 skl_wm_get_hw_state(dev);
15156 else if (HAS_PCH_SPLIT(dev))
15157 ilk_wm_get_hw_state(dev);
15158
15159 if (force_restore) {
15160 i915_redisable_vga(dev);
15161
15162 /*
15163 * We need to use raw interfaces for restoring state to avoid
15164 * checking (bogus) intermediate states.
15165 */
15166 for_each_pipe(dev_priv, pipe) {
15167 struct drm_crtc *crtc =
15168 dev_priv->pipe_to_crtc_mapping[pipe];
15169
15170 intel_crtc_restore_mode(crtc);
15171 }
15172 } else {
15173 intel_modeset_update_staged_output_state(dev);
15174 }
15175
15176 intel_modeset_check_state(dev);
15177 }
15178
15179 void intel_modeset_gem_init(struct drm_device *dev)
15180 {
15181 struct drm_i915_private *dev_priv = dev->dev_private;
15182 struct drm_crtc *c;
15183 struct drm_i915_gem_object *obj;
15184 int ret;
15185
15186 mutex_lock(&dev->struct_mutex);
15187 intel_init_gt_powersave(dev);
15188 mutex_unlock(&dev->struct_mutex);
15189
15190 /*
15191 * There may be no VBT; and if the BIOS enabled SSC we can
15192 * just keep using it to avoid unnecessary flicker. Whereas if the
15193 * BIOS isn't using it, don't assume it will work even if the VBT
15194 * indicates as much.
15195 */
15196 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15197 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15198 DREF_SSC1_ENABLE);
15199
15200 intel_modeset_init_hw(dev);
15201
15202 intel_setup_overlay(dev);
15203
15204 /*
15205 * Make sure any fbs we allocated at startup are properly
15206 * pinned & fenced. When we do the allocation it's too early
15207 * for this.
15208 */
15209 for_each_crtc(dev, c) {
15210 obj = intel_fb_obj(c->primary->fb);
15211 if (obj == NULL)
15212 continue;
15213
15214 mutex_lock(&dev->struct_mutex);
15215 ret = intel_pin_and_fence_fb_obj(c->primary,
15216 c->primary->fb,
15217 c->primary->state,
15218 NULL);
15219 mutex_unlock(&dev->struct_mutex);
15220 if (ret) {
15221 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15222 to_intel_crtc(c)->pipe);
15223 drm_framebuffer_unreference(c->primary->fb);
15224 c->primary->fb = NULL;
15225 update_state_fb(c->primary);
15226 }
15227 }
15228
15229 intel_backlight_register(dev);
15230 }
15231
15232 void intel_connector_unregister(struct intel_connector *intel_connector)
15233 {
15234 struct drm_connector *connector = &intel_connector->base;
15235
15236 intel_panel_destroy_backlight(connector);
15237 drm_connector_unregister(connector);
15238 }
15239
15240 void intel_modeset_cleanup(struct drm_device *dev)
15241 {
15242 struct drm_i915_private *dev_priv = dev->dev_private;
15243 struct drm_connector *connector;
15244
15245 intel_disable_gt_powersave(dev);
15246
15247 intel_backlight_unregister(dev);
15248
15249 /*
15250 * Interrupts and polling as the first thing to avoid creating havoc.
15251 * Too much stuff here (turning of connectors, ...) would
15252 * experience fancy races otherwise.
15253 */
15254 intel_irq_uninstall(dev_priv);
15255
15256 /*
15257 * Due to the hpd irq storm handling the hotplug work can re-arm the
15258 * poll handlers. Hence disable polling after hpd handling is shut down.
15259 */
15260 drm_kms_helper_poll_fini(dev);
15261
15262 mutex_lock(&dev->struct_mutex);
15263
15264 intel_unregister_dsm_handler();
15265
15266 intel_fbc_disable(dev);
15267
15268 mutex_unlock(&dev->struct_mutex);
15269
15270 /* flush any delayed tasks or pending work */
15271 flush_scheduled_work();
15272
15273 /* destroy the backlight and sysfs files before encoders/connectors */
15274 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15275 struct intel_connector *intel_connector;
15276
15277 intel_connector = to_intel_connector(connector);
15278 intel_connector->unregister(intel_connector);
15279 }
15280
15281 drm_mode_config_cleanup(dev);
15282
15283 intel_cleanup_overlay(dev);
15284
15285 mutex_lock(&dev->struct_mutex);
15286 intel_cleanup_gt_powersave(dev);
15287 mutex_unlock(&dev->struct_mutex);
15288 }
15289
15290 /*
15291 * Return which encoder is currently attached for connector.
15292 */
15293 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15294 {
15295 return &intel_attached_encoder(connector)->base;
15296 }
15297
15298 void intel_connector_attach_encoder(struct intel_connector *connector,
15299 struct intel_encoder *encoder)
15300 {
15301 connector->encoder = encoder;
15302 drm_mode_connector_attach_encoder(&connector->base,
15303 &encoder->base);
15304 }
15305
15306 /*
15307 * set vga decode state - true == enable VGA decode
15308 */
15309 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15310 {
15311 struct drm_i915_private *dev_priv = dev->dev_private;
15312 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15313 u16 gmch_ctrl;
15314
15315 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15316 DRM_ERROR("failed to read control word\n");
15317 return -EIO;
15318 }
15319
15320 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15321 return 0;
15322
15323 if (state)
15324 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15325 else
15326 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15327
15328 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15329 DRM_ERROR("failed to write control word\n");
15330 return -EIO;
15331 }
15332
15333 return 0;
15334 }
15335
15336 struct intel_display_error_state {
15337
15338 u32 power_well_driver;
15339
15340 int num_transcoders;
15341
15342 struct intel_cursor_error_state {
15343 u32 control;
15344 u32 position;
15345 u32 base;
15346 u32 size;
15347 } cursor[I915_MAX_PIPES];
15348
15349 struct intel_pipe_error_state {
15350 bool power_domain_on;
15351 u32 source;
15352 u32 stat;
15353 } pipe[I915_MAX_PIPES];
15354
15355 struct intel_plane_error_state {
15356 u32 control;
15357 u32 stride;
15358 u32 size;
15359 u32 pos;
15360 u32 addr;
15361 u32 surface;
15362 u32 tile_offset;
15363 } plane[I915_MAX_PIPES];
15364
15365 struct intel_transcoder_error_state {
15366 bool power_domain_on;
15367 enum transcoder cpu_transcoder;
15368
15369 u32 conf;
15370
15371 u32 htotal;
15372 u32 hblank;
15373 u32 hsync;
15374 u32 vtotal;
15375 u32 vblank;
15376 u32 vsync;
15377 } transcoder[4];
15378 };
15379
15380 struct intel_display_error_state *
15381 intel_display_capture_error_state(struct drm_device *dev)
15382 {
15383 struct drm_i915_private *dev_priv = dev->dev_private;
15384 struct intel_display_error_state *error;
15385 int transcoders[] = {
15386 TRANSCODER_A,
15387 TRANSCODER_B,
15388 TRANSCODER_C,
15389 TRANSCODER_EDP,
15390 };
15391 int i;
15392
15393 if (INTEL_INFO(dev)->num_pipes == 0)
15394 return NULL;
15395
15396 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15397 if (error == NULL)
15398 return NULL;
15399
15400 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15401 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15402
15403 for_each_pipe(dev_priv, i) {
15404 error->pipe[i].power_domain_on =
15405 __intel_display_power_is_enabled(dev_priv,
15406 POWER_DOMAIN_PIPE(i));
15407 if (!error->pipe[i].power_domain_on)
15408 continue;
15409
15410 error->cursor[i].control = I915_READ(CURCNTR(i));
15411 error->cursor[i].position = I915_READ(CURPOS(i));
15412 error->cursor[i].base = I915_READ(CURBASE(i));
15413
15414 error->plane[i].control = I915_READ(DSPCNTR(i));
15415 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15416 if (INTEL_INFO(dev)->gen <= 3) {
15417 error->plane[i].size = I915_READ(DSPSIZE(i));
15418 error->plane[i].pos = I915_READ(DSPPOS(i));
15419 }
15420 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15421 error->plane[i].addr = I915_READ(DSPADDR(i));
15422 if (INTEL_INFO(dev)->gen >= 4) {
15423 error->plane[i].surface = I915_READ(DSPSURF(i));
15424 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15425 }
15426
15427 error->pipe[i].source = I915_READ(PIPESRC(i));
15428
15429 if (HAS_GMCH_DISPLAY(dev))
15430 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15431 }
15432
15433 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15434 if (HAS_DDI(dev_priv->dev))
15435 error->num_transcoders++; /* Account for eDP. */
15436
15437 for (i = 0; i < error->num_transcoders; i++) {
15438 enum transcoder cpu_transcoder = transcoders[i];
15439
15440 error->transcoder[i].power_domain_on =
15441 __intel_display_power_is_enabled(dev_priv,
15442 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15443 if (!error->transcoder[i].power_domain_on)
15444 continue;
15445
15446 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15447
15448 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15449 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15450 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15451 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15452 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15453 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15454 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15455 }
15456
15457 return error;
15458 }
15459
15460 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15461
15462 void
15463 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15464 struct drm_device *dev,
15465 struct intel_display_error_state *error)
15466 {
15467 struct drm_i915_private *dev_priv = dev->dev_private;
15468 int i;
15469
15470 if (!error)
15471 return;
15472
15473 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15474 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15475 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15476 error->power_well_driver);
15477 for_each_pipe(dev_priv, i) {
15478 err_printf(m, "Pipe [%d]:\n", i);
15479 err_printf(m, " Power: %s\n",
15480 error->pipe[i].power_domain_on ? "on" : "off");
15481 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15482 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15483
15484 err_printf(m, "Plane [%d]:\n", i);
15485 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15486 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15487 if (INTEL_INFO(dev)->gen <= 3) {
15488 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15489 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15490 }
15491 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15492 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15493 if (INTEL_INFO(dev)->gen >= 4) {
15494 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15495 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15496 }
15497
15498 err_printf(m, "Cursor [%d]:\n", i);
15499 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15500 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15501 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15502 }
15503
15504 for (i = 0; i < error->num_transcoders; i++) {
15505 err_printf(m, "CPU transcoder: %c\n",
15506 transcoder_name(error->transcoder[i].cpu_transcoder));
15507 err_printf(m, " Power: %s\n",
15508 error->transcoder[i].power_domain_on ? "on" : "off");
15509 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15510 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15511 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15512 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15513 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15514 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15515 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15516 }
15517 }
15518
15519 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15520 {
15521 struct intel_crtc *crtc;
15522
15523 for_each_intel_crtc(dev, crtc) {
15524 struct intel_unpin_work *work;
15525
15526 spin_lock_irq(&dev->event_lock);
15527
15528 work = crtc->unpin_work;
15529
15530 if (work && work->event &&
15531 work->event->base.file_priv == file) {
15532 kfree(work->event);
15533 work->event = NULL;
15534 }
15535
15536 spin_unlock_irq(&dev->event_lock);
15537 }
15538 }
Linux kernel - Deliverables
This page took 0.397995 seconds and 6 git commands to generate.