2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
52 DRM_FORMAT_XRGB8888, \
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2
[] = {
57 COMMON_PRIMARY_FORMATS
,
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4
[] = {
64 COMMON_PRIMARY_FORMATS
, \
67 DRM_FORMAT_XRGB2101010
,
68 DRM_FORMAT_ARGB2101010
,
69 DRM_FORMAT_XBGR2101010
,
70 DRM_FORMAT_ABGR2101010
,
74 static const uint32_t intel_cursor_formats
[] = {
78 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
80 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
81 struct intel_crtc_state
*pipe_config
);
82 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
83 struct intel_crtc_state
*pipe_config
);
85 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
86 int x
, int y
, struct drm_framebuffer
*old_fb
);
87 static int intel_framebuffer_init(struct drm_device
*dev
,
88 struct intel_framebuffer
*ifb
,
89 struct drm_mode_fb_cmd2
*mode_cmd
,
90 struct drm_i915_gem_object
*obj
);
91 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
92 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
94 struct intel_link_m_n
*m_n
,
95 struct intel_link_m_n
*m2_n2
);
96 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
97 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
98 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
99 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
100 const struct intel_crtc_state
*pipe_config
);
101 static void chv_prepare_pll(struct intel_crtc
*crtc
,
102 const struct intel_crtc_state
*pipe_config
);
103 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
);
104 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
);
106 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
108 if (!connector
->mst_port
)
109 return connector
->encoder
;
111 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
120 int p2_slow
, p2_fast
;
123 typedef struct intel_limit intel_limit_t
;
125 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
130 intel_pch_rawclk(struct drm_device
*dev
)
132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 WARN_ON(!HAS_PCH_SPLIT(dev
));
136 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
139 static inline u32
/* units of 100MHz */
140 intel_fdi_link_freq(struct drm_device
*dev
)
143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
144 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
149 static const intel_limit_t intel_limits_i8xx_dac
= {
150 .dot
= { .min
= 25000, .max
= 350000 },
151 .vco
= { .min
= 908000, .max
= 1512000 },
152 .n
= { .min
= 2, .max
= 16 },
153 .m
= { .min
= 96, .max
= 140 },
154 .m1
= { .min
= 18, .max
= 26 },
155 .m2
= { .min
= 6, .max
= 16 },
156 .p
= { .min
= 4, .max
= 128 },
157 .p1
= { .min
= 2, .max
= 33 },
158 .p2
= { .dot_limit
= 165000,
159 .p2_slow
= 4, .p2_fast
= 2 },
162 static const intel_limit_t intel_limits_i8xx_dvo
= {
163 .dot
= { .min
= 25000, .max
= 350000 },
164 .vco
= { .min
= 908000, .max
= 1512000 },
165 .n
= { .min
= 2, .max
= 16 },
166 .m
= { .min
= 96, .max
= 140 },
167 .m1
= { .min
= 18, .max
= 26 },
168 .m2
= { .min
= 6, .max
= 16 },
169 .p
= { .min
= 4, .max
= 128 },
170 .p1
= { .min
= 2, .max
= 33 },
171 .p2
= { .dot_limit
= 165000,
172 .p2_slow
= 4, .p2_fast
= 4 },
175 static const intel_limit_t intel_limits_i8xx_lvds
= {
176 .dot
= { .min
= 25000, .max
= 350000 },
177 .vco
= { .min
= 908000, .max
= 1512000 },
178 .n
= { .min
= 2, .max
= 16 },
179 .m
= { .min
= 96, .max
= 140 },
180 .m1
= { .min
= 18, .max
= 26 },
181 .m2
= { .min
= 6, .max
= 16 },
182 .p
= { .min
= 4, .max
= 128 },
183 .p1
= { .min
= 1, .max
= 6 },
184 .p2
= { .dot_limit
= 165000,
185 .p2_slow
= 14, .p2_fast
= 7 },
188 static const intel_limit_t intel_limits_i9xx_sdvo
= {
189 .dot
= { .min
= 20000, .max
= 400000 },
190 .vco
= { .min
= 1400000, .max
= 2800000 },
191 .n
= { .min
= 1, .max
= 6 },
192 .m
= { .min
= 70, .max
= 120 },
193 .m1
= { .min
= 8, .max
= 18 },
194 .m2
= { .min
= 3, .max
= 7 },
195 .p
= { .min
= 5, .max
= 80 },
196 .p1
= { .min
= 1, .max
= 8 },
197 .p2
= { .dot_limit
= 200000,
198 .p2_slow
= 10, .p2_fast
= 5 },
201 static const intel_limit_t intel_limits_i9xx_lvds
= {
202 .dot
= { .min
= 20000, .max
= 400000 },
203 .vco
= { .min
= 1400000, .max
= 2800000 },
204 .n
= { .min
= 1, .max
= 6 },
205 .m
= { .min
= 70, .max
= 120 },
206 .m1
= { .min
= 8, .max
= 18 },
207 .m2
= { .min
= 3, .max
= 7 },
208 .p
= { .min
= 7, .max
= 98 },
209 .p1
= { .min
= 1, .max
= 8 },
210 .p2
= { .dot_limit
= 112000,
211 .p2_slow
= 14, .p2_fast
= 7 },
215 static const intel_limit_t intel_limits_g4x_sdvo
= {
216 .dot
= { .min
= 25000, .max
= 270000 },
217 .vco
= { .min
= 1750000, .max
= 3500000},
218 .n
= { .min
= 1, .max
= 4 },
219 .m
= { .min
= 104, .max
= 138 },
220 .m1
= { .min
= 17, .max
= 23 },
221 .m2
= { .min
= 5, .max
= 11 },
222 .p
= { .min
= 10, .max
= 30 },
223 .p1
= { .min
= 1, .max
= 3},
224 .p2
= { .dot_limit
= 270000,
230 static const intel_limit_t intel_limits_g4x_hdmi
= {
231 .dot
= { .min
= 22000, .max
= 400000 },
232 .vco
= { .min
= 1750000, .max
= 3500000},
233 .n
= { .min
= 1, .max
= 4 },
234 .m
= { .min
= 104, .max
= 138 },
235 .m1
= { .min
= 16, .max
= 23 },
236 .m2
= { .min
= 5, .max
= 11 },
237 .p
= { .min
= 5, .max
= 80 },
238 .p1
= { .min
= 1, .max
= 8},
239 .p2
= { .dot_limit
= 165000,
240 .p2_slow
= 10, .p2_fast
= 5 },
243 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
244 .dot
= { .min
= 20000, .max
= 115000 },
245 .vco
= { .min
= 1750000, .max
= 3500000 },
246 .n
= { .min
= 1, .max
= 3 },
247 .m
= { .min
= 104, .max
= 138 },
248 .m1
= { .min
= 17, .max
= 23 },
249 .m2
= { .min
= 5, .max
= 11 },
250 .p
= { .min
= 28, .max
= 112 },
251 .p1
= { .min
= 2, .max
= 8 },
252 .p2
= { .dot_limit
= 0,
253 .p2_slow
= 14, .p2_fast
= 14
257 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
258 .dot
= { .min
= 80000, .max
= 224000 },
259 .vco
= { .min
= 1750000, .max
= 3500000 },
260 .n
= { .min
= 1, .max
= 3 },
261 .m
= { .min
= 104, .max
= 138 },
262 .m1
= { .min
= 17, .max
= 23 },
263 .m2
= { .min
= 5, .max
= 11 },
264 .p
= { .min
= 14, .max
= 42 },
265 .p1
= { .min
= 2, .max
= 6 },
266 .p2
= { .dot_limit
= 0,
267 .p2_slow
= 7, .p2_fast
= 7
271 static const intel_limit_t intel_limits_pineview_sdvo
= {
272 .dot
= { .min
= 20000, .max
= 400000},
273 .vco
= { .min
= 1700000, .max
= 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n
= { .min
= 3, .max
= 6 },
276 .m
= { .min
= 2, .max
= 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1
= { .min
= 0, .max
= 0 },
279 .m2
= { .min
= 0, .max
= 254 },
280 .p
= { .min
= 5, .max
= 80 },
281 .p1
= { .min
= 1, .max
= 8 },
282 .p2
= { .dot_limit
= 200000,
283 .p2_slow
= 10, .p2_fast
= 5 },
286 static const intel_limit_t intel_limits_pineview_lvds
= {
287 .dot
= { .min
= 20000, .max
= 400000 },
288 .vco
= { .min
= 1700000, .max
= 3500000 },
289 .n
= { .min
= 3, .max
= 6 },
290 .m
= { .min
= 2, .max
= 256 },
291 .m1
= { .min
= 0, .max
= 0 },
292 .m2
= { .min
= 0, .max
= 254 },
293 .p
= { .min
= 7, .max
= 112 },
294 .p1
= { .min
= 1, .max
= 8 },
295 .p2
= { .dot_limit
= 112000,
296 .p2_slow
= 14, .p2_fast
= 14 },
299 /* Ironlake / Sandybridge
301 * We calculate clock using (register_value + 2) for N/M1/M2, so here
302 * the range value for them is (actual_value - 2).
304 static const intel_limit_t intel_limits_ironlake_dac
= {
305 .dot
= { .min
= 25000, .max
= 350000 },
306 .vco
= { .min
= 1760000, .max
= 3510000 },
307 .n
= { .min
= 1, .max
= 5 },
308 .m
= { .min
= 79, .max
= 127 },
309 .m1
= { .min
= 12, .max
= 22 },
310 .m2
= { .min
= 5, .max
= 9 },
311 .p
= { .min
= 5, .max
= 80 },
312 .p1
= { .min
= 1, .max
= 8 },
313 .p2
= { .dot_limit
= 225000,
314 .p2_slow
= 10, .p2_fast
= 5 },
317 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
318 .dot
= { .min
= 25000, .max
= 350000 },
319 .vco
= { .min
= 1760000, .max
= 3510000 },
320 .n
= { .min
= 1, .max
= 3 },
321 .m
= { .min
= 79, .max
= 118 },
322 .m1
= { .min
= 12, .max
= 22 },
323 .m2
= { .min
= 5, .max
= 9 },
324 .p
= { .min
= 28, .max
= 112 },
325 .p1
= { .min
= 2, .max
= 8 },
326 .p2
= { .dot_limit
= 225000,
327 .p2_slow
= 14, .p2_fast
= 14 },
330 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
331 .dot
= { .min
= 25000, .max
= 350000 },
332 .vco
= { .min
= 1760000, .max
= 3510000 },
333 .n
= { .min
= 1, .max
= 3 },
334 .m
= { .min
= 79, .max
= 127 },
335 .m1
= { .min
= 12, .max
= 22 },
336 .m2
= { .min
= 5, .max
= 9 },
337 .p
= { .min
= 14, .max
= 56 },
338 .p1
= { .min
= 2, .max
= 8 },
339 .p2
= { .dot_limit
= 225000,
340 .p2_slow
= 7, .p2_fast
= 7 },
343 /* LVDS 100mhz refclk limits. */
344 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
345 .dot
= { .min
= 25000, .max
= 350000 },
346 .vco
= { .min
= 1760000, .max
= 3510000 },
347 .n
= { .min
= 1, .max
= 2 },
348 .m
= { .min
= 79, .max
= 126 },
349 .m1
= { .min
= 12, .max
= 22 },
350 .m2
= { .min
= 5, .max
= 9 },
351 .p
= { .min
= 28, .max
= 112 },
352 .p1
= { .min
= 2, .max
= 8 },
353 .p2
= { .dot_limit
= 225000,
354 .p2_slow
= 14, .p2_fast
= 14 },
357 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
358 .dot
= { .min
= 25000, .max
= 350000 },
359 .vco
= { .min
= 1760000, .max
= 3510000 },
360 .n
= { .min
= 1, .max
= 3 },
361 .m
= { .min
= 79, .max
= 126 },
362 .m1
= { .min
= 12, .max
= 22 },
363 .m2
= { .min
= 5, .max
= 9 },
364 .p
= { .min
= 14, .max
= 42 },
365 .p1
= { .min
= 2, .max
= 6 },
366 .p2
= { .dot_limit
= 225000,
367 .p2_slow
= 7, .p2_fast
= 7 },
370 static const intel_limit_t intel_limits_vlv
= {
372 * These are the data rate limits (measured in fast clocks)
373 * since those are the strictest limits we have. The fast
374 * clock and actual rate limits are more relaxed, so checking
375 * them would make no difference.
377 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
378 .vco
= { .min
= 4000000, .max
= 6000000 },
379 .n
= { .min
= 1, .max
= 7 },
380 .m1
= { .min
= 2, .max
= 3 },
381 .m2
= { .min
= 11, .max
= 156 },
382 .p1
= { .min
= 2, .max
= 3 },
383 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
386 static const intel_limit_t intel_limits_chv
= {
388 * These are the data rate limits (measured in fast clocks)
389 * since those are the strictest limits we have. The fast
390 * clock and actual rate limits are more relaxed, so checking
391 * them would make no difference.
393 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
394 .vco
= { .min
= 4860000, .max
= 6700000 },
395 .n
= { .min
= 1, .max
= 1 },
396 .m1
= { .min
= 2, .max
= 2 },
397 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
398 .p1
= { .min
= 2, .max
= 4 },
399 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
402 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
404 clock
->m
= clock
->m1
* clock
->m2
;
405 clock
->p
= clock
->p1
* clock
->p2
;
406 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
408 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
409 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
413 * Returns whether any output on the specified pipe is of the specified type
415 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
417 struct drm_device
*dev
= crtc
->base
.dev
;
418 struct intel_encoder
*encoder
;
420 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
421 if (encoder
->type
== type
)
428 * Returns whether any output on the specified pipe will have the specified
429 * type after a staged modeset is complete, i.e., the same as
430 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
433 static bool intel_pipe_will_have_type(struct intel_crtc
*crtc
, int type
)
435 struct drm_device
*dev
= crtc
->base
.dev
;
436 struct intel_encoder
*encoder
;
438 for_each_intel_encoder(dev
, encoder
)
439 if (encoder
->new_crtc
== crtc
&& encoder
->type
== type
)
445 static const intel_limit_t
*intel_ironlake_limit(struct intel_crtc
*crtc
,
448 struct drm_device
*dev
= crtc
->base
.dev
;
449 const intel_limit_t
*limit
;
451 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
452 if (intel_is_dual_link_lvds(dev
)) {
453 if (refclk
== 100000)
454 limit
= &intel_limits_ironlake_dual_lvds_100m
;
456 limit
= &intel_limits_ironlake_dual_lvds
;
458 if (refclk
== 100000)
459 limit
= &intel_limits_ironlake_single_lvds_100m
;
461 limit
= &intel_limits_ironlake_single_lvds
;
464 limit
= &intel_limits_ironlake_dac
;
469 static const intel_limit_t
*intel_g4x_limit(struct intel_crtc
*crtc
)
471 struct drm_device
*dev
= crtc
->base
.dev
;
472 const intel_limit_t
*limit
;
474 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
475 if (intel_is_dual_link_lvds(dev
))
476 limit
= &intel_limits_g4x_dual_channel_lvds
;
478 limit
= &intel_limits_g4x_single_channel_lvds
;
479 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
) ||
480 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
481 limit
= &intel_limits_g4x_hdmi
;
482 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
)) {
483 limit
= &intel_limits_g4x_sdvo
;
484 } else /* The option is for other outputs */
485 limit
= &intel_limits_i9xx_sdvo
;
490 static const intel_limit_t
*intel_limit(struct intel_crtc
*crtc
, int refclk
)
492 struct drm_device
*dev
= crtc
->base
.dev
;
493 const intel_limit_t
*limit
;
495 if (HAS_PCH_SPLIT(dev
))
496 limit
= intel_ironlake_limit(crtc
, refclk
);
497 else if (IS_G4X(dev
)) {
498 limit
= intel_g4x_limit(crtc
);
499 } else if (IS_PINEVIEW(dev
)) {
500 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
501 limit
= &intel_limits_pineview_lvds
;
503 limit
= &intel_limits_pineview_sdvo
;
504 } else if (IS_CHERRYVIEW(dev
)) {
505 limit
= &intel_limits_chv
;
506 } else if (IS_VALLEYVIEW(dev
)) {
507 limit
= &intel_limits_vlv
;
508 } else if (!IS_GEN2(dev
)) {
509 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
510 limit
= &intel_limits_i9xx_lvds
;
512 limit
= &intel_limits_i9xx_sdvo
;
514 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
515 limit
= &intel_limits_i8xx_lvds
;
516 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
517 limit
= &intel_limits_i8xx_dvo
;
519 limit
= &intel_limits_i8xx_dac
;
524 /* m1 is reserved as 0 in Pineview, n is a ring counter */
525 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
527 clock
->m
= clock
->m2
+ 2;
528 clock
->p
= clock
->p1
* clock
->p2
;
529 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
531 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
532 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
535 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
537 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
540 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
542 clock
->m
= i9xx_dpll_compute_m(clock
);
543 clock
->p
= clock
->p1
* clock
->p2
;
544 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
546 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
547 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
550 static void chv_clock(int refclk
, intel_clock_t
*clock
)
552 clock
->m
= clock
->m1
* clock
->m2
;
553 clock
->p
= clock
->p1
* clock
->p2
;
554 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
556 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
558 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
561 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
563 * Returns whether the given set of divisors are valid for a given refclk with
564 * the given connectors.
567 static bool intel_PLL_is_valid(struct drm_device
*dev
,
568 const intel_limit_t
*limit
,
569 const intel_clock_t
*clock
)
571 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
572 INTELPllInvalid("n out of range\n");
573 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
574 INTELPllInvalid("p1 out of range\n");
575 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
576 INTELPllInvalid("m2 out of range\n");
577 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
578 INTELPllInvalid("m1 out of range\n");
580 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
581 if (clock
->m1
<= clock
->m2
)
582 INTELPllInvalid("m1 <= m2\n");
584 if (!IS_VALLEYVIEW(dev
)) {
585 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
586 INTELPllInvalid("p out of range\n");
587 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
588 INTELPllInvalid("m out of range\n");
591 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
592 INTELPllInvalid("vco out of range\n");
593 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
594 * connector, etc., rather than just a single range.
596 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
597 INTELPllInvalid("dot out of range\n");
603 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
604 int target
, int refclk
, intel_clock_t
*match_clock
,
605 intel_clock_t
*best_clock
)
607 struct drm_device
*dev
= crtc
->base
.dev
;
611 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
617 if (intel_is_dual_link_lvds(dev
))
618 clock
.p2
= limit
->p2
.p2_fast
;
620 clock
.p2
= limit
->p2
.p2_slow
;
622 if (target
< limit
->p2
.dot_limit
)
623 clock
.p2
= limit
->p2
.p2_slow
;
625 clock
.p2
= limit
->p2
.p2_fast
;
628 memset(best_clock
, 0, sizeof(*best_clock
));
630 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
632 for (clock
.m2
= limit
->m2
.min
;
633 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
634 if (clock
.m2
>= clock
.m1
)
636 for (clock
.n
= limit
->n
.min
;
637 clock
.n
<= limit
->n
.max
; clock
.n
++) {
638 for (clock
.p1
= limit
->p1
.min
;
639 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
642 i9xx_clock(refclk
, &clock
);
643 if (!intel_PLL_is_valid(dev
, limit
,
647 clock
.p
!= match_clock
->p
)
650 this_err
= abs(clock
.dot
- target
);
651 if (this_err
< err
) {
660 return (err
!= target
);
664 pnv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
665 int target
, int refclk
, intel_clock_t
*match_clock
,
666 intel_clock_t
*best_clock
)
668 struct drm_device
*dev
= crtc
->base
.dev
;
672 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
674 * For LVDS just rely on its current settings for dual-channel.
675 * We haven't figured out how to reliably set up different
676 * single/dual channel state, if we even can.
678 if (intel_is_dual_link_lvds(dev
))
679 clock
.p2
= limit
->p2
.p2_fast
;
681 clock
.p2
= limit
->p2
.p2_slow
;
683 if (target
< limit
->p2
.dot_limit
)
684 clock
.p2
= limit
->p2
.p2_slow
;
686 clock
.p2
= limit
->p2
.p2_fast
;
689 memset(best_clock
, 0, sizeof(*best_clock
));
691 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
693 for (clock
.m2
= limit
->m2
.min
;
694 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
695 for (clock
.n
= limit
->n
.min
;
696 clock
.n
<= limit
->n
.max
; clock
.n
++) {
697 for (clock
.p1
= limit
->p1
.min
;
698 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
701 pineview_clock(refclk
, &clock
);
702 if (!intel_PLL_is_valid(dev
, limit
,
706 clock
.p
!= match_clock
->p
)
709 this_err
= abs(clock
.dot
- target
);
710 if (this_err
< err
) {
719 return (err
!= target
);
723 g4x_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
724 int target
, int refclk
, intel_clock_t
*match_clock
,
725 intel_clock_t
*best_clock
)
727 struct drm_device
*dev
= crtc
->base
.dev
;
731 /* approximately equals target * 0.00585 */
732 int err_most
= (target
>> 8) + (target
>> 9);
735 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
736 if (intel_is_dual_link_lvds(dev
))
737 clock
.p2
= limit
->p2
.p2_fast
;
739 clock
.p2
= limit
->p2
.p2_slow
;
741 if (target
< limit
->p2
.dot_limit
)
742 clock
.p2
= limit
->p2
.p2_slow
;
744 clock
.p2
= limit
->p2
.p2_fast
;
747 memset(best_clock
, 0, sizeof(*best_clock
));
748 max_n
= limit
->n
.max
;
749 /* based on hardware requirement, prefer smaller n to precision */
750 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
751 /* based on hardware requirement, prefere larger m1,m2 */
752 for (clock
.m1
= limit
->m1
.max
;
753 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
754 for (clock
.m2
= limit
->m2
.max
;
755 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
756 for (clock
.p1
= limit
->p1
.max
;
757 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
760 i9xx_clock(refclk
, &clock
);
761 if (!intel_PLL_is_valid(dev
, limit
,
765 this_err
= abs(clock
.dot
- target
);
766 if (this_err
< err_most
) {
780 vlv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
781 int target
, int refclk
, intel_clock_t
*match_clock
,
782 intel_clock_t
*best_clock
)
784 struct drm_device
*dev
= crtc
->base
.dev
;
786 unsigned int bestppm
= 1000000;
787 /* min update 19.2 MHz */
788 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
791 target
*= 5; /* fast clock */
793 memset(best_clock
, 0, sizeof(*best_clock
));
795 /* based on hardware requirement, prefer smaller n to precision */
796 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
797 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
798 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
799 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
800 clock
.p
= clock
.p1
* clock
.p2
;
801 /* based on hardware requirement, prefer bigger m1,m2 values */
802 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
803 unsigned int ppm
, diff
;
805 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
808 vlv_clock(refclk
, &clock
);
810 if (!intel_PLL_is_valid(dev
, limit
,
814 diff
= abs(clock
.dot
- target
);
815 ppm
= div_u64(1000000ULL * diff
, target
);
817 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
823 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
837 chv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
838 int target
, int refclk
, intel_clock_t
*match_clock
,
839 intel_clock_t
*best_clock
)
841 struct drm_device
*dev
= crtc
->base
.dev
;
846 memset(best_clock
, 0, sizeof(*best_clock
));
849 * Based on hardware doc, the n always set to 1, and m1 always
850 * set to 2. If requires to support 200Mhz refclk, we need to
851 * revisit this because n may not 1 anymore.
853 clock
.n
= 1, clock
.m1
= 2;
854 target
*= 5; /* fast clock */
856 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
857 for (clock
.p2
= limit
->p2
.p2_fast
;
858 clock
.p2
>= limit
->p2
.p2_slow
;
859 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
861 clock
.p
= clock
.p1
* clock
.p2
;
863 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
864 clock
.n
) << 22, refclk
* clock
.m1
);
866 if (m2
> INT_MAX
/clock
.m1
)
871 chv_clock(refclk
, &clock
);
873 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
876 /* based on hardware requirement, prefer bigger p
878 if (clock
.p
> best_clock
->p
) {
888 bool intel_crtc_active(struct drm_crtc
*crtc
)
890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
892 /* Be paranoid as we can arrive here with only partial
893 * state retrieved from the hardware during setup.
895 * We can ditch the adjusted_mode.crtc_clock check as soon
896 * as Haswell has gained clock readout/fastboot support.
898 * We can ditch the crtc->primary->fb check as soon as we can
899 * properly reconstruct framebuffers.
901 return intel_crtc
->active
&& crtc
->primary
->fb
&&
902 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
905 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
908 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
909 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
911 return intel_crtc
->config
->cpu_transcoder
;
914 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
917 u32 reg
= PIPEDSL(pipe
);
922 line_mask
= DSL_LINEMASK_GEN2
;
924 line_mask
= DSL_LINEMASK_GEN3
;
926 line1
= I915_READ(reg
) & line_mask
;
928 line2
= I915_READ(reg
) & line_mask
;
930 return line1
== line2
;
934 * intel_wait_for_pipe_off - wait for pipe to turn off
935 * @crtc: crtc whose pipe to wait for
937 * After disabling a pipe, we can't wait for vblank in the usual way,
938 * spinning on the vblank interrupt status bit, since we won't actually
939 * see an interrupt when the pipe is disabled.
942 * wait for the pipe register state bit to turn off
945 * wait for the display line value to settle (it usually
946 * ends up stopping at the start of the next frame).
949 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
951 struct drm_device
*dev
= crtc
->base
.dev
;
952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
953 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
954 enum pipe pipe
= crtc
->pipe
;
956 if (INTEL_INFO(dev
)->gen
>= 4) {
957 int reg
= PIPECONF(cpu_transcoder
);
959 /* Wait for the Pipe State to go off */
960 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
962 WARN(1, "pipe_off wait timed out\n");
964 /* Wait for the display line to settle */
965 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
966 WARN(1, "pipe_off wait timed out\n");
971 * ibx_digital_port_connected - is the specified port connected?
972 * @dev_priv: i915 private structure
973 * @port: the port to test
975 * Returns true if @port is connected, false otherwise.
977 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
978 struct intel_digital_port
*port
)
982 if (HAS_PCH_IBX(dev_priv
->dev
)) {
983 switch (port
->port
) {
985 bit
= SDE_PORTB_HOTPLUG
;
988 bit
= SDE_PORTC_HOTPLUG
;
991 bit
= SDE_PORTD_HOTPLUG
;
997 switch (port
->port
) {
999 bit
= SDE_PORTB_HOTPLUG_CPT
;
1002 bit
= SDE_PORTC_HOTPLUG_CPT
;
1005 bit
= SDE_PORTD_HOTPLUG_CPT
;
1012 return I915_READ(SDEISR
) & bit
;
1015 static const char *state_string(bool enabled
)
1017 return enabled
? "on" : "off";
1020 /* Only for pre-ILK configs */
1021 void assert_pll(struct drm_i915_private
*dev_priv
,
1022 enum pipe pipe
, bool state
)
1029 val
= I915_READ(reg
);
1030 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1031 I915_STATE_WARN(cur_state
!= state
,
1032 "PLL state assertion failure (expected %s, current %s)\n",
1033 state_string(state
), state_string(cur_state
));
1036 /* XXX: the dsi pll is shared between MIPI DSI ports */
1037 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1042 mutex_lock(&dev_priv
->dpio_lock
);
1043 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1044 mutex_unlock(&dev_priv
->dpio_lock
);
1046 cur_state
= val
& DSI_PLL_VCO_EN
;
1047 I915_STATE_WARN(cur_state
!= state
,
1048 "DSI PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state
), state_string(cur_state
));
1051 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1052 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1054 struct intel_shared_dpll
*
1055 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1057 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1059 if (crtc
->config
->shared_dpll
< 0)
1062 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1066 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1067 struct intel_shared_dpll
*pll
,
1071 struct intel_dpll_hw_state hw_state
;
1074 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1077 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1078 I915_STATE_WARN(cur_state
!= state
,
1079 "%s assertion failure (expected %s, current %s)\n",
1080 pll
->name
, state_string(state
), state_string(cur_state
));
1083 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1084 enum pipe pipe
, bool state
)
1089 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1092 if (HAS_DDI(dev_priv
->dev
)) {
1093 /* DDI does not have a specific FDI_TX register */
1094 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1095 val
= I915_READ(reg
);
1096 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1098 reg
= FDI_TX_CTL(pipe
);
1099 val
= I915_READ(reg
);
1100 cur_state
= !!(val
& FDI_TX_ENABLE
);
1102 I915_STATE_WARN(cur_state
!= state
,
1103 "FDI TX state assertion failure (expected %s, current %s)\n",
1104 state_string(state
), state_string(cur_state
));
1106 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1107 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1109 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1110 enum pipe pipe
, bool state
)
1116 reg
= FDI_RX_CTL(pipe
);
1117 val
= I915_READ(reg
);
1118 cur_state
= !!(val
& FDI_RX_ENABLE
);
1119 I915_STATE_WARN(cur_state
!= state
,
1120 "FDI RX state assertion failure (expected %s, current %s)\n",
1121 state_string(state
), state_string(cur_state
));
1123 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1124 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1126 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1132 /* ILK FDI PLL is always enabled */
1133 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1136 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1137 if (HAS_DDI(dev_priv
->dev
))
1140 reg
= FDI_TX_CTL(pipe
);
1141 val
= I915_READ(reg
);
1142 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1145 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1146 enum pipe pipe
, bool state
)
1152 reg
= FDI_RX_CTL(pipe
);
1153 val
= I915_READ(reg
);
1154 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1155 I915_STATE_WARN(cur_state
!= state
,
1156 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1157 state_string(state
), state_string(cur_state
));
1160 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1163 struct drm_device
*dev
= dev_priv
->dev
;
1166 enum pipe panel_pipe
= PIPE_A
;
1169 if (WARN_ON(HAS_DDI(dev
)))
1172 if (HAS_PCH_SPLIT(dev
)) {
1175 pp_reg
= PCH_PP_CONTROL
;
1176 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1178 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1179 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1180 panel_pipe
= PIPE_B
;
1181 /* XXX: else fix for eDP */
1182 } else if (IS_VALLEYVIEW(dev
)) {
1183 /* presumably write lock depends on pipe, not port select */
1184 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1187 pp_reg
= PP_CONTROL
;
1188 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1189 panel_pipe
= PIPE_B
;
1192 val
= I915_READ(pp_reg
);
1193 if (!(val
& PANEL_POWER_ON
) ||
1194 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1197 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1198 "panel assertion failure, pipe %c regs locked\n",
1202 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1203 enum pipe pipe
, bool state
)
1205 struct drm_device
*dev
= dev_priv
->dev
;
1208 if (IS_845G(dev
) || IS_I865G(dev
))
1209 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1211 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1213 I915_STATE_WARN(cur_state
!= state
,
1214 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1215 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1217 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1218 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1220 void assert_pipe(struct drm_i915_private
*dev_priv
,
1221 enum pipe pipe
, bool state
)
1226 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1229 /* if we need the pipe quirk it must be always on */
1230 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1231 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1234 if (!intel_display_power_is_enabled(dev_priv
,
1235 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1238 reg
= PIPECONF(cpu_transcoder
);
1239 val
= I915_READ(reg
);
1240 cur_state
= !!(val
& PIPECONF_ENABLE
);
1243 I915_STATE_WARN(cur_state
!= state
,
1244 "pipe %c assertion failure (expected %s, current %s)\n",
1245 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1248 static void assert_plane(struct drm_i915_private
*dev_priv
,
1249 enum plane plane
, bool state
)
1255 reg
= DSPCNTR(plane
);
1256 val
= I915_READ(reg
);
1257 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1258 I915_STATE_WARN(cur_state
!= state
,
1259 "plane %c assertion failure (expected %s, current %s)\n",
1260 plane_name(plane
), state_string(state
), state_string(cur_state
));
1263 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1264 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1266 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1269 struct drm_device
*dev
= dev_priv
->dev
;
1274 /* Primary planes are fixed to pipes on gen4+ */
1275 if (INTEL_INFO(dev
)->gen
>= 4) {
1276 reg
= DSPCNTR(pipe
);
1277 val
= I915_READ(reg
);
1278 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1279 "plane %c assertion failure, should be disabled but not\n",
1284 /* Need to check both planes against the pipe */
1285 for_each_pipe(dev_priv
, i
) {
1287 val
= I915_READ(reg
);
1288 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1289 DISPPLANE_SEL_PIPE_SHIFT
;
1290 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1291 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1292 plane_name(i
), pipe_name(pipe
));
1296 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1299 struct drm_device
*dev
= dev_priv
->dev
;
1303 if (INTEL_INFO(dev
)->gen
>= 9) {
1304 for_each_sprite(pipe
, sprite
) {
1305 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1306 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1307 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1308 sprite
, pipe_name(pipe
));
1310 } else if (IS_VALLEYVIEW(dev
)) {
1311 for_each_sprite(pipe
, sprite
) {
1312 reg
= SPCNTR(pipe
, sprite
);
1313 val
= I915_READ(reg
);
1314 I915_STATE_WARN(val
& SP_ENABLE
,
1315 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1316 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1318 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1320 val
= I915_READ(reg
);
1321 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1322 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1323 plane_name(pipe
), pipe_name(pipe
));
1324 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1325 reg
= DVSCNTR(pipe
);
1326 val
= I915_READ(reg
);
1327 I915_STATE_WARN(val
& DVS_ENABLE
,
1328 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1329 plane_name(pipe
), pipe_name(pipe
));
1333 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1335 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1336 drm_crtc_vblank_put(crtc
);
1339 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1344 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1346 val
= I915_READ(PCH_DREF_CONTROL
);
1347 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1348 DREF_SUPERSPREAD_SOURCE_MASK
));
1349 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1352 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1359 reg
= PCH_TRANSCONF(pipe
);
1360 val
= I915_READ(reg
);
1361 enabled
= !!(val
& TRANS_ENABLE
);
1362 I915_STATE_WARN(enabled
,
1363 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1367 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1368 enum pipe pipe
, u32 port_sel
, u32 val
)
1370 if ((val
& DP_PORT_EN
) == 0)
1373 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1374 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1375 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1376 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1378 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1379 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1382 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1388 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1389 enum pipe pipe
, u32 val
)
1391 if ((val
& SDVO_ENABLE
) == 0)
1394 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1395 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1397 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1398 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1401 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1407 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1408 enum pipe pipe
, u32 val
)
1410 if ((val
& LVDS_PORT_EN
) == 0)
1413 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1414 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1417 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1423 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1424 enum pipe pipe
, u32 val
)
1426 if ((val
& ADPA_DAC_ENABLE
) == 0)
1428 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1429 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1432 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1438 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1439 enum pipe pipe
, int reg
, u32 port_sel
)
1441 u32 val
= I915_READ(reg
);
1442 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1443 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1444 reg
, pipe_name(pipe
));
1446 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1447 && (val
& DP_PIPEB_SELECT
),
1448 "IBX PCH dp port still using transcoder B\n");
1451 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1452 enum pipe pipe
, int reg
)
1454 u32 val
= I915_READ(reg
);
1455 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1456 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1457 reg
, pipe_name(pipe
));
1459 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1460 && (val
& SDVO_PIPE_B_SELECT
),
1461 "IBX PCH hdmi port still using transcoder B\n");
1464 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1470 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1471 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1472 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1475 val
= I915_READ(reg
);
1476 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1477 "PCH VGA enabled on transcoder %c, should be disabled\n",
1481 val
= I915_READ(reg
);
1482 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1483 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1487 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1488 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1491 static void intel_init_dpio(struct drm_device
*dev
)
1493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1495 if (!IS_VALLEYVIEW(dev
))
1499 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1500 * CHV x1 PHY (DP/HDMI D)
1501 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1503 if (IS_CHERRYVIEW(dev
)) {
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1505 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1507 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1511 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1512 const struct intel_crtc_state
*pipe_config
)
1514 struct drm_device
*dev
= crtc
->base
.dev
;
1515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1516 int reg
= DPLL(crtc
->pipe
);
1517 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1519 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1521 /* No really, not for ILK+ */
1522 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1524 /* PLL is protected by panel, make sure we can write it */
1525 if (IS_MOBILE(dev_priv
->dev
))
1526 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1528 I915_WRITE(reg
, dpll
);
1532 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1533 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1535 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1536 POSTING_READ(DPLL_MD(crtc
->pipe
));
1538 /* We do this three times for luck */
1539 I915_WRITE(reg
, dpll
);
1541 udelay(150); /* wait for warmup */
1542 I915_WRITE(reg
, dpll
);
1544 udelay(150); /* wait for warmup */
1545 I915_WRITE(reg
, dpll
);
1547 udelay(150); /* wait for warmup */
1550 static void chv_enable_pll(struct intel_crtc
*crtc
,
1551 const struct intel_crtc_state
*pipe_config
)
1553 struct drm_device
*dev
= crtc
->base
.dev
;
1554 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1555 int pipe
= crtc
->pipe
;
1556 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1559 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1561 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1563 mutex_lock(&dev_priv
->dpio_lock
);
1565 /* Enable back the 10bit clock to display controller */
1566 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1567 tmp
|= DPIO_DCLKP_EN
;
1568 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1571 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1576 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1578 /* Check PLL is locked */
1579 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1580 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1582 /* not sure when this should be written */
1583 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1584 POSTING_READ(DPLL_MD(pipe
));
1586 mutex_unlock(&dev_priv
->dpio_lock
);
1589 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1591 struct intel_crtc
*crtc
;
1594 for_each_intel_crtc(dev
, crtc
)
1595 count
+= crtc
->active
&&
1596 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1601 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1603 struct drm_device
*dev
= crtc
->base
.dev
;
1604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1605 int reg
= DPLL(crtc
->pipe
);
1606 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1608 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1610 /* No really, not for ILK+ */
1611 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1613 /* PLL is protected by panel, make sure we can write it */
1614 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1615 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1617 /* Enable DVO 2x clock on both PLLs if necessary */
1618 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1620 * It appears to be important that we don't enable this
1621 * for the current pipe before otherwise configuring the
1622 * PLL. No idea how this should be handled if multiple
1623 * DVO outputs are enabled simultaneosly.
1625 dpll
|= DPLL_DVO_2X_MODE
;
1626 I915_WRITE(DPLL(!crtc
->pipe
),
1627 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1630 /* Wait for the clocks to stabilize. */
1634 if (INTEL_INFO(dev
)->gen
>= 4) {
1635 I915_WRITE(DPLL_MD(crtc
->pipe
),
1636 crtc
->config
->dpll_hw_state
.dpll_md
);
1638 /* The pixel multiplier can only be updated once the
1639 * DPLL is enabled and the clocks are stable.
1641 * So write it again.
1643 I915_WRITE(reg
, dpll
);
1646 /* We do this three times for luck */
1647 I915_WRITE(reg
, dpll
);
1649 udelay(150); /* wait for warmup */
1650 I915_WRITE(reg
, dpll
);
1652 udelay(150); /* wait for warmup */
1653 I915_WRITE(reg
, dpll
);
1655 udelay(150); /* wait for warmup */
1659 * i9xx_disable_pll - disable a PLL
1660 * @dev_priv: i915 private structure
1661 * @pipe: pipe PLL to disable
1663 * Disable the PLL for @pipe, making sure the pipe is off first.
1665 * Note! This is for pre-ILK only.
1667 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1669 struct drm_device
*dev
= crtc
->base
.dev
;
1670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1671 enum pipe pipe
= crtc
->pipe
;
1673 /* Disable DVO 2x clock on both PLLs if necessary */
1675 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1676 intel_num_dvo_pipes(dev
) == 1) {
1677 I915_WRITE(DPLL(PIPE_B
),
1678 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1679 I915_WRITE(DPLL(PIPE_A
),
1680 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1683 /* Don't disable pipe or pipe PLLs if needed */
1684 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1685 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1688 /* Make sure the pipe isn't still relying on us */
1689 assert_pipe_disabled(dev_priv
, pipe
);
1691 I915_WRITE(DPLL(pipe
), 0);
1692 POSTING_READ(DPLL(pipe
));
1695 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1699 /* Make sure the pipe isn't still relying on us */
1700 assert_pipe_disabled(dev_priv
, pipe
);
1703 * Leave integrated clock source and reference clock enabled for pipe B.
1704 * The latter is needed for VGA hotplug / manual detection.
1707 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1708 I915_WRITE(DPLL(pipe
), val
);
1709 POSTING_READ(DPLL(pipe
));
1713 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1715 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1718 /* Make sure the pipe isn't still relying on us */
1719 assert_pipe_disabled(dev_priv
, pipe
);
1721 /* Set PLL en = 0 */
1722 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1724 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1725 I915_WRITE(DPLL(pipe
), val
);
1726 POSTING_READ(DPLL(pipe
));
1728 mutex_lock(&dev_priv
->dpio_lock
);
1730 /* Disable 10bit clock to display controller */
1731 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1732 val
&= ~DPIO_DCLKP_EN
;
1733 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1735 /* disable left/right clock distribution */
1736 if (pipe
!= PIPE_B
) {
1737 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1738 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1739 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1741 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1742 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1743 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1746 mutex_unlock(&dev_priv
->dpio_lock
);
1749 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1750 struct intel_digital_port
*dport
)
1755 switch (dport
->port
) {
1757 port_mask
= DPLL_PORTB_READY_MASK
;
1761 port_mask
= DPLL_PORTC_READY_MASK
;
1765 port_mask
= DPLL_PORTD_READY_MASK
;
1766 dpll_reg
= DPIO_PHY_STATUS
;
1772 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1773 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1774 port_name(dport
->port
), I915_READ(dpll_reg
));
1777 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1779 struct drm_device
*dev
= crtc
->base
.dev
;
1780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1781 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1783 if (WARN_ON(pll
== NULL
))
1786 WARN_ON(!pll
->config
.crtc_mask
);
1787 if (pll
->active
== 0) {
1788 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1790 assert_shared_dpll_disabled(dev_priv
, pll
);
1792 pll
->mode_set(dev_priv
, pll
);
1797 * intel_enable_shared_dpll - enable PCH PLL
1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe PLL to enable
1801 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1802 * drives the transcoder clock.
1804 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1806 struct drm_device
*dev
= crtc
->base
.dev
;
1807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1808 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1810 if (WARN_ON(pll
== NULL
))
1813 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1816 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1817 pll
->name
, pll
->active
, pll
->on
,
1818 crtc
->base
.base
.id
);
1820 if (pll
->active
++) {
1822 assert_shared_dpll_enabled(dev_priv
, pll
);
1827 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1829 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1830 pll
->enable(dev_priv
, pll
);
1834 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1836 struct drm_device
*dev
= crtc
->base
.dev
;
1837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1838 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1840 /* PCH only available on ILK+ */
1841 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1842 if (WARN_ON(pll
== NULL
))
1845 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1848 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1849 pll
->name
, pll
->active
, pll
->on
,
1850 crtc
->base
.base
.id
);
1852 if (WARN_ON(pll
->active
== 0)) {
1853 assert_shared_dpll_disabled(dev_priv
, pll
);
1857 assert_shared_dpll_enabled(dev_priv
, pll
);
1862 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1863 pll
->disable(dev_priv
, pll
);
1866 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1869 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1872 struct drm_device
*dev
= dev_priv
->dev
;
1873 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1874 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1875 uint32_t reg
, val
, pipeconf_val
;
1877 /* PCH only available on ILK+ */
1878 BUG_ON(!HAS_PCH_SPLIT(dev
));
1880 /* Make sure PCH DPLL is enabled */
1881 assert_shared_dpll_enabled(dev_priv
,
1882 intel_crtc_to_shared_dpll(intel_crtc
));
1884 /* FDI must be feeding us bits for PCH ports */
1885 assert_fdi_tx_enabled(dev_priv
, pipe
);
1886 assert_fdi_rx_enabled(dev_priv
, pipe
);
1888 if (HAS_PCH_CPT(dev
)) {
1889 /* Workaround: Set the timing override bit before enabling the
1890 * pch transcoder. */
1891 reg
= TRANS_CHICKEN2(pipe
);
1892 val
= I915_READ(reg
);
1893 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1894 I915_WRITE(reg
, val
);
1897 reg
= PCH_TRANSCONF(pipe
);
1898 val
= I915_READ(reg
);
1899 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1901 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1903 * make the BPC in transcoder be consistent with
1904 * that in pipeconf reg.
1906 val
&= ~PIPECONF_BPC_MASK
;
1907 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1910 val
&= ~TRANS_INTERLACE_MASK
;
1911 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1912 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1913 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1914 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1916 val
|= TRANS_INTERLACED
;
1918 val
|= TRANS_PROGRESSIVE
;
1920 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1921 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1922 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1925 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1926 enum transcoder cpu_transcoder
)
1928 u32 val
, pipeconf_val
;
1930 /* PCH only available on ILK+ */
1931 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
1933 /* FDI must be feeding us bits for PCH ports */
1934 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1935 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1937 /* Workaround: set timing override bit. */
1938 val
= I915_READ(_TRANSA_CHICKEN2
);
1939 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1940 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1943 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1945 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1946 PIPECONF_INTERLACED_ILK
)
1947 val
|= TRANS_INTERLACED
;
1949 val
|= TRANS_PROGRESSIVE
;
1951 I915_WRITE(LPT_TRANSCONF
, val
);
1952 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1953 DRM_ERROR("Failed to enable PCH transcoder\n");
1956 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1959 struct drm_device
*dev
= dev_priv
->dev
;
1962 /* FDI relies on the transcoder */
1963 assert_fdi_tx_disabled(dev_priv
, pipe
);
1964 assert_fdi_rx_disabled(dev_priv
, pipe
);
1966 /* Ports must be off as well */
1967 assert_pch_ports_disabled(dev_priv
, pipe
);
1969 reg
= PCH_TRANSCONF(pipe
);
1970 val
= I915_READ(reg
);
1971 val
&= ~TRANS_ENABLE
;
1972 I915_WRITE(reg
, val
);
1973 /* wait for PCH transcoder off, transcoder state */
1974 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1975 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1977 if (!HAS_PCH_IBX(dev
)) {
1978 /* Workaround: Clear the timing override chicken bit again. */
1979 reg
= TRANS_CHICKEN2(pipe
);
1980 val
= I915_READ(reg
);
1981 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1982 I915_WRITE(reg
, val
);
1986 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1990 val
= I915_READ(LPT_TRANSCONF
);
1991 val
&= ~TRANS_ENABLE
;
1992 I915_WRITE(LPT_TRANSCONF
, val
);
1993 /* wait for PCH transcoder off, transcoder state */
1994 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1995 DRM_ERROR("Failed to disable PCH transcoder\n");
1997 /* Workaround: clear timing override bit. */
1998 val
= I915_READ(_TRANSA_CHICKEN2
);
1999 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2000 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2004 * intel_enable_pipe - enable a pipe, asserting requirements
2005 * @crtc: crtc responsible for the pipe
2007 * Enable @crtc's pipe, making sure that various hardware specific requirements
2008 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2010 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2012 struct drm_device
*dev
= crtc
->base
.dev
;
2013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2014 enum pipe pipe
= crtc
->pipe
;
2015 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2017 enum pipe pch_transcoder
;
2021 assert_planes_disabled(dev_priv
, pipe
);
2022 assert_cursor_disabled(dev_priv
, pipe
);
2023 assert_sprites_disabled(dev_priv
, pipe
);
2025 if (HAS_PCH_LPT(dev_priv
->dev
))
2026 pch_transcoder
= TRANSCODER_A
;
2028 pch_transcoder
= pipe
;
2031 * A pipe without a PLL won't actually be able to drive bits from
2032 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2035 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2036 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2037 assert_dsi_pll_enabled(dev_priv
);
2039 assert_pll_enabled(dev_priv
, pipe
);
2041 if (crtc
->config
->has_pch_encoder
) {
2042 /* if driving the PCH, we need FDI enabled */
2043 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2044 assert_fdi_tx_pll_enabled(dev_priv
,
2045 (enum pipe
) cpu_transcoder
);
2047 /* FIXME: assert CPU port conditions for SNB+ */
2050 reg
= PIPECONF(cpu_transcoder
);
2051 val
= I915_READ(reg
);
2052 if (val
& PIPECONF_ENABLE
) {
2053 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2054 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2058 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2063 * intel_disable_pipe - disable a pipe, asserting requirements
2064 * @crtc: crtc whose pipes is to be disabled
2066 * Disable the pipe of @crtc, making sure that various hardware
2067 * specific requirements are met, if applicable, e.g. plane
2068 * disabled, panel fitter off, etc.
2070 * Will wait until the pipe has shut down before returning.
2072 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2074 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2075 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2076 enum pipe pipe
= crtc
->pipe
;
2081 * Make sure planes won't keep trying to pump pixels to us,
2082 * or we might hang the display.
2084 assert_planes_disabled(dev_priv
, pipe
);
2085 assert_cursor_disabled(dev_priv
, pipe
);
2086 assert_sprites_disabled(dev_priv
, pipe
);
2088 reg
= PIPECONF(cpu_transcoder
);
2089 val
= I915_READ(reg
);
2090 if ((val
& PIPECONF_ENABLE
) == 0)
2094 * Double wide has implications for planes
2095 * so best keep it disabled when not needed.
2097 if (crtc
->config
->double_wide
)
2098 val
&= ~PIPECONF_DOUBLE_WIDE
;
2100 /* Don't disable pipe or pipe PLLs if needed */
2101 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2102 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2103 val
&= ~PIPECONF_ENABLE
;
2105 I915_WRITE(reg
, val
);
2106 if ((val
& PIPECONF_ENABLE
) == 0)
2107 intel_wait_for_pipe_off(crtc
);
2111 * Plane regs are double buffered, going from enabled->disabled needs a
2112 * trigger in order to latch. The display address reg provides this.
2114 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2117 struct drm_device
*dev
= dev_priv
->dev
;
2118 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2120 I915_WRITE(reg
, I915_READ(reg
));
2125 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2126 * @plane: plane to be enabled
2127 * @crtc: crtc for the plane
2129 * Enable @plane on @crtc, making sure that the pipe is running first.
2131 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2132 struct drm_crtc
*crtc
)
2134 struct drm_device
*dev
= plane
->dev
;
2135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2136 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2138 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2139 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2141 if (intel_crtc
->primary_enabled
)
2144 intel_crtc
->primary_enabled
= true;
2146 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2150 * BDW signals flip done immediately if the plane
2151 * is disabled, even if the plane enable is already
2152 * armed to occur at the next vblank :(
2154 if (IS_BROADWELL(dev
))
2155 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2159 * intel_disable_primary_hw_plane - disable the primary hardware plane
2160 * @plane: plane to be disabled
2161 * @crtc: crtc for the plane
2163 * Disable @plane on @crtc, making sure that the pipe is running first.
2165 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2166 struct drm_crtc
*crtc
)
2168 struct drm_device
*dev
= plane
->dev
;
2169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2170 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2172 if (WARN_ON(!intel_crtc
->active
))
2175 if (!intel_crtc
->primary_enabled
)
2178 intel_crtc
->primary_enabled
= false;
2180 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2184 static bool need_vtd_wa(struct drm_device
*dev
)
2186 #ifdef CONFIG_INTEL_IOMMU
2187 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2194 intel_fb_align_height(struct drm_device
*dev
, int height
, unsigned int tiling
)
2198 tile_height
= tiling
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2199 return ALIGN(height
, tile_height
);
2203 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2204 struct drm_framebuffer
*fb
,
2205 struct intel_engine_cs
*pipelined
)
2207 struct drm_device
*dev
= fb
->dev
;
2208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2209 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2213 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2215 switch (obj
->tiling_mode
) {
2216 case I915_TILING_NONE
:
2217 if (INTEL_INFO(dev
)->gen
>= 9)
2218 alignment
= 256 * 1024;
2219 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2220 alignment
= 128 * 1024;
2221 else if (INTEL_INFO(dev
)->gen
>= 4)
2222 alignment
= 4 * 1024;
2224 alignment
= 64 * 1024;
2227 if (INTEL_INFO(dev
)->gen
>= 9)
2228 alignment
= 256 * 1024;
2230 /* pin() will align the object as required by fence */
2235 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2241 /* Note that the w/a also requires 64 PTE of padding following the
2242 * bo. We currently fill all unused PTE with the shadow page and so
2243 * we should always have valid PTE following the scanout preventing
2246 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2247 alignment
= 256 * 1024;
2250 * Global gtt pte registers are special registers which actually forward
2251 * writes to a chunk of system memory. Which means that there is no risk
2252 * that the register values disappear as soon as we call
2253 * intel_runtime_pm_put(), so it is correct to wrap only the
2254 * pin/unpin/fence and not more.
2256 intel_runtime_pm_get(dev_priv
);
2258 dev_priv
->mm
.interruptible
= false;
2259 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2261 goto err_interruptible
;
2263 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2264 * fence, whereas 965+ only requires a fence if using
2265 * framebuffer compression. For simplicity, we always install
2266 * a fence as the cost is not that onerous.
2268 ret
= i915_gem_object_get_fence(obj
);
2272 i915_gem_object_pin_fence(obj
);
2274 dev_priv
->mm
.interruptible
= true;
2275 intel_runtime_pm_put(dev_priv
);
2279 i915_gem_object_unpin_from_display_plane(obj
);
2281 dev_priv
->mm
.interruptible
= true;
2282 intel_runtime_pm_put(dev_priv
);
2286 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2288 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2290 i915_gem_object_unpin_fence(obj
);
2291 i915_gem_object_unpin_from_display_plane(obj
);
2294 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2295 * is assumed to be a power-of-two. */
2296 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2297 unsigned int tiling_mode
,
2301 if (tiling_mode
!= I915_TILING_NONE
) {
2302 unsigned int tile_rows
, tiles
;
2307 tiles
= *x
/ (512/cpp
);
2310 return tile_rows
* pitch
* 8 + tiles
* 4096;
2312 unsigned int offset
;
2314 offset
= *y
* pitch
+ *x
* cpp
;
2316 *x
= (offset
& 4095) / cpp
;
2317 return offset
& -4096;
2321 static int i9xx_format_to_fourcc(int format
)
2324 case DISPPLANE_8BPP
:
2325 return DRM_FORMAT_C8
;
2326 case DISPPLANE_BGRX555
:
2327 return DRM_FORMAT_XRGB1555
;
2328 case DISPPLANE_BGRX565
:
2329 return DRM_FORMAT_RGB565
;
2331 case DISPPLANE_BGRX888
:
2332 return DRM_FORMAT_XRGB8888
;
2333 case DISPPLANE_RGBX888
:
2334 return DRM_FORMAT_XBGR8888
;
2335 case DISPPLANE_BGRX101010
:
2336 return DRM_FORMAT_XRGB2101010
;
2337 case DISPPLANE_RGBX101010
:
2338 return DRM_FORMAT_XBGR2101010
;
2342 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2345 case PLANE_CTL_FORMAT_RGB_565
:
2346 return DRM_FORMAT_RGB565
;
2348 case PLANE_CTL_FORMAT_XRGB_8888
:
2351 return DRM_FORMAT_ABGR8888
;
2353 return DRM_FORMAT_XBGR8888
;
2356 return DRM_FORMAT_ARGB8888
;
2358 return DRM_FORMAT_XRGB8888
;
2360 case PLANE_CTL_FORMAT_XRGB_2101010
:
2362 return DRM_FORMAT_XBGR2101010
;
2364 return DRM_FORMAT_XRGB2101010
;
2369 intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2370 struct intel_initial_plane_config
*plane_config
)
2372 struct drm_device
*dev
= crtc
->base
.dev
;
2373 struct drm_i915_gem_object
*obj
= NULL
;
2374 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2375 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2376 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2379 size_aligned
-= base_aligned
;
2381 if (plane_config
->size
== 0)
2384 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2391 obj
->tiling_mode
= plane_config
->tiling
;
2392 if (obj
->tiling_mode
== I915_TILING_X
)
2393 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2395 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2396 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2397 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2398 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2400 mutex_lock(&dev
->struct_mutex
);
2402 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2404 DRM_DEBUG_KMS("intel fb init failed\n");
2408 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2409 mutex_unlock(&dev
->struct_mutex
);
2411 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2415 drm_gem_object_unreference(&obj
->base
);
2416 mutex_unlock(&dev
->struct_mutex
);
2420 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2422 update_state_fb(struct drm_plane
*plane
)
2424 if (plane
->fb
!= plane
->state
->fb
)
2425 drm_atomic_set_fb_for_plane(plane
->state
, plane
->fb
);
2429 intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2430 struct intel_initial_plane_config
*plane_config
)
2432 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2435 struct intel_crtc
*i
;
2436 struct drm_i915_gem_object
*obj
;
2438 if (!intel_crtc
->base
.primary
->fb
)
2441 if (intel_alloc_plane_obj(intel_crtc
, plane_config
)) {
2442 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2444 primary
->state
->crtc
= &intel_crtc
->base
;
2445 primary
->crtc
= &intel_crtc
->base
;
2446 update_state_fb(primary
);
2451 kfree(intel_crtc
->base
.primary
->fb
);
2452 intel_crtc
->base
.primary
->fb
= NULL
;
2455 * Failed to alloc the obj, check to see if we should share
2456 * an fb with another CRTC instead
2458 for_each_crtc(dev
, c
) {
2459 i
= to_intel_crtc(c
);
2461 if (c
== &intel_crtc
->base
)
2467 obj
= intel_fb_obj(c
->primary
->fb
);
2471 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2472 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2474 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2475 dev_priv
->preserve_bios_swizzle
= true;
2477 drm_framebuffer_reference(c
->primary
->fb
);
2478 primary
->fb
= c
->primary
->fb
;
2479 primary
->state
->crtc
= &intel_crtc
->base
;
2480 primary
->crtc
= &intel_crtc
->base
;
2481 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2486 update_state_fb(intel_crtc
->base
.primary
);
2489 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2490 struct drm_framebuffer
*fb
,
2493 struct drm_device
*dev
= crtc
->dev
;
2494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2495 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2496 struct drm_i915_gem_object
*obj
;
2497 int plane
= intel_crtc
->plane
;
2498 unsigned long linear_offset
;
2500 u32 reg
= DSPCNTR(plane
);
2503 if (!intel_crtc
->primary_enabled
) {
2505 if (INTEL_INFO(dev
)->gen
>= 4)
2506 I915_WRITE(DSPSURF(plane
), 0);
2508 I915_WRITE(DSPADDR(plane
), 0);
2513 obj
= intel_fb_obj(fb
);
2514 if (WARN_ON(obj
== NULL
))
2517 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2519 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2521 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2523 if (INTEL_INFO(dev
)->gen
< 4) {
2524 if (intel_crtc
->pipe
== PIPE_B
)
2525 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2527 /* pipesrc and dspsize control the size that is scaled from,
2528 * which should always be the user's requested size.
2530 I915_WRITE(DSPSIZE(plane
),
2531 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2532 (intel_crtc
->config
->pipe_src_w
- 1));
2533 I915_WRITE(DSPPOS(plane
), 0);
2534 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2535 I915_WRITE(PRIMSIZE(plane
),
2536 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2537 (intel_crtc
->config
->pipe_src_w
- 1));
2538 I915_WRITE(PRIMPOS(plane
), 0);
2539 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2542 switch (fb
->pixel_format
) {
2544 dspcntr
|= DISPPLANE_8BPP
;
2546 case DRM_FORMAT_XRGB1555
:
2547 case DRM_FORMAT_ARGB1555
:
2548 dspcntr
|= DISPPLANE_BGRX555
;
2550 case DRM_FORMAT_RGB565
:
2551 dspcntr
|= DISPPLANE_BGRX565
;
2553 case DRM_FORMAT_XRGB8888
:
2554 case DRM_FORMAT_ARGB8888
:
2555 dspcntr
|= DISPPLANE_BGRX888
;
2557 case DRM_FORMAT_XBGR8888
:
2558 case DRM_FORMAT_ABGR8888
:
2559 dspcntr
|= DISPPLANE_RGBX888
;
2561 case DRM_FORMAT_XRGB2101010
:
2562 case DRM_FORMAT_ARGB2101010
:
2563 dspcntr
|= DISPPLANE_BGRX101010
;
2565 case DRM_FORMAT_XBGR2101010
:
2566 case DRM_FORMAT_ABGR2101010
:
2567 dspcntr
|= DISPPLANE_RGBX101010
;
2573 if (INTEL_INFO(dev
)->gen
>= 4 &&
2574 obj
->tiling_mode
!= I915_TILING_NONE
)
2575 dspcntr
|= DISPPLANE_TILED
;
2578 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2580 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2582 if (INTEL_INFO(dev
)->gen
>= 4) {
2583 intel_crtc
->dspaddr_offset
=
2584 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2587 linear_offset
-= intel_crtc
->dspaddr_offset
;
2589 intel_crtc
->dspaddr_offset
= linear_offset
;
2592 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2593 dspcntr
|= DISPPLANE_ROTATE_180
;
2595 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2596 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2598 /* Finding the last pixel of the last line of the display
2599 data and adding to linear_offset*/
2601 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2602 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2605 I915_WRITE(reg
, dspcntr
);
2607 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2608 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2610 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2611 if (INTEL_INFO(dev
)->gen
>= 4) {
2612 I915_WRITE(DSPSURF(plane
),
2613 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2614 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2615 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2617 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2621 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2622 struct drm_framebuffer
*fb
,
2625 struct drm_device
*dev
= crtc
->dev
;
2626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2627 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2628 struct drm_i915_gem_object
*obj
;
2629 int plane
= intel_crtc
->plane
;
2630 unsigned long linear_offset
;
2632 u32 reg
= DSPCNTR(plane
);
2635 if (!intel_crtc
->primary_enabled
) {
2637 I915_WRITE(DSPSURF(plane
), 0);
2642 obj
= intel_fb_obj(fb
);
2643 if (WARN_ON(obj
== NULL
))
2646 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2648 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2650 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2652 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2653 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2655 switch (fb
->pixel_format
) {
2657 dspcntr
|= DISPPLANE_8BPP
;
2659 case DRM_FORMAT_RGB565
:
2660 dspcntr
|= DISPPLANE_BGRX565
;
2662 case DRM_FORMAT_XRGB8888
:
2663 case DRM_FORMAT_ARGB8888
:
2664 dspcntr
|= DISPPLANE_BGRX888
;
2666 case DRM_FORMAT_XBGR8888
:
2667 case DRM_FORMAT_ABGR8888
:
2668 dspcntr
|= DISPPLANE_RGBX888
;
2670 case DRM_FORMAT_XRGB2101010
:
2671 case DRM_FORMAT_ARGB2101010
:
2672 dspcntr
|= DISPPLANE_BGRX101010
;
2674 case DRM_FORMAT_XBGR2101010
:
2675 case DRM_FORMAT_ABGR2101010
:
2676 dspcntr
|= DISPPLANE_RGBX101010
;
2682 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2683 dspcntr
|= DISPPLANE_TILED
;
2685 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2686 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2688 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2689 intel_crtc
->dspaddr_offset
=
2690 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2693 linear_offset
-= intel_crtc
->dspaddr_offset
;
2694 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2695 dspcntr
|= DISPPLANE_ROTATE_180
;
2697 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2698 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2699 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2701 /* Finding the last pixel of the last line of the display
2702 data and adding to linear_offset*/
2704 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2705 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2709 I915_WRITE(reg
, dspcntr
);
2711 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2712 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2714 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2715 I915_WRITE(DSPSURF(plane
),
2716 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2717 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2718 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2720 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2721 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2726 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
2727 struct drm_framebuffer
*fb
,
2730 struct drm_device
*dev
= crtc
->dev
;
2731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2732 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2733 struct intel_framebuffer
*intel_fb
;
2734 struct drm_i915_gem_object
*obj
;
2735 int pipe
= intel_crtc
->pipe
;
2736 u32 plane_ctl
, stride
;
2738 if (!intel_crtc
->primary_enabled
) {
2739 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
2740 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
2741 POSTING_READ(PLANE_CTL(pipe
, 0));
2745 plane_ctl
= PLANE_CTL_ENABLE
|
2746 PLANE_CTL_PIPE_GAMMA_ENABLE
|
2747 PLANE_CTL_PIPE_CSC_ENABLE
;
2749 switch (fb
->pixel_format
) {
2750 case DRM_FORMAT_RGB565
:
2751 plane_ctl
|= PLANE_CTL_FORMAT_RGB_565
;
2753 case DRM_FORMAT_XRGB8888
:
2754 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2756 case DRM_FORMAT_ARGB8888
:
2757 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2758 plane_ctl
|= PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2760 case DRM_FORMAT_XBGR8888
:
2761 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2762 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2764 case DRM_FORMAT_ABGR8888
:
2765 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2766 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2767 plane_ctl
|= PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2769 case DRM_FORMAT_XRGB2101010
:
2770 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2772 case DRM_FORMAT_XBGR2101010
:
2773 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2774 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2780 intel_fb
= to_intel_framebuffer(fb
);
2781 obj
= intel_fb
->obj
;
2784 * The stride is either expressed as a multiple of 64 bytes chunks for
2785 * linear buffers or in number of tiles for tiled buffers.
2787 switch (obj
->tiling_mode
) {
2788 case I915_TILING_NONE
:
2789 stride
= fb
->pitches
[0] >> 6;
2792 plane_ctl
|= PLANE_CTL_TILED_X
;
2793 stride
= fb
->pitches
[0] >> 9;
2799 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
2800 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
))
2801 plane_ctl
|= PLANE_CTL_ROTATE_180
;
2803 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
2805 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2806 i915_gem_obj_ggtt_offset(obj
),
2807 x
, y
, fb
->width
, fb
->height
,
2810 I915_WRITE(PLANE_POS(pipe
, 0), 0);
2811 I915_WRITE(PLANE_OFFSET(pipe
, 0), (y
<< 16) | x
);
2812 I915_WRITE(PLANE_SIZE(pipe
, 0),
2813 (intel_crtc
->config
->pipe_src_h
- 1) << 16 |
2814 (intel_crtc
->config
->pipe_src_w
- 1));
2815 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
2816 I915_WRITE(PLANE_SURF(pipe
, 0), i915_gem_obj_ggtt_offset(obj
));
2818 POSTING_READ(PLANE_SURF(pipe
, 0));
2821 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2823 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2824 int x
, int y
, enum mode_set_atomic state
)
2826 struct drm_device
*dev
= crtc
->dev
;
2827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2829 if (dev_priv
->display
.disable_fbc
)
2830 dev_priv
->display
.disable_fbc(dev
);
2832 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2837 static void intel_complete_page_flips(struct drm_device
*dev
)
2839 struct drm_crtc
*crtc
;
2841 for_each_crtc(dev
, crtc
) {
2842 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2843 enum plane plane
= intel_crtc
->plane
;
2845 intel_prepare_page_flip(dev
, plane
);
2846 intel_finish_page_flip_plane(dev
, plane
);
2850 static void intel_update_primary_planes(struct drm_device
*dev
)
2852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2853 struct drm_crtc
*crtc
;
2855 for_each_crtc(dev
, crtc
) {
2856 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2858 drm_modeset_lock(&crtc
->mutex
, NULL
);
2860 * FIXME: Once we have proper support for primary planes (and
2861 * disabling them without disabling the entire crtc) allow again
2862 * a NULL crtc->primary->fb.
2864 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2865 dev_priv
->display
.update_primary_plane(crtc
,
2869 drm_modeset_unlock(&crtc
->mutex
);
2873 void intel_prepare_reset(struct drm_device
*dev
)
2875 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2876 struct intel_crtc
*crtc
;
2878 /* no reset support for gen2 */
2882 /* reset doesn't touch the display */
2883 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
2886 drm_modeset_lock_all(dev
);
2889 * Disabling the crtcs gracefully seems nicer. Also the
2890 * g33 docs say we should at least disable all the planes.
2892 for_each_intel_crtc(dev
, crtc
) {
2894 dev_priv
->display
.crtc_disable(&crtc
->base
);
2898 void intel_finish_reset(struct drm_device
*dev
)
2900 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2903 * Flips in the rings will be nuked by the reset,
2904 * so complete all pending flips so that user space
2905 * will get its events and not get stuck.
2907 intel_complete_page_flips(dev
);
2909 /* no reset support for gen2 */
2913 /* reset doesn't touch the display */
2914 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
2916 * Flips in the rings have been nuked by the reset,
2917 * so update the base address of all primary
2918 * planes to the the last fb to make sure we're
2919 * showing the correct fb after a reset.
2921 intel_update_primary_planes(dev
);
2926 * The display has been reset as well,
2927 * so need a full re-initialization.
2929 intel_runtime_pm_disable_interrupts(dev_priv
);
2930 intel_runtime_pm_enable_interrupts(dev_priv
);
2932 intel_modeset_init_hw(dev
);
2934 spin_lock_irq(&dev_priv
->irq_lock
);
2935 if (dev_priv
->display
.hpd_irq_setup
)
2936 dev_priv
->display
.hpd_irq_setup(dev
);
2937 spin_unlock_irq(&dev_priv
->irq_lock
);
2939 intel_modeset_setup_hw_state(dev
, true);
2941 intel_hpd_init(dev_priv
);
2943 drm_modeset_unlock_all(dev
);
2947 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2949 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2950 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2951 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2954 /* Big Hammer, we also need to ensure that any pending
2955 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2956 * current scanout is retired before unpinning the old
2959 * This should only fail upon a hung GPU, in which case we
2960 * can safely continue.
2962 dev_priv
->mm
.interruptible
= false;
2963 ret
= i915_gem_object_finish_gpu(obj
);
2964 dev_priv
->mm
.interruptible
= was_interruptible
;
2969 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2971 struct drm_device
*dev
= crtc
->dev
;
2972 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2973 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2976 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2977 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2980 spin_lock_irq(&dev
->event_lock
);
2981 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2982 spin_unlock_irq(&dev
->event_lock
);
2987 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
2989 struct drm_device
*dev
= crtc
->base
.dev
;
2990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2991 const struct drm_display_mode
*adjusted_mode
;
2997 * Update pipe size and adjust fitter if needed: the reason for this is
2998 * that in compute_mode_changes we check the native mode (not the pfit
2999 * mode) to see if we can flip rather than do a full mode set. In the
3000 * fastboot case, we'll flip, but if we don't update the pipesrc and
3001 * pfit state, we'll end up with a big fb scanned out into the wrong
3004 * To fix this properly, we need to hoist the checks up into
3005 * compute_mode_changes (or above), check the actual pfit state and
3006 * whether the platform allows pfit disable with pipe active, and only
3007 * then update the pipesrc and pfit state, even on the flip path.
3010 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
3012 I915_WRITE(PIPESRC(crtc
->pipe
),
3013 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
3014 (adjusted_mode
->crtc_vdisplay
- 1));
3015 if (!crtc
->config
->pch_pfit
.enabled
&&
3016 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3017 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3018 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
3019 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
3020 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
3022 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
3023 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
3026 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3028 struct drm_device
*dev
= crtc
->dev
;
3029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3030 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3031 int pipe
= intel_crtc
->pipe
;
3034 /* enable normal train */
3035 reg
= FDI_TX_CTL(pipe
);
3036 temp
= I915_READ(reg
);
3037 if (IS_IVYBRIDGE(dev
)) {
3038 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3039 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3041 temp
&= ~FDI_LINK_TRAIN_NONE
;
3042 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3044 I915_WRITE(reg
, temp
);
3046 reg
= FDI_RX_CTL(pipe
);
3047 temp
= I915_READ(reg
);
3048 if (HAS_PCH_CPT(dev
)) {
3049 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3050 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3052 temp
&= ~FDI_LINK_TRAIN_NONE
;
3053 temp
|= FDI_LINK_TRAIN_NONE
;
3055 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3057 /* wait one idle pattern time */
3061 /* IVB wants error correction enabled */
3062 if (IS_IVYBRIDGE(dev
))
3063 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3064 FDI_FE_ERRC_ENABLE
);
3067 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
3069 return crtc
->base
.enabled
&& crtc
->active
&&
3070 crtc
->config
->has_pch_encoder
;
3073 static void ivb_modeset_global_resources(struct drm_device
*dev
)
3075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3076 struct intel_crtc
*pipe_B_crtc
=
3077 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
3078 struct intel_crtc
*pipe_C_crtc
=
3079 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
3083 * When everything is off disable fdi C so that we could enable fdi B
3084 * with all lanes. Note that we don't care about enabled pipes without
3085 * an enabled pch encoder.
3087 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
3088 !pipe_has_enabled_pch(pipe_C_crtc
)) {
3089 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3090 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3092 temp
= I915_READ(SOUTH_CHICKEN1
);
3093 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
3094 DRM_DEBUG_KMS("disabling fdi C rx\n");
3095 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3099 /* The FDI link training functions for ILK/Ibexpeak. */
3100 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3102 struct drm_device
*dev
= crtc
->dev
;
3103 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3104 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3105 int pipe
= intel_crtc
->pipe
;
3106 u32 reg
, temp
, tries
;
3108 /* FDI needs bits from pipe first */
3109 assert_pipe_enabled(dev_priv
, pipe
);
3111 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3113 reg
= FDI_RX_IMR(pipe
);
3114 temp
= I915_READ(reg
);
3115 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3116 temp
&= ~FDI_RX_BIT_LOCK
;
3117 I915_WRITE(reg
, temp
);
3121 /* enable CPU FDI TX and PCH FDI RX */
3122 reg
= FDI_TX_CTL(pipe
);
3123 temp
= I915_READ(reg
);
3124 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3125 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3126 temp
&= ~FDI_LINK_TRAIN_NONE
;
3127 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3128 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3130 reg
= FDI_RX_CTL(pipe
);
3131 temp
= I915_READ(reg
);
3132 temp
&= ~FDI_LINK_TRAIN_NONE
;
3133 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3134 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3139 /* Ironlake workaround, enable clock pointer after FDI enable*/
3140 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3141 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3142 FDI_RX_PHASE_SYNC_POINTER_EN
);
3144 reg
= FDI_RX_IIR(pipe
);
3145 for (tries
= 0; tries
< 5; tries
++) {
3146 temp
= I915_READ(reg
);
3147 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3149 if ((temp
& FDI_RX_BIT_LOCK
)) {
3150 DRM_DEBUG_KMS("FDI train 1 done.\n");
3151 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3156 DRM_ERROR("FDI train 1 fail!\n");
3159 reg
= FDI_TX_CTL(pipe
);
3160 temp
= I915_READ(reg
);
3161 temp
&= ~FDI_LINK_TRAIN_NONE
;
3162 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3163 I915_WRITE(reg
, temp
);
3165 reg
= FDI_RX_CTL(pipe
);
3166 temp
= I915_READ(reg
);
3167 temp
&= ~FDI_LINK_TRAIN_NONE
;
3168 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3169 I915_WRITE(reg
, temp
);
3174 reg
= FDI_RX_IIR(pipe
);
3175 for (tries
= 0; tries
< 5; tries
++) {
3176 temp
= I915_READ(reg
);
3177 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3179 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3180 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3181 DRM_DEBUG_KMS("FDI train 2 done.\n");
3186 DRM_ERROR("FDI train 2 fail!\n");
3188 DRM_DEBUG_KMS("FDI train done\n");
3192 static const int snb_b_fdi_train_param
[] = {
3193 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3194 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3195 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3196 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3199 /* The FDI link training functions for SNB/Cougarpoint. */
3200 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3202 struct drm_device
*dev
= crtc
->dev
;
3203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3204 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3205 int pipe
= intel_crtc
->pipe
;
3206 u32 reg
, temp
, i
, retry
;
3208 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3210 reg
= FDI_RX_IMR(pipe
);
3211 temp
= I915_READ(reg
);
3212 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3213 temp
&= ~FDI_RX_BIT_LOCK
;
3214 I915_WRITE(reg
, temp
);
3219 /* enable CPU FDI TX and PCH FDI RX */
3220 reg
= FDI_TX_CTL(pipe
);
3221 temp
= I915_READ(reg
);
3222 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3223 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3224 temp
&= ~FDI_LINK_TRAIN_NONE
;
3225 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3226 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3228 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3229 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3231 I915_WRITE(FDI_RX_MISC(pipe
),
3232 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3234 reg
= FDI_RX_CTL(pipe
);
3235 temp
= I915_READ(reg
);
3236 if (HAS_PCH_CPT(dev
)) {
3237 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3238 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3240 temp
&= ~FDI_LINK_TRAIN_NONE
;
3241 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3243 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3248 for (i
= 0; i
< 4; i
++) {
3249 reg
= FDI_TX_CTL(pipe
);
3250 temp
= I915_READ(reg
);
3251 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3252 temp
|= snb_b_fdi_train_param
[i
];
3253 I915_WRITE(reg
, temp
);
3258 for (retry
= 0; retry
< 5; retry
++) {
3259 reg
= FDI_RX_IIR(pipe
);
3260 temp
= I915_READ(reg
);
3261 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3262 if (temp
& FDI_RX_BIT_LOCK
) {
3263 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3264 DRM_DEBUG_KMS("FDI train 1 done.\n");
3273 DRM_ERROR("FDI train 1 fail!\n");
3276 reg
= FDI_TX_CTL(pipe
);
3277 temp
= I915_READ(reg
);
3278 temp
&= ~FDI_LINK_TRAIN_NONE
;
3279 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3281 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3283 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3285 I915_WRITE(reg
, temp
);
3287 reg
= FDI_RX_CTL(pipe
);
3288 temp
= I915_READ(reg
);
3289 if (HAS_PCH_CPT(dev
)) {
3290 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3291 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3293 temp
&= ~FDI_LINK_TRAIN_NONE
;
3294 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3296 I915_WRITE(reg
, temp
);
3301 for (i
= 0; i
< 4; i
++) {
3302 reg
= FDI_TX_CTL(pipe
);
3303 temp
= I915_READ(reg
);
3304 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3305 temp
|= snb_b_fdi_train_param
[i
];
3306 I915_WRITE(reg
, temp
);
3311 for (retry
= 0; retry
< 5; retry
++) {
3312 reg
= FDI_RX_IIR(pipe
);
3313 temp
= I915_READ(reg
);
3314 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3315 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3316 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3317 DRM_DEBUG_KMS("FDI train 2 done.\n");
3326 DRM_ERROR("FDI train 2 fail!\n");
3328 DRM_DEBUG_KMS("FDI train done.\n");
3331 /* Manual link training for Ivy Bridge A0 parts */
3332 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3334 struct drm_device
*dev
= crtc
->dev
;
3335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3336 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3337 int pipe
= intel_crtc
->pipe
;
3338 u32 reg
, temp
, i
, j
;
3340 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3342 reg
= FDI_RX_IMR(pipe
);
3343 temp
= I915_READ(reg
);
3344 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3345 temp
&= ~FDI_RX_BIT_LOCK
;
3346 I915_WRITE(reg
, temp
);
3351 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3352 I915_READ(FDI_RX_IIR(pipe
)));
3354 /* Try each vswing and preemphasis setting twice before moving on */
3355 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3356 /* disable first in case we need to retry */
3357 reg
= FDI_TX_CTL(pipe
);
3358 temp
= I915_READ(reg
);
3359 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3360 temp
&= ~FDI_TX_ENABLE
;
3361 I915_WRITE(reg
, temp
);
3363 reg
= FDI_RX_CTL(pipe
);
3364 temp
= I915_READ(reg
);
3365 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3366 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3367 temp
&= ~FDI_RX_ENABLE
;
3368 I915_WRITE(reg
, temp
);
3370 /* enable CPU FDI TX and PCH FDI RX */
3371 reg
= FDI_TX_CTL(pipe
);
3372 temp
= I915_READ(reg
);
3373 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3374 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3375 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3376 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3377 temp
|= snb_b_fdi_train_param
[j
/2];
3378 temp
|= FDI_COMPOSITE_SYNC
;
3379 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3381 I915_WRITE(FDI_RX_MISC(pipe
),
3382 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3384 reg
= FDI_RX_CTL(pipe
);
3385 temp
= I915_READ(reg
);
3386 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3387 temp
|= FDI_COMPOSITE_SYNC
;
3388 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3391 udelay(1); /* should be 0.5us */
3393 for (i
= 0; i
< 4; i
++) {
3394 reg
= FDI_RX_IIR(pipe
);
3395 temp
= I915_READ(reg
);
3396 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3398 if (temp
& FDI_RX_BIT_LOCK
||
3399 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3400 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3401 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3405 udelay(1); /* should be 0.5us */
3408 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3413 reg
= FDI_TX_CTL(pipe
);
3414 temp
= I915_READ(reg
);
3415 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3416 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3417 I915_WRITE(reg
, temp
);
3419 reg
= FDI_RX_CTL(pipe
);
3420 temp
= I915_READ(reg
);
3421 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3422 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3423 I915_WRITE(reg
, temp
);
3426 udelay(2); /* should be 1.5us */
3428 for (i
= 0; i
< 4; i
++) {
3429 reg
= FDI_RX_IIR(pipe
);
3430 temp
= I915_READ(reg
);
3431 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3433 if (temp
& FDI_RX_SYMBOL_LOCK
||
3434 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3435 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3436 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3440 udelay(2); /* should be 1.5us */
3443 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3447 DRM_DEBUG_KMS("FDI train done.\n");
3450 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3452 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3454 int pipe
= intel_crtc
->pipe
;
3458 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3459 reg
= FDI_RX_CTL(pipe
);
3460 temp
= I915_READ(reg
);
3461 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3462 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3463 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3464 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3469 /* Switch from Rawclk to PCDclk */
3470 temp
= I915_READ(reg
);
3471 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3476 /* Enable CPU FDI TX PLL, always on for Ironlake */
3477 reg
= FDI_TX_CTL(pipe
);
3478 temp
= I915_READ(reg
);
3479 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3480 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3487 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3489 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3490 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3491 int pipe
= intel_crtc
->pipe
;
3494 /* Switch from PCDclk to Rawclk */
3495 reg
= FDI_RX_CTL(pipe
);
3496 temp
= I915_READ(reg
);
3497 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3499 /* Disable CPU FDI TX PLL */
3500 reg
= FDI_TX_CTL(pipe
);
3501 temp
= I915_READ(reg
);
3502 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3507 reg
= FDI_RX_CTL(pipe
);
3508 temp
= I915_READ(reg
);
3509 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3511 /* Wait for the clocks to turn off. */
3516 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3518 struct drm_device
*dev
= crtc
->dev
;
3519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3520 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3521 int pipe
= intel_crtc
->pipe
;
3524 /* disable CPU FDI tx and PCH FDI rx */
3525 reg
= FDI_TX_CTL(pipe
);
3526 temp
= I915_READ(reg
);
3527 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3530 reg
= FDI_RX_CTL(pipe
);
3531 temp
= I915_READ(reg
);
3532 temp
&= ~(0x7 << 16);
3533 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3534 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3539 /* Ironlake workaround, disable clock pointer after downing FDI */
3540 if (HAS_PCH_IBX(dev
))
3541 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3543 /* still set train pattern 1 */
3544 reg
= FDI_TX_CTL(pipe
);
3545 temp
= I915_READ(reg
);
3546 temp
&= ~FDI_LINK_TRAIN_NONE
;
3547 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3548 I915_WRITE(reg
, temp
);
3550 reg
= FDI_RX_CTL(pipe
);
3551 temp
= I915_READ(reg
);
3552 if (HAS_PCH_CPT(dev
)) {
3553 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3554 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3556 temp
&= ~FDI_LINK_TRAIN_NONE
;
3557 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3559 /* BPC in FDI rx is consistent with that in PIPECONF */
3560 temp
&= ~(0x07 << 16);
3561 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3562 I915_WRITE(reg
, temp
);
3568 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3570 struct intel_crtc
*crtc
;
3572 /* Note that we don't need to be called with mode_config.lock here
3573 * as our list of CRTC objects is static for the lifetime of the
3574 * device and so cannot disappear as we iterate. Similarly, we can
3575 * happily treat the predicates as racy, atomic checks as userspace
3576 * cannot claim and pin a new fb without at least acquring the
3577 * struct_mutex and so serialising with us.
3579 for_each_intel_crtc(dev
, crtc
) {
3580 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3583 if (crtc
->unpin_work
)
3584 intel_wait_for_vblank(dev
, crtc
->pipe
);
3592 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3594 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3595 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3597 /* ensure that the unpin work is consistent wrt ->pending. */
3599 intel_crtc
->unpin_work
= NULL
;
3602 drm_send_vblank_event(intel_crtc
->base
.dev
,
3606 drm_crtc_vblank_put(&intel_crtc
->base
);
3608 wake_up_all(&dev_priv
->pending_flip_queue
);
3609 queue_work(dev_priv
->wq
, &work
->work
);
3611 trace_i915_flip_complete(intel_crtc
->plane
,
3612 work
->pending_flip_obj
);
3615 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3617 struct drm_device
*dev
= crtc
->dev
;
3618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3620 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3621 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3622 !intel_crtc_has_pending_flip(crtc
),
3624 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3626 spin_lock_irq(&dev
->event_lock
);
3627 if (intel_crtc
->unpin_work
) {
3628 WARN_ONCE(1, "Removing stuck page flip\n");
3629 page_flip_completed(intel_crtc
);
3631 spin_unlock_irq(&dev
->event_lock
);
3634 if (crtc
->primary
->fb
) {
3635 mutex_lock(&dev
->struct_mutex
);
3636 intel_finish_fb(crtc
->primary
->fb
);
3637 mutex_unlock(&dev
->struct_mutex
);
3641 /* Program iCLKIP clock to the desired frequency */
3642 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3644 struct drm_device
*dev
= crtc
->dev
;
3645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3646 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3647 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3650 mutex_lock(&dev_priv
->dpio_lock
);
3652 /* It is necessary to ungate the pixclk gate prior to programming
3653 * the divisors, and gate it back when it is done.
3655 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3657 /* Disable SSCCTL */
3658 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3659 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3663 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3664 if (clock
== 20000) {
3669 /* The iCLK virtual clock root frequency is in MHz,
3670 * but the adjusted_mode->crtc_clock in in KHz. To get the
3671 * divisors, it is necessary to divide one by another, so we
3672 * convert the virtual clock precision to KHz here for higher
3675 u32 iclk_virtual_root_freq
= 172800 * 1000;
3676 u32 iclk_pi_range
= 64;
3677 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3679 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3680 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3681 pi_value
= desired_divisor
% iclk_pi_range
;
3684 divsel
= msb_divisor_value
- 2;
3685 phaseinc
= pi_value
;
3688 /* This should not happen with any sane values */
3689 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3690 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3691 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3692 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3694 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3701 /* Program SSCDIVINTPHASE6 */
3702 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3703 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3704 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3705 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3706 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3707 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3708 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3709 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3711 /* Program SSCAUXDIV */
3712 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3713 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3714 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3715 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3717 /* Enable modulator and associated divider */
3718 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3719 temp
&= ~SBI_SSCCTL_DISABLE
;
3720 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3722 /* Wait for initialization time */
3725 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3727 mutex_unlock(&dev_priv
->dpio_lock
);
3730 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3731 enum pipe pch_transcoder
)
3733 struct drm_device
*dev
= crtc
->base
.dev
;
3734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3735 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
3737 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3738 I915_READ(HTOTAL(cpu_transcoder
)));
3739 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3740 I915_READ(HBLANK(cpu_transcoder
)));
3741 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3742 I915_READ(HSYNC(cpu_transcoder
)));
3744 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3745 I915_READ(VTOTAL(cpu_transcoder
)));
3746 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3747 I915_READ(VBLANK(cpu_transcoder
)));
3748 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3749 I915_READ(VSYNC(cpu_transcoder
)));
3750 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3751 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3754 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3759 temp
= I915_READ(SOUTH_CHICKEN1
);
3760 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3763 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3764 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3766 temp
|= FDI_BC_BIFURCATION_SELECT
;
3767 DRM_DEBUG_KMS("enabling fdi C rx\n");
3768 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3769 POSTING_READ(SOUTH_CHICKEN1
);
3772 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3774 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3777 switch (intel_crtc
->pipe
) {
3781 if (intel_crtc
->config
->fdi_lanes
> 2)
3782 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3784 cpt_enable_fdi_bc_bifurcation(dev
);
3788 cpt_enable_fdi_bc_bifurcation(dev
);
3797 * Enable PCH resources required for PCH ports:
3799 * - FDI training & RX/TX
3800 * - update transcoder timings
3801 * - DP transcoding bits
3804 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3806 struct drm_device
*dev
= crtc
->dev
;
3807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3808 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3809 int pipe
= intel_crtc
->pipe
;
3812 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3814 if (IS_IVYBRIDGE(dev
))
3815 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3817 /* Write the TU size bits before fdi link training, so that error
3818 * detection works. */
3819 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3820 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3822 /* For PCH output, training FDI link */
3823 dev_priv
->display
.fdi_link_train(crtc
);
3825 /* We need to program the right clock selection before writing the pixel
3826 * mutliplier into the DPLL. */
3827 if (HAS_PCH_CPT(dev
)) {
3830 temp
= I915_READ(PCH_DPLL_SEL
);
3831 temp
|= TRANS_DPLL_ENABLE(pipe
);
3832 sel
= TRANS_DPLLB_SEL(pipe
);
3833 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
3837 I915_WRITE(PCH_DPLL_SEL
, temp
);
3840 /* XXX: pch pll's can be enabled any time before we enable the PCH
3841 * transcoder, and we actually should do this to not upset any PCH
3842 * transcoder that already use the clock when we share it.
3844 * Note that enable_shared_dpll tries to do the right thing, but
3845 * get_shared_dpll unconditionally resets the pll - we need that to have
3846 * the right LVDS enable sequence. */
3847 intel_enable_shared_dpll(intel_crtc
);
3849 /* set transcoder timing, panel must allow it */
3850 assert_panel_unlocked(dev_priv
, pipe
);
3851 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3853 intel_fdi_normal_train(crtc
);
3855 /* For PCH DP, enable TRANS_DP_CTL */
3856 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
3857 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3858 reg
= TRANS_DP_CTL(pipe
);
3859 temp
= I915_READ(reg
);
3860 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3861 TRANS_DP_SYNC_MASK
|
3863 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3864 TRANS_DP_ENH_FRAMING
);
3865 temp
|= bpc
<< 9; /* same format but at 11:9 */
3867 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3868 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3869 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3870 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3872 switch (intel_trans_dp_port_sel(crtc
)) {
3874 temp
|= TRANS_DP_PORT_SEL_B
;
3877 temp
|= TRANS_DP_PORT_SEL_C
;
3880 temp
|= TRANS_DP_PORT_SEL_D
;
3886 I915_WRITE(reg
, temp
);
3889 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3892 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3894 struct drm_device
*dev
= crtc
->dev
;
3895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3896 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3897 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
3899 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3901 lpt_program_iclkip(crtc
);
3903 /* Set transcoder timing. */
3904 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3906 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3909 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3911 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3916 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
3917 WARN(1, "bad %s crtc mask\n", pll
->name
);
3921 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
3922 if (pll
->config
.crtc_mask
== 0) {
3924 WARN_ON(pll
->active
);
3927 crtc
->config
->shared_dpll
= DPLL_ID_PRIVATE
;
3930 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
3931 struct intel_crtc_state
*crtc_state
)
3933 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3934 struct intel_shared_dpll
*pll
;
3935 enum intel_dpll_id i
;
3937 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3938 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3939 i
= (enum intel_dpll_id
) crtc
->pipe
;
3940 pll
= &dev_priv
->shared_dplls
[i
];
3942 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3943 crtc
->base
.base
.id
, pll
->name
);
3945 WARN_ON(pll
->new_config
->crtc_mask
);
3950 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3951 pll
= &dev_priv
->shared_dplls
[i
];
3953 /* Only want to check enabled timings first */
3954 if (pll
->new_config
->crtc_mask
== 0)
3957 if (memcmp(&crtc_state
->dpll_hw_state
,
3958 &pll
->new_config
->hw_state
,
3959 sizeof(pll
->new_config
->hw_state
)) == 0) {
3960 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3961 crtc
->base
.base
.id
, pll
->name
,
3962 pll
->new_config
->crtc_mask
,
3968 /* Ok no matching timings, maybe there's a free one? */
3969 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3970 pll
= &dev_priv
->shared_dplls
[i
];
3971 if (pll
->new_config
->crtc_mask
== 0) {
3972 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3973 crtc
->base
.base
.id
, pll
->name
);
3981 if (pll
->new_config
->crtc_mask
== 0)
3982 pll
->new_config
->hw_state
= crtc_state
->dpll_hw_state
;
3984 crtc_state
->shared_dpll
= i
;
3985 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3986 pipe_name(crtc
->pipe
));
3988 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
3994 * intel_shared_dpll_start_config - start a new PLL staged config
3995 * @dev_priv: DRM device
3996 * @clear_pipes: mask of pipes that will have their PLLs freed
3998 * Starts a new PLL staged config, copying the current config but
3999 * releasing the references of pipes specified in clear_pipes.
4001 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
4002 unsigned clear_pipes
)
4004 struct intel_shared_dpll
*pll
;
4005 enum intel_dpll_id i
;
4007 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4008 pll
= &dev_priv
->shared_dplls
[i
];
4010 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
4012 if (!pll
->new_config
)
4015 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
4022 pll
= &dev_priv
->shared_dplls
[i
];
4023 kfree(pll
->new_config
);
4024 pll
->new_config
= NULL
;
4030 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
4032 struct intel_shared_dpll
*pll
;
4033 enum intel_dpll_id i
;
4035 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4036 pll
= &dev_priv
->shared_dplls
[i
];
4038 WARN_ON(pll
->new_config
== &pll
->config
);
4040 pll
->config
= *pll
->new_config
;
4041 kfree(pll
->new_config
);
4042 pll
->new_config
= NULL
;
4046 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
4048 struct intel_shared_dpll
*pll
;
4049 enum intel_dpll_id i
;
4051 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4052 pll
= &dev_priv
->shared_dplls
[i
];
4054 WARN_ON(pll
->new_config
== &pll
->config
);
4056 kfree(pll
->new_config
);
4057 pll
->new_config
= NULL
;
4061 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4064 int dslreg
= PIPEDSL(pipe
);
4067 temp
= I915_READ(dslreg
);
4069 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4070 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4071 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4075 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4077 struct drm_device
*dev
= crtc
->base
.dev
;
4078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4079 int pipe
= crtc
->pipe
;
4081 if (crtc
->config
->pch_pfit
.enabled
) {
4082 I915_WRITE(PS_CTL(pipe
), PS_ENABLE
);
4083 I915_WRITE(PS_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4084 I915_WRITE(PS_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4088 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4090 struct drm_device
*dev
= crtc
->base
.dev
;
4091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4092 int pipe
= crtc
->pipe
;
4094 if (crtc
->config
->pch_pfit
.enabled
) {
4095 /* Force use of hard-coded filter coefficients
4096 * as some pre-programmed values are broken,
4099 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4100 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4101 PF_PIPE_SEL_IVB(pipe
));
4103 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4104 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4105 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4109 static void intel_enable_sprite_planes(struct drm_crtc
*crtc
)
4111 struct drm_device
*dev
= crtc
->dev
;
4112 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4113 struct drm_plane
*plane
;
4114 struct intel_plane
*intel_plane
;
4116 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4117 intel_plane
= to_intel_plane(plane
);
4118 if (intel_plane
->pipe
== pipe
)
4119 intel_plane_restore(&intel_plane
->base
);
4123 static void intel_disable_sprite_planes(struct drm_crtc
*crtc
)
4125 struct drm_device
*dev
= crtc
->dev
;
4126 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4127 struct drm_plane
*plane
;
4128 struct intel_plane
*intel_plane
;
4130 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4131 intel_plane
= to_intel_plane(plane
);
4132 if (intel_plane
->pipe
== pipe
)
4133 plane
->funcs
->disable_plane(plane
);
4137 void hsw_enable_ips(struct intel_crtc
*crtc
)
4139 struct drm_device
*dev
= crtc
->base
.dev
;
4140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4142 if (!crtc
->config
->ips_enabled
)
4145 /* We can only enable IPS after we enable a plane and wait for a vblank */
4146 intel_wait_for_vblank(dev
, crtc
->pipe
);
4148 assert_plane_enabled(dev_priv
, crtc
->plane
);
4149 if (IS_BROADWELL(dev
)) {
4150 mutex_lock(&dev_priv
->rps
.hw_lock
);
4151 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4152 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4153 /* Quoting Art Runyan: "its not safe to expect any particular
4154 * value in IPS_CTL bit 31 after enabling IPS through the
4155 * mailbox." Moreover, the mailbox may return a bogus state,
4156 * so we need to just enable it and continue on.
4159 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4160 /* The bit only becomes 1 in the next vblank, so this wait here
4161 * is essentially intel_wait_for_vblank. If we don't have this
4162 * and don't wait for vblanks until the end of crtc_enable, then
4163 * the HW state readout code will complain that the expected
4164 * IPS_CTL value is not the one we read. */
4165 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4166 DRM_ERROR("Timed out waiting for IPS enable\n");
4170 void hsw_disable_ips(struct intel_crtc
*crtc
)
4172 struct drm_device
*dev
= crtc
->base
.dev
;
4173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4175 if (!crtc
->config
->ips_enabled
)
4178 assert_plane_enabled(dev_priv
, crtc
->plane
);
4179 if (IS_BROADWELL(dev
)) {
4180 mutex_lock(&dev_priv
->rps
.hw_lock
);
4181 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4182 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4183 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4184 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4185 DRM_ERROR("Timed out waiting for IPS disable\n");
4187 I915_WRITE(IPS_CTL
, 0);
4188 POSTING_READ(IPS_CTL
);
4191 /* We need to wait for a vblank before we can disable the plane. */
4192 intel_wait_for_vblank(dev
, crtc
->pipe
);
4195 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4196 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4198 struct drm_device
*dev
= crtc
->dev
;
4199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4200 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4201 enum pipe pipe
= intel_crtc
->pipe
;
4202 int palreg
= PALETTE(pipe
);
4204 bool reenable_ips
= false;
4206 /* The clocks have to be on to load the palette. */
4207 if (!crtc
->enabled
|| !intel_crtc
->active
)
4210 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
4211 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4212 assert_dsi_pll_enabled(dev_priv
);
4214 assert_pll_enabled(dev_priv
, pipe
);
4217 /* use legacy palette for Ironlake */
4218 if (!HAS_GMCH_DISPLAY(dev
))
4219 palreg
= LGC_PALETTE(pipe
);
4221 /* Workaround : Do not read or write the pipe palette/gamma data while
4222 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4224 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4225 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4226 GAMMA_MODE_MODE_SPLIT
)) {
4227 hsw_disable_ips(intel_crtc
);
4228 reenable_ips
= true;
4231 for (i
= 0; i
< 256; i
++) {
4232 I915_WRITE(palreg
+ 4 * i
,
4233 (intel_crtc
->lut_r
[i
] << 16) |
4234 (intel_crtc
->lut_g
[i
] << 8) |
4235 intel_crtc
->lut_b
[i
]);
4239 hsw_enable_ips(intel_crtc
);
4242 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
4244 if (!enable
&& intel_crtc
->overlay
) {
4245 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4248 mutex_lock(&dev
->struct_mutex
);
4249 dev_priv
->mm
.interruptible
= false;
4250 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4251 dev_priv
->mm
.interruptible
= true;
4252 mutex_unlock(&dev
->struct_mutex
);
4255 /* Let userspace switch the overlay on again. In most cases userspace
4256 * has to recompute where to put it anyway.
4260 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4262 struct drm_device
*dev
= crtc
->dev
;
4263 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4264 int pipe
= intel_crtc
->pipe
;
4266 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4267 intel_enable_sprite_planes(crtc
);
4268 intel_crtc_update_cursor(crtc
, true);
4269 intel_crtc_dpms_overlay(intel_crtc
, true);
4271 hsw_enable_ips(intel_crtc
);
4273 mutex_lock(&dev
->struct_mutex
);
4274 intel_fbc_update(dev
);
4275 mutex_unlock(&dev
->struct_mutex
);
4278 * FIXME: Once we grow proper nuclear flip support out of this we need
4279 * to compute the mask of flip planes precisely. For the time being
4280 * consider this a flip from a NULL plane.
4282 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4285 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4287 struct drm_device
*dev
= crtc
->dev
;
4288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4289 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4290 int pipe
= intel_crtc
->pipe
;
4291 int plane
= intel_crtc
->plane
;
4293 intel_crtc_wait_for_pending_flips(crtc
);
4295 if (dev_priv
->fbc
.plane
== plane
)
4296 intel_fbc_disable(dev
);
4298 hsw_disable_ips(intel_crtc
);
4300 intel_crtc_dpms_overlay(intel_crtc
, false);
4301 intel_crtc_update_cursor(crtc
, false);
4302 intel_disable_sprite_planes(crtc
);
4303 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4306 * FIXME: Once we grow proper nuclear flip support out of this we need
4307 * to compute the mask of flip planes precisely. For the time being
4308 * consider this a flip to a NULL plane.
4310 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4313 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4315 struct drm_device
*dev
= crtc
->dev
;
4316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4317 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4318 struct intel_encoder
*encoder
;
4319 int pipe
= intel_crtc
->pipe
;
4321 WARN_ON(!crtc
->enabled
);
4323 if (intel_crtc
->active
)
4326 if (intel_crtc
->config
->has_pch_encoder
)
4327 intel_prepare_shared_dpll(intel_crtc
);
4329 if (intel_crtc
->config
->has_dp_encoder
)
4330 intel_dp_set_m_n(intel_crtc
);
4332 intel_set_pipe_timings(intel_crtc
);
4334 if (intel_crtc
->config
->has_pch_encoder
) {
4335 intel_cpu_transcoder_set_m_n(intel_crtc
,
4336 &intel_crtc
->config
->fdi_m_n
, NULL
);
4339 ironlake_set_pipeconf(crtc
);
4341 intel_crtc
->active
= true;
4343 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4344 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4346 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4347 if (encoder
->pre_enable
)
4348 encoder
->pre_enable(encoder
);
4350 if (intel_crtc
->config
->has_pch_encoder
) {
4351 /* Note: FDI PLL enabling _must_ be done before we enable the
4352 * cpu pipes, hence this is separate from all the other fdi/pch
4354 ironlake_fdi_pll_enable(intel_crtc
);
4356 assert_fdi_tx_disabled(dev_priv
, pipe
);
4357 assert_fdi_rx_disabled(dev_priv
, pipe
);
4360 ironlake_pfit_enable(intel_crtc
);
4363 * On ILK+ LUT must be loaded before the pipe is running but with
4366 intel_crtc_load_lut(crtc
);
4368 intel_update_watermarks(crtc
);
4369 intel_enable_pipe(intel_crtc
);
4371 if (intel_crtc
->config
->has_pch_encoder
)
4372 ironlake_pch_enable(crtc
);
4374 assert_vblank_disabled(crtc
);
4375 drm_crtc_vblank_on(crtc
);
4377 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4378 encoder
->enable(encoder
);
4380 if (HAS_PCH_CPT(dev
))
4381 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4383 intel_crtc_enable_planes(crtc
);
4386 /* IPS only exists on ULT machines and is tied to pipe A. */
4387 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4389 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4393 * This implements the workaround described in the "notes" section of the mode
4394 * set sequence documentation. When going from no pipes or single pipe to
4395 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4396 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4398 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4400 struct drm_device
*dev
= crtc
->base
.dev
;
4401 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4403 /* We want to get the other_active_crtc only if there's only 1 other
4405 for_each_intel_crtc(dev
, crtc_it
) {
4406 if (!crtc_it
->active
|| crtc_it
== crtc
)
4409 if (other_active_crtc
)
4412 other_active_crtc
= crtc_it
;
4414 if (!other_active_crtc
)
4417 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4418 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4421 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4423 struct drm_device
*dev
= crtc
->dev
;
4424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4425 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4426 struct intel_encoder
*encoder
;
4427 int pipe
= intel_crtc
->pipe
;
4429 WARN_ON(!crtc
->enabled
);
4431 if (intel_crtc
->active
)
4434 if (intel_crtc_to_shared_dpll(intel_crtc
))
4435 intel_enable_shared_dpll(intel_crtc
);
4437 if (intel_crtc
->config
->has_dp_encoder
)
4438 intel_dp_set_m_n(intel_crtc
);
4440 intel_set_pipe_timings(intel_crtc
);
4442 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
4443 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
4444 intel_crtc
->config
->pixel_multiplier
- 1);
4447 if (intel_crtc
->config
->has_pch_encoder
) {
4448 intel_cpu_transcoder_set_m_n(intel_crtc
,
4449 &intel_crtc
->config
->fdi_m_n
, NULL
);
4452 haswell_set_pipeconf(crtc
);
4454 intel_set_pipe_csc(crtc
);
4456 intel_crtc
->active
= true;
4458 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4459 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4460 if (encoder
->pre_enable
)
4461 encoder
->pre_enable(encoder
);
4463 if (intel_crtc
->config
->has_pch_encoder
) {
4464 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4466 dev_priv
->display
.fdi_link_train(crtc
);
4469 intel_ddi_enable_pipe_clock(intel_crtc
);
4471 if (IS_SKYLAKE(dev
))
4472 skylake_pfit_enable(intel_crtc
);
4474 ironlake_pfit_enable(intel_crtc
);
4477 * On ILK+ LUT must be loaded before the pipe is running but with
4480 intel_crtc_load_lut(crtc
);
4482 intel_ddi_set_pipe_settings(crtc
);
4483 intel_ddi_enable_transcoder_func(crtc
);
4485 intel_update_watermarks(crtc
);
4486 intel_enable_pipe(intel_crtc
);
4488 if (intel_crtc
->config
->has_pch_encoder
)
4489 lpt_pch_enable(crtc
);
4491 if (intel_crtc
->config
->dp_encoder_is_mst
)
4492 intel_ddi_set_vc_payload_alloc(crtc
, true);
4494 assert_vblank_disabled(crtc
);
4495 drm_crtc_vblank_on(crtc
);
4497 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4498 encoder
->enable(encoder
);
4499 intel_opregion_notify_encoder(encoder
, true);
4502 /* If we change the relative order between pipe/planes enabling, we need
4503 * to change the workaround. */
4504 haswell_mode_set_planes_workaround(intel_crtc
);
4505 intel_crtc_enable_planes(crtc
);
4508 static void skylake_pfit_disable(struct intel_crtc
*crtc
)
4510 struct drm_device
*dev
= crtc
->base
.dev
;
4511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4512 int pipe
= crtc
->pipe
;
4514 /* To avoid upsetting the power well on haswell only disable the pfit if
4515 * it's in use. The hw state code will make sure we get this right. */
4516 if (crtc
->config
->pch_pfit
.enabled
) {
4517 I915_WRITE(PS_CTL(pipe
), 0);
4518 I915_WRITE(PS_WIN_POS(pipe
), 0);
4519 I915_WRITE(PS_WIN_SZ(pipe
), 0);
4523 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4525 struct drm_device
*dev
= crtc
->base
.dev
;
4526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4527 int pipe
= crtc
->pipe
;
4529 /* To avoid upsetting the power well on haswell only disable the pfit if
4530 * it's in use. The hw state code will make sure we get this right. */
4531 if (crtc
->config
->pch_pfit
.enabled
) {
4532 I915_WRITE(PF_CTL(pipe
), 0);
4533 I915_WRITE(PF_WIN_POS(pipe
), 0);
4534 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4538 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4540 struct drm_device
*dev
= crtc
->dev
;
4541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4542 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4543 struct intel_encoder
*encoder
;
4544 int pipe
= intel_crtc
->pipe
;
4547 if (!intel_crtc
->active
)
4550 intel_crtc_disable_planes(crtc
);
4552 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4553 encoder
->disable(encoder
);
4555 drm_crtc_vblank_off(crtc
);
4556 assert_vblank_disabled(crtc
);
4558 if (intel_crtc
->config
->has_pch_encoder
)
4559 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4561 intel_disable_pipe(intel_crtc
);
4563 ironlake_pfit_disable(intel_crtc
);
4565 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4566 if (encoder
->post_disable
)
4567 encoder
->post_disable(encoder
);
4569 if (intel_crtc
->config
->has_pch_encoder
) {
4570 ironlake_fdi_disable(crtc
);
4572 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4574 if (HAS_PCH_CPT(dev
)) {
4575 /* disable TRANS_DP_CTL */
4576 reg
= TRANS_DP_CTL(pipe
);
4577 temp
= I915_READ(reg
);
4578 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4579 TRANS_DP_PORT_SEL_MASK
);
4580 temp
|= TRANS_DP_PORT_SEL_NONE
;
4581 I915_WRITE(reg
, temp
);
4583 /* disable DPLL_SEL */
4584 temp
= I915_READ(PCH_DPLL_SEL
);
4585 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4586 I915_WRITE(PCH_DPLL_SEL
, temp
);
4589 /* disable PCH DPLL */
4590 intel_disable_shared_dpll(intel_crtc
);
4592 ironlake_fdi_pll_disable(intel_crtc
);
4595 intel_crtc
->active
= false;
4596 intel_update_watermarks(crtc
);
4598 mutex_lock(&dev
->struct_mutex
);
4599 intel_fbc_update(dev
);
4600 mutex_unlock(&dev
->struct_mutex
);
4603 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4605 struct drm_device
*dev
= crtc
->dev
;
4606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4607 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4608 struct intel_encoder
*encoder
;
4609 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4611 if (!intel_crtc
->active
)
4614 intel_crtc_disable_planes(crtc
);
4616 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4617 intel_opregion_notify_encoder(encoder
, false);
4618 encoder
->disable(encoder
);
4621 drm_crtc_vblank_off(crtc
);
4622 assert_vblank_disabled(crtc
);
4624 if (intel_crtc
->config
->has_pch_encoder
)
4625 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4627 intel_disable_pipe(intel_crtc
);
4629 if (intel_crtc
->config
->dp_encoder_is_mst
)
4630 intel_ddi_set_vc_payload_alloc(crtc
, false);
4632 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4634 if (IS_SKYLAKE(dev
))
4635 skylake_pfit_disable(intel_crtc
);
4637 ironlake_pfit_disable(intel_crtc
);
4639 intel_ddi_disable_pipe_clock(intel_crtc
);
4641 if (intel_crtc
->config
->has_pch_encoder
) {
4642 lpt_disable_pch_transcoder(dev_priv
);
4643 intel_ddi_fdi_disable(crtc
);
4646 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4647 if (encoder
->post_disable
)
4648 encoder
->post_disable(encoder
);
4650 intel_crtc
->active
= false;
4651 intel_update_watermarks(crtc
);
4653 mutex_lock(&dev
->struct_mutex
);
4654 intel_fbc_update(dev
);
4655 mutex_unlock(&dev
->struct_mutex
);
4657 if (intel_crtc_to_shared_dpll(intel_crtc
))
4658 intel_disable_shared_dpll(intel_crtc
);
4661 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4663 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4664 intel_put_shared_dpll(intel_crtc
);
4668 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4670 struct drm_device
*dev
= crtc
->base
.dev
;
4671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4672 struct intel_crtc_state
*pipe_config
= crtc
->config
;
4674 if (!pipe_config
->gmch_pfit
.control
)
4678 * The panel fitter should only be adjusted whilst the pipe is disabled,
4679 * according to register description and PRM.
4681 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4682 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4684 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4685 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4687 /* Border color in case we don't scale up to the full screen. Black by
4688 * default, change to something else for debugging. */
4689 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4692 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4696 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4698 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4700 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4702 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4705 return POWER_DOMAIN_PORT_OTHER
;
4709 #define for_each_power_domain(domain, mask) \
4710 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4711 if ((1 << (domain)) & (mask))
4713 enum intel_display_power_domain
4714 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4716 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4717 struct intel_digital_port
*intel_dig_port
;
4719 switch (intel_encoder
->type
) {
4720 case INTEL_OUTPUT_UNKNOWN
:
4721 /* Only DDI platforms should ever use this output type */
4722 WARN_ON_ONCE(!HAS_DDI(dev
));
4723 case INTEL_OUTPUT_DISPLAYPORT
:
4724 case INTEL_OUTPUT_HDMI
:
4725 case INTEL_OUTPUT_EDP
:
4726 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4727 return port_to_power_domain(intel_dig_port
->port
);
4728 case INTEL_OUTPUT_DP_MST
:
4729 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4730 return port_to_power_domain(intel_dig_port
->port
);
4731 case INTEL_OUTPUT_ANALOG
:
4732 return POWER_DOMAIN_PORT_CRT
;
4733 case INTEL_OUTPUT_DSI
:
4734 return POWER_DOMAIN_PORT_DSI
;
4736 return POWER_DOMAIN_PORT_OTHER
;
4740 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4742 struct drm_device
*dev
= crtc
->dev
;
4743 struct intel_encoder
*intel_encoder
;
4744 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4745 enum pipe pipe
= intel_crtc
->pipe
;
4747 enum transcoder transcoder
;
4749 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4751 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4752 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4753 if (intel_crtc
->config
->pch_pfit
.enabled
||
4754 intel_crtc
->config
->pch_pfit
.force_thru
)
4755 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4757 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4758 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4763 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4766 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4767 struct intel_crtc
*crtc
;
4770 * First get all needed power domains, then put all unneeded, to avoid
4771 * any unnecessary toggling of the power wells.
4773 for_each_intel_crtc(dev
, crtc
) {
4774 enum intel_display_power_domain domain
;
4776 if (!crtc
->base
.enabled
)
4779 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4781 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4782 intel_display_power_get(dev_priv
, domain
);
4785 if (dev_priv
->display
.modeset_global_resources
)
4786 dev_priv
->display
.modeset_global_resources(dev
);
4788 for_each_intel_crtc(dev
, crtc
) {
4789 enum intel_display_power_domain domain
;
4791 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4792 intel_display_power_put(dev_priv
, domain
);
4794 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4797 intel_display_set_init_power(dev_priv
, false);
4800 /* returns HPLL frequency in kHz */
4801 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4803 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4805 /* Obtain SKU information */
4806 mutex_lock(&dev_priv
->dpio_lock
);
4807 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4808 CCK_FUSE_HPLL_FREQ_MASK
;
4809 mutex_unlock(&dev_priv
->dpio_lock
);
4811 return vco_freq
[hpll_freq
] * 1000;
4814 static void vlv_update_cdclk(struct drm_device
*dev
)
4816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4818 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4819 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4820 dev_priv
->vlv_cdclk_freq
);
4823 * Program the gmbus_freq based on the cdclk frequency.
4824 * BSpec erroneously claims we should aim for 4MHz, but
4825 * in fact 1MHz is the correct frequency.
4827 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->vlv_cdclk_freq
, 1000));
4830 /* Adjust CDclk dividers to allow high res or save power if possible */
4831 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4836 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4838 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4840 else if (cdclk
== 266667)
4845 mutex_lock(&dev_priv
->rps
.hw_lock
);
4846 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4847 val
&= ~DSPFREQGUAR_MASK
;
4848 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4849 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4850 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4851 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4853 DRM_ERROR("timed out waiting for CDclk change\n");
4855 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4857 if (cdclk
== 400000) {
4860 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
4862 mutex_lock(&dev_priv
->dpio_lock
);
4863 /* adjust cdclk divider */
4864 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4865 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4867 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4869 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4870 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4872 DRM_ERROR("timed out waiting for CDclk change\n");
4873 mutex_unlock(&dev_priv
->dpio_lock
);
4876 mutex_lock(&dev_priv
->dpio_lock
);
4877 /* adjust self-refresh exit latency value */
4878 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4882 * For high bandwidth configs, we set a higher latency in the bunit
4883 * so that the core display fetch happens in time to avoid underruns.
4885 if (cdclk
== 400000)
4886 val
|= 4500 / 250; /* 4.5 usec */
4888 val
|= 3000 / 250; /* 3.0 usec */
4889 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4890 mutex_unlock(&dev_priv
->dpio_lock
);
4892 vlv_update_cdclk(dev
);
4895 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4900 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4917 MISSING_CASE(cdclk
);
4921 mutex_lock(&dev_priv
->rps
.hw_lock
);
4922 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4923 val
&= ~DSPFREQGUAR_MASK_CHV
;
4924 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
4925 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4926 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4927 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
4929 DRM_ERROR("timed out waiting for CDclk change\n");
4931 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4933 vlv_update_cdclk(dev
);
4936 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4939 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
4941 /* FIXME: Punit isn't quite ready yet */
4942 if (IS_CHERRYVIEW(dev_priv
->dev
))
4946 * Really only a few cases to deal with, as only 4 CDclks are supported:
4949 * 320/333MHz (depends on HPLL freq)
4951 * So we check to see whether we're above 90% of the lower bin and
4954 * We seem to get an unstable or solid color picture at 200MHz.
4955 * Not sure what's wrong. For now use 200MHz only when all pipes
4958 if (max_pixclk
> freq_320
*9/10)
4960 else if (max_pixclk
> 266667*9/10)
4962 else if (max_pixclk
> 0)
4968 /* compute the max pixel clock for new configuration */
4969 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4971 struct drm_device
*dev
= dev_priv
->dev
;
4972 struct intel_crtc
*intel_crtc
;
4975 for_each_intel_crtc(dev
, intel_crtc
) {
4976 if (intel_crtc
->new_enabled
)
4977 max_pixclk
= max(max_pixclk
,
4978 intel_crtc
->new_config
->base
.adjusted_mode
.crtc_clock
);
4984 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4985 unsigned *prepare_pipes
)
4987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4988 struct intel_crtc
*intel_crtc
;
4989 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4991 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4992 dev_priv
->vlv_cdclk_freq
)
4995 /* disable/enable all currently active pipes while we change cdclk */
4996 for_each_intel_crtc(dev
, intel_crtc
)
4997 if (intel_crtc
->base
.enabled
)
4998 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
5001 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
5003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5004 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
5005 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5007 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
5009 * FIXME: We can end up here with all power domains off, yet
5010 * with a CDCLK frequency other than the minimum. To account
5011 * for this take the PIPE-A power domain, which covers the HW
5012 * blocks needed for the following programming. This can be
5013 * removed once it's guaranteed that we get here either with
5014 * the minimum CDCLK set, or the required power domains
5017 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
5019 if (IS_CHERRYVIEW(dev
))
5020 cherryview_set_cdclk(dev
, req_cdclk
);
5022 valleyview_set_cdclk(dev
, req_cdclk
);
5024 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
5028 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
5030 struct drm_device
*dev
= crtc
->dev
;
5031 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5032 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5033 struct intel_encoder
*encoder
;
5034 int pipe
= intel_crtc
->pipe
;
5037 WARN_ON(!crtc
->enabled
);
5039 if (intel_crtc
->active
)
5042 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
5045 if (IS_CHERRYVIEW(dev
))
5046 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5048 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5051 if (intel_crtc
->config
->has_dp_encoder
)
5052 intel_dp_set_m_n(intel_crtc
);
5054 intel_set_pipe_timings(intel_crtc
);
5056 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
5057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5059 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
5060 I915_WRITE(CHV_CANVAS(pipe
), 0);
5063 i9xx_set_pipeconf(intel_crtc
);
5065 intel_crtc
->active
= true;
5067 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5069 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5070 if (encoder
->pre_pll_enable
)
5071 encoder
->pre_pll_enable(encoder
);
5074 if (IS_CHERRYVIEW(dev
))
5075 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
5077 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
5080 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5081 if (encoder
->pre_enable
)
5082 encoder
->pre_enable(encoder
);
5084 i9xx_pfit_enable(intel_crtc
);
5086 intel_crtc_load_lut(crtc
);
5088 intel_update_watermarks(crtc
);
5089 intel_enable_pipe(intel_crtc
);
5091 assert_vblank_disabled(crtc
);
5092 drm_crtc_vblank_on(crtc
);
5094 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5095 encoder
->enable(encoder
);
5097 intel_crtc_enable_planes(crtc
);
5099 /* Underruns don't raise interrupts, so check manually. */
5100 i9xx_check_fifo_underruns(dev_priv
);
5103 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
5105 struct drm_device
*dev
= crtc
->base
.dev
;
5106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5108 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
5109 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
5112 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
5114 struct drm_device
*dev
= crtc
->dev
;
5115 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5116 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5117 struct intel_encoder
*encoder
;
5118 int pipe
= intel_crtc
->pipe
;
5120 WARN_ON(!crtc
->enabled
);
5122 if (intel_crtc
->active
)
5125 i9xx_set_pll_dividers(intel_crtc
);
5127 if (intel_crtc
->config
->has_dp_encoder
)
5128 intel_dp_set_m_n(intel_crtc
);
5130 intel_set_pipe_timings(intel_crtc
);
5132 i9xx_set_pipeconf(intel_crtc
);
5134 intel_crtc
->active
= true;
5137 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5139 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5140 if (encoder
->pre_enable
)
5141 encoder
->pre_enable(encoder
);
5143 i9xx_enable_pll(intel_crtc
);
5145 i9xx_pfit_enable(intel_crtc
);
5147 intel_crtc_load_lut(crtc
);
5149 intel_update_watermarks(crtc
);
5150 intel_enable_pipe(intel_crtc
);
5152 assert_vblank_disabled(crtc
);
5153 drm_crtc_vblank_on(crtc
);
5155 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5156 encoder
->enable(encoder
);
5158 intel_crtc_enable_planes(crtc
);
5161 * Gen2 reports pipe underruns whenever all planes are disabled.
5162 * So don't enable underrun reporting before at least some planes
5164 * FIXME: Need to fix the logic to work when we turn off all planes
5165 * but leave the pipe running.
5168 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5170 /* Underruns don't raise interrupts, so check manually. */
5171 i9xx_check_fifo_underruns(dev_priv
);
5174 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5176 struct drm_device
*dev
= crtc
->base
.dev
;
5177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5179 if (!crtc
->config
->gmch_pfit
.control
)
5182 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5184 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5185 I915_READ(PFIT_CONTROL
));
5186 I915_WRITE(PFIT_CONTROL
, 0);
5189 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
5191 struct drm_device
*dev
= crtc
->dev
;
5192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5193 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5194 struct intel_encoder
*encoder
;
5195 int pipe
= intel_crtc
->pipe
;
5197 if (!intel_crtc
->active
)
5201 * Gen2 reports pipe underruns whenever all planes are disabled.
5202 * So diasble underrun reporting before all the planes get disabled.
5203 * FIXME: Need to fix the logic to work when we turn off all planes
5204 * but leave the pipe running.
5207 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5210 * Vblank time updates from the shadow to live plane control register
5211 * are blocked if the memory self-refresh mode is active at that
5212 * moment. So to make sure the plane gets truly disabled, disable
5213 * first the self-refresh mode. The self-refresh enable bit in turn
5214 * will be checked/applied by the HW only at the next frame start
5215 * event which is after the vblank start event, so we need to have a
5216 * wait-for-vblank between disabling the plane and the pipe.
5218 intel_set_memory_cxsr(dev_priv
, false);
5219 intel_crtc_disable_planes(crtc
);
5222 * On gen2 planes are double buffered but the pipe isn't, so we must
5223 * wait for planes to fully turn off before disabling the pipe.
5224 * We also need to wait on all gmch platforms because of the
5225 * self-refresh mode constraint explained above.
5227 intel_wait_for_vblank(dev
, pipe
);
5229 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5230 encoder
->disable(encoder
);
5232 drm_crtc_vblank_off(crtc
);
5233 assert_vblank_disabled(crtc
);
5235 intel_disable_pipe(intel_crtc
);
5237 i9xx_pfit_disable(intel_crtc
);
5239 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5240 if (encoder
->post_disable
)
5241 encoder
->post_disable(encoder
);
5243 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
5244 if (IS_CHERRYVIEW(dev
))
5245 chv_disable_pll(dev_priv
, pipe
);
5246 else if (IS_VALLEYVIEW(dev
))
5247 vlv_disable_pll(dev_priv
, pipe
);
5249 i9xx_disable_pll(intel_crtc
);
5253 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5255 intel_crtc
->active
= false;
5256 intel_update_watermarks(crtc
);
5258 mutex_lock(&dev
->struct_mutex
);
5259 intel_fbc_update(dev
);
5260 mutex_unlock(&dev
->struct_mutex
);
5263 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
5267 /* Master function to enable/disable CRTC and corresponding power wells */
5268 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
5270 struct drm_device
*dev
= crtc
->dev
;
5271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5272 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5273 enum intel_display_power_domain domain
;
5274 unsigned long domains
;
5277 if (!intel_crtc
->active
) {
5278 domains
= get_crtc_power_domains(crtc
);
5279 for_each_power_domain(domain
, domains
)
5280 intel_display_power_get(dev_priv
, domain
);
5281 intel_crtc
->enabled_power_domains
= domains
;
5283 dev_priv
->display
.crtc_enable(crtc
);
5286 if (intel_crtc
->active
) {
5287 dev_priv
->display
.crtc_disable(crtc
);
5289 domains
= intel_crtc
->enabled_power_domains
;
5290 for_each_power_domain(domain
, domains
)
5291 intel_display_power_put(dev_priv
, domain
);
5292 intel_crtc
->enabled_power_domains
= 0;
5298 * Sets the power management mode of the pipe and plane.
5300 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
5302 struct drm_device
*dev
= crtc
->dev
;
5303 struct intel_encoder
*intel_encoder
;
5304 bool enable
= false;
5306 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5307 enable
|= intel_encoder
->connectors_active
;
5309 intel_crtc_control(crtc
, enable
);
5312 static void intel_crtc_disable(struct drm_crtc
*crtc
)
5314 struct drm_device
*dev
= crtc
->dev
;
5315 struct drm_connector
*connector
;
5316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5318 /* crtc should still be enabled when we disable it. */
5319 WARN_ON(!crtc
->enabled
);
5321 dev_priv
->display
.crtc_disable(crtc
);
5322 dev_priv
->display
.off(crtc
);
5324 crtc
->primary
->funcs
->disable_plane(crtc
->primary
);
5326 /* Update computed state. */
5327 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5328 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5331 if (connector
->encoder
->crtc
!= crtc
)
5334 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5335 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5339 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5341 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5343 drm_encoder_cleanup(encoder
);
5344 kfree(intel_encoder
);
5347 /* Simple dpms helper for encoders with just one connector, no cloning and only
5348 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5349 * state of the entire output pipe. */
5350 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5352 if (mode
== DRM_MODE_DPMS_ON
) {
5353 encoder
->connectors_active
= true;
5355 intel_crtc_update_dpms(encoder
->base
.crtc
);
5357 encoder
->connectors_active
= false;
5359 intel_crtc_update_dpms(encoder
->base
.crtc
);
5363 /* Cross check the actual hw state with our own modeset state tracking (and it's
5364 * internal consistency). */
5365 static void intel_connector_check_state(struct intel_connector
*connector
)
5367 if (connector
->get_hw_state(connector
)) {
5368 struct intel_encoder
*encoder
= connector
->encoder
;
5369 struct drm_crtc
*crtc
;
5370 bool encoder_enabled
;
5373 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5374 connector
->base
.base
.id
,
5375 connector
->base
.name
);
5377 /* there is no real hw state for MST connectors */
5378 if (connector
->mst_port
)
5381 I915_STATE_WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5382 "wrong connector dpms state\n");
5383 I915_STATE_WARN(connector
->base
.encoder
!= &encoder
->base
,
5384 "active connector not linked to encoder\n");
5387 I915_STATE_WARN(!encoder
->connectors_active
,
5388 "encoder->connectors_active not set\n");
5390 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5391 I915_STATE_WARN(!encoder_enabled
, "encoder not enabled\n");
5392 if (I915_STATE_WARN_ON(!encoder
->base
.crtc
))
5395 crtc
= encoder
->base
.crtc
;
5397 I915_STATE_WARN(!crtc
->enabled
, "crtc not enabled\n");
5398 I915_STATE_WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5399 I915_STATE_WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5400 "encoder active on the wrong pipe\n");
5405 /* Even simpler default implementation, if there's really no special case to
5407 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5409 /* All the simple cases only support two dpms states. */
5410 if (mode
!= DRM_MODE_DPMS_ON
)
5411 mode
= DRM_MODE_DPMS_OFF
;
5413 if (mode
== connector
->dpms
)
5416 connector
->dpms
= mode
;
5418 /* Only need to change hw state when actually enabled */
5419 if (connector
->encoder
)
5420 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5422 intel_modeset_check_state(connector
->dev
);
5425 /* Simple connector->get_hw_state implementation for encoders that support only
5426 * one connector and no cloning and hence the encoder state determines the state
5427 * of the connector. */
5428 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5431 struct intel_encoder
*encoder
= connector
->encoder
;
5433 return encoder
->get_hw_state(encoder
, &pipe
);
5436 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5437 struct intel_crtc_state
*pipe_config
)
5439 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5440 struct intel_crtc
*pipe_B_crtc
=
5441 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5443 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5444 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5445 if (pipe_config
->fdi_lanes
> 4) {
5446 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5447 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5451 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5452 if (pipe_config
->fdi_lanes
> 2) {
5453 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5454 pipe_config
->fdi_lanes
);
5461 if (INTEL_INFO(dev
)->num_pipes
== 2)
5464 /* Ivybridge 3 pipe is really complicated */
5469 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5470 pipe_config
->fdi_lanes
> 2) {
5471 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5472 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5477 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5478 pipe_B_crtc
->config
->fdi_lanes
<= 2) {
5479 if (pipe_config
->fdi_lanes
> 2) {
5480 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5481 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5485 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5495 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5496 struct intel_crtc_state
*pipe_config
)
5498 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5499 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
5500 int lane
, link_bw
, fdi_dotclock
;
5501 bool setup_ok
, needs_recompute
= false;
5504 /* FDI is a binary signal running at ~2.7GHz, encoding
5505 * each output octet as 10 bits. The actual frequency
5506 * is stored as a divider into a 100MHz clock, and the
5507 * mode pixel clock is stored in units of 1KHz.
5508 * Hence the bw of each lane in terms of the mode signal
5511 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5513 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5515 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5516 pipe_config
->pipe_bpp
);
5518 pipe_config
->fdi_lanes
= lane
;
5520 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5521 link_bw
, &pipe_config
->fdi_m_n
);
5523 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5524 intel_crtc
->pipe
, pipe_config
);
5525 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5526 pipe_config
->pipe_bpp
-= 2*3;
5527 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5528 pipe_config
->pipe_bpp
);
5529 needs_recompute
= true;
5530 pipe_config
->bw_constrained
= true;
5535 if (needs_recompute
)
5538 return setup_ok
? 0 : -EINVAL
;
5541 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5542 struct intel_crtc_state
*pipe_config
)
5544 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5545 hsw_crtc_supports_ips(crtc
) &&
5546 pipe_config
->pipe_bpp
<= 24;
5549 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5550 struct intel_crtc_state
*pipe_config
)
5552 struct drm_device
*dev
= crtc
->base
.dev
;
5553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5554 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
5556 /* FIXME should check pixel clock limits on all platforms */
5557 if (INTEL_INFO(dev
)->gen
< 4) {
5559 dev_priv
->display
.get_display_clock_speed(dev
);
5562 * Enable pixel doubling when the dot clock
5563 * is > 90% of the (display) core speed.
5565 * GDG double wide on either pipe,
5566 * otherwise pipe A only.
5568 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5569 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5571 pipe_config
->double_wide
= true;
5574 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5579 * Pipe horizontal size must be even in:
5581 * - LVDS dual channel mode
5582 * - Double wide pipe
5584 if ((intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5585 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5586 pipe_config
->pipe_src_w
&= ~1;
5588 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5589 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5591 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5592 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5595 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5596 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5597 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5598 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5600 pipe_config
->pipe_bpp
= 8*3;
5604 hsw_compute_ips_config(crtc
, pipe_config
);
5606 if (pipe_config
->has_pch_encoder
)
5607 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5612 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5618 /* FIXME: Punit isn't quite ready yet */
5619 if (IS_CHERRYVIEW(dev
))
5622 if (dev_priv
->hpll_freq
== 0)
5623 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
5625 mutex_lock(&dev_priv
->dpio_lock
);
5626 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5627 mutex_unlock(&dev_priv
->dpio_lock
);
5629 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5631 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5632 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5633 "cdclk change in progress\n");
5635 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
5638 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5643 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5648 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5653 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5657 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5659 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5660 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5662 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5664 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5666 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5669 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5670 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5672 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5677 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5681 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5683 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5686 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5687 case GC_DISPLAY_CLOCK_333_MHZ
:
5690 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5696 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5701 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5704 /* Assume that the hardware is in the high speed state. This
5705 * should be the default.
5707 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5708 case GC_CLOCK_133_200
:
5709 case GC_CLOCK_100_200
:
5711 case GC_CLOCK_166_250
:
5713 case GC_CLOCK_100_133
:
5717 /* Shouldn't happen */
5721 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5727 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5729 while (*num
> DATA_LINK_M_N_MASK
||
5730 *den
> DATA_LINK_M_N_MASK
) {
5736 static void compute_m_n(unsigned int m
, unsigned int n
,
5737 uint32_t *ret_m
, uint32_t *ret_n
)
5739 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5740 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5741 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5745 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5746 int pixel_clock
, int link_clock
,
5747 struct intel_link_m_n
*m_n
)
5751 compute_m_n(bits_per_pixel
* pixel_clock
,
5752 link_clock
* nlanes
* 8,
5753 &m_n
->gmch_m
, &m_n
->gmch_n
);
5755 compute_m_n(pixel_clock
, link_clock
,
5756 &m_n
->link_m
, &m_n
->link_n
);
5759 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5761 if (i915
.panel_use_ssc
>= 0)
5762 return i915
.panel_use_ssc
!= 0;
5763 return dev_priv
->vbt
.lvds_use_ssc
5764 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5767 static int i9xx_get_refclk(struct intel_crtc
*crtc
, int num_connectors
)
5769 struct drm_device
*dev
= crtc
->base
.dev
;
5770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5773 if (IS_VALLEYVIEW(dev
)) {
5775 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5776 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5777 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5778 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5779 } else if (!IS_GEN2(dev
)) {
5788 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5790 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5793 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5795 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5798 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5799 struct intel_crtc_state
*crtc_state
,
5800 intel_clock_t
*reduced_clock
)
5802 struct drm_device
*dev
= crtc
->base
.dev
;
5805 if (IS_PINEVIEW(dev
)) {
5806 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
5808 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5810 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
5812 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5815 crtc_state
->dpll_hw_state
.fp0
= fp
;
5817 crtc
->lowfreq_avail
= false;
5818 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5819 reduced_clock
&& i915
.powersave
) {
5820 crtc_state
->dpll_hw_state
.fp1
= fp2
;
5821 crtc
->lowfreq_avail
= true;
5823 crtc_state
->dpll_hw_state
.fp1
= fp
;
5827 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5833 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5834 * and set it to a reasonable value instead.
5836 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5837 reg_val
&= 0xffffff00;
5838 reg_val
|= 0x00000030;
5839 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5841 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5842 reg_val
&= 0x8cffffff;
5843 reg_val
= 0x8c000000;
5844 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5846 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5847 reg_val
&= 0xffffff00;
5848 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5850 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5851 reg_val
&= 0x00ffffff;
5852 reg_val
|= 0xb0000000;
5853 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5856 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5857 struct intel_link_m_n
*m_n
)
5859 struct drm_device
*dev
= crtc
->base
.dev
;
5860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5861 int pipe
= crtc
->pipe
;
5863 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5864 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5865 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5866 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5869 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5870 struct intel_link_m_n
*m_n
,
5871 struct intel_link_m_n
*m2_n2
)
5873 struct drm_device
*dev
= crtc
->base
.dev
;
5874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5875 int pipe
= crtc
->pipe
;
5876 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
5878 if (INTEL_INFO(dev
)->gen
>= 5) {
5879 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5880 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5881 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5882 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5883 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5884 * for gen < 8) and if DRRS is supported (to make sure the
5885 * registers are not unnecessarily accessed).
5887 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
5888 crtc
->config
->has_drrs
) {
5889 I915_WRITE(PIPE_DATA_M2(transcoder
),
5890 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5891 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5892 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5893 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5896 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5897 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5898 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5899 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5903 void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5905 if (crtc
->config
->has_pch_encoder
)
5906 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
5908 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
,
5909 &crtc
->config
->dp_m2_n2
);
5912 static void vlv_update_pll(struct intel_crtc
*crtc
,
5913 struct intel_crtc_state
*pipe_config
)
5918 * Enable DPIO clock input. We should never disable the reference
5919 * clock for pipe B, since VGA hotplug / manual detection depends
5922 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5923 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5924 /* We should never disable this, set it here for state tracking */
5925 if (crtc
->pipe
== PIPE_B
)
5926 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5927 dpll
|= DPLL_VCO_ENABLE
;
5928 pipe_config
->dpll_hw_state
.dpll
= dpll
;
5930 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
5931 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5932 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
5935 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
5936 const struct intel_crtc_state
*pipe_config
)
5938 struct drm_device
*dev
= crtc
->base
.dev
;
5939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5940 int pipe
= crtc
->pipe
;
5942 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5943 u32 coreclk
, reg_val
;
5945 mutex_lock(&dev_priv
->dpio_lock
);
5947 bestn
= pipe_config
->dpll
.n
;
5948 bestm1
= pipe_config
->dpll
.m1
;
5949 bestm2
= pipe_config
->dpll
.m2
;
5950 bestp1
= pipe_config
->dpll
.p1
;
5951 bestp2
= pipe_config
->dpll
.p2
;
5953 /* See eDP HDMI DPIO driver vbios notes doc */
5955 /* PLL B needs special handling */
5957 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5959 /* Set up Tx target for periodic Rcomp update */
5960 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5962 /* Disable target IRef on PLL */
5963 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5964 reg_val
&= 0x00ffffff;
5965 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5967 /* Disable fast lock */
5968 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5970 /* Set idtafcrecal before PLL is enabled */
5971 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5972 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5973 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5974 mdiv
|= (1 << DPIO_K_SHIFT
);
5977 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5978 * but we don't support that).
5979 * Note: don't use the DAC post divider as it seems unstable.
5981 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5982 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5984 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5985 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5987 /* Set HBR and RBR LPF coefficients */
5988 if (pipe_config
->port_clock
== 162000 ||
5989 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
5990 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
5991 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5994 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5997 if (pipe_config
->has_dp_encoder
) {
5998 /* Use SSC source */
6000 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6003 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6005 } else { /* HDMI or VGA */
6006 /* Use bend source */
6008 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6011 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6015 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
6016 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
6017 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
6018 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
6019 coreclk
|= 0x01000000;
6020 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
6022 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
6023 mutex_unlock(&dev_priv
->dpio_lock
);
6026 static void chv_update_pll(struct intel_crtc
*crtc
,
6027 struct intel_crtc_state
*pipe_config
)
6029 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
6030 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
6032 if (crtc
->pipe
!= PIPE_A
)
6033 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6035 pipe_config
->dpll_hw_state
.dpll_md
=
6036 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6039 static void chv_prepare_pll(struct intel_crtc
*crtc
,
6040 const struct intel_crtc_state
*pipe_config
)
6042 struct drm_device
*dev
= crtc
->base
.dev
;
6043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6044 int pipe
= crtc
->pipe
;
6045 int dpll_reg
= DPLL(crtc
->pipe
);
6046 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6047 u32 loopfilter
, intcoeff
;
6048 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
6051 bestn
= pipe_config
->dpll
.n
;
6052 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
6053 bestm1
= pipe_config
->dpll
.m1
;
6054 bestm2
= pipe_config
->dpll
.m2
>> 22;
6055 bestp1
= pipe_config
->dpll
.p1
;
6056 bestp2
= pipe_config
->dpll
.p2
;
6059 * Enable Refclk and SSC
6061 I915_WRITE(dpll_reg
,
6062 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
6064 mutex_lock(&dev_priv
->dpio_lock
);
6066 /* p1 and p2 divider */
6067 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
6068 5 << DPIO_CHV_S1_DIV_SHIFT
|
6069 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
6070 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
6071 1 << DPIO_CHV_K_DIV_SHIFT
);
6073 /* Feedback post-divider - m2 */
6074 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
6076 /* Feedback refclk divider - n and m1 */
6077 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
6078 DPIO_CHV_M1_DIV_BY_2
|
6079 1 << DPIO_CHV_N_DIV_SHIFT
);
6081 /* M2 fraction division */
6082 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
6084 /* M2 fraction division enable */
6085 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
6086 DPIO_CHV_FRAC_DIV_EN
|
6087 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
6090 refclk
= i9xx_get_refclk(crtc
, 0);
6091 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
6092 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
6093 if (refclk
== 100000)
6095 else if (refclk
== 38400)
6099 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
6100 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
6103 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
6104 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
6107 mutex_unlock(&dev_priv
->dpio_lock
);
6111 * vlv_force_pll_on - forcibly enable just the PLL
6112 * @dev_priv: i915 private structure
6113 * @pipe: pipe PLL to enable
6114 * @dpll: PLL configuration
6116 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6117 * in cases where we need the PLL enabled even when @pipe is not going to
6120 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
6121 const struct dpll
*dpll
)
6123 struct intel_crtc
*crtc
=
6124 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
6125 struct intel_crtc_state pipe_config
= {
6126 .pixel_multiplier
= 1,
6130 if (IS_CHERRYVIEW(dev
)) {
6131 chv_update_pll(crtc
, &pipe_config
);
6132 chv_prepare_pll(crtc
, &pipe_config
);
6133 chv_enable_pll(crtc
, &pipe_config
);
6135 vlv_update_pll(crtc
, &pipe_config
);
6136 vlv_prepare_pll(crtc
, &pipe_config
);
6137 vlv_enable_pll(crtc
, &pipe_config
);
6142 * vlv_force_pll_off - forcibly disable just the PLL
6143 * @dev_priv: i915 private structure
6144 * @pipe: pipe PLL to disable
6146 * Disable the PLL for @pipe. To be used in cases where we need
6147 * the PLL enabled even when @pipe is not going to be enabled.
6149 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
6151 if (IS_CHERRYVIEW(dev
))
6152 chv_disable_pll(to_i915(dev
), pipe
);
6154 vlv_disable_pll(to_i915(dev
), pipe
);
6157 static void i9xx_update_pll(struct intel_crtc
*crtc
,
6158 struct intel_crtc_state
*crtc_state
,
6159 intel_clock_t
*reduced_clock
,
6162 struct drm_device
*dev
= crtc
->base
.dev
;
6163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6166 struct dpll
*clock
= &crtc_state
->dpll
;
6168 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6170 is_sdvo
= intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
) ||
6171 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
);
6173 dpll
= DPLL_VGA_MODE_DIS
;
6175 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
6176 dpll
|= DPLLB_MODE_LVDS
;
6178 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6180 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6181 dpll
|= (crtc_state
->pixel_multiplier
- 1)
6182 << SDVO_MULTIPLIER_SHIFT_HIRES
;
6186 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6188 if (crtc_state
->has_dp_encoder
)
6189 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6191 /* compute bitmask from p1 value */
6192 if (IS_PINEVIEW(dev
))
6193 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
6195 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6196 if (IS_G4X(dev
) && reduced_clock
)
6197 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6199 switch (clock
->p2
) {
6201 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6204 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6207 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6210 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6213 if (INTEL_INFO(dev
)->gen
>= 4)
6214 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
6216 if (crtc_state
->sdvo_tv_clock
)
6217 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
6218 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6219 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6220 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6222 dpll
|= PLL_REF_INPUT_DREFCLK
;
6224 dpll
|= DPLL_VCO_ENABLE
;
6225 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6227 if (INTEL_INFO(dev
)->gen
>= 4) {
6228 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
6229 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6230 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
6234 static void i8xx_update_pll(struct intel_crtc
*crtc
,
6235 struct intel_crtc_state
*crtc_state
,
6236 intel_clock_t
*reduced_clock
,
6239 struct drm_device
*dev
= crtc
->base
.dev
;
6240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6242 struct dpll
*clock
= &crtc_state
->dpll
;
6244 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6246 dpll
= DPLL_VGA_MODE_DIS
;
6248 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
6249 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6252 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
6254 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6256 dpll
|= PLL_P2_DIVIDE_BY_4
;
6259 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
6260 dpll
|= DPLL_DVO_2X_MODE
;
6262 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6263 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6264 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6266 dpll
|= PLL_REF_INPUT_DREFCLK
;
6268 dpll
|= DPLL_VCO_ENABLE
;
6269 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6272 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
6274 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6276 enum pipe pipe
= intel_crtc
->pipe
;
6277 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
6278 struct drm_display_mode
*adjusted_mode
=
6279 &intel_crtc
->config
->base
.adjusted_mode
;
6280 uint32_t crtc_vtotal
, crtc_vblank_end
;
6283 /* We need to be careful not to changed the adjusted mode, for otherwise
6284 * the hw state checker will get angry at the mismatch. */
6285 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
6286 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
6288 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6289 /* the chip adds 2 halflines automatically */
6291 crtc_vblank_end
-= 1;
6293 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6294 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
6296 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
6297 adjusted_mode
->crtc_htotal
/ 2;
6299 vsyncshift
+= adjusted_mode
->crtc_htotal
;
6302 if (INTEL_INFO(dev
)->gen
> 3)
6303 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
6305 I915_WRITE(HTOTAL(cpu_transcoder
),
6306 (adjusted_mode
->crtc_hdisplay
- 1) |
6307 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6308 I915_WRITE(HBLANK(cpu_transcoder
),
6309 (adjusted_mode
->crtc_hblank_start
- 1) |
6310 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6311 I915_WRITE(HSYNC(cpu_transcoder
),
6312 (adjusted_mode
->crtc_hsync_start
- 1) |
6313 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6315 I915_WRITE(VTOTAL(cpu_transcoder
),
6316 (adjusted_mode
->crtc_vdisplay
- 1) |
6317 ((crtc_vtotal
- 1) << 16));
6318 I915_WRITE(VBLANK(cpu_transcoder
),
6319 (adjusted_mode
->crtc_vblank_start
- 1) |
6320 ((crtc_vblank_end
- 1) << 16));
6321 I915_WRITE(VSYNC(cpu_transcoder
),
6322 (adjusted_mode
->crtc_vsync_start
- 1) |
6323 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6325 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6326 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6327 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6329 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
6330 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
6331 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
6333 /* pipesrc controls the size that is scaled from, which should
6334 * always be the user's requested size.
6336 I915_WRITE(PIPESRC(pipe
),
6337 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
6338 (intel_crtc
->config
->pipe_src_h
- 1));
6341 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
6342 struct intel_crtc_state
*pipe_config
)
6344 struct drm_device
*dev
= crtc
->base
.dev
;
6345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6346 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6349 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
6350 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
6351 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
6352 tmp
= I915_READ(HBLANK(cpu_transcoder
));
6353 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
6354 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6355 tmp
= I915_READ(HSYNC(cpu_transcoder
));
6356 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
6357 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6359 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
6360 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
6361 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
6362 tmp
= I915_READ(VBLANK(cpu_transcoder
));
6363 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
6364 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6365 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6366 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6367 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6369 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6370 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6371 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
6372 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
6375 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6376 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6377 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6379 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
6380 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
6383 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6384 struct intel_crtc_state
*pipe_config
)
6386 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
6387 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
6388 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
6389 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
6391 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
6392 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
6393 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
6394 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
6396 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
6398 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
6399 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
6402 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6404 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6410 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6411 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6412 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6414 if (intel_crtc
->config
->double_wide
)
6415 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6417 /* only g4x and later have fancy bpc/dither controls */
6418 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6419 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6420 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
6421 pipeconf
|= PIPECONF_DITHER_EN
|
6422 PIPECONF_DITHER_TYPE_SP
;
6424 switch (intel_crtc
->config
->pipe_bpp
) {
6426 pipeconf
|= PIPECONF_6BPC
;
6429 pipeconf
|= PIPECONF_8BPC
;
6432 pipeconf
|= PIPECONF_10BPC
;
6435 /* Case prevented by intel_choose_pipe_bpp_dither. */
6440 if (HAS_PIPE_CXSR(dev
)) {
6441 if (intel_crtc
->lowfreq_avail
) {
6442 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6443 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6445 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6449 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6450 if (INTEL_INFO(dev
)->gen
< 4 ||
6451 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6452 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6454 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6456 pipeconf
|= PIPECONF_PROGRESSIVE
;
6458 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
6459 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6461 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6462 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6465 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
6466 struct intel_crtc_state
*crtc_state
)
6468 struct drm_device
*dev
= crtc
->base
.dev
;
6469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6470 int refclk
, num_connectors
= 0;
6471 intel_clock_t clock
, reduced_clock
;
6472 bool ok
, has_reduced_clock
= false;
6473 bool is_lvds
= false, is_dsi
= false;
6474 struct intel_encoder
*encoder
;
6475 const intel_limit_t
*limit
;
6477 for_each_intel_encoder(dev
, encoder
) {
6478 if (encoder
->new_crtc
!= crtc
)
6481 switch (encoder
->type
) {
6482 case INTEL_OUTPUT_LVDS
:
6485 case INTEL_OUTPUT_DSI
:
6498 if (!crtc_state
->clock_set
) {
6499 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6502 * Returns a set of divisors for the desired target clock with
6503 * the given refclk, or FALSE. The returned values represent
6504 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6507 limit
= intel_limit(crtc
, refclk
);
6508 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6509 crtc_state
->port_clock
,
6510 refclk
, NULL
, &clock
);
6512 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6516 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6518 * Ensure we match the reduced clock's P to the target
6519 * clock. If the clocks don't match, we can't switch
6520 * the display clock by using the FP0/FP1. In such case
6521 * we will disable the LVDS downclock feature.
6524 dev_priv
->display
.find_dpll(limit
, crtc
,
6525 dev_priv
->lvds_downclock
,
6529 /* Compat-code for transition, will disappear. */
6530 crtc_state
->dpll
.n
= clock
.n
;
6531 crtc_state
->dpll
.m1
= clock
.m1
;
6532 crtc_state
->dpll
.m2
= clock
.m2
;
6533 crtc_state
->dpll
.p1
= clock
.p1
;
6534 crtc_state
->dpll
.p2
= clock
.p2
;
6538 i8xx_update_pll(crtc
, crtc_state
,
6539 has_reduced_clock
? &reduced_clock
: NULL
,
6541 } else if (IS_CHERRYVIEW(dev
)) {
6542 chv_update_pll(crtc
, crtc_state
);
6543 } else if (IS_VALLEYVIEW(dev
)) {
6544 vlv_update_pll(crtc
, crtc_state
);
6546 i9xx_update_pll(crtc
, crtc_state
,
6547 has_reduced_clock
? &reduced_clock
: NULL
,
6554 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6555 struct intel_crtc_state
*pipe_config
)
6557 struct drm_device
*dev
= crtc
->base
.dev
;
6558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6561 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6564 tmp
= I915_READ(PFIT_CONTROL
);
6565 if (!(tmp
& PFIT_ENABLE
))
6568 /* Check whether the pfit is attached to our pipe. */
6569 if (INTEL_INFO(dev
)->gen
< 4) {
6570 if (crtc
->pipe
!= PIPE_B
)
6573 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6577 pipe_config
->gmch_pfit
.control
= tmp
;
6578 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6579 if (INTEL_INFO(dev
)->gen
< 5)
6580 pipe_config
->gmch_pfit
.lvds_border_bits
=
6581 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6584 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6585 struct intel_crtc_state
*pipe_config
)
6587 struct drm_device
*dev
= crtc
->base
.dev
;
6588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6589 int pipe
= pipe_config
->cpu_transcoder
;
6590 intel_clock_t clock
;
6592 int refclk
= 100000;
6594 /* In case of MIPI DPLL will not even be used */
6595 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6598 mutex_lock(&dev_priv
->dpio_lock
);
6599 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6600 mutex_unlock(&dev_priv
->dpio_lock
);
6602 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6603 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6604 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6605 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6606 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6608 vlv_clock(refclk
, &clock
);
6610 /* clock.dot is the fast clock */
6611 pipe_config
->port_clock
= clock
.dot
/ 5;
6615 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
6616 struct intel_initial_plane_config
*plane_config
)
6618 struct drm_device
*dev
= crtc
->base
.dev
;
6619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6620 u32 val
, base
, offset
;
6621 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6622 int fourcc
, pixel_format
;
6624 struct drm_framebuffer
*fb
;
6625 struct intel_framebuffer
*intel_fb
;
6627 val
= I915_READ(DSPCNTR(plane
));
6628 if (!(val
& DISPLAY_PLANE_ENABLE
))
6631 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6633 DRM_DEBUG_KMS("failed to alloc fb\n");
6637 fb
= &intel_fb
->base
;
6639 if (INTEL_INFO(dev
)->gen
>= 4)
6640 if (val
& DISPPLANE_TILED
)
6641 plane_config
->tiling
= I915_TILING_X
;
6643 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6644 fourcc
= i9xx_format_to_fourcc(pixel_format
);
6645 fb
->pixel_format
= fourcc
;
6646 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
6648 if (INTEL_INFO(dev
)->gen
>= 4) {
6649 if (plane_config
->tiling
)
6650 offset
= I915_READ(DSPTILEOFF(plane
));
6652 offset
= I915_READ(DSPLINOFF(plane
));
6653 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6655 base
= I915_READ(DSPADDR(plane
));
6657 plane_config
->base
= base
;
6659 val
= I915_READ(PIPESRC(pipe
));
6660 fb
->width
= ((val
>> 16) & 0xfff) + 1;
6661 fb
->height
= ((val
>> 0) & 0xfff) + 1;
6663 val
= I915_READ(DSPSTRIDE(pipe
));
6664 fb
->pitches
[0] = val
& 0xffffffc0;
6666 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
6667 plane_config
->tiling
);
6669 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
6671 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6672 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
6673 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
6674 plane_config
->size
);
6676 crtc
->base
.primary
->fb
= fb
;
6679 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6680 struct intel_crtc_state
*pipe_config
)
6682 struct drm_device
*dev
= crtc
->base
.dev
;
6683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6684 int pipe
= pipe_config
->cpu_transcoder
;
6685 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6686 intel_clock_t clock
;
6687 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6688 int refclk
= 100000;
6690 mutex_lock(&dev_priv
->dpio_lock
);
6691 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6692 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6693 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6694 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6695 mutex_unlock(&dev_priv
->dpio_lock
);
6697 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6698 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6699 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6700 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6701 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6703 chv_clock(refclk
, &clock
);
6705 /* clock.dot is the fast clock */
6706 pipe_config
->port_clock
= clock
.dot
/ 5;
6709 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6710 struct intel_crtc_state
*pipe_config
)
6712 struct drm_device
*dev
= crtc
->base
.dev
;
6713 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6716 if (!intel_display_power_is_enabled(dev_priv
,
6717 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6720 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6721 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6723 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6724 if (!(tmp
& PIPECONF_ENABLE
))
6727 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6728 switch (tmp
& PIPECONF_BPC_MASK
) {
6730 pipe_config
->pipe_bpp
= 18;
6733 pipe_config
->pipe_bpp
= 24;
6735 case PIPECONF_10BPC
:
6736 pipe_config
->pipe_bpp
= 30;
6743 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6744 pipe_config
->limited_color_range
= true;
6746 if (INTEL_INFO(dev
)->gen
< 4)
6747 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6749 intel_get_pipe_timings(crtc
, pipe_config
);
6751 i9xx_get_pfit_config(crtc
, pipe_config
);
6753 if (INTEL_INFO(dev
)->gen
>= 4) {
6754 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6755 pipe_config
->pixel_multiplier
=
6756 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6757 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6758 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6759 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6760 tmp
= I915_READ(DPLL(crtc
->pipe
));
6761 pipe_config
->pixel_multiplier
=
6762 ((tmp
& SDVO_MULTIPLIER_MASK
)
6763 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6765 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6766 * port and will be fixed up in the encoder->get_config
6768 pipe_config
->pixel_multiplier
= 1;
6770 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6771 if (!IS_VALLEYVIEW(dev
)) {
6773 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6774 * on 830. Filter it out here so that we don't
6775 * report errors due to that.
6778 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
6780 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6781 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6783 /* Mask out read-only status bits. */
6784 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6785 DPLL_PORTC_READY_MASK
|
6786 DPLL_PORTB_READY_MASK
);
6789 if (IS_CHERRYVIEW(dev
))
6790 chv_crtc_clock_get(crtc
, pipe_config
);
6791 else if (IS_VALLEYVIEW(dev
))
6792 vlv_crtc_clock_get(crtc
, pipe_config
);
6794 i9xx_crtc_clock_get(crtc
, pipe_config
);
6799 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6802 struct intel_encoder
*encoder
;
6804 bool has_lvds
= false;
6805 bool has_cpu_edp
= false;
6806 bool has_panel
= false;
6807 bool has_ck505
= false;
6808 bool can_ssc
= false;
6810 /* We need to take the global config into account */
6811 for_each_intel_encoder(dev
, encoder
) {
6812 switch (encoder
->type
) {
6813 case INTEL_OUTPUT_LVDS
:
6817 case INTEL_OUTPUT_EDP
:
6819 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6827 if (HAS_PCH_IBX(dev
)) {
6828 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6829 can_ssc
= has_ck505
;
6835 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6836 has_panel
, has_lvds
, has_ck505
);
6838 /* Ironlake: try to setup display ref clock before DPLL
6839 * enabling. This is only under driver's control after
6840 * PCH B stepping, previous chipset stepping should be
6841 * ignoring this setting.
6843 val
= I915_READ(PCH_DREF_CONTROL
);
6845 /* As we must carefully and slowly disable/enable each source in turn,
6846 * compute the final state we want first and check if we need to
6847 * make any changes at all.
6850 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6852 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6854 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6856 final
&= ~DREF_SSC_SOURCE_MASK
;
6857 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6858 final
&= ~DREF_SSC1_ENABLE
;
6861 final
|= DREF_SSC_SOURCE_ENABLE
;
6863 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6864 final
|= DREF_SSC1_ENABLE
;
6867 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6868 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6870 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6872 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6874 final
|= DREF_SSC_SOURCE_DISABLE
;
6875 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6881 /* Always enable nonspread source */
6882 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6885 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6887 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6890 val
&= ~DREF_SSC_SOURCE_MASK
;
6891 val
|= DREF_SSC_SOURCE_ENABLE
;
6893 /* SSC must be turned on before enabling the CPU output */
6894 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6895 DRM_DEBUG_KMS("Using SSC on panel\n");
6896 val
|= DREF_SSC1_ENABLE
;
6898 val
&= ~DREF_SSC1_ENABLE
;
6900 /* Get SSC going before enabling the outputs */
6901 I915_WRITE(PCH_DREF_CONTROL
, val
);
6902 POSTING_READ(PCH_DREF_CONTROL
);
6905 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6907 /* Enable CPU source on CPU attached eDP */
6909 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6910 DRM_DEBUG_KMS("Using SSC on eDP\n");
6911 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6913 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6915 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6917 I915_WRITE(PCH_DREF_CONTROL
, val
);
6918 POSTING_READ(PCH_DREF_CONTROL
);
6921 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6923 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6925 /* Turn off CPU output */
6926 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6928 I915_WRITE(PCH_DREF_CONTROL
, val
);
6929 POSTING_READ(PCH_DREF_CONTROL
);
6932 /* Turn off the SSC source */
6933 val
&= ~DREF_SSC_SOURCE_MASK
;
6934 val
|= DREF_SSC_SOURCE_DISABLE
;
6937 val
&= ~DREF_SSC1_ENABLE
;
6939 I915_WRITE(PCH_DREF_CONTROL
, val
);
6940 POSTING_READ(PCH_DREF_CONTROL
);
6944 BUG_ON(val
!= final
);
6947 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6951 tmp
= I915_READ(SOUTH_CHICKEN2
);
6952 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6953 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6955 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6956 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6957 DRM_ERROR("FDI mPHY reset assert timeout\n");
6959 tmp
= I915_READ(SOUTH_CHICKEN2
);
6960 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6961 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6963 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6964 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6965 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6968 /* WaMPhyProgramming:hsw */
6969 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6973 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6974 tmp
&= ~(0xFF << 24);
6975 tmp
|= (0x12 << 24);
6976 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6978 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6980 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6982 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6984 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6986 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6987 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6988 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6990 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6991 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6992 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6994 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6997 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6999 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
7002 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
7004 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
7007 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
7009 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
7012 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
7014 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
7015 tmp
&= ~(0xFF << 16);
7016 tmp
|= (0x1C << 16);
7017 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
7019 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
7020 tmp
&= ~(0xFF << 16);
7021 tmp
|= (0x1C << 16);
7022 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
7024 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
7026 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
7028 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
7030 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
7032 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
7033 tmp
&= ~(0xF << 28);
7035 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
7037 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
7038 tmp
&= ~(0xF << 28);
7040 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
7043 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7044 * Programming" based on the parameters passed:
7045 * - Sequence to enable CLKOUT_DP
7046 * - Sequence to enable CLKOUT_DP without spread
7047 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7049 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
7052 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7055 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
7057 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
7058 with_fdi
, "LP PCH doesn't have FDI\n"))
7061 mutex_lock(&dev_priv
->dpio_lock
);
7063 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7064 tmp
&= ~SBI_SSCCTL_DISABLE
;
7065 tmp
|= SBI_SSCCTL_PATHALT
;
7066 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7071 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7072 tmp
&= ~SBI_SSCCTL_PATHALT
;
7073 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7076 lpt_reset_fdi_mphy(dev_priv
);
7077 lpt_program_fdi_mphy(dev_priv
);
7081 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7082 SBI_GEN0
: SBI_DBUFF0
;
7083 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7084 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7085 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7087 mutex_unlock(&dev_priv
->dpio_lock
);
7090 /* Sequence to disable CLKOUT_DP */
7091 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
7093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7096 mutex_lock(&dev_priv
->dpio_lock
);
7098 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7099 SBI_GEN0
: SBI_DBUFF0
;
7100 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7101 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7102 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7104 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7105 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
7106 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
7107 tmp
|= SBI_SSCCTL_PATHALT
;
7108 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7111 tmp
|= SBI_SSCCTL_DISABLE
;
7112 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7115 mutex_unlock(&dev_priv
->dpio_lock
);
7118 static void lpt_init_pch_refclk(struct drm_device
*dev
)
7120 struct intel_encoder
*encoder
;
7121 bool has_vga
= false;
7123 for_each_intel_encoder(dev
, encoder
) {
7124 switch (encoder
->type
) {
7125 case INTEL_OUTPUT_ANALOG
:
7134 lpt_enable_clkout_dp(dev
, true, true);
7136 lpt_disable_clkout_dp(dev
);
7140 * Initialize reference clocks when the driver loads
7142 void intel_init_pch_refclk(struct drm_device
*dev
)
7144 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
7145 ironlake_init_pch_refclk(dev
);
7146 else if (HAS_PCH_LPT(dev
))
7147 lpt_init_pch_refclk(dev
);
7150 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
7152 struct drm_device
*dev
= crtc
->dev
;
7153 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7154 struct intel_encoder
*encoder
;
7155 int num_connectors
= 0;
7156 bool is_lvds
= false;
7158 for_each_intel_encoder(dev
, encoder
) {
7159 if (encoder
->new_crtc
!= to_intel_crtc(crtc
))
7162 switch (encoder
->type
) {
7163 case INTEL_OUTPUT_LVDS
:
7172 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7173 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7174 dev_priv
->vbt
.lvds_ssc_freq
);
7175 return dev_priv
->vbt
.lvds_ssc_freq
;
7181 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
7183 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
7184 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7185 int pipe
= intel_crtc
->pipe
;
7190 switch (intel_crtc
->config
->pipe_bpp
) {
7192 val
|= PIPECONF_6BPC
;
7195 val
|= PIPECONF_8BPC
;
7198 val
|= PIPECONF_10BPC
;
7201 val
|= PIPECONF_12BPC
;
7204 /* Case prevented by intel_choose_pipe_bpp_dither. */
7208 if (intel_crtc
->config
->dither
)
7209 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7211 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7212 val
|= PIPECONF_INTERLACED_ILK
;
7214 val
|= PIPECONF_PROGRESSIVE
;
7216 if (intel_crtc
->config
->limited_color_range
)
7217 val
|= PIPECONF_COLOR_RANGE_SELECT
;
7219 I915_WRITE(PIPECONF(pipe
), val
);
7220 POSTING_READ(PIPECONF(pipe
));
7224 * Set up the pipe CSC unit.
7226 * Currently only full range RGB to limited range RGB conversion
7227 * is supported, but eventually this should handle various
7228 * RGB<->YCbCr scenarios as well.
7230 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
7232 struct drm_device
*dev
= crtc
->dev
;
7233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7234 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7235 int pipe
= intel_crtc
->pipe
;
7236 uint16_t coeff
= 0x7800; /* 1.0 */
7239 * TODO: Check what kind of values actually come out of the pipe
7240 * with these coeff/postoff values and adjust to get the best
7241 * accuracy. Perhaps we even need to take the bpc value into
7245 if (intel_crtc
->config
->limited_color_range
)
7246 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7249 * GY/GU and RY/RU should be the other way around according
7250 * to BSpec, but reality doesn't agree. Just set them up in
7251 * a way that results in the correct picture.
7253 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
7254 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
7256 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
7257 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
7259 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
7260 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
7262 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
7263 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
7264 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
7266 if (INTEL_INFO(dev
)->gen
> 6) {
7267 uint16_t postoff
= 0;
7269 if (intel_crtc
->config
->limited_color_range
)
7270 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
7272 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
7273 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
7274 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
7276 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
7278 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
7280 if (intel_crtc
->config
->limited_color_range
)
7281 mode
|= CSC_BLACK_SCREEN_OFFSET
;
7283 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
7287 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
7289 struct drm_device
*dev
= crtc
->dev
;
7290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7291 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7292 enum pipe pipe
= intel_crtc
->pipe
;
7293 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7298 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
7299 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7301 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7302 val
|= PIPECONF_INTERLACED_ILK
;
7304 val
|= PIPECONF_PROGRESSIVE
;
7306 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
7307 POSTING_READ(PIPECONF(cpu_transcoder
));
7309 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
7310 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
7312 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
7315 switch (intel_crtc
->config
->pipe_bpp
) {
7317 val
|= PIPEMISC_DITHER_6_BPC
;
7320 val
|= PIPEMISC_DITHER_8_BPC
;
7323 val
|= PIPEMISC_DITHER_10_BPC
;
7326 val
|= PIPEMISC_DITHER_12_BPC
;
7329 /* Case prevented by pipe_config_set_bpp. */
7333 if (intel_crtc
->config
->dither
)
7334 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
7336 I915_WRITE(PIPEMISC(pipe
), val
);
7340 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
7341 struct intel_crtc_state
*crtc_state
,
7342 intel_clock_t
*clock
,
7343 bool *has_reduced_clock
,
7344 intel_clock_t
*reduced_clock
)
7346 struct drm_device
*dev
= crtc
->dev
;
7347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7348 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7350 const intel_limit_t
*limit
;
7351 bool ret
, is_lvds
= false;
7353 is_lvds
= intel_pipe_will_have_type(intel_crtc
, INTEL_OUTPUT_LVDS
);
7355 refclk
= ironlake_get_refclk(crtc
);
7358 * Returns a set of divisors for the desired target clock with the given
7359 * refclk, or FALSE. The returned values represent the clock equation:
7360 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7362 limit
= intel_limit(intel_crtc
, refclk
);
7363 ret
= dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7364 crtc_state
->port_clock
,
7365 refclk
, NULL
, clock
);
7369 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7371 * Ensure we match the reduced clock's P to the target clock.
7372 * If the clocks don't match, we can't switch the display clock
7373 * by using the FP0/FP1. In such case we will disable the LVDS
7374 * downclock feature.
7376 *has_reduced_clock
=
7377 dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7378 dev_priv
->lvds_downclock
,
7386 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7389 * Account for spread spectrum to avoid
7390 * oversubscribing the link. Max center spread
7391 * is 2.5%; use 5% for safety's sake.
7393 u32 bps
= target_clock
* bpp
* 21 / 20;
7394 return DIV_ROUND_UP(bps
, link_bw
* 8);
7397 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7399 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7402 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7403 struct intel_crtc_state
*crtc_state
,
7405 intel_clock_t
*reduced_clock
, u32
*fp2
)
7407 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7408 struct drm_device
*dev
= crtc
->dev
;
7409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7410 struct intel_encoder
*intel_encoder
;
7412 int factor
, num_connectors
= 0;
7413 bool is_lvds
= false, is_sdvo
= false;
7415 for_each_intel_encoder(dev
, intel_encoder
) {
7416 if (intel_encoder
->new_crtc
!= to_intel_crtc(crtc
))
7419 switch (intel_encoder
->type
) {
7420 case INTEL_OUTPUT_LVDS
:
7423 case INTEL_OUTPUT_SDVO
:
7424 case INTEL_OUTPUT_HDMI
:
7434 /* Enable autotuning of the PLL clock (if permissible) */
7437 if ((intel_panel_use_ssc(dev_priv
) &&
7438 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7439 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7441 } else if (crtc_state
->sdvo_tv_clock
)
7444 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
7447 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7453 dpll
|= DPLLB_MODE_LVDS
;
7455 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7457 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7458 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7461 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7462 if (crtc_state
->has_dp_encoder
)
7463 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7465 /* compute bitmask from p1 value */
7466 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7468 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7470 switch (crtc_state
->dpll
.p2
) {
7472 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7475 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7478 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7481 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7485 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7486 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7488 dpll
|= PLL_REF_INPUT_DREFCLK
;
7490 return dpll
| DPLL_VCO_ENABLE
;
7493 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
7494 struct intel_crtc_state
*crtc_state
)
7496 struct drm_device
*dev
= crtc
->base
.dev
;
7497 intel_clock_t clock
, reduced_clock
;
7498 u32 dpll
= 0, fp
= 0, fp2
= 0;
7499 bool ok
, has_reduced_clock
= false;
7500 bool is_lvds
= false;
7501 struct intel_shared_dpll
*pll
;
7503 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
7505 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7506 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7508 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
7509 &has_reduced_clock
, &reduced_clock
);
7510 if (!ok
&& !crtc_state
->clock_set
) {
7511 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7514 /* Compat-code for transition, will disappear. */
7515 if (!crtc_state
->clock_set
) {
7516 crtc_state
->dpll
.n
= clock
.n
;
7517 crtc_state
->dpll
.m1
= clock
.m1
;
7518 crtc_state
->dpll
.m2
= clock
.m2
;
7519 crtc_state
->dpll
.p1
= clock
.p1
;
7520 crtc_state
->dpll
.p2
= clock
.p2
;
7523 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7524 if (crtc_state
->has_pch_encoder
) {
7525 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7526 if (has_reduced_clock
)
7527 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7529 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
7530 &fp
, &reduced_clock
,
7531 has_reduced_clock
? &fp2
: NULL
);
7533 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7534 crtc_state
->dpll_hw_state
.fp0
= fp
;
7535 if (has_reduced_clock
)
7536 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7538 crtc_state
->dpll_hw_state
.fp1
= fp
;
7540 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
7542 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7543 pipe_name(crtc
->pipe
));
7548 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7549 crtc
->lowfreq_avail
= true;
7551 crtc
->lowfreq_avail
= false;
7556 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7557 struct intel_link_m_n
*m_n
)
7559 struct drm_device
*dev
= crtc
->base
.dev
;
7560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7561 enum pipe pipe
= crtc
->pipe
;
7563 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7564 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7565 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7567 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7568 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7569 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7572 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7573 enum transcoder transcoder
,
7574 struct intel_link_m_n
*m_n
,
7575 struct intel_link_m_n
*m2_n2
)
7577 struct drm_device
*dev
= crtc
->base
.dev
;
7578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7579 enum pipe pipe
= crtc
->pipe
;
7581 if (INTEL_INFO(dev
)->gen
>= 5) {
7582 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7583 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7584 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7586 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7587 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7588 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7589 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7590 * gen < 8) and if DRRS is supported (to make sure the
7591 * registers are not unnecessarily read).
7593 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7594 crtc
->config
->has_drrs
) {
7595 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7596 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7597 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7599 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7600 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7601 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7604 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7605 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7606 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7608 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7609 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7610 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7614 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7615 struct intel_crtc_state
*pipe_config
)
7617 if (pipe_config
->has_pch_encoder
)
7618 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7620 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7621 &pipe_config
->dp_m_n
,
7622 &pipe_config
->dp_m2_n2
);
7625 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7626 struct intel_crtc_state
*pipe_config
)
7628 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7629 &pipe_config
->fdi_m_n
, NULL
);
7632 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
7633 struct intel_crtc_state
*pipe_config
)
7635 struct drm_device
*dev
= crtc
->base
.dev
;
7636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7639 tmp
= I915_READ(PS_CTL(crtc
->pipe
));
7641 if (tmp
& PS_ENABLE
) {
7642 pipe_config
->pch_pfit
.enabled
= true;
7643 pipe_config
->pch_pfit
.pos
= I915_READ(PS_WIN_POS(crtc
->pipe
));
7644 pipe_config
->pch_pfit
.size
= I915_READ(PS_WIN_SZ(crtc
->pipe
));
7649 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
7650 struct intel_initial_plane_config
*plane_config
)
7652 struct drm_device
*dev
= crtc
->base
.dev
;
7653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7654 u32 val
, base
, offset
, stride_mult
;
7655 int pipe
= crtc
->pipe
;
7656 int fourcc
, pixel_format
;
7658 struct drm_framebuffer
*fb
;
7659 struct intel_framebuffer
*intel_fb
;
7661 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7663 DRM_DEBUG_KMS("failed to alloc fb\n");
7667 fb
= &intel_fb
->base
;
7669 val
= I915_READ(PLANE_CTL(pipe
, 0));
7670 if (!(val
& PLANE_CTL_ENABLE
))
7673 if (val
& PLANE_CTL_TILED_MASK
)
7674 plane_config
->tiling
= I915_TILING_X
;
7676 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
7677 fourcc
= skl_format_to_fourcc(pixel_format
,
7678 val
& PLANE_CTL_ORDER_RGBX
,
7679 val
& PLANE_CTL_ALPHA_MASK
);
7680 fb
->pixel_format
= fourcc
;
7681 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7683 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
7684 plane_config
->base
= base
;
7686 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
7688 val
= I915_READ(PLANE_SIZE(pipe
, 0));
7689 fb
->height
= ((val
>> 16) & 0xfff) + 1;
7690 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
7692 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
7693 switch (plane_config
->tiling
) {
7694 case I915_TILING_NONE
:
7701 MISSING_CASE(plane_config
->tiling
);
7704 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
7706 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7707 plane_config
->tiling
);
7709 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7711 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7712 pipe_name(pipe
), fb
->width
, fb
->height
,
7713 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7714 plane_config
->size
);
7716 crtc
->base
.primary
->fb
= fb
;
7723 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7724 struct intel_crtc_state
*pipe_config
)
7726 struct drm_device
*dev
= crtc
->base
.dev
;
7727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7730 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7732 if (tmp
& PF_ENABLE
) {
7733 pipe_config
->pch_pfit
.enabled
= true;
7734 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7735 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7737 /* We currently do not free assignements of panel fitters on
7738 * ivb/hsw (since we don't use the higher upscaling modes which
7739 * differentiates them) so just WARN about this case for now. */
7741 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7742 PF_PIPE_SEL_IVB(crtc
->pipe
));
7748 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
7749 struct intel_initial_plane_config
*plane_config
)
7751 struct drm_device
*dev
= crtc
->base
.dev
;
7752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7753 u32 val
, base
, offset
;
7754 int pipe
= crtc
->pipe
;
7755 int fourcc
, pixel_format
;
7757 struct drm_framebuffer
*fb
;
7758 struct intel_framebuffer
*intel_fb
;
7760 val
= I915_READ(DSPCNTR(pipe
));
7761 if (!(val
& DISPLAY_PLANE_ENABLE
))
7764 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7766 DRM_DEBUG_KMS("failed to alloc fb\n");
7770 fb
= &intel_fb
->base
;
7772 if (INTEL_INFO(dev
)->gen
>= 4)
7773 if (val
& DISPPLANE_TILED
)
7774 plane_config
->tiling
= I915_TILING_X
;
7776 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7777 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7778 fb
->pixel_format
= fourcc
;
7779 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7781 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
7782 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7783 offset
= I915_READ(DSPOFFSET(pipe
));
7785 if (plane_config
->tiling
)
7786 offset
= I915_READ(DSPTILEOFF(pipe
));
7788 offset
= I915_READ(DSPLINOFF(pipe
));
7790 plane_config
->base
= base
;
7792 val
= I915_READ(PIPESRC(pipe
));
7793 fb
->width
= ((val
>> 16) & 0xfff) + 1;
7794 fb
->height
= ((val
>> 0) & 0xfff) + 1;
7796 val
= I915_READ(DSPSTRIDE(pipe
));
7797 fb
->pitches
[0] = val
& 0xffffffc0;
7799 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7800 plane_config
->tiling
);
7802 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7804 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7805 pipe_name(pipe
), fb
->width
, fb
->height
,
7806 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7807 plane_config
->size
);
7809 crtc
->base
.primary
->fb
= fb
;
7812 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7813 struct intel_crtc_state
*pipe_config
)
7815 struct drm_device
*dev
= crtc
->base
.dev
;
7816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7819 if (!intel_display_power_is_enabled(dev_priv
,
7820 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7823 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7824 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7826 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7827 if (!(tmp
& PIPECONF_ENABLE
))
7830 switch (tmp
& PIPECONF_BPC_MASK
) {
7832 pipe_config
->pipe_bpp
= 18;
7835 pipe_config
->pipe_bpp
= 24;
7837 case PIPECONF_10BPC
:
7838 pipe_config
->pipe_bpp
= 30;
7840 case PIPECONF_12BPC
:
7841 pipe_config
->pipe_bpp
= 36;
7847 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7848 pipe_config
->limited_color_range
= true;
7850 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7851 struct intel_shared_dpll
*pll
;
7853 pipe_config
->has_pch_encoder
= true;
7855 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7856 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7857 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7859 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7861 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7862 pipe_config
->shared_dpll
=
7863 (enum intel_dpll_id
) crtc
->pipe
;
7865 tmp
= I915_READ(PCH_DPLL_SEL
);
7866 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7867 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7869 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7872 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7874 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7875 &pipe_config
->dpll_hw_state
));
7877 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7878 pipe_config
->pixel_multiplier
=
7879 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7880 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7882 ironlake_pch_clock_get(crtc
, pipe_config
);
7884 pipe_config
->pixel_multiplier
= 1;
7887 intel_get_pipe_timings(crtc
, pipe_config
);
7889 ironlake_get_pfit_config(crtc
, pipe_config
);
7894 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7896 struct drm_device
*dev
= dev_priv
->dev
;
7897 struct intel_crtc
*crtc
;
7899 for_each_intel_crtc(dev
, crtc
)
7900 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7901 pipe_name(crtc
->pipe
));
7903 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7904 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7905 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7906 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7907 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7908 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7909 "CPU PWM1 enabled\n");
7910 if (IS_HASWELL(dev
))
7911 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7912 "CPU PWM2 enabled\n");
7913 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7914 "PCH PWM1 enabled\n");
7915 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7916 "Utility pin enabled\n");
7917 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7920 * In theory we can still leave IRQs enabled, as long as only the HPD
7921 * interrupts remain enabled. We used to check for that, but since it's
7922 * gen-specific and since we only disable LCPLL after we fully disable
7923 * the interrupts, the check below should be enough.
7925 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7928 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7930 struct drm_device
*dev
= dev_priv
->dev
;
7932 if (IS_HASWELL(dev
))
7933 return I915_READ(D_COMP_HSW
);
7935 return I915_READ(D_COMP_BDW
);
7938 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7940 struct drm_device
*dev
= dev_priv
->dev
;
7942 if (IS_HASWELL(dev
)) {
7943 mutex_lock(&dev_priv
->rps
.hw_lock
);
7944 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7946 DRM_ERROR("Failed to write to D_COMP\n");
7947 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7949 I915_WRITE(D_COMP_BDW
, val
);
7950 POSTING_READ(D_COMP_BDW
);
7955 * This function implements pieces of two sequences from BSpec:
7956 * - Sequence for display software to disable LCPLL
7957 * - Sequence for display software to allow package C8+
7958 * The steps implemented here are just the steps that actually touch the LCPLL
7959 * register. Callers should take care of disabling all the display engine
7960 * functions, doing the mode unset, fixing interrupts, etc.
7962 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7963 bool switch_to_fclk
, bool allow_power_down
)
7967 assert_can_disable_lcpll(dev_priv
);
7969 val
= I915_READ(LCPLL_CTL
);
7971 if (switch_to_fclk
) {
7972 val
|= LCPLL_CD_SOURCE_FCLK
;
7973 I915_WRITE(LCPLL_CTL
, val
);
7975 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7976 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7977 DRM_ERROR("Switching to FCLK failed\n");
7979 val
= I915_READ(LCPLL_CTL
);
7982 val
|= LCPLL_PLL_DISABLE
;
7983 I915_WRITE(LCPLL_CTL
, val
);
7984 POSTING_READ(LCPLL_CTL
);
7986 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7987 DRM_ERROR("LCPLL still locked\n");
7989 val
= hsw_read_dcomp(dev_priv
);
7990 val
|= D_COMP_COMP_DISABLE
;
7991 hsw_write_dcomp(dev_priv
, val
);
7994 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7996 DRM_ERROR("D_COMP RCOMP still in progress\n");
7998 if (allow_power_down
) {
7999 val
= I915_READ(LCPLL_CTL
);
8000 val
|= LCPLL_POWER_DOWN_ALLOW
;
8001 I915_WRITE(LCPLL_CTL
, val
);
8002 POSTING_READ(LCPLL_CTL
);
8007 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8010 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
8014 val
= I915_READ(LCPLL_CTL
);
8016 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
8017 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
8021 * Make sure we're not on PC8 state before disabling PC8, otherwise
8022 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8024 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
8026 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
8027 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
8028 I915_WRITE(LCPLL_CTL
, val
);
8029 POSTING_READ(LCPLL_CTL
);
8032 val
= hsw_read_dcomp(dev_priv
);
8033 val
|= D_COMP_COMP_FORCE
;
8034 val
&= ~D_COMP_COMP_DISABLE
;
8035 hsw_write_dcomp(dev_priv
, val
);
8037 val
= I915_READ(LCPLL_CTL
);
8038 val
&= ~LCPLL_PLL_DISABLE
;
8039 I915_WRITE(LCPLL_CTL
, val
);
8041 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
8042 DRM_ERROR("LCPLL not locked yet\n");
8044 if (val
& LCPLL_CD_SOURCE_FCLK
) {
8045 val
= I915_READ(LCPLL_CTL
);
8046 val
&= ~LCPLL_CD_SOURCE_FCLK
;
8047 I915_WRITE(LCPLL_CTL
, val
);
8049 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
8050 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
8051 DRM_ERROR("Switching back to LCPLL failed\n");
8054 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
8058 * Package states C8 and deeper are really deep PC states that can only be
8059 * reached when all the devices on the system allow it, so even if the graphics
8060 * device allows PC8+, it doesn't mean the system will actually get to these
8061 * states. Our driver only allows PC8+ when going into runtime PM.
8063 * The requirements for PC8+ are that all the outputs are disabled, the power
8064 * well is disabled and most interrupts are disabled, and these are also
8065 * requirements for runtime PM. When these conditions are met, we manually do
8066 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8067 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8070 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8071 * the state of some registers, so when we come back from PC8+ we need to
8072 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8073 * need to take care of the registers kept by RC6. Notice that this happens even
8074 * if we don't put the device in PCI D3 state (which is what currently happens
8075 * because of the runtime PM support).
8077 * For more, read "Display Sequences for Package C8" on the hardware
8080 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
8082 struct drm_device
*dev
= dev_priv
->dev
;
8085 DRM_DEBUG_KMS("Enabling package C8+\n");
8087 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
8088 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8089 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
8090 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8093 lpt_disable_clkout_dp(dev
);
8094 hsw_disable_lcpll(dev_priv
, true, true);
8097 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
8099 struct drm_device
*dev
= dev_priv
->dev
;
8102 DRM_DEBUG_KMS("Disabling package C8+\n");
8104 hsw_restore_lcpll(dev_priv
);
8105 lpt_init_pch_refclk(dev
);
8107 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
8108 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8109 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
8110 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8113 intel_prepare_ddi(dev
);
8116 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
8117 struct intel_crtc_state
*crtc_state
)
8119 if (!intel_ddi_pll_select(crtc
, crtc_state
))
8122 crtc
->lowfreq_avail
= false;
8127 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8129 struct intel_crtc_state
*pipe_config
)
8131 u32 temp
, dpll_ctl1
;
8133 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
8134 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
8136 switch (pipe_config
->ddi_pll_sel
) {
8139 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8140 * of the shared DPLL framework and thus needs to be read out
8143 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
8144 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
8147 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
8150 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
8153 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
8158 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8160 struct intel_crtc_state
*pipe_config
)
8162 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
8164 switch (pipe_config
->ddi_pll_sel
) {
8165 case PORT_CLK_SEL_WRPLL1
:
8166 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
8168 case PORT_CLK_SEL_WRPLL2
:
8169 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
8174 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
8175 struct intel_crtc_state
*pipe_config
)
8177 struct drm_device
*dev
= crtc
->base
.dev
;
8178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8179 struct intel_shared_dpll
*pll
;
8183 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
8185 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
8187 if (IS_SKYLAKE(dev
))
8188 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
8190 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
8192 if (pipe_config
->shared_dpll
>= 0) {
8193 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8195 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8196 &pipe_config
->dpll_hw_state
));
8200 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8201 * DDI E. So just check whether this pipe is wired to DDI E and whether
8202 * the PCH transcoder is on.
8204 if (INTEL_INFO(dev
)->gen
< 9 &&
8205 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
8206 pipe_config
->has_pch_encoder
= true;
8208 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
8209 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8210 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8212 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8216 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
8217 struct intel_crtc_state
*pipe_config
)
8219 struct drm_device
*dev
= crtc
->base
.dev
;
8220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8221 enum intel_display_power_domain pfit_domain
;
8224 if (!intel_display_power_is_enabled(dev_priv
,
8225 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8228 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8229 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8231 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
8232 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
8233 enum pipe trans_edp_pipe
;
8234 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
8236 WARN(1, "unknown pipe linked to edp transcoder\n");
8237 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
8238 case TRANS_DDI_EDP_INPUT_A_ON
:
8239 trans_edp_pipe
= PIPE_A
;
8241 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
8242 trans_edp_pipe
= PIPE_B
;
8244 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
8245 trans_edp_pipe
= PIPE_C
;
8249 if (trans_edp_pipe
== crtc
->pipe
)
8250 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
8253 if (!intel_display_power_is_enabled(dev_priv
,
8254 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
8257 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
8258 if (!(tmp
& PIPECONF_ENABLE
))
8261 haswell_get_ddi_port_state(crtc
, pipe_config
);
8263 intel_get_pipe_timings(crtc
, pipe_config
);
8265 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
8266 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
8267 if (IS_SKYLAKE(dev
))
8268 skylake_get_pfit_config(crtc
, pipe_config
);
8270 ironlake_get_pfit_config(crtc
, pipe_config
);
8273 if (IS_HASWELL(dev
))
8274 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
8275 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
8277 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
8278 pipe_config
->pixel_multiplier
=
8279 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
8281 pipe_config
->pixel_multiplier
= 1;
8287 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8289 struct drm_device
*dev
= crtc
->dev
;
8290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8291 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8292 uint32_t cntl
= 0, size
= 0;
8295 unsigned int width
= intel_crtc
->cursor_width
;
8296 unsigned int height
= intel_crtc
->cursor_height
;
8297 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8301 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8312 cntl
|= CURSOR_ENABLE
|
8313 CURSOR_GAMMA_ENABLE
|
8314 CURSOR_FORMAT_ARGB
|
8315 CURSOR_STRIDE(stride
);
8317 size
= (height
<< 12) | width
;
8320 if (intel_crtc
->cursor_cntl
!= 0 &&
8321 (intel_crtc
->cursor_base
!= base
||
8322 intel_crtc
->cursor_size
!= size
||
8323 intel_crtc
->cursor_cntl
!= cntl
)) {
8324 /* On these chipsets we can only modify the base/size/stride
8325 * whilst the cursor is disabled.
8327 I915_WRITE(_CURACNTR
, 0);
8328 POSTING_READ(_CURACNTR
);
8329 intel_crtc
->cursor_cntl
= 0;
8332 if (intel_crtc
->cursor_base
!= base
) {
8333 I915_WRITE(_CURABASE
, base
);
8334 intel_crtc
->cursor_base
= base
;
8337 if (intel_crtc
->cursor_size
!= size
) {
8338 I915_WRITE(CURSIZE
, size
);
8339 intel_crtc
->cursor_size
= size
;
8342 if (intel_crtc
->cursor_cntl
!= cntl
) {
8343 I915_WRITE(_CURACNTR
, cntl
);
8344 POSTING_READ(_CURACNTR
);
8345 intel_crtc
->cursor_cntl
= cntl
;
8349 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8351 struct drm_device
*dev
= crtc
->dev
;
8352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8353 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8354 int pipe
= intel_crtc
->pipe
;
8359 cntl
= MCURSOR_GAMMA_ENABLE
;
8360 switch (intel_crtc
->cursor_width
) {
8362 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8365 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8368 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8371 MISSING_CASE(intel_crtc
->cursor_width
);
8374 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8376 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8377 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8380 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
8381 cntl
|= CURSOR_ROTATE_180
;
8383 if (intel_crtc
->cursor_cntl
!= cntl
) {
8384 I915_WRITE(CURCNTR(pipe
), cntl
);
8385 POSTING_READ(CURCNTR(pipe
));
8386 intel_crtc
->cursor_cntl
= cntl
;
8389 /* and commit changes on next vblank */
8390 I915_WRITE(CURBASE(pipe
), base
);
8391 POSTING_READ(CURBASE(pipe
));
8393 intel_crtc
->cursor_base
= base
;
8396 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8397 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8400 struct drm_device
*dev
= crtc
->dev
;
8401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8402 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8403 int pipe
= intel_crtc
->pipe
;
8404 int x
= crtc
->cursor_x
;
8405 int y
= crtc
->cursor_y
;
8406 u32 base
= 0, pos
= 0;
8409 base
= intel_crtc
->cursor_addr
;
8411 if (x
>= intel_crtc
->config
->pipe_src_w
)
8414 if (y
>= intel_crtc
->config
->pipe_src_h
)
8418 if (x
+ intel_crtc
->cursor_width
<= 0)
8421 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8424 pos
|= x
<< CURSOR_X_SHIFT
;
8427 if (y
+ intel_crtc
->cursor_height
<= 0)
8430 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8433 pos
|= y
<< CURSOR_Y_SHIFT
;
8435 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8438 I915_WRITE(CURPOS(pipe
), pos
);
8440 /* ILK+ do this automagically */
8441 if (HAS_GMCH_DISPLAY(dev
) &&
8442 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
8443 base
+= (intel_crtc
->cursor_height
*
8444 intel_crtc
->cursor_width
- 1) * 4;
8447 if (IS_845G(dev
) || IS_I865G(dev
))
8448 i845_update_cursor(crtc
, base
);
8450 i9xx_update_cursor(crtc
, base
);
8453 static bool cursor_size_ok(struct drm_device
*dev
,
8454 uint32_t width
, uint32_t height
)
8456 if (width
== 0 || height
== 0)
8460 * 845g/865g are special in that they are only limited by
8461 * the width of their cursors, the height is arbitrary up to
8462 * the precision of the register. Everything else requires
8463 * square cursors, limited to a few power-of-two sizes.
8465 if (IS_845G(dev
) || IS_I865G(dev
)) {
8466 if ((width
& 63) != 0)
8469 if (width
> (IS_845G(dev
) ? 64 : 512))
8475 switch (width
| height
) {
8490 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8491 u16
*blue
, uint32_t start
, uint32_t size
)
8493 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8494 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8496 for (i
= start
; i
< end
; i
++) {
8497 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8498 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8499 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8502 intel_crtc_load_lut(crtc
);
8505 /* VESA 640x480x72Hz mode to set on the pipe */
8506 static struct drm_display_mode load_detect_mode
= {
8507 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8508 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8511 struct drm_framebuffer
*
8512 __intel_framebuffer_create(struct drm_device
*dev
,
8513 struct drm_mode_fb_cmd2
*mode_cmd
,
8514 struct drm_i915_gem_object
*obj
)
8516 struct intel_framebuffer
*intel_fb
;
8519 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8521 drm_gem_object_unreference(&obj
->base
);
8522 return ERR_PTR(-ENOMEM
);
8525 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8529 return &intel_fb
->base
;
8531 drm_gem_object_unreference(&obj
->base
);
8534 return ERR_PTR(ret
);
8537 static struct drm_framebuffer
*
8538 intel_framebuffer_create(struct drm_device
*dev
,
8539 struct drm_mode_fb_cmd2
*mode_cmd
,
8540 struct drm_i915_gem_object
*obj
)
8542 struct drm_framebuffer
*fb
;
8545 ret
= i915_mutex_lock_interruptible(dev
);
8547 return ERR_PTR(ret
);
8548 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8549 mutex_unlock(&dev
->struct_mutex
);
8555 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8557 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8558 return ALIGN(pitch
, 64);
8562 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8564 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8565 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8568 static struct drm_framebuffer
*
8569 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8570 struct drm_display_mode
*mode
,
8573 struct drm_i915_gem_object
*obj
;
8574 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8576 obj
= i915_gem_alloc_object(dev
,
8577 intel_framebuffer_size_for_mode(mode
, bpp
));
8579 return ERR_PTR(-ENOMEM
);
8581 mode_cmd
.width
= mode
->hdisplay
;
8582 mode_cmd
.height
= mode
->vdisplay
;
8583 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8585 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8587 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8590 static struct drm_framebuffer
*
8591 mode_fits_in_fbdev(struct drm_device
*dev
,
8592 struct drm_display_mode
*mode
)
8594 #ifdef CONFIG_DRM_I915_FBDEV
8595 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8596 struct drm_i915_gem_object
*obj
;
8597 struct drm_framebuffer
*fb
;
8599 if (!dev_priv
->fbdev
)
8602 if (!dev_priv
->fbdev
->fb
)
8605 obj
= dev_priv
->fbdev
->fb
->obj
;
8608 fb
= &dev_priv
->fbdev
->fb
->base
;
8609 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8610 fb
->bits_per_pixel
))
8613 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8622 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8623 struct drm_display_mode
*mode
,
8624 struct intel_load_detect_pipe
*old
,
8625 struct drm_modeset_acquire_ctx
*ctx
)
8627 struct intel_crtc
*intel_crtc
;
8628 struct intel_encoder
*intel_encoder
=
8629 intel_attached_encoder(connector
);
8630 struct drm_crtc
*possible_crtc
;
8631 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8632 struct drm_crtc
*crtc
= NULL
;
8633 struct drm_device
*dev
= encoder
->dev
;
8634 struct drm_framebuffer
*fb
;
8635 struct drm_mode_config
*config
= &dev
->mode_config
;
8638 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8639 connector
->base
.id
, connector
->name
,
8640 encoder
->base
.id
, encoder
->name
);
8643 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8648 * Algorithm gets a little messy:
8650 * - if the connector already has an assigned crtc, use it (but make
8651 * sure it's on first)
8653 * - try to find the first unused crtc that can drive this connector,
8654 * and use that if we find one
8657 /* See if we already have a CRTC for this connector */
8658 if (encoder
->crtc
) {
8659 crtc
= encoder
->crtc
;
8661 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8664 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
8668 old
->dpms_mode
= connector
->dpms
;
8669 old
->load_detect_temp
= false;
8671 /* Make sure the crtc and connector are running */
8672 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8673 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8678 /* Find an unused one (if possible) */
8679 for_each_crtc(dev
, possible_crtc
) {
8681 if (!(encoder
->possible_crtcs
& (1 << i
)))
8683 if (possible_crtc
->enabled
)
8685 /* This can occur when applying the pipe A quirk on resume. */
8686 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8689 crtc
= possible_crtc
;
8694 * If we didn't find an unused CRTC, don't use any.
8697 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8701 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8704 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
8707 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8708 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8710 intel_crtc
= to_intel_crtc(crtc
);
8711 intel_crtc
->new_enabled
= true;
8712 intel_crtc
->new_config
= intel_crtc
->config
;
8713 old
->dpms_mode
= connector
->dpms
;
8714 old
->load_detect_temp
= true;
8715 old
->release_fb
= NULL
;
8718 mode
= &load_detect_mode
;
8720 /* We need a framebuffer large enough to accommodate all accesses
8721 * that the plane may generate whilst we perform load detection.
8722 * We can not rely on the fbcon either being present (we get called
8723 * during its initialisation to detect all boot displays, or it may
8724 * not even exist) or that it is large enough to satisfy the
8727 fb
= mode_fits_in_fbdev(dev
, mode
);
8729 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8730 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8731 old
->release_fb
= fb
;
8733 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8735 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8739 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8740 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8741 if (old
->release_fb
)
8742 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8745 crtc
->primary
->crtc
= crtc
;
8747 /* let the connector get through one full cycle before testing */
8748 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8752 intel_crtc
->new_enabled
= crtc
->enabled
;
8753 if (intel_crtc
->new_enabled
)
8754 intel_crtc
->new_config
= intel_crtc
->config
;
8756 intel_crtc
->new_config
= NULL
;
8758 if (ret
== -EDEADLK
) {
8759 drm_modeset_backoff(ctx
);
8766 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8767 struct intel_load_detect_pipe
*old
)
8769 struct intel_encoder
*intel_encoder
=
8770 intel_attached_encoder(connector
);
8771 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8772 struct drm_crtc
*crtc
= encoder
->crtc
;
8773 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8775 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8776 connector
->base
.id
, connector
->name
,
8777 encoder
->base
.id
, encoder
->name
);
8779 if (old
->load_detect_temp
) {
8780 to_intel_connector(connector
)->new_encoder
= NULL
;
8781 intel_encoder
->new_crtc
= NULL
;
8782 intel_crtc
->new_enabled
= false;
8783 intel_crtc
->new_config
= NULL
;
8784 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8786 if (old
->release_fb
) {
8787 drm_framebuffer_unregister_private(old
->release_fb
);
8788 drm_framebuffer_unreference(old
->release_fb
);
8794 /* Switch crtc and encoder back off if necessary */
8795 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8796 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8799 static int i9xx_pll_refclk(struct drm_device
*dev
,
8800 const struct intel_crtc_state
*pipe_config
)
8802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8803 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8805 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8806 return dev_priv
->vbt
.lvds_ssc_freq
;
8807 else if (HAS_PCH_SPLIT(dev
))
8809 else if (!IS_GEN2(dev
))
8815 /* Returns the clock of the currently programmed mode of the given pipe. */
8816 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8817 struct intel_crtc_state
*pipe_config
)
8819 struct drm_device
*dev
= crtc
->base
.dev
;
8820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8821 int pipe
= pipe_config
->cpu_transcoder
;
8822 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8824 intel_clock_t clock
;
8825 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8827 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8828 fp
= pipe_config
->dpll_hw_state
.fp0
;
8830 fp
= pipe_config
->dpll_hw_state
.fp1
;
8832 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8833 if (IS_PINEVIEW(dev
)) {
8834 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8835 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8837 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8838 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8841 if (!IS_GEN2(dev
)) {
8842 if (IS_PINEVIEW(dev
))
8843 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8844 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8846 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8847 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8849 switch (dpll
& DPLL_MODE_MASK
) {
8850 case DPLLB_MODE_DAC_SERIAL
:
8851 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8854 case DPLLB_MODE_LVDS
:
8855 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8859 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8860 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8864 if (IS_PINEVIEW(dev
))
8865 pineview_clock(refclk
, &clock
);
8867 i9xx_clock(refclk
, &clock
);
8869 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8870 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8873 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8874 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8876 if (lvds
& LVDS_CLKB_POWER_UP
)
8881 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8884 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8885 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8887 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8893 i9xx_clock(refclk
, &clock
);
8897 * This value includes pixel_multiplier. We will use
8898 * port_clock to compute adjusted_mode.crtc_clock in the
8899 * encoder's get_config() function.
8901 pipe_config
->port_clock
= clock
.dot
;
8904 int intel_dotclock_calculate(int link_freq
,
8905 const struct intel_link_m_n
*m_n
)
8908 * The calculation for the data clock is:
8909 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8910 * But we want to avoid losing precison if possible, so:
8911 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8913 * and the link clock is simpler:
8914 * link_clock = (m * link_clock) / n
8920 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8923 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8924 struct intel_crtc_state
*pipe_config
)
8926 struct drm_device
*dev
= crtc
->base
.dev
;
8928 /* read out port_clock from the DPLL */
8929 i9xx_crtc_clock_get(crtc
, pipe_config
);
8932 * This value does not include pixel_multiplier.
8933 * We will check that port_clock and adjusted_mode.crtc_clock
8934 * agree once we know their relationship in the encoder's
8935 * get_config() function.
8937 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8938 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8939 &pipe_config
->fdi_m_n
);
8942 /** Returns the currently programmed mode of the given pipe. */
8943 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8944 struct drm_crtc
*crtc
)
8946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8947 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8948 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8949 struct drm_display_mode
*mode
;
8950 struct intel_crtc_state pipe_config
;
8951 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8952 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8953 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8954 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8955 enum pipe pipe
= intel_crtc
->pipe
;
8957 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8962 * Construct a pipe_config sufficient for getting the clock info
8963 * back out of crtc_clock_get.
8965 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8966 * to use a real value here instead.
8968 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8969 pipe_config
.pixel_multiplier
= 1;
8970 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8971 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8972 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8973 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8975 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8976 mode
->hdisplay
= (htot
& 0xffff) + 1;
8977 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8978 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8979 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8980 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8981 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8982 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8983 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8985 drm_mode_set_name(mode
);
8990 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8992 struct drm_device
*dev
= crtc
->dev
;
8993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8994 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8996 if (!HAS_GMCH_DISPLAY(dev
))
8999 if (!dev_priv
->lvds_downclock_avail
)
9003 * Since this is called by a timer, we should never get here in
9006 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
9007 int pipe
= intel_crtc
->pipe
;
9008 int dpll_reg
= DPLL(pipe
);
9011 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9013 assert_panel_unlocked(dev_priv
, pipe
);
9015 dpll
= I915_READ(dpll_reg
);
9016 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
9017 I915_WRITE(dpll_reg
, dpll
);
9018 intel_wait_for_vblank(dev
, pipe
);
9019 dpll
= I915_READ(dpll_reg
);
9020 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
9021 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9026 void intel_mark_busy(struct drm_device
*dev
)
9028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9030 if (dev_priv
->mm
.busy
)
9033 intel_runtime_pm_get(dev_priv
);
9034 i915_update_gfx_val(dev_priv
);
9035 dev_priv
->mm
.busy
= true;
9038 void intel_mark_idle(struct drm_device
*dev
)
9040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9041 struct drm_crtc
*crtc
;
9043 if (!dev_priv
->mm
.busy
)
9046 dev_priv
->mm
.busy
= false;
9048 if (!i915
.powersave
)
9051 for_each_crtc(dev
, crtc
) {
9052 if (!crtc
->primary
->fb
)
9055 intel_decrease_pllclock(crtc
);
9058 if (INTEL_INFO(dev
)->gen
>= 6)
9059 gen6_rps_idle(dev
->dev_private
);
9062 intel_runtime_pm_put(dev_priv
);
9065 static void intel_crtc_set_state(struct intel_crtc
*crtc
,
9066 struct intel_crtc_state
*crtc_state
)
9068 kfree(crtc
->config
);
9069 crtc
->config
= crtc_state
;
9070 crtc
->base
.state
= &crtc_state
->base
;
9073 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9075 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9076 struct drm_device
*dev
= crtc
->dev
;
9077 struct intel_unpin_work
*work
;
9079 spin_lock_irq(&dev
->event_lock
);
9080 work
= intel_crtc
->unpin_work
;
9081 intel_crtc
->unpin_work
= NULL
;
9082 spin_unlock_irq(&dev
->event_lock
);
9085 cancel_work_sync(&work
->work
);
9089 intel_crtc_set_state(intel_crtc
, NULL
);
9090 drm_crtc_cleanup(crtc
);
9095 static void intel_unpin_work_fn(struct work_struct
*__work
)
9097 struct intel_unpin_work
*work
=
9098 container_of(__work
, struct intel_unpin_work
, work
);
9099 struct drm_device
*dev
= work
->crtc
->dev
;
9100 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9102 mutex_lock(&dev
->struct_mutex
);
9103 intel_unpin_fb_obj(work
->old_fb_obj
);
9104 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9105 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9107 intel_fbc_update(dev
);
9109 if (work
->flip_queued_req
)
9110 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
9111 mutex_unlock(&dev
->struct_mutex
);
9113 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9115 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9116 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9121 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9122 struct drm_crtc
*crtc
)
9124 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9125 struct intel_unpin_work
*work
;
9126 unsigned long flags
;
9128 /* Ignore early vblank irqs */
9129 if (intel_crtc
== NULL
)
9133 * This is called both by irq handlers and the reset code (to complete
9134 * lost pageflips) so needs the full irqsave spinlocks.
9136 spin_lock_irqsave(&dev
->event_lock
, flags
);
9137 work
= intel_crtc
->unpin_work
;
9139 /* Ensure we don't miss a work->pending update ... */
9142 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9143 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9147 page_flip_completed(intel_crtc
);
9149 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9152 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9155 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9157 do_intel_finish_page_flip(dev
, crtc
);
9160 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9163 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9165 do_intel_finish_page_flip(dev
, crtc
);
9168 /* Is 'a' after or equal to 'b'? */
9169 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9171 return !((a
- b
) & 0x80000000);
9174 static bool page_flip_finished(struct intel_crtc
*crtc
)
9176 struct drm_device
*dev
= crtc
->base
.dev
;
9177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9179 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
9180 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
9184 * The relevant registers doen't exist on pre-ctg.
9185 * As the flip done interrupt doesn't trigger for mmio
9186 * flips on gmch platforms, a flip count check isn't
9187 * really needed there. But since ctg has the registers,
9188 * include it in the check anyway.
9190 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9194 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9195 * used the same base address. In that case the mmio flip might
9196 * have completed, but the CS hasn't even executed the flip yet.
9198 * A flip count check isn't enough as the CS might have updated
9199 * the base address just after start of vblank, but before we
9200 * managed to process the interrupt. This means we'd complete the
9203 * Combining both checks should get us a good enough result. It may
9204 * still happen that the CS flip has been executed, but has not
9205 * yet actually completed. But in case the base address is the same
9206 * anyway, we don't really care.
9208 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9209 crtc
->unpin_work
->gtt_offset
&&
9210 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9211 crtc
->unpin_work
->flip_count
);
9214 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9217 struct intel_crtc
*intel_crtc
=
9218 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9219 unsigned long flags
;
9223 * This is called both by irq handlers and the reset code (to complete
9224 * lost pageflips) so needs the full irqsave spinlocks.
9226 * NB: An MMIO update of the plane base pointer will also
9227 * generate a page-flip completion irq, i.e. every modeset
9228 * is also accompanied by a spurious intel_prepare_page_flip().
9230 spin_lock_irqsave(&dev
->event_lock
, flags
);
9231 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9232 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9233 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9236 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9238 /* Ensure that the work item is consistent when activating it ... */
9240 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9241 /* and that it is marked active as soon as the irq could fire. */
9245 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9246 struct drm_crtc
*crtc
,
9247 struct drm_framebuffer
*fb
,
9248 struct drm_i915_gem_object
*obj
,
9249 struct intel_engine_cs
*ring
,
9252 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9256 ret
= intel_ring_begin(ring
, 6);
9260 /* Can't queue multiple flips, so wait for the previous
9261 * one to finish before executing the next.
9263 if (intel_crtc
->plane
)
9264 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9266 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9267 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9268 intel_ring_emit(ring
, MI_NOOP
);
9269 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9270 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9271 intel_ring_emit(ring
, fb
->pitches
[0]);
9272 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9273 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9275 intel_mark_page_flip_active(intel_crtc
);
9276 __intel_ring_advance(ring
);
9280 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9281 struct drm_crtc
*crtc
,
9282 struct drm_framebuffer
*fb
,
9283 struct drm_i915_gem_object
*obj
,
9284 struct intel_engine_cs
*ring
,
9287 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9291 ret
= intel_ring_begin(ring
, 6);
9295 if (intel_crtc
->plane
)
9296 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9298 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9299 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9300 intel_ring_emit(ring
, MI_NOOP
);
9301 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9302 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9303 intel_ring_emit(ring
, fb
->pitches
[0]);
9304 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9305 intel_ring_emit(ring
, MI_NOOP
);
9307 intel_mark_page_flip_active(intel_crtc
);
9308 __intel_ring_advance(ring
);
9312 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9313 struct drm_crtc
*crtc
,
9314 struct drm_framebuffer
*fb
,
9315 struct drm_i915_gem_object
*obj
,
9316 struct intel_engine_cs
*ring
,
9319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9320 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9321 uint32_t pf
, pipesrc
;
9324 ret
= intel_ring_begin(ring
, 4);
9328 /* i965+ uses the linear or tiled offsets from the
9329 * Display Registers (which do not change across a page-flip)
9330 * so we need only reprogram the base address.
9332 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9333 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9334 intel_ring_emit(ring
, fb
->pitches
[0]);
9335 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9338 /* XXX Enabling the panel-fitter across page-flip is so far
9339 * untested on non-native modes, so ignore it for now.
9340 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9343 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9344 intel_ring_emit(ring
, pf
| pipesrc
);
9346 intel_mark_page_flip_active(intel_crtc
);
9347 __intel_ring_advance(ring
);
9351 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9352 struct drm_crtc
*crtc
,
9353 struct drm_framebuffer
*fb
,
9354 struct drm_i915_gem_object
*obj
,
9355 struct intel_engine_cs
*ring
,
9358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9359 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9360 uint32_t pf
, pipesrc
;
9363 ret
= intel_ring_begin(ring
, 4);
9367 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9368 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9369 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9370 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9372 /* Contrary to the suggestions in the documentation,
9373 * "Enable Panel Fitter" does not seem to be required when page
9374 * flipping with a non-native mode, and worse causes a normal
9376 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9379 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9380 intel_ring_emit(ring
, pf
| pipesrc
);
9382 intel_mark_page_flip_active(intel_crtc
);
9383 __intel_ring_advance(ring
);
9387 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9388 struct drm_crtc
*crtc
,
9389 struct drm_framebuffer
*fb
,
9390 struct drm_i915_gem_object
*obj
,
9391 struct intel_engine_cs
*ring
,
9394 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9395 uint32_t plane_bit
= 0;
9398 switch (intel_crtc
->plane
) {
9400 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9403 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9406 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9409 WARN_ONCE(1, "unknown plane in flip command\n");
9414 if (ring
->id
== RCS
) {
9417 * On Gen 8, SRM is now taking an extra dword to accommodate
9418 * 48bits addresses, and we need a NOOP for the batch size to
9426 * BSpec MI_DISPLAY_FLIP for IVB:
9427 * "The full packet must be contained within the same cache line."
9429 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9430 * cacheline, if we ever start emitting more commands before
9431 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9432 * then do the cacheline alignment, and finally emit the
9435 ret
= intel_ring_cacheline_align(ring
);
9439 ret
= intel_ring_begin(ring
, len
);
9443 /* Unmask the flip-done completion message. Note that the bspec says that
9444 * we should do this for both the BCS and RCS, and that we must not unmask
9445 * more than one flip event at any time (or ensure that one flip message
9446 * can be sent by waiting for flip-done prior to queueing new flips).
9447 * Experimentation says that BCS works despite DERRMR masking all
9448 * flip-done completion events and that unmasking all planes at once
9449 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9450 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9452 if (ring
->id
== RCS
) {
9453 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9454 intel_ring_emit(ring
, DERRMR
);
9455 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9456 DERRMR_PIPEB_PRI_FLIP_DONE
|
9457 DERRMR_PIPEC_PRI_FLIP_DONE
));
9459 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9460 MI_SRM_LRM_GLOBAL_GTT
);
9462 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9463 MI_SRM_LRM_GLOBAL_GTT
);
9464 intel_ring_emit(ring
, DERRMR
);
9465 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9467 intel_ring_emit(ring
, 0);
9468 intel_ring_emit(ring
, MI_NOOP
);
9472 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9473 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9474 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9475 intel_ring_emit(ring
, (MI_NOOP
));
9477 intel_mark_page_flip_active(intel_crtc
);
9478 __intel_ring_advance(ring
);
9482 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9483 struct drm_i915_gem_object
*obj
)
9486 * This is not being used for older platforms, because
9487 * non-availability of flip done interrupt forces us to use
9488 * CS flips. Older platforms derive flip done using some clever
9489 * tricks involving the flip_pending status bits and vblank irqs.
9490 * So using MMIO flips there would disrupt this mechanism.
9496 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9499 if (i915
.use_mmio_flip
< 0)
9501 else if (i915
.use_mmio_flip
> 0)
9503 else if (i915
.enable_execlists
)
9506 return ring
!= i915_gem_request_get_ring(obj
->last_read_req
);
9509 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9511 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9513 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
9514 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9515 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9516 const enum pipe pipe
= intel_crtc
->pipe
;
9519 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
9520 ctl
&= ~PLANE_CTL_TILED_MASK
;
9521 if (obj
->tiling_mode
== I915_TILING_X
)
9522 ctl
|= PLANE_CTL_TILED_X
;
9525 * The stride is either expressed as a multiple of 64 bytes chunks for
9526 * linear buffers or in number of tiles for tiled buffers.
9528 stride
= fb
->pitches
[0] >> 6;
9529 if (obj
->tiling_mode
== I915_TILING_X
)
9530 stride
= fb
->pitches
[0] >> 9; /* X tiles are 512 bytes wide */
9533 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9534 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9536 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
9537 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
9539 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
9540 POSTING_READ(PLANE_SURF(pipe
, 0));
9543 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9545 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9547 struct intel_framebuffer
*intel_fb
=
9548 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9549 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9553 reg
= DSPCNTR(intel_crtc
->plane
);
9554 dspcntr
= I915_READ(reg
);
9556 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9557 dspcntr
|= DISPPLANE_TILED
;
9559 dspcntr
&= ~DISPPLANE_TILED
;
9561 I915_WRITE(reg
, dspcntr
);
9563 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9564 intel_crtc
->unpin_work
->gtt_offset
);
9565 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9570 * XXX: This is the temporary way to update the plane registers until we get
9571 * around to using the usual plane update functions for MMIO flips
9573 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9575 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9577 u32 start_vbl_count
;
9579 intel_mark_page_flip_active(intel_crtc
);
9581 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
9583 if (INTEL_INFO(dev
)->gen
>= 9)
9584 skl_do_mmio_flip(intel_crtc
);
9586 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9587 ilk_do_mmio_flip(intel_crtc
);
9590 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
9593 static void intel_mmio_flip_work_func(struct work_struct
*work
)
9595 struct intel_crtc
*crtc
=
9596 container_of(work
, struct intel_crtc
, mmio_flip
.work
);
9597 struct intel_mmio_flip
*mmio_flip
;
9599 mmio_flip
= &crtc
->mmio_flip
;
9601 WARN_ON(__i915_wait_request(mmio_flip
->req
,
9602 crtc
->reset_counter
,
9603 false, NULL
, NULL
) != 0);
9605 intel_do_mmio_flip(crtc
);
9606 if (mmio_flip
->req
) {
9607 mutex_lock(&crtc
->base
.dev
->struct_mutex
);
9608 i915_gem_request_assign(&mmio_flip
->req
, NULL
);
9609 mutex_unlock(&crtc
->base
.dev
->struct_mutex
);
9613 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9614 struct drm_crtc
*crtc
,
9615 struct drm_framebuffer
*fb
,
9616 struct drm_i915_gem_object
*obj
,
9617 struct intel_engine_cs
*ring
,
9620 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9622 i915_gem_request_assign(&intel_crtc
->mmio_flip
.req
,
9623 obj
->last_write_req
);
9625 schedule_work(&intel_crtc
->mmio_flip
.work
);
9630 static int intel_gen9_queue_flip(struct drm_device
*dev
,
9631 struct drm_crtc
*crtc
,
9632 struct drm_framebuffer
*fb
,
9633 struct drm_i915_gem_object
*obj
,
9634 struct intel_engine_cs
*ring
,
9637 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9638 uint32_t plane
= 0, stride
;
9641 switch(intel_crtc
->pipe
) {
9643 plane
= MI_DISPLAY_FLIP_SKL_PLANE_1_A
;
9646 plane
= MI_DISPLAY_FLIP_SKL_PLANE_1_B
;
9649 plane
= MI_DISPLAY_FLIP_SKL_PLANE_1_C
;
9652 WARN_ONCE(1, "unknown plane in flip command\n");
9656 switch (obj
->tiling_mode
) {
9657 case I915_TILING_NONE
:
9658 stride
= fb
->pitches
[0] >> 6;
9661 stride
= fb
->pitches
[0] >> 9;
9664 WARN_ONCE(1, "unknown tiling in flip command\n");
9668 ret
= intel_ring_begin(ring
, 10);
9672 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9673 intel_ring_emit(ring
, DERRMR
);
9674 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9675 DERRMR_PIPEB_PRI_FLIP_DONE
|
9676 DERRMR_PIPEC_PRI_FLIP_DONE
));
9677 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9678 MI_SRM_LRM_GLOBAL_GTT
);
9679 intel_ring_emit(ring
, DERRMR
);
9680 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9681 intel_ring_emit(ring
, 0);
9683 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane
);
9684 intel_ring_emit(ring
, stride
<< 6 | obj
->tiling_mode
);
9685 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9687 intel_mark_page_flip_active(intel_crtc
);
9688 __intel_ring_advance(ring
);
9693 static int intel_default_queue_flip(struct drm_device
*dev
,
9694 struct drm_crtc
*crtc
,
9695 struct drm_framebuffer
*fb
,
9696 struct drm_i915_gem_object
*obj
,
9697 struct intel_engine_cs
*ring
,
9703 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
9704 struct drm_crtc
*crtc
)
9706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9707 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9708 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
9711 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
9714 if (!work
->enable_stall_check
)
9717 if (work
->flip_ready_vblank
== 0) {
9718 if (work
->flip_queued_req
&&
9719 !i915_gem_request_completed(work
->flip_queued_req
, true))
9722 work
->flip_ready_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9725 if (drm_vblank_count(dev
, intel_crtc
->pipe
) - work
->flip_ready_vblank
< 3)
9728 /* Potential stall - if we see that the flip has happened,
9729 * assume a missed interrupt. */
9730 if (INTEL_INFO(dev
)->gen
>= 4)
9731 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
9733 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
9735 /* There is a potential issue here with a false positive after a flip
9736 * to the same address. We could address this by checking for a
9737 * non-incrementing frame counter.
9739 return addr
== work
->gtt_offset
;
9742 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
9744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9745 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9746 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9748 WARN_ON(!in_interrupt());
9753 spin_lock(&dev
->event_lock
);
9754 if (intel_crtc
->unpin_work
&& __intel_pageflip_stall_check(dev
, crtc
)) {
9755 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9756 intel_crtc
->unpin_work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
9757 page_flip_completed(intel_crtc
);
9759 spin_unlock(&dev
->event_lock
);
9762 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9763 struct drm_framebuffer
*fb
,
9764 struct drm_pending_vblank_event
*event
,
9765 uint32_t page_flip_flags
)
9767 struct drm_device
*dev
= crtc
->dev
;
9768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9769 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9770 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9771 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9772 struct drm_plane
*primary
= crtc
->primary
;
9773 enum pipe pipe
= intel_crtc
->pipe
;
9774 struct intel_unpin_work
*work
;
9775 struct intel_engine_cs
*ring
;
9779 * drm_mode_page_flip_ioctl() should already catch this, but double
9780 * check to be safe. In the future we may enable pageflipping from
9781 * a disabled primary plane.
9783 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9786 /* Can't change pixel format via MI display flips. */
9787 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9791 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9792 * Note that pitch changes could also affect these register.
9794 if (INTEL_INFO(dev
)->gen
> 3 &&
9795 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9796 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9799 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9802 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9806 work
->event
= event
;
9808 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9809 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9811 ret
= drm_crtc_vblank_get(crtc
);
9815 /* We borrow the event spin lock for protecting unpin_work */
9816 spin_lock_irq(&dev
->event_lock
);
9817 if (intel_crtc
->unpin_work
) {
9818 /* Before declaring the flip queue wedged, check if
9819 * the hardware completed the operation behind our backs.
9821 if (__intel_pageflip_stall_check(dev
, crtc
)) {
9822 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9823 page_flip_completed(intel_crtc
);
9825 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9826 spin_unlock_irq(&dev
->event_lock
);
9828 drm_crtc_vblank_put(crtc
);
9833 intel_crtc
->unpin_work
= work
;
9834 spin_unlock_irq(&dev
->event_lock
);
9836 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9837 flush_workqueue(dev_priv
->wq
);
9839 ret
= i915_mutex_lock_interruptible(dev
);
9843 /* Reference the objects for the scheduled work. */
9844 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9845 drm_gem_object_reference(&obj
->base
);
9847 crtc
->primary
->fb
= fb
;
9848 update_state_fb(crtc
->primary
);
9850 work
->pending_flip_obj
= obj
;
9852 atomic_inc(&intel_crtc
->unpin_work_count
);
9853 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9855 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9856 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9858 if (IS_VALLEYVIEW(dev
)) {
9859 ring
= &dev_priv
->ring
[BCS
];
9860 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
9861 /* vlv: DISPLAY_FLIP fails to change tiling */
9863 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
9864 ring
= &dev_priv
->ring
[BCS
];
9865 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9866 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
9867 if (ring
== NULL
|| ring
->id
!= RCS
)
9868 ring
= &dev_priv
->ring
[BCS
];
9870 ring
= &dev_priv
->ring
[RCS
];
9873 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
, ring
);
9875 goto cleanup_pending
;
9878 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9880 if (use_mmio_flip(ring
, obj
)) {
9881 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
9886 i915_gem_request_assign(&work
->flip_queued_req
,
9887 obj
->last_write_req
);
9889 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
9894 i915_gem_request_assign(&work
->flip_queued_req
,
9895 intel_ring_get_request(ring
));
9898 work
->flip_queued_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9899 work
->enable_stall_check
= true;
9901 i915_gem_track_fb(work
->old_fb_obj
, obj
,
9902 INTEL_FRONTBUFFER_PRIMARY(pipe
));
9904 intel_fbc_disable(dev
);
9905 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9906 mutex_unlock(&dev
->struct_mutex
);
9908 trace_i915_flip_request(intel_crtc
->plane
, obj
);
9913 intel_unpin_fb_obj(obj
);
9915 atomic_dec(&intel_crtc
->unpin_work_count
);
9916 crtc
->primary
->fb
= old_fb
;
9917 update_state_fb(crtc
->primary
);
9918 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9919 drm_gem_object_unreference(&obj
->base
);
9920 mutex_unlock(&dev
->struct_mutex
);
9923 spin_lock_irq(&dev
->event_lock
);
9924 intel_crtc
->unpin_work
= NULL
;
9925 spin_unlock_irq(&dev
->event_lock
);
9927 drm_crtc_vblank_put(crtc
);
9933 ret
= intel_plane_restore(primary
);
9934 if (ret
== 0 && event
) {
9935 spin_lock_irq(&dev
->event_lock
);
9936 drm_send_vblank_event(dev
, pipe
, event
);
9937 spin_unlock_irq(&dev
->event_lock
);
9943 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
9944 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
9945 .load_lut
= intel_crtc_load_lut
,
9946 .atomic_begin
= intel_begin_crtc_commit
,
9947 .atomic_flush
= intel_finish_crtc_commit
,
9951 * intel_modeset_update_staged_output_state
9953 * Updates the staged output configuration state, e.g. after we've read out the
9956 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
9958 struct intel_crtc
*crtc
;
9959 struct intel_encoder
*encoder
;
9960 struct intel_connector
*connector
;
9962 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9964 connector
->new_encoder
=
9965 to_intel_encoder(connector
->base
.encoder
);
9968 for_each_intel_encoder(dev
, encoder
) {
9970 to_intel_crtc(encoder
->base
.crtc
);
9973 for_each_intel_crtc(dev
, crtc
) {
9974 crtc
->new_enabled
= crtc
->base
.enabled
;
9976 if (crtc
->new_enabled
)
9977 crtc
->new_config
= crtc
->config
;
9979 crtc
->new_config
= NULL
;
9984 * intel_modeset_commit_output_state
9986 * This function copies the stage display pipe configuration to the real one.
9988 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
9990 struct intel_crtc
*crtc
;
9991 struct intel_encoder
*encoder
;
9992 struct intel_connector
*connector
;
9994 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9996 connector
->base
.encoder
= &connector
->new_encoder
->base
;
9999 for_each_intel_encoder(dev
, encoder
) {
10000 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
10003 for_each_intel_crtc(dev
, crtc
) {
10004 crtc
->base
.enabled
= crtc
->new_enabled
;
10009 connected_sink_compute_bpp(struct intel_connector
*connector
,
10010 struct intel_crtc_state
*pipe_config
)
10012 int bpp
= pipe_config
->pipe_bpp
;
10014 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10015 connector
->base
.base
.id
,
10016 connector
->base
.name
);
10018 /* Don't use an invalid EDID bpc value */
10019 if (connector
->base
.display_info
.bpc
&&
10020 connector
->base
.display_info
.bpc
* 3 < bpp
) {
10021 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10022 bpp
, connector
->base
.display_info
.bpc
*3);
10023 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
10026 /* Clamp bpp to 8 on screens without EDID 1.4 */
10027 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
10028 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10030 pipe_config
->pipe_bpp
= 24;
10035 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
10036 struct drm_framebuffer
*fb
,
10037 struct intel_crtc_state
*pipe_config
)
10039 struct drm_device
*dev
= crtc
->base
.dev
;
10040 struct intel_connector
*connector
;
10043 switch (fb
->pixel_format
) {
10044 case DRM_FORMAT_C8
:
10045 bpp
= 8*3; /* since we go through a colormap */
10047 case DRM_FORMAT_XRGB1555
:
10048 case DRM_FORMAT_ARGB1555
:
10049 /* checked in intel_framebuffer_init already */
10050 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
10052 case DRM_FORMAT_RGB565
:
10053 bpp
= 6*3; /* min is 18bpp */
10055 case DRM_FORMAT_XBGR8888
:
10056 case DRM_FORMAT_ABGR8888
:
10057 /* checked in intel_framebuffer_init already */
10058 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10060 case DRM_FORMAT_XRGB8888
:
10061 case DRM_FORMAT_ARGB8888
:
10064 case DRM_FORMAT_XRGB2101010
:
10065 case DRM_FORMAT_ARGB2101010
:
10066 case DRM_FORMAT_XBGR2101010
:
10067 case DRM_FORMAT_ABGR2101010
:
10068 /* checked in intel_framebuffer_init already */
10069 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10073 /* TODO: gen4+ supports 16 bpc floating point, too. */
10075 DRM_DEBUG_KMS("unsupported depth\n");
10079 pipe_config
->pipe_bpp
= bpp
;
10081 /* Clamp display bpp to EDID value */
10082 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10084 if (!connector
->new_encoder
||
10085 connector
->new_encoder
->new_crtc
!= crtc
)
10088 connected_sink_compute_bpp(connector
, pipe_config
);
10094 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10096 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10097 "type: 0x%x flags: 0x%x\n",
10099 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10100 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10101 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10102 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10105 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10106 struct intel_crtc_state
*pipe_config
,
10107 const char *context
)
10109 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
10110 context
, pipe_name(crtc
->pipe
));
10112 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
10113 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10114 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10115 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10116 pipe_config
->has_pch_encoder
,
10117 pipe_config
->fdi_lanes
,
10118 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10119 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10120 pipe_config
->fdi_m_n
.tu
);
10121 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10122 pipe_config
->has_dp_encoder
,
10123 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10124 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10125 pipe_config
->dp_m_n
.tu
);
10127 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10128 pipe_config
->has_dp_encoder
,
10129 pipe_config
->dp_m2_n2
.gmch_m
,
10130 pipe_config
->dp_m2_n2
.gmch_n
,
10131 pipe_config
->dp_m2_n2
.link_m
,
10132 pipe_config
->dp_m2_n2
.link_n
,
10133 pipe_config
->dp_m2_n2
.tu
);
10135 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10136 pipe_config
->has_audio
,
10137 pipe_config
->has_infoframe
);
10139 DRM_DEBUG_KMS("requested mode:\n");
10140 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
10141 DRM_DEBUG_KMS("adjusted mode:\n");
10142 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
10143 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
10144 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10145 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10146 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10147 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10148 pipe_config
->gmch_pfit
.control
,
10149 pipe_config
->gmch_pfit
.pgm_ratios
,
10150 pipe_config
->gmch_pfit
.lvds_border_bits
);
10151 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10152 pipe_config
->pch_pfit
.pos
,
10153 pipe_config
->pch_pfit
.size
,
10154 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10155 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10156 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10159 static bool encoders_cloneable(const struct intel_encoder
*a
,
10160 const struct intel_encoder
*b
)
10162 /* masks could be asymmetric, so check both ways */
10163 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10164 b
->cloneable
& (1 << a
->type
));
10167 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10168 struct intel_encoder
*encoder
)
10170 struct drm_device
*dev
= crtc
->base
.dev
;
10171 struct intel_encoder
*source_encoder
;
10173 for_each_intel_encoder(dev
, source_encoder
) {
10174 if (source_encoder
->new_crtc
!= crtc
)
10177 if (!encoders_cloneable(encoder
, source_encoder
))
10184 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10186 struct drm_device
*dev
= crtc
->base
.dev
;
10187 struct intel_encoder
*encoder
;
10189 for_each_intel_encoder(dev
, encoder
) {
10190 if (encoder
->new_crtc
!= crtc
)
10193 if (!check_single_encoder_cloning(crtc
, encoder
))
10200 static bool check_digital_port_conflicts(struct drm_device
*dev
)
10202 struct intel_connector
*connector
;
10203 unsigned int used_ports
= 0;
10206 * Walk the connector list instead of the encoder
10207 * list to detect the problem on ddi platforms
10208 * where there's just one encoder per digital port.
10210 list_for_each_entry(connector
,
10211 &dev
->mode_config
.connector_list
, base
.head
) {
10212 struct intel_encoder
*encoder
= connector
->new_encoder
;
10217 WARN_ON(!encoder
->new_crtc
);
10219 switch (encoder
->type
) {
10220 unsigned int port_mask
;
10221 case INTEL_OUTPUT_UNKNOWN
:
10222 if (WARN_ON(!HAS_DDI(dev
)))
10224 case INTEL_OUTPUT_DISPLAYPORT
:
10225 case INTEL_OUTPUT_HDMI
:
10226 case INTEL_OUTPUT_EDP
:
10227 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
10229 /* the same port mustn't appear more than once */
10230 if (used_ports
& port_mask
)
10233 used_ports
|= port_mask
;
10242 static struct intel_crtc_state
*
10243 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10244 struct drm_framebuffer
*fb
,
10245 struct drm_display_mode
*mode
)
10247 struct drm_device
*dev
= crtc
->dev
;
10248 struct intel_encoder
*encoder
;
10249 struct intel_crtc_state
*pipe_config
;
10250 int plane_bpp
, ret
= -EINVAL
;
10253 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10254 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10255 return ERR_PTR(-EINVAL
);
10258 if (!check_digital_port_conflicts(dev
)) {
10259 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10260 return ERR_PTR(-EINVAL
);
10263 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10265 return ERR_PTR(-ENOMEM
);
10267 drm_mode_copy(&pipe_config
->base
.adjusted_mode
, mode
);
10268 drm_mode_copy(&pipe_config
->base
.mode
, mode
);
10270 pipe_config
->cpu_transcoder
=
10271 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10272 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10275 * Sanitize sync polarity flags based on requested ones. If neither
10276 * positive or negative polarity is requested, treat this as meaning
10277 * negative polarity.
10279 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10280 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10281 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10283 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10284 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10285 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10287 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10288 * plane pixel format and any sink constraints into account. Returns the
10289 * source plane bpp so that dithering can be selected on mismatches
10290 * after encoders and crtc also have had their say. */
10291 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10297 * Determine the real pipe dimensions. Note that stereo modes can
10298 * increase the actual pipe size due to the frame doubling and
10299 * insertion of additional space for blanks between the frame. This
10300 * is stored in the crtc timings. We use the requested mode to do this
10301 * computation to clearly distinguish it from the adjusted mode, which
10302 * can be changed by the connectors in the below retry loop.
10304 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
10305 &pipe_config
->pipe_src_w
,
10306 &pipe_config
->pipe_src_h
);
10309 /* Ensure the port clock defaults are reset when retrying. */
10310 pipe_config
->port_clock
= 0;
10311 pipe_config
->pixel_multiplier
= 1;
10313 /* Fill in default crtc timings, allow encoders to overwrite them. */
10314 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
10315 CRTC_STEREO_DOUBLE
);
10317 /* Pass our mode to the connectors and the CRTC to give them a chance to
10318 * adjust it according to limitations or connector properties, and also
10319 * a chance to reject the mode entirely.
10321 for_each_intel_encoder(dev
, encoder
) {
10323 if (&encoder
->new_crtc
->base
!= crtc
)
10326 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10327 DRM_DEBUG_KMS("Encoder config failure\n");
10332 /* Set default port clock if not overwritten by the encoder. Needs to be
10333 * done afterwards in case the encoder adjusts the mode. */
10334 if (!pipe_config
->port_clock
)
10335 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
10336 * pipe_config
->pixel_multiplier
;
10338 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10340 DRM_DEBUG_KMS("CRTC fixup failed\n");
10344 if (ret
== RETRY
) {
10345 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10350 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10352 goto encoder_retry
;
10355 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10356 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10357 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10359 return pipe_config
;
10361 kfree(pipe_config
);
10362 return ERR_PTR(ret
);
10365 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10366 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10368 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10369 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10371 struct intel_crtc
*intel_crtc
;
10372 struct drm_device
*dev
= crtc
->dev
;
10373 struct intel_encoder
*encoder
;
10374 struct intel_connector
*connector
;
10375 struct drm_crtc
*tmp_crtc
;
10377 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10379 /* Check which crtcs have changed outputs connected to them, these need
10380 * to be part of the prepare_pipes mask. We don't (yet) support global
10381 * modeset across multiple crtcs, so modeset_pipes will only have one
10382 * bit set at most. */
10383 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10385 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10388 if (connector
->base
.encoder
) {
10389 tmp_crtc
= connector
->base
.encoder
->crtc
;
10391 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10394 if (connector
->new_encoder
)
10396 1 << connector
->new_encoder
->new_crtc
->pipe
;
10399 for_each_intel_encoder(dev
, encoder
) {
10400 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10403 if (encoder
->base
.crtc
) {
10404 tmp_crtc
= encoder
->base
.crtc
;
10406 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10409 if (encoder
->new_crtc
)
10410 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10413 /* Check for pipes that will be enabled/disabled ... */
10414 for_each_intel_crtc(dev
, intel_crtc
) {
10415 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10418 if (!intel_crtc
->new_enabled
)
10419 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10421 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10425 /* set_mode is also used to update properties on life display pipes. */
10426 intel_crtc
= to_intel_crtc(crtc
);
10427 if (intel_crtc
->new_enabled
)
10428 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10431 * For simplicity do a full modeset on any pipe where the output routing
10432 * changed. We could be more clever, but that would require us to be
10433 * more careful with calling the relevant encoder->mode_set functions.
10435 if (*prepare_pipes
)
10436 *modeset_pipes
= *prepare_pipes
;
10438 /* ... and mask these out. */
10439 *modeset_pipes
&= ~(*disable_pipes
);
10440 *prepare_pipes
&= ~(*disable_pipes
);
10443 * HACK: We don't (yet) fully support global modesets. intel_set_config
10444 * obies this rule, but the modeset restore mode of
10445 * intel_modeset_setup_hw_state does not.
10447 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10448 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10450 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10451 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10454 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10456 struct drm_encoder
*encoder
;
10457 struct drm_device
*dev
= crtc
->dev
;
10459 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10460 if (encoder
->crtc
== crtc
)
10467 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10470 struct intel_encoder
*intel_encoder
;
10471 struct intel_crtc
*intel_crtc
;
10472 struct drm_connector
*connector
;
10474 intel_shared_dpll_commit(dev_priv
);
10476 for_each_intel_encoder(dev
, intel_encoder
) {
10477 if (!intel_encoder
->base
.crtc
)
10480 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10482 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10483 intel_encoder
->connectors_active
= false;
10486 intel_modeset_commit_output_state(dev
);
10488 /* Double check state. */
10489 for_each_intel_crtc(dev
, intel_crtc
) {
10490 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10491 WARN_ON(intel_crtc
->new_config
&&
10492 intel_crtc
->new_config
!= intel_crtc
->config
);
10493 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10496 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10497 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10500 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10502 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10503 struct drm_property
*dpms_property
=
10504 dev
->mode_config
.dpms_property
;
10506 connector
->dpms
= DRM_MODE_DPMS_ON
;
10507 drm_object_property_set_value(&connector
->base
,
10511 intel_encoder
= to_intel_encoder(connector
->encoder
);
10512 intel_encoder
->connectors_active
= true;
10518 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10522 if (clock1
== clock2
)
10525 if (!clock1
|| !clock2
)
10528 diff
= abs(clock1
- clock2
);
10530 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10536 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10537 list_for_each_entry((intel_crtc), \
10538 &(dev)->mode_config.crtc_list, \
10540 if (mask & (1 <<(intel_crtc)->pipe))
10543 intel_pipe_config_compare(struct drm_device
*dev
,
10544 struct intel_crtc_state
*current_config
,
10545 struct intel_crtc_state
*pipe_config
)
10547 #define PIPE_CONF_CHECK_X(name) \
10548 if (current_config->name != pipe_config->name) { \
10549 DRM_ERROR("mismatch in " #name " " \
10550 "(expected 0x%08x, found 0x%08x)\n", \
10551 current_config->name, \
10552 pipe_config->name); \
10556 #define PIPE_CONF_CHECK_I(name) \
10557 if (current_config->name != pipe_config->name) { \
10558 DRM_ERROR("mismatch in " #name " " \
10559 "(expected %i, found %i)\n", \
10560 current_config->name, \
10561 pipe_config->name); \
10565 /* This is required for BDW+ where there is only one set of registers for
10566 * switching between high and low RR.
10567 * This macro can be used whenever a comparison has to be made between one
10568 * hw state and multiple sw state variables.
10570 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10571 if ((current_config->name != pipe_config->name) && \
10572 (current_config->alt_name != pipe_config->name)) { \
10573 DRM_ERROR("mismatch in " #name " " \
10574 "(expected %i or %i, found %i)\n", \
10575 current_config->name, \
10576 current_config->alt_name, \
10577 pipe_config->name); \
10581 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10582 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10583 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10584 "(expected %i, found %i)\n", \
10585 current_config->name & (mask), \
10586 pipe_config->name & (mask)); \
10590 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10591 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10592 DRM_ERROR("mismatch in " #name " " \
10593 "(expected %i, found %i)\n", \
10594 current_config->name, \
10595 pipe_config->name); \
10599 #define PIPE_CONF_QUIRK(quirk) \
10600 ((current_config->quirks | pipe_config->quirks) & (quirk))
10602 PIPE_CONF_CHECK_I(cpu_transcoder
);
10604 PIPE_CONF_CHECK_I(has_pch_encoder
);
10605 PIPE_CONF_CHECK_I(fdi_lanes
);
10606 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10607 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10608 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10609 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10610 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10612 PIPE_CONF_CHECK_I(has_dp_encoder
);
10614 if (INTEL_INFO(dev
)->gen
< 8) {
10615 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10616 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10617 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10618 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10619 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10621 if (current_config
->has_drrs
) {
10622 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10623 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10624 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10625 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10626 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10629 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10630 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10631 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10632 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10633 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10636 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
10637 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
10638 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
10639 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
10640 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
10641 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
10643 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
10644 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
10645 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
10646 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
10647 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
10648 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
10650 PIPE_CONF_CHECK_I(pixel_multiplier
);
10651 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10652 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10653 IS_VALLEYVIEW(dev
))
10654 PIPE_CONF_CHECK_I(limited_color_range
);
10655 PIPE_CONF_CHECK_I(has_infoframe
);
10657 PIPE_CONF_CHECK_I(has_audio
);
10659 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10660 DRM_MODE_FLAG_INTERLACE
);
10662 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10663 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10664 DRM_MODE_FLAG_PHSYNC
);
10665 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10666 DRM_MODE_FLAG_NHSYNC
);
10667 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10668 DRM_MODE_FLAG_PVSYNC
);
10669 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10670 DRM_MODE_FLAG_NVSYNC
);
10673 PIPE_CONF_CHECK_I(pipe_src_w
);
10674 PIPE_CONF_CHECK_I(pipe_src_h
);
10677 * FIXME: BIOS likes to set up a cloned config with lvds+external
10678 * screen. Since we don't yet re-compute the pipe config when moving
10679 * just the lvds port away to another pipe the sw tracking won't match.
10681 * Proper atomic modesets with recomputed global state will fix this.
10682 * Until then just don't check gmch state for inherited modes.
10684 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10685 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10686 /* pfit ratios are autocomputed by the hw on gen4+ */
10687 if (INTEL_INFO(dev
)->gen
< 4)
10688 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10689 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10692 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10693 if (current_config
->pch_pfit
.enabled
) {
10694 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10695 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10698 /* BDW+ don't expose a synchronous way to read the state */
10699 if (IS_HASWELL(dev
))
10700 PIPE_CONF_CHECK_I(ips_enabled
);
10702 PIPE_CONF_CHECK_I(double_wide
);
10704 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10706 PIPE_CONF_CHECK_I(shared_dpll
);
10707 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10708 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10709 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10710 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10711 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10712 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
10713 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
10714 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
10716 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10717 PIPE_CONF_CHECK_I(pipe_bpp
);
10719 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
10720 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10722 #undef PIPE_CONF_CHECK_X
10723 #undef PIPE_CONF_CHECK_I
10724 #undef PIPE_CONF_CHECK_I_ALT
10725 #undef PIPE_CONF_CHECK_FLAGS
10726 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10727 #undef PIPE_CONF_QUIRK
10732 static void check_wm_state(struct drm_device
*dev
)
10734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10735 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
10736 struct intel_crtc
*intel_crtc
;
10739 if (INTEL_INFO(dev
)->gen
< 9)
10742 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
10743 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
10745 for_each_intel_crtc(dev
, intel_crtc
) {
10746 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
10747 const enum pipe pipe
= intel_crtc
->pipe
;
10749 if (!intel_crtc
->active
)
10753 for_each_plane(pipe
, plane
) {
10754 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
10755 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
10757 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
10760 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10761 "(expected (%u,%u), found (%u,%u))\n",
10762 pipe_name(pipe
), plane
+ 1,
10763 sw_entry
->start
, sw_entry
->end
,
10764 hw_entry
->start
, hw_entry
->end
);
10768 hw_entry
= &hw_ddb
.cursor
[pipe
];
10769 sw_entry
= &sw_ddb
->cursor
[pipe
];
10771 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
10774 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10775 "(expected (%u,%u), found (%u,%u))\n",
10777 sw_entry
->start
, sw_entry
->end
,
10778 hw_entry
->start
, hw_entry
->end
);
10783 check_connector_state(struct drm_device
*dev
)
10785 struct intel_connector
*connector
;
10787 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10789 /* This also checks the encoder/connector hw state with the
10790 * ->get_hw_state callbacks. */
10791 intel_connector_check_state(connector
);
10793 I915_STATE_WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10794 "connector's staged encoder doesn't match current encoder\n");
10799 check_encoder_state(struct drm_device
*dev
)
10801 struct intel_encoder
*encoder
;
10802 struct intel_connector
*connector
;
10804 for_each_intel_encoder(dev
, encoder
) {
10805 bool enabled
= false;
10806 bool active
= false;
10807 enum pipe pipe
, tracked_pipe
;
10809 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10810 encoder
->base
.base
.id
,
10811 encoder
->base
.name
);
10813 I915_STATE_WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10814 "encoder's stage crtc doesn't match current crtc\n");
10815 I915_STATE_WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10816 "encoder's active_connectors set, but no crtc\n");
10818 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10820 if (connector
->base
.encoder
!= &encoder
->base
)
10823 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10827 * for MST connectors if we unplug the connector is gone
10828 * away but the encoder is still connected to a crtc
10829 * until a modeset happens in response to the hotplug.
10831 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10834 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
10835 "encoder's enabled state mismatch "
10836 "(expected %i, found %i)\n",
10837 !!encoder
->base
.crtc
, enabled
);
10838 I915_STATE_WARN(active
&& !encoder
->base
.crtc
,
10839 "active encoder with no crtc\n");
10841 I915_STATE_WARN(encoder
->connectors_active
!= active
,
10842 "encoder's computed active state doesn't match tracked active state "
10843 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10845 active
= encoder
->get_hw_state(encoder
, &pipe
);
10846 I915_STATE_WARN(active
!= encoder
->connectors_active
,
10847 "encoder's hw state doesn't match sw tracking "
10848 "(expected %i, found %i)\n",
10849 encoder
->connectors_active
, active
);
10851 if (!encoder
->base
.crtc
)
10854 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10855 I915_STATE_WARN(active
&& pipe
!= tracked_pipe
,
10856 "active encoder's pipe doesn't match"
10857 "(expected %i, found %i)\n",
10858 tracked_pipe
, pipe
);
10864 check_crtc_state(struct drm_device
*dev
)
10866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10867 struct intel_crtc
*crtc
;
10868 struct intel_encoder
*encoder
;
10869 struct intel_crtc_state pipe_config
;
10871 for_each_intel_crtc(dev
, crtc
) {
10872 bool enabled
= false;
10873 bool active
= false;
10875 memset(&pipe_config
, 0, sizeof(pipe_config
));
10877 DRM_DEBUG_KMS("[CRTC:%d]\n",
10878 crtc
->base
.base
.id
);
10880 I915_STATE_WARN(crtc
->active
&& !crtc
->base
.enabled
,
10881 "active crtc, but not enabled in sw tracking\n");
10883 for_each_intel_encoder(dev
, encoder
) {
10884 if (encoder
->base
.crtc
!= &crtc
->base
)
10887 if (encoder
->connectors_active
)
10891 I915_STATE_WARN(active
!= crtc
->active
,
10892 "crtc's computed active state doesn't match tracked active state "
10893 "(expected %i, found %i)\n", active
, crtc
->active
);
10894 I915_STATE_WARN(enabled
!= crtc
->base
.enabled
,
10895 "crtc's computed enabled state doesn't match tracked enabled state "
10896 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10898 active
= dev_priv
->display
.get_pipe_config(crtc
,
10901 /* hw state is inconsistent with the pipe quirk */
10902 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
10903 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
10904 active
= crtc
->active
;
10906 for_each_intel_encoder(dev
, encoder
) {
10908 if (encoder
->base
.crtc
!= &crtc
->base
)
10910 if (encoder
->get_hw_state(encoder
, &pipe
))
10911 encoder
->get_config(encoder
, &pipe_config
);
10914 I915_STATE_WARN(crtc
->active
!= active
,
10915 "crtc active state doesn't match with hw state "
10916 "(expected %i, found %i)\n", crtc
->active
, active
);
10919 !intel_pipe_config_compare(dev
, crtc
->config
, &pipe_config
)) {
10920 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10921 intel_dump_pipe_config(crtc
, &pipe_config
,
10923 intel_dump_pipe_config(crtc
, crtc
->config
,
10930 check_shared_dpll_state(struct drm_device
*dev
)
10932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10933 struct intel_crtc
*crtc
;
10934 struct intel_dpll_hw_state dpll_hw_state
;
10937 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10938 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10939 int enabled_crtcs
= 0, active_crtcs
= 0;
10942 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10944 DRM_DEBUG_KMS("%s\n", pll
->name
);
10946 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10948 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
10949 "more active pll users than references: %i vs %i\n",
10950 pll
->active
, hweight32(pll
->config
.crtc_mask
));
10951 I915_STATE_WARN(pll
->active
&& !pll
->on
,
10952 "pll in active use but not on in sw tracking\n");
10953 I915_STATE_WARN(pll
->on
&& !pll
->active
,
10954 "pll in on but not on in use in sw tracking\n");
10955 I915_STATE_WARN(pll
->on
!= active
,
10956 "pll on state mismatch (expected %i, found %i)\n",
10959 for_each_intel_crtc(dev
, crtc
) {
10960 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10962 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10965 I915_STATE_WARN(pll
->active
!= active_crtcs
,
10966 "pll active crtcs mismatch (expected %i, found %i)\n",
10967 pll
->active
, active_crtcs
);
10968 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
10969 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10970 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
10972 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
10973 sizeof(dpll_hw_state
)),
10974 "pll hw state mismatch\n");
10979 intel_modeset_check_state(struct drm_device
*dev
)
10981 check_wm_state(dev
);
10982 check_connector_state(dev
);
10983 check_encoder_state(dev
);
10984 check_crtc_state(dev
);
10985 check_shared_dpll_state(dev
);
10988 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
10992 * FDI already provided one idea for the dotclock.
10993 * Yell if the encoder disagrees.
10995 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
10996 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10997 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
11000 static void update_scanline_offset(struct intel_crtc
*crtc
)
11002 struct drm_device
*dev
= crtc
->base
.dev
;
11005 * The scanline counter increments at the leading edge of hsync.
11007 * On most platforms it starts counting from vtotal-1 on the
11008 * first active line. That means the scanline counter value is
11009 * always one less than what we would expect. Ie. just after
11010 * start of vblank, which also occurs at start of hsync (on the
11011 * last active line), the scanline counter will read vblank_start-1.
11013 * On gen2 the scanline counter starts counting from 1 instead
11014 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11015 * to keep the value positive), instead of adding one.
11017 * On HSW+ the behaviour of the scanline counter depends on the output
11018 * type. For DP ports it behaves like most other platforms, but on HDMI
11019 * there's an extra 1 line difference. So we need to add two instead of
11020 * one to the value.
11022 if (IS_GEN2(dev
)) {
11023 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
11026 vtotal
= mode
->crtc_vtotal
;
11027 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
11030 crtc
->scanline_offset
= vtotal
- 1;
11031 } else if (HAS_DDI(dev
) &&
11032 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
11033 crtc
->scanline_offset
= 2;
11035 crtc
->scanline_offset
= 1;
11038 static struct intel_crtc_state
*
11039 intel_modeset_compute_config(struct drm_crtc
*crtc
,
11040 struct drm_display_mode
*mode
,
11041 struct drm_framebuffer
*fb
,
11042 unsigned *modeset_pipes
,
11043 unsigned *prepare_pipes
,
11044 unsigned *disable_pipes
)
11046 struct intel_crtc_state
*pipe_config
= NULL
;
11048 intel_modeset_affected_pipes(crtc
, modeset_pipes
,
11049 prepare_pipes
, disable_pipes
);
11051 if ((*modeset_pipes
) == 0)
11055 * Note this needs changes when we start tracking multiple modes
11056 * and crtcs. At that point we'll need to compute the whole config
11057 * (i.e. one pipe_config for each crtc) rather than just the one
11060 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
11061 if (IS_ERR(pipe_config
)) {
11064 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
11068 return pipe_config
;
11071 static int __intel_set_mode_setup_plls(struct drm_device
*dev
,
11072 unsigned modeset_pipes
,
11073 unsigned disable_pipes
)
11075 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11076 unsigned clear_pipes
= modeset_pipes
| disable_pipes
;
11077 struct intel_crtc
*intel_crtc
;
11080 if (!dev_priv
->display
.crtc_compute_clock
)
11083 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
11087 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11088 struct intel_crtc_state
*state
= intel_crtc
->new_config
;
11089 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11092 intel_shared_dpll_abort_config(dev_priv
);
11101 static int __intel_set_mode(struct drm_crtc
*crtc
,
11102 struct drm_display_mode
*mode
,
11103 int x
, int y
, struct drm_framebuffer
*fb
,
11104 struct intel_crtc_state
*pipe_config
,
11105 unsigned modeset_pipes
,
11106 unsigned prepare_pipes
,
11107 unsigned disable_pipes
)
11109 struct drm_device
*dev
= crtc
->dev
;
11110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11111 struct drm_display_mode
*saved_mode
;
11112 struct intel_crtc
*intel_crtc
;
11115 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
11119 *saved_mode
= crtc
->mode
;
11122 to_intel_crtc(crtc
)->new_config
= pipe_config
;
11125 * See if the config requires any additional preparation, e.g.
11126 * to adjust global state with pipes off. We need to do this
11127 * here so we can get the modeset_pipe updated config for the new
11128 * mode set on this crtc. For other crtcs we need to use the
11129 * adjusted_mode bits in the crtc directly.
11131 if (IS_VALLEYVIEW(dev
)) {
11132 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
11134 /* may have added more to prepare_pipes than we should */
11135 prepare_pipes
&= ~disable_pipes
;
11138 ret
= __intel_set_mode_setup_plls(dev
, modeset_pipes
, disable_pipes
);
11142 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
11143 intel_crtc_disable(&intel_crtc
->base
);
11145 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11146 if (intel_crtc
->base
.enabled
)
11147 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
11150 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11151 * to set it here already despite that we pass it down the callchain.
11153 * Note we'll need to fix this up when we start tracking multiple
11154 * pipes; here we assume a single modeset_pipe and only track the
11155 * single crtc and mode.
11157 if (modeset_pipes
) {
11158 crtc
->mode
= *mode
;
11159 /* mode_set/enable/disable functions rely on a correct pipe
11161 intel_crtc_set_state(to_intel_crtc(crtc
), pipe_config
);
11164 * Calculate and store various constants which
11165 * are later needed by vblank and swap-completion
11166 * timestamping. They are derived from true hwmode.
11168 drm_calc_timestamping_constants(crtc
,
11169 &pipe_config
->base
.adjusted_mode
);
11172 /* Only after disabling all output pipelines that will be changed can we
11173 * update the the output configuration. */
11174 intel_modeset_update_state(dev
, prepare_pipes
);
11176 modeset_update_crtc_power_domains(dev
);
11178 /* Set up the DPLL and any encoders state that needs to adjust or depend
11181 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11182 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
11183 int vdisplay
, hdisplay
;
11185 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
11186 ret
= primary
->funcs
->update_plane(primary
, &intel_crtc
->base
,
11188 hdisplay
, vdisplay
,
11190 hdisplay
<< 16, vdisplay
<< 16);
11193 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11194 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11195 update_scanline_offset(intel_crtc
);
11197 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11200 /* FIXME: add subpixel order */
11202 if (ret
&& crtc
->enabled
)
11203 crtc
->mode
= *saved_mode
;
11209 static int intel_set_mode_pipes(struct drm_crtc
*crtc
,
11210 struct drm_display_mode
*mode
,
11211 int x
, int y
, struct drm_framebuffer
*fb
,
11212 struct intel_crtc_state
*pipe_config
,
11213 unsigned modeset_pipes
,
11214 unsigned prepare_pipes
,
11215 unsigned disable_pipes
)
11219 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
, pipe_config
, modeset_pipes
,
11220 prepare_pipes
, disable_pipes
);
11223 intel_modeset_check_state(crtc
->dev
);
11228 static int intel_set_mode(struct drm_crtc
*crtc
,
11229 struct drm_display_mode
*mode
,
11230 int x
, int y
, struct drm_framebuffer
*fb
)
11232 struct intel_crtc_state
*pipe_config
;
11233 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
11235 pipe_config
= intel_modeset_compute_config(crtc
, mode
, fb
,
11240 if (IS_ERR(pipe_config
))
11241 return PTR_ERR(pipe_config
);
11243 return intel_set_mode_pipes(crtc
, mode
, x
, y
, fb
, pipe_config
,
11244 modeset_pipes
, prepare_pipes
,
11248 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11250 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
11253 #undef for_each_intel_crtc_masked
11255 static void intel_set_config_free(struct intel_set_config
*config
)
11260 kfree(config
->save_connector_encoders
);
11261 kfree(config
->save_encoder_crtcs
);
11262 kfree(config
->save_crtc_enabled
);
11266 static int intel_set_config_save_state(struct drm_device
*dev
,
11267 struct intel_set_config
*config
)
11269 struct drm_crtc
*crtc
;
11270 struct drm_encoder
*encoder
;
11271 struct drm_connector
*connector
;
11274 config
->save_crtc_enabled
=
11275 kcalloc(dev
->mode_config
.num_crtc
,
11276 sizeof(bool), GFP_KERNEL
);
11277 if (!config
->save_crtc_enabled
)
11280 config
->save_encoder_crtcs
=
11281 kcalloc(dev
->mode_config
.num_encoder
,
11282 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11283 if (!config
->save_encoder_crtcs
)
11286 config
->save_connector_encoders
=
11287 kcalloc(dev
->mode_config
.num_connector
,
11288 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11289 if (!config
->save_connector_encoders
)
11292 /* Copy data. Note that driver private data is not affected.
11293 * Should anything bad happen only the expected state is
11294 * restored, not the drivers personal bookkeeping.
11297 for_each_crtc(dev
, crtc
) {
11298 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
11302 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11303 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11307 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11308 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11314 static void intel_set_config_restore_state(struct drm_device
*dev
,
11315 struct intel_set_config
*config
)
11317 struct intel_crtc
*crtc
;
11318 struct intel_encoder
*encoder
;
11319 struct intel_connector
*connector
;
11323 for_each_intel_crtc(dev
, crtc
) {
11324 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11326 if (crtc
->new_enabled
)
11327 crtc
->new_config
= crtc
->config
;
11329 crtc
->new_config
= NULL
;
11333 for_each_intel_encoder(dev
, encoder
) {
11334 encoder
->new_crtc
=
11335 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11339 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11340 connector
->new_encoder
=
11341 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11346 is_crtc_connector_off(struct drm_mode_set
*set
)
11350 if (set
->num_connectors
== 0)
11353 if (WARN_ON(set
->connectors
== NULL
))
11356 for (i
= 0; i
< set
->num_connectors
; i
++)
11357 if (set
->connectors
[i
]->encoder
&&
11358 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11359 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11366 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11367 struct intel_set_config
*config
)
11370 /* We should be able to check here if the fb has the same properties
11371 * and then just flip_or_move it */
11372 if (is_crtc_connector_off(set
)) {
11373 config
->mode_changed
= true;
11374 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11376 * If we have no fb, we can only flip as long as the crtc is
11377 * active, otherwise we need a full mode set. The crtc may
11378 * be active if we've only disabled the primary plane, or
11379 * in fastboot situations.
11381 if (set
->crtc
->primary
->fb
== NULL
) {
11382 struct intel_crtc
*intel_crtc
=
11383 to_intel_crtc(set
->crtc
);
11385 if (intel_crtc
->active
) {
11386 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11387 config
->fb_changed
= true;
11389 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11390 config
->mode_changed
= true;
11392 } else if (set
->fb
== NULL
) {
11393 config
->mode_changed
= true;
11394 } else if (set
->fb
->pixel_format
!=
11395 set
->crtc
->primary
->fb
->pixel_format
) {
11396 config
->mode_changed
= true;
11398 config
->fb_changed
= true;
11402 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11403 config
->fb_changed
= true;
11405 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11406 DRM_DEBUG_KMS("modes are different, full mode set\n");
11407 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11408 drm_mode_debug_printmodeline(set
->mode
);
11409 config
->mode_changed
= true;
11412 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11413 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11417 intel_modeset_stage_output_state(struct drm_device
*dev
,
11418 struct drm_mode_set
*set
,
11419 struct intel_set_config
*config
)
11421 struct intel_connector
*connector
;
11422 struct intel_encoder
*encoder
;
11423 struct intel_crtc
*crtc
;
11426 /* The upper layers ensure that we either disable a crtc or have a list
11427 * of connectors. For paranoia, double-check this. */
11428 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11429 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11431 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11433 /* Otherwise traverse passed in connector list and get encoders
11435 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11436 if (set
->connectors
[ro
] == &connector
->base
) {
11437 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11442 /* If we disable the crtc, disable all its connectors. Also, if
11443 * the connector is on the changing crtc but not on the new
11444 * connector list, disable it. */
11445 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11446 connector
->base
.encoder
&&
11447 connector
->base
.encoder
->crtc
== set
->crtc
) {
11448 connector
->new_encoder
= NULL
;
11450 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11451 connector
->base
.base
.id
,
11452 connector
->base
.name
);
11456 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11457 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11458 config
->mode_changed
= true;
11461 /* connector->new_encoder is now updated for all connectors. */
11463 /* Update crtc of enabled connectors. */
11464 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11466 struct drm_crtc
*new_crtc
;
11468 if (!connector
->new_encoder
)
11471 new_crtc
= connector
->new_encoder
->base
.crtc
;
11473 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11474 if (set
->connectors
[ro
] == &connector
->base
)
11475 new_crtc
= set
->crtc
;
11478 /* Make sure the new CRTC will work with the encoder */
11479 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11483 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11485 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11486 connector
->base
.base
.id
,
11487 connector
->base
.name
,
11488 new_crtc
->base
.id
);
11491 /* Check for any encoders that needs to be disabled. */
11492 for_each_intel_encoder(dev
, encoder
) {
11493 int num_connectors
= 0;
11494 list_for_each_entry(connector
,
11495 &dev
->mode_config
.connector_list
,
11497 if (connector
->new_encoder
== encoder
) {
11498 WARN_ON(!connector
->new_encoder
->new_crtc
);
11503 if (num_connectors
== 0)
11504 encoder
->new_crtc
= NULL
;
11505 else if (num_connectors
> 1)
11508 /* Only now check for crtc changes so we don't miss encoders
11509 * that will be disabled. */
11510 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11511 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11512 config
->mode_changed
= true;
11515 /* Now we've also updated encoder->new_crtc for all encoders. */
11516 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11518 if (connector
->new_encoder
)
11519 if (connector
->new_encoder
!= connector
->encoder
)
11520 connector
->encoder
= connector
->new_encoder
;
11522 for_each_intel_crtc(dev
, crtc
) {
11523 crtc
->new_enabled
= false;
11525 for_each_intel_encoder(dev
, encoder
) {
11526 if (encoder
->new_crtc
== crtc
) {
11527 crtc
->new_enabled
= true;
11532 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11533 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11534 crtc
->new_enabled
? "en" : "dis");
11535 config
->mode_changed
= true;
11538 if (crtc
->new_enabled
)
11539 crtc
->new_config
= crtc
->config
;
11541 crtc
->new_config
= NULL
;
11547 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11549 struct drm_device
*dev
= crtc
->base
.dev
;
11550 struct intel_encoder
*encoder
;
11551 struct intel_connector
*connector
;
11553 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11554 pipe_name(crtc
->pipe
));
11556 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11557 if (connector
->new_encoder
&&
11558 connector
->new_encoder
->new_crtc
== crtc
)
11559 connector
->new_encoder
= NULL
;
11562 for_each_intel_encoder(dev
, encoder
) {
11563 if (encoder
->new_crtc
== crtc
)
11564 encoder
->new_crtc
= NULL
;
11567 crtc
->new_enabled
= false;
11568 crtc
->new_config
= NULL
;
11571 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11573 struct drm_device
*dev
;
11574 struct drm_mode_set save_set
;
11575 struct intel_set_config
*config
;
11576 struct intel_crtc_state
*pipe_config
;
11577 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
11581 BUG_ON(!set
->crtc
);
11582 BUG_ON(!set
->crtc
->helper_private
);
11584 /* Enforce sane interface api - has been abused by the fb helper. */
11585 BUG_ON(!set
->mode
&& set
->fb
);
11586 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11589 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11590 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11591 (int)set
->num_connectors
, set
->x
, set
->y
);
11593 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11596 dev
= set
->crtc
->dev
;
11599 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11603 ret
= intel_set_config_save_state(dev
, config
);
11607 save_set
.crtc
= set
->crtc
;
11608 save_set
.mode
= &set
->crtc
->mode
;
11609 save_set
.x
= set
->crtc
->x
;
11610 save_set
.y
= set
->crtc
->y
;
11611 save_set
.fb
= set
->crtc
->primary
->fb
;
11613 /* Compute whether we need a full modeset, only an fb base update or no
11614 * change at all. In the future we might also check whether only the
11615 * mode changed, e.g. for LVDS where we only change the panel fitter in
11617 intel_set_config_compute_mode_changes(set
, config
);
11619 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11623 pipe_config
= intel_modeset_compute_config(set
->crtc
, set
->mode
,
11628 if (IS_ERR(pipe_config
)) {
11629 ret
= PTR_ERR(pipe_config
);
11631 } else if (pipe_config
) {
11632 if (pipe_config
->has_audio
!=
11633 to_intel_crtc(set
->crtc
)->config
->has_audio
)
11634 config
->mode_changed
= true;
11637 * Note we have an issue here with infoframes: current code
11638 * only updates them on the full mode set path per hw
11639 * requirements. So here we should be checking for any
11640 * required changes and forcing a mode set.
11644 /* set_mode will free it in the mode_changed case */
11645 if (!config
->mode_changed
)
11646 kfree(pipe_config
);
11648 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
11650 if (config
->mode_changed
) {
11651 ret
= intel_set_mode_pipes(set
->crtc
, set
->mode
,
11652 set
->x
, set
->y
, set
->fb
, pipe_config
,
11653 modeset_pipes
, prepare_pipes
,
11655 } else if (config
->fb_changed
) {
11656 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11657 struct drm_plane
*primary
= set
->crtc
->primary
;
11658 int vdisplay
, hdisplay
;
11660 drm_crtc_get_hv_timing(set
->mode
, &hdisplay
, &vdisplay
);
11661 ret
= primary
->funcs
->update_plane(primary
, set
->crtc
, set
->fb
,
11662 0, 0, hdisplay
, vdisplay
,
11663 set
->x
<< 16, set
->y
<< 16,
11664 hdisplay
<< 16, vdisplay
<< 16);
11667 * We need to make sure the primary plane is re-enabled if it
11668 * has previously been turned off.
11670 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11671 WARN_ON(!intel_crtc
->active
);
11672 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11676 * In the fastboot case this may be our only check of the
11677 * state after boot. It would be better to only do it on
11678 * the first update, but we don't have a nice way of doing that
11679 * (and really, set_config isn't used much for high freq page
11680 * flipping, so increasing its cost here shouldn't be a big
11683 if (i915
.fastboot
&& ret
== 0)
11684 intel_modeset_check_state(set
->crtc
->dev
);
11688 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11689 set
->crtc
->base
.id
, ret
);
11691 intel_set_config_restore_state(dev
, config
);
11694 * HACK: if the pipe was on, but we didn't have a framebuffer,
11695 * force the pipe off to avoid oopsing in the modeset code
11696 * due to fb==NULL. This should only happen during boot since
11697 * we don't yet reconstruct the FB from the hardware state.
11699 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11700 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11702 /* Try to restore the config */
11703 if (config
->mode_changed
&&
11704 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11705 save_set
.x
, save_set
.y
, save_set
.fb
))
11706 DRM_ERROR("failed to restore config after modeset failure\n");
11710 intel_set_config_free(config
);
11714 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11715 .gamma_set
= intel_crtc_gamma_set
,
11716 .set_config
= intel_crtc_set_config
,
11717 .destroy
= intel_crtc_destroy
,
11718 .page_flip
= intel_crtc_page_flip
,
11719 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
11720 .atomic_destroy_state
= intel_crtc_destroy_state
,
11723 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11724 struct intel_shared_dpll
*pll
,
11725 struct intel_dpll_hw_state
*hw_state
)
11729 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11732 val
= I915_READ(PCH_DPLL(pll
->id
));
11733 hw_state
->dpll
= val
;
11734 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11735 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11737 return val
& DPLL_VCO_ENABLE
;
11740 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11741 struct intel_shared_dpll
*pll
)
11743 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
11744 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
11747 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11748 struct intel_shared_dpll
*pll
)
11750 /* PCH refclock must be enabled first */
11751 ibx_assert_pch_refclk_enabled(dev_priv
);
11753 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11755 /* Wait for the clocks to stabilize. */
11756 POSTING_READ(PCH_DPLL(pll
->id
));
11759 /* The pixel multiplier can only be updated once the
11760 * DPLL is enabled and the clocks are stable.
11762 * So write it again.
11764 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11765 POSTING_READ(PCH_DPLL(pll
->id
));
11769 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11770 struct intel_shared_dpll
*pll
)
11772 struct drm_device
*dev
= dev_priv
->dev
;
11773 struct intel_crtc
*crtc
;
11775 /* Make sure no transcoder isn't still depending on us. */
11776 for_each_intel_crtc(dev
, crtc
) {
11777 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11778 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11781 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11782 POSTING_READ(PCH_DPLL(pll
->id
));
11786 static char *ibx_pch_dpll_names
[] = {
11791 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11796 dev_priv
->num_shared_dpll
= 2;
11798 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11799 dev_priv
->shared_dplls
[i
].id
= i
;
11800 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11801 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11802 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11803 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11804 dev_priv
->shared_dplls
[i
].get_hw_state
=
11805 ibx_pch_dpll_get_hw_state
;
11809 static void intel_shared_dpll_init(struct drm_device
*dev
)
11811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11814 intel_ddi_pll_init(dev
);
11815 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11816 ibx_pch_dpll_init(dev
);
11818 dev_priv
->num_shared_dpll
= 0;
11820 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11824 * intel_prepare_plane_fb - Prepare fb for usage on plane
11825 * @plane: drm plane to prepare for
11826 * @fb: framebuffer to prepare for presentation
11828 * Prepares a framebuffer for usage on a display plane. Generally this
11829 * involves pinning the underlying object and updating the frontbuffer tracking
11830 * bits. Some older platforms need special physical address handling for
11833 * Returns 0 on success, negative error code on failure.
11836 intel_prepare_plane_fb(struct drm_plane
*plane
,
11837 struct drm_framebuffer
*fb
)
11839 struct drm_device
*dev
= plane
->dev
;
11840 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11841 enum pipe pipe
= intel_plane
->pipe
;
11842 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11843 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11844 unsigned frontbuffer_bits
= 0;
11850 switch (plane
->type
) {
11851 case DRM_PLANE_TYPE_PRIMARY
:
11852 frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
11854 case DRM_PLANE_TYPE_CURSOR
:
11855 frontbuffer_bits
= INTEL_FRONTBUFFER_CURSOR(pipe
);
11857 case DRM_PLANE_TYPE_OVERLAY
:
11858 frontbuffer_bits
= INTEL_FRONTBUFFER_SPRITE(pipe
);
11862 mutex_lock(&dev
->struct_mutex
);
11864 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
11865 INTEL_INFO(dev
)->cursor_needs_physical
) {
11866 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
11867 ret
= i915_gem_object_attach_phys(obj
, align
);
11869 DRM_DEBUG_KMS("failed to attach phys object\n");
11871 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, NULL
);
11875 i915_gem_track_fb(old_obj
, obj
, frontbuffer_bits
);
11877 mutex_unlock(&dev
->struct_mutex
);
11883 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11884 * @plane: drm plane to clean up for
11885 * @fb: old framebuffer that was on plane
11887 * Cleans up a framebuffer that has just been removed from a plane.
11890 intel_cleanup_plane_fb(struct drm_plane
*plane
,
11891 struct drm_framebuffer
*fb
)
11893 struct drm_device
*dev
= plane
->dev
;
11894 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11899 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
11900 !INTEL_INFO(dev
)->cursor_needs_physical
) {
11901 mutex_lock(&dev
->struct_mutex
);
11902 intel_unpin_fb_obj(obj
);
11903 mutex_unlock(&dev
->struct_mutex
);
11908 intel_check_primary_plane(struct drm_plane
*plane
,
11909 struct intel_plane_state
*state
)
11911 struct drm_device
*dev
= plane
->dev
;
11912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11913 struct drm_crtc
*crtc
= state
->base
.crtc
;
11914 struct intel_crtc
*intel_crtc
;
11915 struct drm_framebuffer
*fb
= state
->base
.fb
;
11916 struct drm_rect
*dest
= &state
->dst
;
11917 struct drm_rect
*src
= &state
->src
;
11918 const struct drm_rect
*clip
= &state
->clip
;
11921 crtc
= crtc
? crtc
: plane
->crtc
;
11922 intel_crtc
= to_intel_crtc(crtc
);
11924 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11926 DRM_PLANE_HELPER_NO_SCALING
,
11927 DRM_PLANE_HELPER_NO_SCALING
,
11928 false, true, &state
->visible
);
11932 if (intel_crtc
->active
) {
11933 intel_crtc
->atomic
.wait_for_flips
= true;
11936 * FBC does not work on some platforms for rotated
11937 * planes, so disable it when rotation is not 0 and
11938 * update it when rotation is set back to 0.
11940 * FIXME: This is redundant with the fbc update done in
11941 * the primary plane enable function except that that
11942 * one is done too late. We eventually need to unify
11945 if (intel_crtc
->primary_enabled
&&
11946 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11947 dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
11948 state
->base
.rotation
!= BIT(DRM_ROTATE_0
)) {
11949 intel_crtc
->atomic
.disable_fbc
= true;
11952 if (state
->visible
) {
11954 * BDW signals flip done immediately if the plane
11955 * is disabled, even if the plane enable is already
11956 * armed to occur at the next vblank :(
11958 if (IS_BROADWELL(dev
) && !intel_crtc
->primary_enabled
)
11959 intel_crtc
->atomic
.wait_vblank
= true;
11962 intel_crtc
->atomic
.fb_bits
|=
11963 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
11965 intel_crtc
->atomic
.update_fbc
= true;
11972 intel_commit_primary_plane(struct drm_plane
*plane
,
11973 struct intel_plane_state
*state
)
11975 struct drm_crtc
*crtc
= state
->base
.crtc
;
11976 struct drm_framebuffer
*fb
= state
->base
.fb
;
11977 struct drm_device
*dev
= plane
->dev
;
11978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11979 struct intel_crtc
*intel_crtc
;
11980 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11981 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11982 struct drm_rect
*src
= &state
->src
;
11984 crtc
= crtc
? crtc
: plane
->crtc
;
11985 intel_crtc
= to_intel_crtc(crtc
);
11988 crtc
->x
= src
->x1
>> 16;
11989 crtc
->y
= src
->y1
>> 16;
11991 intel_plane
->obj
= obj
;
11993 if (intel_crtc
->active
) {
11994 if (state
->visible
) {
11995 /* FIXME: kill this fastboot hack */
11996 intel_update_pipe_size(intel_crtc
);
11998 intel_crtc
->primary_enabled
= true;
12000 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
12004 * If clipping results in a non-visible primary plane,
12005 * we'll disable the primary plane. Note that this is
12006 * a bit different than what happens if userspace
12007 * explicitly disables the plane by passing fb=0
12008 * because plane->fb still gets set and pinned.
12010 intel_disable_primary_hw_plane(plane
, crtc
);
12015 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
)
12017 struct drm_device
*dev
= crtc
->dev
;
12018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12019 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12020 struct intel_plane
*intel_plane
;
12021 struct drm_plane
*p
;
12022 unsigned fb_bits
= 0;
12024 /* Track fb's for any planes being disabled */
12025 list_for_each_entry(p
, &dev
->mode_config
.plane_list
, head
) {
12026 intel_plane
= to_intel_plane(p
);
12028 if (intel_crtc
->atomic
.disabled_planes
&
12029 (1 << drm_plane_index(p
))) {
12031 case DRM_PLANE_TYPE_PRIMARY
:
12032 fb_bits
= INTEL_FRONTBUFFER_PRIMARY(intel_plane
->pipe
);
12034 case DRM_PLANE_TYPE_CURSOR
:
12035 fb_bits
= INTEL_FRONTBUFFER_CURSOR(intel_plane
->pipe
);
12037 case DRM_PLANE_TYPE_OVERLAY
:
12038 fb_bits
= INTEL_FRONTBUFFER_SPRITE(intel_plane
->pipe
);
12042 mutex_lock(&dev
->struct_mutex
);
12043 i915_gem_track_fb(intel_fb_obj(p
->fb
), NULL
, fb_bits
);
12044 mutex_unlock(&dev
->struct_mutex
);
12048 if (intel_crtc
->atomic
.wait_for_flips
)
12049 intel_crtc_wait_for_pending_flips(crtc
);
12051 if (intel_crtc
->atomic
.disable_fbc
)
12052 intel_fbc_disable(dev
);
12054 if (intel_crtc
->atomic
.pre_disable_primary
)
12055 intel_pre_disable_primary(crtc
);
12057 if (intel_crtc
->atomic
.update_wm
)
12058 intel_update_watermarks(crtc
);
12060 intel_runtime_pm_get(dev_priv
);
12062 /* Perform vblank evasion around commit operation */
12063 if (intel_crtc
->active
)
12064 intel_crtc
->atomic
.evade
=
12065 intel_pipe_update_start(intel_crtc
,
12066 &intel_crtc
->atomic
.start_vbl_count
);
12069 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
)
12071 struct drm_device
*dev
= crtc
->dev
;
12072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12073 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12074 struct drm_plane
*p
;
12076 if (intel_crtc
->atomic
.evade
)
12077 intel_pipe_update_end(intel_crtc
,
12078 intel_crtc
->atomic
.start_vbl_count
);
12080 intel_runtime_pm_put(dev_priv
);
12082 if (intel_crtc
->atomic
.wait_vblank
)
12083 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
12085 intel_frontbuffer_flip(dev
, intel_crtc
->atomic
.fb_bits
);
12087 if (intel_crtc
->atomic
.update_fbc
) {
12088 mutex_lock(&dev
->struct_mutex
);
12089 intel_fbc_update(dev
);
12090 mutex_unlock(&dev
->struct_mutex
);
12093 if (intel_crtc
->atomic
.post_enable_primary
)
12094 intel_post_enable_primary(crtc
);
12096 drm_for_each_legacy_plane(p
, &dev
->mode_config
.plane_list
)
12097 if (intel_crtc
->atomic
.update_sprite_watermarks
& drm_plane_index(p
))
12098 intel_update_sprite_watermarks(p
, crtc
, 0, 0, 0,
12101 memset(&intel_crtc
->atomic
, 0, sizeof(intel_crtc
->atomic
));
12105 * intel_plane_destroy - destroy a plane
12106 * @plane: plane to destroy
12108 * Common destruction function for all types of planes (primary, cursor,
12111 void intel_plane_destroy(struct drm_plane
*plane
)
12113 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12114 drm_plane_cleanup(plane
);
12115 kfree(intel_plane
);
12118 const struct drm_plane_funcs intel_plane_funcs
= {
12119 .update_plane
= drm_plane_helper_update
,
12120 .disable_plane
= drm_plane_helper_disable
,
12121 .destroy
= intel_plane_destroy
,
12122 .set_property
= drm_atomic_helper_plane_set_property
,
12123 .atomic_get_property
= intel_plane_atomic_get_property
,
12124 .atomic_set_property
= intel_plane_atomic_set_property
,
12125 .atomic_duplicate_state
= intel_plane_duplicate_state
,
12126 .atomic_destroy_state
= intel_plane_destroy_state
,
12130 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
12133 struct intel_plane
*primary
;
12134 struct intel_plane_state
*state
;
12135 const uint32_t *intel_primary_formats
;
12138 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
12139 if (primary
== NULL
)
12142 state
= intel_create_plane_state(&primary
->base
);
12147 primary
->base
.state
= &state
->base
;
12149 primary
->can_scale
= false;
12150 primary
->max_downscale
= 1;
12151 primary
->pipe
= pipe
;
12152 primary
->plane
= pipe
;
12153 primary
->check_plane
= intel_check_primary_plane
;
12154 primary
->commit_plane
= intel_commit_primary_plane
;
12155 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
12156 primary
->plane
= !pipe
;
12158 if (INTEL_INFO(dev
)->gen
<= 3) {
12159 intel_primary_formats
= intel_primary_formats_gen2
;
12160 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
12162 intel_primary_formats
= intel_primary_formats_gen4
;
12163 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
12166 drm_universal_plane_init(dev
, &primary
->base
, 0,
12167 &intel_plane_funcs
,
12168 intel_primary_formats
, num_formats
,
12169 DRM_PLANE_TYPE_PRIMARY
);
12171 if (INTEL_INFO(dev
)->gen
>= 4) {
12172 if (!dev
->mode_config
.rotation_property
)
12173 dev
->mode_config
.rotation_property
=
12174 drm_mode_create_rotation_property(dev
,
12175 BIT(DRM_ROTATE_0
) |
12176 BIT(DRM_ROTATE_180
));
12177 if (dev
->mode_config
.rotation_property
)
12178 drm_object_attach_property(&primary
->base
.base
,
12179 dev
->mode_config
.rotation_property
,
12180 state
->base
.rotation
);
12183 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
12185 return &primary
->base
;
12189 intel_check_cursor_plane(struct drm_plane
*plane
,
12190 struct intel_plane_state
*state
)
12192 struct drm_crtc
*crtc
= state
->base
.crtc
;
12193 struct drm_device
*dev
= plane
->dev
;
12194 struct drm_framebuffer
*fb
= state
->base
.fb
;
12195 struct drm_rect
*dest
= &state
->dst
;
12196 struct drm_rect
*src
= &state
->src
;
12197 const struct drm_rect
*clip
= &state
->clip
;
12198 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12199 struct intel_crtc
*intel_crtc
;
12203 crtc
= crtc
? crtc
: plane
->crtc
;
12204 intel_crtc
= to_intel_crtc(crtc
);
12206 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
12208 DRM_PLANE_HELPER_NO_SCALING
,
12209 DRM_PLANE_HELPER_NO_SCALING
,
12210 true, true, &state
->visible
);
12215 /* if we want to turn off the cursor ignore width and height */
12219 /* Check for which cursor types we support */
12220 if (!cursor_size_ok(dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
12221 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12222 state
->base
.crtc_w
, state
->base
.crtc_h
);
12226 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
12227 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
12228 DRM_DEBUG_KMS("buffer is too small\n");
12232 /* we only need to pin inside GTT if cursor is non-phy */
12233 mutex_lock(&dev
->struct_mutex
);
12234 if (!INTEL_INFO(dev
)->cursor_needs_physical
&& obj
->tiling_mode
) {
12235 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12238 mutex_unlock(&dev
->struct_mutex
);
12241 if (intel_crtc
->active
) {
12242 if (intel_crtc
->cursor_width
!= state
->base
.crtc_w
)
12243 intel_crtc
->atomic
.update_wm
= true;
12245 intel_crtc
->atomic
.fb_bits
|=
12246 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
);
12253 intel_commit_cursor_plane(struct drm_plane
*plane
,
12254 struct intel_plane_state
*state
)
12256 struct drm_crtc
*crtc
= state
->base
.crtc
;
12257 struct drm_device
*dev
= plane
->dev
;
12258 struct intel_crtc
*intel_crtc
;
12259 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12260 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
12263 crtc
= crtc
? crtc
: plane
->crtc
;
12264 intel_crtc
= to_intel_crtc(crtc
);
12266 plane
->fb
= state
->base
.fb
;
12267 crtc
->cursor_x
= state
->base
.crtc_x
;
12268 crtc
->cursor_y
= state
->base
.crtc_y
;
12270 intel_plane
->obj
= obj
;
12272 if (intel_crtc
->cursor_bo
== obj
)
12277 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
12278 addr
= i915_gem_obj_ggtt_offset(obj
);
12280 addr
= obj
->phys_handle
->busaddr
;
12282 intel_crtc
->cursor_addr
= addr
;
12283 intel_crtc
->cursor_bo
= obj
;
12285 intel_crtc
->cursor_width
= state
->base
.crtc_w
;
12286 intel_crtc
->cursor_height
= state
->base
.crtc_h
;
12288 if (intel_crtc
->active
)
12289 intel_crtc_update_cursor(crtc
, state
->visible
);
12292 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
12295 struct intel_plane
*cursor
;
12296 struct intel_plane_state
*state
;
12298 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
12299 if (cursor
== NULL
)
12302 state
= intel_create_plane_state(&cursor
->base
);
12307 cursor
->base
.state
= &state
->base
;
12309 cursor
->can_scale
= false;
12310 cursor
->max_downscale
= 1;
12311 cursor
->pipe
= pipe
;
12312 cursor
->plane
= pipe
;
12313 cursor
->check_plane
= intel_check_cursor_plane
;
12314 cursor
->commit_plane
= intel_commit_cursor_plane
;
12316 drm_universal_plane_init(dev
, &cursor
->base
, 0,
12317 &intel_plane_funcs
,
12318 intel_cursor_formats
,
12319 ARRAY_SIZE(intel_cursor_formats
),
12320 DRM_PLANE_TYPE_CURSOR
);
12322 if (INTEL_INFO(dev
)->gen
>= 4) {
12323 if (!dev
->mode_config
.rotation_property
)
12324 dev
->mode_config
.rotation_property
=
12325 drm_mode_create_rotation_property(dev
,
12326 BIT(DRM_ROTATE_0
) |
12327 BIT(DRM_ROTATE_180
));
12328 if (dev
->mode_config
.rotation_property
)
12329 drm_object_attach_property(&cursor
->base
.base
,
12330 dev
->mode_config
.rotation_property
,
12331 state
->base
.rotation
);
12334 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
12336 return &cursor
->base
;
12339 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
12341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12342 struct intel_crtc
*intel_crtc
;
12343 struct intel_crtc_state
*crtc_state
= NULL
;
12344 struct drm_plane
*primary
= NULL
;
12345 struct drm_plane
*cursor
= NULL
;
12348 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
12349 if (intel_crtc
== NULL
)
12352 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
12355 intel_crtc_set_state(intel_crtc
, crtc_state
);
12357 primary
= intel_primary_plane_create(dev
, pipe
);
12361 cursor
= intel_cursor_plane_create(dev
, pipe
);
12365 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
12366 cursor
, &intel_crtc_funcs
);
12370 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
12371 for (i
= 0; i
< 256; i
++) {
12372 intel_crtc
->lut_r
[i
] = i
;
12373 intel_crtc
->lut_g
[i
] = i
;
12374 intel_crtc
->lut_b
[i
] = i
;
12378 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12379 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12381 intel_crtc
->pipe
= pipe
;
12382 intel_crtc
->plane
= pipe
;
12383 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
12384 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12385 intel_crtc
->plane
= !pipe
;
12388 intel_crtc
->cursor_base
= ~0;
12389 intel_crtc
->cursor_cntl
= ~0;
12390 intel_crtc
->cursor_size
= ~0;
12392 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
12393 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
12394 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
12395 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
12397 INIT_WORK(&intel_crtc
->mmio_flip
.work
, intel_mmio_flip_work_func
);
12399 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
12401 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
12406 drm_plane_cleanup(primary
);
12408 drm_plane_cleanup(cursor
);
12413 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
12415 struct drm_encoder
*encoder
= connector
->base
.encoder
;
12416 struct drm_device
*dev
= connector
->base
.dev
;
12418 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12420 if (!encoder
|| WARN_ON(!encoder
->crtc
))
12421 return INVALID_PIPE
;
12423 return to_intel_crtc(encoder
->crtc
)->pipe
;
12426 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12427 struct drm_file
*file
)
12429 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12430 struct drm_crtc
*drmmode_crtc
;
12431 struct intel_crtc
*crtc
;
12433 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
12436 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12438 if (!drmmode_crtc
) {
12439 DRM_ERROR("no such CRTC id\n");
12443 crtc
= to_intel_crtc(drmmode_crtc
);
12444 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12449 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12451 struct drm_device
*dev
= encoder
->base
.dev
;
12452 struct intel_encoder
*source_encoder
;
12453 int index_mask
= 0;
12456 for_each_intel_encoder(dev
, source_encoder
) {
12457 if (encoders_cloneable(encoder
, source_encoder
))
12458 index_mask
|= (1 << entry
);
12466 static bool has_edp_a(struct drm_device
*dev
)
12468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12470 if (!IS_MOBILE(dev
))
12473 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12476 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12482 static bool intel_crt_present(struct drm_device
*dev
)
12484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12486 if (INTEL_INFO(dev
)->gen
>= 9)
12489 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
12492 if (IS_CHERRYVIEW(dev
))
12495 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12501 static void intel_setup_outputs(struct drm_device
*dev
)
12503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12504 struct intel_encoder
*encoder
;
12505 struct drm_connector
*connector
;
12506 bool dpd_is_edp
= false;
12508 intel_lvds_init(dev
);
12510 if (intel_crt_present(dev
))
12511 intel_crt_init(dev
);
12513 if (HAS_DDI(dev
)) {
12516 /* Haswell uses DDI functions to detect digital outputs */
12517 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12518 /* DDI A only supports eDP */
12520 intel_ddi_init(dev
, PORT_A
);
12522 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12524 found
= I915_READ(SFUSE_STRAP
);
12526 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12527 intel_ddi_init(dev
, PORT_B
);
12528 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12529 intel_ddi_init(dev
, PORT_C
);
12530 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12531 intel_ddi_init(dev
, PORT_D
);
12532 } else if (HAS_PCH_SPLIT(dev
)) {
12534 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12536 if (has_edp_a(dev
))
12537 intel_dp_init(dev
, DP_A
, PORT_A
);
12539 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12540 /* PCH SDVOB multiplex with HDMIB */
12541 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12543 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12544 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12545 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12548 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12549 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12551 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12552 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12554 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12555 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12557 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12558 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12559 } else if (IS_VALLEYVIEW(dev
)) {
12561 * The DP_DETECTED bit is the latched state of the DDC
12562 * SDA pin at boot. However since eDP doesn't require DDC
12563 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12564 * eDP ports may have been muxed to an alternate function.
12565 * Thus we can't rely on the DP_DETECTED bit alone to detect
12566 * eDP ports. Consult the VBT as well as DP_DETECTED to
12567 * detect eDP ports.
12569 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
12570 !intel_dp_is_edp(dev
, PORT_B
))
12571 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12573 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
12574 intel_dp_is_edp(dev
, PORT_B
))
12575 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12577 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
12578 !intel_dp_is_edp(dev
, PORT_C
))
12579 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12581 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
12582 intel_dp_is_edp(dev
, PORT_C
))
12583 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12585 if (IS_CHERRYVIEW(dev
)) {
12586 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
12587 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12589 /* eDP not supported on port D, so don't check VBT */
12590 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12591 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12594 intel_dsi_init(dev
);
12595 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12596 bool found
= false;
12598 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12599 DRM_DEBUG_KMS("probing SDVOB\n");
12600 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12601 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12602 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12603 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12606 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12607 intel_dp_init(dev
, DP_B
, PORT_B
);
12610 /* Before G4X SDVOC doesn't have its own detect register */
12612 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12613 DRM_DEBUG_KMS("probing SDVOC\n");
12614 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12617 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12619 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12620 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12621 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12623 if (SUPPORTS_INTEGRATED_DP(dev
))
12624 intel_dp_init(dev
, DP_C
, PORT_C
);
12627 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12628 (I915_READ(DP_D
) & DP_DETECTED
))
12629 intel_dp_init(dev
, DP_D
, PORT_D
);
12630 } else if (IS_GEN2(dev
))
12631 intel_dvo_init(dev
);
12633 if (SUPPORTS_TV(dev
))
12634 intel_tv_init(dev
);
12637 * FIXME: We don't have full atomic support yet, but we want to be
12638 * able to enable/test plane updates via the atomic interface in the
12639 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12640 * will take some atomic codepaths to lookup properties during
12641 * drmModeGetConnector() that unconditionally dereference
12642 * connector->state.
12644 * We create a dummy connector state here for each connector to ensure
12645 * the DRM core doesn't try to dereference a NULL connector->state.
12646 * The actual connector properties will never be updated or contain
12647 * useful information, but since we're doing this specifically for
12648 * testing/debug of the plane operations (and only when a specific
12649 * kernel module option is given), that shouldn't really matter.
12651 * Once atomic support for crtc's + connectors lands, this loop should
12652 * be removed since we'll be setting up real connector state, which
12653 * will contain Intel-specific properties.
12655 if (drm_core_check_feature(dev
, DRIVER_ATOMIC
)) {
12656 list_for_each_entry(connector
,
12657 &dev
->mode_config
.connector_list
,
12659 if (!WARN_ON(connector
->state
)) {
12661 kzalloc(sizeof(*connector
->state
),
12667 intel_psr_init(dev
);
12669 for_each_intel_encoder(dev
, encoder
) {
12670 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12671 encoder
->base
.possible_clones
=
12672 intel_encoder_clones(encoder
);
12675 intel_init_pch_refclk(dev
);
12677 drm_helper_move_panel_connectors_to_head(dev
);
12680 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12682 struct drm_device
*dev
= fb
->dev
;
12683 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12685 drm_framebuffer_cleanup(fb
);
12686 mutex_lock(&dev
->struct_mutex
);
12687 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12688 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12689 mutex_unlock(&dev
->struct_mutex
);
12693 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12694 struct drm_file
*file
,
12695 unsigned int *handle
)
12697 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12698 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12700 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12703 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12704 .destroy
= intel_user_framebuffer_destroy
,
12705 .create_handle
= intel_user_framebuffer_create_handle
,
12708 static int intel_framebuffer_init(struct drm_device
*dev
,
12709 struct intel_framebuffer
*intel_fb
,
12710 struct drm_mode_fb_cmd2
*mode_cmd
,
12711 struct drm_i915_gem_object
*obj
)
12713 int aligned_height
;
12717 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12719 if (obj
->tiling_mode
== I915_TILING_Y
) {
12720 DRM_DEBUG("hardware does not support tiling Y\n");
12724 if (mode_cmd
->pitches
[0] & 63) {
12725 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12726 mode_cmd
->pitches
[0]);
12730 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12731 pitch_limit
= 32*1024;
12732 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12733 if (obj
->tiling_mode
)
12734 pitch_limit
= 16*1024;
12736 pitch_limit
= 32*1024;
12737 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12738 if (obj
->tiling_mode
)
12739 pitch_limit
= 8*1024;
12741 pitch_limit
= 16*1024;
12743 /* XXX DSPC is limited to 4k tiled */
12744 pitch_limit
= 8*1024;
12746 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12747 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12748 obj
->tiling_mode
? "tiled" : "linear",
12749 mode_cmd
->pitches
[0], pitch_limit
);
12753 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12754 mode_cmd
->pitches
[0] != obj
->stride
) {
12755 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12756 mode_cmd
->pitches
[0], obj
->stride
);
12760 /* Reject formats not supported by any plane early. */
12761 switch (mode_cmd
->pixel_format
) {
12762 case DRM_FORMAT_C8
:
12763 case DRM_FORMAT_RGB565
:
12764 case DRM_FORMAT_XRGB8888
:
12765 case DRM_FORMAT_ARGB8888
:
12767 case DRM_FORMAT_XRGB1555
:
12768 case DRM_FORMAT_ARGB1555
:
12769 if (INTEL_INFO(dev
)->gen
> 3) {
12770 DRM_DEBUG("unsupported pixel format: %s\n",
12771 drm_get_format_name(mode_cmd
->pixel_format
));
12775 case DRM_FORMAT_XBGR8888
:
12776 case DRM_FORMAT_ABGR8888
:
12777 case DRM_FORMAT_XRGB2101010
:
12778 case DRM_FORMAT_ARGB2101010
:
12779 case DRM_FORMAT_XBGR2101010
:
12780 case DRM_FORMAT_ABGR2101010
:
12781 if (INTEL_INFO(dev
)->gen
< 4) {
12782 DRM_DEBUG("unsupported pixel format: %s\n",
12783 drm_get_format_name(mode_cmd
->pixel_format
));
12787 case DRM_FORMAT_YUYV
:
12788 case DRM_FORMAT_UYVY
:
12789 case DRM_FORMAT_YVYU
:
12790 case DRM_FORMAT_VYUY
:
12791 if (INTEL_INFO(dev
)->gen
< 5) {
12792 DRM_DEBUG("unsupported pixel format: %s\n",
12793 drm_get_format_name(mode_cmd
->pixel_format
));
12798 DRM_DEBUG("unsupported pixel format: %s\n",
12799 drm_get_format_name(mode_cmd
->pixel_format
));
12803 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12804 if (mode_cmd
->offsets
[0] != 0)
12807 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
12809 /* FIXME drm helper for size checks (especially planar formats)? */
12810 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12813 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12814 intel_fb
->obj
= obj
;
12815 intel_fb
->obj
->framebuffer_references
++;
12817 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12819 DRM_ERROR("framebuffer init failed %d\n", ret
);
12826 static struct drm_framebuffer
*
12827 intel_user_framebuffer_create(struct drm_device
*dev
,
12828 struct drm_file
*filp
,
12829 struct drm_mode_fb_cmd2
*mode_cmd
)
12831 struct drm_i915_gem_object
*obj
;
12833 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12834 mode_cmd
->handles
[0]));
12835 if (&obj
->base
== NULL
)
12836 return ERR_PTR(-ENOENT
);
12838 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12841 #ifndef CONFIG_DRM_I915_FBDEV
12842 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12847 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12848 .fb_create
= intel_user_framebuffer_create
,
12849 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12850 .atomic_check
= intel_atomic_check
,
12851 .atomic_commit
= intel_atomic_commit
,
12854 /* Set up chip specific display functions */
12855 static void intel_init_display(struct drm_device
*dev
)
12857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12859 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12860 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12861 else if (IS_CHERRYVIEW(dev
))
12862 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12863 else if (IS_VALLEYVIEW(dev
))
12864 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12865 else if (IS_PINEVIEW(dev
))
12866 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12868 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12870 if (INTEL_INFO(dev
)->gen
>= 9) {
12871 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12872 dev_priv
->display
.get_initial_plane_config
=
12873 skylake_get_initial_plane_config
;
12874 dev_priv
->display
.crtc_compute_clock
=
12875 haswell_crtc_compute_clock
;
12876 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12877 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12878 dev_priv
->display
.off
= ironlake_crtc_off
;
12879 dev_priv
->display
.update_primary_plane
=
12880 skylake_update_primary_plane
;
12881 } else if (HAS_DDI(dev
)) {
12882 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12883 dev_priv
->display
.get_initial_plane_config
=
12884 ironlake_get_initial_plane_config
;
12885 dev_priv
->display
.crtc_compute_clock
=
12886 haswell_crtc_compute_clock
;
12887 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12888 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12889 dev_priv
->display
.off
= ironlake_crtc_off
;
12890 dev_priv
->display
.update_primary_plane
=
12891 ironlake_update_primary_plane
;
12892 } else if (HAS_PCH_SPLIT(dev
)) {
12893 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12894 dev_priv
->display
.get_initial_plane_config
=
12895 ironlake_get_initial_plane_config
;
12896 dev_priv
->display
.crtc_compute_clock
=
12897 ironlake_crtc_compute_clock
;
12898 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12899 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12900 dev_priv
->display
.off
= ironlake_crtc_off
;
12901 dev_priv
->display
.update_primary_plane
=
12902 ironlake_update_primary_plane
;
12903 } else if (IS_VALLEYVIEW(dev
)) {
12904 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12905 dev_priv
->display
.get_initial_plane_config
=
12906 i9xx_get_initial_plane_config
;
12907 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
12908 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12909 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12910 dev_priv
->display
.off
= i9xx_crtc_off
;
12911 dev_priv
->display
.update_primary_plane
=
12912 i9xx_update_primary_plane
;
12914 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12915 dev_priv
->display
.get_initial_plane_config
=
12916 i9xx_get_initial_plane_config
;
12917 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
12918 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12919 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12920 dev_priv
->display
.off
= i9xx_crtc_off
;
12921 dev_priv
->display
.update_primary_plane
=
12922 i9xx_update_primary_plane
;
12925 /* Returns the core display clock speed */
12926 if (IS_VALLEYVIEW(dev
))
12927 dev_priv
->display
.get_display_clock_speed
=
12928 valleyview_get_display_clock_speed
;
12929 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12930 dev_priv
->display
.get_display_clock_speed
=
12931 i945_get_display_clock_speed
;
12932 else if (IS_I915G(dev
))
12933 dev_priv
->display
.get_display_clock_speed
=
12934 i915_get_display_clock_speed
;
12935 else if (IS_I945GM(dev
) || IS_845G(dev
))
12936 dev_priv
->display
.get_display_clock_speed
=
12937 i9xx_misc_get_display_clock_speed
;
12938 else if (IS_PINEVIEW(dev
))
12939 dev_priv
->display
.get_display_clock_speed
=
12940 pnv_get_display_clock_speed
;
12941 else if (IS_I915GM(dev
))
12942 dev_priv
->display
.get_display_clock_speed
=
12943 i915gm_get_display_clock_speed
;
12944 else if (IS_I865G(dev
))
12945 dev_priv
->display
.get_display_clock_speed
=
12946 i865_get_display_clock_speed
;
12947 else if (IS_I85X(dev
))
12948 dev_priv
->display
.get_display_clock_speed
=
12949 i855_get_display_clock_speed
;
12950 else /* 852, 830 */
12951 dev_priv
->display
.get_display_clock_speed
=
12952 i830_get_display_clock_speed
;
12954 if (IS_GEN5(dev
)) {
12955 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12956 } else if (IS_GEN6(dev
)) {
12957 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12958 } else if (IS_IVYBRIDGE(dev
)) {
12959 /* FIXME: detect B0+ stepping and use auto training */
12960 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12961 dev_priv
->display
.modeset_global_resources
=
12962 ivb_modeset_global_resources
;
12963 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
12964 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12965 } else if (IS_VALLEYVIEW(dev
)) {
12966 dev_priv
->display
.modeset_global_resources
=
12967 valleyview_modeset_global_resources
;
12970 /* Default just returns -ENODEV to indicate unsupported */
12971 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12973 switch (INTEL_INFO(dev
)->gen
) {
12975 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12979 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12984 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12988 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12991 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12992 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12995 dev_priv
->display
.queue_flip
= intel_gen9_queue_flip
;
12999 intel_panel_init_backlight_funcs(dev
);
13001 mutex_init(&dev_priv
->pps_mutex
);
13005 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13006 * resume, or other times. This quirk makes sure that's the case for
13007 * affected systems.
13009 static void quirk_pipea_force(struct drm_device
*dev
)
13011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13013 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
13014 DRM_INFO("applying pipe a force quirk\n");
13017 static void quirk_pipeb_force(struct drm_device
*dev
)
13019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13021 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
13022 DRM_INFO("applying pipe b force quirk\n");
13026 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13028 static void quirk_ssc_force_disable(struct drm_device
*dev
)
13030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13031 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
13032 DRM_INFO("applying lvds SSC disable quirk\n");
13036 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13039 static void quirk_invert_brightness(struct drm_device
*dev
)
13041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13042 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
13043 DRM_INFO("applying inverted panel brightness quirk\n");
13046 /* Some VBT's incorrectly indicate no backlight is present */
13047 static void quirk_backlight_present(struct drm_device
*dev
)
13049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13050 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
13051 DRM_INFO("applying backlight present quirk\n");
13054 struct intel_quirk
{
13056 int subsystem_vendor
;
13057 int subsystem_device
;
13058 void (*hook
)(struct drm_device
*dev
);
13061 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13062 struct intel_dmi_quirk
{
13063 void (*hook
)(struct drm_device
*dev
);
13064 const struct dmi_system_id (*dmi_id_list
)[];
13067 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
13069 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
13073 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
13075 .dmi_id_list
= &(const struct dmi_system_id
[]) {
13077 .callback
= intel_dmi_reverse_brightness
,
13078 .ident
= "NCR Corporation",
13079 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
13080 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
13083 { } /* terminating entry */
13085 .hook
= quirk_invert_brightness
,
13089 static struct intel_quirk intel_quirks
[] = {
13090 /* HP Mini needs pipe A force quirk (LP: #322104) */
13091 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
13093 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13094 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
13096 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13097 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
13099 /* 830 needs to leave pipe A & dpll A up */
13100 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
13102 /* 830 needs to leave pipe B & dpll B up */
13103 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
13105 /* Lenovo U160 cannot use SSC on LVDS */
13106 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
13108 /* Sony Vaio Y cannot use SSC on LVDS */
13109 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
13111 /* Acer Aspire 5734Z must invert backlight brightness */
13112 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
13114 /* Acer/eMachines G725 */
13115 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
13117 /* Acer/eMachines e725 */
13118 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
13120 /* Acer/Packard Bell NCL20 */
13121 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
13123 /* Acer Aspire 4736Z */
13124 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
13126 /* Acer Aspire 5336 */
13127 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
13129 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13130 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
13132 /* Acer C720 Chromebook (Core i3 4005U) */
13133 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
13135 /* Apple Macbook 2,1 (Core 2 T7400) */
13136 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
13138 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13139 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
13141 /* HP Chromebook 14 (Celeron 2955U) */
13142 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
13144 /* Dell Chromebook 11 */
13145 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
13148 static void intel_init_quirks(struct drm_device
*dev
)
13150 struct pci_dev
*d
= dev
->pdev
;
13153 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
13154 struct intel_quirk
*q
= &intel_quirks
[i
];
13156 if (d
->device
== q
->device
&&
13157 (d
->subsystem_vendor
== q
->subsystem_vendor
||
13158 q
->subsystem_vendor
== PCI_ANY_ID
) &&
13159 (d
->subsystem_device
== q
->subsystem_device
||
13160 q
->subsystem_device
== PCI_ANY_ID
))
13163 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
13164 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
13165 intel_dmi_quirks
[i
].hook(dev
);
13169 /* Disable the VGA plane that we never use */
13170 static void i915_disable_vga(struct drm_device
*dev
)
13172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13174 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13176 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13177 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
13178 outb(SR01
, VGA_SR_INDEX
);
13179 sr1
= inb(VGA_SR_DATA
);
13180 outb(sr1
| 1<<5, VGA_SR_DATA
);
13181 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
13184 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
13185 POSTING_READ(vga_reg
);
13188 void intel_modeset_init_hw(struct drm_device
*dev
)
13190 intel_prepare_ddi(dev
);
13192 if (IS_VALLEYVIEW(dev
))
13193 vlv_update_cdclk(dev
);
13195 intel_init_clock_gating(dev
);
13197 intel_enable_gt_powersave(dev
);
13200 void intel_modeset_init(struct drm_device
*dev
)
13202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13205 struct intel_crtc
*crtc
;
13207 drm_mode_config_init(dev
);
13209 dev
->mode_config
.min_width
= 0;
13210 dev
->mode_config
.min_height
= 0;
13212 dev
->mode_config
.preferred_depth
= 24;
13213 dev
->mode_config
.prefer_shadow
= 1;
13215 dev
->mode_config
.funcs
= &intel_mode_funcs
;
13217 intel_init_quirks(dev
);
13219 intel_init_pm(dev
);
13221 if (INTEL_INFO(dev
)->num_pipes
== 0)
13224 intel_init_display(dev
);
13225 intel_init_audio(dev
);
13227 if (IS_GEN2(dev
)) {
13228 dev
->mode_config
.max_width
= 2048;
13229 dev
->mode_config
.max_height
= 2048;
13230 } else if (IS_GEN3(dev
)) {
13231 dev
->mode_config
.max_width
= 4096;
13232 dev
->mode_config
.max_height
= 4096;
13234 dev
->mode_config
.max_width
= 8192;
13235 dev
->mode_config
.max_height
= 8192;
13238 if (IS_845G(dev
) || IS_I865G(dev
)) {
13239 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
13240 dev
->mode_config
.cursor_height
= 1023;
13241 } else if (IS_GEN2(dev
)) {
13242 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
13243 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
13245 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
13246 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
13249 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
13251 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13252 INTEL_INFO(dev
)->num_pipes
,
13253 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
13255 for_each_pipe(dev_priv
, pipe
) {
13256 intel_crtc_init(dev
, pipe
);
13257 for_each_sprite(pipe
, sprite
) {
13258 ret
= intel_plane_init(dev
, pipe
, sprite
);
13260 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13261 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
13265 intel_init_dpio(dev
);
13267 intel_shared_dpll_init(dev
);
13269 /* Just disable it once at startup */
13270 i915_disable_vga(dev
);
13271 intel_setup_outputs(dev
);
13273 /* Just in case the BIOS is doing something questionable. */
13274 intel_fbc_disable(dev
);
13276 drm_modeset_lock_all(dev
);
13277 intel_modeset_setup_hw_state(dev
, false);
13278 drm_modeset_unlock_all(dev
);
13280 for_each_intel_crtc(dev
, crtc
) {
13285 * Note that reserving the BIOS fb up front prevents us
13286 * from stuffing other stolen allocations like the ring
13287 * on top. This prevents some ugliness at boot time, and
13288 * can even allow for smooth boot transitions if the BIOS
13289 * fb is large enough for the active pipe configuration.
13291 if (dev_priv
->display
.get_initial_plane_config
) {
13292 dev_priv
->display
.get_initial_plane_config(crtc
,
13293 &crtc
->plane_config
);
13295 * If the fb is shared between multiple heads, we'll
13296 * just get the first one.
13298 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
13303 static void intel_enable_pipe_a(struct drm_device
*dev
)
13305 struct intel_connector
*connector
;
13306 struct drm_connector
*crt
= NULL
;
13307 struct intel_load_detect_pipe load_detect_temp
;
13308 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
13310 /* We can't just switch on the pipe A, we need to set things up with a
13311 * proper mode and output configuration. As a gross hack, enable pipe A
13312 * by enabling the load detect pipe once. */
13313 list_for_each_entry(connector
,
13314 &dev
->mode_config
.connector_list
,
13316 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
13317 crt
= &connector
->base
;
13325 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
13326 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
13330 intel_check_plane_mapping(struct intel_crtc
*crtc
)
13332 struct drm_device
*dev
= crtc
->base
.dev
;
13333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13336 if (INTEL_INFO(dev
)->num_pipes
== 1)
13339 reg
= DSPCNTR(!crtc
->plane
);
13340 val
= I915_READ(reg
);
13342 if ((val
& DISPLAY_PLANE_ENABLE
) &&
13343 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
13349 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
13351 struct drm_device
*dev
= crtc
->base
.dev
;
13352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13355 /* Clear any frame start delays used for debugging left by the BIOS */
13356 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
13357 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
13359 /* restore vblank interrupts to correct state */
13360 if (crtc
->active
) {
13361 update_scanline_offset(crtc
);
13362 drm_vblank_on(dev
, crtc
->pipe
);
13364 drm_vblank_off(dev
, crtc
->pipe
);
13366 /* We need to sanitize the plane -> pipe mapping first because this will
13367 * disable the crtc (and hence change the state) if it is wrong. Note
13368 * that gen4+ has a fixed plane -> pipe mapping. */
13369 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
13370 struct intel_connector
*connector
;
13373 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13374 crtc
->base
.base
.id
);
13376 /* Pipe has the wrong plane attached and the plane is active.
13377 * Temporarily change the plane mapping and disable everything
13379 plane
= crtc
->plane
;
13380 crtc
->plane
= !plane
;
13381 crtc
->primary_enabled
= true;
13382 dev_priv
->display
.crtc_disable(&crtc
->base
);
13383 crtc
->plane
= plane
;
13385 /* ... and break all links. */
13386 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13388 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
13391 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13392 connector
->base
.encoder
= NULL
;
13394 /* multiple connectors may have the same encoder:
13395 * handle them and break crtc link separately */
13396 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13398 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
13399 connector
->encoder
->base
.crtc
= NULL
;
13400 connector
->encoder
->connectors_active
= false;
13403 WARN_ON(crtc
->active
);
13404 crtc
->base
.enabled
= false;
13407 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
13408 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
13409 /* BIOS forgot to enable pipe A, this mostly happens after
13410 * resume. Force-enable the pipe to fix this, the update_dpms
13411 * call below we restore the pipe to the right state, but leave
13412 * the required bits on. */
13413 intel_enable_pipe_a(dev
);
13416 /* Adjust the state of the output pipe according to whether we
13417 * have active connectors/encoders. */
13418 intel_crtc_update_dpms(&crtc
->base
);
13420 if (crtc
->active
!= crtc
->base
.enabled
) {
13421 struct intel_encoder
*encoder
;
13423 /* This can happen either due to bugs in the get_hw_state
13424 * functions or because the pipe is force-enabled due to the
13426 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13427 crtc
->base
.base
.id
,
13428 crtc
->base
.enabled
? "enabled" : "disabled",
13429 crtc
->active
? "enabled" : "disabled");
13431 crtc
->base
.enabled
= crtc
->active
;
13433 /* Because we only establish the connector -> encoder ->
13434 * crtc links if something is active, this means the
13435 * crtc is now deactivated. Break the links. connector
13436 * -> encoder links are only establish when things are
13437 * actually up, hence no need to break them. */
13438 WARN_ON(crtc
->active
);
13440 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
13441 WARN_ON(encoder
->connectors_active
);
13442 encoder
->base
.crtc
= NULL
;
13446 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
13448 * We start out with underrun reporting disabled to avoid races.
13449 * For correct bookkeeping mark this on active crtcs.
13451 * Also on gmch platforms we dont have any hardware bits to
13452 * disable the underrun reporting. Which means we need to start
13453 * out with underrun reporting disabled also on inactive pipes,
13454 * since otherwise we'll complain about the garbage we read when
13455 * e.g. coming up after runtime pm.
13457 * No protection against concurrent access is required - at
13458 * worst a fifo underrun happens which also sets this to false.
13460 crtc
->cpu_fifo_underrun_disabled
= true;
13461 crtc
->pch_fifo_underrun_disabled
= true;
13465 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
13467 struct intel_connector
*connector
;
13468 struct drm_device
*dev
= encoder
->base
.dev
;
13470 /* We need to check both for a crtc link (meaning that the
13471 * encoder is active and trying to read from a pipe) and the
13472 * pipe itself being active. */
13473 bool has_active_crtc
= encoder
->base
.crtc
&&
13474 to_intel_crtc(encoder
->base
.crtc
)->active
;
13476 if (encoder
->connectors_active
&& !has_active_crtc
) {
13477 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13478 encoder
->base
.base
.id
,
13479 encoder
->base
.name
);
13481 /* Connector is active, but has no active pipe. This is
13482 * fallout from our resume register restoring. Disable
13483 * the encoder manually again. */
13484 if (encoder
->base
.crtc
) {
13485 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13486 encoder
->base
.base
.id
,
13487 encoder
->base
.name
);
13488 encoder
->disable(encoder
);
13489 if (encoder
->post_disable
)
13490 encoder
->post_disable(encoder
);
13492 encoder
->base
.crtc
= NULL
;
13493 encoder
->connectors_active
= false;
13495 /* Inconsistent output/port/pipe state happens presumably due to
13496 * a bug in one of the get_hw_state functions. Or someplace else
13497 * in our code, like the register restore mess on resume. Clamp
13498 * things to off as a safer default. */
13499 list_for_each_entry(connector
,
13500 &dev
->mode_config
.connector_list
,
13502 if (connector
->encoder
!= encoder
)
13504 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13505 connector
->base
.encoder
= NULL
;
13508 /* Enabled encoders without active connectors will be fixed in
13509 * the crtc fixup. */
13512 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13515 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13517 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13518 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13519 i915_disable_vga(dev
);
13523 void i915_redisable_vga(struct drm_device
*dev
)
13525 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13527 /* This function can be called both from intel_modeset_setup_hw_state or
13528 * at a very early point in our resume sequence, where the power well
13529 * structures are not yet restored. Since this function is at a very
13530 * paranoid "someone might have enabled VGA while we were not looking"
13531 * level, just check if the power well is enabled instead of trying to
13532 * follow the "don't touch the power well if we don't need it" policy
13533 * the rest of the driver uses. */
13534 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13537 i915_redisable_vga_power_on(dev
);
13540 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13542 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13547 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13550 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13554 struct intel_crtc
*crtc
;
13555 struct intel_encoder
*encoder
;
13556 struct intel_connector
*connector
;
13559 for_each_intel_crtc(dev
, crtc
) {
13560 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
13562 crtc
->config
->quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13564 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13567 crtc
->base
.enabled
= crtc
->active
;
13568 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13570 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13571 crtc
->base
.base
.id
,
13572 crtc
->active
? "enabled" : "disabled");
13575 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13576 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13578 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
13579 &pll
->config
.hw_state
);
13581 pll
->config
.crtc_mask
= 0;
13582 for_each_intel_crtc(dev
, crtc
) {
13583 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
13585 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
13589 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13590 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
13592 if (pll
->config
.crtc_mask
)
13593 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13596 for_each_intel_encoder(dev
, encoder
) {
13599 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13600 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13601 encoder
->base
.crtc
= &crtc
->base
;
13602 encoder
->get_config(encoder
, crtc
->config
);
13604 encoder
->base
.crtc
= NULL
;
13607 encoder
->connectors_active
= false;
13608 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13609 encoder
->base
.base
.id
,
13610 encoder
->base
.name
,
13611 encoder
->base
.crtc
? "enabled" : "disabled",
13615 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13617 if (connector
->get_hw_state(connector
)) {
13618 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13619 connector
->encoder
->connectors_active
= true;
13620 connector
->base
.encoder
= &connector
->encoder
->base
;
13622 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13623 connector
->base
.encoder
= NULL
;
13625 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13626 connector
->base
.base
.id
,
13627 connector
->base
.name
,
13628 connector
->base
.encoder
? "enabled" : "disabled");
13632 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13633 * and i915 state tracking structures. */
13634 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13635 bool force_restore
)
13637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13639 struct intel_crtc
*crtc
;
13640 struct intel_encoder
*encoder
;
13643 intel_modeset_readout_hw_state(dev
);
13646 * Now that we have the config, copy it to each CRTC struct
13647 * Note that this could go away if we move to using crtc_config
13648 * checking everywhere.
13650 for_each_intel_crtc(dev
, crtc
) {
13651 if (crtc
->active
&& i915
.fastboot
) {
13652 intel_mode_from_pipe_config(&crtc
->base
.mode
,
13654 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13655 crtc
->base
.base
.id
);
13656 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13660 /* HW state is read out, now we need to sanitize this mess. */
13661 for_each_intel_encoder(dev
, encoder
) {
13662 intel_sanitize_encoder(encoder
);
13665 for_each_pipe(dev_priv
, pipe
) {
13666 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13667 intel_sanitize_crtc(crtc
);
13668 intel_dump_pipe_config(crtc
, crtc
->config
,
13669 "[setup_hw_state]");
13672 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13673 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13675 if (!pll
->on
|| pll
->active
)
13678 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13680 pll
->disable(dev_priv
, pll
);
13685 skl_wm_get_hw_state(dev
);
13686 else if (HAS_PCH_SPLIT(dev
))
13687 ilk_wm_get_hw_state(dev
);
13689 if (force_restore
) {
13690 i915_redisable_vga(dev
);
13693 * We need to use raw interfaces for restoring state to avoid
13694 * checking (bogus) intermediate states.
13696 for_each_pipe(dev_priv
, pipe
) {
13697 struct drm_crtc
*crtc
=
13698 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13700 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13701 crtc
->primary
->fb
);
13704 intel_modeset_update_staged_output_state(dev
);
13707 intel_modeset_check_state(dev
);
13710 void intel_modeset_gem_init(struct drm_device
*dev
)
13712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13713 struct drm_crtc
*c
;
13714 struct drm_i915_gem_object
*obj
;
13716 mutex_lock(&dev
->struct_mutex
);
13717 intel_init_gt_powersave(dev
);
13718 mutex_unlock(&dev
->struct_mutex
);
13721 * There may be no VBT; and if the BIOS enabled SSC we can
13722 * just keep using it to avoid unnecessary flicker. Whereas if the
13723 * BIOS isn't using it, don't assume it will work even if the VBT
13724 * indicates as much.
13726 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
13727 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
13730 intel_modeset_init_hw(dev
);
13732 intel_setup_overlay(dev
);
13735 * Make sure any fbs we allocated at startup are properly
13736 * pinned & fenced. When we do the allocation it's too early
13739 mutex_lock(&dev
->struct_mutex
);
13740 for_each_crtc(dev
, c
) {
13741 obj
= intel_fb_obj(c
->primary
->fb
);
13745 if (intel_pin_and_fence_fb_obj(c
->primary
,
13748 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13749 to_intel_crtc(c
)->pipe
);
13750 drm_framebuffer_unreference(c
->primary
->fb
);
13751 c
->primary
->fb
= NULL
;
13752 update_state_fb(c
->primary
);
13755 mutex_unlock(&dev
->struct_mutex
);
13757 intel_backlight_register(dev
);
13760 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13762 struct drm_connector
*connector
= &intel_connector
->base
;
13764 intel_panel_destroy_backlight(connector
);
13765 drm_connector_unregister(connector
);
13768 void intel_modeset_cleanup(struct drm_device
*dev
)
13770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13771 struct drm_connector
*connector
;
13773 intel_disable_gt_powersave(dev
);
13775 intel_backlight_unregister(dev
);
13778 * Interrupts and polling as the first thing to avoid creating havoc.
13779 * Too much stuff here (turning of connectors, ...) would
13780 * experience fancy races otherwise.
13782 intel_irq_uninstall(dev_priv
);
13785 * Due to the hpd irq storm handling the hotplug work can re-arm the
13786 * poll handlers. Hence disable polling after hpd handling is shut down.
13788 drm_kms_helper_poll_fini(dev
);
13790 mutex_lock(&dev
->struct_mutex
);
13792 intel_unregister_dsm_handler();
13794 intel_fbc_disable(dev
);
13796 ironlake_teardown_rc6(dev
);
13798 mutex_unlock(&dev
->struct_mutex
);
13800 /* flush any delayed tasks or pending work */
13801 flush_scheduled_work();
13803 /* destroy the backlight and sysfs files before encoders/connectors */
13804 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13805 struct intel_connector
*intel_connector
;
13807 intel_connector
= to_intel_connector(connector
);
13808 intel_connector
->unregister(intel_connector
);
13811 drm_mode_config_cleanup(dev
);
13813 intel_cleanup_overlay(dev
);
13815 mutex_lock(&dev
->struct_mutex
);
13816 intel_cleanup_gt_powersave(dev
);
13817 mutex_unlock(&dev
->struct_mutex
);
13821 * Return which encoder is currently attached for connector.
13823 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13825 return &intel_attached_encoder(connector
)->base
;
13828 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13829 struct intel_encoder
*encoder
)
13831 connector
->encoder
= encoder
;
13832 drm_mode_connector_attach_encoder(&connector
->base
,
13837 * set vga decode state - true == enable VGA decode
13839 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13842 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13845 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13846 DRM_ERROR("failed to read control word\n");
13850 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13854 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13856 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13858 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13859 DRM_ERROR("failed to write control word\n");
13866 struct intel_display_error_state
{
13868 u32 power_well_driver
;
13870 int num_transcoders
;
13872 struct intel_cursor_error_state
{
13877 } cursor
[I915_MAX_PIPES
];
13879 struct intel_pipe_error_state
{
13880 bool power_domain_on
;
13883 } pipe
[I915_MAX_PIPES
];
13885 struct intel_plane_error_state
{
13893 } plane
[I915_MAX_PIPES
];
13895 struct intel_transcoder_error_state
{
13896 bool power_domain_on
;
13897 enum transcoder cpu_transcoder
;
13910 struct intel_display_error_state
*
13911 intel_display_capture_error_state(struct drm_device
*dev
)
13913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13914 struct intel_display_error_state
*error
;
13915 int transcoders
[] = {
13923 if (INTEL_INFO(dev
)->num_pipes
== 0)
13926 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13930 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13931 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13933 for_each_pipe(dev_priv
, i
) {
13934 error
->pipe
[i
].power_domain_on
=
13935 __intel_display_power_is_enabled(dev_priv
,
13936 POWER_DOMAIN_PIPE(i
));
13937 if (!error
->pipe
[i
].power_domain_on
)
13940 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13941 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13942 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13944 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13945 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13946 if (INTEL_INFO(dev
)->gen
<= 3) {
13947 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13948 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13950 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13951 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13952 if (INTEL_INFO(dev
)->gen
>= 4) {
13953 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13954 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13957 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13959 if (HAS_GMCH_DISPLAY(dev
))
13960 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13963 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13964 if (HAS_DDI(dev_priv
->dev
))
13965 error
->num_transcoders
++; /* Account for eDP. */
13967 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13968 enum transcoder cpu_transcoder
= transcoders
[i
];
13970 error
->transcoder
[i
].power_domain_on
=
13971 __intel_display_power_is_enabled(dev_priv
,
13972 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13973 if (!error
->transcoder
[i
].power_domain_on
)
13976 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13978 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13979 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13980 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13981 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13982 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13983 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13984 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13990 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13993 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13994 struct drm_device
*dev
,
13995 struct intel_display_error_state
*error
)
13997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14003 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
14004 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
14005 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
14006 error
->power_well_driver
);
14007 for_each_pipe(dev_priv
, i
) {
14008 err_printf(m
, "Pipe [%d]:\n", i
);
14009 err_printf(m
, " Power: %s\n",
14010 error
->pipe
[i
].power_domain_on
? "on" : "off");
14011 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
14012 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
14014 err_printf(m
, "Plane [%d]:\n", i
);
14015 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
14016 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
14017 if (INTEL_INFO(dev
)->gen
<= 3) {
14018 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
14019 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
14021 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
14022 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
14023 if (INTEL_INFO(dev
)->gen
>= 4) {
14024 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
14025 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
14028 err_printf(m
, "Cursor [%d]:\n", i
);
14029 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
14030 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
14031 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
14034 for (i
= 0; i
< error
->num_transcoders
; i
++) {
14035 err_printf(m
, "CPU transcoder: %c\n",
14036 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
14037 err_printf(m
, " Power: %s\n",
14038 error
->transcoder
[i
].power_domain_on
? "on" : "off");
14039 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
14040 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
14041 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
14042 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
14043 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
14044 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
14045 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
14049 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
14051 struct intel_crtc
*crtc
;
14053 for_each_intel_crtc(dev
, crtc
) {
14054 struct intel_unpin_work
*work
;
14056 spin_lock_irq(&dev
->event_lock
);
14058 work
= crtc
->unpin_work
;
14060 if (work
&& work
->event
&&
14061 work
->event
->base
.file_priv
== file
) {
14062 kfree(work
->event
);
14063 work
->event
= NULL
;
14066 spin_unlock_irq(&dev
->event_lock
);