2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
51 static bool is_mmio_work(struct intel_flip_work
*work
)
53 return work
->mmio_work
.func
;
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats
[] = {
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats
[] = {
70 DRM_FORMAT_XRGB2101010
,
71 DRM_FORMAT_XBGR2101010
,
74 static const uint32_t skl_primary_formats
[] = {
81 DRM_FORMAT_XRGB2101010
,
82 DRM_FORMAT_XBGR2101010
,
90 static const uint32_t intel_cursor_formats
[] = {
94 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
95 struct intel_crtc_state
*pipe_config
);
96 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
97 struct intel_crtc_state
*pipe_config
);
99 static int intel_framebuffer_init(struct drm_device
*dev
,
100 struct intel_framebuffer
*ifb
,
101 struct drm_mode_fb_cmd2
*mode_cmd
,
102 struct drm_i915_gem_object
*obj
);
103 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
104 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
105 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
107 struct intel_link_m_n
*m_n
,
108 struct intel_link_m_n
*m2_n2
);
109 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
110 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
111 static void haswell_set_pipemisc(struct drm_crtc
*crtc
);
112 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
113 const struct intel_crtc_state
*pipe_config
);
114 static void chv_prepare_pll(struct intel_crtc
*crtc
,
115 const struct intel_crtc_state
*pipe_config
);
116 static void intel_begin_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
117 static void intel_finish_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
118 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
119 struct intel_crtc_state
*crtc_state
);
120 static void skylake_pfit_enable(struct intel_crtc
*crtc
);
121 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
);
122 static void ironlake_pfit_enable(struct intel_crtc
*crtc
);
123 static void intel_modeset_setup_hw_state(struct drm_device
*dev
);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
);
125 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
);
126 static int broxton_calc_cdclk(int max_pixclk
);
131 } dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
135 int p2_slow
, p2_fast
;
139 /* returns HPLL frequency in kHz */
140 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
142 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
144 /* Obtain SKU information */
145 mutex_lock(&dev_priv
->sb_lock
);
146 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
147 CCK_FUSE_HPLL_FREQ_MASK
;
148 mutex_unlock(&dev_priv
->sb_lock
);
150 return vco_freq
[hpll_freq
] * 1000;
153 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
154 const char *name
, u32 reg
, int ref_freq
)
159 mutex_lock(&dev_priv
->sb_lock
);
160 val
= vlv_cck_read(dev_priv
, reg
);
161 mutex_unlock(&dev_priv
->sb_lock
);
163 divider
= val
& CCK_FREQUENCY_VALUES
;
165 WARN((val
& CCK_FREQUENCY_STATUS
) !=
166 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
167 "%s change in progress\n", name
);
169 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
172 static int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
173 const char *name
, u32 reg
)
175 if (dev_priv
->hpll_freq
== 0)
176 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
178 return vlv_get_cck_clock(dev_priv
, name
, reg
,
179 dev_priv
->hpll_freq
);
183 intel_pch_rawclk(struct drm_i915_private
*dev_priv
)
185 return (I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
) * 1000;
189 intel_vlv_hrawclk(struct drm_i915_private
*dev_priv
)
191 /* RAWCLK_FREQ_VLV register updated from power well code */
192 return vlv_get_cck_clock_hpll(dev_priv
, "hrawclk",
193 CCK_DISPLAY_REF_CLOCK_CONTROL
);
197 intel_g4x_hrawclk(struct drm_i915_private
*dev_priv
)
201 /* hrawclock is 1/4 the FSB frequency */
202 clkcfg
= I915_READ(CLKCFG
);
203 switch (clkcfg
& CLKCFG_FSB_MASK
) {
212 case CLKCFG_FSB_1067
:
214 case CLKCFG_FSB_1333
:
216 /* these two are just a guess; one of them might be right */
217 case CLKCFG_FSB_1600
:
218 case CLKCFG_FSB_1600_ALT
:
225 void intel_update_rawclk(struct drm_i915_private
*dev_priv
)
227 if (HAS_PCH_SPLIT(dev_priv
))
228 dev_priv
->rawclk_freq
= intel_pch_rawclk(dev_priv
);
229 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
230 dev_priv
->rawclk_freq
= intel_vlv_hrawclk(dev_priv
);
231 else if (IS_G4X(dev_priv
) || IS_PINEVIEW(dev_priv
))
232 dev_priv
->rawclk_freq
= intel_g4x_hrawclk(dev_priv
);
234 return; /* no rawclk on other platforms, or no need to know it */
236 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv
->rawclk_freq
);
239 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
241 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
244 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
245 CCK_CZ_CLOCK_CONTROL
);
247 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
250 static inline u32
/* units of 100MHz */
251 intel_fdi_link_freq(struct drm_i915_private
*dev_priv
,
252 const struct intel_crtc_state
*pipe_config
)
254 if (HAS_DDI(dev_priv
))
255 return pipe_config
->port_clock
; /* SPLL */
256 else if (IS_GEN5(dev_priv
))
257 return ((I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2) * 10000;
262 static const struct intel_limit intel_limits_i8xx_dac
= {
263 .dot
= { .min
= 25000, .max
= 350000 },
264 .vco
= { .min
= 908000, .max
= 1512000 },
265 .n
= { .min
= 2, .max
= 16 },
266 .m
= { .min
= 96, .max
= 140 },
267 .m1
= { .min
= 18, .max
= 26 },
268 .m2
= { .min
= 6, .max
= 16 },
269 .p
= { .min
= 4, .max
= 128 },
270 .p1
= { .min
= 2, .max
= 33 },
271 .p2
= { .dot_limit
= 165000,
272 .p2_slow
= 4, .p2_fast
= 2 },
275 static const struct intel_limit intel_limits_i8xx_dvo
= {
276 .dot
= { .min
= 25000, .max
= 350000 },
277 .vco
= { .min
= 908000, .max
= 1512000 },
278 .n
= { .min
= 2, .max
= 16 },
279 .m
= { .min
= 96, .max
= 140 },
280 .m1
= { .min
= 18, .max
= 26 },
281 .m2
= { .min
= 6, .max
= 16 },
282 .p
= { .min
= 4, .max
= 128 },
283 .p1
= { .min
= 2, .max
= 33 },
284 .p2
= { .dot_limit
= 165000,
285 .p2_slow
= 4, .p2_fast
= 4 },
288 static const struct intel_limit intel_limits_i8xx_lvds
= {
289 .dot
= { .min
= 25000, .max
= 350000 },
290 .vco
= { .min
= 908000, .max
= 1512000 },
291 .n
= { .min
= 2, .max
= 16 },
292 .m
= { .min
= 96, .max
= 140 },
293 .m1
= { .min
= 18, .max
= 26 },
294 .m2
= { .min
= 6, .max
= 16 },
295 .p
= { .min
= 4, .max
= 128 },
296 .p1
= { .min
= 1, .max
= 6 },
297 .p2
= { .dot_limit
= 165000,
298 .p2_slow
= 14, .p2_fast
= 7 },
301 static const struct intel_limit intel_limits_i9xx_sdvo
= {
302 .dot
= { .min
= 20000, .max
= 400000 },
303 .vco
= { .min
= 1400000, .max
= 2800000 },
304 .n
= { .min
= 1, .max
= 6 },
305 .m
= { .min
= 70, .max
= 120 },
306 .m1
= { .min
= 8, .max
= 18 },
307 .m2
= { .min
= 3, .max
= 7 },
308 .p
= { .min
= 5, .max
= 80 },
309 .p1
= { .min
= 1, .max
= 8 },
310 .p2
= { .dot_limit
= 200000,
311 .p2_slow
= 10, .p2_fast
= 5 },
314 static const struct intel_limit intel_limits_i9xx_lvds
= {
315 .dot
= { .min
= 20000, .max
= 400000 },
316 .vco
= { .min
= 1400000, .max
= 2800000 },
317 .n
= { .min
= 1, .max
= 6 },
318 .m
= { .min
= 70, .max
= 120 },
319 .m1
= { .min
= 8, .max
= 18 },
320 .m2
= { .min
= 3, .max
= 7 },
321 .p
= { .min
= 7, .max
= 98 },
322 .p1
= { .min
= 1, .max
= 8 },
323 .p2
= { .dot_limit
= 112000,
324 .p2_slow
= 14, .p2_fast
= 7 },
328 static const struct intel_limit intel_limits_g4x_sdvo
= {
329 .dot
= { .min
= 25000, .max
= 270000 },
330 .vco
= { .min
= 1750000, .max
= 3500000},
331 .n
= { .min
= 1, .max
= 4 },
332 .m
= { .min
= 104, .max
= 138 },
333 .m1
= { .min
= 17, .max
= 23 },
334 .m2
= { .min
= 5, .max
= 11 },
335 .p
= { .min
= 10, .max
= 30 },
336 .p1
= { .min
= 1, .max
= 3},
337 .p2
= { .dot_limit
= 270000,
343 static const struct intel_limit intel_limits_g4x_hdmi
= {
344 .dot
= { .min
= 22000, .max
= 400000 },
345 .vco
= { .min
= 1750000, .max
= 3500000},
346 .n
= { .min
= 1, .max
= 4 },
347 .m
= { .min
= 104, .max
= 138 },
348 .m1
= { .min
= 16, .max
= 23 },
349 .m2
= { .min
= 5, .max
= 11 },
350 .p
= { .min
= 5, .max
= 80 },
351 .p1
= { .min
= 1, .max
= 8},
352 .p2
= { .dot_limit
= 165000,
353 .p2_slow
= 10, .p2_fast
= 5 },
356 static const struct intel_limit intel_limits_g4x_single_channel_lvds
= {
357 .dot
= { .min
= 20000, .max
= 115000 },
358 .vco
= { .min
= 1750000, .max
= 3500000 },
359 .n
= { .min
= 1, .max
= 3 },
360 .m
= { .min
= 104, .max
= 138 },
361 .m1
= { .min
= 17, .max
= 23 },
362 .m2
= { .min
= 5, .max
= 11 },
363 .p
= { .min
= 28, .max
= 112 },
364 .p1
= { .min
= 2, .max
= 8 },
365 .p2
= { .dot_limit
= 0,
366 .p2_slow
= 14, .p2_fast
= 14
370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds
= {
371 .dot
= { .min
= 80000, .max
= 224000 },
372 .vco
= { .min
= 1750000, .max
= 3500000 },
373 .n
= { .min
= 1, .max
= 3 },
374 .m
= { .min
= 104, .max
= 138 },
375 .m1
= { .min
= 17, .max
= 23 },
376 .m2
= { .min
= 5, .max
= 11 },
377 .p
= { .min
= 14, .max
= 42 },
378 .p1
= { .min
= 2, .max
= 6 },
379 .p2
= { .dot_limit
= 0,
380 .p2_slow
= 7, .p2_fast
= 7
384 static const struct intel_limit intel_limits_pineview_sdvo
= {
385 .dot
= { .min
= 20000, .max
= 400000},
386 .vco
= { .min
= 1700000, .max
= 3500000 },
387 /* Pineview's Ncounter is a ring counter */
388 .n
= { .min
= 3, .max
= 6 },
389 .m
= { .min
= 2, .max
= 256 },
390 /* Pineview only has one combined m divider, which we treat as m2. */
391 .m1
= { .min
= 0, .max
= 0 },
392 .m2
= { .min
= 0, .max
= 254 },
393 .p
= { .min
= 5, .max
= 80 },
394 .p1
= { .min
= 1, .max
= 8 },
395 .p2
= { .dot_limit
= 200000,
396 .p2_slow
= 10, .p2_fast
= 5 },
399 static const struct intel_limit intel_limits_pineview_lvds
= {
400 .dot
= { .min
= 20000, .max
= 400000 },
401 .vco
= { .min
= 1700000, .max
= 3500000 },
402 .n
= { .min
= 3, .max
= 6 },
403 .m
= { .min
= 2, .max
= 256 },
404 .m1
= { .min
= 0, .max
= 0 },
405 .m2
= { .min
= 0, .max
= 254 },
406 .p
= { .min
= 7, .max
= 112 },
407 .p1
= { .min
= 1, .max
= 8 },
408 .p2
= { .dot_limit
= 112000,
409 .p2_slow
= 14, .p2_fast
= 14 },
412 /* Ironlake / Sandybridge
414 * We calculate clock using (register_value + 2) for N/M1/M2, so here
415 * the range value for them is (actual_value - 2).
417 static const struct intel_limit intel_limits_ironlake_dac
= {
418 .dot
= { .min
= 25000, .max
= 350000 },
419 .vco
= { .min
= 1760000, .max
= 3510000 },
420 .n
= { .min
= 1, .max
= 5 },
421 .m
= { .min
= 79, .max
= 127 },
422 .m1
= { .min
= 12, .max
= 22 },
423 .m2
= { .min
= 5, .max
= 9 },
424 .p
= { .min
= 5, .max
= 80 },
425 .p1
= { .min
= 1, .max
= 8 },
426 .p2
= { .dot_limit
= 225000,
427 .p2_slow
= 10, .p2_fast
= 5 },
430 static const struct intel_limit intel_limits_ironlake_single_lvds
= {
431 .dot
= { .min
= 25000, .max
= 350000 },
432 .vco
= { .min
= 1760000, .max
= 3510000 },
433 .n
= { .min
= 1, .max
= 3 },
434 .m
= { .min
= 79, .max
= 118 },
435 .m1
= { .min
= 12, .max
= 22 },
436 .m2
= { .min
= 5, .max
= 9 },
437 .p
= { .min
= 28, .max
= 112 },
438 .p1
= { .min
= 2, .max
= 8 },
439 .p2
= { .dot_limit
= 225000,
440 .p2_slow
= 14, .p2_fast
= 14 },
443 static const struct intel_limit intel_limits_ironlake_dual_lvds
= {
444 .dot
= { .min
= 25000, .max
= 350000 },
445 .vco
= { .min
= 1760000, .max
= 3510000 },
446 .n
= { .min
= 1, .max
= 3 },
447 .m
= { .min
= 79, .max
= 127 },
448 .m1
= { .min
= 12, .max
= 22 },
449 .m2
= { .min
= 5, .max
= 9 },
450 .p
= { .min
= 14, .max
= 56 },
451 .p1
= { .min
= 2, .max
= 8 },
452 .p2
= { .dot_limit
= 225000,
453 .p2_slow
= 7, .p2_fast
= 7 },
456 /* LVDS 100mhz refclk limits. */
457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m
= {
458 .dot
= { .min
= 25000, .max
= 350000 },
459 .vco
= { .min
= 1760000, .max
= 3510000 },
460 .n
= { .min
= 1, .max
= 2 },
461 .m
= { .min
= 79, .max
= 126 },
462 .m1
= { .min
= 12, .max
= 22 },
463 .m2
= { .min
= 5, .max
= 9 },
464 .p
= { .min
= 28, .max
= 112 },
465 .p1
= { .min
= 2, .max
= 8 },
466 .p2
= { .dot_limit
= 225000,
467 .p2_slow
= 14, .p2_fast
= 14 },
470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m
= {
471 .dot
= { .min
= 25000, .max
= 350000 },
472 .vco
= { .min
= 1760000, .max
= 3510000 },
473 .n
= { .min
= 1, .max
= 3 },
474 .m
= { .min
= 79, .max
= 126 },
475 .m1
= { .min
= 12, .max
= 22 },
476 .m2
= { .min
= 5, .max
= 9 },
477 .p
= { .min
= 14, .max
= 42 },
478 .p1
= { .min
= 2, .max
= 6 },
479 .p2
= { .dot_limit
= 225000,
480 .p2_slow
= 7, .p2_fast
= 7 },
483 static const struct intel_limit intel_limits_vlv
= {
485 * These are the data rate limits (measured in fast clocks)
486 * since those are the strictest limits we have. The fast
487 * clock and actual rate limits are more relaxed, so checking
488 * them would make no difference.
490 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
491 .vco
= { .min
= 4000000, .max
= 6000000 },
492 .n
= { .min
= 1, .max
= 7 },
493 .m1
= { .min
= 2, .max
= 3 },
494 .m2
= { .min
= 11, .max
= 156 },
495 .p1
= { .min
= 2, .max
= 3 },
496 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
499 static const struct intel_limit intel_limits_chv
= {
501 * These are the data rate limits (measured in fast clocks)
502 * since those are the strictest limits we have. The fast
503 * clock and actual rate limits are more relaxed, so checking
504 * them would make no difference.
506 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
507 .vco
= { .min
= 4800000, .max
= 6480000 },
508 .n
= { .min
= 1, .max
= 1 },
509 .m1
= { .min
= 2, .max
= 2 },
510 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
511 .p1
= { .min
= 2, .max
= 4 },
512 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
515 static const struct intel_limit intel_limits_bxt
= {
516 /* FIXME: find real dot limits */
517 .dot
= { .min
= 0, .max
= INT_MAX
},
518 .vco
= { .min
= 4800000, .max
= 6700000 },
519 .n
= { .min
= 1, .max
= 1 },
520 .m1
= { .min
= 2, .max
= 2 },
521 /* FIXME: find real m2 limits */
522 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
523 .p1
= { .min
= 2, .max
= 4 },
524 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
528 needs_modeset(struct drm_crtc_state
*state
)
530 return drm_atomic_crtc_needs_modeset(state
);
534 * Returns whether any output on the specified pipe is of the specified type
536 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
538 struct drm_device
*dev
= crtc
->base
.dev
;
539 struct intel_encoder
*encoder
;
541 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
542 if (encoder
->type
== type
)
549 * Returns whether any output on the specified pipe will have the specified
550 * type after a staged modeset is complete, i.e., the same as
551 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
554 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
557 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
558 struct drm_connector
*connector
;
559 struct drm_connector_state
*connector_state
;
560 struct intel_encoder
*encoder
;
561 int i
, num_connectors
= 0;
563 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
564 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
569 encoder
= to_intel_encoder(connector_state
->best_encoder
);
570 if (encoder
->type
== type
)
574 WARN_ON(num_connectors
== 0);
580 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
581 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
582 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
583 * The helpers' return value is the rate of the clock that is fed to the
584 * display engine's pipe which can be the above fast dot clock rate or a
585 * divided-down version of it.
587 /* m1 is reserved as 0 in Pineview, n is a ring counter */
588 static int pnv_calc_dpll_params(int refclk
, struct dpll
*clock
)
590 clock
->m
= clock
->m2
+ 2;
591 clock
->p
= clock
->p1
* clock
->p2
;
592 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
594 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
595 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
600 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
602 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
605 static int i9xx_calc_dpll_params(int refclk
, struct dpll
*clock
)
607 clock
->m
= i9xx_dpll_compute_m(clock
);
608 clock
->p
= clock
->p1
* clock
->p2
;
609 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
611 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
612 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
617 static int vlv_calc_dpll_params(int refclk
, struct dpll
*clock
)
619 clock
->m
= clock
->m1
* clock
->m2
;
620 clock
->p
= clock
->p1
* clock
->p2
;
621 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
623 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
624 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
626 return clock
->dot
/ 5;
629 int chv_calc_dpll_params(int refclk
, struct dpll
*clock
)
631 clock
->m
= clock
->m1
* clock
->m2
;
632 clock
->p
= clock
->p1
* clock
->p2
;
633 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
635 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
637 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
639 return clock
->dot
/ 5;
642 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
644 * Returns whether the given set of divisors are valid for a given refclk with
645 * the given connectors.
648 static bool intel_PLL_is_valid(struct drm_device
*dev
,
649 const struct intel_limit
*limit
,
650 const struct dpll
*clock
)
652 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
653 INTELPllInvalid("n out of range\n");
654 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
655 INTELPllInvalid("p1 out of range\n");
656 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
657 INTELPllInvalid("m2 out of range\n");
658 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
659 INTELPllInvalid("m1 out of range\n");
661 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) &&
662 !IS_CHERRYVIEW(dev
) && !IS_BROXTON(dev
))
663 if (clock
->m1
<= clock
->m2
)
664 INTELPllInvalid("m1 <= m2\n");
666 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) && !IS_BROXTON(dev
)) {
667 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
668 INTELPllInvalid("p out of range\n");
669 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
670 INTELPllInvalid("m out of range\n");
673 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
674 INTELPllInvalid("vco out of range\n");
675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
678 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
679 INTELPllInvalid("dot out of range\n");
685 i9xx_select_p2_div(const struct intel_limit
*limit
,
686 const struct intel_crtc_state
*crtc_state
,
689 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
691 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
693 * For LVDS just rely on its current settings for dual-channel.
694 * We haven't figured out how to reliably set up different
695 * single/dual channel state, if we even can.
697 if (intel_is_dual_link_lvds(dev
))
698 return limit
->p2
.p2_fast
;
700 return limit
->p2
.p2_slow
;
702 if (target
< limit
->p2
.dot_limit
)
703 return limit
->p2
.p2_slow
;
705 return limit
->p2
.p2_fast
;
710 * Returns a set of divisors for the desired target clock with the given
711 * refclk, or FALSE. The returned values represent the clock equation:
712 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
714 * Target and reference clocks are specified in kHz.
716 * If match_clock is provided, then best_clock P divider must match the P
717 * divider from @match_clock used for LVDS downclocking.
720 i9xx_find_best_dpll(const struct intel_limit
*limit
,
721 struct intel_crtc_state
*crtc_state
,
722 int target
, int refclk
, struct dpll
*match_clock
,
723 struct dpll
*best_clock
)
725 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
729 memset(best_clock
, 0, sizeof(*best_clock
));
731 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
733 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
735 for (clock
.m2
= limit
->m2
.min
;
736 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
737 if (clock
.m2
>= clock
.m1
)
739 for (clock
.n
= limit
->n
.min
;
740 clock
.n
<= limit
->n
.max
; clock
.n
++) {
741 for (clock
.p1
= limit
->p1
.min
;
742 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
745 i9xx_calc_dpll_params(refclk
, &clock
);
746 if (!intel_PLL_is_valid(dev
, limit
,
750 clock
.p
!= match_clock
->p
)
753 this_err
= abs(clock
.dot
- target
);
754 if (this_err
< err
) {
763 return (err
!= target
);
767 * Returns a set of divisors for the desired target clock with the given
768 * refclk, or FALSE. The returned values represent the clock equation:
769 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
771 * Target and reference clocks are specified in kHz.
773 * If match_clock is provided, then best_clock P divider must match the P
774 * divider from @match_clock used for LVDS downclocking.
777 pnv_find_best_dpll(const struct intel_limit
*limit
,
778 struct intel_crtc_state
*crtc_state
,
779 int target
, int refclk
, struct dpll
*match_clock
,
780 struct dpll
*best_clock
)
782 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
786 memset(best_clock
, 0, sizeof(*best_clock
));
788 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
790 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
792 for (clock
.m2
= limit
->m2
.min
;
793 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
794 for (clock
.n
= limit
->n
.min
;
795 clock
.n
<= limit
->n
.max
; clock
.n
++) {
796 for (clock
.p1
= limit
->p1
.min
;
797 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
800 pnv_calc_dpll_params(refclk
, &clock
);
801 if (!intel_PLL_is_valid(dev
, limit
,
805 clock
.p
!= match_clock
->p
)
808 this_err
= abs(clock
.dot
- target
);
809 if (this_err
< err
) {
818 return (err
!= target
);
822 * Returns a set of divisors for the desired target clock with the given
823 * refclk, or FALSE. The returned values represent the clock equation:
824 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
826 * Target and reference clocks are specified in kHz.
828 * If match_clock is provided, then best_clock P divider must match the P
829 * divider from @match_clock used for LVDS downclocking.
832 g4x_find_best_dpll(const struct intel_limit
*limit
,
833 struct intel_crtc_state
*crtc_state
,
834 int target
, int refclk
, struct dpll
*match_clock
,
835 struct dpll
*best_clock
)
837 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
841 /* approximately equals target * 0.00585 */
842 int err_most
= (target
>> 8) + (target
>> 9);
844 memset(best_clock
, 0, sizeof(*best_clock
));
846 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
848 max_n
= limit
->n
.max
;
849 /* based on hardware requirement, prefer smaller n to precision */
850 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
851 /* based on hardware requirement, prefere larger m1,m2 */
852 for (clock
.m1
= limit
->m1
.max
;
853 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
854 for (clock
.m2
= limit
->m2
.max
;
855 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
856 for (clock
.p1
= limit
->p1
.max
;
857 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
860 i9xx_calc_dpll_params(refclk
, &clock
);
861 if (!intel_PLL_is_valid(dev
, limit
,
865 this_err
= abs(clock
.dot
- target
);
866 if (this_err
< err_most
) {
880 * Check if the calculated PLL configuration is more optimal compared to the
881 * best configuration and error found so far. Return the calculated error.
883 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
884 const struct dpll
*calculated_clock
,
885 const struct dpll
*best_clock
,
886 unsigned int best_error_ppm
,
887 unsigned int *error_ppm
)
890 * For CHV ignore the error and consider only the P value.
891 * Prefer a bigger P value based on HW requirements.
893 if (IS_CHERRYVIEW(dev
)) {
896 return calculated_clock
->p
> best_clock
->p
;
899 if (WARN_ON_ONCE(!target_freq
))
902 *error_ppm
= div_u64(1000000ULL *
903 abs(target_freq
- calculated_clock
->dot
),
906 * Prefer a better P value over a better (smaller) error if the error
907 * is small. Ensure this preference for future configurations too by
908 * setting the error to 0.
910 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
916 return *error_ppm
+ 10 < best_error_ppm
;
920 * Returns a set of divisors for the desired target clock with the given
921 * refclk, or FALSE. The returned values represent the clock equation:
922 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
925 vlv_find_best_dpll(const struct intel_limit
*limit
,
926 struct intel_crtc_state
*crtc_state
,
927 int target
, int refclk
, struct dpll
*match_clock
,
928 struct dpll
*best_clock
)
930 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
931 struct drm_device
*dev
= crtc
->base
.dev
;
933 unsigned int bestppm
= 1000000;
934 /* min update 19.2 MHz */
935 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
938 target
*= 5; /* fast clock */
940 memset(best_clock
, 0, sizeof(*best_clock
));
942 /* based on hardware requirement, prefer smaller n to precision */
943 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
944 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
945 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
946 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
947 clock
.p
= clock
.p1
* clock
.p2
;
948 /* based on hardware requirement, prefer bigger m1,m2 values */
949 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
952 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
955 vlv_calc_dpll_params(refclk
, &clock
);
957 if (!intel_PLL_is_valid(dev
, limit
,
961 if (!vlv_PLL_is_optimal(dev
, target
,
979 * Returns a set of divisors for the desired target clock with the given
980 * refclk, or FALSE. The returned values represent the clock equation:
981 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
984 chv_find_best_dpll(const struct intel_limit
*limit
,
985 struct intel_crtc_state
*crtc_state
,
986 int target
, int refclk
, struct dpll
*match_clock
,
987 struct dpll
*best_clock
)
989 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
990 struct drm_device
*dev
= crtc
->base
.dev
;
991 unsigned int best_error_ppm
;
996 memset(best_clock
, 0, sizeof(*best_clock
));
997 best_error_ppm
= 1000000;
1000 * Based on hardware doc, the n always set to 1, and m1 always
1001 * set to 2. If requires to support 200Mhz refclk, we need to
1002 * revisit this because n may not 1 anymore.
1004 clock
.n
= 1, clock
.m1
= 2;
1005 target
*= 5; /* fast clock */
1007 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
1008 for (clock
.p2
= limit
->p2
.p2_fast
;
1009 clock
.p2
>= limit
->p2
.p2_slow
;
1010 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
1011 unsigned int error_ppm
;
1013 clock
.p
= clock
.p1
* clock
.p2
;
1015 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
1016 clock
.n
) << 22, refclk
* clock
.m1
);
1018 if (m2
> INT_MAX
/clock
.m1
)
1023 chv_calc_dpll_params(refclk
, &clock
);
1025 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
1028 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
1029 best_error_ppm
, &error_ppm
))
1032 *best_clock
= clock
;
1033 best_error_ppm
= error_ppm
;
1041 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1042 struct dpll
*best_clock
)
1044 int refclk
= 100000;
1045 const struct intel_limit
*limit
= &intel_limits_bxt
;
1047 return chv_find_best_dpll(limit
, crtc_state
,
1048 target_clock
, refclk
, NULL
, best_clock
);
1051 bool intel_crtc_active(struct drm_crtc
*crtc
)
1053 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1055 /* Be paranoid as we can arrive here with only partial
1056 * state retrieved from the hardware during setup.
1058 * We can ditch the adjusted_mode.crtc_clock check as soon
1059 * as Haswell has gained clock readout/fastboot support.
1061 * We can ditch the crtc->primary->fb check as soon as we can
1062 * properly reconstruct framebuffers.
1064 * FIXME: The intel_crtc->active here should be switched to
1065 * crtc->state->active once we have proper CRTC states wired up
1068 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
1069 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1072 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1075 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1076 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1078 return intel_crtc
->config
->cpu_transcoder
;
1081 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1084 i915_reg_t reg
= PIPEDSL(pipe
);
1089 line_mask
= DSL_LINEMASK_GEN2
;
1091 line_mask
= DSL_LINEMASK_GEN3
;
1093 line1
= I915_READ(reg
) & line_mask
;
1095 line2
= I915_READ(reg
) & line_mask
;
1097 return line1
== line2
;
1101 * intel_wait_for_pipe_off - wait for pipe to turn off
1102 * @crtc: crtc whose pipe to wait for
1104 * After disabling a pipe, we can't wait for vblank in the usual way,
1105 * spinning on the vblank interrupt status bit, since we won't actually
1106 * see an interrupt when the pipe is disabled.
1108 * On Gen4 and above:
1109 * wait for the pipe register state bit to turn off
1112 * wait for the display line value to settle (it usually
1113 * ends up stopping at the start of the next frame).
1116 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1118 struct drm_device
*dev
= crtc
->base
.dev
;
1119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1120 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1121 enum pipe pipe
= crtc
->pipe
;
1123 if (INTEL_INFO(dev
)->gen
>= 4) {
1124 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
1126 /* Wait for the Pipe State to go off */
1127 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1129 WARN(1, "pipe_off wait timed out\n");
1131 /* Wait for the display line to settle */
1132 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1133 WARN(1, "pipe_off wait timed out\n");
1137 /* Only for pre-ILK configs */
1138 void assert_pll(struct drm_i915_private
*dev_priv
,
1139 enum pipe pipe
, bool state
)
1144 val
= I915_READ(DPLL(pipe
));
1145 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1146 I915_STATE_WARN(cur_state
!= state
,
1147 "PLL state assertion failure (expected %s, current %s)\n",
1148 onoff(state
), onoff(cur_state
));
1151 /* XXX: the dsi pll is shared between MIPI DSI ports */
1152 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1157 mutex_lock(&dev_priv
->sb_lock
);
1158 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1159 mutex_unlock(&dev_priv
->sb_lock
);
1161 cur_state
= val
& DSI_PLL_VCO_EN
;
1162 I915_STATE_WARN(cur_state
!= state
,
1163 "DSI PLL state assertion failure (expected %s, current %s)\n",
1164 onoff(state
), onoff(cur_state
));
1167 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1168 enum pipe pipe
, bool state
)
1171 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1174 if (HAS_DDI(dev_priv
)) {
1175 /* DDI does not have a specific FDI_TX register */
1176 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1177 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1179 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1180 cur_state
= !!(val
& FDI_TX_ENABLE
);
1182 I915_STATE_WARN(cur_state
!= state
,
1183 "FDI TX state assertion failure (expected %s, current %s)\n",
1184 onoff(state
), onoff(cur_state
));
1186 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1187 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1189 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1190 enum pipe pipe
, bool state
)
1195 val
= I915_READ(FDI_RX_CTL(pipe
));
1196 cur_state
= !!(val
& FDI_RX_ENABLE
);
1197 I915_STATE_WARN(cur_state
!= state
,
1198 "FDI RX state assertion failure (expected %s, current %s)\n",
1199 onoff(state
), onoff(cur_state
));
1201 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1202 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1204 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1209 /* ILK FDI PLL is always enabled */
1210 if (IS_GEN5(dev_priv
))
1213 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1214 if (HAS_DDI(dev_priv
))
1217 val
= I915_READ(FDI_TX_CTL(pipe
));
1218 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1221 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1222 enum pipe pipe
, bool state
)
1227 val
= I915_READ(FDI_RX_CTL(pipe
));
1228 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1229 I915_STATE_WARN(cur_state
!= state
,
1230 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1231 onoff(state
), onoff(cur_state
));
1234 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1237 struct drm_device
*dev
= dev_priv
->dev
;
1240 enum pipe panel_pipe
= PIPE_A
;
1243 if (WARN_ON(HAS_DDI(dev
)))
1246 if (HAS_PCH_SPLIT(dev
)) {
1249 pp_reg
= PCH_PP_CONTROL
;
1250 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1252 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1253 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1254 panel_pipe
= PIPE_B
;
1255 /* XXX: else fix for eDP */
1256 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1257 /* presumably write lock depends on pipe, not port select */
1258 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1261 pp_reg
= PP_CONTROL
;
1262 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1263 panel_pipe
= PIPE_B
;
1266 val
= I915_READ(pp_reg
);
1267 if (!(val
& PANEL_POWER_ON
) ||
1268 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1271 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1272 "panel assertion failure, pipe %c regs locked\n",
1276 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1277 enum pipe pipe
, bool state
)
1279 struct drm_device
*dev
= dev_priv
->dev
;
1282 if (IS_845G(dev
) || IS_I865G(dev
))
1283 cur_state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
1285 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1287 I915_STATE_WARN(cur_state
!= state
,
1288 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1289 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1291 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1292 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1294 void assert_pipe(struct drm_i915_private
*dev_priv
,
1295 enum pipe pipe
, bool state
)
1298 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1300 enum intel_display_power_domain power_domain
;
1302 /* if we need the pipe quirk it must be always on */
1303 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1304 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1307 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
1308 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
1309 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1310 cur_state
= !!(val
& PIPECONF_ENABLE
);
1312 intel_display_power_put(dev_priv
, power_domain
);
1317 I915_STATE_WARN(cur_state
!= state
,
1318 "pipe %c assertion failure (expected %s, current %s)\n",
1319 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1322 static void assert_plane(struct drm_i915_private
*dev_priv
,
1323 enum plane plane
, bool state
)
1328 val
= I915_READ(DSPCNTR(plane
));
1329 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1330 I915_STATE_WARN(cur_state
!= state
,
1331 "plane %c assertion failure (expected %s, current %s)\n",
1332 plane_name(plane
), onoff(state
), onoff(cur_state
));
1335 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1338 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1341 struct drm_device
*dev
= dev_priv
->dev
;
1344 /* Primary planes are fixed to pipes on gen4+ */
1345 if (INTEL_INFO(dev
)->gen
>= 4) {
1346 u32 val
= I915_READ(DSPCNTR(pipe
));
1347 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1348 "plane %c assertion failure, should be disabled but not\n",
1353 /* Need to check both planes against the pipe */
1354 for_each_pipe(dev_priv
, i
) {
1355 u32 val
= I915_READ(DSPCNTR(i
));
1356 enum pipe cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1357 DISPPLANE_SEL_PIPE_SHIFT
;
1358 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1359 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1360 plane_name(i
), pipe_name(pipe
));
1364 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1367 struct drm_device
*dev
= dev_priv
->dev
;
1370 if (INTEL_INFO(dev
)->gen
>= 9) {
1371 for_each_sprite(dev_priv
, pipe
, sprite
) {
1372 u32 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1373 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1374 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1375 sprite
, pipe_name(pipe
));
1377 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1378 for_each_sprite(dev_priv
, pipe
, sprite
) {
1379 u32 val
= I915_READ(SPCNTR(pipe
, sprite
));
1380 I915_STATE_WARN(val
& SP_ENABLE
,
1381 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1382 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1384 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1385 u32 val
= I915_READ(SPRCTL(pipe
));
1386 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388 plane_name(pipe
), pipe_name(pipe
));
1389 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1390 u32 val
= I915_READ(DVSCNTR(pipe
));
1391 I915_STATE_WARN(val
& DVS_ENABLE
,
1392 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(pipe
), pipe_name(pipe
));
1397 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1399 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1400 drm_crtc_vblank_put(crtc
);
1403 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1409 val
= I915_READ(PCH_TRANSCONF(pipe
));
1410 enabled
= !!(val
& TRANS_ENABLE
);
1411 I915_STATE_WARN(enabled
,
1412 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1416 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1417 enum pipe pipe
, u32 port_sel
, u32 val
)
1419 if ((val
& DP_PORT_EN
) == 0)
1422 if (HAS_PCH_CPT(dev_priv
)) {
1423 u32 trans_dp_ctl
= I915_READ(TRANS_DP_CTL(pipe
));
1424 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1426 } else if (IS_CHERRYVIEW(dev_priv
)) {
1427 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1430 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1436 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1437 enum pipe pipe
, u32 val
)
1439 if ((val
& SDVO_ENABLE
) == 0)
1442 if (HAS_PCH_CPT(dev_priv
)) {
1443 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1445 } else if (IS_CHERRYVIEW(dev_priv
)) {
1446 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1449 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1455 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1456 enum pipe pipe
, u32 val
)
1458 if ((val
& LVDS_PORT_EN
) == 0)
1461 if (HAS_PCH_CPT(dev_priv
)) {
1462 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1465 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1471 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1472 enum pipe pipe
, u32 val
)
1474 if ((val
& ADPA_DAC_ENABLE
) == 0)
1476 if (HAS_PCH_CPT(dev_priv
)) {
1477 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1480 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1486 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1487 enum pipe pipe
, i915_reg_t reg
,
1490 u32 val
= I915_READ(reg
);
1491 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1492 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1493 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1495 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& DP_PORT_EN
) == 0
1496 && (val
& DP_PIPEB_SELECT
),
1497 "IBX PCH dp port still using transcoder B\n");
1500 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1501 enum pipe pipe
, i915_reg_t reg
)
1503 u32 val
= I915_READ(reg
);
1504 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1505 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1506 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1508 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& SDVO_ENABLE
) == 0
1509 && (val
& SDVO_PIPE_B_SELECT
),
1510 "IBX PCH hdmi port still using transcoder B\n");
1513 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1518 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1519 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1520 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1522 val
= I915_READ(PCH_ADPA
);
1523 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1524 "PCH VGA enabled on transcoder %c, should be disabled\n",
1527 val
= I915_READ(PCH_LVDS
);
1528 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1529 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1532 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1533 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1534 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1537 static void _vlv_enable_pll(struct intel_crtc
*crtc
,
1538 const struct intel_crtc_state
*pipe_config
)
1540 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1541 enum pipe pipe
= crtc
->pipe
;
1543 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1544 POSTING_READ(DPLL(pipe
));
1547 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1548 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
1551 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1552 const struct intel_crtc_state
*pipe_config
)
1554 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1555 enum pipe pipe
= crtc
->pipe
;
1557 assert_pipe_disabled(dev_priv
, pipe
);
1559 /* PLL is protected by panel, make sure we can write it */
1560 assert_panel_unlocked(dev_priv
, pipe
);
1562 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1563 _vlv_enable_pll(crtc
, pipe_config
);
1565 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1566 POSTING_READ(DPLL_MD(pipe
));
1570 static void _chv_enable_pll(struct intel_crtc
*crtc
,
1571 const struct intel_crtc_state
*pipe_config
)
1573 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1574 enum pipe pipe
= crtc
->pipe
;
1575 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1578 mutex_lock(&dev_priv
->sb_lock
);
1580 /* Enable back the 10bit clock to display controller */
1581 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1582 tmp
|= DPIO_DCLKP_EN
;
1583 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1585 mutex_unlock(&dev_priv
->sb_lock
);
1588 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1593 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1595 /* Check PLL is locked */
1596 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1597 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1600 static void chv_enable_pll(struct intel_crtc
*crtc
,
1601 const struct intel_crtc_state
*pipe_config
)
1603 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1604 enum pipe pipe
= crtc
->pipe
;
1606 assert_pipe_disabled(dev_priv
, pipe
);
1608 /* PLL is protected by panel, make sure we can write it */
1609 assert_panel_unlocked(dev_priv
, pipe
);
1611 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1612 _chv_enable_pll(crtc
, pipe_config
);
1614 if (pipe
!= PIPE_A
) {
1616 * WaPixelRepeatModeFixForC0:chv
1618 * DPLLCMD is AWOL. Use chicken bits to propagate
1619 * the value from DPLLBMD to either pipe B or C.
1621 I915_WRITE(CBR4_VLV
, pipe
== PIPE_B
? CBR_DPLLBMD_PIPE_B
: CBR_DPLLBMD_PIPE_C
);
1622 I915_WRITE(DPLL_MD(PIPE_B
), pipe_config
->dpll_hw_state
.dpll_md
);
1623 I915_WRITE(CBR4_VLV
, 0);
1624 dev_priv
->chv_dpll_md
[pipe
] = pipe_config
->dpll_hw_state
.dpll_md
;
1627 * DPLLB VGA mode also seems to cause problems.
1628 * We should always have it disabled.
1630 WARN_ON((I915_READ(DPLL(PIPE_B
)) & DPLL_VGA_MODE_DIS
) == 0);
1632 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1633 POSTING_READ(DPLL_MD(pipe
));
1637 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1639 struct intel_crtc
*crtc
;
1642 for_each_intel_crtc(dev
, crtc
)
1643 count
+= crtc
->base
.state
->active
&&
1644 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1649 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1651 struct drm_device
*dev
= crtc
->base
.dev
;
1652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1653 i915_reg_t reg
= DPLL(crtc
->pipe
);
1654 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1656 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1658 /* PLL is protected by panel, make sure we can write it */
1659 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1660 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1662 /* Enable DVO 2x clock on both PLLs if necessary */
1663 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1665 * It appears to be important that we don't enable this
1666 * for the current pipe before otherwise configuring the
1667 * PLL. No idea how this should be handled if multiple
1668 * DVO outputs are enabled simultaneosly.
1670 dpll
|= DPLL_DVO_2X_MODE
;
1671 I915_WRITE(DPLL(!crtc
->pipe
),
1672 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1676 * Apparently we need to have VGA mode enabled prior to changing
1677 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1678 * dividers, even though the register value does change.
1682 I915_WRITE(reg
, dpll
);
1684 /* Wait for the clocks to stabilize. */
1688 if (INTEL_INFO(dev
)->gen
>= 4) {
1689 I915_WRITE(DPLL_MD(crtc
->pipe
),
1690 crtc
->config
->dpll_hw_state
.dpll_md
);
1692 /* The pixel multiplier can only be updated once the
1693 * DPLL is enabled and the clocks are stable.
1695 * So write it again.
1697 I915_WRITE(reg
, dpll
);
1700 /* We do this three times for luck */
1701 I915_WRITE(reg
, dpll
);
1703 udelay(150); /* wait for warmup */
1704 I915_WRITE(reg
, dpll
);
1706 udelay(150); /* wait for warmup */
1707 I915_WRITE(reg
, dpll
);
1709 udelay(150); /* wait for warmup */
1713 * i9xx_disable_pll - disable a PLL
1714 * @dev_priv: i915 private structure
1715 * @pipe: pipe PLL to disable
1717 * Disable the PLL for @pipe, making sure the pipe is off first.
1719 * Note! This is for pre-ILK only.
1721 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1723 struct drm_device
*dev
= crtc
->base
.dev
;
1724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1725 enum pipe pipe
= crtc
->pipe
;
1727 /* Disable DVO 2x clock on both PLLs if necessary */
1729 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1730 !intel_num_dvo_pipes(dev
)) {
1731 I915_WRITE(DPLL(PIPE_B
),
1732 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1733 I915_WRITE(DPLL(PIPE_A
),
1734 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1737 /* Don't disable pipe or pipe PLLs if needed */
1738 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1739 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1742 /* Make sure the pipe isn't still relying on us */
1743 assert_pipe_disabled(dev_priv
, pipe
);
1745 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1746 POSTING_READ(DPLL(pipe
));
1749 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1753 /* Make sure the pipe isn't still relying on us */
1754 assert_pipe_disabled(dev_priv
, pipe
);
1756 val
= DPLL_INTEGRATED_REF_CLK_VLV
|
1757 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1759 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1761 I915_WRITE(DPLL(pipe
), val
);
1762 POSTING_READ(DPLL(pipe
));
1765 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1767 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1770 /* Make sure the pipe isn't still relying on us */
1771 assert_pipe_disabled(dev_priv
, pipe
);
1773 val
= DPLL_SSC_REF_CLK_CHV
|
1774 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1776 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1778 I915_WRITE(DPLL(pipe
), val
);
1779 POSTING_READ(DPLL(pipe
));
1781 mutex_lock(&dev_priv
->sb_lock
);
1783 /* Disable 10bit clock to display controller */
1784 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1785 val
&= ~DPIO_DCLKP_EN
;
1786 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1788 mutex_unlock(&dev_priv
->sb_lock
);
1791 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1792 struct intel_digital_port
*dport
,
1793 unsigned int expected_mask
)
1796 i915_reg_t dpll_reg
;
1798 switch (dport
->port
) {
1800 port_mask
= DPLL_PORTB_READY_MASK
;
1804 port_mask
= DPLL_PORTC_READY_MASK
;
1806 expected_mask
<<= 4;
1809 port_mask
= DPLL_PORTD_READY_MASK
;
1810 dpll_reg
= DPIO_PHY_STATUS
;
1816 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == expected_mask
, 1000))
1817 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1818 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1821 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1824 struct drm_device
*dev
= dev_priv
->dev
;
1825 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1826 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1828 uint32_t val
, pipeconf_val
;
1830 /* Make sure PCH DPLL is enabled */
1831 assert_shared_dpll_enabled(dev_priv
, intel_crtc
->config
->shared_dpll
);
1833 /* FDI must be feeding us bits for PCH ports */
1834 assert_fdi_tx_enabled(dev_priv
, pipe
);
1835 assert_fdi_rx_enabled(dev_priv
, pipe
);
1837 if (HAS_PCH_CPT(dev
)) {
1838 /* Workaround: Set the timing override bit before enabling the
1839 * pch transcoder. */
1840 reg
= TRANS_CHICKEN2(pipe
);
1841 val
= I915_READ(reg
);
1842 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1843 I915_WRITE(reg
, val
);
1846 reg
= PCH_TRANSCONF(pipe
);
1847 val
= I915_READ(reg
);
1848 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1850 if (HAS_PCH_IBX(dev_priv
)) {
1852 * Make the BPC in transcoder be consistent with
1853 * that in pipeconf reg. For HDMI we must use 8bpc
1854 * here for both 8bpc and 12bpc.
1856 val
&= ~PIPECONF_BPC_MASK
;
1857 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_HDMI
))
1858 val
|= PIPECONF_8BPC
;
1860 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1863 val
&= ~TRANS_INTERLACE_MASK
;
1864 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1865 if (HAS_PCH_IBX(dev_priv
) &&
1866 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1867 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1869 val
|= TRANS_INTERLACED
;
1871 val
|= TRANS_PROGRESSIVE
;
1873 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1874 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1875 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1878 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1879 enum transcoder cpu_transcoder
)
1881 u32 val
, pipeconf_val
;
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1885 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1887 /* Workaround: set timing override bit. */
1888 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1889 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1890 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1893 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1895 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1896 PIPECONF_INTERLACED_ILK
)
1897 val
|= TRANS_INTERLACED
;
1899 val
|= TRANS_PROGRESSIVE
;
1901 I915_WRITE(LPT_TRANSCONF
, val
);
1902 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1903 DRM_ERROR("Failed to enable PCH transcoder\n");
1906 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1909 struct drm_device
*dev
= dev_priv
->dev
;
1913 /* FDI relies on the transcoder */
1914 assert_fdi_tx_disabled(dev_priv
, pipe
);
1915 assert_fdi_rx_disabled(dev_priv
, pipe
);
1917 /* Ports must be off as well */
1918 assert_pch_ports_disabled(dev_priv
, pipe
);
1920 reg
= PCH_TRANSCONF(pipe
);
1921 val
= I915_READ(reg
);
1922 val
&= ~TRANS_ENABLE
;
1923 I915_WRITE(reg
, val
);
1924 /* wait for PCH transcoder off, transcoder state */
1925 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1926 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1928 if (HAS_PCH_CPT(dev
)) {
1929 /* Workaround: Clear the timing override chicken bit again. */
1930 reg
= TRANS_CHICKEN2(pipe
);
1931 val
= I915_READ(reg
);
1932 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1933 I915_WRITE(reg
, val
);
1937 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1941 val
= I915_READ(LPT_TRANSCONF
);
1942 val
&= ~TRANS_ENABLE
;
1943 I915_WRITE(LPT_TRANSCONF
, val
);
1944 /* wait for PCH transcoder off, transcoder state */
1945 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1946 DRM_ERROR("Failed to disable PCH transcoder\n");
1948 /* Workaround: clear timing override bit. */
1949 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1950 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1951 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1955 * intel_enable_pipe - enable a pipe, asserting requirements
1956 * @crtc: crtc responsible for the pipe
1958 * Enable @crtc's pipe, making sure that various hardware specific requirements
1959 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1961 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1963 struct drm_device
*dev
= crtc
->base
.dev
;
1964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1965 enum pipe pipe
= crtc
->pipe
;
1966 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1967 enum pipe pch_transcoder
;
1971 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
1973 assert_planes_disabled(dev_priv
, pipe
);
1974 assert_cursor_disabled(dev_priv
, pipe
);
1975 assert_sprites_disabled(dev_priv
, pipe
);
1977 if (HAS_PCH_LPT(dev_priv
))
1978 pch_transcoder
= TRANSCODER_A
;
1980 pch_transcoder
= pipe
;
1983 * A pipe without a PLL won't actually be able to drive bits from
1984 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1987 if (HAS_GMCH_DISPLAY(dev_priv
))
1988 if (crtc
->config
->has_dsi_encoder
)
1989 assert_dsi_pll_enabled(dev_priv
);
1991 assert_pll_enabled(dev_priv
, pipe
);
1993 if (crtc
->config
->has_pch_encoder
) {
1994 /* if driving the PCH, we need FDI enabled */
1995 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1996 assert_fdi_tx_pll_enabled(dev_priv
,
1997 (enum pipe
) cpu_transcoder
);
1999 /* FIXME: assert CPU port conditions for SNB+ */
2002 reg
= PIPECONF(cpu_transcoder
);
2003 val
= I915_READ(reg
);
2004 if (val
& PIPECONF_ENABLE
) {
2005 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2006 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2010 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2014 * Until the pipe starts DSL will read as 0, which would cause
2015 * an apparent vblank timestamp jump, which messes up also the
2016 * frame count when it's derived from the timestamps. So let's
2017 * wait for the pipe to start properly before we call
2018 * drm_crtc_vblank_on()
2020 if (dev
->max_vblank_count
== 0 &&
2021 wait_for(intel_get_crtc_scanline(crtc
) != crtc
->scanline_offset
, 50))
2022 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe
));
2026 * intel_disable_pipe - disable a pipe, asserting requirements
2027 * @crtc: crtc whose pipes is to be disabled
2029 * Disable the pipe of @crtc, making sure that various hardware
2030 * specific requirements are met, if applicable, e.g. plane
2031 * disabled, panel fitter off, etc.
2033 * Will wait until the pipe has shut down before returning.
2035 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2037 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2038 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2039 enum pipe pipe
= crtc
->pipe
;
2043 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
2046 * Make sure planes won't keep trying to pump pixels to us,
2047 * or we might hang the display.
2049 assert_planes_disabled(dev_priv
, pipe
);
2050 assert_cursor_disabled(dev_priv
, pipe
);
2051 assert_sprites_disabled(dev_priv
, pipe
);
2053 reg
= PIPECONF(cpu_transcoder
);
2054 val
= I915_READ(reg
);
2055 if ((val
& PIPECONF_ENABLE
) == 0)
2059 * Double wide has implications for planes
2060 * so best keep it disabled when not needed.
2062 if (crtc
->config
->double_wide
)
2063 val
&= ~PIPECONF_DOUBLE_WIDE
;
2065 /* Don't disable pipe or pipe PLLs if needed */
2066 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2067 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2068 val
&= ~PIPECONF_ENABLE
;
2070 I915_WRITE(reg
, val
);
2071 if ((val
& PIPECONF_ENABLE
) == 0)
2072 intel_wait_for_pipe_off(crtc
);
2075 static bool need_vtd_wa(struct drm_device
*dev
)
2077 #ifdef CONFIG_INTEL_IOMMU
2078 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2084 static unsigned int intel_tile_size(const struct drm_i915_private
*dev_priv
)
2086 return IS_GEN2(dev_priv
) ? 2048 : 4096;
2089 static unsigned int intel_tile_width_bytes(const struct drm_i915_private
*dev_priv
,
2090 uint64_t fb_modifier
, unsigned int cpp
)
2092 switch (fb_modifier
) {
2093 case DRM_FORMAT_MOD_NONE
:
2095 case I915_FORMAT_MOD_X_TILED
:
2096 if (IS_GEN2(dev_priv
))
2100 case I915_FORMAT_MOD_Y_TILED
:
2101 if (IS_GEN2(dev_priv
) || HAS_128_BYTE_Y_TILING(dev_priv
))
2105 case I915_FORMAT_MOD_Yf_TILED
:
2121 MISSING_CASE(fb_modifier
);
2126 unsigned int intel_tile_height(const struct drm_i915_private
*dev_priv
,
2127 uint64_t fb_modifier
, unsigned int cpp
)
2129 if (fb_modifier
== DRM_FORMAT_MOD_NONE
)
2132 return intel_tile_size(dev_priv
) /
2133 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2136 /* Return the tile dimensions in pixel units */
2137 static void intel_tile_dims(const struct drm_i915_private
*dev_priv
,
2138 unsigned int *tile_width
,
2139 unsigned int *tile_height
,
2140 uint64_t fb_modifier
,
2143 unsigned int tile_width_bytes
=
2144 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2146 *tile_width
= tile_width_bytes
/ cpp
;
2147 *tile_height
= intel_tile_size(dev_priv
) / tile_width_bytes
;
2151 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2152 uint32_t pixel_format
, uint64_t fb_modifier
)
2154 unsigned int cpp
= drm_format_plane_cpp(pixel_format
, 0);
2155 unsigned int tile_height
= intel_tile_height(to_i915(dev
), fb_modifier
, cpp
);
2157 return ALIGN(height
, tile_height
);
2160 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
2162 unsigned int size
= 0;
2165 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
2166 size
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2172 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
,
2173 const struct drm_framebuffer
*fb
,
2174 unsigned int rotation
)
2176 if (intel_rotation_90_or_270(rotation
)) {
2177 *view
= i915_ggtt_view_rotated
;
2178 view
->params
.rotated
= to_intel_framebuffer(fb
)->rot_info
;
2180 *view
= i915_ggtt_view_normal
;
2185 intel_fill_fb_info(struct drm_i915_private
*dev_priv
,
2186 struct drm_framebuffer
*fb
)
2188 struct intel_rotation_info
*info
= &to_intel_framebuffer(fb
)->rot_info
;
2189 unsigned int tile_size
, tile_width
, tile_height
, cpp
;
2191 tile_size
= intel_tile_size(dev_priv
);
2193 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2194 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2195 fb
->modifier
[0], cpp
);
2197 info
->plane
[0].width
= DIV_ROUND_UP(fb
->pitches
[0], tile_width
* cpp
);
2198 info
->plane
[0].height
= DIV_ROUND_UP(fb
->height
, tile_height
);
2200 if (info
->pixel_format
== DRM_FORMAT_NV12
) {
2201 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 1);
2202 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2203 fb
->modifier
[1], cpp
);
2205 info
->uv_offset
= fb
->offsets
[1];
2206 info
->plane
[1].width
= DIV_ROUND_UP(fb
->pitches
[1], tile_width
* cpp
);
2207 info
->plane
[1].height
= DIV_ROUND_UP(fb
->height
/ 2, tile_height
);
2211 static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv
)
2213 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2215 else if (IS_BROADWATER(dev_priv
) || IS_CRESTLINE(dev_priv
) ||
2216 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2218 else if (INTEL_INFO(dev_priv
)->gen
>= 4)
2224 static unsigned int intel_surf_alignment(const struct drm_i915_private
*dev_priv
,
2225 uint64_t fb_modifier
)
2227 switch (fb_modifier
) {
2228 case DRM_FORMAT_MOD_NONE
:
2229 return intel_linear_alignment(dev_priv
);
2230 case I915_FORMAT_MOD_X_TILED
:
2231 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2234 case I915_FORMAT_MOD_Y_TILED
:
2235 case I915_FORMAT_MOD_Yf_TILED
:
2236 return 1 * 1024 * 1024;
2238 MISSING_CASE(fb_modifier
);
2244 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
2245 unsigned int rotation
)
2247 struct drm_device
*dev
= fb
->dev
;
2248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2249 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2250 struct i915_ggtt_view view
;
2254 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2256 alignment
= intel_surf_alignment(dev_priv
, fb
->modifier
[0]);
2258 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2260 /* Note that the w/a also requires 64 PTE of padding following the
2261 * bo. We currently fill all unused PTE with the shadow page and so
2262 * we should always have valid PTE following the scanout preventing
2265 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2266 alignment
= 256 * 1024;
2269 * Global gtt pte registers are special registers which actually forward
2270 * writes to a chunk of system memory. Which means that there is no risk
2271 * that the register values disappear as soon as we call
2272 * intel_runtime_pm_put(), so it is correct to wrap only the
2273 * pin/unpin/fence and not more.
2275 intel_runtime_pm_get(dev_priv
);
2277 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
,
2282 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2283 * fence, whereas 965+ only requires a fence if using
2284 * framebuffer compression. For simplicity, we always install
2285 * a fence as the cost is not that onerous.
2287 if (view
.type
== I915_GGTT_VIEW_NORMAL
) {
2288 ret
= i915_gem_object_get_fence(obj
);
2289 if (ret
== -EDEADLK
) {
2291 * -EDEADLK means there are no free fences
2294 * This is propagated to atomic, but it uses
2295 * -EDEADLK to force a locking recovery, so
2296 * change the returned error to -EBUSY.
2303 i915_gem_object_pin_fence(obj
);
2306 intel_runtime_pm_put(dev_priv
);
2310 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2312 intel_runtime_pm_put(dev_priv
);
2316 void intel_unpin_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
)
2318 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2319 struct i915_ggtt_view view
;
2321 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2323 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2325 if (view
.type
== I915_GGTT_VIEW_NORMAL
)
2326 i915_gem_object_unpin_fence(obj
);
2328 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2332 * Adjust the tile offset by moving the difference into
2335 * Input tile dimensions and pitch must already be
2336 * rotated to match x and y, and in pixel units.
2338 static u32
intel_adjust_tile_offset(int *x
, int *y
,
2339 unsigned int tile_width
,
2340 unsigned int tile_height
,
2341 unsigned int tile_size
,
2342 unsigned int pitch_tiles
,
2348 WARN_ON(old_offset
& (tile_size
- 1));
2349 WARN_ON(new_offset
& (tile_size
- 1));
2350 WARN_ON(new_offset
> old_offset
);
2352 tiles
= (old_offset
- new_offset
) / tile_size
;
2354 *y
+= tiles
/ pitch_tiles
* tile_height
;
2355 *x
+= tiles
% pitch_tiles
* tile_width
;
2361 * Computes the linear offset to the base tile and adjusts
2362 * x, y. bytes per pixel is assumed to be a power-of-two.
2364 * In the 90/270 rotated case, x and y are assumed
2365 * to be already rotated to match the rotated GTT view, and
2366 * pitch is the tile_height aligned framebuffer height.
2368 u32
intel_compute_tile_offset(int *x
, int *y
,
2369 const struct drm_framebuffer
*fb
, int plane
,
2371 unsigned int rotation
)
2373 const struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2374 uint64_t fb_modifier
= fb
->modifier
[plane
];
2375 unsigned int cpp
= drm_format_plane_cpp(fb
->pixel_format
, plane
);
2376 u32 offset
, offset_aligned
, alignment
;
2378 alignment
= intel_surf_alignment(dev_priv
, fb_modifier
);
2382 if (fb_modifier
!= DRM_FORMAT_MOD_NONE
) {
2383 unsigned int tile_size
, tile_width
, tile_height
;
2384 unsigned int tile_rows
, tiles
, pitch_tiles
;
2386 tile_size
= intel_tile_size(dev_priv
);
2387 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2390 if (intel_rotation_90_or_270(rotation
)) {
2391 pitch_tiles
= pitch
/ tile_height
;
2392 swap(tile_width
, tile_height
);
2394 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2397 tile_rows
= *y
/ tile_height
;
2400 tiles
= *x
/ tile_width
;
2403 offset
= (tile_rows
* pitch_tiles
+ tiles
) * tile_size
;
2404 offset_aligned
= offset
& ~alignment
;
2406 intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2407 tile_size
, pitch_tiles
,
2408 offset
, offset_aligned
);
2410 offset
= *y
* pitch
+ *x
* cpp
;
2411 offset_aligned
= offset
& ~alignment
;
2413 *y
= (offset
& alignment
) / pitch
;
2414 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2417 return offset_aligned
;
2420 static int i9xx_format_to_fourcc(int format
)
2423 case DISPPLANE_8BPP
:
2424 return DRM_FORMAT_C8
;
2425 case DISPPLANE_BGRX555
:
2426 return DRM_FORMAT_XRGB1555
;
2427 case DISPPLANE_BGRX565
:
2428 return DRM_FORMAT_RGB565
;
2430 case DISPPLANE_BGRX888
:
2431 return DRM_FORMAT_XRGB8888
;
2432 case DISPPLANE_RGBX888
:
2433 return DRM_FORMAT_XBGR8888
;
2434 case DISPPLANE_BGRX101010
:
2435 return DRM_FORMAT_XRGB2101010
;
2436 case DISPPLANE_RGBX101010
:
2437 return DRM_FORMAT_XBGR2101010
;
2441 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2444 case PLANE_CTL_FORMAT_RGB_565
:
2445 return DRM_FORMAT_RGB565
;
2447 case PLANE_CTL_FORMAT_XRGB_8888
:
2450 return DRM_FORMAT_ABGR8888
;
2452 return DRM_FORMAT_XBGR8888
;
2455 return DRM_FORMAT_ARGB8888
;
2457 return DRM_FORMAT_XRGB8888
;
2459 case PLANE_CTL_FORMAT_XRGB_2101010
:
2461 return DRM_FORMAT_XBGR2101010
;
2463 return DRM_FORMAT_XRGB2101010
;
2468 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2469 struct intel_initial_plane_config
*plane_config
)
2471 struct drm_device
*dev
= crtc
->base
.dev
;
2472 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2473 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2474 struct drm_i915_gem_object
*obj
= NULL
;
2475 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2476 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2477 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2478 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2481 size_aligned
-= base_aligned
;
2483 if (plane_config
->size
== 0)
2486 /* If the FB is too big, just don't use it since fbdev is not very
2487 * important and we should probably use that space with FBC or other
2489 if (size_aligned
* 2 > ggtt
->stolen_usable_size
)
2492 mutex_lock(&dev
->struct_mutex
);
2494 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2499 mutex_unlock(&dev
->struct_mutex
);
2503 obj
->tiling_mode
= plane_config
->tiling
;
2504 if (obj
->tiling_mode
== I915_TILING_X
)
2505 obj
->stride
= fb
->pitches
[0];
2507 mode_cmd
.pixel_format
= fb
->pixel_format
;
2508 mode_cmd
.width
= fb
->width
;
2509 mode_cmd
.height
= fb
->height
;
2510 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2511 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2512 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2514 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2516 DRM_DEBUG_KMS("intel fb init failed\n");
2520 mutex_unlock(&dev
->struct_mutex
);
2522 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2526 drm_gem_object_unreference(&obj
->base
);
2527 mutex_unlock(&dev
->struct_mutex
);
2531 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2533 update_state_fb(struct drm_plane
*plane
)
2535 if (plane
->fb
== plane
->state
->fb
)
2538 if (plane
->state
->fb
)
2539 drm_framebuffer_unreference(plane
->state
->fb
);
2540 plane
->state
->fb
= plane
->fb
;
2541 if (plane
->state
->fb
)
2542 drm_framebuffer_reference(plane
->state
->fb
);
2546 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2547 struct intel_initial_plane_config
*plane_config
)
2549 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2552 struct intel_crtc
*i
;
2553 struct drm_i915_gem_object
*obj
;
2554 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2555 struct drm_plane_state
*plane_state
= primary
->state
;
2556 struct drm_crtc_state
*crtc_state
= intel_crtc
->base
.state
;
2557 struct intel_plane
*intel_plane
= to_intel_plane(primary
);
2558 struct intel_plane_state
*intel_state
=
2559 to_intel_plane_state(plane_state
);
2560 struct drm_framebuffer
*fb
;
2562 if (!plane_config
->fb
)
2565 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2566 fb
= &plane_config
->fb
->base
;
2570 kfree(plane_config
->fb
);
2573 * Failed to alloc the obj, check to see if we should share
2574 * an fb with another CRTC instead
2576 for_each_crtc(dev
, c
) {
2577 i
= to_intel_crtc(c
);
2579 if (c
== &intel_crtc
->base
)
2585 fb
= c
->primary
->fb
;
2589 obj
= intel_fb_obj(fb
);
2590 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2591 drm_framebuffer_reference(fb
);
2597 * We've failed to reconstruct the BIOS FB. Current display state
2598 * indicates that the primary plane is visible, but has a NULL FB,
2599 * which will lead to problems later if we don't fix it up. The
2600 * simplest solution is to just disable the primary plane now and
2601 * pretend the BIOS never had it enabled.
2603 to_intel_plane_state(plane_state
)->visible
= false;
2604 crtc_state
->plane_mask
&= ~(1 << drm_plane_index(primary
));
2605 intel_pre_disable_primary_noatomic(&intel_crtc
->base
);
2606 intel_plane
->disable_plane(primary
, &intel_crtc
->base
);
2611 plane_state
->src_x
= 0;
2612 plane_state
->src_y
= 0;
2613 plane_state
->src_w
= fb
->width
<< 16;
2614 plane_state
->src_h
= fb
->height
<< 16;
2616 plane_state
->crtc_x
= 0;
2617 plane_state
->crtc_y
= 0;
2618 plane_state
->crtc_w
= fb
->width
;
2619 plane_state
->crtc_h
= fb
->height
;
2621 intel_state
->src
.x1
= plane_state
->src_x
;
2622 intel_state
->src
.y1
= plane_state
->src_y
;
2623 intel_state
->src
.x2
= plane_state
->src_x
+ plane_state
->src_w
;
2624 intel_state
->src
.y2
= plane_state
->src_y
+ plane_state
->src_h
;
2625 intel_state
->dst
.x1
= plane_state
->crtc_x
;
2626 intel_state
->dst
.y1
= plane_state
->crtc_y
;
2627 intel_state
->dst
.x2
= plane_state
->crtc_x
+ plane_state
->crtc_w
;
2628 intel_state
->dst
.y2
= plane_state
->crtc_y
+ plane_state
->crtc_h
;
2630 obj
= intel_fb_obj(fb
);
2631 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2632 dev_priv
->preserve_bios_swizzle
= true;
2634 drm_framebuffer_reference(fb
);
2635 primary
->fb
= primary
->state
->fb
= fb
;
2636 primary
->crtc
= primary
->state
->crtc
= &intel_crtc
->base
;
2637 intel_crtc
->base
.state
->plane_mask
|= (1 << drm_plane_index(primary
));
2638 obj
->frontbuffer_bits
|= to_intel_plane(primary
)->frontbuffer_bit
;
2641 static void i9xx_update_primary_plane(struct drm_plane
*primary
,
2642 const struct intel_crtc_state
*crtc_state
,
2643 const struct intel_plane_state
*plane_state
)
2645 struct drm_device
*dev
= primary
->dev
;
2646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2647 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2648 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2649 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2650 int plane
= intel_crtc
->plane
;
2653 i915_reg_t reg
= DSPCNTR(plane
);
2654 unsigned int rotation
= plane_state
->base
.rotation
;
2655 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2656 int x
= plane_state
->src
.x1
>> 16;
2657 int y
= plane_state
->src
.y1
>> 16;
2659 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2661 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2663 if (INTEL_INFO(dev
)->gen
< 4) {
2664 if (intel_crtc
->pipe
== PIPE_B
)
2665 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2667 /* pipesrc and dspsize control the size that is scaled from,
2668 * which should always be the user's requested size.
2670 I915_WRITE(DSPSIZE(plane
),
2671 ((crtc_state
->pipe_src_h
- 1) << 16) |
2672 (crtc_state
->pipe_src_w
- 1));
2673 I915_WRITE(DSPPOS(plane
), 0);
2674 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2675 I915_WRITE(PRIMSIZE(plane
),
2676 ((crtc_state
->pipe_src_h
- 1) << 16) |
2677 (crtc_state
->pipe_src_w
- 1));
2678 I915_WRITE(PRIMPOS(plane
), 0);
2679 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2682 switch (fb
->pixel_format
) {
2684 dspcntr
|= DISPPLANE_8BPP
;
2686 case DRM_FORMAT_XRGB1555
:
2687 dspcntr
|= DISPPLANE_BGRX555
;
2689 case DRM_FORMAT_RGB565
:
2690 dspcntr
|= DISPPLANE_BGRX565
;
2692 case DRM_FORMAT_XRGB8888
:
2693 dspcntr
|= DISPPLANE_BGRX888
;
2695 case DRM_FORMAT_XBGR8888
:
2696 dspcntr
|= DISPPLANE_RGBX888
;
2698 case DRM_FORMAT_XRGB2101010
:
2699 dspcntr
|= DISPPLANE_BGRX101010
;
2701 case DRM_FORMAT_XBGR2101010
:
2702 dspcntr
|= DISPPLANE_RGBX101010
;
2708 if (INTEL_INFO(dev
)->gen
>= 4 &&
2709 obj
->tiling_mode
!= I915_TILING_NONE
)
2710 dspcntr
|= DISPPLANE_TILED
;
2713 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2715 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
2717 if (INTEL_INFO(dev
)->gen
>= 4) {
2718 intel_crtc
->dspaddr_offset
=
2719 intel_compute_tile_offset(&x
, &y
, fb
, 0,
2720 fb
->pitches
[0], rotation
);
2721 linear_offset
-= intel_crtc
->dspaddr_offset
;
2723 intel_crtc
->dspaddr_offset
= linear_offset
;
2726 if (rotation
== BIT(DRM_ROTATE_180
)) {
2727 dspcntr
|= DISPPLANE_ROTATE_180
;
2729 x
+= (crtc_state
->pipe_src_w
- 1);
2730 y
+= (crtc_state
->pipe_src_h
- 1);
2732 /* Finding the last pixel of the last line of the display
2733 data and adding to linear_offset*/
2735 (crtc_state
->pipe_src_h
- 1) * fb
->pitches
[0] +
2736 (crtc_state
->pipe_src_w
- 1) * cpp
;
2739 intel_crtc
->adjusted_x
= x
;
2740 intel_crtc
->adjusted_y
= y
;
2742 I915_WRITE(reg
, dspcntr
);
2744 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2745 if (INTEL_INFO(dev
)->gen
>= 4) {
2746 I915_WRITE(DSPSURF(plane
),
2747 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2748 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2749 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2751 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2755 static void i9xx_disable_primary_plane(struct drm_plane
*primary
,
2756 struct drm_crtc
*crtc
)
2758 struct drm_device
*dev
= crtc
->dev
;
2759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2760 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2761 int plane
= intel_crtc
->plane
;
2763 I915_WRITE(DSPCNTR(plane
), 0);
2764 if (INTEL_INFO(dev_priv
)->gen
>= 4)
2765 I915_WRITE(DSPSURF(plane
), 0);
2767 I915_WRITE(DSPADDR(plane
), 0);
2768 POSTING_READ(DSPCNTR(plane
));
2771 static void ironlake_update_primary_plane(struct drm_plane
*primary
,
2772 const struct intel_crtc_state
*crtc_state
,
2773 const struct intel_plane_state
*plane_state
)
2775 struct drm_device
*dev
= primary
->dev
;
2776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2777 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2778 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2779 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2780 int plane
= intel_crtc
->plane
;
2783 i915_reg_t reg
= DSPCNTR(plane
);
2784 unsigned int rotation
= plane_state
->base
.rotation
;
2785 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2786 int x
= plane_state
->src
.x1
>> 16;
2787 int y
= plane_state
->src
.y1
>> 16;
2789 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2790 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2792 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2793 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2795 switch (fb
->pixel_format
) {
2797 dspcntr
|= DISPPLANE_8BPP
;
2799 case DRM_FORMAT_RGB565
:
2800 dspcntr
|= DISPPLANE_BGRX565
;
2802 case DRM_FORMAT_XRGB8888
:
2803 dspcntr
|= DISPPLANE_BGRX888
;
2805 case DRM_FORMAT_XBGR8888
:
2806 dspcntr
|= DISPPLANE_RGBX888
;
2808 case DRM_FORMAT_XRGB2101010
:
2809 dspcntr
|= DISPPLANE_BGRX101010
;
2811 case DRM_FORMAT_XBGR2101010
:
2812 dspcntr
|= DISPPLANE_RGBX101010
;
2818 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2819 dspcntr
|= DISPPLANE_TILED
;
2821 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2822 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2824 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
2825 intel_crtc
->dspaddr_offset
=
2826 intel_compute_tile_offset(&x
, &y
, fb
, 0,
2827 fb
->pitches
[0], rotation
);
2828 linear_offset
-= intel_crtc
->dspaddr_offset
;
2829 if (rotation
== BIT(DRM_ROTATE_180
)) {
2830 dspcntr
|= DISPPLANE_ROTATE_180
;
2832 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2833 x
+= (crtc_state
->pipe_src_w
- 1);
2834 y
+= (crtc_state
->pipe_src_h
- 1);
2836 /* Finding the last pixel of the last line of the display
2837 data and adding to linear_offset*/
2839 (crtc_state
->pipe_src_h
- 1) * fb
->pitches
[0] +
2840 (crtc_state
->pipe_src_w
- 1) * cpp
;
2844 intel_crtc
->adjusted_x
= x
;
2845 intel_crtc
->adjusted_y
= y
;
2847 I915_WRITE(reg
, dspcntr
);
2849 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2850 I915_WRITE(DSPSURF(plane
),
2851 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2852 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2853 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2855 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2856 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2861 u32
intel_fb_stride_alignment(const struct drm_i915_private
*dev_priv
,
2862 uint64_t fb_modifier
, uint32_t pixel_format
)
2864 if (fb_modifier
== DRM_FORMAT_MOD_NONE
) {
2867 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
2869 return intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2873 u32
intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2874 struct drm_i915_gem_object
*obj
,
2877 struct i915_ggtt_view view
;
2878 struct i915_vma
*vma
;
2881 intel_fill_fb_ggtt_view(&view
, intel_plane
->base
.state
->fb
,
2882 intel_plane
->base
.state
->rotation
);
2884 vma
= i915_gem_obj_to_ggtt_view(obj
, &view
);
2885 if (WARN(!vma
, "ggtt vma for display object not found! (view=%u)\n",
2889 offset
= vma
->node
.start
;
2892 offset
+= vma
->ggtt_view
.params
.rotated
.uv_start_page
*
2896 WARN_ON(upper_32_bits(offset
));
2898 return lower_32_bits(offset
);
2901 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
2903 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2906 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
2907 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
2908 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
2912 * This function detaches (aka. unbinds) unused scalers in hardware
2914 static void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2916 struct intel_crtc_scaler_state
*scaler_state
;
2919 scaler_state
= &intel_crtc
->config
->scaler_state
;
2921 /* loop through and disable scalers that aren't in use */
2922 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2923 if (!scaler_state
->scalers
[i
].in_use
)
2924 skl_detach_scaler(intel_crtc
, i
);
2928 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2930 switch (pixel_format
) {
2932 return PLANE_CTL_FORMAT_INDEXED
;
2933 case DRM_FORMAT_RGB565
:
2934 return PLANE_CTL_FORMAT_RGB_565
;
2935 case DRM_FORMAT_XBGR8888
:
2936 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2937 case DRM_FORMAT_XRGB8888
:
2938 return PLANE_CTL_FORMAT_XRGB_8888
;
2940 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2941 * to be already pre-multiplied. We need to add a knob (or a different
2942 * DRM_FORMAT) for user-space to configure that.
2944 case DRM_FORMAT_ABGR8888
:
2945 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
2946 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2947 case DRM_FORMAT_ARGB8888
:
2948 return PLANE_CTL_FORMAT_XRGB_8888
|
2949 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2950 case DRM_FORMAT_XRGB2101010
:
2951 return PLANE_CTL_FORMAT_XRGB_2101010
;
2952 case DRM_FORMAT_XBGR2101010
:
2953 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
2954 case DRM_FORMAT_YUYV
:
2955 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
2956 case DRM_FORMAT_YVYU
:
2957 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
2958 case DRM_FORMAT_UYVY
:
2959 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
2960 case DRM_FORMAT_VYUY
:
2961 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
2963 MISSING_CASE(pixel_format
);
2969 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
2971 switch (fb_modifier
) {
2972 case DRM_FORMAT_MOD_NONE
:
2974 case I915_FORMAT_MOD_X_TILED
:
2975 return PLANE_CTL_TILED_X
;
2976 case I915_FORMAT_MOD_Y_TILED
:
2977 return PLANE_CTL_TILED_Y
;
2978 case I915_FORMAT_MOD_Yf_TILED
:
2979 return PLANE_CTL_TILED_YF
;
2981 MISSING_CASE(fb_modifier
);
2987 u32
skl_plane_ctl_rotation(unsigned int rotation
)
2990 case BIT(DRM_ROTATE_0
):
2993 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2994 * while i915 HW rotation is clockwise, thats why this swapping.
2996 case BIT(DRM_ROTATE_90
):
2997 return PLANE_CTL_ROTATE_270
;
2998 case BIT(DRM_ROTATE_180
):
2999 return PLANE_CTL_ROTATE_180
;
3000 case BIT(DRM_ROTATE_270
):
3001 return PLANE_CTL_ROTATE_90
;
3003 MISSING_CASE(rotation
);
3009 static void skylake_update_primary_plane(struct drm_plane
*plane
,
3010 const struct intel_crtc_state
*crtc_state
,
3011 const struct intel_plane_state
*plane_state
)
3013 struct drm_device
*dev
= plane
->dev
;
3014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3015 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3016 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3017 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
3018 int pipe
= intel_crtc
->pipe
;
3019 u32 plane_ctl
, stride_div
, stride
;
3020 u32 tile_height
, plane_offset
, plane_size
;
3021 unsigned int rotation
= plane_state
->base
.rotation
;
3022 int x_offset
, y_offset
;
3024 int scaler_id
= plane_state
->scaler_id
;
3025 int src_x
= plane_state
->src
.x1
>> 16;
3026 int src_y
= plane_state
->src
.y1
>> 16;
3027 int src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3028 int src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3029 int dst_x
= plane_state
->dst
.x1
;
3030 int dst_y
= plane_state
->dst
.y1
;
3031 int dst_w
= drm_rect_width(&plane_state
->dst
);
3032 int dst_h
= drm_rect_height(&plane_state
->dst
);
3034 plane_ctl
= PLANE_CTL_ENABLE
|
3035 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3036 PLANE_CTL_PIPE_CSC_ENABLE
;
3038 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3039 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3040 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3041 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3043 stride_div
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
3045 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
, 0);
3047 WARN_ON(drm_rect_width(&plane_state
->src
) == 0);
3049 if (intel_rotation_90_or_270(rotation
)) {
3050 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
3052 /* stride = Surface height in tiles */
3053 tile_height
= intel_tile_height(dev_priv
, fb
->modifier
[0], cpp
);
3054 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3055 x_offset
= stride
* tile_height
- src_y
- src_h
;
3057 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3059 stride
= fb
->pitches
[0] / stride_div
;
3062 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3064 plane_offset
= y_offset
<< 16 | x_offset
;
3066 intel_crtc
->adjusted_x
= x_offset
;
3067 intel_crtc
->adjusted_y
= y_offset
;
3069 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3070 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3071 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3072 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3074 if (scaler_id
>= 0) {
3075 uint32_t ps_ctrl
= 0;
3077 WARN_ON(!dst_w
|| !dst_h
);
3078 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3079 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3080 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3081 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3082 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3083 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3084 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3086 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3089 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3091 POSTING_READ(PLANE_SURF(pipe
, 0));
3094 static void skylake_disable_primary_plane(struct drm_plane
*primary
,
3095 struct drm_crtc
*crtc
)
3097 struct drm_device
*dev
= crtc
->dev
;
3098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3099 int pipe
= to_intel_crtc(crtc
)->pipe
;
3101 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3102 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3103 POSTING_READ(PLANE_SURF(pipe
, 0));
3106 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3108 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3109 int x
, int y
, enum mode_set_atomic state
)
3111 /* Support for kgdboc is disabled, this needs a major rework. */
3112 DRM_ERROR("legacy panic handler not supported any more.\n");
3117 static void intel_complete_page_flips(struct drm_i915_private
*dev_priv
)
3119 struct intel_crtc
*crtc
;
3121 for_each_intel_crtc(dev_priv
->dev
, crtc
)
3122 intel_finish_page_flip_cs(dev_priv
, crtc
->pipe
);
3125 static void intel_update_primary_planes(struct drm_device
*dev
)
3127 struct drm_crtc
*crtc
;
3129 for_each_crtc(dev
, crtc
) {
3130 struct intel_plane
*plane
= to_intel_plane(crtc
->primary
);
3131 struct intel_plane_state
*plane_state
;
3133 drm_modeset_lock_crtc(crtc
, &plane
->base
);
3134 plane_state
= to_intel_plane_state(plane
->base
.state
);
3136 if (plane_state
->visible
)
3137 plane
->update_plane(&plane
->base
,
3138 to_intel_crtc_state(crtc
->state
),
3141 drm_modeset_unlock_crtc(crtc
);
3145 void intel_prepare_reset(struct drm_i915_private
*dev_priv
)
3147 /* no reset support for gen2 */
3148 if (IS_GEN2(dev_priv
))
3151 /* reset doesn't touch the display */
3152 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
3155 drm_modeset_lock_all(dev_priv
->dev
);
3157 * Disabling the crtcs gracefully seems nicer. Also the
3158 * g33 docs say we should at least disable all the planes.
3160 intel_display_suspend(dev_priv
->dev
);
3163 void intel_finish_reset(struct drm_i915_private
*dev_priv
)
3166 * Flips in the rings will be nuked by the reset,
3167 * so complete all pending flips so that user space
3168 * will get its events and not get stuck.
3170 intel_complete_page_flips(dev_priv
);
3172 /* no reset support for gen2 */
3173 if (IS_GEN2(dev_priv
))
3176 /* reset doesn't touch the display */
3177 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
)) {
3179 * Flips in the rings have been nuked by the reset,
3180 * so update the base address of all primary
3181 * planes to the the last fb to make sure we're
3182 * showing the correct fb after a reset.
3184 * FIXME: Atomic will make this obsolete since we won't schedule
3185 * CS-based flips (which might get lost in gpu resets) any more.
3187 intel_update_primary_planes(dev_priv
->dev
);
3192 * The display has been reset as well,
3193 * so need a full re-initialization.
3195 intel_runtime_pm_disable_interrupts(dev_priv
);
3196 intel_runtime_pm_enable_interrupts(dev_priv
);
3198 intel_modeset_init_hw(dev_priv
->dev
);
3200 spin_lock_irq(&dev_priv
->irq_lock
);
3201 if (dev_priv
->display
.hpd_irq_setup
)
3202 dev_priv
->display
.hpd_irq_setup(dev_priv
);
3203 spin_unlock_irq(&dev_priv
->irq_lock
);
3205 intel_display_resume(dev_priv
->dev
);
3207 intel_hpd_init(dev_priv
);
3209 drm_modeset_unlock_all(dev_priv
->dev
);
3212 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3214 struct drm_device
*dev
= crtc
->dev
;
3215 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3216 unsigned reset_counter
;
3219 reset_counter
= i915_reset_counter(&to_i915(dev
)->gpu_error
);
3220 if (intel_crtc
->reset_counter
!= reset_counter
)
3223 spin_lock_irq(&dev
->event_lock
);
3224 pending
= to_intel_crtc(crtc
)->flip_work
!= NULL
;
3225 spin_unlock_irq(&dev
->event_lock
);
3230 static void intel_update_pipe_config(struct intel_crtc
*crtc
,
3231 struct intel_crtc_state
*old_crtc_state
)
3233 struct drm_device
*dev
= crtc
->base
.dev
;
3234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3235 struct intel_crtc_state
*pipe_config
=
3236 to_intel_crtc_state(crtc
->base
.state
);
3238 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3239 crtc
->base
.mode
= crtc
->base
.state
->mode
;
3241 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3242 old_crtc_state
->pipe_src_w
, old_crtc_state
->pipe_src_h
,
3243 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
3246 * Update pipe size and adjust fitter if needed: the reason for this is
3247 * that in compute_mode_changes we check the native mode (not the pfit
3248 * mode) to see if we can flip rather than do a full mode set. In the
3249 * fastboot case, we'll flip, but if we don't update the pipesrc and
3250 * pfit state, we'll end up with a big fb scanned out into the wrong
3254 I915_WRITE(PIPESRC(crtc
->pipe
),
3255 ((pipe_config
->pipe_src_w
- 1) << 16) |
3256 (pipe_config
->pipe_src_h
- 1));
3258 /* on skylake this is done by detaching scalers */
3259 if (INTEL_INFO(dev
)->gen
>= 9) {
3260 skl_detach_scalers(crtc
);
3262 if (pipe_config
->pch_pfit
.enabled
)
3263 skylake_pfit_enable(crtc
);
3264 } else if (HAS_PCH_SPLIT(dev
)) {
3265 if (pipe_config
->pch_pfit
.enabled
)
3266 ironlake_pfit_enable(crtc
);
3267 else if (old_crtc_state
->pch_pfit
.enabled
)
3268 ironlake_pfit_disable(crtc
, true);
3272 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3274 struct drm_device
*dev
= crtc
->dev
;
3275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3276 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3277 int pipe
= intel_crtc
->pipe
;
3281 /* enable normal train */
3282 reg
= FDI_TX_CTL(pipe
);
3283 temp
= I915_READ(reg
);
3284 if (IS_IVYBRIDGE(dev
)) {
3285 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3286 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3288 temp
&= ~FDI_LINK_TRAIN_NONE
;
3289 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3291 I915_WRITE(reg
, temp
);
3293 reg
= FDI_RX_CTL(pipe
);
3294 temp
= I915_READ(reg
);
3295 if (HAS_PCH_CPT(dev
)) {
3296 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3297 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3299 temp
&= ~FDI_LINK_TRAIN_NONE
;
3300 temp
|= FDI_LINK_TRAIN_NONE
;
3302 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3304 /* wait one idle pattern time */
3308 /* IVB wants error correction enabled */
3309 if (IS_IVYBRIDGE(dev
))
3310 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3311 FDI_FE_ERRC_ENABLE
);
3314 /* The FDI link training functions for ILK/Ibexpeak. */
3315 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3317 struct drm_device
*dev
= crtc
->dev
;
3318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3319 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3320 int pipe
= intel_crtc
->pipe
;
3324 /* FDI needs bits from pipe first */
3325 assert_pipe_enabled(dev_priv
, pipe
);
3327 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3329 reg
= FDI_RX_IMR(pipe
);
3330 temp
= I915_READ(reg
);
3331 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3332 temp
&= ~FDI_RX_BIT_LOCK
;
3333 I915_WRITE(reg
, temp
);
3337 /* enable CPU FDI TX and PCH FDI RX */
3338 reg
= FDI_TX_CTL(pipe
);
3339 temp
= I915_READ(reg
);
3340 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3341 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3342 temp
&= ~FDI_LINK_TRAIN_NONE
;
3343 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3344 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3346 reg
= FDI_RX_CTL(pipe
);
3347 temp
= I915_READ(reg
);
3348 temp
&= ~FDI_LINK_TRAIN_NONE
;
3349 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3350 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3355 /* Ironlake workaround, enable clock pointer after FDI enable*/
3356 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3357 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3358 FDI_RX_PHASE_SYNC_POINTER_EN
);
3360 reg
= FDI_RX_IIR(pipe
);
3361 for (tries
= 0; tries
< 5; tries
++) {
3362 temp
= I915_READ(reg
);
3363 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3365 if ((temp
& FDI_RX_BIT_LOCK
)) {
3366 DRM_DEBUG_KMS("FDI train 1 done.\n");
3367 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3372 DRM_ERROR("FDI train 1 fail!\n");
3375 reg
= FDI_TX_CTL(pipe
);
3376 temp
= I915_READ(reg
);
3377 temp
&= ~FDI_LINK_TRAIN_NONE
;
3378 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3379 I915_WRITE(reg
, temp
);
3381 reg
= FDI_RX_CTL(pipe
);
3382 temp
= I915_READ(reg
);
3383 temp
&= ~FDI_LINK_TRAIN_NONE
;
3384 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3385 I915_WRITE(reg
, temp
);
3390 reg
= FDI_RX_IIR(pipe
);
3391 for (tries
= 0; tries
< 5; tries
++) {
3392 temp
= I915_READ(reg
);
3393 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3395 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3396 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3397 DRM_DEBUG_KMS("FDI train 2 done.\n");
3402 DRM_ERROR("FDI train 2 fail!\n");
3404 DRM_DEBUG_KMS("FDI train done\n");
3408 static const int snb_b_fdi_train_param
[] = {
3409 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3410 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3411 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3412 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3415 /* The FDI link training functions for SNB/Cougarpoint. */
3416 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3418 struct drm_device
*dev
= crtc
->dev
;
3419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3420 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3421 int pipe
= intel_crtc
->pipe
;
3425 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3427 reg
= FDI_RX_IMR(pipe
);
3428 temp
= I915_READ(reg
);
3429 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3430 temp
&= ~FDI_RX_BIT_LOCK
;
3431 I915_WRITE(reg
, temp
);
3436 /* enable CPU FDI TX and PCH FDI RX */
3437 reg
= FDI_TX_CTL(pipe
);
3438 temp
= I915_READ(reg
);
3439 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3440 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3441 temp
&= ~FDI_LINK_TRAIN_NONE
;
3442 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3443 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3445 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3446 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3448 I915_WRITE(FDI_RX_MISC(pipe
),
3449 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3451 reg
= FDI_RX_CTL(pipe
);
3452 temp
= I915_READ(reg
);
3453 if (HAS_PCH_CPT(dev
)) {
3454 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3455 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3457 temp
&= ~FDI_LINK_TRAIN_NONE
;
3458 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3460 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3465 for (i
= 0; i
< 4; i
++) {
3466 reg
= FDI_TX_CTL(pipe
);
3467 temp
= I915_READ(reg
);
3468 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3469 temp
|= snb_b_fdi_train_param
[i
];
3470 I915_WRITE(reg
, temp
);
3475 for (retry
= 0; retry
< 5; retry
++) {
3476 reg
= FDI_RX_IIR(pipe
);
3477 temp
= I915_READ(reg
);
3478 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3479 if (temp
& FDI_RX_BIT_LOCK
) {
3480 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3481 DRM_DEBUG_KMS("FDI train 1 done.\n");
3490 DRM_ERROR("FDI train 1 fail!\n");
3493 reg
= FDI_TX_CTL(pipe
);
3494 temp
= I915_READ(reg
);
3495 temp
&= ~FDI_LINK_TRAIN_NONE
;
3496 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3498 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3500 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3502 I915_WRITE(reg
, temp
);
3504 reg
= FDI_RX_CTL(pipe
);
3505 temp
= I915_READ(reg
);
3506 if (HAS_PCH_CPT(dev
)) {
3507 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3508 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3510 temp
&= ~FDI_LINK_TRAIN_NONE
;
3511 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3513 I915_WRITE(reg
, temp
);
3518 for (i
= 0; i
< 4; i
++) {
3519 reg
= FDI_TX_CTL(pipe
);
3520 temp
= I915_READ(reg
);
3521 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3522 temp
|= snb_b_fdi_train_param
[i
];
3523 I915_WRITE(reg
, temp
);
3528 for (retry
= 0; retry
< 5; retry
++) {
3529 reg
= FDI_RX_IIR(pipe
);
3530 temp
= I915_READ(reg
);
3531 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3532 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3533 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3534 DRM_DEBUG_KMS("FDI train 2 done.\n");
3543 DRM_ERROR("FDI train 2 fail!\n");
3545 DRM_DEBUG_KMS("FDI train done.\n");
3548 /* Manual link training for Ivy Bridge A0 parts */
3549 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3551 struct drm_device
*dev
= crtc
->dev
;
3552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3553 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3554 int pipe
= intel_crtc
->pipe
;
3558 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3560 reg
= FDI_RX_IMR(pipe
);
3561 temp
= I915_READ(reg
);
3562 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3563 temp
&= ~FDI_RX_BIT_LOCK
;
3564 I915_WRITE(reg
, temp
);
3569 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3570 I915_READ(FDI_RX_IIR(pipe
)));
3572 /* Try each vswing and preemphasis setting twice before moving on */
3573 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3574 /* disable first in case we need to retry */
3575 reg
= FDI_TX_CTL(pipe
);
3576 temp
= I915_READ(reg
);
3577 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3578 temp
&= ~FDI_TX_ENABLE
;
3579 I915_WRITE(reg
, temp
);
3581 reg
= FDI_RX_CTL(pipe
);
3582 temp
= I915_READ(reg
);
3583 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3584 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3585 temp
&= ~FDI_RX_ENABLE
;
3586 I915_WRITE(reg
, temp
);
3588 /* enable CPU FDI TX and PCH FDI RX */
3589 reg
= FDI_TX_CTL(pipe
);
3590 temp
= I915_READ(reg
);
3591 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3592 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3593 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3594 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3595 temp
|= snb_b_fdi_train_param
[j
/2];
3596 temp
|= FDI_COMPOSITE_SYNC
;
3597 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3599 I915_WRITE(FDI_RX_MISC(pipe
),
3600 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3602 reg
= FDI_RX_CTL(pipe
);
3603 temp
= I915_READ(reg
);
3604 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3605 temp
|= FDI_COMPOSITE_SYNC
;
3606 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3609 udelay(1); /* should be 0.5us */
3611 for (i
= 0; i
< 4; i
++) {
3612 reg
= FDI_RX_IIR(pipe
);
3613 temp
= I915_READ(reg
);
3614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3616 if (temp
& FDI_RX_BIT_LOCK
||
3617 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3618 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3619 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3623 udelay(1); /* should be 0.5us */
3626 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3631 reg
= FDI_TX_CTL(pipe
);
3632 temp
= I915_READ(reg
);
3633 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3634 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3635 I915_WRITE(reg
, temp
);
3637 reg
= FDI_RX_CTL(pipe
);
3638 temp
= I915_READ(reg
);
3639 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3640 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3641 I915_WRITE(reg
, temp
);
3644 udelay(2); /* should be 1.5us */
3646 for (i
= 0; i
< 4; i
++) {
3647 reg
= FDI_RX_IIR(pipe
);
3648 temp
= I915_READ(reg
);
3649 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3651 if (temp
& FDI_RX_SYMBOL_LOCK
||
3652 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3653 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3654 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3658 udelay(2); /* should be 1.5us */
3661 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3665 DRM_DEBUG_KMS("FDI train done.\n");
3668 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3670 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3672 int pipe
= intel_crtc
->pipe
;
3676 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3677 reg
= FDI_RX_CTL(pipe
);
3678 temp
= I915_READ(reg
);
3679 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3680 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3681 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3682 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3687 /* Switch from Rawclk to PCDclk */
3688 temp
= I915_READ(reg
);
3689 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3694 /* Enable CPU FDI TX PLL, always on for Ironlake */
3695 reg
= FDI_TX_CTL(pipe
);
3696 temp
= I915_READ(reg
);
3697 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3698 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3705 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3707 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3709 int pipe
= intel_crtc
->pipe
;
3713 /* Switch from PCDclk to Rawclk */
3714 reg
= FDI_RX_CTL(pipe
);
3715 temp
= I915_READ(reg
);
3716 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3718 /* Disable CPU FDI TX PLL */
3719 reg
= FDI_TX_CTL(pipe
);
3720 temp
= I915_READ(reg
);
3721 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3726 reg
= FDI_RX_CTL(pipe
);
3727 temp
= I915_READ(reg
);
3728 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3730 /* Wait for the clocks to turn off. */
3735 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3737 struct drm_device
*dev
= crtc
->dev
;
3738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3739 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3740 int pipe
= intel_crtc
->pipe
;
3744 /* disable CPU FDI tx and PCH FDI rx */
3745 reg
= FDI_TX_CTL(pipe
);
3746 temp
= I915_READ(reg
);
3747 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3750 reg
= FDI_RX_CTL(pipe
);
3751 temp
= I915_READ(reg
);
3752 temp
&= ~(0x7 << 16);
3753 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3754 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3759 /* Ironlake workaround, disable clock pointer after downing FDI */
3760 if (HAS_PCH_IBX(dev
))
3761 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3763 /* still set train pattern 1 */
3764 reg
= FDI_TX_CTL(pipe
);
3765 temp
= I915_READ(reg
);
3766 temp
&= ~FDI_LINK_TRAIN_NONE
;
3767 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3768 I915_WRITE(reg
, temp
);
3770 reg
= FDI_RX_CTL(pipe
);
3771 temp
= I915_READ(reg
);
3772 if (HAS_PCH_CPT(dev
)) {
3773 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3774 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3776 temp
&= ~FDI_LINK_TRAIN_NONE
;
3777 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3779 /* BPC in FDI rx is consistent with that in PIPECONF */
3780 temp
&= ~(0x07 << 16);
3781 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3782 I915_WRITE(reg
, temp
);
3788 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3790 struct intel_crtc
*crtc
;
3792 /* Note that we don't need to be called with mode_config.lock here
3793 * as our list of CRTC objects is static for the lifetime of the
3794 * device and so cannot disappear as we iterate. Similarly, we can
3795 * happily treat the predicates as racy, atomic checks as userspace
3796 * cannot claim and pin a new fb without at least acquring the
3797 * struct_mutex and so serialising with us.
3799 for_each_intel_crtc(dev
, crtc
) {
3800 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3803 if (crtc
->flip_work
)
3804 intel_wait_for_vblank(dev
, crtc
->pipe
);
3812 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3814 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3815 struct intel_flip_work
*work
= intel_crtc
->flip_work
;
3817 intel_crtc
->flip_work
= NULL
;
3820 drm_crtc_send_vblank_event(&intel_crtc
->base
, work
->event
);
3822 drm_crtc_vblank_put(&intel_crtc
->base
);
3824 wake_up_all(&dev_priv
->pending_flip_queue
);
3825 queue_work(dev_priv
->wq
, &work
->unpin_work
);
3827 trace_i915_flip_complete(intel_crtc
->plane
,
3828 work
->pending_flip_obj
);
3831 static int intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3833 struct drm_device
*dev
= crtc
->dev
;
3834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3837 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3839 ret
= wait_event_interruptible_timeout(
3840 dev_priv
->pending_flip_queue
,
3841 !intel_crtc_has_pending_flip(crtc
),
3848 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3849 struct intel_flip_work
*work
;
3851 spin_lock_irq(&dev
->event_lock
);
3852 work
= intel_crtc
->flip_work
;
3853 if (work
&& !is_mmio_work(work
)) {
3854 WARN_ONCE(1, "Removing stuck page flip\n");
3855 page_flip_completed(intel_crtc
);
3857 spin_unlock_irq(&dev
->event_lock
);
3863 static void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
)
3867 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3869 mutex_lock(&dev_priv
->sb_lock
);
3871 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3872 temp
|= SBI_SSCCTL_DISABLE
;
3873 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3875 mutex_unlock(&dev_priv
->sb_lock
);
3878 /* Program iCLKIP clock to the desired frequency */
3879 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3881 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
3882 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3883 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3886 lpt_disable_iclkip(dev_priv
);
3888 /* The iCLK virtual clock root frequency is in MHz,
3889 * but the adjusted_mode->crtc_clock in in KHz. To get the
3890 * divisors, it is necessary to divide one by another, so we
3891 * convert the virtual clock precision to KHz here for higher
3894 for (auxdiv
= 0; auxdiv
< 2; auxdiv
++) {
3895 u32 iclk_virtual_root_freq
= 172800 * 1000;
3896 u32 iclk_pi_range
= 64;
3897 u32 desired_divisor
;
3899 desired_divisor
= DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
3901 divsel
= (desired_divisor
/ iclk_pi_range
) - 2;
3902 phaseinc
= desired_divisor
% iclk_pi_range
;
3905 * Near 20MHz is a corner case which is
3906 * out of range for the 7-bit divisor
3912 /* This should not happen with any sane values */
3913 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3914 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3915 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3916 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3918 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3925 mutex_lock(&dev_priv
->sb_lock
);
3927 /* Program SSCDIVINTPHASE6 */
3928 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3929 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3930 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3931 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3932 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3933 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3934 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3935 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3937 /* Program SSCAUXDIV */
3938 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3939 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3940 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3941 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3943 /* Enable modulator and associated divider */
3944 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3945 temp
&= ~SBI_SSCCTL_DISABLE
;
3946 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3948 mutex_unlock(&dev_priv
->sb_lock
);
3950 /* Wait for initialization time */
3953 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3956 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
)
3958 u32 divsel
, phaseinc
, auxdiv
;
3959 u32 iclk_virtual_root_freq
= 172800 * 1000;
3960 u32 iclk_pi_range
= 64;
3961 u32 desired_divisor
;
3964 if ((I915_READ(PIXCLK_GATE
) & PIXCLK_GATE_UNGATE
) == 0)
3967 mutex_lock(&dev_priv
->sb_lock
);
3969 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3970 if (temp
& SBI_SSCCTL_DISABLE
) {
3971 mutex_unlock(&dev_priv
->sb_lock
);
3975 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3976 divsel
= (temp
& SBI_SSCDIVINTPHASE_DIVSEL_MASK
) >>
3977 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT
;
3978 phaseinc
= (temp
& SBI_SSCDIVINTPHASE_INCVAL_MASK
) >>
3979 SBI_SSCDIVINTPHASE_INCVAL_SHIFT
;
3981 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3982 auxdiv
= (temp
& SBI_SSCAUXDIV_FINALDIV2SEL_MASK
) >>
3983 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT
;
3985 mutex_unlock(&dev_priv
->sb_lock
);
3987 desired_divisor
= (divsel
+ 2) * iclk_pi_range
+ phaseinc
;
3989 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
3990 desired_divisor
<< auxdiv
);
3993 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3994 enum pipe pch_transcoder
)
3996 struct drm_device
*dev
= crtc
->base
.dev
;
3997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3998 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4000 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4001 I915_READ(HTOTAL(cpu_transcoder
)));
4002 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4003 I915_READ(HBLANK(cpu_transcoder
)));
4004 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4005 I915_READ(HSYNC(cpu_transcoder
)));
4007 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4008 I915_READ(VTOTAL(cpu_transcoder
)));
4009 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4010 I915_READ(VBLANK(cpu_transcoder
)));
4011 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4012 I915_READ(VSYNC(cpu_transcoder
)));
4013 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4014 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4017 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4022 temp
= I915_READ(SOUTH_CHICKEN1
);
4023 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4026 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4027 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4029 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4031 temp
|= FDI_BC_BIFURCATION_SELECT
;
4033 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4034 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4035 POSTING_READ(SOUTH_CHICKEN1
);
4038 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4040 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4042 switch (intel_crtc
->pipe
) {
4046 if (intel_crtc
->config
->fdi_lanes
> 2)
4047 cpt_set_fdi_bc_bifurcation(dev
, false);
4049 cpt_set_fdi_bc_bifurcation(dev
, true);
4053 cpt_set_fdi_bc_bifurcation(dev
, true);
4061 /* Return which DP Port should be selected for Transcoder DP control */
4063 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4065 struct drm_device
*dev
= crtc
->dev
;
4066 struct intel_encoder
*encoder
;
4068 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4069 if (encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4070 encoder
->type
== INTEL_OUTPUT_EDP
)
4071 return enc_to_dig_port(&encoder
->base
)->port
;
4078 * Enable PCH resources required for PCH ports:
4080 * - FDI training & RX/TX
4081 * - update transcoder timings
4082 * - DP transcoding bits
4085 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4087 struct drm_device
*dev
= crtc
->dev
;
4088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4089 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4090 int pipe
= intel_crtc
->pipe
;
4093 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4095 if (IS_IVYBRIDGE(dev
))
4096 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4098 /* Write the TU size bits before fdi link training, so that error
4099 * detection works. */
4100 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4101 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4103 /* For PCH output, training FDI link */
4104 dev_priv
->display
.fdi_link_train(crtc
);
4106 /* We need to program the right clock selection before writing the pixel
4107 * mutliplier into the DPLL. */
4108 if (HAS_PCH_CPT(dev
)) {
4111 temp
= I915_READ(PCH_DPLL_SEL
);
4112 temp
|= TRANS_DPLL_ENABLE(pipe
);
4113 sel
= TRANS_DPLLB_SEL(pipe
);
4114 if (intel_crtc
->config
->shared_dpll
==
4115 intel_get_shared_dpll_by_id(dev_priv
, DPLL_ID_PCH_PLL_B
))
4119 I915_WRITE(PCH_DPLL_SEL
, temp
);
4122 /* XXX: pch pll's can be enabled any time before we enable the PCH
4123 * transcoder, and we actually should do this to not upset any PCH
4124 * transcoder that already use the clock when we share it.
4126 * Note that enable_shared_dpll tries to do the right thing, but
4127 * get_shared_dpll unconditionally resets the pll - we need that to have
4128 * the right LVDS enable sequence. */
4129 intel_enable_shared_dpll(intel_crtc
);
4131 /* set transcoder timing, panel must allow it */
4132 assert_panel_unlocked(dev_priv
, pipe
);
4133 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4135 intel_fdi_normal_train(crtc
);
4137 /* For PCH DP, enable TRANS_DP_CTL */
4138 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4139 const struct drm_display_mode
*adjusted_mode
=
4140 &intel_crtc
->config
->base
.adjusted_mode
;
4141 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4142 i915_reg_t reg
= TRANS_DP_CTL(pipe
);
4143 temp
= I915_READ(reg
);
4144 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4145 TRANS_DP_SYNC_MASK
|
4147 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4148 temp
|= bpc
<< 9; /* same format but at 11:9 */
4150 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
4151 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4152 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
4153 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4155 switch (intel_trans_dp_port_sel(crtc
)) {
4157 temp
|= TRANS_DP_PORT_SEL_B
;
4160 temp
|= TRANS_DP_PORT_SEL_C
;
4163 temp
|= TRANS_DP_PORT_SEL_D
;
4169 I915_WRITE(reg
, temp
);
4172 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4175 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4177 struct drm_device
*dev
= crtc
->dev
;
4178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4179 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4180 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4182 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4184 lpt_program_iclkip(crtc
);
4186 /* Set transcoder timing. */
4187 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4189 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4192 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4195 i915_reg_t dslreg
= PIPEDSL(pipe
);
4198 temp
= I915_READ(dslreg
);
4200 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4201 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4202 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4207 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
4208 unsigned scaler_user
, int *scaler_id
, unsigned int rotation
,
4209 int src_w
, int src_h
, int dst_w
, int dst_h
)
4211 struct intel_crtc_scaler_state
*scaler_state
=
4212 &crtc_state
->scaler_state
;
4213 struct intel_crtc
*intel_crtc
=
4214 to_intel_crtc(crtc_state
->base
.crtc
);
4217 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4218 (src_h
!= dst_w
|| src_w
!= dst_h
):
4219 (src_w
!= dst_w
|| src_h
!= dst_h
);
4222 * if plane is being disabled or scaler is no more required or force detach
4223 * - free scaler binded to this plane/crtc
4224 * - in order to do this, update crtc->scaler_usage
4226 * Here scaler state in crtc_state is set free so that
4227 * scaler can be assigned to other user. Actual register
4228 * update to free the scaler is done in plane/panel-fit programming.
4229 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4231 if (force_detach
|| !need_scaling
) {
4232 if (*scaler_id
>= 0) {
4233 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
4234 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4236 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4237 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4238 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
4239 scaler_state
->scaler_users
);
4246 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4247 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4249 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4250 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4251 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4252 "size is out of scaler range\n",
4253 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
4257 /* mark this plane as a scaler user in crtc_state */
4258 scaler_state
->scaler_users
|= (1 << scaler_user
);
4259 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4260 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4261 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
4262 scaler_state
->scaler_users
);
4268 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4270 * @state: crtc's scaler state
4273 * 0 - scaler_usage updated successfully
4274 * error - requested scaling cannot be supported or other error condition
4276 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
4278 struct intel_crtc
*intel_crtc
= to_intel_crtc(state
->base
.crtc
);
4279 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
4281 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4282 intel_crtc
->base
.base
.id
, intel_crtc
->base
.name
,
4283 intel_crtc
->pipe
, SKL_CRTC_INDEX
);
4285 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
4286 &state
->scaler_state
.scaler_id
, BIT(DRM_ROTATE_0
),
4287 state
->pipe_src_w
, state
->pipe_src_h
,
4288 adjusted_mode
->crtc_hdisplay
, adjusted_mode
->crtc_vdisplay
);
4292 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4294 * @state: crtc's scaler state
4295 * @plane_state: atomic plane state to update
4298 * 0 - scaler_usage updated successfully
4299 * error - requested scaling cannot be supported or other error condition
4301 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
4302 struct intel_plane_state
*plane_state
)
4305 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4306 struct intel_plane
*intel_plane
=
4307 to_intel_plane(plane_state
->base
.plane
);
4308 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4311 bool force_detach
= !fb
|| !plane_state
->visible
;
4313 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4314 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
4315 intel_crtc
->pipe
, drm_plane_index(&intel_plane
->base
));
4317 ret
= skl_update_scaler(crtc_state
, force_detach
,
4318 drm_plane_index(&intel_plane
->base
),
4319 &plane_state
->scaler_id
,
4320 plane_state
->base
.rotation
,
4321 drm_rect_width(&plane_state
->src
) >> 16,
4322 drm_rect_height(&plane_state
->src
) >> 16,
4323 drm_rect_width(&plane_state
->dst
),
4324 drm_rect_height(&plane_state
->dst
));
4326 if (ret
|| plane_state
->scaler_id
< 0)
4329 /* check colorkey */
4330 if (plane_state
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4331 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4332 intel_plane
->base
.base
.id
,
4333 intel_plane
->base
.name
);
4337 /* Check src format */
4338 switch (fb
->pixel_format
) {
4339 case DRM_FORMAT_RGB565
:
4340 case DRM_FORMAT_XBGR8888
:
4341 case DRM_FORMAT_XRGB8888
:
4342 case DRM_FORMAT_ABGR8888
:
4343 case DRM_FORMAT_ARGB8888
:
4344 case DRM_FORMAT_XRGB2101010
:
4345 case DRM_FORMAT_XBGR2101010
:
4346 case DRM_FORMAT_YUYV
:
4347 case DRM_FORMAT_YVYU
:
4348 case DRM_FORMAT_UYVY
:
4349 case DRM_FORMAT_VYUY
:
4352 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4353 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
4354 fb
->base
.id
, fb
->pixel_format
);
4361 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
4365 for (i
= 0; i
< crtc
->num_scalers
; i
++)
4366 skl_detach_scaler(crtc
, i
);
4369 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4371 struct drm_device
*dev
= crtc
->base
.dev
;
4372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4373 int pipe
= crtc
->pipe
;
4374 struct intel_crtc_scaler_state
*scaler_state
=
4375 &crtc
->config
->scaler_state
;
4377 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4379 if (crtc
->config
->pch_pfit
.enabled
) {
4382 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4383 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4387 id
= scaler_state
->scaler_id
;
4388 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4389 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4390 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4391 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4393 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4397 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4399 struct drm_device
*dev
= crtc
->base
.dev
;
4400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4401 int pipe
= crtc
->pipe
;
4403 if (crtc
->config
->pch_pfit
.enabled
) {
4404 /* Force use of hard-coded filter coefficients
4405 * as some pre-programmed values are broken,
4408 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4409 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4410 PF_PIPE_SEL_IVB(pipe
));
4412 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4413 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4414 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4418 void hsw_enable_ips(struct intel_crtc
*crtc
)
4420 struct drm_device
*dev
= crtc
->base
.dev
;
4421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4423 if (!crtc
->config
->ips_enabled
)
4427 * We can only enable IPS after we enable a plane and wait for a vblank
4428 * This function is called from post_plane_update, which is run after
4432 assert_plane_enabled(dev_priv
, crtc
->plane
);
4433 if (IS_BROADWELL(dev
)) {
4434 mutex_lock(&dev_priv
->rps
.hw_lock
);
4435 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4436 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4437 /* Quoting Art Runyan: "its not safe to expect any particular
4438 * value in IPS_CTL bit 31 after enabling IPS through the
4439 * mailbox." Moreover, the mailbox may return a bogus state,
4440 * so we need to just enable it and continue on.
4443 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4444 /* The bit only becomes 1 in the next vblank, so this wait here
4445 * is essentially intel_wait_for_vblank. If we don't have this
4446 * and don't wait for vblanks until the end of crtc_enable, then
4447 * the HW state readout code will complain that the expected
4448 * IPS_CTL value is not the one we read. */
4449 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4450 DRM_ERROR("Timed out waiting for IPS enable\n");
4454 void hsw_disable_ips(struct intel_crtc
*crtc
)
4456 struct drm_device
*dev
= crtc
->base
.dev
;
4457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4459 if (!crtc
->config
->ips_enabled
)
4462 assert_plane_enabled(dev_priv
, crtc
->plane
);
4463 if (IS_BROADWELL(dev
)) {
4464 mutex_lock(&dev_priv
->rps
.hw_lock
);
4465 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4466 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4467 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4468 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4469 DRM_ERROR("Timed out waiting for IPS disable\n");
4471 I915_WRITE(IPS_CTL
, 0);
4472 POSTING_READ(IPS_CTL
);
4475 /* We need to wait for a vblank before we can disable the plane. */
4476 intel_wait_for_vblank(dev
, crtc
->pipe
);
4479 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4481 if (intel_crtc
->overlay
) {
4482 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4485 mutex_lock(&dev
->struct_mutex
);
4486 dev_priv
->mm
.interruptible
= false;
4487 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4488 dev_priv
->mm
.interruptible
= true;
4489 mutex_unlock(&dev
->struct_mutex
);
4492 /* Let userspace switch the overlay on again. In most cases userspace
4493 * has to recompute where to put it anyway.
4498 * intel_post_enable_primary - Perform operations after enabling primary plane
4499 * @crtc: the CRTC whose primary plane was just enabled
4501 * Performs potentially sleeping operations that must be done after the primary
4502 * plane is enabled, such as updating FBC and IPS. Note that this may be
4503 * called due to an explicit primary plane update, or due to an implicit
4504 * re-enable that is caused when a sprite plane is updated to no longer
4505 * completely hide the primary plane.
4508 intel_post_enable_primary(struct drm_crtc
*crtc
)
4510 struct drm_device
*dev
= crtc
->dev
;
4511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4512 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4513 int pipe
= intel_crtc
->pipe
;
4516 * FIXME IPS should be fine as long as one plane is
4517 * enabled, but in practice it seems to have problems
4518 * when going from primary only to sprite only and vice
4521 hsw_enable_ips(intel_crtc
);
4524 * Gen2 reports pipe underruns whenever all planes are disabled.
4525 * So don't enable underrun reporting before at least some planes
4527 * FIXME: Need to fix the logic to work when we turn off all planes
4528 * but leave the pipe running.
4531 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4533 /* Underruns don't always raise interrupts, so check manually. */
4534 intel_check_cpu_fifo_underruns(dev_priv
);
4535 intel_check_pch_fifo_underruns(dev_priv
);
4538 /* FIXME move all this to pre_plane_update() with proper state tracking */
4540 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4542 struct drm_device
*dev
= crtc
->dev
;
4543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4544 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4545 int pipe
= intel_crtc
->pipe
;
4548 * Gen2 reports pipe underruns whenever all planes are disabled.
4549 * So diasble underrun reporting before all the planes get disabled.
4550 * FIXME: Need to fix the logic to work when we turn off all planes
4551 * but leave the pipe running.
4554 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4557 * FIXME IPS should be fine as long as one plane is
4558 * enabled, but in practice it seems to have problems
4559 * when going from primary only to sprite only and vice
4562 hsw_disable_ips(intel_crtc
);
4565 /* FIXME get rid of this and use pre_plane_update */
4567 intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
)
4569 struct drm_device
*dev
= crtc
->dev
;
4570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4571 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4572 int pipe
= intel_crtc
->pipe
;
4574 intel_pre_disable_primary(crtc
);
4577 * Vblank time updates from the shadow to live plane control register
4578 * are blocked if the memory self-refresh mode is active at that
4579 * moment. So to make sure the plane gets truly disabled, disable
4580 * first the self-refresh mode. The self-refresh enable bit in turn
4581 * will be checked/applied by the HW only at the next frame start
4582 * event which is after the vblank start event, so we need to have a
4583 * wait-for-vblank between disabling the plane and the pipe.
4585 if (HAS_GMCH_DISPLAY(dev
)) {
4586 intel_set_memory_cxsr(dev_priv
, false);
4587 dev_priv
->wm
.vlv
.cxsr
= false;
4588 intel_wait_for_vblank(dev
, pipe
);
4592 static void intel_post_plane_update(struct intel_crtc_state
*old_crtc_state
)
4594 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
4595 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
4596 struct intel_crtc_state
*pipe_config
=
4597 to_intel_crtc_state(crtc
->base
.state
);
4598 struct drm_device
*dev
= crtc
->base
.dev
;
4599 struct drm_plane
*primary
= crtc
->base
.primary
;
4600 struct drm_plane_state
*old_pri_state
=
4601 drm_atomic_get_existing_plane_state(old_state
, primary
);
4603 intel_frontbuffer_flip(dev
, pipe_config
->fb_bits
);
4605 crtc
->wm
.cxsr_allowed
= true;
4607 if (pipe_config
->update_wm_post
&& pipe_config
->base
.active
)
4608 intel_update_watermarks(&crtc
->base
);
4610 if (old_pri_state
) {
4611 struct intel_plane_state
*primary_state
=
4612 to_intel_plane_state(primary
->state
);
4613 struct intel_plane_state
*old_primary_state
=
4614 to_intel_plane_state(old_pri_state
);
4616 intel_fbc_post_update(crtc
);
4618 if (primary_state
->visible
&&
4619 (needs_modeset(&pipe_config
->base
) ||
4620 !old_primary_state
->visible
))
4621 intel_post_enable_primary(&crtc
->base
);
4625 static void intel_pre_plane_update(struct intel_crtc_state
*old_crtc_state
)
4627 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
4628 struct drm_device
*dev
= crtc
->base
.dev
;
4629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4630 struct intel_crtc_state
*pipe_config
=
4631 to_intel_crtc_state(crtc
->base
.state
);
4632 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
4633 struct drm_plane
*primary
= crtc
->base
.primary
;
4634 struct drm_plane_state
*old_pri_state
=
4635 drm_atomic_get_existing_plane_state(old_state
, primary
);
4636 bool modeset
= needs_modeset(&pipe_config
->base
);
4638 if (old_pri_state
) {
4639 struct intel_plane_state
*primary_state
=
4640 to_intel_plane_state(primary
->state
);
4641 struct intel_plane_state
*old_primary_state
=
4642 to_intel_plane_state(old_pri_state
);
4644 intel_fbc_pre_update(crtc
);
4646 if (old_primary_state
->visible
&&
4647 (modeset
|| !primary_state
->visible
))
4648 intel_pre_disable_primary(&crtc
->base
);
4651 if (pipe_config
->disable_cxsr
) {
4652 crtc
->wm
.cxsr_allowed
= false;
4655 * Vblank time updates from the shadow to live plane control register
4656 * are blocked if the memory self-refresh mode is active at that
4657 * moment. So to make sure the plane gets truly disabled, disable
4658 * first the self-refresh mode. The self-refresh enable bit in turn
4659 * will be checked/applied by the HW only at the next frame start
4660 * event which is after the vblank start event, so we need to have a
4661 * wait-for-vblank between disabling the plane and the pipe.
4663 if (old_crtc_state
->base
.active
) {
4664 intel_set_memory_cxsr(dev_priv
, false);
4665 dev_priv
->wm
.vlv
.cxsr
= false;
4666 intel_wait_for_vblank(dev
, crtc
->pipe
);
4671 * IVB workaround: must disable low power watermarks for at least
4672 * one frame before enabling scaling. LP watermarks can be re-enabled
4673 * when scaling is disabled.
4675 * WaCxSRDisabledForSpriteScaling:ivb
4677 if (pipe_config
->disable_lp_wm
) {
4678 ilk_disable_lp_wm(dev
);
4679 intel_wait_for_vblank(dev
, crtc
->pipe
);
4683 * If we're doing a modeset, we're done. No need to do any pre-vblank
4684 * watermark programming here.
4686 if (needs_modeset(&pipe_config
->base
))
4690 * For platforms that support atomic watermarks, program the
4691 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4692 * will be the intermediate values that are safe for both pre- and
4693 * post- vblank; when vblank happens, the 'active' values will be set
4694 * to the final 'target' values and we'll do this again to get the
4695 * optimal watermarks. For gen9+ platforms, the values we program here
4696 * will be the final target values which will get automatically latched
4697 * at vblank time; no further programming will be necessary.
4699 * If a platform hasn't been transitioned to atomic watermarks yet,
4700 * we'll continue to update watermarks the old way, if flags tell
4703 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4704 dev_priv
->display
.initial_watermarks(pipe_config
);
4705 else if (pipe_config
->update_wm_pre
)
4706 intel_update_watermarks(&crtc
->base
);
4709 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
, unsigned plane_mask
)
4711 struct drm_device
*dev
= crtc
->dev
;
4712 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4713 struct drm_plane
*p
;
4714 int pipe
= intel_crtc
->pipe
;
4716 intel_crtc_dpms_overlay_disable(intel_crtc
);
4718 drm_for_each_plane_mask(p
, dev
, plane_mask
)
4719 to_intel_plane(p
)->disable_plane(p
, crtc
);
4722 * FIXME: Once we grow proper nuclear flip support out of this we need
4723 * to compute the mask of flip planes precisely. For the time being
4724 * consider this a flip to a NULL plane.
4726 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4729 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4731 struct drm_device
*dev
= crtc
->dev
;
4732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4733 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4734 struct intel_encoder
*encoder
;
4735 int pipe
= intel_crtc
->pipe
;
4736 struct intel_crtc_state
*pipe_config
=
4737 to_intel_crtc_state(crtc
->state
);
4739 if (WARN_ON(intel_crtc
->active
))
4743 * Sometimes spurious CPU pipe underruns happen during FDI
4744 * training, at least with VGA+HDMI cloning. Suppress them.
4746 * On ILK we get an occasional spurious CPU pipe underruns
4747 * between eDP port A enable and vdd enable. Also PCH port
4748 * enable seems to result in the occasional CPU pipe underrun.
4750 * Spurious PCH underruns also occur during PCH enabling.
4752 if (intel_crtc
->config
->has_pch_encoder
|| IS_GEN5(dev_priv
))
4753 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4754 if (intel_crtc
->config
->has_pch_encoder
)
4755 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4757 if (intel_crtc
->config
->has_pch_encoder
)
4758 intel_prepare_shared_dpll(intel_crtc
);
4760 if (intel_crtc
->config
->has_dp_encoder
)
4761 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4763 intel_set_pipe_timings(intel_crtc
);
4764 intel_set_pipe_src_size(intel_crtc
);
4766 if (intel_crtc
->config
->has_pch_encoder
) {
4767 intel_cpu_transcoder_set_m_n(intel_crtc
,
4768 &intel_crtc
->config
->fdi_m_n
, NULL
);
4771 ironlake_set_pipeconf(crtc
);
4773 intel_crtc
->active
= true;
4775 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4776 if (encoder
->pre_enable
)
4777 encoder
->pre_enable(encoder
);
4779 if (intel_crtc
->config
->has_pch_encoder
) {
4780 /* Note: FDI PLL enabling _must_ be done before we enable the
4781 * cpu pipes, hence this is separate from all the other fdi/pch
4783 ironlake_fdi_pll_enable(intel_crtc
);
4785 assert_fdi_tx_disabled(dev_priv
, pipe
);
4786 assert_fdi_rx_disabled(dev_priv
, pipe
);
4789 ironlake_pfit_enable(intel_crtc
);
4792 * On ILK+ LUT must be loaded before the pipe is running but with
4795 intel_color_load_luts(&pipe_config
->base
);
4797 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4798 dev_priv
->display
.initial_watermarks(intel_crtc
->config
);
4799 intel_enable_pipe(intel_crtc
);
4801 if (intel_crtc
->config
->has_pch_encoder
)
4802 ironlake_pch_enable(crtc
);
4804 assert_vblank_disabled(crtc
);
4805 drm_crtc_vblank_on(crtc
);
4807 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4808 encoder
->enable(encoder
);
4810 if (HAS_PCH_CPT(dev
))
4811 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4813 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4814 if (intel_crtc
->config
->has_pch_encoder
)
4815 intel_wait_for_vblank(dev
, pipe
);
4816 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4817 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4820 /* IPS only exists on ULT machines and is tied to pipe A. */
4821 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4823 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4826 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4828 struct drm_device
*dev
= crtc
->dev
;
4829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4830 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4831 struct intel_encoder
*encoder
;
4832 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
4833 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4834 struct intel_crtc_state
*pipe_config
=
4835 to_intel_crtc_state(crtc
->state
);
4837 if (WARN_ON(intel_crtc
->active
))
4840 if (intel_crtc
->config
->has_pch_encoder
)
4841 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4844 if (intel_crtc
->config
->shared_dpll
)
4845 intel_enable_shared_dpll(intel_crtc
);
4847 if (intel_crtc
->config
->has_dp_encoder
)
4848 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4850 if (!intel_crtc
->config
->has_dsi_encoder
)
4851 intel_set_pipe_timings(intel_crtc
);
4853 intel_set_pipe_src_size(intel_crtc
);
4855 if (cpu_transcoder
!= TRANSCODER_EDP
&&
4856 !transcoder_is_dsi(cpu_transcoder
)) {
4857 I915_WRITE(PIPE_MULT(cpu_transcoder
),
4858 intel_crtc
->config
->pixel_multiplier
- 1);
4861 if (intel_crtc
->config
->has_pch_encoder
) {
4862 intel_cpu_transcoder_set_m_n(intel_crtc
,
4863 &intel_crtc
->config
->fdi_m_n
, NULL
);
4866 if (!intel_crtc
->config
->has_dsi_encoder
)
4867 haswell_set_pipeconf(crtc
);
4869 haswell_set_pipemisc(crtc
);
4871 intel_color_set_csc(&pipe_config
->base
);
4873 intel_crtc
->active
= true;
4875 if (intel_crtc
->config
->has_pch_encoder
)
4876 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4878 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4880 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4881 if (encoder
->pre_enable
)
4882 encoder
->pre_enable(encoder
);
4885 if (intel_crtc
->config
->has_pch_encoder
)
4886 dev_priv
->display
.fdi_link_train(crtc
);
4888 if (!intel_crtc
->config
->has_dsi_encoder
)
4889 intel_ddi_enable_pipe_clock(intel_crtc
);
4891 if (INTEL_INFO(dev
)->gen
>= 9)
4892 skylake_pfit_enable(intel_crtc
);
4894 ironlake_pfit_enable(intel_crtc
);
4897 * On ILK+ LUT must be loaded before the pipe is running but with
4900 intel_color_load_luts(&pipe_config
->base
);
4902 intel_ddi_set_pipe_settings(crtc
);
4903 if (!intel_crtc
->config
->has_dsi_encoder
)
4904 intel_ddi_enable_transcoder_func(crtc
);
4906 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4907 dev_priv
->display
.initial_watermarks(pipe_config
);
4909 intel_update_watermarks(crtc
);
4911 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4912 if (!intel_crtc
->config
->has_dsi_encoder
)
4913 intel_enable_pipe(intel_crtc
);
4915 if (intel_crtc
->config
->has_pch_encoder
)
4916 lpt_pch_enable(crtc
);
4918 if (intel_crtc
->config
->dp_encoder_is_mst
)
4919 intel_ddi_set_vc_payload_alloc(crtc
, true);
4921 assert_vblank_disabled(crtc
);
4922 drm_crtc_vblank_on(crtc
);
4924 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4925 encoder
->enable(encoder
);
4926 intel_opregion_notify_encoder(encoder
, true);
4929 if (intel_crtc
->config
->has_pch_encoder
) {
4930 intel_wait_for_vblank(dev
, pipe
);
4931 intel_wait_for_vblank(dev
, pipe
);
4932 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4933 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4937 /* If we change the relative order between pipe/planes enabling, we need
4938 * to change the workaround. */
4939 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
4940 if (IS_HASWELL(dev
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
4941 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
4942 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
4946 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
)
4948 struct drm_device
*dev
= crtc
->base
.dev
;
4949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4950 int pipe
= crtc
->pipe
;
4952 /* To avoid upsetting the power well on haswell only disable the pfit if
4953 * it's in use. The hw state code will make sure we get this right. */
4954 if (force
|| crtc
->config
->pch_pfit
.enabled
) {
4955 I915_WRITE(PF_CTL(pipe
), 0);
4956 I915_WRITE(PF_WIN_POS(pipe
), 0);
4957 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4961 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4963 struct drm_device
*dev
= crtc
->dev
;
4964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4965 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4966 struct intel_encoder
*encoder
;
4967 int pipe
= intel_crtc
->pipe
;
4970 * Sometimes spurious CPU pipe underruns happen when the
4971 * pipe is already disabled, but FDI RX/TX is still enabled.
4972 * Happens at least with VGA+HDMI cloning. Suppress them.
4974 if (intel_crtc
->config
->has_pch_encoder
) {
4975 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4976 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4979 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4980 encoder
->disable(encoder
);
4982 drm_crtc_vblank_off(crtc
);
4983 assert_vblank_disabled(crtc
);
4985 intel_disable_pipe(intel_crtc
);
4987 ironlake_pfit_disable(intel_crtc
, false);
4989 if (intel_crtc
->config
->has_pch_encoder
)
4990 ironlake_fdi_disable(crtc
);
4992 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4993 if (encoder
->post_disable
)
4994 encoder
->post_disable(encoder
);
4996 if (intel_crtc
->config
->has_pch_encoder
) {
4997 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4999 if (HAS_PCH_CPT(dev
)) {
5003 /* disable TRANS_DP_CTL */
5004 reg
= TRANS_DP_CTL(pipe
);
5005 temp
= I915_READ(reg
);
5006 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5007 TRANS_DP_PORT_SEL_MASK
);
5008 temp
|= TRANS_DP_PORT_SEL_NONE
;
5009 I915_WRITE(reg
, temp
);
5011 /* disable DPLL_SEL */
5012 temp
= I915_READ(PCH_DPLL_SEL
);
5013 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5014 I915_WRITE(PCH_DPLL_SEL
, temp
);
5017 ironlake_fdi_pll_disable(intel_crtc
);
5020 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5021 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5024 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5026 struct drm_device
*dev
= crtc
->dev
;
5027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5028 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5029 struct intel_encoder
*encoder
;
5030 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5032 if (intel_crtc
->config
->has_pch_encoder
)
5033 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5036 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5037 intel_opregion_notify_encoder(encoder
, false);
5038 encoder
->disable(encoder
);
5041 drm_crtc_vblank_off(crtc
);
5042 assert_vblank_disabled(crtc
);
5044 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5045 if (!intel_crtc
->config
->has_dsi_encoder
)
5046 intel_disable_pipe(intel_crtc
);
5048 if (intel_crtc
->config
->dp_encoder_is_mst
)
5049 intel_ddi_set_vc_payload_alloc(crtc
, false);
5051 if (!intel_crtc
->config
->has_dsi_encoder
)
5052 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5054 if (INTEL_INFO(dev
)->gen
>= 9)
5055 skylake_scaler_disable(intel_crtc
);
5057 ironlake_pfit_disable(intel_crtc
, false);
5059 if (!intel_crtc
->config
->has_dsi_encoder
)
5060 intel_ddi_disable_pipe_clock(intel_crtc
);
5062 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5063 if (encoder
->post_disable
)
5064 encoder
->post_disable(encoder
);
5066 if (intel_crtc
->config
->has_pch_encoder
) {
5067 lpt_disable_pch_transcoder(dev_priv
);
5068 lpt_disable_iclkip(dev_priv
);
5069 intel_ddi_fdi_disable(crtc
);
5071 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5076 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5078 struct drm_device
*dev
= crtc
->base
.dev
;
5079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5080 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5082 if (!pipe_config
->gmch_pfit
.control
)
5086 * The panel fitter should only be adjusted whilst the pipe is disabled,
5087 * according to register description and PRM.
5089 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5090 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5092 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5093 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5095 /* Border color in case we don't scale up to the full screen. Black by
5096 * default, change to something else for debugging. */
5097 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5100 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5104 return POWER_DOMAIN_PORT_DDI_A_LANES
;
5106 return POWER_DOMAIN_PORT_DDI_B_LANES
;
5108 return POWER_DOMAIN_PORT_DDI_C_LANES
;
5110 return POWER_DOMAIN_PORT_DDI_D_LANES
;
5112 return POWER_DOMAIN_PORT_DDI_E_LANES
;
5115 return POWER_DOMAIN_PORT_OTHER
;
5119 static enum intel_display_power_domain
port_to_aux_power_domain(enum port port
)
5123 return POWER_DOMAIN_AUX_A
;
5125 return POWER_DOMAIN_AUX_B
;
5127 return POWER_DOMAIN_AUX_C
;
5129 return POWER_DOMAIN_AUX_D
;
5131 /* FIXME: Check VBT for actual wiring of PORT E */
5132 return POWER_DOMAIN_AUX_D
;
5135 return POWER_DOMAIN_AUX_A
;
5139 enum intel_display_power_domain
5140 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5142 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5143 struct intel_digital_port
*intel_dig_port
;
5145 switch (intel_encoder
->type
) {
5146 case INTEL_OUTPUT_UNKNOWN
:
5147 /* Only DDI platforms should ever use this output type */
5148 WARN_ON_ONCE(!HAS_DDI(dev
));
5149 case INTEL_OUTPUT_DISPLAYPORT
:
5150 case INTEL_OUTPUT_HDMI
:
5151 case INTEL_OUTPUT_EDP
:
5152 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5153 return port_to_power_domain(intel_dig_port
->port
);
5154 case INTEL_OUTPUT_DP_MST
:
5155 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5156 return port_to_power_domain(intel_dig_port
->port
);
5157 case INTEL_OUTPUT_ANALOG
:
5158 return POWER_DOMAIN_PORT_CRT
;
5159 case INTEL_OUTPUT_DSI
:
5160 return POWER_DOMAIN_PORT_DSI
;
5162 return POWER_DOMAIN_PORT_OTHER
;
5166 enum intel_display_power_domain
5167 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
)
5169 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5170 struct intel_digital_port
*intel_dig_port
;
5172 switch (intel_encoder
->type
) {
5173 case INTEL_OUTPUT_UNKNOWN
:
5174 case INTEL_OUTPUT_HDMI
:
5176 * Only DDI platforms should ever use these output types.
5177 * We can get here after the HDMI detect code has already set
5178 * the type of the shared encoder. Since we can't be sure
5179 * what's the status of the given connectors, play safe and
5180 * run the DP detection too.
5182 WARN_ON_ONCE(!HAS_DDI(dev
));
5183 case INTEL_OUTPUT_DISPLAYPORT
:
5184 case INTEL_OUTPUT_EDP
:
5185 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5186 return port_to_aux_power_domain(intel_dig_port
->port
);
5187 case INTEL_OUTPUT_DP_MST
:
5188 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5189 return port_to_aux_power_domain(intel_dig_port
->port
);
5191 MISSING_CASE(intel_encoder
->type
);
5192 return POWER_DOMAIN_AUX_A
;
5196 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
,
5197 struct intel_crtc_state
*crtc_state
)
5199 struct drm_device
*dev
= crtc
->dev
;
5200 struct drm_encoder
*encoder
;
5201 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5202 enum pipe pipe
= intel_crtc
->pipe
;
5204 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
5206 if (!crtc_state
->base
.active
)
5209 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5210 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5211 if (crtc_state
->pch_pfit
.enabled
||
5212 crtc_state
->pch_pfit
.force_thru
)
5213 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5215 drm_for_each_encoder_mask(encoder
, dev
, crtc_state
->base
.encoder_mask
) {
5216 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5218 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5221 if (crtc_state
->shared_dpll
)
5222 mask
|= BIT(POWER_DOMAIN_PLLS
);
5227 static unsigned long
5228 modeset_get_crtc_power_domains(struct drm_crtc
*crtc
,
5229 struct intel_crtc_state
*crtc_state
)
5231 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5232 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5233 enum intel_display_power_domain domain
;
5234 unsigned long domains
, new_domains
, old_domains
;
5236 old_domains
= intel_crtc
->enabled_power_domains
;
5237 intel_crtc
->enabled_power_domains
= new_domains
=
5238 get_crtc_power_domains(crtc
, crtc_state
);
5240 domains
= new_domains
& ~old_domains
;
5242 for_each_power_domain(domain
, domains
)
5243 intel_display_power_get(dev_priv
, domain
);
5245 return old_domains
& ~new_domains
;
5248 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
5249 unsigned long domains
)
5251 enum intel_display_power_domain domain
;
5253 for_each_power_domain(domain
, domains
)
5254 intel_display_power_put(dev_priv
, domain
);
5257 static int intel_compute_max_dotclk(struct drm_i915_private
*dev_priv
)
5259 int max_cdclk_freq
= dev_priv
->max_cdclk_freq
;
5261 if (INTEL_INFO(dev_priv
)->gen
>= 9 ||
5262 IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5263 return max_cdclk_freq
;
5264 else if (IS_CHERRYVIEW(dev_priv
))
5265 return max_cdclk_freq
*95/100;
5266 else if (INTEL_INFO(dev_priv
)->gen
< 4)
5267 return 2*max_cdclk_freq
*90/100;
5269 return max_cdclk_freq
*90/100;
5272 static int skl_calc_cdclk(int max_pixclk
, int vco
);
5274 static void intel_update_max_cdclk(struct drm_device
*dev
)
5276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5278 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
5279 u32 limit
= I915_READ(SKL_DFSM
) & SKL_DFSM_CDCLK_LIMIT_MASK
;
5282 vco
= dev_priv
->skl_preferred_vco_freq
;
5283 WARN_ON(vco
!= 8100000 && vco
!= 8640000);
5286 * Use the lower (vco 8640) cdclk values as a
5287 * first guess. skl_calc_cdclk() will correct it
5288 * if the preferred vco is 8100 instead.
5290 if (limit
== SKL_DFSM_CDCLK_LIMIT_675
)
5292 else if (limit
== SKL_DFSM_CDCLK_LIMIT_540
)
5294 else if (limit
== SKL_DFSM_CDCLK_LIMIT_450
)
5299 dev_priv
->max_cdclk_freq
= skl_calc_cdclk(max_cdclk
, vco
);
5300 } else if (IS_BROXTON(dev
)) {
5301 dev_priv
->max_cdclk_freq
= 624000;
5302 } else if (IS_BROADWELL(dev
)) {
5304 * FIXME with extra cooling we can allow
5305 * 540 MHz for ULX and 675 Mhz for ULT.
5306 * How can we know if extra cooling is
5307 * available? PCI ID, VTB, something else?
5309 if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5310 dev_priv
->max_cdclk_freq
= 450000;
5311 else if (IS_BDW_ULX(dev
))
5312 dev_priv
->max_cdclk_freq
= 450000;
5313 else if (IS_BDW_ULT(dev
))
5314 dev_priv
->max_cdclk_freq
= 540000;
5316 dev_priv
->max_cdclk_freq
= 675000;
5317 } else if (IS_CHERRYVIEW(dev
)) {
5318 dev_priv
->max_cdclk_freq
= 320000;
5319 } else if (IS_VALLEYVIEW(dev
)) {
5320 dev_priv
->max_cdclk_freq
= 400000;
5322 /* otherwise assume cdclk is fixed */
5323 dev_priv
->max_cdclk_freq
= dev_priv
->cdclk_freq
;
5326 dev_priv
->max_dotclk_freq
= intel_compute_max_dotclk(dev_priv
);
5328 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5329 dev_priv
->max_cdclk_freq
);
5331 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5332 dev_priv
->max_dotclk_freq
);
5335 static void intel_update_cdclk(struct drm_device
*dev
)
5337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5339 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5341 if (INTEL_GEN(dev_priv
) >= 9)
5342 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5343 dev_priv
->cdclk_freq
, dev_priv
->cdclk_pll
.vco
,
5344 dev_priv
->cdclk_pll
.ref
);
5346 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5347 dev_priv
->cdclk_freq
);
5350 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5351 * Programmng [sic] note: bit[9:2] should be programmed to the number
5352 * of cdclk that generates 4MHz reference clock freq which is used to
5353 * generate GMBus clock. This will vary with the cdclk freq.
5355 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5356 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5359 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5360 static int skl_cdclk_decimal(int cdclk
)
5362 return DIV_ROUND_CLOSEST(cdclk
- 1000, 500);
5365 static int bxt_de_pll_vco(struct drm_i915_private
*dev_priv
, int cdclk
)
5369 if (cdclk
== dev_priv
->cdclk_pll
.ref
)
5374 MISSING_CASE(cdclk
);
5386 return dev_priv
->cdclk_pll
.ref
* ratio
;
5389 static void bxt_de_pll_disable(struct drm_i915_private
*dev_priv
)
5391 I915_WRITE(BXT_DE_PLL_ENABLE
, 0);
5394 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
) == 0, 1))
5395 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5397 dev_priv
->cdclk_pll
.vco
= 0;
5400 static void bxt_de_pll_enable(struct drm_i915_private
*dev_priv
, int vco
)
5402 int ratio
= DIV_ROUND_CLOSEST(vco
, dev_priv
->cdclk_pll
.ref
);
5405 val
= I915_READ(BXT_DE_PLL_CTL
);
5406 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5407 val
|= BXT_DE_PLL_RATIO(ratio
);
5408 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5410 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5413 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
) != 0, 1))
5414 DRM_ERROR("timeout waiting for DE PLL lock\n");
5416 dev_priv
->cdclk_pll
.vco
= vco
;
5419 static void broxton_set_cdclk(struct drm_i915_private
*dev_priv
, int cdclk
)
5424 vco
= bxt_de_pll_vco(dev_priv
, cdclk
);
5426 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk
, vco
);
5428 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5429 switch (DIV_ROUND_CLOSEST(vco
, cdclk
)) {
5431 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5434 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5437 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5440 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5443 WARN_ON(cdclk
!= dev_priv
->cdclk_pll
.ref
);
5446 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5450 /* Inform power controller of upcoming frequency change */
5451 mutex_lock(&dev_priv
->rps
.hw_lock
);
5452 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5454 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5457 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5462 if (dev_priv
->cdclk_pll
.vco
!= 0 &&
5463 dev_priv
->cdclk_pll
.vco
!= vco
)
5464 bxt_de_pll_disable(dev_priv
);
5466 if (dev_priv
->cdclk_pll
.vco
!= vco
)
5467 bxt_de_pll_enable(dev_priv
, vco
);
5469 val
= divider
| skl_cdclk_decimal(cdclk
);
5471 * FIXME if only the cd2x divider needs changing, it could be done
5472 * without shutting off the pipe (if only one pipe is active).
5474 val
|= BXT_CDCLK_CD2X_PIPE_NONE
;
5476 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5479 if (cdclk
>= 500000)
5480 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5481 I915_WRITE(CDCLK_CTL
, val
);
5483 mutex_lock(&dev_priv
->rps
.hw_lock
);
5484 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5485 DIV_ROUND_UP(cdclk
, 25000));
5486 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5489 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5494 intel_update_cdclk(dev_priv
->dev
);
5497 static void bxt_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
5499 u32 cdctl
, expected
;
5501 intel_update_cdclk(dev_priv
->dev
);
5503 if (dev_priv
->cdclk_pll
.vco
== 0 ||
5504 dev_priv
->cdclk_freq
== dev_priv
->cdclk_pll
.ref
)
5507 /* DPLL okay; verify the cdclock
5509 * Some BIOS versions leave an incorrect decimal frequency value and
5510 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5511 * so sanitize this register.
5513 cdctl
= I915_READ(CDCLK_CTL
);
5515 * Let's ignore the pipe field, since BIOS could have configured the
5516 * dividers both synching to an active pipe, or asynchronously
5519 cdctl
&= ~BXT_CDCLK_CD2X_PIPE_NONE
;
5521 expected
= (cdctl
& BXT_CDCLK_CD2X_DIV_SEL_MASK
) |
5522 skl_cdclk_decimal(dev_priv
->cdclk_freq
);
5524 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5527 if (dev_priv
->cdclk_freq
>= 500000)
5528 expected
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5530 if (cdctl
== expected
)
5531 /* All well; nothing to sanitize */
5535 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5537 /* force cdclk programming */
5538 dev_priv
->cdclk_freq
= 0;
5540 /* force full PLL disable + enable */
5541 dev_priv
->cdclk_pll
.vco
= -1;
5544 void broxton_init_cdclk(struct drm_i915_private
*dev_priv
)
5546 bxt_sanitize_cdclk(dev_priv
);
5548 if (dev_priv
->cdclk_freq
!= 0 && dev_priv
->cdclk_pll
.vco
!= 0)
5553 * - The initial CDCLK needs to be read from VBT.
5554 * Need to make this change after VBT has changes for BXT.
5556 broxton_set_cdclk(dev_priv
, broxton_calc_cdclk(0));
5559 void broxton_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5561 broxton_set_cdclk(dev_priv
, dev_priv
->cdclk_pll
.ref
);
5564 static int skl_calc_cdclk(int max_pixclk
, int vco
)
5566 if (vco
== 8640000) {
5567 if (max_pixclk
> 540000)
5569 else if (max_pixclk
> 432000)
5571 else if (max_pixclk
> 308571)
5576 if (max_pixclk
> 540000)
5578 else if (max_pixclk
> 450000)
5580 else if (max_pixclk
> 337500)
5588 skl_dpll0_update(struct drm_i915_private
*dev_priv
)
5592 dev_priv
->cdclk_pll
.ref
= 24000;
5593 dev_priv
->cdclk_pll
.vco
= 0;
5595 val
= I915_READ(LCPLL1_CTL
);
5596 if ((val
& LCPLL_PLL_ENABLE
) == 0)
5599 if (WARN_ON((val
& LCPLL_PLL_LOCK
) == 0))
5602 val
= I915_READ(DPLL_CTRL1
);
5604 if (WARN_ON((val
& (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) |
5605 DPLL_CTRL1_SSC(SKL_DPLL0
) |
5606 DPLL_CTRL1_OVERRIDE(SKL_DPLL0
))) !=
5607 DPLL_CTRL1_OVERRIDE(SKL_DPLL0
)))
5610 switch (val
& DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) {
5611 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
, SKL_DPLL0
):
5612 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
, SKL_DPLL0
):
5613 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
, SKL_DPLL0
):
5614 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
, SKL_DPLL0
):
5615 dev_priv
->cdclk_pll
.vco
= 8100000;
5617 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
, SKL_DPLL0
):
5618 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
, SKL_DPLL0
):
5619 dev_priv
->cdclk_pll
.vco
= 8640000;
5622 MISSING_CASE(val
& DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5627 void skl_set_preferred_cdclk_vco(struct drm_i915_private
*dev_priv
, int vco
)
5629 bool changed
= dev_priv
->skl_preferred_vco_freq
!= vco
;
5631 dev_priv
->skl_preferred_vco_freq
= vco
;
5634 intel_update_max_cdclk(dev_priv
->dev
);
5638 skl_dpll0_enable(struct drm_i915_private
*dev_priv
, int vco
)
5640 int min_cdclk
= skl_calc_cdclk(0, vco
);
5643 WARN_ON(vco
!= 8100000 && vco
!= 8640000);
5645 /* select the minimum CDCLK before enabling DPLL 0 */
5646 val
= CDCLK_FREQ_337_308
| skl_cdclk_decimal(min_cdclk
);
5647 I915_WRITE(CDCLK_CTL
, val
);
5648 POSTING_READ(CDCLK_CTL
);
5651 * We always enable DPLL0 with the lowest link rate possible, but still
5652 * taking into account the VCO required to operate the eDP panel at the
5653 * desired frequency. The usual DP link rates operate with a VCO of
5654 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5655 * The modeset code is responsible for the selection of the exact link
5656 * rate later on, with the constraint of choosing a frequency that
5659 val
= I915_READ(DPLL_CTRL1
);
5661 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
5662 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5663 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
5665 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
5668 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
5671 I915_WRITE(DPLL_CTRL1
, val
);
5672 POSTING_READ(DPLL_CTRL1
);
5674 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
5676 if (wait_for(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
, 5))
5677 DRM_ERROR("DPLL0 not locked\n");
5679 dev_priv
->cdclk_pll
.vco
= vco
;
5681 /* We'll want to keep using the current vco from now on. */
5682 skl_set_preferred_cdclk_vco(dev_priv
, vco
);
5686 skl_dpll0_disable(struct drm_i915_private
*dev_priv
)
5688 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) & ~LCPLL_PLL_ENABLE
);
5689 if (wait_for(!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
), 1))
5690 DRM_ERROR("Couldn't disable DPLL0\n");
5692 dev_priv
->cdclk_pll
.vco
= 0;
5695 static bool skl_cdclk_pcu_ready(struct drm_i915_private
*dev_priv
)
5700 /* inform PCU we want to change CDCLK */
5701 val
= SKL_CDCLK_PREPARE_FOR_CHANGE
;
5702 mutex_lock(&dev_priv
->rps
.hw_lock
);
5703 ret
= sandybridge_pcode_read(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, &val
);
5704 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5706 return ret
== 0 && (val
& SKL_CDCLK_READY_FOR_CHANGE
);
5709 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private
*dev_priv
)
5713 for (i
= 0; i
< 15; i
++) {
5714 if (skl_cdclk_pcu_ready(dev_priv
))
5722 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
, int cdclk
, int vco
)
5724 struct drm_device
*dev
= dev_priv
->dev
;
5725 u32 freq_select
, pcu_ack
;
5727 WARN_ON((cdclk
== 24000) != (vco
== 0));
5729 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk
, vco
);
5731 if (!skl_cdclk_wait_for_pcu_ready(dev_priv
)) {
5732 DRM_ERROR("failed to inform PCU about cdclk change\n");
5740 freq_select
= CDCLK_FREQ_450_432
;
5744 freq_select
= CDCLK_FREQ_540
;
5750 freq_select
= CDCLK_FREQ_337_308
;
5755 freq_select
= CDCLK_FREQ_675_617
;
5760 if (dev_priv
->cdclk_pll
.vco
!= 0 &&
5761 dev_priv
->cdclk_pll
.vco
!= vco
)
5762 skl_dpll0_disable(dev_priv
);
5764 if (dev_priv
->cdclk_pll
.vco
!= vco
)
5765 skl_dpll0_enable(dev_priv
, vco
);
5767 I915_WRITE(CDCLK_CTL
, freq_select
| skl_cdclk_decimal(cdclk
));
5768 POSTING_READ(CDCLK_CTL
);
5770 /* inform PCU of the change */
5771 mutex_lock(&dev_priv
->rps
.hw_lock
);
5772 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
5773 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5775 intel_update_cdclk(dev
);
5778 static void skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
);
5780 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5782 skl_set_cdclk(dev_priv
, dev_priv
->cdclk_pll
.ref
, 0);
5785 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
5789 skl_sanitize_cdclk(dev_priv
);
5791 if (dev_priv
->cdclk_freq
!= 0 && dev_priv
->cdclk_pll
.vco
!= 0) {
5793 * Use the current vco as our initial
5794 * guess as to what the preferred vco is.
5796 if (dev_priv
->skl_preferred_vco_freq
== 0)
5797 skl_set_preferred_cdclk_vco(dev_priv
,
5798 dev_priv
->cdclk_pll
.vco
);
5802 vco
= dev_priv
->skl_preferred_vco_freq
;
5805 cdclk
= skl_calc_cdclk(0, vco
);
5807 skl_set_cdclk(dev_priv
, cdclk
, vco
);
5810 static void skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
5812 uint32_t cdctl
, expected
;
5815 * check if the pre-os intialized the display
5816 * There is SWF18 scratchpad register defined which is set by the
5817 * pre-os which can be used by the OS drivers to check the status
5819 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5822 intel_update_cdclk(dev_priv
->dev
);
5823 /* Is PLL enabled and locked ? */
5824 if (dev_priv
->cdclk_pll
.vco
== 0 ||
5825 dev_priv
->cdclk_freq
== dev_priv
->cdclk_pll
.ref
)
5828 /* DPLL okay; verify the cdclock
5830 * Noticed in some instances that the freq selection is correct but
5831 * decimal part is programmed wrong from BIOS where pre-os does not
5832 * enable display. Verify the same as well.
5834 cdctl
= I915_READ(CDCLK_CTL
);
5835 expected
= (cdctl
& CDCLK_FREQ_SEL_MASK
) |
5836 skl_cdclk_decimal(dev_priv
->cdclk_freq
);
5837 if (cdctl
== expected
)
5838 /* All well; nothing to sanitize */
5842 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5844 /* force cdclk programming */
5845 dev_priv
->cdclk_freq
= 0;
5846 /* force full PLL disable + enable */
5847 dev_priv
->cdclk_pll
.vco
= -1;
5850 /* Adjust CDclk dividers to allow high res or save power if possible */
5851 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5856 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5857 != dev_priv
->cdclk_freq
);
5859 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5861 else if (cdclk
== 266667)
5866 mutex_lock(&dev_priv
->rps
.hw_lock
);
5867 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5868 val
&= ~DSPFREQGUAR_MASK
;
5869 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5870 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5871 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5872 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5874 DRM_ERROR("timed out waiting for CDclk change\n");
5876 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5878 mutex_lock(&dev_priv
->sb_lock
);
5880 if (cdclk
== 400000) {
5883 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5885 /* adjust cdclk divider */
5886 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5887 val
&= ~CCK_FREQUENCY_VALUES
;
5889 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5891 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5892 CCK_FREQUENCY_STATUS
) == (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
5894 DRM_ERROR("timed out waiting for CDclk change\n");
5897 /* adjust self-refresh exit latency value */
5898 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5902 * For high bandwidth configs, we set a higher latency in the bunit
5903 * so that the core display fetch happens in time to avoid underruns.
5905 if (cdclk
== 400000)
5906 val
|= 4500 / 250; /* 4.5 usec */
5908 val
|= 3000 / 250; /* 3.0 usec */
5909 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5911 mutex_unlock(&dev_priv
->sb_lock
);
5913 intel_update_cdclk(dev
);
5916 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5921 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5922 != dev_priv
->cdclk_freq
);
5931 MISSING_CASE(cdclk
);
5936 * Specs are full of misinformation, but testing on actual
5937 * hardware has shown that we just need to write the desired
5938 * CCK divider into the Punit register.
5940 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5942 mutex_lock(&dev_priv
->rps
.hw_lock
);
5943 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5944 val
&= ~DSPFREQGUAR_MASK_CHV
;
5945 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5946 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5947 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5948 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5950 DRM_ERROR("timed out waiting for CDclk change\n");
5952 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5954 intel_update_cdclk(dev
);
5957 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5960 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5961 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5964 * Really only a few cases to deal with, as only 4 CDclks are supported:
5967 * 320/333MHz (depends on HPLL freq)
5969 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5970 * of the lower bin and adjust if needed.
5972 * We seem to get an unstable or solid color picture at 200MHz.
5973 * Not sure what's wrong. For now use 200MHz only when all pipes
5976 if (!IS_CHERRYVIEW(dev_priv
) &&
5977 max_pixclk
> freq_320
*limit
/100)
5979 else if (max_pixclk
> 266667*limit
/100)
5981 else if (max_pixclk
> 0)
5987 static int broxton_calc_cdclk(int max_pixclk
)
5989 if (max_pixclk
> 576000)
5991 else if (max_pixclk
> 384000)
5993 else if (max_pixclk
> 288000)
5995 else if (max_pixclk
> 144000)
6001 /* Compute the max pixel clock for new configuration. */
6002 static int intel_mode_max_pixclk(struct drm_device
*dev
,
6003 struct drm_atomic_state
*state
)
6005 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
6006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6007 struct drm_crtc
*crtc
;
6008 struct drm_crtc_state
*crtc_state
;
6009 unsigned max_pixclk
= 0, i
;
6012 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
6013 sizeof(intel_state
->min_pixclk
));
6015 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
6018 if (crtc_state
->enable
)
6019 pixclk
= crtc_state
->adjusted_mode
.crtc_clock
;
6021 intel_state
->min_pixclk
[i
] = pixclk
;
6024 for_each_pipe(dev_priv
, pipe
)
6025 max_pixclk
= max(intel_state
->min_pixclk
[pipe
], max_pixclk
);
6030 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state
*state
)
6032 struct drm_device
*dev
= state
->dev
;
6033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6034 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
6035 struct intel_atomic_state
*intel_state
=
6036 to_intel_atomic_state(state
);
6038 intel_state
->cdclk
= intel_state
->dev_cdclk
=
6039 valleyview_calc_cdclk(dev_priv
, max_pixclk
);
6041 if (!intel_state
->active_crtcs
)
6042 intel_state
->dev_cdclk
= valleyview_calc_cdclk(dev_priv
, 0);
6047 static int broxton_modeset_calc_cdclk(struct drm_atomic_state
*state
)
6049 int max_pixclk
= ilk_max_pixel_rate(state
);
6050 struct intel_atomic_state
*intel_state
=
6051 to_intel_atomic_state(state
);
6053 intel_state
->cdclk
= intel_state
->dev_cdclk
=
6054 broxton_calc_cdclk(max_pixclk
);
6056 if (!intel_state
->active_crtcs
)
6057 intel_state
->dev_cdclk
= broxton_calc_cdclk(0);
6062 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
6064 unsigned int credits
, default_credits
;
6066 if (IS_CHERRYVIEW(dev_priv
))
6067 default_credits
= PFI_CREDIT(12);
6069 default_credits
= PFI_CREDIT(8);
6071 if (dev_priv
->cdclk_freq
>= dev_priv
->czclk_freq
) {
6072 /* CHV suggested value is 31 or 63 */
6073 if (IS_CHERRYVIEW(dev_priv
))
6074 credits
= PFI_CREDIT_63
;
6076 credits
= PFI_CREDIT(15);
6078 credits
= default_credits
;
6082 * WA - write default credits before re-programming
6083 * FIXME: should we also set the resend bit here?
6085 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6088 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6089 credits
| PFI_CREDIT_RESEND
);
6092 * FIXME is this guaranteed to clear
6093 * immediately or should we poll for it?
6095 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
6098 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
6100 struct drm_device
*dev
= old_state
->dev
;
6101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6102 struct intel_atomic_state
*old_intel_state
=
6103 to_intel_atomic_state(old_state
);
6104 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
6107 * FIXME: We can end up here with all power domains off, yet
6108 * with a CDCLK frequency other than the minimum. To account
6109 * for this take the PIPE-A power domain, which covers the HW
6110 * blocks needed for the following programming. This can be
6111 * removed once it's guaranteed that we get here either with
6112 * the minimum CDCLK set, or the required power domains
6115 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
6117 if (IS_CHERRYVIEW(dev
))
6118 cherryview_set_cdclk(dev
, req_cdclk
);
6120 valleyview_set_cdclk(dev
, req_cdclk
);
6122 vlv_program_pfi_credits(dev_priv
);
6124 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
6127 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
6129 struct drm_device
*dev
= crtc
->dev
;
6130 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6131 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6132 struct intel_encoder
*encoder
;
6133 struct intel_crtc_state
*pipe_config
=
6134 to_intel_crtc_state(crtc
->state
);
6135 int pipe
= intel_crtc
->pipe
;
6137 if (WARN_ON(intel_crtc
->active
))
6140 if (intel_crtc
->config
->has_dp_encoder
)
6141 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6143 intel_set_pipe_timings(intel_crtc
);
6144 intel_set_pipe_src_size(intel_crtc
);
6146 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
6147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6149 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6150 I915_WRITE(CHV_CANVAS(pipe
), 0);
6153 i9xx_set_pipeconf(intel_crtc
);
6155 intel_crtc
->active
= true;
6157 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6159 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6160 if (encoder
->pre_pll_enable
)
6161 encoder
->pre_pll_enable(encoder
);
6163 if (IS_CHERRYVIEW(dev
)) {
6164 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6165 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
6167 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6168 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
6171 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6172 if (encoder
->pre_enable
)
6173 encoder
->pre_enable(encoder
);
6175 i9xx_pfit_enable(intel_crtc
);
6177 intel_color_load_luts(&pipe_config
->base
);
6179 intel_update_watermarks(crtc
);
6180 intel_enable_pipe(intel_crtc
);
6182 assert_vblank_disabled(crtc
);
6183 drm_crtc_vblank_on(crtc
);
6185 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6186 encoder
->enable(encoder
);
6189 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
6191 struct drm_device
*dev
= crtc
->base
.dev
;
6192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6194 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
6195 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
6198 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
6200 struct drm_device
*dev
= crtc
->dev
;
6201 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6202 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6203 struct intel_encoder
*encoder
;
6204 struct intel_crtc_state
*pipe_config
=
6205 to_intel_crtc_state(crtc
->state
);
6206 enum pipe pipe
= intel_crtc
->pipe
;
6208 if (WARN_ON(intel_crtc
->active
))
6211 i9xx_set_pll_dividers(intel_crtc
);
6213 if (intel_crtc
->config
->has_dp_encoder
)
6214 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6216 intel_set_pipe_timings(intel_crtc
);
6217 intel_set_pipe_src_size(intel_crtc
);
6219 i9xx_set_pipeconf(intel_crtc
);
6221 intel_crtc
->active
= true;
6224 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6226 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6227 if (encoder
->pre_enable
)
6228 encoder
->pre_enable(encoder
);
6230 i9xx_enable_pll(intel_crtc
);
6232 i9xx_pfit_enable(intel_crtc
);
6234 intel_color_load_luts(&pipe_config
->base
);
6236 intel_update_watermarks(crtc
);
6237 intel_enable_pipe(intel_crtc
);
6239 assert_vblank_disabled(crtc
);
6240 drm_crtc_vblank_on(crtc
);
6242 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6243 encoder
->enable(encoder
);
6246 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6248 struct drm_device
*dev
= crtc
->base
.dev
;
6249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6251 if (!crtc
->config
->gmch_pfit
.control
)
6254 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6256 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6257 I915_READ(PFIT_CONTROL
));
6258 I915_WRITE(PFIT_CONTROL
, 0);
6261 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6263 struct drm_device
*dev
= crtc
->dev
;
6264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6265 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6266 struct intel_encoder
*encoder
;
6267 int pipe
= intel_crtc
->pipe
;
6270 * On gen2 planes are double buffered but the pipe isn't, so we must
6271 * wait for planes to fully turn off before disabling the pipe.
6274 intel_wait_for_vblank(dev
, pipe
);
6276 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6277 encoder
->disable(encoder
);
6279 drm_crtc_vblank_off(crtc
);
6280 assert_vblank_disabled(crtc
);
6282 intel_disable_pipe(intel_crtc
);
6284 i9xx_pfit_disable(intel_crtc
);
6286 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6287 if (encoder
->post_disable
)
6288 encoder
->post_disable(encoder
);
6290 if (!intel_crtc
->config
->has_dsi_encoder
) {
6291 if (IS_CHERRYVIEW(dev
))
6292 chv_disable_pll(dev_priv
, pipe
);
6293 else if (IS_VALLEYVIEW(dev
))
6294 vlv_disable_pll(dev_priv
, pipe
);
6296 i9xx_disable_pll(intel_crtc
);
6299 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6300 if (encoder
->post_pll_disable
)
6301 encoder
->post_pll_disable(encoder
);
6304 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6307 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
)
6309 struct intel_encoder
*encoder
;
6310 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6311 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6312 enum intel_display_power_domain domain
;
6313 unsigned long domains
;
6315 if (!intel_crtc
->active
)
6318 if (to_intel_plane_state(crtc
->primary
->state
)->visible
) {
6319 WARN_ON(intel_crtc
->flip_work
);
6321 intel_pre_disable_primary_noatomic(crtc
);
6323 intel_crtc_disable_planes(crtc
, 1 << drm_plane_index(crtc
->primary
));
6324 to_intel_plane_state(crtc
->primary
->state
)->visible
= false;
6327 dev_priv
->display
.crtc_disable(crtc
);
6329 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6330 crtc
->base
.id
, crtc
->name
);
6332 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->state
, NULL
) < 0);
6333 crtc
->state
->active
= false;
6334 intel_crtc
->active
= false;
6335 crtc
->enabled
= false;
6336 crtc
->state
->connector_mask
= 0;
6337 crtc
->state
->encoder_mask
= 0;
6339 for_each_encoder_on_crtc(crtc
->dev
, crtc
, encoder
)
6340 encoder
->base
.crtc
= NULL
;
6342 intel_fbc_disable(intel_crtc
);
6343 intel_update_watermarks(crtc
);
6344 intel_disable_shared_dpll(intel_crtc
);
6346 domains
= intel_crtc
->enabled_power_domains
;
6347 for_each_power_domain(domain
, domains
)
6348 intel_display_power_put(dev_priv
, domain
);
6349 intel_crtc
->enabled_power_domains
= 0;
6351 dev_priv
->active_crtcs
&= ~(1 << intel_crtc
->pipe
);
6352 dev_priv
->min_pixclk
[intel_crtc
->pipe
] = 0;
6356 * turn all crtc's off, but do not adjust state
6357 * This has to be paired with a call to intel_modeset_setup_hw_state.
6359 int intel_display_suspend(struct drm_device
*dev
)
6361 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6362 struct drm_atomic_state
*state
;
6365 state
= drm_atomic_helper_suspend(dev
);
6366 ret
= PTR_ERR_OR_ZERO(state
);
6368 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6370 dev_priv
->modeset_restore_state
= state
;
6374 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6376 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6378 drm_encoder_cleanup(encoder
);
6379 kfree(intel_encoder
);
6382 /* Cross check the actual hw state with our own modeset state tracking (and it's
6383 * internal consistency). */
6384 static void intel_connector_verify_state(struct intel_connector
*connector
)
6386 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
6388 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6389 connector
->base
.base
.id
,
6390 connector
->base
.name
);
6392 if (connector
->get_hw_state(connector
)) {
6393 struct intel_encoder
*encoder
= connector
->encoder
;
6394 struct drm_connector_state
*conn_state
= connector
->base
.state
;
6396 I915_STATE_WARN(!crtc
,
6397 "connector enabled without attached crtc\n");
6402 I915_STATE_WARN(!crtc
->state
->active
,
6403 "connector is active, but attached crtc isn't\n");
6405 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
6408 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
6409 "atomic encoder doesn't match attached encoder\n");
6411 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
6412 "attached encoder crtc differs from connector crtc\n");
6414 I915_STATE_WARN(crtc
&& crtc
->state
->active
,
6415 "attached crtc is active, but connector isn't\n");
6416 I915_STATE_WARN(!crtc
&& connector
->base
.state
->best_encoder
,
6417 "best encoder set without crtc!\n");
6421 int intel_connector_init(struct intel_connector
*connector
)
6423 drm_atomic_helper_connector_reset(&connector
->base
);
6425 if (!connector
->base
.state
)
6431 struct intel_connector
*intel_connector_alloc(void)
6433 struct intel_connector
*connector
;
6435 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6439 if (intel_connector_init(connector
) < 0) {
6447 /* Simple connector->get_hw_state implementation for encoders that support only
6448 * one connector and no cloning and hence the encoder state determines the state
6449 * of the connector. */
6450 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6453 struct intel_encoder
*encoder
= connector
->encoder
;
6455 return encoder
->get_hw_state(encoder
, &pipe
);
6458 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6460 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6461 return crtc_state
->fdi_lanes
;
6466 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6467 struct intel_crtc_state
*pipe_config
)
6469 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6470 struct intel_crtc
*other_crtc
;
6471 struct intel_crtc_state
*other_crtc_state
;
6473 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6474 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6475 if (pipe_config
->fdi_lanes
> 4) {
6476 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6477 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6481 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6482 if (pipe_config
->fdi_lanes
> 2) {
6483 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6484 pipe_config
->fdi_lanes
);
6491 if (INTEL_INFO(dev
)->num_pipes
== 2)
6494 /* Ivybridge 3 pipe is really complicated */
6499 if (pipe_config
->fdi_lanes
<= 2)
6502 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6504 intel_atomic_get_crtc_state(state
, other_crtc
);
6505 if (IS_ERR(other_crtc_state
))
6506 return PTR_ERR(other_crtc_state
);
6508 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6509 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6510 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6515 if (pipe_config
->fdi_lanes
> 2) {
6516 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6517 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6521 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6523 intel_atomic_get_crtc_state(state
, other_crtc
);
6524 if (IS_ERR(other_crtc_state
))
6525 return PTR_ERR(other_crtc_state
);
6527 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6528 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6538 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6539 struct intel_crtc_state
*pipe_config
)
6541 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6542 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6543 int lane
, link_bw
, fdi_dotclock
, ret
;
6544 bool needs_recompute
= false;
6547 /* FDI is a binary signal running at ~2.7GHz, encoding
6548 * each output octet as 10 bits. The actual frequency
6549 * is stored as a divider into a 100MHz clock, and the
6550 * mode pixel clock is stored in units of 1KHz.
6551 * Hence the bw of each lane in terms of the mode signal
6554 link_bw
= intel_fdi_link_freq(to_i915(dev
), pipe_config
);
6556 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6558 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6559 pipe_config
->pipe_bpp
);
6561 pipe_config
->fdi_lanes
= lane
;
6563 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6564 link_bw
, &pipe_config
->fdi_m_n
);
6566 ret
= ironlake_check_fdi_lanes(dev
, intel_crtc
->pipe
, pipe_config
);
6567 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6568 pipe_config
->pipe_bpp
-= 2*3;
6569 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6570 pipe_config
->pipe_bpp
);
6571 needs_recompute
= true;
6572 pipe_config
->bw_constrained
= true;
6577 if (needs_recompute
)
6583 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
6584 struct intel_crtc_state
*pipe_config
)
6586 if (pipe_config
->pipe_bpp
> 24)
6589 /* HSW can handle pixel rate up to cdclk? */
6590 if (IS_HASWELL(dev_priv
))
6594 * We compare against max which means we must take
6595 * the increased cdclk requirement into account when
6596 * calculating the new cdclk.
6598 * Should measure whether using a lower cdclk w/o IPS
6600 return ilk_pipe_pixel_rate(pipe_config
) <=
6601 dev_priv
->max_cdclk_freq
* 95 / 100;
6604 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6605 struct intel_crtc_state
*pipe_config
)
6607 struct drm_device
*dev
= crtc
->base
.dev
;
6608 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6610 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6611 hsw_crtc_supports_ips(crtc
) &&
6612 pipe_config_supports_ips(dev_priv
, pipe_config
);
6615 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
6617 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6619 /* GDG double wide on either pipe, otherwise pipe A only */
6620 return INTEL_INFO(dev_priv
)->gen
< 4 &&
6621 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
6624 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6625 struct intel_crtc_state
*pipe_config
)
6627 struct drm_device
*dev
= crtc
->base
.dev
;
6628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6629 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6630 int clock_limit
= dev_priv
->max_dotclk_freq
;
6632 if (INTEL_INFO(dev
)->gen
< 4) {
6633 clock_limit
= dev_priv
->max_cdclk_freq
* 9 / 10;
6636 * Enable double wide mode when the dot clock
6637 * is > 90% of the (display) core speed.
6639 if (intel_crtc_supports_double_wide(crtc
) &&
6640 adjusted_mode
->crtc_clock
> clock_limit
) {
6641 clock_limit
= dev_priv
->max_dotclk_freq
;
6642 pipe_config
->double_wide
= true;
6646 if (adjusted_mode
->crtc_clock
> clock_limit
) {
6647 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6648 adjusted_mode
->crtc_clock
, clock_limit
,
6649 yesno(pipe_config
->double_wide
));
6654 * Pipe horizontal size must be even in:
6656 * - LVDS dual channel mode
6657 * - Double wide pipe
6659 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6660 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6661 pipe_config
->pipe_src_w
&= ~1;
6663 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6664 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6666 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6667 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
6671 hsw_compute_ips_config(crtc
, pipe_config
);
6673 if (pipe_config
->has_pch_encoder
)
6674 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6679 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6681 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6684 skl_dpll0_update(dev_priv
);
6686 if (dev_priv
->cdclk_pll
.vco
== 0)
6687 return dev_priv
->cdclk_pll
.ref
;
6689 cdctl
= I915_READ(CDCLK_CTL
);
6691 if (dev_priv
->cdclk_pll
.vco
== 8640000) {
6692 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6693 case CDCLK_FREQ_450_432
:
6695 case CDCLK_FREQ_337_308
:
6697 case CDCLK_FREQ_540
:
6699 case CDCLK_FREQ_675_617
:
6702 MISSING_CASE(cdctl
& CDCLK_FREQ_SEL_MASK
);
6705 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6706 case CDCLK_FREQ_450_432
:
6708 case CDCLK_FREQ_337_308
:
6710 case CDCLK_FREQ_540
:
6712 case CDCLK_FREQ_675_617
:
6715 MISSING_CASE(cdctl
& CDCLK_FREQ_SEL_MASK
);
6719 return dev_priv
->cdclk_pll
.ref
;
6722 static void bxt_de_pll_update(struct drm_i915_private
*dev_priv
)
6726 dev_priv
->cdclk_pll
.ref
= 19200;
6727 dev_priv
->cdclk_pll
.vco
= 0;
6729 val
= I915_READ(BXT_DE_PLL_ENABLE
);
6730 if ((val
& BXT_DE_PLL_PLL_ENABLE
) == 0)
6733 if (WARN_ON((val
& BXT_DE_PLL_LOCK
) == 0))
6736 val
= I915_READ(BXT_DE_PLL_CTL
);
6737 dev_priv
->cdclk_pll
.vco
= (val
& BXT_DE_PLL_RATIO_MASK
) *
6738 dev_priv
->cdclk_pll
.ref
;
6741 static int broxton_get_display_clock_speed(struct drm_device
*dev
)
6743 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6747 bxt_de_pll_update(dev_priv
);
6749 vco
= dev_priv
->cdclk_pll
.vco
;
6751 return dev_priv
->cdclk_pll
.ref
;
6753 divider
= I915_READ(CDCLK_CTL
) & BXT_CDCLK_CD2X_DIV_SEL_MASK
;
6756 case BXT_CDCLK_CD2X_DIV_SEL_1
:
6759 case BXT_CDCLK_CD2X_DIV_SEL_1_5
:
6762 case BXT_CDCLK_CD2X_DIV_SEL_2
:
6765 case BXT_CDCLK_CD2X_DIV_SEL_4
:
6769 MISSING_CASE(divider
);
6770 return dev_priv
->cdclk_pll
.ref
;
6773 return DIV_ROUND_CLOSEST(vco
, div
);
6776 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6779 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6780 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6782 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6784 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6786 else if (freq
== LCPLL_CLK_FREQ_450
)
6788 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6790 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6796 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6798 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6799 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6800 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6802 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6804 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6806 else if (freq
== LCPLL_CLK_FREQ_450
)
6808 else if (IS_HSW_ULT(dev
))
6814 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6816 return vlv_get_cck_clock_hpll(to_i915(dev
), "cdclk",
6817 CCK_DISPLAY_CLOCK_CONTROL
);
6820 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6825 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6830 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6835 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6840 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6844 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6846 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6847 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6849 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6851 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6853 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6856 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6857 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6859 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6864 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6868 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6870 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6873 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6874 case GC_DISPLAY_CLOCK_333_MHZ
:
6877 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6883 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6888 static int i85x_get_display_clock_speed(struct drm_device
*dev
)
6893 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6894 * encoding is different :(
6895 * FIXME is this the right way to detect 852GM/852GMV?
6897 if (dev
->pdev
->revision
== 0x1)
6900 pci_bus_read_config_word(dev
->pdev
->bus
,
6901 PCI_DEVFN(0, 3), HPLLCC
, &hpllcc
);
6903 /* Assume that the hardware is in the high speed state. This
6904 * should be the default.
6906 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6907 case GC_CLOCK_133_200
:
6908 case GC_CLOCK_133_200_2
:
6909 case GC_CLOCK_100_200
:
6911 case GC_CLOCK_166_250
:
6913 case GC_CLOCK_100_133
:
6915 case GC_CLOCK_133_266
:
6916 case GC_CLOCK_133_266_2
:
6917 case GC_CLOCK_166_266
:
6921 /* Shouldn't happen */
6925 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6930 static unsigned int intel_hpll_vco(struct drm_device
*dev
)
6932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6933 static const unsigned int blb_vco
[8] = {
6940 static const unsigned int pnv_vco
[8] = {
6947 static const unsigned int cl_vco
[8] = {
6956 static const unsigned int elk_vco
[8] = {
6962 static const unsigned int ctg_vco
[8] = {
6970 const unsigned int *vco_table
;
6974 /* FIXME other chipsets? */
6976 vco_table
= ctg_vco
;
6977 else if (IS_G4X(dev
))
6978 vco_table
= elk_vco
;
6979 else if (IS_CRESTLINE(dev
))
6981 else if (IS_PINEVIEW(dev
))
6982 vco_table
= pnv_vco
;
6983 else if (IS_G33(dev
))
6984 vco_table
= blb_vco
;
6988 tmp
= I915_READ(IS_MOBILE(dev
) ? HPLLVCO_MOBILE
: HPLLVCO
);
6990 vco
= vco_table
[tmp
& 0x7];
6992 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp
);
6994 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco
);
6999 static int gm45_get_display_clock_speed(struct drm_device
*dev
)
7001 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7004 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7006 cdclk_sel
= (tmp
>> 12) & 0x1;
7012 return cdclk_sel
? 333333 : 222222;
7014 return cdclk_sel
? 320000 : 228571;
7016 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco
, tmp
);
7021 static int i965gm_get_display_clock_speed(struct drm_device
*dev
)
7023 static const uint8_t div_3200
[] = { 16, 10, 8 };
7024 static const uint8_t div_4000
[] = { 20, 12, 10 };
7025 static const uint8_t div_5333
[] = { 24, 16, 14 };
7026 const uint8_t *div_table
;
7027 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7030 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7032 cdclk_sel
= ((tmp
>> 8) & 0x1f) - 1;
7034 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7039 div_table
= div_3200
;
7042 div_table
= div_4000
;
7045 div_table
= div_5333
;
7051 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7054 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco
, tmp
);
7058 static int g33_get_display_clock_speed(struct drm_device
*dev
)
7060 static const uint8_t div_3200
[] = { 12, 10, 8, 7, 5, 16 };
7061 static const uint8_t div_4000
[] = { 14, 12, 10, 8, 6, 20 };
7062 static const uint8_t div_4800
[] = { 20, 14, 12, 10, 8, 24 };
7063 static const uint8_t div_5333
[] = { 20, 16, 12, 12, 8, 28 };
7064 const uint8_t *div_table
;
7065 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7068 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7070 cdclk_sel
= (tmp
>> 4) & 0x7;
7072 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7077 div_table
= div_3200
;
7080 div_table
= div_4000
;
7083 div_table
= div_4800
;
7086 div_table
= div_5333
;
7092 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7095 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco
, tmp
);
7100 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
7102 while (*num
> DATA_LINK_M_N_MASK
||
7103 *den
> DATA_LINK_M_N_MASK
) {
7109 static void compute_m_n(unsigned int m
, unsigned int n
,
7110 uint32_t *ret_m
, uint32_t *ret_n
)
7112 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7113 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
7114 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7118 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
7119 int pixel_clock
, int link_clock
,
7120 struct intel_link_m_n
*m_n
)
7124 compute_m_n(bits_per_pixel
* pixel_clock
,
7125 link_clock
* nlanes
* 8,
7126 &m_n
->gmch_m
, &m_n
->gmch_n
);
7128 compute_m_n(pixel_clock
, link_clock
,
7129 &m_n
->link_m
, &m_n
->link_n
);
7132 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7134 if (i915
.panel_use_ssc
>= 0)
7135 return i915
.panel_use_ssc
!= 0;
7136 return dev_priv
->vbt
.lvds_use_ssc
7137 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7140 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
7142 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7145 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
7147 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7150 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7151 struct intel_crtc_state
*crtc_state
,
7152 struct dpll
*reduced_clock
)
7154 struct drm_device
*dev
= crtc
->base
.dev
;
7157 if (IS_PINEVIEW(dev
)) {
7158 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7160 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7162 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7164 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7167 crtc_state
->dpll_hw_state
.fp0
= fp
;
7169 crtc
->lowfreq_avail
= false;
7170 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7172 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7173 crtc
->lowfreq_avail
= true;
7175 crtc_state
->dpll_hw_state
.fp1
= fp
;
7179 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7185 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7186 * and set it to a reasonable value instead.
7188 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7189 reg_val
&= 0xffffff00;
7190 reg_val
|= 0x00000030;
7191 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7193 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7194 reg_val
&= 0x8cffffff;
7195 reg_val
= 0x8c000000;
7196 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7198 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7199 reg_val
&= 0xffffff00;
7200 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7202 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7203 reg_val
&= 0x00ffffff;
7204 reg_val
|= 0xb0000000;
7205 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7208 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
7209 struct intel_link_m_n
*m_n
)
7211 struct drm_device
*dev
= crtc
->base
.dev
;
7212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7213 int pipe
= crtc
->pipe
;
7215 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7216 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7217 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7218 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7221 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
7222 struct intel_link_m_n
*m_n
,
7223 struct intel_link_m_n
*m2_n2
)
7225 struct drm_device
*dev
= crtc
->base
.dev
;
7226 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7227 int pipe
= crtc
->pipe
;
7228 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
7230 if (INTEL_INFO(dev
)->gen
>= 5) {
7231 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7232 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7233 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7234 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7235 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7236 * for gen < 8) and if DRRS is supported (to make sure the
7237 * registers are not unnecessarily accessed).
7239 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
7240 crtc
->config
->has_drrs
) {
7241 I915_WRITE(PIPE_DATA_M2(transcoder
),
7242 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7243 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7244 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7245 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7248 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7249 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7250 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7251 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7255 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
7257 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7260 dp_m_n
= &crtc
->config
->dp_m_n
;
7261 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
7262 } else if (m_n
== M2_N2
) {
7265 * M2_N2 registers are not supported. Hence m2_n2 divider value
7266 * needs to be programmed into M1_N1.
7268 dp_m_n
= &crtc
->config
->dp_m2_n2
;
7270 DRM_ERROR("Unsupported divider value\n");
7274 if (crtc
->config
->has_pch_encoder
)
7275 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
7277 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
7280 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7281 struct intel_crtc_state
*pipe_config
)
7283 pipe_config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
7284 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7285 if (crtc
->pipe
!= PIPE_A
)
7286 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7288 /* DPLL not used with DSI, but still need the rest set up */
7289 if (!pipe_config
->has_dsi_encoder
)
7290 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
|
7291 DPLL_EXT_BUFFER_ENABLE_VLV
;
7293 pipe_config
->dpll_hw_state
.dpll_md
=
7294 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7297 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7298 struct intel_crtc_state
*pipe_config
)
7300 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7301 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7302 if (crtc
->pipe
!= PIPE_A
)
7303 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7305 /* DPLL not used with DSI, but still need the rest set up */
7306 if (!pipe_config
->has_dsi_encoder
)
7307 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
;
7309 pipe_config
->dpll_hw_state
.dpll_md
=
7310 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7313 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7314 const struct intel_crtc_state
*pipe_config
)
7316 struct drm_device
*dev
= crtc
->base
.dev
;
7317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7318 enum pipe pipe
= crtc
->pipe
;
7320 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7321 u32 coreclk
, reg_val
;
7324 I915_WRITE(DPLL(pipe
),
7325 pipe_config
->dpll_hw_state
.dpll
&
7326 ~(DPLL_VCO_ENABLE
| DPLL_EXT_BUFFER_ENABLE_VLV
));
7328 /* No need to actually set up the DPLL with DSI */
7329 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7332 mutex_lock(&dev_priv
->sb_lock
);
7334 bestn
= pipe_config
->dpll
.n
;
7335 bestm1
= pipe_config
->dpll
.m1
;
7336 bestm2
= pipe_config
->dpll
.m2
;
7337 bestp1
= pipe_config
->dpll
.p1
;
7338 bestp2
= pipe_config
->dpll
.p2
;
7340 /* See eDP HDMI DPIO driver vbios notes doc */
7342 /* PLL B needs special handling */
7344 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7346 /* Set up Tx target for periodic Rcomp update */
7347 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7349 /* Disable target IRef on PLL */
7350 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7351 reg_val
&= 0x00ffffff;
7352 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7354 /* Disable fast lock */
7355 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7357 /* Set idtafcrecal before PLL is enabled */
7358 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7359 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7360 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7361 mdiv
|= (1 << DPIO_K_SHIFT
);
7364 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7365 * but we don't support that).
7366 * Note: don't use the DAC post divider as it seems unstable.
7368 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7369 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7371 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7372 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7374 /* Set HBR and RBR LPF coefficients */
7375 if (pipe_config
->port_clock
== 162000 ||
7376 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
7377 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
7378 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7381 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7384 if (pipe_config
->has_dp_encoder
) {
7385 /* Use SSC source */
7387 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7390 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7392 } else { /* HDMI or VGA */
7393 /* Use bend source */
7395 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7398 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7402 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7403 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7404 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
7405 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
7406 coreclk
|= 0x01000000;
7407 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7409 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7410 mutex_unlock(&dev_priv
->sb_lock
);
7413 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7414 const struct intel_crtc_state
*pipe_config
)
7416 struct drm_device
*dev
= crtc
->base
.dev
;
7417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7418 enum pipe pipe
= crtc
->pipe
;
7419 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7420 u32 loopfilter
, tribuf_calcntr
;
7421 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7425 /* Enable Refclk and SSC */
7426 I915_WRITE(DPLL(pipe
),
7427 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7429 /* No need to actually set up the DPLL with DSI */
7430 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7433 bestn
= pipe_config
->dpll
.n
;
7434 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7435 bestm1
= pipe_config
->dpll
.m1
;
7436 bestm2
= pipe_config
->dpll
.m2
>> 22;
7437 bestp1
= pipe_config
->dpll
.p1
;
7438 bestp2
= pipe_config
->dpll
.p2
;
7439 vco
= pipe_config
->dpll
.vco
;
7443 mutex_lock(&dev_priv
->sb_lock
);
7445 /* p1 and p2 divider */
7446 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7447 5 << DPIO_CHV_S1_DIV_SHIFT
|
7448 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7449 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7450 1 << DPIO_CHV_K_DIV_SHIFT
);
7452 /* Feedback post-divider - m2 */
7453 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7455 /* Feedback refclk divider - n and m1 */
7456 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7457 DPIO_CHV_M1_DIV_BY_2
|
7458 1 << DPIO_CHV_N_DIV_SHIFT
);
7460 /* M2 fraction division */
7461 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7463 /* M2 fraction division enable */
7464 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7465 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7466 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7468 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7469 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7471 /* Program digital lock detect threshold */
7472 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7473 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7474 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7475 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7477 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7478 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7481 if (vco
== 5400000) {
7482 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7483 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7484 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7485 tribuf_calcntr
= 0x9;
7486 } else if (vco
<= 6200000) {
7487 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7488 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7489 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7490 tribuf_calcntr
= 0x9;
7491 } else if (vco
<= 6480000) {
7492 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7493 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7494 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7495 tribuf_calcntr
= 0x8;
7497 /* Not supported. Apply the same limits as in the max case */
7498 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7499 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7500 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7503 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7505 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7506 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7507 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7508 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7511 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7512 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7515 mutex_unlock(&dev_priv
->sb_lock
);
7519 * vlv_force_pll_on - forcibly enable just the PLL
7520 * @dev_priv: i915 private structure
7521 * @pipe: pipe PLL to enable
7522 * @dpll: PLL configuration
7524 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7525 * in cases where we need the PLL enabled even when @pipe is not going to
7528 int vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7529 const struct dpll
*dpll
)
7531 struct intel_crtc
*crtc
=
7532 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7533 struct intel_crtc_state
*pipe_config
;
7535 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7539 pipe_config
->base
.crtc
= &crtc
->base
;
7540 pipe_config
->pixel_multiplier
= 1;
7541 pipe_config
->dpll
= *dpll
;
7543 if (IS_CHERRYVIEW(dev
)) {
7544 chv_compute_dpll(crtc
, pipe_config
);
7545 chv_prepare_pll(crtc
, pipe_config
);
7546 chv_enable_pll(crtc
, pipe_config
);
7548 vlv_compute_dpll(crtc
, pipe_config
);
7549 vlv_prepare_pll(crtc
, pipe_config
);
7550 vlv_enable_pll(crtc
, pipe_config
);
7559 * vlv_force_pll_off - forcibly disable just the PLL
7560 * @dev_priv: i915 private structure
7561 * @pipe: pipe PLL to disable
7563 * Disable the PLL for @pipe. To be used in cases where we need
7564 * the PLL enabled even when @pipe is not going to be enabled.
7566 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7568 if (IS_CHERRYVIEW(dev
))
7569 chv_disable_pll(to_i915(dev
), pipe
);
7571 vlv_disable_pll(to_i915(dev
), pipe
);
7574 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
7575 struct intel_crtc_state
*crtc_state
,
7576 struct dpll
*reduced_clock
)
7578 struct drm_device
*dev
= crtc
->base
.dev
;
7579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7582 struct dpll
*clock
= &crtc_state
->dpll
;
7584 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7586 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7587 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
7589 dpll
= DPLL_VGA_MODE_DIS
;
7591 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7592 dpll
|= DPLLB_MODE_LVDS
;
7594 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7596 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7597 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7598 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7602 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7604 if (crtc_state
->has_dp_encoder
)
7605 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7607 /* compute bitmask from p1 value */
7608 if (IS_PINEVIEW(dev
))
7609 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7611 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7612 if (IS_G4X(dev
) && reduced_clock
)
7613 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7615 switch (clock
->p2
) {
7617 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7620 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7623 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7626 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7629 if (INTEL_INFO(dev
)->gen
>= 4)
7630 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7632 if (crtc_state
->sdvo_tv_clock
)
7633 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7634 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7635 intel_panel_use_ssc(dev_priv
))
7636 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7638 dpll
|= PLL_REF_INPUT_DREFCLK
;
7640 dpll
|= DPLL_VCO_ENABLE
;
7641 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7643 if (INTEL_INFO(dev
)->gen
>= 4) {
7644 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7645 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7646 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7650 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
7651 struct intel_crtc_state
*crtc_state
,
7652 struct dpll
*reduced_clock
)
7654 struct drm_device
*dev
= crtc
->base
.dev
;
7655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7657 struct dpll
*clock
= &crtc_state
->dpll
;
7659 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7661 dpll
= DPLL_VGA_MODE_DIS
;
7663 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7664 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7667 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7669 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7671 dpll
|= PLL_P2_DIVIDE_BY_4
;
7674 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
7675 dpll
|= DPLL_DVO_2X_MODE
;
7677 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7678 intel_panel_use_ssc(dev_priv
))
7679 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7681 dpll
|= PLL_REF_INPUT_DREFCLK
;
7683 dpll
|= DPLL_VCO_ENABLE
;
7684 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7687 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7689 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7691 enum pipe pipe
= intel_crtc
->pipe
;
7692 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7693 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
7694 uint32_t crtc_vtotal
, crtc_vblank_end
;
7697 /* We need to be careful not to changed the adjusted mode, for otherwise
7698 * the hw state checker will get angry at the mismatch. */
7699 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7700 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7702 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7703 /* the chip adds 2 halflines automatically */
7705 crtc_vblank_end
-= 1;
7707 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7708 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7710 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7711 adjusted_mode
->crtc_htotal
/ 2;
7713 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7716 if (INTEL_INFO(dev
)->gen
> 3)
7717 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7719 I915_WRITE(HTOTAL(cpu_transcoder
),
7720 (adjusted_mode
->crtc_hdisplay
- 1) |
7721 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7722 I915_WRITE(HBLANK(cpu_transcoder
),
7723 (adjusted_mode
->crtc_hblank_start
- 1) |
7724 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7725 I915_WRITE(HSYNC(cpu_transcoder
),
7726 (adjusted_mode
->crtc_hsync_start
- 1) |
7727 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7729 I915_WRITE(VTOTAL(cpu_transcoder
),
7730 (adjusted_mode
->crtc_vdisplay
- 1) |
7731 ((crtc_vtotal
- 1) << 16));
7732 I915_WRITE(VBLANK(cpu_transcoder
),
7733 (adjusted_mode
->crtc_vblank_start
- 1) |
7734 ((crtc_vblank_end
- 1) << 16));
7735 I915_WRITE(VSYNC(cpu_transcoder
),
7736 (adjusted_mode
->crtc_vsync_start
- 1) |
7737 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7739 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7740 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7741 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7743 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7744 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7745 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7749 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
)
7751 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7753 enum pipe pipe
= intel_crtc
->pipe
;
7755 /* pipesrc controls the size that is scaled from, which should
7756 * always be the user's requested size.
7758 I915_WRITE(PIPESRC(pipe
),
7759 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7760 (intel_crtc
->config
->pipe_src_h
- 1));
7763 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7764 struct intel_crtc_state
*pipe_config
)
7766 struct drm_device
*dev
= crtc
->base
.dev
;
7767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7768 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7771 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7772 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7773 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7774 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7775 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7776 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7777 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7778 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7779 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7781 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7782 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7783 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7784 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7785 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7786 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7787 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7788 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7789 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7791 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7792 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7793 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7794 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7798 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
7799 struct intel_crtc_state
*pipe_config
)
7801 struct drm_device
*dev
= crtc
->base
.dev
;
7802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7805 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7806 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7807 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7809 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7810 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7813 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7814 struct intel_crtc_state
*pipe_config
)
7816 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7817 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7818 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7819 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7821 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7822 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7823 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7824 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7826 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7827 mode
->type
= DRM_MODE_TYPE_DRIVER
;
7829 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7830 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7832 mode
->hsync
= drm_mode_hsync(mode
);
7833 mode
->vrefresh
= drm_mode_vrefresh(mode
);
7834 drm_mode_set_name(mode
);
7837 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7839 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7845 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7846 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7847 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7849 if (intel_crtc
->config
->double_wide
)
7850 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7852 /* only g4x and later have fancy bpc/dither controls */
7853 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
7854 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7855 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7856 pipeconf
|= PIPECONF_DITHER_EN
|
7857 PIPECONF_DITHER_TYPE_SP
;
7859 switch (intel_crtc
->config
->pipe_bpp
) {
7861 pipeconf
|= PIPECONF_6BPC
;
7864 pipeconf
|= PIPECONF_8BPC
;
7867 pipeconf
|= PIPECONF_10BPC
;
7870 /* Case prevented by intel_choose_pipe_bpp_dither. */
7875 if (HAS_PIPE_CXSR(dev
)) {
7876 if (intel_crtc
->lowfreq_avail
) {
7877 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7878 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7880 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7884 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7885 if (INTEL_INFO(dev
)->gen
< 4 ||
7886 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7887 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7889 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7891 pipeconf
|= PIPECONF_PROGRESSIVE
;
7893 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
7894 intel_crtc
->config
->limited_color_range
)
7895 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7897 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7898 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7901 static int i8xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7902 struct intel_crtc_state
*crtc_state
)
7904 struct drm_device
*dev
= crtc
->base
.dev
;
7905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7906 const struct intel_limit
*limit
;
7909 memset(&crtc_state
->dpll_hw_state
, 0,
7910 sizeof(crtc_state
->dpll_hw_state
));
7912 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7913 if (intel_panel_use_ssc(dev_priv
)) {
7914 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7915 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7918 limit
= &intel_limits_i8xx_lvds
;
7919 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
)) {
7920 limit
= &intel_limits_i8xx_dvo
;
7922 limit
= &intel_limits_i8xx_dac
;
7925 if (!crtc_state
->clock_set
&&
7926 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7927 refclk
, NULL
, &crtc_state
->dpll
)) {
7928 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7932 i8xx_compute_dpll(crtc
, crtc_state
, NULL
);
7937 static int g4x_crtc_compute_clock(struct intel_crtc
*crtc
,
7938 struct intel_crtc_state
*crtc_state
)
7940 struct drm_device
*dev
= crtc
->base
.dev
;
7941 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7942 const struct intel_limit
*limit
;
7945 memset(&crtc_state
->dpll_hw_state
, 0,
7946 sizeof(crtc_state
->dpll_hw_state
));
7948 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7949 if (intel_panel_use_ssc(dev_priv
)) {
7950 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7951 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7954 if (intel_is_dual_link_lvds(dev
))
7955 limit
= &intel_limits_g4x_dual_channel_lvds
;
7957 limit
= &intel_limits_g4x_single_channel_lvds
;
7958 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
7959 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
7960 limit
= &intel_limits_g4x_hdmi
;
7961 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
7962 limit
= &intel_limits_g4x_sdvo
;
7964 /* The option is for other outputs */
7965 limit
= &intel_limits_i9xx_sdvo
;
7968 if (!crtc_state
->clock_set
&&
7969 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7970 refclk
, NULL
, &crtc_state
->dpll
)) {
7971 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7975 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7980 static int pnv_crtc_compute_clock(struct intel_crtc
*crtc
,
7981 struct intel_crtc_state
*crtc_state
)
7983 struct drm_device
*dev
= crtc
->base
.dev
;
7984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7985 const struct intel_limit
*limit
;
7988 memset(&crtc_state
->dpll_hw_state
, 0,
7989 sizeof(crtc_state
->dpll_hw_state
));
7991 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7992 if (intel_panel_use_ssc(dev_priv
)) {
7993 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7994 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7997 limit
= &intel_limits_pineview_lvds
;
7999 limit
= &intel_limits_pineview_sdvo
;
8002 if (!crtc_state
->clock_set
&&
8003 !pnv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8004 refclk
, NULL
, &crtc_state
->dpll
)) {
8005 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8009 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8014 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
8015 struct intel_crtc_state
*crtc_state
)
8017 struct drm_device
*dev
= crtc
->base
.dev
;
8018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8019 const struct intel_limit
*limit
;
8022 memset(&crtc_state
->dpll_hw_state
, 0,
8023 sizeof(crtc_state
->dpll_hw_state
));
8025 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8026 if (intel_panel_use_ssc(dev_priv
)) {
8027 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8028 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8031 limit
= &intel_limits_i9xx_lvds
;
8033 limit
= &intel_limits_i9xx_sdvo
;
8036 if (!crtc_state
->clock_set
&&
8037 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8038 refclk
, NULL
, &crtc_state
->dpll
)) {
8039 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8043 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8048 static int chv_crtc_compute_clock(struct intel_crtc
*crtc
,
8049 struct intel_crtc_state
*crtc_state
)
8051 int refclk
= 100000;
8052 const struct intel_limit
*limit
= &intel_limits_chv
;
8054 memset(&crtc_state
->dpll_hw_state
, 0,
8055 sizeof(crtc_state
->dpll_hw_state
));
8057 if (!crtc_state
->clock_set
&&
8058 !chv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8059 refclk
, NULL
, &crtc_state
->dpll
)) {
8060 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8064 chv_compute_dpll(crtc
, crtc_state
);
8069 static int vlv_crtc_compute_clock(struct intel_crtc
*crtc
,
8070 struct intel_crtc_state
*crtc_state
)
8072 int refclk
= 100000;
8073 const struct intel_limit
*limit
= &intel_limits_vlv
;
8075 memset(&crtc_state
->dpll_hw_state
, 0,
8076 sizeof(crtc_state
->dpll_hw_state
));
8078 if (!crtc_state
->clock_set
&&
8079 !vlv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8080 refclk
, NULL
, &crtc_state
->dpll
)) {
8081 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8085 vlv_compute_dpll(crtc
, crtc_state
);
8090 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
8091 struct intel_crtc_state
*pipe_config
)
8093 struct drm_device
*dev
= crtc
->base
.dev
;
8094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8097 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
8100 tmp
= I915_READ(PFIT_CONTROL
);
8101 if (!(tmp
& PFIT_ENABLE
))
8104 /* Check whether the pfit is attached to our pipe. */
8105 if (INTEL_INFO(dev
)->gen
< 4) {
8106 if (crtc
->pipe
!= PIPE_B
)
8109 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
8113 pipe_config
->gmch_pfit
.control
= tmp
;
8114 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
8117 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
8118 struct intel_crtc_state
*pipe_config
)
8120 struct drm_device
*dev
= crtc
->base
.dev
;
8121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8122 int pipe
= pipe_config
->cpu_transcoder
;
8125 int refclk
= 100000;
8127 /* In case of DSI, DPLL will not be used */
8128 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8131 mutex_lock(&dev_priv
->sb_lock
);
8132 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8133 mutex_unlock(&dev_priv
->sb_lock
);
8135 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8136 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8137 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8138 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8139 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8141 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
8145 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8146 struct intel_initial_plane_config
*plane_config
)
8148 struct drm_device
*dev
= crtc
->base
.dev
;
8149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8150 u32 val
, base
, offset
;
8151 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
8152 int fourcc
, pixel_format
;
8153 unsigned int aligned_height
;
8154 struct drm_framebuffer
*fb
;
8155 struct intel_framebuffer
*intel_fb
;
8157 val
= I915_READ(DSPCNTR(plane
));
8158 if (!(val
& DISPLAY_PLANE_ENABLE
))
8161 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8163 DRM_DEBUG_KMS("failed to alloc fb\n");
8167 fb
= &intel_fb
->base
;
8169 if (INTEL_INFO(dev
)->gen
>= 4) {
8170 if (val
& DISPPLANE_TILED
) {
8171 plane_config
->tiling
= I915_TILING_X
;
8172 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8176 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8177 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8178 fb
->pixel_format
= fourcc
;
8179 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8181 if (INTEL_INFO(dev
)->gen
>= 4) {
8182 if (plane_config
->tiling
)
8183 offset
= I915_READ(DSPTILEOFF(plane
));
8185 offset
= I915_READ(DSPLINOFF(plane
));
8186 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
8188 base
= I915_READ(DSPADDR(plane
));
8190 plane_config
->base
= base
;
8192 val
= I915_READ(PIPESRC(pipe
));
8193 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8194 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8196 val
= I915_READ(DSPSTRIDE(pipe
));
8197 fb
->pitches
[0] = val
& 0xffffffc0;
8199 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8203 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8205 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8206 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
8207 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8208 plane_config
->size
);
8210 plane_config
->fb
= intel_fb
;
8213 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8214 struct intel_crtc_state
*pipe_config
)
8216 struct drm_device
*dev
= crtc
->base
.dev
;
8217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8218 int pipe
= pipe_config
->cpu_transcoder
;
8219 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8221 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
8222 int refclk
= 100000;
8224 /* In case of DSI, DPLL will not be used */
8225 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8228 mutex_lock(&dev_priv
->sb_lock
);
8229 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8230 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8231 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8232 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8233 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8234 mutex_unlock(&dev_priv
->sb_lock
);
8236 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8237 clock
.m2
= (pll_dw0
& 0xff) << 22;
8238 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
8239 clock
.m2
|= pll_dw2
& 0x3fffff;
8240 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8241 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8242 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8244 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8247 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8248 struct intel_crtc_state
*pipe_config
)
8250 struct drm_device
*dev
= crtc
->base
.dev
;
8251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8252 enum intel_display_power_domain power_domain
;
8256 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
8257 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
8260 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8261 pipe_config
->shared_dpll
= NULL
;
8265 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8266 if (!(tmp
& PIPECONF_ENABLE
))
8269 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
8270 switch (tmp
& PIPECONF_BPC_MASK
) {
8272 pipe_config
->pipe_bpp
= 18;
8275 pipe_config
->pipe_bpp
= 24;
8277 case PIPECONF_10BPC
:
8278 pipe_config
->pipe_bpp
= 30;
8285 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
8286 (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8287 pipe_config
->limited_color_range
= true;
8289 if (INTEL_INFO(dev
)->gen
< 4)
8290 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8292 intel_get_pipe_timings(crtc
, pipe_config
);
8293 intel_get_pipe_src_size(crtc
, pipe_config
);
8295 i9xx_get_pfit_config(crtc
, pipe_config
);
8297 if (INTEL_INFO(dev
)->gen
>= 4) {
8298 /* No way to read it out on pipes B and C */
8299 if (IS_CHERRYVIEW(dev
) && crtc
->pipe
!= PIPE_A
)
8300 tmp
= dev_priv
->chv_dpll_md
[crtc
->pipe
];
8302 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8303 pipe_config
->pixel_multiplier
=
8304 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8305 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8306 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8307 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
8308 tmp
= I915_READ(DPLL(crtc
->pipe
));
8309 pipe_config
->pixel_multiplier
=
8310 ((tmp
& SDVO_MULTIPLIER_MASK
)
8311 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8313 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8314 * port and will be fixed up in the encoder->get_config
8316 pipe_config
->pixel_multiplier
= 1;
8318 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8319 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
8321 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8322 * on 830. Filter it out here so that we don't
8323 * report errors due to that.
8326 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
8328 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8329 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8331 /* Mask out read-only status bits. */
8332 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8333 DPLL_PORTC_READY_MASK
|
8334 DPLL_PORTB_READY_MASK
);
8337 if (IS_CHERRYVIEW(dev
))
8338 chv_crtc_clock_get(crtc
, pipe_config
);
8339 else if (IS_VALLEYVIEW(dev
))
8340 vlv_crtc_clock_get(crtc
, pipe_config
);
8342 i9xx_crtc_clock_get(crtc
, pipe_config
);
8345 * Normally the dotclock is filled in by the encoder .get_config()
8346 * but in case the pipe is enabled w/o any ports we need a sane
8349 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8350 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8355 intel_display_power_put(dev_priv
, power_domain
);
8360 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
8362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8363 struct intel_encoder
*encoder
;
8366 bool has_lvds
= false;
8367 bool has_cpu_edp
= false;
8368 bool has_panel
= false;
8369 bool has_ck505
= false;
8370 bool can_ssc
= false;
8371 bool using_ssc_source
= false;
8373 /* We need to take the global config into account */
8374 for_each_intel_encoder(dev
, encoder
) {
8375 switch (encoder
->type
) {
8376 case INTEL_OUTPUT_LVDS
:
8380 case INTEL_OUTPUT_EDP
:
8382 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
8390 if (HAS_PCH_IBX(dev
)) {
8391 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8392 can_ssc
= has_ck505
;
8398 /* Check if any DPLLs are using the SSC source */
8399 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8400 u32 temp
= I915_READ(PCH_DPLL(i
));
8402 if (!(temp
& DPLL_VCO_ENABLE
))
8405 if ((temp
& PLL_REF_INPUT_MASK
) ==
8406 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
8407 using_ssc_source
= true;
8412 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8413 has_panel
, has_lvds
, has_ck505
, using_ssc_source
);
8415 /* Ironlake: try to setup display ref clock before DPLL
8416 * enabling. This is only under driver's control after
8417 * PCH B stepping, previous chipset stepping should be
8418 * ignoring this setting.
8420 val
= I915_READ(PCH_DREF_CONTROL
);
8422 /* As we must carefully and slowly disable/enable each source in turn,
8423 * compute the final state we want first and check if we need to
8424 * make any changes at all.
8427 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8429 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8431 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8433 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8435 if (!using_ssc_source
) {
8436 final
&= ~DREF_SSC_SOURCE_MASK
;
8437 final
&= ~DREF_SSC1_ENABLE
;
8441 final
|= DREF_SSC_SOURCE_ENABLE
;
8443 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8444 final
|= DREF_SSC1_ENABLE
;
8447 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8448 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8450 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8452 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8454 final
|= DREF_SSC_SOURCE_DISABLE
;
8455 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8461 /* Always enable nonspread source */
8462 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8465 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8467 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8470 val
&= ~DREF_SSC_SOURCE_MASK
;
8471 val
|= DREF_SSC_SOURCE_ENABLE
;
8473 /* SSC must be turned on before enabling the CPU output */
8474 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8475 DRM_DEBUG_KMS("Using SSC on panel\n");
8476 val
|= DREF_SSC1_ENABLE
;
8478 val
&= ~DREF_SSC1_ENABLE
;
8480 /* Get SSC going before enabling the outputs */
8481 I915_WRITE(PCH_DREF_CONTROL
, val
);
8482 POSTING_READ(PCH_DREF_CONTROL
);
8485 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8487 /* Enable CPU source on CPU attached eDP */
8489 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8490 DRM_DEBUG_KMS("Using SSC on eDP\n");
8491 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8493 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8495 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8497 I915_WRITE(PCH_DREF_CONTROL
, val
);
8498 POSTING_READ(PCH_DREF_CONTROL
);
8501 DRM_DEBUG_KMS("Disabling CPU source output\n");
8503 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8505 /* Turn off CPU output */
8506 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8508 I915_WRITE(PCH_DREF_CONTROL
, val
);
8509 POSTING_READ(PCH_DREF_CONTROL
);
8512 if (!using_ssc_source
) {
8513 DRM_DEBUG_KMS("Disabling SSC source\n");
8515 /* Turn off the SSC source */
8516 val
&= ~DREF_SSC_SOURCE_MASK
;
8517 val
|= DREF_SSC_SOURCE_DISABLE
;
8520 val
&= ~DREF_SSC1_ENABLE
;
8522 I915_WRITE(PCH_DREF_CONTROL
, val
);
8523 POSTING_READ(PCH_DREF_CONTROL
);
8528 BUG_ON(val
!= final
);
8531 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8535 tmp
= I915_READ(SOUTH_CHICKEN2
);
8536 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8537 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8539 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
8540 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8541 DRM_ERROR("FDI mPHY reset assert timeout\n");
8543 tmp
= I915_READ(SOUTH_CHICKEN2
);
8544 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8545 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8547 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
8548 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8549 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8552 /* WaMPhyProgramming:hsw */
8553 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8557 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8558 tmp
&= ~(0xFF << 24);
8559 tmp
|= (0x12 << 24);
8560 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8562 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8564 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8566 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8568 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8570 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8571 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8572 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8574 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8575 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8576 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8578 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8581 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8583 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8586 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8588 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8591 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8593 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8596 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8598 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8599 tmp
&= ~(0xFF << 16);
8600 tmp
|= (0x1C << 16);
8601 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8603 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8604 tmp
&= ~(0xFF << 16);
8605 tmp
|= (0x1C << 16);
8606 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8608 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8610 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8612 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8614 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8616 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8617 tmp
&= ~(0xF << 28);
8619 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8621 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8622 tmp
&= ~(0xF << 28);
8624 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8627 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8628 * Programming" based on the parameters passed:
8629 * - Sequence to enable CLKOUT_DP
8630 * - Sequence to enable CLKOUT_DP without spread
8631 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8633 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8639 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8641 if (WARN(HAS_PCH_LPT_LP(dev
) && with_fdi
, "LP PCH doesn't have FDI\n"))
8644 mutex_lock(&dev_priv
->sb_lock
);
8646 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8647 tmp
&= ~SBI_SSCCTL_DISABLE
;
8648 tmp
|= SBI_SSCCTL_PATHALT
;
8649 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8654 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8655 tmp
&= ~SBI_SSCCTL_PATHALT
;
8656 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8659 lpt_reset_fdi_mphy(dev_priv
);
8660 lpt_program_fdi_mphy(dev_priv
);
8664 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8665 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8666 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8667 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8669 mutex_unlock(&dev_priv
->sb_lock
);
8672 /* Sequence to disable CLKOUT_DP */
8673 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8678 mutex_lock(&dev_priv
->sb_lock
);
8680 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8681 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8682 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8683 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8685 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8686 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8687 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8688 tmp
|= SBI_SSCCTL_PATHALT
;
8689 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8692 tmp
|= SBI_SSCCTL_DISABLE
;
8693 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8696 mutex_unlock(&dev_priv
->sb_lock
);
8699 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8701 static const uint16_t sscdivintphase
[] = {
8702 [BEND_IDX( 50)] = 0x3B23,
8703 [BEND_IDX( 45)] = 0x3B23,
8704 [BEND_IDX( 40)] = 0x3C23,
8705 [BEND_IDX( 35)] = 0x3C23,
8706 [BEND_IDX( 30)] = 0x3D23,
8707 [BEND_IDX( 25)] = 0x3D23,
8708 [BEND_IDX( 20)] = 0x3E23,
8709 [BEND_IDX( 15)] = 0x3E23,
8710 [BEND_IDX( 10)] = 0x3F23,
8711 [BEND_IDX( 5)] = 0x3F23,
8712 [BEND_IDX( 0)] = 0x0025,
8713 [BEND_IDX( -5)] = 0x0025,
8714 [BEND_IDX(-10)] = 0x0125,
8715 [BEND_IDX(-15)] = 0x0125,
8716 [BEND_IDX(-20)] = 0x0225,
8717 [BEND_IDX(-25)] = 0x0225,
8718 [BEND_IDX(-30)] = 0x0325,
8719 [BEND_IDX(-35)] = 0x0325,
8720 [BEND_IDX(-40)] = 0x0425,
8721 [BEND_IDX(-45)] = 0x0425,
8722 [BEND_IDX(-50)] = 0x0525,
8727 * steps -50 to 50 inclusive, in steps of 5
8728 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8729 * change in clock period = -(steps / 10) * 5.787 ps
8731 static void lpt_bend_clkout_dp(struct drm_i915_private
*dev_priv
, int steps
)
8734 int idx
= BEND_IDX(steps
);
8736 if (WARN_ON(steps
% 5 != 0))
8739 if (WARN_ON(idx
>= ARRAY_SIZE(sscdivintphase
)))
8742 mutex_lock(&dev_priv
->sb_lock
);
8744 if (steps
% 10 != 0)
8748 intel_sbi_write(dev_priv
, SBI_SSCDITHPHASE
, tmp
, SBI_ICLK
);
8750 tmp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE
, SBI_ICLK
);
8752 tmp
|= sscdivintphase
[idx
];
8753 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE
, tmp
, SBI_ICLK
);
8755 mutex_unlock(&dev_priv
->sb_lock
);
8760 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8762 struct intel_encoder
*encoder
;
8763 bool has_vga
= false;
8765 for_each_intel_encoder(dev
, encoder
) {
8766 switch (encoder
->type
) {
8767 case INTEL_OUTPUT_ANALOG
:
8776 lpt_bend_clkout_dp(to_i915(dev
), 0);
8777 lpt_enable_clkout_dp(dev
, true, true);
8779 lpt_disable_clkout_dp(dev
);
8784 * Initialize reference clocks when the driver loads
8786 void intel_init_pch_refclk(struct drm_device
*dev
)
8788 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8789 ironlake_init_pch_refclk(dev
);
8790 else if (HAS_PCH_LPT(dev
))
8791 lpt_init_pch_refclk(dev
);
8794 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8796 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8797 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8798 int pipe
= intel_crtc
->pipe
;
8803 switch (intel_crtc
->config
->pipe_bpp
) {
8805 val
|= PIPECONF_6BPC
;
8808 val
|= PIPECONF_8BPC
;
8811 val
|= PIPECONF_10BPC
;
8814 val
|= PIPECONF_12BPC
;
8817 /* Case prevented by intel_choose_pipe_bpp_dither. */
8821 if (intel_crtc
->config
->dither
)
8822 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8824 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8825 val
|= PIPECONF_INTERLACED_ILK
;
8827 val
|= PIPECONF_PROGRESSIVE
;
8829 if (intel_crtc
->config
->limited_color_range
)
8830 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8832 I915_WRITE(PIPECONF(pipe
), val
);
8833 POSTING_READ(PIPECONF(pipe
));
8836 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8838 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8839 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8840 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8843 if (IS_HASWELL(dev_priv
) && intel_crtc
->config
->dither
)
8844 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8846 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8847 val
|= PIPECONF_INTERLACED_ILK
;
8849 val
|= PIPECONF_PROGRESSIVE
;
8851 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8852 POSTING_READ(PIPECONF(cpu_transcoder
));
8855 static void haswell_set_pipemisc(struct drm_crtc
*crtc
)
8857 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8858 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8860 if (IS_BROADWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 9) {
8863 switch (intel_crtc
->config
->pipe_bpp
) {
8865 val
|= PIPEMISC_DITHER_6_BPC
;
8868 val
|= PIPEMISC_DITHER_8_BPC
;
8871 val
|= PIPEMISC_DITHER_10_BPC
;
8874 val
|= PIPEMISC_DITHER_12_BPC
;
8877 /* Case prevented by pipe_config_set_bpp. */
8881 if (intel_crtc
->config
->dither
)
8882 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8884 I915_WRITE(PIPEMISC(intel_crtc
->pipe
), val
);
8888 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8891 * Account for spread spectrum to avoid
8892 * oversubscribing the link. Max center spread
8893 * is 2.5%; use 5% for safety's sake.
8895 u32 bps
= target_clock
* bpp
* 21 / 20;
8896 return DIV_ROUND_UP(bps
, link_bw
* 8);
8899 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8901 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8904 static void ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8905 struct intel_crtc_state
*crtc_state
,
8906 struct dpll
*reduced_clock
)
8908 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8909 struct drm_device
*dev
= crtc
->dev
;
8910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8911 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8912 struct drm_connector
*connector
;
8913 struct drm_connector_state
*connector_state
;
8914 struct intel_encoder
*encoder
;
8917 bool is_lvds
= false, is_sdvo
= false;
8919 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8920 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8923 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8925 switch (encoder
->type
) {
8926 case INTEL_OUTPUT_LVDS
:
8929 case INTEL_OUTPUT_SDVO
:
8930 case INTEL_OUTPUT_HDMI
:
8938 /* Enable autotuning of the PLL clock (if permissible) */
8941 if ((intel_panel_use_ssc(dev_priv
) &&
8942 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8943 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8945 } else if (crtc_state
->sdvo_tv_clock
)
8948 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8950 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8953 if (reduced_clock
) {
8954 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
8956 if (reduced_clock
->m
< factor
* reduced_clock
->n
)
8965 dpll
|= DPLLB_MODE_LVDS
;
8967 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8969 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8970 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8973 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8974 if (crtc_state
->has_dp_encoder
)
8975 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8977 /* compute bitmask from p1 value */
8978 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8980 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8982 switch (crtc_state
->dpll
.p2
) {
8984 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8987 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8990 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8993 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8997 if (is_lvds
&& intel_panel_use_ssc(dev_priv
))
8998 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
9000 dpll
|= PLL_REF_INPUT_DREFCLK
;
9002 dpll
|= DPLL_VCO_ENABLE
;
9004 crtc_state
->dpll_hw_state
.dpll
= dpll
;
9005 crtc_state
->dpll_hw_state
.fp0
= fp
;
9006 crtc_state
->dpll_hw_state
.fp1
= fp2
;
9009 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
9010 struct intel_crtc_state
*crtc_state
)
9012 struct drm_device
*dev
= crtc
->base
.dev
;
9013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9014 struct dpll reduced_clock
;
9015 bool has_reduced_clock
= false;
9016 struct intel_shared_dpll
*pll
;
9017 const struct intel_limit
*limit
;
9018 int refclk
= 120000;
9020 memset(&crtc_state
->dpll_hw_state
, 0,
9021 sizeof(crtc_state
->dpll_hw_state
));
9023 crtc
->lowfreq_avail
= false;
9025 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9026 if (!crtc_state
->has_pch_encoder
)
9029 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
9030 if (intel_panel_use_ssc(dev_priv
)) {
9031 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9032 dev_priv
->vbt
.lvds_ssc_freq
);
9033 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
9036 if (intel_is_dual_link_lvds(dev
)) {
9037 if (refclk
== 100000)
9038 limit
= &intel_limits_ironlake_dual_lvds_100m
;
9040 limit
= &intel_limits_ironlake_dual_lvds
;
9042 if (refclk
== 100000)
9043 limit
= &intel_limits_ironlake_single_lvds_100m
;
9045 limit
= &intel_limits_ironlake_single_lvds
;
9048 limit
= &intel_limits_ironlake_dac
;
9051 if (!crtc_state
->clock_set
&&
9052 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
9053 refclk
, NULL
, &crtc_state
->dpll
)) {
9054 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9058 ironlake_compute_dpll(crtc
, crtc_state
,
9059 has_reduced_clock
? &reduced_clock
: NULL
);
9061 pll
= intel_get_shared_dpll(crtc
, crtc_state
, NULL
);
9063 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9064 pipe_name(crtc
->pipe
));
9068 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
9070 crtc
->lowfreq_avail
= true;
9075 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
9076 struct intel_link_m_n
*m_n
)
9078 struct drm_device
*dev
= crtc
->base
.dev
;
9079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9080 enum pipe pipe
= crtc
->pipe
;
9082 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
9083 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
9084 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
9086 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
9087 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
9088 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9091 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
9092 enum transcoder transcoder
,
9093 struct intel_link_m_n
*m_n
,
9094 struct intel_link_m_n
*m2_n2
)
9096 struct drm_device
*dev
= crtc
->base
.dev
;
9097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9098 enum pipe pipe
= crtc
->pipe
;
9100 if (INTEL_INFO(dev
)->gen
>= 5) {
9101 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
9102 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
9103 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
9105 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
9106 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
9107 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9108 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9109 * gen < 8) and if DRRS is supported (to make sure the
9110 * registers are not unnecessarily read).
9112 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
9113 crtc
->config
->has_drrs
) {
9114 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
9115 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
9116 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
9118 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
9119 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
9120 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9123 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
9124 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
9125 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
9127 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
9128 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
9129 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9133 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
9134 struct intel_crtc_state
*pipe_config
)
9136 if (pipe_config
->has_pch_encoder
)
9137 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
9139 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9140 &pipe_config
->dp_m_n
,
9141 &pipe_config
->dp_m2_n2
);
9144 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9145 struct intel_crtc_state
*pipe_config
)
9147 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9148 &pipe_config
->fdi_m_n
, NULL
);
9151 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9152 struct intel_crtc_state
*pipe_config
)
9154 struct drm_device
*dev
= crtc
->base
.dev
;
9155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9156 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9157 uint32_t ps_ctrl
= 0;
9161 /* find scaler attached to this pipe */
9162 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9163 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9164 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9166 pipe_config
->pch_pfit
.enabled
= true;
9167 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9168 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9173 scaler_state
->scaler_id
= id
;
9175 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9177 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9182 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9183 struct intel_initial_plane_config
*plane_config
)
9185 struct drm_device
*dev
= crtc
->base
.dev
;
9186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9187 u32 val
, base
, offset
, stride_mult
, tiling
;
9188 int pipe
= crtc
->pipe
;
9189 int fourcc
, pixel_format
;
9190 unsigned int aligned_height
;
9191 struct drm_framebuffer
*fb
;
9192 struct intel_framebuffer
*intel_fb
;
9194 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9196 DRM_DEBUG_KMS("failed to alloc fb\n");
9200 fb
= &intel_fb
->base
;
9202 val
= I915_READ(PLANE_CTL(pipe
, 0));
9203 if (!(val
& PLANE_CTL_ENABLE
))
9206 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9207 fourcc
= skl_format_to_fourcc(pixel_format
,
9208 val
& PLANE_CTL_ORDER_RGBX
,
9209 val
& PLANE_CTL_ALPHA_MASK
);
9210 fb
->pixel_format
= fourcc
;
9211 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9213 tiling
= val
& PLANE_CTL_TILED_MASK
;
9215 case PLANE_CTL_TILED_LINEAR
:
9216 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
9218 case PLANE_CTL_TILED_X
:
9219 plane_config
->tiling
= I915_TILING_X
;
9220 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9222 case PLANE_CTL_TILED_Y
:
9223 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
9225 case PLANE_CTL_TILED_YF
:
9226 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
9229 MISSING_CASE(tiling
);
9233 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
9234 plane_config
->base
= base
;
9236 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
9238 val
= I915_READ(PLANE_SIZE(pipe
, 0));
9239 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9240 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9242 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
9243 stride_mult
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
9245 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9247 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9251 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9253 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9254 pipe_name(pipe
), fb
->width
, fb
->height
,
9255 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9256 plane_config
->size
);
9258 plane_config
->fb
= intel_fb
;
9265 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9266 struct intel_crtc_state
*pipe_config
)
9268 struct drm_device
*dev
= crtc
->base
.dev
;
9269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9272 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9274 if (tmp
& PF_ENABLE
) {
9275 pipe_config
->pch_pfit
.enabled
= true;
9276 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9277 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9279 /* We currently do not free assignements of panel fitters on
9280 * ivb/hsw (since we don't use the higher upscaling modes which
9281 * differentiates them) so just WARN about this case for now. */
9283 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9284 PF_PIPE_SEL_IVB(crtc
->pipe
));
9290 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
9291 struct intel_initial_plane_config
*plane_config
)
9293 struct drm_device
*dev
= crtc
->base
.dev
;
9294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9295 u32 val
, base
, offset
;
9296 int pipe
= crtc
->pipe
;
9297 int fourcc
, pixel_format
;
9298 unsigned int aligned_height
;
9299 struct drm_framebuffer
*fb
;
9300 struct intel_framebuffer
*intel_fb
;
9302 val
= I915_READ(DSPCNTR(pipe
));
9303 if (!(val
& DISPLAY_PLANE_ENABLE
))
9306 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9308 DRM_DEBUG_KMS("failed to alloc fb\n");
9312 fb
= &intel_fb
->base
;
9314 if (INTEL_INFO(dev
)->gen
>= 4) {
9315 if (val
& DISPPLANE_TILED
) {
9316 plane_config
->tiling
= I915_TILING_X
;
9317 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9321 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
9322 fourcc
= i9xx_format_to_fourcc(pixel_format
);
9323 fb
->pixel_format
= fourcc
;
9324 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9326 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
9327 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
9328 offset
= I915_READ(DSPOFFSET(pipe
));
9330 if (plane_config
->tiling
)
9331 offset
= I915_READ(DSPTILEOFF(pipe
));
9333 offset
= I915_READ(DSPLINOFF(pipe
));
9335 plane_config
->base
= base
;
9337 val
= I915_READ(PIPESRC(pipe
));
9338 fb
->width
= ((val
>> 16) & 0xfff) + 1;
9339 fb
->height
= ((val
>> 0) & 0xfff) + 1;
9341 val
= I915_READ(DSPSTRIDE(pipe
));
9342 fb
->pitches
[0] = val
& 0xffffffc0;
9344 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9348 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9350 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9351 pipe_name(pipe
), fb
->width
, fb
->height
,
9352 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9353 plane_config
->size
);
9355 plane_config
->fb
= intel_fb
;
9358 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9359 struct intel_crtc_state
*pipe_config
)
9361 struct drm_device
*dev
= crtc
->base
.dev
;
9362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9363 enum intel_display_power_domain power_domain
;
9367 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9368 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9371 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9372 pipe_config
->shared_dpll
= NULL
;
9375 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9376 if (!(tmp
& PIPECONF_ENABLE
))
9379 switch (tmp
& PIPECONF_BPC_MASK
) {
9381 pipe_config
->pipe_bpp
= 18;
9384 pipe_config
->pipe_bpp
= 24;
9386 case PIPECONF_10BPC
:
9387 pipe_config
->pipe_bpp
= 30;
9389 case PIPECONF_12BPC
:
9390 pipe_config
->pipe_bpp
= 36;
9396 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9397 pipe_config
->limited_color_range
= true;
9399 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9400 struct intel_shared_dpll
*pll
;
9401 enum intel_dpll_id pll_id
;
9403 pipe_config
->has_pch_encoder
= true;
9405 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9406 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9407 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9409 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9411 if (HAS_PCH_IBX(dev_priv
)) {
9413 * The pipe->pch transcoder and pch transcoder->pll
9416 pll_id
= (enum intel_dpll_id
) crtc
->pipe
;
9418 tmp
= I915_READ(PCH_DPLL_SEL
);
9419 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9420 pll_id
= DPLL_ID_PCH_PLL_B
;
9422 pll_id
= DPLL_ID_PCH_PLL_A
;
9425 pipe_config
->shared_dpll
=
9426 intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
9427 pll
= pipe_config
->shared_dpll
;
9429 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
9430 &pipe_config
->dpll_hw_state
));
9432 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9433 pipe_config
->pixel_multiplier
=
9434 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9435 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9437 ironlake_pch_clock_get(crtc
, pipe_config
);
9439 pipe_config
->pixel_multiplier
= 1;
9442 intel_get_pipe_timings(crtc
, pipe_config
);
9443 intel_get_pipe_src_size(crtc
, pipe_config
);
9445 ironlake_get_pfit_config(crtc
, pipe_config
);
9450 intel_display_power_put(dev_priv
, power_domain
);
9455 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
9457 struct drm_device
*dev
= dev_priv
->dev
;
9458 struct intel_crtc
*crtc
;
9460 for_each_intel_crtc(dev
, crtc
)
9461 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
9462 pipe_name(crtc
->pipe
));
9464 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
9465 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
9466 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
9467 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
9468 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
9469 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
9470 "CPU PWM1 enabled\n");
9471 if (IS_HASWELL(dev
))
9472 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
9473 "CPU PWM2 enabled\n");
9474 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
9475 "PCH PWM1 enabled\n");
9476 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
9477 "Utility pin enabled\n");
9478 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
9481 * In theory we can still leave IRQs enabled, as long as only the HPD
9482 * interrupts remain enabled. We used to check for that, but since it's
9483 * gen-specific and since we only disable LCPLL after we fully disable
9484 * the interrupts, the check below should be enough.
9486 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
9489 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
9491 struct drm_device
*dev
= dev_priv
->dev
;
9493 if (IS_HASWELL(dev
))
9494 return I915_READ(D_COMP_HSW
);
9496 return I915_READ(D_COMP_BDW
);
9499 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
9501 struct drm_device
*dev
= dev_priv
->dev
;
9503 if (IS_HASWELL(dev
)) {
9504 mutex_lock(&dev_priv
->rps
.hw_lock
);
9505 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
9507 DRM_ERROR("Failed to write to D_COMP\n");
9508 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9510 I915_WRITE(D_COMP_BDW
, val
);
9511 POSTING_READ(D_COMP_BDW
);
9516 * This function implements pieces of two sequences from BSpec:
9517 * - Sequence for display software to disable LCPLL
9518 * - Sequence for display software to allow package C8+
9519 * The steps implemented here are just the steps that actually touch the LCPLL
9520 * register. Callers should take care of disabling all the display engine
9521 * functions, doing the mode unset, fixing interrupts, etc.
9523 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9524 bool switch_to_fclk
, bool allow_power_down
)
9528 assert_can_disable_lcpll(dev_priv
);
9530 val
= I915_READ(LCPLL_CTL
);
9532 if (switch_to_fclk
) {
9533 val
|= LCPLL_CD_SOURCE_FCLK
;
9534 I915_WRITE(LCPLL_CTL
, val
);
9536 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9537 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9538 DRM_ERROR("Switching to FCLK failed\n");
9540 val
= I915_READ(LCPLL_CTL
);
9543 val
|= LCPLL_PLL_DISABLE
;
9544 I915_WRITE(LCPLL_CTL
, val
);
9545 POSTING_READ(LCPLL_CTL
);
9547 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
9548 DRM_ERROR("LCPLL still locked\n");
9550 val
= hsw_read_dcomp(dev_priv
);
9551 val
|= D_COMP_COMP_DISABLE
;
9552 hsw_write_dcomp(dev_priv
, val
);
9555 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9557 DRM_ERROR("D_COMP RCOMP still in progress\n");
9559 if (allow_power_down
) {
9560 val
= I915_READ(LCPLL_CTL
);
9561 val
|= LCPLL_POWER_DOWN_ALLOW
;
9562 I915_WRITE(LCPLL_CTL
, val
);
9563 POSTING_READ(LCPLL_CTL
);
9568 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9571 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9575 val
= I915_READ(LCPLL_CTL
);
9577 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9578 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9582 * Make sure we're not on PC8 state before disabling PC8, otherwise
9583 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9585 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9587 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9588 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9589 I915_WRITE(LCPLL_CTL
, val
);
9590 POSTING_READ(LCPLL_CTL
);
9593 val
= hsw_read_dcomp(dev_priv
);
9594 val
|= D_COMP_COMP_FORCE
;
9595 val
&= ~D_COMP_COMP_DISABLE
;
9596 hsw_write_dcomp(dev_priv
, val
);
9598 val
= I915_READ(LCPLL_CTL
);
9599 val
&= ~LCPLL_PLL_DISABLE
;
9600 I915_WRITE(LCPLL_CTL
, val
);
9602 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
9603 DRM_ERROR("LCPLL not locked yet\n");
9605 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9606 val
= I915_READ(LCPLL_CTL
);
9607 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9608 I915_WRITE(LCPLL_CTL
, val
);
9610 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9611 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9612 DRM_ERROR("Switching back to LCPLL failed\n");
9615 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9616 intel_update_cdclk(dev_priv
->dev
);
9620 * Package states C8 and deeper are really deep PC states that can only be
9621 * reached when all the devices on the system allow it, so even if the graphics
9622 * device allows PC8+, it doesn't mean the system will actually get to these
9623 * states. Our driver only allows PC8+ when going into runtime PM.
9625 * The requirements for PC8+ are that all the outputs are disabled, the power
9626 * well is disabled and most interrupts are disabled, and these are also
9627 * requirements for runtime PM. When these conditions are met, we manually do
9628 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9629 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9632 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9633 * the state of some registers, so when we come back from PC8+ we need to
9634 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9635 * need to take care of the registers kept by RC6. Notice that this happens even
9636 * if we don't put the device in PCI D3 state (which is what currently happens
9637 * because of the runtime PM support).
9639 * For more, read "Display Sequences for Package C8" on the hardware
9642 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9644 struct drm_device
*dev
= dev_priv
->dev
;
9647 DRM_DEBUG_KMS("Enabling package C8+\n");
9649 if (HAS_PCH_LPT_LP(dev
)) {
9650 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9651 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9652 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9655 lpt_disable_clkout_dp(dev
);
9656 hsw_disable_lcpll(dev_priv
, true, true);
9659 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9661 struct drm_device
*dev
= dev_priv
->dev
;
9664 DRM_DEBUG_KMS("Disabling package C8+\n");
9666 hsw_restore_lcpll(dev_priv
);
9667 lpt_init_pch_refclk(dev
);
9669 if (HAS_PCH_LPT_LP(dev
)) {
9670 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9671 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9672 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9676 static void broxton_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9678 struct drm_device
*dev
= old_state
->dev
;
9679 struct intel_atomic_state
*old_intel_state
=
9680 to_intel_atomic_state(old_state
);
9681 unsigned int req_cdclk
= old_intel_state
->dev_cdclk
;
9683 broxton_set_cdclk(to_i915(dev
), req_cdclk
);
9686 /* compute the max rate for new configuration */
9687 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
)
9689 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
9690 struct drm_i915_private
*dev_priv
= state
->dev
->dev_private
;
9691 struct drm_crtc
*crtc
;
9692 struct drm_crtc_state
*cstate
;
9693 struct intel_crtc_state
*crtc_state
;
9694 unsigned max_pixel_rate
= 0, i
;
9697 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
9698 sizeof(intel_state
->min_pixclk
));
9700 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
9703 crtc_state
= to_intel_crtc_state(cstate
);
9704 if (!crtc_state
->base
.enable
) {
9705 intel_state
->min_pixclk
[i
] = 0;
9709 pixel_rate
= ilk_pipe_pixel_rate(crtc_state
);
9711 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9712 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
9713 pixel_rate
= DIV_ROUND_UP(pixel_rate
* 100, 95);
9715 intel_state
->min_pixclk
[i
] = pixel_rate
;
9718 for_each_pipe(dev_priv
, pipe
)
9719 max_pixel_rate
= max(intel_state
->min_pixclk
[pipe
], max_pixel_rate
);
9721 return max_pixel_rate
;
9724 static void broadwell_set_cdclk(struct drm_device
*dev
, int cdclk
)
9726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9730 if (WARN((I915_READ(LCPLL_CTL
) &
9731 (LCPLL_PLL_DISABLE
| LCPLL_PLL_LOCK
|
9732 LCPLL_CD_CLOCK_DISABLE
| LCPLL_ROOT_CD_CLOCK_DISABLE
|
9733 LCPLL_CD2X_CLOCK_DISABLE
| LCPLL_POWER_DOWN_ALLOW
|
9734 LCPLL_CD_SOURCE_FCLK
)) != LCPLL_PLL_LOCK
,
9735 "trying to change cdclk frequency with cdclk not enabled\n"))
9738 mutex_lock(&dev_priv
->rps
.hw_lock
);
9739 ret
= sandybridge_pcode_write(dev_priv
,
9740 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
, 0x0);
9741 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9743 DRM_ERROR("failed to inform pcode about cdclk change\n");
9747 val
= I915_READ(LCPLL_CTL
);
9748 val
|= LCPLL_CD_SOURCE_FCLK
;
9749 I915_WRITE(LCPLL_CTL
, val
);
9751 if (wait_for_us(I915_READ(LCPLL_CTL
) &
9752 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9753 DRM_ERROR("Switching to FCLK failed\n");
9755 val
= I915_READ(LCPLL_CTL
);
9756 val
&= ~LCPLL_CLK_FREQ_MASK
;
9760 val
|= LCPLL_CLK_FREQ_450
;
9764 val
|= LCPLL_CLK_FREQ_54O_BDW
;
9768 val
|= LCPLL_CLK_FREQ_337_5_BDW
;
9772 val
|= LCPLL_CLK_FREQ_675_BDW
;
9776 WARN(1, "invalid cdclk frequency\n");
9780 I915_WRITE(LCPLL_CTL
, val
);
9782 val
= I915_READ(LCPLL_CTL
);
9783 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9784 I915_WRITE(LCPLL_CTL
, val
);
9786 if (wait_for_us((I915_READ(LCPLL_CTL
) &
9787 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9788 DRM_ERROR("Switching back to LCPLL failed\n");
9790 mutex_lock(&dev_priv
->rps
.hw_lock
);
9791 sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
, data
);
9792 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9794 I915_WRITE(CDCLK_FREQ
, DIV_ROUND_CLOSEST(cdclk
, 1000) - 1);
9796 intel_update_cdclk(dev
);
9798 WARN(cdclk
!= dev_priv
->cdclk_freq
,
9799 "cdclk requested %d kHz but got %d kHz\n",
9800 cdclk
, dev_priv
->cdclk_freq
);
9803 static int broadwell_calc_cdclk(int max_pixclk
)
9805 if (max_pixclk
> 540000)
9807 else if (max_pixclk
> 450000)
9809 else if (max_pixclk
> 337500)
9815 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state
*state
)
9817 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9818 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
9819 int max_pixclk
= ilk_max_pixel_rate(state
);
9823 * FIXME should also account for plane ratio
9824 * once 64bpp pixel formats are supported.
9826 cdclk
= broadwell_calc_cdclk(max_pixclk
);
9828 if (cdclk
> dev_priv
->max_cdclk_freq
) {
9829 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9830 cdclk
, dev_priv
->max_cdclk_freq
);
9834 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
9835 if (!intel_state
->active_crtcs
)
9836 intel_state
->dev_cdclk
= broadwell_calc_cdclk(0);
9841 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9843 struct drm_device
*dev
= old_state
->dev
;
9844 struct intel_atomic_state
*old_intel_state
=
9845 to_intel_atomic_state(old_state
);
9846 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
9848 broadwell_set_cdclk(dev
, req_cdclk
);
9851 static int skl_modeset_calc_cdclk(struct drm_atomic_state
*state
)
9853 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
9854 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9855 const int max_pixclk
= ilk_max_pixel_rate(state
);
9856 int vco
= intel_state
->cdclk_pll_vco
;
9860 * FIXME should also account for plane ratio
9861 * once 64bpp pixel formats are supported.
9863 cdclk
= skl_calc_cdclk(max_pixclk
, vco
);
9866 * FIXME move the cdclk caclulation to
9867 * compute_config() so we can fail gracegully.
9869 if (cdclk
> dev_priv
->max_cdclk_freq
) {
9870 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9871 cdclk
, dev_priv
->max_cdclk_freq
);
9872 cdclk
= dev_priv
->max_cdclk_freq
;
9875 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
9876 if (!intel_state
->active_crtcs
)
9877 intel_state
->dev_cdclk
= skl_calc_cdclk(0, vco
);
9882 static void skl_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9884 struct drm_i915_private
*dev_priv
= to_i915(old_state
->dev
);
9885 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(old_state
);
9886 unsigned int req_cdclk
= intel_state
->dev_cdclk
;
9887 unsigned int req_vco
= intel_state
->cdclk_pll_vco
;
9889 skl_set_cdclk(dev_priv
, req_cdclk
, req_vco
);
9892 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9893 struct intel_crtc_state
*crtc_state
)
9895 struct intel_encoder
*intel_encoder
=
9896 intel_ddi_get_crtc_new_encoder(crtc_state
);
9898 if (intel_encoder
->type
!= INTEL_OUTPUT_DSI
) {
9899 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9903 crtc
->lowfreq_avail
= false;
9908 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9910 struct intel_crtc_state
*pipe_config
)
9912 enum intel_dpll_id id
;
9916 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9917 id
= DPLL_ID_SKL_DPLL0
;
9920 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9921 id
= DPLL_ID_SKL_DPLL1
;
9924 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9925 id
= DPLL_ID_SKL_DPLL2
;
9928 DRM_ERROR("Incorrect port type\n");
9932 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9935 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9937 struct intel_crtc_state
*pipe_config
)
9939 enum intel_dpll_id id
;
9942 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9943 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9945 switch (pipe_config
->ddi_pll_sel
) {
9947 id
= DPLL_ID_SKL_DPLL0
;
9950 id
= DPLL_ID_SKL_DPLL1
;
9953 id
= DPLL_ID_SKL_DPLL2
;
9956 id
= DPLL_ID_SKL_DPLL3
;
9959 MISSING_CASE(pipe_config
->ddi_pll_sel
);
9963 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9966 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9968 struct intel_crtc_state
*pipe_config
)
9970 enum intel_dpll_id id
;
9972 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9974 switch (pipe_config
->ddi_pll_sel
) {
9975 case PORT_CLK_SEL_WRPLL1
:
9976 id
= DPLL_ID_WRPLL1
;
9978 case PORT_CLK_SEL_WRPLL2
:
9979 id
= DPLL_ID_WRPLL2
;
9981 case PORT_CLK_SEL_SPLL
:
9984 case PORT_CLK_SEL_LCPLL_810
:
9985 id
= DPLL_ID_LCPLL_810
;
9987 case PORT_CLK_SEL_LCPLL_1350
:
9988 id
= DPLL_ID_LCPLL_1350
;
9990 case PORT_CLK_SEL_LCPLL_2700
:
9991 id
= DPLL_ID_LCPLL_2700
;
9994 MISSING_CASE(pipe_config
->ddi_pll_sel
);
9996 case PORT_CLK_SEL_NONE
:
10000 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
10003 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
10004 struct intel_crtc_state
*pipe_config
,
10005 unsigned long *power_domain_mask
)
10007 struct drm_device
*dev
= crtc
->base
.dev
;
10008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10009 enum intel_display_power_domain power_domain
;
10013 * The pipe->transcoder mapping is fixed with the exception of the eDP
10014 * transcoder handled below.
10016 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
10019 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10020 * consistency and less surprising code; it's in always on power).
10022 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
10023 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
10024 enum pipe trans_edp_pipe
;
10025 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
10027 WARN(1, "unknown pipe linked to edp transcoder\n");
10028 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
10029 case TRANS_DDI_EDP_INPUT_A_ON
:
10030 trans_edp_pipe
= PIPE_A
;
10032 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
10033 trans_edp_pipe
= PIPE_B
;
10035 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
10036 trans_edp_pipe
= PIPE_C
;
10040 if (trans_edp_pipe
== crtc
->pipe
)
10041 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
10044 power_domain
= POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
);
10045 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10047 *power_domain_mask
|= BIT(power_domain
);
10049 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
10051 return tmp
& PIPECONF_ENABLE
;
10054 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
10055 struct intel_crtc_state
*pipe_config
,
10056 unsigned long *power_domain_mask
)
10058 struct drm_device
*dev
= crtc
->base
.dev
;
10059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10060 enum intel_display_power_domain power_domain
;
10062 enum transcoder cpu_transcoder
;
10065 pipe_config
->has_dsi_encoder
= false;
10067 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
10068 if (port
== PORT_A
)
10069 cpu_transcoder
= TRANSCODER_DSI_A
;
10071 cpu_transcoder
= TRANSCODER_DSI_C
;
10073 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
10074 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10076 *power_domain_mask
|= BIT(power_domain
);
10079 * The PLL needs to be enabled with a valid divider
10080 * configuration, otherwise accessing DSI registers will hang
10081 * the machine. See BSpec North Display Engine
10082 * registers/MIPI[BXT]. We can break out here early, since we
10083 * need the same DSI PLL to be enabled for both DSI ports.
10085 if (!intel_dsi_pll_is_enabled(dev_priv
))
10088 /* XXX: this works for video mode only */
10089 tmp
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
10090 if (!(tmp
& DPI_ENABLE
))
10093 tmp
= I915_READ(MIPI_CTRL(port
));
10094 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
10097 pipe_config
->cpu_transcoder
= cpu_transcoder
;
10098 pipe_config
->has_dsi_encoder
= true;
10102 return pipe_config
->has_dsi_encoder
;
10105 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
10106 struct intel_crtc_state
*pipe_config
)
10108 struct drm_device
*dev
= crtc
->base
.dev
;
10109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10110 struct intel_shared_dpll
*pll
;
10114 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
10116 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
10118 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
10119 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
10120 else if (IS_BROXTON(dev
))
10121 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
10123 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
10125 pll
= pipe_config
->shared_dpll
;
10127 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
10128 &pipe_config
->dpll_hw_state
));
10132 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10133 * DDI E. So just check whether this pipe is wired to DDI E and whether
10134 * the PCH transcoder is on.
10136 if (INTEL_INFO(dev
)->gen
< 9 &&
10137 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
10138 pipe_config
->has_pch_encoder
= true;
10140 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
10141 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
10142 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
10144 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
10148 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
10149 struct intel_crtc_state
*pipe_config
)
10151 struct drm_device
*dev
= crtc
->base
.dev
;
10152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10153 enum intel_display_power_domain power_domain
;
10154 unsigned long power_domain_mask
;
10157 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
10158 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10160 power_domain_mask
= BIT(power_domain
);
10162 pipe_config
->shared_dpll
= NULL
;
10164 active
= hsw_get_transcoder_state(crtc
, pipe_config
, &power_domain_mask
);
10166 if (IS_BROXTON(dev_priv
)) {
10167 bxt_get_dsi_transcoder_state(crtc
, pipe_config
,
10168 &power_domain_mask
);
10169 WARN_ON(active
&& pipe_config
->has_dsi_encoder
);
10170 if (pipe_config
->has_dsi_encoder
)
10177 if (!pipe_config
->has_dsi_encoder
) {
10178 haswell_get_ddi_port_state(crtc
, pipe_config
);
10179 intel_get_pipe_timings(crtc
, pipe_config
);
10182 intel_get_pipe_src_size(crtc
, pipe_config
);
10184 pipe_config
->gamma_mode
=
10185 I915_READ(GAMMA_MODE(crtc
->pipe
)) & GAMMA_MODE_MODE_MASK
;
10187 if (INTEL_INFO(dev
)->gen
>= 9) {
10188 skl_init_scalers(dev
, crtc
, pipe_config
);
10191 if (INTEL_INFO(dev
)->gen
>= 9) {
10192 pipe_config
->scaler_state
.scaler_id
= -1;
10193 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
10196 power_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
10197 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
10198 power_domain_mask
|= BIT(power_domain
);
10199 if (INTEL_INFO(dev
)->gen
>= 9)
10200 skylake_get_pfit_config(crtc
, pipe_config
);
10202 ironlake_get_pfit_config(crtc
, pipe_config
);
10205 if (IS_HASWELL(dev
))
10206 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
10207 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
10209 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
10210 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10211 pipe_config
->pixel_multiplier
=
10212 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
10214 pipe_config
->pixel_multiplier
= 1;
10218 for_each_power_domain(power_domain
, power_domain_mask
)
10219 intel_display_power_put(dev_priv
, power_domain
);
10224 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10225 const struct intel_plane_state
*plane_state
)
10227 struct drm_device
*dev
= crtc
->dev
;
10228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10229 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10230 uint32_t cntl
= 0, size
= 0;
10232 if (plane_state
&& plane_state
->visible
) {
10233 unsigned int width
= plane_state
->base
.crtc_w
;
10234 unsigned int height
= plane_state
->base
.crtc_h
;
10235 unsigned int stride
= roundup_pow_of_two(width
) * 4;
10239 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10250 cntl
|= CURSOR_ENABLE
|
10251 CURSOR_GAMMA_ENABLE
|
10252 CURSOR_FORMAT_ARGB
|
10253 CURSOR_STRIDE(stride
);
10255 size
= (height
<< 12) | width
;
10258 if (intel_crtc
->cursor_cntl
!= 0 &&
10259 (intel_crtc
->cursor_base
!= base
||
10260 intel_crtc
->cursor_size
!= size
||
10261 intel_crtc
->cursor_cntl
!= cntl
)) {
10262 /* On these chipsets we can only modify the base/size/stride
10263 * whilst the cursor is disabled.
10265 I915_WRITE(CURCNTR(PIPE_A
), 0);
10266 POSTING_READ(CURCNTR(PIPE_A
));
10267 intel_crtc
->cursor_cntl
= 0;
10270 if (intel_crtc
->cursor_base
!= base
) {
10271 I915_WRITE(CURBASE(PIPE_A
), base
);
10272 intel_crtc
->cursor_base
= base
;
10275 if (intel_crtc
->cursor_size
!= size
) {
10276 I915_WRITE(CURSIZE
, size
);
10277 intel_crtc
->cursor_size
= size
;
10280 if (intel_crtc
->cursor_cntl
!= cntl
) {
10281 I915_WRITE(CURCNTR(PIPE_A
), cntl
);
10282 POSTING_READ(CURCNTR(PIPE_A
));
10283 intel_crtc
->cursor_cntl
= cntl
;
10287 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10288 const struct intel_plane_state
*plane_state
)
10290 struct drm_device
*dev
= crtc
->dev
;
10291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10292 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10293 int pipe
= intel_crtc
->pipe
;
10296 if (plane_state
&& plane_state
->visible
) {
10297 cntl
= MCURSOR_GAMMA_ENABLE
;
10298 switch (plane_state
->base
.crtc_w
) {
10300 cntl
|= CURSOR_MODE_64_ARGB_AX
;
10303 cntl
|= CURSOR_MODE_128_ARGB_AX
;
10306 cntl
|= CURSOR_MODE_256_ARGB_AX
;
10309 MISSING_CASE(plane_state
->base
.crtc_w
);
10312 cntl
|= pipe
<< 28; /* Connect to correct pipe */
10315 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
10317 if (plane_state
->base
.rotation
== BIT(DRM_ROTATE_180
))
10318 cntl
|= CURSOR_ROTATE_180
;
10321 if (intel_crtc
->cursor_cntl
!= cntl
) {
10322 I915_WRITE(CURCNTR(pipe
), cntl
);
10323 POSTING_READ(CURCNTR(pipe
));
10324 intel_crtc
->cursor_cntl
= cntl
;
10327 /* and commit changes on next vblank */
10328 I915_WRITE(CURBASE(pipe
), base
);
10329 POSTING_READ(CURBASE(pipe
));
10331 intel_crtc
->cursor_base
= base
;
10334 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10335 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
10336 const struct intel_plane_state
*plane_state
)
10338 struct drm_device
*dev
= crtc
->dev
;
10339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10340 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10341 int pipe
= intel_crtc
->pipe
;
10342 u32 base
= intel_crtc
->cursor_addr
;
10346 int x
= plane_state
->base
.crtc_x
;
10347 int y
= plane_state
->base
.crtc_y
;
10350 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10353 pos
|= x
<< CURSOR_X_SHIFT
;
10356 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10359 pos
|= y
<< CURSOR_Y_SHIFT
;
10361 /* ILK+ do this automagically */
10362 if (HAS_GMCH_DISPLAY(dev
) &&
10363 plane_state
->base
.rotation
== BIT(DRM_ROTATE_180
)) {
10364 base
+= (plane_state
->base
.crtc_h
*
10365 plane_state
->base
.crtc_w
- 1) * 4;
10369 I915_WRITE(CURPOS(pipe
), pos
);
10371 if (IS_845G(dev
) || IS_I865G(dev
))
10372 i845_update_cursor(crtc
, base
, plane_state
);
10374 i9xx_update_cursor(crtc
, base
, plane_state
);
10377 static bool cursor_size_ok(struct drm_device
*dev
,
10378 uint32_t width
, uint32_t height
)
10380 if (width
== 0 || height
== 0)
10384 * 845g/865g are special in that they are only limited by
10385 * the width of their cursors, the height is arbitrary up to
10386 * the precision of the register. Everything else requires
10387 * square cursors, limited to a few power-of-two sizes.
10389 if (IS_845G(dev
) || IS_I865G(dev
)) {
10390 if ((width
& 63) != 0)
10393 if (width
> (IS_845G(dev
) ? 64 : 512))
10399 switch (width
| height
) {
10414 /* VESA 640x480x72Hz mode to set on the pipe */
10415 static struct drm_display_mode load_detect_mode
= {
10416 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10417 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10420 struct drm_framebuffer
*
10421 __intel_framebuffer_create(struct drm_device
*dev
,
10422 struct drm_mode_fb_cmd2
*mode_cmd
,
10423 struct drm_i915_gem_object
*obj
)
10425 struct intel_framebuffer
*intel_fb
;
10428 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10430 return ERR_PTR(-ENOMEM
);
10432 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
10436 return &intel_fb
->base
;
10440 return ERR_PTR(ret
);
10443 static struct drm_framebuffer
*
10444 intel_framebuffer_create(struct drm_device
*dev
,
10445 struct drm_mode_fb_cmd2
*mode_cmd
,
10446 struct drm_i915_gem_object
*obj
)
10448 struct drm_framebuffer
*fb
;
10451 ret
= i915_mutex_lock_interruptible(dev
);
10453 return ERR_PTR(ret
);
10454 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
10455 mutex_unlock(&dev
->struct_mutex
);
10461 intel_framebuffer_pitch_for_width(int width
, int bpp
)
10463 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
10464 return ALIGN(pitch
, 64);
10468 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
10470 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
10471 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
10474 static struct drm_framebuffer
*
10475 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
10476 struct drm_display_mode
*mode
,
10477 int depth
, int bpp
)
10479 struct drm_framebuffer
*fb
;
10480 struct drm_i915_gem_object
*obj
;
10481 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
10483 obj
= i915_gem_object_create(dev
,
10484 intel_framebuffer_size_for_mode(mode
, bpp
));
10486 return ERR_CAST(obj
);
10488 mode_cmd
.width
= mode
->hdisplay
;
10489 mode_cmd
.height
= mode
->vdisplay
;
10490 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
10492 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
10494 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
10496 drm_gem_object_unreference_unlocked(&obj
->base
);
10501 static struct drm_framebuffer
*
10502 mode_fits_in_fbdev(struct drm_device
*dev
,
10503 struct drm_display_mode
*mode
)
10505 #ifdef CONFIG_DRM_FBDEV_EMULATION
10506 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10507 struct drm_i915_gem_object
*obj
;
10508 struct drm_framebuffer
*fb
;
10510 if (!dev_priv
->fbdev
)
10513 if (!dev_priv
->fbdev
->fb
)
10516 obj
= dev_priv
->fbdev
->fb
->obj
;
10519 fb
= &dev_priv
->fbdev
->fb
->base
;
10520 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
10521 fb
->bits_per_pixel
))
10524 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
10527 drm_framebuffer_reference(fb
);
10534 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
10535 struct drm_crtc
*crtc
,
10536 struct drm_display_mode
*mode
,
10537 struct drm_framebuffer
*fb
,
10540 struct drm_plane_state
*plane_state
;
10541 int hdisplay
, vdisplay
;
10544 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
10545 if (IS_ERR(plane_state
))
10546 return PTR_ERR(plane_state
);
10549 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
10551 hdisplay
= vdisplay
= 0;
10553 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
10556 drm_atomic_set_fb_for_plane(plane_state
, fb
);
10557 plane_state
->crtc_x
= 0;
10558 plane_state
->crtc_y
= 0;
10559 plane_state
->crtc_w
= hdisplay
;
10560 plane_state
->crtc_h
= vdisplay
;
10561 plane_state
->src_x
= x
<< 16;
10562 plane_state
->src_y
= y
<< 16;
10563 plane_state
->src_w
= hdisplay
<< 16;
10564 plane_state
->src_h
= vdisplay
<< 16;
10569 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
10570 struct drm_display_mode
*mode
,
10571 struct intel_load_detect_pipe
*old
,
10572 struct drm_modeset_acquire_ctx
*ctx
)
10574 struct intel_crtc
*intel_crtc
;
10575 struct intel_encoder
*intel_encoder
=
10576 intel_attached_encoder(connector
);
10577 struct drm_crtc
*possible_crtc
;
10578 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10579 struct drm_crtc
*crtc
= NULL
;
10580 struct drm_device
*dev
= encoder
->dev
;
10581 struct drm_framebuffer
*fb
;
10582 struct drm_mode_config
*config
= &dev
->mode_config
;
10583 struct drm_atomic_state
*state
= NULL
, *restore_state
= NULL
;
10584 struct drm_connector_state
*connector_state
;
10585 struct intel_crtc_state
*crtc_state
;
10588 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10589 connector
->base
.id
, connector
->name
,
10590 encoder
->base
.id
, encoder
->name
);
10592 old
->restore_state
= NULL
;
10595 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
10600 * Algorithm gets a little messy:
10602 * - if the connector already has an assigned crtc, use it (but make
10603 * sure it's on first)
10605 * - try to find the first unused crtc that can drive this connector,
10606 * and use that if we find one
10609 /* See if we already have a CRTC for this connector */
10610 if (connector
->state
->crtc
) {
10611 crtc
= connector
->state
->crtc
;
10613 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10617 /* Make sure the crtc and connector are running */
10621 /* Find an unused one (if possible) */
10622 for_each_crtc(dev
, possible_crtc
) {
10624 if (!(encoder
->possible_crtcs
& (1 << i
)))
10627 ret
= drm_modeset_lock(&possible_crtc
->mutex
, ctx
);
10631 if (possible_crtc
->state
->enable
) {
10632 drm_modeset_unlock(&possible_crtc
->mutex
);
10636 crtc
= possible_crtc
;
10641 * If we didn't find an unused CRTC, don't use any.
10644 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10649 intel_crtc
= to_intel_crtc(crtc
);
10651 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10655 state
= drm_atomic_state_alloc(dev
);
10656 restore_state
= drm_atomic_state_alloc(dev
);
10657 if (!state
|| !restore_state
) {
10662 state
->acquire_ctx
= ctx
;
10663 restore_state
->acquire_ctx
= ctx
;
10665 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10666 if (IS_ERR(connector_state
)) {
10667 ret
= PTR_ERR(connector_state
);
10671 ret
= drm_atomic_set_crtc_for_connector(connector_state
, crtc
);
10675 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10676 if (IS_ERR(crtc_state
)) {
10677 ret
= PTR_ERR(crtc_state
);
10681 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10684 mode
= &load_detect_mode
;
10686 /* We need a framebuffer large enough to accommodate all accesses
10687 * that the plane may generate whilst we perform load detection.
10688 * We can not rely on the fbcon either being present (we get called
10689 * during its initialisation to detect all boot displays, or it may
10690 * not even exist) or that it is large enough to satisfy the
10693 fb
= mode_fits_in_fbdev(dev
, mode
);
10695 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10696 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
10698 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10700 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10704 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
10708 drm_framebuffer_unreference(fb
);
10710 ret
= drm_atomic_set_mode_for_crtc(&crtc_state
->base
, mode
);
10714 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state
, connector
));
10716 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state
, crtc
));
10718 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state
, crtc
->primary
));
10720 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret
);
10724 ret
= drm_atomic_commit(state
);
10726 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10730 old
->restore_state
= restore_state
;
10732 /* let the connector get through one full cycle before testing */
10733 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
10737 drm_atomic_state_free(state
);
10738 drm_atomic_state_free(restore_state
);
10739 restore_state
= state
= NULL
;
10741 if (ret
== -EDEADLK
) {
10742 drm_modeset_backoff(ctx
);
10749 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10750 struct intel_load_detect_pipe
*old
,
10751 struct drm_modeset_acquire_ctx
*ctx
)
10753 struct intel_encoder
*intel_encoder
=
10754 intel_attached_encoder(connector
);
10755 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10756 struct drm_atomic_state
*state
= old
->restore_state
;
10759 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10760 connector
->base
.id
, connector
->name
,
10761 encoder
->base
.id
, encoder
->name
);
10766 ret
= drm_atomic_commit(state
);
10768 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret
);
10769 drm_atomic_state_free(state
);
10773 static int i9xx_pll_refclk(struct drm_device
*dev
,
10774 const struct intel_crtc_state
*pipe_config
)
10776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10777 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10779 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10780 return dev_priv
->vbt
.lvds_ssc_freq
;
10781 else if (HAS_PCH_SPLIT(dev
))
10783 else if (!IS_GEN2(dev
))
10789 /* Returns the clock of the currently programmed mode of the given pipe. */
10790 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10791 struct intel_crtc_state
*pipe_config
)
10793 struct drm_device
*dev
= crtc
->base
.dev
;
10794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10795 int pipe
= pipe_config
->cpu_transcoder
;
10796 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10800 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10802 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10803 fp
= pipe_config
->dpll_hw_state
.fp0
;
10805 fp
= pipe_config
->dpll_hw_state
.fp1
;
10807 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10808 if (IS_PINEVIEW(dev
)) {
10809 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10810 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10812 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10813 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10816 if (!IS_GEN2(dev
)) {
10817 if (IS_PINEVIEW(dev
))
10818 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10819 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10821 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10822 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10824 switch (dpll
& DPLL_MODE_MASK
) {
10825 case DPLLB_MODE_DAC_SERIAL
:
10826 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10829 case DPLLB_MODE_LVDS
:
10830 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10834 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10835 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10839 if (IS_PINEVIEW(dev
))
10840 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
10842 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10844 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10845 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10848 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10849 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10851 if (lvds
& LVDS_CLKB_POWER_UP
)
10856 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10859 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10860 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10862 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10868 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10872 * This value includes pixel_multiplier. We will use
10873 * port_clock to compute adjusted_mode.crtc_clock in the
10874 * encoder's get_config() function.
10876 pipe_config
->port_clock
= port_clock
;
10879 int intel_dotclock_calculate(int link_freq
,
10880 const struct intel_link_m_n
*m_n
)
10883 * The calculation for the data clock is:
10884 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10885 * But we want to avoid losing precison if possible, so:
10886 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10888 * and the link clock is simpler:
10889 * link_clock = (m * link_clock) / n
10895 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10898 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10899 struct intel_crtc_state
*pipe_config
)
10901 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10903 /* read out port_clock from the DPLL */
10904 i9xx_crtc_clock_get(crtc
, pipe_config
);
10907 * In case there is an active pipe without active ports,
10908 * we may need some idea for the dotclock anyway.
10909 * Calculate one based on the FDI configuration.
10911 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10912 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
10913 &pipe_config
->fdi_m_n
);
10916 /** Returns the currently programmed mode of the given pipe. */
10917 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10918 struct drm_crtc
*crtc
)
10920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10921 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10922 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10923 struct drm_display_mode
*mode
;
10924 struct intel_crtc_state
*pipe_config
;
10925 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10926 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10927 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10928 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10929 enum pipe pipe
= intel_crtc
->pipe
;
10931 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10935 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10936 if (!pipe_config
) {
10942 * Construct a pipe_config sufficient for getting the clock info
10943 * back out of crtc_clock_get.
10945 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10946 * to use a real value here instead.
10948 pipe_config
->cpu_transcoder
= (enum transcoder
) pipe
;
10949 pipe_config
->pixel_multiplier
= 1;
10950 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10951 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10952 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10953 i9xx_crtc_clock_get(intel_crtc
, pipe_config
);
10955 mode
->clock
= pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
10956 mode
->hdisplay
= (htot
& 0xffff) + 1;
10957 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10958 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10959 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10960 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10961 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10962 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10963 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10965 drm_mode_set_name(mode
);
10967 kfree(pipe_config
);
10972 void intel_mark_busy(struct drm_i915_private
*dev_priv
)
10974 if (dev_priv
->mm
.busy
)
10977 intel_runtime_pm_get(dev_priv
);
10978 i915_update_gfx_val(dev_priv
);
10979 if (INTEL_GEN(dev_priv
) >= 6)
10980 gen6_rps_busy(dev_priv
);
10981 dev_priv
->mm
.busy
= true;
10984 void intel_mark_idle(struct drm_i915_private
*dev_priv
)
10986 if (!dev_priv
->mm
.busy
)
10989 dev_priv
->mm
.busy
= false;
10991 if (INTEL_GEN(dev_priv
) >= 6)
10992 gen6_rps_idle(dev_priv
);
10994 intel_runtime_pm_put(dev_priv
);
10997 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10999 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11000 struct drm_device
*dev
= crtc
->dev
;
11001 struct intel_flip_work
*work
;
11003 spin_lock_irq(&dev
->event_lock
);
11004 work
= intel_crtc
->flip_work
;
11005 intel_crtc
->flip_work
= NULL
;
11006 spin_unlock_irq(&dev
->event_lock
);
11009 cancel_work_sync(&work
->mmio_work
);
11010 cancel_work_sync(&work
->unpin_work
);
11014 drm_crtc_cleanup(crtc
);
11019 static void intel_unpin_work_fn(struct work_struct
*__work
)
11021 struct intel_flip_work
*work
=
11022 container_of(__work
, struct intel_flip_work
, unpin_work
);
11023 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
11024 struct drm_device
*dev
= crtc
->base
.dev
;
11025 struct drm_plane
*primary
= crtc
->base
.primary
;
11027 if (is_mmio_work(work
))
11028 flush_work(&work
->mmio_work
);
11030 mutex_lock(&dev
->struct_mutex
);
11031 intel_unpin_fb_obj(work
->old_fb
, primary
->state
->rotation
);
11032 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
11034 if (work
->flip_queued_req
)
11035 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
11036 mutex_unlock(&dev
->struct_mutex
);
11038 intel_frontbuffer_flip_complete(dev
, to_intel_plane(primary
)->frontbuffer_bit
);
11039 intel_fbc_post_update(crtc
);
11040 drm_framebuffer_unreference(work
->old_fb
);
11042 BUG_ON(atomic_read(&crtc
->unpin_work_count
) == 0);
11043 atomic_dec(&crtc
->unpin_work_count
);
11048 /* Is 'a' after or equal to 'b'? */
11049 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
11051 return !((a
- b
) & 0x80000000);
11054 static bool __pageflip_finished_cs(struct intel_crtc
*crtc
,
11055 struct intel_flip_work
*work
)
11057 struct drm_device
*dev
= crtc
->base
.dev
;
11058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11059 unsigned reset_counter
;
11061 reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
11062 if (crtc
->reset_counter
!= reset_counter
)
11066 * The relevant registers doen't exist on pre-ctg.
11067 * As the flip done interrupt doesn't trigger for mmio
11068 * flips on gmch platforms, a flip count check isn't
11069 * really needed there. But since ctg has the registers,
11070 * include it in the check anyway.
11072 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
11076 * BDW signals flip done immediately if the plane
11077 * is disabled, even if the plane enable is already
11078 * armed to occur at the next vblank :(
11082 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11083 * used the same base address. In that case the mmio flip might
11084 * have completed, but the CS hasn't even executed the flip yet.
11086 * A flip count check isn't enough as the CS might have updated
11087 * the base address just after start of vblank, but before we
11088 * managed to process the interrupt. This means we'd complete the
11089 * CS flip too soon.
11091 * Combining both checks should get us a good enough result. It may
11092 * still happen that the CS flip has been executed, but has not
11093 * yet actually completed. But in case the base address is the same
11094 * anyway, we don't really care.
11096 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
11097 crtc
->flip_work
->gtt_offset
&&
11098 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc
->pipe
)),
11099 crtc
->flip_work
->flip_count
);
11103 __pageflip_finished_mmio(struct intel_crtc
*crtc
,
11104 struct intel_flip_work
*work
)
11107 * MMIO work completes when vblank is different from
11108 * flip_queued_vblank.
11110 * Reset counter value doesn't matter, this is handled by
11111 * i915_wait_request finishing early, so no need to handle
11114 return intel_crtc_get_vblank_counter(crtc
) != work
->flip_queued_vblank
;
11118 static bool pageflip_finished(struct intel_crtc
*crtc
,
11119 struct intel_flip_work
*work
)
11121 if (!atomic_read(&work
->pending
))
11126 if (is_mmio_work(work
))
11127 return __pageflip_finished_mmio(crtc
, work
);
11129 return __pageflip_finished_cs(crtc
, work
);
11132 void intel_finish_page_flip_cs(struct drm_i915_private
*dev_priv
, int pipe
)
11134 struct drm_device
*dev
= dev_priv
->dev
;
11135 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11136 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11137 struct intel_flip_work
*work
;
11138 unsigned long flags
;
11140 /* Ignore early vblank irqs */
11145 * This is called both by irq handlers and the reset code (to complete
11146 * lost pageflips) so needs the full irqsave spinlocks.
11148 spin_lock_irqsave(&dev
->event_lock
, flags
);
11149 work
= intel_crtc
->flip_work
;
11151 if (work
!= NULL
&&
11152 !is_mmio_work(work
) &&
11153 pageflip_finished(intel_crtc
, work
))
11154 page_flip_completed(intel_crtc
);
11156 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
11159 void intel_finish_page_flip_mmio(struct drm_i915_private
*dev_priv
, int pipe
)
11161 struct drm_device
*dev
= dev_priv
->dev
;
11162 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11163 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11164 struct intel_flip_work
*work
;
11165 unsigned long flags
;
11167 /* Ignore early vblank irqs */
11172 * This is called both by irq handlers and the reset code (to complete
11173 * lost pageflips) so needs the full irqsave spinlocks.
11175 spin_lock_irqsave(&dev
->event_lock
, flags
);
11176 work
= intel_crtc
->flip_work
;
11178 if (work
!= NULL
&&
11179 is_mmio_work(work
) &&
11180 pageflip_finished(intel_crtc
, work
))
11181 page_flip_completed(intel_crtc
);
11183 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
11186 static inline void intel_mark_page_flip_active(struct intel_crtc
*crtc
,
11187 struct intel_flip_work
*work
)
11189 work
->flip_queued_vblank
= intel_crtc_get_vblank_counter(crtc
);
11191 /* Ensure that the work item is consistent when activating it ... */
11192 smp_mb__before_atomic();
11193 atomic_set(&work
->pending
, 1);
11196 static int intel_gen2_queue_flip(struct drm_device
*dev
,
11197 struct drm_crtc
*crtc
,
11198 struct drm_framebuffer
*fb
,
11199 struct drm_i915_gem_object
*obj
,
11200 struct drm_i915_gem_request
*req
,
11203 struct intel_engine_cs
*engine
= req
->engine
;
11204 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11208 ret
= intel_ring_begin(req
, 6);
11212 /* Can't queue multiple flips, so wait for the previous
11213 * one to finish before executing the next.
11215 if (intel_crtc
->plane
)
11216 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11218 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11219 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| flip_mask
);
11220 intel_ring_emit(engine
, MI_NOOP
);
11221 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11222 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11223 intel_ring_emit(engine
, fb
->pitches
[0]);
11224 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
);
11225 intel_ring_emit(engine
, 0); /* aux display base address, unused */
11230 static int intel_gen3_queue_flip(struct drm_device
*dev
,
11231 struct drm_crtc
*crtc
,
11232 struct drm_framebuffer
*fb
,
11233 struct drm_i915_gem_object
*obj
,
11234 struct drm_i915_gem_request
*req
,
11237 struct intel_engine_cs
*engine
= req
->engine
;
11238 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11242 ret
= intel_ring_begin(req
, 6);
11246 if (intel_crtc
->plane
)
11247 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11249 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11250 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| flip_mask
);
11251 intel_ring_emit(engine
, MI_NOOP
);
11252 intel_ring_emit(engine
, MI_DISPLAY_FLIP_I915
|
11253 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11254 intel_ring_emit(engine
, fb
->pitches
[0]);
11255 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
);
11256 intel_ring_emit(engine
, MI_NOOP
);
11261 static int intel_gen4_queue_flip(struct drm_device
*dev
,
11262 struct drm_crtc
*crtc
,
11263 struct drm_framebuffer
*fb
,
11264 struct drm_i915_gem_object
*obj
,
11265 struct drm_i915_gem_request
*req
,
11268 struct intel_engine_cs
*engine
= req
->engine
;
11269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11270 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11271 uint32_t pf
, pipesrc
;
11274 ret
= intel_ring_begin(req
, 4);
11278 /* i965+ uses the linear or tiled offsets from the
11279 * Display Registers (which do not change across a page-flip)
11280 * so we need only reprogram the base address.
11282 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11283 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11284 intel_ring_emit(engine
, fb
->pitches
[0]);
11285 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
|
11288 /* XXX Enabling the panel-fitter across page-flip is so far
11289 * untested on non-native modes, so ignore it for now.
11290 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11293 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11294 intel_ring_emit(engine
, pf
| pipesrc
);
11299 static int intel_gen6_queue_flip(struct drm_device
*dev
,
11300 struct drm_crtc
*crtc
,
11301 struct drm_framebuffer
*fb
,
11302 struct drm_i915_gem_object
*obj
,
11303 struct drm_i915_gem_request
*req
,
11306 struct intel_engine_cs
*engine
= req
->engine
;
11307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11308 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11309 uint32_t pf
, pipesrc
;
11312 ret
= intel_ring_begin(req
, 4);
11316 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11317 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11318 intel_ring_emit(engine
, fb
->pitches
[0] | obj
->tiling_mode
);
11319 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
);
11321 /* Contrary to the suggestions in the documentation,
11322 * "Enable Panel Fitter" does not seem to be required when page
11323 * flipping with a non-native mode, and worse causes a normal
11325 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11328 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11329 intel_ring_emit(engine
, pf
| pipesrc
);
11334 static int intel_gen7_queue_flip(struct drm_device
*dev
,
11335 struct drm_crtc
*crtc
,
11336 struct drm_framebuffer
*fb
,
11337 struct drm_i915_gem_object
*obj
,
11338 struct drm_i915_gem_request
*req
,
11341 struct intel_engine_cs
*engine
= req
->engine
;
11342 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11343 uint32_t plane_bit
= 0;
11346 switch (intel_crtc
->plane
) {
11348 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
11351 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
11354 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
11357 WARN_ONCE(1, "unknown plane in flip command\n");
11362 if (engine
->id
== RCS
) {
11365 * On Gen 8, SRM is now taking an extra dword to accommodate
11366 * 48bits addresses, and we need a NOOP for the batch size to
11374 * BSpec MI_DISPLAY_FLIP for IVB:
11375 * "The full packet must be contained within the same cache line."
11377 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11378 * cacheline, if we ever start emitting more commands before
11379 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11380 * then do the cacheline alignment, and finally emit the
11383 ret
= intel_ring_cacheline_align(req
);
11387 ret
= intel_ring_begin(req
, len
);
11391 /* Unmask the flip-done completion message. Note that the bspec says that
11392 * we should do this for both the BCS and RCS, and that we must not unmask
11393 * more than one flip event at any time (or ensure that one flip message
11394 * can be sent by waiting for flip-done prior to queueing new flips).
11395 * Experimentation says that BCS works despite DERRMR masking all
11396 * flip-done completion events and that unmasking all planes at once
11397 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11398 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11400 if (engine
->id
== RCS
) {
11401 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
11402 intel_ring_emit_reg(engine
, DERRMR
);
11403 intel_ring_emit(engine
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
11404 DERRMR_PIPEB_PRI_FLIP_DONE
|
11405 DERRMR_PIPEC_PRI_FLIP_DONE
));
11407 intel_ring_emit(engine
, MI_STORE_REGISTER_MEM_GEN8
|
11408 MI_SRM_LRM_GLOBAL_GTT
);
11410 intel_ring_emit(engine
, MI_STORE_REGISTER_MEM
|
11411 MI_SRM_LRM_GLOBAL_GTT
);
11412 intel_ring_emit_reg(engine
, DERRMR
);
11413 intel_ring_emit(engine
, engine
->scratch
.gtt_offset
+ 256);
11414 if (IS_GEN8(dev
)) {
11415 intel_ring_emit(engine
, 0);
11416 intel_ring_emit(engine
, MI_NOOP
);
11420 intel_ring_emit(engine
, MI_DISPLAY_FLIP_I915
| plane_bit
);
11421 intel_ring_emit(engine
, (fb
->pitches
[0] | obj
->tiling_mode
));
11422 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
);
11423 intel_ring_emit(engine
, (MI_NOOP
));
11428 static bool use_mmio_flip(struct intel_engine_cs
*engine
,
11429 struct drm_i915_gem_object
*obj
)
11432 * This is not being used for older platforms, because
11433 * non-availability of flip done interrupt forces us to use
11434 * CS flips. Older platforms derive flip done using some clever
11435 * tricks involving the flip_pending status bits and vblank irqs.
11436 * So using MMIO flips there would disrupt this mechanism.
11439 if (engine
== NULL
)
11442 if (INTEL_GEN(engine
->i915
) < 5)
11445 if (i915
.use_mmio_flip
< 0)
11447 else if (i915
.use_mmio_flip
> 0)
11449 else if (i915
.enable_execlists
)
11451 else if (obj
->base
.dma_buf
&&
11452 !reservation_object_test_signaled_rcu(obj
->base
.dma_buf
->resv
,
11456 return engine
!= i915_gem_request_get_engine(obj
->last_write_req
);
11459 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
,
11460 unsigned int rotation
,
11461 struct intel_flip_work
*work
)
11463 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11465 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
11466 const enum pipe pipe
= intel_crtc
->pipe
;
11467 u32 ctl
, stride
, tile_height
;
11469 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
11470 ctl
&= ~PLANE_CTL_TILED_MASK
;
11471 switch (fb
->modifier
[0]) {
11472 case DRM_FORMAT_MOD_NONE
:
11474 case I915_FORMAT_MOD_X_TILED
:
11475 ctl
|= PLANE_CTL_TILED_X
;
11477 case I915_FORMAT_MOD_Y_TILED
:
11478 ctl
|= PLANE_CTL_TILED_Y
;
11480 case I915_FORMAT_MOD_Yf_TILED
:
11481 ctl
|= PLANE_CTL_TILED_YF
;
11484 MISSING_CASE(fb
->modifier
[0]);
11488 * The stride is either expressed as a multiple of 64 bytes chunks for
11489 * linear buffers or in number of tiles for tiled buffers.
11491 if (intel_rotation_90_or_270(rotation
)) {
11492 /* stride = Surface height in tiles */
11493 tile_height
= intel_tile_height(dev_priv
, fb
->modifier
[0], 0);
11494 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
11496 stride
= fb
->pitches
[0] /
11497 intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
11502 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11503 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11505 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
11506 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
11508 I915_WRITE(PLANE_SURF(pipe
, 0), work
->gtt_offset
);
11509 POSTING_READ(PLANE_SURF(pipe
, 0));
11512 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
,
11513 struct intel_flip_work
*work
)
11515 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11517 struct intel_framebuffer
*intel_fb
=
11518 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
11519 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11520 i915_reg_t reg
= DSPCNTR(intel_crtc
->plane
);
11523 dspcntr
= I915_READ(reg
);
11525 if (obj
->tiling_mode
!= I915_TILING_NONE
)
11526 dspcntr
|= DISPPLANE_TILED
;
11528 dspcntr
&= ~DISPPLANE_TILED
;
11530 I915_WRITE(reg
, dspcntr
);
11532 I915_WRITE(DSPSURF(intel_crtc
->plane
), work
->gtt_offset
);
11533 POSTING_READ(DSPSURF(intel_crtc
->plane
));
11536 static void intel_mmio_flip_work_func(struct work_struct
*w
)
11538 struct intel_flip_work
*work
=
11539 container_of(w
, struct intel_flip_work
, mmio_work
);
11540 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
11541 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11542 struct intel_framebuffer
*intel_fb
=
11543 to_intel_framebuffer(crtc
->base
.primary
->fb
);
11544 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11546 if (work
->flip_queued_req
)
11547 WARN_ON(__i915_wait_request(work
->flip_queued_req
,
11549 &dev_priv
->rps
.mmioflips
));
11551 /* For framebuffer backed by dmabuf, wait for fence */
11552 if (obj
->base
.dma_buf
)
11553 WARN_ON(reservation_object_wait_timeout_rcu(obj
->base
.dma_buf
->resv
,
11555 MAX_SCHEDULE_TIMEOUT
) < 0);
11557 intel_pipe_update_start(crtc
);
11559 if (INTEL_GEN(dev_priv
) >= 9)
11560 skl_do_mmio_flip(crtc
, work
->rotation
, work
);
11562 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11563 ilk_do_mmio_flip(crtc
, work
);
11565 intel_pipe_update_end(crtc
, work
);
11568 static int intel_default_queue_flip(struct drm_device
*dev
,
11569 struct drm_crtc
*crtc
,
11570 struct drm_framebuffer
*fb
,
11571 struct drm_i915_gem_object
*obj
,
11572 struct drm_i915_gem_request
*req
,
11578 static bool __pageflip_stall_check_cs(struct drm_i915_private
*dev_priv
,
11579 struct intel_crtc
*intel_crtc
,
11580 struct intel_flip_work
*work
)
11584 if (!atomic_read(&work
->pending
))
11589 vblank
= intel_crtc_get_vblank_counter(intel_crtc
);
11590 if (work
->flip_ready_vblank
== 0) {
11591 if (work
->flip_queued_req
&&
11592 !i915_gem_request_completed(work
->flip_queued_req
, true))
11595 work
->flip_ready_vblank
= vblank
;
11598 if (vblank
- work
->flip_ready_vblank
< 3)
11601 /* Potential stall - if we see that the flip has happened,
11602 * assume a missed interrupt. */
11603 if (INTEL_GEN(dev_priv
) >= 4)
11604 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
11606 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
11608 /* There is a potential issue here with a false positive after a flip
11609 * to the same address. We could address this by checking for a
11610 * non-incrementing frame counter.
11612 return addr
== work
->gtt_offset
;
11615 void intel_check_page_flip(struct drm_i915_private
*dev_priv
, int pipe
)
11617 struct drm_device
*dev
= dev_priv
->dev
;
11618 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11619 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11620 struct intel_flip_work
*work
;
11622 WARN_ON(!in_interrupt());
11627 spin_lock(&dev
->event_lock
);
11628 work
= intel_crtc
->flip_work
;
11630 if (work
!= NULL
&& !is_mmio_work(work
) &&
11631 __pageflip_stall_check_cs(dev_priv
, intel_crtc
, work
)) {
11633 "Kicking stuck page flip: queued at %d, now %d\n",
11634 work
->flip_queued_vblank
, intel_crtc_get_vblank_counter(intel_crtc
));
11635 page_flip_completed(intel_crtc
);
11639 if (work
!= NULL
&& !is_mmio_work(work
) &&
11640 intel_crtc_get_vblank_counter(intel_crtc
) - work
->flip_queued_vblank
> 1)
11641 intel_queue_rps_boost_for_request(work
->flip_queued_req
);
11642 spin_unlock(&dev
->event_lock
);
11645 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
11646 struct drm_framebuffer
*fb
,
11647 struct drm_pending_vblank_event
*event
,
11648 uint32_t page_flip_flags
)
11650 struct drm_device
*dev
= crtc
->dev
;
11651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11652 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11653 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11654 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11655 struct drm_plane
*primary
= crtc
->primary
;
11656 enum pipe pipe
= intel_crtc
->pipe
;
11657 struct intel_flip_work
*work
;
11658 struct intel_engine_cs
*engine
;
11660 struct drm_i915_gem_request
*request
= NULL
;
11664 * drm_mode_page_flip_ioctl() should already catch this, but double
11665 * check to be safe. In the future we may enable pageflipping from
11666 * a disabled primary plane.
11668 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
11671 /* Can't change pixel format via MI display flips. */
11672 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
11676 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11677 * Note that pitch changes could also affect these register.
11679 if (INTEL_INFO(dev
)->gen
> 3 &&
11680 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
11681 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
11684 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
11687 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
11691 work
->event
= event
;
11693 work
->old_fb
= old_fb
;
11694 INIT_WORK(&work
->unpin_work
, intel_unpin_work_fn
);
11696 ret
= drm_crtc_vblank_get(crtc
);
11700 /* We borrow the event spin lock for protecting flip_work */
11701 spin_lock_irq(&dev
->event_lock
);
11702 if (intel_crtc
->flip_work
) {
11703 /* Before declaring the flip queue wedged, check if
11704 * the hardware completed the operation behind our backs.
11706 if (pageflip_finished(intel_crtc
, intel_crtc
->flip_work
)) {
11707 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11708 page_flip_completed(intel_crtc
);
11710 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11711 spin_unlock_irq(&dev
->event_lock
);
11713 drm_crtc_vblank_put(crtc
);
11718 intel_crtc
->flip_work
= work
;
11719 spin_unlock_irq(&dev
->event_lock
);
11721 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
11722 flush_workqueue(dev_priv
->wq
);
11724 /* Reference the objects for the scheduled work. */
11725 drm_framebuffer_reference(work
->old_fb
);
11726 drm_gem_object_reference(&obj
->base
);
11728 crtc
->primary
->fb
= fb
;
11729 update_state_fb(crtc
->primary
);
11730 intel_fbc_pre_update(intel_crtc
);
11732 work
->pending_flip_obj
= obj
;
11734 ret
= i915_mutex_lock_interruptible(dev
);
11738 intel_crtc
->reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
11739 if (__i915_reset_in_progress_or_wedged(intel_crtc
->reset_counter
)) {
11744 atomic_inc(&intel_crtc
->unpin_work_count
);
11746 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
11747 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_G4X(pipe
)) + 1;
11749 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
11750 engine
= &dev_priv
->engine
[BCS
];
11751 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
11752 /* vlv: DISPLAY_FLIP fails to change tiling */
11754 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
11755 engine
= &dev_priv
->engine
[BCS
];
11756 } else if (INTEL_INFO(dev
)->gen
>= 7) {
11757 engine
= i915_gem_request_get_engine(obj
->last_write_req
);
11758 if (engine
== NULL
|| engine
->id
!= RCS
)
11759 engine
= &dev_priv
->engine
[BCS
];
11761 engine
= &dev_priv
->engine
[RCS
];
11764 mmio_flip
= use_mmio_flip(engine
, obj
);
11766 /* When using CS flips, we want to emit semaphores between rings.
11767 * However, when using mmio flips we will create a task to do the
11768 * synchronisation, so all we want here is to pin the framebuffer
11769 * into the display plane and skip any waits.
11772 ret
= i915_gem_object_sync(obj
, engine
, &request
);
11773 if (!ret
&& !request
) {
11774 request
= i915_gem_request_alloc(engine
, NULL
);
11775 ret
= PTR_ERR_OR_ZERO(request
);
11779 goto cleanup_pending
;
11782 ret
= intel_pin_and_fence_fb_obj(fb
, primary
->state
->rotation
);
11784 goto cleanup_pending
;
11786 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
),
11788 work
->gtt_offset
+= intel_crtc
->dspaddr_offset
;
11789 work
->rotation
= crtc
->primary
->state
->rotation
;
11792 INIT_WORK(&work
->mmio_work
, intel_mmio_flip_work_func
);
11794 i915_gem_request_assign(&work
->flip_queued_req
,
11795 obj
->last_write_req
);
11797 schedule_work(&work
->mmio_work
);
11799 i915_gem_request_assign(&work
->flip_queued_req
, request
);
11800 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, request
,
11803 goto cleanup_unpin
;
11805 intel_mark_page_flip_active(intel_crtc
, work
);
11807 i915_add_request_no_flush(request
);
11810 i915_gem_track_fb(intel_fb_obj(old_fb
), obj
,
11811 to_intel_plane(primary
)->frontbuffer_bit
);
11812 mutex_unlock(&dev
->struct_mutex
);
11814 intel_frontbuffer_flip_prepare(dev
,
11815 to_intel_plane(primary
)->frontbuffer_bit
);
11817 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11822 intel_unpin_fb_obj(fb
, crtc
->primary
->state
->rotation
);
11824 if (!IS_ERR_OR_NULL(request
))
11825 i915_add_request_no_flush(request
);
11826 atomic_dec(&intel_crtc
->unpin_work_count
);
11827 mutex_unlock(&dev
->struct_mutex
);
11829 crtc
->primary
->fb
= old_fb
;
11830 update_state_fb(crtc
->primary
);
11832 drm_gem_object_unreference_unlocked(&obj
->base
);
11833 drm_framebuffer_unreference(work
->old_fb
);
11835 spin_lock_irq(&dev
->event_lock
);
11836 intel_crtc
->flip_work
= NULL
;
11837 spin_unlock_irq(&dev
->event_lock
);
11839 drm_crtc_vblank_put(crtc
);
11844 struct drm_atomic_state
*state
;
11845 struct drm_plane_state
*plane_state
;
11848 state
= drm_atomic_state_alloc(dev
);
11851 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
11854 plane_state
= drm_atomic_get_plane_state(state
, primary
);
11855 ret
= PTR_ERR_OR_ZERO(plane_state
);
11857 drm_atomic_set_fb_for_plane(plane_state
, fb
);
11859 ret
= drm_atomic_set_crtc_for_plane(plane_state
, crtc
);
11861 ret
= drm_atomic_commit(state
);
11864 if (ret
== -EDEADLK
) {
11865 drm_modeset_backoff(state
->acquire_ctx
);
11866 drm_atomic_state_clear(state
);
11871 drm_atomic_state_free(state
);
11873 if (ret
== 0 && event
) {
11874 spin_lock_irq(&dev
->event_lock
);
11875 drm_crtc_send_vblank_event(crtc
, event
);
11876 spin_unlock_irq(&dev
->event_lock
);
11884 * intel_wm_need_update - Check whether watermarks need updating
11885 * @plane: drm plane
11886 * @state: new plane state
11888 * Check current plane state versus the new one to determine whether
11889 * watermarks need to be recalculated.
11891 * Returns true or false.
11893 static bool intel_wm_need_update(struct drm_plane
*plane
,
11894 struct drm_plane_state
*state
)
11896 struct intel_plane_state
*new = to_intel_plane_state(state
);
11897 struct intel_plane_state
*cur
= to_intel_plane_state(plane
->state
);
11899 /* Update watermarks on tiling or size changes. */
11900 if (new->visible
!= cur
->visible
)
11903 if (!cur
->base
.fb
|| !new->base
.fb
)
11906 if (cur
->base
.fb
->modifier
[0] != new->base
.fb
->modifier
[0] ||
11907 cur
->base
.rotation
!= new->base
.rotation
||
11908 drm_rect_width(&new->src
) != drm_rect_width(&cur
->src
) ||
11909 drm_rect_height(&new->src
) != drm_rect_height(&cur
->src
) ||
11910 drm_rect_width(&new->dst
) != drm_rect_width(&cur
->dst
) ||
11911 drm_rect_height(&new->dst
) != drm_rect_height(&cur
->dst
))
11917 static bool needs_scaling(struct intel_plane_state
*state
)
11919 int src_w
= drm_rect_width(&state
->src
) >> 16;
11920 int src_h
= drm_rect_height(&state
->src
) >> 16;
11921 int dst_w
= drm_rect_width(&state
->dst
);
11922 int dst_h
= drm_rect_height(&state
->dst
);
11924 return (src_w
!= dst_w
|| src_h
!= dst_h
);
11927 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
11928 struct drm_plane_state
*plane_state
)
11930 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc_state
);
11931 struct drm_crtc
*crtc
= crtc_state
->crtc
;
11932 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11933 struct drm_plane
*plane
= plane_state
->plane
;
11934 struct drm_device
*dev
= crtc
->dev
;
11935 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11936 struct intel_plane_state
*old_plane_state
=
11937 to_intel_plane_state(plane
->state
);
11938 bool mode_changed
= needs_modeset(crtc_state
);
11939 bool was_crtc_enabled
= crtc
->state
->active
;
11940 bool is_crtc_enabled
= crtc_state
->active
;
11941 bool turn_off
, turn_on
, visible
, was_visible
;
11942 struct drm_framebuffer
*fb
= plane_state
->fb
;
11945 if (crtc_state
&& INTEL_INFO(dev
)->gen
>= 9 &&
11946 plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11947 ret
= skl_update_scaler_plane(
11948 to_intel_crtc_state(crtc_state
),
11949 to_intel_plane_state(plane_state
));
11954 was_visible
= old_plane_state
->visible
;
11955 visible
= to_intel_plane_state(plane_state
)->visible
;
11957 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
11958 was_visible
= false;
11961 * Visibility is calculated as if the crtc was on, but
11962 * after scaler setup everything depends on it being off
11963 * when the crtc isn't active.
11965 * FIXME this is wrong for watermarks. Watermarks should also
11966 * be computed as if the pipe would be active. Perhaps move
11967 * per-plane wm computation to the .check_plane() hook, and
11968 * only combine the results from all planes in the current place?
11970 if (!is_crtc_enabled
)
11971 to_intel_plane_state(plane_state
)->visible
= visible
= false;
11973 if (!was_visible
&& !visible
)
11976 if (fb
!= old_plane_state
->base
.fb
)
11977 pipe_config
->fb_changed
= true;
11979 turn_off
= was_visible
&& (!visible
|| mode_changed
);
11980 turn_on
= visible
&& (!was_visible
|| mode_changed
);
11982 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11983 intel_crtc
->base
.base
.id
,
11984 intel_crtc
->base
.name
,
11985 plane
->base
.id
, plane
->name
,
11986 fb
? fb
->base
.id
: -1);
11988 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11989 plane
->base
.id
, plane
->name
,
11990 was_visible
, visible
,
11991 turn_off
, turn_on
, mode_changed
);
11994 pipe_config
->update_wm_pre
= true;
11996 /* must disable cxsr around plane enable/disable */
11997 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
11998 pipe_config
->disable_cxsr
= true;
11999 } else if (turn_off
) {
12000 pipe_config
->update_wm_post
= true;
12002 /* must disable cxsr around plane enable/disable */
12003 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
12004 pipe_config
->disable_cxsr
= true;
12005 } else if (intel_wm_need_update(plane
, plane_state
)) {
12006 /* FIXME bollocks */
12007 pipe_config
->update_wm_pre
= true;
12008 pipe_config
->update_wm_post
= true;
12011 /* Pre-gen9 platforms need two-step watermark updates */
12012 if ((pipe_config
->update_wm_pre
|| pipe_config
->update_wm_post
) &&
12013 INTEL_INFO(dev
)->gen
< 9 && dev_priv
->display
.optimize_watermarks
)
12014 to_intel_crtc_state(crtc_state
)->wm
.need_postvbl_update
= true;
12016 if (visible
|| was_visible
)
12017 pipe_config
->fb_bits
|= to_intel_plane(plane
)->frontbuffer_bit
;
12020 * WaCxSRDisabledForSpriteScaling:ivb
12022 * cstate->update_wm was already set above, so this flag will
12023 * take effect when we commit and program watermarks.
12025 if (plane
->type
== DRM_PLANE_TYPE_OVERLAY
&& IS_IVYBRIDGE(dev
) &&
12026 needs_scaling(to_intel_plane_state(plane_state
)) &&
12027 !needs_scaling(old_plane_state
))
12028 pipe_config
->disable_lp_wm
= true;
12033 static bool encoders_cloneable(const struct intel_encoder
*a
,
12034 const struct intel_encoder
*b
)
12036 /* masks could be asymmetric, so check both ways */
12037 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
12038 b
->cloneable
& (1 << a
->type
));
12041 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
12042 struct intel_crtc
*crtc
,
12043 struct intel_encoder
*encoder
)
12045 struct intel_encoder
*source_encoder
;
12046 struct drm_connector
*connector
;
12047 struct drm_connector_state
*connector_state
;
12050 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12051 if (connector_state
->crtc
!= &crtc
->base
)
12055 to_intel_encoder(connector_state
->best_encoder
);
12056 if (!encoders_cloneable(encoder
, source_encoder
))
12063 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
12064 struct intel_crtc
*crtc
)
12066 struct intel_encoder
*encoder
;
12067 struct drm_connector
*connector
;
12068 struct drm_connector_state
*connector_state
;
12071 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12072 if (connector_state
->crtc
!= &crtc
->base
)
12075 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12076 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
12083 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
12084 struct drm_crtc_state
*crtc_state
)
12086 struct drm_device
*dev
= crtc
->dev
;
12087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12088 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12089 struct intel_crtc_state
*pipe_config
=
12090 to_intel_crtc_state(crtc_state
);
12091 struct drm_atomic_state
*state
= crtc_state
->state
;
12093 bool mode_changed
= needs_modeset(crtc_state
);
12095 if (mode_changed
&& !check_encoder_cloning(state
, intel_crtc
)) {
12096 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12100 if (mode_changed
&& !crtc_state
->active
)
12101 pipe_config
->update_wm_post
= true;
12103 if (mode_changed
&& crtc_state
->enable
&&
12104 dev_priv
->display
.crtc_compute_clock
&&
12105 !WARN_ON(pipe_config
->shared_dpll
)) {
12106 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
12112 if (crtc_state
->color_mgmt_changed
) {
12113 ret
= intel_color_check(crtc
, crtc_state
);
12119 if (dev_priv
->display
.compute_pipe_wm
) {
12120 ret
= dev_priv
->display
.compute_pipe_wm(pipe_config
);
12122 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12127 if (dev_priv
->display
.compute_intermediate_wm
&&
12128 !to_intel_atomic_state(state
)->skip_intermediate_wm
) {
12129 if (WARN_ON(!dev_priv
->display
.compute_pipe_wm
))
12133 * Calculate 'intermediate' watermarks that satisfy both the
12134 * old state and the new state. We can program these
12137 ret
= dev_priv
->display
.compute_intermediate_wm(crtc
->dev
,
12141 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12144 } else if (dev_priv
->display
.compute_intermediate_wm
) {
12145 if (HAS_PCH_SPLIT(dev_priv
) && INTEL_GEN(dev_priv
) < 9)
12146 pipe_config
->wm
.ilk
.intermediate
= pipe_config
->wm
.ilk
.optimal
;
12149 if (INTEL_INFO(dev
)->gen
>= 9) {
12151 ret
= skl_update_scaler_crtc(pipe_config
);
12154 ret
= intel_atomic_setup_scalers(dev
, intel_crtc
,
12161 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
12162 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
12163 .atomic_begin
= intel_begin_crtc_commit
,
12164 .atomic_flush
= intel_finish_crtc_commit
,
12165 .atomic_check
= intel_crtc_atomic_check
,
12168 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
12170 struct intel_connector
*connector
;
12172 for_each_intel_connector(dev
, connector
) {
12173 if (connector
->base
.state
->crtc
)
12174 drm_connector_unreference(&connector
->base
);
12176 if (connector
->base
.encoder
) {
12177 connector
->base
.state
->best_encoder
=
12178 connector
->base
.encoder
;
12179 connector
->base
.state
->crtc
=
12180 connector
->base
.encoder
->crtc
;
12182 drm_connector_reference(&connector
->base
);
12184 connector
->base
.state
->best_encoder
= NULL
;
12185 connector
->base
.state
->crtc
= NULL
;
12191 connected_sink_compute_bpp(struct intel_connector
*connector
,
12192 struct intel_crtc_state
*pipe_config
)
12194 int bpp
= pipe_config
->pipe_bpp
;
12196 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12197 connector
->base
.base
.id
,
12198 connector
->base
.name
);
12200 /* Don't use an invalid EDID bpc value */
12201 if (connector
->base
.display_info
.bpc
&&
12202 connector
->base
.display_info
.bpc
* 3 < bpp
) {
12203 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12204 bpp
, connector
->base
.display_info
.bpc
*3);
12205 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
12208 /* Clamp bpp to default limit on screens without EDID 1.4 */
12209 if (connector
->base
.display_info
.bpc
== 0) {
12210 int type
= connector
->base
.connector_type
;
12211 int clamp_bpp
= 24;
12213 /* Fall back to 18 bpp when DP sink capability is unknown. */
12214 if (type
== DRM_MODE_CONNECTOR_DisplayPort
||
12215 type
== DRM_MODE_CONNECTOR_eDP
)
12218 if (bpp
> clamp_bpp
) {
12219 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12221 pipe_config
->pipe_bpp
= clamp_bpp
;
12227 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
12228 struct intel_crtc_state
*pipe_config
)
12230 struct drm_device
*dev
= crtc
->base
.dev
;
12231 struct drm_atomic_state
*state
;
12232 struct drm_connector
*connector
;
12233 struct drm_connector_state
*connector_state
;
12236 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)))
12238 else if (INTEL_INFO(dev
)->gen
>= 5)
12244 pipe_config
->pipe_bpp
= bpp
;
12246 state
= pipe_config
->base
.state
;
12248 /* Clamp display bpp to EDID value */
12249 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12250 if (connector_state
->crtc
!= &crtc
->base
)
12253 connected_sink_compute_bpp(to_intel_connector(connector
),
12260 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
12262 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12263 "type: 0x%x flags: 0x%x\n",
12265 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
12266 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
12267 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
12268 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
12271 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
12272 struct intel_crtc_state
*pipe_config
,
12273 const char *context
)
12275 struct drm_device
*dev
= crtc
->base
.dev
;
12276 struct drm_plane
*plane
;
12277 struct intel_plane
*intel_plane
;
12278 struct intel_plane_state
*state
;
12279 struct drm_framebuffer
*fb
;
12281 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12282 crtc
->base
.base
.id
, crtc
->base
.name
,
12283 context
, pipe_config
, pipe_name(crtc
->pipe
));
12285 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config
->cpu_transcoder
));
12286 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12287 pipe_config
->pipe_bpp
, pipe_config
->dither
);
12288 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12289 pipe_config
->has_pch_encoder
,
12290 pipe_config
->fdi_lanes
,
12291 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
12292 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
12293 pipe_config
->fdi_m_n
.tu
);
12294 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12295 pipe_config
->has_dp_encoder
,
12296 pipe_config
->lane_count
,
12297 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
12298 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
12299 pipe_config
->dp_m_n
.tu
);
12301 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12302 pipe_config
->has_dp_encoder
,
12303 pipe_config
->lane_count
,
12304 pipe_config
->dp_m2_n2
.gmch_m
,
12305 pipe_config
->dp_m2_n2
.gmch_n
,
12306 pipe_config
->dp_m2_n2
.link_m
,
12307 pipe_config
->dp_m2_n2
.link_n
,
12308 pipe_config
->dp_m2_n2
.tu
);
12310 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12311 pipe_config
->has_audio
,
12312 pipe_config
->has_infoframe
);
12314 DRM_DEBUG_KMS("requested mode:\n");
12315 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
12316 DRM_DEBUG_KMS("adjusted mode:\n");
12317 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
12318 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
12319 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
12320 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12321 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
12322 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12324 pipe_config
->scaler_state
.scaler_users
,
12325 pipe_config
->scaler_state
.scaler_id
);
12326 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12327 pipe_config
->gmch_pfit
.control
,
12328 pipe_config
->gmch_pfit
.pgm_ratios
,
12329 pipe_config
->gmch_pfit
.lvds_border_bits
);
12330 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12331 pipe_config
->pch_pfit
.pos
,
12332 pipe_config
->pch_pfit
.size
,
12333 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
12334 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
12335 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
12337 if (IS_BROXTON(dev
)) {
12338 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12339 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12340 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12341 pipe_config
->ddi_pll_sel
,
12342 pipe_config
->dpll_hw_state
.ebb0
,
12343 pipe_config
->dpll_hw_state
.ebb4
,
12344 pipe_config
->dpll_hw_state
.pll0
,
12345 pipe_config
->dpll_hw_state
.pll1
,
12346 pipe_config
->dpll_hw_state
.pll2
,
12347 pipe_config
->dpll_hw_state
.pll3
,
12348 pipe_config
->dpll_hw_state
.pll6
,
12349 pipe_config
->dpll_hw_state
.pll8
,
12350 pipe_config
->dpll_hw_state
.pll9
,
12351 pipe_config
->dpll_hw_state
.pll10
,
12352 pipe_config
->dpll_hw_state
.pcsdw12
);
12353 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
12354 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12355 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12356 pipe_config
->ddi_pll_sel
,
12357 pipe_config
->dpll_hw_state
.ctrl1
,
12358 pipe_config
->dpll_hw_state
.cfgcr1
,
12359 pipe_config
->dpll_hw_state
.cfgcr2
);
12360 } else if (HAS_DDI(dev
)) {
12361 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12362 pipe_config
->ddi_pll_sel
,
12363 pipe_config
->dpll_hw_state
.wrpll
,
12364 pipe_config
->dpll_hw_state
.spll
);
12366 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12367 "fp0: 0x%x, fp1: 0x%x\n",
12368 pipe_config
->dpll_hw_state
.dpll
,
12369 pipe_config
->dpll_hw_state
.dpll_md
,
12370 pipe_config
->dpll_hw_state
.fp0
,
12371 pipe_config
->dpll_hw_state
.fp1
);
12374 DRM_DEBUG_KMS("planes on this crtc\n");
12375 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
12376 intel_plane
= to_intel_plane(plane
);
12377 if (intel_plane
->pipe
!= crtc
->pipe
)
12380 state
= to_intel_plane_state(plane
->state
);
12381 fb
= state
->base
.fb
;
12383 DRM_DEBUG_KMS("%s [PLANE:%d:%s] plane: %u.%u idx: %d "
12384 "disabled, scaler_id = %d\n",
12385 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12386 plane
->base
.id
, plane
->name
,
12388 (crtc
->base
.primary
== plane
) ? 0 : intel_plane
->plane
+ 1,
12389 drm_plane_index(plane
), state
->scaler_id
);
12393 DRM_DEBUG_KMS("%s [PLANE:%d:%s] plane: %u.%u idx: %d enabled",
12394 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12395 plane
->base
.id
, plane
->name
,
12397 crtc
->base
.primary
== plane
? 0 : intel_plane
->plane
+ 1,
12398 drm_plane_index(plane
));
12399 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12400 fb
->base
.id
, fb
->width
, fb
->height
, fb
->pixel_format
);
12401 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12403 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
12404 drm_rect_width(&state
->src
) >> 16,
12405 drm_rect_height(&state
->src
) >> 16,
12406 state
->dst
.x1
, state
->dst
.y1
,
12407 drm_rect_width(&state
->dst
), drm_rect_height(&state
->dst
));
12411 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
12413 struct drm_device
*dev
= state
->dev
;
12414 struct drm_connector
*connector
;
12415 unsigned int used_ports
= 0;
12418 * Walk the connector list instead of the encoder
12419 * list to detect the problem on ddi platforms
12420 * where there's just one encoder per digital port.
12422 drm_for_each_connector(connector
, dev
) {
12423 struct drm_connector_state
*connector_state
;
12424 struct intel_encoder
*encoder
;
12426 connector_state
= drm_atomic_get_existing_connector_state(state
, connector
);
12427 if (!connector_state
)
12428 connector_state
= connector
->state
;
12430 if (!connector_state
->best_encoder
)
12433 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12435 WARN_ON(!connector_state
->crtc
);
12437 switch (encoder
->type
) {
12438 unsigned int port_mask
;
12439 case INTEL_OUTPUT_UNKNOWN
:
12440 if (WARN_ON(!HAS_DDI(dev
)))
12442 case INTEL_OUTPUT_DISPLAYPORT
:
12443 case INTEL_OUTPUT_HDMI
:
12444 case INTEL_OUTPUT_EDP
:
12445 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
12447 /* the same port mustn't appear more than once */
12448 if (used_ports
& port_mask
)
12451 used_ports
|= port_mask
;
12461 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
12463 struct drm_crtc_state tmp_state
;
12464 struct intel_crtc_scaler_state scaler_state
;
12465 struct intel_dpll_hw_state dpll_hw_state
;
12466 struct intel_shared_dpll
*shared_dpll
;
12467 uint32_t ddi_pll_sel
;
12470 /* FIXME: before the switch to atomic started, a new pipe_config was
12471 * kzalloc'd. Code that depends on any field being zero should be
12472 * fixed, so that the crtc_state can be safely duplicated. For now,
12473 * only fields that are know to not cause problems are preserved. */
12475 tmp_state
= crtc_state
->base
;
12476 scaler_state
= crtc_state
->scaler_state
;
12477 shared_dpll
= crtc_state
->shared_dpll
;
12478 dpll_hw_state
= crtc_state
->dpll_hw_state
;
12479 ddi_pll_sel
= crtc_state
->ddi_pll_sel
;
12480 force_thru
= crtc_state
->pch_pfit
.force_thru
;
12482 memset(crtc_state
, 0, sizeof *crtc_state
);
12484 crtc_state
->base
= tmp_state
;
12485 crtc_state
->scaler_state
= scaler_state
;
12486 crtc_state
->shared_dpll
= shared_dpll
;
12487 crtc_state
->dpll_hw_state
= dpll_hw_state
;
12488 crtc_state
->ddi_pll_sel
= ddi_pll_sel
;
12489 crtc_state
->pch_pfit
.force_thru
= force_thru
;
12493 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
12494 struct intel_crtc_state
*pipe_config
)
12496 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12497 struct intel_encoder
*encoder
;
12498 struct drm_connector
*connector
;
12499 struct drm_connector_state
*connector_state
;
12500 int base_bpp
, ret
= -EINVAL
;
12504 clear_intel_crtc_state(pipe_config
);
12506 pipe_config
->cpu_transcoder
=
12507 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
12510 * Sanitize sync polarity flags based on requested ones. If neither
12511 * positive or negative polarity is requested, treat this as meaning
12512 * negative polarity.
12514 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12515 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
12516 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
12518 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12519 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
12520 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
12522 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
12528 * Determine the real pipe dimensions. Note that stereo modes can
12529 * increase the actual pipe size due to the frame doubling and
12530 * insertion of additional space for blanks between the frame. This
12531 * is stored in the crtc timings. We use the requested mode to do this
12532 * computation to clearly distinguish it from the adjusted mode, which
12533 * can be changed by the connectors in the below retry loop.
12535 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
12536 &pipe_config
->pipe_src_w
,
12537 &pipe_config
->pipe_src_h
);
12540 /* Ensure the port clock defaults are reset when retrying. */
12541 pipe_config
->port_clock
= 0;
12542 pipe_config
->pixel_multiplier
= 1;
12544 /* Fill in default crtc timings, allow encoders to overwrite them. */
12545 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
12546 CRTC_STEREO_DOUBLE
);
12548 /* Pass our mode to the connectors and the CRTC to give them a chance to
12549 * adjust it according to limitations or connector properties, and also
12550 * a chance to reject the mode entirely.
12552 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12553 if (connector_state
->crtc
!= crtc
)
12556 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12558 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
12559 DRM_DEBUG_KMS("Encoder config failure\n");
12564 /* Set default port clock if not overwritten by the encoder. Needs to be
12565 * done afterwards in case the encoder adjusts the mode. */
12566 if (!pipe_config
->port_clock
)
12567 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
12568 * pipe_config
->pixel_multiplier
;
12570 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
12572 DRM_DEBUG_KMS("CRTC fixup failed\n");
12576 if (ret
== RETRY
) {
12577 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
12582 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12584 goto encoder_retry
;
12587 /* Dithering seems to not pass-through bits correctly when it should, so
12588 * only enable it on 6bpc panels. */
12589 pipe_config
->dither
= pipe_config
->pipe_bpp
== 6*3;
12590 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12591 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
12598 intel_modeset_update_crtc_state(struct drm_atomic_state
*state
)
12600 struct drm_crtc
*crtc
;
12601 struct drm_crtc_state
*crtc_state
;
12604 /* Double check state. */
12605 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12606 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(crtc
->state
);
12608 /* Update hwmode for vblank functions */
12609 if (crtc
->state
->active
)
12610 crtc
->hwmode
= crtc
->state
->adjusted_mode
;
12612 crtc
->hwmode
.crtc_clock
= 0;
12615 * Update legacy state to satisfy fbc code. This can
12616 * be removed when fbc uses the atomic state.
12618 if (drm_atomic_get_existing_plane_state(state
, crtc
->primary
)) {
12619 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
12621 crtc
->primary
->fb
= plane_state
->fb
;
12622 crtc
->x
= plane_state
->src_x
>> 16;
12623 crtc
->y
= plane_state
->src_y
>> 16;
12628 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
12632 if (clock1
== clock2
)
12635 if (!clock1
|| !clock2
)
12638 diff
= abs(clock1
- clock2
);
12640 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
12646 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12647 list_for_each_entry((intel_crtc), \
12648 &(dev)->mode_config.crtc_list, \
12650 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12653 intel_compare_m_n(unsigned int m
, unsigned int n
,
12654 unsigned int m2
, unsigned int n2
,
12657 if (m
== m2
&& n
== n2
)
12660 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
12663 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
12670 } else if (n
< n2
) {
12680 return intel_fuzzy_clock_check(m
, m2
);
12684 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
12685 struct intel_link_m_n
*m2_n2
,
12688 if (m_n
->tu
== m2_n2
->tu
&&
12689 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
12690 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
12691 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
12692 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
12703 intel_pipe_config_compare(struct drm_device
*dev
,
12704 struct intel_crtc_state
*current_config
,
12705 struct intel_crtc_state
*pipe_config
,
12710 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12713 DRM_ERROR(fmt, ##__VA_ARGS__); \
12715 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12718 #define PIPE_CONF_CHECK_X(name) \
12719 if (current_config->name != pipe_config->name) { \
12720 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12721 "(expected 0x%08x, found 0x%08x)\n", \
12722 current_config->name, \
12723 pipe_config->name); \
12727 #define PIPE_CONF_CHECK_I(name) \
12728 if (current_config->name != pipe_config->name) { \
12729 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12730 "(expected %i, found %i)\n", \
12731 current_config->name, \
12732 pipe_config->name); \
12736 #define PIPE_CONF_CHECK_P(name) \
12737 if (current_config->name != pipe_config->name) { \
12738 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12739 "(expected %p, found %p)\n", \
12740 current_config->name, \
12741 pipe_config->name); \
12745 #define PIPE_CONF_CHECK_M_N(name) \
12746 if (!intel_compare_link_m_n(¤t_config->name, \
12747 &pipe_config->name,\
12749 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12750 "(expected tu %i gmch %i/%i link %i/%i, " \
12751 "found tu %i, gmch %i/%i link %i/%i)\n", \
12752 current_config->name.tu, \
12753 current_config->name.gmch_m, \
12754 current_config->name.gmch_n, \
12755 current_config->name.link_m, \
12756 current_config->name.link_n, \
12757 pipe_config->name.tu, \
12758 pipe_config->name.gmch_m, \
12759 pipe_config->name.gmch_n, \
12760 pipe_config->name.link_m, \
12761 pipe_config->name.link_n); \
12765 /* This is required for BDW+ where there is only one set of registers for
12766 * switching between high and low RR.
12767 * This macro can be used whenever a comparison has to be made between one
12768 * hw state and multiple sw state variables.
12770 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12771 if (!intel_compare_link_m_n(¤t_config->name, \
12772 &pipe_config->name, adjust) && \
12773 !intel_compare_link_m_n(¤t_config->alt_name, \
12774 &pipe_config->name, adjust)) { \
12775 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12776 "(expected tu %i gmch %i/%i link %i/%i, " \
12777 "or tu %i gmch %i/%i link %i/%i, " \
12778 "found tu %i, gmch %i/%i link %i/%i)\n", \
12779 current_config->name.tu, \
12780 current_config->name.gmch_m, \
12781 current_config->name.gmch_n, \
12782 current_config->name.link_m, \
12783 current_config->name.link_n, \
12784 current_config->alt_name.tu, \
12785 current_config->alt_name.gmch_m, \
12786 current_config->alt_name.gmch_n, \
12787 current_config->alt_name.link_m, \
12788 current_config->alt_name.link_n, \
12789 pipe_config->name.tu, \
12790 pipe_config->name.gmch_m, \
12791 pipe_config->name.gmch_n, \
12792 pipe_config->name.link_m, \
12793 pipe_config->name.link_n); \
12797 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12798 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12799 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12800 "(expected %i, found %i)\n", \
12801 current_config->name & (mask), \
12802 pipe_config->name & (mask)); \
12806 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12807 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12808 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12809 "(expected %i, found %i)\n", \
12810 current_config->name, \
12811 pipe_config->name); \
12815 #define PIPE_CONF_QUIRK(quirk) \
12816 ((current_config->quirks | pipe_config->quirks) & (quirk))
12818 PIPE_CONF_CHECK_I(cpu_transcoder
);
12820 PIPE_CONF_CHECK_I(has_pch_encoder
);
12821 PIPE_CONF_CHECK_I(fdi_lanes
);
12822 PIPE_CONF_CHECK_M_N(fdi_m_n
);
12824 PIPE_CONF_CHECK_I(has_dp_encoder
);
12825 PIPE_CONF_CHECK_I(lane_count
);
12827 if (INTEL_INFO(dev
)->gen
< 8) {
12828 PIPE_CONF_CHECK_M_N(dp_m_n
);
12830 if (current_config
->has_drrs
)
12831 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
12833 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
12835 PIPE_CONF_CHECK_I(has_dsi_encoder
);
12837 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12838 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12839 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12840 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12841 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12842 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12844 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12845 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12846 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12847 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12848 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12849 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12851 PIPE_CONF_CHECK_I(pixel_multiplier
);
12852 PIPE_CONF_CHECK_I(has_hdmi_sink
);
12853 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
12854 IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
12855 PIPE_CONF_CHECK_I(limited_color_range
);
12856 PIPE_CONF_CHECK_I(has_infoframe
);
12858 PIPE_CONF_CHECK_I(has_audio
);
12860 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12861 DRM_MODE_FLAG_INTERLACE
);
12863 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12864 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12865 DRM_MODE_FLAG_PHSYNC
);
12866 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12867 DRM_MODE_FLAG_NHSYNC
);
12868 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12869 DRM_MODE_FLAG_PVSYNC
);
12870 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12871 DRM_MODE_FLAG_NVSYNC
);
12874 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
12875 /* pfit ratios are autocomputed by the hw on gen4+ */
12876 if (INTEL_INFO(dev
)->gen
< 4)
12877 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
12878 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
12881 PIPE_CONF_CHECK_I(pipe_src_w
);
12882 PIPE_CONF_CHECK_I(pipe_src_h
);
12884 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
12885 if (current_config
->pch_pfit
.enabled
) {
12886 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
12887 PIPE_CONF_CHECK_X(pch_pfit
.size
);
12890 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12893 /* BDW+ don't expose a synchronous way to read the state */
12894 if (IS_HASWELL(dev
))
12895 PIPE_CONF_CHECK_I(ips_enabled
);
12897 PIPE_CONF_CHECK_I(double_wide
);
12899 PIPE_CONF_CHECK_X(ddi_pll_sel
);
12901 PIPE_CONF_CHECK_P(shared_dpll
);
12902 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12903 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12904 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12905 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12906 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12907 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
12908 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12909 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12910 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12912 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
12913 PIPE_CONF_CHECK_X(dsi_pll
.div
);
12915 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
12916 PIPE_CONF_CHECK_I(pipe_bpp
);
12918 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12919 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12921 #undef PIPE_CONF_CHECK_X
12922 #undef PIPE_CONF_CHECK_I
12923 #undef PIPE_CONF_CHECK_P
12924 #undef PIPE_CONF_CHECK_FLAGS
12925 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12926 #undef PIPE_CONF_QUIRK
12927 #undef INTEL_ERR_OR_DBG_KMS
12932 static void intel_pipe_config_sanity_check(struct drm_i915_private
*dev_priv
,
12933 const struct intel_crtc_state
*pipe_config
)
12935 if (pipe_config
->has_pch_encoder
) {
12936 int fdi_dotclock
= intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
12937 &pipe_config
->fdi_m_n
);
12938 int dotclock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
12941 * FDI already provided one idea for the dotclock.
12942 * Yell if the encoder disagrees.
12944 WARN(!intel_fuzzy_clock_check(fdi_dotclock
, dotclock
),
12945 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12946 fdi_dotclock
, dotclock
);
12950 static void verify_wm_state(struct drm_crtc
*crtc
,
12951 struct drm_crtc_state
*new_state
)
12953 struct drm_device
*dev
= crtc
->dev
;
12954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12955 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
12956 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
12957 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12958 const enum pipe pipe
= intel_crtc
->pipe
;
12961 if (INTEL_INFO(dev
)->gen
< 9 || !new_state
->active
)
12964 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
12965 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12968 for_each_plane(dev_priv
, pipe
, plane
) {
12969 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
12970 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
12972 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12975 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12976 "(expected (%u,%u), found (%u,%u))\n",
12977 pipe_name(pipe
), plane
+ 1,
12978 sw_entry
->start
, sw_entry
->end
,
12979 hw_entry
->start
, hw_entry
->end
);
12983 hw_entry
= &hw_ddb
.plane
[pipe
][PLANE_CURSOR
];
12984 sw_entry
= &sw_ddb
->plane
[pipe
][PLANE_CURSOR
];
12986 if (!skl_ddb_entry_equal(hw_entry
, sw_entry
)) {
12987 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12988 "(expected (%u,%u), found (%u,%u))\n",
12990 sw_entry
->start
, sw_entry
->end
,
12991 hw_entry
->start
, hw_entry
->end
);
12996 verify_connector_state(struct drm_device
*dev
, struct drm_crtc
*crtc
)
12998 struct drm_connector
*connector
;
13000 drm_for_each_connector(connector
, dev
) {
13001 struct drm_encoder
*encoder
= connector
->encoder
;
13002 struct drm_connector_state
*state
= connector
->state
;
13004 if (state
->crtc
!= crtc
)
13007 intel_connector_verify_state(to_intel_connector(connector
));
13009 I915_STATE_WARN(state
->best_encoder
!= encoder
,
13010 "connector's atomic encoder doesn't match legacy encoder\n");
13015 verify_encoder_state(struct drm_device
*dev
)
13017 struct intel_encoder
*encoder
;
13018 struct intel_connector
*connector
;
13020 for_each_intel_encoder(dev
, encoder
) {
13021 bool enabled
= false;
13024 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13025 encoder
->base
.base
.id
,
13026 encoder
->base
.name
);
13028 for_each_intel_connector(dev
, connector
) {
13029 if (connector
->base
.state
->best_encoder
!= &encoder
->base
)
13033 I915_STATE_WARN(connector
->base
.state
->crtc
!=
13034 encoder
->base
.crtc
,
13035 "connector's crtc doesn't match encoder crtc\n");
13038 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
13039 "encoder's enabled state mismatch "
13040 "(expected %i, found %i)\n",
13041 !!encoder
->base
.crtc
, enabled
);
13043 if (!encoder
->base
.crtc
) {
13046 active
= encoder
->get_hw_state(encoder
, &pipe
);
13047 I915_STATE_WARN(active
,
13048 "encoder detached but still enabled on pipe %c.\n",
13055 verify_crtc_state(struct drm_crtc
*crtc
,
13056 struct drm_crtc_state
*old_crtc_state
,
13057 struct drm_crtc_state
*new_crtc_state
)
13059 struct drm_device
*dev
= crtc
->dev
;
13060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13061 struct intel_encoder
*encoder
;
13062 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13063 struct intel_crtc_state
*pipe_config
, *sw_config
;
13064 struct drm_atomic_state
*old_state
;
13067 old_state
= old_crtc_state
->state
;
13068 __drm_atomic_helper_crtc_destroy_state(crtc
, old_crtc_state
);
13069 pipe_config
= to_intel_crtc_state(old_crtc_state
);
13070 memset(pipe_config
, 0, sizeof(*pipe_config
));
13071 pipe_config
->base
.crtc
= crtc
;
13072 pipe_config
->base
.state
= old_state
;
13074 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc
->base
.id
, crtc
->name
);
13076 active
= dev_priv
->display
.get_pipe_config(intel_crtc
, pipe_config
);
13078 /* hw state is inconsistent with the pipe quirk */
13079 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
13080 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
13081 active
= new_crtc_state
->active
;
13083 I915_STATE_WARN(new_crtc_state
->active
!= active
,
13084 "crtc active state doesn't match with hw state "
13085 "(expected %i, found %i)\n", new_crtc_state
->active
, active
);
13087 I915_STATE_WARN(intel_crtc
->active
!= new_crtc_state
->active
,
13088 "transitional active state does not match atomic hw state "
13089 "(expected %i, found %i)\n", new_crtc_state
->active
, intel_crtc
->active
);
13091 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
13094 active
= encoder
->get_hw_state(encoder
, &pipe
);
13095 I915_STATE_WARN(active
!= new_crtc_state
->active
,
13096 "[ENCODER:%i] active %i with crtc active %i\n",
13097 encoder
->base
.base
.id
, active
, new_crtc_state
->active
);
13099 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
13100 "Encoder connected to wrong pipe %c\n",
13104 encoder
->get_config(encoder
, pipe_config
);
13107 if (!new_crtc_state
->active
)
13110 intel_pipe_config_sanity_check(dev_priv
, pipe_config
);
13112 sw_config
= to_intel_crtc_state(crtc
->state
);
13113 if (!intel_pipe_config_compare(dev
, sw_config
,
13114 pipe_config
, false)) {
13115 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13116 intel_dump_pipe_config(intel_crtc
, pipe_config
,
13118 intel_dump_pipe_config(intel_crtc
, sw_config
,
13124 verify_single_dpll_state(struct drm_i915_private
*dev_priv
,
13125 struct intel_shared_dpll
*pll
,
13126 struct drm_crtc
*crtc
,
13127 struct drm_crtc_state
*new_state
)
13129 struct intel_dpll_hw_state dpll_hw_state
;
13130 unsigned crtc_mask
;
13133 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
13135 DRM_DEBUG_KMS("%s\n", pll
->name
);
13137 active
= pll
->funcs
.get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
13139 if (!(pll
->flags
& INTEL_DPLL_ALWAYS_ON
)) {
13140 I915_STATE_WARN(!pll
->on
&& pll
->active_mask
,
13141 "pll in active use but not on in sw tracking\n");
13142 I915_STATE_WARN(pll
->on
&& !pll
->active_mask
,
13143 "pll is on but not used by any active crtc\n");
13144 I915_STATE_WARN(pll
->on
!= active
,
13145 "pll on state mismatch (expected %i, found %i)\n",
13150 I915_STATE_WARN(pll
->active_mask
& ~pll
->config
.crtc_mask
,
13151 "more active pll users than references: %x vs %x\n",
13152 pll
->active_mask
, pll
->config
.crtc_mask
);
13157 crtc_mask
= 1 << drm_crtc_index(crtc
);
13159 if (new_state
->active
)
13160 I915_STATE_WARN(!(pll
->active_mask
& crtc_mask
),
13161 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13162 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
13164 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13165 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13166 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
13168 I915_STATE_WARN(!(pll
->config
.crtc_mask
& crtc_mask
),
13169 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13170 crtc_mask
, pll
->config
.crtc_mask
);
13172 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
,
13174 sizeof(dpll_hw_state
)),
13175 "pll hw state mismatch\n");
13179 verify_shared_dpll_state(struct drm_device
*dev
, struct drm_crtc
*crtc
,
13180 struct drm_crtc_state
*old_crtc_state
,
13181 struct drm_crtc_state
*new_crtc_state
)
13183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13184 struct intel_crtc_state
*old_state
= to_intel_crtc_state(old_crtc_state
);
13185 struct intel_crtc_state
*new_state
= to_intel_crtc_state(new_crtc_state
);
13187 if (new_state
->shared_dpll
)
13188 verify_single_dpll_state(dev_priv
, new_state
->shared_dpll
, crtc
, new_crtc_state
);
13190 if (old_state
->shared_dpll
&&
13191 old_state
->shared_dpll
!= new_state
->shared_dpll
) {
13192 unsigned crtc_mask
= 1 << drm_crtc_index(crtc
);
13193 struct intel_shared_dpll
*pll
= old_state
->shared_dpll
;
13195 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13196 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13197 pipe_name(drm_crtc_index(crtc
)));
13198 I915_STATE_WARN(pll
->config
.crtc_mask
& crtc_mask
,
13199 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13200 pipe_name(drm_crtc_index(crtc
)));
13205 intel_modeset_verify_crtc(struct drm_crtc
*crtc
,
13206 struct drm_crtc_state
*old_state
,
13207 struct drm_crtc_state
*new_state
)
13209 if (!needs_modeset(new_state
) &&
13210 !to_intel_crtc_state(new_state
)->update_pipe
)
13213 verify_wm_state(crtc
, new_state
);
13214 verify_connector_state(crtc
->dev
, crtc
);
13215 verify_crtc_state(crtc
, old_state
, new_state
);
13216 verify_shared_dpll_state(crtc
->dev
, crtc
, old_state
, new_state
);
13220 verify_disabled_dpll_state(struct drm_device
*dev
)
13222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13225 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++)
13226 verify_single_dpll_state(dev_priv
, &dev_priv
->shared_dplls
[i
], NULL
, NULL
);
13230 intel_modeset_verify_disabled(struct drm_device
*dev
)
13232 verify_encoder_state(dev
);
13233 verify_connector_state(dev
, NULL
);
13234 verify_disabled_dpll_state(dev
);
13237 static void update_scanline_offset(struct intel_crtc
*crtc
)
13239 struct drm_device
*dev
= crtc
->base
.dev
;
13242 * The scanline counter increments at the leading edge of hsync.
13244 * On most platforms it starts counting from vtotal-1 on the
13245 * first active line. That means the scanline counter value is
13246 * always one less than what we would expect. Ie. just after
13247 * start of vblank, which also occurs at start of hsync (on the
13248 * last active line), the scanline counter will read vblank_start-1.
13250 * On gen2 the scanline counter starts counting from 1 instead
13251 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13252 * to keep the value positive), instead of adding one.
13254 * On HSW+ the behaviour of the scanline counter depends on the output
13255 * type. For DP ports it behaves like most other platforms, but on HDMI
13256 * there's an extra 1 line difference. So we need to add two instead of
13257 * one to the value.
13259 if (IS_GEN2(dev
)) {
13260 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
13263 vtotal
= adjusted_mode
->crtc_vtotal
;
13264 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
13267 crtc
->scanline_offset
= vtotal
- 1;
13268 } else if (HAS_DDI(dev
) &&
13269 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
13270 crtc
->scanline_offset
= 2;
13272 crtc
->scanline_offset
= 1;
13275 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
13277 struct drm_device
*dev
= state
->dev
;
13278 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13279 struct intel_shared_dpll_config
*shared_dpll
= NULL
;
13280 struct drm_crtc
*crtc
;
13281 struct drm_crtc_state
*crtc_state
;
13284 if (!dev_priv
->display
.crtc_compute_clock
)
13287 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13288 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13289 struct intel_shared_dpll
*old_dpll
=
13290 to_intel_crtc_state(crtc
->state
)->shared_dpll
;
13292 if (!needs_modeset(crtc_state
))
13295 to_intel_crtc_state(crtc_state
)->shared_dpll
= NULL
;
13301 shared_dpll
= intel_atomic_get_shared_dpll_state(state
);
13303 intel_shared_dpll_config_put(shared_dpll
, old_dpll
, intel_crtc
);
13308 * This implements the workaround described in the "notes" section of the mode
13309 * set sequence documentation. When going from no pipes or single pipe to
13310 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13311 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13313 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
13315 struct drm_crtc_state
*crtc_state
;
13316 struct intel_crtc
*intel_crtc
;
13317 struct drm_crtc
*crtc
;
13318 struct intel_crtc_state
*first_crtc_state
= NULL
;
13319 struct intel_crtc_state
*other_crtc_state
= NULL
;
13320 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
13323 /* look at all crtc's that are going to be enabled in during modeset */
13324 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13325 intel_crtc
= to_intel_crtc(crtc
);
13327 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
13330 if (first_crtc_state
) {
13331 other_crtc_state
= to_intel_crtc_state(crtc_state
);
13334 first_crtc_state
= to_intel_crtc_state(crtc_state
);
13335 first_pipe
= intel_crtc
->pipe
;
13339 /* No workaround needed? */
13340 if (!first_crtc_state
)
13343 /* w/a possibly needed, check how many crtc's are already enabled. */
13344 for_each_intel_crtc(state
->dev
, intel_crtc
) {
13345 struct intel_crtc_state
*pipe_config
;
13347 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
13348 if (IS_ERR(pipe_config
))
13349 return PTR_ERR(pipe_config
);
13351 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
13353 if (!pipe_config
->base
.active
||
13354 needs_modeset(&pipe_config
->base
))
13357 /* 2 or more enabled crtcs means no need for w/a */
13358 if (enabled_pipe
!= INVALID_PIPE
)
13361 enabled_pipe
= intel_crtc
->pipe
;
13364 if (enabled_pipe
!= INVALID_PIPE
)
13365 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
13366 else if (other_crtc_state
)
13367 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
13372 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
13374 struct drm_crtc
*crtc
;
13375 struct drm_crtc_state
*crtc_state
;
13378 /* add all active pipes to the state */
13379 for_each_crtc(state
->dev
, crtc
) {
13380 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13381 if (IS_ERR(crtc_state
))
13382 return PTR_ERR(crtc_state
);
13384 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
13387 crtc_state
->mode_changed
= true;
13389 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13393 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13401 static int intel_modeset_checks(struct drm_atomic_state
*state
)
13403 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13404 struct drm_i915_private
*dev_priv
= state
->dev
->dev_private
;
13405 struct drm_crtc
*crtc
;
13406 struct drm_crtc_state
*crtc_state
;
13409 if (!check_digital_port_conflicts(state
)) {
13410 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13414 intel_state
->modeset
= true;
13415 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
13417 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13418 if (crtc_state
->active
)
13419 intel_state
->active_crtcs
|= 1 << i
;
13421 intel_state
->active_crtcs
&= ~(1 << i
);
13423 if (crtc_state
->active
!= crtc
->state
->active
)
13424 intel_state
->active_pipe_changes
|= drm_crtc_mask(crtc
);
13428 * See if the config requires any additional preparation, e.g.
13429 * to adjust global state with pipes off. We need to do this
13430 * here so we can get the modeset_pipe updated config for the new
13431 * mode set on this crtc. For other crtcs we need to use the
13432 * adjusted_mode bits in the crtc directly.
13434 if (dev_priv
->display
.modeset_calc_cdclk
) {
13435 if (!intel_state
->cdclk_pll_vco
)
13436 intel_state
->cdclk_pll_vco
= dev_priv
->cdclk_pll
.vco
;
13437 if (!intel_state
->cdclk_pll_vco
)
13438 intel_state
->cdclk_pll_vco
= dev_priv
->skl_preferred_vco_freq
;
13440 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
13444 if (intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
||
13445 intel_state
->cdclk_pll_vco
!= dev_priv
->cdclk_pll
.vco
)
13446 ret
= intel_modeset_all_pipes(state
);
13451 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13452 intel_state
->cdclk
, intel_state
->dev_cdclk
);
13454 to_intel_atomic_state(state
)->cdclk
= dev_priv
->atomic_cdclk_freq
;
13456 intel_modeset_clear_plls(state
);
13458 if (IS_HASWELL(dev_priv
))
13459 return haswell_mode_set_planes_workaround(state
);
13465 * Handle calculation of various watermark data at the end of the atomic check
13466 * phase. The code here should be run after the per-crtc and per-plane 'check'
13467 * handlers to ensure that all derived state has been updated.
13469 static int calc_watermark_data(struct drm_atomic_state
*state
)
13471 struct drm_device
*dev
= state
->dev
;
13472 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13474 /* Is there platform-specific watermark information to calculate? */
13475 if (dev_priv
->display
.compute_global_watermarks
)
13476 return dev_priv
->display
.compute_global_watermarks(state
);
13482 * intel_atomic_check - validate state object
13484 * @state: state to validate
13486 static int intel_atomic_check(struct drm_device
*dev
,
13487 struct drm_atomic_state
*state
)
13489 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13490 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13491 struct drm_crtc
*crtc
;
13492 struct drm_crtc_state
*crtc_state
;
13494 bool any_ms
= false;
13496 ret
= drm_atomic_helper_check_modeset(dev
, state
);
13500 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13501 struct intel_crtc_state
*pipe_config
=
13502 to_intel_crtc_state(crtc_state
);
13504 /* Catch I915_MODE_FLAG_INHERITED */
13505 if (crtc_state
->mode
.private_flags
!= crtc
->state
->mode
.private_flags
)
13506 crtc_state
->mode_changed
= true;
13508 if (!needs_modeset(crtc_state
))
13511 if (!crtc_state
->enable
) {
13516 /* FIXME: For only active_changed we shouldn't need to do any
13517 * state recomputation at all. */
13519 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13523 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
13525 intel_dump_pipe_config(to_intel_crtc(crtc
),
13526 pipe_config
, "[failed]");
13530 if (i915
.fastboot
&&
13531 intel_pipe_config_compare(dev
,
13532 to_intel_crtc_state(crtc
->state
),
13533 pipe_config
, true)) {
13534 crtc_state
->mode_changed
= false;
13535 to_intel_crtc_state(crtc_state
)->update_pipe
= true;
13538 if (needs_modeset(crtc_state
))
13541 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13545 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
13546 needs_modeset(crtc_state
) ?
13547 "[modeset]" : "[fastset]");
13551 ret
= intel_modeset_checks(state
);
13556 intel_state
->cdclk
= dev_priv
->cdclk_freq
;
13558 ret
= drm_atomic_helper_check_planes(dev
, state
);
13562 intel_fbc_choose_crtc(dev_priv
, state
);
13563 return calc_watermark_data(state
);
13566 static int intel_atomic_prepare_commit(struct drm_device
*dev
,
13567 struct drm_atomic_state
*state
,
13570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13571 struct drm_plane_state
*plane_state
;
13572 struct drm_crtc_state
*crtc_state
;
13573 struct drm_plane
*plane
;
13574 struct drm_crtc
*crtc
;
13578 DRM_DEBUG_KMS("i915 does not yet support nonblocking commit\n");
13582 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13583 if (state
->legacy_cursor_update
)
13586 ret
= intel_crtc_wait_for_pending_flips(crtc
);
13590 if (atomic_read(&to_intel_crtc(crtc
)->unpin_work_count
) >= 2)
13591 flush_workqueue(dev_priv
->wq
);
13594 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
13598 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
13599 mutex_unlock(&dev
->struct_mutex
);
13601 if (!ret
&& !nonblock
) {
13602 for_each_plane_in_state(state
, plane
, plane_state
, i
) {
13603 struct intel_plane_state
*intel_plane_state
=
13604 to_intel_plane_state(plane_state
);
13606 if (!intel_plane_state
->wait_req
)
13609 ret
= __i915_wait_request(intel_plane_state
->wait_req
,
13612 /* Any hang should be swallowed by the wait */
13613 WARN_ON(ret
== -EIO
);
13614 mutex_lock(&dev
->struct_mutex
);
13615 drm_atomic_helper_cleanup_planes(dev
, state
);
13616 mutex_unlock(&dev
->struct_mutex
);
13625 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
)
13627 struct drm_device
*dev
= crtc
->base
.dev
;
13629 if (!dev
->max_vblank_count
)
13630 return drm_accurate_vblank_count(&crtc
->base
);
13632 return dev
->driver
->get_vblank_counter(dev
, crtc
->pipe
);
13635 static void intel_atomic_wait_for_vblanks(struct drm_device
*dev
,
13636 struct drm_i915_private
*dev_priv
,
13637 unsigned crtc_mask
)
13639 unsigned last_vblank_count
[I915_MAX_PIPES
];
13646 for_each_pipe(dev_priv
, pipe
) {
13647 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
13649 if (!((1 << pipe
) & crtc_mask
))
13652 ret
= drm_crtc_vblank_get(crtc
);
13653 if (WARN_ON(ret
!= 0)) {
13654 crtc_mask
&= ~(1 << pipe
);
13658 last_vblank_count
[pipe
] = drm_crtc_vblank_count(crtc
);
13661 for_each_pipe(dev_priv
, pipe
) {
13662 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
13665 if (!((1 << pipe
) & crtc_mask
))
13668 lret
= wait_event_timeout(dev
->vblank
[pipe
].queue
,
13669 last_vblank_count
[pipe
] !=
13670 drm_crtc_vblank_count(crtc
),
13671 msecs_to_jiffies(50));
13673 WARN(!lret
, "pipe %c vblank wait timed out\n", pipe_name(pipe
));
13675 drm_crtc_vblank_put(crtc
);
13679 static bool needs_vblank_wait(struct intel_crtc_state
*crtc_state
)
13681 /* fb updated, need to unpin old fb */
13682 if (crtc_state
->fb_changed
)
13685 /* wm changes, need vblank before final wm's */
13686 if (crtc_state
->update_wm_post
)
13690 * cxsr is re-enabled after vblank.
13691 * This is already handled by crtc_state->update_wm_post,
13692 * but added for clarity.
13694 if (crtc_state
->disable_cxsr
)
13701 * intel_atomic_commit - commit validated state object
13703 * @state: the top-level driver state object
13704 * @nonblock: nonblocking commit
13706 * This function commits a top-level state object that has been validated
13707 * with drm_atomic_helper_check().
13709 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13710 * we can only handle plane-related operations and do not yet support
13711 * nonblocking commit.
13714 * Zero for success or -errno.
13716 static int intel_atomic_commit(struct drm_device
*dev
,
13717 struct drm_atomic_state
*state
,
13720 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13722 struct drm_crtc_state
*old_crtc_state
;
13723 struct drm_crtc
*crtc
;
13724 struct intel_crtc_state
*intel_cstate
;
13726 bool hw_check
= intel_state
->modeset
;
13727 unsigned long put_domains
[I915_MAX_PIPES
] = {};
13728 unsigned crtc_vblank_mask
= 0;
13730 ret
= intel_atomic_prepare_commit(dev
, state
, nonblock
);
13732 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret
);
13736 drm_atomic_helper_swap_state(dev
, state
);
13737 dev_priv
->wm
.distrust_bios_wm
= false;
13738 dev_priv
->wm
.skl_results
= intel_state
->wm_results
;
13739 intel_shared_dpll_commit(state
);
13741 if (intel_state
->modeset
) {
13742 memcpy(dev_priv
->min_pixclk
, intel_state
->min_pixclk
,
13743 sizeof(intel_state
->min_pixclk
));
13744 dev_priv
->active_crtcs
= intel_state
->active_crtcs
;
13745 dev_priv
->atomic_cdclk_freq
= intel_state
->cdclk
;
13747 intel_display_power_get(dev_priv
, POWER_DOMAIN_MODESET
);
13750 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13751 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13753 if (needs_modeset(crtc
->state
) ||
13754 to_intel_crtc_state(crtc
->state
)->update_pipe
) {
13757 put_domains
[to_intel_crtc(crtc
)->pipe
] =
13758 modeset_get_crtc_power_domains(crtc
,
13759 to_intel_crtc_state(crtc
->state
));
13762 if (!needs_modeset(crtc
->state
))
13765 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
13767 if (old_crtc_state
->active
) {
13768 intel_crtc_disable_planes(crtc
, old_crtc_state
->plane_mask
);
13769 dev_priv
->display
.crtc_disable(crtc
);
13770 intel_crtc
->active
= false;
13771 intel_fbc_disable(intel_crtc
);
13772 intel_disable_shared_dpll(intel_crtc
);
13775 * Underruns don't always raise
13776 * interrupts, so check manually.
13778 intel_check_cpu_fifo_underruns(dev_priv
);
13779 intel_check_pch_fifo_underruns(dev_priv
);
13781 if (!crtc
->state
->active
)
13782 intel_update_watermarks(crtc
);
13786 /* Only after disabling all output pipelines that will be changed can we
13787 * update the the output configuration. */
13788 intel_modeset_update_crtc_state(state
);
13790 if (intel_state
->modeset
) {
13791 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
13793 if (dev_priv
->display
.modeset_commit_cdclk
&&
13794 (intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
||
13795 intel_state
->cdclk_pll_vco
!= dev_priv
->cdclk_pll
.vco
))
13796 dev_priv
->display
.modeset_commit_cdclk(state
);
13798 intel_modeset_verify_disabled(dev
);
13801 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13802 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13803 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13804 bool modeset
= needs_modeset(crtc
->state
);
13805 struct intel_crtc_state
*pipe_config
=
13806 to_intel_crtc_state(crtc
->state
);
13807 bool update_pipe
= !modeset
&& pipe_config
->update_pipe
;
13809 if (modeset
&& crtc
->state
->active
) {
13810 update_scanline_offset(to_intel_crtc(crtc
));
13811 dev_priv
->display
.crtc_enable(crtc
);
13815 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
13817 if (crtc
->state
->active
&&
13818 drm_atomic_get_existing_plane_state(state
, crtc
->primary
))
13819 intel_fbc_enable(intel_crtc
);
13821 if (crtc
->state
->active
&&
13822 (crtc
->state
->planes_changed
|| update_pipe
))
13823 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state
);
13825 if (pipe_config
->base
.active
&& needs_vblank_wait(pipe_config
))
13826 crtc_vblank_mask
|= 1 << i
;
13829 /* FIXME: add subpixel order */
13831 if (!state
->legacy_cursor_update
)
13832 intel_atomic_wait_for_vblanks(dev
, dev_priv
, crtc_vblank_mask
);
13835 * Now that the vblank has passed, we can go ahead and program the
13836 * optimal watermarks on platforms that need two-step watermark
13839 * TODO: Move this (and other cleanup) to an async worker eventually.
13841 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13842 intel_cstate
= to_intel_crtc_state(crtc
->state
);
13844 if (dev_priv
->display
.optimize_watermarks
)
13845 dev_priv
->display
.optimize_watermarks(intel_cstate
);
13848 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13849 intel_post_plane_update(to_intel_crtc_state(old_crtc_state
));
13851 if (put_domains
[i
])
13852 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
13854 intel_modeset_verify_crtc(crtc
, old_crtc_state
, crtc
->state
);
13857 if (intel_state
->modeset
)
13858 intel_display_power_put(dev_priv
, POWER_DOMAIN_MODESET
);
13860 mutex_lock(&dev
->struct_mutex
);
13861 drm_atomic_helper_cleanup_planes(dev
, state
);
13862 mutex_unlock(&dev
->struct_mutex
);
13864 drm_atomic_state_free(state
);
13866 /* As one of the primary mmio accessors, KMS has a high likelihood
13867 * of triggering bugs in unclaimed access. After we finish
13868 * modesetting, see if an error has been flagged, and if so
13869 * enable debugging for the next modeset - and hope we catch
13872 * XXX note that we assume display power is on at this point.
13873 * This might hold true now but we need to add pm helper to check
13874 * unclaimed only when the hardware is on, as atomic commits
13875 * can happen also when the device is completely off.
13877 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
13882 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
13884 struct drm_device
*dev
= crtc
->dev
;
13885 struct drm_atomic_state
*state
;
13886 struct drm_crtc_state
*crtc_state
;
13889 state
= drm_atomic_state_alloc(dev
);
13891 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13892 crtc
->base
.id
, crtc
->name
);
13896 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
13899 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13900 ret
= PTR_ERR_OR_ZERO(crtc_state
);
13902 if (!crtc_state
->active
)
13905 crtc_state
->mode_changed
= true;
13906 ret
= drm_atomic_commit(state
);
13909 if (ret
== -EDEADLK
) {
13910 drm_atomic_state_clear(state
);
13911 drm_modeset_backoff(state
->acquire_ctx
);
13917 drm_atomic_state_free(state
);
13920 #undef for_each_intel_crtc_masked
13922 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13923 .gamma_set
= drm_atomic_helper_legacy_gamma_set
,
13924 .set_config
= drm_atomic_helper_set_config
,
13925 .set_property
= drm_atomic_helper_crtc_set_property
,
13926 .destroy
= intel_crtc_destroy
,
13927 .page_flip
= intel_crtc_page_flip
,
13928 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13929 .atomic_destroy_state
= intel_crtc_destroy_state
,
13933 * intel_prepare_plane_fb - Prepare fb for usage on plane
13934 * @plane: drm plane to prepare for
13935 * @fb: framebuffer to prepare for presentation
13937 * Prepares a framebuffer for usage on a display plane. Generally this
13938 * involves pinning the underlying object and updating the frontbuffer tracking
13939 * bits. Some older platforms need special physical address handling for
13942 * Must be called with struct_mutex held.
13944 * Returns 0 on success, negative error code on failure.
13947 intel_prepare_plane_fb(struct drm_plane
*plane
,
13948 const struct drm_plane_state
*new_state
)
13950 struct drm_device
*dev
= plane
->dev
;
13951 struct drm_framebuffer
*fb
= new_state
->fb
;
13952 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13953 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13954 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->state
->fb
);
13957 if (!obj
&& !old_obj
)
13961 struct drm_crtc_state
*crtc_state
=
13962 drm_atomic_get_existing_crtc_state(new_state
->state
, plane
->state
->crtc
);
13964 /* Big Hammer, we also need to ensure that any pending
13965 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13966 * current scanout is retired before unpinning the old
13967 * framebuffer. Note that we rely on userspace rendering
13968 * into the buffer attached to the pipe they are waiting
13969 * on. If not, userspace generates a GPU hang with IPEHR
13970 * point to the MI_WAIT_FOR_EVENT.
13972 * This should only fail upon a hung GPU, in which case we
13973 * can safely continue.
13975 if (needs_modeset(crtc_state
))
13976 ret
= i915_gem_object_wait_rendering(old_obj
, true);
13978 /* GPU hangs should have been swallowed by the wait */
13979 WARN_ON(ret
== -EIO
);
13984 /* For framebuffer backed by dmabuf, wait for fence */
13985 if (obj
&& obj
->base
.dma_buf
) {
13988 lret
= reservation_object_wait_timeout_rcu(obj
->base
.dma_buf
->resv
,
13990 MAX_SCHEDULE_TIMEOUT
);
13991 if (lret
== -ERESTARTSYS
)
13994 WARN(lret
< 0, "waiting returns %li\n", lret
);
13999 } else if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
14000 INTEL_INFO(dev
)->cursor_needs_physical
) {
14001 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
14002 ret
= i915_gem_object_attach_phys(obj
, align
);
14004 DRM_DEBUG_KMS("failed to attach phys object\n");
14006 ret
= intel_pin_and_fence_fb_obj(fb
, new_state
->rotation
);
14011 struct intel_plane_state
*plane_state
=
14012 to_intel_plane_state(new_state
);
14014 i915_gem_request_assign(&plane_state
->wait_req
,
14015 obj
->last_write_req
);
14018 i915_gem_track_fb(old_obj
, obj
, intel_plane
->frontbuffer_bit
);
14025 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14026 * @plane: drm plane to clean up for
14027 * @fb: old framebuffer that was on plane
14029 * Cleans up a framebuffer that has just been removed from a plane.
14031 * Must be called with struct_mutex held.
14034 intel_cleanup_plane_fb(struct drm_plane
*plane
,
14035 const struct drm_plane_state
*old_state
)
14037 struct drm_device
*dev
= plane
->dev
;
14038 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
14039 struct intel_plane_state
*old_intel_state
;
14040 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_state
->fb
);
14041 struct drm_i915_gem_object
*obj
= intel_fb_obj(plane
->state
->fb
);
14043 old_intel_state
= to_intel_plane_state(old_state
);
14045 if (!obj
&& !old_obj
)
14048 if (old_obj
&& (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
14049 !INTEL_INFO(dev
)->cursor_needs_physical
))
14050 intel_unpin_fb_obj(old_state
->fb
, old_state
->rotation
);
14052 /* prepare_fb aborted? */
14053 if ((old_obj
&& (old_obj
->frontbuffer_bits
& intel_plane
->frontbuffer_bit
)) ||
14054 (obj
&& !(obj
->frontbuffer_bits
& intel_plane
->frontbuffer_bit
)))
14055 i915_gem_track_fb(old_obj
, obj
, intel_plane
->frontbuffer_bit
);
14057 i915_gem_request_assign(&old_intel_state
->wait_req
, NULL
);
14061 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
14064 struct drm_device
*dev
;
14065 struct drm_i915_private
*dev_priv
;
14066 int crtc_clock
, cdclk
;
14068 if (!intel_crtc
|| !crtc_state
->base
.enable
)
14069 return DRM_PLANE_HELPER_NO_SCALING
;
14071 dev
= intel_crtc
->base
.dev
;
14072 dev_priv
= dev
->dev_private
;
14073 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
14074 cdclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
;
14076 if (WARN_ON_ONCE(!crtc_clock
|| cdclk
< crtc_clock
))
14077 return DRM_PLANE_HELPER_NO_SCALING
;
14080 * skl max scale is lower of:
14081 * close to 3 but not 3, -1 is for that purpose
14085 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
14091 intel_check_primary_plane(struct drm_plane
*plane
,
14092 struct intel_crtc_state
*crtc_state
,
14093 struct intel_plane_state
*state
)
14095 struct drm_crtc
*crtc
= state
->base
.crtc
;
14096 struct drm_framebuffer
*fb
= state
->base
.fb
;
14097 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
14098 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
14099 bool can_position
= false;
14101 if (INTEL_INFO(plane
->dev
)->gen
>= 9) {
14102 /* use scaler when colorkey is not required */
14103 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
14105 max_scale
= skl_max_scale(to_intel_crtc(crtc
), crtc_state
);
14107 can_position
= true;
14110 return drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
14111 &state
->dst
, &state
->clip
,
14112 min_scale
, max_scale
,
14113 can_position
, true,
14117 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
,
14118 struct drm_crtc_state
*old_crtc_state
)
14120 struct drm_device
*dev
= crtc
->dev
;
14121 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14122 struct intel_crtc_state
*old_intel_state
=
14123 to_intel_crtc_state(old_crtc_state
);
14124 bool modeset
= needs_modeset(crtc
->state
);
14126 /* Perform vblank evasion around commit operation */
14127 intel_pipe_update_start(intel_crtc
);
14132 if (crtc
->state
->color_mgmt_changed
|| to_intel_crtc_state(crtc
->state
)->update_pipe
) {
14133 intel_color_set_csc(crtc
->state
);
14134 intel_color_load_luts(crtc
->state
);
14137 if (to_intel_crtc_state(crtc
->state
)->update_pipe
)
14138 intel_update_pipe_config(intel_crtc
, old_intel_state
);
14139 else if (INTEL_INFO(dev
)->gen
>= 9)
14140 skl_detach_scalers(intel_crtc
);
14143 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
,
14144 struct drm_crtc_state
*old_crtc_state
)
14146 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14148 intel_pipe_update_end(intel_crtc
, NULL
);
14152 * intel_plane_destroy - destroy a plane
14153 * @plane: plane to destroy
14155 * Common destruction function for all types of planes (primary, cursor,
14158 void intel_plane_destroy(struct drm_plane
*plane
)
14160 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
14161 drm_plane_cleanup(plane
);
14162 kfree(intel_plane
);
14165 const struct drm_plane_funcs intel_plane_funcs
= {
14166 .update_plane
= drm_atomic_helper_update_plane
,
14167 .disable_plane
= drm_atomic_helper_disable_plane
,
14168 .destroy
= intel_plane_destroy
,
14169 .set_property
= drm_atomic_helper_plane_set_property
,
14170 .atomic_get_property
= intel_plane_atomic_get_property
,
14171 .atomic_set_property
= intel_plane_atomic_set_property
,
14172 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14173 .atomic_destroy_state
= intel_plane_destroy_state
,
14177 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
14180 struct intel_plane
*primary
= NULL
;
14181 struct intel_plane_state
*state
= NULL
;
14182 const uint32_t *intel_primary_formats
;
14183 unsigned int num_formats
;
14186 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
14190 state
= intel_create_plane_state(&primary
->base
);
14193 primary
->base
.state
= &state
->base
;
14195 primary
->can_scale
= false;
14196 primary
->max_downscale
= 1;
14197 if (INTEL_INFO(dev
)->gen
>= 9) {
14198 primary
->can_scale
= true;
14199 state
->scaler_id
= -1;
14201 primary
->pipe
= pipe
;
14202 primary
->plane
= pipe
;
14203 primary
->frontbuffer_bit
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
14204 primary
->check_plane
= intel_check_primary_plane
;
14205 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
14206 primary
->plane
= !pipe
;
14208 if (INTEL_INFO(dev
)->gen
>= 9) {
14209 intel_primary_formats
= skl_primary_formats
;
14210 num_formats
= ARRAY_SIZE(skl_primary_formats
);
14212 primary
->update_plane
= skylake_update_primary_plane
;
14213 primary
->disable_plane
= skylake_disable_primary_plane
;
14214 } else if (HAS_PCH_SPLIT(dev
)) {
14215 intel_primary_formats
= i965_primary_formats
;
14216 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14218 primary
->update_plane
= ironlake_update_primary_plane
;
14219 primary
->disable_plane
= i9xx_disable_primary_plane
;
14220 } else if (INTEL_INFO(dev
)->gen
>= 4) {
14221 intel_primary_formats
= i965_primary_formats
;
14222 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14224 primary
->update_plane
= i9xx_update_primary_plane
;
14225 primary
->disable_plane
= i9xx_disable_primary_plane
;
14227 intel_primary_formats
= i8xx_primary_formats
;
14228 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
14230 primary
->update_plane
= i9xx_update_primary_plane
;
14231 primary
->disable_plane
= i9xx_disable_primary_plane
;
14234 ret
= drm_universal_plane_init(dev
, &primary
->base
, 0,
14235 &intel_plane_funcs
,
14236 intel_primary_formats
, num_formats
,
14237 DRM_PLANE_TYPE_PRIMARY
, NULL
);
14241 if (INTEL_INFO(dev
)->gen
>= 4)
14242 intel_create_rotation_property(dev
, primary
);
14244 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
14246 return &primary
->base
;
14255 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
14257 if (!dev
->mode_config
.rotation_property
) {
14258 unsigned long flags
= BIT(DRM_ROTATE_0
) |
14259 BIT(DRM_ROTATE_180
);
14261 if (INTEL_INFO(dev
)->gen
>= 9)
14262 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
14264 dev
->mode_config
.rotation_property
=
14265 drm_mode_create_rotation_property(dev
, flags
);
14267 if (dev
->mode_config
.rotation_property
)
14268 drm_object_attach_property(&plane
->base
.base
,
14269 dev
->mode_config
.rotation_property
,
14270 plane
->base
.state
->rotation
);
14274 intel_check_cursor_plane(struct drm_plane
*plane
,
14275 struct intel_crtc_state
*crtc_state
,
14276 struct intel_plane_state
*state
)
14278 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
14279 struct drm_framebuffer
*fb
= state
->base
.fb
;
14280 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
14281 enum pipe pipe
= to_intel_plane(plane
)->pipe
;
14285 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
14286 &state
->dst
, &state
->clip
,
14287 DRM_PLANE_HELPER_NO_SCALING
,
14288 DRM_PLANE_HELPER_NO_SCALING
,
14289 true, true, &state
->visible
);
14293 /* if we want to turn off the cursor ignore width and height */
14297 /* Check for which cursor types we support */
14298 if (!cursor_size_ok(plane
->dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
14299 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14300 state
->base
.crtc_w
, state
->base
.crtc_h
);
14304 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
14305 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
14306 DRM_DEBUG_KMS("buffer is too small\n");
14310 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
14311 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14316 * There's something wrong with the cursor on CHV pipe C.
14317 * If it straddles the left edge of the screen then
14318 * moving it away from the edge or disabling it often
14319 * results in a pipe underrun, and often that can lead to
14320 * dead pipe (constant underrun reported, and it scans
14321 * out just a solid color). To recover from that, the
14322 * display power well must be turned off and on again.
14323 * Refuse the put the cursor into that compromised position.
14325 if (IS_CHERRYVIEW(plane
->dev
) && pipe
== PIPE_C
&&
14326 state
->visible
&& state
->base
.crtc_x
< 0) {
14327 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14335 intel_disable_cursor_plane(struct drm_plane
*plane
,
14336 struct drm_crtc
*crtc
)
14338 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14340 intel_crtc
->cursor_addr
= 0;
14341 intel_crtc_update_cursor(crtc
, NULL
);
14345 intel_update_cursor_plane(struct drm_plane
*plane
,
14346 const struct intel_crtc_state
*crtc_state
,
14347 const struct intel_plane_state
*state
)
14349 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
14350 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14351 struct drm_device
*dev
= plane
->dev
;
14352 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
14357 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
14358 addr
= i915_gem_obj_ggtt_offset(obj
);
14360 addr
= obj
->phys_handle
->busaddr
;
14362 intel_crtc
->cursor_addr
= addr
;
14363 intel_crtc_update_cursor(crtc
, state
);
14366 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
14369 struct intel_plane
*cursor
= NULL
;
14370 struct intel_plane_state
*state
= NULL
;
14373 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
14377 state
= intel_create_plane_state(&cursor
->base
);
14380 cursor
->base
.state
= &state
->base
;
14382 cursor
->can_scale
= false;
14383 cursor
->max_downscale
= 1;
14384 cursor
->pipe
= pipe
;
14385 cursor
->plane
= pipe
;
14386 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER_CURSOR(pipe
);
14387 cursor
->check_plane
= intel_check_cursor_plane
;
14388 cursor
->update_plane
= intel_update_cursor_plane
;
14389 cursor
->disable_plane
= intel_disable_cursor_plane
;
14391 ret
= drm_universal_plane_init(dev
, &cursor
->base
, 0,
14392 &intel_plane_funcs
,
14393 intel_cursor_formats
,
14394 ARRAY_SIZE(intel_cursor_formats
),
14395 DRM_PLANE_TYPE_CURSOR
, NULL
);
14399 if (INTEL_INFO(dev
)->gen
>= 4) {
14400 if (!dev
->mode_config
.rotation_property
)
14401 dev
->mode_config
.rotation_property
=
14402 drm_mode_create_rotation_property(dev
,
14403 BIT(DRM_ROTATE_0
) |
14404 BIT(DRM_ROTATE_180
));
14405 if (dev
->mode_config
.rotation_property
)
14406 drm_object_attach_property(&cursor
->base
.base
,
14407 dev
->mode_config
.rotation_property
,
14408 state
->base
.rotation
);
14411 if (INTEL_INFO(dev
)->gen
>=9)
14412 state
->scaler_id
= -1;
14414 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
14416 return &cursor
->base
;
14425 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
14426 struct intel_crtc_state
*crtc_state
)
14429 struct intel_scaler
*intel_scaler
;
14430 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
14432 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
14433 intel_scaler
= &scaler_state
->scalers
[i
];
14434 intel_scaler
->in_use
= 0;
14435 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
14438 scaler_state
->scaler_id
= -1;
14441 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
14443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14444 struct intel_crtc
*intel_crtc
;
14445 struct intel_crtc_state
*crtc_state
= NULL
;
14446 struct drm_plane
*primary
= NULL
;
14447 struct drm_plane
*cursor
= NULL
;
14450 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
14451 if (intel_crtc
== NULL
)
14454 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
14457 intel_crtc
->config
= crtc_state
;
14458 intel_crtc
->base
.state
= &crtc_state
->base
;
14459 crtc_state
->base
.crtc
= &intel_crtc
->base
;
14461 /* initialize shared scalers */
14462 if (INTEL_INFO(dev
)->gen
>= 9) {
14463 if (pipe
== PIPE_C
)
14464 intel_crtc
->num_scalers
= 1;
14466 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
14468 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
14471 primary
= intel_primary_plane_create(dev
, pipe
);
14475 cursor
= intel_cursor_plane_create(dev
, pipe
);
14479 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
14480 cursor
, &intel_crtc_funcs
, NULL
);
14485 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14486 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14488 intel_crtc
->pipe
= pipe
;
14489 intel_crtc
->plane
= pipe
;
14490 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
14491 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14492 intel_crtc
->plane
= !pipe
;
14495 intel_crtc
->cursor_base
= ~0;
14496 intel_crtc
->cursor_cntl
= ~0;
14497 intel_crtc
->cursor_size
= ~0;
14499 intel_crtc
->wm
.cxsr_allowed
= true;
14501 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
14502 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
14503 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
14504 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
14506 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
14508 intel_color_init(&intel_crtc
->base
);
14510 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
14515 drm_plane_cleanup(primary
);
14517 drm_plane_cleanup(cursor
);
14522 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
14524 struct drm_encoder
*encoder
= connector
->base
.encoder
;
14525 struct drm_device
*dev
= connector
->base
.dev
;
14527 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
14529 if (!encoder
|| WARN_ON(!encoder
->crtc
))
14530 return INVALID_PIPE
;
14532 return to_intel_crtc(encoder
->crtc
)->pipe
;
14535 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
14536 struct drm_file
*file
)
14538 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
14539 struct drm_crtc
*drmmode_crtc
;
14540 struct intel_crtc
*crtc
;
14542 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
14544 if (!drmmode_crtc
) {
14545 DRM_ERROR("no such CRTC id\n");
14549 crtc
= to_intel_crtc(drmmode_crtc
);
14550 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
14555 static int intel_encoder_clones(struct intel_encoder
*encoder
)
14557 struct drm_device
*dev
= encoder
->base
.dev
;
14558 struct intel_encoder
*source_encoder
;
14559 int index_mask
= 0;
14562 for_each_intel_encoder(dev
, source_encoder
) {
14563 if (encoders_cloneable(encoder
, source_encoder
))
14564 index_mask
|= (1 << entry
);
14572 static bool has_edp_a(struct drm_device
*dev
)
14574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14576 if (!IS_MOBILE(dev
))
14579 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
14582 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
14588 static bool intel_crt_present(struct drm_device
*dev
)
14590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14592 if (INTEL_INFO(dev
)->gen
>= 9)
14595 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
14598 if (IS_CHERRYVIEW(dev
))
14601 if (HAS_PCH_LPT_H(dev
) && I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
14604 /* DDI E can't be used if DDI A requires 4 lanes */
14605 if (HAS_DDI(dev
) && I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
14608 if (!dev_priv
->vbt
.int_crt_support
)
14614 static void intel_setup_outputs(struct drm_device
*dev
)
14616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14617 struct intel_encoder
*encoder
;
14618 bool dpd_is_edp
= false;
14620 intel_lvds_init(dev
);
14622 if (intel_crt_present(dev
))
14623 intel_crt_init(dev
);
14625 if (IS_BROXTON(dev
)) {
14627 * FIXME: Broxton doesn't support port detection via the
14628 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14629 * detect the ports.
14631 intel_ddi_init(dev
, PORT_A
);
14632 intel_ddi_init(dev
, PORT_B
);
14633 intel_ddi_init(dev
, PORT_C
);
14635 intel_dsi_init(dev
);
14636 } else if (HAS_DDI(dev
)) {
14640 * Haswell uses DDI functions to detect digital outputs.
14641 * On SKL pre-D0 the strap isn't connected, so we assume
14644 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
14645 /* WaIgnoreDDIAStrap: skl */
14646 if (found
|| IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
14647 intel_ddi_init(dev
, PORT_A
);
14649 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14651 found
= I915_READ(SFUSE_STRAP
);
14653 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
14654 intel_ddi_init(dev
, PORT_B
);
14655 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
14656 intel_ddi_init(dev
, PORT_C
);
14657 if (found
& SFUSE_STRAP_DDID_DETECTED
)
14658 intel_ddi_init(dev
, PORT_D
);
14660 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14662 if ((IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) &&
14663 (dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dp
||
14664 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dvi
||
14665 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_hdmi
))
14666 intel_ddi_init(dev
, PORT_E
);
14668 } else if (HAS_PCH_SPLIT(dev
)) {
14670 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
14672 if (has_edp_a(dev
))
14673 intel_dp_init(dev
, DP_A
, PORT_A
);
14675 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
14676 /* PCH SDVOB multiplex with HDMIB */
14677 found
= intel_sdvo_init(dev
, PCH_SDVOB
, PORT_B
);
14679 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
14680 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
14681 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
14684 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
14685 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
14687 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
14688 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
14690 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
14691 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
14693 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
14694 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
14695 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
14697 * The DP_DETECTED bit is the latched state of the DDC
14698 * SDA pin at boot. However since eDP doesn't require DDC
14699 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14700 * eDP ports may have been muxed to an alternate function.
14701 * Thus we can't rely on the DP_DETECTED bit alone to detect
14702 * eDP ports. Consult the VBT as well as DP_DETECTED to
14703 * detect eDP ports.
14705 if (I915_READ(VLV_HDMIB
) & SDVO_DETECTED
&&
14706 !intel_dp_is_edp(dev
, PORT_B
))
14707 intel_hdmi_init(dev
, VLV_HDMIB
, PORT_B
);
14708 if (I915_READ(VLV_DP_B
) & DP_DETECTED
||
14709 intel_dp_is_edp(dev
, PORT_B
))
14710 intel_dp_init(dev
, VLV_DP_B
, PORT_B
);
14712 if (I915_READ(VLV_HDMIC
) & SDVO_DETECTED
&&
14713 !intel_dp_is_edp(dev
, PORT_C
))
14714 intel_hdmi_init(dev
, VLV_HDMIC
, PORT_C
);
14715 if (I915_READ(VLV_DP_C
) & DP_DETECTED
||
14716 intel_dp_is_edp(dev
, PORT_C
))
14717 intel_dp_init(dev
, VLV_DP_C
, PORT_C
);
14719 if (IS_CHERRYVIEW(dev
)) {
14720 /* eDP not supported on port D, so don't check VBT */
14721 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
)
14722 intel_hdmi_init(dev
, CHV_HDMID
, PORT_D
);
14723 if (I915_READ(CHV_DP_D
) & DP_DETECTED
)
14724 intel_dp_init(dev
, CHV_DP_D
, PORT_D
);
14727 intel_dsi_init(dev
);
14728 } else if (!IS_GEN2(dev
) && !IS_PINEVIEW(dev
)) {
14729 bool found
= false;
14731 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14732 DRM_DEBUG_KMS("probing SDVOB\n");
14733 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, PORT_B
);
14734 if (!found
&& IS_G4X(dev
)) {
14735 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14736 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
14739 if (!found
&& IS_G4X(dev
))
14740 intel_dp_init(dev
, DP_B
, PORT_B
);
14743 /* Before G4X SDVOC doesn't have its own detect register */
14745 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14746 DRM_DEBUG_KMS("probing SDVOC\n");
14747 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, PORT_C
);
14750 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14753 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14754 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
14757 intel_dp_init(dev
, DP_C
, PORT_C
);
14761 (I915_READ(DP_D
) & DP_DETECTED
))
14762 intel_dp_init(dev
, DP_D
, PORT_D
);
14763 } else if (IS_GEN2(dev
))
14764 intel_dvo_init(dev
);
14766 if (SUPPORTS_TV(dev
))
14767 intel_tv_init(dev
);
14769 intel_psr_init(dev
);
14771 for_each_intel_encoder(dev
, encoder
) {
14772 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
14773 encoder
->base
.possible_clones
=
14774 intel_encoder_clones(encoder
);
14777 intel_init_pch_refclk(dev
);
14779 drm_helper_move_panel_connectors_to_head(dev
);
14782 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
14784 struct drm_device
*dev
= fb
->dev
;
14785 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14787 drm_framebuffer_cleanup(fb
);
14788 mutex_lock(&dev
->struct_mutex
);
14789 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
14790 drm_gem_object_unreference(&intel_fb
->obj
->base
);
14791 mutex_unlock(&dev
->struct_mutex
);
14795 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
14796 struct drm_file
*file
,
14797 unsigned int *handle
)
14799 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14800 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14802 if (obj
->userptr
.mm
) {
14803 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14807 return drm_gem_handle_create(file
, &obj
->base
, handle
);
14810 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
14811 struct drm_file
*file
,
14812 unsigned flags
, unsigned color
,
14813 struct drm_clip_rect
*clips
,
14814 unsigned num_clips
)
14816 struct drm_device
*dev
= fb
->dev
;
14817 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14818 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14820 mutex_lock(&dev
->struct_mutex
);
14821 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
14822 mutex_unlock(&dev
->struct_mutex
);
14827 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
14828 .destroy
= intel_user_framebuffer_destroy
,
14829 .create_handle
= intel_user_framebuffer_create_handle
,
14830 .dirty
= intel_user_framebuffer_dirty
,
14834 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
14835 uint32_t pixel_format
)
14837 u32 gen
= INTEL_INFO(dev
)->gen
;
14840 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
14842 /* "The stride in bytes must not exceed the of the size of 8K
14843 * pixels and 32K bytes."
14845 return min(8192 * cpp
, 32768);
14846 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
14848 } else if (gen
>= 4) {
14849 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14853 } else if (gen
>= 3) {
14854 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14859 /* XXX DSPC is limited to 4k tiled */
14864 static int intel_framebuffer_init(struct drm_device
*dev
,
14865 struct intel_framebuffer
*intel_fb
,
14866 struct drm_mode_fb_cmd2
*mode_cmd
,
14867 struct drm_i915_gem_object
*obj
)
14869 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14870 unsigned int aligned_height
;
14872 u32 pitch_limit
, stride_alignment
;
14874 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
14876 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
14877 /* Enforce that fb modifier and tiling mode match, but only for
14878 * X-tiled. This is needed for FBC. */
14879 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
14880 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
14881 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14885 if (obj
->tiling_mode
== I915_TILING_X
)
14886 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
14887 else if (obj
->tiling_mode
== I915_TILING_Y
) {
14888 DRM_DEBUG("No Y tiling for legacy addfb\n");
14893 /* Passed in modifier sanity checking. */
14894 switch (mode_cmd
->modifier
[0]) {
14895 case I915_FORMAT_MOD_Y_TILED
:
14896 case I915_FORMAT_MOD_Yf_TILED
:
14897 if (INTEL_INFO(dev
)->gen
< 9) {
14898 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14899 mode_cmd
->modifier
[0]);
14902 case DRM_FORMAT_MOD_NONE
:
14903 case I915_FORMAT_MOD_X_TILED
:
14906 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14907 mode_cmd
->modifier
[0]);
14911 stride_alignment
= intel_fb_stride_alignment(dev_priv
,
14912 mode_cmd
->modifier
[0],
14913 mode_cmd
->pixel_format
);
14914 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
14915 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14916 mode_cmd
->pitches
[0], stride_alignment
);
14920 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
14921 mode_cmd
->pixel_format
);
14922 if (mode_cmd
->pitches
[0] > pitch_limit
) {
14923 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14924 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
14925 "tiled" : "linear",
14926 mode_cmd
->pitches
[0], pitch_limit
);
14930 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
14931 mode_cmd
->pitches
[0] != obj
->stride
) {
14932 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14933 mode_cmd
->pitches
[0], obj
->stride
);
14937 /* Reject formats not supported by any plane early. */
14938 switch (mode_cmd
->pixel_format
) {
14939 case DRM_FORMAT_C8
:
14940 case DRM_FORMAT_RGB565
:
14941 case DRM_FORMAT_XRGB8888
:
14942 case DRM_FORMAT_ARGB8888
:
14944 case DRM_FORMAT_XRGB1555
:
14945 if (INTEL_INFO(dev
)->gen
> 3) {
14946 DRM_DEBUG("unsupported pixel format: %s\n",
14947 drm_get_format_name(mode_cmd
->pixel_format
));
14951 case DRM_FORMAT_ABGR8888
:
14952 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
14953 INTEL_INFO(dev
)->gen
< 9) {
14954 DRM_DEBUG("unsupported pixel format: %s\n",
14955 drm_get_format_name(mode_cmd
->pixel_format
));
14959 case DRM_FORMAT_XBGR8888
:
14960 case DRM_FORMAT_XRGB2101010
:
14961 case DRM_FORMAT_XBGR2101010
:
14962 if (INTEL_INFO(dev
)->gen
< 4) {
14963 DRM_DEBUG("unsupported pixel format: %s\n",
14964 drm_get_format_name(mode_cmd
->pixel_format
));
14968 case DRM_FORMAT_ABGR2101010
:
14969 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
14970 DRM_DEBUG("unsupported pixel format: %s\n",
14971 drm_get_format_name(mode_cmd
->pixel_format
));
14975 case DRM_FORMAT_YUYV
:
14976 case DRM_FORMAT_UYVY
:
14977 case DRM_FORMAT_YVYU
:
14978 case DRM_FORMAT_VYUY
:
14979 if (INTEL_INFO(dev
)->gen
< 5) {
14980 DRM_DEBUG("unsupported pixel format: %s\n",
14981 drm_get_format_name(mode_cmd
->pixel_format
));
14986 DRM_DEBUG("unsupported pixel format: %s\n",
14987 drm_get_format_name(mode_cmd
->pixel_format
));
14991 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14992 if (mode_cmd
->offsets
[0] != 0)
14995 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
14996 mode_cmd
->pixel_format
,
14997 mode_cmd
->modifier
[0]);
14998 /* FIXME drm helper for size checks (especially planar formats)? */
14999 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
15002 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
15003 intel_fb
->obj
= obj
;
15005 intel_fill_fb_info(dev_priv
, &intel_fb
->base
);
15007 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
15009 DRM_ERROR("framebuffer init failed %d\n", ret
);
15013 intel_fb
->obj
->framebuffer_references
++;
15018 static struct drm_framebuffer
*
15019 intel_user_framebuffer_create(struct drm_device
*dev
,
15020 struct drm_file
*filp
,
15021 const struct drm_mode_fb_cmd2
*user_mode_cmd
)
15023 struct drm_framebuffer
*fb
;
15024 struct drm_i915_gem_object
*obj
;
15025 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
15027 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
15028 mode_cmd
.handles
[0]));
15029 if (&obj
->base
== NULL
)
15030 return ERR_PTR(-ENOENT
);
15032 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
15034 drm_gem_object_unreference_unlocked(&obj
->base
);
15039 #ifndef CONFIG_DRM_FBDEV_EMULATION
15040 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
15045 static const struct drm_mode_config_funcs intel_mode_funcs
= {
15046 .fb_create
= intel_user_framebuffer_create
,
15047 .output_poll_changed
= intel_fbdev_output_poll_changed
,
15048 .atomic_check
= intel_atomic_check
,
15049 .atomic_commit
= intel_atomic_commit
,
15050 .atomic_state_alloc
= intel_atomic_state_alloc
,
15051 .atomic_state_clear
= intel_atomic_state_clear
,
15055 * intel_init_display_hooks - initialize the display modesetting hooks
15056 * @dev_priv: device private
15058 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
15060 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
15061 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15062 dev_priv
->display
.get_initial_plane_config
=
15063 skylake_get_initial_plane_config
;
15064 dev_priv
->display
.crtc_compute_clock
=
15065 haswell_crtc_compute_clock
;
15066 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15067 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15068 } else if (HAS_DDI(dev_priv
)) {
15069 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15070 dev_priv
->display
.get_initial_plane_config
=
15071 ironlake_get_initial_plane_config
;
15072 dev_priv
->display
.crtc_compute_clock
=
15073 haswell_crtc_compute_clock
;
15074 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15075 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15076 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15077 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
15078 dev_priv
->display
.get_initial_plane_config
=
15079 ironlake_get_initial_plane_config
;
15080 dev_priv
->display
.crtc_compute_clock
=
15081 ironlake_crtc_compute_clock
;
15082 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
15083 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
15084 } else if (IS_CHERRYVIEW(dev_priv
)) {
15085 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15086 dev_priv
->display
.get_initial_plane_config
=
15087 i9xx_get_initial_plane_config
;
15088 dev_priv
->display
.crtc_compute_clock
= chv_crtc_compute_clock
;
15089 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15090 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15091 } else if (IS_VALLEYVIEW(dev_priv
)) {
15092 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15093 dev_priv
->display
.get_initial_plane_config
=
15094 i9xx_get_initial_plane_config
;
15095 dev_priv
->display
.crtc_compute_clock
= vlv_crtc_compute_clock
;
15096 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15097 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15098 } else if (IS_G4X(dev_priv
)) {
15099 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15100 dev_priv
->display
.get_initial_plane_config
=
15101 i9xx_get_initial_plane_config
;
15102 dev_priv
->display
.crtc_compute_clock
= g4x_crtc_compute_clock
;
15103 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15104 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15105 } else if (IS_PINEVIEW(dev_priv
)) {
15106 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15107 dev_priv
->display
.get_initial_plane_config
=
15108 i9xx_get_initial_plane_config
;
15109 dev_priv
->display
.crtc_compute_clock
= pnv_crtc_compute_clock
;
15110 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15111 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15112 } else if (!IS_GEN2(dev_priv
)) {
15113 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15114 dev_priv
->display
.get_initial_plane_config
=
15115 i9xx_get_initial_plane_config
;
15116 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
15117 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15118 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15120 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15121 dev_priv
->display
.get_initial_plane_config
=
15122 i9xx_get_initial_plane_config
;
15123 dev_priv
->display
.crtc_compute_clock
= i8xx_crtc_compute_clock
;
15124 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15125 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15128 /* Returns the core display clock speed */
15129 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
15130 dev_priv
->display
.get_display_clock_speed
=
15131 skylake_get_display_clock_speed
;
15132 else if (IS_BROXTON(dev_priv
))
15133 dev_priv
->display
.get_display_clock_speed
=
15134 broxton_get_display_clock_speed
;
15135 else if (IS_BROADWELL(dev_priv
))
15136 dev_priv
->display
.get_display_clock_speed
=
15137 broadwell_get_display_clock_speed
;
15138 else if (IS_HASWELL(dev_priv
))
15139 dev_priv
->display
.get_display_clock_speed
=
15140 haswell_get_display_clock_speed
;
15141 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15142 dev_priv
->display
.get_display_clock_speed
=
15143 valleyview_get_display_clock_speed
;
15144 else if (IS_GEN5(dev_priv
))
15145 dev_priv
->display
.get_display_clock_speed
=
15146 ilk_get_display_clock_speed
;
15147 else if (IS_I945G(dev_priv
) || IS_BROADWATER(dev_priv
) ||
15148 IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
))
15149 dev_priv
->display
.get_display_clock_speed
=
15150 i945_get_display_clock_speed
;
15151 else if (IS_GM45(dev_priv
))
15152 dev_priv
->display
.get_display_clock_speed
=
15153 gm45_get_display_clock_speed
;
15154 else if (IS_CRESTLINE(dev_priv
))
15155 dev_priv
->display
.get_display_clock_speed
=
15156 i965gm_get_display_clock_speed
;
15157 else if (IS_PINEVIEW(dev_priv
))
15158 dev_priv
->display
.get_display_clock_speed
=
15159 pnv_get_display_clock_speed
;
15160 else if (IS_G33(dev_priv
) || IS_G4X(dev_priv
))
15161 dev_priv
->display
.get_display_clock_speed
=
15162 g33_get_display_clock_speed
;
15163 else if (IS_I915G(dev_priv
))
15164 dev_priv
->display
.get_display_clock_speed
=
15165 i915_get_display_clock_speed
;
15166 else if (IS_I945GM(dev_priv
) || IS_845G(dev_priv
))
15167 dev_priv
->display
.get_display_clock_speed
=
15168 i9xx_misc_get_display_clock_speed
;
15169 else if (IS_I915GM(dev_priv
))
15170 dev_priv
->display
.get_display_clock_speed
=
15171 i915gm_get_display_clock_speed
;
15172 else if (IS_I865G(dev_priv
))
15173 dev_priv
->display
.get_display_clock_speed
=
15174 i865_get_display_clock_speed
;
15175 else if (IS_I85X(dev_priv
))
15176 dev_priv
->display
.get_display_clock_speed
=
15177 i85x_get_display_clock_speed
;
15179 WARN(!IS_I830(dev_priv
), "Unknown platform. Assuming 133 MHz CDCLK\n");
15180 dev_priv
->display
.get_display_clock_speed
=
15181 i830_get_display_clock_speed
;
15184 if (IS_GEN5(dev_priv
)) {
15185 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
15186 } else if (IS_GEN6(dev_priv
)) {
15187 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
15188 } else if (IS_IVYBRIDGE(dev_priv
)) {
15189 /* FIXME: detect B0+ stepping and use auto training */
15190 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
15191 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
15192 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
15195 if (IS_BROADWELL(dev_priv
)) {
15196 dev_priv
->display
.modeset_commit_cdclk
=
15197 broadwell_modeset_commit_cdclk
;
15198 dev_priv
->display
.modeset_calc_cdclk
=
15199 broadwell_modeset_calc_cdclk
;
15200 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
15201 dev_priv
->display
.modeset_commit_cdclk
=
15202 valleyview_modeset_commit_cdclk
;
15203 dev_priv
->display
.modeset_calc_cdclk
=
15204 valleyview_modeset_calc_cdclk
;
15205 } else if (IS_BROXTON(dev_priv
)) {
15206 dev_priv
->display
.modeset_commit_cdclk
=
15207 broxton_modeset_commit_cdclk
;
15208 dev_priv
->display
.modeset_calc_cdclk
=
15209 broxton_modeset_calc_cdclk
;
15210 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
15211 dev_priv
->display
.modeset_commit_cdclk
=
15212 skl_modeset_commit_cdclk
;
15213 dev_priv
->display
.modeset_calc_cdclk
=
15214 skl_modeset_calc_cdclk
;
15217 switch (INTEL_INFO(dev_priv
)->gen
) {
15219 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
15223 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
15228 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
15232 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
15235 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15236 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
15239 /* Drop through - unsupported since execlist only. */
15241 /* Default just returns -ENODEV to indicate unsupported */
15242 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
15247 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15248 * resume, or other times. This quirk makes sure that's the case for
15249 * affected systems.
15251 static void quirk_pipea_force(struct drm_device
*dev
)
15253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15255 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
15256 DRM_INFO("applying pipe a force quirk\n");
15259 static void quirk_pipeb_force(struct drm_device
*dev
)
15261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15263 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
15264 DRM_INFO("applying pipe b force quirk\n");
15268 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15270 static void quirk_ssc_force_disable(struct drm_device
*dev
)
15272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15273 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
15274 DRM_INFO("applying lvds SSC disable quirk\n");
15278 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15281 static void quirk_invert_brightness(struct drm_device
*dev
)
15283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15284 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
15285 DRM_INFO("applying inverted panel brightness quirk\n");
15288 /* Some VBT's incorrectly indicate no backlight is present */
15289 static void quirk_backlight_present(struct drm_device
*dev
)
15291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15292 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
15293 DRM_INFO("applying backlight present quirk\n");
15296 struct intel_quirk
{
15298 int subsystem_vendor
;
15299 int subsystem_device
;
15300 void (*hook
)(struct drm_device
*dev
);
15303 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15304 struct intel_dmi_quirk
{
15305 void (*hook
)(struct drm_device
*dev
);
15306 const struct dmi_system_id (*dmi_id_list
)[];
15309 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
15311 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
15315 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
15317 .dmi_id_list
= &(const struct dmi_system_id
[]) {
15319 .callback
= intel_dmi_reverse_brightness
,
15320 .ident
= "NCR Corporation",
15321 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
15322 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
15325 { } /* terminating entry */
15327 .hook
= quirk_invert_brightness
,
15331 static struct intel_quirk intel_quirks
[] = {
15332 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15333 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
15335 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15336 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
15338 /* 830 needs to leave pipe A & dpll A up */
15339 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
15341 /* 830 needs to leave pipe B & dpll B up */
15342 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
15344 /* Lenovo U160 cannot use SSC on LVDS */
15345 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
15347 /* Sony Vaio Y cannot use SSC on LVDS */
15348 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
15350 /* Acer Aspire 5734Z must invert backlight brightness */
15351 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
15353 /* Acer/eMachines G725 */
15354 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
15356 /* Acer/eMachines e725 */
15357 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
15359 /* Acer/Packard Bell NCL20 */
15360 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
15362 /* Acer Aspire 4736Z */
15363 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
15365 /* Acer Aspire 5336 */
15366 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
15368 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15369 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
15371 /* Acer C720 Chromebook (Core i3 4005U) */
15372 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
15374 /* Apple Macbook 2,1 (Core 2 T7400) */
15375 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
15377 /* Apple Macbook 4,1 */
15378 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present
},
15380 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15381 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
15383 /* HP Chromebook 14 (Celeron 2955U) */
15384 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
15386 /* Dell Chromebook 11 */
15387 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
15389 /* Dell Chromebook 11 (2015 version) */
15390 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present
},
15393 static void intel_init_quirks(struct drm_device
*dev
)
15395 struct pci_dev
*d
= dev
->pdev
;
15398 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
15399 struct intel_quirk
*q
= &intel_quirks
[i
];
15401 if (d
->device
== q
->device
&&
15402 (d
->subsystem_vendor
== q
->subsystem_vendor
||
15403 q
->subsystem_vendor
== PCI_ANY_ID
) &&
15404 (d
->subsystem_device
== q
->subsystem_device
||
15405 q
->subsystem_device
== PCI_ANY_ID
))
15408 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
15409 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
15410 intel_dmi_quirks
[i
].hook(dev
);
15414 /* Disable the VGA plane that we never use */
15415 static void i915_disable_vga(struct drm_device
*dev
)
15417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15419 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev
);
15421 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15422 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15423 outb(SR01
, VGA_SR_INDEX
);
15424 sr1
= inb(VGA_SR_DATA
);
15425 outb(sr1
| 1<<5, VGA_SR_DATA
);
15426 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15429 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
15430 POSTING_READ(vga_reg
);
15433 void intel_modeset_init_hw(struct drm_device
*dev
)
15435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15437 intel_update_cdclk(dev
);
15439 dev_priv
->atomic_cdclk_freq
= dev_priv
->cdclk_freq
;
15441 intel_init_clock_gating(dev
);
15442 intel_enable_gt_powersave(dev_priv
);
15446 * Calculate what we think the watermarks should be for the state we've read
15447 * out of the hardware and then immediately program those watermarks so that
15448 * we ensure the hardware settings match our internal state.
15450 * We can calculate what we think WM's should be by creating a duplicate of the
15451 * current state (which was constructed during hardware readout) and running it
15452 * through the atomic check code to calculate new watermark values in the
15455 static void sanitize_watermarks(struct drm_device
*dev
)
15457 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15458 struct drm_atomic_state
*state
;
15459 struct drm_crtc
*crtc
;
15460 struct drm_crtc_state
*cstate
;
15461 struct drm_modeset_acquire_ctx ctx
;
15465 /* Only supported on platforms that use atomic watermark design */
15466 if (!dev_priv
->display
.optimize_watermarks
)
15470 * We need to hold connection_mutex before calling duplicate_state so
15471 * that the connector loop is protected.
15473 drm_modeset_acquire_init(&ctx
, 0);
15475 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
15476 if (ret
== -EDEADLK
) {
15477 drm_modeset_backoff(&ctx
);
15479 } else if (WARN_ON(ret
)) {
15483 state
= drm_atomic_helper_duplicate_state(dev
, &ctx
);
15484 if (WARN_ON(IS_ERR(state
)))
15488 * Hardware readout is the only time we don't want to calculate
15489 * intermediate watermarks (since we don't trust the current
15492 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
15494 ret
= intel_atomic_check(dev
, state
);
15497 * If we fail here, it means that the hardware appears to be
15498 * programmed in a way that shouldn't be possible, given our
15499 * understanding of watermark requirements. This might mean a
15500 * mistake in the hardware readout code or a mistake in the
15501 * watermark calculations for a given platform. Raise a WARN
15502 * so that this is noticeable.
15504 * If this actually happens, we'll have to just leave the
15505 * BIOS-programmed watermarks untouched and hope for the best.
15507 WARN(true, "Could not determine valid watermarks for inherited state\n");
15511 /* Write calculated watermark values back */
15512 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
15513 struct intel_crtc_state
*cs
= to_intel_crtc_state(cstate
);
15515 cs
->wm
.need_postvbl_update
= true;
15516 dev_priv
->display
.optimize_watermarks(cs
);
15519 drm_atomic_state_free(state
);
15521 drm_modeset_drop_locks(&ctx
);
15522 drm_modeset_acquire_fini(&ctx
);
15525 void intel_modeset_init(struct drm_device
*dev
)
15527 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15528 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
15531 struct intel_crtc
*crtc
;
15533 drm_mode_config_init(dev
);
15535 dev
->mode_config
.min_width
= 0;
15536 dev
->mode_config
.min_height
= 0;
15538 dev
->mode_config
.preferred_depth
= 24;
15539 dev
->mode_config
.prefer_shadow
= 1;
15541 dev
->mode_config
.allow_fb_modifiers
= true;
15543 dev
->mode_config
.funcs
= &intel_mode_funcs
;
15545 intel_init_quirks(dev
);
15547 intel_init_pm(dev
);
15549 if (INTEL_INFO(dev
)->num_pipes
== 0)
15553 * There may be no VBT; and if the BIOS enabled SSC we can
15554 * just keep using it to avoid unnecessary flicker. Whereas if the
15555 * BIOS isn't using it, don't assume it will work even if the VBT
15556 * indicates as much.
15558 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
15559 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15562 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
15563 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15564 bios_lvds_use_ssc
? "en" : "dis",
15565 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
15566 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
15570 if (IS_GEN2(dev
)) {
15571 dev
->mode_config
.max_width
= 2048;
15572 dev
->mode_config
.max_height
= 2048;
15573 } else if (IS_GEN3(dev
)) {
15574 dev
->mode_config
.max_width
= 4096;
15575 dev
->mode_config
.max_height
= 4096;
15577 dev
->mode_config
.max_width
= 8192;
15578 dev
->mode_config
.max_height
= 8192;
15581 if (IS_845G(dev
) || IS_I865G(dev
)) {
15582 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
15583 dev
->mode_config
.cursor_height
= 1023;
15584 } else if (IS_GEN2(dev
)) {
15585 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
15586 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
15588 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
15589 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
15592 dev
->mode_config
.fb_base
= ggtt
->mappable_base
;
15594 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15595 INTEL_INFO(dev
)->num_pipes
,
15596 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
15598 for_each_pipe(dev_priv
, pipe
) {
15599 intel_crtc_init(dev
, pipe
);
15600 for_each_sprite(dev_priv
, pipe
, sprite
) {
15601 ret
= intel_plane_init(dev
, pipe
, sprite
);
15603 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15604 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
15608 intel_update_czclk(dev_priv
);
15609 intel_update_cdclk(dev
);
15611 intel_shared_dpll_init(dev
);
15613 if (dev_priv
->max_cdclk_freq
== 0)
15614 intel_update_max_cdclk(dev
);
15616 /* Just disable it once at startup */
15617 i915_disable_vga(dev
);
15618 intel_setup_outputs(dev
);
15620 drm_modeset_lock_all(dev
);
15621 intel_modeset_setup_hw_state(dev
);
15622 drm_modeset_unlock_all(dev
);
15624 for_each_intel_crtc(dev
, crtc
) {
15625 struct intel_initial_plane_config plane_config
= {};
15631 * Note that reserving the BIOS fb up front prevents us
15632 * from stuffing other stolen allocations like the ring
15633 * on top. This prevents some ugliness at boot time, and
15634 * can even allow for smooth boot transitions if the BIOS
15635 * fb is large enough for the active pipe configuration.
15637 dev_priv
->display
.get_initial_plane_config(crtc
,
15641 * If the fb is shared between multiple heads, we'll
15642 * just get the first one.
15644 intel_find_initial_plane_obj(crtc
, &plane_config
);
15648 * Make sure hardware watermarks really match the state we read out.
15649 * Note that we need to do this after reconstructing the BIOS fb's
15650 * since the watermark calculation done here will use pstate->fb.
15652 sanitize_watermarks(dev
);
15655 static void intel_enable_pipe_a(struct drm_device
*dev
)
15657 struct intel_connector
*connector
;
15658 struct drm_connector
*crt
= NULL
;
15659 struct intel_load_detect_pipe load_detect_temp
;
15660 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
15662 /* We can't just switch on the pipe A, we need to set things up with a
15663 * proper mode and output configuration. As a gross hack, enable pipe A
15664 * by enabling the load detect pipe once. */
15665 for_each_intel_connector(dev
, connector
) {
15666 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
15667 crt
= &connector
->base
;
15675 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
15676 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
15680 intel_check_plane_mapping(struct intel_crtc
*crtc
)
15682 struct drm_device
*dev
= crtc
->base
.dev
;
15683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15686 if (INTEL_INFO(dev
)->num_pipes
== 1)
15689 val
= I915_READ(DSPCNTR(!crtc
->plane
));
15691 if ((val
& DISPLAY_PLANE_ENABLE
) &&
15692 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
15698 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
15700 struct drm_device
*dev
= crtc
->base
.dev
;
15701 struct intel_encoder
*encoder
;
15703 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
15709 static bool intel_encoder_has_connectors(struct intel_encoder
*encoder
)
15711 struct drm_device
*dev
= encoder
->base
.dev
;
15712 struct intel_connector
*connector
;
15714 for_each_connector_on_encoder(dev
, &encoder
->base
, connector
)
15720 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
15722 struct drm_device
*dev
= crtc
->base
.dev
;
15723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15724 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
15726 /* Clear any frame start delays used for debugging left by the BIOS */
15727 if (!transcoder_is_dsi(cpu_transcoder
)) {
15728 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
15731 I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
15734 /* restore vblank interrupts to correct state */
15735 drm_crtc_vblank_reset(&crtc
->base
);
15736 if (crtc
->active
) {
15737 struct intel_plane
*plane
;
15739 drm_crtc_vblank_on(&crtc
->base
);
15741 /* Disable everything but the primary plane */
15742 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
15743 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
15746 plane
->disable_plane(&plane
->base
, &crtc
->base
);
15750 /* We need to sanitize the plane -> pipe mapping first because this will
15751 * disable the crtc (and hence change the state) if it is wrong. Note
15752 * that gen4+ has a fixed plane -> pipe mapping. */
15753 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
15756 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15757 crtc
->base
.base
.id
, crtc
->base
.name
);
15759 /* Pipe has the wrong plane attached and the plane is active.
15760 * Temporarily change the plane mapping and disable everything
15762 plane
= crtc
->plane
;
15763 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
15764 crtc
->plane
= !plane
;
15765 intel_crtc_disable_noatomic(&crtc
->base
);
15766 crtc
->plane
= plane
;
15769 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
15770 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
15771 /* BIOS forgot to enable pipe A, this mostly happens after
15772 * resume. Force-enable the pipe to fix this, the update_dpms
15773 * call below we restore the pipe to the right state, but leave
15774 * the required bits on. */
15775 intel_enable_pipe_a(dev
);
15778 /* Adjust the state of the output pipe according to whether we
15779 * have active connectors/encoders. */
15780 if (crtc
->active
&& !intel_crtc_has_encoders(crtc
))
15781 intel_crtc_disable_noatomic(&crtc
->base
);
15783 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
15785 * We start out with underrun reporting disabled to avoid races.
15786 * For correct bookkeeping mark this on active crtcs.
15788 * Also on gmch platforms we dont have any hardware bits to
15789 * disable the underrun reporting. Which means we need to start
15790 * out with underrun reporting disabled also on inactive pipes,
15791 * since otherwise we'll complain about the garbage we read when
15792 * e.g. coming up after runtime pm.
15794 * No protection against concurrent access is required - at
15795 * worst a fifo underrun happens which also sets this to false.
15797 crtc
->cpu_fifo_underrun_disabled
= true;
15798 crtc
->pch_fifo_underrun_disabled
= true;
15802 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
15804 struct intel_connector
*connector
;
15805 struct drm_device
*dev
= encoder
->base
.dev
;
15807 /* We need to check both for a crtc link (meaning that the
15808 * encoder is active and trying to read from a pipe) and the
15809 * pipe itself being active. */
15810 bool has_active_crtc
= encoder
->base
.crtc
&&
15811 to_intel_crtc(encoder
->base
.crtc
)->active
;
15813 if (intel_encoder_has_connectors(encoder
) && !has_active_crtc
) {
15814 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15815 encoder
->base
.base
.id
,
15816 encoder
->base
.name
);
15818 /* Connector is active, but has no active pipe. This is
15819 * fallout from our resume register restoring. Disable
15820 * the encoder manually again. */
15821 if (encoder
->base
.crtc
) {
15822 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15823 encoder
->base
.base
.id
,
15824 encoder
->base
.name
);
15825 encoder
->disable(encoder
);
15826 if (encoder
->post_disable
)
15827 encoder
->post_disable(encoder
);
15829 encoder
->base
.crtc
= NULL
;
15831 /* Inconsistent output/port/pipe state happens presumably due to
15832 * a bug in one of the get_hw_state functions. Or someplace else
15833 * in our code, like the register restore mess on resume. Clamp
15834 * things to off as a safer default. */
15835 for_each_intel_connector(dev
, connector
) {
15836 if (connector
->encoder
!= encoder
)
15838 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15839 connector
->base
.encoder
= NULL
;
15842 /* Enabled encoders without active connectors will be fixed in
15843 * the crtc fixup. */
15846 void i915_redisable_vga_power_on(struct drm_device
*dev
)
15848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15849 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev
);
15851 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
15852 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15853 i915_disable_vga(dev
);
15857 void i915_redisable_vga(struct drm_device
*dev
)
15859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15861 /* This function can be called both from intel_modeset_setup_hw_state or
15862 * at a very early point in our resume sequence, where the power well
15863 * structures are not yet restored. Since this function is at a very
15864 * paranoid "someone might have enabled VGA while we were not looking"
15865 * level, just check if the power well is enabled instead of trying to
15866 * follow the "don't touch the power well if we don't need it" policy
15867 * the rest of the driver uses. */
15868 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_VGA
))
15871 i915_redisable_vga_power_on(dev
);
15873 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
);
15876 static bool primary_get_hw_state(struct intel_plane
*plane
)
15878 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
15880 return I915_READ(DSPCNTR(plane
->plane
)) & DISPLAY_PLANE_ENABLE
;
15883 /* FIXME read out full plane state for all planes */
15884 static void readout_plane_state(struct intel_crtc
*crtc
)
15886 struct drm_plane
*primary
= crtc
->base
.primary
;
15887 struct intel_plane_state
*plane_state
=
15888 to_intel_plane_state(primary
->state
);
15890 plane_state
->visible
= crtc
->active
&&
15891 primary_get_hw_state(to_intel_plane(primary
));
15893 if (plane_state
->visible
)
15894 crtc
->base
.state
->plane_mask
|= 1 << drm_plane_index(primary
);
15897 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
15899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15901 struct intel_crtc
*crtc
;
15902 struct intel_encoder
*encoder
;
15903 struct intel_connector
*connector
;
15906 dev_priv
->active_crtcs
= 0;
15908 for_each_intel_crtc(dev
, crtc
) {
15909 struct intel_crtc_state
*crtc_state
= crtc
->config
;
15912 __drm_atomic_helper_crtc_destroy_state(&crtc
->base
, &crtc_state
->base
);
15913 memset(crtc_state
, 0, sizeof(*crtc_state
));
15914 crtc_state
->base
.crtc
= &crtc
->base
;
15916 crtc_state
->base
.active
= crtc_state
->base
.enable
=
15917 dev_priv
->display
.get_pipe_config(crtc
, crtc_state
);
15919 crtc
->base
.enabled
= crtc_state
->base
.enable
;
15920 crtc
->active
= crtc_state
->base
.active
;
15922 if (crtc_state
->base
.active
) {
15923 dev_priv
->active_crtcs
|= 1 << crtc
->pipe
;
15925 if (INTEL_GEN(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
))
15926 pixclk
= ilk_pipe_pixel_rate(crtc_state
);
15927 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15928 pixclk
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
15930 WARN_ON(dev_priv
->display
.modeset_calc_cdclk
);
15932 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15933 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
15934 pixclk
= DIV_ROUND_UP(pixclk
* 100, 95);
15937 dev_priv
->min_pixclk
[crtc
->pipe
] = pixclk
;
15939 readout_plane_state(crtc
);
15941 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15942 crtc
->base
.base
.id
, crtc
->base
.name
,
15943 crtc
->active
? "enabled" : "disabled");
15946 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15947 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15949 pll
->on
= pll
->funcs
.get_hw_state(dev_priv
, pll
,
15950 &pll
->config
.hw_state
);
15951 pll
->config
.crtc_mask
= 0;
15952 for_each_intel_crtc(dev
, crtc
) {
15953 if (crtc
->active
&& crtc
->config
->shared_dpll
== pll
)
15954 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
15956 pll
->active_mask
= pll
->config
.crtc_mask
;
15958 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15959 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
15962 for_each_intel_encoder(dev
, encoder
) {
15965 if (encoder
->get_hw_state(encoder
, &pipe
)) {
15966 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15967 encoder
->base
.crtc
= &crtc
->base
;
15968 encoder
->get_config(encoder
, crtc
->config
);
15970 encoder
->base
.crtc
= NULL
;
15973 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15974 encoder
->base
.base
.id
,
15975 encoder
->base
.name
,
15976 encoder
->base
.crtc
? "enabled" : "disabled",
15980 for_each_intel_connector(dev
, connector
) {
15981 if (connector
->get_hw_state(connector
)) {
15982 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
15984 encoder
= connector
->encoder
;
15985 connector
->base
.encoder
= &encoder
->base
;
15987 if (encoder
->base
.crtc
&&
15988 encoder
->base
.crtc
->state
->active
) {
15990 * This has to be done during hardware readout
15991 * because anything calling .crtc_disable may
15992 * rely on the connector_mask being accurate.
15994 encoder
->base
.crtc
->state
->connector_mask
|=
15995 1 << drm_connector_index(&connector
->base
);
15996 encoder
->base
.crtc
->state
->encoder_mask
|=
15997 1 << drm_encoder_index(&encoder
->base
);
16001 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16002 connector
->base
.encoder
= NULL
;
16004 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16005 connector
->base
.base
.id
,
16006 connector
->base
.name
,
16007 connector
->base
.encoder
? "enabled" : "disabled");
16010 for_each_intel_crtc(dev
, crtc
) {
16011 crtc
->base
.hwmode
= crtc
->config
->base
.adjusted_mode
;
16013 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
16014 if (crtc
->base
.state
->active
) {
16015 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc
->config
);
16016 intel_mode_from_pipe_config(&crtc
->base
.state
->adjusted_mode
, crtc
->config
);
16017 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
16020 * The initial mode needs to be set in order to keep
16021 * the atomic core happy. It wants a valid mode if the
16022 * crtc's enabled, so we do the above call.
16024 * At this point some state updated by the connectors
16025 * in their ->detect() callback has not run yet, so
16026 * no recalculation can be done yet.
16028 * Even if we could do a recalculation and modeset
16029 * right now it would cause a double modeset if
16030 * fbdev or userspace chooses a different initial mode.
16032 * If that happens, someone indicated they wanted a
16033 * mode change, which means it's safe to do a full
16036 crtc
->base
.state
->mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
16038 drm_calc_timestamping_constants(&crtc
->base
, &crtc
->base
.hwmode
);
16039 update_scanline_offset(crtc
);
16042 intel_pipe_config_sanity_check(dev_priv
, crtc
->config
);
16046 /* Scan out the current hw modeset state,
16047 * and sanitizes it to the current state
16050 intel_modeset_setup_hw_state(struct drm_device
*dev
)
16052 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
16054 struct intel_crtc
*crtc
;
16055 struct intel_encoder
*encoder
;
16058 intel_modeset_readout_hw_state(dev
);
16060 /* HW state is read out, now we need to sanitize this mess. */
16061 for_each_intel_encoder(dev
, encoder
) {
16062 intel_sanitize_encoder(encoder
);
16065 for_each_pipe(dev_priv
, pipe
) {
16066 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
16067 intel_sanitize_crtc(crtc
);
16068 intel_dump_pipe_config(crtc
, crtc
->config
,
16069 "[setup_hw_state]");
16072 intel_modeset_update_connector_atomic_state(dev
);
16074 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
16075 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
16077 if (!pll
->on
|| pll
->active_mask
)
16080 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
16082 pll
->funcs
.disable(dev_priv
, pll
);
16086 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
16087 vlv_wm_get_hw_state(dev
);
16088 else if (IS_GEN9(dev
))
16089 skl_wm_get_hw_state(dev
);
16090 else if (HAS_PCH_SPLIT(dev
))
16091 ilk_wm_get_hw_state(dev
);
16093 for_each_intel_crtc(dev
, crtc
) {
16094 unsigned long put_domains
;
16096 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
, crtc
->config
);
16097 if (WARN_ON(put_domains
))
16098 modeset_put_power_domains(dev_priv
, put_domains
);
16100 intel_display_set_init_power(dev_priv
, false);
16102 intel_fbc_init_pipe_state(dev_priv
);
16105 void intel_display_resume(struct drm_device
*dev
)
16107 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16108 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
16109 struct drm_modeset_acquire_ctx ctx
;
16111 bool setup
= false;
16113 dev_priv
->modeset_restore_state
= NULL
;
16116 * This is a cludge because with real atomic modeset mode_config.mutex
16117 * won't be taken. Unfortunately some probed state like
16118 * audio_codec_enable is still protected by mode_config.mutex, so lock
16121 mutex_lock(&dev
->mode_config
.mutex
);
16122 drm_modeset_acquire_init(&ctx
, 0);
16125 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
16127 if (ret
== 0 && !setup
) {
16130 intel_modeset_setup_hw_state(dev
);
16131 i915_redisable_vga(dev
);
16134 if (ret
== 0 && state
) {
16135 struct drm_crtc_state
*crtc_state
;
16136 struct drm_crtc
*crtc
;
16139 state
->acquire_ctx
= &ctx
;
16141 /* ignore any reset values/BIOS leftovers in the WM registers */
16142 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
16144 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
16146 * Force recalculation even if we restore
16147 * current state. With fast modeset this may not result
16148 * in a modeset when the state is compatible.
16150 crtc_state
->mode_changed
= true;
16153 ret
= drm_atomic_commit(state
);
16156 if (ret
== -EDEADLK
) {
16157 drm_modeset_backoff(&ctx
);
16161 drm_modeset_drop_locks(&ctx
);
16162 drm_modeset_acquire_fini(&ctx
);
16163 mutex_unlock(&dev
->mode_config
.mutex
);
16166 DRM_ERROR("Restoring old state failed with %i\n", ret
);
16167 drm_atomic_state_free(state
);
16171 void intel_modeset_gem_init(struct drm_device
*dev
)
16173 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16174 struct drm_crtc
*c
;
16175 struct drm_i915_gem_object
*obj
;
16178 intel_init_gt_powersave(dev_priv
);
16180 intel_modeset_init_hw(dev
);
16182 intel_setup_overlay(dev_priv
);
16185 * Make sure any fbs we allocated at startup are properly
16186 * pinned & fenced. When we do the allocation it's too early
16189 for_each_crtc(dev
, c
) {
16190 obj
= intel_fb_obj(c
->primary
->fb
);
16194 mutex_lock(&dev
->struct_mutex
);
16195 ret
= intel_pin_and_fence_fb_obj(c
->primary
->fb
,
16196 c
->primary
->state
->rotation
);
16197 mutex_unlock(&dev
->struct_mutex
);
16199 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16200 to_intel_crtc(c
)->pipe
);
16201 drm_framebuffer_unreference(c
->primary
->fb
);
16202 c
->primary
->fb
= NULL
;
16203 c
->primary
->crtc
= c
->primary
->state
->crtc
= NULL
;
16204 update_state_fb(c
->primary
);
16205 c
->state
->plane_mask
&= ~(1 << drm_plane_index(c
->primary
));
16209 intel_backlight_register(dev
);
16212 void intel_connector_unregister(struct intel_connector
*intel_connector
)
16214 struct drm_connector
*connector
= &intel_connector
->base
;
16216 intel_panel_destroy_backlight(connector
);
16217 drm_connector_unregister(connector
);
16220 void intel_modeset_cleanup(struct drm_device
*dev
)
16222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
16223 struct intel_connector
*connector
;
16225 intel_disable_gt_powersave(dev_priv
);
16227 intel_backlight_unregister(dev
);
16230 * Interrupts and polling as the first thing to avoid creating havoc.
16231 * Too much stuff here (turning of connectors, ...) would
16232 * experience fancy races otherwise.
16234 intel_irq_uninstall(dev_priv
);
16237 * Due to the hpd irq storm handling the hotplug work can re-arm the
16238 * poll handlers. Hence disable polling after hpd handling is shut down.
16240 drm_kms_helper_poll_fini(dev
);
16242 intel_unregister_dsm_handler();
16244 intel_fbc_global_disable(dev_priv
);
16246 /* flush any delayed tasks or pending work */
16247 flush_scheduled_work();
16249 /* destroy the backlight and sysfs files before encoders/connectors */
16250 for_each_intel_connector(dev
, connector
)
16251 connector
->unregister(connector
);
16253 drm_mode_config_cleanup(dev
);
16255 intel_cleanup_overlay(dev_priv
);
16257 intel_cleanup_gt_powersave(dev_priv
);
16259 intel_teardown_gmbus(dev
);
16263 * Return which encoder is currently attached for connector.
16265 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
16267 return &intel_attached_encoder(connector
)->base
;
16270 void intel_connector_attach_encoder(struct intel_connector
*connector
,
16271 struct intel_encoder
*encoder
)
16273 connector
->encoder
= encoder
;
16274 drm_mode_connector_attach_encoder(&connector
->base
,
16279 * set vga decode state - true == enable VGA decode
16281 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
16283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
16284 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
16287 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
16288 DRM_ERROR("failed to read control word\n");
16292 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
16296 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
16298 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
16300 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
16301 DRM_ERROR("failed to write control word\n");
16308 struct intel_display_error_state
{
16310 u32 power_well_driver
;
16312 int num_transcoders
;
16314 struct intel_cursor_error_state
{
16319 } cursor
[I915_MAX_PIPES
];
16321 struct intel_pipe_error_state
{
16322 bool power_domain_on
;
16325 } pipe
[I915_MAX_PIPES
];
16327 struct intel_plane_error_state
{
16335 } plane
[I915_MAX_PIPES
];
16337 struct intel_transcoder_error_state
{
16338 bool power_domain_on
;
16339 enum transcoder cpu_transcoder
;
16352 struct intel_display_error_state
*
16353 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
)
16355 struct intel_display_error_state
*error
;
16356 int transcoders
[] = {
16364 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
16367 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
16371 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
16372 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
16374 for_each_pipe(dev_priv
, i
) {
16375 error
->pipe
[i
].power_domain_on
=
16376 __intel_display_power_is_enabled(dev_priv
,
16377 POWER_DOMAIN_PIPE(i
));
16378 if (!error
->pipe
[i
].power_domain_on
)
16381 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
16382 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
16383 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
16385 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
16386 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
16387 if (INTEL_GEN(dev_priv
) <= 3) {
16388 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
16389 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
16391 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
16392 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
16393 if (INTEL_GEN(dev_priv
) >= 4) {
16394 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
16395 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
16398 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
16400 if (HAS_GMCH_DISPLAY(dev_priv
))
16401 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
16404 /* Note: this does not include DSI transcoders. */
16405 error
->num_transcoders
= INTEL_INFO(dev_priv
)->num_pipes
;
16406 if (HAS_DDI(dev_priv
))
16407 error
->num_transcoders
++; /* Account for eDP. */
16409 for (i
= 0; i
< error
->num_transcoders
; i
++) {
16410 enum transcoder cpu_transcoder
= transcoders
[i
];
16412 error
->transcoder
[i
].power_domain_on
=
16413 __intel_display_power_is_enabled(dev_priv
,
16414 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
16415 if (!error
->transcoder
[i
].power_domain_on
)
16418 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
16420 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
16421 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
16422 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
16423 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
16424 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
16425 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
16426 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
16432 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16435 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
16436 struct drm_device
*dev
,
16437 struct intel_display_error_state
*error
)
16439 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
16445 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
16446 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
16447 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
16448 error
->power_well_driver
);
16449 for_each_pipe(dev_priv
, i
) {
16450 err_printf(m
, "Pipe [%d]:\n", i
);
16451 err_printf(m
, " Power: %s\n",
16452 onoff(error
->pipe
[i
].power_domain_on
));
16453 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
16454 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
16456 err_printf(m
, "Plane [%d]:\n", i
);
16457 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
16458 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
16459 if (INTEL_INFO(dev
)->gen
<= 3) {
16460 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
16461 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
16463 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
16464 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
16465 if (INTEL_INFO(dev
)->gen
>= 4) {
16466 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
16467 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
16470 err_printf(m
, "Cursor [%d]:\n", i
);
16471 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
16472 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
16473 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
16476 for (i
= 0; i
< error
->num_transcoders
; i
++) {
16477 err_printf(m
, "CPU transcoder: %s\n",
16478 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
16479 err_printf(m
, " Power: %s\n",
16480 onoff(error
->transcoder
[i
].power_domain_on
));
16481 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
16482 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
16483 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
16484 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
16485 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
16486 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
16487 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);