2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
51 /* Primary plane formats for gen <= 3 */
52 static const uint32_t i8xx_primary_formats
[] = {
59 /* Primary plane formats for gen >= 4 */
60 static const uint32_t i965_primary_formats
[] = {
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_XBGR2101010
,
69 static const uint32_t skl_primary_formats
[] = {
76 DRM_FORMAT_XRGB2101010
,
77 DRM_FORMAT_XBGR2101010
,
85 static const uint32_t intel_cursor_formats
[] = {
89 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
90 struct intel_crtc_state
*pipe_config
);
91 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
92 struct intel_crtc_state
*pipe_config
);
94 static int intel_framebuffer_init(struct drm_device
*dev
,
95 struct intel_framebuffer
*ifb
,
96 struct drm_mode_fb_cmd2
*mode_cmd
,
97 struct drm_i915_gem_object
*obj
);
98 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
99 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
100 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
102 struct intel_link_m_n
*m_n
,
103 struct intel_link_m_n
*m2_n2
);
104 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
105 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
106 static void haswell_set_pipemisc(struct drm_crtc
*crtc
);
107 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
108 const struct intel_crtc_state
*pipe_config
);
109 static void chv_prepare_pll(struct intel_crtc
*crtc
,
110 const struct intel_crtc_state
*pipe_config
);
111 static void intel_begin_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
112 static void intel_finish_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
113 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
114 struct intel_crtc_state
*crtc_state
);
115 static void skylake_pfit_enable(struct intel_crtc
*crtc
);
116 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
);
117 static void ironlake_pfit_enable(struct intel_crtc
*crtc
);
118 static void intel_modeset_setup_hw_state(struct drm_device
*dev
);
119 static void intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
);
127 int p2_slow
, p2_fast
;
130 typedef struct intel_limit intel_limit_t
;
132 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
139 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv
->sb_lock
);
143 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
144 CCK_FUSE_HPLL_FREQ_MASK
;
145 mutex_unlock(&dev_priv
->sb_lock
);
147 return vco_freq
[hpll_freq
] * 1000;
150 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
151 const char *name
, u32 reg
, int ref_freq
)
156 mutex_lock(&dev_priv
->sb_lock
);
157 val
= vlv_cck_read(dev_priv
, reg
);
158 mutex_unlock(&dev_priv
->sb_lock
);
160 divider
= val
& CCK_FREQUENCY_VALUES
;
162 WARN((val
& CCK_FREQUENCY_STATUS
) !=
163 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
164 "%s change in progress\n", name
);
166 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
169 static int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
170 const char *name
, u32 reg
)
172 if (dev_priv
->hpll_freq
== 0)
173 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
175 return vlv_get_cck_clock(dev_priv
, name
, reg
,
176 dev_priv
->hpll_freq
);
180 intel_pch_rawclk(struct drm_i915_private
*dev_priv
)
182 return (I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
) * 1000;
186 intel_vlv_hrawclk(struct drm_i915_private
*dev_priv
)
188 return vlv_get_cck_clock_hpll(dev_priv
, "hrawclk",
189 CCK_DISPLAY_REF_CLOCK_CONTROL
);
193 intel_g4x_hrawclk(struct drm_i915_private
*dev_priv
)
197 /* hrawclock is 1/4 the FSB frequency */
198 clkcfg
= I915_READ(CLKCFG
);
199 switch (clkcfg
& CLKCFG_FSB_MASK
) {
208 case CLKCFG_FSB_1067
:
210 case CLKCFG_FSB_1333
:
212 /* these two are just a guess; one of them might be right */
213 case CLKCFG_FSB_1600
:
214 case CLKCFG_FSB_1600_ALT
:
221 static void intel_update_rawclk(struct drm_i915_private
*dev_priv
)
223 if (HAS_PCH_SPLIT(dev_priv
))
224 dev_priv
->rawclk_freq
= intel_pch_rawclk(dev_priv
);
225 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
226 dev_priv
->rawclk_freq
= intel_vlv_hrawclk(dev_priv
);
227 else if (IS_G4X(dev_priv
) || IS_PINEVIEW(dev_priv
))
228 dev_priv
->rawclk_freq
= intel_g4x_hrawclk(dev_priv
);
230 return; /* no rawclk on other platforms, or no need to know it */
232 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv
->rawclk_freq
);
235 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
237 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
240 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
241 CCK_CZ_CLOCK_CONTROL
);
243 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
246 static inline u32
/* units of 100MHz */
247 intel_fdi_link_freq(struct drm_i915_private
*dev_priv
,
248 const struct intel_crtc_state
*pipe_config
)
250 if (HAS_DDI(dev_priv
))
251 return pipe_config
->port_clock
; /* SPLL */
252 else if (IS_GEN5(dev_priv
))
253 return ((I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2) * 10000;
258 static const intel_limit_t intel_limits_i8xx_dac
= {
259 .dot
= { .min
= 25000, .max
= 350000 },
260 .vco
= { .min
= 908000, .max
= 1512000 },
261 .n
= { .min
= 2, .max
= 16 },
262 .m
= { .min
= 96, .max
= 140 },
263 .m1
= { .min
= 18, .max
= 26 },
264 .m2
= { .min
= 6, .max
= 16 },
265 .p
= { .min
= 4, .max
= 128 },
266 .p1
= { .min
= 2, .max
= 33 },
267 .p2
= { .dot_limit
= 165000,
268 .p2_slow
= 4, .p2_fast
= 2 },
271 static const intel_limit_t intel_limits_i8xx_dvo
= {
272 .dot
= { .min
= 25000, .max
= 350000 },
273 .vco
= { .min
= 908000, .max
= 1512000 },
274 .n
= { .min
= 2, .max
= 16 },
275 .m
= { .min
= 96, .max
= 140 },
276 .m1
= { .min
= 18, .max
= 26 },
277 .m2
= { .min
= 6, .max
= 16 },
278 .p
= { .min
= 4, .max
= 128 },
279 .p1
= { .min
= 2, .max
= 33 },
280 .p2
= { .dot_limit
= 165000,
281 .p2_slow
= 4, .p2_fast
= 4 },
284 static const intel_limit_t intel_limits_i8xx_lvds
= {
285 .dot
= { .min
= 25000, .max
= 350000 },
286 .vco
= { .min
= 908000, .max
= 1512000 },
287 .n
= { .min
= 2, .max
= 16 },
288 .m
= { .min
= 96, .max
= 140 },
289 .m1
= { .min
= 18, .max
= 26 },
290 .m2
= { .min
= 6, .max
= 16 },
291 .p
= { .min
= 4, .max
= 128 },
292 .p1
= { .min
= 1, .max
= 6 },
293 .p2
= { .dot_limit
= 165000,
294 .p2_slow
= 14, .p2_fast
= 7 },
297 static const intel_limit_t intel_limits_i9xx_sdvo
= {
298 .dot
= { .min
= 20000, .max
= 400000 },
299 .vco
= { .min
= 1400000, .max
= 2800000 },
300 .n
= { .min
= 1, .max
= 6 },
301 .m
= { .min
= 70, .max
= 120 },
302 .m1
= { .min
= 8, .max
= 18 },
303 .m2
= { .min
= 3, .max
= 7 },
304 .p
= { .min
= 5, .max
= 80 },
305 .p1
= { .min
= 1, .max
= 8 },
306 .p2
= { .dot_limit
= 200000,
307 .p2_slow
= 10, .p2_fast
= 5 },
310 static const intel_limit_t intel_limits_i9xx_lvds
= {
311 .dot
= { .min
= 20000, .max
= 400000 },
312 .vco
= { .min
= 1400000, .max
= 2800000 },
313 .n
= { .min
= 1, .max
= 6 },
314 .m
= { .min
= 70, .max
= 120 },
315 .m1
= { .min
= 8, .max
= 18 },
316 .m2
= { .min
= 3, .max
= 7 },
317 .p
= { .min
= 7, .max
= 98 },
318 .p1
= { .min
= 1, .max
= 8 },
319 .p2
= { .dot_limit
= 112000,
320 .p2_slow
= 14, .p2_fast
= 7 },
324 static const intel_limit_t intel_limits_g4x_sdvo
= {
325 .dot
= { .min
= 25000, .max
= 270000 },
326 .vco
= { .min
= 1750000, .max
= 3500000},
327 .n
= { .min
= 1, .max
= 4 },
328 .m
= { .min
= 104, .max
= 138 },
329 .m1
= { .min
= 17, .max
= 23 },
330 .m2
= { .min
= 5, .max
= 11 },
331 .p
= { .min
= 10, .max
= 30 },
332 .p1
= { .min
= 1, .max
= 3},
333 .p2
= { .dot_limit
= 270000,
339 static const intel_limit_t intel_limits_g4x_hdmi
= {
340 .dot
= { .min
= 22000, .max
= 400000 },
341 .vco
= { .min
= 1750000, .max
= 3500000},
342 .n
= { .min
= 1, .max
= 4 },
343 .m
= { .min
= 104, .max
= 138 },
344 .m1
= { .min
= 16, .max
= 23 },
345 .m2
= { .min
= 5, .max
= 11 },
346 .p
= { .min
= 5, .max
= 80 },
347 .p1
= { .min
= 1, .max
= 8},
348 .p2
= { .dot_limit
= 165000,
349 .p2_slow
= 10, .p2_fast
= 5 },
352 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
353 .dot
= { .min
= 20000, .max
= 115000 },
354 .vco
= { .min
= 1750000, .max
= 3500000 },
355 .n
= { .min
= 1, .max
= 3 },
356 .m
= { .min
= 104, .max
= 138 },
357 .m1
= { .min
= 17, .max
= 23 },
358 .m2
= { .min
= 5, .max
= 11 },
359 .p
= { .min
= 28, .max
= 112 },
360 .p1
= { .min
= 2, .max
= 8 },
361 .p2
= { .dot_limit
= 0,
362 .p2_slow
= 14, .p2_fast
= 14
366 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
367 .dot
= { .min
= 80000, .max
= 224000 },
368 .vco
= { .min
= 1750000, .max
= 3500000 },
369 .n
= { .min
= 1, .max
= 3 },
370 .m
= { .min
= 104, .max
= 138 },
371 .m1
= { .min
= 17, .max
= 23 },
372 .m2
= { .min
= 5, .max
= 11 },
373 .p
= { .min
= 14, .max
= 42 },
374 .p1
= { .min
= 2, .max
= 6 },
375 .p2
= { .dot_limit
= 0,
376 .p2_slow
= 7, .p2_fast
= 7
380 static const intel_limit_t intel_limits_pineview_sdvo
= {
381 .dot
= { .min
= 20000, .max
= 400000},
382 .vco
= { .min
= 1700000, .max
= 3500000 },
383 /* Pineview's Ncounter is a ring counter */
384 .n
= { .min
= 3, .max
= 6 },
385 .m
= { .min
= 2, .max
= 256 },
386 /* Pineview only has one combined m divider, which we treat as m2. */
387 .m1
= { .min
= 0, .max
= 0 },
388 .m2
= { .min
= 0, .max
= 254 },
389 .p
= { .min
= 5, .max
= 80 },
390 .p1
= { .min
= 1, .max
= 8 },
391 .p2
= { .dot_limit
= 200000,
392 .p2_slow
= 10, .p2_fast
= 5 },
395 static const intel_limit_t intel_limits_pineview_lvds
= {
396 .dot
= { .min
= 20000, .max
= 400000 },
397 .vco
= { .min
= 1700000, .max
= 3500000 },
398 .n
= { .min
= 3, .max
= 6 },
399 .m
= { .min
= 2, .max
= 256 },
400 .m1
= { .min
= 0, .max
= 0 },
401 .m2
= { .min
= 0, .max
= 254 },
402 .p
= { .min
= 7, .max
= 112 },
403 .p1
= { .min
= 1, .max
= 8 },
404 .p2
= { .dot_limit
= 112000,
405 .p2_slow
= 14, .p2_fast
= 14 },
408 /* Ironlake / Sandybridge
410 * We calculate clock using (register_value + 2) for N/M1/M2, so here
411 * the range value for them is (actual_value - 2).
413 static const intel_limit_t intel_limits_ironlake_dac
= {
414 .dot
= { .min
= 25000, .max
= 350000 },
415 .vco
= { .min
= 1760000, .max
= 3510000 },
416 .n
= { .min
= 1, .max
= 5 },
417 .m
= { .min
= 79, .max
= 127 },
418 .m1
= { .min
= 12, .max
= 22 },
419 .m2
= { .min
= 5, .max
= 9 },
420 .p
= { .min
= 5, .max
= 80 },
421 .p1
= { .min
= 1, .max
= 8 },
422 .p2
= { .dot_limit
= 225000,
423 .p2_slow
= 10, .p2_fast
= 5 },
426 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
427 .dot
= { .min
= 25000, .max
= 350000 },
428 .vco
= { .min
= 1760000, .max
= 3510000 },
429 .n
= { .min
= 1, .max
= 3 },
430 .m
= { .min
= 79, .max
= 118 },
431 .m1
= { .min
= 12, .max
= 22 },
432 .m2
= { .min
= 5, .max
= 9 },
433 .p
= { .min
= 28, .max
= 112 },
434 .p1
= { .min
= 2, .max
= 8 },
435 .p2
= { .dot_limit
= 225000,
436 .p2_slow
= 14, .p2_fast
= 14 },
439 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
440 .dot
= { .min
= 25000, .max
= 350000 },
441 .vco
= { .min
= 1760000, .max
= 3510000 },
442 .n
= { .min
= 1, .max
= 3 },
443 .m
= { .min
= 79, .max
= 127 },
444 .m1
= { .min
= 12, .max
= 22 },
445 .m2
= { .min
= 5, .max
= 9 },
446 .p
= { .min
= 14, .max
= 56 },
447 .p1
= { .min
= 2, .max
= 8 },
448 .p2
= { .dot_limit
= 225000,
449 .p2_slow
= 7, .p2_fast
= 7 },
452 /* LVDS 100mhz refclk limits. */
453 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
454 .dot
= { .min
= 25000, .max
= 350000 },
455 .vco
= { .min
= 1760000, .max
= 3510000 },
456 .n
= { .min
= 1, .max
= 2 },
457 .m
= { .min
= 79, .max
= 126 },
458 .m1
= { .min
= 12, .max
= 22 },
459 .m2
= { .min
= 5, .max
= 9 },
460 .p
= { .min
= 28, .max
= 112 },
461 .p1
= { .min
= 2, .max
= 8 },
462 .p2
= { .dot_limit
= 225000,
463 .p2_slow
= 14, .p2_fast
= 14 },
466 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
467 .dot
= { .min
= 25000, .max
= 350000 },
468 .vco
= { .min
= 1760000, .max
= 3510000 },
469 .n
= { .min
= 1, .max
= 3 },
470 .m
= { .min
= 79, .max
= 126 },
471 .m1
= { .min
= 12, .max
= 22 },
472 .m2
= { .min
= 5, .max
= 9 },
473 .p
= { .min
= 14, .max
= 42 },
474 .p1
= { .min
= 2, .max
= 6 },
475 .p2
= { .dot_limit
= 225000,
476 .p2_slow
= 7, .p2_fast
= 7 },
479 static const intel_limit_t intel_limits_vlv
= {
481 * These are the data rate limits (measured in fast clocks)
482 * since those are the strictest limits we have. The fast
483 * clock and actual rate limits are more relaxed, so checking
484 * them would make no difference.
486 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
487 .vco
= { .min
= 4000000, .max
= 6000000 },
488 .n
= { .min
= 1, .max
= 7 },
489 .m1
= { .min
= 2, .max
= 3 },
490 .m2
= { .min
= 11, .max
= 156 },
491 .p1
= { .min
= 2, .max
= 3 },
492 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
495 static const intel_limit_t intel_limits_chv
= {
497 * These are the data rate limits (measured in fast clocks)
498 * since those are the strictest limits we have. The fast
499 * clock and actual rate limits are more relaxed, so checking
500 * them would make no difference.
502 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
503 .vco
= { .min
= 4800000, .max
= 6480000 },
504 .n
= { .min
= 1, .max
= 1 },
505 .m1
= { .min
= 2, .max
= 2 },
506 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
507 .p1
= { .min
= 2, .max
= 4 },
508 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
511 static const intel_limit_t intel_limits_bxt
= {
512 /* FIXME: find real dot limits */
513 .dot
= { .min
= 0, .max
= INT_MAX
},
514 .vco
= { .min
= 4800000, .max
= 6700000 },
515 .n
= { .min
= 1, .max
= 1 },
516 .m1
= { .min
= 2, .max
= 2 },
517 /* FIXME: find real m2 limits */
518 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
519 .p1
= { .min
= 2, .max
= 4 },
520 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
524 needs_modeset(struct drm_crtc_state
*state
)
526 return drm_atomic_crtc_needs_modeset(state
);
530 * Returns whether any output on the specified pipe is of the specified type
532 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
534 struct drm_device
*dev
= crtc
->base
.dev
;
535 struct intel_encoder
*encoder
;
537 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
538 if (encoder
->type
== type
)
545 * Returns whether any output on the specified pipe will have the specified
546 * type after a staged modeset is complete, i.e., the same as
547 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
550 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
553 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
554 struct drm_connector
*connector
;
555 struct drm_connector_state
*connector_state
;
556 struct intel_encoder
*encoder
;
557 int i
, num_connectors
= 0;
559 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
560 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
565 encoder
= to_intel_encoder(connector_state
->best_encoder
);
566 if (encoder
->type
== type
)
570 WARN_ON(num_connectors
== 0);
576 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
577 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
578 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
579 * The helpers' return value is the rate of the clock that is fed to the
580 * display engine's pipe which can be the above fast dot clock rate or a
581 * divided-down version of it.
583 /* m1 is reserved as 0 in Pineview, n is a ring counter */
584 static int pnv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
586 clock
->m
= clock
->m2
+ 2;
587 clock
->p
= clock
->p1
* clock
->p2
;
588 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
590 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
591 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
596 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
598 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
601 static int i9xx_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
603 clock
->m
= i9xx_dpll_compute_m(clock
);
604 clock
->p
= clock
->p1
* clock
->p2
;
605 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
607 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
608 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
613 static int vlv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
615 clock
->m
= clock
->m1
* clock
->m2
;
616 clock
->p
= clock
->p1
* clock
->p2
;
617 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
619 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
620 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
622 return clock
->dot
/ 5;
625 int chv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
627 clock
->m
= clock
->m1
* clock
->m2
;
628 clock
->p
= clock
->p1
* clock
->p2
;
629 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
631 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
633 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
635 return clock
->dot
/ 5;
638 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
640 * Returns whether the given set of divisors are valid for a given refclk with
641 * the given connectors.
644 static bool intel_PLL_is_valid(struct drm_device
*dev
,
645 const intel_limit_t
*limit
,
646 const intel_clock_t
*clock
)
648 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
649 INTELPllInvalid("n out of range\n");
650 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
651 INTELPllInvalid("p1 out of range\n");
652 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
653 INTELPllInvalid("m2 out of range\n");
654 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
655 INTELPllInvalid("m1 out of range\n");
657 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) &&
658 !IS_CHERRYVIEW(dev
) && !IS_BROXTON(dev
))
659 if (clock
->m1
<= clock
->m2
)
660 INTELPllInvalid("m1 <= m2\n");
662 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) && !IS_BROXTON(dev
)) {
663 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
664 INTELPllInvalid("p out of range\n");
665 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
666 INTELPllInvalid("m out of range\n");
669 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
670 INTELPllInvalid("vco out of range\n");
671 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
672 * connector, etc., rather than just a single range.
674 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
675 INTELPllInvalid("dot out of range\n");
681 i9xx_select_p2_div(const intel_limit_t
*limit
,
682 const struct intel_crtc_state
*crtc_state
,
685 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
687 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
689 * For LVDS just rely on its current settings for dual-channel.
690 * We haven't figured out how to reliably set up different
691 * single/dual channel state, if we even can.
693 if (intel_is_dual_link_lvds(dev
))
694 return limit
->p2
.p2_fast
;
696 return limit
->p2
.p2_slow
;
698 if (target
< limit
->p2
.dot_limit
)
699 return limit
->p2
.p2_slow
;
701 return limit
->p2
.p2_fast
;
706 * Returns a set of divisors for the desired target clock with the given
707 * refclk, or FALSE. The returned values represent the clock equation:
708 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
710 * Target and reference clocks are specified in kHz.
712 * If match_clock is provided, then best_clock P divider must match the P
713 * divider from @match_clock used for LVDS downclocking.
716 i9xx_find_best_dpll(const intel_limit_t
*limit
,
717 struct intel_crtc_state
*crtc_state
,
718 int target
, int refclk
, intel_clock_t
*match_clock
,
719 intel_clock_t
*best_clock
)
721 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
725 memset(best_clock
, 0, sizeof(*best_clock
));
727 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
729 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
731 for (clock
.m2
= limit
->m2
.min
;
732 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
733 if (clock
.m2
>= clock
.m1
)
735 for (clock
.n
= limit
->n
.min
;
736 clock
.n
<= limit
->n
.max
; clock
.n
++) {
737 for (clock
.p1
= limit
->p1
.min
;
738 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
741 i9xx_calc_dpll_params(refclk
, &clock
);
742 if (!intel_PLL_is_valid(dev
, limit
,
746 clock
.p
!= match_clock
->p
)
749 this_err
= abs(clock
.dot
- target
);
750 if (this_err
< err
) {
759 return (err
!= target
);
763 * Returns a set of divisors for the desired target clock with the given
764 * refclk, or FALSE. The returned values represent the clock equation:
765 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
767 * Target and reference clocks are specified in kHz.
769 * If match_clock is provided, then best_clock P divider must match the P
770 * divider from @match_clock used for LVDS downclocking.
773 pnv_find_best_dpll(const intel_limit_t
*limit
,
774 struct intel_crtc_state
*crtc_state
,
775 int target
, int refclk
, intel_clock_t
*match_clock
,
776 intel_clock_t
*best_clock
)
778 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
782 memset(best_clock
, 0, sizeof(*best_clock
));
784 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
786 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
788 for (clock
.m2
= limit
->m2
.min
;
789 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
790 for (clock
.n
= limit
->n
.min
;
791 clock
.n
<= limit
->n
.max
; clock
.n
++) {
792 for (clock
.p1
= limit
->p1
.min
;
793 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
796 pnv_calc_dpll_params(refclk
, &clock
);
797 if (!intel_PLL_is_valid(dev
, limit
,
801 clock
.p
!= match_clock
->p
)
804 this_err
= abs(clock
.dot
- target
);
805 if (this_err
< err
) {
814 return (err
!= target
);
818 * Returns a set of divisors for the desired target clock with the given
819 * refclk, or FALSE. The returned values represent the clock equation:
820 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
822 * Target and reference clocks are specified in kHz.
824 * If match_clock is provided, then best_clock P divider must match the P
825 * divider from @match_clock used for LVDS downclocking.
828 g4x_find_best_dpll(const intel_limit_t
*limit
,
829 struct intel_crtc_state
*crtc_state
,
830 int target
, int refclk
, intel_clock_t
*match_clock
,
831 intel_clock_t
*best_clock
)
833 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
837 /* approximately equals target * 0.00585 */
838 int err_most
= (target
>> 8) + (target
>> 9);
840 memset(best_clock
, 0, sizeof(*best_clock
));
842 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
844 max_n
= limit
->n
.max
;
845 /* based on hardware requirement, prefer smaller n to precision */
846 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
847 /* based on hardware requirement, prefere larger m1,m2 */
848 for (clock
.m1
= limit
->m1
.max
;
849 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
850 for (clock
.m2
= limit
->m2
.max
;
851 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
852 for (clock
.p1
= limit
->p1
.max
;
853 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
856 i9xx_calc_dpll_params(refclk
, &clock
);
857 if (!intel_PLL_is_valid(dev
, limit
,
861 this_err
= abs(clock
.dot
- target
);
862 if (this_err
< err_most
) {
876 * Check if the calculated PLL configuration is more optimal compared to the
877 * best configuration and error found so far. Return the calculated error.
879 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
880 const intel_clock_t
*calculated_clock
,
881 const intel_clock_t
*best_clock
,
882 unsigned int best_error_ppm
,
883 unsigned int *error_ppm
)
886 * For CHV ignore the error and consider only the P value.
887 * Prefer a bigger P value based on HW requirements.
889 if (IS_CHERRYVIEW(dev
)) {
892 return calculated_clock
->p
> best_clock
->p
;
895 if (WARN_ON_ONCE(!target_freq
))
898 *error_ppm
= div_u64(1000000ULL *
899 abs(target_freq
- calculated_clock
->dot
),
902 * Prefer a better P value over a better (smaller) error if the error
903 * is small. Ensure this preference for future configurations too by
904 * setting the error to 0.
906 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
912 return *error_ppm
+ 10 < best_error_ppm
;
916 * Returns a set of divisors for the desired target clock with the given
917 * refclk, or FALSE. The returned values represent the clock equation:
918 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
921 vlv_find_best_dpll(const intel_limit_t
*limit
,
922 struct intel_crtc_state
*crtc_state
,
923 int target
, int refclk
, intel_clock_t
*match_clock
,
924 intel_clock_t
*best_clock
)
926 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
927 struct drm_device
*dev
= crtc
->base
.dev
;
929 unsigned int bestppm
= 1000000;
930 /* min update 19.2 MHz */
931 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
934 target
*= 5; /* fast clock */
936 memset(best_clock
, 0, sizeof(*best_clock
));
938 /* based on hardware requirement, prefer smaller n to precision */
939 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
940 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
941 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
942 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
943 clock
.p
= clock
.p1
* clock
.p2
;
944 /* based on hardware requirement, prefer bigger m1,m2 values */
945 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
948 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
951 vlv_calc_dpll_params(refclk
, &clock
);
953 if (!intel_PLL_is_valid(dev
, limit
,
957 if (!vlv_PLL_is_optimal(dev
, target
,
975 * Returns a set of divisors for the desired target clock with the given
976 * refclk, or FALSE. The returned values represent the clock equation:
977 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
980 chv_find_best_dpll(const intel_limit_t
*limit
,
981 struct intel_crtc_state
*crtc_state
,
982 int target
, int refclk
, intel_clock_t
*match_clock
,
983 intel_clock_t
*best_clock
)
985 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
986 struct drm_device
*dev
= crtc
->base
.dev
;
987 unsigned int best_error_ppm
;
992 memset(best_clock
, 0, sizeof(*best_clock
));
993 best_error_ppm
= 1000000;
996 * Based on hardware doc, the n always set to 1, and m1 always
997 * set to 2. If requires to support 200Mhz refclk, we need to
998 * revisit this because n may not 1 anymore.
1000 clock
.n
= 1, clock
.m1
= 2;
1001 target
*= 5; /* fast clock */
1003 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
1004 for (clock
.p2
= limit
->p2
.p2_fast
;
1005 clock
.p2
>= limit
->p2
.p2_slow
;
1006 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
1007 unsigned int error_ppm
;
1009 clock
.p
= clock
.p1
* clock
.p2
;
1011 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
1012 clock
.n
) << 22, refclk
* clock
.m1
);
1014 if (m2
> INT_MAX
/clock
.m1
)
1019 chv_calc_dpll_params(refclk
, &clock
);
1021 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
1024 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
1025 best_error_ppm
, &error_ppm
))
1028 *best_clock
= clock
;
1029 best_error_ppm
= error_ppm
;
1037 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1038 intel_clock_t
*best_clock
)
1040 int refclk
= 100000;
1041 const intel_limit_t
*limit
= &intel_limits_bxt
;
1043 return chv_find_best_dpll(limit
, crtc_state
,
1044 target_clock
, refclk
, NULL
, best_clock
);
1047 bool intel_crtc_active(struct drm_crtc
*crtc
)
1049 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1051 /* Be paranoid as we can arrive here with only partial
1052 * state retrieved from the hardware during setup.
1054 * We can ditch the adjusted_mode.crtc_clock check as soon
1055 * as Haswell has gained clock readout/fastboot support.
1057 * We can ditch the crtc->primary->fb check as soon as we can
1058 * properly reconstruct framebuffers.
1060 * FIXME: The intel_crtc->active here should be switched to
1061 * crtc->state->active once we have proper CRTC states wired up
1064 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
1065 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1068 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1071 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1072 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1074 return intel_crtc
->config
->cpu_transcoder
;
1077 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1080 i915_reg_t reg
= PIPEDSL(pipe
);
1085 line_mask
= DSL_LINEMASK_GEN2
;
1087 line_mask
= DSL_LINEMASK_GEN3
;
1089 line1
= I915_READ(reg
) & line_mask
;
1091 line2
= I915_READ(reg
) & line_mask
;
1093 return line1
== line2
;
1097 * intel_wait_for_pipe_off - wait for pipe to turn off
1098 * @crtc: crtc whose pipe to wait for
1100 * After disabling a pipe, we can't wait for vblank in the usual way,
1101 * spinning on the vblank interrupt status bit, since we won't actually
1102 * see an interrupt when the pipe is disabled.
1104 * On Gen4 and above:
1105 * wait for the pipe register state bit to turn off
1108 * wait for the display line value to settle (it usually
1109 * ends up stopping at the start of the next frame).
1112 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1114 struct drm_device
*dev
= crtc
->base
.dev
;
1115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1116 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1117 enum pipe pipe
= crtc
->pipe
;
1119 if (INTEL_INFO(dev
)->gen
>= 4) {
1120 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
1122 /* Wait for the Pipe State to go off */
1123 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1125 WARN(1, "pipe_off wait timed out\n");
1127 /* Wait for the display line to settle */
1128 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1129 WARN(1, "pipe_off wait timed out\n");
1133 /* Only for pre-ILK configs */
1134 void assert_pll(struct drm_i915_private
*dev_priv
,
1135 enum pipe pipe
, bool state
)
1140 val
= I915_READ(DPLL(pipe
));
1141 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1142 I915_STATE_WARN(cur_state
!= state
,
1143 "PLL state assertion failure (expected %s, current %s)\n",
1144 onoff(state
), onoff(cur_state
));
1147 /* XXX: the dsi pll is shared between MIPI DSI ports */
1148 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1153 mutex_lock(&dev_priv
->sb_lock
);
1154 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1155 mutex_unlock(&dev_priv
->sb_lock
);
1157 cur_state
= val
& DSI_PLL_VCO_EN
;
1158 I915_STATE_WARN(cur_state
!= state
,
1159 "DSI PLL state assertion failure (expected %s, current %s)\n",
1160 onoff(state
), onoff(cur_state
));
1163 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1164 enum pipe pipe
, bool state
)
1167 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1170 if (HAS_DDI(dev_priv
)) {
1171 /* DDI does not have a specific FDI_TX register */
1172 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1173 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1175 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1176 cur_state
= !!(val
& FDI_TX_ENABLE
);
1178 I915_STATE_WARN(cur_state
!= state
,
1179 "FDI TX state assertion failure (expected %s, current %s)\n",
1180 onoff(state
), onoff(cur_state
));
1182 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1183 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1185 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1186 enum pipe pipe
, bool state
)
1191 val
= I915_READ(FDI_RX_CTL(pipe
));
1192 cur_state
= !!(val
& FDI_RX_ENABLE
);
1193 I915_STATE_WARN(cur_state
!= state
,
1194 "FDI RX state assertion failure (expected %s, current %s)\n",
1195 onoff(state
), onoff(cur_state
));
1197 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1198 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1200 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1205 /* ILK FDI PLL is always enabled */
1206 if (INTEL_INFO(dev_priv
)->gen
== 5)
1209 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1210 if (HAS_DDI(dev_priv
))
1213 val
= I915_READ(FDI_TX_CTL(pipe
));
1214 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1217 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1218 enum pipe pipe
, bool state
)
1223 val
= I915_READ(FDI_RX_CTL(pipe
));
1224 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1225 I915_STATE_WARN(cur_state
!= state
,
1226 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1227 onoff(state
), onoff(cur_state
));
1230 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1233 struct drm_device
*dev
= dev_priv
->dev
;
1236 enum pipe panel_pipe
= PIPE_A
;
1239 if (WARN_ON(HAS_DDI(dev
)))
1242 if (HAS_PCH_SPLIT(dev
)) {
1245 pp_reg
= PCH_PP_CONTROL
;
1246 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1248 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1249 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1250 panel_pipe
= PIPE_B
;
1251 /* XXX: else fix for eDP */
1252 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1253 /* presumably write lock depends on pipe, not port select */
1254 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1257 pp_reg
= PP_CONTROL
;
1258 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1259 panel_pipe
= PIPE_B
;
1262 val
= I915_READ(pp_reg
);
1263 if (!(val
& PANEL_POWER_ON
) ||
1264 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1267 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1268 "panel assertion failure, pipe %c regs locked\n",
1272 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1273 enum pipe pipe
, bool state
)
1275 struct drm_device
*dev
= dev_priv
->dev
;
1278 if (IS_845G(dev
) || IS_I865G(dev
))
1279 cur_state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
1281 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1283 I915_STATE_WARN(cur_state
!= state
,
1284 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1285 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1287 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1288 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1290 void assert_pipe(struct drm_i915_private
*dev_priv
,
1291 enum pipe pipe
, bool state
)
1294 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1296 enum intel_display_power_domain power_domain
;
1298 /* if we need the pipe quirk it must be always on */
1299 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1300 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1303 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
1304 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
1305 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1306 cur_state
= !!(val
& PIPECONF_ENABLE
);
1308 intel_display_power_put(dev_priv
, power_domain
);
1313 I915_STATE_WARN(cur_state
!= state
,
1314 "pipe %c assertion failure (expected %s, current %s)\n",
1315 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1318 static void assert_plane(struct drm_i915_private
*dev_priv
,
1319 enum plane plane
, bool state
)
1324 val
= I915_READ(DSPCNTR(plane
));
1325 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1326 I915_STATE_WARN(cur_state
!= state
,
1327 "plane %c assertion failure (expected %s, current %s)\n",
1328 plane_name(plane
), onoff(state
), onoff(cur_state
));
1331 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1332 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1334 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1337 struct drm_device
*dev
= dev_priv
->dev
;
1340 /* Primary planes are fixed to pipes on gen4+ */
1341 if (INTEL_INFO(dev
)->gen
>= 4) {
1342 u32 val
= I915_READ(DSPCNTR(pipe
));
1343 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1344 "plane %c assertion failure, should be disabled but not\n",
1349 /* Need to check both planes against the pipe */
1350 for_each_pipe(dev_priv
, i
) {
1351 u32 val
= I915_READ(DSPCNTR(i
));
1352 enum pipe cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1353 DISPPLANE_SEL_PIPE_SHIFT
;
1354 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1355 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1356 plane_name(i
), pipe_name(pipe
));
1360 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1363 struct drm_device
*dev
= dev_priv
->dev
;
1366 if (INTEL_INFO(dev
)->gen
>= 9) {
1367 for_each_sprite(dev_priv
, pipe
, sprite
) {
1368 u32 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1369 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1370 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1371 sprite
, pipe_name(pipe
));
1373 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1374 for_each_sprite(dev_priv
, pipe
, sprite
) {
1375 u32 val
= I915_READ(SPCNTR(pipe
, sprite
));
1376 I915_STATE_WARN(val
& SP_ENABLE
,
1377 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1378 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1380 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1381 u32 val
= I915_READ(SPRCTL(pipe
));
1382 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1383 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1384 plane_name(pipe
), pipe_name(pipe
));
1385 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1386 u32 val
= I915_READ(DVSCNTR(pipe
));
1387 I915_STATE_WARN(val
& DVS_ENABLE
,
1388 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(pipe
), pipe_name(pipe
));
1393 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1395 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1396 drm_crtc_vblank_put(crtc
);
1399 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1405 val
= I915_READ(PCH_TRANSCONF(pipe
));
1406 enabled
= !!(val
& TRANS_ENABLE
);
1407 I915_STATE_WARN(enabled
,
1408 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1412 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1413 enum pipe pipe
, u32 port_sel
, u32 val
)
1415 if ((val
& DP_PORT_EN
) == 0)
1418 if (HAS_PCH_CPT(dev_priv
)) {
1419 u32 trans_dp_ctl
= I915_READ(TRANS_DP_CTL(pipe
));
1420 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1422 } else if (IS_CHERRYVIEW(dev_priv
)) {
1423 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1426 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1432 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1433 enum pipe pipe
, u32 val
)
1435 if ((val
& SDVO_ENABLE
) == 0)
1438 if (HAS_PCH_CPT(dev_priv
)) {
1439 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1441 } else if (IS_CHERRYVIEW(dev_priv
)) {
1442 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1445 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1451 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1452 enum pipe pipe
, u32 val
)
1454 if ((val
& LVDS_PORT_EN
) == 0)
1457 if (HAS_PCH_CPT(dev_priv
)) {
1458 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1461 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1467 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1468 enum pipe pipe
, u32 val
)
1470 if ((val
& ADPA_DAC_ENABLE
) == 0)
1472 if (HAS_PCH_CPT(dev_priv
)) {
1473 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1476 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1482 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1483 enum pipe pipe
, i915_reg_t reg
,
1486 u32 val
= I915_READ(reg
);
1487 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1488 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1489 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1491 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& DP_PORT_EN
) == 0
1492 && (val
& DP_PIPEB_SELECT
),
1493 "IBX PCH dp port still using transcoder B\n");
1496 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1497 enum pipe pipe
, i915_reg_t reg
)
1499 u32 val
= I915_READ(reg
);
1500 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1501 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1502 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1504 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& SDVO_ENABLE
) == 0
1505 && (val
& SDVO_PIPE_B_SELECT
),
1506 "IBX PCH hdmi port still using transcoder B\n");
1509 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1514 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1515 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1516 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1518 val
= I915_READ(PCH_ADPA
);
1519 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1520 "PCH VGA enabled on transcoder %c, should be disabled\n",
1523 val
= I915_READ(PCH_LVDS
);
1524 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1525 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1528 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1529 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1530 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1533 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1534 const struct intel_crtc_state
*pipe_config
)
1536 struct drm_device
*dev
= crtc
->base
.dev
;
1537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1538 enum pipe pipe
= crtc
->pipe
;
1539 i915_reg_t reg
= DPLL(pipe
);
1540 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1542 assert_pipe_disabled(dev_priv
, pipe
);
1544 /* PLL is protected by panel, make sure we can write it */
1545 assert_panel_unlocked(dev_priv
, pipe
);
1547 I915_WRITE(reg
, dpll
);
1551 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1552 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
1554 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1555 POSTING_READ(DPLL_MD(pipe
));
1558 static void chv_enable_pll(struct intel_crtc
*crtc
,
1559 const struct intel_crtc_state
*pipe_config
)
1561 struct drm_device
*dev
= crtc
->base
.dev
;
1562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1563 enum pipe pipe
= crtc
->pipe
;
1564 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1567 assert_pipe_disabled(dev_priv
, pipe
);
1569 /* PLL is protected by panel, make sure we can write it */
1570 assert_panel_unlocked(dev_priv
, pipe
);
1572 mutex_lock(&dev_priv
->sb_lock
);
1574 /* Enable back the 10bit clock to display controller */
1575 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1576 tmp
|= DPIO_DCLKP_EN
;
1577 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1579 mutex_unlock(&dev_priv
->sb_lock
);
1582 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1587 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1589 /* Check PLL is locked */
1590 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1591 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1593 if (pipe
!= PIPE_A
) {
1595 * WaPixelRepeatModeFixForC0:chv
1597 * DPLLCMD is AWOL. Use chicken bits to propagate
1598 * the value from DPLLBMD to either pipe B or C.
1600 I915_WRITE(CBR4_VLV
, pipe
== PIPE_B
? CBR_DPLLBMD_PIPE_B
: CBR_DPLLBMD_PIPE_C
);
1601 I915_WRITE(DPLL_MD(PIPE_B
), pipe_config
->dpll_hw_state
.dpll_md
);
1602 I915_WRITE(CBR4_VLV
, 0);
1603 dev_priv
->chv_dpll_md
[pipe
] = pipe_config
->dpll_hw_state
.dpll_md
;
1606 * DPLLB VGA mode also seems to cause problems.
1607 * We should always have it disabled.
1609 WARN_ON((I915_READ(DPLL(PIPE_B
)) & DPLL_VGA_MODE_DIS
) == 0);
1611 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1612 POSTING_READ(DPLL_MD(pipe
));
1616 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1618 struct intel_crtc
*crtc
;
1621 for_each_intel_crtc(dev
, crtc
)
1622 count
+= crtc
->base
.state
->active
&&
1623 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1628 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1630 struct drm_device
*dev
= crtc
->base
.dev
;
1631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1632 i915_reg_t reg
= DPLL(crtc
->pipe
);
1633 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1635 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1637 /* PLL is protected by panel, make sure we can write it */
1638 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1639 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1641 /* Enable DVO 2x clock on both PLLs if necessary */
1642 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1644 * It appears to be important that we don't enable this
1645 * for the current pipe before otherwise configuring the
1646 * PLL. No idea how this should be handled if multiple
1647 * DVO outputs are enabled simultaneosly.
1649 dpll
|= DPLL_DVO_2X_MODE
;
1650 I915_WRITE(DPLL(!crtc
->pipe
),
1651 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1655 * Apparently we need to have VGA mode enabled prior to changing
1656 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1657 * dividers, even though the register value does change.
1661 I915_WRITE(reg
, dpll
);
1663 /* Wait for the clocks to stabilize. */
1667 if (INTEL_INFO(dev
)->gen
>= 4) {
1668 I915_WRITE(DPLL_MD(crtc
->pipe
),
1669 crtc
->config
->dpll_hw_state
.dpll_md
);
1671 /* The pixel multiplier can only be updated once the
1672 * DPLL is enabled and the clocks are stable.
1674 * So write it again.
1676 I915_WRITE(reg
, dpll
);
1679 /* We do this three times for luck */
1680 I915_WRITE(reg
, dpll
);
1682 udelay(150); /* wait for warmup */
1683 I915_WRITE(reg
, dpll
);
1685 udelay(150); /* wait for warmup */
1686 I915_WRITE(reg
, dpll
);
1688 udelay(150); /* wait for warmup */
1692 * i9xx_disable_pll - disable a PLL
1693 * @dev_priv: i915 private structure
1694 * @pipe: pipe PLL to disable
1696 * Disable the PLL for @pipe, making sure the pipe is off first.
1698 * Note! This is for pre-ILK only.
1700 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1702 struct drm_device
*dev
= crtc
->base
.dev
;
1703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1704 enum pipe pipe
= crtc
->pipe
;
1706 /* Disable DVO 2x clock on both PLLs if necessary */
1708 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1709 !intel_num_dvo_pipes(dev
)) {
1710 I915_WRITE(DPLL(PIPE_B
),
1711 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1712 I915_WRITE(DPLL(PIPE_A
),
1713 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1716 /* Don't disable pipe or pipe PLLs if needed */
1717 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1718 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1721 /* Make sure the pipe isn't still relying on us */
1722 assert_pipe_disabled(dev_priv
, pipe
);
1724 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1725 POSTING_READ(DPLL(pipe
));
1728 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1732 /* Make sure the pipe isn't still relying on us */
1733 assert_pipe_disabled(dev_priv
, pipe
);
1735 val
= DPLL_INTEGRATED_REF_CLK_VLV
|
1736 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1738 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1740 I915_WRITE(DPLL(pipe
), val
);
1741 POSTING_READ(DPLL(pipe
));
1744 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1746 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1749 /* Make sure the pipe isn't still relying on us */
1750 assert_pipe_disabled(dev_priv
, pipe
);
1752 val
= DPLL_SSC_REF_CLK_CHV
|
1753 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1755 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1757 I915_WRITE(DPLL(pipe
), val
);
1758 POSTING_READ(DPLL(pipe
));
1760 mutex_lock(&dev_priv
->sb_lock
);
1762 /* Disable 10bit clock to display controller */
1763 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1764 val
&= ~DPIO_DCLKP_EN
;
1765 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1767 mutex_unlock(&dev_priv
->sb_lock
);
1770 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1771 struct intel_digital_port
*dport
,
1772 unsigned int expected_mask
)
1775 i915_reg_t dpll_reg
;
1777 switch (dport
->port
) {
1779 port_mask
= DPLL_PORTB_READY_MASK
;
1783 port_mask
= DPLL_PORTC_READY_MASK
;
1785 expected_mask
<<= 4;
1788 port_mask
= DPLL_PORTD_READY_MASK
;
1789 dpll_reg
= DPIO_PHY_STATUS
;
1795 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == expected_mask
, 1000))
1796 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1797 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1800 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1803 struct drm_device
*dev
= dev_priv
->dev
;
1804 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1805 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1807 uint32_t val
, pipeconf_val
;
1809 /* Make sure PCH DPLL is enabled */
1810 assert_shared_dpll_enabled(dev_priv
, intel_crtc
->config
->shared_dpll
);
1812 /* FDI must be feeding us bits for PCH ports */
1813 assert_fdi_tx_enabled(dev_priv
, pipe
);
1814 assert_fdi_rx_enabled(dev_priv
, pipe
);
1816 if (HAS_PCH_CPT(dev
)) {
1817 /* Workaround: Set the timing override bit before enabling the
1818 * pch transcoder. */
1819 reg
= TRANS_CHICKEN2(pipe
);
1820 val
= I915_READ(reg
);
1821 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1822 I915_WRITE(reg
, val
);
1825 reg
= PCH_TRANSCONF(pipe
);
1826 val
= I915_READ(reg
);
1827 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1829 if (HAS_PCH_IBX(dev_priv
)) {
1831 * Make the BPC in transcoder be consistent with
1832 * that in pipeconf reg. For HDMI we must use 8bpc
1833 * here for both 8bpc and 12bpc.
1835 val
&= ~PIPECONF_BPC_MASK
;
1836 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_HDMI
))
1837 val
|= PIPECONF_8BPC
;
1839 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1842 val
&= ~TRANS_INTERLACE_MASK
;
1843 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1844 if (HAS_PCH_IBX(dev_priv
) &&
1845 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1846 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1848 val
|= TRANS_INTERLACED
;
1850 val
|= TRANS_PROGRESSIVE
;
1852 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1853 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1854 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1857 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1858 enum transcoder cpu_transcoder
)
1860 u32 val
, pipeconf_val
;
1862 /* FDI must be feeding us bits for PCH ports */
1863 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1864 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1866 /* Workaround: set timing override bit. */
1867 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1868 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1869 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1872 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1874 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1875 PIPECONF_INTERLACED_ILK
)
1876 val
|= TRANS_INTERLACED
;
1878 val
|= TRANS_PROGRESSIVE
;
1880 I915_WRITE(LPT_TRANSCONF
, val
);
1881 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1882 DRM_ERROR("Failed to enable PCH transcoder\n");
1885 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1888 struct drm_device
*dev
= dev_priv
->dev
;
1892 /* FDI relies on the transcoder */
1893 assert_fdi_tx_disabled(dev_priv
, pipe
);
1894 assert_fdi_rx_disabled(dev_priv
, pipe
);
1896 /* Ports must be off as well */
1897 assert_pch_ports_disabled(dev_priv
, pipe
);
1899 reg
= PCH_TRANSCONF(pipe
);
1900 val
= I915_READ(reg
);
1901 val
&= ~TRANS_ENABLE
;
1902 I915_WRITE(reg
, val
);
1903 /* wait for PCH transcoder off, transcoder state */
1904 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1905 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1907 if (HAS_PCH_CPT(dev
)) {
1908 /* Workaround: Clear the timing override chicken bit again. */
1909 reg
= TRANS_CHICKEN2(pipe
);
1910 val
= I915_READ(reg
);
1911 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1912 I915_WRITE(reg
, val
);
1916 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1920 val
= I915_READ(LPT_TRANSCONF
);
1921 val
&= ~TRANS_ENABLE
;
1922 I915_WRITE(LPT_TRANSCONF
, val
);
1923 /* wait for PCH transcoder off, transcoder state */
1924 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1925 DRM_ERROR("Failed to disable PCH transcoder\n");
1927 /* Workaround: clear timing override bit. */
1928 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1929 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1930 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1934 * intel_enable_pipe - enable a pipe, asserting requirements
1935 * @crtc: crtc responsible for the pipe
1937 * Enable @crtc's pipe, making sure that various hardware specific requirements
1938 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1940 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1942 struct drm_device
*dev
= crtc
->base
.dev
;
1943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1944 enum pipe pipe
= crtc
->pipe
;
1945 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1946 enum pipe pch_transcoder
;
1950 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
1952 assert_planes_disabled(dev_priv
, pipe
);
1953 assert_cursor_disabled(dev_priv
, pipe
);
1954 assert_sprites_disabled(dev_priv
, pipe
);
1956 if (HAS_PCH_LPT(dev_priv
))
1957 pch_transcoder
= TRANSCODER_A
;
1959 pch_transcoder
= pipe
;
1962 * A pipe without a PLL won't actually be able to drive bits from
1963 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1966 if (HAS_GMCH_DISPLAY(dev_priv
))
1967 if (crtc
->config
->has_dsi_encoder
)
1968 assert_dsi_pll_enabled(dev_priv
);
1970 assert_pll_enabled(dev_priv
, pipe
);
1972 if (crtc
->config
->has_pch_encoder
) {
1973 /* if driving the PCH, we need FDI enabled */
1974 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1975 assert_fdi_tx_pll_enabled(dev_priv
,
1976 (enum pipe
) cpu_transcoder
);
1978 /* FIXME: assert CPU port conditions for SNB+ */
1981 reg
= PIPECONF(cpu_transcoder
);
1982 val
= I915_READ(reg
);
1983 if (val
& PIPECONF_ENABLE
) {
1984 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1985 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
1989 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1993 * Until the pipe starts DSL will read as 0, which would cause
1994 * an apparent vblank timestamp jump, which messes up also the
1995 * frame count when it's derived from the timestamps. So let's
1996 * wait for the pipe to start properly before we call
1997 * drm_crtc_vblank_on()
1999 if (dev
->max_vblank_count
== 0 &&
2000 wait_for(intel_get_crtc_scanline(crtc
) != crtc
->scanline_offset
, 50))
2001 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe
));
2005 * intel_disable_pipe - disable a pipe, asserting requirements
2006 * @crtc: crtc whose pipes is to be disabled
2008 * Disable the pipe of @crtc, making sure that various hardware
2009 * specific requirements are met, if applicable, e.g. plane
2010 * disabled, panel fitter off, etc.
2012 * Will wait until the pipe has shut down before returning.
2014 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2016 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2017 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2018 enum pipe pipe
= crtc
->pipe
;
2022 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
2025 * Make sure planes won't keep trying to pump pixels to us,
2026 * or we might hang the display.
2028 assert_planes_disabled(dev_priv
, pipe
);
2029 assert_cursor_disabled(dev_priv
, pipe
);
2030 assert_sprites_disabled(dev_priv
, pipe
);
2032 reg
= PIPECONF(cpu_transcoder
);
2033 val
= I915_READ(reg
);
2034 if ((val
& PIPECONF_ENABLE
) == 0)
2038 * Double wide has implications for planes
2039 * so best keep it disabled when not needed.
2041 if (crtc
->config
->double_wide
)
2042 val
&= ~PIPECONF_DOUBLE_WIDE
;
2044 /* Don't disable pipe or pipe PLLs if needed */
2045 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2046 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2047 val
&= ~PIPECONF_ENABLE
;
2049 I915_WRITE(reg
, val
);
2050 if ((val
& PIPECONF_ENABLE
) == 0)
2051 intel_wait_for_pipe_off(crtc
);
2054 static bool need_vtd_wa(struct drm_device
*dev
)
2056 #ifdef CONFIG_INTEL_IOMMU
2057 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2063 static unsigned int intel_tile_size(const struct drm_i915_private
*dev_priv
)
2065 return IS_GEN2(dev_priv
) ? 2048 : 4096;
2068 static unsigned int intel_tile_width_bytes(const struct drm_i915_private
*dev_priv
,
2069 uint64_t fb_modifier
, unsigned int cpp
)
2071 switch (fb_modifier
) {
2072 case DRM_FORMAT_MOD_NONE
:
2074 case I915_FORMAT_MOD_X_TILED
:
2075 if (IS_GEN2(dev_priv
))
2079 case I915_FORMAT_MOD_Y_TILED
:
2080 if (IS_GEN2(dev_priv
) || HAS_128_BYTE_Y_TILING(dev_priv
))
2084 case I915_FORMAT_MOD_Yf_TILED
:
2100 MISSING_CASE(fb_modifier
);
2105 unsigned int intel_tile_height(const struct drm_i915_private
*dev_priv
,
2106 uint64_t fb_modifier
, unsigned int cpp
)
2108 if (fb_modifier
== DRM_FORMAT_MOD_NONE
)
2111 return intel_tile_size(dev_priv
) /
2112 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2115 /* Return the tile dimensions in pixel units */
2116 static void intel_tile_dims(const struct drm_i915_private
*dev_priv
,
2117 unsigned int *tile_width
,
2118 unsigned int *tile_height
,
2119 uint64_t fb_modifier
,
2122 unsigned int tile_width_bytes
=
2123 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2125 *tile_width
= tile_width_bytes
/ cpp
;
2126 *tile_height
= intel_tile_size(dev_priv
) / tile_width_bytes
;
2130 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2131 uint32_t pixel_format
, uint64_t fb_modifier
)
2133 unsigned int cpp
= drm_format_plane_cpp(pixel_format
, 0);
2134 unsigned int tile_height
= intel_tile_height(to_i915(dev
), fb_modifier
, cpp
);
2136 return ALIGN(height
, tile_height
);
2139 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
2141 unsigned int size
= 0;
2144 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
2145 size
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2151 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
,
2152 const struct drm_framebuffer
*fb
,
2153 unsigned int rotation
)
2155 if (intel_rotation_90_or_270(rotation
)) {
2156 *view
= i915_ggtt_view_rotated
;
2157 view
->params
.rotated
= to_intel_framebuffer(fb
)->rot_info
;
2159 *view
= i915_ggtt_view_normal
;
2164 intel_fill_fb_info(struct drm_i915_private
*dev_priv
,
2165 struct drm_framebuffer
*fb
)
2167 struct intel_rotation_info
*info
= &to_intel_framebuffer(fb
)->rot_info
;
2168 unsigned int tile_size
, tile_width
, tile_height
, cpp
;
2170 tile_size
= intel_tile_size(dev_priv
);
2172 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2173 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2174 fb
->modifier
[0], cpp
);
2176 info
->plane
[0].width
= DIV_ROUND_UP(fb
->pitches
[0], tile_width
* cpp
);
2177 info
->plane
[0].height
= DIV_ROUND_UP(fb
->height
, tile_height
);
2179 if (info
->pixel_format
== DRM_FORMAT_NV12
) {
2180 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 1);
2181 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2182 fb
->modifier
[1], cpp
);
2184 info
->uv_offset
= fb
->offsets
[1];
2185 info
->plane
[1].width
= DIV_ROUND_UP(fb
->pitches
[1], tile_width
* cpp
);
2186 info
->plane
[1].height
= DIV_ROUND_UP(fb
->height
/ 2, tile_height
);
2190 static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv
)
2192 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2194 else if (IS_BROADWATER(dev_priv
) || IS_CRESTLINE(dev_priv
) ||
2195 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2197 else if (INTEL_INFO(dev_priv
)->gen
>= 4)
2203 static unsigned int intel_surf_alignment(const struct drm_i915_private
*dev_priv
,
2204 uint64_t fb_modifier
)
2206 switch (fb_modifier
) {
2207 case DRM_FORMAT_MOD_NONE
:
2208 return intel_linear_alignment(dev_priv
);
2209 case I915_FORMAT_MOD_X_TILED
:
2210 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2213 case I915_FORMAT_MOD_Y_TILED
:
2214 case I915_FORMAT_MOD_Yf_TILED
:
2215 return 1 * 1024 * 1024;
2217 MISSING_CASE(fb_modifier
);
2223 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
2224 unsigned int rotation
)
2226 struct drm_device
*dev
= fb
->dev
;
2227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2228 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2229 struct i915_ggtt_view view
;
2233 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2235 alignment
= intel_surf_alignment(dev_priv
, fb
->modifier
[0]);
2237 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2239 /* Note that the w/a also requires 64 PTE of padding following the
2240 * bo. We currently fill all unused PTE with the shadow page and so
2241 * we should always have valid PTE following the scanout preventing
2244 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2245 alignment
= 256 * 1024;
2248 * Global gtt pte registers are special registers which actually forward
2249 * writes to a chunk of system memory. Which means that there is no risk
2250 * that the register values disappear as soon as we call
2251 * intel_runtime_pm_put(), so it is correct to wrap only the
2252 * pin/unpin/fence and not more.
2254 intel_runtime_pm_get(dev_priv
);
2256 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
,
2261 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2262 * fence, whereas 965+ only requires a fence if using
2263 * framebuffer compression. For simplicity, we always install
2264 * a fence as the cost is not that onerous.
2266 if (view
.type
== I915_GGTT_VIEW_NORMAL
) {
2267 ret
= i915_gem_object_get_fence(obj
);
2268 if (ret
== -EDEADLK
) {
2270 * -EDEADLK means there are no free fences
2273 * This is propagated to atomic, but it uses
2274 * -EDEADLK to force a locking recovery, so
2275 * change the returned error to -EBUSY.
2282 i915_gem_object_pin_fence(obj
);
2285 intel_runtime_pm_put(dev_priv
);
2289 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2291 intel_runtime_pm_put(dev_priv
);
2295 static void intel_unpin_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
)
2297 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2298 struct i915_ggtt_view view
;
2300 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2302 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2304 if (view
.type
== I915_GGTT_VIEW_NORMAL
)
2305 i915_gem_object_unpin_fence(obj
);
2307 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2311 * Adjust the tile offset by moving the difference into
2314 * Input tile dimensions and pitch must already be
2315 * rotated to match x and y, and in pixel units.
2317 static u32
intel_adjust_tile_offset(int *x
, int *y
,
2318 unsigned int tile_width
,
2319 unsigned int tile_height
,
2320 unsigned int tile_size
,
2321 unsigned int pitch_tiles
,
2327 WARN_ON(old_offset
& (tile_size
- 1));
2328 WARN_ON(new_offset
& (tile_size
- 1));
2329 WARN_ON(new_offset
> old_offset
);
2331 tiles
= (old_offset
- new_offset
) / tile_size
;
2333 *y
+= tiles
/ pitch_tiles
* tile_height
;
2334 *x
+= tiles
% pitch_tiles
* tile_width
;
2340 * Computes the linear offset to the base tile and adjusts
2341 * x, y. bytes per pixel is assumed to be a power-of-two.
2343 * In the 90/270 rotated case, x and y are assumed
2344 * to be already rotated to match the rotated GTT view, and
2345 * pitch is the tile_height aligned framebuffer height.
2347 u32
intel_compute_tile_offset(int *x
, int *y
,
2348 const struct drm_framebuffer
*fb
, int plane
,
2350 unsigned int rotation
)
2352 const struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2353 uint64_t fb_modifier
= fb
->modifier
[plane
];
2354 unsigned int cpp
= drm_format_plane_cpp(fb
->pixel_format
, plane
);
2355 u32 offset
, offset_aligned
, alignment
;
2357 alignment
= intel_surf_alignment(dev_priv
, fb_modifier
);
2361 if (fb_modifier
!= DRM_FORMAT_MOD_NONE
) {
2362 unsigned int tile_size
, tile_width
, tile_height
;
2363 unsigned int tile_rows
, tiles
, pitch_tiles
;
2365 tile_size
= intel_tile_size(dev_priv
);
2366 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2369 if (intel_rotation_90_or_270(rotation
)) {
2370 pitch_tiles
= pitch
/ tile_height
;
2371 swap(tile_width
, tile_height
);
2373 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2376 tile_rows
= *y
/ tile_height
;
2379 tiles
= *x
/ tile_width
;
2382 offset
= (tile_rows
* pitch_tiles
+ tiles
) * tile_size
;
2383 offset_aligned
= offset
& ~alignment
;
2385 intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2386 tile_size
, pitch_tiles
,
2387 offset
, offset_aligned
);
2389 offset
= *y
* pitch
+ *x
* cpp
;
2390 offset_aligned
= offset
& ~alignment
;
2392 *y
= (offset
& alignment
) / pitch
;
2393 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2396 return offset_aligned
;
2399 static int i9xx_format_to_fourcc(int format
)
2402 case DISPPLANE_8BPP
:
2403 return DRM_FORMAT_C8
;
2404 case DISPPLANE_BGRX555
:
2405 return DRM_FORMAT_XRGB1555
;
2406 case DISPPLANE_BGRX565
:
2407 return DRM_FORMAT_RGB565
;
2409 case DISPPLANE_BGRX888
:
2410 return DRM_FORMAT_XRGB8888
;
2411 case DISPPLANE_RGBX888
:
2412 return DRM_FORMAT_XBGR8888
;
2413 case DISPPLANE_BGRX101010
:
2414 return DRM_FORMAT_XRGB2101010
;
2415 case DISPPLANE_RGBX101010
:
2416 return DRM_FORMAT_XBGR2101010
;
2420 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2423 case PLANE_CTL_FORMAT_RGB_565
:
2424 return DRM_FORMAT_RGB565
;
2426 case PLANE_CTL_FORMAT_XRGB_8888
:
2429 return DRM_FORMAT_ABGR8888
;
2431 return DRM_FORMAT_XBGR8888
;
2434 return DRM_FORMAT_ARGB8888
;
2436 return DRM_FORMAT_XRGB8888
;
2438 case PLANE_CTL_FORMAT_XRGB_2101010
:
2440 return DRM_FORMAT_XBGR2101010
;
2442 return DRM_FORMAT_XRGB2101010
;
2447 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2448 struct intel_initial_plane_config
*plane_config
)
2450 struct drm_device
*dev
= crtc
->base
.dev
;
2451 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2452 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2453 struct drm_i915_gem_object
*obj
= NULL
;
2454 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2455 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2456 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2457 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2460 size_aligned
-= base_aligned
;
2462 if (plane_config
->size
== 0)
2465 /* If the FB is too big, just don't use it since fbdev is not very
2466 * important and we should probably use that space with FBC or other
2468 if (size_aligned
* 2 > ggtt
->stolen_usable_size
)
2471 mutex_lock(&dev
->struct_mutex
);
2473 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2478 mutex_unlock(&dev
->struct_mutex
);
2482 obj
->tiling_mode
= plane_config
->tiling
;
2483 if (obj
->tiling_mode
== I915_TILING_X
)
2484 obj
->stride
= fb
->pitches
[0];
2486 mode_cmd
.pixel_format
= fb
->pixel_format
;
2487 mode_cmd
.width
= fb
->width
;
2488 mode_cmd
.height
= fb
->height
;
2489 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2490 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2491 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2493 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2495 DRM_DEBUG_KMS("intel fb init failed\n");
2499 mutex_unlock(&dev
->struct_mutex
);
2501 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2505 drm_gem_object_unreference(&obj
->base
);
2506 mutex_unlock(&dev
->struct_mutex
);
2510 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2512 update_state_fb(struct drm_plane
*plane
)
2514 if (plane
->fb
== plane
->state
->fb
)
2517 if (plane
->state
->fb
)
2518 drm_framebuffer_unreference(plane
->state
->fb
);
2519 plane
->state
->fb
= plane
->fb
;
2520 if (plane
->state
->fb
)
2521 drm_framebuffer_reference(plane
->state
->fb
);
2525 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2526 struct intel_initial_plane_config
*plane_config
)
2528 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2531 struct intel_crtc
*i
;
2532 struct drm_i915_gem_object
*obj
;
2533 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2534 struct drm_plane_state
*plane_state
= primary
->state
;
2535 struct drm_crtc_state
*crtc_state
= intel_crtc
->base
.state
;
2536 struct intel_plane
*intel_plane
= to_intel_plane(primary
);
2537 struct intel_plane_state
*intel_state
=
2538 to_intel_plane_state(plane_state
);
2539 struct drm_framebuffer
*fb
;
2541 if (!plane_config
->fb
)
2544 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2545 fb
= &plane_config
->fb
->base
;
2549 kfree(plane_config
->fb
);
2552 * Failed to alloc the obj, check to see if we should share
2553 * an fb with another CRTC instead
2555 for_each_crtc(dev
, c
) {
2556 i
= to_intel_crtc(c
);
2558 if (c
== &intel_crtc
->base
)
2564 fb
= c
->primary
->fb
;
2568 obj
= intel_fb_obj(fb
);
2569 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2570 drm_framebuffer_reference(fb
);
2576 * We've failed to reconstruct the BIOS FB. Current display state
2577 * indicates that the primary plane is visible, but has a NULL FB,
2578 * which will lead to problems later if we don't fix it up. The
2579 * simplest solution is to just disable the primary plane now and
2580 * pretend the BIOS never had it enabled.
2582 to_intel_plane_state(plane_state
)->visible
= false;
2583 crtc_state
->plane_mask
&= ~(1 << drm_plane_index(primary
));
2584 intel_pre_disable_primary_noatomic(&intel_crtc
->base
);
2585 intel_plane
->disable_plane(primary
, &intel_crtc
->base
);
2590 plane_state
->src_x
= 0;
2591 plane_state
->src_y
= 0;
2592 plane_state
->src_w
= fb
->width
<< 16;
2593 plane_state
->src_h
= fb
->height
<< 16;
2595 plane_state
->crtc_x
= 0;
2596 plane_state
->crtc_y
= 0;
2597 plane_state
->crtc_w
= fb
->width
;
2598 plane_state
->crtc_h
= fb
->height
;
2600 intel_state
->src
.x1
= plane_state
->src_x
;
2601 intel_state
->src
.y1
= plane_state
->src_y
;
2602 intel_state
->src
.x2
= plane_state
->src_x
+ plane_state
->src_w
;
2603 intel_state
->src
.y2
= plane_state
->src_y
+ plane_state
->src_h
;
2604 intel_state
->dst
.x1
= plane_state
->crtc_x
;
2605 intel_state
->dst
.y1
= plane_state
->crtc_y
;
2606 intel_state
->dst
.x2
= plane_state
->crtc_x
+ plane_state
->crtc_w
;
2607 intel_state
->dst
.y2
= plane_state
->crtc_y
+ plane_state
->crtc_h
;
2609 obj
= intel_fb_obj(fb
);
2610 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2611 dev_priv
->preserve_bios_swizzle
= true;
2613 drm_framebuffer_reference(fb
);
2614 primary
->fb
= primary
->state
->fb
= fb
;
2615 primary
->crtc
= primary
->state
->crtc
= &intel_crtc
->base
;
2616 intel_crtc
->base
.state
->plane_mask
|= (1 << drm_plane_index(primary
));
2617 obj
->frontbuffer_bits
|= to_intel_plane(primary
)->frontbuffer_bit
;
2620 static void i9xx_update_primary_plane(struct drm_plane
*primary
,
2621 const struct intel_crtc_state
*crtc_state
,
2622 const struct intel_plane_state
*plane_state
)
2624 struct drm_device
*dev
= primary
->dev
;
2625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2626 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2627 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2628 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2629 int plane
= intel_crtc
->plane
;
2632 i915_reg_t reg
= DSPCNTR(plane
);
2633 unsigned int rotation
= plane_state
->base
.rotation
;
2634 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2635 int x
= plane_state
->src
.x1
>> 16;
2636 int y
= plane_state
->src
.y1
>> 16;
2638 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2640 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2642 if (INTEL_INFO(dev
)->gen
< 4) {
2643 if (intel_crtc
->pipe
== PIPE_B
)
2644 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2646 /* pipesrc and dspsize control the size that is scaled from,
2647 * which should always be the user's requested size.
2649 I915_WRITE(DSPSIZE(plane
),
2650 ((crtc_state
->pipe_src_h
- 1) << 16) |
2651 (crtc_state
->pipe_src_w
- 1));
2652 I915_WRITE(DSPPOS(plane
), 0);
2653 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2654 I915_WRITE(PRIMSIZE(plane
),
2655 ((crtc_state
->pipe_src_h
- 1) << 16) |
2656 (crtc_state
->pipe_src_w
- 1));
2657 I915_WRITE(PRIMPOS(plane
), 0);
2658 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2661 switch (fb
->pixel_format
) {
2663 dspcntr
|= DISPPLANE_8BPP
;
2665 case DRM_FORMAT_XRGB1555
:
2666 dspcntr
|= DISPPLANE_BGRX555
;
2668 case DRM_FORMAT_RGB565
:
2669 dspcntr
|= DISPPLANE_BGRX565
;
2671 case DRM_FORMAT_XRGB8888
:
2672 dspcntr
|= DISPPLANE_BGRX888
;
2674 case DRM_FORMAT_XBGR8888
:
2675 dspcntr
|= DISPPLANE_RGBX888
;
2677 case DRM_FORMAT_XRGB2101010
:
2678 dspcntr
|= DISPPLANE_BGRX101010
;
2680 case DRM_FORMAT_XBGR2101010
:
2681 dspcntr
|= DISPPLANE_RGBX101010
;
2687 if (INTEL_INFO(dev
)->gen
>= 4 &&
2688 obj
->tiling_mode
!= I915_TILING_NONE
)
2689 dspcntr
|= DISPPLANE_TILED
;
2692 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2694 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
2696 if (INTEL_INFO(dev
)->gen
>= 4) {
2697 intel_crtc
->dspaddr_offset
=
2698 intel_compute_tile_offset(&x
, &y
, fb
, 0,
2699 fb
->pitches
[0], rotation
);
2700 linear_offset
-= intel_crtc
->dspaddr_offset
;
2702 intel_crtc
->dspaddr_offset
= linear_offset
;
2705 if (rotation
== BIT(DRM_ROTATE_180
)) {
2706 dspcntr
|= DISPPLANE_ROTATE_180
;
2708 x
+= (crtc_state
->pipe_src_w
- 1);
2709 y
+= (crtc_state
->pipe_src_h
- 1);
2711 /* Finding the last pixel of the last line of the display
2712 data and adding to linear_offset*/
2714 (crtc_state
->pipe_src_h
- 1) * fb
->pitches
[0] +
2715 (crtc_state
->pipe_src_w
- 1) * cpp
;
2718 intel_crtc
->adjusted_x
= x
;
2719 intel_crtc
->adjusted_y
= y
;
2721 I915_WRITE(reg
, dspcntr
);
2723 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2724 if (INTEL_INFO(dev
)->gen
>= 4) {
2725 I915_WRITE(DSPSURF(plane
),
2726 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2727 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2728 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2730 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2734 static void i9xx_disable_primary_plane(struct drm_plane
*primary
,
2735 struct drm_crtc
*crtc
)
2737 struct drm_device
*dev
= crtc
->dev
;
2738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2739 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2740 int plane
= intel_crtc
->plane
;
2742 I915_WRITE(DSPCNTR(plane
), 0);
2743 if (INTEL_INFO(dev_priv
)->gen
>= 4)
2744 I915_WRITE(DSPSURF(plane
), 0);
2746 I915_WRITE(DSPADDR(plane
), 0);
2747 POSTING_READ(DSPCNTR(plane
));
2750 static void ironlake_update_primary_plane(struct drm_plane
*primary
,
2751 const struct intel_crtc_state
*crtc_state
,
2752 const struct intel_plane_state
*plane_state
)
2754 struct drm_device
*dev
= primary
->dev
;
2755 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2756 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2757 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2758 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2759 int plane
= intel_crtc
->plane
;
2762 i915_reg_t reg
= DSPCNTR(plane
);
2763 unsigned int rotation
= plane_state
->base
.rotation
;
2764 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2765 int x
= plane_state
->src
.x1
>> 16;
2766 int y
= plane_state
->src
.y1
>> 16;
2768 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2769 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2771 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2772 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2774 switch (fb
->pixel_format
) {
2776 dspcntr
|= DISPPLANE_8BPP
;
2778 case DRM_FORMAT_RGB565
:
2779 dspcntr
|= DISPPLANE_BGRX565
;
2781 case DRM_FORMAT_XRGB8888
:
2782 dspcntr
|= DISPPLANE_BGRX888
;
2784 case DRM_FORMAT_XBGR8888
:
2785 dspcntr
|= DISPPLANE_RGBX888
;
2787 case DRM_FORMAT_XRGB2101010
:
2788 dspcntr
|= DISPPLANE_BGRX101010
;
2790 case DRM_FORMAT_XBGR2101010
:
2791 dspcntr
|= DISPPLANE_RGBX101010
;
2797 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2798 dspcntr
|= DISPPLANE_TILED
;
2800 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2801 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2803 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
2804 intel_crtc
->dspaddr_offset
=
2805 intel_compute_tile_offset(&x
, &y
, fb
, 0,
2806 fb
->pitches
[0], rotation
);
2807 linear_offset
-= intel_crtc
->dspaddr_offset
;
2808 if (rotation
== BIT(DRM_ROTATE_180
)) {
2809 dspcntr
|= DISPPLANE_ROTATE_180
;
2811 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2812 x
+= (crtc_state
->pipe_src_w
- 1);
2813 y
+= (crtc_state
->pipe_src_h
- 1);
2815 /* Finding the last pixel of the last line of the display
2816 data and adding to linear_offset*/
2818 (crtc_state
->pipe_src_h
- 1) * fb
->pitches
[0] +
2819 (crtc_state
->pipe_src_w
- 1) * cpp
;
2823 intel_crtc
->adjusted_x
= x
;
2824 intel_crtc
->adjusted_y
= y
;
2826 I915_WRITE(reg
, dspcntr
);
2828 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2829 I915_WRITE(DSPSURF(plane
),
2830 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2831 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2832 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2834 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2835 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2840 u32
intel_fb_stride_alignment(const struct drm_i915_private
*dev_priv
,
2841 uint64_t fb_modifier
, uint32_t pixel_format
)
2843 if (fb_modifier
== DRM_FORMAT_MOD_NONE
) {
2846 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
2848 return intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2852 u32
intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2853 struct drm_i915_gem_object
*obj
,
2856 struct i915_ggtt_view view
;
2857 struct i915_vma
*vma
;
2860 intel_fill_fb_ggtt_view(&view
, intel_plane
->base
.state
->fb
,
2861 intel_plane
->base
.state
->rotation
);
2863 vma
= i915_gem_obj_to_ggtt_view(obj
, &view
);
2864 if (WARN(!vma
, "ggtt vma for display object not found! (view=%u)\n",
2868 offset
= vma
->node
.start
;
2871 offset
+= vma
->ggtt_view
.params
.rotated
.uv_start_page
*
2875 WARN_ON(upper_32_bits(offset
));
2877 return lower_32_bits(offset
);
2880 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
2882 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2885 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
2886 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
2887 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
2891 * This function detaches (aka. unbinds) unused scalers in hardware
2893 static void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2895 struct intel_crtc_scaler_state
*scaler_state
;
2898 scaler_state
= &intel_crtc
->config
->scaler_state
;
2900 /* loop through and disable scalers that aren't in use */
2901 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2902 if (!scaler_state
->scalers
[i
].in_use
)
2903 skl_detach_scaler(intel_crtc
, i
);
2907 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2909 switch (pixel_format
) {
2911 return PLANE_CTL_FORMAT_INDEXED
;
2912 case DRM_FORMAT_RGB565
:
2913 return PLANE_CTL_FORMAT_RGB_565
;
2914 case DRM_FORMAT_XBGR8888
:
2915 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2916 case DRM_FORMAT_XRGB8888
:
2917 return PLANE_CTL_FORMAT_XRGB_8888
;
2919 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2920 * to be already pre-multiplied. We need to add a knob (or a different
2921 * DRM_FORMAT) for user-space to configure that.
2923 case DRM_FORMAT_ABGR8888
:
2924 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
2925 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2926 case DRM_FORMAT_ARGB8888
:
2927 return PLANE_CTL_FORMAT_XRGB_8888
|
2928 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2929 case DRM_FORMAT_XRGB2101010
:
2930 return PLANE_CTL_FORMAT_XRGB_2101010
;
2931 case DRM_FORMAT_XBGR2101010
:
2932 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
2933 case DRM_FORMAT_YUYV
:
2934 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
2935 case DRM_FORMAT_YVYU
:
2936 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
2937 case DRM_FORMAT_UYVY
:
2938 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
2939 case DRM_FORMAT_VYUY
:
2940 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
2942 MISSING_CASE(pixel_format
);
2948 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
2950 switch (fb_modifier
) {
2951 case DRM_FORMAT_MOD_NONE
:
2953 case I915_FORMAT_MOD_X_TILED
:
2954 return PLANE_CTL_TILED_X
;
2955 case I915_FORMAT_MOD_Y_TILED
:
2956 return PLANE_CTL_TILED_Y
;
2957 case I915_FORMAT_MOD_Yf_TILED
:
2958 return PLANE_CTL_TILED_YF
;
2960 MISSING_CASE(fb_modifier
);
2966 u32
skl_plane_ctl_rotation(unsigned int rotation
)
2969 case BIT(DRM_ROTATE_0
):
2972 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2973 * while i915 HW rotation is clockwise, thats why this swapping.
2975 case BIT(DRM_ROTATE_90
):
2976 return PLANE_CTL_ROTATE_270
;
2977 case BIT(DRM_ROTATE_180
):
2978 return PLANE_CTL_ROTATE_180
;
2979 case BIT(DRM_ROTATE_270
):
2980 return PLANE_CTL_ROTATE_90
;
2982 MISSING_CASE(rotation
);
2988 static void skylake_update_primary_plane(struct drm_plane
*plane
,
2989 const struct intel_crtc_state
*crtc_state
,
2990 const struct intel_plane_state
*plane_state
)
2992 struct drm_device
*dev
= plane
->dev
;
2993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2994 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2995 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2996 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2997 int pipe
= intel_crtc
->pipe
;
2998 u32 plane_ctl
, stride_div
, stride
;
2999 u32 tile_height
, plane_offset
, plane_size
;
3000 unsigned int rotation
= plane_state
->base
.rotation
;
3001 int x_offset
, y_offset
;
3003 int scaler_id
= plane_state
->scaler_id
;
3004 int src_x
= plane_state
->src
.x1
>> 16;
3005 int src_y
= plane_state
->src
.y1
>> 16;
3006 int src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3007 int src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3008 int dst_x
= plane_state
->dst
.x1
;
3009 int dst_y
= plane_state
->dst
.y1
;
3010 int dst_w
= drm_rect_width(&plane_state
->dst
);
3011 int dst_h
= drm_rect_height(&plane_state
->dst
);
3013 plane_ctl
= PLANE_CTL_ENABLE
|
3014 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3015 PLANE_CTL_PIPE_CSC_ENABLE
;
3017 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3018 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3019 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3020 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3022 stride_div
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
3024 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
, 0);
3026 WARN_ON(drm_rect_width(&plane_state
->src
) == 0);
3028 if (intel_rotation_90_or_270(rotation
)) {
3029 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
3031 /* stride = Surface height in tiles */
3032 tile_height
= intel_tile_height(dev_priv
, fb
->modifier
[0], cpp
);
3033 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3034 x_offset
= stride
* tile_height
- src_y
- src_h
;
3036 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3038 stride
= fb
->pitches
[0] / stride_div
;
3041 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3043 plane_offset
= y_offset
<< 16 | x_offset
;
3045 intel_crtc
->adjusted_x
= x_offset
;
3046 intel_crtc
->adjusted_y
= y_offset
;
3048 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3049 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3050 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3051 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3053 if (scaler_id
>= 0) {
3054 uint32_t ps_ctrl
= 0;
3056 WARN_ON(!dst_w
|| !dst_h
);
3057 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3058 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3059 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3060 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3061 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3062 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3063 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3065 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3068 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3070 POSTING_READ(PLANE_SURF(pipe
, 0));
3073 static void skylake_disable_primary_plane(struct drm_plane
*primary
,
3074 struct drm_crtc
*crtc
)
3076 struct drm_device
*dev
= crtc
->dev
;
3077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3078 int pipe
= to_intel_crtc(crtc
)->pipe
;
3080 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3081 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3082 POSTING_READ(PLANE_SURF(pipe
, 0));
3085 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3087 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3088 int x
, int y
, enum mode_set_atomic state
)
3090 /* Support for kgdboc is disabled, this needs a major rework. */
3091 DRM_ERROR("legacy panic handler not supported any more.\n");
3096 static void intel_complete_page_flips(struct drm_device
*dev
)
3098 struct drm_crtc
*crtc
;
3100 for_each_crtc(dev
, crtc
) {
3101 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3102 enum plane plane
= intel_crtc
->plane
;
3104 intel_prepare_page_flip(dev
, plane
);
3105 intel_finish_page_flip_plane(dev
, plane
);
3109 static void intel_update_primary_planes(struct drm_device
*dev
)
3111 struct drm_crtc
*crtc
;
3113 for_each_crtc(dev
, crtc
) {
3114 struct intel_plane
*plane
= to_intel_plane(crtc
->primary
);
3115 struct intel_plane_state
*plane_state
;
3117 drm_modeset_lock_crtc(crtc
, &plane
->base
);
3118 plane_state
= to_intel_plane_state(plane
->base
.state
);
3120 if (plane_state
->visible
)
3121 plane
->update_plane(&plane
->base
,
3122 to_intel_crtc_state(crtc
->state
),
3125 drm_modeset_unlock_crtc(crtc
);
3129 void intel_prepare_reset(struct drm_device
*dev
)
3131 /* no reset support for gen2 */
3135 /* reset doesn't touch the display */
3136 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
3139 drm_modeset_lock_all(dev
);
3141 * Disabling the crtcs gracefully seems nicer. Also the
3142 * g33 docs say we should at least disable all the planes.
3144 intel_display_suspend(dev
);
3147 void intel_finish_reset(struct drm_device
*dev
)
3149 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3152 * Flips in the rings will be nuked by the reset,
3153 * so complete all pending flips so that user space
3154 * will get its events and not get stuck.
3156 intel_complete_page_flips(dev
);
3158 /* no reset support for gen2 */
3162 /* reset doesn't touch the display */
3163 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3165 * Flips in the rings have been nuked by the reset,
3166 * so update the base address of all primary
3167 * planes to the the last fb to make sure we're
3168 * showing the correct fb after a reset.
3170 * FIXME: Atomic will make this obsolete since we won't schedule
3171 * CS-based flips (which might get lost in gpu resets) any more.
3173 intel_update_primary_planes(dev
);
3178 * The display has been reset as well,
3179 * so need a full re-initialization.
3181 intel_runtime_pm_disable_interrupts(dev_priv
);
3182 intel_runtime_pm_enable_interrupts(dev_priv
);
3184 intel_modeset_init_hw(dev
);
3186 spin_lock_irq(&dev_priv
->irq_lock
);
3187 if (dev_priv
->display
.hpd_irq_setup
)
3188 dev_priv
->display
.hpd_irq_setup(dev
);
3189 spin_unlock_irq(&dev_priv
->irq_lock
);
3191 intel_display_resume(dev
);
3193 intel_hpd_init(dev_priv
);
3195 drm_modeset_unlock_all(dev
);
3198 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3200 struct drm_device
*dev
= crtc
->dev
;
3201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3202 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3205 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3206 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3209 spin_lock_irq(&dev
->event_lock
);
3210 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3211 spin_unlock_irq(&dev
->event_lock
);
3216 static void intel_update_pipe_config(struct intel_crtc
*crtc
,
3217 struct intel_crtc_state
*old_crtc_state
)
3219 struct drm_device
*dev
= crtc
->base
.dev
;
3220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3221 struct intel_crtc_state
*pipe_config
=
3222 to_intel_crtc_state(crtc
->base
.state
);
3224 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3225 crtc
->base
.mode
= crtc
->base
.state
->mode
;
3227 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3228 old_crtc_state
->pipe_src_w
, old_crtc_state
->pipe_src_h
,
3229 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
3232 * Update pipe size and adjust fitter if needed: the reason for this is
3233 * that in compute_mode_changes we check the native mode (not the pfit
3234 * mode) to see if we can flip rather than do a full mode set. In the
3235 * fastboot case, we'll flip, but if we don't update the pipesrc and
3236 * pfit state, we'll end up with a big fb scanned out into the wrong
3240 I915_WRITE(PIPESRC(crtc
->pipe
),
3241 ((pipe_config
->pipe_src_w
- 1) << 16) |
3242 (pipe_config
->pipe_src_h
- 1));
3244 /* on skylake this is done by detaching scalers */
3245 if (INTEL_INFO(dev
)->gen
>= 9) {
3246 skl_detach_scalers(crtc
);
3248 if (pipe_config
->pch_pfit
.enabled
)
3249 skylake_pfit_enable(crtc
);
3250 } else if (HAS_PCH_SPLIT(dev
)) {
3251 if (pipe_config
->pch_pfit
.enabled
)
3252 ironlake_pfit_enable(crtc
);
3253 else if (old_crtc_state
->pch_pfit
.enabled
)
3254 ironlake_pfit_disable(crtc
, true);
3258 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3260 struct drm_device
*dev
= crtc
->dev
;
3261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3262 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3263 int pipe
= intel_crtc
->pipe
;
3267 /* enable normal train */
3268 reg
= FDI_TX_CTL(pipe
);
3269 temp
= I915_READ(reg
);
3270 if (IS_IVYBRIDGE(dev
)) {
3271 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3272 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3274 temp
&= ~FDI_LINK_TRAIN_NONE
;
3275 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3277 I915_WRITE(reg
, temp
);
3279 reg
= FDI_RX_CTL(pipe
);
3280 temp
= I915_READ(reg
);
3281 if (HAS_PCH_CPT(dev
)) {
3282 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3283 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3285 temp
&= ~FDI_LINK_TRAIN_NONE
;
3286 temp
|= FDI_LINK_TRAIN_NONE
;
3288 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3290 /* wait one idle pattern time */
3294 /* IVB wants error correction enabled */
3295 if (IS_IVYBRIDGE(dev
))
3296 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3297 FDI_FE_ERRC_ENABLE
);
3300 /* The FDI link training functions for ILK/Ibexpeak. */
3301 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3303 struct drm_device
*dev
= crtc
->dev
;
3304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3305 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3306 int pipe
= intel_crtc
->pipe
;
3310 /* FDI needs bits from pipe first */
3311 assert_pipe_enabled(dev_priv
, pipe
);
3313 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3315 reg
= FDI_RX_IMR(pipe
);
3316 temp
= I915_READ(reg
);
3317 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3318 temp
&= ~FDI_RX_BIT_LOCK
;
3319 I915_WRITE(reg
, temp
);
3323 /* enable CPU FDI TX and PCH FDI RX */
3324 reg
= FDI_TX_CTL(pipe
);
3325 temp
= I915_READ(reg
);
3326 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3327 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3328 temp
&= ~FDI_LINK_TRAIN_NONE
;
3329 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3330 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3332 reg
= FDI_RX_CTL(pipe
);
3333 temp
= I915_READ(reg
);
3334 temp
&= ~FDI_LINK_TRAIN_NONE
;
3335 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3336 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3341 /* Ironlake workaround, enable clock pointer after FDI enable*/
3342 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3343 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3344 FDI_RX_PHASE_SYNC_POINTER_EN
);
3346 reg
= FDI_RX_IIR(pipe
);
3347 for (tries
= 0; tries
< 5; tries
++) {
3348 temp
= I915_READ(reg
);
3349 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3351 if ((temp
& FDI_RX_BIT_LOCK
)) {
3352 DRM_DEBUG_KMS("FDI train 1 done.\n");
3353 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3358 DRM_ERROR("FDI train 1 fail!\n");
3361 reg
= FDI_TX_CTL(pipe
);
3362 temp
= I915_READ(reg
);
3363 temp
&= ~FDI_LINK_TRAIN_NONE
;
3364 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3365 I915_WRITE(reg
, temp
);
3367 reg
= FDI_RX_CTL(pipe
);
3368 temp
= I915_READ(reg
);
3369 temp
&= ~FDI_LINK_TRAIN_NONE
;
3370 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3371 I915_WRITE(reg
, temp
);
3376 reg
= FDI_RX_IIR(pipe
);
3377 for (tries
= 0; tries
< 5; tries
++) {
3378 temp
= I915_READ(reg
);
3379 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3381 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3382 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3383 DRM_DEBUG_KMS("FDI train 2 done.\n");
3388 DRM_ERROR("FDI train 2 fail!\n");
3390 DRM_DEBUG_KMS("FDI train done\n");
3394 static const int snb_b_fdi_train_param
[] = {
3395 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3396 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3397 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3398 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3401 /* The FDI link training functions for SNB/Cougarpoint. */
3402 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3404 struct drm_device
*dev
= crtc
->dev
;
3405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3406 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3407 int pipe
= intel_crtc
->pipe
;
3411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3413 reg
= FDI_RX_IMR(pipe
);
3414 temp
= I915_READ(reg
);
3415 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3416 temp
&= ~FDI_RX_BIT_LOCK
;
3417 I915_WRITE(reg
, temp
);
3422 /* enable CPU FDI TX and PCH FDI RX */
3423 reg
= FDI_TX_CTL(pipe
);
3424 temp
= I915_READ(reg
);
3425 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3426 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3427 temp
&= ~FDI_LINK_TRAIN_NONE
;
3428 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3429 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3431 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3432 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3434 I915_WRITE(FDI_RX_MISC(pipe
),
3435 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3437 reg
= FDI_RX_CTL(pipe
);
3438 temp
= I915_READ(reg
);
3439 if (HAS_PCH_CPT(dev
)) {
3440 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3441 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3443 temp
&= ~FDI_LINK_TRAIN_NONE
;
3444 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3446 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3451 for (i
= 0; i
< 4; i
++) {
3452 reg
= FDI_TX_CTL(pipe
);
3453 temp
= I915_READ(reg
);
3454 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3455 temp
|= snb_b_fdi_train_param
[i
];
3456 I915_WRITE(reg
, temp
);
3461 for (retry
= 0; retry
< 5; retry
++) {
3462 reg
= FDI_RX_IIR(pipe
);
3463 temp
= I915_READ(reg
);
3464 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3465 if (temp
& FDI_RX_BIT_LOCK
) {
3466 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3467 DRM_DEBUG_KMS("FDI train 1 done.\n");
3476 DRM_ERROR("FDI train 1 fail!\n");
3479 reg
= FDI_TX_CTL(pipe
);
3480 temp
= I915_READ(reg
);
3481 temp
&= ~FDI_LINK_TRAIN_NONE
;
3482 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3484 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3486 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3488 I915_WRITE(reg
, temp
);
3490 reg
= FDI_RX_CTL(pipe
);
3491 temp
= I915_READ(reg
);
3492 if (HAS_PCH_CPT(dev
)) {
3493 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3494 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3496 temp
&= ~FDI_LINK_TRAIN_NONE
;
3497 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3499 I915_WRITE(reg
, temp
);
3504 for (i
= 0; i
< 4; i
++) {
3505 reg
= FDI_TX_CTL(pipe
);
3506 temp
= I915_READ(reg
);
3507 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3508 temp
|= snb_b_fdi_train_param
[i
];
3509 I915_WRITE(reg
, temp
);
3514 for (retry
= 0; retry
< 5; retry
++) {
3515 reg
= FDI_RX_IIR(pipe
);
3516 temp
= I915_READ(reg
);
3517 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3518 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3519 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3520 DRM_DEBUG_KMS("FDI train 2 done.\n");
3529 DRM_ERROR("FDI train 2 fail!\n");
3531 DRM_DEBUG_KMS("FDI train done.\n");
3534 /* Manual link training for Ivy Bridge A0 parts */
3535 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3537 struct drm_device
*dev
= crtc
->dev
;
3538 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3539 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3540 int pipe
= intel_crtc
->pipe
;
3544 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3546 reg
= FDI_RX_IMR(pipe
);
3547 temp
= I915_READ(reg
);
3548 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3549 temp
&= ~FDI_RX_BIT_LOCK
;
3550 I915_WRITE(reg
, temp
);
3555 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3556 I915_READ(FDI_RX_IIR(pipe
)));
3558 /* Try each vswing and preemphasis setting twice before moving on */
3559 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3560 /* disable first in case we need to retry */
3561 reg
= FDI_TX_CTL(pipe
);
3562 temp
= I915_READ(reg
);
3563 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3564 temp
&= ~FDI_TX_ENABLE
;
3565 I915_WRITE(reg
, temp
);
3567 reg
= FDI_RX_CTL(pipe
);
3568 temp
= I915_READ(reg
);
3569 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3570 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3571 temp
&= ~FDI_RX_ENABLE
;
3572 I915_WRITE(reg
, temp
);
3574 /* enable CPU FDI TX and PCH FDI RX */
3575 reg
= FDI_TX_CTL(pipe
);
3576 temp
= I915_READ(reg
);
3577 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3578 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3579 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3580 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3581 temp
|= snb_b_fdi_train_param
[j
/2];
3582 temp
|= FDI_COMPOSITE_SYNC
;
3583 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3585 I915_WRITE(FDI_RX_MISC(pipe
),
3586 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3588 reg
= FDI_RX_CTL(pipe
);
3589 temp
= I915_READ(reg
);
3590 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3591 temp
|= FDI_COMPOSITE_SYNC
;
3592 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3595 udelay(1); /* should be 0.5us */
3597 for (i
= 0; i
< 4; i
++) {
3598 reg
= FDI_RX_IIR(pipe
);
3599 temp
= I915_READ(reg
);
3600 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3602 if (temp
& FDI_RX_BIT_LOCK
||
3603 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3604 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3605 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3609 udelay(1); /* should be 0.5us */
3612 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3617 reg
= FDI_TX_CTL(pipe
);
3618 temp
= I915_READ(reg
);
3619 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3620 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3621 I915_WRITE(reg
, temp
);
3623 reg
= FDI_RX_CTL(pipe
);
3624 temp
= I915_READ(reg
);
3625 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3626 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3627 I915_WRITE(reg
, temp
);
3630 udelay(2); /* should be 1.5us */
3632 for (i
= 0; i
< 4; i
++) {
3633 reg
= FDI_RX_IIR(pipe
);
3634 temp
= I915_READ(reg
);
3635 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3637 if (temp
& FDI_RX_SYMBOL_LOCK
||
3638 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3639 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3640 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3644 udelay(2); /* should be 1.5us */
3647 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3651 DRM_DEBUG_KMS("FDI train done.\n");
3654 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3656 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3658 int pipe
= intel_crtc
->pipe
;
3662 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3663 reg
= FDI_RX_CTL(pipe
);
3664 temp
= I915_READ(reg
);
3665 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3666 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3667 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3668 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3673 /* Switch from Rawclk to PCDclk */
3674 temp
= I915_READ(reg
);
3675 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3680 /* Enable CPU FDI TX PLL, always on for Ironlake */
3681 reg
= FDI_TX_CTL(pipe
);
3682 temp
= I915_READ(reg
);
3683 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3684 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3691 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3693 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3695 int pipe
= intel_crtc
->pipe
;
3699 /* Switch from PCDclk to Rawclk */
3700 reg
= FDI_RX_CTL(pipe
);
3701 temp
= I915_READ(reg
);
3702 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3704 /* Disable CPU FDI TX PLL */
3705 reg
= FDI_TX_CTL(pipe
);
3706 temp
= I915_READ(reg
);
3707 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3712 reg
= FDI_RX_CTL(pipe
);
3713 temp
= I915_READ(reg
);
3714 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3716 /* Wait for the clocks to turn off. */
3721 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3723 struct drm_device
*dev
= crtc
->dev
;
3724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3725 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3726 int pipe
= intel_crtc
->pipe
;
3730 /* disable CPU FDI tx and PCH FDI rx */
3731 reg
= FDI_TX_CTL(pipe
);
3732 temp
= I915_READ(reg
);
3733 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3736 reg
= FDI_RX_CTL(pipe
);
3737 temp
= I915_READ(reg
);
3738 temp
&= ~(0x7 << 16);
3739 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3740 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3745 /* Ironlake workaround, disable clock pointer after downing FDI */
3746 if (HAS_PCH_IBX(dev
))
3747 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3749 /* still set train pattern 1 */
3750 reg
= FDI_TX_CTL(pipe
);
3751 temp
= I915_READ(reg
);
3752 temp
&= ~FDI_LINK_TRAIN_NONE
;
3753 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3754 I915_WRITE(reg
, temp
);
3756 reg
= FDI_RX_CTL(pipe
);
3757 temp
= I915_READ(reg
);
3758 if (HAS_PCH_CPT(dev
)) {
3759 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3760 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3762 temp
&= ~FDI_LINK_TRAIN_NONE
;
3763 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3765 /* BPC in FDI rx is consistent with that in PIPECONF */
3766 temp
&= ~(0x07 << 16);
3767 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3768 I915_WRITE(reg
, temp
);
3774 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3776 struct intel_crtc
*crtc
;
3778 /* Note that we don't need to be called with mode_config.lock here
3779 * as our list of CRTC objects is static for the lifetime of the
3780 * device and so cannot disappear as we iterate. Similarly, we can
3781 * happily treat the predicates as racy, atomic checks as userspace
3782 * cannot claim and pin a new fb without at least acquring the
3783 * struct_mutex and so serialising with us.
3785 for_each_intel_crtc(dev
, crtc
) {
3786 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3789 if (crtc
->unpin_work
)
3790 intel_wait_for_vblank(dev
, crtc
->pipe
);
3798 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3800 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3801 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3803 /* ensure that the unpin work is consistent wrt ->pending. */
3805 intel_crtc
->unpin_work
= NULL
;
3808 drm_send_vblank_event(intel_crtc
->base
.dev
,
3812 drm_crtc_vblank_put(&intel_crtc
->base
);
3814 wake_up_all(&dev_priv
->pending_flip_queue
);
3815 queue_work(dev_priv
->wq
, &work
->work
);
3817 trace_i915_flip_complete(intel_crtc
->plane
,
3818 work
->pending_flip_obj
);
3821 static int intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3823 struct drm_device
*dev
= crtc
->dev
;
3824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3827 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3829 ret
= wait_event_interruptible_timeout(
3830 dev_priv
->pending_flip_queue
,
3831 !intel_crtc_has_pending_flip(crtc
),
3838 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3840 spin_lock_irq(&dev
->event_lock
);
3841 if (intel_crtc
->unpin_work
) {
3842 WARN_ONCE(1, "Removing stuck page flip\n");
3843 page_flip_completed(intel_crtc
);
3845 spin_unlock_irq(&dev
->event_lock
);
3851 static void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
)
3855 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3857 mutex_lock(&dev_priv
->sb_lock
);
3859 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3860 temp
|= SBI_SSCCTL_DISABLE
;
3861 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3863 mutex_unlock(&dev_priv
->sb_lock
);
3866 /* Program iCLKIP clock to the desired frequency */
3867 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3869 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
3870 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3871 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3874 lpt_disable_iclkip(dev_priv
);
3876 /* The iCLK virtual clock root frequency is in MHz,
3877 * but the adjusted_mode->crtc_clock in in KHz. To get the
3878 * divisors, it is necessary to divide one by another, so we
3879 * convert the virtual clock precision to KHz here for higher
3882 for (auxdiv
= 0; auxdiv
< 2; auxdiv
++) {
3883 u32 iclk_virtual_root_freq
= 172800 * 1000;
3884 u32 iclk_pi_range
= 64;
3885 u32 desired_divisor
;
3887 desired_divisor
= DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
3889 divsel
= (desired_divisor
/ iclk_pi_range
) - 2;
3890 phaseinc
= desired_divisor
% iclk_pi_range
;
3893 * Near 20MHz is a corner case which is
3894 * out of range for the 7-bit divisor
3900 /* This should not happen with any sane values */
3901 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3902 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3903 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3904 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3906 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3913 mutex_lock(&dev_priv
->sb_lock
);
3915 /* Program SSCDIVINTPHASE6 */
3916 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3917 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3918 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3919 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3920 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3921 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3922 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3923 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3925 /* Program SSCAUXDIV */
3926 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3927 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3928 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3929 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3931 /* Enable modulator and associated divider */
3932 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3933 temp
&= ~SBI_SSCCTL_DISABLE
;
3934 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3936 mutex_unlock(&dev_priv
->sb_lock
);
3938 /* Wait for initialization time */
3941 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3944 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
)
3946 u32 divsel
, phaseinc
, auxdiv
;
3947 u32 iclk_virtual_root_freq
= 172800 * 1000;
3948 u32 iclk_pi_range
= 64;
3949 u32 desired_divisor
;
3952 if ((I915_READ(PIXCLK_GATE
) & PIXCLK_GATE_UNGATE
) == 0)
3955 mutex_lock(&dev_priv
->sb_lock
);
3957 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3958 if (temp
& SBI_SSCCTL_DISABLE
) {
3959 mutex_unlock(&dev_priv
->sb_lock
);
3963 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3964 divsel
= (temp
& SBI_SSCDIVINTPHASE_DIVSEL_MASK
) >>
3965 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT
;
3966 phaseinc
= (temp
& SBI_SSCDIVINTPHASE_INCVAL_MASK
) >>
3967 SBI_SSCDIVINTPHASE_INCVAL_SHIFT
;
3969 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3970 auxdiv
= (temp
& SBI_SSCAUXDIV_FINALDIV2SEL_MASK
) >>
3971 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT
;
3973 mutex_unlock(&dev_priv
->sb_lock
);
3975 desired_divisor
= (divsel
+ 2) * iclk_pi_range
+ phaseinc
;
3977 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
3978 desired_divisor
<< auxdiv
);
3981 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3982 enum pipe pch_transcoder
)
3984 struct drm_device
*dev
= crtc
->base
.dev
;
3985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3986 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
3988 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3989 I915_READ(HTOTAL(cpu_transcoder
)));
3990 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3991 I915_READ(HBLANK(cpu_transcoder
)));
3992 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3993 I915_READ(HSYNC(cpu_transcoder
)));
3995 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3996 I915_READ(VTOTAL(cpu_transcoder
)));
3997 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3998 I915_READ(VBLANK(cpu_transcoder
)));
3999 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4000 I915_READ(VSYNC(cpu_transcoder
)));
4001 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4002 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4005 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4010 temp
= I915_READ(SOUTH_CHICKEN1
);
4011 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4014 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4015 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4017 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4019 temp
|= FDI_BC_BIFURCATION_SELECT
;
4021 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4022 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4023 POSTING_READ(SOUTH_CHICKEN1
);
4026 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4028 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4030 switch (intel_crtc
->pipe
) {
4034 if (intel_crtc
->config
->fdi_lanes
> 2)
4035 cpt_set_fdi_bc_bifurcation(dev
, false);
4037 cpt_set_fdi_bc_bifurcation(dev
, true);
4041 cpt_set_fdi_bc_bifurcation(dev
, true);
4049 /* Return which DP Port should be selected for Transcoder DP control */
4051 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4053 struct drm_device
*dev
= crtc
->dev
;
4054 struct intel_encoder
*encoder
;
4056 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4057 if (encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4058 encoder
->type
== INTEL_OUTPUT_EDP
)
4059 return enc_to_dig_port(&encoder
->base
)->port
;
4066 * Enable PCH resources required for PCH ports:
4068 * - FDI training & RX/TX
4069 * - update transcoder timings
4070 * - DP transcoding bits
4073 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4075 struct drm_device
*dev
= crtc
->dev
;
4076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4077 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4078 int pipe
= intel_crtc
->pipe
;
4081 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4083 if (IS_IVYBRIDGE(dev
))
4084 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4086 /* Write the TU size bits before fdi link training, so that error
4087 * detection works. */
4088 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4089 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4091 /* For PCH output, training FDI link */
4092 dev_priv
->display
.fdi_link_train(crtc
);
4094 /* We need to program the right clock selection before writing the pixel
4095 * mutliplier into the DPLL. */
4096 if (HAS_PCH_CPT(dev
)) {
4099 temp
= I915_READ(PCH_DPLL_SEL
);
4100 temp
|= TRANS_DPLL_ENABLE(pipe
);
4101 sel
= TRANS_DPLLB_SEL(pipe
);
4102 if (intel_crtc
->config
->shared_dpll
==
4103 intel_get_shared_dpll_by_id(dev_priv
, DPLL_ID_PCH_PLL_B
))
4107 I915_WRITE(PCH_DPLL_SEL
, temp
);
4110 /* XXX: pch pll's can be enabled any time before we enable the PCH
4111 * transcoder, and we actually should do this to not upset any PCH
4112 * transcoder that already use the clock when we share it.
4114 * Note that enable_shared_dpll tries to do the right thing, but
4115 * get_shared_dpll unconditionally resets the pll - we need that to have
4116 * the right LVDS enable sequence. */
4117 intel_enable_shared_dpll(intel_crtc
);
4119 /* set transcoder timing, panel must allow it */
4120 assert_panel_unlocked(dev_priv
, pipe
);
4121 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4123 intel_fdi_normal_train(crtc
);
4125 /* For PCH DP, enable TRANS_DP_CTL */
4126 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4127 const struct drm_display_mode
*adjusted_mode
=
4128 &intel_crtc
->config
->base
.adjusted_mode
;
4129 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4130 i915_reg_t reg
= TRANS_DP_CTL(pipe
);
4131 temp
= I915_READ(reg
);
4132 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4133 TRANS_DP_SYNC_MASK
|
4135 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4136 temp
|= bpc
<< 9; /* same format but at 11:9 */
4138 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
4139 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4140 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
4141 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4143 switch (intel_trans_dp_port_sel(crtc
)) {
4145 temp
|= TRANS_DP_PORT_SEL_B
;
4148 temp
|= TRANS_DP_PORT_SEL_C
;
4151 temp
|= TRANS_DP_PORT_SEL_D
;
4157 I915_WRITE(reg
, temp
);
4160 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4163 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4165 struct drm_device
*dev
= crtc
->dev
;
4166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4167 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4168 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4170 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4172 lpt_program_iclkip(crtc
);
4174 /* Set transcoder timing. */
4175 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4177 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4180 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4183 i915_reg_t dslreg
= PIPEDSL(pipe
);
4186 temp
= I915_READ(dslreg
);
4188 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4189 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4190 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4195 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
4196 unsigned scaler_user
, int *scaler_id
, unsigned int rotation
,
4197 int src_w
, int src_h
, int dst_w
, int dst_h
)
4199 struct intel_crtc_scaler_state
*scaler_state
=
4200 &crtc_state
->scaler_state
;
4201 struct intel_crtc
*intel_crtc
=
4202 to_intel_crtc(crtc_state
->base
.crtc
);
4205 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4206 (src_h
!= dst_w
|| src_w
!= dst_h
):
4207 (src_w
!= dst_w
|| src_h
!= dst_h
);
4210 * if plane is being disabled or scaler is no more required or force detach
4211 * - free scaler binded to this plane/crtc
4212 * - in order to do this, update crtc->scaler_usage
4214 * Here scaler state in crtc_state is set free so that
4215 * scaler can be assigned to other user. Actual register
4216 * update to free the scaler is done in plane/panel-fit programming.
4217 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4219 if (force_detach
|| !need_scaling
) {
4220 if (*scaler_id
>= 0) {
4221 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
4222 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4224 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4225 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4226 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
4227 scaler_state
->scaler_users
);
4234 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4235 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4237 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4238 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4239 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4240 "size is out of scaler range\n",
4241 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
4245 /* mark this plane as a scaler user in crtc_state */
4246 scaler_state
->scaler_users
|= (1 << scaler_user
);
4247 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4248 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4249 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
4250 scaler_state
->scaler_users
);
4256 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4258 * @state: crtc's scaler state
4261 * 0 - scaler_usage updated successfully
4262 * error - requested scaling cannot be supported or other error condition
4264 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
4266 struct intel_crtc
*intel_crtc
= to_intel_crtc(state
->base
.crtc
);
4267 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
4269 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4270 intel_crtc
->base
.base
.id
, intel_crtc
->pipe
, SKL_CRTC_INDEX
);
4272 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
4273 &state
->scaler_state
.scaler_id
, BIT(DRM_ROTATE_0
),
4274 state
->pipe_src_w
, state
->pipe_src_h
,
4275 adjusted_mode
->crtc_hdisplay
, adjusted_mode
->crtc_vdisplay
);
4279 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4281 * @state: crtc's scaler state
4282 * @plane_state: atomic plane state to update
4285 * 0 - scaler_usage updated successfully
4286 * error - requested scaling cannot be supported or other error condition
4288 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
4289 struct intel_plane_state
*plane_state
)
4292 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4293 struct intel_plane
*intel_plane
=
4294 to_intel_plane(plane_state
->base
.plane
);
4295 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4298 bool force_detach
= !fb
|| !plane_state
->visible
;
4300 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4301 intel_plane
->base
.base
.id
, intel_crtc
->pipe
,
4302 drm_plane_index(&intel_plane
->base
));
4304 ret
= skl_update_scaler(crtc_state
, force_detach
,
4305 drm_plane_index(&intel_plane
->base
),
4306 &plane_state
->scaler_id
,
4307 plane_state
->base
.rotation
,
4308 drm_rect_width(&plane_state
->src
) >> 16,
4309 drm_rect_height(&plane_state
->src
) >> 16,
4310 drm_rect_width(&plane_state
->dst
),
4311 drm_rect_height(&plane_state
->dst
));
4313 if (ret
|| plane_state
->scaler_id
< 0)
4316 /* check colorkey */
4317 if (plane_state
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4318 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4319 intel_plane
->base
.base
.id
);
4323 /* Check src format */
4324 switch (fb
->pixel_format
) {
4325 case DRM_FORMAT_RGB565
:
4326 case DRM_FORMAT_XBGR8888
:
4327 case DRM_FORMAT_XRGB8888
:
4328 case DRM_FORMAT_ABGR8888
:
4329 case DRM_FORMAT_ARGB8888
:
4330 case DRM_FORMAT_XRGB2101010
:
4331 case DRM_FORMAT_XBGR2101010
:
4332 case DRM_FORMAT_YUYV
:
4333 case DRM_FORMAT_YVYU
:
4334 case DRM_FORMAT_UYVY
:
4335 case DRM_FORMAT_VYUY
:
4338 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4339 intel_plane
->base
.base
.id
, fb
->base
.id
, fb
->pixel_format
);
4346 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
4350 for (i
= 0; i
< crtc
->num_scalers
; i
++)
4351 skl_detach_scaler(crtc
, i
);
4354 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4356 struct drm_device
*dev
= crtc
->base
.dev
;
4357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4358 int pipe
= crtc
->pipe
;
4359 struct intel_crtc_scaler_state
*scaler_state
=
4360 &crtc
->config
->scaler_state
;
4362 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4364 if (crtc
->config
->pch_pfit
.enabled
) {
4367 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4368 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4372 id
= scaler_state
->scaler_id
;
4373 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4374 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4375 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4376 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4378 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4382 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4384 struct drm_device
*dev
= crtc
->base
.dev
;
4385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4386 int pipe
= crtc
->pipe
;
4388 if (crtc
->config
->pch_pfit
.enabled
) {
4389 /* Force use of hard-coded filter coefficients
4390 * as some pre-programmed values are broken,
4393 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4394 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4395 PF_PIPE_SEL_IVB(pipe
));
4397 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4398 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4399 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4403 void hsw_enable_ips(struct intel_crtc
*crtc
)
4405 struct drm_device
*dev
= crtc
->base
.dev
;
4406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4408 if (!crtc
->config
->ips_enabled
)
4412 * We can only enable IPS after we enable a plane and wait for a vblank
4413 * This function is called from post_plane_update, which is run after
4417 assert_plane_enabled(dev_priv
, crtc
->plane
);
4418 if (IS_BROADWELL(dev
)) {
4419 mutex_lock(&dev_priv
->rps
.hw_lock
);
4420 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4421 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4422 /* Quoting Art Runyan: "its not safe to expect any particular
4423 * value in IPS_CTL bit 31 after enabling IPS through the
4424 * mailbox." Moreover, the mailbox may return a bogus state,
4425 * so we need to just enable it and continue on.
4428 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4429 /* The bit only becomes 1 in the next vblank, so this wait here
4430 * is essentially intel_wait_for_vblank. If we don't have this
4431 * and don't wait for vblanks until the end of crtc_enable, then
4432 * the HW state readout code will complain that the expected
4433 * IPS_CTL value is not the one we read. */
4434 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4435 DRM_ERROR("Timed out waiting for IPS enable\n");
4439 void hsw_disable_ips(struct intel_crtc
*crtc
)
4441 struct drm_device
*dev
= crtc
->base
.dev
;
4442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4444 if (!crtc
->config
->ips_enabled
)
4447 assert_plane_enabled(dev_priv
, crtc
->plane
);
4448 if (IS_BROADWELL(dev
)) {
4449 mutex_lock(&dev_priv
->rps
.hw_lock
);
4450 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4451 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4452 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4453 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4454 DRM_ERROR("Timed out waiting for IPS disable\n");
4456 I915_WRITE(IPS_CTL
, 0);
4457 POSTING_READ(IPS_CTL
);
4460 /* We need to wait for a vblank before we can disable the plane. */
4461 intel_wait_for_vblank(dev
, crtc
->pipe
);
4464 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4466 if (intel_crtc
->overlay
) {
4467 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4470 mutex_lock(&dev
->struct_mutex
);
4471 dev_priv
->mm
.interruptible
= false;
4472 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4473 dev_priv
->mm
.interruptible
= true;
4474 mutex_unlock(&dev
->struct_mutex
);
4477 /* Let userspace switch the overlay on again. In most cases userspace
4478 * has to recompute where to put it anyway.
4483 * intel_post_enable_primary - Perform operations after enabling primary plane
4484 * @crtc: the CRTC whose primary plane was just enabled
4486 * Performs potentially sleeping operations that must be done after the primary
4487 * plane is enabled, such as updating FBC and IPS. Note that this may be
4488 * called due to an explicit primary plane update, or due to an implicit
4489 * re-enable that is caused when a sprite plane is updated to no longer
4490 * completely hide the primary plane.
4493 intel_post_enable_primary(struct drm_crtc
*crtc
)
4495 struct drm_device
*dev
= crtc
->dev
;
4496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4497 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4498 int pipe
= intel_crtc
->pipe
;
4501 * FIXME IPS should be fine as long as one plane is
4502 * enabled, but in practice it seems to have problems
4503 * when going from primary only to sprite only and vice
4506 hsw_enable_ips(intel_crtc
);
4509 * Gen2 reports pipe underruns whenever all planes are disabled.
4510 * So don't enable underrun reporting before at least some planes
4512 * FIXME: Need to fix the logic to work when we turn off all planes
4513 * but leave the pipe running.
4516 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4518 /* Underruns don't always raise interrupts, so check manually. */
4519 intel_check_cpu_fifo_underruns(dev_priv
);
4520 intel_check_pch_fifo_underruns(dev_priv
);
4523 /* FIXME move all this to pre_plane_update() with proper state tracking */
4525 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4527 struct drm_device
*dev
= crtc
->dev
;
4528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4529 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4530 int pipe
= intel_crtc
->pipe
;
4533 * Gen2 reports pipe underruns whenever all planes are disabled.
4534 * So diasble underrun reporting before all the planes get disabled.
4535 * FIXME: Need to fix the logic to work when we turn off all planes
4536 * but leave the pipe running.
4539 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4542 * FIXME IPS should be fine as long as one plane is
4543 * enabled, but in practice it seems to have problems
4544 * when going from primary only to sprite only and vice
4547 hsw_disable_ips(intel_crtc
);
4550 /* FIXME get rid of this and use pre_plane_update */
4552 intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
)
4554 struct drm_device
*dev
= crtc
->dev
;
4555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4556 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4557 int pipe
= intel_crtc
->pipe
;
4559 intel_pre_disable_primary(crtc
);
4562 * Vblank time updates from the shadow to live plane control register
4563 * are blocked if the memory self-refresh mode is active at that
4564 * moment. So to make sure the plane gets truly disabled, disable
4565 * first the self-refresh mode. The self-refresh enable bit in turn
4566 * will be checked/applied by the HW only at the next frame start
4567 * event which is after the vblank start event, so we need to have a
4568 * wait-for-vblank between disabling the plane and the pipe.
4570 if (HAS_GMCH_DISPLAY(dev
)) {
4571 intel_set_memory_cxsr(dev_priv
, false);
4572 dev_priv
->wm
.vlv
.cxsr
= false;
4573 intel_wait_for_vblank(dev
, pipe
);
4577 static void intel_post_plane_update(struct intel_crtc_state
*old_crtc_state
)
4579 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
4580 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
4581 struct intel_crtc_state
*pipe_config
=
4582 to_intel_crtc_state(crtc
->base
.state
);
4583 struct drm_device
*dev
= crtc
->base
.dev
;
4584 struct drm_plane
*primary
= crtc
->base
.primary
;
4585 struct drm_plane_state
*old_pri_state
=
4586 drm_atomic_get_existing_plane_state(old_state
, primary
);
4588 intel_frontbuffer_flip(dev
, pipe_config
->fb_bits
);
4590 crtc
->wm
.cxsr_allowed
= true;
4592 if (pipe_config
->update_wm_post
&& pipe_config
->base
.active
)
4593 intel_update_watermarks(&crtc
->base
);
4595 if (old_pri_state
) {
4596 struct intel_plane_state
*primary_state
=
4597 to_intel_plane_state(primary
->state
);
4598 struct intel_plane_state
*old_primary_state
=
4599 to_intel_plane_state(old_pri_state
);
4601 intel_fbc_post_update(crtc
);
4603 if (primary_state
->visible
&&
4604 (needs_modeset(&pipe_config
->base
) ||
4605 !old_primary_state
->visible
))
4606 intel_post_enable_primary(&crtc
->base
);
4610 static void intel_pre_plane_update(struct intel_crtc_state
*old_crtc_state
)
4612 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
4613 struct drm_device
*dev
= crtc
->base
.dev
;
4614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4615 struct intel_crtc_state
*pipe_config
=
4616 to_intel_crtc_state(crtc
->base
.state
);
4617 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
4618 struct drm_plane
*primary
= crtc
->base
.primary
;
4619 struct drm_plane_state
*old_pri_state
=
4620 drm_atomic_get_existing_plane_state(old_state
, primary
);
4621 bool modeset
= needs_modeset(&pipe_config
->base
);
4623 if (old_pri_state
) {
4624 struct intel_plane_state
*primary_state
=
4625 to_intel_plane_state(primary
->state
);
4626 struct intel_plane_state
*old_primary_state
=
4627 to_intel_plane_state(old_pri_state
);
4629 intel_fbc_pre_update(crtc
);
4631 if (old_primary_state
->visible
&&
4632 (modeset
|| !primary_state
->visible
))
4633 intel_pre_disable_primary(&crtc
->base
);
4636 if (pipe_config
->disable_cxsr
) {
4637 crtc
->wm
.cxsr_allowed
= false;
4640 * Vblank time updates from the shadow to live plane control register
4641 * are blocked if the memory self-refresh mode is active at that
4642 * moment. So to make sure the plane gets truly disabled, disable
4643 * first the self-refresh mode. The self-refresh enable bit in turn
4644 * will be checked/applied by the HW only at the next frame start
4645 * event which is after the vblank start event, so we need to have a
4646 * wait-for-vblank between disabling the plane and the pipe.
4648 if (old_crtc_state
->base
.active
) {
4649 intel_set_memory_cxsr(dev_priv
, false);
4650 dev_priv
->wm
.vlv
.cxsr
= false;
4651 intel_wait_for_vblank(dev
, crtc
->pipe
);
4656 * IVB workaround: must disable low power watermarks for at least
4657 * one frame before enabling scaling. LP watermarks can be re-enabled
4658 * when scaling is disabled.
4660 * WaCxSRDisabledForSpriteScaling:ivb
4662 if (pipe_config
->disable_lp_wm
) {
4663 ilk_disable_lp_wm(dev
);
4664 intel_wait_for_vblank(dev
, crtc
->pipe
);
4668 * If we're doing a modeset, we're done. No need to do any pre-vblank
4669 * watermark programming here.
4671 if (needs_modeset(&pipe_config
->base
))
4675 * For platforms that support atomic watermarks, program the
4676 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4677 * will be the intermediate values that are safe for both pre- and
4678 * post- vblank; when vblank happens, the 'active' values will be set
4679 * to the final 'target' values and we'll do this again to get the
4680 * optimal watermarks. For gen9+ platforms, the values we program here
4681 * will be the final target values which will get automatically latched
4682 * at vblank time; no further programming will be necessary.
4684 * If a platform hasn't been transitioned to atomic watermarks yet,
4685 * we'll continue to update watermarks the old way, if flags tell
4688 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4689 dev_priv
->display
.initial_watermarks(pipe_config
);
4690 else if (pipe_config
->update_wm_pre
)
4691 intel_update_watermarks(&crtc
->base
);
4694 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
, unsigned plane_mask
)
4696 struct drm_device
*dev
= crtc
->dev
;
4697 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4698 struct drm_plane
*p
;
4699 int pipe
= intel_crtc
->pipe
;
4701 intel_crtc_dpms_overlay_disable(intel_crtc
);
4703 drm_for_each_plane_mask(p
, dev
, plane_mask
)
4704 to_intel_plane(p
)->disable_plane(p
, crtc
);
4707 * FIXME: Once we grow proper nuclear flip support out of this we need
4708 * to compute the mask of flip planes precisely. For the time being
4709 * consider this a flip to a NULL plane.
4711 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4714 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4716 struct drm_device
*dev
= crtc
->dev
;
4717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4718 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4719 struct intel_encoder
*encoder
;
4720 int pipe
= intel_crtc
->pipe
;
4721 struct intel_crtc_state
*pipe_config
=
4722 to_intel_crtc_state(crtc
->state
);
4724 if (WARN_ON(intel_crtc
->active
))
4728 * Sometimes spurious CPU pipe underruns happen during FDI
4729 * training, at least with VGA+HDMI cloning. Suppress them.
4731 * On ILK we get an occasional spurious CPU pipe underruns
4732 * between eDP port A enable and vdd enable. Also PCH port
4733 * enable seems to result in the occasional CPU pipe underrun.
4735 * Spurious PCH underruns also occur during PCH enabling.
4737 if (intel_crtc
->config
->has_pch_encoder
|| IS_GEN5(dev_priv
))
4738 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4739 if (intel_crtc
->config
->has_pch_encoder
)
4740 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4742 if (intel_crtc
->config
->has_pch_encoder
)
4743 intel_prepare_shared_dpll(intel_crtc
);
4745 if (intel_crtc
->config
->has_dp_encoder
)
4746 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4748 intel_set_pipe_timings(intel_crtc
);
4749 intel_set_pipe_src_size(intel_crtc
);
4751 if (intel_crtc
->config
->has_pch_encoder
) {
4752 intel_cpu_transcoder_set_m_n(intel_crtc
,
4753 &intel_crtc
->config
->fdi_m_n
, NULL
);
4756 ironlake_set_pipeconf(crtc
);
4758 intel_crtc
->active
= true;
4760 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4761 if (encoder
->pre_enable
)
4762 encoder
->pre_enable(encoder
);
4764 if (intel_crtc
->config
->has_pch_encoder
) {
4765 /* Note: FDI PLL enabling _must_ be done before we enable the
4766 * cpu pipes, hence this is separate from all the other fdi/pch
4768 ironlake_fdi_pll_enable(intel_crtc
);
4770 assert_fdi_tx_disabled(dev_priv
, pipe
);
4771 assert_fdi_rx_disabled(dev_priv
, pipe
);
4774 ironlake_pfit_enable(intel_crtc
);
4777 * On ILK+ LUT must be loaded before the pipe is running but with
4780 intel_color_load_luts(&pipe_config
->base
);
4782 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4783 dev_priv
->display
.initial_watermarks(intel_crtc
->config
);
4784 intel_enable_pipe(intel_crtc
);
4786 if (intel_crtc
->config
->has_pch_encoder
)
4787 ironlake_pch_enable(crtc
);
4789 assert_vblank_disabled(crtc
);
4790 drm_crtc_vblank_on(crtc
);
4792 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4793 encoder
->enable(encoder
);
4795 if (HAS_PCH_CPT(dev
))
4796 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4798 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4799 if (intel_crtc
->config
->has_pch_encoder
)
4800 intel_wait_for_vblank(dev
, pipe
);
4801 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4802 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4805 /* IPS only exists on ULT machines and is tied to pipe A. */
4806 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4808 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4811 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4813 struct drm_device
*dev
= crtc
->dev
;
4814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4815 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4816 struct intel_encoder
*encoder
;
4817 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
4818 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4819 struct intel_crtc_state
*pipe_config
=
4820 to_intel_crtc_state(crtc
->state
);
4822 if (WARN_ON(intel_crtc
->active
))
4825 if (intel_crtc
->config
->has_pch_encoder
)
4826 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4829 if (intel_crtc
->config
->shared_dpll
)
4830 intel_enable_shared_dpll(intel_crtc
);
4832 if (intel_crtc
->config
->has_dp_encoder
)
4833 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4835 if (!intel_crtc
->config
->has_dsi_encoder
)
4836 intel_set_pipe_timings(intel_crtc
);
4838 intel_set_pipe_src_size(intel_crtc
);
4840 if (cpu_transcoder
!= TRANSCODER_EDP
&&
4841 !transcoder_is_dsi(cpu_transcoder
)) {
4842 I915_WRITE(PIPE_MULT(cpu_transcoder
),
4843 intel_crtc
->config
->pixel_multiplier
- 1);
4846 if (intel_crtc
->config
->has_pch_encoder
) {
4847 intel_cpu_transcoder_set_m_n(intel_crtc
,
4848 &intel_crtc
->config
->fdi_m_n
, NULL
);
4851 if (!intel_crtc
->config
->has_dsi_encoder
)
4852 haswell_set_pipeconf(crtc
);
4854 haswell_set_pipemisc(crtc
);
4856 intel_color_set_csc(&pipe_config
->base
);
4858 intel_crtc
->active
= true;
4860 if (intel_crtc
->config
->has_pch_encoder
)
4861 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4863 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4865 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4866 if (encoder
->pre_enable
)
4867 encoder
->pre_enable(encoder
);
4870 if (intel_crtc
->config
->has_pch_encoder
)
4871 dev_priv
->display
.fdi_link_train(crtc
);
4873 if (!intel_crtc
->config
->has_dsi_encoder
)
4874 intel_ddi_enable_pipe_clock(intel_crtc
);
4876 if (INTEL_INFO(dev
)->gen
>= 9)
4877 skylake_pfit_enable(intel_crtc
);
4879 ironlake_pfit_enable(intel_crtc
);
4882 * On ILK+ LUT must be loaded before the pipe is running but with
4885 intel_color_load_luts(&pipe_config
->base
);
4887 intel_ddi_set_pipe_settings(crtc
);
4888 if (!intel_crtc
->config
->has_dsi_encoder
)
4889 intel_ddi_enable_transcoder_func(crtc
);
4891 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4892 dev_priv
->display
.initial_watermarks(pipe_config
);
4894 intel_update_watermarks(crtc
);
4896 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4897 if (!intel_crtc
->config
->has_dsi_encoder
)
4898 intel_enable_pipe(intel_crtc
);
4900 if (intel_crtc
->config
->has_pch_encoder
)
4901 lpt_pch_enable(crtc
);
4903 if (intel_crtc
->config
->dp_encoder_is_mst
)
4904 intel_ddi_set_vc_payload_alloc(crtc
, true);
4906 assert_vblank_disabled(crtc
);
4907 drm_crtc_vblank_on(crtc
);
4909 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4910 encoder
->enable(encoder
);
4911 intel_opregion_notify_encoder(encoder
, true);
4914 if (intel_crtc
->config
->has_pch_encoder
) {
4915 intel_wait_for_vblank(dev
, pipe
);
4916 intel_wait_for_vblank(dev
, pipe
);
4917 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4918 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4922 /* If we change the relative order between pipe/planes enabling, we need
4923 * to change the workaround. */
4924 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
4925 if (IS_HASWELL(dev
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
4926 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
4927 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
4931 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
)
4933 struct drm_device
*dev
= crtc
->base
.dev
;
4934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4935 int pipe
= crtc
->pipe
;
4937 /* To avoid upsetting the power well on haswell only disable the pfit if
4938 * it's in use. The hw state code will make sure we get this right. */
4939 if (force
|| crtc
->config
->pch_pfit
.enabled
) {
4940 I915_WRITE(PF_CTL(pipe
), 0);
4941 I915_WRITE(PF_WIN_POS(pipe
), 0);
4942 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4946 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4948 struct drm_device
*dev
= crtc
->dev
;
4949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4950 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4951 struct intel_encoder
*encoder
;
4952 int pipe
= intel_crtc
->pipe
;
4955 * Sometimes spurious CPU pipe underruns happen when the
4956 * pipe is already disabled, but FDI RX/TX is still enabled.
4957 * Happens at least with VGA+HDMI cloning. Suppress them.
4959 if (intel_crtc
->config
->has_pch_encoder
) {
4960 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4961 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4964 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4965 encoder
->disable(encoder
);
4967 drm_crtc_vblank_off(crtc
);
4968 assert_vblank_disabled(crtc
);
4970 intel_disable_pipe(intel_crtc
);
4972 ironlake_pfit_disable(intel_crtc
, false);
4974 if (intel_crtc
->config
->has_pch_encoder
)
4975 ironlake_fdi_disable(crtc
);
4977 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4978 if (encoder
->post_disable
)
4979 encoder
->post_disable(encoder
);
4981 if (intel_crtc
->config
->has_pch_encoder
) {
4982 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4984 if (HAS_PCH_CPT(dev
)) {
4988 /* disable TRANS_DP_CTL */
4989 reg
= TRANS_DP_CTL(pipe
);
4990 temp
= I915_READ(reg
);
4991 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4992 TRANS_DP_PORT_SEL_MASK
);
4993 temp
|= TRANS_DP_PORT_SEL_NONE
;
4994 I915_WRITE(reg
, temp
);
4996 /* disable DPLL_SEL */
4997 temp
= I915_READ(PCH_DPLL_SEL
);
4998 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4999 I915_WRITE(PCH_DPLL_SEL
, temp
);
5002 ironlake_fdi_pll_disable(intel_crtc
);
5005 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5006 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5009 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5011 struct drm_device
*dev
= crtc
->dev
;
5012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5013 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5014 struct intel_encoder
*encoder
;
5015 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5017 if (intel_crtc
->config
->has_pch_encoder
)
5018 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5021 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5022 intel_opregion_notify_encoder(encoder
, false);
5023 encoder
->disable(encoder
);
5026 drm_crtc_vblank_off(crtc
);
5027 assert_vblank_disabled(crtc
);
5029 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5030 if (!intel_crtc
->config
->has_dsi_encoder
)
5031 intel_disable_pipe(intel_crtc
);
5033 if (intel_crtc
->config
->dp_encoder_is_mst
)
5034 intel_ddi_set_vc_payload_alloc(crtc
, false);
5036 if (!intel_crtc
->config
->has_dsi_encoder
)
5037 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5039 if (INTEL_INFO(dev
)->gen
>= 9)
5040 skylake_scaler_disable(intel_crtc
);
5042 ironlake_pfit_disable(intel_crtc
, false);
5044 if (!intel_crtc
->config
->has_dsi_encoder
)
5045 intel_ddi_disable_pipe_clock(intel_crtc
);
5047 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5048 if (encoder
->post_disable
)
5049 encoder
->post_disable(encoder
);
5051 if (intel_crtc
->config
->has_pch_encoder
) {
5052 lpt_disable_pch_transcoder(dev_priv
);
5053 lpt_disable_iclkip(dev_priv
);
5054 intel_ddi_fdi_disable(crtc
);
5056 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5061 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5063 struct drm_device
*dev
= crtc
->base
.dev
;
5064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5065 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5067 if (!pipe_config
->gmch_pfit
.control
)
5071 * The panel fitter should only be adjusted whilst the pipe is disabled,
5072 * according to register description and PRM.
5074 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5075 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5077 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5078 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5080 /* Border color in case we don't scale up to the full screen. Black by
5081 * default, change to something else for debugging. */
5082 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5085 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5089 return POWER_DOMAIN_PORT_DDI_A_LANES
;
5091 return POWER_DOMAIN_PORT_DDI_B_LANES
;
5093 return POWER_DOMAIN_PORT_DDI_C_LANES
;
5095 return POWER_DOMAIN_PORT_DDI_D_LANES
;
5097 return POWER_DOMAIN_PORT_DDI_E_LANES
;
5100 return POWER_DOMAIN_PORT_OTHER
;
5104 static enum intel_display_power_domain
port_to_aux_power_domain(enum port port
)
5108 return POWER_DOMAIN_AUX_A
;
5110 return POWER_DOMAIN_AUX_B
;
5112 return POWER_DOMAIN_AUX_C
;
5114 return POWER_DOMAIN_AUX_D
;
5116 /* FIXME: Check VBT for actual wiring of PORT E */
5117 return POWER_DOMAIN_AUX_D
;
5120 return POWER_DOMAIN_AUX_A
;
5124 enum intel_display_power_domain
5125 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5127 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5128 struct intel_digital_port
*intel_dig_port
;
5130 switch (intel_encoder
->type
) {
5131 case INTEL_OUTPUT_UNKNOWN
:
5132 /* Only DDI platforms should ever use this output type */
5133 WARN_ON_ONCE(!HAS_DDI(dev
));
5134 case INTEL_OUTPUT_DISPLAYPORT
:
5135 case INTEL_OUTPUT_HDMI
:
5136 case INTEL_OUTPUT_EDP
:
5137 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5138 return port_to_power_domain(intel_dig_port
->port
);
5139 case INTEL_OUTPUT_DP_MST
:
5140 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5141 return port_to_power_domain(intel_dig_port
->port
);
5142 case INTEL_OUTPUT_ANALOG
:
5143 return POWER_DOMAIN_PORT_CRT
;
5144 case INTEL_OUTPUT_DSI
:
5145 return POWER_DOMAIN_PORT_DSI
;
5147 return POWER_DOMAIN_PORT_OTHER
;
5151 enum intel_display_power_domain
5152 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
)
5154 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5155 struct intel_digital_port
*intel_dig_port
;
5157 switch (intel_encoder
->type
) {
5158 case INTEL_OUTPUT_UNKNOWN
:
5159 case INTEL_OUTPUT_HDMI
:
5161 * Only DDI platforms should ever use these output types.
5162 * We can get here after the HDMI detect code has already set
5163 * the type of the shared encoder. Since we can't be sure
5164 * what's the status of the given connectors, play safe and
5165 * run the DP detection too.
5167 WARN_ON_ONCE(!HAS_DDI(dev
));
5168 case INTEL_OUTPUT_DISPLAYPORT
:
5169 case INTEL_OUTPUT_EDP
:
5170 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5171 return port_to_aux_power_domain(intel_dig_port
->port
);
5172 case INTEL_OUTPUT_DP_MST
:
5173 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5174 return port_to_aux_power_domain(intel_dig_port
->port
);
5176 MISSING_CASE(intel_encoder
->type
);
5177 return POWER_DOMAIN_AUX_A
;
5181 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
,
5182 struct intel_crtc_state
*crtc_state
)
5184 struct drm_device
*dev
= crtc
->dev
;
5185 struct drm_encoder
*encoder
;
5186 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5187 enum pipe pipe
= intel_crtc
->pipe
;
5189 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
5191 if (!crtc_state
->base
.active
)
5194 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5195 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5196 if (crtc_state
->pch_pfit
.enabled
||
5197 crtc_state
->pch_pfit
.force_thru
)
5198 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5200 drm_for_each_encoder_mask(encoder
, dev
, crtc_state
->base
.encoder_mask
) {
5201 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5203 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5206 if (crtc_state
->shared_dpll
)
5207 mask
|= BIT(POWER_DOMAIN_PLLS
);
5212 static unsigned long
5213 modeset_get_crtc_power_domains(struct drm_crtc
*crtc
,
5214 struct intel_crtc_state
*crtc_state
)
5216 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5217 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5218 enum intel_display_power_domain domain
;
5219 unsigned long domains
, new_domains
, old_domains
;
5221 old_domains
= intel_crtc
->enabled_power_domains
;
5222 intel_crtc
->enabled_power_domains
= new_domains
=
5223 get_crtc_power_domains(crtc
, crtc_state
);
5225 domains
= new_domains
& ~old_domains
;
5227 for_each_power_domain(domain
, domains
)
5228 intel_display_power_get(dev_priv
, domain
);
5230 return old_domains
& ~new_domains
;
5233 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
5234 unsigned long domains
)
5236 enum intel_display_power_domain domain
;
5238 for_each_power_domain(domain
, domains
)
5239 intel_display_power_put(dev_priv
, domain
);
5242 static int intel_compute_max_dotclk(struct drm_i915_private
*dev_priv
)
5244 int max_cdclk_freq
= dev_priv
->max_cdclk_freq
;
5246 if (INTEL_INFO(dev_priv
)->gen
>= 9 ||
5247 IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5248 return max_cdclk_freq
;
5249 else if (IS_CHERRYVIEW(dev_priv
))
5250 return max_cdclk_freq
*95/100;
5251 else if (INTEL_INFO(dev_priv
)->gen
< 4)
5252 return 2*max_cdclk_freq
*90/100;
5254 return max_cdclk_freq
*90/100;
5257 static void intel_update_max_cdclk(struct drm_device
*dev
)
5259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5261 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
5262 u32 limit
= I915_READ(SKL_DFSM
) & SKL_DFSM_CDCLK_LIMIT_MASK
;
5264 if (limit
== SKL_DFSM_CDCLK_LIMIT_675
)
5265 dev_priv
->max_cdclk_freq
= 675000;
5266 else if (limit
== SKL_DFSM_CDCLK_LIMIT_540
)
5267 dev_priv
->max_cdclk_freq
= 540000;
5268 else if (limit
== SKL_DFSM_CDCLK_LIMIT_450
)
5269 dev_priv
->max_cdclk_freq
= 450000;
5271 dev_priv
->max_cdclk_freq
= 337500;
5272 } else if (IS_BROXTON(dev
)) {
5273 dev_priv
->max_cdclk_freq
= 624000;
5274 } else if (IS_BROADWELL(dev
)) {
5276 * FIXME with extra cooling we can allow
5277 * 540 MHz for ULX and 675 Mhz for ULT.
5278 * How can we know if extra cooling is
5279 * available? PCI ID, VTB, something else?
5281 if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5282 dev_priv
->max_cdclk_freq
= 450000;
5283 else if (IS_BDW_ULX(dev
))
5284 dev_priv
->max_cdclk_freq
= 450000;
5285 else if (IS_BDW_ULT(dev
))
5286 dev_priv
->max_cdclk_freq
= 540000;
5288 dev_priv
->max_cdclk_freq
= 675000;
5289 } else if (IS_CHERRYVIEW(dev
)) {
5290 dev_priv
->max_cdclk_freq
= 320000;
5291 } else if (IS_VALLEYVIEW(dev
)) {
5292 dev_priv
->max_cdclk_freq
= 400000;
5294 /* otherwise assume cdclk is fixed */
5295 dev_priv
->max_cdclk_freq
= dev_priv
->cdclk_freq
;
5298 dev_priv
->max_dotclk_freq
= intel_compute_max_dotclk(dev_priv
);
5300 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5301 dev_priv
->max_cdclk_freq
);
5303 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5304 dev_priv
->max_dotclk_freq
);
5307 static void intel_update_cdclk(struct drm_device
*dev
)
5309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5311 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5312 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5313 dev_priv
->cdclk_freq
);
5316 * Program the gmbus_freq based on the cdclk frequency.
5317 * BSpec erroneously claims we should aim for 4MHz, but
5318 * in fact 1MHz is the correct frequency.
5320 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5322 * Program the gmbus_freq based on the cdclk frequency.
5323 * BSpec erroneously claims we should aim for 4MHz, but
5324 * in fact 1MHz is the correct frequency.
5326 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5329 if (dev_priv
->max_cdclk_freq
== 0)
5330 intel_update_max_cdclk(dev
);
5333 static void broxton_set_cdclk(struct drm_device
*dev
, int frequency
)
5335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5338 uint32_t current_freq
;
5341 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5342 switch (frequency
) {
5344 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5345 ratio
= BXT_DE_PLL_RATIO(60);
5348 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5349 ratio
= BXT_DE_PLL_RATIO(60);
5352 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5353 ratio
= BXT_DE_PLL_RATIO(60);
5356 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5357 ratio
= BXT_DE_PLL_RATIO(60);
5360 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5361 ratio
= BXT_DE_PLL_RATIO(65);
5365 * Bypass frequency with DE PLL disabled. Init ratio, divider
5366 * to suppress GCC warning.
5372 DRM_ERROR("unsupported CDCLK freq %d", frequency
);
5377 mutex_lock(&dev_priv
->rps
.hw_lock
);
5378 /* Inform power controller of upcoming frequency change */
5379 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5381 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5384 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5389 current_freq
= I915_READ(CDCLK_CTL
) & CDCLK_FREQ_DECIMAL_MASK
;
5390 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5391 current_freq
= current_freq
* 500 + 1000;
5394 * DE PLL has to be disabled when
5395 * - setting to 19.2MHz (bypass, PLL isn't used)
5396 * - before setting to 624MHz (PLL needs toggling)
5397 * - before setting to any frequency from 624MHz (PLL needs toggling)
5399 if (frequency
== 19200 || frequency
== 624000 ||
5400 current_freq
== 624000) {
5401 I915_WRITE(BXT_DE_PLL_ENABLE
, ~BXT_DE_PLL_PLL_ENABLE
);
5403 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
),
5405 DRM_ERROR("timout waiting for DE PLL unlock\n");
5408 if (frequency
!= 19200) {
5411 val
= I915_READ(BXT_DE_PLL_CTL
);
5412 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5414 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5416 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5418 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
, 1))
5419 DRM_ERROR("timeout waiting for DE PLL lock\n");
5421 val
= I915_READ(CDCLK_CTL
);
5422 val
&= ~BXT_CDCLK_CD2X_DIV_SEL_MASK
;
5425 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5428 val
&= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5429 if (frequency
>= 500000)
5430 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5432 val
&= ~CDCLK_FREQ_DECIMAL_MASK
;
5433 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5434 val
|= (frequency
- 1000) / 500;
5435 I915_WRITE(CDCLK_CTL
, val
);
5438 mutex_lock(&dev_priv
->rps
.hw_lock
);
5439 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5440 DIV_ROUND_UP(frequency
, 25000));
5441 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5444 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5449 intel_update_cdclk(dev
);
5452 void broxton_init_cdclk(struct drm_device
*dev
)
5454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5458 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5459 * or else the reset will hang because there is no PCH to respond.
5460 * Move the handshake programming to initialization sequence.
5461 * Previously was left up to BIOS.
5463 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5464 val
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5465 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
);
5467 /* Enable PG1 for cdclk */
5468 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5470 /* check if cd clock is enabled */
5471 if (I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_PLL_ENABLE
) {
5472 DRM_DEBUG_KMS("Display already initialized\n");
5478 * - The initial CDCLK needs to be read from VBT.
5479 * Need to make this change after VBT has changes for BXT.
5480 * - check if setting the max (or any) cdclk freq is really necessary
5481 * here, it belongs to modeset time
5483 broxton_set_cdclk(dev
, 624000);
5485 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5486 POSTING_READ(DBUF_CTL
);
5490 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5491 DRM_ERROR("DBuf power enable timeout!\n");
5494 void broxton_uninit_cdclk(struct drm_device
*dev
)
5496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5498 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5499 POSTING_READ(DBUF_CTL
);
5503 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5504 DRM_ERROR("DBuf power disable timeout!\n");
5506 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5507 broxton_set_cdclk(dev
, 19200);
5509 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5512 static const struct skl_cdclk_entry
{
5515 } skl_cdclk_frequencies
[] = {
5516 { .freq
= 308570, .vco
= 8640 },
5517 { .freq
= 337500, .vco
= 8100 },
5518 { .freq
= 432000, .vco
= 8640 },
5519 { .freq
= 450000, .vco
= 8100 },
5520 { .freq
= 540000, .vco
= 8100 },
5521 { .freq
= 617140, .vco
= 8640 },
5522 { .freq
= 675000, .vco
= 8100 },
5525 static unsigned int skl_cdclk_decimal(unsigned int freq
)
5527 return (freq
- 1000) / 500;
5530 static unsigned int skl_cdclk_get_vco(unsigned int freq
)
5534 for (i
= 0; i
< ARRAY_SIZE(skl_cdclk_frequencies
); i
++) {
5535 const struct skl_cdclk_entry
*e
= &skl_cdclk_frequencies
[i
];
5537 if (e
->freq
== freq
)
5545 skl_dpll0_enable(struct drm_i915_private
*dev_priv
, unsigned int required_vco
)
5547 unsigned int min_freq
;
5550 /* select the minimum CDCLK before enabling DPLL 0 */
5551 val
= I915_READ(CDCLK_CTL
);
5552 val
&= ~CDCLK_FREQ_SEL_MASK
| ~CDCLK_FREQ_DECIMAL_MASK
;
5553 val
|= CDCLK_FREQ_337_308
;
5555 if (required_vco
== 8640)
5560 val
= CDCLK_FREQ_337_308
| skl_cdclk_decimal(min_freq
);
5562 I915_WRITE(CDCLK_CTL
, val
);
5563 POSTING_READ(CDCLK_CTL
);
5566 * We always enable DPLL0 with the lowest link rate possible, but still
5567 * taking into account the VCO required to operate the eDP panel at the
5568 * desired frequency. The usual DP link rates operate with a VCO of
5569 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5570 * The modeset code is responsible for the selection of the exact link
5571 * rate later on, with the constraint of choosing a frequency that
5572 * works with required_vco.
5574 val
= I915_READ(DPLL_CTRL1
);
5576 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
5577 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5578 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
5579 if (required_vco
== 8640)
5580 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
5583 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
5586 I915_WRITE(DPLL_CTRL1
, val
);
5587 POSTING_READ(DPLL_CTRL1
);
5589 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
5591 if (wait_for(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
, 5))
5592 DRM_ERROR("DPLL0 not locked\n");
5595 static bool skl_cdclk_pcu_ready(struct drm_i915_private
*dev_priv
)
5600 /* inform PCU we want to change CDCLK */
5601 val
= SKL_CDCLK_PREPARE_FOR_CHANGE
;
5602 mutex_lock(&dev_priv
->rps
.hw_lock
);
5603 ret
= sandybridge_pcode_read(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, &val
);
5604 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5606 return ret
== 0 && (val
& SKL_CDCLK_READY_FOR_CHANGE
);
5609 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private
*dev_priv
)
5613 for (i
= 0; i
< 15; i
++) {
5614 if (skl_cdclk_pcu_ready(dev_priv
))
5622 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
, unsigned int freq
)
5624 struct drm_device
*dev
= dev_priv
->dev
;
5625 u32 freq_select
, pcu_ack
;
5627 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq
);
5629 if (!skl_cdclk_wait_for_pcu_ready(dev_priv
)) {
5630 DRM_ERROR("failed to inform PCU about cdclk change\n");
5638 freq_select
= CDCLK_FREQ_450_432
;
5642 freq_select
= CDCLK_FREQ_540
;
5648 freq_select
= CDCLK_FREQ_337_308
;
5653 freq_select
= CDCLK_FREQ_675_617
;
5658 I915_WRITE(CDCLK_CTL
, freq_select
| skl_cdclk_decimal(freq
));
5659 POSTING_READ(CDCLK_CTL
);
5661 /* inform PCU of the change */
5662 mutex_lock(&dev_priv
->rps
.hw_lock
);
5663 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
5664 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5666 intel_update_cdclk(dev
);
5669 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5671 /* disable DBUF power */
5672 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5673 POSTING_READ(DBUF_CTL
);
5677 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5678 DRM_ERROR("DBuf power disable timeout\n");
5681 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) & ~LCPLL_PLL_ENABLE
);
5682 if (wait_for(!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
), 1))
5683 DRM_ERROR("Couldn't disable DPLL0\n");
5686 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
5688 unsigned int required_vco
;
5690 /* DPLL0 not enabled (happens on early BIOS versions) */
5691 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
)) {
5693 required_vco
= skl_cdclk_get_vco(dev_priv
->skl_boot_cdclk
);
5694 skl_dpll0_enable(dev_priv
, required_vco
);
5697 /* set CDCLK to the frequency the BIOS chose */
5698 skl_set_cdclk(dev_priv
, dev_priv
->skl_boot_cdclk
);
5700 /* enable DBUF power */
5701 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5702 POSTING_READ(DBUF_CTL
);
5706 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5707 DRM_ERROR("DBuf power enable timeout\n");
5710 int skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
5712 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
5713 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
5714 int freq
= dev_priv
->skl_boot_cdclk
;
5717 * check if the pre-os intialized the display
5718 * There is SWF18 scratchpad register defined which is set by the
5719 * pre-os which can be used by the OS drivers to check the status
5721 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5724 /* Is PLL enabled and locked ? */
5725 if (!((lcpll1
& LCPLL_PLL_ENABLE
) && (lcpll1
& LCPLL_PLL_LOCK
)))
5728 /* DPLL okay; verify the cdclock
5730 * Noticed in some instances that the freq selection is correct but
5731 * decimal part is programmed wrong from BIOS where pre-os does not
5732 * enable display. Verify the same as well.
5734 if (cdctl
== ((cdctl
& CDCLK_FREQ_SEL_MASK
) | skl_cdclk_decimal(freq
)))
5735 /* All well; nothing to sanitize */
5739 * As of now initialize with max cdclk till
5740 * we get dynamic cdclk support
5742 dev_priv
->skl_boot_cdclk
= dev_priv
->max_cdclk_freq
;
5743 skl_init_cdclk(dev_priv
);
5745 /* we did have to sanitize */
5749 /* Adjust CDclk dividers to allow high res or save power if possible */
5750 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5755 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5756 != dev_priv
->cdclk_freq
);
5758 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5760 else if (cdclk
== 266667)
5765 mutex_lock(&dev_priv
->rps
.hw_lock
);
5766 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5767 val
&= ~DSPFREQGUAR_MASK
;
5768 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5769 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5770 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5771 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5773 DRM_ERROR("timed out waiting for CDclk change\n");
5775 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5777 mutex_lock(&dev_priv
->sb_lock
);
5779 if (cdclk
== 400000) {
5782 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5784 /* adjust cdclk divider */
5785 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5786 val
&= ~CCK_FREQUENCY_VALUES
;
5788 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5790 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5791 CCK_FREQUENCY_STATUS
) == (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
5793 DRM_ERROR("timed out waiting for CDclk change\n");
5796 /* adjust self-refresh exit latency value */
5797 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5801 * For high bandwidth configs, we set a higher latency in the bunit
5802 * so that the core display fetch happens in time to avoid underruns.
5804 if (cdclk
== 400000)
5805 val
|= 4500 / 250; /* 4.5 usec */
5807 val
|= 3000 / 250; /* 3.0 usec */
5808 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5810 mutex_unlock(&dev_priv
->sb_lock
);
5812 intel_update_cdclk(dev
);
5815 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5820 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5821 != dev_priv
->cdclk_freq
);
5830 MISSING_CASE(cdclk
);
5835 * Specs are full of misinformation, but testing on actual
5836 * hardware has shown that we just need to write the desired
5837 * CCK divider into the Punit register.
5839 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5841 mutex_lock(&dev_priv
->rps
.hw_lock
);
5842 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5843 val
&= ~DSPFREQGUAR_MASK_CHV
;
5844 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5845 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5846 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5847 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5849 DRM_ERROR("timed out waiting for CDclk change\n");
5851 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5853 intel_update_cdclk(dev
);
5856 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5859 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5860 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5863 * Really only a few cases to deal with, as only 4 CDclks are supported:
5866 * 320/333MHz (depends on HPLL freq)
5868 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5869 * of the lower bin and adjust if needed.
5871 * We seem to get an unstable or solid color picture at 200MHz.
5872 * Not sure what's wrong. For now use 200MHz only when all pipes
5875 if (!IS_CHERRYVIEW(dev_priv
) &&
5876 max_pixclk
> freq_320
*limit
/100)
5878 else if (max_pixclk
> 266667*limit
/100)
5880 else if (max_pixclk
> 0)
5886 static int broxton_calc_cdclk(struct drm_i915_private
*dev_priv
,
5891 * - remove the guardband, it's not needed on BXT
5892 * - set 19.2MHz bypass frequency if there are no active pipes
5894 if (max_pixclk
> 576000*9/10)
5896 else if (max_pixclk
> 384000*9/10)
5898 else if (max_pixclk
> 288000*9/10)
5900 else if (max_pixclk
> 144000*9/10)
5906 /* Compute the max pixel clock for new configuration. */
5907 static int intel_mode_max_pixclk(struct drm_device
*dev
,
5908 struct drm_atomic_state
*state
)
5910 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
5911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5912 struct drm_crtc
*crtc
;
5913 struct drm_crtc_state
*crtc_state
;
5914 unsigned max_pixclk
= 0, i
;
5917 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
5918 sizeof(intel_state
->min_pixclk
));
5920 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5923 if (crtc_state
->enable
)
5924 pixclk
= crtc_state
->adjusted_mode
.crtc_clock
;
5926 intel_state
->min_pixclk
[i
] = pixclk
;
5929 for_each_pipe(dev_priv
, pipe
)
5930 max_pixclk
= max(intel_state
->min_pixclk
[pipe
], max_pixclk
);
5935 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state
*state
)
5937 struct drm_device
*dev
= state
->dev
;
5938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5939 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
5940 struct intel_atomic_state
*intel_state
=
5941 to_intel_atomic_state(state
);
5946 intel_state
->cdclk
= intel_state
->dev_cdclk
=
5947 valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5949 if (!intel_state
->active_crtcs
)
5950 intel_state
->dev_cdclk
= valleyview_calc_cdclk(dev_priv
, 0);
5955 static int broxton_modeset_calc_cdclk(struct drm_atomic_state
*state
)
5957 struct drm_device
*dev
= state
->dev
;
5958 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5959 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
5960 struct intel_atomic_state
*intel_state
=
5961 to_intel_atomic_state(state
);
5966 intel_state
->cdclk
= intel_state
->dev_cdclk
=
5967 broxton_calc_cdclk(dev_priv
, max_pixclk
);
5969 if (!intel_state
->active_crtcs
)
5970 intel_state
->dev_cdclk
= broxton_calc_cdclk(dev_priv
, 0);
5975 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
5977 unsigned int credits
, default_credits
;
5979 if (IS_CHERRYVIEW(dev_priv
))
5980 default_credits
= PFI_CREDIT(12);
5982 default_credits
= PFI_CREDIT(8);
5984 if (dev_priv
->cdclk_freq
>= dev_priv
->czclk_freq
) {
5985 /* CHV suggested value is 31 or 63 */
5986 if (IS_CHERRYVIEW(dev_priv
))
5987 credits
= PFI_CREDIT_63
;
5989 credits
= PFI_CREDIT(15);
5991 credits
= default_credits
;
5995 * WA - write default credits before re-programming
5996 * FIXME: should we also set the resend bit here?
5998 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6001 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6002 credits
| PFI_CREDIT_RESEND
);
6005 * FIXME is this guaranteed to clear
6006 * immediately or should we poll for it?
6008 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
6011 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
6013 struct drm_device
*dev
= old_state
->dev
;
6014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6015 struct intel_atomic_state
*old_intel_state
=
6016 to_intel_atomic_state(old_state
);
6017 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
6020 * FIXME: We can end up here with all power domains off, yet
6021 * with a CDCLK frequency other than the minimum. To account
6022 * for this take the PIPE-A power domain, which covers the HW
6023 * blocks needed for the following programming. This can be
6024 * removed once it's guaranteed that we get here either with
6025 * the minimum CDCLK set, or the required power domains
6028 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
6030 if (IS_CHERRYVIEW(dev
))
6031 cherryview_set_cdclk(dev
, req_cdclk
);
6033 valleyview_set_cdclk(dev
, req_cdclk
);
6035 vlv_program_pfi_credits(dev_priv
);
6037 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
6040 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
6042 struct drm_device
*dev
= crtc
->dev
;
6043 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6044 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6045 struct intel_encoder
*encoder
;
6046 struct intel_crtc_state
*pipe_config
=
6047 to_intel_crtc_state(crtc
->state
);
6048 int pipe
= intel_crtc
->pipe
;
6050 if (WARN_ON(intel_crtc
->active
))
6053 if (intel_crtc
->config
->has_dp_encoder
)
6054 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6056 intel_set_pipe_timings(intel_crtc
);
6057 intel_set_pipe_src_size(intel_crtc
);
6059 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
6060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6062 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6063 I915_WRITE(CHV_CANVAS(pipe
), 0);
6066 i9xx_set_pipeconf(intel_crtc
);
6068 intel_crtc
->active
= true;
6070 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6072 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6073 if (encoder
->pre_pll_enable
)
6074 encoder
->pre_pll_enable(encoder
);
6076 if (!intel_crtc
->config
->has_dsi_encoder
) {
6077 if (IS_CHERRYVIEW(dev
)) {
6078 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6079 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
6081 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6082 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
6086 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6087 if (encoder
->pre_enable
)
6088 encoder
->pre_enable(encoder
);
6090 i9xx_pfit_enable(intel_crtc
);
6092 intel_color_load_luts(&pipe_config
->base
);
6094 intel_update_watermarks(crtc
);
6095 intel_enable_pipe(intel_crtc
);
6097 assert_vblank_disabled(crtc
);
6098 drm_crtc_vblank_on(crtc
);
6100 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6101 encoder
->enable(encoder
);
6104 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
6106 struct drm_device
*dev
= crtc
->base
.dev
;
6107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6109 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
6110 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
6113 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
6115 struct drm_device
*dev
= crtc
->dev
;
6116 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6117 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6118 struct intel_encoder
*encoder
;
6119 struct intel_crtc_state
*pipe_config
=
6120 to_intel_crtc_state(crtc
->state
);
6121 int pipe
= intel_crtc
->pipe
;
6123 if (WARN_ON(intel_crtc
->active
))
6126 i9xx_set_pll_dividers(intel_crtc
);
6128 if (intel_crtc
->config
->has_dp_encoder
)
6129 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6131 intel_set_pipe_timings(intel_crtc
);
6132 intel_set_pipe_src_size(intel_crtc
);
6134 i9xx_set_pipeconf(intel_crtc
);
6136 intel_crtc
->active
= true;
6139 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6141 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6142 if (encoder
->pre_enable
)
6143 encoder
->pre_enable(encoder
);
6145 i9xx_enable_pll(intel_crtc
);
6147 i9xx_pfit_enable(intel_crtc
);
6149 intel_color_load_luts(&pipe_config
->base
);
6151 intel_update_watermarks(crtc
);
6152 intel_enable_pipe(intel_crtc
);
6154 assert_vblank_disabled(crtc
);
6155 drm_crtc_vblank_on(crtc
);
6157 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6158 encoder
->enable(encoder
);
6161 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6163 struct drm_device
*dev
= crtc
->base
.dev
;
6164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6166 if (!crtc
->config
->gmch_pfit
.control
)
6169 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6171 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6172 I915_READ(PFIT_CONTROL
));
6173 I915_WRITE(PFIT_CONTROL
, 0);
6176 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6178 struct drm_device
*dev
= crtc
->dev
;
6179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6180 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6181 struct intel_encoder
*encoder
;
6182 int pipe
= intel_crtc
->pipe
;
6185 * On gen2 planes are double buffered but the pipe isn't, so we must
6186 * wait for planes to fully turn off before disabling the pipe.
6189 intel_wait_for_vblank(dev
, pipe
);
6191 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6192 encoder
->disable(encoder
);
6194 drm_crtc_vblank_off(crtc
);
6195 assert_vblank_disabled(crtc
);
6197 intel_disable_pipe(intel_crtc
);
6199 i9xx_pfit_disable(intel_crtc
);
6201 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6202 if (encoder
->post_disable
)
6203 encoder
->post_disable(encoder
);
6205 if (!intel_crtc
->config
->has_dsi_encoder
) {
6206 if (IS_CHERRYVIEW(dev
))
6207 chv_disable_pll(dev_priv
, pipe
);
6208 else if (IS_VALLEYVIEW(dev
))
6209 vlv_disable_pll(dev_priv
, pipe
);
6211 i9xx_disable_pll(intel_crtc
);
6214 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6215 if (encoder
->post_pll_disable
)
6216 encoder
->post_pll_disable(encoder
);
6219 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6222 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
)
6224 struct intel_encoder
*encoder
;
6225 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6226 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6227 enum intel_display_power_domain domain
;
6228 unsigned long domains
;
6230 if (!intel_crtc
->active
)
6233 if (to_intel_plane_state(crtc
->primary
->state
)->visible
) {
6234 WARN_ON(intel_crtc
->unpin_work
);
6236 intel_pre_disable_primary_noatomic(crtc
);
6238 intel_crtc_disable_planes(crtc
, 1 << drm_plane_index(crtc
->primary
));
6239 to_intel_plane_state(crtc
->primary
->state
)->visible
= false;
6242 dev_priv
->display
.crtc_disable(crtc
);
6244 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6247 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->state
, NULL
) < 0);
6248 crtc
->state
->active
= false;
6249 intel_crtc
->active
= false;
6250 crtc
->enabled
= false;
6251 crtc
->state
->connector_mask
= 0;
6252 crtc
->state
->encoder_mask
= 0;
6254 for_each_encoder_on_crtc(crtc
->dev
, crtc
, encoder
)
6255 encoder
->base
.crtc
= NULL
;
6257 intel_fbc_disable(intel_crtc
);
6258 intel_update_watermarks(crtc
);
6259 intel_disable_shared_dpll(intel_crtc
);
6261 domains
= intel_crtc
->enabled_power_domains
;
6262 for_each_power_domain(domain
, domains
)
6263 intel_display_power_put(dev_priv
, domain
);
6264 intel_crtc
->enabled_power_domains
= 0;
6266 dev_priv
->active_crtcs
&= ~(1 << intel_crtc
->pipe
);
6267 dev_priv
->min_pixclk
[intel_crtc
->pipe
] = 0;
6271 * turn all crtc's off, but do not adjust state
6272 * This has to be paired with a call to intel_modeset_setup_hw_state.
6274 int intel_display_suspend(struct drm_device
*dev
)
6276 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6277 struct drm_atomic_state
*state
;
6280 state
= drm_atomic_helper_suspend(dev
);
6281 ret
= PTR_ERR_OR_ZERO(state
);
6283 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6285 dev_priv
->modeset_restore_state
= state
;
6289 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6291 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6293 drm_encoder_cleanup(encoder
);
6294 kfree(intel_encoder
);
6297 /* Cross check the actual hw state with our own modeset state tracking (and it's
6298 * internal consistency). */
6299 static void intel_connector_verify_state(struct intel_connector
*connector
)
6301 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
6303 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6304 connector
->base
.base
.id
,
6305 connector
->base
.name
);
6307 if (connector
->get_hw_state(connector
)) {
6308 struct intel_encoder
*encoder
= connector
->encoder
;
6309 struct drm_connector_state
*conn_state
= connector
->base
.state
;
6311 I915_STATE_WARN(!crtc
,
6312 "connector enabled without attached crtc\n");
6317 I915_STATE_WARN(!crtc
->state
->active
,
6318 "connector is active, but attached crtc isn't\n");
6320 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
6323 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
6324 "atomic encoder doesn't match attached encoder\n");
6326 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
6327 "attached encoder crtc differs from connector crtc\n");
6329 I915_STATE_WARN(crtc
&& crtc
->state
->active
,
6330 "attached crtc is active, but connector isn't\n");
6331 I915_STATE_WARN(!crtc
&& connector
->base
.state
->best_encoder
,
6332 "best encoder set without crtc!\n");
6336 int intel_connector_init(struct intel_connector
*connector
)
6338 drm_atomic_helper_connector_reset(&connector
->base
);
6340 if (!connector
->base
.state
)
6346 struct intel_connector
*intel_connector_alloc(void)
6348 struct intel_connector
*connector
;
6350 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6354 if (intel_connector_init(connector
) < 0) {
6362 /* Simple connector->get_hw_state implementation for encoders that support only
6363 * one connector and no cloning and hence the encoder state determines the state
6364 * of the connector. */
6365 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6368 struct intel_encoder
*encoder
= connector
->encoder
;
6370 return encoder
->get_hw_state(encoder
, &pipe
);
6373 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6375 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6376 return crtc_state
->fdi_lanes
;
6381 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6382 struct intel_crtc_state
*pipe_config
)
6384 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6385 struct intel_crtc
*other_crtc
;
6386 struct intel_crtc_state
*other_crtc_state
;
6388 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6389 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6390 if (pipe_config
->fdi_lanes
> 4) {
6391 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6392 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6396 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6397 if (pipe_config
->fdi_lanes
> 2) {
6398 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6399 pipe_config
->fdi_lanes
);
6406 if (INTEL_INFO(dev
)->num_pipes
== 2)
6409 /* Ivybridge 3 pipe is really complicated */
6414 if (pipe_config
->fdi_lanes
<= 2)
6417 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6419 intel_atomic_get_crtc_state(state
, other_crtc
);
6420 if (IS_ERR(other_crtc_state
))
6421 return PTR_ERR(other_crtc_state
);
6423 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6424 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6425 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6430 if (pipe_config
->fdi_lanes
> 2) {
6431 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6432 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6436 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6438 intel_atomic_get_crtc_state(state
, other_crtc
);
6439 if (IS_ERR(other_crtc_state
))
6440 return PTR_ERR(other_crtc_state
);
6442 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6443 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6453 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6454 struct intel_crtc_state
*pipe_config
)
6456 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6457 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6458 int lane
, link_bw
, fdi_dotclock
, ret
;
6459 bool needs_recompute
= false;
6462 /* FDI is a binary signal running at ~2.7GHz, encoding
6463 * each output octet as 10 bits. The actual frequency
6464 * is stored as a divider into a 100MHz clock, and the
6465 * mode pixel clock is stored in units of 1KHz.
6466 * Hence the bw of each lane in terms of the mode signal
6469 link_bw
= intel_fdi_link_freq(to_i915(dev
), pipe_config
);
6471 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6473 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6474 pipe_config
->pipe_bpp
);
6476 pipe_config
->fdi_lanes
= lane
;
6478 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6479 link_bw
, &pipe_config
->fdi_m_n
);
6481 ret
= ironlake_check_fdi_lanes(dev
, intel_crtc
->pipe
, pipe_config
);
6482 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6483 pipe_config
->pipe_bpp
-= 2*3;
6484 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6485 pipe_config
->pipe_bpp
);
6486 needs_recompute
= true;
6487 pipe_config
->bw_constrained
= true;
6492 if (needs_recompute
)
6498 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
6499 struct intel_crtc_state
*pipe_config
)
6501 if (pipe_config
->pipe_bpp
> 24)
6504 /* HSW can handle pixel rate up to cdclk? */
6505 if (IS_HASWELL(dev_priv
))
6509 * We compare against max which means we must take
6510 * the increased cdclk requirement into account when
6511 * calculating the new cdclk.
6513 * Should measure whether using a lower cdclk w/o IPS
6515 return ilk_pipe_pixel_rate(pipe_config
) <=
6516 dev_priv
->max_cdclk_freq
* 95 / 100;
6519 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6520 struct intel_crtc_state
*pipe_config
)
6522 struct drm_device
*dev
= crtc
->base
.dev
;
6523 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6525 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6526 hsw_crtc_supports_ips(crtc
) &&
6527 pipe_config_supports_ips(dev_priv
, pipe_config
);
6530 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
6532 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6534 /* GDG double wide on either pipe, otherwise pipe A only */
6535 return INTEL_INFO(dev_priv
)->gen
< 4 &&
6536 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
6539 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6540 struct intel_crtc_state
*pipe_config
)
6542 struct drm_device
*dev
= crtc
->base
.dev
;
6543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6544 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6546 /* FIXME should check pixel clock limits on all platforms */
6547 if (INTEL_INFO(dev
)->gen
< 4) {
6548 int clock_limit
= dev_priv
->max_cdclk_freq
* 9 / 10;
6551 * Enable double wide mode when the dot clock
6552 * is > 90% of the (display) core speed.
6554 if (intel_crtc_supports_double_wide(crtc
) &&
6555 adjusted_mode
->crtc_clock
> clock_limit
) {
6557 pipe_config
->double_wide
= true;
6560 if (adjusted_mode
->crtc_clock
> clock_limit
) {
6561 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6562 adjusted_mode
->crtc_clock
, clock_limit
,
6563 yesno(pipe_config
->double_wide
));
6569 * Pipe horizontal size must be even in:
6571 * - LVDS dual channel mode
6572 * - Double wide pipe
6574 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6575 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6576 pipe_config
->pipe_src_w
&= ~1;
6578 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6579 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6581 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6582 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
6586 hsw_compute_ips_config(crtc
, pipe_config
);
6588 if (pipe_config
->has_pch_encoder
)
6589 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6594 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6596 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6597 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
6598 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6601 if (!(lcpll1
& LCPLL_PLL_ENABLE
))
6602 return 24000; /* 24MHz is the cd freq with NSSC ref */
6604 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
6607 linkrate
= (I915_READ(DPLL_CTRL1
) &
6608 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
6610 if (linkrate
== DPLL_CTRL1_LINK_RATE_2160
||
6611 linkrate
== DPLL_CTRL1_LINK_RATE_1080
) {
6613 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6614 case CDCLK_FREQ_450_432
:
6616 case CDCLK_FREQ_337_308
:
6618 case CDCLK_FREQ_675_617
:
6621 WARN(1, "Unknown cd freq selection\n");
6625 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6626 case CDCLK_FREQ_450_432
:
6628 case CDCLK_FREQ_337_308
:
6630 case CDCLK_FREQ_675_617
:
6633 WARN(1, "Unknown cd freq selection\n");
6637 /* error case, do as if DPLL0 isn't enabled */
6641 static int broxton_get_display_clock_speed(struct drm_device
*dev
)
6643 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6644 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6645 uint32_t pll_ratio
= I915_READ(BXT_DE_PLL_CTL
) & BXT_DE_PLL_RATIO_MASK
;
6646 uint32_t pll_enab
= I915_READ(BXT_DE_PLL_ENABLE
);
6649 if (!(pll_enab
& BXT_DE_PLL_PLL_ENABLE
))
6652 cdclk
= 19200 * pll_ratio
/ 2;
6654 switch (cdctl
& BXT_CDCLK_CD2X_DIV_SEL_MASK
) {
6655 case BXT_CDCLK_CD2X_DIV_SEL_1
:
6656 return cdclk
; /* 576MHz or 624MHz */
6657 case BXT_CDCLK_CD2X_DIV_SEL_1_5
:
6658 return cdclk
* 2 / 3; /* 384MHz */
6659 case BXT_CDCLK_CD2X_DIV_SEL_2
:
6660 return cdclk
/ 2; /* 288MHz */
6661 case BXT_CDCLK_CD2X_DIV_SEL_4
:
6662 return cdclk
/ 4; /* 144MHz */
6665 /* error case, do as if DE PLL isn't enabled */
6669 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6672 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6673 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6675 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6677 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6679 else if (freq
== LCPLL_CLK_FREQ_450
)
6681 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6683 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6689 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6692 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6693 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6695 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6697 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6699 else if (freq
== LCPLL_CLK_FREQ_450
)
6701 else if (IS_HSW_ULT(dev
))
6707 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6709 return vlv_get_cck_clock_hpll(to_i915(dev
), "cdclk",
6710 CCK_DISPLAY_CLOCK_CONTROL
);
6713 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6718 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6723 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6728 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6733 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6737 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6739 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6740 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6742 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6744 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6746 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6749 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6750 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6752 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6757 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6761 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6763 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6766 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6767 case GC_DISPLAY_CLOCK_333_MHZ
:
6770 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6776 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6781 static int i85x_get_display_clock_speed(struct drm_device
*dev
)
6786 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6787 * encoding is different :(
6788 * FIXME is this the right way to detect 852GM/852GMV?
6790 if (dev
->pdev
->revision
== 0x1)
6793 pci_bus_read_config_word(dev
->pdev
->bus
,
6794 PCI_DEVFN(0, 3), HPLLCC
, &hpllcc
);
6796 /* Assume that the hardware is in the high speed state. This
6797 * should be the default.
6799 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6800 case GC_CLOCK_133_200
:
6801 case GC_CLOCK_133_200_2
:
6802 case GC_CLOCK_100_200
:
6804 case GC_CLOCK_166_250
:
6806 case GC_CLOCK_100_133
:
6808 case GC_CLOCK_133_266
:
6809 case GC_CLOCK_133_266_2
:
6810 case GC_CLOCK_166_266
:
6814 /* Shouldn't happen */
6818 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6823 static unsigned int intel_hpll_vco(struct drm_device
*dev
)
6825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6826 static const unsigned int blb_vco
[8] = {
6833 static const unsigned int pnv_vco
[8] = {
6840 static const unsigned int cl_vco
[8] = {
6849 static const unsigned int elk_vco
[8] = {
6855 static const unsigned int ctg_vco
[8] = {
6863 const unsigned int *vco_table
;
6867 /* FIXME other chipsets? */
6869 vco_table
= ctg_vco
;
6870 else if (IS_G4X(dev
))
6871 vco_table
= elk_vco
;
6872 else if (IS_CRESTLINE(dev
))
6874 else if (IS_PINEVIEW(dev
))
6875 vco_table
= pnv_vco
;
6876 else if (IS_G33(dev
))
6877 vco_table
= blb_vco
;
6881 tmp
= I915_READ(IS_MOBILE(dev
) ? HPLLVCO_MOBILE
: HPLLVCO
);
6883 vco
= vco_table
[tmp
& 0x7];
6885 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp
);
6887 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco
);
6892 static int gm45_get_display_clock_speed(struct drm_device
*dev
)
6894 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6897 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6899 cdclk_sel
= (tmp
>> 12) & 0x1;
6905 return cdclk_sel
? 333333 : 222222;
6907 return cdclk_sel
? 320000 : 228571;
6909 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco
, tmp
);
6914 static int i965gm_get_display_clock_speed(struct drm_device
*dev
)
6916 static const uint8_t div_3200
[] = { 16, 10, 8 };
6917 static const uint8_t div_4000
[] = { 20, 12, 10 };
6918 static const uint8_t div_5333
[] = { 24, 16, 14 };
6919 const uint8_t *div_table
;
6920 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6923 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6925 cdclk_sel
= ((tmp
>> 8) & 0x1f) - 1;
6927 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
6932 div_table
= div_3200
;
6935 div_table
= div_4000
;
6938 div_table
= div_5333
;
6944 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
6947 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco
, tmp
);
6951 static int g33_get_display_clock_speed(struct drm_device
*dev
)
6953 static const uint8_t div_3200
[] = { 12, 10, 8, 7, 5, 16 };
6954 static const uint8_t div_4000
[] = { 14, 12, 10, 8, 6, 20 };
6955 static const uint8_t div_4800
[] = { 20, 14, 12, 10, 8, 24 };
6956 static const uint8_t div_5333
[] = { 20, 16, 12, 12, 8, 28 };
6957 const uint8_t *div_table
;
6958 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6961 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6963 cdclk_sel
= (tmp
>> 4) & 0x7;
6965 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
6970 div_table
= div_3200
;
6973 div_table
= div_4000
;
6976 div_table
= div_4800
;
6979 div_table
= div_5333
;
6985 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
6988 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco
, tmp
);
6993 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
6995 while (*num
> DATA_LINK_M_N_MASK
||
6996 *den
> DATA_LINK_M_N_MASK
) {
7002 static void compute_m_n(unsigned int m
, unsigned int n
,
7003 uint32_t *ret_m
, uint32_t *ret_n
)
7005 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7006 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
7007 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7011 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
7012 int pixel_clock
, int link_clock
,
7013 struct intel_link_m_n
*m_n
)
7017 compute_m_n(bits_per_pixel
* pixel_clock
,
7018 link_clock
* nlanes
* 8,
7019 &m_n
->gmch_m
, &m_n
->gmch_n
);
7021 compute_m_n(pixel_clock
, link_clock
,
7022 &m_n
->link_m
, &m_n
->link_n
);
7025 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7027 if (i915
.panel_use_ssc
>= 0)
7028 return i915
.panel_use_ssc
!= 0;
7029 return dev_priv
->vbt
.lvds_use_ssc
7030 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7033 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
7035 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7038 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
7040 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7043 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7044 struct intel_crtc_state
*crtc_state
,
7045 intel_clock_t
*reduced_clock
)
7047 struct drm_device
*dev
= crtc
->base
.dev
;
7050 if (IS_PINEVIEW(dev
)) {
7051 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7053 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7055 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7057 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7060 crtc_state
->dpll_hw_state
.fp0
= fp
;
7062 crtc
->lowfreq_avail
= false;
7063 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7065 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7066 crtc
->lowfreq_avail
= true;
7068 crtc_state
->dpll_hw_state
.fp1
= fp
;
7072 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7078 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7079 * and set it to a reasonable value instead.
7081 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7082 reg_val
&= 0xffffff00;
7083 reg_val
|= 0x00000030;
7084 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7086 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7087 reg_val
&= 0x8cffffff;
7088 reg_val
= 0x8c000000;
7089 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7091 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7092 reg_val
&= 0xffffff00;
7093 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7095 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7096 reg_val
&= 0x00ffffff;
7097 reg_val
|= 0xb0000000;
7098 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7101 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
7102 struct intel_link_m_n
*m_n
)
7104 struct drm_device
*dev
= crtc
->base
.dev
;
7105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7106 int pipe
= crtc
->pipe
;
7108 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7109 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7110 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7111 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7114 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
7115 struct intel_link_m_n
*m_n
,
7116 struct intel_link_m_n
*m2_n2
)
7118 struct drm_device
*dev
= crtc
->base
.dev
;
7119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7120 int pipe
= crtc
->pipe
;
7121 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
7123 if (INTEL_INFO(dev
)->gen
>= 5) {
7124 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7125 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7126 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7127 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7128 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7129 * for gen < 8) and if DRRS is supported (to make sure the
7130 * registers are not unnecessarily accessed).
7132 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
7133 crtc
->config
->has_drrs
) {
7134 I915_WRITE(PIPE_DATA_M2(transcoder
),
7135 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7136 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7137 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7138 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7141 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7142 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7143 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7144 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7148 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
7150 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7153 dp_m_n
= &crtc
->config
->dp_m_n
;
7154 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
7155 } else if (m_n
== M2_N2
) {
7158 * M2_N2 registers are not supported. Hence m2_n2 divider value
7159 * needs to be programmed into M1_N1.
7161 dp_m_n
= &crtc
->config
->dp_m2_n2
;
7163 DRM_ERROR("Unsupported divider value\n");
7167 if (crtc
->config
->has_pch_encoder
)
7168 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
7170 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
7173 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7174 struct intel_crtc_state
*pipe_config
)
7176 pipe_config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
7177 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
7178 DPLL_VCO_ENABLE
| DPLL_EXT_BUFFER_ENABLE_VLV
;
7179 if (crtc
->pipe
!= PIPE_A
)
7180 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7182 pipe_config
->dpll_hw_state
.dpll_md
=
7183 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7186 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7187 struct intel_crtc_state
*pipe_config
)
7189 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7190 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
7192 if (crtc
->pipe
!= PIPE_A
)
7193 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7195 pipe_config
->dpll_hw_state
.dpll_md
=
7196 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7199 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7200 const struct intel_crtc_state
*pipe_config
)
7202 struct drm_device
*dev
= crtc
->base
.dev
;
7203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7204 int pipe
= crtc
->pipe
;
7206 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7207 u32 coreclk
, reg_val
;
7209 mutex_lock(&dev_priv
->sb_lock
);
7211 bestn
= pipe_config
->dpll
.n
;
7212 bestm1
= pipe_config
->dpll
.m1
;
7213 bestm2
= pipe_config
->dpll
.m2
;
7214 bestp1
= pipe_config
->dpll
.p1
;
7215 bestp2
= pipe_config
->dpll
.p2
;
7217 /* See eDP HDMI DPIO driver vbios notes doc */
7219 /* PLL B needs special handling */
7221 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7223 /* Set up Tx target for periodic Rcomp update */
7224 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7226 /* Disable target IRef on PLL */
7227 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7228 reg_val
&= 0x00ffffff;
7229 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7231 /* Disable fast lock */
7232 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7234 /* Set idtafcrecal before PLL is enabled */
7235 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7236 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7237 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7238 mdiv
|= (1 << DPIO_K_SHIFT
);
7241 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7242 * but we don't support that).
7243 * Note: don't use the DAC post divider as it seems unstable.
7245 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7246 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7248 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7249 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7251 /* Set HBR and RBR LPF coefficients */
7252 if (pipe_config
->port_clock
== 162000 ||
7253 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
7254 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
7255 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7258 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7261 if (pipe_config
->has_dp_encoder
) {
7262 /* Use SSC source */
7264 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7267 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7269 } else { /* HDMI or VGA */
7270 /* Use bend source */
7272 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7275 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7279 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7280 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7281 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
7282 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
7283 coreclk
|= 0x01000000;
7284 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7286 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7287 mutex_unlock(&dev_priv
->sb_lock
);
7290 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7291 const struct intel_crtc_state
*pipe_config
)
7293 struct drm_device
*dev
= crtc
->base
.dev
;
7294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7295 int pipe
= crtc
->pipe
;
7296 i915_reg_t dpll_reg
= DPLL(crtc
->pipe
);
7297 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7298 u32 loopfilter
, tribuf_calcntr
;
7299 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7303 bestn
= pipe_config
->dpll
.n
;
7304 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7305 bestm1
= pipe_config
->dpll
.m1
;
7306 bestm2
= pipe_config
->dpll
.m2
>> 22;
7307 bestp1
= pipe_config
->dpll
.p1
;
7308 bestp2
= pipe_config
->dpll
.p2
;
7309 vco
= pipe_config
->dpll
.vco
;
7314 * Enable Refclk and SSC
7316 I915_WRITE(dpll_reg
,
7317 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7319 mutex_lock(&dev_priv
->sb_lock
);
7321 /* p1 and p2 divider */
7322 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7323 5 << DPIO_CHV_S1_DIV_SHIFT
|
7324 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7325 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7326 1 << DPIO_CHV_K_DIV_SHIFT
);
7328 /* Feedback post-divider - m2 */
7329 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7331 /* Feedback refclk divider - n and m1 */
7332 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7333 DPIO_CHV_M1_DIV_BY_2
|
7334 1 << DPIO_CHV_N_DIV_SHIFT
);
7336 /* M2 fraction division */
7337 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7339 /* M2 fraction division enable */
7340 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7341 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7342 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7344 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7345 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7347 /* Program digital lock detect threshold */
7348 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7349 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7350 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7351 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7353 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7354 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7357 if (vco
== 5400000) {
7358 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7359 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7360 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7361 tribuf_calcntr
= 0x9;
7362 } else if (vco
<= 6200000) {
7363 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7364 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7365 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7366 tribuf_calcntr
= 0x9;
7367 } else if (vco
<= 6480000) {
7368 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7369 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7370 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7371 tribuf_calcntr
= 0x8;
7373 /* Not supported. Apply the same limits as in the max case */
7374 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7375 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7376 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7379 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7381 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7382 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7383 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7384 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7387 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7388 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7391 mutex_unlock(&dev_priv
->sb_lock
);
7395 * vlv_force_pll_on - forcibly enable just the PLL
7396 * @dev_priv: i915 private structure
7397 * @pipe: pipe PLL to enable
7398 * @dpll: PLL configuration
7400 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7401 * in cases where we need the PLL enabled even when @pipe is not going to
7404 int vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7405 const struct dpll
*dpll
)
7407 struct intel_crtc
*crtc
=
7408 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7409 struct intel_crtc_state
*pipe_config
;
7411 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7415 pipe_config
->base
.crtc
= &crtc
->base
;
7416 pipe_config
->pixel_multiplier
= 1;
7417 pipe_config
->dpll
= *dpll
;
7419 if (IS_CHERRYVIEW(dev
)) {
7420 chv_compute_dpll(crtc
, pipe_config
);
7421 chv_prepare_pll(crtc
, pipe_config
);
7422 chv_enable_pll(crtc
, pipe_config
);
7424 vlv_compute_dpll(crtc
, pipe_config
);
7425 vlv_prepare_pll(crtc
, pipe_config
);
7426 vlv_enable_pll(crtc
, pipe_config
);
7435 * vlv_force_pll_off - forcibly disable just the PLL
7436 * @dev_priv: i915 private structure
7437 * @pipe: pipe PLL to disable
7439 * Disable the PLL for @pipe. To be used in cases where we need
7440 * the PLL enabled even when @pipe is not going to be enabled.
7442 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7444 if (IS_CHERRYVIEW(dev
))
7445 chv_disable_pll(to_i915(dev
), pipe
);
7447 vlv_disable_pll(to_i915(dev
), pipe
);
7450 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
7451 struct intel_crtc_state
*crtc_state
,
7452 intel_clock_t
*reduced_clock
)
7454 struct drm_device
*dev
= crtc
->base
.dev
;
7455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7458 struct dpll
*clock
= &crtc_state
->dpll
;
7460 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7462 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7463 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
7465 dpll
= DPLL_VGA_MODE_DIS
;
7467 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7468 dpll
|= DPLLB_MODE_LVDS
;
7470 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7472 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7473 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7474 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7478 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7480 if (crtc_state
->has_dp_encoder
)
7481 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7483 /* compute bitmask from p1 value */
7484 if (IS_PINEVIEW(dev
))
7485 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7487 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7488 if (IS_G4X(dev
) && reduced_clock
)
7489 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7491 switch (clock
->p2
) {
7493 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7496 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7499 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7502 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7505 if (INTEL_INFO(dev
)->gen
>= 4)
7506 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7508 if (crtc_state
->sdvo_tv_clock
)
7509 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7510 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7511 intel_panel_use_ssc(dev_priv
))
7512 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7514 dpll
|= PLL_REF_INPUT_DREFCLK
;
7516 dpll
|= DPLL_VCO_ENABLE
;
7517 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7519 if (INTEL_INFO(dev
)->gen
>= 4) {
7520 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7521 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7522 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7526 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
7527 struct intel_crtc_state
*crtc_state
,
7528 intel_clock_t
*reduced_clock
)
7530 struct drm_device
*dev
= crtc
->base
.dev
;
7531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7533 struct dpll
*clock
= &crtc_state
->dpll
;
7535 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7537 dpll
= DPLL_VGA_MODE_DIS
;
7539 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7540 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7543 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7545 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7547 dpll
|= PLL_P2_DIVIDE_BY_4
;
7550 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
7551 dpll
|= DPLL_DVO_2X_MODE
;
7553 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7554 intel_panel_use_ssc(dev_priv
))
7555 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7557 dpll
|= PLL_REF_INPUT_DREFCLK
;
7559 dpll
|= DPLL_VCO_ENABLE
;
7560 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7563 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7565 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7567 enum pipe pipe
= intel_crtc
->pipe
;
7568 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7569 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
7570 uint32_t crtc_vtotal
, crtc_vblank_end
;
7573 /* We need to be careful not to changed the adjusted mode, for otherwise
7574 * the hw state checker will get angry at the mismatch. */
7575 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7576 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7578 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7579 /* the chip adds 2 halflines automatically */
7581 crtc_vblank_end
-= 1;
7583 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7584 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7586 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7587 adjusted_mode
->crtc_htotal
/ 2;
7589 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7592 if (INTEL_INFO(dev
)->gen
> 3)
7593 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7595 I915_WRITE(HTOTAL(cpu_transcoder
),
7596 (adjusted_mode
->crtc_hdisplay
- 1) |
7597 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7598 I915_WRITE(HBLANK(cpu_transcoder
),
7599 (adjusted_mode
->crtc_hblank_start
- 1) |
7600 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7601 I915_WRITE(HSYNC(cpu_transcoder
),
7602 (adjusted_mode
->crtc_hsync_start
- 1) |
7603 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7605 I915_WRITE(VTOTAL(cpu_transcoder
),
7606 (adjusted_mode
->crtc_vdisplay
- 1) |
7607 ((crtc_vtotal
- 1) << 16));
7608 I915_WRITE(VBLANK(cpu_transcoder
),
7609 (adjusted_mode
->crtc_vblank_start
- 1) |
7610 ((crtc_vblank_end
- 1) << 16));
7611 I915_WRITE(VSYNC(cpu_transcoder
),
7612 (adjusted_mode
->crtc_vsync_start
- 1) |
7613 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7615 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7616 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7617 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7619 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7620 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7621 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7625 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
)
7627 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7629 enum pipe pipe
= intel_crtc
->pipe
;
7631 /* pipesrc controls the size that is scaled from, which should
7632 * always be the user's requested size.
7634 I915_WRITE(PIPESRC(pipe
),
7635 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7636 (intel_crtc
->config
->pipe_src_h
- 1));
7639 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7640 struct intel_crtc_state
*pipe_config
)
7642 struct drm_device
*dev
= crtc
->base
.dev
;
7643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7644 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7647 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7648 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7649 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7650 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7651 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7652 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7653 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7654 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7655 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7657 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7658 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7659 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7660 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7661 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7662 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7663 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7664 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7665 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7667 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7668 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7669 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7670 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7674 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
7675 struct intel_crtc_state
*pipe_config
)
7677 struct drm_device
*dev
= crtc
->base
.dev
;
7678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7681 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7682 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7683 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7685 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7686 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7689 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7690 struct intel_crtc_state
*pipe_config
)
7692 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7693 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7694 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7695 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7697 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7698 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7699 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7700 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7702 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7703 mode
->type
= DRM_MODE_TYPE_DRIVER
;
7705 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7706 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7708 mode
->hsync
= drm_mode_hsync(mode
);
7709 mode
->vrefresh
= drm_mode_vrefresh(mode
);
7710 drm_mode_set_name(mode
);
7713 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7715 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7721 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7722 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7723 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7725 if (intel_crtc
->config
->double_wide
)
7726 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7728 /* only g4x and later have fancy bpc/dither controls */
7729 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
7730 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7731 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7732 pipeconf
|= PIPECONF_DITHER_EN
|
7733 PIPECONF_DITHER_TYPE_SP
;
7735 switch (intel_crtc
->config
->pipe_bpp
) {
7737 pipeconf
|= PIPECONF_6BPC
;
7740 pipeconf
|= PIPECONF_8BPC
;
7743 pipeconf
|= PIPECONF_10BPC
;
7746 /* Case prevented by intel_choose_pipe_bpp_dither. */
7751 if (HAS_PIPE_CXSR(dev
)) {
7752 if (intel_crtc
->lowfreq_avail
) {
7753 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7754 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7756 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7760 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7761 if (INTEL_INFO(dev
)->gen
< 4 ||
7762 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7763 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7765 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7767 pipeconf
|= PIPECONF_PROGRESSIVE
;
7769 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
7770 intel_crtc
->config
->limited_color_range
)
7771 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7773 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7774 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7777 static int i8xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7778 struct intel_crtc_state
*crtc_state
)
7780 struct drm_device
*dev
= crtc
->base
.dev
;
7781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7782 const intel_limit_t
*limit
;
7785 memset(&crtc_state
->dpll_hw_state
, 0,
7786 sizeof(crtc_state
->dpll_hw_state
));
7788 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7789 if (intel_panel_use_ssc(dev_priv
)) {
7790 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7791 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7794 limit
= &intel_limits_i8xx_lvds
;
7795 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
)) {
7796 limit
= &intel_limits_i8xx_dvo
;
7798 limit
= &intel_limits_i8xx_dac
;
7801 if (!crtc_state
->clock_set
&&
7802 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7803 refclk
, NULL
, &crtc_state
->dpll
)) {
7804 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7808 i8xx_compute_dpll(crtc
, crtc_state
, NULL
);
7813 static int g4x_crtc_compute_clock(struct intel_crtc
*crtc
,
7814 struct intel_crtc_state
*crtc_state
)
7816 struct drm_device
*dev
= crtc
->base
.dev
;
7817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7818 const intel_limit_t
*limit
;
7821 memset(&crtc_state
->dpll_hw_state
, 0,
7822 sizeof(crtc_state
->dpll_hw_state
));
7824 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7825 if (intel_panel_use_ssc(dev_priv
)) {
7826 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7827 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7830 if (intel_is_dual_link_lvds(dev
))
7831 limit
= &intel_limits_g4x_dual_channel_lvds
;
7833 limit
= &intel_limits_g4x_single_channel_lvds
;
7834 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
7835 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
7836 limit
= &intel_limits_g4x_hdmi
;
7837 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
7838 limit
= &intel_limits_g4x_sdvo
;
7840 /* The option is for other outputs */
7841 limit
= &intel_limits_i9xx_sdvo
;
7844 if (!crtc_state
->clock_set
&&
7845 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7846 refclk
, NULL
, &crtc_state
->dpll
)) {
7847 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7851 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7856 static int pnv_crtc_compute_clock(struct intel_crtc
*crtc
,
7857 struct intel_crtc_state
*crtc_state
)
7859 struct drm_device
*dev
= crtc
->base
.dev
;
7860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7861 const intel_limit_t
*limit
;
7864 memset(&crtc_state
->dpll_hw_state
, 0,
7865 sizeof(crtc_state
->dpll_hw_state
));
7867 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7868 if (intel_panel_use_ssc(dev_priv
)) {
7869 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7870 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7873 limit
= &intel_limits_pineview_lvds
;
7875 limit
= &intel_limits_pineview_sdvo
;
7878 if (!crtc_state
->clock_set
&&
7879 !pnv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7880 refclk
, NULL
, &crtc_state
->dpll
)) {
7881 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7885 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7890 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7891 struct intel_crtc_state
*crtc_state
)
7893 struct drm_device
*dev
= crtc
->base
.dev
;
7894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7895 const intel_limit_t
*limit
;
7898 memset(&crtc_state
->dpll_hw_state
, 0,
7899 sizeof(crtc_state
->dpll_hw_state
));
7901 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7902 if (intel_panel_use_ssc(dev_priv
)) {
7903 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7904 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7907 limit
= &intel_limits_i9xx_lvds
;
7909 limit
= &intel_limits_i9xx_sdvo
;
7912 if (!crtc_state
->clock_set
&&
7913 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7914 refclk
, NULL
, &crtc_state
->dpll
)) {
7915 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7919 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7924 static int chv_crtc_compute_clock(struct intel_crtc
*crtc
,
7925 struct intel_crtc_state
*crtc_state
)
7927 int refclk
= 100000;
7928 const intel_limit_t
*limit
= &intel_limits_chv
;
7930 memset(&crtc_state
->dpll_hw_state
, 0,
7931 sizeof(crtc_state
->dpll_hw_state
));
7933 if (crtc_state
->has_dsi_encoder
)
7936 if (!crtc_state
->clock_set
&&
7937 !chv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7938 refclk
, NULL
, &crtc_state
->dpll
)) {
7939 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7943 chv_compute_dpll(crtc
, crtc_state
);
7948 static int vlv_crtc_compute_clock(struct intel_crtc
*crtc
,
7949 struct intel_crtc_state
*crtc_state
)
7951 int refclk
= 100000;
7952 const intel_limit_t
*limit
= &intel_limits_vlv
;
7954 memset(&crtc_state
->dpll_hw_state
, 0,
7955 sizeof(crtc_state
->dpll_hw_state
));
7957 if (crtc_state
->has_dsi_encoder
)
7960 if (!crtc_state
->clock_set
&&
7961 !vlv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7962 refclk
, NULL
, &crtc_state
->dpll
)) {
7963 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7967 vlv_compute_dpll(crtc
, crtc_state
);
7972 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7973 struct intel_crtc_state
*pipe_config
)
7975 struct drm_device
*dev
= crtc
->base
.dev
;
7976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7979 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
7982 tmp
= I915_READ(PFIT_CONTROL
);
7983 if (!(tmp
& PFIT_ENABLE
))
7986 /* Check whether the pfit is attached to our pipe. */
7987 if (INTEL_INFO(dev
)->gen
< 4) {
7988 if (crtc
->pipe
!= PIPE_B
)
7991 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
7995 pipe_config
->gmch_pfit
.control
= tmp
;
7996 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
7997 if (INTEL_INFO(dev
)->gen
< 5)
7998 pipe_config
->gmch_pfit
.lvds_border_bits
=
7999 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
8002 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
8003 struct intel_crtc_state
*pipe_config
)
8005 struct drm_device
*dev
= crtc
->base
.dev
;
8006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8007 int pipe
= pipe_config
->cpu_transcoder
;
8008 intel_clock_t clock
;
8010 int refclk
= 100000;
8012 /* In case of MIPI DPLL will not even be used */
8013 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
8016 mutex_lock(&dev_priv
->sb_lock
);
8017 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8018 mutex_unlock(&dev_priv
->sb_lock
);
8020 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8021 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8022 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8023 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8024 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8026 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
8030 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8031 struct intel_initial_plane_config
*plane_config
)
8033 struct drm_device
*dev
= crtc
->base
.dev
;
8034 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8035 u32 val
, base
, offset
;
8036 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
8037 int fourcc
, pixel_format
;
8038 unsigned int aligned_height
;
8039 struct drm_framebuffer
*fb
;
8040 struct intel_framebuffer
*intel_fb
;
8042 val
= I915_READ(DSPCNTR(plane
));
8043 if (!(val
& DISPLAY_PLANE_ENABLE
))
8046 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8048 DRM_DEBUG_KMS("failed to alloc fb\n");
8052 fb
= &intel_fb
->base
;
8054 if (INTEL_INFO(dev
)->gen
>= 4) {
8055 if (val
& DISPPLANE_TILED
) {
8056 plane_config
->tiling
= I915_TILING_X
;
8057 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8061 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8062 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8063 fb
->pixel_format
= fourcc
;
8064 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8066 if (INTEL_INFO(dev
)->gen
>= 4) {
8067 if (plane_config
->tiling
)
8068 offset
= I915_READ(DSPTILEOFF(plane
));
8070 offset
= I915_READ(DSPLINOFF(plane
));
8071 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
8073 base
= I915_READ(DSPADDR(plane
));
8075 plane_config
->base
= base
;
8077 val
= I915_READ(PIPESRC(pipe
));
8078 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8079 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8081 val
= I915_READ(DSPSTRIDE(pipe
));
8082 fb
->pitches
[0] = val
& 0xffffffc0;
8084 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8088 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8090 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8091 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
8092 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8093 plane_config
->size
);
8095 plane_config
->fb
= intel_fb
;
8098 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8099 struct intel_crtc_state
*pipe_config
)
8101 struct drm_device
*dev
= crtc
->base
.dev
;
8102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8103 int pipe
= pipe_config
->cpu_transcoder
;
8104 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8105 intel_clock_t clock
;
8106 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
8107 int refclk
= 100000;
8109 mutex_lock(&dev_priv
->sb_lock
);
8110 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8111 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8112 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8113 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8114 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8115 mutex_unlock(&dev_priv
->sb_lock
);
8117 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8118 clock
.m2
= (pll_dw0
& 0xff) << 22;
8119 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
8120 clock
.m2
|= pll_dw2
& 0x3fffff;
8121 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8122 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8123 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8125 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8128 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8129 struct intel_crtc_state
*pipe_config
)
8131 struct drm_device
*dev
= crtc
->base
.dev
;
8132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8133 enum intel_display_power_domain power_domain
;
8137 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
8138 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
8141 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8142 pipe_config
->shared_dpll
= NULL
;
8146 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8147 if (!(tmp
& PIPECONF_ENABLE
))
8150 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
8151 switch (tmp
& PIPECONF_BPC_MASK
) {
8153 pipe_config
->pipe_bpp
= 18;
8156 pipe_config
->pipe_bpp
= 24;
8158 case PIPECONF_10BPC
:
8159 pipe_config
->pipe_bpp
= 30;
8166 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
8167 (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8168 pipe_config
->limited_color_range
= true;
8170 if (INTEL_INFO(dev
)->gen
< 4)
8171 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8173 intel_get_pipe_timings(crtc
, pipe_config
);
8174 intel_get_pipe_src_size(crtc
, pipe_config
);
8176 i9xx_get_pfit_config(crtc
, pipe_config
);
8178 if (INTEL_INFO(dev
)->gen
>= 4) {
8179 /* No way to read it out on pipes B and C */
8180 if (IS_CHERRYVIEW(dev
) && crtc
->pipe
!= PIPE_A
)
8181 tmp
= dev_priv
->chv_dpll_md
[crtc
->pipe
];
8183 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8184 pipe_config
->pixel_multiplier
=
8185 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8186 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8187 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8188 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
8189 tmp
= I915_READ(DPLL(crtc
->pipe
));
8190 pipe_config
->pixel_multiplier
=
8191 ((tmp
& SDVO_MULTIPLIER_MASK
)
8192 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8194 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8195 * port and will be fixed up in the encoder->get_config
8197 pipe_config
->pixel_multiplier
= 1;
8199 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8200 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
8202 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8203 * on 830. Filter it out here so that we don't
8204 * report errors due to that.
8207 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
8209 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8210 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8212 /* Mask out read-only status bits. */
8213 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8214 DPLL_PORTC_READY_MASK
|
8215 DPLL_PORTB_READY_MASK
);
8218 if (IS_CHERRYVIEW(dev
))
8219 chv_crtc_clock_get(crtc
, pipe_config
);
8220 else if (IS_VALLEYVIEW(dev
))
8221 vlv_crtc_clock_get(crtc
, pipe_config
);
8223 i9xx_crtc_clock_get(crtc
, pipe_config
);
8226 * Normally the dotclock is filled in by the encoder .get_config()
8227 * but in case the pipe is enabled w/o any ports we need a sane
8230 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8231 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8236 intel_display_power_put(dev_priv
, power_domain
);
8241 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
8243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8244 struct intel_encoder
*encoder
;
8246 bool has_lvds
= false;
8247 bool has_cpu_edp
= false;
8248 bool has_panel
= false;
8249 bool has_ck505
= false;
8250 bool can_ssc
= false;
8252 /* We need to take the global config into account */
8253 for_each_intel_encoder(dev
, encoder
) {
8254 switch (encoder
->type
) {
8255 case INTEL_OUTPUT_LVDS
:
8259 case INTEL_OUTPUT_EDP
:
8261 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
8269 if (HAS_PCH_IBX(dev
)) {
8270 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8271 can_ssc
= has_ck505
;
8277 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8278 has_panel
, has_lvds
, has_ck505
);
8280 /* Ironlake: try to setup display ref clock before DPLL
8281 * enabling. This is only under driver's control after
8282 * PCH B stepping, previous chipset stepping should be
8283 * ignoring this setting.
8285 val
= I915_READ(PCH_DREF_CONTROL
);
8287 /* As we must carefully and slowly disable/enable each source in turn,
8288 * compute the final state we want first and check if we need to
8289 * make any changes at all.
8292 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8294 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8296 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8298 final
&= ~DREF_SSC_SOURCE_MASK
;
8299 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8300 final
&= ~DREF_SSC1_ENABLE
;
8303 final
|= DREF_SSC_SOURCE_ENABLE
;
8305 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8306 final
|= DREF_SSC1_ENABLE
;
8309 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8310 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8312 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8314 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8316 final
|= DREF_SSC_SOURCE_DISABLE
;
8317 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8323 /* Always enable nonspread source */
8324 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8327 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8329 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8332 val
&= ~DREF_SSC_SOURCE_MASK
;
8333 val
|= DREF_SSC_SOURCE_ENABLE
;
8335 /* SSC must be turned on before enabling the CPU output */
8336 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8337 DRM_DEBUG_KMS("Using SSC on panel\n");
8338 val
|= DREF_SSC1_ENABLE
;
8340 val
&= ~DREF_SSC1_ENABLE
;
8342 /* Get SSC going before enabling the outputs */
8343 I915_WRITE(PCH_DREF_CONTROL
, val
);
8344 POSTING_READ(PCH_DREF_CONTROL
);
8347 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8349 /* Enable CPU source on CPU attached eDP */
8351 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8352 DRM_DEBUG_KMS("Using SSC on eDP\n");
8353 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8355 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8357 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8359 I915_WRITE(PCH_DREF_CONTROL
, val
);
8360 POSTING_READ(PCH_DREF_CONTROL
);
8363 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8365 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8367 /* Turn off CPU output */
8368 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8370 I915_WRITE(PCH_DREF_CONTROL
, val
);
8371 POSTING_READ(PCH_DREF_CONTROL
);
8374 /* Turn off the SSC source */
8375 val
&= ~DREF_SSC_SOURCE_MASK
;
8376 val
|= DREF_SSC_SOURCE_DISABLE
;
8379 val
&= ~DREF_SSC1_ENABLE
;
8381 I915_WRITE(PCH_DREF_CONTROL
, val
);
8382 POSTING_READ(PCH_DREF_CONTROL
);
8386 BUG_ON(val
!= final
);
8389 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8393 tmp
= I915_READ(SOUTH_CHICKEN2
);
8394 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8395 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8397 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
8398 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8399 DRM_ERROR("FDI mPHY reset assert timeout\n");
8401 tmp
= I915_READ(SOUTH_CHICKEN2
);
8402 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8403 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8405 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
8406 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8407 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8410 /* WaMPhyProgramming:hsw */
8411 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8415 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8416 tmp
&= ~(0xFF << 24);
8417 tmp
|= (0x12 << 24);
8418 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8420 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8422 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8424 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8426 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8428 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8429 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8430 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8432 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8433 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8434 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8436 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8439 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8441 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8444 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8446 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8449 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8451 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8454 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8456 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8457 tmp
&= ~(0xFF << 16);
8458 tmp
|= (0x1C << 16);
8459 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8461 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8462 tmp
&= ~(0xFF << 16);
8463 tmp
|= (0x1C << 16);
8464 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8466 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8468 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8470 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8472 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8474 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8475 tmp
&= ~(0xF << 28);
8477 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8479 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8480 tmp
&= ~(0xF << 28);
8482 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8485 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8486 * Programming" based on the parameters passed:
8487 * - Sequence to enable CLKOUT_DP
8488 * - Sequence to enable CLKOUT_DP without spread
8489 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8491 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8497 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8499 if (WARN(HAS_PCH_LPT_LP(dev
) && with_fdi
, "LP PCH doesn't have FDI\n"))
8502 mutex_lock(&dev_priv
->sb_lock
);
8504 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8505 tmp
&= ~SBI_SSCCTL_DISABLE
;
8506 tmp
|= SBI_SSCCTL_PATHALT
;
8507 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8512 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8513 tmp
&= ~SBI_SSCCTL_PATHALT
;
8514 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8517 lpt_reset_fdi_mphy(dev_priv
);
8518 lpt_program_fdi_mphy(dev_priv
);
8522 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8523 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8524 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8525 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8527 mutex_unlock(&dev_priv
->sb_lock
);
8530 /* Sequence to disable CLKOUT_DP */
8531 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8536 mutex_lock(&dev_priv
->sb_lock
);
8538 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8539 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8540 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8541 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8543 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8544 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8545 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8546 tmp
|= SBI_SSCCTL_PATHALT
;
8547 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8550 tmp
|= SBI_SSCCTL_DISABLE
;
8551 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8554 mutex_unlock(&dev_priv
->sb_lock
);
8557 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8559 static const uint16_t sscdivintphase
[] = {
8560 [BEND_IDX( 50)] = 0x3B23,
8561 [BEND_IDX( 45)] = 0x3B23,
8562 [BEND_IDX( 40)] = 0x3C23,
8563 [BEND_IDX( 35)] = 0x3C23,
8564 [BEND_IDX( 30)] = 0x3D23,
8565 [BEND_IDX( 25)] = 0x3D23,
8566 [BEND_IDX( 20)] = 0x3E23,
8567 [BEND_IDX( 15)] = 0x3E23,
8568 [BEND_IDX( 10)] = 0x3F23,
8569 [BEND_IDX( 5)] = 0x3F23,
8570 [BEND_IDX( 0)] = 0x0025,
8571 [BEND_IDX( -5)] = 0x0025,
8572 [BEND_IDX(-10)] = 0x0125,
8573 [BEND_IDX(-15)] = 0x0125,
8574 [BEND_IDX(-20)] = 0x0225,
8575 [BEND_IDX(-25)] = 0x0225,
8576 [BEND_IDX(-30)] = 0x0325,
8577 [BEND_IDX(-35)] = 0x0325,
8578 [BEND_IDX(-40)] = 0x0425,
8579 [BEND_IDX(-45)] = 0x0425,
8580 [BEND_IDX(-50)] = 0x0525,
8585 * steps -50 to 50 inclusive, in steps of 5
8586 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8587 * change in clock period = -(steps / 10) * 5.787 ps
8589 static void lpt_bend_clkout_dp(struct drm_i915_private
*dev_priv
, int steps
)
8592 int idx
= BEND_IDX(steps
);
8594 if (WARN_ON(steps
% 5 != 0))
8597 if (WARN_ON(idx
>= ARRAY_SIZE(sscdivintphase
)))
8600 mutex_lock(&dev_priv
->sb_lock
);
8602 if (steps
% 10 != 0)
8606 intel_sbi_write(dev_priv
, SBI_SSCDITHPHASE
, tmp
, SBI_ICLK
);
8608 tmp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE
, SBI_ICLK
);
8610 tmp
|= sscdivintphase
[idx
];
8611 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE
, tmp
, SBI_ICLK
);
8613 mutex_unlock(&dev_priv
->sb_lock
);
8618 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8620 struct intel_encoder
*encoder
;
8621 bool has_vga
= false;
8623 for_each_intel_encoder(dev
, encoder
) {
8624 switch (encoder
->type
) {
8625 case INTEL_OUTPUT_ANALOG
:
8634 lpt_bend_clkout_dp(to_i915(dev
), 0);
8635 lpt_enable_clkout_dp(dev
, true, true);
8637 lpt_disable_clkout_dp(dev
);
8642 * Initialize reference clocks when the driver loads
8644 void intel_init_pch_refclk(struct drm_device
*dev
)
8646 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8647 ironlake_init_pch_refclk(dev
);
8648 else if (HAS_PCH_LPT(dev
))
8649 lpt_init_pch_refclk(dev
);
8652 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8654 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8655 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8656 int pipe
= intel_crtc
->pipe
;
8661 switch (intel_crtc
->config
->pipe_bpp
) {
8663 val
|= PIPECONF_6BPC
;
8666 val
|= PIPECONF_8BPC
;
8669 val
|= PIPECONF_10BPC
;
8672 val
|= PIPECONF_12BPC
;
8675 /* Case prevented by intel_choose_pipe_bpp_dither. */
8679 if (intel_crtc
->config
->dither
)
8680 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8682 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8683 val
|= PIPECONF_INTERLACED_ILK
;
8685 val
|= PIPECONF_PROGRESSIVE
;
8687 if (intel_crtc
->config
->limited_color_range
)
8688 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8690 I915_WRITE(PIPECONF(pipe
), val
);
8691 POSTING_READ(PIPECONF(pipe
));
8694 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8696 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8697 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8698 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8701 if (IS_HASWELL(dev_priv
) && intel_crtc
->config
->dither
)
8702 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8704 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8705 val
|= PIPECONF_INTERLACED_ILK
;
8707 val
|= PIPECONF_PROGRESSIVE
;
8709 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8710 POSTING_READ(PIPECONF(cpu_transcoder
));
8713 static void haswell_set_pipemisc(struct drm_crtc
*crtc
)
8715 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8716 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8718 if (IS_BROADWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 9) {
8721 switch (intel_crtc
->config
->pipe_bpp
) {
8723 val
|= PIPEMISC_DITHER_6_BPC
;
8726 val
|= PIPEMISC_DITHER_8_BPC
;
8729 val
|= PIPEMISC_DITHER_10_BPC
;
8732 val
|= PIPEMISC_DITHER_12_BPC
;
8735 /* Case prevented by pipe_config_set_bpp. */
8739 if (intel_crtc
->config
->dither
)
8740 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8742 I915_WRITE(PIPEMISC(intel_crtc
->pipe
), val
);
8746 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8749 * Account for spread spectrum to avoid
8750 * oversubscribing the link. Max center spread
8751 * is 2.5%; use 5% for safety's sake.
8753 u32 bps
= target_clock
* bpp
* 21 / 20;
8754 return DIV_ROUND_UP(bps
, link_bw
* 8);
8757 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8759 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8762 static void ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8763 struct intel_crtc_state
*crtc_state
,
8764 intel_clock_t
*reduced_clock
)
8766 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8767 struct drm_device
*dev
= crtc
->dev
;
8768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8769 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8770 struct drm_connector
*connector
;
8771 struct drm_connector_state
*connector_state
;
8772 struct intel_encoder
*encoder
;
8775 bool is_lvds
= false, is_sdvo
= false;
8777 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8778 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8781 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8783 switch (encoder
->type
) {
8784 case INTEL_OUTPUT_LVDS
:
8787 case INTEL_OUTPUT_SDVO
:
8788 case INTEL_OUTPUT_HDMI
:
8796 /* Enable autotuning of the PLL clock (if permissible) */
8799 if ((intel_panel_use_ssc(dev_priv
) &&
8800 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8801 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8803 } else if (crtc_state
->sdvo_tv_clock
)
8806 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8808 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8811 if (reduced_clock
) {
8812 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
8814 if (reduced_clock
->m
< factor
* reduced_clock
->n
)
8823 dpll
|= DPLLB_MODE_LVDS
;
8825 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8827 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8828 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8831 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8832 if (crtc_state
->has_dp_encoder
)
8833 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8835 /* compute bitmask from p1 value */
8836 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8838 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8840 switch (crtc_state
->dpll
.p2
) {
8842 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8845 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8848 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8851 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8855 if (is_lvds
&& intel_panel_use_ssc(dev_priv
))
8856 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8858 dpll
|= PLL_REF_INPUT_DREFCLK
;
8860 dpll
|= DPLL_VCO_ENABLE
;
8862 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8863 crtc_state
->dpll_hw_state
.fp0
= fp
;
8864 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8867 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8868 struct intel_crtc_state
*crtc_state
)
8870 struct drm_device
*dev
= crtc
->base
.dev
;
8871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8872 intel_clock_t reduced_clock
;
8873 bool has_reduced_clock
= false;
8874 struct intel_shared_dpll
*pll
;
8875 const intel_limit_t
*limit
;
8876 int refclk
= 120000;
8878 memset(&crtc_state
->dpll_hw_state
, 0,
8879 sizeof(crtc_state
->dpll_hw_state
));
8881 crtc
->lowfreq_avail
= false;
8883 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8884 if (!crtc_state
->has_pch_encoder
)
8887 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8888 if (intel_panel_use_ssc(dev_priv
)) {
8889 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8890 dev_priv
->vbt
.lvds_ssc_freq
);
8891 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8894 if (intel_is_dual_link_lvds(dev
)) {
8895 if (refclk
== 100000)
8896 limit
= &intel_limits_ironlake_dual_lvds_100m
;
8898 limit
= &intel_limits_ironlake_dual_lvds
;
8900 if (refclk
== 100000)
8901 limit
= &intel_limits_ironlake_single_lvds_100m
;
8903 limit
= &intel_limits_ironlake_single_lvds
;
8906 limit
= &intel_limits_ironlake_dac
;
8909 if (!crtc_state
->clock_set
&&
8910 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8911 refclk
, NULL
, &crtc_state
->dpll
)) {
8912 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8916 ironlake_compute_dpll(crtc
, crtc_state
,
8917 has_reduced_clock
? &reduced_clock
: NULL
);
8919 pll
= intel_get_shared_dpll(crtc
, crtc_state
, NULL
);
8921 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8922 pipe_name(crtc
->pipe
));
8926 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
8928 crtc
->lowfreq_avail
= true;
8933 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
8934 struct intel_link_m_n
*m_n
)
8936 struct drm_device
*dev
= crtc
->base
.dev
;
8937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8938 enum pipe pipe
= crtc
->pipe
;
8940 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
8941 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
8942 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
8944 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
8945 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
8946 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8949 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
8950 enum transcoder transcoder
,
8951 struct intel_link_m_n
*m_n
,
8952 struct intel_link_m_n
*m2_n2
)
8954 struct drm_device
*dev
= crtc
->base
.dev
;
8955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8956 enum pipe pipe
= crtc
->pipe
;
8958 if (INTEL_INFO(dev
)->gen
>= 5) {
8959 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8960 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8961 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8963 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8964 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8965 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8966 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8967 * gen < 8) and if DRRS is supported (to make sure the
8968 * registers are not unnecessarily read).
8970 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
8971 crtc
->config
->has_drrs
) {
8972 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
8973 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
8974 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
8976 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
8977 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
8978 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8981 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
8982 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
8983 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
8985 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
8986 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
8987 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8991 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
8992 struct intel_crtc_state
*pipe_config
)
8994 if (pipe_config
->has_pch_encoder
)
8995 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
8997 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8998 &pipe_config
->dp_m_n
,
8999 &pipe_config
->dp_m2_n2
);
9002 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9003 struct intel_crtc_state
*pipe_config
)
9005 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9006 &pipe_config
->fdi_m_n
, NULL
);
9009 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9010 struct intel_crtc_state
*pipe_config
)
9012 struct drm_device
*dev
= crtc
->base
.dev
;
9013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9014 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9015 uint32_t ps_ctrl
= 0;
9019 /* find scaler attached to this pipe */
9020 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9021 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9022 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9024 pipe_config
->pch_pfit
.enabled
= true;
9025 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9026 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9031 scaler_state
->scaler_id
= id
;
9033 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9035 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9040 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9041 struct intel_initial_plane_config
*plane_config
)
9043 struct drm_device
*dev
= crtc
->base
.dev
;
9044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9045 u32 val
, base
, offset
, stride_mult
, tiling
;
9046 int pipe
= crtc
->pipe
;
9047 int fourcc
, pixel_format
;
9048 unsigned int aligned_height
;
9049 struct drm_framebuffer
*fb
;
9050 struct intel_framebuffer
*intel_fb
;
9052 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9054 DRM_DEBUG_KMS("failed to alloc fb\n");
9058 fb
= &intel_fb
->base
;
9060 val
= I915_READ(PLANE_CTL(pipe
, 0));
9061 if (!(val
& PLANE_CTL_ENABLE
))
9064 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9065 fourcc
= skl_format_to_fourcc(pixel_format
,
9066 val
& PLANE_CTL_ORDER_RGBX
,
9067 val
& PLANE_CTL_ALPHA_MASK
);
9068 fb
->pixel_format
= fourcc
;
9069 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9071 tiling
= val
& PLANE_CTL_TILED_MASK
;
9073 case PLANE_CTL_TILED_LINEAR
:
9074 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
9076 case PLANE_CTL_TILED_X
:
9077 plane_config
->tiling
= I915_TILING_X
;
9078 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9080 case PLANE_CTL_TILED_Y
:
9081 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
9083 case PLANE_CTL_TILED_YF
:
9084 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
9087 MISSING_CASE(tiling
);
9091 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
9092 plane_config
->base
= base
;
9094 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
9096 val
= I915_READ(PLANE_SIZE(pipe
, 0));
9097 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9098 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9100 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
9101 stride_mult
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
9103 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9105 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9109 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9111 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9112 pipe_name(pipe
), fb
->width
, fb
->height
,
9113 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9114 plane_config
->size
);
9116 plane_config
->fb
= intel_fb
;
9123 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9124 struct intel_crtc_state
*pipe_config
)
9126 struct drm_device
*dev
= crtc
->base
.dev
;
9127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9130 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9132 if (tmp
& PF_ENABLE
) {
9133 pipe_config
->pch_pfit
.enabled
= true;
9134 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9135 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9137 /* We currently do not free assignements of panel fitters on
9138 * ivb/hsw (since we don't use the higher upscaling modes which
9139 * differentiates them) so just WARN about this case for now. */
9141 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9142 PF_PIPE_SEL_IVB(crtc
->pipe
));
9148 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
9149 struct intel_initial_plane_config
*plane_config
)
9151 struct drm_device
*dev
= crtc
->base
.dev
;
9152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9153 u32 val
, base
, offset
;
9154 int pipe
= crtc
->pipe
;
9155 int fourcc
, pixel_format
;
9156 unsigned int aligned_height
;
9157 struct drm_framebuffer
*fb
;
9158 struct intel_framebuffer
*intel_fb
;
9160 val
= I915_READ(DSPCNTR(pipe
));
9161 if (!(val
& DISPLAY_PLANE_ENABLE
))
9164 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9166 DRM_DEBUG_KMS("failed to alloc fb\n");
9170 fb
= &intel_fb
->base
;
9172 if (INTEL_INFO(dev
)->gen
>= 4) {
9173 if (val
& DISPPLANE_TILED
) {
9174 plane_config
->tiling
= I915_TILING_X
;
9175 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9179 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
9180 fourcc
= i9xx_format_to_fourcc(pixel_format
);
9181 fb
->pixel_format
= fourcc
;
9182 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9184 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
9185 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
9186 offset
= I915_READ(DSPOFFSET(pipe
));
9188 if (plane_config
->tiling
)
9189 offset
= I915_READ(DSPTILEOFF(pipe
));
9191 offset
= I915_READ(DSPLINOFF(pipe
));
9193 plane_config
->base
= base
;
9195 val
= I915_READ(PIPESRC(pipe
));
9196 fb
->width
= ((val
>> 16) & 0xfff) + 1;
9197 fb
->height
= ((val
>> 0) & 0xfff) + 1;
9199 val
= I915_READ(DSPSTRIDE(pipe
));
9200 fb
->pitches
[0] = val
& 0xffffffc0;
9202 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9206 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9208 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9209 pipe_name(pipe
), fb
->width
, fb
->height
,
9210 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9211 plane_config
->size
);
9213 plane_config
->fb
= intel_fb
;
9216 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9217 struct intel_crtc_state
*pipe_config
)
9219 struct drm_device
*dev
= crtc
->base
.dev
;
9220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9221 enum intel_display_power_domain power_domain
;
9225 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9226 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9229 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9230 pipe_config
->shared_dpll
= NULL
;
9233 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9234 if (!(tmp
& PIPECONF_ENABLE
))
9237 switch (tmp
& PIPECONF_BPC_MASK
) {
9239 pipe_config
->pipe_bpp
= 18;
9242 pipe_config
->pipe_bpp
= 24;
9244 case PIPECONF_10BPC
:
9245 pipe_config
->pipe_bpp
= 30;
9247 case PIPECONF_12BPC
:
9248 pipe_config
->pipe_bpp
= 36;
9254 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9255 pipe_config
->limited_color_range
= true;
9257 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9258 struct intel_shared_dpll
*pll
;
9259 enum intel_dpll_id pll_id
;
9261 pipe_config
->has_pch_encoder
= true;
9263 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9264 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9265 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9267 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9269 if (HAS_PCH_IBX(dev_priv
)) {
9270 pll_id
= (enum intel_dpll_id
) crtc
->pipe
;
9272 tmp
= I915_READ(PCH_DPLL_SEL
);
9273 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9274 pll_id
= DPLL_ID_PCH_PLL_B
;
9276 pll_id
= DPLL_ID_PCH_PLL_A
;
9279 pipe_config
->shared_dpll
=
9280 intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
9281 pll
= pipe_config
->shared_dpll
;
9283 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
9284 &pipe_config
->dpll_hw_state
));
9286 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9287 pipe_config
->pixel_multiplier
=
9288 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9289 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9291 ironlake_pch_clock_get(crtc
, pipe_config
);
9293 pipe_config
->pixel_multiplier
= 1;
9296 intel_get_pipe_timings(crtc
, pipe_config
);
9297 intel_get_pipe_src_size(crtc
, pipe_config
);
9299 ironlake_get_pfit_config(crtc
, pipe_config
);
9304 intel_display_power_put(dev_priv
, power_domain
);
9309 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
9311 struct drm_device
*dev
= dev_priv
->dev
;
9312 struct intel_crtc
*crtc
;
9314 for_each_intel_crtc(dev
, crtc
)
9315 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
9316 pipe_name(crtc
->pipe
));
9318 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
9319 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
9320 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
9321 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
9322 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
9323 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
9324 "CPU PWM1 enabled\n");
9325 if (IS_HASWELL(dev
))
9326 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
9327 "CPU PWM2 enabled\n");
9328 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
9329 "PCH PWM1 enabled\n");
9330 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
9331 "Utility pin enabled\n");
9332 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
9335 * In theory we can still leave IRQs enabled, as long as only the HPD
9336 * interrupts remain enabled. We used to check for that, but since it's
9337 * gen-specific and since we only disable LCPLL after we fully disable
9338 * the interrupts, the check below should be enough.
9340 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
9343 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
9345 struct drm_device
*dev
= dev_priv
->dev
;
9347 if (IS_HASWELL(dev
))
9348 return I915_READ(D_COMP_HSW
);
9350 return I915_READ(D_COMP_BDW
);
9353 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
9355 struct drm_device
*dev
= dev_priv
->dev
;
9357 if (IS_HASWELL(dev
)) {
9358 mutex_lock(&dev_priv
->rps
.hw_lock
);
9359 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
9361 DRM_ERROR("Failed to write to D_COMP\n");
9362 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9364 I915_WRITE(D_COMP_BDW
, val
);
9365 POSTING_READ(D_COMP_BDW
);
9370 * This function implements pieces of two sequences from BSpec:
9371 * - Sequence for display software to disable LCPLL
9372 * - Sequence for display software to allow package C8+
9373 * The steps implemented here are just the steps that actually touch the LCPLL
9374 * register. Callers should take care of disabling all the display engine
9375 * functions, doing the mode unset, fixing interrupts, etc.
9377 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9378 bool switch_to_fclk
, bool allow_power_down
)
9382 assert_can_disable_lcpll(dev_priv
);
9384 val
= I915_READ(LCPLL_CTL
);
9386 if (switch_to_fclk
) {
9387 val
|= LCPLL_CD_SOURCE_FCLK
;
9388 I915_WRITE(LCPLL_CTL
, val
);
9390 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9391 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9392 DRM_ERROR("Switching to FCLK failed\n");
9394 val
= I915_READ(LCPLL_CTL
);
9397 val
|= LCPLL_PLL_DISABLE
;
9398 I915_WRITE(LCPLL_CTL
, val
);
9399 POSTING_READ(LCPLL_CTL
);
9401 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
9402 DRM_ERROR("LCPLL still locked\n");
9404 val
= hsw_read_dcomp(dev_priv
);
9405 val
|= D_COMP_COMP_DISABLE
;
9406 hsw_write_dcomp(dev_priv
, val
);
9409 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9411 DRM_ERROR("D_COMP RCOMP still in progress\n");
9413 if (allow_power_down
) {
9414 val
= I915_READ(LCPLL_CTL
);
9415 val
|= LCPLL_POWER_DOWN_ALLOW
;
9416 I915_WRITE(LCPLL_CTL
, val
);
9417 POSTING_READ(LCPLL_CTL
);
9422 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9425 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9429 val
= I915_READ(LCPLL_CTL
);
9431 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9432 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9436 * Make sure we're not on PC8 state before disabling PC8, otherwise
9437 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9439 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9441 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9442 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9443 I915_WRITE(LCPLL_CTL
, val
);
9444 POSTING_READ(LCPLL_CTL
);
9447 val
= hsw_read_dcomp(dev_priv
);
9448 val
|= D_COMP_COMP_FORCE
;
9449 val
&= ~D_COMP_COMP_DISABLE
;
9450 hsw_write_dcomp(dev_priv
, val
);
9452 val
= I915_READ(LCPLL_CTL
);
9453 val
&= ~LCPLL_PLL_DISABLE
;
9454 I915_WRITE(LCPLL_CTL
, val
);
9456 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
9457 DRM_ERROR("LCPLL not locked yet\n");
9459 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9460 val
= I915_READ(LCPLL_CTL
);
9461 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9462 I915_WRITE(LCPLL_CTL
, val
);
9464 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9465 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9466 DRM_ERROR("Switching back to LCPLL failed\n");
9469 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9470 intel_update_cdclk(dev_priv
->dev
);
9474 * Package states C8 and deeper are really deep PC states that can only be
9475 * reached when all the devices on the system allow it, so even if the graphics
9476 * device allows PC8+, it doesn't mean the system will actually get to these
9477 * states. Our driver only allows PC8+ when going into runtime PM.
9479 * The requirements for PC8+ are that all the outputs are disabled, the power
9480 * well is disabled and most interrupts are disabled, and these are also
9481 * requirements for runtime PM. When these conditions are met, we manually do
9482 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9483 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9486 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9487 * the state of some registers, so when we come back from PC8+ we need to
9488 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9489 * need to take care of the registers kept by RC6. Notice that this happens even
9490 * if we don't put the device in PCI D3 state (which is what currently happens
9491 * because of the runtime PM support).
9493 * For more, read "Display Sequences for Package C8" on the hardware
9496 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9498 struct drm_device
*dev
= dev_priv
->dev
;
9501 DRM_DEBUG_KMS("Enabling package C8+\n");
9503 if (HAS_PCH_LPT_LP(dev
)) {
9504 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9505 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9506 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9509 lpt_disable_clkout_dp(dev
);
9510 hsw_disable_lcpll(dev_priv
, true, true);
9513 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9515 struct drm_device
*dev
= dev_priv
->dev
;
9518 DRM_DEBUG_KMS("Disabling package C8+\n");
9520 hsw_restore_lcpll(dev_priv
);
9521 lpt_init_pch_refclk(dev
);
9523 if (HAS_PCH_LPT_LP(dev
)) {
9524 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9525 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9526 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9530 static void broxton_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9532 struct drm_device
*dev
= old_state
->dev
;
9533 struct intel_atomic_state
*old_intel_state
=
9534 to_intel_atomic_state(old_state
);
9535 unsigned int req_cdclk
= old_intel_state
->dev_cdclk
;
9537 broxton_set_cdclk(dev
, req_cdclk
);
9540 /* compute the max rate for new configuration */
9541 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
)
9543 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
9544 struct drm_i915_private
*dev_priv
= state
->dev
->dev_private
;
9545 struct drm_crtc
*crtc
;
9546 struct drm_crtc_state
*cstate
;
9547 struct intel_crtc_state
*crtc_state
;
9548 unsigned max_pixel_rate
= 0, i
;
9551 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
9552 sizeof(intel_state
->min_pixclk
));
9554 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
9557 crtc_state
= to_intel_crtc_state(cstate
);
9558 if (!crtc_state
->base
.enable
) {
9559 intel_state
->min_pixclk
[i
] = 0;
9563 pixel_rate
= ilk_pipe_pixel_rate(crtc_state
);
9565 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9566 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
9567 pixel_rate
= DIV_ROUND_UP(pixel_rate
* 100, 95);
9569 intel_state
->min_pixclk
[i
] = pixel_rate
;
9572 for_each_pipe(dev_priv
, pipe
)
9573 max_pixel_rate
= max(intel_state
->min_pixclk
[pipe
], max_pixel_rate
);
9575 return max_pixel_rate
;
9578 static void broadwell_set_cdclk(struct drm_device
*dev
, int cdclk
)
9580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9584 if (WARN((I915_READ(LCPLL_CTL
) &
9585 (LCPLL_PLL_DISABLE
| LCPLL_PLL_LOCK
|
9586 LCPLL_CD_CLOCK_DISABLE
| LCPLL_ROOT_CD_CLOCK_DISABLE
|
9587 LCPLL_CD2X_CLOCK_DISABLE
| LCPLL_POWER_DOWN_ALLOW
|
9588 LCPLL_CD_SOURCE_FCLK
)) != LCPLL_PLL_LOCK
,
9589 "trying to change cdclk frequency with cdclk not enabled\n"))
9592 mutex_lock(&dev_priv
->rps
.hw_lock
);
9593 ret
= sandybridge_pcode_write(dev_priv
,
9594 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
, 0x0);
9595 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9597 DRM_ERROR("failed to inform pcode about cdclk change\n");
9601 val
= I915_READ(LCPLL_CTL
);
9602 val
|= LCPLL_CD_SOURCE_FCLK
;
9603 I915_WRITE(LCPLL_CTL
, val
);
9605 if (wait_for_us(I915_READ(LCPLL_CTL
) &
9606 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9607 DRM_ERROR("Switching to FCLK failed\n");
9609 val
= I915_READ(LCPLL_CTL
);
9610 val
&= ~LCPLL_CLK_FREQ_MASK
;
9614 val
|= LCPLL_CLK_FREQ_450
;
9618 val
|= LCPLL_CLK_FREQ_54O_BDW
;
9622 val
|= LCPLL_CLK_FREQ_337_5_BDW
;
9626 val
|= LCPLL_CLK_FREQ_675_BDW
;
9630 WARN(1, "invalid cdclk frequency\n");
9634 I915_WRITE(LCPLL_CTL
, val
);
9636 val
= I915_READ(LCPLL_CTL
);
9637 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9638 I915_WRITE(LCPLL_CTL
, val
);
9640 if (wait_for_us((I915_READ(LCPLL_CTL
) &
9641 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9642 DRM_ERROR("Switching back to LCPLL failed\n");
9644 mutex_lock(&dev_priv
->rps
.hw_lock
);
9645 sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
, data
);
9646 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9648 intel_update_cdclk(dev
);
9650 WARN(cdclk
!= dev_priv
->cdclk_freq
,
9651 "cdclk requested %d kHz but got %d kHz\n",
9652 cdclk
, dev_priv
->cdclk_freq
);
9655 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state
*state
)
9657 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9658 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
9659 int max_pixclk
= ilk_max_pixel_rate(state
);
9663 * FIXME should also account for plane ratio
9664 * once 64bpp pixel formats are supported.
9666 if (max_pixclk
> 540000)
9668 else if (max_pixclk
> 450000)
9670 else if (max_pixclk
> 337500)
9675 if (cdclk
> dev_priv
->max_cdclk_freq
) {
9676 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9677 cdclk
, dev_priv
->max_cdclk_freq
);
9681 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
9682 if (!intel_state
->active_crtcs
)
9683 intel_state
->dev_cdclk
= 337500;
9688 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9690 struct drm_device
*dev
= old_state
->dev
;
9691 struct intel_atomic_state
*old_intel_state
=
9692 to_intel_atomic_state(old_state
);
9693 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
9695 broadwell_set_cdclk(dev
, req_cdclk
);
9698 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9699 struct intel_crtc_state
*crtc_state
)
9701 struct intel_encoder
*intel_encoder
=
9702 intel_ddi_get_crtc_new_encoder(crtc_state
);
9704 if (intel_encoder
->type
!= INTEL_OUTPUT_DSI
) {
9705 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9709 crtc
->lowfreq_avail
= false;
9714 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9716 struct intel_crtc_state
*pipe_config
)
9718 enum intel_dpll_id id
;
9722 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9723 id
= DPLL_ID_SKL_DPLL0
;
9726 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9727 id
= DPLL_ID_SKL_DPLL1
;
9730 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9731 id
= DPLL_ID_SKL_DPLL2
;
9734 DRM_ERROR("Incorrect port type\n");
9738 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9741 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9743 struct intel_crtc_state
*pipe_config
)
9745 enum intel_dpll_id id
;
9748 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9749 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9751 switch (pipe_config
->ddi_pll_sel
) {
9753 id
= DPLL_ID_SKL_DPLL0
;
9756 id
= DPLL_ID_SKL_DPLL1
;
9759 id
= DPLL_ID_SKL_DPLL2
;
9762 id
= DPLL_ID_SKL_DPLL3
;
9765 MISSING_CASE(pipe_config
->ddi_pll_sel
);
9769 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9772 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9774 struct intel_crtc_state
*pipe_config
)
9776 enum intel_dpll_id id
;
9778 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9780 switch (pipe_config
->ddi_pll_sel
) {
9781 case PORT_CLK_SEL_WRPLL1
:
9782 id
= DPLL_ID_WRPLL1
;
9784 case PORT_CLK_SEL_WRPLL2
:
9785 id
= DPLL_ID_WRPLL2
;
9787 case PORT_CLK_SEL_SPLL
:
9790 case PORT_CLK_SEL_LCPLL_810
:
9791 id
= DPLL_ID_LCPLL_810
;
9793 case PORT_CLK_SEL_LCPLL_1350
:
9794 id
= DPLL_ID_LCPLL_1350
;
9796 case PORT_CLK_SEL_LCPLL_2700
:
9797 id
= DPLL_ID_LCPLL_2700
;
9800 MISSING_CASE(pipe_config
->ddi_pll_sel
);
9802 case PORT_CLK_SEL_NONE
:
9806 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9809 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
9810 struct intel_crtc_state
*pipe_config
,
9811 unsigned long *power_domain_mask
)
9813 struct drm_device
*dev
= crtc
->base
.dev
;
9814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9815 enum intel_display_power_domain power_domain
;
9818 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9821 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9822 * consistency and less surprising code; it's in always on power).
9824 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9825 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9826 enum pipe trans_edp_pipe
;
9827 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9829 WARN(1, "unknown pipe linked to edp transcoder\n");
9830 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9831 case TRANS_DDI_EDP_INPUT_A_ON
:
9832 trans_edp_pipe
= PIPE_A
;
9834 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9835 trans_edp_pipe
= PIPE_B
;
9837 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9838 trans_edp_pipe
= PIPE_C
;
9842 if (trans_edp_pipe
== crtc
->pipe
)
9843 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9846 power_domain
= POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
);
9847 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9849 *power_domain_mask
|= BIT(power_domain
);
9851 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9853 return tmp
& PIPECONF_ENABLE
;
9856 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
9857 struct intel_crtc_state
*pipe_config
,
9858 unsigned long *power_domain_mask
)
9860 struct drm_device
*dev
= crtc
->base
.dev
;
9861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9862 enum intel_display_power_domain power_domain
;
9864 enum transcoder cpu_transcoder
;
9867 pipe_config
->has_dsi_encoder
= false;
9869 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
9871 cpu_transcoder
= TRANSCODER_DSI_A
;
9873 cpu_transcoder
= TRANSCODER_DSI_C
;
9875 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
9876 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9878 *power_domain_mask
|= BIT(power_domain
);
9881 * The PLL needs to be enabled with a valid divider
9882 * configuration, otherwise accessing DSI registers will hang
9883 * the machine. See BSpec North Display Engine
9884 * registers/MIPI[BXT]. We can break out here early, since we
9885 * need the same DSI PLL to be enabled for both DSI ports.
9887 if (!intel_dsi_pll_is_enabled(dev_priv
))
9890 /* XXX: this works for video mode only */
9891 tmp
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
9892 if (!(tmp
& DPI_ENABLE
))
9895 tmp
= I915_READ(MIPI_CTRL(port
));
9896 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
9899 pipe_config
->cpu_transcoder
= cpu_transcoder
;
9900 pipe_config
->has_dsi_encoder
= true;
9904 return pipe_config
->has_dsi_encoder
;
9907 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9908 struct intel_crtc_state
*pipe_config
)
9910 struct drm_device
*dev
= crtc
->base
.dev
;
9911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9912 struct intel_shared_dpll
*pll
;
9916 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9918 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9920 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
9921 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9922 else if (IS_BROXTON(dev
))
9923 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9925 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9927 pll
= pipe_config
->shared_dpll
;
9929 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
9930 &pipe_config
->dpll_hw_state
));
9934 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9935 * DDI E. So just check whether this pipe is wired to DDI E and whether
9936 * the PCH transcoder is on.
9938 if (INTEL_INFO(dev
)->gen
< 9 &&
9939 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9940 pipe_config
->has_pch_encoder
= true;
9942 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9943 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9944 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9946 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9950 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9951 struct intel_crtc_state
*pipe_config
)
9953 struct drm_device
*dev
= crtc
->base
.dev
;
9954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9955 enum intel_display_power_domain power_domain
;
9956 unsigned long power_domain_mask
;
9959 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9960 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9962 power_domain_mask
= BIT(power_domain
);
9964 pipe_config
->shared_dpll
= NULL
;
9966 active
= hsw_get_transcoder_state(crtc
, pipe_config
, &power_domain_mask
);
9968 if (IS_BROXTON(dev_priv
)) {
9969 bxt_get_dsi_transcoder_state(crtc
, pipe_config
,
9970 &power_domain_mask
);
9971 WARN_ON(active
&& pipe_config
->has_dsi_encoder
);
9972 if (pipe_config
->has_dsi_encoder
)
9979 if (!pipe_config
->has_dsi_encoder
) {
9980 haswell_get_ddi_port_state(crtc
, pipe_config
);
9981 intel_get_pipe_timings(crtc
, pipe_config
);
9984 intel_get_pipe_src_size(crtc
, pipe_config
);
9986 pipe_config
->gamma_mode
=
9987 I915_READ(GAMMA_MODE(crtc
->pipe
)) & GAMMA_MODE_MODE_MASK
;
9989 if (INTEL_INFO(dev
)->gen
>= 9) {
9990 skl_init_scalers(dev
, crtc
, pipe_config
);
9993 if (INTEL_INFO(dev
)->gen
>= 9) {
9994 pipe_config
->scaler_state
.scaler_id
= -1;
9995 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9998 power_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
9999 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
10000 power_domain_mask
|= BIT(power_domain
);
10001 if (INTEL_INFO(dev
)->gen
>= 9)
10002 skylake_get_pfit_config(crtc
, pipe_config
);
10004 ironlake_get_pfit_config(crtc
, pipe_config
);
10007 if (IS_HASWELL(dev
))
10008 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
10009 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
10011 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
10012 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10013 pipe_config
->pixel_multiplier
=
10014 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
10016 pipe_config
->pixel_multiplier
= 1;
10020 for_each_power_domain(power_domain
, power_domain_mask
)
10021 intel_display_power_put(dev_priv
, power_domain
);
10026 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10027 const struct intel_plane_state
*plane_state
)
10029 struct drm_device
*dev
= crtc
->dev
;
10030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10031 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10032 uint32_t cntl
= 0, size
= 0;
10034 if (plane_state
&& plane_state
->visible
) {
10035 unsigned int width
= plane_state
->base
.crtc_w
;
10036 unsigned int height
= plane_state
->base
.crtc_h
;
10037 unsigned int stride
= roundup_pow_of_two(width
) * 4;
10041 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10052 cntl
|= CURSOR_ENABLE
|
10053 CURSOR_GAMMA_ENABLE
|
10054 CURSOR_FORMAT_ARGB
|
10055 CURSOR_STRIDE(stride
);
10057 size
= (height
<< 12) | width
;
10060 if (intel_crtc
->cursor_cntl
!= 0 &&
10061 (intel_crtc
->cursor_base
!= base
||
10062 intel_crtc
->cursor_size
!= size
||
10063 intel_crtc
->cursor_cntl
!= cntl
)) {
10064 /* On these chipsets we can only modify the base/size/stride
10065 * whilst the cursor is disabled.
10067 I915_WRITE(CURCNTR(PIPE_A
), 0);
10068 POSTING_READ(CURCNTR(PIPE_A
));
10069 intel_crtc
->cursor_cntl
= 0;
10072 if (intel_crtc
->cursor_base
!= base
) {
10073 I915_WRITE(CURBASE(PIPE_A
), base
);
10074 intel_crtc
->cursor_base
= base
;
10077 if (intel_crtc
->cursor_size
!= size
) {
10078 I915_WRITE(CURSIZE
, size
);
10079 intel_crtc
->cursor_size
= size
;
10082 if (intel_crtc
->cursor_cntl
!= cntl
) {
10083 I915_WRITE(CURCNTR(PIPE_A
), cntl
);
10084 POSTING_READ(CURCNTR(PIPE_A
));
10085 intel_crtc
->cursor_cntl
= cntl
;
10089 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10090 const struct intel_plane_state
*plane_state
)
10092 struct drm_device
*dev
= crtc
->dev
;
10093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10094 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10095 int pipe
= intel_crtc
->pipe
;
10098 if (plane_state
&& plane_state
->visible
) {
10099 cntl
= MCURSOR_GAMMA_ENABLE
;
10100 switch (plane_state
->base
.crtc_w
) {
10102 cntl
|= CURSOR_MODE_64_ARGB_AX
;
10105 cntl
|= CURSOR_MODE_128_ARGB_AX
;
10108 cntl
|= CURSOR_MODE_256_ARGB_AX
;
10111 MISSING_CASE(plane_state
->base
.crtc_w
);
10114 cntl
|= pipe
<< 28; /* Connect to correct pipe */
10117 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
10119 if (plane_state
->base
.rotation
== BIT(DRM_ROTATE_180
))
10120 cntl
|= CURSOR_ROTATE_180
;
10123 if (intel_crtc
->cursor_cntl
!= cntl
) {
10124 I915_WRITE(CURCNTR(pipe
), cntl
);
10125 POSTING_READ(CURCNTR(pipe
));
10126 intel_crtc
->cursor_cntl
= cntl
;
10129 /* and commit changes on next vblank */
10130 I915_WRITE(CURBASE(pipe
), base
);
10131 POSTING_READ(CURBASE(pipe
));
10133 intel_crtc
->cursor_base
= base
;
10136 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10137 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
10138 const struct intel_plane_state
*plane_state
)
10140 struct drm_device
*dev
= crtc
->dev
;
10141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10142 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10143 int pipe
= intel_crtc
->pipe
;
10144 u32 base
= intel_crtc
->cursor_addr
;
10148 int x
= plane_state
->base
.crtc_x
;
10149 int y
= plane_state
->base
.crtc_y
;
10152 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10155 pos
|= x
<< CURSOR_X_SHIFT
;
10158 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10161 pos
|= y
<< CURSOR_Y_SHIFT
;
10163 /* ILK+ do this automagically */
10164 if (HAS_GMCH_DISPLAY(dev
) &&
10165 plane_state
->base
.rotation
== BIT(DRM_ROTATE_180
)) {
10166 base
+= (plane_state
->base
.crtc_h
*
10167 plane_state
->base
.crtc_w
- 1) * 4;
10171 I915_WRITE(CURPOS(pipe
), pos
);
10173 if (IS_845G(dev
) || IS_I865G(dev
))
10174 i845_update_cursor(crtc
, base
, plane_state
);
10176 i9xx_update_cursor(crtc
, base
, plane_state
);
10179 static bool cursor_size_ok(struct drm_device
*dev
,
10180 uint32_t width
, uint32_t height
)
10182 if (width
== 0 || height
== 0)
10186 * 845g/865g are special in that they are only limited by
10187 * the width of their cursors, the height is arbitrary up to
10188 * the precision of the register. Everything else requires
10189 * square cursors, limited to a few power-of-two sizes.
10191 if (IS_845G(dev
) || IS_I865G(dev
)) {
10192 if ((width
& 63) != 0)
10195 if (width
> (IS_845G(dev
) ? 64 : 512))
10201 switch (width
| height
) {
10216 /* VESA 640x480x72Hz mode to set on the pipe */
10217 static struct drm_display_mode load_detect_mode
= {
10218 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10219 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10222 struct drm_framebuffer
*
10223 __intel_framebuffer_create(struct drm_device
*dev
,
10224 struct drm_mode_fb_cmd2
*mode_cmd
,
10225 struct drm_i915_gem_object
*obj
)
10227 struct intel_framebuffer
*intel_fb
;
10230 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10232 return ERR_PTR(-ENOMEM
);
10234 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
10238 return &intel_fb
->base
;
10242 return ERR_PTR(ret
);
10245 static struct drm_framebuffer
*
10246 intel_framebuffer_create(struct drm_device
*dev
,
10247 struct drm_mode_fb_cmd2
*mode_cmd
,
10248 struct drm_i915_gem_object
*obj
)
10250 struct drm_framebuffer
*fb
;
10253 ret
= i915_mutex_lock_interruptible(dev
);
10255 return ERR_PTR(ret
);
10256 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
10257 mutex_unlock(&dev
->struct_mutex
);
10263 intel_framebuffer_pitch_for_width(int width
, int bpp
)
10265 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
10266 return ALIGN(pitch
, 64);
10270 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
10272 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
10273 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
10276 static struct drm_framebuffer
*
10277 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
10278 struct drm_display_mode
*mode
,
10279 int depth
, int bpp
)
10281 struct drm_framebuffer
*fb
;
10282 struct drm_i915_gem_object
*obj
;
10283 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
10285 obj
= i915_gem_alloc_object(dev
,
10286 intel_framebuffer_size_for_mode(mode
, bpp
));
10288 return ERR_PTR(-ENOMEM
);
10290 mode_cmd
.width
= mode
->hdisplay
;
10291 mode_cmd
.height
= mode
->vdisplay
;
10292 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
10294 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
10296 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
10298 drm_gem_object_unreference_unlocked(&obj
->base
);
10303 static struct drm_framebuffer
*
10304 mode_fits_in_fbdev(struct drm_device
*dev
,
10305 struct drm_display_mode
*mode
)
10307 #ifdef CONFIG_DRM_FBDEV_EMULATION
10308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10309 struct drm_i915_gem_object
*obj
;
10310 struct drm_framebuffer
*fb
;
10312 if (!dev_priv
->fbdev
)
10315 if (!dev_priv
->fbdev
->fb
)
10318 obj
= dev_priv
->fbdev
->fb
->obj
;
10321 fb
= &dev_priv
->fbdev
->fb
->base
;
10322 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
10323 fb
->bits_per_pixel
))
10326 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
10329 drm_framebuffer_reference(fb
);
10336 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
10337 struct drm_crtc
*crtc
,
10338 struct drm_display_mode
*mode
,
10339 struct drm_framebuffer
*fb
,
10342 struct drm_plane_state
*plane_state
;
10343 int hdisplay
, vdisplay
;
10346 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
10347 if (IS_ERR(plane_state
))
10348 return PTR_ERR(plane_state
);
10351 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
10353 hdisplay
= vdisplay
= 0;
10355 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
10358 drm_atomic_set_fb_for_plane(plane_state
, fb
);
10359 plane_state
->crtc_x
= 0;
10360 plane_state
->crtc_y
= 0;
10361 plane_state
->crtc_w
= hdisplay
;
10362 plane_state
->crtc_h
= vdisplay
;
10363 plane_state
->src_x
= x
<< 16;
10364 plane_state
->src_y
= y
<< 16;
10365 plane_state
->src_w
= hdisplay
<< 16;
10366 plane_state
->src_h
= vdisplay
<< 16;
10371 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
10372 struct drm_display_mode
*mode
,
10373 struct intel_load_detect_pipe
*old
,
10374 struct drm_modeset_acquire_ctx
*ctx
)
10376 struct intel_crtc
*intel_crtc
;
10377 struct intel_encoder
*intel_encoder
=
10378 intel_attached_encoder(connector
);
10379 struct drm_crtc
*possible_crtc
;
10380 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10381 struct drm_crtc
*crtc
= NULL
;
10382 struct drm_device
*dev
= encoder
->dev
;
10383 struct drm_framebuffer
*fb
;
10384 struct drm_mode_config
*config
= &dev
->mode_config
;
10385 struct drm_atomic_state
*state
= NULL
, *restore_state
= NULL
;
10386 struct drm_connector_state
*connector_state
;
10387 struct intel_crtc_state
*crtc_state
;
10390 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10391 connector
->base
.id
, connector
->name
,
10392 encoder
->base
.id
, encoder
->name
);
10394 old
->restore_state
= NULL
;
10397 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
10402 * Algorithm gets a little messy:
10404 * - if the connector already has an assigned crtc, use it (but make
10405 * sure it's on first)
10407 * - try to find the first unused crtc that can drive this connector,
10408 * and use that if we find one
10411 /* See if we already have a CRTC for this connector */
10412 if (connector
->state
->crtc
) {
10413 crtc
= connector
->state
->crtc
;
10415 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10419 /* Make sure the crtc and connector are running */
10423 /* Find an unused one (if possible) */
10424 for_each_crtc(dev
, possible_crtc
) {
10426 if (!(encoder
->possible_crtcs
& (1 << i
)))
10429 ret
= drm_modeset_lock(&possible_crtc
->mutex
, ctx
);
10433 if (possible_crtc
->state
->enable
) {
10434 drm_modeset_unlock(&possible_crtc
->mutex
);
10438 crtc
= possible_crtc
;
10443 * If we didn't find an unused CRTC, don't use any.
10446 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10451 intel_crtc
= to_intel_crtc(crtc
);
10453 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10457 state
= drm_atomic_state_alloc(dev
);
10458 restore_state
= drm_atomic_state_alloc(dev
);
10459 if (!state
|| !restore_state
) {
10464 state
->acquire_ctx
= ctx
;
10465 restore_state
->acquire_ctx
= ctx
;
10467 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10468 if (IS_ERR(connector_state
)) {
10469 ret
= PTR_ERR(connector_state
);
10473 ret
= drm_atomic_set_crtc_for_connector(connector_state
, crtc
);
10477 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10478 if (IS_ERR(crtc_state
)) {
10479 ret
= PTR_ERR(crtc_state
);
10483 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10486 mode
= &load_detect_mode
;
10488 /* We need a framebuffer large enough to accommodate all accesses
10489 * that the plane may generate whilst we perform load detection.
10490 * We can not rely on the fbcon either being present (we get called
10491 * during its initialisation to detect all boot displays, or it may
10492 * not even exist) or that it is large enough to satisfy the
10495 fb
= mode_fits_in_fbdev(dev
, mode
);
10497 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10498 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
10500 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10502 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10506 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
10510 drm_framebuffer_unreference(fb
);
10512 ret
= drm_atomic_set_mode_for_crtc(&crtc_state
->base
, mode
);
10516 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state
, connector
));
10518 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state
, crtc
));
10520 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state
, crtc
->primary
));
10522 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret
);
10526 ret
= drm_atomic_commit(state
);
10528 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10532 old
->restore_state
= restore_state
;
10534 /* let the connector get through one full cycle before testing */
10535 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
10539 drm_atomic_state_free(state
);
10540 drm_atomic_state_free(restore_state
);
10541 restore_state
= state
= NULL
;
10543 if (ret
== -EDEADLK
) {
10544 drm_modeset_backoff(ctx
);
10551 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10552 struct intel_load_detect_pipe
*old
,
10553 struct drm_modeset_acquire_ctx
*ctx
)
10555 struct intel_encoder
*intel_encoder
=
10556 intel_attached_encoder(connector
);
10557 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10558 struct drm_atomic_state
*state
= old
->restore_state
;
10561 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10562 connector
->base
.id
, connector
->name
,
10563 encoder
->base
.id
, encoder
->name
);
10568 ret
= drm_atomic_commit(state
);
10570 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret
);
10571 drm_atomic_state_free(state
);
10575 static int i9xx_pll_refclk(struct drm_device
*dev
,
10576 const struct intel_crtc_state
*pipe_config
)
10578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10579 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10581 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10582 return dev_priv
->vbt
.lvds_ssc_freq
;
10583 else if (HAS_PCH_SPLIT(dev
))
10585 else if (!IS_GEN2(dev
))
10591 /* Returns the clock of the currently programmed mode of the given pipe. */
10592 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10593 struct intel_crtc_state
*pipe_config
)
10595 struct drm_device
*dev
= crtc
->base
.dev
;
10596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10597 int pipe
= pipe_config
->cpu_transcoder
;
10598 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10600 intel_clock_t clock
;
10602 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10604 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10605 fp
= pipe_config
->dpll_hw_state
.fp0
;
10607 fp
= pipe_config
->dpll_hw_state
.fp1
;
10609 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10610 if (IS_PINEVIEW(dev
)) {
10611 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10612 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10614 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10615 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10618 if (!IS_GEN2(dev
)) {
10619 if (IS_PINEVIEW(dev
))
10620 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10621 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10623 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10624 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10626 switch (dpll
& DPLL_MODE_MASK
) {
10627 case DPLLB_MODE_DAC_SERIAL
:
10628 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10631 case DPLLB_MODE_LVDS
:
10632 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10636 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10637 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10641 if (IS_PINEVIEW(dev
))
10642 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
10644 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10646 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10647 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10650 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10651 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10653 if (lvds
& LVDS_CLKB_POWER_UP
)
10658 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10661 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10662 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10664 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10670 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10674 * This value includes pixel_multiplier. We will use
10675 * port_clock to compute adjusted_mode.crtc_clock in the
10676 * encoder's get_config() function.
10678 pipe_config
->port_clock
= port_clock
;
10681 int intel_dotclock_calculate(int link_freq
,
10682 const struct intel_link_m_n
*m_n
)
10685 * The calculation for the data clock is:
10686 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10687 * But we want to avoid losing precison if possible, so:
10688 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10690 * and the link clock is simpler:
10691 * link_clock = (m * link_clock) / n
10697 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10700 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10701 struct intel_crtc_state
*pipe_config
)
10703 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10705 /* read out port_clock from the DPLL */
10706 i9xx_crtc_clock_get(crtc
, pipe_config
);
10709 * In case there is an active pipe without active ports,
10710 * we may need some idea for the dotclock anyway.
10711 * Calculate one based on the FDI configuration.
10713 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10714 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
10715 &pipe_config
->fdi_m_n
);
10718 /** Returns the currently programmed mode of the given pipe. */
10719 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10720 struct drm_crtc
*crtc
)
10722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10723 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10724 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10725 struct drm_display_mode
*mode
;
10726 struct intel_crtc_state
*pipe_config
;
10727 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10728 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10729 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10730 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10731 enum pipe pipe
= intel_crtc
->pipe
;
10733 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10737 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10738 if (!pipe_config
) {
10744 * Construct a pipe_config sufficient for getting the clock info
10745 * back out of crtc_clock_get.
10747 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10748 * to use a real value here instead.
10750 pipe_config
->cpu_transcoder
= (enum transcoder
) pipe
;
10751 pipe_config
->pixel_multiplier
= 1;
10752 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10753 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10754 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10755 i9xx_crtc_clock_get(intel_crtc
, pipe_config
);
10757 mode
->clock
= pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
10758 mode
->hdisplay
= (htot
& 0xffff) + 1;
10759 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10760 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10761 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10762 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10763 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10764 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10765 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10767 drm_mode_set_name(mode
);
10769 kfree(pipe_config
);
10774 void intel_mark_busy(struct drm_device
*dev
)
10776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10778 if (dev_priv
->mm
.busy
)
10781 intel_runtime_pm_get(dev_priv
);
10782 i915_update_gfx_val(dev_priv
);
10783 if (INTEL_INFO(dev
)->gen
>= 6)
10784 gen6_rps_busy(dev_priv
);
10785 dev_priv
->mm
.busy
= true;
10788 void intel_mark_idle(struct drm_device
*dev
)
10790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10792 if (!dev_priv
->mm
.busy
)
10795 dev_priv
->mm
.busy
= false;
10797 if (INTEL_INFO(dev
)->gen
>= 6)
10798 gen6_rps_idle(dev
->dev_private
);
10800 intel_runtime_pm_put(dev_priv
);
10803 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10805 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10806 struct drm_device
*dev
= crtc
->dev
;
10807 struct intel_unpin_work
*work
;
10809 spin_lock_irq(&dev
->event_lock
);
10810 work
= intel_crtc
->unpin_work
;
10811 intel_crtc
->unpin_work
= NULL
;
10812 spin_unlock_irq(&dev
->event_lock
);
10815 cancel_work_sync(&work
->work
);
10819 drm_crtc_cleanup(crtc
);
10824 static void intel_unpin_work_fn(struct work_struct
*__work
)
10826 struct intel_unpin_work
*work
=
10827 container_of(__work
, struct intel_unpin_work
, work
);
10828 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
10829 struct drm_device
*dev
= crtc
->base
.dev
;
10830 struct drm_plane
*primary
= crtc
->base
.primary
;
10832 mutex_lock(&dev
->struct_mutex
);
10833 intel_unpin_fb_obj(work
->old_fb
, primary
->state
->rotation
);
10834 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10836 if (work
->flip_queued_req
)
10837 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10838 mutex_unlock(&dev
->struct_mutex
);
10840 intel_frontbuffer_flip_complete(dev
, to_intel_plane(primary
)->frontbuffer_bit
);
10841 intel_fbc_post_update(crtc
);
10842 drm_framebuffer_unreference(work
->old_fb
);
10844 BUG_ON(atomic_read(&crtc
->unpin_work_count
) == 0);
10845 atomic_dec(&crtc
->unpin_work_count
);
10850 static void do_intel_finish_page_flip(struct drm_device
*dev
,
10851 struct drm_crtc
*crtc
)
10853 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10854 struct intel_unpin_work
*work
;
10855 unsigned long flags
;
10857 /* Ignore early vblank irqs */
10858 if (intel_crtc
== NULL
)
10862 * This is called both by irq handlers and the reset code (to complete
10863 * lost pageflips) so needs the full irqsave spinlocks.
10865 spin_lock_irqsave(&dev
->event_lock
, flags
);
10866 work
= intel_crtc
->unpin_work
;
10868 /* Ensure we don't miss a work->pending update ... */
10871 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
10872 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10876 page_flip_completed(intel_crtc
);
10878 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10881 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
10883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10884 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10886 do_intel_finish_page_flip(dev
, crtc
);
10889 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
10891 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10892 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
10894 do_intel_finish_page_flip(dev
, crtc
);
10897 /* Is 'a' after or equal to 'b'? */
10898 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10900 return !((a
- b
) & 0x80000000);
10903 static bool page_flip_finished(struct intel_crtc
*crtc
)
10905 struct drm_device
*dev
= crtc
->base
.dev
;
10906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10908 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
10909 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
10913 * The relevant registers doen't exist on pre-ctg.
10914 * As the flip done interrupt doesn't trigger for mmio
10915 * flips on gmch platforms, a flip count check isn't
10916 * really needed there. But since ctg has the registers,
10917 * include it in the check anyway.
10919 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
10923 * BDW signals flip done immediately if the plane
10924 * is disabled, even if the plane enable is already
10925 * armed to occur at the next vblank :(
10929 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10930 * used the same base address. In that case the mmio flip might
10931 * have completed, but the CS hasn't even executed the flip yet.
10933 * A flip count check isn't enough as the CS might have updated
10934 * the base address just after start of vblank, but before we
10935 * managed to process the interrupt. This means we'd complete the
10936 * CS flip too soon.
10938 * Combining both checks should get us a good enough result. It may
10939 * still happen that the CS flip has been executed, but has not
10940 * yet actually completed. But in case the base address is the same
10941 * anyway, we don't really care.
10943 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
10944 crtc
->unpin_work
->gtt_offset
&&
10945 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc
->pipe
)),
10946 crtc
->unpin_work
->flip_count
);
10949 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
10951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10952 struct intel_crtc
*intel_crtc
=
10953 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
10954 unsigned long flags
;
10958 * This is called both by irq handlers and the reset code (to complete
10959 * lost pageflips) so needs the full irqsave spinlocks.
10961 * NB: An MMIO update of the plane base pointer will also
10962 * generate a page-flip completion irq, i.e. every modeset
10963 * is also accompanied by a spurious intel_prepare_page_flip().
10965 spin_lock_irqsave(&dev
->event_lock
, flags
);
10966 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
10967 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
10968 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10971 static inline void intel_mark_page_flip_active(struct intel_unpin_work
*work
)
10973 /* Ensure that the work item is consistent when activating it ... */
10975 atomic_set(&work
->pending
, INTEL_FLIP_PENDING
);
10976 /* and that it is marked active as soon as the irq could fire. */
10980 static int intel_gen2_queue_flip(struct drm_device
*dev
,
10981 struct drm_crtc
*crtc
,
10982 struct drm_framebuffer
*fb
,
10983 struct drm_i915_gem_object
*obj
,
10984 struct drm_i915_gem_request
*req
,
10987 struct intel_engine_cs
*engine
= req
->engine
;
10988 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10992 ret
= intel_ring_begin(req
, 6);
10996 /* Can't queue multiple flips, so wait for the previous
10997 * one to finish before executing the next.
10999 if (intel_crtc
->plane
)
11000 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11002 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11003 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| flip_mask
);
11004 intel_ring_emit(engine
, MI_NOOP
);
11005 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11006 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11007 intel_ring_emit(engine
, fb
->pitches
[0]);
11008 intel_ring_emit(engine
, intel_crtc
->unpin_work
->gtt_offset
);
11009 intel_ring_emit(engine
, 0); /* aux display base address, unused */
11011 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
11015 static int intel_gen3_queue_flip(struct drm_device
*dev
,
11016 struct drm_crtc
*crtc
,
11017 struct drm_framebuffer
*fb
,
11018 struct drm_i915_gem_object
*obj
,
11019 struct drm_i915_gem_request
*req
,
11022 struct intel_engine_cs
*engine
= req
->engine
;
11023 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11027 ret
= intel_ring_begin(req
, 6);
11031 if (intel_crtc
->plane
)
11032 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11034 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11035 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| flip_mask
);
11036 intel_ring_emit(engine
, MI_NOOP
);
11037 intel_ring_emit(engine
, MI_DISPLAY_FLIP_I915
|
11038 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11039 intel_ring_emit(engine
, fb
->pitches
[0]);
11040 intel_ring_emit(engine
, intel_crtc
->unpin_work
->gtt_offset
);
11041 intel_ring_emit(engine
, MI_NOOP
);
11043 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
11047 static int intel_gen4_queue_flip(struct drm_device
*dev
,
11048 struct drm_crtc
*crtc
,
11049 struct drm_framebuffer
*fb
,
11050 struct drm_i915_gem_object
*obj
,
11051 struct drm_i915_gem_request
*req
,
11054 struct intel_engine_cs
*engine
= req
->engine
;
11055 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11056 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11057 uint32_t pf
, pipesrc
;
11060 ret
= intel_ring_begin(req
, 4);
11064 /* i965+ uses the linear or tiled offsets from the
11065 * Display Registers (which do not change across a page-flip)
11066 * so we need only reprogram the base address.
11068 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11069 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11070 intel_ring_emit(engine
, fb
->pitches
[0]);
11071 intel_ring_emit(engine
, intel_crtc
->unpin_work
->gtt_offset
|
11074 /* XXX Enabling the panel-fitter across page-flip is so far
11075 * untested on non-native modes, so ignore it for now.
11076 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11079 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11080 intel_ring_emit(engine
, pf
| pipesrc
);
11082 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
11086 static int intel_gen6_queue_flip(struct drm_device
*dev
,
11087 struct drm_crtc
*crtc
,
11088 struct drm_framebuffer
*fb
,
11089 struct drm_i915_gem_object
*obj
,
11090 struct drm_i915_gem_request
*req
,
11093 struct intel_engine_cs
*engine
= req
->engine
;
11094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11095 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11096 uint32_t pf
, pipesrc
;
11099 ret
= intel_ring_begin(req
, 4);
11103 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11104 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11105 intel_ring_emit(engine
, fb
->pitches
[0] | obj
->tiling_mode
);
11106 intel_ring_emit(engine
, intel_crtc
->unpin_work
->gtt_offset
);
11108 /* Contrary to the suggestions in the documentation,
11109 * "Enable Panel Fitter" does not seem to be required when page
11110 * flipping with a non-native mode, and worse causes a normal
11112 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11115 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11116 intel_ring_emit(engine
, pf
| pipesrc
);
11118 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
11122 static int intel_gen7_queue_flip(struct drm_device
*dev
,
11123 struct drm_crtc
*crtc
,
11124 struct drm_framebuffer
*fb
,
11125 struct drm_i915_gem_object
*obj
,
11126 struct drm_i915_gem_request
*req
,
11129 struct intel_engine_cs
*engine
= req
->engine
;
11130 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11131 uint32_t plane_bit
= 0;
11134 switch (intel_crtc
->plane
) {
11136 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
11139 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
11142 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
11145 WARN_ONCE(1, "unknown plane in flip command\n");
11150 if (engine
->id
== RCS
) {
11153 * On Gen 8, SRM is now taking an extra dword to accommodate
11154 * 48bits addresses, and we need a NOOP for the batch size to
11162 * BSpec MI_DISPLAY_FLIP for IVB:
11163 * "The full packet must be contained within the same cache line."
11165 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11166 * cacheline, if we ever start emitting more commands before
11167 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11168 * then do the cacheline alignment, and finally emit the
11171 ret
= intel_ring_cacheline_align(req
);
11175 ret
= intel_ring_begin(req
, len
);
11179 /* Unmask the flip-done completion message. Note that the bspec says that
11180 * we should do this for both the BCS and RCS, and that we must not unmask
11181 * more than one flip event at any time (or ensure that one flip message
11182 * can be sent by waiting for flip-done prior to queueing new flips).
11183 * Experimentation says that BCS works despite DERRMR masking all
11184 * flip-done completion events and that unmasking all planes at once
11185 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11186 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11188 if (engine
->id
== RCS
) {
11189 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
11190 intel_ring_emit_reg(engine
, DERRMR
);
11191 intel_ring_emit(engine
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
11192 DERRMR_PIPEB_PRI_FLIP_DONE
|
11193 DERRMR_PIPEC_PRI_FLIP_DONE
));
11195 intel_ring_emit(engine
, MI_STORE_REGISTER_MEM_GEN8
|
11196 MI_SRM_LRM_GLOBAL_GTT
);
11198 intel_ring_emit(engine
, MI_STORE_REGISTER_MEM
|
11199 MI_SRM_LRM_GLOBAL_GTT
);
11200 intel_ring_emit_reg(engine
, DERRMR
);
11201 intel_ring_emit(engine
, engine
->scratch
.gtt_offset
+ 256);
11202 if (IS_GEN8(dev
)) {
11203 intel_ring_emit(engine
, 0);
11204 intel_ring_emit(engine
, MI_NOOP
);
11208 intel_ring_emit(engine
, MI_DISPLAY_FLIP_I915
| plane_bit
);
11209 intel_ring_emit(engine
, (fb
->pitches
[0] | obj
->tiling_mode
));
11210 intel_ring_emit(engine
, intel_crtc
->unpin_work
->gtt_offset
);
11211 intel_ring_emit(engine
, (MI_NOOP
));
11213 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
11217 static bool use_mmio_flip(struct intel_engine_cs
*engine
,
11218 struct drm_i915_gem_object
*obj
)
11221 * This is not being used for older platforms, because
11222 * non-availability of flip done interrupt forces us to use
11223 * CS flips. Older platforms derive flip done using some clever
11224 * tricks involving the flip_pending status bits and vblank irqs.
11225 * So using MMIO flips there would disrupt this mechanism.
11228 if (engine
== NULL
)
11231 if (INTEL_INFO(engine
->dev
)->gen
< 5)
11234 if (i915
.use_mmio_flip
< 0)
11236 else if (i915
.use_mmio_flip
> 0)
11238 else if (i915
.enable_execlists
)
11240 else if (obj
->base
.dma_buf
&&
11241 !reservation_object_test_signaled_rcu(obj
->base
.dma_buf
->resv
,
11245 return engine
!= i915_gem_request_get_engine(obj
->last_write_req
);
11248 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
,
11249 unsigned int rotation
,
11250 struct intel_unpin_work
*work
)
11252 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11254 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
11255 const enum pipe pipe
= intel_crtc
->pipe
;
11256 u32 ctl
, stride
, tile_height
;
11258 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
11259 ctl
&= ~PLANE_CTL_TILED_MASK
;
11260 switch (fb
->modifier
[0]) {
11261 case DRM_FORMAT_MOD_NONE
:
11263 case I915_FORMAT_MOD_X_TILED
:
11264 ctl
|= PLANE_CTL_TILED_X
;
11266 case I915_FORMAT_MOD_Y_TILED
:
11267 ctl
|= PLANE_CTL_TILED_Y
;
11269 case I915_FORMAT_MOD_Yf_TILED
:
11270 ctl
|= PLANE_CTL_TILED_YF
;
11273 MISSING_CASE(fb
->modifier
[0]);
11277 * The stride is either expressed as a multiple of 64 bytes chunks for
11278 * linear buffers or in number of tiles for tiled buffers.
11280 if (intel_rotation_90_or_270(rotation
)) {
11281 /* stride = Surface height in tiles */
11282 tile_height
= intel_tile_height(dev_priv
, fb
->modifier
[0], 0);
11283 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
11285 stride
= fb
->pitches
[0] /
11286 intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
11291 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11292 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11294 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
11295 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
11297 I915_WRITE(PLANE_SURF(pipe
, 0), work
->gtt_offset
);
11298 POSTING_READ(PLANE_SURF(pipe
, 0));
11301 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
,
11302 struct intel_unpin_work
*work
)
11304 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11306 struct intel_framebuffer
*intel_fb
=
11307 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
11308 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11309 i915_reg_t reg
= DSPCNTR(intel_crtc
->plane
);
11312 dspcntr
= I915_READ(reg
);
11314 if (obj
->tiling_mode
!= I915_TILING_NONE
)
11315 dspcntr
|= DISPPLANE_TILED
;
11317 dspcntr
&= ~DISPPLANE_TILED
;
11319 I915_WRITE(reg
, dspcntr
);
11321 I915_WRITE(DSPSURF(intel_crtc
->plane
), work
->gtt_offset
);
11322 POSTING_READ(DSPSURF(intel_crtc
->plane
));
11326 * XXX: This is the temporary way to update the plane registers until we get
11327 * around to using the usual plane update functions for MMIO flips
11329 static void intel_do_mmio_flip(struct intel_mmio_flip
*mmio_flip
)
11331 struct intel_crtc
*crtc
= mmio_flip
->crtc
;
11332 struct intel_unpin_work
*work
;
11334 spin_lock_irq(&crtc
->base
.dev
->event_lock
);
11335 work
= crtc
->unpin_work
;
11336 spin_unlock_irq(&crtc
->base
.dev
->event_lock
);
11340 intel_mark_page_flip_active(work
);
11342 intel_pipe_update_start(crtc
);
11344 if (INTEL_INFO(mmio_flip
->i915
)->gen
>= 9)
11345 skl_do_mmio_flip(crtc
, mmio_flip
->rotation
, work
);
11347 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11348 ilk_do_mmio_flip(crtc
, work
);
11350 intel_pipe_update_end(crtc
);
11353 static void intel_mmio_flip_work_func(struct work_struct
*work
)
11355 struct intel_mmio_flip
*mmio_flip
=
11356 container_of(work
, struct intel_mmio_flip
, work
);
11357 struct intel_framebuffer
*intel_fb
=
11358 to_intel_framebuffer(mmio_flip
->crtc
->base
.primary
->fb
);
11359 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11361 if (mmio_flip
->req
) {
11362 WARN_ON(__i915_wait_request(mmio_flip
->req
,
11363 mmio_flip
->crtc
->reset_counter
,
11365 &mmio_flip
->i915
->rps
.mmioflips
));
11366 i915_gem_request_unreference__unlocked(mmio_flip
->req
);
11369 /* For framebuffer backed by dmabuf, wait for fence */
11370 if (obj
->base
.dma_buf
)
11371 WARN_ON(reservation_object_wait_timeout_rcu(obj
->base
.dma_buf
->resv
,
11373 MAX_SCHEDULE_TIMEOUT
) < 0);
11375 intel_do_mmio_flip(mmio_flip
);
11379 static int intel_queue_mmio_flip(struct drm_device
*dev
,
11380 struct drm_crtc
*crtc
,
11381 struct drm_i915_gem_object
*obj
)
11383 struct intel_mmio_flip
*mmio_flip
;
11385 mmio_flip
= kmalloc(sizeof(*mmio_flip
), GFP_KERNEL
);
11386 if (mmio_flip
== NULL
)
11389 mmio_flip
->i915
= to_i915(dev
);
11390 mmio_flip
->req
= i915_gem_request_reference(obj
->last_write_req
);
11391 mmio_flip
->crtc
= to_intel_crtc(crtc
);
11392 mmio_flip
->rotation
= crtc
->primary
->state
->rotation
;
11394 INIT_WORK(&mmio_flip
->work
, intel_mmio_flip_work_func
);
11395 schedule_work(&mmio_flip
->work
);
11400 static int intel_default_queue_flip(struct drm_device
*dev
,
11401 struct drm_crtc
*crtc
,
11402 struct drm_framebuffer
*fb
,
11403 struct drm_i915_gem_object
*obj
,
11404 struct drm_i915_gem_request
*req
,
11410 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
11411 struct drm_crtc
*crtc
)
11413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11414 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11415 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
11418 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
11421 if (atomic_read(&work
->pending
) < INTEL_FLIP_PENDING
)
11424 if (!work
->enable_stall_check
)
11427 if (work
->flip_ready_vblank
== 0) {
11428 if (work
->flip_queued_req
&&
11429 !i915_gem_request_completed(work
->flip_queued_req
, true))
11432 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
11435 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
11438 /* Potential stall - if we see that the flip has happened,
11439 * assume a missed interrupt. */
11440 if (INTEL_INFO(dev
)->gen
>= 4)
11441 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
11443 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
11445 /* There is a potential issue here with a false positive after a flip
11446 * to the same address. We could address this by checking for a
11447 * non-incrementing frame counter.
11449 return addr
== work
->gtt_offset
;
11452 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
11454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11455 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11456 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11457 struct intel_unpin_work
*work
;
11459 WARN_ON(!in_interrupt());
11464 spin_lock(&dev
->event_lock
);
11465 work
= intel_crtc
->unpin_work
;
11466 if (work
!= NULL
&& __intel_pageflip_stall_check(dev
, crtc
)) {
11467 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11468 work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
11469 page_flip_completed(intel_crtc
);
11472 if (work
!= NULL
&&
11473 drm_vblank_count(dev
, pipe
) - work
->flip_queued_vblank
> 1)
11474 intel_queue_rps_boost_for_request(dev
, work
->flip_queued_req
);
11475 spin_unlock(&dev
->event_lock
);
11478 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
11479 struct drm_framebuffer
*fb
,
11480 struct drm_pending_vblank_event
*event
,
11481 uint32_t page_flip_flags
)
11483 struct drm_device
*dev
= crtc
->dev
;
11484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11485 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11486 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11487 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11488 struct drm_plane
*primary
= crtc
->primary
;
11489 enum pipe pipe
= intel_crtc
->pipe
;
11490 struct intel_unpin_work
*work
;
11491 struct intel_engine_cs
*engine
;
11493 struct drm_i915_gem_request
*request
= NULL
;
11497 * drm_mode_page_flip_ioctl() should already catch this, but double
11498 * check to be safe. In the future we may enable pageflipping from
11499 * a disabled primary plane.
11501 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
11504 /* Can't change pixel format via MI display flips. */
11505 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
11509 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11510 * Note that pitch changes could also affect these register.
11512 if (INTEL_INFO(dev
)->gen
> 3 &&
11513 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
11514 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
11517 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
11520 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
11524 work
->event
= event
;
11526 work
->old_fb
= old_fb
;
11527 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
11529 ret
= drm_crtc_vblank_get(crtc
);
11533 /* We borrow the event spin lock for protecting unpin_work */
11534 spin_lock_irq(&dev
->event_lock
);
11535 if (intel_crtc
->unpin_work
) {
11536 /* Before declaring the flip queue wedged, check if
11537 * the hardware completed the operation behind our backs.
11539 if (__intel_pageflip_stall_check(dev
, crtc
)) {
11540 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11541 page_flip_completed(intel_crtc
);
11543 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11544 spin_unlock_irq(&dev
->event_lock
);
11546 drm_crtc_vblank_put(crtc
);
11551 intel_crtc
->unpin_work
= work
;
11552 spin_unlock_irq(&dev
->event_lock
);
11554 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
11555 flush_workqueue(dev_priv
->wq
);
11557 /* Reference the objects for the scheduled work. */
11558 drm_framebuffer_reference(work
->old_fb
);
11559 drm_gem_object_reference(&obj
->base
);
11561 crtc
->primary
->fb
= fb
;
11562 update_state_fb(crtc
->primary
);
11563 intel_fbc_pre_update(intel_crtc
);
11565 work
->pending_flip_obj
= obj
;
11567 ret
= i915_mutex_lock_interruptible(dev
);
11571 atomic_inc(&intel_crtc
->unpin_work_count
);
11572 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
11574 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
11575 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_G4X(pipe
)) + 1;
11577 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
11578 engine
= &dev_priv
->engine
[BCS
];
11579 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
11580 /* vlv: DISPLAY_FLIP fails to change tiling */
11582 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
11583 engine
= &dev_priv
->engine
[BCS
];
11584 } else if (INTEL_INFO(dev
)->gen
>= 7) {
11585 engine
= i915_gem_request_get_engine(obj
->last_write_req
);
11586 if (engine
== NULL
|| engine
->id
!= RCS
)
11587 engine
= &dev_priv
->engine
[BCS
];
11589 engine
= &dev_priv
->engine
[RCS
];
11592 mmio_flip
= use_mmio_flip(engine
, obj
);
11594 /* When using CS flips, we want to emit semaphores between rings.
11595 * However, when using mmio flips we will create a task to do the
11596 * synchronisation, so all we want here is to pin the framebuffer
11597 * into the display plane and skip any waits.
11600 ret
= i915_gem_object_sync(obj
, engine
, &request
);
11602 goto cleanup_pending
;
11605 ret
= intel_pin_and_fence_fb_obj(fb
, primary
->state
->rotation
);
11607 goto cleanup_pending
;
11609 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
),
11611 work
->gtt_offset
+= intel_crtc
->dspaddr_offset
;
11614 ret
= intel_queue_mmio_flip(dev
, crtc
, obj
);
11616 goto cleanup_unpin
;
11618 i915_gem_request_assign(&work
->flip_queued_req
,
11619 obj
->last_write_req
);
11622 request
= i915_gem_request_alloc(engine
, NULL
);
11623 if (IS_ERR(request
)) {
11624 ret
= PTR_ERR(request
);
11625 goto cleanup_unpin
;
11629 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, request
,
11632 goto cleanup_unpin
;
11634 i915_gem_request_assign(&work
->flip_queued_req
, request
);
11638 i915_add_request_no_flush(request
);
11640 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
11641 work
->enable_stall_check
= true;
11643 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
11644 to_intel_plane(primary
)->frontbuffer_bit
);
11645 mutex_unlock(&dev
->struct_mutex
);
11647 intel_frontbuffer_flip_prepare(dev
,
11648 to_intel_plane(primary
)->frontbuffer_bit
);
11650 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11655 intel_unpin_fb_obj(fb
, crtc
->primary
->state
->rotation
);
11657 if (!IS_ERR_OR_NULL(request
))
11658 i915_gem_request_cancel(request
);
11659 atomic_dec(&intel_crtc
->unpin_work_count
);
11660 mutex_unlock(&dev
->struct_mutex
);
11662 crtc
->primary
->fb
= old_fb
;
11663 update_state_fb(crtc
->primary
);
11665 drm_gem_object_unreference_unlocked(&obj
->base
);
11666 drm_framebuffer_unreference(work
->old_fb
);
11668 spin_lock_irq(&dev
->event_lock
);
11669 intel_crtc
->unpin_work
= NULL
;
11670 spin_unlock_irq(&dev
->event_lock
);
11672 drm_crtc_vblank_put(crtc
);
11677 struct drm_atomic_state
*state
;
11678 struct drm_plane_state
*plane_state
;
11681 state
= drm_atomic_state_alloc(dev
);
11684 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
11687 plane_state
= drm_atomic_get_plane_state(state
, primary
);
11688 ret
= PTR_ERR_OR_ZERO(plane_state
);
11690 drm_atomic_set_fb_for_plane(plane_state
, fb
);
11692 ret
= drm_atomic_set_crtc_for_plane(plane_state
, crtc
);
11694 ret
= drm_atomic_commit(state
);
11697 if (ret
== -EDEADLK
) {
11698 drm_modeset_backoff(state
->acquire_ctx
);
11699 drm_atomic_state_clear(state
);
11704 drm_atomic_state_free(state
);
11706 if (ret
== 0 && event
) {
11707 spin_lock_irq(&dev
->event_lock
);
11708 drm_send_vblank_event(dev
, pipe
, event
);
11709 spin_unlock_irq(&dev
->event_lock
);
11717 * intel_wm_need_update - Check whether watermarks need updating
11718 * @plane: drm plane
11719 * @state: new plane state
11721 * Check current plane state versus the new one to determine whether
11722 * watermarks need to be recalculated.
11724 * Returns true or false.
11726 static bool intel_wm_need_update(struct drm_plane
*plane
,
11727 struct drm_plane_state
*state
)
11729 struct intel_plane_state
*new = to_intel_plane_state(state
);
11730 struct intel_plane_state
*cur
= to_intel_plane_state(plane
->state
);
11732 /* Update watermarks on tiling or size changes. */
11733 if (new->visible
!= cur
->visible
)
11736 if (!cur
->base
.fb
|| !new->base
.fb
)
11739 if (cur
->base
.fb
->modifier
[0] != new->base
.fb
->modifier
[0] ||
11740 cur
->base
.rotation
!= new->base
.rotation
||
11741 drm_rect_width(&new->src
) != drm_rect_width(&cur
->src
) ||
11742 drm_rect_height(&new->src
) != drm_rect_height(&cur
->src
) ||
11743 drm_rect_width(&new->dst
) != drm_rect_width(&cur
->dst
) ||
11744 drm_rect_height(&new->dst
) != drm_rect_height(&cur
->dst
))
11750 static bool needs_scaling(struct intel_plane_state
*state
)
11752 int src_w
= drm_rect_width(&state
->src
) >> 16;
11753 int src_h
= drm_rect_height(&state
->src
) >> 16;
11754 int dst_w
= drm_rect_width(&state
->dst
);
11755 int dst_h
= drm_rect_height(&state
->dst
);
11757 return (src_w
!= dst_w
|| src_h
!= dst_h
);
11760 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
11761 struct drm_plane_state
*plane_state
)
11763 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc_state
);
11764 struct drm_crtc
*crtc
= crtc_state
->crtc
;
11765 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11766 struct drm_plane
*plane
= plane_state
->plane
;
11767 struct drm_device
*dev
= crtc
->dev
;
11768 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11769 struct intel_plane_state
*old_plane_state
=
11770 to_intel_plane_state(plane
->state
);
11771 int idx
= intel_crtc
->base
.base
.id
, ret
;
11772 bool mode_changed
= needs_modeset(crtc_state
);
11773 bool was_crtc_enabled
= crtc
->state
->active
;
11774 bool is_crtc_enabled
= crtc_state
->active
;
11775 bool turn_off
, turn_on
, visible
, was_visible
;
11776 struct drm_framebuffer
*fb
= plane_state
->fb
;
11778 if (crtc_state
&& INTEL_INFO(dev
)->gen
>= 9 &&
11779 plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11780 ret
= skl_update_scaler_plane(
11781 to_intel_crtc_state(crtc_state
),
11782 to_intel_plane_state(plane_state
));
11787 was_visible
= old_plane_state
->visible
;
11788 visible
= to_intel_plane_state(plane_state
)->visible
;
11790 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
11791 was_visible
= false;
11794 * Visibility is calculated as if the crtc was on, but
11795 * after scaler setup everything depends on it being off
11796 * when the crtc isn't active.
11798 if (!is_crtc_enabled
)
11799 to_intel_plane_state(plane_state
)->visible
= visible
= false;
11801 if (!was_visible
&& !visible
)
11804 if (fb
!= old_plane_state
->base
.fb
)
11805 pipe_config
->fb_changed
= true;
11807 turn_off
= was_visible
&& (!visible
|| mode_changed
);
11808 turn_on
= visible
&& (!was_visible
|| mode_changed
);
11810 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx
,
11811 plane
->base
.id
, fb
? fb
->base
.id
: -1);
11813 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11814 plane
->base
.id
, was_visible
, visible
,
11815 turn_off
, turn_on
, mode_changed
);
11818 pipe_config
->update_wm_pre
= true;
11820 /* must disable cxsr around plane enable/disable */
11821 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
11822 pipe_config
->disable_cxsr
= true;
11823 } else if (turn_off
) {
11824 pipe_config
->update_wm_post
= true;
11826 /* must disable cxsr around plane enable/disable */
11827 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
11828 pipe_config
->disable_cxsr
= true;
11829 } else if (intel_wm_need_update(plane
, plane_state
)) {
11830 /* FIXME bollocks */
11831 pipe_config
->update_wm_pre
= true;
11832 pipe_config
->update_wm_post
= true;
11835 /* Pre-gen9 platforms need two-step watermark updates */
11836 if ((pipe_config
->update_wm_pre
|| pipe_config
->update_wm_post
) &&
11837 INTEL_INFO(dev
)->gen
< 9 && dev_priv
->display
.optimize_watermarks
)
11838 to_intel_crtc_state(crtc_state
)->wm
.need_postvbl_update
= true;
11840 if (visible
|| was_visible
)
11841 pipe_config
->fb_bits
|= to_intel_plane(plane
)->frontbuffer_bit
;
11844 * WaCxSRDisabledForSpriteScaling:ivb
11846 * cstate->update_wm was already set above, so this flag will
11847 * take effect when we commit and program watermarks.
11849 if (plane
->type
== DRM_PLANE_TYPE_OVERLAY
&& IS_IVYBRIDGE(dev
) &&
11850 needs_scaling(to_intel_plane_state(plane_state
)) &&
11851 !needs_scaling(old_plane_state
))
11852 pipe_config
->disable_lp_wm
= true;
11857 static bool encoders_cloneable(const struct intel_encoder
*a
,
11858 const struct intel_encoder
*b
)
11860 /* masks could be asymmetric, so check both ways */
11861 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11862 b
->cloneable
& (1 << a
->type
));
11865 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11866 struct intel_crtc
*crtc
,
11867 struct intel_encoder
*encoder
)
11869 struct intel_encoder
*source_encoder
;
11870 struct drm_connector
*connector
;
11871 struct drm_connector_state
*connector_state
;
11874 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11875 if (connector_state
->crtc
!= &crtc
->base
)
11879 to_intel_encoder(connector_state
->best_encoder
);
11880 if (!encoders_cloneable(encoder
, source_encoder
))
11887 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
11888 struct intel_crtc
*crtc
)
11890 struct intel_encoder
*encoder
;
11891 struct drm_connector
*connector
;
11892 struct drm_connector_state
*connector_state
;
11895 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11896 if (connector_state
->crtc
!= &crtc
->base
)
11899 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11900 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
11907 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
11908 struct drm_crtc_state
*crtc_state
)
11910 struct drm_device
*dev
= crtc
->dev
;
11911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11912 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11913 struct intel_crtc_state
*pipe_config
=
11914 to_intel_crtc_state(crtc_state
);
11915 struct drm_atomic_state
*state
= crtc_state
->state
;
11917 bool mode_changed
= needs_modeset(crtc_state
);
11919 if (mode_changed
&& !check_encoder_cloning(state
, intel_crtc
)) {
11920 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11924 if (mode_changed
&& !crtc_state
->active
)
11925 pipe_config
->update_wm_post
= true;
11927 if (mode_changed
&& crtc_state
->enable
&&
11928 dev_priv
->display
.crtc_compute_clock
&&
11929 !WARN_ON(pipe_config
->shared_dpll
)) {
11930 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11936 if (crtc_state
->color_mgmt_changed
) {
11937 ret
= intel_color_check(crtc
, crtc_state
);
11943 if (dev_priv
->display
.compute_pipe_wm
) {
11944 ret
= dev_priv
->display
.compute_pipe_wm(pipe_config
);
11946 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11951 if (dev_priv
->display
.compute_intermediate_wm
&&
11952 !to_intel_atomic_state(state
)->skip_intermediate_wm
) {
11953 if (WARN_ON(!dev_priv
->display
.compute_pipe_wm
))
11957 * Calculate 'intermediate' watermarks that satisfy both the
11958 * old state and the new state. We can program these
11961 ret
= dev_priv
->display
.compute_intermediate_wm(crtc
->dev
,
11965 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11970 if (INTEL_INFO(dev
)->gen
>= 9) {
11972 ret
= skl_update_scaler_crtc(pipe_config
);
11975 ret
= intel_atomic_setup_scalers(dev
, intel_crtc
,
11982 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11983 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
11984 .atomic_begin
= intel_begin_crtc_commit
,
11985 .atomic_flush
= intel_finish_crtc_commit
,
11986 .atomic_check
= intel_crtc_atomic_check
,
11989 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11991 struct intel_connector
*connector
;
11993 for_each_intel_connector(dev
, connector
) {
11994 if (connector
->base
.encoder
) {
11995 connector
->base
.state
->best_encoder
=
11996 connector
->base
.encoder
;
11997 connector
->base
.state
->crtc
=
11998 connector
->base
.encoder
->crtc
;
12000 connector
->base
.state
->best_encoder
= NULL
;
12001 connector
->base
.state
->crtc
= NULL
;
12007 connected_sink_compute_bpp(struct intel_connector
*connector
,
12008 struct intel_crtc_state
*pipe_config
)
12010 int bpp
= pipe_config
->pipe_bpp
;
12012 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12013 connector
->base
.base
.id
,
12014 connector
->base
.name
);
12016 /* Don't use an invalid EDID bpc value */
12017 if (connector
->base
.display_info
.bpc
&&
12018 connector
->base
.display_info
.bpc
* 3 < bpp
) {
12019 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12020 bpp
, connector
->base
.display_info
.bpc
*3);
12021 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
12024 /* Clamp bpp to default limit on screens without EDID 1.4 */
12025 if (connector
->base
.display_info
.bpc
== 0) {
12026 int type
= connector
->base
.connector_type
;
12027 int clamp_bpp
= 24;
12029 /* Fall back to 18 bpp when DP sink capability is unknown. */
12030 if (type
== DRM_MODE_CONNECTOR_DisplayPort
||
12031 type
== DRM_MODE_CONNECTOR_eDP
)
12034 if (bpp
> clamp_bpp
) {
12035 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12037 pipe_config
->pipe_bpp
= clamp_bpp
;
12043 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
12044 struct intel_crtc_state
*pipe_config
)
12046 struct drm_device
*dev
= crtc
->base
.dev
;
12047 struct drm_atomic_state
*state
;
12048 struct drm_connector
*connector
;
12049 struct drm_connector_state
*connector_state
;
12052 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)))
12054 else if (INTEL_INFO(dev
)->gen
>= 5)
12060 pipe_config
->pipe_bpp
= bpp
;
12062 state
= pipe_config
->base
.state
;
12064 /* Clamp display bpp to EDID value */
12065 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12066 if (connector_state
->crtc
!= &crtc
->base
)
12069 connected_sink_compute_bpp(to_intel_connector(connector
),
12076 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
12078 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12079 "type: 0x%x flags: 0x%x\n",
12081 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
12082 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
12083 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
12084 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
12087 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
12088 struct intel_crtc_state
*pipe_config
,
12089 const char *context
)
12091 struct drm_device
*dev
= crtc
->base
.dev
;
12092 struct drm_plane
*plane
;
12093 struct intel_plane
*intel_plane
;
12094 struct intel_plane_state
*state
;
12095 struct drm_framebuffer
*fb
;
12097 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc
->base
.base
.id
,
12098 context
, pipe_config
, pipe_name(crtc
->pipe
));
12100 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config
->cpu_transcoder
));
12101 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12102 pipe_config
->pipe_bpp
, pipe_config
->dither
);
12103 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12104 pipe_config
->has_pch_encoder
,
12105 pipe_config
->fdi_lanes
,
12106 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
12107 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
12108 pipe_config
->fdi_m_n
.tu
);
12109 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12110 pipe_config
->has_dp_encoder
,
12111 pipe_config
->lane_count
,
12112 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
12113 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
12114 pipe_config
->dp_m_n
.tu
);
12116 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12117 pipe_config
->has_dp_encoder
,
12118 pipe_config
->lane_count
,
12119 pipe_config
->dp_m2_n2
.gmch_m
,
12120 pipe_config
->dp_m2_n2
.gmch_n
,
12121 pipe_config
->dp_m2_n2
.link_m
,
12122 pipe_config
->dp_m2_n2
.link_n
,
12123 pipe_config
->dp_m2_n2
.tu
);
12125 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12126 pipe_config
->has_audio
,
12127 pipe_config
->has_infoframe
);
12129 DRM_DEBUG_KMS("requested mode:\n");
12130 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
12131 DRM_DEBUG_KMS("adjusted mode:\n");
12132 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
12133 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
12134 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
12135 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12136 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
12137 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12139 pipe_config
->scaler_state
.scaler_users
,
12140 pipe_config
->scaler_state
.scaler_id
);
12141 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12142 pipe_config
->gmch_pfit
.control
,
12143 pipe_config
->gmch_pfit
.pgm_ratios
,
12144 pipe_config
->gmch_pfit
.lvds_border_bits
);
12145 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12146 pipe_config
->pch_pfit
.pos
,
12147 pipe_config
->pch_pfit
.size
,
12148 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
12149 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
12150 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
12152 if (IS_BROXTON(dev
)) {
12153 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12154 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12155 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12156 pipe_config
->ddi_pll_sel
,
12157 pipe_config
->dpll_hw_state
.ebb0
,
12158 pipe_config
->dpll_hw_state
.ebb4
,
12159 pipe_config
->dpll_hw_state
.pll0
,
12160 pipe_config
->dpll_hw_state
.pll1
,
12161 pipe_config
->dpll_hw_state
.pll2
,
12162 pipe_config
->dpll_hw_state
.pll3
,
12163 pipe_config
->dpll_hw_state
.pll6
,
12164 pipe_config
->dpll_hw_state
.pll8
,
12165 pipe_config
->dpll_hw_state
.pll9
,
12166 pipe_config
->dpll_hw_state
.pll10
,
12167 pipe_config
->dpll_hw_state
.pcsdw12
);
12168 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
12169 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12170 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12171 pipe_config
->ddi_pll_sel
,
12172 pipe_config
->dpll_hw_state
.ctrl1
,
12173 pipe_config
->dpll_hw_state
.cfgcr1
,
12174 pipe_config
->dpll_hw_state
.cfgcr2
);
12175 } else if (HAS_DDI(dev
)) {
12176 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12177 pipe_config
->ddi_pll_sel
,
12178 pipe_config
->dpll_hw_state
.wrpll
,
12179 pipe_config
->dpll_hw_state
.spll
);
12181 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12182 "fp0: 0x%x, fp1: 0x%x\n",
12183 pipe_config
->dpll_hw_state
.dpll
,
12184 pipe_config
->dpll_hw_state
.dpll_md
,
12185 pipe_config
->dpll_hw_state
.fp0
,
12186 pipe_config
->dpll_hw_state
.fp1
);
12189 DRM_DEBUG_KMS("planes on this crtc\n");
12190 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
12191 intel_plane
= to_intel_plane(plane
);
12192 if (intel_plane
->pipe
!= crtc
->pipe
)
12195 state
= to_intel_plane_state(plane
->state
);
12196 fb
= state
->base
.fb
;
12198 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12199 "disabled, scaler_id = %d\n",
12200 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12201 plane
->base
.id
, intel_plane
->pipe
,
12202 (crtc
->base
.primary
== plane
) ? 0 : intel_plane
->plane
+ 1,
12203 drm_plane_index(plane
), state
->scaler_id
);
12207 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12208 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12209 plane
->base
.id
, intel_plane
->pipe
,
12210 crtc
->base
.primary
== plane
? 0 : intel_plane
->plane
+ 1,
12211 drm_plane_index(plane
));
12212 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12213 fb
->base
.id
, fb
->width
, fb
->height
, fb
->pixel_format
);
12214 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12216 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
12217 drm_rect_width(&state
->src
) >> 16,
12218 drm_rect_height(&state
->src
) >> 16,
12219 state
->dst
.x1
, state
->dst
.y1
,
12220 drm_rect_width(&state
->dst
), drm_rect_height(&state
->dst
));
12224 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
12226 struct drm_device
*dev
= state
->dev
;
12227 struct drm_connector
*connector
;
12228 unsigned int used_ports
= 0;
12231 * Walk the connector list instead of the encoder
12232 * list to detect the problem on ddi platforms
12233 * where there's just one encoder per digital port.
12235 drm_for_each_connector(connector
, dev
) {
12236 struct drm_connector_state
*connector_state
;
12237 struct intel_encoder
*encoder
;
12239 connector_state
= drm_atomic_get_existing_connector_state(state
, connector
);
12240 if (!connector_state
)
12241 connector_state
= connector
->state
;
12243 if (!connector_state
->best_encoder
)
12246 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12248 WARN_ON(!connector_state
->crtc
);
12250 switch (encoder
->type
) {
12251 unsigned int port_mask
;
12252 case INTEL_OUTPUT_UNKNOWN
:
12253 if (WARN_ON(!HAS_DDI(dev
)))
12255 case INTEL_OUTPUT_DISPLAYPORT
:
12256 case INTEL_OUTPUT_HDMI
:
12257 case INTEL_OUTPUT_EDP
:
12258 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
12260 /* the same port mustn't appear more than once */
12261 if (used_ports
& port_mask
)
12264 used_ports
|= port_mask
;
12274 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
12276 struct drm_crtc_state tmp_state
;
12277 struct intel_crtc_scaler_state scaler_state
;
12278 struct intel_dpll_hw_state dpll_hw_state
;
12279 struct intel_shared_dpll
*shared_dpll
;
12280 uint32_t ddi_pll_sel
;
12283 /* FIXME: before the switch to atomic started, a new pipe_config was
12284 * kzalloc'd. Code that depends on any field being zero should be
12285 * fixed, so that the crtc_state can be safely duplicated. For now,
12286 * only fields that are know to not cause problems are preserved. */
12288 tmp_state
= crtc_state
->base
;
12289 scaler_state
= crtc_state
->scaler_state
;
12290 shared_dpll
= crtc_state
->shared_dpll
;
12291 dpll_hw_state
= crtc_state
->dpll_hw_state
;
12292 ddi_pll_sel
= crtc_state
->ddi_pll_sel
;
12293 force_thru
= crtc_state
->pch_pfit
.force_thru
;
12295 memset(crtc_state
, 0, sizeof *crtc_state
);
12297 crtc_state
->base
= tmp_state
;
12298 crtc_state
->scaler_state
= scaler_state
;
12299 crtc_state
->shared_dpll
= shared_dpll
;
12300 crtc_state
->dpll_hw_state
= dpll_hw_state
;
12301 crtc_state
->ddi_pll_sel
= ddi_pll_sel
;
12302 crtc_state
->pch_pfit
.force_thru
= force_thru
;
12306 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
12307 struct intel_crtc_state
*pipe_config
)
12309 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12310 struct intel_encoder
*encoder
;
12311 struct drm_connector
*connector
;
12312 struct drm_connector_state
*connector_state
;
12313 int base_bpp
, ret
= -EINVAL
;
12317 clear_intel_crtc_state(pipe_config
);
12319 pipe_config
->cpu_transcoder
=
12320 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
12323 * Sanitize sync polarity flags based on requested ones. If neither
12324 * positive or negative polarity is requested, treat this as meaning
12325 * negative polarity.
12327 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12328 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
12329 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
12331 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12332 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
12333 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
12335 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
12341 * Determine the real pipe dimensions. Note that stereo modes can
12342 * increase the actual pipe size due to the frame doubling and
12343 * insertion of additional space for blanks between the frame. This
12344 * is stored in the crtc timings. We use the requested mode to do this
12345 * computation to clearly distinguish it from the adjusted mode, which
12346 * can be changed by the connectors in the below retry loop.
12348 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
12349 &pipe_config
->pipe_src_w
,
12350 &pipe_config
->pipe_src_h
);
12353 /* Ensure the port clock defaults are reset when retrying. */
12354 pipe_config
->port_clock
= 0;
12355 pipe_config
->pixel_multiplier
= 1;
12357 /* Fill in default crtc timings, allow encoders to overwrite them. */
12358 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
12359 CRTC_STEREO_DOUBLE
);
12361 /* Pass our mode to the connectors and the CRTC to give them a chance to
12362 * adjust it according to limitations or connector properties, and also
12363 * a chance to reject the mode entirely.
12365 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12366 if (connector_state
->crtc
!= crtc
)
12369 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12371 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
12372 DRM_DEBUG_KMS("Encoder config failure\n");
12377 /* Set default port clock if not overwritten by the encoder. Needs to be
12378 * done afterwards in case the encoder adjusts the mode. */
12379 if (!pipe_config
->port_clock
)
12380 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
12381 * pipe_config
->pixel_multiplier
;
12383 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
12385 DRM_DEBUG_KMS("CRTC fixup failed\n");
12389 if (ret
== RETRY
) {
12390 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
12395 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12397 goto encoder_retry
;
12400 /* Dithering seems to not pass-through bits correctly when it should, so
12401 * only enable it on 6bpc panels. */
12402 pipe_config
->dither
= pipe_config
->pipe_bpp
== 6*3;
12403 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12404 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
12411 intel_modeset_update_crtc_state(struct drm_atomic_state
*state
)
12413 struct drm_crtc
*crtc
;
12414 struct drm_crtc_state
*crtc_state
;
12417 /* Double check state. */
12418 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12419 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(crtc
->state
);
12421 /* Update hwmode for vblank functions */
12422 if (crtc
->state
->active
)
12423 crtc
->hwmode
= crtc
->state
->adjusted_mode
;
12425 crtc
->hwmode
.crtc_clock
= 0;
12428 * Update legacy state to satisfy fbc code. This can
12429 * be removed when fbc uses the atomic state.
12431 if (drm_atomic_get_existing_plane_state(state
, crtc
->primary
)) {
12432 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
12434 crtc
->primary
->fb
= plane_state
->fb
;
12435 crtc
->x
= plane_state
->src_x
>> 16;
12436 crtc
->y
= plane_state
->src_y
>> 16;
12441 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
12445 if (clock1
== clock2
)
12448 if (!clock1
|| !clock2
)
12451 diff
= abs(clock1
- clock2
);
12453 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
12459 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12460 list_for_each_entry((intel_crtc), \
12461 &(dev)->mode_config.crtc_list, \
12463 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12466 intel_compare_m_n(unsigned int m
, unsigned int n
,
12467 unsigned int m2
, unsigned int n2
,
12470 if (m
== m2
&& n
== n2
)
12473 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
12476 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
12483 } else if (n
< n2
) {
12493 return intel_fuzzy_clock_check(m
, m2
);
12497 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
12498 struct intel_link_m_n
*m2_n2
,
12501 if (m_n
->tu
== m2_n2
->tu
&&
12502 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
12503 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
12504 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
12505 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
12516 intel_pipe_config_compare(struct drm_device
*dev
,
12517 struct intel_crtc_state
*current_config
,
12518 struct intel_crtc_state
*pipe_config
,
12523 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12526 DRM_ERROR(fmt, ##__VA_ARGS__); \
12528 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12531 #define PIPE_CONF_CHECK_X(name) \
12532 if (current_config->name != pipe_config->name) { \
12533 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12534 "(expected 0x%08x, found 0x%08x)\n", \
12535 current_config->name, \
12536 pipe_config->name); \
12540 #define PIPE_CONF_CHECK_I(name) \
12541 if (current_config->name != pipe_config->name) { \
12542 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12543 "(expected %i, found %i)\n", \
12544 current_config->name, \
12545 pipe_config->name); \
12549 #define PIPE_CONF_CHECK_P(name) \
12550 if (current_config->name != pipe_config->name) { \
12551 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12552 "(expected %p, found %p)\n", \
12553 current_config->name, \
12554 pipe_config->name); \
12558 #define PIPE_CONF_CHECK_M_N(name) \
12559 if (!intel_compare_link_m_n(¤t_config->name, \
12560 &pipe_config->name,\
12562 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12563 "(expected tu %i gmch %i/%i link %i/%i, " \
12564 "found tu %i, gmch %i/%i link %i/%i)\n", \
12565 current_config->name.tu, \
12566 current_config->name.gmch_m, \
12567 current_config->name.gmch_n, \
12568 current_config->name.link_m, \
12569 current_config->name.link_n, \
12570 pipe_config->name.tu, \
12571 pipe_config->name.gmch_m, \
12572 pipe_config->name.gmch_n, \
12573 pipe_config->name.link_m, \
12574 pipe_config->name.link_n); \
12578 /* This is required for BDW+ where there is only one set of registers for
12579 * switching between high and low RR.
12580 * This macro can be used whenever a comparison has to be made between one
12581 * hw state and multiple sw state variables.
12583 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12584 if (!intel_compare_link_m_n(¤t_config->name, \
12585 &pipe_config->name, adjust) && \
12586 !intel_compare_link_m_n(¤t_config->alt_name, \
12587 &pipe_config->name, adjust)) { \
12588 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12589 "(expected tu %i gmch %i/%i link %i/%i, " \
12590 "or tu %i gmch %i/%i link %i/%i, " \
12591 "found tu %i, gmch %i/%i link %i/%i)\n", \
12592 current_config->name.tu, \
12593 current_config->name.gmch_m, \
12594 current_config->name.gmch_n, \
12595 current_config->name.link_m, \
12596 current_config->name.link_n, \
12597 current_config->alt_name.tu, \
12598 current_config->alt_name.gmch_m, \
12599 current_config->alt_name.gmch_n, \
12600 current_config->alt_name.link_m, \
12601 current_config->alt_name.link_n, \
12602 pipe_config->name.tu, \
12603 pipe_config->name.gmch_m, \
12604 pipe_config->name.gmch_n, \
12605 pipe_config->name.link_m, \
12606 pipe_config->name.link_n); \
12610 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12611 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12612 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12613 "(expected %i, found %i)\n", \
12614 current_config->name & (mask), \
12615 pipe_config->name & (mask)); \
12619 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12620 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12621 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12622 "(expected %i, found %i)\n", \
12623 current_config->name, \
12624 pipe_config->name); \
12628 #define PIPE_CONF_QUIRK(quirk) \
12629 ((current_config->quirks | pipe_config->quirks) & (quirk))
12631 PIPE_CONF_CHECK_I(cpu_transcoder
);
12633 PIPE_CONF_CHECK_I(has_pch_encoder
);
12634 PIPE_CONF_CHECK_I(fdi_lanes
);
12635 PIPE_CONF_CHECK_M_N(fdi_m_n
);
12637 PIPE_CONF_CHECK_I(has_dp_encoder
);
12638 PIPE_CONF_CHECK_I(lane_count
);
12640 if (INTEL_INFO(dev
)->gen
< 8) {
12641 PIPE_CONF_CHECK_M_N(dp_m_n
);
12643 if (current_config
->has_drrs
)
12644 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
12646 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
12648 PIPE_CONF_CHECK_I(has_dsi_encoder
);
12650 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12651 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12652 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12653 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12654 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12655 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12657 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12658 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12659 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12660 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12661 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12662 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12664 PIPE_CONF_CHECK_I(pixel_multiplier
);
12665 PIPE_CONF_CHECK_I(has_hdmi_sink
);
12666 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
12667 IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
12668 PIPE_CONF_CHECK_I(limited_color_range
);
12669 PIPE_CONF_CHECK_I(has_infoframe
);
12671 PIPE_CONF_CHECK_I(has_audio
);
12673 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12674 DRM_MODE_FLAG_INTERLACE
);
12676 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12677 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12678 DRM_MODE_FLAG_PHSYNC
);
12679 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12680 DRM_MODE_FLAG_NHSYNC
);
12681 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12682 DRM_MODE_FLAG_PVSYNC
);
12683 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12684 DRM_MODE_FLAG_NVSYNC
);
12687 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
12688 /* pfit ratios are autocomputed by the hw on gen4+ */
12689 if (INTEL_INFO(dev
)->gen
< 4)
12690 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
12691 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
12694 PIPE_CONF_CHECK_I(pipe_src_w
);
12695 PIPE_CONF_CHECK_I(pipe_src_h
);
12697 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
12698 if (current_config
->pch_pfit
.enabled
) {
12699 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
12700 PIPE_CONF_CHECK_X(pch_pfit
.size
);
12703 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12706 /* BDW+ don't expose a synchronous way to read the state */
12707 if (IS_HASWELL(dev
))
12708 PIPE_CONF_CHECK_I(ips_enabled
);
12710 PIPE_CONF_CHECK_I(double_wide
);
12712 PIPE_CONF_CHECK_X(ddi_pll_sel
);
12714 PIPE_CONF_CHECK_P(shared_dpll
);
12715 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12716 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12717 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12718 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12719 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12720 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
12721 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12722 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12723 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12725 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
12726 PIPE_CONF_CHECK_I(pipe_bpp
);
12728 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12729 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12731 #undef PIPE_CONF_CHECK_X
12732 #undef PIPE_CONF_CHECK_I
12733 #undef PIPE_CONF_CHECK_P
12734 #undef PIPE_CONF_CHECK_FLAGS
12735 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12736 #undef PIPE_CONF_QUIRK
12737 #undef INTEL_ERR_OR_DBG_KMS
12742 static void intel_pipe_config_sanity_check(struct drm_i915_private
*dev_priv
,
12743 const struct intel_crtc_state
*pipe_config
)
12745 if (pipe_config
->has_pch_encoder
) {
12746 int fdi_dotclock
= intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
12747 &pipe_config
->fdi_m_n
);
12748 int dotclock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
12751 * FDI already provided one idea for the dotclock.
12752 * Yell if the encoder disagrees.
12754 WARN(!intel_fuzzy_clock_check(fdi_dotclock
, dotclock
),
12755 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12756 fdi_dotclock
, dotclock
);
12760 static void verify_wm_state(struct drm_crtc
*crtc
,
12761 struct drm_crtc_state
*new_state
)
12763 struct drm_device
*dev
= crtc
->dev
;
12764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12765 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
12766 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
12767 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12768 const enum pipe pipe
= intel_crtc
->pipe
;
12771 if (INTEL_INFO(dev
)->gen
< 9 || !new_state
->active
)
12774 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
12775 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12778 for_each_plane(dev_priv
, pipe
, plane
) {
12779 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
12780 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
12782 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12785 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12786 "(expected (%u,%u), found (%u,%u))\n",
12787 pipe_name(pipe
), plane
+ 1,
12788 sw_entry
->start
, sw_entry
->end
,
12789 hw_entry
->start
, hw_entry
->end
);
12793 hw_entry
= &hw_ddb
.plane
[pipe
][PLANE_CURSOR
];
12794 sw_entry
= &sw_ddb
->plane
[pipe
][PLANE_CURSOR
];
12796 if (!skl_ddb_entry_equal(hw_entry
, sw_entry
)) {
12797 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12798 "(expected (%u,%u), found (%u,%u))\n",
12800 sw_entry
->start
, sw_entry
->end
,
12801 hw_entry
->start
, hw_entry
->end
);
12806 verify_connector_state(struct drm_device
*dev
, struct drm_crtc
*crtc
)
12808 struct drm_connector
*connector
;
12810 drm_for_each_connector(connector
, dev
) {
12811 struct drm_encoder
*encoder
= connector
->encoder
;
12812 struct drm_connector_state
*state
= connector
->state
;
12814 if (state
->crtc
!= crtc
)
12817 intel_connector_verify_state(to_intel_connector(connector
));
12819 I915_STATE_WARN(state
->best_encoder
!= encoder
,
12820 "connector's atomic encoder doesn't match legacy encoder\n");
12825 verify_encoder_state(struct drm_device
*dev
)
12827 struct intel_encoder
*encoder
;
12828 struct intel_connector
*connector
;
12830 for_each_intel_encoder(dev
, encoder
) {
12831 bool enabled
= false;
12834 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12835 encoder
->base
.base
.id
,
12836 encoder
->base
.name
);
12838 for_each_intel_connector(dev
, connector
) {
12839 if (connector
->base
.state
->best_encoder
!= &encoder
->base
)
12843 I915_STATE_WARN(connector
->base
.state
->crtc
!=
12844 encoder
->base
.crtc
,
12845 "connector's crtc doesn't match encoder crtc\n");
12848 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12849 "encoder's enabled state mismatch "
12850 "(expected %i, found %i)\n",
12851 !!encoder
->base
.crtc
, enabled
);
12853 if (!encoder
->base
.crtc
) {
12856 active
= encoder
->get_hw_state(encoder
, &pipe
);
12857 I915_STATE_WARN(active
,
12858 "encoder detached but still enabled on pipe %c.\n",
12865 verify_crtc_state(struct drm_crtc
*crtc
,
12866 struct drm_crtc_state
*old_crtc_state
,
12867 struct drm_crtc_state
*new_crtc_state
)
12869 struct drm_device
*dev
= crtc
->dev
;
12870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12871 struct intel_encoder
*encoder
;
12872 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12873 struct intel_crtc_state
*pipe_config
, *sw_config
;
12874 struct drm_atomic_state
*old_state
;
12877 old_state
= old_crtc_state
->state
;
12878 __drm_atomic_helper_crtc_destroy_state(crtc
, old_crtc_state
);
12879 pipe_config
= to_intel_crtc_state(old_crtc_state
);
12880 memset(pipe_config
, 0, sizeof(*pipe_config
));
12881 pipe_config
->base
.crtc
= crtc
;
12882 pipe_config
->base
.state
= old_state
;
12884 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
12886 active
= dev_priv
->display
.get_pipe_config(intel_crtc
, pipe_config
);
12888 /* hw state is inconsistent with the pipe quirk */
12889 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
12890 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
12891 active
= new_crtc_state
->active
;
12893 I915_STATE_WARN(new_crtc_state
->active
!= active
,
12894 "crtc active state doesn't match with hw state "
12895 "(expected %i, found %i)\n", new_crtc_state
->active
, active
);
12897 I915_STATE_WARN(intel_crtc
->active
!= new_crtc_state
->active
,
12898 "transitional active state does not match atomic hw state "
12899 "(expected %i, found %i)\n", new_crtc_state
->active
, intel_crtc
->active
);
12901 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
12904 active
= encoder
->get_hw_state(encoder
, &pipe
);
12905 I915_STATE_WARN(active
!= new_crtc_state
->active
,
12906 "[ENCODER:%i] active %i with crtc active %i\n",
12907 encoder
->base
.base
.id
, active
, new_crtc_state
->active
);
12909 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
12910 "Encoder connected to wrong pipe %c\n",
12914 encoder
->get_config(encoder
, pipe_config
);
12917 if (!new_crtc_state
->active
)
12920 intel_pipe_config_sanity_check(dev_priv
, pipe_config
);
12922 sw_config
= to_intel_crtc_state(crtc
->state
);
12923 if (!intel_pipe_config_compare(dev
, sw_config
,
12924 pipe_config
, false)) {
12925 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12926 intel_dump_pipe_config(intel_crtc
, pipe_config
,
12928 intel_dump_pipe_config(intel_crtc
, sw_config
,
12934 verify_single_dpll_state(struct drm_i915_private
*dev_priv
,
12935 struct intel_shared_dpll
*pll
,
12936 struct drm_crtc
*crtc
,
12937 struct drm_crtc_state
*new_state
)
12939 struct intel_dpll_hw_state dpll_hw_state
;
12940 unsigned crtc_mask
;
12943 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12945 DRM_DEBUG_KMS("%s\n", pll
->name
);
12947 active
= pll
->funcs
.get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12949 if (!(pll
->flags
& INTEL_DPLL_ALWAYS_ON
)) {
12950 I915_STATE_WARN(!pll
->on
&& pll
->active_mask
,
12951 "pll in active use but not on in sw tracking\n");
12952 I915_STATE_WARN(pll
->on
&& !pll
->active_mask
,
12953 "pll is on but not used by any active crtc\n");
12954 I915_STATE_WARN(pll
->on
!= active
,
12955 "pll on state mismatch (expected %i, found %i)\n",
12960 I915_STATE_WARN(pll
->active_mask
& ~pll
->config
.crtc_mask
,
12961 "more active pll users than references: %x vs %x\n",
12962 pll
->active_mask
, pll
->config
.crtc_mask
);
12967 crtc_mask
= 1 << drm_crtc_index(crtc
);
12969 if (new_state
->active
)
12970 I915_STATE_WARN(!(pll
->active_mask
& crtc_mask
),
12971 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12972 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
12974 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
12975 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12976 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
12978 I915_STATE_WARN(!(pll
->config
.crtc_mask
& crtc_mask
),
12979 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12980 crtc_mask
, pll
->config
.crtc_mask
);
12982 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
,
12984 sizeof(dpll_hw_state
)),
12985 "pll hw state mismatch\n");
12989 verify_shared_dpll_state(struct drm_device
*dev
, struct drm_crtc
*crtc
,
12990 struct drm_crtc_state
*old_crtc_state
,
12991 struct drm_crtc_state
*new_crtc_state
)
12993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12994 struct intel_crtc_state
*old_state
= to_intel_crtc_state(old_crtc_state
);
12995 struct intel_crtc_state
*new_state
= to_intel_crtc_state(new_crtc_state
);
12997 if (new_state
->shared_dpll
)
12998 verify_single_dpll_state(dev_priv
, new_state
->shared_dpll
, crtc
, new_crtc_state
);
13000 if (old_state
->shared_dpll
&&
13001 old_state
->shared_dpll
!= new_state
->shared_dpll
) {
13002 unsigned crtc_mask
= 1 << drm_crtc_index(crtc
);
13003 struct intel_shared_dpll
*pll
= old_state
->shared_dpll
;
13005 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13006 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13007 pipe_name(drm_crtc_index(crtc
)));
13008 I915_STATE_WARN(pll
->config
.crtc_mask
& crtc_mask
,
13009 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13010 pipe_name(drm_crtc_index(crtc
)));
13015 intel_modeset_verify_crtc(struct drm_crtc
*crtc
,
13016 struct drm_crtc_state
*old_state
,
13017 struct drm_crtc_state
*new_state
)
13019 if (!needs_modeset(new_state
) &&
13020 !to_intel_crtc_state(new_state
)->update_pipe
)
13023 verify_wm_state(crtc
, new_state
);
13024 verify_connector_state(crtc
->dev
, crtc
);
13025 verify_crtc_state(crtc
, old_state
, new_state
);
13026 verify_shared_dpll_state(crtc
->dev
, crtc
, old_state
, new_state
);
13030 verify_disabled_dpll_state(struct drm_device
*dev
)
13032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13035 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++)
13036 verify_single_dpll_state(dev_priv
, &dev_priv
->shared_dplls
[i
], NULL
, NULL
);
13040 intel_modeset_verify_disabled(struct drm_device
*dev
)
13042 verify_encoder_state(dev
);
13043 verify_connector_state(dev
, NULL
);
13044 verify_disabled_dpll_state(dev
);
13047 static void update_scanline_offset(struct intel_crtc
*crtc
)
13049 struct drm_device
*dev
= crtc
->base
.dev
;
13052 * The scanline counter increments at the leading edge of hsync.
13054 * On most platforms it starts counting from vtotal-1 on the
13055 * first active line. That means the scanline counter value is
13056 * always one less than what we would expect. Ie. just after
13057 * start of vblank, which also occurs at start of hsync (on the
13058 * last active line), the scanline counter will read vblank_start-1.
13060 * On gen2 the scanline counter starts counting from 1 instead
13061 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13062 * to keep the value positive), instead of adding one.
13064 * On HSW+ the behaviour of the scanline counter depends on the output
13065 * type. For DP ports it behaves like most other platforms, but on HDMI
13066 * there's an extra 1 line difference. So we need to add two instead of
13067 * one to the value.
13069 if (IS_GEN2(dev
)) {
13070 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
13073 vtotal
= adjusted_mode
->crtc_vtotal
;
13074 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
13077 crtc
->scanline_offset
= vtotal
- 1;
13078 } else if (HAS_DDI(dev
) &&
13079 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
13080 crtc
->scanline_offset
= 2;
13082 crtc
->scanline_offset
= 1;
13085 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
13087 struct drm_device
*dev
= state
->dev
;
13088 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13089 struct intel_shared_dpll_config
*shared_dpll
= NULL
;
13090 struct drm_crtc
*crtc
;
13091 struct drm_crtc_state
*crtc_state
;
13094 if (!dev_priv
->display
.crtc_compute_clock
)
13097 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13098 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13099 struct intel_shared_dpll
*old_dpll
=
13100 to_intel_crtc_state(crtc
->state
)->shared_dpll
;
13102 if (!needs_modeset(crtc_state
))
13105 to_intel_crtc_state(crtc_state
)->shared_dpll
= NULL
;
13111 shared_dpll
= intel_atomic_get_shared_dpll_state(state
);
13113 intel_shared_dpll_config_put(shared_dpll
, old_dpll
, intel_crtc
);
13118 * This implements the workaround described in the "notes" section of the mode
13119 * set sequence documentation. When going from no pipes or single pipe to
13120 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13121 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13123 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
13125 struct drm_crtc_state
*crtc_state
;
13126 struct intel_crtc
*intel_crtc
;
13127 struct drm_crtc
*crtc
;
13128 struct intel_crtc_state
*first_crtc_state
= NULL
;
13129 struct intel_crtc_state
*other_crtc_state
= NULL
;
13130 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
13133 /* look at all crtc's that are going to be enabled in during modeset */
13134 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13135 intel_crtc
= to_intel_crtc(crtc
);
13137 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
13140 if (first_crtc_state
) {
13141 other_crtc_state
= to_intel_crtc_state(crtc_state
);
13144 first_crtc_state
= to_intel_crtc_state(crtc_state
);
13145 first_pipe
= intel_crtc
->pipe
;
13149 /* No workaround needed? */
13150 if (!first_crtc_state
)
13153 /* w/a possibly needed, check how many crtc's are already enabled. */
13154 for_each_intel_crtc(state
->dev
, intel_crtc
) {
13155 struct intel_crtc_state
*pipe_config
;
13157 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
13158 if (IS_ERR(pipe_config
))
13159 return PTR_ERR(pipe_config
);
13161 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
13163 if (!pipe_config
->base
.active
||
13164 needs_modeset(&pipe_config
->base
))
13167 /* 2 or more enabled crtcs means no need for w/a */
13168 if (enabled_pipe
!= INVALID_PIPE
)
13171 enabled_pipe
= intel_crtc
->pipe
;
13174 if (enabled_pipe
!= INVALID_PIPE
)
13175 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
13176 else if (other_crtc_state
)
13177 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
13182 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
13184 struct drm_crtc
*crtc
;
13185 struct drm_crtc_state
*crtc_state
;
13188 /* add all active pipes to the state */
13189 for_each_crtc(state
->dev
, crtc
) {
13190 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13191 if (IS_ERR(crtc_state
))
13192 return PTR_ERR(crtc_state
);
13194 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
13197 crtc_state
->mode_changed
= true;
13199 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13203 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13211 static int intel_modeset_checks(struct drm_atomic_state
*state
)
13213 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13214 struct drm_i915_private
*dev_priv
= state
->dev
->dev_private
;
13215 struct drm_crtc
*crtc
;
13216 struct drm_crtc_state
*crtc_state
;
13219 if (!check_digital_port_conflicts(state
)) {
13220 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13224 intel_state
->modeset
= true;
13225 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
13227 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13228 if (crtc_state
->active
)
13229 intel_state
->active_crtcs
|= 1 << i
;
13231 intel_state
->active_crtcs
&= ~(1 << i
);
13235 * See if the config requires any additional preparation, e.g.
13236 * to adjust global state with pipes off. We need to do this
13237 * here so we can get the modeset_pipe updated config for the new
13238 * mode set on this crtc. For other crtcs we need to use the
13239 * adjusted_mode bits in the crtc directly.
13241 if (dev_priv
->display
.modeset_calc_cdclk
) {
13242 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
13244 if (!ret
&& intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
)
13245 ret
= intel_modeset_all_pipes(state
);
13250 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13251 intel_state
->cdclk
, intel_state
->dev_cdclk
);
13253 to_intel_atomic_state(state
)->cdclk
= dev_priv
->atomic_cdclk_freq
;
13255 intel_modeset_clear_plls(state
);
13257 if (IS_HASWELL(dev_priv
))
13258 return haswell_mode_set_planes_workaround(state
);
13264 * Handle calculation of various watermark data at the end of the atomic check
13265 * phase. The code here should be run after the per-crtc and per-plane 'check'
13266 * handlers to ensure that all derived state has been updated.
13268 static void calc_watermark_data(struct drm_atomic_state
*state
)
13270 struct drm_device
*dev
= state
->dev
;
13271 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13272 struct drm_crtc
*crtc
;
13273 struct drm_crtc_state
*cstate
;
13274 struct drm_plane
*plane
;
13275 struct drm_plane_state
*pstate
;
13278 * Calculate watermark configuration details now that derived
13279 * plane/crtc state is all properly updated.
13281 drm_for_each_crtc(crtc
, dev
) {
13282 cstate
= drm_atomic_get_existing_crtc_state(state
, crtc
) ?:
13285 if (cstate
->active
)
13286 intel_state
->wm_config
.num_pipes_active
++;
13288 drm_for_each_legacy_plane(plane
, dev
) {
13289 pstate
= drm_atomic_get_existing_plane_state(state
, plane
) ?:
13292 if (!to_intel_plane_state(pstate
)->visible
)
13295 intel_state
->wm_config
.sprites_enabled
= true;
13296 if (pstate
->crtc_w
!= pstate
->src_w
>> 16 ||
13297 pstate
->crtc_h
!= pstate
->src_h
>> 16)
13298 intel_state
->wm_config
.sprites_scaled
= true;
13303 * intel_atomic_check - validate state object
13305 * @state: state to validate
13307 static int intel_atomic_check(struct drm_device
*dev
,
13308 struct drm_atomic_state
*state
)
13310 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13311 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13312 struct drm_crtc
*crtc
;
13313 struct drm_crtc_state
*crtc_state
;
13315 bool any_ms
= false;
13317 ret
= drm_atomic_helper_check_modeset(dev
, state
);
13321 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13322 struct intel_crtc_state
*pipe_config
=
13323 to_intel_crtc_state(crtc_state
);
13325 /* Catch I915_MODE_FLAG_INHERITED */
13326 if (crtc_state
->mode
.private_flags
!= crtc
->state
->mode
.private_flags
)
13327 crtc_state
->mode_changed
= true;
13329 if (!crtc_state
->enable
) {
13330 if (needs_modeset(crtc_state
))
13335 if (!needs_modeset(crtc_state
))
13338 /* FIXME: For only active_changed we shouldn't need to do any
13339 * state recomputation at all. */
13341 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13345 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
13349 if (i915
.fastboot
&&
13350 intel_pipe_config_compare(dev
,
13351 to_intel_crtc_state(crtc
->state
),
13352 pipe_config
, true)) {
13353 crtc_state
->mode_changed
= false;
13354 to_intel_crtc_state(crtc_state
)->update_pipe
= true;
13357 if (needs_modeset(crtc_state
)) {
13360 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13365 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
13366 needs_modeset(crtc_state
) ?
13367 "[modeset]" : "[fastset]");
13371 ret
= intel_modeset_checks(state
);
13376 intel_state
->cdclk
= dev_priv
->cdclk_freq
;
13378 ret
= drm_atomic_helper_check_planes(dev
, state
);
13382 intel_fbc_choose_crtc(dev_priv
, state
);
13383 calc_watermark_data(state
);
13388 static int intel_atomic_prepare_commit(struct drm_device
*dev
,
13389 struct drm_atomic_state
*state
,
13392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13393 struct drm_plane_state
*plane_state
;
13394 struct drm_crtc_state
*crtc_state
;
13395 struct drm_plane
*plane
;
13396 struct drm_crtc
*crtc
;
13400 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13404 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13405 ret
= intel_crtc_wait_for_pending_flips(crtc
);
13409 if (atomic_read(&to_intel_crtc(crtc
)->unpin_work_count
) >= 2)
13410 flush_workqueue(dev_priv
->wq
);
13413 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
13417 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
13418 if (!ret
&& !async
&& !i915_reset_in_progress(&dev_priv
->gpu_error
)) {
13421 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
13422 mutex_unlock(&dev
->struct_mutex
);
13424 for_each_plane_in_state(state
, plane
, plane_state
, i
) {
13425 struct intel_plane_state
*intel_plane_state
=
13426 to_intel_plane_state(plane_state
);
13428 if (!intel_plane_state
->wait_req
)
13431 ret
= __i915_wait_request(intel_plane_state
->wait_req
,
13432 reset_counter
, true,
13435 /* Swallow -EIO errors to allow updates during hw lockup. */
13446 mutex_lock(&dev
->struct_mutex
);
13447 drm_atomic_helper_cleanup_planes(dev
, state
);
13450 mutex_unlock(&dev
->struct_mutex
);
13454 static void intel_atomic_wait_for_vblanks(struct drm_device
*dev
,
13455 struct drm_i915_private
*dev_priv
,
13456 unsigned crtc_mask
)
13458 unsigned last_vblank_count
[I915_MAX_PIPES
];
13465 for_each_pipe(dev_priv
, pipe
) {
13466 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
13468 if (!((1 << pipe
) & crtc_mask
))
13471 ret
= drm_crtc_vblank_get(crtc
);
13472 if (WARN_ON(ret
!= 0)) {
13473 crtc_mask
&= ~(1 << pipe
);
13477 last_vblank_count
[pipe
] = drm_crtc_vblank_count(crtc
);
13480 for_each_pipe(dev_priv
, pipe
) {
13481 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
13484 if (!((1 << pipe
) & crtc_mask
))
13487 lret
= wait_event_timeout(dev
->vblank
[pipe
].queue
,
13488 last_vblank_count
[pipe
] !=
13489 drm_crtc_vblank_count(crtc
),
13490 msecs_to_jiffies(50));
13494 drm_crtc_vblank_put(crtc
);
13498 static bool needs_vblank_wait(struct intel_crtc_state
*crtc_state
)
13500 /* fb updated, need to unpin old fb */
13501 if (crtc_state
->fb_changed
)
13504 /* wm changes, need vblank before final wm's */
13505 if (crtc_state
->update_wm_post
)
13509 * cxsr is re-enabled after vblank.
13510 * This is already handled by crtc_state->update_wm_post,
13511 * but added for clarity.
13513 if (crtc_state
->disable_cxsr
)
13520 * intel_atomic_commit - commit validated state object
13522 * @state: the top-level driver state object
13523 * @async: asynchronous commit
13525 * This function commits a top-level state object that has been validated
13526 * with drm_atomic_helper_check().
13528 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13529 * we can only handle plane-related operations and do not yet support
13530 * asynchronous commit.
13533 * Zero for success or -errno.
13535 static int intel_atomic_commit(struct drm_device
*dev
,
13536 struct drm_atomic_state
*state
,
13539 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13541 struct drm_crtc_state
*old_crtc_state
;
13542 struct drm_crtc
*crtc
;
13543 struct intel_crtc_state
*intel_cstate
;
13545 bool hw_check
= intel_state
->modeset
;
13546 unsigned long put_domains
[I915_MAX_PIPES
] = {};
13547 unsigned crtc_vblank_mask
= 0;
13549 ret
= intel_atomic_prepare_commit(dev
, state
, async
);
13551 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret
);
13555 drm_atomic_helper_swap_state(dev
, state
);
13556 dev_priv
->wm
.config
= intel_state
->wm_config
;
13557 intel_shared_dpll_commit(state
);
13559 if (intel_state
->modeset
) {
13560 memcpy(dev_priv
->min_pixclk
, intel_state
->min_pixclk
,
13561 sizeof(intel_state
->min_pixclk
));
13562 dev_priv
->active_crtcs
= intel_state
->active_crtcs
;
13563 dev_priv
->atomic_cdclk_freq
= intel_state
->cdclk
;
13565 intel_display_power_get(dev_priv
, POWER_DOMAIN_MODESET
);
13568 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13569 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13571 if (needs_modeset(crtc
->state
) ||
13572 to_intel_crtc_state(crtc
->state
)->update_pipe
) {
13575 put_domains
[to_intel_crtc(crtc
)->pipe
] =
13576 modeset_get_crtc_power_domains(crtc
,
13577 to_intel_crtc_state(crtc
->state
));
13580 if (!needs_modeset(crtc
->state
))
13583 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
13585 if (old_crtc_state
->active
) {
13586 intel_crtc_disable_planes(crtc
, old_crtc_state
->plane_mask
);
13587 dev_priv
->display
.crtc_disable(crtc
);
13588 intel_crtc
->active
= false;
13589 intel_fbc_disable(intel_crtc
);
13590 intel_disable_shared_dpll(intel_crtc
);
13593 * Underruns don't always raise
13594 * interrupts, so check manually.
13596 intel_check_cpu_fifo_underruns(dev_priv
);
13597 intel_check_pch_fifo_underruns(dev_priv
);
13599 if (!crtc
->state
->active
)
13600 intel_update_watermarks(crtc
);
13604 /* Only after disabling all output pipelines that will be changed can we
13605 * update the the output configuration. */
13606 intel_modeset_update_crtc_state(state
);
13608 if (intel_state
->modeset
) {
13609 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
13611 if (dev_priv
->display
.modeset_commit_cdclk
&&
13612 intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
)
13613 dev_priv
->display
.modeset_commit_cdclk(state
);
13615 intel_modeset_verify_disabled(dev
);
13618 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13619 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13620 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13621 bool modeset
= needs_modeset(crtc
->state
);
13622 struct intel_crtc_state
*pipe_config
=
13623 to_intel_crtc_state(crtc
->state
);
13624 bool update_pipe
= !modeset
&& pipe_config
->update_pipe
;
13626 if (modeset
&& crtc
->state
->active
) {
13627 update_scanline_offset(to_intel_crtc(crtc
));
13628 dev_priv
->display
.crtc_enable(crtc
);
13632 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
13634 if (crtc
->state
->active
&&
13635 drm_atomic_get_existing_plane_state(state
, crtc
->primary
))
13636 intel_fbc_enable(intel_crtc
);
13638 if (crtc
->state
->active
&&
13639 (crtc
->state
->planes_changed
|| update_pipe
))
13640 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state
);
13642 if (pipe_config
->base
.active
&& needs_vblank_wait(pipe_config
))
13643 crtc_vblank_mask
|= 1 << i
;
13646 /* FIXME: add subpixel order */
13648 if (!state
->legacy_cursor_update
)
13649 intel_atomic_wait_for_vblanks(dev
, dev_priv
, crtc_vblank_mask
);
13652 * Now that the vblank has passed, we can go ahead and program the
13653 * optimal watermarks on platforms that need two-step watermark
13656 * TODO: Move this (and other cleanup) to an async worker eventually.
13658 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13659 intel_cstate
= to_intel_crtc_state(crtc
->state
);
13661 if (dev_priv
->display
.optimize_watermarks
)
13662 dev_priv
->display
.optimize_watermarks(intel_cstate
);
13665 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13666 intel_post_plane_update(to_intel_crtc_state(old_crtc_state
));
13668 if (put_domains
[i
])
13669 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
13671 intel_modeset_verify_crtc(crtc
, old_crtc_state
, crtc
->state
);
13674 if (intel_state
->modeset
)
13675 intel_display_power_put(dev_priv
, POWER_DOMAIN_MODESET
);
13677 mutex_lock(&dev
->struct_mutex
);
13678 drm_atomic_helper_cleanup_planes(dev
, state
);
13679 mutex_unlock(&dev
->struct_mutex
);
13681 drm_atomic_state_free(state
);
13683 /* As one of the primary mmio accessors, KMS has a high likelihood
13684 * of triggering bugs in unclaimed access. After we finish
13685 * modesetting, see if an error has been flagged, and if so
13686 * enable debugging for the next modeset - and hope we catch
13689 * XXX note that we assume display power is on at this point.
13690 * This might hold true now but we need to add pm helper to check
13691 * unclaimed only when the hardware is on, as atomic commits
13692 * can happen also when the device is completely off.
13694 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
13699 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
13701 struct drm_device
*dev
= crtc
->dev
;
13702 struct drm_atomic_state
*state
;
13703 struct drm_crtc_state
*crtc_state
;
13706 state
= drm_atomic_state_alloc(dev
);
13708 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13713 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
13716 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13717 ret
= PTR_ERR_OR_ZERO(crtc_state
);
13719 if (!crtc_state
->active
)
13722 crtc_state
->mode_changed
= true;
13723 ret
= drm_atomic_commit(state
);
13726 if (ret
== -EDEADLK
) {
13727 drm_atomic_state_clear(state
);
13728 drm_modeset_backoff(state
->acquire_ctx
);
13734 drm_atomic_state_free(state
);
13737 #undef for_each_intel_crtc_masked
13739 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13740 .gamma_set
= drm_atomic_helper_legacy_gamma_set
,
13741 .set_config
= drm_atomic_helper_set_config
,
13742 .set_property
= drm_atomic_helper_crtc_set_property
,
13743 .destroy
= intel_crtc_destroy
,
13744 .page_flip
= intel_crtc_page_flip
,
13745 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13746 .atomic_destroy_state
= intel_crtc_destroy_state
,
13750 * intel_prepare_plane_fb - Prepare fb for usage on plane
13751 * @plane: drm plane to prepare for
13752 * @fb: framebuffer to prepare for presentation
13754 * Prepares a framebuffer for usage on a display plane. Generally this
13755 * involves pinning the underlying object and updating the frontbuffer tracking
13756 * bits. Some older platforms need special physical address handling for
13759 * Must be called with struct_mutex held.
13761 * Returns 0 on success, negative error code on failure.
13764 intel_prepare_plane_fb(struct drm_plane
*plane
,
13765 const struct drm_plane_state
*new_state
)
13767 struct drm_device
*dev
= plane
->dev
;
13768 struct drm_framebuffer
*fb
= new_state
->fb
;
13769 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13770 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13771 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->state
->fb
);
13774 if (!obj
&& !old_obj
)
13778 struct drm_crtc_state
*crtc_state
=
13779 drm_atomic_get_existing_crtc_state(new_state
->state
, plane
->state
->crtc
);
13781 /* Big Hammer, we also need to ensure that any pending
13782 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13783 * current scanout is retired before unpinning the old
13784 * framebuffer. Note that we rely on userspace rendering
13785 * into the buffer attached to the pipe they are waiting
13786 * on. If not, userspace generates a GPU hang with IPEHR
13787 * point to the MI_WAIT_FOR_EVENT.
13789 * This should only fail upon a hung GPU, in which case we
13790 * can safely continue.
13792 if (needs_modeset(crtc_state
))
13793 ret
= i915_gem_object_wait_rendering(old_obj
, true);
13795 /* Swallow -EIO errors to allow updates during hw lockup. */
13796 if (ret
&& ret
!= -EIO
)
13800 /* For framebuffer backed by dmabuf, wait for fence */
13801 if (obj
&& obj
->base
.dma_buf
) {
13804 lret
= reservation_object_wait_timeout_rcu(obj
->base
.dma_buf
->resv
,
13806 MAX_SCHEDULE_TIMEOUT
);
13807 if (lret
== -ERESTARTSYS
)
13810 WARN(lret
< 0, "waiting returns %li\n", lret
);
13815 } else if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
13816 INTEL_INFO(dev
)->cursor_needs_physical
) {
13817 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
13818 ret
= i915_gem_object_attach_phys(obj
, align
);
13820 DRM_DEBUG_KMS("failed to attach phys object\n");
13822 ret
= intel_pin_and_fence_fb_obj(fb
, new_state
->rotation
);
13827 struct intel_plane_state
*plane_state
=
13828 to_intel_plane_state(new_state
);
13830 i915_gem_request_assign(&plane_state
->wait_req
,
13831 obj
->last_write_req
);
13834 i915_gem_track_fb(old_obj
, obj
, intel_plane
->frontbuffer_bit
);
13841 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13842 * @plane: drm plane to clean up for
13843 * @fb: old framebuffer that was on plane
13845 * Cleans up a framebuffer that has just been removed from a plane.
13847 * Must be called with struct_mutex held.
13850 intel_cleanup_plane_fb(struct drm_plane
*plane
,
13851 const struct drm_plane_state
*old_state
)
13853 struct drm_device
*dev
= plane
->dev
;
13854 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13855 struct intel_plane_state
*old_intel_state
;
13856 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_state
->fb
);
13857 struct drm_i915_gem_object
*obj
= intel_fb_obj(plane
->state
->fb
);
13859 old_intel_state
= to_intel_plane_state(old_state
);
13861 if (!obj
&& !old_obj
)
13864 if (old_obj
&& (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
13865 !INTEL_INFO(dev
)->cursor_needs_physical
))
13866 intel_unpin_fb_obj(old_state
->fb
, old_state
->rotation
);
13868 /* prepare_fb aborted? */
13869 if ((old_obj
&& (old_obj
->frontbuffer_bits
& intel_plane
->frontbuffer_bit
)) ||
13870 (obj
&& !(obj
->frontbuffer_bits
& intel_plane
->frontbuffer_bit
)))
13871 i915_gem_track_fb(old_obj
, obj
, intel_plane
->frontbuffer_bit
);
13873 i915_gem_request_assign(&old_intel_state
->wait_req
, NULL
);
13877 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
13880 struct drm_device
*dev
;
13881 struct drm_i915_private
*dev_priv
;
13882 int crtc_clock
, cdclk
;
13884 if (!intel_crtc
|| !crtc_state
->base
.enable
)
13885 return DRM_PLANE_HELPER_NO_SCALING
;
13887 dev
= intel_crtc
->base
.dev
;
13888 dev_priv
= dev
->dev_private
;
13889 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
13890 cdclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
;
13892 if (WARN_ON_ONCE(!crtc_clock
|| cdclk
< crtc_clock
))
13893 return DRM_PLANE_HELPER_NO_SCALING
;
13896 * skl max scale is lower of:
13897 * close to 3 but not 3, -1 is for that purpose
13901 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
13907 intel_check_primary_plane(struct drm_plane
*plane
,
13908 struct intel_crtc_state
*crtc_state
,
13909 struct intel_plane_state
*state
)
13911 struct drm_crtc
*crtc
= state
->base
.crtc
;
13912 struct drm_framebuffer
*fb
= state
->base
.fb
;
13913 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13914 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13915 bool can_position
= false;
13917 if (INTEL_INFO(plane
->dev
)->gen
>= 9) {
13918 /* use scaler when colorkey is not required */
13919 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
13921 max_scale
= skl_max_scale(to_intel_crtc(crtc
), crtc_state
);
13923 can_position
= true;
13926 return drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
13927 &state
->dst
, &state
->clip
,
13928 min_scale
, max_scale
,
13929 can_position
, true,
13933 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
,
13934 struct drm_crtc_state
*old_crtc_state
)
13936 struct drm_device
*dev
= crtc
->dev
;
13937 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13938 struct intel_crtc_state
*old_intel_state
=
13939 to_intel_crtc_state(old_crtc_state
);
13940 bool modeset
= needs_modeset(crtc
->state
);
13942 /* Perform vblank evasion around commit operation */
13943 intel_pipe_update_start(intel_crtc
);
13948 if (crtc
->state
->color_mgmt_changed
|| to_intel_crtc_state(crtc
->state
)->update_pipe
) {
13949 intel_color_set_csc(crtc
->state
);
13950 intel_color_load_luts(crtc
->state
);
13953 if (to_intel_crtc_state(crtc
->state
)->update_pipe
)
13954 intel_update_pipe_config(intel_crtc
, old_intel_state
);
13955 else if (INTEL_INFO(dev
)->gen
>= 9)
13956 skl_detach_scalers(intel_crtc
);
13959 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
,
13960 struct drm_crtc_state
*old_crtc_state
)
13962 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13964 intel_pipe_update_end(intel_crtc
);
13968 * intel_plane_destroy - destroy a plane
13969 * @plane: plane to destroy
13971 * Common destruction function for all types of planes (primary, cursor,
13974 void intel_plane_destroy(struct drm_plane
*plane
)
13976 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13977 drm_plane_cleanup(plane
);
13978 kfree(intel_plane
);
13981 const struct drm_plane_funcs intel_plane_funcs
= {
13982 .update_plane
= drm_atomic_helper_update_plane
,
13983 .disable_plane
= drm_atomic_helper_disable_plane
,
13984 .destroy
= intel_plane_destroy
,
13985 .set_property
= drm_atomic_helper_plane_set_property
,
13986 .atomic_get_property
= intel_plane_atomic_get_property
,
13987 .atomic_set_property
= intel_plane_atomic_set_property
,
13988 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13989 .atomic_destroy_state
= intel_plane_destroy_state
,
13993 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
13996 struct intel_plane
*primary
= NULL
;
13997 struct intel_plane_state
*state
= NULL
;
13998 const uint32_t *intel_primary_formats
;
13999 unsigned int num_formats
;
14002 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
14006 state
= intel_create_plane_state(&primary
->base
);
14009 primary
->base
.state
= &state
->base
;
14011 primary
->can_scale
= false;
14012 primary
->max_downscale
= 1;
14013 if (INTEL_INFO(dev
)->gen
>= 9) {
14014 primary
->can_scale
= true;
14015 state
->scaler_id
= -1;
14017 primary
->pipe
= pipe
;
14018 primary
->plane
= pipe
;
14019 primary
->frontbuffer_bit
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
14020 primary
->check_plane
= intel_check_primary_plane
;
14021 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
14022 primary
->plane
= !pipe
;
14024 if (INTEL_INFO(dev
)->gen
>= 9) {
14025 intel_primary_formats
= skl_primary_formats
;
14026 num_formats
= ARRAY_SIZE(skl_primary_formats
);
14028 primary
->update_plane
= skylake_update_primary_plane
;
14029 primary
->disable_plane
= skylake_disable_primary_plane
;
14030 } else if (HAS_PCH_SPLIT(dev
)) {
14031 intel_primary_formats
= i965_primary_formats
;
14032 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14034 primary
->update_plane
= ironlake_update_primary_plane
;
14035 primary
->disable_plane
= i9xx_disable_primary_plane
;
14036 } else if (INTEL_INFO(dev
)->gen
>= 4) {
14037 intel_primary_formats
= i965_primary_formats
;
14038 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14040 primary
->update_plane
= i9xx_update_primary_plane
;
14041 primary
->disable_plane
= i9xx_disable_primary_plane
;
14043 intel_primary_formats
= i8xx_primary_formats
;
14044 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
14046 primary
->update_plane
= i9xx_update_primary_plane
;
14047 primary
->disable_plane
= i9xx_disable_primary_plane
;
14050 ret
= drm_universal_plane_init(dev
, &primary
->base
, 0,
14051 &intel_plane_funcs
,
14052 intel_primary_formats
, num_formats
,
14053 DRM_PLANE_TYPE_PRIMARY
, NULL
);
14057 if (INTEL_INFO(dev
)->gen
>= 4)
14058 intel_create_rotation_property(dev
, primary
);
14060 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
14062 return &primary
->base
;
14071 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
14073 if (!dev
->mode_config
.rotation_property
) {
14074 unsigned long flags
= BIT(DRM_ROTATE_0
) |
14075 BIT(DRM_ROTATE_180
);
14077 if (INTEL_INFO(dev
)->gen
>= 9)
14078 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
14080 dev
->mode_config
.rotation_property
=
14081 drm_mode_create_rotation_property(dev
, flags
);
14083 if (dev
->mode_config
.rotation_property
)
14084 drm_object_attach_property(&plane
->base
.base
,
14085 dev
->mode_config
.rotation_property
,
14086 plane
->base
.state
->rotation
);
14090 intel_check_cursor_plane(struct drm_plane
*plane
,
14091 struct intel_crtc_state
*crtc_state
,
14092 struct intel_plane_state
*state
)
14094 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
14095 struct drm_framebuffer
*fb
= state
->base
.fb
;
14096 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
14097 enum pipe pipe
= to_intel_plane(plane
)->pipe
;
14101 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
14102 &state
->dst
, &state
->clip
,
14103 DRM_PLANE_HELPER_NO_SCALING
,
14104 DRM_PLANE_HELPER_NO_SCALING
,
14105 true, true, &state
->visible
);
14109 /* if we want to turn off the cursor ignore width and height */
14113 /* Check for which cursor types we support */
14114 if (!cursor_size_ok(plane
->dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
14115 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14116 state
->base
.crtc_w
, state
->base
.crtc_h
);
14120 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
14121 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
14122 DRM_DEBUG_KMS("buffer is too small\n");
14126 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
14127 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14132 * There's something wrong with the cursor on CHV pipe C.
14133 * If it straddles the left edge of the screen then
14134 * moving it away from the edge or disabling it often
14135 * results in a pipe underrun, and often that can lead to
14136 * dead pipe (constant underrun reported, and it scans
14137 * out just a solid color). To recover from that, the
14138 * display power well must be turned off and on again.
14139 * Refuse the put the cursor into that compromised position.
14141 if (IS_CHERRYVIEW(plane
->dev
) && pipe
== PIPE_C
&&
14142 state
->visible
&& state
->base
.crtc_x
< 0) {
14143 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14151 intel_disable_cursor_plane(struct drm_plane
*plane
,
14152 struct drm_crtc
*crtc
)
14154 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14156 intel_crtc
->cursor_addr
= 0;
14157 intel_crtc_update_cursor(crtc
, NULL
);
14161 intel_update_cursor_plane(struct drm_plane
*plane
,
14162 const struct intel_crtc_state
*crtc_state
,
14163 const struct intel_plane_state
*state
)
14165 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
14166 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14167 struct drm_device
*dev
= plane
->dev
;
14168 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
14173 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
14174 addr
= i915_gem_obj_ggtt_offset(obj
);
14176 addr
= obj
->phys_handle
->busaddr
;
14178 intel_crtc
->cursor_addr
= addr
;
14179 intel_crtc_update_cursor(crtc
, state
);
14182 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
14185 struct intel_plane
*cursor
= NULL
;
14186 struct intel_plane_state
*state
= NULL
;
14189 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
14193 state
= intel_create_plane_state(&cursor
->base
);
14196 cursor
->base
.state
= &state
->base
;
14198 cursor
->can_scale
= false;
14199 cursor
->max_downscale
= 1;
14200 cursor
->pipe
= pipe
;
14201 cursor
->plane
= pipe
;
14202 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER_CURSOR(pipe
);
14203 cursor
->check_plane
= intel_check_cursor_plane
;
14204 cursor
->update_plane
= intel_update_cursor_plane
;
14205 cursor
->disable_plane
= intel_disable_cursor_plane
;
14207 ret
= drm_universal_plane_init(dev
, &cursor
->base
, 0,
14208 &intel_plane_funcs
,
14209 intel_cursor_formats
,
14210 ARRAY_SIZE(intel_cursor_formats
),
14211 DRM_PLANE_TYPE_CURSOR
, NULL
);
14215 if (INTEL_INFO(dev
)->gen
>= 4) {
14216 if (!dev
->mode_config
.rotation_property
)
14217 dev
->mode_config
.rotation_property
=
14218 drm_mode_create_rotation_property(dev
,
14219 BIT(DRM_ROTATE_0
) |
14220 BIT(DRM_ROTATE_180
));
14221 if (dev
->mode_config
.rotation_property
)
14222 drm_object_attach_property(&cursor
->base
.base
,
14223 dev
->mode_config
.rotation_property
,
14224 state
->base
.rotation
);
14227 if (INTEL_INFO(dev
)->gen
>=9)
14228 state
->scaler_id
= -1;
14230 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
14232 return &cursor
->base
;
14241 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
14242 struct intel_crtc_state
*crtc_state
)
14245 struct intel_scaler
*intel_scaler
;
14246 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
14248 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
14249 intel_scaler
= &scaler_state
->scalers
[i
];
14250 intel_scaler
->in_use
= 0;
14251 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
14254 scaler_state
->scaler_id
= -1;
14257 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
14259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14260 struct intel_crtc
*intel_crtc
;
14261 struct intel_crtc_state
*crtc_state
= NULL
;
14262 struct drm_plane
*primary
= NULL
;
14263 struct drm_plane
*cursor
= NULL
;
14266 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
14267 if (intel_crtc
== NULL
)
14270 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
14273 intel_crtc
->config
= crtc_state
;
14274 intel_crtc
->base
.state
= &crtc_state
->base
;
14275 crtc_state
->base
.crtc
= &intel_crtc
->base
;
14277 /* initialize shared scalers */
14278 if (INTEL_INFO(dev
)->gen
>= 9) {
14279 if (pipe
== PIPE_C
)
14280 intel_crtc
->num_scalers
= 1;
14282 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
14284 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
14287 primary
= intel_primary_plane_create(dev
, pipe
);
14291 cursor
= intel_cursor_plane_create(dev
, pipe
);
14295 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
14296 cursor
, &intel_crtc_funcs
, NULL
);
14301 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14302 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14304 intel_crtc
->pipe
= pipe
;
14305 intel_crtc
->plane
= pipe
;
14306 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
14307 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14308 intel_crtc
->plane
= !pipe
;
14311 intel_crtc
->cursor_base
= ~0;
14312 intel_crtc
->cursor_cntl
= ~0;
14313 intel_crtc
->cursor_size
= ~0;
14315 intel_crtc
->wm
.cxsr_allowed
= true;
14317 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
14318 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
14319 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
14320 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
14322 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
14324 intel_color_init(&intel_crtc
->base
);
14326 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
14331 drm_plane_cleanup(primary
);
14333 drm_plane_cleanup(cursor
);
14338 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
14340 struct drm_encoder
*encoder
= connector
->base
.encoder
;
14341 struct drm_device
*dev
= connector
->base
.dev
;
14343 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
14345 if (!encoder
|| WARN_ON(!encoder
->crtc
))
14346 return INVALID_PIPE
;
14348 return to_intel_crtc(encoder
->crtc
)->pipe
;
14351 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
14352 struct drm_file
*file
)
14354 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
14355 struct drm_crtc
*drmmode_crtc
;
14356 struct intel_crtc
*crtc
;
14358 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
14360 if (!drmmode_crtc
) {
14361 DRM_ERROR("no such CRTC id\n");
14365 crtc
= to_intel_crtc(drmmode_crtc
);
14366 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
14371 static int intel_encoder_clones(struct intel_encoder
*encoder
)
14373 struct drm_device
*dev
= encoder
->base
.dev
;
14374 struct intel_encoder
*source_encoder
;
14375 int index_mask
= 0;
14378 for_each_intel_encoder(dev
, source_encoder
) {
14379 if (encoders_cloneable(encoder
, source_encoder
))
14380 index_mask
|= (1 << entry
);
14388 static bool has_edp_a(struct drm_device
*dev
)
14390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14392 if (!IS_MOBILE(dev
))
14395 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
14398 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
14404 static bool intel_crt_present(struct drm_device
*dev
)
14406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14408 if (INTEL_INFO(dev
)->gen
>= 9)
14411 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
14414 if (IS_CHERRYVIEW(dev
))
14417 if (HAS_PCH_LPT_H(dev
) && I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
14420 /* DDI E can't be used if DDI A requires 4 lanes */
14421 if (HAS_DDI(dev
) && I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
14424 if (!dev_priv
->vbt
.int_crt_support
)
14430 static void intel_setup_outputs(struct drm_device
*dev
)
14432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14433 struct intel_encoder
*encoder
;
14434 bool dpd_is_edp
= false;
14436 intel_lvds_init(dev
);
14438 if (intel_crt_present(dev
))
14439 intel_crt_init(dev
);
14441 if (IS_BROXTON(dev
)) {
14443 * FIXME: Broxton doesn't support port detection via the
14444 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14445 * detect the ports.
14447 intel_ddi_init(dev
, PORT_A
);
14448 intel_ddi_init(dev
, PORT_B
);
14449 intel_ddi_init(dev
, PORT_C
);
14451 intel_dsi_init(dev
);
14452 } else if (HAS_DDI(dev
)) {
14456 * Haswell uses DDI functions to detect digital outputs.
14457 * On SKL pre-D0 the strap isn't connected, so we assume
14460 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
14461 /* WaIgnoreDDIAStrap: skl */
14462 if (found
|| IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
14463 intel_ddi_init(dev
, PORT_A
);
14465 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14467 found
= I915_READ(SFUSE_STRAP
);
14469 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
14470 intel_ddi_init(dev
, PORT_B
);
14471 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
14472 intel_ddi_init(dev
, PORT_C
);
14473 if (found
& SFUSE_STRAP_DDID_DETECTED
)
14474 intel_ddi_init(dev
, PORT_D
);
14476 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14478 if ((IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) &&
14479 (dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dp
||
14480 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dvi
||
14481 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_hdmi
))
14482 intel_ddi_init(dev
, PORT_E
);
14484 } else if (HAS_PCH_SPLIT(dev
)) {
14486 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
14488 if (has_edp_a(dev
))
14489 intel_dp_init(dev
, DP_A
, PORT_A
);
14491 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
14492 /* PCH SDVOB multiplex with HDMIB */
14493 found
= intel_sdvo_init(dev
, PCH_SDVOB
, PORT_B
);
14495 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
14496 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
14497 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
14500 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
14501 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
14503 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
14504 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
14506 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
14507 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
14509 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
14510 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
14511 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
14513 * The DP_DETECTED bit is the latched state of the DDC
14514 * SDA pin at boot. However since eDP doesn't require DDC
14515 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14516 * eDP ports may have been muxed to an alternate function.
14517 * Thus we can't rely on the DP_DETECTED bit alone to detect
14518 * eDP ports. Consult the VBT as well as DP_DETECTED to
14519 * detect eDP ports.
14521 if (I915_READ(VLV_HDMIB
) & SDVO_DETECTED
&&
14522 !intel_dp_is_edp(dev
, PORT_B
))
14523 intel_hdmi_init(dev
, VLV_HDMIB
, PORT_B
);
14524 if (I915_READ(VLV_DP_B
) & DP_DETECTED
||
14525 intel_dp_is_edp(dev
, PORT_B
))
14526 intel_dp_init(dev
, VLV_DP_B
, PORT_B
);
14528 if (I915_READ(VLV_HDMIC
) & SDVO_DETECTED
&&
14529 !intel_dp_is_edp(dev
, PORT_C
))
14530 intel_hdmi_init(dev
, VLV_HDMIC
, PORT_C
);
14531 if (I915_READ(VLV_DP_C
) & DP_DETECTED
||
14532 intel_dp_is_edp(dev
, PORT_C
))
14533 intel_dp_init(dev
, VLV_DP_C
, PORT_C
);
14535 if (IS_CHERRYVIEW(dev
)) {
14536 /* eDP not supported on port D, so don't check VBT */
14537 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
)
14538 intel_hdmi_init(dev
, CHV_HDMID
, PORT_D
);
14539 if (I915_READ(CHV_DP_D
) & DP_DETECTED
)
14540 intel_dp_init(dev
, CHV_DP_D
, PORT_D
);
14543 intel_dsi_init(dev
);
14544 } else if (!IS_GEN2(dev
) && !IS_PINEVIEW(dev
)) {
14545 bool found
= false;
14547 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14548 DRM_DEBUG_KMS("probing SDVOB\n");
14549 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, PORT_B
);
14550 if (!found
&& IS_G4X(dev
)) {
14551 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14552 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
14555 if (!found
&& IS_G4X(dev
))
14556 intel_dp_init(dev
, DP_B
, PORT_B
);
14559 /* Before G4X SDVOC doesn't have its own detect register */
14561 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14562 DRM_DEBUG_KMS("probing SDVOC\n");
14563 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, PORT_C
);
14566 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14569 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14570 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
14573 intel_dp_init(dev
, DP_C
, PORT_C
);
14577 (I915_READ(DP_D
) & DP_DETECTED
))
14578 intel_dp_init(dev
, DP_D
, PORT_D
);
14579 } else if (IS_GEN2(dev
))
14580 intel_dvo_init(dev
);
14582 if (SUPPORTS_TV(dev
))
14583 intel_tv_init(dev
);
14585 intel_psr_init(dev
);
14587 for_each_intel_encoder(dev
, encoder
) {
14588 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
14589 encoder
->base
.possible_clones
=
14590 intel_encoder_clones(encoder
);
14593 intel_init_pch_refclk(dev
);
14595 drm_helper_move_panel_connectors_to_head(dev
);
14598 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
14600 struct drm_device
*dev
= fb
->dev
;
14601 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14603 drm_framebuffer_cleanup(fb
);
14604 mutex_lock(&dev
->struct_mutex
);
14605 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
14606 drm_gem_object_unreference(&intel_fb
->obj
->base
);
14607 mutex_unlock(&dev
->struct_mutex
);
14611 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
14612 struct drm_file
*file
,
14613 unsigned int *handle
)
14615 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14616 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14618 if (obj
->userptr
.mm
) {
14619 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14623 return drm_gem_handle_create(file
, &obj
->base
, handle
);
14626 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
14627 struct drm_file
*file
,
14628 unsigned flags
, unsigned color
,
14629 struct drm_clip_rect
*clips
,
14630 unsigned num_clips
)
14632 struct drm_device
*dev
= fb
->dev
;
14633 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14634 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14636 mutex_lock(&dev
->struct_mutex
);
14637 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
14638 mutex_unlock(&dev
->struct_mutex
);
14643 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
14644 .destroy
= intel_user_framebuffer_destroy
,
14645 .create_handle
= intel_user_framebuffer_create_handle
,
14646 .dirty
= intel_user_framebuffer_dirty
,
14650 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
14651 uint32_t pixel_format
)
14653 u32 gen
= INTEL_INFO(dev
)->gen
;
14656 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
14658 /* "The stride in bytes must not exceed the of the size of 8K
14659 * pixels and 32K bytes."
14661 return min(8192 * cpp
, 32768);
14662 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
14664 } else if (gen
>= 4) {
14665 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14669 } else if (gen
>= 3) {
14670 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14675 /* XXX DSPC is limited to 4k tiled */
14680 static int intel_framebuffer_init(struct drm_device
*dev
,
14681 struct intel_framebuffer
*intel_fb
,
14682 struct drm_mode_fb_cmd2
*mode_cmd
,
14683 struct drm_i915_gem_object
*obj
)
14685 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14686 unsigned int aligned_height
;
14688 u32 pitch_limit
, stride_alignment
;
14690 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
14692 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
14693 /* Enforce that fb modifier and tiling mode match, but only for
14694 * X-tiled. This is needed for FBC. */
14695 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
14696 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
14697 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14701 if (obj
->tiling_mode
== I915_TILING_X
)
14702 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
14703 else if (obj
->tiling_mode
== I915_TILING_Y
) {
14704 DRM_DEBUG("No Y tiling for legacy addfb\n");
14709 /* Passed in modifier sanity checking. */
14710 switch (mode_cmd
->modifier
[0]) {
14711 case I915_FORMAT_MOD_Y_TILED
:
14712 case I915_FORMAT_MOD_Yf_TILED
:
14713 if (INTEL_INFO(dev
)->gen
< 9) {
14714 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14715 mode_cmd
->modifier
[0]);
14718 case DRM_FORMAT_MOD_NONE
:
14719 case I915_FORMAT_MOD_X_TILED
:
14722 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14723 mode_cmd
->modifier
[0]);
14727 stride_alignment
= intel_fb_stride_alignment(dev_priv
,
14728 mode_cmd
->modifier
[0],
14729 mode_cmd
->pixel_format
);
14730 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
14731 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14732 mode_cmd
->pitches
[0], stride_alignment
);
14736 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
14737 mode_cmd
->pixel_format
);
14738 if (mode_cmd
->pitches
[0] > pitch_limit
) {
14739 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14740 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
14741 "tiled" : "linear",
14742 mode_cmd
->pitches
[0], pitch_limit
);
14746 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
14747 mode_cmd
->pitches
[0] != obj
->stride
) {
14748 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14749 mode_cmd
->pitches
[0], obj
->stride
);
14753 /* Reject formats not supported by any plane early. */
14754 switch (mode_cmd
->pixel_format
) {
14755 case DRM_FORMAT_C8
:
14756 case DRM_FORMAT_RGB565
:
14757 case DRM_FORMAT_XRGB8888
:
14758 case DRM_FORMAT_ARGB8888
:
14760 case DRM_FORMAT_XRGB1555
:
14761 if (INTEL_INFO(dev
)->gen
> 3) {
14762 DRM_DEBUG("unsupported pixel format: %s\n",
14763 drm_get_format_name(mode_cmd
->pixel_format
));
14767 case DRM_FORMAT_ABGR8888
:
14768 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
14769 INTEL_INFO(dev
)->gen
< 9) {
14770 DRM_DEBUG("unsupported pixel format: %s\n",
14771 drm_get_format_name(mode_cmd
->pixel_format
));
14775 case DRM_FORMAT_XBGR8888
:
14776 case DRM_FORMAT_XRGB2101010
:
14777 case DRM_FORMAT_XBGR2101010
:
14778 if (INTEL_INFO(dev
)->gen
< 4) {
14779 DRM_DEBUG("unsupported pixel format: %s\n",
14780 drm_get_format_name(mode_cmd
->pixel_format
));
14784 case DRM_FORMAT_ABGR2101010
:
14785 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
14786 DRM_DEBUG("unsupported pixel format: %s\n",
14787 drm_get_format_name(mode_cmd
->pixel_format
));
14791 case DRM_FORMAT_YUYV
:
14792 case DRM_FORMAT_UYVY
:
14793 case DRM_FORMAT_YVYU
:
14794 case DRM_FORMAT_VYUY
:
14795 if (INTEL_INFO(dev
)->gen
< 5) {
14796 DRM_DEBUG("unsupported pixel format: %s\n",
14797 drm_get_format_name(mode_cmd
->pixel_format
));
14802 DRM_DEBUG("unsupported pixel format: %s\n",
14803 drm_get_format_name(mode_cmd
->pixel_format
));
14807 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14808 if (mode_cmd
->offsets
[0] != 0)
14811 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
14812 mode_cmd
->pixel_format
,
14813 mode_cmd
->modifier
[0]);
14814 /* FIXME drm helper for size checks (especially planar formats)? */
14815 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
14818 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
14819 intel_fb
->obj
= obj
;
14821 intel_fill_fb_info(dev_priv
, &intel_fb
->base
);
14823 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
14825 DRM_ERROR("framebuffer init failed %d\n", ret
);
14829 intel_fb
->obj
->framebuffer_references
++;
14834 static struct drm_framebuffer
*
14835 intel_user_framebuffer_create(struct drm_device
*dev
,
14836 struct drm_file
*filp
,
14837 const struct drm_mode_fb_cmd2
*user_mode_cmd
)
14839 struct drm_framebuffer
*fb
;
14840 struct drm_i915_gem_object
*obj
;
14841 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
14843 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
14844 mode_cmd
.handles
[0]));
14845 if (&obj
->base
== NULL
)
14846 return ERR_PTR(-ENOENT
);
14848 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
14850 drm_gem_object_unreference_unlocked(&obj
->base
);
14855 #ifndef CONFIG_DRM_FBDEV_EMULATION
14856 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
14861 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14862 .fb_create
= intel_user_framebuffer_create
,
14863 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14864 .atomic_check
= intel_atomic_check
,
14865 .atomic_commit
= intel_atomic_commit
,
14866 .atomic_state_alloc
= intel_atomic_state_alloc
,
14867 .atomic_state_clear
= intel_atomic_state_clear
,
14871 * intel_init_display_hooks - initialize the display modesetting hooks
14872 * @dev_priv: device private
14874 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
14876 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
14877 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14878 dev_priv
->display
.get_initial_plane_config
=
14879 skylake_get_initial_plane_config
;
14880 dev_priv
->display
.crtc_compute_clock
=
14881 haswell_crtc_compute_clock
;
14882 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14883 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14884 } else if (HAS_DDI(dev_priv
)) {
14885 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14886 dev_priv
->display
.get_initial_plane_config
=
14887 ironlake_get_initial_plane_config
;
14888 dev_priv
->display
.crtc_compute_clock
=
14889 haswell_crtc_compute_clock
;
14890 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14891 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14892 } else if (HAS_PCH_SPLIT(dev_priv
)) {
14893 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14894 dev_priv
->display
.get_initial_plane_config
=
14895 ironlake_get_initial_plane_config
;
14896 dev_priv
->display
.crtc_compute_clock
=
14897 ironlake_crtc_compute_clock
;
14898 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14899 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14900 } else if (IS_CHERRYVIEW(dev_priv
)) {
14901 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14902 dev_priv
->display
.get_initial_plane_config
=
14903 i9xx_get_initial_plane_config
;
14904 dev_priv
->display
.crtc_compute_clock
= chv_crtc_compute_clock
;
14905 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14906 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14907 } else if (IS_VALLEYVIEW(dev_priv
)) {
14908 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14909 dev_priv
->display
.get_initial_plane_config
=
14910 i9xx_get_initial_plane_config
;
14911 dev_priv
->display
.crtc_compute_clock
= vlv_crtc_compute_clock
;
14912 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14913 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14914 } else if (IS_G4X(dev_priv
)) {
14915 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14916 dev_priv
->display
.get_initial_plane_config
=
14917 i9xx_get_initial_plane_config
;
14918 dev_priv
->display
.crtc_compute_clock
= g4x_crtc_compute_clock
;
14919 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14920 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14921 } else if (IS_PINEVIEW(dev_priv
)) {
14922 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14923 dev_priv
->display
.get_initial_plane_config
=
14924 i9xx_get_initial_plane_config
;
14925 dev_priv
->display
.crtc_compute_clock
= pnv_crtc_compute_clock
;
14926 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14927 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14928 } else if (!IS_GEN2(dev_priv
)) {
14929 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14930 dev_priv
->display
.get_initial_plane_config
=
14931 i9xx_get_initial_plane_config
;
14932 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14933 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14934 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14936 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14937 dev_priv
->display
.get_initial_plane_config
=
14938 i9xx_get_initial_plane_config
;
14939 dev_priv
->display
.crtc_compute_clock
= i8xx_crtc_compute_clock
;
14940 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14941 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14944 /* Returns the core display clock speed */
14945 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
14946 dev_priv
->display
.get_display_clock_speed
=
14947 skylake_get_display_clock_speed
;
14948 else if (IS_BROXTON(dev_priv
))
14949 dev_priv
->display
.get_display_clock_speed
=
14950 broxton_get_display_clock_speed
;
14951 else if (IS_BROADWELL(dev_priv
))
14952 dev_priv
->display
.get_display_clock_speed
=
14953 broadwell_get_display_clock_speed
;
14954 else if (IS_HASWELL(dev_priv
))
14955 dev_priv
->display
.get_display_clock_speed
=
14956 haswell_get_display_clock_speed
;
14957 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
14958 dev_priv
->display
.get_display_clock_speed
=
14959 valleyview_get_display_clock_speed
;
14960 else if (IS_GEN5(dev_priv
))
14961 dev_priv
->display
.get_display_clock_speed
=
14962 ilk_get_display_clock_speed
;
14963 else if (IS_I945G(dev_priv
) || IS_BROADWATER(dev_priv
) ||
14964 IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
))
14965 dev_priv
->display
.get_display_clock_speed
=
14966 i945_get_display_clock_speed
;
14967 else if (IS_GM45(dev_priv
))
14968 dev_priv
->display
.get_display_clock_speed
=
14969 gm45_get_display_clock_speed
;
14970 else if (IS_CRESTLINE(dev_priv
))
14971 dev_priv
->display
.get_display_clock_speed
=
14972 i965gm_get_display_clock_speed
;
14973 else if (IS_PINEVIEW(dev_priv
))
14974 dev_priv
->display
.get_display_clock_speed
=
14975 pnv_get_display_clock_speed
;
14976 else if (IS_G33(dev_priv
) || IS_G4X(dev_priv
))
14977 dev_priv
->display
.get_display_clock_speed
=
14978 g33_get_display_clock_speed
;
14979 else if (IS_I915G(dev_priv
))
14980 dev_priv
->display
.get_display_clock_speed
=
14981 i915_get_display_clock_speed
;
14982 else if (IS_I945GM(dev_priv
) || IS_845G(dev_priv
))
14983 dev_priv
->display
.get_display_clock_speed
=
14984 i9xx_misc_get_display_clock_speed
;
14985 else if (IS_I915GM(dev_priv
))
14986 dev_priv
->display
.get_display_clock_speed
=
14987 i915gm_get_display_clock_speed
;
14988 else if (IS_I865G(dev_priv
))
14989 dev_priv
->display
.get_display_clock_speed
=
14990 i865_get_display_clock_speed
;
14991 else if (IS_I85X(dev_priv
))
14992 dev_priv
->display
.get_display_clock_speed
=
14993 i85x_get_display_clock_speed
;
14995 WARN(!IS_I830(dev_priv
), "Unknown platform. Assuming 133 MHz CDCLK\n");
14996 dev_priv
->display
.get_display_clock_speed
=
14997 i830_get_display_clock_speed
;
15000 if (IS_GEN5(dev_priv
)) {
15001 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
15002 } else if (IS_GEN6(dev_priv
)) {
15003 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
15004 } else if (IS_IVYBRIDGE(dev_priv
)) {
15005 /* FIXME: detect B0+ stepping and use auto training */
15006 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
15007 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
15008 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
15009 if (IS_BROADWELL(dev_priv
)) {
15010 dev_priv
->display
.modeset_commit_cdclk
=
15011 broadwell_modeset_commit_cdclk
;
15012 dev_priv
->display
.modeset_calc_cdclk
=
15013 broadwell_modeset_calc_cdclk
;
15015 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
15016 dev_priv
->display
.modeset_commit_cdclk
=
15017 valleyview_modeset_commit_cdclk
;
15018 dev_priv
->display
.modeset_calc_cdclk
=
15019 valleyview_modeset_calc_cdclk
;
15020 } else if (IS_BROXTON(dev_priv
)) {
15021 dev_priv
->display
.modeset_commit_cdclk
=
15022 broxton_modeset_commit_cdclk
;
15023 dev_priv
->display
.modeset_calc_cdclk
=
15024 broxton_modeset_calc_cdclk
;
15027 switch (INTEL_INFO(dev_priv
)->gen
) {
15029 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
15033 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
15038 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
15042 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
15045 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15046 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
15049 /* Drop through - unsupported since execlist only. */
15051 /* Default just returns -ENODEV to indicate unsupported */
15052 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
15057 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15058 * resume, or other times. This quirk makes sure that's the case for
15059 * affected systems.
15061 static void quirk_pipea_force(struct drm_device
*dev
)
15063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15065 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
15066 DRM_INFO("applying pipe a force quirk\n");
15069 static void quirk_pipeb_force(struct drm_device
*dev
)
15071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15073 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
15074 DRM_INFO("applying pipe b force quirk\n");
15078 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15080 static void quirk_ssc_force_disable(struct drm_device
*dev
)
15082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15083 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
15084 DRM_INFO("applying lvds SSC disable quirk\n");
15088 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15091 static void quirk_invert_brightness(struct drm_device
*dev
)
15093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15094 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
15095 DRM_INFO("applying inverted panel brightness quirk\n");
15098 /* Some VBT's incorrectly indicate no backlight is present */
15099 static void quirk_backlight_present(struct drm_device
*dev
)
15101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15102 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
15103 DRM_INFO("applying backlight present quirk\n");
15106 struct intel_quirk
{
15108 int subsystem_vendor
;
15109 int subsystem_device
;
15110 void (*hook
)(struct drm_device
*dev
);
15113 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15114 struct intel_dmi_quirk
{
15115 void (*hook
)(struct drm_device
*dev
);
15116 const struct dmi_system_id (*dmi_id_list
)[];
15119 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
15121 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
15125 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
15127 .dmi_id_list
= &(const struct dmi_system_id
[]) {
15129 .callback
= intel_dmi_reverse_brightness
,
15130 .ident
= "NCR Corporation",
15131 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
15132 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
15135 { } /* terminating entry */
15137 .hook
= quirk_invert_brightness
,
15141 static struct intel_quirk intel_quirks
[] = {
15142 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15143 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
15145 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15146 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
15148 /* 830 needs to leave pipe A & dpll A up */
15149 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
15151 /* 830 needs to leave pipe B & dpll B up */
15152 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
15154 /* Lenovo U160 cannot use SSC on LVDS */
15155 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
15157 /* Sony Vaio Y cannot use SSC on LVDS */
15158 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
15160 /* Acer Aspire 5734Z must invert backlight brightness */
15161 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
15163 /* Acer/eMachines G725 */
15164 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
15166 /* Acer/eMachines e725 */
15167 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
15169 /* Acer/Packard Bell NCL20 */
15170 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
15172 /* Acer Aspire 4736Z */
15173 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
15175 /* Acer Aspire 5336 */
15176 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
15178 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15179 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
15181 /* Acer C720 Chromebook (Core i3 4005U) */
15182 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
15184 /* Apple Macbook 2,1 (Core 2 T7400) */
15185 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
15187 /* Apple Macbook 4,1 */
15188 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present
},
15190 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15191 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
15193 /* HP Chromebook 14 (Celeron 2955U) */
15194 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
15196 /* Dell Chromebook 11 */
15197 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
15199 /* Dell Chromebook 11 (2015 version) */
15200 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present
},
15203 static void intel_init_quirks(struct drm_device
*dev
)
15205 struct pci_dev
*d
= dev
->pdev
;
15208 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
15209 struct intel_quirk
*q
= &intel_quirks
[i
];
15211 if (d
->device
== q
->device
&&
15212 (d
->subsystem_vendor
== q
->subsystem_vendor
||
15213 q
->subsystem_vendor
== PCI_ANY_ID
) &&
15214 (d
->subsystem_device
== q
->subsystem_device
||
15215 q
->subsystem_device
== PCI_ANY_ID
))
15218 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
15219 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
15220 intel_dmi_quirks
[i
].hook(dev
);
15224 /* Disable the VGA plane that we never use */
15225 static void i915_disable_vga(struct drm_device
*dev
)
15227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15229 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev
);
15231 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15232 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15233 outb(SR01
, VGA_SR_INDEX
);
15234 sr1
= inb(VGA_SR_DATA
);
15235 outb(sr1
| 1<<5, VGA_SR_DATA
);
15236 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15239 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
15240 POSTING_READ(vga_reg
);
15243 void intel_modeset_init_hw(struct drm_device
*dev
)
15245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15247 intel_update_cdclk(dev
);
15249 dev_priv
->atomic_cdclk_freq
= dev_priv
->cdclk_freq
;
15251 intel_init_clock_gating(dev
);
15252 intel_enable_gt_powersave(dev
);
15256 * Calculate what we think the watermarks should be for the state we've read
15257 * out of the hardware and then immediately program those watermarks so that
15258 * we ensure the hardware settings match our internal state.
15260 * We can calculate what we think WM's should be by creating a duplicate of the
15261 * current state (which was constructed during hardware readout) and running it
15262 * through the atomic check code to calculate new watermark values in the
15265 static void sanitize_watermarks(struct drm_device
*dev
)
15267 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15268 struct drm_atomic_state
*state
;
15269 struct drm_crtc
*crtc
;
15270 struct drm_crtc_state
*cstate
;
15271 struct drm_modeset_acquire_ctx ctx
;
15275 /* Only supported on platforms that use atomic watermark design */
15276 if (!dev_priv
->display
.optimize_watermarks
)
15280 * We need to hold connection_mutex before calling duplicate_state so
15281 * that the connector loop is protected.
15283 drm_modeset_acquire_init(&ctx
, 0);
15285 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
15286 if (ret
== -EDEADLK
) {
15287 drm_modeset_backoff(&ctx
);
15289 } else if (WARN_ON(ret
)) {
15293 state
= drm_atomic_helper_duplicate_state(dev
, &ctx
);
15294 if (WARN_ON(IS_ERR(state
)))
15298 * Hardware readout is the only time we don't want to calculate
15299 * intermediate watermarks (since we don't trust the current
15302 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
15304 ret
= intel_atomic_check(dev
, state
);
15307 * If we fail here, it means that the hardware appears to be
15308 * programmed in a way that shouldn't be possible, given our
15309 * understanding of watermark requirements. This might mean a
15310 * mistake in the hardware readout code or a mistake in the
15311 * watermark calculations for a given platform. Raise a WARN
15312 * so that this is noticeable.
15314 * If this actually happens, we'll have to just leave the
15315 * BIOS-programmed watermarks untouched and hope for the best.
15317 WARN(true, "Could not determine valid watermarks for inherited state\n");
15321 /* Write calculated watermark values back */
15322 to_i915(dev
)->wm
.config
= to_intel_atomic_state(state
)->wm_config
;
15323 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
15324 struct intel_crtc_state
*cs
= to_intel_crtc_state(cstate
);
15326 cs
->wm
.need_postvbl_update
= true;
15327 dev_priv
->display
.optimize_watermarks(cs
);
15330 drm_atomic_state_free(state
);
15332 drm_modeset_drop_locks(&ctx
);
15333 drm_modeset_acquire_fini(&ctx
);
15336 void intel_modeset_init(struct drm_device
*dev
)
15338 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15339 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
15342 struct intel_crtc
*crtc
;
15344 drm_mode_config_init(dev
);
15346 dev
->mode_config
.min_width
= 0;
15347 dev
->mode_config
.min_height
= 0;
15349 dev
->mode_config
.preferred_depth
= 24;
15350 dev
->mode_config
.prefer_shadow
= 1;
15352 dev
->mode_config
.allow_fb_modifiers
= true;
15354 dev
->mode_config
.funcs
= &intel_mode_funcs
;
15356 intel_init_quirks(dev
);
15358 intel_init_pm(dev
);
15360 if (INTEL_INFO(dev
)->num_pipes
== 0)
15364 * There may be no VBT; and if the BIOS enabled SSC we can
15365 * just keep using it to avoid unnecessary flicker. Whereas if the
15366 * BIOS isn't using it, don't assume it will work even if the VBT
15367 * indicates as much.
15369 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
15370 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15373 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
15374 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15375 bios_lvds_use_ssc
? "en" : "dis",
15376 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
15377 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
15381 if (IS_GEN2(dev
)) {
15382 dev
->mode_config
.max_width
= 2048;
15383 dev
->mode_config
.max_height
= 2048;
15384 } else if (IS_GEN3(dev
)) {
15385 dev
->mode_config
.max_width
= 4096;
15386 dev
->mode_config
.max_height
= 4096;
15388 dev
->mode_config
.max_width
= 8192;
15389 dev
->mode_config
.max_height
= 8192;
15392 if (IS_845G(dev
) || IS_I865G(dev
)) {
15393 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
15394 dev
->mode_config
.cursor_height
= 1023;
15395 } else if (IS_GEN2(dev
)) {
15396 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
15397 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
15399 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
15400 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
15403 dev
->mode_config
.fb_base
= ggtt
->mappable_base
;
15405 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15406 INTEL_INFO(dev
)->num_pipes
,
15407 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
15409 for_each_pipe(dev_priv
, pipe
) {
15410 intel_crtc_init(dev
, pipe
);
15411 for_each_sprite(dev_priv
, pipe
, sprite
) {
15412 ret
= intel_plane_init(dev
, pipe
, sprite
);
15414 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15415 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
15419 intel_update_czclk(dev_priv
);
15420 intel_update_rawclk(dev_priv
);
15421 intel_update_cdclk(dev
);
15423 intel_shared_dpll_init(dev
);
15425 /* Just disable it once at startup */
15426 i915_disable_vga(dev
);
15427 intel_setup_outputs(dev
);
15429 drm_modeset_lock_all(dev
);
15430 intel_modeset_setup_hw_state(dev
);
15431 drm_modeset_unlock_all(dev
);
15433 for_each_intel_crtc(dev
, crtc
) {
15434 struct intel_initial_plane_config plane_config
= {};
15440 * Note that reserving the BIOS fb up front prevents us
15441 * from stuffing other stolen allocations like the ring
15442 * on top. This prevents some ugliness at boot time, and
15443 * can even allow for smooth boot transitions if the BIOS
15444 * fb is large enough for the active pipe configuration.
15446 dev_priv
->display
.get_initial_plane_config(crtc
,
15450 * If the fb is shared between multiple heads, we'll
15451 * just get the first one.
15453 intel_find_initial_plane_obj(crtc
, &plane_config
);
15457 * Make sure hardware watermarks really match the state we read out.
15458 * Note that we need to do this after reconstructing the BIOS fb's
15459 * since the watermark calculation done here will use pstate->fb.
15461 sanitize_watermarks(dev
);
15464 static void intel_enable_pipe_a(struct drm_device
*dev
)
15466 struct intel_connector
*connector
;
15467 struct drm_connector
*crt
= NULL
;
15468 struct intel_load_detect_pipe load_detect_temp
;
15469 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
15471 /* We can't just switch on the pipe A, we need to set things up with a
15472 * proper mode and output configuration. As a gross hack, enable pipe A
15473 * by enabling the load detect pipe once. */
15474 for_each_intel_connector(dev
, connector
) {
15475 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
15476 crt
= &connector
->base
;
15484 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
15485 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
15489 intel_check_plane_mapping(struct intel_crtc
*crtc
)
15491 struct drm_device
*dev
= crtc
->base
.dev
;
15492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15495 if (INTEL_INFO(dev
)->num_pipes
== 1)
15498 val
= I915_READ(DSPCNTR(!crtc
->plane
));
15500 if ((val
& DISPLAY_PLANE_ENABLE
) &&
15501 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
15507 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
15509 struct drm_device
*dev
= crtc
->base
.dev
;
15510 struct intel_encoder
*encoder
;
15512 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
15518 static bool intel_encoder_has_connectors(struct intel_encoder
*encoder
)
15520 struct drm_device
*dev
= encoder
->base
.dev
;
15521 struct intel_connector
*connector
;
15523 for_each_connector_on_encoder(dev
, &encoder
->base
, connector
)
15529 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
15531 struct drm_device
*dev
= crtc
->base
.dev
;
15532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15533 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
15535 /* Clear any frame start delays used for debugging left by the BIOS */
15536 if (!transcoder_is_dsi(cpu_transcoder
)) {
15537 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
15540 I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
15543 /* restore vblank interrupts to correct state */
15544 drm_crtc_vblank_reset(&crtc
->base
);
15545 if (crtc
->active
) {
15546 struct intel_plane
*plane
;
15548 drm_crtc_vblank_on(&crtc
->base
);
15550 /* Disable everything but the primary plane */
15551 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
15552 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
15555 plane
->disable_plane(&plane
->base
, &crtc
->base
);
15559 /* We need to sanitize the plane -> pipe mapping first because this will
15560 * disable the crtc (and hence change the state) if it is wrong. Note
15561 * that gen4+ has a fixed plane -> pipe mapping. */
15562 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
15565 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15566 crtc
->base
.base
.id
);
15568 /* Pipe has the wrong plane attached and the plane is active.
15569 * Temporarily change the plane mapping and disable everything
15571 plane
= crtc
->plane
;
15572 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
15573 crtc
->plane
= !plane
;
15574 intel_crtc_disable_noatomic(&crtc
->base
);
15575 crtc
->plane
= plane
;
15578 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
15579 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
15580 /* BIOS forgot to enable pipe A, this mostly happens after
15581 * resume. Force-enable the pipe to fix this, the update_dpms
15582 * call below we restore the pipe to the right state, but leave
15583 * the required bits on. */
15584 intel_enable_pipe_a(dev
);
15587 /* Adjust the state of the output pipe according to whether we
15588 * have active connectors/encoders. */
15589 if (crtc
->active
&& !intel_crtc_has_encoders(crtc
))
15590 intel_crtc_disable_noatomic(&crtc
->base
);
15592 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
15594 * We start out with underrun reporting disabled to avoid races.
15595 * For correct bookkeeping mark this on active crtcs.
15597 * Also on gmch platforms we dont have any hardware bits to
15598 * disable the underrun reporting. Which means we need to start
15599 * out with underrun reporting disabled also on inactive pipes,
15600 * since otherwise we'll complain about the garbage we read when
15601 * e.g. coming up after runtime pm.
15603 * No protection against concurrent access is required - at
15604 * worst a fifo underrun happens which also sets this to false.
15606 crtc
->cpu_fifo_underrun_disabled
= true;
15607 crtc
->pch_fifo_underrun_disabled
= true;
15611 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
15613 struct intel_connector
*connector
;
15614 struct drm_device
*dev
= encoder
->base
.dev
;
15616 /* We need to check both for a crtc link (meaning that the
15617 * encoder is active and trying to read from a pipe) and the
15618 * pipe itself being active. */
15619 bool has_active_crtc
= encoder
->base
.crtc
&&
15620 to_intel_crtc(encoder
->base
.crtc
)->active
;
15622 if (intel_encoder_has_connectors(encoder
) && !has_active_crtc
) {
15623 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15624 encoder
->base
.base
.id
,
15625 encoder
->base
.name
);
15627 /* Connector is active, but has no active pipe. This is
15628 * fallout from our resume register restoring. Disable
15629 * the encoder manually again. */
15630 if (encoder
->base
.crtc
) {
15631 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15632 encoder
->base
.base
.id
,
15633 encoder
->base
.name
);
15634 encoder
->disable(encoder
);
15635 if (encoder
->post_disable
)
15636 encoder
->post_disable(encoder
);
15638 encoder
->base
.crtc
= NULL
;
15640 /* Inconsistent output/port/pipe state happens presumably due to
15641 * a bug in one of the get_hw_state functions. Or someplace else
15642 * in our code, like the register restore mess on resume. Clamp
15643 * things to off as a safer default. */
15644 for_each_intel_connector(dev
, connector
) {
15645 if (connector
->encoder
!= encoder
)
15647 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15648 connector
->base
.encoder
= NULL
;
15651 /* Enabled encoders without active connectors will be fixed in
15652 * the crtc fixup. */
15655 void i915_redisable_vga_power_on(struct drm_device
*dev
)
15657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15658 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev
);
15660 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
15661 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15662 i915_disable_vga(dev
);
15666 void i915_redisable_vga(struct drm_device
*dev
)
15668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15670 /* This function can be called both from intel_modeset_setup_hw_state or
15671 * at a very early point in our resume sequence, where the power well
15672 * structures are not yet restored. Since this function is at a very
15673 * paranoid "someone might have enabled VGA while we were not looking"
15674 * level, just check if the power well is enabled instead of trying to
15675 * follow the "don't touch the power well if we don't need it" policy
15676 * the rest of the driver uses. */
15677 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_VGA
))
15680 i915_redisable_vga_power_on(dev
);
15682 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
);
15685 static bool primary_get_hw_state(struct intel_plane
*plane
)
15687 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
15689 return I915_READ(DSPCNTR(plane
->plane
)) & DISPLAY_PLANE_ENABLE
;
15692 /* FIXME read out full plane state for all planes */
15693 static void readout_plane_state(struct intel_crtc
*crtc
)
15695 struct drm_plane
*primary
= crtc
->base
.primary
;
15696 struct intel_plane_state
*plane_state
=
15697 to_intel_plane_state(primary
->state
);
15699 plane_state
->visible
= crtc
->active
&&
15700 primary_get_hw_state(to_intel_plane(primary
));
15702 if (plane_state
->visible
)
15703 crtc
->base
.state
->plane_mask
|= 1 << drm_plane_index(primary
);
15706 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
15708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15710 struct intel_crtc
*crtc
;
15711 struct intel_encoder
*encoder
;
15712 struct intel_connector
*connector
;
15715 dev_priv
->active_crtcs
= 0;
15717 for_each_intel_crtc(dev
, crtc
) {
15718 struct intel_crtc_state
*crtc_state
= crtc
->config
;
15721 __drm_atomic_helper_crtc_destroy_state(&crtc
->base
, &crtc_state
->base
);
15722 memset(crtc_state
, 0, sizeof(*crtc_state
));
15723 crtc_state
->base
.crtc
= &crtc
->base
;
15725 crtc_state
->base
.active
= crtc_state
->base
.enable
=
15726 dev_priv
->display
.get_pipe_config(crtc
, crtc_state
);
15728 crtc
->base
.enabled
= crtc_state
->base
.enable
;
15729 crtc
->active
= crtc_state
->base
.active
;
15731 if (crtc_state
->base
.active
) {
15732 dev_priv
->active_crtcs
|= 1 << crtc
->pipe
;
15734 if (IS_BROADWELL(dev_priv
)) {
15735 pixclk
= ilk_pipe_pixel_rate(crtc_state
);
15737 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15738 if (crtc_state
->ips_enabled
)
15739 pixclk
= DIV_ROUND_UP(pixclk
* 100, 95);
15740 } else if (IS_VALLEYVIEW(dev_priv
) ||
15741 IS_CHERRYVIEW(dev_priv
) ||
15742 IS_BROXTON(dev_priv
))
15743 pixclk
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
15745 WARN_ON(dev_priv
->display
.modeset_calc_cdclk
);
15748 dev_priv
->min_pixclk
[crtc
->pipe
] = pixclk
;
15750 readout_plane_state(crtc
);
15752 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15753 crtc
->base
.base
.id
,
15754 crtc
->active
? "enabled" : "disabled");
15757 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15758 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15760 pll
->on
= pll
->funcs
.get_hw_state(dev_priv
, pll
,
15761 &pll
->config
.hw_state
);
15762 pll
->config
.crtc_mask
= 0;
15763 for_each_intel_crtc(dev
, crtc
) {
15764 if (crtc
->active
&& crtc
->config
->shared_dpll
== pll
)
15765 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
15767 pll
->active_mask
= pll
->config
.crtc_mask
;
15769 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15770 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
15773 for_each_intel_encoder(dev
, encoder
) {
15776 if (encoder
->get_hw_state(encoder
, &pipe
)) {
15777 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15778 encoder
->base
.crtc
= &crtc
->base
;
15779 encoder
->get_config(encoder
, crtc
->config
);
15781 encoder
->base
.crtc
= NULL
;
15784 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15785 encoder
->base
.base
.id
,
15786 encoder
->base
.name
,
15787 encoder
->base
.crtc
? "enabled" : "disabled",
15791 for_each_intel_connector(dev
, connector
) {
15792 if (connector
->get_hw_state(connector
)) {
15793 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
15795 encoder
= connector
->encoder
;
15796 connector
->base
.encoder
= &encoder
->base
;
15798 if (encoder
->base
.crtc
&&
15799 encoder
->base
.crtc
->state
->active
) {
15801 * This has to be done during hardware readout
15802 * because anything calling .crtc_disable may
15803 * rely on the connector_mask being accurate.
15805 encoder
->base
.crtc
->state
->connector_mask
|=
15806 1 << drm_connector_index(&connector
->base
);
15807 encoder
->base
.crtc
->state
->encoder_mask
|=
15808 1 << drm_encoder_index(&encoder
->base
);
15812 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15813 connector
->base
.encoder
= NULL
;
15815 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15816 connector
->base
.base
.id
,
15817 connector
->base
.name
,
15818 connector
->base
.encoder
? "enabled" : "disabled");
15821 for_each_intel_crtc(dev
, crtc
) {
15822 crtc
->base
.hwmode
= crtc
->config
->base
.adjusted_mode
;
15824 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
15825 if (crtc
->base
.state
->active
) {
15826 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc
->config
);
15827 intel_mode_from_pipe_config(&crtc
->base
.state
->adjusted_mode
, crtc
->config
);
15828 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
15831 * The initial mode needs to be set in order to keep
15832 * the atomic core happy. It wants a valid mode if the
15833 * crtc's enabled, so we do the above call.
15835 * At this point some state updated by the connectors
15836 * in their ->detect() callback has not run yet, so
15837 * no recalculation can be done yet.
15839 * Even if we could do a recalculation and modeset
15840 * right now it would cause a double modeset if
15841 * fbdev or userspace chooses a different initial mode.
15843 * If that happens, someone indicated they wanted a
15844 * mode change, which means it's safe to do a full
15847 crtc
->base
.state
->mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
15849 drm_calc_timestamping_constants(&crtc
->base
, &crtc
->base
.hwmode
);
15850 update_scanline_offset(crtc
);
15853 intel_pipe_config_sanity_check(dev_priv
, crtc
->config
);
15857 /* Scan out the current hw modeset state,
15858 * and sanitizes it to the current state
15861 intel_modeset_setup_hw_state(struct drm_device
*dev
)
15863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15865 struct intel_crtc
*crtc
;
15866 struct intel_encoder
*encoder
;
15869 intel_modeset_readout_hw_state(dev
);
15871 /* HW state is read out, now we need to sanitize this mess. */
15872 for_each_intel_encoder(dev
, encoder
) {
15873 intel_sanitize_encoder(encoder
);
15876 for_each_pipe(dev_priv
, pipe
) {
15877 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15878 intel_sanitize_crtc(crtc
);
15879 intel_dump_pipe_config(crtc
, crtc
->config
,
15880 "[setup_hw_state]");
15883 intel_modeset_update_connector_atomic_state(dev
);
15885 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15886 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15888 if (!pll
->on
|| pll
->active_mask
)
15891 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
15893 pll
->funcs
.disable(dev_priv
, pll
);
15897 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
15898 vlv_wm_get_hw_state(dev
);
15899 else if (IS_GEN9(dev
))
15900 skl_wm_get_hw_state(dev
);
15901 else if (HAS_PCH_SPLIT(dev
))
15902 ilk_wm_get_hw_state(dev
);
15904 for_each_intel_crtc(dev
, crtc
) {
15905 unsigned long put_domains
;
15907 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
, crtc
->config
);
15908 if (WARN_ON(put_domains
))
15909 modeset_put_power_domains(dev_priv
, put_domains
);
15911 intel_display_set_init_power(dev_priv
, false);
15913 intel_fbc_init_pipe_state(dev_priv
);
15916 void intel_display_resume(struct drm_device
*dev
)
15918 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15919 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
15920 struct drm_modeset_acquire_ctx ctx
;
15922 bool setup
= false;
15924 dev_priv
->modeset_restore_state
= NULL
;
15927 * This is a cludge because with real atomic modeset mode_config.mutex
15928 * won't be taken. Unfortunately some probed state like
15929 * audio_codec_enable is still protected by mode_config.mutex, so lock
15932 mutex_lock(&dev
->mode_config
.mutex
);
15933 drm_modeset_acquire_init(&ctx
, 0);
15936 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
15938 if (ret
== 0 && !setup
) {
15941 intel_modeset_setup_hw_state(dev
);
15942 i915_redisable_vga(dev
);
15945 if (ret
== 0 && state
) {
15946 struct drm_crtc_state
*crtc_state
;
15947 struct drm_crtc
*crtc
;
15950 state
->acquire_ctx
= &ctx
;
15952 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
15954 * Force recalculation even if we restore
15955 * current state. With fast modeset this may not result
15956 * in a modeset when the state is compatible.
15958 crtc_state
->mode_changed
= true;
15961 ret
= drm_atomic_commit(state
);
15964 if (ret
== -EDEADLK
) {
15965 drm_modeset_backoff(&ctx
);
15969 drm_modeset_drop_locks(&ctx
);
15970 drm_modeset_acquire_fini(&ctx
);
15971 mutex_unlock(&dev
->mode_config
.mutex
);
15974 DRM_ERROR("Restoring old state failed with %i\n", ret
);
15975 drm_atomic_state_free(state
);
15979 void intel_modeset_gem_init(struct drm_device
*dev
)
15981 struct drm_crtc
*c
;
15982 struct drm_i915_gem_object
*obj
;
15985 intel_init_gt_powersave(dev
);
15987 intel_modeset_init_hw(dev
);
15989 intel_setup_overlay(dev
);
15992 * Make sure any fbs we allocated at startup are properly
15993 * pinned & fenced. When we do the allocation it's too early
15996 for_each_crtc(dev
, c
) {
15997 obj
= intel_fb_obj(c
->primary
->fb
);
16001 mutex_lock(&dev
->struct_mutex
);
16002 ret
= intel_pin_and_fence_fb_obj(c
->primary
->fb
,
16003 c
->primary
->state
->rotation
);
16004 mutex_unlock(&dev
->struct_mutex
);
16006 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16007 to_intel_crtc(c
)->pipe
);
16008 drm_framebuffer_unreference(c
->primary
->fb
);
16009 c
->primary
->fb
= NULL
;
16010 c
->primary
->crtc
= c
->primary
->state
->crtc
= NULL
;
16011 update_state_fb(c
->primary
);
16012 c
->state
->plane_mask
&= ~(1 << drm_plane_index(c
->primary
));
16016 intel_backlight_register(dev
);
16019 void intel_connector_unregister(struct intel_connector
*intel_connector
)
16021 struct drm_connector
*connector
= &intel_connector
->base
;
16023 intel_panel_destroy_backlight(connector
);
16024 drm_connector_unregister(connector
);
16027 void intel_modeset_cleanup(struct drm_device
*dev
)
16029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
16030 struct intel_connector
*connector
;
16032 intel_disable_gt_powersave(dev
);
16034 intel_backlight_unregister(dev
);
16037 * Interrupts and polling as the first thing to avoid creating havoc.
16038 * Too much stuff here (turning of connectors, ...) would
16039 * experience fancy races otherwise.
16041 intel_irq_uninstall(dev_priv
);
16044 * Due to the hpd irq storm handling the hotplug work can re-arm the
16045 * poll handlers. Hence disable polling after hpd handling is shut down.
16047 drm_kms_helper_poll_fini(dev
);
16049 intel_unregister_dsm_handler();
16051 intel_fbc_global_disable(dev_priv
);
16053 /* flush any delayed tasks or pending work */
16054 flush_scheduled_work();
16056 /* destroy the backlight and sysfs files before encoders/connectors */
16057 for_each_intel_connector(dev
, connector
)
16058 connector
->unregister(connector
);
16060 drm_mode_config_cleanup(dev
);
16062 intel_cleanup_overlay(dev
);
16064 intel_cleanup_gt_powersave(dev
);
16066 intel_teardown_gmbus(dev
);
16070 * Return which encoder is currently attached for connector.
16072 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
16074 return &intel_attached_encoder(connector
)->base
;
16077 void intel_connector_attach_encoder(struct intel_connector
*connector
,
16078 struct intel_encoder
*encoder
)
16080 connector
->encoder
= encoder
;
16081 drm_mode_connector_attach_encoder(&connector
->base
,
16086 * set vga decode state - true == enable VGA decode
16088 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
16090 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
16091 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
16094 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
16095 DRM_ERROR("failed to read control word\n");
16099 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
16103 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
16105 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
16107 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
16108 DRM_ERROR("failed to write control word\n");
16115 struct intel_display_error_state
{
16117 u32 power_well_driver
;
16119 int num_transcoders
;
16121 struct intel_cursor_error_state
{
16126 } cursor
[I915_MAX_PIPES
];
16128 struct intel_pipe_error_state
{
16129 bool power_domain_on
;
16132 } pipe
[I915_MAX_PIPES
];
16134 struct intel_plane_error_state
{
16142 } plane
[I915_MAX_PIPES
];
16144 struct intel_transcoder_error_state
{
16145 bool power_domain_on
;
16146 enum transcoder cpu_transcoder
;
16159 struct intel_display_error_state
*
16160 intel_display_capture_error_state(struct drm_device
*dev
)
16162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
16163 struct intel_display_error_state
*error
;
16164 int transcoders
[] = {
16172 if (INTEL_INFO(dev
)->num_pipes
== 0)
16175 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
16179 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
16180 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
16182 for_each_pipe(dev_priv
, i
) {
16183 error
->pipe
[i
].power_domain_on
=
16184 __intel_display_power_is_enabled(dev_priv
,
16185 POWER_DOMAIN_PIPE(i
));
16186 if (!error
->pipe
[i
].power_domain_on
)
16189 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
16190 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
16191 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
16193 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
16194 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
16195 if (INTEL_INFO(dev
)->gen
<= 3) {
16196 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
16197 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
16199 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
16200 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
16201 if (INTEL_INFO(dev
)->gen
>= 4) {
16202 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
16203 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
16206 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
16208 if (HAS_GMCH_DISPLAY(dev
))
16209 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
16212 /* Note: this does not include DSI transcoders. */
16213 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
16214 if (HAS_DDI(dev_priv
))
16215 error
->num_transcoders
++; /* Account for eDP. */
16217 for (i
= 0; i
< error
->num_transcoders
; i
++) {
16218 enum transcoder cpu_transcoder
= transcoders
[i
];
16220 error
->transcoder
[i
].power_domain_on
=
16221 __intel_display_power_is_enabled(dev_priv
,
16222 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
16223 if (!error
->transcoder
[i
].power_domain_on
)
16226 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
16228 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
16229 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
16230 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
16231 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
16232 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
16233 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
16234 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
16240 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16243 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
16244 struct drm_device
*dev
,
16245 struct intel_display_error_state
*error
)
16247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
16253 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
16254 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
16255 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
16256 error
->power_well_driver
);
16257 for_each_pipe(dev_priv
, i
) {
16258 err_printf(m
, "Pipe [%d]:\n", i
);
16259 err_printf(m
, " Power: %s\n",
16260 onoff(error
->pipe
[i
].power_domain_on
));
16261 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
16262 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
16264 err_printf(m
, "Plane [%d]:\n", i
);
16265 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
16266 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
16267 if (INTEL_INFO(dev
)->gen
<= 3) {
16268 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
16269 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
16271 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
16272 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
16273 if (INTEL_INFO(dev
)->gen
>= 4) {
16274 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
16275 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
16278 err_printf(m
, "Cursor [%d]:\n", i
);
16279 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
16280 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
16281 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
16284 for (i
= 0; i
< error
->num_transcoders
; i
++) {
16285 err_printf(m
, "CPU transcoder: %s\n",
16286 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
16287 err_printf(m
, " Power: %s\n",
16288 onoff(error
->transcoder
[i
].power_domain_on
));
16289 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
16290 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
16291 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
16292 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
16293 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
16294 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
16295 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);