2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
45 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
47 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
48 struct intel_crtc_config
*pipe_config
);
49 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
50 struct intel_crtc_config
*pipe_config
);
52 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
53 int x
, int y
, struct drm_framebuffer
*old_fb
);
65 typedef struct intel_limit intel_limit_t
;
67 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
72 intel_pch_rawclk(struct drm_device
*dev
)
74 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
76 WARN_ON(!HAS_PCH_SPLIT(dev
));
78 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
81 static inline u32
/* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device
*dev
)
85 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
86 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac
= {
92 .dot
= { .min
= 25000, .max
= 350000 },
93 .vco
= { .min
= 930000, .max
= 1400000 },
94 .n
= { .min
= 3, .max
= 16 },
95 .m
= { .min
= 96, .max
= 140 },
96 .m1
= { .min
= 18, .max
= 26 },
97 .m2
= { .min
= 6, .max
= 16 },
98 .p
= { .min
= 4, .max
= 128 },
99 .p1
= { .min
= 2, .max
= 33 },
100 .p2
= { .dot_limit
= 165000,
101 .p2_slow
= 4, .p2_fast
= 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo
= {
105 .dot
= { .min
= 25000, .max
= 350000 },
106 .vco
= { .min
= 930000, .max
= 1400000 },
107 .n
= { .min
= 3, .max
= 16 },
108 .m
= { .min
= 96, .max
= 140 },
109 .m1
= { .min
= 18, .max
= 26 },
110 .m2
= { .min
= 6, .max
= 16 },
111 .p
= { .min
= 4, .max
= 128 },
112 .p1
= { .min
= 2, .max
= 33 },
113 .p2
= { .dot_limit
= 165000,
114 .p2_slow
= 4, .p2_fast
= 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds
= {
118 .dot
= { .min
= 25000, .max
= 350000 },
119 .vco
= { .min
= 930000, .max
= 1400000 },
120 .n
= { .min
= 3, .max
= 16 },
121 .m
= { .min
= 96, .max
= 140 },
122 .m1
= { .min
= 18, .max
= 26 },
123 .m2
= { .min
= 6, .max
= 16 },
124 .p
= { .min
= 4, .max
= 128 },
125 .p1
= { .min
= 1, .max
= 6 },
126 .p2
= { .dot_limit
= 165000,
127 .p2_slow
= 14, .p2_fast
= 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo
= {
131 .dot
= { .min
= 20000, .max
= 400000 },
132 .vco
= { .min
= 1400000, .max
= 2800000 },
133 .n
= { .min
= 1, .max
= 6 },
134 .m
= { .min
= 70, .max
= 120 },
135 .m1
= { .min
= 8, .max
= 18 },
136 .m2
= { .min
= 3, .max
= 7 },
137 .p
= { .min
= 5, .max
= 80 },
138 .p1
= { .min
= 1, .max
= 8 },
139 .p2
= { .dot_limit
= 200000,
140 .p2_slow
= 10, .p2_fast
= 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds
= {
144 .dot
= { .min
= 20000, .max
= 400000 },
145 .vco
= { .min
= 1400000, .max
= 2800000 },
146 .n
= { .min
= 1, .max
= 6 },
147 .m
= { .min
= 70, .max
= 120 },
148 .m1
= { .min
= 8, .max
= 18 },
149 .m2
= { .min
= 3, .max
= 7 },
150 .p
= { .min
= 7, .max
= 98 },
151 .p1
= { .min
= 1, .max
= 8 },
152 .p2
= { .dot_limit
= 112000,
153 .p2_slow
= 14, .p2_fast
= 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo
= {
158 .dot
= { .min
= 25000, .max
= 270000 },
159 .vco
= { .min
= 1750000, .max
= 3500000},
160 .n
= { .min
= 1, .max
= 4 },
161 .m
= { .min
= 104, .max
= 138 },
162 .m1
= { .min
= 17, .max
= 23 },
163 .m2
= { .min
= 5, .max
= 11 },
164 .p
= { .min
= 10, .max
= 30 },
165 .p1
= { .min
= 1, .max
= 3},
166 .p2
= { .dot_limit
= 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi
= {
173 .dot
= { .min
= 22000, .max
= 400000 },
174 .vco
= { .min
= 1750000, .max
= 3500000},
175 .n
= { .min
= 1, .max
= 4 },
176 .m
= { .min
= 104, .max
= 138 },
177 .m1
= { .min
= 16, .max
= 23 },
178 .m2
= { .min
= 5, .max
= 11 },
179 .p
= { .min
= 5, .max
= 80 },
180 .p1
= { .min
= 1, .max
= 8},
181 .p2
= { .dot_limit
= 165000,
182 .p2_slow
= 10, .p2_fast
= 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
186 .dot
= { .min
= 20000, .max
= 115000 },
187 .vco
= { .min
= 1750000, .max
= 3500000 },
188 .n
= { .min
= 1, .max
= 3 },
189 .m
= { .min
= 104, .max
= 138 },
190 .m1
= { .min
= 17, .max
= 23 },
191 .m2
= { .min
= 5, .max
= 11 },
192 .p
= { .min
= 28, .max
= 112 },
193 .p1
= { .min
= 2, .max
= 8 },
194 .p2
= { .dot_limit
= 0,
195 .p2_slow
= 14, .p2_fast
= 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
200 .dot
= { .min
= 80000, .max
= 224000 },
201 .vco
= { .min
= 1750000, .max
= 3500000 },
202 .n
= { .min
= 1, .max
= 3 },
203 .m
= { .min
= 104, .max
= 138 },
204 .m1
= { .min
= 17, .max
= 23 },
205 .m2
= { .min
= 5, .max
= 11 },
206 .p
= { .min
= 14, .max
= 42 },
207 .p1
= { .min
= 2, .max
= 6 },
208 .p2
= { .dot_limit
= 0,
209 .p2_slow
= 7, .p2_fast
= 7
213 static const intel_limit_t intel_limits_pineview_sdvo
= {
214 .dot
= { .min
= 20000, .max
= 400000},
215 .vco
= { .min
= 1700000, .max
= 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n
= { .min
= 3, .max
= 6 },
218 .m
= { .min
= 2, .max
= 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1
= { .min
= 0, .max
= 0 },
221 .m2
= { .min
= 0, .max
= 254 },
222 .p
= { .min
= 5, .max
= 80 },
223 .p1
= { .min
= 1, .max
= 8 },
224 .p2
= { .dot_limit
= 200000,
225 .p2_slow
= 10, .p2_fast
= 5 },
228 static const intel_limit_t intel_limits_pineview_lvds
= {
229 .dot
= { .min
= 20000, .max
= 400000 },
230 .vco
= { .min
= 1700000, .max
= 3500000 },
231 .n
= { .min
= 3, .max
= 6 },
232 .m
= { .min
= 2, .max
= 256 },
233 .m1
= { .min
= 0, .max
= 0 },
234 .m2
= { .min
= 0, .max
= 254 },
235 .p
= { .min
= 7, .max
= 112 },
236 .p1
= { .min
= 1, .max
= 8 },
237 .p2
= { .dot_limit
= 112000,
238 .p2_slow
= 14, .p2_fast
= 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac
= {
247 .dot
= { .min
= 25000, .max
= 350000 },
248 .vco
= { .min
= 1760000, .max
= 3510000 },
249 .n
= { .min
= 1, .max
= 5 },
250 .m
= { .min
= 79, .max
= 127 },
251 .m1
= { .min
= 12, .max
= 22 },
252 .m2
= { .min
= 5, .max
= 9 },
253 .p
= { .min
= 5, .max
= 80 },
254 .p1
= { .min
= 1, .max
= 8 },
255 .p2
= { .dot_limit
= 225000,
256 .p2_slow
= 10, .p2_fast
= 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
260 .dot
= { .min
= 25000, .max
= 350000 },
261 .vco
= { .min
= 1760000, .max
= 3510000 },
262 .n
= { .min
= 1, .max
= 3 },
263 .m
= { .min
= 79, .max
= 118 },
264 .m1
= { .min
= 12, .max
= 22 },
265 .m2
= { .min
= 5, .max
= 9 },
266 .p
= { .min
= 28, .max
= 112 },
267 .p1
= { .min
= 2, .max
= 8 },
268 .p2
= { .dot_limit
= 225000,
269 .p2_slow
= 14, .p2_fast
= 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
273 .dot
= { .min
= 25000, .max
= 350000 },
274 .vco
= { .min
= 1760000, .max
= 3510000 },
275 .n
= { .min
= 1, .max
= 3 },
276 .m
= { .min
= 79, .max
= 127 },
277 .m1
= { .min
= 12, .max
= 22 },
278 .m2
= { .min
= 5, .max
= 9 },
279 .p
= { .min
= 14, .max
= 56 },
280 .p1
= { .min
= 2, .max
= 8 },
281 .p2
= { .dot_limit
= 225000,
282 .p2_slow
= 7, .p2_fast
= 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
287 .dot
= { .min
= 25000, .max
= 350000 },
288 .vco
= { .min
= 1760000, .max
= 3510000 },
289 .n
= { .min
= 1, .max
= 2 },
290 .m
= { .min
= 79, .max
= 126 },
291 .m1
= { .min
= 12, .max
= 22 },
292 .m2
= { .min
= 5, .max
= 9 },
293 .p
= { .min
= 28, .max
= 112 },
294 .p1
= { .min
= 2, .max
= 8 },
295 .p2
= { .dot_limit
= 225000,
296 .p2_slow
= 14, .p2_fast
= 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
300 .dot
= { .min
= 25000, .max
= 350000 },
301 .vco
= { .min
= 1760000, .max
= 3510000 },
302 .n
= { .min
= 1, .max
= 3 },
303 .m
= { .min
= 79, .max
= 126 },
304 .m1
= { .min
= 12, .max
= 22 },
305 .m2
= { .min
= 5, .max
= 9 },
306 .p
= { .min
= 14, .max
= 42 },
307 .p1
= { .min
= 2, .max
= 6 },
308 .p2
= { .dot_limit
= 225000,
309 .p2_slow
= 7, .p2_fast
= 7 },
312 static const intel_limit_t intel_limits_vlv_dac
= {
313 .dot
= { .min
= 25000, .max
= 270000 },
314 .vco
= { .min
= 4000000, .max
= 6000000 },
315 .n
= { .min
= 1, .max
= 7 },
316 .m
= { .min
= 22, .max
= 450 }, /* guess */
317 .m1
= { .min
= 2, .max
= 3 },
318 .m2
= { .min
= 11, .max
= 156 },
319 .p
= { .min
= 10, .max
= 30 },
320 .p1
= { .min
= 1, .max
= 3 },
321 .p2
= { .dot_limit
= 270000,
322 .p2_slow
= 2, .p2_fast
= 20 },
325 static const intel_limit_t intel_limits_vlv_hdmi
= {
326 .dot
= { .min
= 25000, .max
= 270000 },
327 .vco
= { .min
= 4000000, .max
= 6000000 },
328 .n
= { .min
= 1, .max
= 7 },
329 .m
= { .min
= 60, .max
= 300 }, /* guess */
330 .m1
= { .min
= 2, .max
= 3 },
331 .m2
= { .min
= 11, .max
= 156 },
332 .p
= { .min
= 10, .max
= 30 },
333 .p1
= { .min
= 2, .max
= 3 },
334 .p2
= { .dot_limit
= 270000,
335 .p2_slow
= 2, .p2_fast
= 20 },
339 * Returns whether any output on the specified pipe is of the specified type
341 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
343 struct drm_device
*dev
= crtc
->dev
;
344 struct intel_encoder
*encoder
;
346 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
347 if (encoder
->type
== type
)
353 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
356 struct drm_device
*dev
= crtc
->dev
;
357 const intel_limit_t
*limit
;
359 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
360 if (intel_is_dual_link_lvds(dev
)) {
361 if (refclk
== 100000)
362 limit
= &intel_limits_ironlake_dual_lvds_100m
;
364 limit
= &intel_limits_ironlake_dual_lvds
;
366 if (refclk
== 100000)
367 limit
= &intel_limits_ironlake_single_lvds_100m
;
369 limit
= &intel_limits_ironlake_single_lvds
;
372 limit
= &intel_limits_ironlake_dac
;
377 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
379 struct drm_device
*dev
= crtc
->dev
;
380 const intel_limit_t
*limit
;
382 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
383 if (intel_is_dual_link_lvds(dev
))
384 limit
= &intel_limits_g4x_dual_channel_lvds
;
386 limit
= &intel_limits_g4x_single_channel_lvds
;
387 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
388 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
389 limit
= &intel_limits_g4x_hdmi
;
390 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
391 limit
= &intel_limits_g4x_sdvo
;
392 } else /* The option is for other outputs */
393 limit
= &intel_limits_i9xx_sdvo
;
398 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
400 struct drm_device
*dev
= crtc
->dev
;
401 const intel_limit_t
*limit
;
403 if (HAS_PCH_SPLIT(dev
))
404 limit
= intel_ironlake_limit(crtc
, refclk
);
405 else if (IS_G4X(dev
)) {
406 limit
= intel_g4x_limit(crtc
);
407 } else if (IS_PINEVIEW(dev
)) {
408 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
409 limit
= &intel_limits_pineview_lvds
;
411 limit
= &intel_limits_pineview_sdvo
;
412 } else if (IS_VALLEYVIEW(dev
)) {
413 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
414 limit
= &intel_limits_vlv_dac
;
416 limit
= &intel_limits_vlv_hdmi
;
417 } else if (!IS_GEN2(dev
)) {
418 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
419 limit
= &intel_limits_i9xx_lvds
;
421 limit
= &intel_limits_i9xx_sdvo
;
423 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
424 limit
= &intel_limits_i8xx_lvds
;
425 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
426 limit
= &intel_limits_i8xx_dvo
;
428 limit
= &intel_limits_i8xx_dac
;
433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
434 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
436 clock
->m
= clock
->m2
+ 2;
437 clock
->p
= clock
->p1
* clock
->p2
;
438 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
439 clock
->dot
= clock
->vco
/ clock
->p
;
442 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
444 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
447 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
449 clock
->m
= i9xx_dpll_compute_m(clock
);
450 clock
->p
= clock
->p1
* clock
->p2
;
451 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
452 clock
->dot
= clock
->vco
/ clock
->p
;
455 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
457 * Returns whether the given set of divisors are valid for a given refclk with
458 * the given connectors.
461 static bool intel_PLL_is_valid(struct drm_device
*dev
,
462 const intel_limit_t
*limit
,
463 const intel_clock_t
*clock
)
465 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
466 INTELPllInvalid("p1 out of range\n");
467 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
468 INTELPllInvalid("p out of range\n");
469 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
470 INTELPllInvalid("m2 out of range\n");
471 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
472 INTELPllInvalid("m1 out of range\n");
473 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
474 INTELPllInvalid("m1 <= m2\n");
475 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
476 INTELPllInvalid("m out of range\n");
477 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
478 INTELPllInvalid("n out of range\n");
479 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
480 INTELPllInvalid("vco out of range\n");
481 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
482 * connector, etc., rather than just a single range.
484 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
485 INTELPllInvalid("dot out of range\n");
491 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
492 int target
, int refclk
, intel_clock_t
*match_clock
,
493 intel_clock_t
*best_clock
)
495 struct drm_device
*dev
= crtc
->dev
;
499 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
501 * For LVDS just rely on its current settings for dual-channel.
502 * We haven't figured out how to reliably set up different
503 * single/dual channel state, if we even can.
505 if (intel_is_dual_link_lvds(dev
))
506 clock
.p2
= limit
->p2
.p2_fast
;
508 clock
.p2
= limit
->p2
.p2_slow
;
510 if (target
< limit
->p2
.dot_limit
)
511 clock
.p2
= limit
->p2
.p2_slow
;
513 clock
.p2
= limit
->p2
.p2_fast
;
516 memset(best_clock
, 0, sizeof(*best_clock
));
518 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
520 for (clock
.m2
= limit
->m2
.min
;
521 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
522 if (clock
.m2
>= clock
.m1
)
524 for (clock
.n
= limit
->n
.min
;
525 clock
.n
<= limit
->n
.max
; clock
.n
++) {
526 for (clock
.p1
= limit
->p1
.min
;
527 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
530 i9xx_clock(refclk
, &clock
);
531 if (!intel_PLL_is_valid(dev
, limit
,
535 clock
.p
!= match_clock
->p
)
538 this_err
= abs(clock
.dot
- target
);
539 if (this_err
< err
) {
548 return (err
!= target
);
552 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
553 int target
, int refclk
, intel_clock_t
*match_clock
,
554 intel_clock_t
*best_clock
)
556 struct drm_device
*dev
= crtc
->dev
;
560 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
562 * For LVDS just rely on its current settings for dual-channel.
563 * We haven't figured out how to reliably set up different
564 * single/dual channel state, if we even can.
566 if (intel_is_dual_link_lvds(dev
))
567 clock
.p2
= limit
->p2
.p2_fast
;
569 clock
.p2
= limit
->p2
.p2_slow
;
571 if (target
< limit
->p2
.dot_limit
)
572 clock
.p2
= limit
->p2
.p2_slow
;
574 clock
.p2
= limit
->p2
.p2_fast
;
577 memset(best_clock
, 0, sizeof(*best_clock
));
579 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
581 for (clock
.m2
= limit
->m2
.min
;
582 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
583 for (clock
.n
= limit
->n
.min
;
584 clock
.n
<= limit
->n
.max
; clock
.n
++) {
585 for (clock
.p1
= limit
->p1
.min
;
586 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
589 pineview_clock(refclk
, &clock
);
590 if (!intel_PLL_is_valid(dev
, limit
,
594 clock
.p
!= match_clock
->p
)
597 this_err
= abs(clock
.dot
- target
);
598 if (this_err
< err
) {
607 return (err
!= target
);
611 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
612 int target
, int refclk
, intel_clock_t
*match_clock
,
613 intel_clock_t
*best_clock
)
615 struct drm_device
*dev
= crtc
->dev
;
619 /* approximately equals target * 0.00585 */
620 int err_most
= (target
>> 8) + (target
>> 9);
623 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
624 if (intel_is_dual_link_lvds(dev
))
625 clock
.p2
= limit
->p2
.p2_fast
;
627 clock
.p2
= limit
->p2
.p2_slow
;
629 if (target
< limit
->p2
.dot_limit
)
630 clock
.p2
= limit
->p2
.p2_slow
;
632 clock
.p2
= limit
->p2
.p2_fast
;
635 memset(best_clock
, 0, sizeof(*best_clock
));
636 max_n
= limit
->n
.max
;
637 /* based on hardware requirement, prefer smaller n to precision */
638 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
639 /* based on hardware requirement, prefere larger m1,m2 */
640 for (clock
.m1
= limit
->m1
.max
;
641 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
642 for (clock
.m2
= limit
->m2
.max
;
643 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
644 for (clock
.p1
= limit
->p1
.max
;
645 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
648 i9xx_clock(refclk
, &clock
);
649 if (!intel_PLL_is_valid(dev
, limit
,
653 this_err
= abs(clock
.dot
- target
);
654 if (this_err
< err_most
) {
668 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
669 int target
, int refclk
, intel_clock_t
*match_clock
,
670 intel_clock_t
*best_clock
)
672 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
674 u32 updrate
, minupdate
, p
;
675 unsigned long bestppm
, ppm
, absppm
;
679 dotclk
= target
* 1000;
682 fastclk
= dotclk
/ (2*100);
685 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
686 bestm1
= bestm2
= bestp1
= bestp2
= 0;
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
690 updrate
= refclk
/ n
;
691 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
692 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
698 m2
= DIV_ROUND_CLOSEST(fastclk
* p
* n
, refclk
* m1
);
702 if (vco
< limit
->vco
.min
|| vco
>= limit
->vco
.max
)
705 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
706 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
707 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
711 if (absppm
< bestppm
- 10) {
727 best_clock
->n
= bestn
;
728 best_clock
->m1
= bestm1
;
729 best_clock
->m2
= bestm2
;
730 best_clock
->p1
= bestp1
;
731 best_clock
->p2
= bestp2
;
736 bool intel_crtc_active(struct drm_crtc
*crtc
)
738 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
743 * We can ditch the adjusted_mode.crtc_clock check as soon
744 * as Haswell has gained clock readout/fastboot support.
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
749 return intel_crtc
->active
&& crtc
->fb
&&
750 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
753 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
756 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
757 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
759 return intel_crtc
->config
.cpu_transcoder
;
762 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
765 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
767 frame
= I915_READ(frame_reg
);
769 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
774 * intel_wait_for_vblank - wait for vblank on a given pipe
776 * @pipe: pipe to wait for
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
781 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
784 int pipestat_reg
= PIPESTAT(pipe
);
786 if (INTEL_INFO(dev
)->gen
>= 5) {
787 ironlake_wait_for_vblank(dev
, pipe
);
791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
804 I915_WRITE(pipestat_reg
,
805 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
807 /* Wait for vblank interrupt bit to set */
808 if (wait_for(I915_READ(pipestat_reg
) &
809 PIPE_VBLANK_INTERRUPT_STATUS
,
811 DRM_DEBUG_KMS("vblank wait timed out\n");
815 * intel_wait_for_pipe_off - wait for pipe to turn off
817 * @pipe: pipe to wait for
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
824 * wait for the pipe register state bit to turn off
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
831 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
834 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
837 if (INTEL_INFO(dev
)->gen
>= 4) {
838 int reg
= PIPECONF(cpu_transcoder
);
840 /* Wait for the Pipe State to go off */
841 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
843 WARN(1, "pipe_off wait timed out\n");
845 u32 last_line
, line_mask
;
846 int reg
= PIPEDSL(pipe
);
847 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
850 line_mask
= DSL_LINEMASK_GEN2
;
852 line_mask
= DSL_LINEMASK_GEN3
;
854 /* Wait for the display line to settle */
856 last_line
= I915_READ(reg
) & line_mask
;
858 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
859 time_after(timeout
, jiffies
));
860 if (time_after(jiffies
, timeout
))
861 WARN(1, "pipe_off wait timed out\n");
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
870 * Returns true if @port is connected, false otherwise.
872 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
873 struct intel_digital_port
*port
)
877 if (HAS_PCH_IBX(dev_priv
->dev
)) {
880 bit
= SDE_PORTB_HOTPLUG
;
883 bit
= SDE_PORTC_HOTPLUG
;
886 bit
= SDE_PORTD_HOTPLUG
;
894 bit
= SDE_PORTB_HOTPLUG_CPT
;
897 bit
= SDE_PORTC_HOTPLUG_CPT
;
900 bit
= SDE_PORTD_HOTPLUG_CPT
;
907 return I915_READ(SDEISR
) & bit
;
910 static const char *state_string(bool enabled
)
912 return enabled
? "on" : "off";
915 /* Only for pre-ILK configs */
916 void assert_pll(struct drm_i915_private
*dev_priv
,
917 enum pipe pipe
, bool state
)
924 val
= I915_READ(reg
);
925 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
926 WARN(cur_state
!= state
,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state
), state_string(cur_state
));
931 /* XXX: the dsi pll is shared between MIPI DSI ports */
932 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
937 mutex_lock(&dev_priv
->dpio_lock
);
938 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
939 mutex_unlock(&dev_priv
->dpio_lock
);
941 cur_state
= val
& DSI_PLL_VCO_EN
;
942 WARN(cur_state
!= state
,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state
), state_string(cur_state
));
946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
949 struct intel_shared_dpll
*
950 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
952 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
954 if (crtc
->config
.shared_dpll
< 0)
957 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
961 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
962 struct intel_shared_dpll
*pll
,
966 struct intel_dpll_hw_state hw_state
;
968 if (HAS_PCH_LPT(dev_priv
->dev
)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
974 "asserting DPLL %s with no DPLL\n", state_string(state
)))
977 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
978 WARN(cur_state
!= state
,
979 "%s assertion failure (expected %s, current %s)\n",
980 pll
->name
, state_string(state
), state_string(cur_state
));
983 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
984 enum pipe pipe
, bool state
)
989 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
992 if (HAS_DDI(dev_priv
->dev
)) {
993 /* DDI does not have a specific FDI_TX register */
994 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
995 val
= I915_READ(reg
);
996 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
998 reg
= FDI_TX_CTL(pipe
);
999 val
= I915_READ(reg
);
1000 cur_state
= !!(val
& FDI_TX_ENABLE
);
1002 WARN(cur_state
!= state
,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state
), state_string(cur_state
));
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1009 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1010 enum pipe pipe
, bool state
)
1016 reg
= FDI_RX_CTL(pipe
);
1017 val
= I915_READ(reg
);
1018 cur_state
= !!(val
& FDI_RX_ENABLE
);
1019 WARN(cur_state
!= state
,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state
), state_string(cur_state
));
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv
->info
->gen
== 5)
1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037 if (HAS_DDI(dev_priv
->dev
))
1040 reg
= FDI_TX_CTL(pipe
);
1041 val
= I915_READ(reg
);
1042 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1045 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1046 enum pipe pipe
, bool state
)
1052 reg
= FDI_RX_CTL(pipe
);
1053 val
= I915_READ(reg
);
1054 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1055 WARN(cur_state
!= state
,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state
), state_string(cur_state
));
1060 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1063 int pp_reg
, lvds_reg
;
1065 enum pipe panel_pipe
= PIPE_A
;
1068 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1069 pp_reg
= PCH_PP_CONTROL
;
1070 lvds_reg
= PCH_LVDS
;
1072 pp_reg
= PP_CONTROL
;
1076 val
= I915_READ(pp_reg
);
1077 if (!(val
& PANEL_POWER_ON
) ||
1078 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1081 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1082 panel_pipe
= PIPE_B
;
1084 WARN(panel_pipe
== pipe
&& locked
,
1085 "panel assertion failure, pipe %c regs locked\n",
1089 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1090 enum pipe pipe
, bool state
)
1092 struct drm_device
*dev
= dev_priv
->dev
;
1095 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
1096 cur_state
= I915_READ(CURCNTR_IVB(pipe
)) & CURSOR_MODE
;
1097 else if (IS_845G(dev
) || IS_I865G(dev
))
1098 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1100 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1102 WARN(cur_state
!= state
,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1109 void assert_pipe(struct drm_i915_private
*dev_priv
,
1110 enum pipe pipe
, bool state
)
1115 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1122 if (!intel_display_power_enabled(dev_priv
->dev
,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1126 reg
= PIPECONF(cpu_transcoder
);
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& PIPECONF_ENABLE
);
1131 WARN(cur_state
!= state
,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
1133 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1136 static void assert_plane(struct drm_i915_private
*dev_priv
,
1137 enum plane plane
, bool state
)
1143 reg
= DSPCNTR(plane
);
1144 val
= I915_READ(reg
);
1145 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1146 WARN(cur_state
!= state
,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane
), state_string(state
), state_string(cur_state
));
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1154 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1157 struct drm_device
*dev
= dev_priv
->dev
;
1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev
)->gen
>= 4) {
1164 reg
= DSPCNTR(pipe
);
1165 val
= I915_READ(reg
);
1166 WARN((val
& DISPLAY_PLANE_ENABLE
),
1167 "plane %c assertion failure, should be disabled but not\n",
1172 /* Need to check both planes against the pipe */
1175 val
= I915_READ(reg
);
1176 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1177 DISPPLANE_SEL_PIPE_SHIFT
;
1178 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i
), pipe_name(pipe
));
1184 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1187 struct drm_device
*dev
= dev_priv
->dev
;
1191 if (IS_VALLEYVIEW(dev
)) {
1192 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1193 reg
= SPCNTR(pipe
, i
);
1194 val
= I915_READ(reg
);
1195 WARN((val
& SP_ENABLE
),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe
, i
), pipe_name(pipe
));
1199 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1201 val
= I915_READ(reg
);
1202 WARN((val
& SPRITE_ENABLE
),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe
), pipe_name(pipe
));
1205 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1206 reg
= DVSCNTR(pipe
);
1207 val
= I915_READ(reg
);
1208 WARN((val
& DVS_ENABLE
),
1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210 plane_name(pipe
), pipe_name(pipe
));
1214 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1219 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1224 val
= I915_READ(PCH_DREF_CONTROL
);
1225 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1226 DREF_SUPERSPREAD_SOURCE_MASK
));
1227 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1237 reg
= PCH_TRANSCONF(pipe
);
1238 val
= I915_READ(reg
);
1239 enabled
= !!(val
& TRANS_ENABLE
);
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1245 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1246 enum pipe pipe
, u32 port_sel
, u32 val
)
1248 if ((val
& DP_PORT_EN
) == 0)
1251 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1252 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1253 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1254 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1257 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1263 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1264 enum pipe pipe
, u32 val
)
1266 if ((val
& SDVO_ENABLE
) == 0)
1269 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1270 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1273 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1279 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1280 enum pipe pipe
, u32 val
)
1282 if ((val
& LVDS_PORT_EN
) == 0)
1285 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1286 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1289 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1295 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1296 enum pipe pipe
, u32 val
)
1298 if ((val
& ADPA_DAC_ENABLE
) == 0)
1300 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1301 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1304 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1310 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1311 enum pipe pipe
, int reg
, u32 port_sel
)
1313 u32 val
= I915_READ(reg
);
1314 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg
, pipe_name(pipe
));
1318 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1319 && (val
& DP_PIPEB_SELECT
),
1320 "IBX PCH dp port still using transcoder B\n");
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1324 enum pipe pipe
, int reg
)
1326 u32 val
= I915_READ(reg
);
1327 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg
, pipe_name(pipe
));
1331 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1332 && (val
& SDVO_PIPE_B_SELECT
),
1333 "IBX PCH hdmi port still using transcoder B\n");
1336 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1342 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1343 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1344 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1347 val
= I915_READ(reg
);
1348 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1353 val
= I915_READ(reg
);
1354 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1358 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1359 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1360 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1363 static void intel_init_dpio(struct drm_device
*dev
)
1365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1367 if (!IS_VALLEYVIEW(dev
))
1371 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1372 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1373 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1374 * b. The other bits such as sfr settings / modesel may all be set
1377 * This should only be done on init and resume from S3 with both
1378 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1380 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
1383 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1385 struct drm_device
*dev
= crtc
->base
.dev
;
1386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1387 int reg
= DPLL(crtc
->pipe
);
1388 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1390 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1392 /* No really, not for ILK+ */
1393 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1395 /* PLL is protected by panel, make sure we can write it */
1396 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1397 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1399 I915_WRITE(reg
, dpll
);
1403 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1404 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1406 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1407 POSTING_READ(DPLL_MD(crtc
->pipe
));
1409 /* We do this three times for luck */
1410 I915_WRITE(reg
, dpll
);
1412 udelay(150); /* wait for warmup */
1413 I915_WRITE(reg
, dpll
);
1415 udelay(150); /* wait for warmup */
1416 I915_WRITE(reg
, dpll
);
1418 udelay(150); /* wait for warmup */
1421 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1423 struct drm_device
*dev
= crtc
->base
.dev
;
1424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1425 int reg
= DPLL(crtc
->pipe
);
1426 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1428 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1430 /* No really, not for ILK+ */
1431 BUG_ON(dev_priv
->info
->gen
>= 5);
1433 /* PLL is protected by panel, make sure we can write it */
1434 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1435 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1437 I915_WRITE(reg
, dpll
);
1439 /* Wait for the clocks to stabilize. */
1443 if (INTEL_INFO(dev
)->gen
>= 4) {
1444 I915_WRITE(DPLL_MD(crtc
->pipe
),
1445 crtc
->config
.dpll_hw_state
.dpll_md
);
1447 /* The pixel multiplier can only be updated once the
1448 * DPLL is enabled and the clocks are stable.
1450 * So write it again.
1452 I915_WRITE(reg
, dpll
);
1455 /* We do this three times for luck */
1456 I915_WRITE(reg
, dpll
);
1458 udelay(150); /* wait for warmup */
1459 I915_WRITE(reg
, dpll
);
1461 udelay(150); /* wait for warmup */
1462 I915_WRITE(reg
, dpll
);
1464 udelay(150); /* wait for warmup */
1468 * i9xx_disable_pll - disable a PLL
1469 * @dev_priv: i915 private structure
1470 * @pipe: pipe PLL to disable
1472 * Disable the PLL for @pipe, making sure the pipe is off first.
1474 * Note! This is for pre-ILK only.
1476 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1478 /* Don't disable pipe A or pipe A PLLs if needed */
1479 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1482 /* Make sure the pipe isn't still relying on us */
1483 assert_pipe_disabled(dev_priv
, pipe
);
1485 I915_WRITE(DPLL(pipe
), 0);
1486 POSTING_READ(DPLL(pipe
));
1489 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1493 /* Make sure the pipe isn't still relying on us */
1494 assert_pipe_disabled(dev_priv
, pipe
);
1496 /* Leave integrated clock source enabled */
1498 val
= DPLL_INTEGRATED_CRI_CLK_VLV
;
1499 I915_WRITE(DPLL(pipe
), val
);
1500 POSTING_READ(DPLL(pipe
));
1503 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1508 port_mask
= DPLL_PORTB_READY_MASK
;
1510 port_mask
= DPLL_PORTC_READY_MASK
;
1512 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1513 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1514 'B' + port
, I915_READ(DPLL(0)));
1518 * ironlake_enable_shared_dpll - enable PCH PLL
1519 * @dev_priv: i915 private structure
1520 * @pipe: pipe PLL to enable
1522 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1523 * drives the transcoder clock.
1525 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1527 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1528 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1530 /* PCH PLLs only available on ILK, SNB and IVB */
1531 BUG_ON(dev_priv
->info
->gen
< 5);
1532 if (WARN_ON(pll
== NULL
))
1535 if (WARN_ON(pll
->refcount
== 0))
1538 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1539 pll
->name
, pll
->active
, pll
->on
,
1540 crtc
->base
.base
.id
);
1542 if (pll
->active
++) {
1544 assert_shared_dpll_enabled(dev_priv
, pll
);
1549 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1550 pll
->enable(dev_priv
, pll
);
1554 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1556 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1557 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1559 /* PCH only available on ILK+ */
1560 BUG_ON(dev_priv
->info
->gen
< 5);
1561 if (WARN_ON(pll
== NULL
))
1564 if (WARN_ON(pll
->refcount
== 0))
1567 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1568 pll
->name
, pll
->active
, pll
->on
,
1569 crtc
->base
.base
.id
);
1571 if (WARN_ON(pll
->active
== 0)) {
1572 assert_shared_dpll_disabled(dev_priv
, pll
);
1576 assert_shared_dpll_enabled(dev_priv
, pll
);
1581 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1582 pll
->disable(dev_priv
, pll
);
1586 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1589 struct drm_device
*dev
= dev_priv
->dev
;
1590 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1591 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1592 uint32_t reg
, val
, pipeconf_val
;
1594 /* PCH only available on ILK+ */
1595 BUG_ON(dev_priv
->info
->gen
< 5);
1597 /* Make sure PCH DPLL is enabled */
1598 assert_shared_dpll_enabled(dev_priv
,
1599 intel_crtc_to_shared_dpll(intel_crtc
));
1601 /* FDI must be feeding us bits for PCH ports */
1602 assert_fdi_tx_enabled(dev_priv
, pipe
);
1603 assert_fdi_rx_enabled(dev_priv
, pipe
);
1605 if (HAS_PCH_CPT(dev
)) {
1606 /* Workaround: Set the timing override bit before enabling the
1607 * pch transcoder. */
1608 reg
= TRANS_CHICKEN2(pipe
);
1609 val
= I915_READ(reg
);
1610 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1611 I915_WRITE(reg
, val
);
1614 reg
= PCH_TRANSCONF(pipe
);
1615 val
= I915_READ(reg
);
1616 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1618 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1620 * make the BPC in transcoder be consistent with
1621 * that in pipeconf reg.
1623 val
&= ~PIPECONF_BPC_MASK
;
1624 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1627 val
&= ~TRANS_INTERLACE_MASK
;
1628 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1629 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1630 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1631 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1633 val
|= TRANS_INTERLACED
;
1635 val
|= TRANS_PROGRESSIVE
;
1637 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1638 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1639 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1642 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1643 enum transcoder cpu_transcoder
)
1645 u32 val
, pipeconf_val
;
1647 /* PCH only available on ILK+ */
1648 BUG_ON(dev_priv
->info
->gen
< 5);
1650 /* FDI must be feeding us bits for PCH ports */
1651 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1652 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1654 /* Workaround: set timing override bit. */
1655 val
= I915_READ(_TRANSA_CHICKEN2
);
1656 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1657 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1660 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1662 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1663 PIPECONF_INTERLACED_ILK
)
1664 val
|= TRANS_INTERLACED
;
1666 val
|= TRANS_PROGRESSIVE
;
1668 I915_WRITE(LPT_TRANSCONF
, val
);
1669 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1670 DRM_ERROR("Failed to enable PCH transcoder\n");
1673 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1676 struct drm_device
*dev
= dev_priv
->dev
;
1679 /* FDI relies on the transcoder */
1680 assert_fdi_tx_disabled(dev_priv
, pipe
);
1681 assert_fdi_rx_disabled(dev_priv
, pipe
);
1683 /* Ports must be off as well */
1684 assert_pch_ports_disabled(dev_priv
, pipe
);
1686 reg
= PCH_TRANSCONF(pipe
);
1687 val
= I915_READ(reg
);
1688 val
&= ~TRANS_ENABLE
;
1689 I915_WRITE(reg
, val
);
1690 /* wait for PCH transcoder off, transcoder state */
1691 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1692 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1694 if (!HAS_PCH_IBX(dev
)) {
1695 /* Workaround: Clear the timing override chicken bit again. */
1696 reg
= TRANS_CHICKEN2(pipe
);
1697 val
= I915_READ(reg
);
1698 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1699 I915_WRITE(reg
, val
);
1703 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1707 val
= I915_READ(LPT_TRANSCONF
);
1708 val
&= ~TRANS_ENABLE
;
1709 I915_WRITE(LPT_TRANSCONF
, val
);
1710 /* wait for PCH transcoder off, transcoder state */
1711 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1712 DRM_ERROR("Failed to disable PCH transcoder\n");
1714 /* Workaround: clear timing override bit. */
1715 val
= I915_READ(_TRANSA_CHICKEN2
);
1716 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1717 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1721 * intel_enable_pipe - enable a pipe, asserting requirements
1722 * @dev_priv: i915 private structure
1723 * @pipe: pipe to enable
1724 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1726 * Enable @pipe, making sure that various hardware specific requirements
1727 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1729 * @pipe should be %PIPE_A or %PIPE_B.
1731 * Will wait until the pipe is actually running (i.e. first vblank) before
1734 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1735 bool pch_port
, bool dsi
)
1737 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1739 enum pipe pch_transcoder
;
1743 assert_planes_disabled(dev_priv
, pipe
);
1744 assert_cursor_disabled(dev_priv
, pipe
);
1745 assert_sprites_disabled(dev_priv
, pipe
);
1747 if (HAS_PCH_LPT(dev_priv
->dev
))
1748 pch_transcoder
= TRANSCODER_A
;
1750 pch_transcoder
= pipe
;
1753 * A pipe without a PLL won't actually be able to drive bits from
1754 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1757 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1759 assert_dsi_pll_enabled(dev_priv
);
1761 assert_pll_enabled(dev_priv
, pipe
);
1764 /* if driving the PCH, we need FDI enabled */
1765 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1766 assert_fdi_tx_pll_enabled(dev_priv
,
1767 (enum pipe
) cpu_transcoder
);
1769 /* FIXME: assert CPU port conditions for SNB+ */
1772 reg
= PIPECONF(cpu_transcoder
);
1773 val
= I915_READ(reg
);
1774 if (val
& PIPECONF_ENABLE
)
1777 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1778 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1782 * intel_disable_pipe - disable a pipe, asserting requirements
1783 * @dev_priv: i915 private structure
1784 * @pipe: pipe to disable
1786 * Disable @pipe, making sure that various hardware specific requirements
1787 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1789 * @pipe should be %PIPE_A or %PIPE_B.
1791 * Will wait until the pipe has shut down before returning.
1793 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1796 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1802 * Make sure planes won't keep trying to pump pixels to us,
1803 * or we might hang the display.
1805 assert_planes_disabled(dev_priv
, pipe
);
1806 assert_cursor_disabled(dev_priv
, pipe
);
1807 assert_sprites_disabled(dev_priv
, pipe
);
1809 /* Don't disable pipe A or pipe A PLLs if needed */
1810 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1813 reg
= PIPECONF(cpu_transcoder
);
1814 val
= I915_READ(reg
);
1815 if ((val
& PIPECONF_ENABLE
) == 0)
1818 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1819 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1823 * Plane regs are double buffered, going from enabled->disabled needs a
1824 * trigger in order to latch. The display address reg provides this.
1826 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1829 if (dev_priv
->info
->gen
>= 4)
1830 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1832 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1836 * intel_enable_plane - enable a display plane on a given pipe
1837 * @dev_priv: i915 private structure
1838 * @plane: plane to enable
1839 * @pipe: pipe being fed
1841 * Enable @plane on @pipe, making sure that @pipe is running first.
1843 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1844 enum plane plane
, enum pipe pipe
)
1849 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1850 assert_pipe_enabled(dev_priv
, pipe
);
1852 reg
= DSPCNTR(plane
);
1853 val
= I915_READ(reg
);
1854 if (val
& DISPLAY_PLANE_ENABLE
)
1857 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1858 intel_flush_display_plane(dev_priv
, plane
);
1859 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1863 * intel_disable_plane - disable a display plane
1864 * @dev_priv: i915 private structure
1865 * @plane: plane to disable
1866 * @pipe: pipe consuming the data
1868 * Disable @plane; should be an independent operation.
1870 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1871 enum plane plane
, enum pipe pipe
)
1876 reg
= DSPCNTR(plane
);
1877 val
= I915_READ(reg
);
1878 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1881 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1882 intel_flush_display_plane(dev_priv
, plane
);
1883 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1886 static bool need_vtd_wa(struct drm_device
*dev
)
1888 #ifdef CONFIG_INTEL_IOMMU
1889 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1896 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1897 struct drm_i915_gem_object
*obj
,
1898 struct intel_ring_buffer
*pipelined
)
1900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1904 switch (obj
->tiling_mode
) {
1905 case I915_TILING_NONE
:
1906 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1907 alignment
= 128 * 1024;
1908 else if (INTEL_INFO(dev
)->gen
>= 4)
1909 alignment
= 4 * 1024;
1911 alignment
= 64 * 1024;
1914 /* pin() will align the object as required by fence */
1918 /* Despite that we check this in framebuffer_init userspace can
1919 * screw us over and change the tiling after the fact. Only
1920 * pinned buffers can't change their tiling. */
1921 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1927 /* Note that the w/a also requires 64 PTE of padding following the
1928 * bo. We currently fill all unused PTE with the shadow page and so
1929 * we should always have valid PTE following the scanout preventing
1932 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1933 alignment
= 256 * 1024;
1935 dev_priv
->mm
.interruptible
= false;
1936 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1938 goto err_interruptible
;
1940 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1941 * fence, whereas 965+ only requires a fence if using
1942 * framebuffer compression. For simplicity, we always install
1943 * a fence as the cost is not that onerous.
1945 ret
= i915_gem_object_get_fence(obj
);
1949 i915_gem_object_pin_fence(obj
);
1951 dev_priv
->mm
.interruptible
= true;
1955 i915_gem_object_unpin_from_display_plane(obj
);
1957 dev_priv
->mm
.interruptible
= true;
1961 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1963 i915_gem_object_unpin_fence(obj
);
1964 i915_gem_object_unpin_from_display_plane(obj
);
1967 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1968 * is assumed to be a power-of-two. */
1969 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1970 unsigned int tiling_mode
,
1974 if (tiling_mode
!= I915_TILING_NONE
) {
1975 unsigned int tile_rows
, tiles
;
1980 tiles
= *x
/ (512/cpp
);
1983 return tile_rows
* pitch
* 8 + tiles
* 4096;
1985 unsigned int offset
;
1987 offset
= *y
* pitch
+ *x
* cpp
;
1989 *x
= (offset
& 4095) / cpp
;
1990 return offset
& -4096;
1994 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1997 struct drm_device
*dev
= crtc
->dev
;
1998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1999 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2000 struct intel_framebuffer
*intel_fb
;
2001 struct drm_i915_gem_object
*obj
;
2002 int plane
= intel_crtc
->plane
;
2003 unsigned long linear_offset
;
2012 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2016 intel_fb
= to_intel_framebuffer(fb
);
2017 obj
= intel_fb
->obj
;
2019 reg
= DSPCNTR(plane
);
2020 dspcntr
= I915_READ(reg
);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2023 switch (fb
->pixel_format
) {
2025 dspcntr
|= DISPPLANE_8BPP
;
2027 case DRM_FORMAT_XRGB1555
:
2028 case DRM_FORMAT_ARGB1555
:
2029 dspcntr
|= DISPPLANE_BGRX555
;
2031 case DRM_FORMAT_RGB565
:
2032 dspcntr
|= DISPPLANE_BGRX565
;
2034 case DRM_FORMAT_XRGB8888
:
2035 case DRM_FORMAT_ARGB8888
:
2036 dspcntr
|= DISPPLANE_BGRX888
;
2038 case DRM_FORMAT_XBGR8888
:
2039 case DRM_FORMAT_ABGR8888
:
2040 dspcntr
|= DISPPLANE_RGBX888
;
2042 case DRM_FORMAT_XRGB2101010
:
2043 case DRM_FORMAT_ARGB2101010
:
2044 dspcntr
|= DISPPLANE_BGRX101010
;
2046 case DRM_FORMAT_XBGR2101010
:
2047 case DRM_FORMAT_ABGR2101010
:
2048 dspcntr
|= DISPPLANE_RGBX101010
;
2054 if (INTEL_INFO(dev
)->gen
>= 4) {
2055 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2056 dspcntr
|= DISPPLANE_TILED
;
2058 dspcntr
&= ~DISPPLANE_TILED
;
2062 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2064 I915_WRITE(reg
, dspcntr
);
2066 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2068 if (INTEL_INFO(dev
)->gen
>= 4) {
2069 intel_crtc
->dspaddr_offset
=
2070 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2071 fb
->bits_per_pixel
/ 8,
2073 linear_offset
-= intel_crtc
->dspaddr_offset
;
2075 intel_crtc
->dspaddr_offset
= linear_offset
;
2078 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2081 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2082 if (INTEL_INFO(dev
)->gen
>= 4) {
2083 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2084 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2085 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2086 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2088 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2094 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2095 struct drm_framebuffer
*fb
, int x
, int y
)
2097 struct drm_device
*dev
= crtc
->dev
;
2098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2099 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2100 struct intel_framebuffer
*intel_fb
;
2101 struct drm_i915_gem_object
*obj
;
2102 int plane
= intel_crtc
->plane
;
2103 unsigned long linear_offset
;
2113 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2117 intel_fb
= to_intel_framebuffer(fb
);
2118 obj
= intel_fb
->obj
;
2120 reg
= DSPCNTR(plane
);
2121 dspcntr
= I915_READ(reg
);
2122 /* Mask out pixel format bits in case we change it */
2123 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2124 switch (fb
->pixel_format
) {
2126 dspcntr
|= DISPPLANE_8BPP
;
2128 case DRM_FORMAT_RGB565
:
2129 dspcntr
|= DISPPLANE_BGRX565
;
2131 case DRM_FORMAT_XRGB8888
:
2132 case DRM_FORMAT_ARGB8888
:
2133 dspcntr
|= DISPPLANE_BGRX888
;
2135 case DRM_FORMAT_XBGR8888
:
2136 case DRM_FORMAT_ABGR8888
:
2137 dspcntr
|= DISPPLANE_RGBX888
;
2139 case DRM_FORMAT_XRGB2101010
:
2140 case DRM_FORMAT_ARGB2101010
:
2141 dspcntr
|= DISPPLANE_BGRX101010
;
2143 case DRM_FORMAT_XBGR2101010
:
2144 case DRM_FORMAT_ABGR2101010
:
2145 dspcntr
|= DISPPLANE_RGBX101010
;
2151 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2152 dspcntr
|= DISPPLANE_TILED
;
2154 dspcntr
&= ~DISPPLANE_TILED
;
2156 if (IS_HASWELL(dev
))
2157 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2159 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2161 I915_WRITE(reg
, dspcntr
);
2163 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2164 intel_crtc
->dspaddr_offset
=
2165 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2166 fb
->bits_per_pixel
/ 8,
2168 linear_offset
-= intel_crtc
->dspaddr_offset
;
2170 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2171 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2173 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2174 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2175 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2176 if (IS_HASWELL(dev
)) {
2177 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2179 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2180 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2187 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2189 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2190 int x
, int y
, enum mode_set_atomic state
)
2192 struct drm_device
*dev
= crtc
->dev
;
2193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2195 if (dev_priv
->display
.disable_fbc
)
2196 dev_priv
->display
.disable_fbc(dev
);
2197 intel_increase_pllclock(crtc
);
2199 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2202 void intel_display_handle_reset(struct drm_device
*dev
)
2204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2205 struct drm_crtc
*crtc
;
2208 * Flips in the rings have been nuked by the reset,
2209 * so complete all pending flips so that user space
2210 * will get its events and not get stuck.
2212 * Also update the base address of all primary
2213 * planes to the the last fb to make sure we're
2214 * showing the correct fb after a reset.
2216 * Need to make two loops over the crtcs so that we
2217 * don't try to grab a crtc mutex before the
2218 * pending_flip_queue really got woken up.
2221 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2222 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2223 enum plane plane
= intel_crtc
->plane
;
2225 intel_prepare_page_flip(dev
, plane
);
2226 intel_finish_page_flip_plane(dev
, plane
);
2229 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2230 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2232 mutex_lock(&crtc
->mutex
);
2233 if (intel_crtc
->active
)
2234 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2236 mutex_unlock(&crtc
->mutex
);
2241 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2243 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2244 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2245 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2248 /* Big Hammer, we also need to ensure that any pending
2249 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2250 * current scanout is retired before unpinning the old
2253 * This should only fail upon a hung GPU, in which case we
2254 * can safely continue.
2256 dev_priv
->mm
.interruptible
= false;
2257 ret
= i915_gem_object_finish_gpu(obj
);
2258 dev_priv
->mm
.interruptible
= was_interruptible
;
2263 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2265 struct drm_device
*dev
= crtc
->dev
;
2266 struct drm_i915_master_private
*master_priv
;
2267 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2269 if (!dev
->primary
->master
)
2272 master_priv
= dev
->primary
->master
->driver_priv
;
2273 if (!master_priv
->sarea_priv
)
2276 switch (intel_crtc
->pipe
) {
2278 master_priv
->sarea_priv
->pipeA_x
= x
;
2279 master_priv
->sarea_priv
->pipeA_y
= y
;
2282 master_priv
->sarea_priv
->pipeB_x
= x
;
2283 master_priv
->sarea_priv
->pipeB_y
= y
;
2291 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2292 struct drm_framebuffer
*fb
)
2294 struct drm_device
*dev
= crtc
->dev
;
2295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2296 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2297 struct drm_framebuffer
*old_fb
;
2302 DRM_ERROR("No FB bound\n");
2306 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2307 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2308 plane_name(intel_crtc
->plane
),
2309 INTEL_INFO(dev
)->num_pipes
);
2313 mutex_lock(&dev
->struct_mutex
);
2314 ret
= intel_pin_and_fence_fb_obj(dev
,
2315 to_intel_framebuffer(fb
)->obj
,
2318 mutex_unlock(&dev
->struct_mutex
);
2319 DRM_ERROR("pin & fence failed\n");
2324 * Update pipe size and adjust fitter if needed: the reason for this is
2325 * that in compute_mode_changes we check the native mode (not the pfit
2326 * mode) to see if we can flip rather than do a full mode set. In the
2327 * fastboot case, we'll flip, but if we don't update the pipesrc and
2328 * pfit state, we'll end up with a big fb scanned out into the wrong
2331 * To fix this properly, we need to hoist the checks up into
2332 * compute_mode_changes (or above), check the actual pfit state and
2333 * whether the platform allows pfit disable with pipe active, and only
2334 * then update the pipesrc and pfit state, even on the flip path.
2336 if (i915_fastboot
) {
2337 const struct drm_display_mode
*adjusted_mode
=
2338 &intel_crtc
->config
.adjusted_mode
;
2340 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2341 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2342 (adjusted_mode
->crtc_vdisplay
- 1));
2343 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2344 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2345 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2346 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2347 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2348 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2352 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2354 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2355 mutex_unlock(&dev
->struct_mutex
);
2356 DRM_ERROR("failed to update base address\n");
2366 if (intel_crtc
->active
&& old_fb
!= fb
)
2367 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2368 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2371 intel_update_fbc(dev
);
2372 intel_edp_psr_update(dev
);
2373 mutex_unlock(&dev
->struct_mutex
);
2375 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2380 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2382 struct drm_device
*dev
= crtc
->dev
;
2383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2384 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2385 int pipe
= intel_crtc
->pipe
;
2388 /* enable normal train */
2389 reg
= FDI_TX_CTL(pipe
);
2390 temp
= I915_READ(reg
);
2391 if (IS_IVYBRIDGE(dev
)) {
2392 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2393 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2395 temp
&= ~FDI_LINK_TRAIN_NONE
;
2396 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2398 I915_WRITE(reg
, temp
);
2400 reg
= FDI_RX_CTL(pipe
);
2401 temp
= I915_READ(reg
);
2402 if (HAS_PCH_CPT(dev
)) {
2403 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2404 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2406 temp
&= ~FDI_LINK_TRAIN_NONE
;
2407 temp
|= FDI_LINK_TRAIN_NONE
;
2409 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2411 /* wait one idle pattern time */
2415 /* IVB wants error correction enabled */
2416 if (IS_IVYBRIDGE(dev
))
2417 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2418 FDI_FE_ERRC_ENABLE
);
2421 static bool pipe_has_enabled_pch(struct intel_crtc
*intel_crtc
)
2423 return intel_crtc
->base
.enabled
&& intel_crtc
->config
.has_pch_encoder
;
2426 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2429 struct intel_crtc
*pipe_B_crtc
=
2430 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2431 struct intel_crtc
*pipe_C_crtc
=
2432 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2436 * When everything is off disable fdi C so that we could enable fdi B
2437 * with all lanes. Note that we don't care about enabled pipes without
2438 * an enabled pch encoder.
2440 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2441 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2442 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2443 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2445 temp
= I915_READ(SOUTH_CHICKEN1
);
2446 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2447 DRM_DEBUG_KMS("disabling fdi C rx\n");
2448 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2452 /* The FDI link training functions for ILK/Ibexpeak. */
2453 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2455 struct drm_device
*dev
= crtc
->dev
;
2456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2457 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2458 int pipe
= intel_crtc
->pipe
;
2459 int plane
= intel_crtc
->plane
;
2460 u32 reg
, temp
, tries
;
2462 /* FDI needs bits from pipe & plane first */
2463 assert_pipe_enabled(dev_priv
, pipe
);
2464 assert_plane_enabled(dev_priv
, plane
);
2466 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2468 reg
= FDI_RX_IMR(pipe
);
2469 temp
= I915_READ(reg
);
2470 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2471 temp
&= ~FDI_RX_BIT_LOCK
;
2472 I915_WRITE(reg
, temp
);
2476 /* enable CPU FDI TX and PCH FDI RX */
2477 reg
= FDI_TX_CTL(pipe
);
2478 temp
= I915_READ(reg
);
2479 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2480 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2481 temp
&= ~FDI_LINK_TRAIN_NONE
;
2482 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2483 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2485 reg
= FDI_RX_CTL(pipe
);
2486 temp
= I915_READ(reg
);
2487 temp
&= ~FDI_LINK_TRAIN_NONE
;
2488 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2489 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2494 /* Ironlake workaround, enable clock pointer after FDI enable*/
2495 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2496 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2497 FDI_RX_PHASE_SYNC_POINTER_EN
);
2499 reg
= FDI_RX_IIR(pipe
);
2500 for (tries
= 0; tries
< 5; tries
++) {
2501 temp
= I915_READ(reg
);
2502 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2504 if ((temp
& FDI_RX_BIT_LOCK
)) {
2505 DRM_DEBUG_KMS("FDI train 1 done.\n");
2506 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2511 DRM_ERROR("FDI train 1 fail!\n");
2514 reg
= FDI_TX_CTL(pipe
);
2515 temp
= I915_READ(reg
);
2516 temp
&= ~FDI_LINK_TRAIN_NONE
;
2517 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2518 I915_WRITE(reg
, temp
);
2520 reg
= FDI_RX_CTL(pipe
);
2521 temp
= I915_READ(reg
);
2522 temp
&= ~FDI_LINK_TRAIN_NONE
;
2523 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2524 I915_WRITE(reg
, temp
);
2529 reg
= FDI_RX_IIR(pipe
);
2530 for (tries
= 0; tries
< 5; tries
++) {
2531 temp
= I915_READ(reg
);
2532 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2534 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2535 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2536 DRM_DEBUG_KMS("FDI train 2 done.\n");
2541 DRM_ERROR("FDI train 2 fail!\n");
2543 DRM_DEBUG_KMS("FDI train done\n");
2547 static const int snb_b_fdi_train_param
[] = {
2548 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2549 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2550 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2551 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2554 /* The FDI link training functions for SNB/Cougarpoint. */
2555 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2557 struct drm_device
*dev
= crtc
->dev
;
2558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2559 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2560 int pipe
= intel_crtc
->pipe
;
2561 u32 reg
, temp
, i
, retry
;
2563 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2565 reg
= FDI_RX_IMR(pipe
);
2566 temp
= I915_READ(reg
);
2567 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2568 temp
&= ~FDI_RX_BIT_LOCK
;
2569 I915_WRITE(reg
, temp
);
2574 /* enable CPU FDI TX and PCH FDI RX */
2575 reg
= FDI_TX_CTL(pipe
);
2576 temp
= I915_READ(reg
);
2577 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2578 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2579 temp
&= ~FDI_LINK_TRAIN_NONE
;
2580 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2581 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2583 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2584 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2586 I915_WRITE(FDI_RX_MISC(pipe
),
2587 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2589 reg
= FDI_RX_CTL(pipe
);
2590 temp
= I915_READ(reg
);
2591 if (HAS_PCH_CPT(dev
)) {
2592 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2593 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2595 temp
&= ~FDI_LINK_TRAIN_NONE
;
2596 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2598 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2603 for (i
= 0; i
< 4; i
++) {
2604 reg
= FDI_TX_CTL(pipe
);
2605 temp
= I915_READ(reg
);
2606 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2607 temp
|= snb_b_fdi_train_param
[i
];
2608 I915_WRITE(reg
, temp
);
2613 for (retry
= 0; retry
< 5; retry
++) {
2614 reg
= FDI_RX_IIR(pipe
);
2615 temp
= I915_READ(reg
);
2616 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2617 if (temp
& FDI_RX_BIT_LOCK
) {
2618 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2619 DRM_DEBUG_KMS("FDI train 1 done.\n");
2628 DRM_ERROR("FDI train 1 fail!\n");
2631 reg
= FDI_TX_CTL(pipe
);
2632 temp
= I915_READ(reg
);
2633 temp
&= ~FDI_LINK_TRAIN_NONE
;
2634 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2636 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2638 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2640 I915_WRITE(reg
, temp
);
2642 reg
= FDI_RX_CTL(pipe
);
2643 temp
= I915_READ(reg
);
2644 if (HAS_PCH_CPT(dev
)) {
2645 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2646 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2648 temp
&= ~FDI_LINK_TRAIN_NONE
;
2649 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2651 I915_WRITE(reg
, temp
);
2656 for (i
= 0; i
< 4; i
++) {
2657 reg
= FDI_TX_CTL(pipe
);
2658 temp
= I915_READ(reg
);
2659 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2660 temp
|= snb_b_fdi_train_param
[i
];
2661 I915_WRITE(reg
, temp
);
2666 for (retry
= 0; retry
< 5; retry
++) {
2667 reg
= FDI_RX_IIR(pipe
);
2668 temp
= I915_READ(reg
);
2669 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2670 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2671 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2672 DRM_DEBUG_KMS("FDI train 2 done.\n");
2681 DRM_ERROR("FDI train 2 fail!\n");
2683 DRM_DEBUG_KMS("FDI train done.\n");
2686 /* Manual link training for Ivy Bridge A0 parts */
2687 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2689 struct drm_device
*dev
= crtc
->dev
;
2690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2691 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2692 int pipe
= intel_crtc
->pipe
;
2693 u32 reg
, temp
, i
, j
;
2695 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2697 reg
= FDI_RX_IMR(pipe
);
2698 temp
= I915_READ(reg
);
2699 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2700 temp
&= ~FDI_RX_BIT_LOCK
;
2701 I915_WRITE(reg
, temp
);
2706 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2707 I915_READ(FDI_RX_IIR(pipe
)));
2709 /* Try each vswing and preemphasis setting twice before moving on */
2710 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
2711 /* disable first in case we need to retry */
2712 reg
= FDI_TX_CTL(pipe
);
2713 temp
= I915_READ(reg
);
2714 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2715 temp
&= ~FDI_TX_ENABLE
;
2716 I915_WRITE(reg
, temp
);
2718 reg
= FDI_RX_CTL(pipe
);
2719 temp
= I915_READ(reg
);
2720 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2721 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2722 temp
&= ~FDI_RX_ENABLE
;
2723 I915_WRITE(reg
, temp
);
2725 /* enable CPU FDI TX and PCH FDI RX */
2726 reg
= FDI_TX_CTL(pipe
);
2727 temp
= I915_READ(reg
);
2728 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2729 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2730 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2731 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2732 temp
|= snb_b_fdi_train_param
[j
/2];
2733 temp
|= FDI_COMPOSITE_SYNC
;
2734 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2736 I915_WRITE(FDI_RX_MISC(pipe
),
2737 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2739 reg
= FDI_RX_CTL(pipe
);
2740 temp
= I915_READ(reg
);
2741 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2742 temp
|= FDI_COMPOSITE_SYNC
;
2743 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2746 udelay(1); /* should be 0.5us */
2748 for (i
= 0; i
< 4; i
++) {
2749 reg
= FDI_RX_IIR(pipe
);
2750 temp
= I915_READ(reg
);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2753 if (temp
& FDI_RX_BIT_LOCK
||
2754 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2755 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2756 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2760 udelay(1); /* should be 0.5us */
2763 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
2768 reg
= FDI_TX_CTL(pipe
);
2769 temp
= I915_READ(reg
);
2770 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2771 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2772 I915_WRITE(reg
, temp
);
2774 reg
= FDI_RX_CTL(pipe
);
2775 temp
= I915_READ(reg
);
2776 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2777 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2778 I915_WRITE(reg
, temp
);
2781 udelay(2); /* should be 1.5us */
2783 for (i
= 0; i
< 4; i
++) {
2784 reg
= FDI_RX_IIR(pipe
);
2785 temp
= I915_READ(reg
);
2786 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2788 if (temp
& FDI_RX_SYMBOL_LOCK
||
2789 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
2790 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2791 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2795 udelay(2); /* should be 1.5us */
2798 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
2802 DRM_DEBUG_KMS("FDI train done.\n");
2805 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2807 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2809 int pipe
= intel_crtc
->pipe
;
2813 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2814 reg
= FDI_RX_CTL(pipe
);
2815 temp
= I915_READ(reg
);
2816 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2817 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2818 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2819 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2824 /* Switch from Rawclk to PCDclk */
2825 temp
= I915_READ(reg
);
2826 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2831 /* Enable CPU FDI TX PLL, always on for Ironlake */
2832 reg
= FDI_TX_CTL(pipe
);
2833 temp
= I915_READ(reg
);
2834 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2835 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2842 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2844 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2846 int pipe
= intel_crtc
->pipe
;
2849 /* Switch from PCDclk to Rawclk */
2850 reg
= FDI_RX_CTL(pipe
);
2851 temp
= I915_READ(reg
);
2852 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2854 /* Disable CPU FDI TX PLL */
2855 reg
= FDI_TX_CTL(pipe
);
2856 temp
= I915_READ(reg
);
2857 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2862 reg
= FDI_RX_CTL(pipe
);
2863 temp
= I915_READ(reg
);
2864 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2866 /* Wait for the clocks to turn off. */
2871 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2873 struct drm_device
*dev
= crtc
->dev
;
2874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2875 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2876 int pipe
= intel_crtc
->pipe
;
2879 /* disable CPU FDI tx and PCH FDI rx */
2880 reg
= FDI_TX_CTL(pipe
);
2881 temp
= I915_READ(reg
);
2882 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2885 reg
= FDI_RX_CTL(pipe
);
2886 temp
= I915_READ(reg
);
2887 temp
&= ~(0x7 << 16);
2888 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2889 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2894 /* Ironlake workaround, disable clock pointer after downing FDI */
2895 if (HAS_PCH_IBX(dev
)) {
2896 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2899 /* still set train pattern 1 */
2900 reg
= FDI_TX_CTL(pipe
);
2901 temp
= I915_READ(reg
);
2902 temp
&= ~FDI_LINK_TRAIN_NONE
;
2903 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2904 I915_WRITE(reg
, temp
);
2906 reg
= FDI_RX_CTL(pipe
);
2907 temp
= I915_READ(reg
);
2908 if (HAS_PCH_CPT(dev
)) {
2909 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2910 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2912 temp
&= ~FDI_LINK_TRAIN_NONE
;
2913 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2915 /* BPC in FDI rx is consistent with that in PIPECONF */
2916 temp
&= ~(0x07 << 16);
2917 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2918 I915_WRITE(reg
, temp
);
2924 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2926 struct drm_device
*dev
= crtc
->dev
;
2927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2928 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2929 unsigned long flags
;
2932 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2933 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2936 spin_lock_irqsave(&dev
->event_lock
, flags
);
2937 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2938 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2943 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2945 struct drm_device
*dev
= crtc
->dev
;
2946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2948 if (crtc
->fb
== NULL
)
2951 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2953 wait_event(dev_priv
->pending_flip_queue
,
2954 !intel_crtc_has_pending_flip(crtc
));
2956 mutex_lock(&dev
->struct_mutex
);
2957 intel_finish_fb(crtc
->fb
);
2958 mutex_unlock(&dev
->struct_mutex
);
2961 /* Program iCLKIP clock to the desired frequency */
2962 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2964 struct drm_device
*dev
= crtc
->dev
;
2965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2966 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
2967 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2970 mutex_lock(&dev_priv
->dpio_lock
);
2972 /* It is necessary to ungate the pixclk gate prior to programming
2973 * the divisors, and gate it back when it is done.
2975 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2977 /* Disable SSCCTL */
2978 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2979 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2983 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2984 if (clock
== 20000) {
2989 /* The iCLK virtual clock root frequency is in MHz,
2990 * but the adjusted_mode->crtc_clock in in KHz. To get the
2991 * divisors, it is necessary to divide one by another, so we
2992 * convert the virtual clock precision to KHz here for higher
2995 u32 iclk_virtual_root_freq
= 172800 * 1000;
2996 u32 iclk_pi_range
= 64;
2997 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2999 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3000 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3001 pi_value
= desired_divisor
% iclk_pi_range
;
3004 divsel
= msb_divisor_value
- 2;
3005 phaseinc
= pi_value
;
3008 /* This should not happen with any sane values */
3009 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3010 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3011 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3012 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3014 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3021 /* Program SSCDIVINTPHASE6 */
3022 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3023 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3024 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3025 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3026 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3027 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3028 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3029 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3031 /* Program SSCAUXDIV */
3032 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3033 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3034 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3035 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3037 /* Enable modulator and associated divider */
3038 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3039 temp
&= ~SBI_SSCCTL_DISABLE
;
3040 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3042 /* Wait for initialization time */
3045 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3047 mutex_unlock(&dev_priv
->dpio_lock
);
3050 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3051 enum pipe pch_transcoder
)
3053 struct drm_device
*dev
= crtc
->base
.dev
;
3054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3055 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3057 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3058 I915_READ(HTOTAL(cpu_transcoder
)));
3059 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3060 I915_READ(HBLANK(cpu_transcoder
)));
3061 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3062 I915_READ(HSYNC(cpu_transcoder
)));
3064 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3065 I915_READ(VTOTAL(cpu_transcoder
)));
3066 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3067 I915_READ(VBLANK(cpu_transcoder
)));
3068 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3069 I915_READ(VSYNC(cpu_transcoder
)));
3070 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3071 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3075 * Enable PCH resources required for PCH ports:
3077 * - FDI training & RX/TX
3078 * - update transcoder timings
3079 * - DP transcoding bits
3082 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3084 struct drm_device
*dev
= crtc
->dev
;
3085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3086 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3087 int pipe
= intel_crtc
->pipe
;
3090 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3092 /* Write the TU size bits before fdi link training, so that error
3093 * detection works. */
3094 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3095 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3097 /* For PCH output, training FDI link */
3098 dev_priv
->display
.fdi_link_train(crtc
);
3100 /* We need to program the right clock selection before writing the pixel
3101 * mutliplier into the DPLL. */
3102 if (HAS_PCH_CPT(dev
)) {
3105 temp
= I915_READ(PCH_DPLL_SEL
);
3106 temp
|= TRANS_DPLL_ENABLE(pipe
);
3107 sel
= TRANS_DPLLB_SEL(pipe
);
3108 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3112 I915_WRITE(PCH_DPLL_SEL
, temp
);
3115 /* XXX: pch pll's can be enabled any time before we enable the PCH
3116 * transcoder, and we actually should do this to not upset any PCH
3117 * transcoder that already use the clock when we share it.
3119 * Note that enable_shared_dpll tries to do the right thing, but
3120 * get_shared_dpll unconditionally resets the pll - we need that to have
3121 * the right LVDS enable sequence. */
3122 ironlake_enable_shared_dpll(intel_crtc
);
3124 /* set transcoder timing, panel must allow it */
3125 assert_panel_unlocked(dev_priv
, pipe
);
3126 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3128 intel_fdi_normal_train(crtc
);
3130 /* For PCH DP, enable TRANS_DP_CTL */
3131 if (HAS_PCH_CPT(dev
) &&
3132 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3133 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3134 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3135 reg
= TRANS_DP_CTL(pipe
);
3136 temp
= I915_READ(reg
);
3137 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3138 TRANS_DP_SYNC_MASK
|
3140 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3141 TRANS_DP_ENH_FRAMING
);
3142 temp
|= bpc
<< 9; /* same format but at 11:9 */
3144 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3145 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3146 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3147 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3149 switch (intel_trans_dp_port_sel(crtc
)) {
3151 temp
|= TRANS_DP_PORT_SEL_B
;
3154 temp
|= TRANS_DP_PORT_SEL_C
;
3157 temp
|= TRANS_DP_PORT_SEL_D
;
3163 I915_WRITE(reg
, temp
);
3166 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3169 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3171 struct drm_device
*dev
= crtc
->dev
;
3172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3173 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3174 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3176 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3178 lpt_program_iclkip(crtc
);
3180 /* Set transcoder timing. */
3181 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3183 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3186 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3188 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3193 if (pll
->refcount
== 0) {
3194 WARN(1, "bad %s refcount\n", pll
->name
);
3198 if (--pll
->refcount
== 0) {
3200 WARN_ON(pll
->active
);
3203 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3206 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3208 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3209 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3210 enum intel_dpll_id i
;
3213 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3214 crtc
->base
.base
.id
, pll
->name
);
3215 intel_put_shared_dpll(crtc
);
3218 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3219 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3220 i
= (enum intel_dpll_id
) crtc
->pipe
;
3221 pll
= &dev_priv
->shared_dplls
[i
];
3223 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3224 crtc
->base
.base
.id
, pll
->name
);
3229 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3230 pll
= &dev_priv
->shared_dplls
[i
];
3232 /* Only want to check enabled timings first */
3233 if (pll
->refcount
== 0)
3236 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3237 sizeof(pll
->hw_state
)) == 0) {
3238 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3240 pll
->name
, pll
->refcount
, pll
->active
);
3246 /* Ok no matching timings, maybe there's a free one? */
3247 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3248 pll
= &dev_priv
->shared_dplls
[i
];
3249 if (pll
->refcount
== 0) {
3250 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3251 crtc
->base
.base
.id
, pll
->name
);
3259 crtc
->config
.shared_dpll
= i
;
3260 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3261 pipe_name(crtc
->pipe
));
3263 if (pll
->active
== 0) {
3264 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3265 sizeof(pll
->hw_state
));
3267 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3269 assert_shared_dpll_disabled(dev_priv
, pll
);
3271 pll
->mode_set(dev_priv
, pll
);
3278 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3281 int dslreg
= PIPEDSL(pipe
);
3284 temp
= I915_READ(dslreg
);
3286 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3287 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3288 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3292 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3294 struct drm_device
*dev
= crtc
->base
.dev
;
3295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3296 int pipe
= crtc
->pipe
;
3298 if (crtc
->config
.pch_pfit
.enabled
) {
3299 /* Force use of hard-coded filter coefficients
3300 * as some pre-programmed values are broken,
3303 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3304 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3305 PF_PIPE_SEL_IVB(pipe
));
3307 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3308 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3309 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3313 static void intel_enable_planes(struct drm_crtc
*crtc
)
3315 struct drm_device
*dev
= crtc
->dev
;
3316 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3317 struct intel_plane
*intel_plane
;
3319 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3320 if (intel_plane
->pipe
== pipe
)
3321 intel_plane_restore(&intel_plane
->base
);
3324 static void intel_disable_planes(struct drm_crtc
*crtc
)
3326 struct drm_device
*dev
= crtc
->dev
;
3327 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3328 struct intel_plane
*intel_plane
;
3330 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3331 if (intel_plane
->pipe
== pipe
)
3332 intel_plane_disable(&intel_plane
->base
);
3335 static void hsw_enable_ips(struct intel_crtc
*crtc
)
3337 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3339 if (!crtc
->config
.ips_enabled
)
3342 /* We can only enable IPS after we enable a plane and wait for a vblank.
3343 * We guarantee that the plane is enabled by calling intel_enable_ips
3344 * only after intel_enable_plane. And intel_enable_plane already waits
3345 * for a vblank, so all we need to do here is to enable the IPS bit. */
3346 assert_plane_enabled(dev_priv
, crtc
->plane
);
3347 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3350 static void hsw_disable_ips(struct intel_crtc
*crtc
)
3352 struct drm_device
*dev
= crtc
->base
.dev
;
3353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3355 if (!crtc
->config
.ips_enabled
)
3358 assert_plane_enabled(dev_priv
, crtc
->plane
);
3359 I915_WRITE(IPS_CTL
, 0);
3360 POSTING_READ(IPS_CTL
);
3362 /* We need to wait for a vblank before we can disable the plane. */
3363 intel_wait_for_vblank(dev
, crtc
->pipe
);
3366 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3367 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3369 struct drm_device
*dev
= crtc
->dev
;
3370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3371 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3372 enum pipe pipe
= intel_crtc
->pipe
;
3373 int palreg
= PALETTE(pipe
);
3375 bool reenable_ips
= false;
3377 /* The clocks have to be on to load the palette. */
3378 if (!crtc
->enabled
|| !intel_crtc
->active
)
3381 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3382 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3383 assert_dsi_pll_enabled(dev_priv
);
3385 assert_pll_enabled(dev_priv
, pipe
);
3388 /* use legacy palette for Ironlake */
3389 if (HAS_PCH_SPLIT(dev
))
3390 palreg
= LGC_PALETTE(pipe
);
3392 /* Workaround : Do not read or write the pipe palette/gamma data while
3393 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3395 if (intel_crtc
->config
.ips_enabled
&&
3396 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3397 GAMMA_MODE_MODE_SPLIT
)) {
3398 hsw_disable_ips(intel_crtc
);
3399 reenable_ips
= true;
3402 for (i
= 0; i
< 256; i
++) {
3403 I915_WRITE(palreg
+ 4 * i
,
3404 (intel_crtc
->lut_r
[i
] << 16) |
3405 (intel_crtc
->lut_g
[i
] << 8) |
3406 intel_crtc
->lut_b
[i
]);
3410 hsw_enable_ips(intel_crtc
);
3413 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3415 struct drm_device
*dev
= crtc
->dev
;
3416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3417 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3418 struct intel_encoder
*encoder
;
3419 int pipe
= intel_crtc
->pipe
;
3420 int plane
= intel_crtc
->plane
;
3422 WARN_ON(!crtc
->enabled
);
3424 if (intel_crtc
->active
)
3427 intel_crtc
->active
= true;
3429 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3430 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3432 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3433 if (encoder
->pre_enable
)
3434 encoder
->pre_enable(encoder
);
3436 if (intel_crtc
->config
.has_pch_encoder
) {
3437 /* Note: FDI PLL enabling _must_ be done before we enable the
3438 * cpu pipes, hence this is separate from all the other fdi/pch
3440 ironlake_fdi_pll_enable(intel_crtc
);
3442 assert_fdi_tx_disabled(dev_priv
, pipe
);
3443 assert_fdi_rx_disabled(dev_priv
, pipe
);
3446 ironlake_pfit_enable(intel_crtc
);
3449 * On ILK+ LUT must be loaded before the pipe is running but with
3452 intel_crtc_load_lut(crtc
);
3454 intel_update_watermarks(crtc
);
3455 intel_enable_pipe(dev_priv
, pipe
,
3456 intel_crtc
->config
.has_pch_encoder
, false);
3457 intel_enable_plane(dev_priv
, plane
, pipe
);
3458 intel_enable_planes(crtc
);
3459 intel_crtc_update_cursor(crtc
, true);
3461 if (intel_crtc
->config
.has_pch_encoder
)
3462 ironlake_pch_enable(crtc
);
3464 mutex_lock(&dev
->struct_mutex
);
3465 intel_update_fbc(dev
);
3466 mutex_unlock(&dev
->struct_mutex
);
3468 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3469 encoder
->enable(encoder
);
3471 if (HAS_PCH_CPT(dev
))
3472 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3475 * There seems to be a race in PCH platform hw (at least on some
3476 * outputs) where an enabled pipe still completes any pageflip right
3477 * away (as if the pipe is off) instead of waiting for vblank. As soon
3478 * as the first vblank happend, everything works as expected. Hence just
3479 * wait for one vblank before returning to avoid strange things
3482 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3485 /* IPS only exists on ULT machines and is tied to pipe A. */
3486 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3488 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3491 static void haswell_crtc_enable_planes(struct drm_crtc
*crtc
)
3493 struct drm_device
*dev
= crtc
->dev
;
3494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3495 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3496 int pipe
= intel_crtc
->pipe
;
3497 int plane
= intel_crtc
->plane
;
3499 intel_enable_plane(dev_priv
, plane
, pipe
);
3500 intel_enable_planes(crtc
);
3501 intel_crtc_update_cursor(crtc
, true);
3503 hsw_enable_ips(intel_crtc
);
3505 mutex_lock(&dev
->struct_mutex
);
3506 intel_update_fbc(dev
);
3507 mutex_unlock(&dev
->struct_mutex
);
3510 static void haswell_crtc_disable_planes(struct drm_crtc
*crtc
)
3512 struct drm_device
*dev
= crtc
->dev
;
3513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3514 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3515 int pipe
= intel_crtc
->pipe
;
3516 int plane
= intel_crtc
->plane
;
3518 intel_crtc_wait_for_pending_flips(crtc
);
3519 drm_vblank_off(dev
, pipe
);
3521 /* FBC must be disabled before disabling the plane on HSW. */
3522 if (dev_priv
->fbc
.plane
== plane
)
3523 intel_disable_fbc(dev
);
3525 hsw_disable_ips(intel_crtc
);
3527 intel_crtc_update_cursor(crtc
, false);
3528 intel_disable_planes(crtc
);
3529 intel_disable_plane(dev_priv
, plane
, pipe
);
3533 * This implements the workaround described in the "notes" section of the mode
3534 * set sequence documentation. When going from no pipes or single pipe to
3535 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3536 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3538 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
3540 struct drm_device
*dev
= crtc
->base
.dev
;
3541 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
3543 /* We want to get the other_active_crtc only if there's only 1 other
3545 list_for_each_entry(crtc_it
, &dev
->mode_config
.crtc_list
, base
.head
) {
3546 if (!crtc_it
->active
|| crtc_it
== crtc
)
3549 if (other_active_crtc
)
3552 other_active_crtc
= crtc_it
;
3554 if (!other_active_crtc
)
3557 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
3558 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
3561 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3563 struct drm_device
*dev
= crtc
->dev
;
3564 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3565 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3566 struct intel_encoder
*encoder
;
3567 int pipe
= intel_crtc
->pipe
;
3569 WARN_ON(!crtc
->enabled
);
3571 if (intel_crtc
->active
)
3574 intel_crtc
->active
= true;
3576 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3577 if (intel_crtc
->config
.has_pch_encoder
)
3578 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3580 if (intel_crtc
->config
.has_pch_encoder
)
3581 dev_priv
->display
.fdi_link_train(crtc
);
3583 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3584 if (encoder
->pre_enable
)
3585 encoder
->pre_enable(encoder
);
3587 intel_ddi_enable_pipe_clock(intel_crtc
);
3589 ironlake_pfit_enable(intel_crtc
);
3592 * On ILK+ LUT must be loaded before the pipe is running but with
3595 intel_crtc_load_lut(crtc
);
3597 intel_ddi_set_pipe_settings(crtc
);
3598 intel_ddi_enable_transcoder_func(crtc
);
3600 intel_update_watermarks(crtc
);
3601 intel_enable_pipe(dev_priv
, pipe
,
3602 intel_crtc
->config
.has_pch_encoder
, false);
3604 if (intel_crtc
->config
.has_pch_encoder
)
3605 lpt_pch_enable(crtc
);
3607 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3608 encoder
->enable(encoder
);
3609 intel_opregion_notify_encoder(encoder
, true);
3612 /* If we change the relative order between pipe/planes enabling, we need
3613 * to change the workaround. */
3614 haswell_mode_set_planes_workaround(intel_crtc
);
3615 haswell_crtc_enable_planes(crtc
);
3618 * There seems to be a race in PCH platform hw (at least on some
3619 * outputs) where an enabled pipe still completes any pageflip right
3620 * away (as if the pipe is off) instead of waiting for vblank. As soon
3621 * as the first vblank happend, everything works as expected. Hence just
3622 * wait for one vblank before returning to avoid strange things
3625 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3628 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3630 struct drm_device
*dev
= crtc
->base
.dev
;
3631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3632 int pipe
= crtc
->pipe
;
3634 /* To avoid upsetting the power well on haswell only disable the pfit if
3635 * it's in use. The hw state code will make sure we get this right. */
3636 if (crtc
->config
.pch_pfit
.enabled
) {
3637 I915_WRITE(PF_CTL(pipe
), 0);
3638 I915_WRITE(PF_WIN_POS(pipe
), 0);
3639 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3643 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3645 struct drm_device
*dev
= crtc
->dev
;
3646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3647 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3648 struct intel_encoder
*encoder
;
3649 int pipe
= intel_crtc
->pipe
;
3650 int plane
= intel_crtc
->plane
;
3654 if (!intel_crtc
->active
)
3657 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3658 encoder
->disable(encoder
);
3660 intel_crtc_wait_for_pending_flips(crtc
);
3661 drm_vblank_off(dev
, pipe
);
3663 if (dev_priv
->fbc
.plane
== plane
)
3664 intel_disable_fbc(dev
);
3666 intel_crtc_update_cursor(crtc
, false);
3667 intel_disable_planes(crtc
);
3668 intel_disable_plane(dev_priv
, plane
, pipe
);
3670 if (intel_crtc
->config
.has_pch_encoder
)
3671 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3673 intel_disable_pipe(dev_priv
, pipe
);
3675 ironlake_pfit_disable(intel_crtc
);
3677 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3678 if (encoder
->post_disable
)
3679 encoder
->post_disable(encoder
);
3681 if (intel_crtc
->config
.has_pch_encoder
) {
3682 ironlake_fdi_disable(crtc
);
3684 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3685 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3687 if (HAS_PCH_CPT(dev
)) {
3688 /* disable TRANS_DP_CTL */
3689 reg
= TRANS_DP_CTL(pipe
);
3690 temp
= I915_READ(reg
);
3691 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3692 TRANS_DP_PORT_SEL_MASK
);
3693 temp
|= TRANS_DP_PORT_SEL_NONE
;
3694 I915_WRITE(reg
, temp
);
3696 /* disable DPLL_SEL */
3697 temp
= I915_READ(PCH_DPLL_SEL
);
3698 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3699 I915_WRITE(PCH_DPLL_SEL
, temp
);
3702 /* disable PCH DPLL */
3703 intel_disable_shared_dpll(intel_crtc
);
3705 ironlake_fdi_pll_disable(intel_crtc
);
3708 intel_crtc
->active
= false;
3709 intel_update_watermarks(crtc
);
3711 mutex_lock(&dev
->struct_mutex
);
3712 intel_update_fbc(dev
);
3713 mutex_unlock(&dev
->struct_mutex
);
3716 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3718 struct drm_device
*dev
= crtc
->dev
;
3719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3720 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3721 struct intel_encoder
*encoder
;
3722 int pipe
= intel_crtc
->pipe
;
3723 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3725 if (!intel_crtc
->active
)
3728 haswell_crtc_disable_planes(crtc
);
3730 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3731 intel_opregion_notify_encoder(encoder
, false);
3732 encoder
->disable(encoder
);
3735 if (intel_crtc
->config
.has_pch_encoder
)
3736 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3737 intel_disable_pipe(dev_priv
, pipe
);
3739 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3741 ironlake_pfit_disable(intel_crtc
);
3743 intel_ddi_disable_pipe_clock(intel_crtc
);
3745 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3746 if (encoder
->post_disable
)
3747 encoder
->post_disable(encoder
);
3749 if (intel_crtc
->config
.has_pch_encoder
) {
3750 lpt_disable_pch_transcoder(dev_priv
);
3751 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3752 intel_ddi_fdi_disable(crtc
);
3755 intel_crtc
->active
= false;
3756 intel_update_watermarks(crtc
);
3758 mutex_lock(&dev
->struct_mutex
);
3759 intel_update_fbc(dev
);
3760 mutex_unlock(&dev
->struct_mutex
);
3763 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3765 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3766 intel_put_shared_dpll(intel_crtc
);
3769 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3771 intel_ddi_put_crtc_pll(crtc
);
3774 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3776 if (!enable
&& intel_crtc
->overlay
) {
3777 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3780 mutex_lock(&dev
->struct_mutex
);
3781 dev_priv
->mm
.interruptible
= false;
3782 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3783 dev_priv
->mm
.interruptible
= true;
3784 mutex_unlock(&dev
->struct_mutex
);
3787 /* Let userspace switch the overlay on again. In most cases userspace
3788 * has to recompute where to put it anyway.
3793 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3794 * cursor plane briefly if not already running after enabling the display
3796 * This workaround avoids occasional blank screens when self refresh is
3800 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3802 u32 cntl
= I915_READ(CURCNTR(pipe
));
3804 if ((cntl
& CURSOR_MODE
) == 0) {
3805 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3807 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3808 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3809 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3810 I915_WRITE(CURCNTR(pipe
), cntl
);
3811 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3812 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3816 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3818 struct drm_device
*dev
= crtc
->base
.dev
;
3819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3820 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3822 if (!crtc
->config
.gmch_pfit
.control
)
3826 * The panel fitter should only be adjusted whilst the pipe is disabled,
3827 * according to register description and PRM.
3829 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3830 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3832 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3833 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3835 /* Border color in case we don't scale up to the full screen. Black by
3836 * default, change to something else for debugging. */
3837 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3840 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3842 struct drm_device
*dev
= crtc
->dev
;
3843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3844 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3845 struct intel_encoder
*encoder
;
3846 int pipe
= intel_crtc
->pipe
;
3847 int plane
= intel_crtc
->plane
;
3850 WARN_ON(!crtc
->enabled
);
3852 if (intel_crtc
->active
)
3855 intel_crtc
->active
= true;
3857 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3858 if (encoder
->pre_pll_enable
)
3859 encoder
->pre_pll_enable(encoder
);
3861 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
3864 vlv_enable_pll(intel_crtc
);
3866 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3867 if (encoder
->pre_enable
)
3868 encoder
->pre_enable(encoder
);
3870 i9xx_pfit_enable(intel_crtc
);
3872 intel_crtc_load_lut(crtc
);
3874 intel_update_watermarks(crtc
);
3875 intel_enable_pipe(dev_priv
, pipe
, false, is_dsi
);
3876 intel_enable_plane(dev_priv
, plane
, pipe
);
3877 intel_enable_planes(crtc
);
3878 intel_crtc_update_cursor(crtc
, true);
3880 intel_update_fbc(dev
);
3882 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3883 encoder
->enable(encoder
);
3886 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3888 struct drm_device
*dev
= crtc
->dev
;
3889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3891 struct intel_encoder
*encoder
;
3892 int pipe
= intel_crtc
->pipe
;
3893 int plane
= intel_crtc
->plane
;
3895 WARN_ON(!crtc
->enabled
);
3897 if (intel_crtc
->active
)
3900 intel_crtc
->active
= true;
3902 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3903 if (encoder
->pre_enable
)
3904 encoder
->pre_enable(encoder
);
3906 i9xx_enable_pll(intel_crtc
);
3908 i9xx_pfit_enable(intel_crtc
);
3910 intel_crtc_load_lut(crtc
);
3912 intel_update_watermarks(crtc
);
3913 intel_enable_pipe(dev_priv
, pipe
, false, false);
3914 intel_enable_plane(dev_priv
, plane
, pipe
);
3915 intel_enable_planes(crtc
);
3916 /* The fixup needs to happen before cursor is enabled */
3918 g4x_fixup_plane(dev_priv
, pipe
);
3919 intel_crtc_update_cursor(crtc
, true);
3921 /* Give the overlay scaler a chance to enable if it's on this pipe */
3922 intel_crtc_dpms_overlay(intel_crtc
, true);
3924 intel_update_fbc(dev
);
3926 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3927 encoder
->enable(encoder
);
3930 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3932 struct drm_device
*dev
= crtc
->base
.dev
;
3933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3935 if (!crtc
->config
.gmch_pfit
.control
)
3938 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3940 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3941 I915_READ(PFIT_CONTROL
));
3942 I915_WRITE(PFIT_CONTROL
, 0);
3945 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3947 struct drm_device
*dev
= crtc
->dev
;
3948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3949 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3950 struct intel_encoder
*encoder
;
3951 int pipe
= intel_crtc
->pipe
;
3952 int plane
= intel_crtc
->plane
;
3954 if (!intel_crtc
->active
)
3957 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3958 encoder
->disable(encoder
);
3960 /* Give the overlay scaler a chance to disable if it's on this pipe */
3961 intel_crtc_wait_for_pending_flips(crtc
);
3962 drm_vblank_off(dev
, pipe
);
3964 if (dev_priv
->fbc
.plane
== plane
)
3965 intel_disable_fbc(dev
);
3967 intel_crtc_dpms_overlay(intel_crtc
, false);
3968 intel_crtc_update_cursor(crtc
, false);
3969 intel_disable_planes(crtc
);
3970 intel_disable_plane(dev_priv
, plane
, pipe
);
3972 intel_disable_pipe(dev_priv
, pipe
);
3974 i9xx_pfit_disable(intel_crtc
);
3976 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3977 if (encoder
->post_disable
)
3978 encoder
->post_disable(encoder
);
3980 if (IS_VALLEYVIEW(dev
) && !intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3981 vlv_disable_pll(dev_priv
, pipe
);
3982 else if (!IS_VALLEYVIEW(dev
))
3983 i9xx_disable_pll(dev_priv
, pipe
);
3985 intel_crtc
->active
= false;
3986 intel_update_watermarks(crtc
);
3988 intel_update_fbc(dev
);
3991 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3995 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3998 struct drm_device
*dev
= crtc
->dev
;
3999 struct drm_i915_master_private
*master_priv
;
4000 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4001 int pipe
= intel_crtc
->pipe
;
4003 if (!dev
->primary
->master
)
4006 master_priv
= dev
->primary
->master
->driver_priv
;
4007 if (!master_priv
->sarea_priv
)
4012 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4013 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4016 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4017 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4020 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4026 * Sets the power management mode of the pipe and plane.
4028 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
4030 struct drm_device
*dev
= crtc
->dev
;
4031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4032 struct intel_encoder
*intel_encoder
;
4033 bool enable
= false;
4035 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4036 enable
|= intel_encoder
->connectors_active
;
4039 dev_priv
->display
.crtc_enable(crtc
);
4041 dev_priv
->display
.crtc_disable(crtc
);
4043 intel_crtc_update_sarea(crtc
, enable
);
4046 static void intel_crtc_disable(struct drm_crtc
*crtc
)
4048 struct drm_device
*dev
= crtc
->dev
;
4049 struct drm_connector
*connector
;
4050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4051 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4053 /* crtc should still be enabled when we disable it. */
4054 WARN_ON(!crtc
->enabled
);
4056 dev_priv
->display
.crtc_disable(crtc
);
4057 intel_crtc
->eld_vld
= false;
4058 intel_crtc_update_sarea(crtc
, false);
4059 dev_priv
->display
.off(crtc
);
4061 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
4062 assert_cursor_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
4063 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
4066 mutex_lock(&dev
->struct_mutex
);
4067 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
4068 mutex_unlock(&dev
->struct_mutex
);
4072 /* Update computed state. */
4073 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
4074 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
4077 if (connector
->encoder
->crtc
!= crtc
)
4080 connector
->dpms
= DRM_MODE_DPMS_OFF
;
4081 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
4085 void intel_encoder_destroy(struct drm_encoder
*encoder
)
4087 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
4089 drm_encoder_cleanup(encoder
);
4090 kfree(intel_encoder
);
4093 /* Simple dpms helper for encoders with just one connector, no cloning and only
4094 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4095 * state of the entire output pipe. */
4096 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
4098 if (mode
== DRM_MODE_DPMS_ON
) {
4099 encoder
->connectors_active
= true;
4101 intel_crtc_update_dpms(encoder
->base
.crtc
);
4103 encoder
->connectors_active
= false;
4105 intel_crtc_update_dpms(encoder
->base
.crtc
);
4109 /* Cross check the actual hw state with our own modeset state tracking (and it's
4110 * internal consistency). */
4111 static void intel_connector_check_state(struct intel_connector
*connector
)
4113 if (connector
->get_hw_state(connector
)) {
4114 struct intel_encoder
*encoder
= connector
->encoder
;
4115 struct drm_crtc
*crtc
;
4116 bool encoder_enabled
;
4119 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4120 connector
->base
.base
.id
,
4121 drm_get_connector_name(&connector
->base
));
4123 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
4124 "wrong connector dpms state\n");
4125 WARN(connector
->base
.encoder
!= &encoder
->base
,
4126 "active connector not linked to encoder\n");
4127 WARN(!encoder
->connectors_active
,
4128 "encoder->connectors_active not set\n");
4130 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
4131 WARN(!encoder_enabled
, "encoder not enabled\n");
4132 if (WARN_ON(!encoder
->base
.crtc
))
4135 crtc
= encoder
->base
.crtc
;
4137 WARN(!crtc
->enabled
, "crtc not enabled\n");
4138 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
4139 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
4140 "encoder active on the wrong pipe\n");
4144 /* Even simpler default implementation, if there's really no special case to
4146 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
4148 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
4150 /* All the simple cases only support two dpms states. */
4151 if (mode
!= DRM_MODE_DPMS_ON
)
4152 mode
= DRM_MODE_DPMS_OFF
;
4154 if (mode
== connector
->dpms
)
4157 connector
->dpms
= mode
;
4159 /* Only need to change hw state when actually enabled */
4160 if (encoder
->base
.crtc
)
4161 intel_encoder_dpms(encoder
, mode
);
4163 WARN_ON(encoder
->connectors_active
!= false);
4165 intel_modeset_check_state(connector
->dev
);
4168 /* Simple connector->get_hw_state implementation for encoders that support only
4169 * one connector and no cloning and hence the encoder state determines the state
4170 * of the connector. */
4171 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
4174 struct intel_encoder
*encoder
= connector
->encoder
;
4176 return encoder
->get_hw_state(encoder
, &pipe
);
4179 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
4180 struct intel_crtc_config
*pipe_config
)
4182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4183 struct intel_crtc
*pipe_B_crtc
=
4184 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
4186 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4187 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4188 if (pipe_config
->fdi_lanes
> 4) {
4189 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4190 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4194 if (IS_HASWELL(dev
)) {
4195 if (pipe_config
->fdi_lanes
> 2) {
4196 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4197 pipe_config
->fdi_lanes
);
4204 if (INTEL_INFO(dev
)->num_pipes
== 2)
4207 /* Ivybridge 3 pipe is really complicated */
4212 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
4213 pipe_config
->fdi_lanes
> 2) {
4214 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4215 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4220 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
4221 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
4222 if (pipe_config
->fdi_lanes
> 2) {
4223 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4224 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4228 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4238 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4239 struct intel_crtc_config
*pipe_config
)
4241 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4242 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4243 int lane
, link_bw
, fdi_dotclock
;
4244 bool setup_ok
, needs_recompute
= false;
4247 /* FDI is a binary signal running at ~2.7GHz, encoding
4248 * each output octet as 10 bits. The actual frequency
4249 * is stored as a divider into a 100MHz clock, and the
4250 * mode pixel clock is stored in units of 1KHz.
4251 * Hence the bw of each lane in terms of the mode signal
4254 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4256 fdi_dotclock
= adjusted_mode
->crtc_clock
;
4258 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4259 pipe_config
->pipe_bpp
);
4261 pipe_config
->fdi_lanes
= lane
;
4263 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4264 link_bw
, &pipe_config
->fdi_m_n
);
4266 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4267 intel_crtc
->pipe
, pipe_config
);
4268 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4269 pipe_config
->pipe_bpp
-= 2*3;
4270 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4271 pipe_config
->pipe_bpp
);
4272 needs_recompute
= true;
4273 pipe_config
->bw_constrained
= true;
4278 if (needs_recompute
)
4281 return setup_ok
? 0 : -EINVAL
;
4284 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4285 struct intel_crtc_config
*pipe_config
)
4287 pipe_config
->ips_enabled
= i915_enable_ips
&&
4288 hsw_crtc_supports_ips(crtc
) &&
4289 pipe_config
->pipe_bpp
<= 24;
4292 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4293 struct intel_crtc_config
*pipe_config
)
4295 struct drm_device
*dev
= crtc
->base
.dev
;
4296 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4298 /* FIXME should check pixel clock limits on all platforms */
4299 if (INTEL_INFO(dev
)->gen
< 4) {
4300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4302 dev_priv
->display
.get_display_clock_speed(dev
);
4305 * Enable pixel doubling when the dot clock
4306 * is > 90% of the (display) core speed.
4308 * GDG double wide on either pipe,
4309 * otherwise pipe A only.
4311 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
4312 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
4314 pipe_config
->double_wide
= true;
4317 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
4322 * Pipe horizontal size must be even in:
4324 * - LVDS dual channel mode
4325 * - Double wide pipe
4327 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4328 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
4329 pipe_config
->pipe_src_w
&= ~1;
4331 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4332 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4334 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4335 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4338 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4339 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4340 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4341 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4343 pipe_config
->pipe_bpp
= 8*3;
4347 hsw_compute_ips_config(crtc
, pipe_config
);
4349 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4350 * clock survives for now. */
4351 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4352 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4354 if (pipe_config
->has_pch_encoder
)
4355 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4360 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4362 return 400000; /* FIXME */
4365 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4370 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4375 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4380 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
4384 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4386 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4387 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
4389 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
4391 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
4393 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
4396 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
4397 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
4399 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
4404 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4408 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4410 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4413 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4414 case GC_DISPLAY_CLOCK_333_MHZ
:
4417 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4423 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4428 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4431 /* Assume that the hardware is in the high speed state. This
4432 * should be the default.
4434 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4435 case GC_CLOCK_133_200
:
4436 case GC_CLOCK_100_200
:
4438 case GC_CLOCK_166_250
:
4440 case GC_CLOCK_100_133
:
4444 /* Shouldn't happen */
4448 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4454 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4456 while (*num
> DATA_LINK_M_N_MASK
||
4457 *den
> DATA_LINK_M_N_MASK
) {
4463 static void compute_m_n(unsigned int m
, unsigned int n
,
4464 uint32_t *ret_m
, uint32_t *ret_n
)
4466 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4467 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4468 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4472 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4473 int pixel_clock
, int link_clock
,
4474 struct intel_link_m_n
*m_n
)
4478 compute_m_n(bits_per_pixel
* pixel_clock
,
4479 link_clock
* nlanes
* 8,
4480 &m_n
->gmch_m
, &m_n
->gmch_n
);
4482 compute_m_n(pixel_clock
, link_clock
,
4483 &m_n
->link_m
, &m_n
->link_n
);
4486 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4488 if (i915_panel_use_ssc
>= 0)
4489 return i915_panel_use_ssc
!= 0;
4490 return dev_priv
->vbt
.lvds_use_ssc
4491 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4494 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4496 struct drm_device
*dev
= crtc
->dev
;
4497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4500 if (IS_VALLEYVIEW(dev
)) {
4502 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4503 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4504 refclk
= dev_priv
->vbt
.lvds_ssc_freq
* 1000;
4505 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4507 } else if (!IS_GEN2(dev
)) {
4516 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4518 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4521 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4523 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4526 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4527 intel_clock_t
*reduced_clock
)
4529 struct drm_device
*dev
= crtc
->base
.dev
;
4530 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4531 int pipe
= crtc
->pipe
;
4534 if (IS_PINEVIEW(dev
)) {
4535 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4537 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4539 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4541 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4544 I915_WRITE(FP0(pipe
), fp
);
4545 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4547 crtc
->lowfreq_avail
= false;
4548 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4549 reduced_clock
&& i915_powersave
) {
4550 I915_WRITE(FP1(pipe
), fp2
);
4551 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4552 crtc
->lowfreq_avail
= true;
4554 I915_WRITE(FP1(pipe
), fp
);
4555 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4559 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
4565 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4566 * and set it to a reasonable value instead.
4568 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4569 reg_val
&= 0xffffff00;
4570 reg_val
|= 0x00000030;
4571 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4573 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4574 reg_val
&= 0x8cffffff;
4575 reg_val
= 0x8c000000;
4576 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4578 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4579 reg_val
&= 0xffffff00;
4580 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4582 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4583 reg_val
&= 0x00ffffff;
4584 reg_val
|= 0xb0000000;
4585 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4588 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4589 struct intel_link_m_n
*m_n
)
4591 struct drm_device
*dev
= crtc
->base
.dev
;
4592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4593 int pipe
= crtc
->pipe
;
4595 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4596 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4597 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4598 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4601 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4602 struct intel_link_m_n
*m_n
)
4604 struct drm_device
*dev
= crtc
->base
.dev
;
4605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4606 int pipe
= crtc
->pipe
;
4607 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4609 if (INTEL_INFO(dev
)->gen
>= 5) {
4610 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4611 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4612 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4613 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4615 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4616 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4617 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4618 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4622 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4624 if (crtc
->config
.has_pch_encoder
)
4625 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4627 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4630 static void vlv_update_pll(struct intel_crtc
*crtc
)
4632 struct drm_device
*dev
= crtc
->base
.dev
;
4633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4634 int pipe
= crtc
->pipe
;
4636 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4637 u32 coreclk
, reg_val
, dpll_md
;
4639 mutex_lock(&dev_priv
->dpio_lock
);
4641 bestn
= crtc
->config
.dpll
.n
;
4642 bestm1
= crtc
->config
.dpll
.m1
;
4643 bestm2
= crtc
->config
.dpll
.m2
;
4644 bestp1
= crtc
->config
.dpll
.p1
;
4645 bestp2
= crtc
->config
.dpll
.p2
;
4647 /* See eDP HDMI DPIO driver vbios notes doc */
4649 /* PLL B needs special handling */
4651 vlv_pllb_recal_opamp(dev_priv
, pipe
);
4653 /* Set up Tx target for periodic Rcomp update */
4654 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_BCAST
, 0x0100000f);
4656 /* Disable target IRef on PLL */
4657 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
));
4658 reg_val
&= 0x00ffffff;
4659 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
), reg_val
);
4661 /* Disable fast lock */
4662 vlv_dpio_write(dev_priv
, pipe
, DPIO_FASTCLK_DISABLE
, 0x610);
4664 /* Set idtafcrecal before PLL is enabled */
4665 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4666 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4667 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4668 mdiv
|= (1 << DPIO_K_SHIFT
);
4671 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4672 * but we don't support that).
4673 * Note: don't use the DAC post divider as it seems unstable.
4675 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4676 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4678 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4679 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4681 /* Set HBR and RBR LPF coefficients */
4682 if (crtc
->config
.port_clock
== 162000 ||
4683 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4684 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4685 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4688 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4691 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4692 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4693 /* Use SSC source */
4695 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4698 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4700 } else { /* HDMI or VGA */
4701 /* Use bend source */
4703 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4706 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4710 coreclk
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
));
4711 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4712 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4713 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4714 coreclk
|= 0x01000000;
4715 vlv_dpio_write(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
), coreclk
);
4717 vlv_dpio_write(dev_priv
, pipe
, DPIO_PLL_CML(pipe
), 0x87871000);
4719 /* Enable DPIO clock input */
4720 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4721 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4722 /* We should never disable this, set it here for state tracking */
4724 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4725 dpll
|= DPLL_VCO_ENABLE
;
4726 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4728 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4729 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4730 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4732 if (crtc
->config
.has_dp_encoder
)
4733 intel_dp_set_m_n(crtc
);
4735 mutex_unlock(&dev_priv
->dpio_lock
);
4738 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4739 intel_clock_t
*reduced_clock
,
4742 struct drm_device
*dev
= crtc
->base
.dev
;
4743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4746 struct dpll
*clock
= &crtc
->config
.dpll
;
4748 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4750 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4751 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4753 dpll
= DPLL_VGA_MODE_DIS
;
4755 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4756 dpll
|= DPLLB_MODE_LVDS
;
4758 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4760 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4761 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4762 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4766 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4768 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4769 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4771 /* compute bitmask from p1 value */
4772 if (IS_PINEVIEW(dev
))
4773 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4775 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4776 if (IS_G4X(dev
) && reduced_clock
)
4777 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4779 switch (clock
->p2
) {
4781 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4784 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4787 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4790 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4793 if (INTEL_INFO(dev
)->gen
>= 4)
4794 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4796 if (crtc
->config
.sdvo_tv_clock
)
4797 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4798 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4799 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4800 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4802 dpll
|= PLL_REF_INPUT_DREFCLK
;
4804 dpll
|= DPLL_VCO_ENABLE
;
4805 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4807 if (INTEL_INFO(dev
)->gen
>= 4) {
4808 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4809 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4810 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4813 if (crtc
->config
.has_dp_encoder
)
4814 intel_dp_set_m_n(crtc
);
4817 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4818 intel_clock_t
*reduced_clock
,
4821 struct drm_device
*dev
= crtc
->base
.dev
;
4822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4824 struct dpll
*clock
= &crtc
->config
.dpll
;
4826 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4828 dpll
= DPLL_VGA_MODE_DIS
;
4830 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4831 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4834 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4836 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4838 dpll
|= PLL_P2_DIVIDE_BY_4
;
4841 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
4842 dpll
|= DPLL_DVO_2X_MODE
;
4844 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4845 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4846 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4848 dpll
|= PLL_REF_INPUT_DREFCLK
;
4850 dpll
|= DPLL_VCO_ENABLE
;
4851 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4854 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
4856 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4858 enum pipe pipe
= intel_crtc
->pipe
;
4859 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4860 struct drm_display_mode
*adjusted_mode
=
4861 &intel_crtc
->config
.adjusted_mode
;
4862 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
4864 /* We need to be careful not to changed the adjusted mode, for otherwise
4865 * the hw state checker will get angry at the mismatch. */
4866 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
4867 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
4869 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4870 /* the chip adds 2 halflines automatically */
4872 crtc_vblank_end
-= 1;
4873 vsyncshift
= adjusted_mode
->crtc_hsync_start
4874 - adjusted_mode
->crtc_htotal
/ 2;
4879 if (INTEL_INFO(dev
)->gen
> 3)
4880 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4882 I915_WRITE(HTOTAL(cpu_transcoder
),
4883 (adjusted_mode
->crtc_hdisplay
- 1) |
4884 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4885 I915_WRITE(HBLANK(cpu_transcoder
),
4886 (adjusted_mode
->crtc_hblank_start
- 1) |
4887 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4888 I915_WRITE(HSYNC(cpu_transcoder
),
4889 (adjusted_mode
->crtc_hsync_start
- 1) |
4890 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4892 I915_WRITE(VTOTAL(cpu_transcoder
),
4893 (adjusted_mode
->crtc_vdisplay
- 1) |
4894 ((crtc_vtotal
- 1) << 16));
4895 I915_WRITE(VBLANK(cpu_transcoder
),
4896 (adjusted_mode
->crtc_vblank_start
- 1) |
4897 ((crtc_vblank_end
- 1) << 16));
4898 I915_WRITE(VSYNC(cpu_transcoder
),
4899 (adjusted_mode
->crtc_vsync_start
- 1) |
4900 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4902 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4903 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4904 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4906 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4907 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4908 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4910 /* pipesrc controls the size that is scaled from, which should
4911 * always be the user's requested size.
4913 I915_WRITE(PIPESRC(pipe
),
4914 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
4915 (intel_crtc
->config
.pipe_src_h
- 1));
4918 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
4919 struct intel_crtc_config
*pipe_config
)
4921 struct drm_device
*dev
= crtc
->base
.dev
;
4922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4923 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
4926 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
4927 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
4928 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
4929 tmp
= I915_READ(HBLANK(cpu_transcoder
));
4930 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
4931 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4932 tmp
= I915_READ(HSYNC(cpu_transcoder
));
4933 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
4934 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4936 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
4937 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
4938 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
4939 tmp
= I915_READ(VBLANK(cpu_transcoder
));
4940 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
4941 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4942 tmp
= I915_READ(VSYNC(cpu_transcoder
));
4943 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
4944 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4946 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
4947 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
4948 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
4949 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
4952 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
4953 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
4954 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
4956 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
4957 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
4960 static void intel_crtc_mode_from_pipe_config(struct intel_crtc
*intel_crtc
,
4961 struct intel_crtc_config
*pipe_config
)
4963 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4965 crtc
->mode
.hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
4966 crtc
->mode
.htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
4967 crtc
->mode
.hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
4968 crtc
->mode
.hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
4970 crtc
->mode
.vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
4971 crtc
->mode
.vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
4972 crtc
->mode
.vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
4973 crtc
->mode
.vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
4975 crtc
->mode
.flags
= pipe_config
->adjusted_mode
.flags
;
4977 crtc
->mode
.clock
= pipe_config
->adjusted_mode
.crtc_clock
;
4978 crtc
->mode
.flags
|= pipe_config
->adjusted_mode
.flags
;
4981 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4983 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4989 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
4990 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
4991 pipeconf
|= PIPECONF_ENABLE
;
4993 if (intel_crtc
->config
.double_wide
)
4994 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4996 /* only g4x and later have fancy bpc/dither controls */
4997 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
4998 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4999 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
5000 pipeconf
|= PIPECONF_DITHER_EN
|
5001 PIPECONF_DITHER_TYPE_SP
;
5003 switch (intel_crtc
->config
.pipe_bpp
) {
5005 pipeconf
|= PIPECONF_6BPC
;
5008 pipeconf
|= PIPECONF_8BPC
;
5011 pipeconf
|= PIPECONF_10BPC
;
5014 /* Case prevented by intel_choose_pipe_bpp_dither. */
5019 if (HAS_PIPE_CXSR(dev
)) {
5020 if (intel_crtc
->lowfreq_avail
) {
5021 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5022 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
5024 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5028 if (!IS_GEN2(dev
) &&
5029 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5030 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
5032 pipeconf
|= PIPECONF_PROGRESSIVE
;
5034 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
5035 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
5037 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
5038 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
5041 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
5043 struct drm_framebuffer
*fb
)
5045 struct drm_device
*dev
= crtc
->dev
;
5046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5047 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5048 int pipe
= intel_crtc
->pipe
;
5049 int plane
= intel_crtc
->plane
;
5050 int refclk
, num_connectors
= 0;
5051 intel_clock_t clock
, reduced_clock
;
5053 bool ok
, has_reduced_clock
= false;
5054 bool is_lvds
= false, is_dsi
= false;
5055 struct intel_encoder
*encoder
;
5056 const intel_limit_t
*limit
;
5059 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5060 switch (encoder
->type
) {
5061 case INTEL_OUTPUT_LVDS
:
5064 case INTEL_OUTPUT_DSI
:
5075 if (!intel_crtc
->config
.clock_set
) {
5076 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
5079 * Returns a set of divisors for the desired target clock with
5080 * the given refclk, or FALSE. The returned values represent
5081 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5084 limit
= intel_limit(crtc
, refclk
);
5085 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
5086 intel_crtc
->config
.port_clock
,
5087 refclk
, NULL
, &clock
);
5089 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5093 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5095 * Ensure we match the reduced clock's P to the target
5096 * clock. If the clocks don't match, we can't switch
5097 * the display clock by using the FP0/FP1. In such case
5098 * we will disable the LVDS downclock feature.
5101 dev_priv
->display
.find_dpll(limit
, crtc
,
5102 dev_priv
->lvds_downclock
,
5106 /* Compat-code for transition, will disappear. */
5107 intel_crtc
->config
.dpll
.n
= clock
.n
;
5108 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5109 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5110 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5111 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5115 i8xx_update_pll(intel_crtc
,
5116 has_reduced_clock
? &reduced_clock
: NULL
,
5118 } else if (IS_VALLEYVIEW(dev
)) {
5119 vlv_update_pll(intel_crtc
);
5121 i9xx_update_pll(intel_crtc
,
5122 has_reduced_clock
? &reduced_clock
: NULL
,
5127 /* Set up the display plane register */
5128 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
5130 if (!IS_VALLEYVIEW(dev
)) {
5132 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
5134 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
5137 intel_set_pipe_timings(intel_crtc
);
5139 /* pipesrc and dspsize control the size that is scaled from,
5140 * which should always be the user's requested size.
5142 I915_WRITE(DSPSIZE(plane
),
5143 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
5144 (intel_crtc
->config
.pipe_src_w
- 1));
5145 I915_WRITE(DSPPOS(plane
), 0);
5147 i9xx_set_pipeconf(intel_crtc
);
5149 I915_WRITE(DSPCNTR(plane
), dspcntr
);
5150 POSTING_READ(DSPCNTR(plane
));
5152 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5157 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
5158 struct intel_crtc_config
*pipe_config
)
5160 struct drm_device
*dev
= crtc
->base
.dev
;
5161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5164 tmp
= I915_READ(PFIT_CONTROL
);
5165 if (!(tmp
& PFIT_ENABLE
))
5168 /* Check whether the pfit is attached to our pipe. */
5169 if (INTEL_INFO(dev
)->gen
< 4) {
5170 if (crtc
->pipe
!= PIPE_B
)
5173 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
5177 pipe_config
->gmch_pfit
.control
= tmp
;
5178 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
5179 if (INTEL_INFO(dev
)->gen
< 5)
5180 pipe_config
->gmch_pfit
.lvds_border_bits
=
5181 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
5184 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
5185 struct intel_crtc_config
*pipe_config
)
5187 struct drm_device
*dev
= crtc
->base
.dev
;
5188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5189 int pipe
= pipe_config
->cpu_transcoder
;
5190 intel_clock_t clock
;
5192 int refclk
= 100000;
5194 mutex_lock(&dev_priv
->dpio_lock
);
5195 mdiv
= vlv_dpio_read(dev_priv
, pipe
, DPIO_DIV(pipe
));
5196 mutex_unlock(&dev_priv
->dpio_lock
);
5198 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
5199 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
5200 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
5201 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
5202 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
5204 clock
.vco
= refclk
* clock
.m1
* clock
.m2
/ clock
.n
;
5205 clock
.dot
= 2 * clock
.vco
/ (clock
.p1
* clock
.p2
);
5207 pipe_config
->port_clock
= clock
.dot
/ 10;
5210 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
5211 struct intel_crtc_config
*pipe_config
)
5213 struct drm_device
*dev
= crtc
->base
.dev
;
5214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5217 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5218 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5220 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5221 if (!(tmp
& PIPECONF_ENABLE
))
5224 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5225 switch (tmp
& PIPECONF_BPC_MASK
) {
5227 pipe_config
->pipe_bpp
= 18;
5230 pipe_config
->pipe_bpp
= 24;
5232 case PIPECONF_10BPC
:
5233 pipe_config
->pipe_bpp
= 30;
5240 if (INTEL_INFO(dev
)->gen
< 4)
5241 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
5243 intel_get_pipe_timings(crtc
, pipe_config
);
5245 i9xx_get_pfit_config(crtc
, pipe_config
);
5247 if (INTEL_INFO(dev
)->gen
>= 4) {
5248 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
5249 pipe_config
->pixel_multiplier
=
5250 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
5251 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
5252 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
5253 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5254 tmp
= I915_READ(DPLL(crtc
->pipe
));
5255 pipe_config
->pixel_multiplier
=
5256 ((tmp
& SDVO_MULTIPLIER_MASK
)
5257 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
5259 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5260 * port and will be fixed up in the encoder->get_config
5262 pipe_config
->pixel_multiplier
= 1;
5264 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
5265 if (!IS_VALLEYVIEW(dev
)) {
5266 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
5267 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
5269 /* Mask out read-only status bits. */
5270 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
5271 DPLL_PORTC_READY_MASK
|
5272 DPLL_PORTB_READY_MASK
);
5275 if (IS_VALLEYVIEW(dev
))
5276 vlv_crtc_clock_get(crtc
, pipe_config
);
5278 i9xx_crtc_clock_get(crtc
, pipe_config
);
5283 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
5285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5286 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5287 struct intel_encoder
*encoder
;
5289 bool has_lvds
= false;
5290 bool has_cpu_edp
= false;
5291 bool has_panel
= false;
5292 bool has_ck505
= false;
5293 bool can_ssc
= false;
5295 /* We need to take the global config into account */
5296 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5298 switch (encoder
->type
) {
5299 case INTEL_OUTPUT_LVDS
:
5303 case INTEL_OUTPUT_EDP
:
5305 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5311 if (HAS_PCH_IBX(dev
)) {
5312 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5313 can_ssc
= has_ck505
;
5319 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5320 has_panel
, has_lvds
, has_ck505
);
5322 /* Ironlake: try to setup display ref clock before DPLL
5323 * enabling. This is only under driver's control after
5324 * PCH B stepping, previous chipset stepping should be
5325 * ignoring this setting.
5327 val
= I915_READ(PCH_DREF_CONTROL
);
5329 /* As we must carefully and slowly disable/enable each source in turn,
5330 * compute the final state we want first and check if we need to
5331 * make any changes at all.
5334 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5336 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5338 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5340 final
&= ~DREF_SSC_SOURCE_MASK
;
5341 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5342 final
&= ~DREF_SSC1_ENABLE
;
5345 final
|= DREF_SSC_SOURCE_ENABLE
;
5347 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5348 final
|= DREF_SSC1_ENABLE
;
5351 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5352 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5354 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5356 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5358 final
|= DREF_SSC_SOURCE_DISABLE
;
5359 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5365 /* Always enable nonspread source */
5366 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5369 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5371 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5374 val
&= ~DREF_SSC_SOURCE_MASK
;
5375 val
|= DREF_SSC_SOURCE_ENABLE
;
5377 /* SSC must be turned on before enabling the CPU output */
5378 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5379 DRM_DEBUG_KMS("Using SSC on panel\n");
5380 val
|= DREF_SSC1_ENABLE
;
5382 val
&= ~DREF_SSC1_ENABLE
;
5384 /* Get SSC going before enabling the outputs */
5385 I915_WRITE(PCH_DREF_CONTROL
, val
);
5386 POSTING_READ(PCH_DREF_CONTROL
);
5389 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5391 /* Enable CPU source on CPU attached eDP */
5393 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5394 DRM_DEBUG_KMS("Using SSC on eDP\n");
5395 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5398 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5400 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5402 I915_WRITE(PCH_DREF_CONTROL
, val
);
5403 POSTING_READ(PCH_DREF_CONTROL
);
5406 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5408 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5410 /* Turn off CPU output */
5411 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5413 I915_WRITE(PCH_DREF_CONTROL
, val
);
5414 POSTING_READ(PCH_DREF_CONTROL
);
5417 /* Turn off the SSC source */
5418 val
&= ~DREF_SSC_SOURCE_MASK
;
5419 val
|= DREF_SSC_SOURCE_DISABLE
;
5422 val
&= ~DREF_SSC1_ENABLE
;
5424 I915_WRITE(PCH_DREF_CONTROL
, val
);
5425 POSTING_READ(PCH_DREF_CONTROL
);
5429 BUG_ON(val
!= final
);
5432 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
5436 tmp
= I915_READ(SOUTH_CHICKEN2
);
5437 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5438 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5440 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5441 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5442 DRM_ERROR("FDI mPHY reset assert timeout\n");
5444 tmp
= I915_READ(SOUTH_CHICKEN2
);
5445 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5446 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5448 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5449 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
5450 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5453 /* WaMPhyProgramming:hsw */
5454 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
5458 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5459 tmp
&= ~(0xFF << 24);
5460 tmp
|= (0x12 << 24);
5461 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5463 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5465 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5467 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5469 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5471 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5472 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5473 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5475 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5476 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5477 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5479 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5482 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5484 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5487 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5489 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5492 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5494 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5497 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5499 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5500 tmp
&= ~(0xFF << 16);
5501 tmp
|= (0x1C << 16);
5502 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5504 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5505 tmp
&= ~(0xFF << 16);
5506 tmp
|= (0x1C << 16);
5507 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5509 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5511 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5513 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5515 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5517 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5518 tmp
&= ~(0xF << 28);
5520 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5522 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5523 tmp
&= ~(0xF << 28);
5525 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5528 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5529 * Programming" based on the parameters passed:
5530 * - Sequence to enable CLKOUT_DP
5531 * - Sequence to enable CLKOUT_DP without spread
5532 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5534 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
5537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5540 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
5542 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
5543 with_fdi
, "LP PCH doesn't have FDI\n"))
5546 mutex_lock(&dev_priv
->dpio_lock
);
5548 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5549 tmp
&= ~SBI_SSCCTL_DISABLE
;
5550 tmp
|= SBI_SSCCTL_PATHALT
;
5551 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5556 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5557 tmp
&= ~SBI_SSCCTL_PATHALT
;
5558 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5561 lpt_reset_fdi_mphy(dev_priv
);
5562 lpt_program_fdi_mphy(dev_priv
);
5566 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5567 SBI_GEN0
: SBI_DBUFF0
;
5568 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5569 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5570 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5572 mutex_unlock(&dev_priv
->dpio_lock
);
5575 /* Sequence to disable CLKOUT_DP */
5576 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
5578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5581 mutex_lock(&dev_priv
->dpio_lock
);
5583 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5584 SBI_GEN0
: SBI_DBUFF0
;
5585 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5586 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5587 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5589 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5590 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
5591 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
5592 tmp
|= SBI_SSCCTL_PATHALT
;
5593 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5596 tmp
|= SBI_SSCCTL_DISABLE
;
5597 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5600 mutex_unlock(&dev_priv
->dpio_lock
);
5603 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5605 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5606 struct intel_encoder
*encoder
;
5607 bool has_vga
= false;
5609 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5610 switch (encoder
->type
) {
5611 case INTEL_OUTPUT_ANALOG
:
5618 lpt_enable_clkout_dp(dev
, true, true);
5620 lpt_disable_clkout_dp(dev
);
5624 * Initialize reference clocks when the driver loads
5626 void intel_init_pch_refclk(struct drm_device
*dev
)
5628 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5629 ironlake_init_pch_refclk(dev
);
5630 else if (HAS_PCH_LPT(dev
))
5631 lpt_init_pch_refclk(dev
);
5634 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5636 struct drm_device
*dev
= crtc
->dev
;
5637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5638 struct intel_encoder
*encoder
;
5639 int num_connectors
= 0;
5640 bool is_lvds
= false;
5642 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5643 switch (encoder
->type
) {
5644 case INTEL_OUTPUT_LVDS
:
5651 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5652 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5653 dev_priv
->vbt
.lvds_ssc_freq
);
5654 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
5660 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5662 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5663 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5664 int pipe
= intel_crtc
->pipe
;
5669 switch (intel_crtc
->config
.pipe_bpp
) {
5671 val
|= PIPECONF_6BPC
;
5674 val
|= PIPECONF_8BPC
;
5677 val
|= PIPECONF_10BPC
;
5680 val
|= PIPECONF_12BPC
;
5683 /* Case prevented by intel_choose_pipe_bpp_dither. */
5687 if (intel_crtc
->config
.dither
)
5688 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5690 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5691 val
|= PIPECONF_INTERLACED_ILK
;
5693 val
|= PIPECONF_PROGRESSIVE
;
5695 if (intel_crtc
->config
.limited_color_range
)
5696 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5698 I915_WRITE(PIPECONF(pipe
), val
);
5699 POSTING_READ(PIPECONF(pipe
));
5703 * Set up the pipe CSC unit.
5705 * Currently only full range RGB to limited range RGB conversion
5706 * is supported, but eventually this should handle various
5707 * RGB<->YCbCr scenarios as well.
5709 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5711 struct drm_device
*dev
= crtc
->dev
;
5712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5713 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5714 int pipe
= intel_crtc
->pipe
;
5715 uint16_t coeff
= 0x7800; /* 1.0 */
5718 * TODO: Check what kind of values actually come out of the pipe
5719 * with these coeff/postoff values and adjust to get the best
5720 * accuracy. Perhaps we even need to take the bpc value into
5724 if (intel_crtc
->config
.limited_color_range
)
5725 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5728 * GY/GU and RY/RU should be the other way around according
5729 * to BSpec, but reality doesn't agree. Just set them up in
5730 * a way that results in the correct picture.
5732 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5733 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5735 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5736 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5738 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5739 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5741 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5742 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5743 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5745 if (INTEL_INFO(dev
)->gen
> 6) {
5746 uint16_t postoff
= 0;
5748 if (intel_crtc
->config
.limited_color_range
)
5749 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5751 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5752 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5753 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5755 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5757 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5759 if (intel_crtc
->config
.limited_color_range
)
5760 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5762 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5766 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
5768 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5769 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5770 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5775 if (intel_crtc
->config
.dither
)
5776 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5778 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5779 val
|= PIPECONF_INTERLACED_ILK
;
5781 val
|= PIPECONF_PROGRESSIVE
;
5783 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5784 POSTING_READ(PIPECONF(cpu_transcoder
));
5786 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
5787 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
5790 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5791 intel_clock_t
*clock
,
5792 bool *has_reduced_clock
,
5793 intel_clock_t
*reduced_clock
)
5795 struct drm_device
*dev
= crtc
->dev
;
5796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5797 struct intel_encoder
*intel_encoder
;
5799 const intel_limit_t
*limit
;
5800 bool ret
, is_lvds
= false;
5802 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5803 switch (intel_encoder
->type
) {
5804 case INTEL_OUTPUT_LVDS
:
5810 refclk
= ironlake_get_refclk(crtc
);
5813 * Returns a set of divisors for the desired target clock with the given
5814 * refclk, or FALSE. The returned values represent the clock equation:
5815 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5817 limit
= intel_limit(crtc
, refclk
);
5818 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
5819 to_intel_crtc(crtc
)->config
.port_clock
,
5820 refclk
, NULL
, clock
);
5824 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5826 * Ensure we match the reduced clock's P to the target clock.
5827 * If the clocks don't match, we can't switch the display clock
5828 * by using the FP0/FP1. In such case we will disable the LVDS
5829 * downclock feature.
5831 *has_reduced_clock
=
5832 dev_priv
->display
.find_dpll(limit
, crtc
,
5833 dev_priv
->lvds_downclock
,
5841 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5846 temp
= I915_READ(SOUTH_CHICKEN1
);
5847 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5850 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5851 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5853 temp
|= FDI_BC_BIFURCATION_SELECT
;
5854 DRM_DEBUG_KMS("enabling fdi C rx\n");
5855 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5856 POSTING_READ(SOUTH_CHICKEN1
);
5859 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
5861 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5862 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5864 switch (intel_crtc
->pipe
) {
5868 if (intel_crtc
->config
.fdi_lanes
> 2)
5869 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5871 cpt_enable_fdi_bc_bifurcation(dev
);
5875 cpt_enable_fdi_bc_bifurcation(dev
);
5883 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5886 * Account for spread spectrum to avoid
5887 * oversubscribing the link. Max center spread
5888 * is 2.5%; use 5% for safety's sake.
5890 u32 bps
= target_clock
* bpp
* 21 / 20;
5891 return bps
/ (link_bw
* 8) + 1;
5894 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
5896 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
5899 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5901 intel_clock_t
*reduced_clock
, u32
*fp2
)
5903 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5904 struct drm_device
*dev
= crtc
->dev
;
5905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5906 struct intel_encoder
*intel_encoder
;
5908 int factor
, num_connectors
= 0;
5909 bool is_lvds
= false, is_sdvo
= false;
5911 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5912 switch (intel_encoder
->type
) {
5913 case INTEL_OUTPUT_LVDS
:
5916 case INTEL_OUTPUT_SDVO
:
5917 case INTEL_OUTPUT_HDMI
:
5925 /* Enable autotuning of the PLL clock (if permissible) */
5928 if ((intel_panel_use_ssc(dev_priv
) &&
5929 dev_priv
->vbt
.lvds_ssc_freq
== 100) ||
5930 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5932 } else if (intel_crtc
->config
.sdvo_tv_clock
)
5935 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
5938 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5944 dpll
|= DPLLB_MODE_LVDS
;
5946 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5948 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5949 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5952 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5953 if (intel_crtc
->config
.has_dp_encoder
)
5954 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5956 /* compute bitmask from p1 value */
5957 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5959 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5961 switch (intel_crtc
->config
.dpll
.p2
) {
5963 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5966 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5969 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5972 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5976 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5977 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5979 dpll
|= PLL_REF_INPUT_DREFCLK
;
5981 return dpll
| DPLL_VCO_ENABLE
;
5984 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5986 struct drm_framebuffer
*fb
)
5988 struct drm_device
*dev
= crtc
->dev
;
5989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5990 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5991 int pipe
= intel_crtc
->pipe
;
5992 int plane
= intel_crtc
->plane
;
5993 int num_connectors
= 0;
5994 intel_clock_t clock
, reduced_clock
;
5995 u32 dpll
= 0, fp
= 0, fp2
= 0;
5996 bool ok
, has_reduced_clock
= false;
5997 bool is_lvds
= false;
5998 struct intel_encoder
*encoder
;
5999 struct intel_shared_dpll
*pll
;
6002 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6003 switch (encoder
->type
) {
6004 case INTEL_OUTPUT_LVDS
:
6012 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
6013 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
6015 ok
= ironlake_compute_clocks(crtc
, &clock
,
6016 &has_reduced_clock
, &reduced_clock
);
6017 if (!ok
&& !intel_crtc
->config
.clock_set
) {
6018 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6021 /* Compat-code for transition, will disappear. */
6022 if (!intel_crtc
->config
.clock_set
) {
6023 intel_crtc
->config
.dpll
.n
= clock
.n
;
6024 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6025 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6026 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6027 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6030 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6031 if (intel_crtc
->config
.has_pch_encoder
) {
6032 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
6033 if (has_reduced_clock
)
6034 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
6036 dpll
= ironlake_compute_dpll(intel_crtc
,
6037 &fp
, &reduced_clock
,
6038 has_reduced_clock
? &fp2
: NULL
);
6040 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
6041 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
6042 if (has_reduced_clock
)
6043 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
6045 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
6047 pll
= intel_get_shared_dpll(intel_crtc
);
6049 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6054 intel_put_shared_dpll(intel_crtc
);
6056 if (intel_crtc
->config
.has_dp_encoder
)
6057 intel_dp_set_m_n(intel_crtc
);
6059 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
6060 intel_crtc
->lowfreq_avail
= true;
6062 intel_crtc
->lowfreq_avail
= false;
6064 if (intel_crtc
->config
.has_pch_encoder
) {
6065 pll
= intel_crtc_to_shared_dpll(intel_crtc
);
6069 intel_set_pipe_timings(intel_crtc
);
6071 if (intel_crtc
->config
.has_pch_encoder
) {
6072 intel_cpu_transcoder_set_m_n(intel_crtc
,
6073 &intel_crtc
->config
.fdi_m_n
);
6076 if (IS_IVYBRIDGE(dev
))
6077 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
6079 ironlake_set_pipeconf(crtc
);
6081 /* Set up the display plane register */
6082 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
6083 POSTING_READ(DSPCNTR(plane
));
6085 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6090 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
6091 struct intel_link_m_n
*m_n
)
6093 struct drm_device
*dev
= crtc
->base
.dev
;
6094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6095 enum pipe pipe
= crtc
->pipe
;
6097 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
6098 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
6099 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
6101 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
6102 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
6103 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6106 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
6107 enum transcoder transcoder
,
6108 struct intel_link_m_n
*m_n
)
6110 struct drm_device
*dev
= crtc
->base
.dev
;
6111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6112 enum pipe pipe
= crtc
->pipe
;
6114 if (INTEL_INFO(dev
)->gen
>= 5) {
6115 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
6116 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
6117 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
6119 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
6120 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
6121 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6123 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
6124 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
6125 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
6127 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
6128 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
6129 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6133 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
6134 struct intel_crtc_config
*pipe_config
)
6136 if (crtc
->config
.has_pch_encoder
)
6137 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
6139 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6140 &pipe_config
->dp_m_n
);
6143 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
6144 struct intel_crtc_config
*pipe_config
)
6146 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6147 &pipe_config
->fdi_m_n
);
6150 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
6151 struct intel_crtc_config
*pipe_config
)
6153 struct drm_device
*dev
= crtc
->base
.dev
;
6154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6157 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
6159 if (tmp
& PF_ENABLE
) {
6160 pipe_config
->pch_pfit
.enabled
= true;
6161 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
6162 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
6164 /* We currently do not free assignements of panel fitters on
6165 * ivb/hsw (since we don't use the higher upscaling modes which
6166 * differentiates them) so just WARN about this case for now. */
6168 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
6169 PF_PIPE_SEL_IVB(crtc
->pipe
));
6174 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
6175 struct intel_crtc_config
*pipe_config
)
6177 struct drm_device
*dev
= crtc
->base
.dev
;
6178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6181 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6182 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6184 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6185 if (!(tmp
& PIPECONF_ENABLE
))
6188 switch (tmp
& PIPECONF_BPC_MASK
) {
6190 pipe_config
->pipe_bpp
= 18;
6193 pipe_config
->pipe_bpp
= 24;
6195 case PIPECONF_10BPC
:
6196 pipe_config
->pipe_bpp
= 30;
6198 case PIPECONF_12BPC
:
6199 pipe_config
->pipe_bpp
= 36;
6205 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
6206 struct intel_shared_dpll
*pll
;
6208 pipe_config
->has_pch_encoder
= true;
6210 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
6211 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6212 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6214 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6216 if (HAS_PCH_IBX(dev_priv
->dev
)) {
6217 pipe_config
->shared_dpll
=
6218 (enum intel_dpll_id
) crtc
->pipe
;
6220 tmp
= I915_READ(PCH_DPLL_SEL
);
6221 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
6222 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
6224 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
6227 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
6229 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
6230 &pipe_config
->dpll_hw_state
));
6232 tmp
= pipe_config
->dpll_hw_state
.dpll
;
6233 pipe_config
->pixel_multiplier
=
6234 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
6235 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
6237 ironlake_pch_clock_get(crtc
, pipe_config
);
6239 pipe_config
->pixel_multiplier
= 1;
6242 intel_get_pipe_timings(crtc
, pipe_config
);
6244 ironlake_get_pfit_config(crtc
, pipe_config
);
6249 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
6251 struct drm_device
*dev
= dev_priv
->dev
;
6252 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
6253 struct intel_crtc
*crtc
;
6254 unsigned long irqflags
;
6257 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6258 WARN(crtc
->base
.enabled
, "CRTC for pipe %c enabled\n",
6259 pipe_name(crtc
->pipe
));
6261 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
6262 WARN(plls
->spll_refcount
, "SPLL enabled\n");
6263 WARN(plls
->wrpll1_refcount
, "WRPLL1 enabled\n");
6264 WARN(plls
->wrpll2_refcount
, "WRPLL2 enabled\n");
6265 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
6266 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
6267 "CPU PWM1 enabled\n");
6268 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
6269 "CPU PWM2 enabled\n");
6270 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
6271 "PCH PWM1 enabled\n");
6272 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
6273 "Utility pin enabled\n");
6274 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
6276 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
6277 val
= I915_READ(DEIMR
);
6278 WARN((val
& ~DE_PCH_EVENT_IVB
) != val
,
6279 "Unexpected DEIMR bits enabled: 0x%x\n", val
);
6280 val
= I915_READ(SDEIMR
);
6281 WARN((val
| SDE_HOTPLUG_MASK_CPT
) != 0xffffffff,
6282 "Unexpected SDEIMR bits enabled: 0x%x\n", val
);
6283 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
6287 * This function implements pieces of two sequences from BSpec:
6288 * - Sequence for display software to disable LCPLL
6289 * - Sequence for display software to allow package C8+
6290 * The steps implemented here are just the steps that actually touch the LCPLL
6291 * register. Callers should take care of disabling all the display engine
6292 * functions, doing the mode unset, fixing interrupts, etc.
6294 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
6295 bool switch_to_fclk
, bool allow_power_down
)
6299 assert_can_disable_lcpll(dev_priv
);
6301 val
= I915_READ(LCPLL_CTL
);
6303 if (switch_to_fclk
) {
6304 val
|= LCPLL_CD_SOURCE_FCLK
;
6305 I915_WRITE(LCPLL_CTL
, val
);
6307 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
6308 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
6309 DRM_ERROR("Switching to FCLK failed\n");
6311 val
= I915_READ(LCPLL_CTL
);
6314 val
|= LCPLL_PLL_DISABLE
;
6315 I915_WRITE(LCPLL_CTL
, val
);
6316 POSTING_READ(LCPLL_CTL
);
6318 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
6319 DRM_ERROR("LCPLL still locked\n");
6321 val
= I915_READ(D_COMP
);
6322 val
|= D_COMP_COMP_DISABLE
;
6323 mutex_lock(&dev_priv
->rps
.hw_lock
);
6324 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6325 DRM_ERROR("Failed to disable D_COMP\n");
6326 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6327 POSTING_READ(D_COMP
);
6330 if (wait_for((I915_READ(D_COMP
) & D_COMP_RCOMP_IN_PROGRESS
) == 0, 1))
6331 DRM_ERROR("D_COMP RCOMP still in progress\n");
6333 if (allow_power_down
) {
6334 val
= I915_READ(LCPLL_CTL
);
6335 val
|= LCPLL_POWER_DOWN_ALLOW
;
6336 I915_WRITE(LCPLL_CTL
, val
);
6337 POSTING_READ(LCPLL_CTL
);
6342 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6345 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
6349 val
= I915_READ(LCPLL_CTL
);
6351 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
6352 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
6355 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6356 * we'll hang the machine! */
6357 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
);
6359 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
6360 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
6361 I915_WRITE(LCPLL_CTL
, val
);
6362 POSTING_READ(LCPLL_CTL
);
6365 val
= I915_READ(D_COMP
);
6366 val
|= D_COMP_COMP_FORCE
;
6367 val
&= ~D_COMP_COMP_DISABLE
;
6368 mutex_lock(&dev_priv
->rps
.hw_lock
);
6369 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6370 DRM_ERROR("Failed to enable D_COMP\n");
6371 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6372 POSTING_READ(D_COMP
);
6374 val
= I915_READ(LCPLL_CTL
);
6375 val
&= ~LCPLL_PLL_DISABLE
;
6376 I915_WRITE(LCPLL_CTL
, val
);
6378 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
6379 DRM_ERROR("LCPLL not locked yet\n");
6381 if (val
& LCPLL_CD_SOURCE_FCLK
) {
6382 val
= I915_READ(LCPLL_CTL
);
6383 val
&= ~LCPLL_CD_SOURCE_FCLK
;
6384 I915_WRITE(LCPLL_CTL
, val
);
6386 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
6387 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
6388 DRM_ERROR("Switching back to LCPLL failed\n");
6391 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
);
6394 void hsw_enable_pc8_work(struct work_struct
*__work
)
6396 struct drm_i915_private
*dev_priv
=
6397 container_of(to_delayed_work(__work
), struct drm_i915_private
,
6399 struct drm_device
*dev
= dev_priv
->dev
;
6402 if (dev_priv
->pc8
.enabled
)
6405 DRM_DEBUG_KMS("Enabling package C8+\n");
6407 dev_priv
->pc8
.enabled
= true;
6409 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6410 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6411 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6412 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6415 lpt_disable_clkout_dp(dev
);
6416 hsw_pc8_disable_interrupts(dev
);
6417 hsw_disable_lcpll(dev_priv
, true, true);
6420 static void __hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6422 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6423 WARN(dev_priv
->pc8
.disable_count
< 1,
6424 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6426 dev_priv
->pc8
.disable_count
--;
6427 if (dev_priv
->pc8
.disable_count
!= 0)
6430 schedule_delayed_work(&dev_priv
->pc8
.enable_work
,
6431 msecs_to_jiffies(i915_pc8_timeout
));
6434 static void __hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6436 struct drm_device
*dev
= dev_priv
->dev
;
6439 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6440 WARN(dev_priv
->pc8
.disable_count
< 0,
6441 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6443 dev_priv
->pc8
.disable_count
++;
6444 if (dev_priv
->pc8
.disable_count
!= 1)
6447 cancel_delayed_work_sync(&dev_priv
->pc8
.enable_work
);
6448 if (!dev_priv
->pc8
.enabled
)
6451 DRM_DEBUG_KMS("Disabling package C8+\n");
6453 hsw_restore_lcpll(dev_priv
);
6454 hsw_pc8_restore_interrupts(dev
);
6455 lpt_init_pch_refclk(dev
);
6457 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6458 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6459 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
6460 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6463 intel_prepare_ddi(dev
);
6464 i915_gem_init_swizzling(dev
);
6465 mutex_lock(&dev_priv
->rps
.hw_lock
);
6466 gen6_update_ring_freq(dev
);
6467 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6468 dev_priv
->pc8
.enabled
= false;
6471 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6473 mutex_lock(&dev_priv
->pc8
.lock
);
6474 __hsw_enable_package_c8(dev_priv
);
6475 mutex_unlock(&dev_priv
->pc8
.lock
);
6478 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6480 mutex_lock(&dev_priv
->pc8
.lock
);
6481 __hsw_disable_package_c8(dev_priv
);
6482 mutex_unlock(&dev_priv
->pc8
.lock
);
6485 static bool hsw_can_enable_package_c8(struct drm_i915_private
*dev_priv
)
6487 struct drm_device
*dev
= dev_priv
->dev
;
6488 struct intel_crtc
*crtc
;
6491 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6492 if (crtc
->base
.enabled
)
6495 /* This case is still possible since we have the i915.disable_power_well
6496 * parameter and also the KVMr or something else might be requesting the
6498 val
= I915_READ(HSW_PWR_WELL_DRIVER
);
6500 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6507 /* Since we're called from modeset_global_resources there's no way to
6508 * symmetrically increase and decrease the refcount, so we use
6509 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6512 static void hsw_update_package_c8(struct drm_device
*dev
)
6514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6517 if (!i915_enable_pc8
)
6520 mutex_lock(&dev_priv
->pc8
.lock
);
6522 allow
= hsw_can_enable_package_c8(dev_priv
);
6524 if (allow
== dev_priv
->pc8
.requirements_met
)
6527 dev_priv
->pc8
.requirements_met
= allow
;
6530 __hsw_enable_package_c8(dev_priv
);
6532 __hsw_disable_package_c8(dev_priv
);
6535 mutex_unlock(&dev_priv
->pc8
.lock
);
6538 static void hsw_package_c8_gpu_idle(struct drm_i915_private
*dev_priv
)
6540 if (!dev_priv
->pc8
.gpu_idle
) {
6541 dev_priv
->pc8
.gpu_idle
= true;
6542 hsw_enable_package_c8(dev_priv
);
6546 static void hsw_package_c8_gpu_busy(struct drm_i915_private
*dev_priv
)
6548 if (dev_priv
->pc8
.gpu_idle
) {
6549 dev_priv
->pc8
.gpu_idle
= false;
6550 hsw_disable_package_c8(dev_priv
);
6554 static void haswell_modeset_global_resources(struct drm_device
*dev
)
6556 bool enable
= false;
6557 struct intel_crtc
*crtc
;
6559 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6560 if (!crtc
->base
.enabled
)
6563 if (crtc
->pipe
!= PIPE_A
|| crtc
->config
.pch_pfit
.enabled
||
6564 crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
)
6568 intel_set_power_well(dev
, enable
);
6570 hsw_update_package_c8(dev
);
6573 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
6575 struct drm_framebuffer
*fb
)
6577 struct drm_device
*dev
= crtc
->dev
;
6578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6579 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6580 int plane
= intel_crtc
->plane
;
6583 if (!intel_ddi_pll_mode_set(crtc
))
6586 if (intel_crtc
->config
.has_dp_encoder
)
6587 intel_dp_set_m_n(intel_crtc
);
6589 intel_crtc
->lowfreq_avail
= false;
6591 intel_set_pipe_timings(intel_crtc
);
6593 if (intel_crtc
->config
.has_pch_encoder
) {
6594 intel_cpu_transcoder_set_m_n(intel_crtc
,
6595 &intel_crtc
->config
.fdi_m_n
);
6598 haswell_set_pipeconf(crtc
);
6600 intel_set_pipe_csc(crtc
);
6602 /* Set up the display plane register */
6603 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
6604 POSTING_READ(DSPCNTR(plane
));
6606 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6611 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
6612 struct intel_crtc_config
*pipe_config
)
6614 struct drm_device
*dev
= crtc
->base
.dev
;
6615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6616 enum intel_display_power_domain pfit_domain
;
6619 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6620 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6622 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
6623 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
6624 enum pipe trans_edp_pipe
;
6625 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
6627 WARN(1, "unknown pipe linked to edp transcoder\n");
6628 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
6629 case TRANS_DDI_EDP_INPUT_A_ON
:
6630 trans_edp_pipe
= PIPE_A
;
6632 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
6633 trans_edp_pipe
= PIPE_B
;
6635 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
6636 trans_edp_pipe
= PIPE_C
;
6640 if (trans_edp_pipe
== crtc
->pipe
)
6641 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
6644 if (!intel_display_power_enabled(dev
,
6645 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
6648 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
6649 if (!(tmp
& PIPECONF_ENABLE
))
6653 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6654 * DDI E. So just check whether this pipe is wired to DDI E and whether
6655 * the PCH transcoder is on.
6657 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
6658 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
6659 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
6660 pipe_config
->has_pch_encoder
= true;
6662 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
6663 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6664 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6666 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6669 intel_get_pipe_timings(crtc
, pipe_config
);
6671 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
6672 if (intel_display_power_enabled(dev
, pfit_domain
))
6673 ironlake_get_pfit_config(crtc
, pipe_config
);
6675 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
6676 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
6678 pipe_config
->pixel_multiplier
= 1;
6683 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6685 struct drm_framebuffer
*fb
)
6687 struct drm_device
*dev
= crtc
->dev
;
6688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6689 struct intel_encoder
*encoder
;
6690 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6691 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
6692 int pipe
= intel_crtc
->pipe
;
6695 drm_vblank_pre_modeset(dev
, pipe
);
6697 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6699 drm_vblank_post_modeset(dev
, pipe
);
6704 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6705 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6706 encoder
->base
.base
.id
,
6707 drm_get_encoder_name(&encoder
->base
),
6708 mode
->base
.id
, mode
->name
);
6709 encoder
->mode_set(encoder
);
6715 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6716 int reg_eldv
, uint32_t bits_eldv
,
6717 int reg_elda
, uint32_t bits_elda
,
6720 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6721 uint8_t *eld
= connector
->eld
;
6724 i
= I915_READ(reg_eldv
);
6733 i
= I915_READ(reg_elda
);
6735 I915_WRITE(reg_elda
, i
);
6737 for (i
= 0; i
< eld
[2]; i
++)
6738 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6744 static void g4x_write_eld(struct drm_connector
*connector
,
6745 struct drm_crtc
*crtc
)
6747 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6748 uint8_t *eld
= connector
->eld
;
6753 i
= I915_READ(G4X_AUD_VID_DID
);
6755 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6756 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6758 eldv
= G4X_ELDV_DEVCTG
;
6760 if (intel_eld_uptodate(connector
,
6761 G4X_AUD_CNTL_ST
, eldv
,
6762 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6763 G4X_HDMIW_HDMIEDID
))
6766 i
= I915_READ(G4X_AUD_CNTL_ST
);
6767 i
&= ~(eldv
| G4X_ELD_ADDR
);
6768 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6769 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6774 len
= min_t(uint8_t, eld
[2], len
);
6775 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6776 for (i
= 0; i
< len
; i
++)
6777 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6779 i
= I915_READ(G4X_AUD_CNTL_ST
);
6781 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6784 static void haswell_write_eld(struct drm_connector
*connector
,
6785 struct drm_crtc
*crtc
)
6787 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6788 uint8_t *eld
= connector
->eld
;
6789 struct drm_device
*dev
= crtc
->dev
;
6790 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6794 int pipe
= to_intel_crtc(crtc
)->pipe
;
6797 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6798 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6799 int aud_config
= HSW_AUD_CFG(pipe
);
6800 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6803 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6805 /* Audio output enable */
6806 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6807 tmp
= I915_READ(aud_cntrl_st2
);
6808 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6809 I915_WRITE(aud_cntrl_st2
, tmp
);
6811 /* Wait for 1 vertical blank */
6812 intel_wait_for_vblank(dev
, pipe
);
6814 /* Set ELD valid state */
6815 tmp
= I915_READ(aud_cntrl_st2
);
6816 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
6817 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6818 I915_WRITE(aud_cntrl_st2
, tmp
);
6819 tmp
= I915_READ(aud_cntrl_st2
);
6820 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
6822 /* Enable HDMI mode */
6823 tmp
= I915_READ(aud_config
);
6824 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
6825 /* clear N_programing_enable and N_value_index */
6826 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6827 I915_WRITE(aud_config
, tmp
);
6829 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6831 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6832 intel_crtc
->eld_vld
= true;
6834 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6835 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6836 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6837 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6839 I915_WRITE(aud_config
, 0);
6841 if (intel_eld_uptodate(connector
,
6842 aud_cntrl_st2
, eldv
,
6843 aud_cntl_st
, IBX_ELD_ADDRESS
,
6847 i
= I915_READ(aud_cntrl_st2
);
6849 I915_WRITE(aud_cntrl_st2
, i
);
6854 i
= I915_READ(aud_cntl_st
);
6855 i
&= ~IBX_ELD_ADDRESS
;
6856 I915_WRITE(aud_cntl_st
, i
);
6857 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6858 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6860 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6861 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6862 for (i
= 0; i
< len
; i
++)
6863 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6865 i
= I915_READ(aud_cntrl_st2
);
6867 I915_WRITE(aud_cntrl_st2
, i
);
6871 static void ironlake_write_eld(struct drm_connector
*connector
,
6872 struct drm_crtc
*crtc
)
6874 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6875 uint8_t *eld
= connector
->eld
;
6883 int pipe
= to_intel_crtc(crtc
)->pipe
;
6885 if (HAS_PCH_IBX(connector
->dev
)) {
6886 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6887 aud_config
= IBX_AUD_CFG(pipe
);
6888 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6889 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6891 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6892 aud_config
= CPT_AUD_CFG(pipe
);
6893 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6894 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6897 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6899 i
= I915_READ(aud_cntl_st
);
6900 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6902 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6903 /* operate blindly on all ports */
6904 eldv
= IBX_ELD_VALIDB
;
6905 eldv
|= IBX_ELD_VALIDB
<< 4;
6906 eldv
|= IBX_ELD_VALIDB
<< 8;
6908 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6909 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6912 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6913 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6914 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6915 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6917 I915_WRITE(aud_config
, 0);
6919 if (intel_eld_uptodate(connector
,
6920 aud_cntrl_st2
, eldv
,
6921 aud_cntl_st
, IBX_ELD_ADDRESS
,
6925 i
= I915_READ(aud_cntrl_st2
);
6927 I915_WRITE(aud_cntrl_st2
, i
);
6932 i
= I915_READ(aud_cntl_st
);
6933 i
&= ~IBX_ELD_ADDRESS
;
6934 I915_WRITE(aud_cntl_st
, i
);
6936 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6937 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6938 for (i
= 0; i
< len
; i
++)
6939 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6941 i
= I915_READ(aud_cntrl_st2
);
6943 I915_WRITE(aud_cntrl_st2
, i
);
6946 void intel_write_eld(struct drm_encoder
*encoder
,
6947 struct drm_display_mode
*mode
)
6949 struct drm_crtc
*crtc
= encoder
->crtc
;
6950 struct drm_connector
*connector
;
6951 struct drm_device
*dev
= encoder
->dev
;
6952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6954 connector
= drm_select_eld(encoder
, mode
);
6958 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6960 drm_get_connector_name(connector
),
6961 connector
->encoder
->base
.id
,
6962 drm_get_encoder_name(connector
->encoder
));
6964 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6966 if (dev_priv
->display
.write_eld
)
6967 dev_priv
->display
.write_eld(connector
, crtc
);
6970 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6972 struct drm_device
*dev
= crtc
->dev
;
6973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6974 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6975 bool visible
= base
!= 0;
6978 if (intel_crtc
->cursor_visible
== visible
)
6981 cntl
= I915_READ(_CURACNTR
);
6983 /* On these chipsets we can only modify the base whilst
6984 * the cursor is disabled.
6986 I915_WRITE(_CURABASE
, base
);
6988 cntl
&= ~(CURSOR_FORMAT_MASK
);
6989 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6990 cntl
|= CURSOR_ENABLE
|
6991 CURSOR_GAMMA_ENABLE
|
6994 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6995 I915_WRITE(_CURACNTR
, cntl
);
6997 intel_crtc
->cursor_visible
= visible
;
7000 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7002 struct drm_device
*dev
= crtc
->dev
;
7003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7004 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7005 int pipe
= intel_crtc
->pipe
;
7006 bool visible
= base
!= 0;
7008 if (intel_crtc
->cursor_visible
!= visible
) {
7009 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
7011 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
7012 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
7013 cntl
|= pipe
<< 28; /* Connect to correct pipe */
7015 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
7016 cntl
|= CURSOR_MODE_DISABLE
;
7018 I915_WRITE(CURCNTR(pipe
), cntl
);
7020 intel_crtc
->cursor_visible
= visible
;
7022 /* and commit changes on next vblank */
7023 I915_WRITE(CURBASE(pipe
), base
);
7026 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7028 struct drm_device
*dev
= crtc
->dev
;
7029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7030 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7031 int pipe
= intel_crtc
->pipe
;
7032 bool visible
= base
!= 0;
7034 if (intel_crtc
->cursor_visible
!= visible
) {
7035 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
7037 cntl
&= ~CURSOR_MODE
;
7038 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
7040 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
7041 cntl
|= CURSOR_MODE_DISABLE
;
7043 if (IS_HASWELL(dev
)) {
7044 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
7045 cntl
&= ~CURSOR_TRICKLE_FEED_DISABLE
;
7047 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
7049 intel_crtc
->cursor_visible
= visible
;
7051 /* and commit changes on next vblank */
7052 I915_WRITE(CURBASE_IVB(pipe
), base
);
7055 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7056 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
7059 struct drm_device
*dev
= crtc
->dev
;
7060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7061 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7062 int pipe
= intel_crtc
->pipe
;
7063 int x
= intel_crtc
->cursor_x
;
7064 int y
= intel_crtc
->cursor_y
;
7065 u32 base
= 0, pos
= 0;
7069 base
= intel_crtc
->cursor_addr
;
7071 if (x
>= intel_crtc
->config
.pipe_src_w
)
7074 if (y
>= intel_crtc
->config
.pipe_src_h
)
7078 if (x
+ intel_crtc
->cursor_width
<= 0)
7081 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
7084 pos
|= x
<< CURSOR_X_SHIFT
;
7087 if (y
+ intel_crtc
->cursor_height
<= 0)
7090 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
7093 pos
|= y
<< CURSOR_Y_SHIFT
;
7095 visible
= base
!= 0;
7096 if (!visible
&& !intel_crtc
->cursor_visible
)
7099 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
7100 I915_WRITE(CURPOS_IVB(pipe
), pos
);
7101 ivb_update_cursor(crtc
, base
);
7103 I915_WRITE(CURPOS(pipe
), pos
);
7104 if (IS_845G(dev
) || IS_I865G(dev
))
7105 i845_update_cursor(crtc
, base
);
7107 i9xx_update_cursor(crtc
, base
);
7111 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
7112 struct drm_file
*file
,
7114 uint32_t width
, uint32_t height
)
7116 struct drm_device
*dev
= crtc
->dev
;
7117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7118 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7119 struct drm_i915_gem_object
*obj
;
7123 /* if we want to turn off the cursor ignore width and height */
7125 DRM_DEBUG_KMS("cursor off\n");
7128 mutex_lock(&dev
->struct_mutex
);
7132 /* Currently we only support 64x64 cursors */
7133 if (width
!= 64 || height
!= 64) {
7134 DRM_ERROR("we currently only support 64x64 cursors\n");
7138 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
7139 if (&obj
->base
== NULL
)
7142 if (obj
->base
.size
< width
* height
* 4) {
7143 DRM_ERROR("buffer is to small\n");
7148 /* we only need to pin inside GTT if cursor is non-phy */
7149 mutex_lock(&dev
->struct_mutex
);
7150 if (!dev_priv
->info
->cursor_needs_physical
) {
7153 if (obj
->tiling_mode
) {
7154 DRM_ERROR("cursor cannot be tiled\n");
7159 /* Note that the w/a also requires 2 PTE of padding following
7160 * the bo. We currently fill all unused PTE with the shadow
7161 * page and so we should always have valid PTE following the
7162 * cursor preventing the VT-d warning.
7165 if (need_vtd_wa(dev
))
7166 alignment
= 64*1024;
7168 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
7170 DRM_ERROR("failed to move cursor bo into the GTT\n");
7174 ret
= i915_gem_object_put_fence(obj
);
7176 DRM_ERROR("failed to release fence for cursor");
7180 addr
= i915_gem_obj_ggtt_offset(obj
);
7182 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
7183 ret
= i915_gem_attach_phys_object(dev
, obj
,
7184 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
7187 DRM_ERROR("failed to attach phys object\n");
7190 addr
= obj
->phys_obj
->handle
->busaddr
;
7194 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
7197 if (intel_crtc
->cursor_bo
) {
7198 if (dev_priv
->info
->cursor_needs_physical
) {
7199 if (intel_crtc
->cursor_bo
!= obj
)
7200 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
7202 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
7203 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
7206 mutex_unlock(&dev
->struct_mutex
);
7208 intel_crtc
->cursor_addr
= addr
;
7209 intel_crtc
->cursor_bo
= obj
;
7210 intel_crtc
->cursor_width
= width
;
7211 intel_crtc
->cursor_height
= height
;
7213 if (intel_crtc
->active
)
7214 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7218 i915_gem_object_unpin_from_display_plane(obj
);
7220 mutex_unlock(&dev
->struct_mutex
);
7222 drm_gem_object_unreference_unlocked(&obj
->base
);
7226 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
7228 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7230 intel_crtc
->cursor_x
= x
;
7231 intel_crtc
->cursor_y
= y
;
7233 if (intel_crtc
->active
)
7234 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7239 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
7240 u16
*blue
, uint32_t start
, uint32_t size
)
7242 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
7243 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7245 for (i
= start
; i
< end
; i
++) {
7246 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
7247 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
7248 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
7251 intel_crtc_load_lut(crtc
);
7254 /* VESA 640x480x72Hz mode to set on the pipe */
7255 static struct drm_display_mode load_detect_mode
= {
7256 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
7257 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
7260 static struct drm_framebuffer
*
7261 intel_framebuffer_create(struct drm_device
*dev
,
7262 struct drm_mode_fb_cmd2
*mode_cmd
,
7263 struct drm_i915_gem_object
*obj
)
7265 struct intel_framebuffer
*intel_fb
;
7268 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7270 drm_gem_object_unreference_unlocked(&obj
->base
);
7271 return ERR_PTR(-ENOMEM
);
7274 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
7276 drm_gem_object_unreference_unlocked(&obj
->base
);
7278 return ERR_PTR(ret
);
7281 return &intel_fb
->base
;
7285 intel_framebuffer_pitch_for_width(int width
, int bpp
)
7287 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
7288 return ALIGN(pitch
, 64);
7292 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
7294 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
7295 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
7298 static struct drm_framebuffer
*
7299 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
7300 struct drm_display_mode
*mode
,
7303 struct drm_i915_gem_object
*obj
;
7304 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
7306 obj
= i915_gem_alloc_object(dev
,
7307 intel_framebuffer_size_for_mode(mode
, bpp
));
7309 return ERR_PTR(-ENOMEM
);
7311 mode_cmd
.width
= mode
->hdisplay
;
7312 mode_cmd
.height
= mode
->vdisplay
;
7313 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
7315 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
7317 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
7320 static struct drm_framebuffer
*
7321 mode_fits_in_fbdev(struct drm_device
*dev
,
7322 struct drm_display_mode
*mode
)
7324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7325 struct drm_i915_gem_object
*obj
;
7326 struct drm_framebuffer
*fb
;
7328 if (dev_priv
->fbdev
== NULL
)
7331 obj
= dev_priv
->fbdev
->ifb
.obj
;
7335 fb
= &dev_priv
->fbdev
->ifb
.base
;
7336 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
7337 fb
->bits_per_pixel
))
7340 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
7346 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
7347 struct drm_display_mode
*mode
,
7348 struct intel_load_detect_pipe
*old
)
7350 struct intel_crtc
*intel_crtc
;
7351 struct intel_encoder
*intel_encoder
=
7352 intel_attached_encoder(connector
);
7353 struct drm_crtc
*possible_crtc
;
7354 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7355 struct drm_crtc
*crtc
= NULL
;
7356 struct drm_device
*dev
= encoder
->dev
;
7357 struct drm_framebuffer
*fb
;
7360 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7361 connector
->base
.id
, drm_get_connector_name(connector
),
7362 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7365 * Algorithm gets a little messy:
7367 * - if the connector already has an assigned crtc, use it (but make
7368 * sure it's on first)
7370 * - try to find the first unused crtc that can drive this connector,
7371 * and use that if we find one
7374 /* See if we already have a CRTC for this connector */
7375 if (encoder
->crtc
) {
7376 crtc
= encoder
->crtc
;
7378 mutex_lock(&crtc
->mutex
);
7380 old
->dpms_mode
= connector
->dpms
;
7381 old
->load_detect_temp
= false;
7383 /* Make sure the crtc and connector are running */
7384 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
7385 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
7390 /* Find an unused one (if possible) */
7391 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
7393 if (!(encoder
->possible_crtcs
& (1 << i
)))
7395 if (!possible_crtc
->enabled
) {
7396 crtc
= possible_crtc
;
7402 * If we didn't find an unused CRTC, don't use any.
7405 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7409 mutex_lock(&crtc
->mutex
);
7410 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
7411 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
7413 intel_crtc
= to_intel_crtc(crtc
);
7414 old
->dpms_mode
= connector
->dpms
;
7415 old
->load_detect_temp
= true;
7416 old
->release_fb
= NULL
;
7419 mode
= &load_detect_mode
;
7421 /* We need a framebuffer large enough to accommodate all accesses
7422 * that the plane may generate whilst we perform load detection.
7423 * We can not rely on the fbcon either being present (we get called
7424 * during its initialisation to detect all boot displays, or it may
7425 * not even exist) or that it is large enough to satisfy the
7428 fb
= mode_fits_in_fbdev(dev
, mode
);
7430 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7431 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
7432 old
->release_fb
= fb
;
7434 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7436 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7437 mutex_unlock(&crtc
->mutex
);
7441 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
7442 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7443 if (old
->release_fb
)
7444 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7445 mutex_unlock(&crtc
->mutex
);
7449 /* let the connector get through one full cycle before testing */
7450 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
7454 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
7455 struct intel_load_detect_pipe
*old
)
7457 struct intel_encoder
*intel_encoder
=
7458 intel_attached_encoder(connector
);
7459 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7460 struct drm_crtc
*crtc
= encoder
->crtc
;
7462 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7463 connector
->base
.id
, drm_get_connector_name(connector
),
7464 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7466 if (old
->load_detect_temp
) {
7467 to_intel_connector(connector
)->new_encoder
= NULL
;
7468 intel_encoder
->new_crtc
= NULL
;
7469 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
7471 if (old
->release_fb
) {
7472 drm_framebuffer_unregister_private(old
->release_fb
);
7473 drm_framebuffer_unreference(old
->release_fb
);
7476 mutex_unlock(&crtc
->mutex
);
7480 /* Switch crtc and encoder back off if necessary */
7481 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
7482 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
7484 mutex_unlock(&crtc
->mutex
);
7487 static int i9xx_pll_refclk(struct drm_device
*dev
,
7488 const struct intel_crtc_config
*pipe_config
)
7490 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7491 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7493 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
7494 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
7495 else if (HAS_PCH_SPLIT(dev
))
7497 else if (!IS_GEN2(dev
))
7503 /* Returns the clock of the currently programmed mode of the given pipe. */
7504 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
7505 struct intel_crtc_config
*pipe_config
)
7507 struct drm_device
*dev
= crtc
->base
.dev
;
7508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7509 int pipe
= pipe_config
->cpu_transcoder
;
7510 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7512 intel_clock_t clock
;
7513 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
7515 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
7516 fp
= pipe_config
->dpll_hw_state
.fp0
;
7518 fp
= pipe_config
->dpll_hw_state
.fp1
;
7520 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
7521 if (IS_PINEVIEW(dev
)) {
7522 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
7523 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7525 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
7526 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7529 if (!IS_GEN2(dev
)) {
7530 if (IS_PINEVIEW(dev
))
7531 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
7532 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
7534 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
7535 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7537 switch (dpll
& DPLL_MODE_MASK
) {
7538 case DPLLB_MODE_DAC_SERIAL
:
7539 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
7542 case DPLLB_MODE_LVDS
:
7543 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
7547 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7548 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
7552 if (IS_PINEVIEW(dev
))
7553 pineview_clock(refclk
, &clock
);
7555 i9xx_clock(refclk
, &clock
);
7557 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
7560 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
7561 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7564 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
7567 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
7568 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
7570 if (dpll
& PLL_P2_DIVIDE_BY_4
)
7576 i9xx_clock(refclk
, &clock
);
7580 * This value includes pixel_multiplier. We will use
7581 * port_clock to compute adjusted_mode.crtc_clock in the
7582 * encoder's get_config() function.
7584 pipe_config
->port_clock
= clock
.dot
;
7587 int intel_dotclock_calculate(int link_freq
,
7588 const struct intel_link_m_n
*m_n
)
7591 * The calculation for the data clock is:
7592 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7593 * But we want to avoid losing precison if possible, so:
7594 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7596 * and the link clock is simpler:
7597 * link_clock = (m * link_clock) / n
7603 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
7606 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
7607 struct intel_crtc_config
*pipe_config
)
7609 struct drm_device
*dev
= crtc
->base
.dev
;
7611 /* read out port_clock from the DPLL */
7612 i9xx_crtc_clock_get(crtc
, pipe_config
);
7615 * This value does not include pixel_multiplier.
7616 * We will check that port_clock and adjusted_mode.crtc_clock
7617 * agree once we know their relationship in the encoder's
7618 * get_config() function.
7620 pipe_config
->adjusted_mode
.crtc_clock
=
7621 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
7622 &pipe_config
->fdi_m_n
);
7625 /** Returns the currently programmed mode of the given pipe. */
7626 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
7627 struct drm_crtc
*crtc
)
7629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7630 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7631 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7632 struct drm_display_mode
*mode
;
7633 struct intel_crtc_config pipe_config
;
7634 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
7635 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
7636 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
7637 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
7638 enum pipe pipe
= intel_crtc
->pipe
;
7640 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
7645 * Construct a pipe_config sufficient for getting the clock info
7646 * back out of crtc_clock_get.
7648 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7649 * to use a real value here instead.
7651 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
7652 pipe_config
.pixel_multiplier
= 1;
7653 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
7654 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
7655 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
7656 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
7658 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
7659 mode
->hdisplay
= (htot
& 0xffff) + 1;
7660 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
7661 mode
->hsync_start
= (hsync
& 0xffff) + 1;
7662 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
7663 mode
->vdisplay
= (vtot
& 0xffff) + 1;
7664 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
7665 mode
->vsync_start
= (vsync
& 0xffff) + 1;
7666 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
7668 drm_mode_set_name(mode
);
7673 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
7675 struct drm_device
*dev
= crtc
->dev
;
7676 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7677 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7678 int pipe
= intel_crtc
->pipe
;
7679 int dpll_reg
= DPLL(pipe
);
7682 if (HAS_PCH_SPLIT(dev
))
7685 if (!dev_priv
->lvds_downclock_avail
)
7688 dpll
= I915_READ(dpll_reg
);
7689 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
7690 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7692 assert_panel_unlocked(dev_priv
, pipe
);
7694 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
7695 I915_WRITE(dpll_reg
, dpll
);
7696 intel_wait_for_vblank(dev
, pipe
);
7698 dpll
= I915_READ(dpll_reg
);
7699 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7700 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7704 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7706 struct drm_device
*dev
= crtc
->dev
;
7707 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7708 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7710 if (HAS_PCH_SPLIT(dev
))
7713 if (!dev_priv
->lvds_downclock_avail
)
7717 * Since this is called by a timer, we should never get here in
7720 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7721 int pipe
= intel_crtc
->pipe
;
7722 int dpll_reg
= DPLL(pipe
);
7725 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7727 assert_panel_unlocked(dev_priv
, pipe
);
7729 dpll
= I915_READ(dpll_reg
);
7730 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7731 I915_WRITE(dpll_reg
, dpll
);
7732 intel_wait_for_vblank(dev
, pipe
);
7733 dpll
= I915_READ(dpll_reg
);
7734 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7735 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7740 void intel_mark_busy(struct drm_device
*dev
)
7742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7744 hsw_package_c8_gpu_busy(dev_priv
);
7745 i915_update_gfx_val(dev_priv
);
7748 void intel_mark_idle(struct drm_device
*dev
)
7750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7751 struct drm_crtc
*crtc
;
7753 hsw_package_c8_gpu_idle(dev_priv
);
7755 if (!i915_powersave
)
7758 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7762 intel_decrease_pllclock(crtc
);
7765 if (dev_priv
->info
->gen
>= 6)
7766 gen6_rps_idle(dev
->dev_private
);
7769 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
7770 struct intel_ring_buffer
*ring
)
7772 struct drm_device
*dev
= obj
->base
.dev
;
7773 struct drm_crtc
*crtc
;
7775 if (!i915_powersave
)
7778 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7782 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
7785 intel_increase_pllclock(crtc
);
7786 if (ring
&& intel_fbc_enabled(dev
))
7787 ring
->fbc_dirty
= true;
7791 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7793 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7794 struct drm_device
*dev
= crtc
->dev
;
7795 struct intel_unpin_work
*work
;
7796 unsigned long flags
;
7798 spin_lock_irqsave(&dev
->event_lock
, flags
);
7799 work
= intel_crtc
->unpin_work
;
7800 intel_crtc
->unpin_work
= NULL
;
7801 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7804 cancel_work_sync(&work
->work
);
7808 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
7810 drm_crtc_cleanup(crtc
);
7815 static void intel_unpin_work_fn(struct work_struct
*__work
)
7817 struct intel_unpin_work
*work
=
7818 container_of(__work
, struct intel_unpin_work
, work
);
7819 struct drm_device
*dev
= work
->crtc
->dev
;
7821 mutex_lock(&dev
->struct_mutex
);
7822 intel_unpin_fb_obj(work
->old_fb_obj
);
7823 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7824 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7826 intel_update_fbc(dev
);
7827 mutex_unlock(&dev
->struct_mutex
);
7829 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7830 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7835 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7836 struct drm_crtc
*crtc
)
7838 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7839 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7840 struct intel_unpin_work
*work
;
7841 unsigned long flags
;
7843 /* Ignore early vblank irqs */
7844 if (intel_crtc
== NULL
)
7847 spin_lock_irqsave(&dev
->event_lock
, flags
);
7848 work
= intel_crtc
->unpin_work
;
7850 /* Ensure we don't miss a work->pending update ... */
7853 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7854 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7858 /* and that the unpin work is consistent wrt ->pending. */
7861 intel_crtc
->unpin_work
= NULL
;
7864 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7866 drm_vblank_put(dev
, intel_crtc
->pipe
);
7868 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7870 wake_up_all(&dev_priv
->pending_flip_queue
);
7872 queue_work(dev_priv
->wq
, &work
->work
);
7874 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7877 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7879 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7880 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7882 do_intel_finish_page_flip(dev
, crtc
);
7885 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7887 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7888 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7890 do_intel_finish_page_flip(dev
, crtc
);
7893 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7895 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7896 struct intel_crtc
*intel_crtc
=
7897 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7898 unsigned long flags
;
7900 /* NB: An MMIO update of the plane base pointer will also
7901 * generate a page-flip completion irq, i.e. every modeset
7902 * is also accompanied by a spurious intel_prepare_page_flip().
7904 spin_lock_irqsave(&dev
->event_lock
, flags
);
7905 if (intel_crtc
->unpin_work
)
7906 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7907 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7910 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7912 /* Ensure that the work item is consistent when activating it ... */
7914 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7915 /* and that it is marked active as soon as the irq could fire. */
7919 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7920 struct drm_crtc
*crtc
,
7921 struct drm_framebuffer
*fb
,
7922 struct drm_i915_gem_object
*obj
,
7925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7926 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7928 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7931 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7935 ret
= intel_ring_begin(ring
, 6);
7939 /* Can't queue multiple flips, so wait for the previous
7940 * one to finish before executing the next.
7942 if (intel_crtc
->plane
)
7943 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7945 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7946 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7947 intel_ring_emit(ring
, MI_NOOP
);
7948 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7949 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7950 intel_ring_emit(ring
, fb
->pitches
[0]);
7951 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7952 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7954 intel_mark_page_flip_active(intel_crtc
);
7955 __intel_ring_advance(ring
);
7959 intel_unpin_fb_obj(obj
);
7964 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7965 struct drm_crtc
*crtc
,
7966 struct drm_framebuffer
*fb
,
7967 struct drm_i915_gem_object
*obj
,
7970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7971 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7973 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7976 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7980 ret
= intel_ring_begin(ring
, 6);
7984 if (intel_crtc
->plane
)
7985 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7987 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7988 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7989 intel_ring_emit(ring
, MI_NOOP
);
7990 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7991 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7992 intel_ring_emit(ring
, fb
->pitches
[0]);
7993 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7994 intel_ring_emit(ring
, MI_NOOP
);
7996 intel_mark_page_flip_active(intel_crtc
);
7997 __intel_ring_advance(ring
);
8001 intel_unpin_fb_obj(obj
);
8006 static int intel_gen4_queue_flip(struct drm_device
*dev
,
8007 struct drm_crtc
*crtc
,
8008 struct drm_framebuffer
*fb
,
8009 struct drm_i915_gem_object
*obj
,
8012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8013 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8014 uint32_t pf
, pipesrc
;
8015 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8018 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8022 ret
= intel_ring_begin(ring
, 4);
8026 /* i965+ uses the linear or tiled offsets from the
8027 * Display Registers (which do not change across a page-flip)
8028 * so we need only reprogram the base address.
8030 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8031 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8032 intel_ring_emit(ring
, fb
->pitches
[0]);
8033 intel_ring_emit(ring
,
8034 (i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
) |
8037 /* XXX Enabling the panel-fitter across page-flip is so far
8038 * untested on non-native modes, so ignore it for now.
8039 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8042 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
8043 intel_ring_emit(ring
, pf
| pipesrc
);
8045 intel_mark_page_flip_active(intel_crtc
);
8046 __intel_ring_advance(ring
);
8050 intel_unpin_fb_obj(obj
);
8055 static int intel_gen6_queue_flip(struct drm_device
*dev
,
8056 struct drm_crtc
*crtc
,
8057 struct drm_framebuffer
*fb
,
8058 struct drm_i915_gem_object
*obj
,
8061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8062 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8063 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8064 uint32_t pf
, pipesrc
;
8067 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8071 ret
= intel_ring_begin(ring
, 4);
8075 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8076 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8077 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
8078 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8080 /* Contrary to the suggestions in the documentation,
8081 * "Enable Panel Fitter" does not seem to be required when page
8082 * flipping with a non-native mode, and worse causes a normal
8084 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8087 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
8088 intel_ring_emit(ring
, pf
| pipesrc
);
8090 intel_mark_page_flip_active(intel_crtc
);
8091 __intel_ring_advance(ring
);
8095 intel_unpin_fb_obj(obj
);
8100 static int intel_gen7_queue_flip(struct drm_device
*dev
,
8101 struct drm_crtc
*crtc
,
8102 struct drm_framebuffer
*fb
,
8103 struct drm_i915_gem_object
*obj
,
8106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8107 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8108 struct intel_ring_buffer
*ring
;
8109 uint32_t plane_bit
= 0;
8113 if (IS_VALLEYVIEW(dev
) || ring
== NULL
|| ring
->id
!= RCS
)
8114 ring
= &dev_priv
->ring
[BCS
];
8116 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8120 switch(intel_crtc
->plane
) {
8122 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
8125 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
8128 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
8131 WARN_ONCE(1, "unknown plane in flip command\n");
8137 if (ring
->id
== RCS
)
8140 ret
= intel_ring_begin(ring
, len
);
8144 /* Unmask the flip-done completion message. Note that the bspec says that
8145 * we should do this for both the BCS and RCS, and that we must not unmask
8146 * more than one flip event at any time (or ensure that one flip message
8147 * can be sent by waiting for flip-done prior to queueing new flips).
8148 * Experimentation says that BCS works despite DERRMR masking all
8149 * flip-done completion events and that unmasking all planes at once
8150 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8151 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8153 if (ring
->id
== RCS
) {
8154 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
8155 intel_ring_emit(ring
, DERRMR
);
8156 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
8157 DERRMR_PIPEB_PRI_FLIP_DONE
|
8158 DERRMR_PIPEC_PRI_FLIP_DONE
));
8159 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1));
8160 intel_ring_emit(ring
, DERRMR
);
8161 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
8164 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
8165 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
8166 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8167 intel_ring_emit(ring
, (MI_NOOP
));
8169 intel_mark_page_flip_active(intel_crtc
);
8170 __intel_ring_advance(ring
);
8174 intel_unpin_fb_obj(obj
);
8179 static int intel_default_queue_flip(struct drm_device
*dev
,
8180 struct drm_crtc
*crtc
,
8181 struct drm_framebuffer
*fb
,
8182 struct drm_i915_gem_object
*obj
,
8188 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
8189 struct drm_framebuffer
*fb
,
8190 struct drm_pending_vblank_event
*event
,
8191 uint32_t page_flip_flags
)
8193 struct drm_device
*dev
= crtc
->dev
;
8194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8195 struct drm_framebuffer
*old_fb
= crtc
->fb
;
8196 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
8197 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8198 struct intel_unpin_work
*work
;
8199 unsigned long flags
;
8202 /* Can't change pixel format via MI display flips. */
8203 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
8207 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8208 * Note that pitch changes could also affect these register.
8210 if (INTEL_INFO(dev
)->gen
> 3 &&
8211 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
8212 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
8215 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
8219 work
->event
= event
;
8221 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
8222 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
8224 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
8228 /* We borrow the event spin lock for protecting unpin_work */
8229 spin_lock_irqsave(&dev
->event_lock
, flags
);
8230 if (intel_crtc
->unpin_work
) {
8231 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8233 drm_vblank_put(dev
, intel_crtc
->pipe
);
8235 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8238 intel_crtc
->unpin_work
= work
;
8239 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8241 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
8242 flush_workqueue(dev_priv
->wq
);
8244 ret
= i915_mutex_lock_interruptible(dev
);
8248 /* Reference the objects for the scheduled work. */
8249 drm_gem_object_reference(&work
->old_fb_obj
->base
);
8250 drm_gem_object_reference(&obj
->base
);
8254 work
->pending_flip_obj
= obj
;
8256 work
->enable_stall_check
= true;
8258 atomic_inc(&intel_crtc
->unpin_work_count
);
8259 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
8261 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, page_flip_flags
);
8263 goto cleanup_pending
;
8265 intel_disable_fbc(dev
);
8266 intel_mark_fb_busy(obj
, NULL
);
8267 mutex_unlock(&dev
->struct_mutex
);
8269 trace_i915_flip_request(intel_crtc
->plane
, obj
);
8274 atomic_dec(&intel_crtc
->unpin_work_count
);
8276 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8277 drm_gem_object_unreference(&obj
->base
);
8278 mutex_unlock(&dev
->struct_mutex
);
8281 spin_lock_irqsave(&dev
->event_lock
, flags
);
8282 intel_crtc
->unpin_work
= NULL
;
8283 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8285 drm_vblank_put(dev
, intel_crtc
->pipe
);
8292 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
8293 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
8294 .load_lut
= intel_crtc_load_lut
,
8297 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
8298 struct drm_crtc
*crtc
)
8300 struct drm_device
*dev
;
8301 struct drm_crtc
*tmp
;
8304 WARN(!crtc
, "checking null crtc?\n");
8308 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
8314 if (encoder
->possible_crtcs
& crtc_mask
)
8320 * intel_modeset_update_staged_output_state
8322 * Updates the staged output configuration state, e.g. after we've read out the
8325 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
8327 struct intel_encoder
*encoder
;
8328 struct intel_connector
*connector
;
8330 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8332 connector
->new_encoder
=
8333 to_intel_encoder(connector
->base
.encoder
);
8336 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8339 to_intel_crtc(encoder
->base
.crtc
);
8344 * intel_modeset_commit_output_state
8346 * This function copies the stage display pipe configuration to the real one.
8348 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
8350 struct intel_encoder
*encoder
;
8351 struct intel_connector
*connector
;
8353 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8355 connector
->base
.encoder
= &connector
->new_encoder
->base
;
8358 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8360 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
8365 connected_sink_compute_bpp(struct intel_connector
* connector
,
8366 struct intel_crtc_config
*pipe_config
)
8368 int bpp
= pipe_config
->pipe_bpp
;
8370 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8371 connector
->base
.base
.id
,
8372 drm_get_connector_name(&connector
->base
));
8374 /* Don't use an invalid EDID bpc value */
8375 if (connector
->base
.display_info
.bpc
&&
8376 connector
->base
.display_info
.bpc
* 3 < bpp
) {
8377 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8378 bpp
, connector
->base
.display_info
.bpc
*3);
8379 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
8382 /* Clamp bpp to 8 on screens without EDID 1.4 */
8383 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
8384 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8386 pipe_config
->pipe_bpp
= 24;
8391 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
8392 struct drm_framebuffer
*fb
,
8393 struct intel_crtc_config
*pipe_config
)
8395 struct drm_device
*dev
= crtc
->base
.dev
;
8396 struct intel_connector
*connector
;
8399 switch (fb
->pixel_format
) {
8401 bpp
= 8*3; /* since we go through a colormap */
8403 case DRM_FORMAT_XRGB1555
:
8404 case DRM_FORMAT_ARGB1555
:
8405 /* checked in intel_framebuffer_init already */
8406 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
8408 case DRM_FORMAT_RGB565
:
8409 bpp
= 6*3; /* min is 18bpp */
8411 case DRM_FORMAT_XBGR8888
:
8412 case DRM_FORMAT_ABGR8888
:
8413 /* checked in intel_framebuffer_init already */
8414 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8416 case DRM_FORMAT_XRGB8888
:
8417 case DRM_FORMAT_ARGB8888
:
8420 case DRM_FORMAT_XRGB2101010
:
8421 case DRM_FORMAT_ARGB2101010
:
8422 case DRM_FORMAT_XBGR2101010
:
8423 case DRM_FORMAT_ABGR2101010
:
8424 /* checked in intel_framebuffer_init already */
8425 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8429 /* TODO: gen4+ supports 16 bpc floating point, too. */
8431 DRM_DEBUG_KMS("unsupported depth\n");
8435 pipe_config
->pipe_bpp
= bpp
;
8437 /* Clamp display bpp to EDID value */
8438 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8440 if (!connector
->new_encoder
||
8441 connector
->new_encoder
->new_crtc
!= crtc
)
8444 connected_sink_compute_bpp(connector
, pipe_config
);
8450 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
8452 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8453 "type: 0x%x flags: 0x%x\n",
8455 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
8456 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
8457 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
8458 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
8461 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
8462 struct intel_crtc_config
*pipe_config
,
8463 const char *context
)
8465 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
8466 context
, pipe_name(crtc
->pipe
));
8468 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
8469 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8470 pipe_config
->pipe_bpp
, pipe_config
->dither
);
8471 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8472 pipe_config
->has_pch_encoder
,
8473 pipe_config
->fdi_lanes
,
8474 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
8475 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
8476 pipe_config
->fdi_m_n
.tu
);
8477 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8478 pipe_config
->has_dp_encoder
,
8479 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
8480 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
8481 pipe_config
->dp_m_n
.tu
);
8482 DRM_DEBUG_KMS("requested mode:\n");
8483 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
8484 DRM_DEBUG_KMS("adjusted mode:\n");
8485 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
8486 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
8487 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
8488 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8489 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
8490 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8491 pipe_config
->gmch_pfit
.control
,
8492 pipe_config
->gmch_pfit
.pgm_ratios
,
8493 pipe_config
->gmch_pfit
.lvds_border_bits
);
8494 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8495 pipe_config
->pch_pfit
.pos
,
8496 pipe_config
->pch_pfit
.size
,
8497 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
8498 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
8499 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
8502 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
8504 int num_encoders
= 0;
8505 bool uncloneable_encoders
= false;
8506 struct intel_encoder
*encoder
;
8508 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
8510 if (&encoder
->new_crtc
->base
!= crtc
)
8514 if (!encoder
->cloneable
)
8515 uncloneable_encoders
= true;
8518 return !(num_encoders
> 1 && uncloneable_encoders
);
8521 static struct intel_crtc_config
*
8522 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
8523 struct drm_framebuffer
*fb
,
8524 struct drm_display_mode
*mode
)
8526 struct drm_device
*dev
= crtc
->dev
;
8527 struct intel_encoder
*encoder
;
8528 struct intel_crtc_config
*pipe_config
;
8529 int plane_bpp
, ret
= -EINVAL
;
8532 if (!check_encoder_cloning(crtc
)) {
8533 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8534 return ERR_PTR(-EINVAL
);
8537 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8539 return ERR_PTR(-ENOMEM
);
8541 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
8542 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
8544 pipe_config
->cpu_transcoder
=
8545 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
8546 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8549 * Sanitize sync polarity flags based on requested ones. If neither
8550 * positive or negative polarity is requested, treat this as meaning
8551 * negative polarity.
8553 if (!(pipe_config
->adjusted_mode
.flags
&
8554 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
8555 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
8557 if (!(pipe_config
->adjusted_mode
.flags
&
8558 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
8559 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
8561 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8562 * plane pixel format and any sink constraints into account. Returns the
8563 * source plane bpp so that dithering can be selected on mismatches
8564 * after encoders and crtc also have had their say. */
8565 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
8571 * Determine the real pipe dimensions. Note that stereo modes can
8572 * increase the actual pipe size due to the frame doubling and
8573 * insertion of additional space for blanks between the frame. This
8574 * is stored in the crtc timings. We use the requested mode to do this
8575 * computation to clearly distinguish it from the adjusted mode, which
8576 * can be changed by the connectors in the below retry loop.
8578 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
8579 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
8580 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
8583 /* Ensure the port clock defaults are reset when retrying. */
8584 pipe_config
->port_clock
= 0;
8585 pipe_config
->pixel_multiplier
= 1;
8587 /* Fill in default crtc timings, allow encoders to overwrite them. */
8588 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
8590 /* Pass our mode to the connectors and the CRTC to give them a chance to
8591 * adjust it according to limitations or connector properties, and also
8592 * a chance to reject the mode entirely.
8594 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8597 if (&encoder
->new_crtc
->base
!= crtc
)
8600 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
8601 DRM_DEBUG_KMS("Encoder config failure\n");
8606 /* Set default port clock if not overwritten by the encoder. Needs to be
8607 * done afterwards in case the encoder adjusts the mode. */
8608 if (!pipe_config
->port_clock
)
8609 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
8610 * pipe_config
->pixel_multiplier
;
8612 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
8614 DRM_DEBUG_KMS("CRTC fixup failed\n");
8619 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
8624 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8629 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
8630 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8631 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
8636 return ERR_PTR(ret
);
8639 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8640 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8642 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
8643 unsigned *prepare_pipes
, unsigned *disable_pipes
)
8645 struct intel_crtc
*intel_crtc
;
8646 struct drm_device
*dev
= crtc
->dev
;
8647 struct intel_encoder
*encoder
;
8648 struct intel_connector
*connector
;
8649 struct drm_crtc
*tmp_crtc
;
8651 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
8653 /* Check which crtcs have changed outputs connected to them, these need
8654 * to be part of the prepare_pipes mask. We don't (yet) support global
8655 * modeset across multiple crtcs, so modeset_pipes will only have one
8656 * bit set at most. */
8657 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8659 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
8662 if (connector
->base
.encoder
) {
8663 tmp_crtc
= connector
->base
.encoder
->crtc
;
8665 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8668 if (connector
->new_encoder
)
8670 1 << connector
->new_encoder
->new_crtc
->pipe
;
8673 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8675 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
8678 if (encoder
->base
.crtc
) {
8679 tmp_crtc
= encoder
->base
.crtc
;
8681 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8684 if (encoder
->new_crtc
)
8685 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
8688 /* Check for any pipes that will be fully disabled ... */
8689 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8693 /* Don't try to disable disabled crtcs. */
8694 if (!intel_crtc
->base
.enabled
)
8697 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8699 if (encoder
->new_crtc
== intel_crtc
)
8704 *disable_pipes
|= 1 << intel_crtc
->pipe
;
8708 /* set_mode is also used to update properties on life display pipes. */
8709 intel_crtc
= to_intel_crtc(crtc
);
8711 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
8714 * For simplicity do a full modeset on any pipe where the output routing
8715 * changed. We could be more clever, but that would require us to be
8716 * more careful with calling the relevant encoder->mode_set functions.
8719 *modeset_pipes
= *prepare_pipes
;
8721 /* ... and mask these out. */
8722 *modeset_pipes
&= ~(*disable_pipes
);
8723 *prepare_pipes
&= ~(*disable_pipes
);
8726 * HACK: We don't (yet) fully support global modesets. intel_set_config
8727 * obies this rule, but the modeset restore mode of
8728 * intel_modeset_setup_hw_state does not.
8730 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
8731 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
8733 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8734 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
8737 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
8739 struct drm_encoder
*encoder
;
8740 struct drm_device
*dev
= crtc
->dev
;
8742 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
8743 if (encoder
->crtc
== crtc
)
8750 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
8752 struct intel_encoder
*intel_encoder
;
8753 struct intel_crtc
*intel_crtc
;
8754 struct drm_connector
*connector
;
8756 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
8758 if (!intel_encoder
->base
.crtc
)
8761 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
8763 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
8764 intel_encoder
->connectors_active
= false;
8767 intel_modeset_commit_output_state(dev
);
8769 /* Update computed state. */
8770 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8772 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
8775 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8776 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
8779 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
8781 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
8782 struct drm_property
*dpms_property
=
8783 dev
->mode_config
.dpms_property
;
8785 connector
->dpms
= DRM_MODE_DPMS_ON
;
8786 drm_object_property_set_value(&connector
->base
,
8790 intel_encoder
= to_intel_encoder(connector
->encoder
);
8791 intel_encoder
->connectors_active
= true;
8797 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
8801 if (clock1
== clock2
)
8804 if (!clock1
|| !clock2
)
8807 diff
= abs(clock1
- clock2
);
8809 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
8815 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8816 list_for_each_entry((intel_crtc), \
8817 &(dev)->mode_config.crtc_list, \
8819 if (mask & (1 <<(intel_crtc)->pipe))
8822 intel_pipe_config_compare(struct drm_device
*dev
,
8823 struct intel_crtc_config
*current_config
,
8824 struct intel_crtc_config
*pipe_config
)
8826 #define PIPE_CONF_CHECK_X(name) \
8827 if (current_config->name != pipe_config->name) { \
8828 DRM_ERROR("mismatch in " #name " " \
8829 "(expected 0x%08x, found 0x%08x)\n", \
8830 current_config->name, \
8831 pipe_config->name); \
8835 #define PIPE_CONF_CHECK_I(name) \
8836 if (current_config->name != pipe_config->name) { \
8837 DRM_ERROR("mismatch in " #name " " \
8838 "(expected %i, found %i)\n", \
8839 current_config->name, \
8840 pipe_config->name); \
8844 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8845 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8846 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8847 "(expected %i, found %i)\n", \
8848 current_config->name & (mask), \
8849 pipe_config->name & (mask)); \
8853 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8854 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8855 DRM_ERROR("mismatch in " #name " " \
8856 "(expected %i, found %i)\n", \
8857 current_config->name, \
8858 pipe_config->name); \
8862 #define PIPE_CONF_QUIRK(quirk) \
8863 ((current_config->quirks | pipe_config->quirks) & (quirk))
8865 PIPE_CONF_CHECK_I(cpu_transcoder
);
8867 PIPE_CONF_CHECK_I(has_pch_encoder
);
8868 PIPE_CONF_CHECK_I(fdi_lanes
);
8869 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
8870 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
8871 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
8872 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
8873 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
8875 PIPE_CONF_CHECK_I(has_dp_encoder
);
8876 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
8877 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
8878 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
8879 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
8880 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
8882 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
8883 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
8884 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
8885 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
8886 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
8887 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
8889 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
8890 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
8891 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
8892 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
8893 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
8894 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
8896 PIPE_CONF_CHECK_I(pixel_multiplier
);
8898 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8899 DRM_MODE_FLAG_INTERLACE
);
8901 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
8902 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8903 DRM_MODE_FLAG_PHSYNC
);
8904 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8905 DRM_MODE_FLAG_NHSYNC
);
8906 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8907 DRM_MODE_FLAG_PVSYNC
);
8908 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8909 DRM_MODE_FLAG_NVSYNC
);
8912 PIPE_CONF_CHECK_I(pipe_src_w
);
8913 PIPE_CONF_CHECK_I(pipe_src_h
);
8915 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
8916 /* pfit ratios are autocomputed by the hw on gen4+ */
8917 if (INTEL_INFO(dev
)->gen
< 4)
8918 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
8919 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
8920 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
8921 if (current_config
->pch_pfit
.enabled
) {
8922 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
8923 PIPE_CONF_CHECK_I(pch_pfit
.size
);
8926 PIPE_CONF_CHECK_I(ips_enabled
);
8928 PIPE_CONF_CHECK_I(double_wide
);
8930 PIPE_CONF_CHECK_I(shared_dpll
);
8931 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
8932 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
8933 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
8934 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
8936 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
8937 PIPE_CONF_CHECK_I(pipe_bpp
);
8939 if (!IS_HASWELL(dev
)) {
8940 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
8941 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
8944 #undef PIPE_CONF_CHECK_X
8945 #undef PIPE_CONF_CHECK_I
8946 #undef PIPE_CONF_CHECK_FLAGS
8947 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8948 #undef PIPE_CONF_QUIRK
8954 check_connector_state(struct drm_device
*dev
)
8956 struct intel_connector
*connector
;
8958 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8960 /* This also checks the encoder/connector hw state with the
8961 * ->get_hw_state callbacks. */
8962 intel_connector_check_state(connector
);
8964 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
8965 "connector's staged encoder doesn't match current encoder\n");
8970 check_encoder_state(struct drm_device
*dev
)
8972 struct intel_encoder
*encoder
;
8973 struct intel_connector
*connector
;
8975 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8977 bool enabled
= false;
8978 bool active
= false;
8979 enum pipe pipe
, tracked_pipe
;
8981 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8982 encoder
->base
.base
.id
,
8983 drm_get_encoder_name(&encoder
->base
));
8985 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
8986 "encoder's stage crtc doesn't match current crtc\n");
8987 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
8988 "encoder's active_connectors set, but no crtc\n");
8990 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8992 if (connector
->base
.encoder
!= &encoder
->base
)
8995 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
8998 WARN(!!encoder
->base
.crtc
!= enabled
,
8999 "encoder's enabled state mismatch "
9000 "(expected %i, found %i)\n",
9001 !!encoder
->base
.crtc
, enabled
);
9002 WARN(active
&& !encoder
->base
.crtc
,
9003 "active encoder with no crtc\n");
9005 WARN(encoder
->connectors_active
!= active
,
9006 "encoder's computed active state doesn't match tracked active state "
9007 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
9009 active
= encoder
->get_hw_state(encoder
, &pipe
);
9010 WARN(active
!= encoder
->connectors_active
,
9011 "encoder's hw state doesn't match sw tracking "
9012 "(expected %i, found %i)\n",
9013 encoder
->connectors_active
, active
);
9015 if (!encoder
->base
.crtc
)
9018 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
9019 WARN(active
&& pipe
!= tracked_pipe
,
9020 "active encoder's pipe doesn't match"
9021 "(expected %i, found %i)\n",
9022 tracked_pipe
, pipe
);
9028 check_crtc_state(struct drm_device
*dev
)
9030 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9031 struct intel_crtc
*crtc
;
9032 struct intel_encoder
*encoder
;
9033 struct intel_crtc_config pipe_config
;
9035 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9037 bool enabled
= false;
9038 bool active
= false;
9040 memset(&pipe_config
, 0, sizeof(pipe_config
));
9042 DRM_DEBUG_KMS("[CRTC:%d]\n",
9043 crtc
->base
.base
.id
);
9045 WARN(crtc
->active
&& !crtc
->base
.enabled
,
9046 "active crtc, but not enabled in sw tracking\n");
9048 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9050 if (encoder
->base
.crtc
!= &crtc
->base
)
9053 if (encoder
->connectors_active
)
9057 WARN(active
!= crtc
->active
,
9058 "crtc's computed active state doesn't match tracked active state "
9059 "(expected %i, found %i)\n", active
, crtc
->active
);
9060 WARN(enabled
!= crtc
->base
.enabled
,
9061 "crtc's computed enabled state doesn't match tracked enabled state "
9062 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
9064 active
= dev_priv
->display
.get_pipe_config(crtc
,
9067 /* hw state is inconsistent with the pipe A quirk */
9068 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
9069 active
= crtc
->active
;
9071 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9074 if (encoder
->base
.crtc
!= &crtc
->base
)
9076 if (encoder
->get_config
&&
9077 encoder
->get_hw_state(encoder
, &pipe
))
9078 encoder
->get_config(encoder
, &pipe_config
);
9081 WARN(crtc
->active
!= active
,
9082 "crtc active state doesn't match with hw state "
9083 "(expected %i, found %i)\n", crtc
->active
, active
);
9086 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
9087 WARN(1, "pipe state doesn't match!\n");
9088 intel_dump_pipe_config(crtc
, &pipe_config
,
9090 intel_dump_pipe_config(crtc
, &crtc
->config
,
9097 check_shared_dpll_state(struct drm_device
*dev
)
9099 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9100 struct intel_crtc
*crtc
;
9101 struct intel_dpll_hw_state dpll_hw_state
;
9104 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9105 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
9106 int enabled_crtcs
= 0, active_crtcs
= 0;
9109 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
9111 DRM_DEBUG_KMS("%s\n", pll
->name
);
9113 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
9115 WARN(pll
->active
> pll
->refcount
,
9116 "more active pll users than references: %i vs %i\n",
9117 pll
->active
, pll
->refcount
);
9118 WARN(pll
->active
&& !pll
->on
,
9119 "pll in active use but not on in sw tracking\n");
9120 WARN(pll
->on
&& !pll
->active
,
9121 "pll in on but not on in use in sw tracking\n");
9122 WARN(pll
->on
!= active
,
9123 "pll on state mismatch (expected %i, found %i)\n",
9126 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9128 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9130 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9133 WARN(pll
->active
!= active_crtcs
,
9134 "pll active crtcs mismatch (expected %i, found %i)\n",
9135 pll
->active
, active_crtcs
);
9136 WARN(pll
->refcount
!= enabled_crtcs
,
9137 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9138 pll
->refcount
, enabled_crtcs
);
9140 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
9141 sizeof(dpll_hw_state
)),
9142 "pll hw state mismatch\n");
9147 intel_modeset_check_state(struct drm_device
*dev
)
9149 check_connector_state(dev
);
9150 check_encoder_state(dev
);
9151 check_crtc_state(dev
);
9152 check_shared_dpll_state(dev
);
9155 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
9159 * FDI already provided one idea for the dotclock.
9160 * Yell if the encoder disagrees.
9162 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
9163 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9164 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
9167 static int __intel_set_mode(struct drm_crtc
*crtc
,
9168 struct drm_display_mode
*mode
,
9169 int x
, int y
, struct drm_framebuffer
*fb
)
9171 struct drm_device
*dev
= crtc
->dev
;
9172 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9173 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
9174 struct intel_crtc_config
*pipe_config
= NULL
;
9175 struct intel_crtc
*intel_crtc
;
9176 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
9179 saved_mode
= kcalloc(2, sizeof(*saved_mode
), GFP_KERNEL
);
9182 saved_hwmode
= saved_mode
+ 1;
9184 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
9185 &prepare_pipes
, &disable_pipes
);
9187 *saved_hwmode
= crtc
->hwmode
;
9188 *saved_mode
= crtc
->mode
;
9190 /* Hack: Because we don't (yet) support global modeset on multiple
9191 * crtcs, we don't keep track of the new mode for more than one crtc.
9192 * Hence simply check whether any bit is set in modeset_pipes in all the
9193 * pieces of code that are not yet converted to deal with mutliple crtcs
9194 * changing their mode at the same time. */
9195 if (modeset_pipes
) {
9196 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
9197 if (IS_ERR(pipe_config
)) {
9198 ret
= PTR_ERR(pipe_config
);
9203 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
9207 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
9208 intel_crtc_disable(&intel_crtc
->base
);
9210 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
9211 if (intel_crtc
->base
.enabled
)
9212 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
9215 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9216 * to set it here already despite that we pass it down the callchain.
9218 if (modeset_pipes
) {
9220 /* mode_set/enable/disable functions rely on a correct pipe
9222 to_intel_crtc(crtc
)->config
= *pipe_config
;
9225 /* Only after disabling all output pipelines that will be changed can we
9226 * update the the output configuration. */
9227 intel_modeset_update_state(dev
, prepare_pipes
);
9229 if (dev_priv
->display
.modeset_global_resources
)
9230 dev_priv
->display
.modeset_global_resources(dev
);
9232 /* Set up the DPLL and any encoders state that needs to adjust or depend
9235 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
9236 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
9242 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9243 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
9244 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
9246 if (modeset_pipes
) {
9247 /* Store real post-adjustment hardware mode. */
9248 crtc
->hwmode
= pipe_config
->adjusted_mode
;
9250 /* Calculate and store various constants which
9251 * are later needed by vblank and swap-completion
9252 * timestamping. They are derived from true hwmode.
9254 drm_calc_timestamping_constants(crtc
);
9257 /* FIXME: add subpixel order */
9259 if (ret
&& crtc
->enabled
) {
9260 crtc
->hwmode
= *saved_hwmode
;
9261 crtc
->mode
= *saved_mode
;
9270 static int intel_set_mode(struct drm_crtc
*crtc
,
9271 struct drm_display_mode
*mode
,
9272 int x
, int y
, struct drm_framebuffer
*fb
)
9276 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
9279 intel_modeset_check_state(crtc
->dev
);
9284 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
9286 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
9289 #undef for_each_intel_crtc_masked
9291 static void intel_set_config_free(struct intel_set_config
*config
)
9296 kfree(config
->save_connector_encoders
);
9297 kfree(config
->save_encoder_crtcs
);
9301 static int intel_set_config_save_state(struct drm_device
*dev
,
9302 struct intel_set_config
*config
)
9304 struct drm_encoder
*encoder
;
9305 struct drm_connector
*connector
;
9308 config
->save_encoder_crtcs
=
9309 kcalloc(dev
->mode_config
.num_encoder
,
9310 sizeof(struct drm_crtc
*), GFP_KERNEL
);
9311 if (!config
->save_encoder_crtcs
)
9314 config
->save_connector_encoders
=
9315 kcalloc(dev
->mode_config
.num_connector
,
9316 sizeof(struct drm_encoder
*), GFP_KERNEL
);
9317 if (!config
->save_connector_encoders
)
9320 /* Copy data. Note that driver private data is not affected.
9321 * Should anything bad happen only the expected state is
9322 * restored, not the drivers personal bookkeeping.
9325 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
9326 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
9330 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9331 config
->save_connector_encoders
[count
++] = connector
->encoder
;
9337 static void intel_set_config_restore_state(struct drm_device
*dev
,
9338 struct intel_set_config
*config
)
9340 struct intel_encoder
*encoder
;
9341 struct intel_connector
*connector
;
9345 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9347 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
9351 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
9352 connector
->new_encoder
=
9353 to_intel_encoder(config
->save_connector_encoders
[count
++]);
9358 is_crtc_connector_off(struct drm_mode_set
*set
)
9362 if (set
->num_connectors
== 0)
9365 if (WARN_ON(set
->connectors
== NULL
))
9368 for (i
= 0; i
< set
->num_connectors
; i
++)
9369 if (set
->connectors
[i
]->encoder
&&
9370 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
9371 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
9378 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
9379 struct intel_set_config
*config
)
9382 /* We should be able to check here if the fb has the same properties
9383 * and then just flip_or_move it */
9384 if (is_crtc_connector_off(set
)) {
9385 config
->mode_changed
= true;
9386 } else if (set
->crtc
->fb
!= set
->fb
) {
9387 /* If we have no fb then treat it as a full mode set */
9388 if (set
->crtc
->fb
== NULL
) {
9389 struct intel_crtc
*intel_crtc
=
9390 to_intel_crtc(set
->crtc
);
9392 if (intel_crtc
->active
&& i915_fastboot
) {
9393 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9394 config
->fb_changed
= true;
9396 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9397 config
->mode_changed
= true;
9399 } else if (set
->fb
== NULL
) {
9400 config
->mode_changed
= true;
9401 } else if (set
->fb
->pixel_format
!=
9402 set
->crtc
->fb
->pixel_format
) {
9403 config
->mode_changed
= true;
9405 config
->fb_changed
= true;
9409 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
9410 config
->fb_changed
= true;
9412 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
9413 DRM_DEBUG_KMS("modes are different, full mode set\n");
9414 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
9415 drm_mode_debug_printmodeline(set
->mode
);
9416 config
->mode_changed
= true;
9419 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9420 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
9424 intel_modeset_stage_output_state(struct drm_device
*dev
,
9425 struct drm_mode_set
*set
,
9426 struct intel_set_config
*config
)
9428 struct drm_crtc
*new_crtc
;
9429 struct intel_connector
*connector
;
9430 struct intel_encoder
*encoder
;
9433 /* The upper layers ensure that we either disable a crtc or have a list
9434 * of connectors. For paranoia, double-check this. */
9435 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
9436 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
9438 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9440 /* Otherwise traverse passed in connector list and get encoders
9442 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9443 if (set
->connectors
[ro
] == &connector
->base
) {
9444 connector
->new_encoder
= connector
->encoder
;
9449 /* If we disable the crtc, disable all its connectors. Also, if
9450 * the connector is on the changing crtc but not on the new
9451 * connector list, disable it. */
9452 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
9453 connector
->base
.encoder
&&
9454 connector
->base
.encoder
->crtc
== set
->crtc
) {
9455 connector
->new_encoder
= NULL
;
9457 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9458 connector
->base
.base
.id
,
9459 drm_get_connector_name(&connector
->base
));
9463 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
9464 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9465 config
->mode_changed
= true;
9468 /* connector->new_encoder is now updated for all connectors. */
9470 /* Update crtc of enabled connectors. */
9471 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9473 if (!connector
->new_encoder
)
9476 new_crtc
= connector
->new_encoder
->base
.crtc
;
9478 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9479 if (set
->connectors
[ro
] == &connector
->base
)
9480 new_crtc
= set
->crtc
;
9483 /* Make sure the new CRTC will work with the encoder */
9484 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
9488 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
9490 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9491 connector
->base
.base
.id
,
9492 drm_get_connector_name(&connector
->base
),
9496 /* Check for any encoders that needs to be disabled. */
9497 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9499 list_for_each_entry(connector
,
9500 &dev
->mode_config
.connector_list
,
9502 if (connector
->new_encoder
== encoder
) {
9503 WARN_ON(!connector
->new_encoder
->new_crtc
);
9508 encoder
->new_crtc
= NULL
;
9510 /* Only now check for crtc changes so we don't miss encoders
9511 * that will be disabled. */
9512 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
9513 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9514 config
->mode_changed
= true;
9517 /* Now we've also updated encoder->new_crtc for all encoders. */
9522 static int intel_crtc_set_config(struct drm_mode_set
*set
)
9524 struct drm_device
*dev
;
9525 struct drm_mode_set save_set
;
9526 struct intel_set_config
*config
;
9531 BUG_ON(!set
->crtc
->helper_private
);
9533 /* Enforce sane interface api - has been abused by the fb helper. */
9534 BUG_ON(!set
->mode
&& set
->fb
);
9535 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
9538 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9539 set
->crtc
->base
.id
, set
->fb
->base
.id
,
9540 (int)set
->num_connectors
, set
->x
, set
->y
);
9542 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
9545 dev
= set
->crtc
->dev
;
9548 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
9552 ret
= intel_set_config_save_state(dev
, config
);
9556 save_set
.crtc
= set
->crtc
;
9557 save_set
.mode
= &set
->crtc
->mode
;
9558 save_set
.x
= set
->crtc
->x
;
9559 save_set
.y
= set
->crtc
->y
;
9560 save_set
.fb
= set
->crtc
->fb
;
9562 /* Compute whether we need a full modeset, only an fb base update or no
9563 * change at all. In the future we might also check whether only the
9564 * mode changed, e.g. for LVDS where we only change the panel fitter in
9566 intel_set_config_compute_mode_changes(set
, config
);
9568 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
9572 if (config
->mode_changed
) {
9573 ret
= intel_set_mode(set
->crtc
, set
->mode
,
9574 set
->x
, set
->y
, set
->fb
);
9575 } else if (config
->fb_changed
) {
9576 intel_crtc_wait_for_pending_flips(set
->crtc
);
9578 ret
= intel_pipe_set_base(set
->crtc
,
9579 set
->x
, set
->y
, set
->fb
);
9583 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9584 set
->crtc
->base
.id
, ret
);
9586 intel_set_config_restore_state(dev
, config
);
9588 /* Try to restore the config */
9589 if (config
->mode_changed
&&
9590 intel_set_mode(save_set
.crtc
, save_set
.mode
,
9591 save_set
.x
, save_set
.y
, save_set
.fb
))
9592 DRM_ERROR("failed to restore config after modeset failure\n");
9596 intel_set_config_free(config
);
9600 static const struct drm_crtc_funcs intel_crtc_funcs
= {
9601 .cursor_set
= intel_crtc_cursor_set
,
9602 .cursor_move
= intel_crtc_cursor_move
,
9603 .gamma_set
= intel_crtc_gamma_set
,
9604 .set_config
= intel_crtc_set_config
,
9605 .destroy
= intel_crtc_destroy
,
9606 .page_flip
= intel_crtc_page_flip
,
9609 static void intel_cpu_pll_init(struct drm_device
*dev
)
9612 intel_ddi_pll_init(dev
);
9615 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
9616 struct intel_shared_dpll
*pll
,
9617 struct intel_dpll_hw_state
*hw_state
)
9621 val
= I915_READ(PCH_DPLL(pll
->id
));
9622 hw_state
->dpll
= val
;
9623 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
9624 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
9626 return val
& DPLL_VCO_ENABLE
;
9629 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
9630 struct intel_shared_dpll
*pll
)
9632 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
9633 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
9636 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
9637 struct intel_shared_dpll
*pll
)
9639 /* PCH refclock must be enabled first */
9640 assert_pch_refclk_enabled(dev_priv
);
9642 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9644 /* Wait for the clocks to stabilize. */
9645 POSTING_READ(PCH_DPLL(pll
->id
));
9648 /* The pixel multiplier can only be updated once the
9649 * DPLL is enabled and the clocks are stable.
9651 * So write it again.
9653 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9654 POSTING_READ(PCH_DPLL(pll
->id
));
9658 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
9659 struct intel_shared_dpll
*pll
)
9661 struct drm_device
*dev
= dev_priv
->dev
;
9662 struct intel_crtc
*crtc
;
9664 /* Make sure no transcoder isn't still depending on us. */
9665 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
9666 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
9667 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
9670 I915_WRITE(PCH_DPLL(pll
->id
), 0);
9671 POSTING_READ(PCH_DPLL(pll
->id
));
9675 static char *ibx_pch_dpll_names
[] = {
9680 static void ibx_pch_dpll_init(struct drm_device
*dev
)
9682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9685 dev_priv
->num_shared_dpll
= 2;
9687 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9688 dev_priv
->shared_dplls
[i
].id
= i
;
9689 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
9690 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
9691 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
9692 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
9693 dev_priv
->shared_dplls
[i
].get_hw_state
=
9694 ibx_pch_dpll_get_hw_state
;
9698 static void intel_shared_dpll_init(struct drm_device
*dev
)
9700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9702 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
9703 ibx_pch_dpll_init(dev
);
9705 dev_priv
->num_shared_dpll
= 0;
9707 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
9708 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9709 dev_priv
->num_shared_dpll
);
9712 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
9714 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9715 struct intel_crtc
*intel_crtc
;
9718 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
9719 if (intel_crtc
== NULL
)
9722 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
9724 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
9725 for (i
= 0; i
< 256; i
++) {
9726 intel_crtc
->lut_r
[i
] = i
;
9727 intel_crtc
->lut_g
[i
] = i
;
9728 intel_crtc
->lut_b
[i
] = i
;
9731 /* Swap pipes & planes for FBC on pre-965 */
9732 intel_crtc
->pipe
= pipe
;
9733 intel_crtc
->plane
= pipe
;
9734 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
9735 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9736 intel_crtc
->plane
= !pipe
;
9739 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
9740 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
9741 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
9742 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
9744 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
9747 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
9748 struct drm_file
*file
)
9750 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
9751 struct drm_mode_object
*drmmode_obj
;
9752 struct intel_crtc
*crtc
;
9754 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
9757 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
9758 DRM_MODE_OBJECT_CRTC
);
9761 DRM_ERROR("no such CRTC id\n");
9765 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
9766 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
9771 static int intel_encoder_clones(struct intel_encoder
*encoder
)
9773 struct drm_device
*dev
= encoder
->base
.dev
;
9774 struct intel_encoder
*source_encoder
;
9778 list_for_each_entry(source_encoder
,
9779 &dev
->mode_config
.encoder_list
, base
.head
) {
9781 if (encoder
== source_encoder
)
9782 index_mask
|= (1 << entry
);
9784 /* Intel hw has only one MUX where enocoders could be cloned. */
9785 if (encoder
->cloneable
&& source_encoder
->cloneable
)
9786 index_mask
|= (1 << entry
);
9794 static bool has_edp_a(struct drm_device
*dev
)
9796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9798 if (!IS_MOBILE(dev
))
9801 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
9805 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
9811 static void intel_setup_outputs(struct drm_device
*dev
)
9813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9814 struct intel_encoder
*encoder
;
9815 bool dpd_is_edp
= false;
9817 intel_lvds_init(dev
);
9820 intel_crt_init(dev
);
9825 /* Haswell uses DDI functions to detect digital outputs */
9826 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
9827 /* DDI A only supports eDP */
9829 intel_ddi_init(dev
, PORT_A
);
9831 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9833 found
= I915_READ(SFUSE_STRAP
);
9835 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
9836 intel_ddi_init(dev
, PORT_B
);
9837 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
9838 intel_ddi_init(dev
, PORT_C
);
9839 if (found
& SFUSE_STRAP_DDID_DETECTED
)
9840 intel_ddi_init(dev
, PORT_D
);
9841 } else if (HAS_PCH_SPLIT(dev
)) {
9843 dpd_is_edp
= intel_dpd_is_edp(dev
);
9846 intel_dp_init(dev
, DP_A
, PORT_A
);
9848 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
9849 /* PCH SDVOB multiplex with HDMIB */
9850 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
9852 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
9853 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
9854 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
9857 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
9858 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
9860 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
9861 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
9863 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
9864 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
9866 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
9867 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
9868 } else if (IS_VALLEYVIEW(dev
)) {
9869 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9870 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
9871 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
9873 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
9874 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
,
9878 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
9879 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
9881 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
9882 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
9885 intel_dsi_init(dev
);
9886 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
9889 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9890 DRM_DEBUG_KMS("probing SDVOB\n");
9891 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
9892 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
9893 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9894 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
9897 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
9898 intel_dp_init(dev
, DP_B
, PORT_B
);
9901 /* Before G4X SDVOC doesn't have its own detect register */
9903 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9904 DRM_DEBUG_KMS("probing SDVOC\n");
9905 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
9908 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
9910 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
9911 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9912 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
9914 if (SUPPORTS_INTEGRATED_DP(dev
))
9915 intel_dp_init(dev
, DP_C
, PORT_C
);
9918 if (SUPPORTS_INTEGRATED_DP(dev
) &&
9919 (I915_READ(DP_D
) & DP_DETECTED
))
9920 intel_dp_init(dev
, DP_D
, PORT_D
);
9921 } else if (IS_GEN2(dev
))
9922 intel_dvo_init(dev
);
9924 if (SUPPORTS_TV(dev
))
9927 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9928 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
9929 encoder
->base
.possible_clones
=
9930 intel_encoder_clones(encoder
);
9933 intel_init_pch_refclk(dev
);
9935 drm_helper_move_panel_connectors_to_head(dev
);
9938 void intel_framebuffer_fini(struct intel_framebuffer
*fb
)
9940 drm_framebuffer_cleanup(&fb
->base
);
9941 drm_gem_object_unreference_unlocked(&fb
->obj
->base
);
9944 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
9946 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9948 intel_framebuffer_fini(intel_fb
);
9952 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
9953 struct drm_file
*file
,
9954 unsigned int *handle
)
9956 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9957 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9959 return drm_gem_handle_create(file
, &obj
->base
, handle
);
9962 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
9963 .destroy
= intel_user_framebuffer_destroy
,
9964 .create_handle
= intel_user_framebuffer_create_handle
,
9967 int intel_framebuffer_init(struct drm_device
*dev
,
9968 struct intel_framebuffer
*intel_fb
,
9969 struct drm_mode_fb_cmd2
*mode_cmd
,
9970 struct drm_i915_gem_object
*obj
)
9975 if (obj
->tiling_mode
== I915_TILING_Y
) {
9976 DRM_DEBUG("hardware does not support tiling Y\n");
9980 if (mode_cmd
->pitches
[0] & 63) {
9981 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9982 mode_cmd
->pitches
[0]);
9986 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
9987 pitch_limit
= 32*1024;
9988 } else if (INTEL_INFO(dev
)->gen
>= 4) {
9989 if (obj
->tiling_mode
)
9990 pitch_limit
= 16*1024;
9992 pitch_limit
= 32*1024;
9993 } else if (INTEL_INFO(dev
)->gen
>= 3) {
9994 if (obj
->tiling_mode
)
9995 pitch_limit
= 8*1024;
9997 pitch_limit
= 16*1024;
9999 /* XXX DSPC is limited to 4k tiled */
10000 pitch_limit
= 8*1024;
10002 if (mode_cmd
->pitches
[0] > pitch_limit
) {
10003 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10004 obj
->tiling_mode
? "tiled" : "linear",
10005 mode_cmd
->pitches
[0], pitch_limit
);
10009 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
10010 mode_cmd
->pitches
[0] != obj
->stride
) {
10011 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10012 mode_cmd
->pitches
[0], obj
->stride
);
10016 /* Reject formats not supported by any plane early. */
10017 switch (mode_cmd
->pixel_format
) {
10018 case DRM_FORMAT_C8
:
10019 case DRM_FORMAT_RGB565
:
10020 case DRM_FORMAT_XRGB8888
:
10021 case DRM_FORMAT_ARGB8888
:
10023 case DRM_FORMAT_XRGB1555
:
10024 case DRM_FORMAT_ARGB1555
:
10025 if (INTEL_INFO(dev
)->gen
> 3) {
10026 DRM_DEBUG("unsupported pixel format: %s\n",
10027 drm_get_format_name(mode_cmd
->pixel_format
));
10031 case DRM_FORMAT_XBGR8888
:
10032 case DRM_FORMAT_ABGR8888
:
10033 case DRM_FORMAT_XRGB2101010
:
10034 case DRM_FORMAT_ARGB2101010
:
10035 case DRM_FORMAT_XBGR2101010
:
10036 case DRM_FORMAT_ABGR2101010
:
10037 if (INTEL_INFO(dev
)->gen
< 4) {
10038 DRM_DEBUG("unsupported pixel format: %s\n",
10039 drm_get_format_name(mode_cmd
->pixel_format
));
10043 case DRM_FORMAT_YUYV
:
10044 case DRM_FORMAT_UYVY
:
10045 case DRM_FORMAT_YVYU
:
10046 case DRM_FORMAT_VYUY
:
10047 if (INTEL_INFO(dev
)->gen
< 5) {
10048 DRM_DEBUG("unsupported pixel format: %s\n",
10049 drm_get_format_name(mode_cmd
->pixel_format
));
10054 DRM_DEBUG("unsupported pixel format: %s\n",
10055 drm_get_format_name(mode_cmd
->pixel_format
));
10059 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10060 if (mode_cmd
->offsets
[0] != 0)
10063 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
10064 intel_fb
->obj
= obj
;
10066 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
10068 DRM_ERROR("framebuffer init failed %d\n", ret
);
10075 static struct drm_framebuffer
*
10076 intel_user_framebuffer_create(struct drm_device
*dev
,
10077 struct drm_file
*filp
,
10078 struct drm_mode_fb_cmd2
*mode_cmd
)
10080 struct drm_i915_gem_object
*obj
;
10082 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
10083 mode_cmd
->handles
[0]));
10084 if (&obj
->base
== NULL
)
10085 return ERR_PTR(-ENOENT
);
10087 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
10090 static const struct drm_mode_config_funcs intel_mode_funcs
= {
10091 .fb_create
= intel_user_framebuffer_create
,
10092 .output_poll_changed
= intel_fb_output_poll_changed
,
10095 /* Set up chip specific display functions */
10096 static void intel_init_display(struct drm_device
*dev
)
10098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10100 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
10101 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
10102 else if (IS_VALLEYVIEW(dev
))
10103 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
10104 else if (IS_PINEVIEW(dev
))
10105 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
10107 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
10109 if (HAS_DDI(dev
)) {
10110 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
10111 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
10112 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
10113 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
10114 dev_priv
->display
.off
= haswell_crtc_off
;
10115 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10116 } else if (HAS_PCH_SPLIT(dev
)) {
10117 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
10118 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
10119 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
10120 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
10121 dev_priv
->display
.off
= ironlake_crtc_off
;
10122 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10123 } else if (IS_VALLEYVIEW(dev
)) {
10124 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10125 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10126 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
10127 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10128 dev_priv
->display
.off
= i9xx_crtc_off
;
10129 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10131 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10132 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10133 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
10134 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10135 dev_priv
->display
.off
= i9xx_crtc_off
;
10136 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10139 /* Returns the core display clock speed */
10140 if (IS_VALLEYVIEW(dev
))
10141 dev_priv
->display
.get_display_clock_speed
=
10142 valleyview_get_display_clock_speed
;
10143 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
10144 dev_priv
->display
.get_display_clock_speed
=
10145 i945_get_display_clock_speed
;
10146 else if (IS_I915G(dev
))
10147 dev_priv
->display
.get_display_clock_speed
=
10148 i915_get_display_clock_speed
;
10149 else if (IS_I945GM(dev
) || IS_845G(dev
))
10150 dev_priv
->display
.get_display_clock_speed
=
10151 i9xx_misc_get_display_clock_speed
;
10152 else if (IS_PINEVIEW(dev
))
10153 dev_priv
->display
.get_display_clock_speed
=
10154 pnv_get_display_clock_speed
;
10155 else if (IS_I915GM(dev
))
10156 dev_priv
->display
.get_display_clock_speed
=
10157 i915gm_get_display_clock_speed
;
10158 else if (IS_I865G(dev
))
10159 dev_priv
->display
.get_display_clock_speed
=
10160 i865_get_display_clock_speed
;
10161 else if (IS_I85X(dev
))
10162 dev_priv
->display
.get_display_clock_speed
=
10163 i855_get_display_clock_speed
;
10164 else /* 852, 830 */
10165 dev_priv
->display
.get_display_clock_speed
=
10166 i830_get_display_clock_speed
;
10168 if (HAS_PCH_SPLIT(dev
)) {
10169 if (IS_GEN5(dev
)) {
10170 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
10171 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10172 } else if (IS_GEN6(dev
)) {
10173 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
10174 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10175 } else if (IS_IVYBRIDGE(dev
)) {
10176 /* FIXME: detect B0+ stepping and use auto training */
10177 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
10178 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10179 dev_priv
->display
.modeset_global_resources
=
10180 ivb_modeset_global_resources
;
10181 } else if (IS_HASWELL(dev
)) {
10182 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
10183 dev_priv
->display
.write_eld
= haswell_write_eld
;
10184 dev_priv
->display
.modeset_global_resources
=
10185 haswell_modeset_global_resources
;
10187 } else if (IS_G4X(dev
)) {
10188 dev_priv
->display
.write_eld
= g4x_write_eld
;
10191 /* Default just returns -ENODEV to indicate unsupported */
10192 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
10194 switch (INTEL_INFO(dev
)->gen
) {
10196 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
10200 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
10205 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
10209 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
10212 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
10218 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10219 * resume, or other times. This quirk makes sure that's the case for
10220 * affected systems.
10222 static void quirk_pipea_force(struct drm_device
*dev
)
10224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10226 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
10227 DRM_INFO("applying pipe a force quirk\n");
10231 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10233 static void quirk_ssc_force_disable(struct drm_device
*dev
)
10235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10236 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
10237 DRM_INFO("applying lvds SSC disable quirk\n");
10241 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10244 static void quirk_invert_brightness(struct drm_device
*dev
)
10246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10247 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
10248 DRM_INFO("applying inverted panel brightness quirk\n");
10252 * Some machines (Dell XPS13) suffer broken backlight controls if
10253 * BLM_PCH_PWM_ENABLE is set.
10255 static void quirk_no_pcm_pwm_enable(struct drm_device
*dev
)
10257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10258 dev_priv
->quirks
|= QUIRK_NO_PCH_PWM_ENABLE
;
10259 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10262 struct intel_quirk
{
10264 int subsystem_vendor
;
10265 int subsystem_device
;
10266 void (*hook
)(struct drm_device
*dev
);
10269 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10270 struct intel_dmi_quirk
{
10271 void (*hook
)(struct drm_device
*dev
);
10272 const struct dmi_system_id (*dmi_id_list
)[];
10275 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
10277 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
10281 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
10283 .dmi_id_list
= &(const struct dmi_system_id
[]) {
10285 .callback
= intel_dmi_reverse_brightness
,
10286 .ident
= "NCR Corporation",
10287 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
10288 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
10291 { } /* terminating entry */
10293 .hook
= quirk_invert_brightness
,
10297 static struct intel_quirk intel_quirks
[] = {
10298 /* HP Mini needs pipe A force quirk (LP: #322104) */
10299 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
10301 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10302 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
10304 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10305 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
10307 /* 830/845 need to leave pipe A & dpll A up */
10308 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10309 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10311 /* Lenovo U160 cannot use SSC on LVDS */
10312 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
10314 /* Sony Vaio Y cannot use SSC on LVDS */
10315 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
10318 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10319 * seem to use inverted backlight PWM.
10321 { 0x2a42, 0x1025, PCI_ANY_ID
, quirk_invert_brightness
},
10323 /* Dell XPS13 HD Sandy Bridge */
10324 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable
},
10325 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10326 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable
},
10329 static void intel_init_quirks(struct drm_device
*dev
)
10331 struct pci_dev
*d
= dev
->pdev
;
10334 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
10335 struct intel_quirk
*q
= &intel_quirks
[i
];
10337 if (d
->device
== q
->device
&&
10338 (d
->subsystem_vendor
== q
->subsystem_vendor
||
10339 q
->subsystem_vendor
== PCI_ANY_ID
) &&
10340 (d
->subsystem_device
== q
->subsystem_device
||
10341 q
->subsystem_device
== PCI_ANY_ID
))
10344 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
10345 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
10346 intel_dmi_quirks
[i
].hook(dev
);
10350 /* Disable the VGA plane that we never use */
10351 static void i915_disable_vga(struct drm_device
*dev
)
10353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10355 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10357 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10358 outb(SR01
, VGA_SR_INDEX
);
10359 sr1
= inb(VGA_SR_DATA
);
10360 outb(sr1
| 1<<5, VGA_SR_DATA
);
10361 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10364 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
10365 POSTING_READ(vga_reg
);
10368 static void i915_enable_vga_mem(struct drm_device
*dev
)
10370 /* Enable VGA memory on Intel HD */
10371 if (HAS_PCH_SPLIT(dev
)) {
10372 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10373 outb(inb(VGA_MSR_READ
) | VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10374 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10375 VGA_RSRC_LEGACY_MEM
|
10376 VGA_RSRC_NORMAL_IO
|
10377 VGA_RSRC_NORMAL_MEM
);
10378 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10382 void i915_disable_vga_mem(struct drm_device
*dev
)
10384 /* Disable VGA memory on Intel HD */
10385 if (HAS_PCH_SPLIT(dev
)) {
10386 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10387 outb(inb(VGA_MSR_READ
) & ~VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10388 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10389 VGA_RSRC_NORMAL_IO
|
10390 VGA_RSRC_NORMAL_MEM
);
10391 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10395 void intel_modeset_init_hw(struct drm_device
*dev
)
10397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10399 intel_prepare_ddi(dev
);
10401 intel_init_clock_gating(dev
);
10403 /* Enable the CRI clock source so we can get at the display */
10404 if (IS_VALLEYVIEW(dev
))
10405 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
10406 DPLL_INTEGRATED_CRI_CLK_VLV
);
10408 intel_init_dpio(dev
);
10410 mutex_lock(&dev
->struct_mutex
);
10411 intel_enable_gt_powersave(dev
);
10412 mutex_unlock(&dev
->struct_mutex
);
10415 void intel_modeset_suspend_hw(struct drm_device
*dev
)
10417 intel_suspend_hw(dev
);
10420 void intel_modeset_init(struct drm_device
*dev
)
10422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10425 drm_mode_config_init(dev
);
10427 dev
->mode_config
.min_width
= 0;
10428 dev
->mode_config
.min_height
= 0;
10430 dev
->mode_config
.preferred_depth
= 24;
10431 dev
->mode_config
.prefer_shadow
= 1;
10433 dev
->mode_config
.funcs
= &intel_mode_funcs
;
10435 intel_init_quirks(dev
);
10437 intel_init_pm(dev
);
10439 if (INTEL_INFO(dev
)->num_pipes
== 0)
10442 intel_init_display(dev
);
10444 if (IS_GEN2(dev
)) {
10445 dev
->mode_config
.max_width
= 2048;
10446 dev
->mode_config
.max_height
= 2048;
10447 } else if (IS_GEN3(dev
)) {
10448 dev
->mode_config
.max_width
= 4096;
10449 dev
->mode_config
.max_height
= 4096;
10451 dev
->mode_config
.max_width
= 8192;
10452 dev
->mode_config
.max_height
= 8192;
10454 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
10456 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10457 INTEL_INFO(dev
)->num_pipes
,
10458 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
10461 intel_crtc_init(dev
, i
);
10462 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
10463 ret
= intel_plane_init(dev
, i
, j
);
10465 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10466 pipe_name(i
), sprite_name(i
, j
), ret
);
10470 intel_cpu_pll_init(dev
);
10471 intel_shared_dpll_init(dev
);
10473 /* Just disable it once at startup */
10474 i915_disable_vga(dev
);
10475 intel_setup_outputs(dev
);
10477 /* Just in case the BIOS is doing something questionable. */
10478 intel_disable_fbc(dev
);
10482 intel_connector_break_all_links(struct intel_connector
*connector
)
10484 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10485 connector
->base
.encoder
= NULL
;
10486 connector
->encoder
->connectors_active
= false;
10487 connector
->encoder
->base
.crtc
= NULL
;
10490 static void intel_enable_pipe_a(struct drm_device
*dev
)
10492 struct intel_connector
*connector
;
10493 struct drm_connector
*crt
= NULL
;
10494 struct intel_load_detect_pipe load_detect_temp
;
10496 /* We can't just switch on the pipe A, we need to set things up with a
10497 * proper mode and output configuration. As a gross hack, enable pipe A
10498 * by enabling the load detect pipe once. */
10499 list_for_each_entry(connector
,
10500 &dev
->mode_config
.connector_list
,
10502 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
10503 crt
= &connector
->base
;
10511 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
10512 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
10518 intel_check_plane_mapping(struct intel_crtc
*crtc
)
10520 struct drm_device
*dev
= crtc
->base
.dev
;
10521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10524 if (INTEL_INFO(dev
)->num_pipes
== 1)
10527 reg
= DSPCNTR(!crtc
->plane
);
10528 val
= I915_READ(reg
);
10530 if ((val
& DISPLAY_PLANE_ENABLE
) &&
10531 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
10537 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
10539 struct drm_device
*dev
= crtc
->base
.dev
;
10540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10543 /* Clear any frame start delays used for debugging left by the BIOS */
10544 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
10545 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
10547 /* We need to sanitize the plane -> pipe mapping first because this will
10548 * disable the crtc (and hence change the state) if it is wrong. Note
10549 * that gen4+ has a fixed plane -> pipe mapping. */
10550 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
10551 struct intel_connector
*connector
;
10554 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10555 crtc
->base
.base
.id
);
10557 /* Pipe has the wrong plane attached and the plane is active.
10558 * Temporarily change the plane mapping and disable everything
10560 plane
= crtc
->plane
;
10561 crtc
->plane
= !plane
;
10562 dev_priv
->display
.crtc_disable(&crtc
->base
);
10563 crtc
->plane
= plane
;
10565 /* ... and break all links. */
10566 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10568 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
10571 intel_connector_break_all_links(connector
);
10574 WARN_ON(crtc
->active
);
10575 crtc
->base
.enabled
= false;
10578 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
10579 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
10580 /* BIOS forgot to enable pipe A, this mostly happens after
10581 * resume. Force-enable the pipe to fix this, the update_dpms
10582 * call below we restore the pipe to the right state, but leave
10583 * the required bits on. */
10584 intel_enable_pipe_a(dev
);
10587 /* Adjust the state of the output pipe according to whether we
10588 * have active connectors/encoders. */
10589 intel_crtc_update_dpms(&crtc
->base
);
10591 if (crtc
->active
!= crtc
->base
.enabled
) {
10592 struct intel_encoder
*encoder
;
10594 /* This can happen either due to bugs in the get_hw_state
10595 * functions or because the pipe is force-enabled due to the
10597 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10598 crtc
->base
.base
.id
,
10599 crtc
->base
.enabled
? "enabled" : "disabled",
10600 crtc
->active
? "enabled" : "disabled");
10602 crtc
->base
.enabled
= crtc
->active
;
10604 /* Because we only establish the connector -> encoder ->
10605 * crtc links if something is active, this means the
10606 * crtc is now deactivated. Break the links. connector
10607 * -> encoder links are only establish when things are
10608 * actually up, hence no need to break them. */
10609 WARN_ON(crtc
->active
);
10611 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
10612 WARN_ON(encoder
->connectors_active
);
10613 encoder
->base
.crtc
= NULL
;
10618 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
10620 struct intel_connector
*connector
;
10621 struct drm_device
*dev
= encoder
->base
.dev
;
10623 /* We need to check both for a crtc link (meaning that the
10624 * encoder is active and trying to read from a pipe) and the
10625 * pipe itself being active. */
10626 bool has_active_crtc
= encoder
->base
.crtc
&&
10627 to_intel_crtc(encoder
->base
.crtc
)->active
;
10629 if (encoder
->connectors_active
&& !has_active_crtc
) {
10630 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10631 encoder
->base
.base
.id
,
10632 drm_get_encoder_name(&encoder
->base
));
10634 /* Connector is active, but has no active pipe. This is
10635 * fallout from our resume register restoring. Disable
10636 * the encoder manually again. */
10637 if (encoder
->base
.crtc
) {
10638 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10639 encoder
->base
.base
.id
,
10640 drm_get_encoder_name(&encoder
->base
));
10641 encoder
->disable(encoder
);
10644 /* Inconsistent output/port/pipe state happens presumably due to
10645 * a bug in one of the get_hw_state functions. Or someplace else
10646 * in our code, like the register restore mess on resume. Clamp
10647 * things to off as a safer default. */
10648 list_for_each_entry(connector
,
10649 &dev
->mode_config
.connector_list
,
10651 if (connector
->encoder
!= encoder
)
10654 intel_connector_break_all_links(connector
);
10657 /* Enabled encoders without active connectors will be fixed in
10658 * the crtc fixup. */
10661 void i915_redisable_vga(struct drm_device
*dev
)
10663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10664 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10666 /* This function can be called both from intel_modeset_setup_hw_state or
10667 * at a very early point in our resume sequence, where the power well
10668 * structures are not yet restored. Since this function is at a very
10669 * paranoid "someone might have enabled VGA while we were not looking"
10670 * level, just check if the power well is enabled instead of trying to
10671 * follow the "don't touch the power well if we don't need it" policy
10672 * the rest of the driver uses. */
10673 if (HAS_POWER_WELL(dev
) &&
10674 (I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_STATE_ENABLED
) == 0)
10677 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
10678 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10679 i915_disable_vga(dev
);
10680 i915_disable_vga_mem(dev
);
10684 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
10686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10688 struct intel_crtc
*crtc
;
10689 struct intel_encoder
*encoder
;
10690 struct intel_connector
*connector
;
10693 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10695 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
10697 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
10700 crtc
->base
.enabled
= crtc
->active
;
10702 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10703 crtc
->base
.base
.id
,
10704 crtc
->active
? "enabled" : "disabled");
10707 /* FIXME: Smash this into the new shared dpll infrastructure. */
10709 intel_ddi_setup_hw_pll_state(dev
);
10711 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10712 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10714 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
10716 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10718 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10721 pll
->refcount
= pll
->active
;
10723 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10724 pll
->name
, pll
->refcount
, pll
->on
);
10727 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10731 if (encoder
->get_hw_state(encoder
, &pipe
)) {
10732 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10733 encoder
->base
.crtc
= &crtc
->base
;
10734 if (encoder
->get_config
)
10735 encoder
->get_config(encoder
, &crtc
->config
);
10737 encoder
->base
.crtc
= NULL
;
10740 encoder
->connectors_active
= false;
10741 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10742 encoder
->base
.base
.id
,
10743 drm_get_encoder_name(&encoder
->base
),
10744 encoder
->base
.crtc
? "enabled" : "disabled",
10748 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10750 if (connector
->get_hw_state(connector
)) {
10751 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
10752 connector
->encoder
->connectors_active
= true;
10753 connector
->base
.encoder
= &connector
->encoder
->base
;
10755 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10756 connector
->base
.encoder
= NULL
;
10758 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10759 connector
->base
.base
.id
,
10760 drm_get_connector_name(&connector
->base
),
10761 connector
->base
.encoder
? "enabled" : "disabled");
10765 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10766 * and i915 state tracking structures. */
10767 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
10768 bool force_restore
)
10770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10772 struct intel_crtc
*crtc
;
10773 struct intel_encoder
*encoder
;
10776 intel_modeset_readout_hw_state(dev
);
10779 * Now that we have the config, copy it to each CRTC struct
10780 * Note that this could go away if we move to using crtc_config
10781 * checking everywhere.
10783 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10785 if (crtc
->active
&& i915_fastboot
) {
10786 intel_crtc_mode_from_pipe_config(crtc
, &crtc
->config
);
10788 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10789 crtc
->base
.base
.id
);
10790 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
10794 /* HW state is read out, now we need to sanitize this mess. */
10795 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10797 intel_sanitize_encoder(encoder
);
10800 for_each_pipe(pipe
) {
10801 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10802 intel_sanitize_crtc(crtc
);
10803 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
10806 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10807 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10809 if (!pll
->on
|| pll
->active
)
10812 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
10814 pll
->disable(dev_priv
, pll
);
10818 if (force_restore
) {
10819 i915_redisable_vga(dev
);
10822 * We need to use raw interfaces for restoring state to avoid
10823 * checking (bogus) intermediate states.
10825 for_each_pipe(pipe
) {
10826 struct drm_crtc
*crtc
=
10827 dev_priv
->pipe_to_crtc_mapping
[pipe
];
10829 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
10833 intel_modeset_update_staged_output_state(dev
);
10836 intel_modeset_check_state(dev
);
10838 drm_mode_config_reset(dev
);
10841 void intel_modeset_gem_init(struct drm_device
*dev
)
10843 intel_modeset_init_hw(dev
);
10845 intel_setup_overlay(dev
);
10847 intel_modeset_setup_hw_state(dev
, false);
10850 void intel_modeset_cleanup(struct drm_device
*dev
)
10852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10853 struct drm_crtc
*crtc
;
10854 struct drm_connector
*connector
;
10857 * Interrupts and polling as the first thing to avoid creating havoc.
10858 * Too much stuff here (turning of rps, connectors, ...) would
10859 * experience fancy races otherwise.
10861 drm_irq_uninstall(dev
);
10862 cancel_work_sync(&dev_priv
->hotplug_work
);
10864 * Due to the hpd irq storm handling the hotplug work can re-arm the
10865 * poll handlers. Hence disable polling after hpd handling is shut down.
10867 drm_kms_helper_poll_fini(dev
);
10869 mutex_lock(&dev
->struct_mutex
);
10871 intel_unregister_dsm_handler();
10873 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
10874 /* Skip inactive CRTCs */
10878 intel_increase_pllclock(crtc
);
10881 intel_disable_fbc(dev
);
10883 i915_enable_vga_mem(dev
);
10885 intel_disable_gt_powersave(dev
);
10887 ironlake_teardown_rc6(dev
);
10889 mutex_unlock(&dev
->struct_mutex
);
10891 /* flush any delayed tasks or pending work */
10892 flush_scheduled_work();
10894 /* destroy backlight, if any, before the connectors */
10895 intel_panel_destroy_backlight(dev
);
10897 /* destroy the sysfs files before encoders/connectors */
10898 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
)
10899 drm_sysfs_connector_remove(connector
);
10901 drm_mode_config_cleanup(dev
);
10903 intel_cleanup_overlay(dev
);
10907 * Return which encoder is currently attached for connector.
10909 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
10911 return &intel_attached_encoder(connector
)->base
;
10914 void intel_connector_attach_encoder(struct intel_connector
*connector
,
10915 struct intel_encoder
*encoder
)
10917 connector
->encoder
= encoder
;
10918 drm_mode_connector_attach_encoder(&connector
->base
,
10923 * set vga decode state - true == enable VGA decode
10925 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
10927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10930 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
10932 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
10934 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
10935 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
10939 struct intel_display_error_state
{
10941 u32 power_well_driver
;
10943 int num_transcoders
;
10945 struct intel_cursor_error_state
{
10950 } cursor
[I915_MAX_PIPES
];
10952 struct intel_pipe_error_state
{
10954 } pipe
[I915_MAX_PIPES
];
10956 struct intel_plane_error_state
{
10964 } plane
[I915_MAX_PIPES
];
10966 struct intel_transcoder_error_state
{
10967 enum transcoder cpu_transcoder
;
10980 struct intel_display_error_state
*
10981 intel_display_capture_error_state(struct drm_device
*dev
)
10983 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
10984 struct intel_display_error_state
*error
;
10985 int transcoders
[] = {
10993 if (INTEL_INFO(dev
)->num_pipes
== 0)
10996 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
11000 if (HAS_POWER_WELL(dev
))
11001 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
11004 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
11005 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
11006 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
11007 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
11009 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
11010 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
11011 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
11014 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
11015 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
11016 if (INTEL_INFO(dev
)->gen
<= 3) {
11017 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
11018 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
11020 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
11021 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
11022 if (INTEL_INFO(dev
)->gen
>= 4) {
11023 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
11024 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
11027 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
11030 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
11031 if (HAS_DDI(dev_priv
->dev
))
11032 error
->num_transcoders
++; /* Account for eDP. */
11034 for (i
= 0; i
< error
->num_transcoders
; i
++) {
11035 enum transcoder cpu_transcoder
= transcoders
[i
];
11037 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
11039 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
11040 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
11041 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
11042 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
11043 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
11044 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
11045 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
11048 /* In the code above we read the registers without checking if the power
11049 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11050 * prevent the next I915_WRITE from detecting it and printing an error
11052 intel_uncore_clear_errors(dev
);
11057 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11060 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
11061 struct drm_device
*dev
,
11062 struct intel_display_error_state
*error
)
11069 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
11070 if (HAS_POWER_WELL(dev
))
11071 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
11072 error
->power_well_driver
);
11074 err_printf(m
, "Pipe [%d]:\n", i
);
11075 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
11077 err_printf(m
, "Plane [%d]:\n", i
);
11078 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
11079 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
11080 if (INTEL_INFO(dev
)->gen
<= 3) {
11081 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
11082 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
11084 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
11085 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
11086 if (INTEL_INFO(dev
)->gen
>= 4) {
11087 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
11088 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
11091 err_printf(m
, "Cursor [%d]:\n", i
);
11092 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
11093 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
11094 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
11097 for (i
= 0; i
< error
->num_transcoders
; i
++) {
11098 err_printf(m
, " CPU transcoder: %c\n",
11099 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
11100 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
11101 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
11102 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
11103 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
11104 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
11105 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
11106 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);